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arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_master/bugs/state_transition/diff.patch

@@ -0,0 +1,11 @@
+--- a/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_master.sv
++++ b/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_master.sv
+@@ -125,7 +125,7 @@
+ 			RADDR_CHANNEL  : if (M_ARVALID && M_ARREADY  ) next_state = RDATA__CHANNEL;
+ 			RDATA__CHANNEL : if (M_RVALID  && M_RREADY   ) next_state = IDLE;
+             WRITE_CHANNEL  : if (write_addr && write_data) next_state = WRESP__CHANNEL;
+-            WRESP__CHANNEL : if (M_BVALID  && M_BREADY   ) next_state = IDLE;
++            WRESP__CHANNEL : if (M_BVALID  && M_BREADY   ) next_state = WRITE_CHANNEL;
+ 			default : next_state = IDLE;
+ 		endcase
+ 	end

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_master/bugs/state_transition/sim_log.txt

@@ -0,0 +1,2 @@
+FST info: dumpfile wave_axi4_lite_top.fst opened for output.
+FST warning: $dumpvars: Unsupported argument type (vpiPackage)

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_slave/bugs/inverted_condition/diff.patch

@@ -0,0 +1,11 @@
+--- a/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv
++++ b/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv
+@@ -119,7 +119,7 @@
+                 if (S_AWVALID) begin
+                     next_state = WRITE_CHANNEL;
+                 end 
+-                else if (S_ARVALID) begin
++                else if (!S_ARVALID) begin
+                     next_state = RADDR_CHANNEL;
+                 end 
+                 else begin

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_slave/bugs/inverted_condition/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "inverted_condition",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv"
+  ],
+  "bug_description": "Inverted 'S_ARVALID' condition in IDLE state \u2014 read address channel transition now triggers when S_ARVALID is deasserted instead of asserted",
+  "signals_affected": [
+    "S_ARVALID"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "The AXI read address channel state machine enters an unexpected invalid state at t=5000, causing all interface signals to become undefined (x). At this point, the interconnect should be idling with S_ARVALID deasserted, waiting for a valid read request, but instead the state machine exits IDLE incorrectly, propagating undefined values through M_ARVALID, M_ARADDR, S_ARREADY, and cascading through the entire write channel (M_AWVALID, M_AWADDR, M_WVALID, S_AWREADY, S_WREADY, S_BVALID). This violates basic AXI protocol requirements where the slave must present valid ready and data signals in response to address transactions, not undefined values.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_slave/bugs/inverted_condition/sim_log.txt

@@ -0,0 +1,2 @@
+FST info: dumpfile wave_axi4_lite_top.fst opened for output.
+FST warning: $dumpvars: Unsupported argument type (vpiPackage)

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_slave/bugs/missing_reset/diff.patch

@@ -0,0 +1,19 @@
+--- a/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv
++++ b/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv
+@@ -69,6 +69,8 @@
+     typedef enum logic [2 : 0] {IDLE,WRITE_CHANNEL,WRESP__CHANNEL, RADDR_CHANNEL, RDATA__CHANNEL} state_type;
+     state_type state , next_state;
+ 
++    initial addr = 'hx;
++
+     // AR
+     assign S_ARREADY = (state == RADDR_CHANNEL) ? 1 : 0;
+     // 
+@@ -106,7 +108,6 @@
+ 
+     always_ff @(posedge ACLK) begin
+         if (!ARESETN) begin
+-            state <= IDLE;
+         end
+         else begin
+             state <= next_state;

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_slave/bugs/missing_reset/metadata.json

@@ -0,0 +1,17 @@
+{
+  "bug_type": "missing_reset",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv"
+  ],
+  "bug_description": "Removed synchronous reset for 'state' register in axi4_lite_slave; state FSM register no longer initializes to IDLE on reset, and 'addr' register is initialized to X to make missing reset observable",
+  "signals_affected": [
+    "state",
+    "addr"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "After reset de-assertion at t=5000, the AXI4-Lite slave outputs are stuck in an undefined state. All control signals\u2014S_ARREADY, S_AWREADY, S_WREADY, S_RVALID, and S_BVALID\u2014show X values instead of their expected low states, and S_RDATA also reads as all Xs. The slave never transitions to a known state and cannot respond to read or write requests. This appears to occur immediately upon reset release, suggesting the internal state machine is not properly initialized during the reset sequence.",
+  "diff_summary": "5 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_slave/bugs/missing_reset/sim_log.txt

@@ -0,0 +1,2 @@
+FST info: dumpfile wave_axi4_lite_top.fst opened for output.
+FST warning: $dumpvars: Unsupported argument type (vpiPackage)

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_top/bugs/unconnected_port/diff.patch

@@ -0,0 +1,11 @@
+--- a/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv
++++ b/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv
+@@ -72,7 +72,7 @@
+         .ACLK(ACLK),
+         .ARESETN(ARESETN),
+         .S_ARREADY(M_ARREADY),
+-        .S_RDATA(S_RDATA),
++        .S_RDATA(),
+         .S_RRESP(S_RRESP),
+         .S_RVALID(S_RVALID),
+         .S_ARADDR(M_ARADDR),

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_top/bugs/unconnected_port/metadata.json

@@ -0,0 +1,5 @@
+{
+  "bug_type": "unconnected_port",
+  "simulation_status": "waveform_identical",
+  "signals_compared": 17
+}

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_top/bugs/unconnected_port/sim_log.txt

@@ -0,0 +1,2 @@
+FST info: dumpfile wave_axi4_lite_top.fst opened for output.
+FST warning: $dumpvars: Unsupported argument type (vpiPackage)

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_top/bugs/wrong_bitwidth/diff.patch

@@ -0,0 +1,11 @@
+--- a/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv
++++ b/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv
+@@ -35,7 +35,7 @@
+     logic  M_ARREADY,S_RVALID,M_ARVALID,M_RREADY,S_AWREADY,S_BVALID,M_AWVALID,M_BREADY,M_WVALID,S_WREADY;
+     logic [ADDRESS-1 : 0] M_ARADDR;
+     logic [ADDRESS-1 : 0] M_AWADDR;
+-    logic [DATA_WIDTH-1:0]M_WDATA;
++    logic [DATA_WIDTH-3:0]M_WDATA;
+     logic [DATA_WIDTH-1:0]S_RDATA;
+     logic [3:0]M_WSTRB;
+     logic [1:0]S_RRESP,S_BRESP;

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_top/bugs/wrong_bitwidth/metadata.json

@@ -0,0 +1,5 @@
+{
+  "bug_type": "wrong_bitwidth",
+  "simulation_status": "waveform_identical",
+  "signals_compared": 17
+}

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_top/bugs/wrong_bitwidth/sim_log.txt

@@ -0,0 +1,8 @@
+FST info: dumpfile wave_axi4_lite_top.fst opened for output.
+FST warning: $dumpvars: Unsupported argument type (vpiPackage)
+
+--- STDERR ---
+/tmp/sim4_simsh_ajdomuh6/source/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv:43: warning: Port 20 (M_WDATA) of axi4_lite_master expects 32 bits, got 30.
+/tmp/sim4_simsh_ajdomuh6/source/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv:43:        : Padding 2 high bits of the port.
+/tmp/sim4_simsh_ajdomuh6/source/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv:70: warning: Port 8 (S_WDATA) of axi4_lite_slave expects 32 bits, got 30.
+/tmp/sim4_simsh_ajdomuh6/source/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv:70:        : Padding 2 high bits of the port.

arhamhashmi01_Axi4-lite/candidates/axi4_lite_top__axi4_lite_top/sim.sh

@@ -0,0 +1,11 @@
+#!/usr/bin/env bash
+set -euo pipefail
+if ! command -v python &>/dev/null; then
+    _TMPBIN=$(mktemp -d)
+    ln -s "$(command -v python3)" "$_TMPBIN/python"
+    export PATH="$_TMPBIN:$PATH"
+    trap 'rm -rf "$_TMPBIN"' EXIT
+fi
+SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+iverilog -g2012 -o /tmp/sim_axi4_lite_top "$SRCDIR/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv" "$SRCDIR/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_master.sv" "$SRCDIR/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv" "$SRCDIR/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sim_1/new/axi4_lite_top_tb.sv"
+vvp /tmp/sim_axi4_lite_top -fst

arhamhashmi01_Axi4-lite/sim_script_map.json

@@ -0,0 +1,3 @@
+{
+  "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sim_1/new/axi4_lite_top_tb.sv": "axi4_lite_top_sim.sh"
+}

arhamhashmi01_Axi4-lite/simulations.jsonl

@@ -0,0 +1 @@
+{"tb_file_path": "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sim_1/new/axi4_lite_top_tb.sv", "simulator": "iverilog", "top_module": "axi4_lite_top", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv", "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_master.sv", "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv", "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sim_1/new/axi4_lite_top_tb.sv"]}, "run": {"args": ["-fst"]}, "waveform": "wave_axi4_lite_top.fst"}

arhamhashmi01_Axi4-lite/source/Axi4-lite-verilator/Makefile

@@ -0,0 +1,26 @@
+MODULE=axi4_lite_top
+
+.PHONY:sim
+sim: waveform.vcd
+
+.PHONY:waves
+waves: waveform.vcd
+	gtkwave waveform.vcd
+
+waveform.vcd: ./obj_dir/V$(MODULE)
+	@./obj_dir/V$(MODULE)
+
+./obj_dir/V$(MODULE): .stamp.verilate
+	make -C obj_dir -f V$(MODULE).mk V$(MODULE)
+
+.stamp.verilate: $(MODULE).sv $(MODULE)_tb.cpp
+	verilator -Wall --trace -cc $(MODULE).sv --exe $(MODULE)_tb.cpp
+
+.PHONY:lint
+lint: $(MODULE).sv
+	verilator --lint-only $(MODULE).sv
+
+.PHONY: clean
+clean:
+	rm -rf ./obj_dir
+	rm -rf waveform.vcd

arhamhashmi01_Axi4-lite/source/Axi4-lite-verilator/axi4_lite_master.sv

@@ -0,0 +1,130 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 05/03/2024 03:21:17 PM
+// Design Name: 
+// Module Name: axi4_lite_master
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module axi4_lite_master #(
+    parameter ADDRESS = 32,
+    parameter DATA_WIDTH = 32
+    )
+    (
+        //Global Signals
+        input                           ACLK,
+        input                           ARESETN,
+
+        input                           START_READ,
+        input                           START_WRITE,
+
+        input          [ADDRESS-1 : 0]  address,
+        input          [DATA_WIDTH-1:0]  W_data,
+
+        //Read Address Channel INPUTS
+        input                           M_ARREADY,
+        //Read Data Channel INPUTS
+        /* verilator lint_off UNUSED */
+        input          [DATA_WIDTH-1:0] M_RDATA,
+        input               [1:0]       M_RRESP,
+        input                           M_RVALID,
+        //Write Address Channel INPUTS
+        input                           M_AWREADY,
+        //
+        input                           M_WREADY,
+        //Write Response Channel INPUTS
+        input             [1:0]         M_BRESP,
+        input                           M_BVALID,
+        //Read Address Channel OUTPUTS
+        output logic    [ADDRESS-1 : 0] M_ARADDR,
+        output logic                    M_ARVALID,
+        //Read Data Channel OUTPUTS
+        output logic                    M_RREADY,
+        //Write Address Channel OUTPUTS
+        output logic    [ADDRESS-1 : 0] M_AWADDR,
+        output logic                    M_AWVALID,
+        //Write Data  Channel OUTPUTS
+        output logic   [DATA_WIDTH-1:0] M_WDATA,
+        output logic   [3:0]            M_WSTRB,
+        output logic                    M_WVALID,
+        //Write Response Channel OUTPUTS
+        output logic                    M_BREADY	
+    );
+    logic read_start;
+    logic write_addr;
+    logic write_data;
+    logic write_start;
+
+    typedef enum logic [2 : 0] {IDLE,WRITE_CHANNEL,WRESP__CHANNEL, RADDR_CHANNEL, RDATA__CHANNEL} state_type;
+    state_type state , next_state;
+
+    //ar
+    assign M_ARADDR  = (state == RADDR_CHANNEL) ? address : 32'h0;
+    assign M_ARVALID = (state == RADDR_CHANNEL) ? 1 : 0;
+    //r
+    assign M_RREADY  = (state == RDATA__CHANNEL ||state == RADDR_CHANNEL) ? 1 : 0;
+    //aw
+    assign M_AWVALID = (state == WRITE_CHANNEL) ? 1 : 0;
+    assign M_AWADDR  = (state == WRITE_CHANNEL) ? address : 32'h0;
+    assign write_addr = M_AWVALID && M_AWREADY;
+    assign write_data = M_WVALID  && M_WREADY;
+    //W
+    assign M_WVALID  = (state == WRITE_CHANNEL) ? 1 : 0;
+    assign M_WDATA   = (state == WRITE_CHANNEL) ? W_data : 32'h0;
+    assign M_WSTRB   = (state == WRITE_CHANNEL)  ?4'b1111:0;
+    // B
+    assign M_BREADY = ((state == WRITE_CHANNEL)||(state == WRESP__CHANNEL)) ? 1 : 0;
+
+
+    always_ff @(posedge ACLK) begin
+        if (~ARESETN) begin
+            state <= IDLE;
+        end else begin
+            state <= next_state;
+        end
+    end
+    
+    always_ff @(posedge ACLK) begin
+        if (~ARESETN) begin
+           read_start <= 0;
+           write_start<= 0;
+        end 
+        else begin
+           read_start <= START_READ;
+           write_start<= START_WRITE;
+        end
+    end
+    
+    always_comb begin
+		case (state)
+            IDLE : begin
+                if (write_start) begin
+                    next_state = WRITE_CHANNEL;
+                end 
+                else if (read_start) begin
+                    next_state = RADDR_CHANNEL;
+                end 
+                else begin
+                    next_state = IDLE;
+                end
+            end
+			RADDR_CHANNEL  : if (M_ARVALID && M_ARREADY  ) next_state = RDATA__CHANNEL;
+			RDATA__CHANNEL : if (M_RVALID  && M_RREADY   ) next_state = IDLE;
+            WRITE_CHANNEL  : if (write_addr && write_data) next_state = WRESP__CHANNEL;
+            WRESP__CHANNEL : if (M_BVALID  && M_BREADY   ) next_state = IDLE;
+			default : next_state = IDLE;
+		endcase
+	end
+endmodule

arhamhashmi01_Axi4-lite/source/Axi4-lite-verilator/axi4_lite_slave.sv

@@ -0,0 +1,134 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 05/03/2024 03:21:17 PM
+// Design Name: 
+// Module Name: axi4_lite_slave
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module axi4_lite_slave #(
+    parameter ADDRESS = 32,
+    parameter DATA_WIDTH = 32
+    )
+    (
+        //Global Signals
+        input                           ACLK,
+        input                           ARESETN,
+
+        ////Read Address Channel INPUTS
+        input           [ADDRESS-1:0]   S_ARADDR,
+        input                           S_ARVALID,
+        //Read Data Channel INPUTS
+        input                           S_RREADY,
+        //Write Address Channel INPUTS
+        /* verilator lint_off UNUSED */
+        input           [ADDRESS-1:0]   S_AWADDR,
+        input                           S_AWVALID,
+        //Write Data  Channel INPUTS
+        input          [DATA_WIDTH-1:0] S_WDATA,
+        input          [3:0]            S_WSTRB,
+        input                           S_WVALID,
+        //Write Response Channel INPUTS
+        input                           S_BREADY,	
+
+        //Read Address Channel OUTPUTS
+        output logic                    S_ARREADY,
+        //Read Data Channel OUTPUTS
+        output logic    [DATA_WIDTH-1:0]S_RDATA,
+        output logic         [1:0]      S_RRESP,
+        output logic                    S_RVALID,
+        //Write Address Channel OUTPUTS
+        output logic                    S_AWREADY,
+        output logic                    S_WREADY,
+        //Write Response Channel OUTPUTS
+        output logic         [1:0]      S_BRESP,
+        output logic                    S_BVALID
+    );
+
+    localparam no_of_registers = 32;
+
+    logic [DATA_WIDTH-1 : 0] register [no_of_registers-1 : 0];
+    logic [ADDRESS-1 : 0]    addr;
+    logic  write_addr;
+    logic  write_data;
+
+    typedef enum logic [2 : 0] {IDLE,WRITE_CHANNEL,WRESP__CHANNEL, RADDR_CHANNEL, RDATA__CHANNEL} state_type;
+    state_type state , next_state;
+
+    // AR
+    assign S_ARREADY = (state == RADDR_CHANNEL) ? 1 : 0;
+    // 
+    assign S_RVALID = (state == RDATA__CHANNEL) ? 1 : 0;
+    assign S_RDATA  = (state == RDATA__CHANNEL) ? register[addr] : 0;
+    assign S_RRESP  = (state == RDATA__CHANNEL) ?2'b00:0;
+    // AW
+    assign S_AWREADY = (state == WRITE_CHANNEL) ? 1 : 0;
+    // W
+    assign S_WREADY = (state == WRITE_CHANNEL) ? 1 : 0;
+    assign write_addr = S_AWVALID && S_AWREADY;
+    assign write_data = S_WREADY &&S_WVALID;
+    // B
+    assign S_BVALID = (state == WRESP__CHANNEL) ? 1 : 0;
+    assign S_BRESP  = (state == WRESP__CHANNEL )? 0:0;
+
+    integer i;
+
+    always_ff @(posedge ACLK) begin
+        // Reset the register array
+        if (~ARESETN) begin
+            for (i = 0; i < 32; i++) begin
+                register[i] <= 32'b0;
+            end
+        end
+        else begin
+            if (state == WRITE_CHANNEL) begin
+                register[S_AWADDR] <= S_WDATA;
+            end
+            else if (state == RADDR_CHANNEL) begin
+                addr <= S_ARADDR;
+            end
+        end
+    end
+
+    always_ff @(posedge ACLK) begin
+        if (!ARESETN) begin
+            state <= IDLE;
+        end
+        else begin
+            state <= next_state;
+        end
+    end
+
+    always_comb begin
+		case (state)
+            IDLE : begin
+                if (S_AWVALID) begin
+                    next_state = WRITE_CHANNEL;
+                end 
+                else if (S_ARVALID) begin
+                    next_state = RADDR_CHANNEL;
+                end 
+                else begin
+                    next_state = IDLE;
+                end
+            end
+            RADDR_CHANNEL   : if (S_ARVALID && S_ARREADY ) next_state = RDATA__CHANNEL;
+            RDATA__CHANNEL  : if (S_RVALID  && S_RREADY  ) next_state = IDLE;
+            WRITE_CHANNEL   : if (write_addr &&write_data) next_state = WRESP__CHANNEL;
+            WRESP__CHANNEL  : if (S_BVALID  && S_BREADY  ) next_state = IDLE;
+            default : next_state = IDLE;
+        endcase
+    end
+endmodule

arhamhashmi01_Axi4-lite/source/Axi4-lite-verilator/axi4_lite_top.sv

@@ -0,0 +1,70 @@
+module axi4_lite_top#(
+    parameter DATA_WIDTH = 32,
+    parameter ADDRESS = 32
+    )(
+        input                           ACLK,
+        input                           ARESETN,
+        input                           read_s,
+        input                           write_s,
+        input    [ADDRESS-1:0]          address,
+        input    [DATA_WIDTH-1:0]       W_data
+    );
+
+    logic  M_ARREADY,S_RVALID,M_ARVALID,M_RREADY,S_AWREADY,S_BVALID,M_AWVALID,M_BREADY,M_WVALID,S_WREADY;
+    logic [ADDRESS-1 : 0] M_ARADDR;
+    logic [ADDRESS-1 : 0] M_AWADDR;
+    logic [DATA_WIDTH-1:0]M_WDATA;
+    logic [DATA_WIDTH-1:0]S_RDATA;
+    logic [3:0]M_WSTRB;
+    logic [1:0]S_RRESP,S_BRESP;
+
+    axi4_lite_master u_axi4_lite_master0
+    (
+        .ACLK(ACLK),
+        .ARESETN(ARESETN),
+        .START_READ(read_s),
+        .address(address),
+        .W_data(W_data),
+        .M_ARREADY(M_ARREADY),
+        .M_RDATA(S_RDATA),
+        .M_RRESP(S_RRESP),
+        .M_RVALID(S_RVALID),
+        .M_ARADDR(M_ARADDR),
+        .M_ARVALID(M_ARVALID),
+        .M_RREADY(M_RREADY),
+        .START_WRITE(write_s),
+        .M_AWREADY(S_AWREADY),
+        .M_WVALID(M_WVALID),
+        .M_WREADY(S_WREADY),
+        .M_BRESP(S_BRESP),
+        .M_BVALID(S_BVALID),
+        .M_AWADDR(M_AWADDR),
+        .M_AWVALID(M_AWVALID),
+        .M_WDATA(M_WDATA),
+        .M_WSTRB(M_WSTRB),
+        .M_BREADY(M_BREADY)
+    );
+
+    axi4_lite_slave u_axi4_lite_slave0
+    (
+        .ACLK(ACLK),
+        .ARESETN(ARESETN),
+        .S_ARREADY(M_ARREADY),
+        .S_RDATA(S_RDATA),
+        .S_RRESP(S_RRESP),
+        .S_RVALID(S_RVALID),
+        .S_ARADDR(M_ARADDR),
+        .S_ARVALID(M_ARVALID),
+        .S_RREADY(M_RREADY),
+        .S_AWREADY(S_AWREADY),
+        .S_WVALID(M_WVALID),
+        .S_WREADY(S_WREADY),
+        .S_BRESP(S_BRESP),
+        .S_BVALID(S_BVALID),
+        .S_AWADDR(M_AWADDR),
+        .S_AWVALID(M_AWVALID),
+        .S_WDATA(M_WDATA),
+        .S_WSTRB(M_WSTRB),
+        .S_BREADY(M_BREADY)
+    );
+endmodule

arhamhashmi01_Axi4-lite/source/Axi4-lite-verilator/axi4_lite_top_tb.sv

@@ -0,0 +1,51 @@
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+#include "Vaxi4_lite_top.h"
+
+vluint64_t sim_time = 0;
+
+void read_values(Vaxi4_lite_top* dut) {
+    if (sim_time == 0 && sim_time < 5) {
+        dut->ACLK = 0;
+        dut->ARESETN = 0;
+    } else if (sim_time >= 5) {
+        dut->ARESETN = 1;
+    }
+    if (sim_time == 7) {
+        dut->write_s = 1;
+        dut->address = 5;
+        dut->W_data  = 4;
+    } else if (sim_time == 9&& sim_time < 15) {
+        dut->write_s = 0;
+    }
+    else if (sim_time == 21) {
+        dut->read_s = 1;
+        dut->address = 5;
+    }
+    else if (sim_time == 23) {
+        dut->read_s = 0;}
+}
+
+int main(int argc, char** argv, char** env) {
+    Vaxi4_lite_top* dut = new Vaxi4_lite_top;
+
+    Verilated::traceEverOn(true);
+    VerilatedVcdC* m_trace = new VerilatedVcdC;
+    dut->trace(m_trace, 99); // Trace 99 levels of hierarchy
+    m_trace->open("waveform.vcd");
+
+    dut->ACLK = 0;
+    dut->ARESETN = 0;
+
+    while (sim_time <= 40) {
+        dut->ACLK = !dut->ACLK;
+        read_values(dut);
+        dut->eval();
+        m_trace->dump(sim_time);
+        sim_time++;
+    }
+
+    m_trace->close();
+    delete dut;
+    exit(EXIT_SUCCESS);
+}

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.hw/Axi4-lite-vivado.lpr

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.ip_user_files/README.txt

@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim/axi4_lite_top_tb.tcl

@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim/axi4_lite_top_tb_vlog.prj

@@ -0,0 +1,12 @@
+# compile verilog/system verilog design source files
+sv xil_defaultlib  \
+"../../../../Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_master.sv" \
+"../../../../Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv" \
+"../../../../Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv" \
+"../../../../Axi4-lite-vivado.srcs/sim_1/new/axi4_lite_top_tb.sv" \
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim/compile.bat

@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2018.2 (64-bit)
+REM
+REM Filename    : compile.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Sat May 04 18:04:08 +0500 2024
+REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
+REM
+REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+echo "xvlog --incr --relax -prj axi4_lite_top_tb_vlog.prj"
+call xvlog  --incr --relax -prj axi4_lite_top_tb_vlog.prj -log xvlog.log
+call type xvlog.log > compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim/elaborate.bat

@@ -0,0 +1,23 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2018.2 (64-bit)
+REM
+REM Filename    : elaborate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Sat May 04 18:04:09 +0500 2024
+REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
+REM
+REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+call xelab  -wto 21efe0d2eda443e9bd204aa321f74156 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot axi4_lite_top_tb_behav xil_defaultlib.axi4_lite_top_tb xil_defaultlib.glbl -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim/elaborate.log

@@ -0,0 +1,7 @@
+Vivado Simulator 2018.2
+Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
+Running: E:/vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 21efe0d2eda443e9bd204aa321f74156 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot axi4_lite_top_tb_behav xil_defaultlib.axi4_lite_top_tb xil_defaultlib.glbl -log elaborate.log 
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim/simulate.bat

@@ -0,0 +1,23 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2018.2 (64-bit)
+REM
+REM Filename    : simulate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Sat May 04 17:57:53 +0500 2024
+REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
+REM
+REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+call xsim axi4_lite_top_tb_behav -key {Behavioral:sim_1:Functional:axi4_lite_top_tb} -tclbatch axi4_lite_top_tb.tcl -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim/webtalk.jou

@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Webtalk v2018.2 (64-bit)
+# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
+# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
+# Start of session at: Sat May  4 18:04:06 2024
+# Process ID: 16528
+# Current directory: E:/projects/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim
+# Command line: wbtcv.exe -mode batch -source E:/projects/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim/xsim.dir/axi4_lite_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace
+# Log file: E:/projects/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim/webtalk.log
+# Journal file: E:/projects/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim\webtalk.jou
+#-----------------------------------------------------------
+source E:/projects/Axi4-lite-vivado/Axi4-lite-vivado.sim/sim_1/behav/xsim/xsim.dir/axi4_lite_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sim_1/new/axi4_lite_top_tb.sv

@@ -0,0 +1,74 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 05/04/2024 05:55:37 PM
+// Design Name: 
+// Module Name: axi4_lite_top_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module axi4_lite_top_tb();
+
+    logic           ACLK_tb;
+    logic           ARESETN_tb;
+    logic           read_s_tb;
+    logic           write_s_tb;
+    logic [31:0]    address_tb;
+    logic [31:0]    W_data_tb;
+    
+    axi4_lite_top u_axi4_lite_top0(
+        .ACLK(ACLK_tb),
+        .ARESETN(ARESETN_tb),
+        .read_s(read_s_tb),
+        .write_s(write_s_tb),
+        .address(address_tb),
+        .W_data(W_data_tb)
+    );
+
+    initial begin
+        #5;
+        ACLK_tb=0;
+        ARESETN_tb=0;
+        read_s_tb=0;  
+        write_s_tb=0;                           
+        #5;
+        ACLK_tb=1;
+        ARESETN_tb=1;
+        write_s_tb=0;
+        #15;
+        write_s_tb=1;
+        address_tb = 5;
+        W_data_tb = 4;
+        
+        //read_s_tb=1;
+        #10;
+        write_s_tb=0;
+        #20;
+        write_s_tb=0;
+        read_s_tb=0;
+        #30;
+        read_s_tb=1;
+        address_tb = 5;
+        #10;
+        read_s_tb=0;
+        #40;
+        $finish;            
+    end
+    
+    always begin
+        #5 ACLK_tb = ~ACLK_tb;
+    end
+endmodule

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_master.sv

@@ -0,0 +1,132 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 05/04/2024 05:52:55 PM
+// Design Name: 
+// Module Name: axi4_lite_master
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module axi4_lite_master #(
+    parameter ADDRESS = 32,
+    parameter DATA_WIDTH = 32
+    )
+    (
+        //Global Signals
+        input                           ACLK,
+        input                           ARESETN,
+
+        input                           START_READ,
+        input                           START_WRITE,
+
+        input          [ADDRESS-1 : 0]  address,
+        input          [DATA_WIDTH-1:0]  W_data,
+
+        //Read Address Channel INPUTS
+        input                           M_ARREADY,
+        //Read Data Channel INPUTS
+        /* verilator lint_off UNUSED */
+        input          [DATA_WIDTH-1:0] M_RDATA,
+        input               [1:0]       M_RRESP,
+        input                           M_RVALID,
+        //Write Address Channel INPUTS
+        input                           M_AWREADY,
+        //
+        input                           M_WREADY,
+        //Write Response Channel INPUTS
+        input             [1:0]         M_BRESP,
+        input                           M_BVALID,
+        //Read Address Channel OUTPUTS
+        output logic    [ADDRESS-1 : 0] M_ARADDR,
+        output logic                    M_ARVALID,
+        //Read Data Channel OUTPUTS
+        output logic                    M_RREADY,
+        //Write Address Channel OUTPUTS
+        output logic    [ADDRESS-1 : 0] M_AWADDR,
+        output logic                    M_AWVALID,
+        //Write Data  Channel OUTPUTS
+        output logic   [DATA_WIDTH-1:0] M_WDATA,
+        output logic   [3:0]            M_WSTRB,
+        output logic                    M_WVALID,
+        //Write Response Channel OUTPUTS
+        output logic                    M_BREADY	
+    );
+    logic read_start;
+    logic write_addr;
+    logic write_data;
+    logic write_start;
+
+    typedef enum logic [2 : 0] {IDLE,WRITE_CHANNEL,WRESP__CHANNEL, RADDR_CHANNEL, RDATA__CHANNEL} state_type;
+    state_type state , next_state;
+
+    //ar
+    assign M_ARADDR  = (state == RADDR_CHANNEL) ? address : 32'h0;
+    assign M_ARVALID = (state == RADDR_CHANNEL) ? 1 : 0;
+    //r
+    assign M_RREADY  = (state == RDATA__CHANNEL ||state == RADDR_CHANNEL) ? 1 : 0;
+    //aw
+    assign M_AWVALID = (state == WRITE_CHANNEL) ? 1 : 0;
+    assign M_AWADDR  = (state == WRITE_CHANNEL) ? address : 32'h0;
+    assign write_addr = M_AWVALID && M_AWREADY;
+    assign write_data = M_WVALID  && M_WREADY;
+    //W
+    assign M_WVALID  = (state == WRITE_CHANNEL) ? 1 : 0;
+    assign M_WDATA   = (state == WRITE_CHANNEL) ? W_data : 32'h0;
+    assign M_WSTRB   = (state == WRITE_CHANNEL)  ?4'b1111:0;
+    // B
+    assign M_BREADY = ((state == WRITE_CHANNEL)||(state == WRESP__CHANNEL)) ? 1 : 0;
+
+
+    always_ff @(posedge ACLK) begin
+        if (~ARESETN) begin
+            state <= IDLE;
+        end else begin
+            state <= next_state;
+        end
+    end
+    
+    always_ff @(posedge ACLK) begin
+        if (~ARESETN) begin
+           read_start <= 0;
+           write_start<= 0;
+        end 
+        else begin
+           read_start <= START_READ;
+           write_start<= START_WRITE;
+        end
+    end
+    
+    always_comb begin
+		case (state)
+            IDLE : begin
+                if (write_start) begin
+                    next_state = WRITE_CHANNEL;
+                end 
+                else if (read_start) begin
+                    next_state = RADDR_CHANNEL;
+                end 
+                else begin
+                    next_state = IDLE;
+                end
+            end
+			RADDR_CHANNEL  : if (M_ARVALID && M_ARREADY  ) next_state = RDATA__CHANNEL;
+			RDATA__CHANNEL : if (M_RVALID  && M_RREADY   ) next_state = IDLE;
+            WRITE_CHANNEL  : if (write_addr && write_data) next_state = WRESP__CHANNEL;
+            WRESP__CHANNEL : if (M_BVALID  && M_BREADY   ) next_state = IDLE;
+			default : next_state = IDLE;
+		endcase
+	end
+endmodule

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv

@@ -0,0 +1,136 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 05/04/2024 05:52:55 PM
+// Design Name: 
+// Module Name: axi4_lite_slave
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module axi4_lite_slave #(
+    parameter ADDRESS = 32,
+    parameter DATA_WIDTH = 32
+    )
+    (
+        //Global Signals
+        input                           ACLK,
+        input                           ARESETN,
+
+        ////Read Address Channel INPUTS
+        input           [ADDRESS-1:0]   S_ARADDR,
+        input                           S_ARVALID,
+        //Read Data Channel INPUTS
+        input                           S_RREADY,
+        //Write Address Channel INPUTS
+        /* verilator lint_off UNUSED */
+        input           [ADDRESS-1:0]   S_AWADDR,
+        input                           S_AWVALID,
+        //Write Data  Channel INPUTS
+        input          [DATA_WIDTH-1:0] S_WDATA,
+        input          [3:0]            S_WSTRB,
+        input                           S_WVALID,
+        //Write Response Channel INPUTS
+        input                           S_BREADY,	
+
+        //Read Address Channel OUTPUTS
+        output logic                    S_ARREADY,
+        //Read Data Channel OUTPUTS
+        output logic    [DATA_WIDTH-1:0]S_RDATA,
+        output logic         [1:0]      S_RRESP,
+        output logic                    S_RVALID,
+        //Write Address Channel OUTPUTS
+        output logic                    S_AWREADY,
+        output logic                    S_WREADY,
+        //Write Response Channel OUTPUTS
+        output logic         [1:0]      S_BRESP,
+        output logic                    S_BVALID
+    );
+
+    localparam no_of_registers = 32;
+
+    logic [DATA_WIDTH-1 : 0] register [no_of_registers-1 : 0];
+    logic [ADDRESS-1 : 0]    addr;
+    logic  write_addr;
+    logic  write_data;
+
+    typedef enum logic [2 : 0] {IDLE,WRITE_CHANNEL,WRESP__CHANNEL, RADDR_CHANNEL, RDATA__CHANNEL} state_type;
+    state_type state , next_state;
+
+    // AR
+    assign S_ARREADY = (state == RADDR_CHANNEL) ? 1 : 0;
+    // 
+    assign S_RVALID = (state == RDATA__CHANNEL) ? 1 : 0;
+    assign S_RDATA  = (state == RDATA__CHANNEL) ? register[addr] : 0;
+    assign S_RRESP  = (state == RDATA__CHANNEL) ?2'b00:0;
+    // AW
+    assign S_AWREADY = (state == WRITE_CHANNEL) ? 1 : 0;
+    // W
+    assign S_WREADY = (state == WRITE_CHANNEL) ? 1 : 0;
+    assign write_addr = S_AWVALID && S_AWREADY;
+    assign write_data = S_WREADY &&S_WVALID;
+    // B
+    assign S_BVALID = (state == WRESP__CHANNEL) ? 1 : 0;
+    assign S_BRESP  = (state == WRESP__CHANNEL )? 0:0;
+
+    integer i;
+
+    always_ff @(posedge ACLK) begin
+        // Reset the register array
+        if (~ARESETN) begin
+            for (i = 0; i < 32; i++) begin
+                register[i] <= 32'b0;
+            end
+        end
+        else begin
+            if (state == WRITE_CHANNEL) begin
+                register[S_AWADDR] <= S_WDATA;
+            end
+            else if (state == RADDR_CHANNEL) begin
+                addr <= S_ARADDR;
+            end
+        end
+    end
+
+    always_ff @(posedge ACLK) begin
+        if (!ARESETN) begin
+            state <= IDLE;
+        end
+        else begin
+            state <= next_state;
+        end
+    end
+
+    always_comb begin
+		case (state)
+            IDLE : begin
+                if (S_AWVALID) begin
+                    next_state = WRITE_CHANNEL;
+                end 
+                else if (S_ARVALID) begin
+                    next_state = RADDR_CHANNEL;
+                end 
+                else begin
+                    next_state = IDLE;
+                end
+            end
+            RADDR_CHANNEL   : if (S_ARVALID && S_ARREADY ) next_state = RDATA__CHANNEL;
+            RDATA__CHANNEL  : if (S_RVALID  && S_RREADY  ) next_state = IDLE;
+            WRITE_CHANNEL   : if (write_addr &&write_data) next_state = WRESP__CHANNEL;
+            WRESP__CHANNEL  : if (S_BVALID  && S_BREADY  ) next_state = IDLE;
+            default : next_state = IDLE;
+        endcase
+    end
+endmodule

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv

@@ -0,0 +1,92 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 05/04/2024 05:52:55 PM
+// Design Name: 
+// Module Name: axi4_lite_top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module axi4_lite_top#(
+    parameter DATA_WIDTH = 32,
+    parameter ADDRESS = 32
+    )(
+        input                           ACLK,
+        input                           ARESETN,
+        input                           read_s,
+        input                           write_s,
+        input    [ADDRESS-1:0]          address,
+        input    [DATA_WIDTH-1:0]       W_data
+    );
+
+    logic  M_ARREADY,S_RVALID,M_ARVALID,M_RREADY,S_AWREADY,S_BVALID,M_AWVALID,M_BREADY,M_WVALID,S_WREADY;
+    logic [ADDRESS-1 : 0] M_ARADDR;
+    logic [ADDRESS-1 : 0] M_AWADDR;
+    logic [DATA_WIDTH-1:0]M_WDATA;
+    logic [DATA_WIDTH-1:0]S_RDATA;
+    logic [3:0]M_WSTRB;
+    logic [1:0]S_RRESP,S_BRESP;
+
+    axi4_lite_master u_axi4_lite_master0
+    (
+        .ACLK(ACLK),
+        .ARESETN(ARESETN),
+        .START_READ(read_s),
+        .address(address),
+        .W_data(W_data),
+        .M_ARREADY(M_ARREADY),
+        .M_RDATA(S_RDATA),
+        .M_RRESP(S_RRESP),
+        .M_RVALID(S_RVALID),
+        .M_ARADDR(M_ARADDR),
+        .M_ARVALID(M_ARVALID),
+        .M_RREADY(M_RREADY),
+        .START_WRITE(write_s),
+        .M_AWREADY(S_AWREADY),
+        .M_WVALID(M_WVALID),
+        .M_WREADY(S_WREADY),
+        .M_BRESP(S_BRESP),
+        .M_BVALID(S_BVALID),
+        .M_AWADDR(M_AWADDR),
+        .M_AWVALID(M_AWVALID),
+        .M_WDATA(M_WDATA),
+        .M_WSTRB(M_WSTRB),
+        .M_BREADY(M_BREADY)
+    );
+
+    axi4_lite_slave u_axi4_lite_slave0
+    (
+        .ACLK(ACLK),
+        .ARESETN(ARESETN),
+        .S_ARREADY(M_ARREADY),
+        .S_RDATA(S_RDATA),
+        .S_RRESP(S_RRESP),
+        .S_RVALID(S_RVALID),
+        .S_ARADDR(M_ARADDR),
+        .S_ARVALID(M_ARVALID),
+        .S_RREADY(M_RREADY),
+        .S_AWREADY(S_AWREADY),
+        .S_WVALID(M_WVALID),
+        .S_WREADY(S_WREADY),
+        .S_BRESP(S_BRESP),
+        .S_BVALID(S_BVALID),
+        .S_AWADDR(M_AWADDR),
+        .S_AWVALID(M_AWVALID),
+        .S_WDATA(M_WDATA),
+        .S_WSTRB(M_WSTRB),
+        .S_BREADY(M_BREADY)
+    );
+endmodule

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/Axi4-lite-vivado.xpr

@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="38" Path="E:/projects/Axi4-lite-vivado/Axi4-lite-vivado.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="21efe0d2eda443e9bd204aa321f74156"/>
+    <Option Name="Part" Val="xc7vx485tffg1157-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSAVendor" Val="xilinx"/>
+    <Option Name="DSANumComputeUnits" Val="60"/>
+    <Option Name="WTXSimLaunchSim" Val="3"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/axi4_lite_master.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/axi4_lite_slave.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/axi4_lite_top.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="axi4_lite_top"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <File Path="$PSRCDIR/sim_1/new/axi4_lite_top_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/waveform.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="axi4_lite_top_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/waveform.wcfg"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+  </Runs>
+  <Board/>
+</Project>

arhamhashmi01_Axi4-lite/source/Axi4-lite-vivado/waveform.wcfg

@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="axi4_lite_top_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="axi4_lite_top_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0fs"></ZoomStartTime>
+      <ZoomEndTime time="135000001fs"></ZoomEndTime>
+      <Cursor1Time time="135000000fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="175"></NameColumnWidth>
+      <ValueColumnWidth column_width="91"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="22" />
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/ACLK" type="logic">
+      <obj_property name="ElementShortName">ACLK</obj_property>
+      <obj_property name="ObjectShortName">ACLK</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/ARESETN" type="logic">
+      <obj_property name="ElementShortName">ARESETN</obj_property>
+      <obj_property name="ObjectShortName">ARESETN</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/read_s" type="logic">
+      <obj_property name="ElementShortName">read_s</obj_property>
+      <obj_property name="ObjectShortName">read_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/write_s" type="logic">
+      <obj_property name="ElementShortName">write_s</obj_property>
+      <obj_property name="ObjectShortName">write_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/state" type="array">
+      <obj_property name="ElementShortName">state[2:0]</obj_property>
+      <obj_property name="ObjectShortName">state[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/M_AWADDR" type="array">
+      <obj_property name="ElementShortName">M_AWADDR[31:0]</obj_property>
+      <obj_property name="ObjectShortName">M_AWADDR[31:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/M_AWVALID" type="logic">
+      <obj_property name="ElementShortName">M_AWVALID</obj_property>
+      <obj_property name="ObjectShortName">M_AWVALID</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_slave0/S_AWREADY" type="logic">
+      <obj_property name="ElementShortName">S_AWREADY</obj_property>
+      <obj_property name="ObjectShortName">S_AWREADY</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/M_WDATA" type="array">
+      <obj_property name="ElementShortName">M_WDATA[31:0]</obj_property>
+      <obj_property name="ObjectShortName">M_WDATA[31:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/M_WVALID" type="logic">
+      <obj_property name="ElementShortName">M_WVALID</obj_property>
+      <obj_property name="ObjectShortName">M_WVALID</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/M_WSTRB" type="array">
+      <obj_property name="ElementShortName">M_WSTRB[3:0]</obj_property>
+      <obj_property name="ObjectShortName">M_WSTRB[3:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_slave0/S_WREADY" type="logic">
+      <obj_property name="ElementShortName">S_WREADY</obj_property>
+      <obj_property name="ObjectShortName">S_WREADY</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_slave0/S_BRESP" type="array">
+      <obj_property name="ElementShortName">S_BRESP[1:0]</obj_property>
+      <obj_property name="ObjectShortName">S_BRESP[1:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_slave0/S_BVALID" type="logic">
+      <obj_property name="ElementShortName">S_BVALID</obj_property>
+      <obj_property name="ObjectShortName">S_BVALID</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/M_BREADY" type="logic">
+      <obj_property name="ElementShortName">M_BREADY</obj_property>
+      <obj_property name="ObjectShortName">M_BREADY</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/M_ARADDR" type="array">
+      <obj_property name="ElementShortName">M_ARADDR[31:0]</obj_property>
+      <obj_property name="ObjectShortName">M_ARADDR[31:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/M_ARVALID" type="logic">
+      <obj_property name="ElementShortName">M_ARVALID</obj_property>
+      <obj_property name="ObjectShortName">M_ARVALID</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/M_ARREADY" type="logic">
+      <obj_property name="ElementShortName">M_ARREADY</obj_property>
+      <obj_property name="ObjectShortName">M_ARREADY</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_master0/M_RREADY" type="logic">
+      <obj_property name="ElementShortName">M_RREADY</obj_property>
+      <obj_property name="ObjectShortName">M_RREADY</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_slave0/S_RDATA" type="array">
+      <obj_property name="ElementShortName">S_RDATA[31:0]</obj_property>
+      <obj_property name="ObjectShortName">S_RDATA[31:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_slave0/S_RVALID" type="logic">
+      <obj_property name="ElementShortName">S_RVALID</obj_property>
+      <obj_property name="ObjectShortName">S_RVALID</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi4_lite_top_tb/u_axi4_lite_top0/u_axi4_lite_slave0/S_RRESP" type="array">
+      <obj_property name="ElementShortName">S_RRESP[1:0]</obj_property>
+      <obj_property name="ObjectShortName">S_RRESP[1:0]</obj_property>
+   </wvobject>
+</wave_config>

arhamhashmi01_Axi4-lite/source/README.md

@@ -0,0 +1,80 @@
+# AXI4-Lite Interface
+## Introduction to AXI4-Lite
+Advanced eXtensible Interface 4 (AXI4) is a family of buses defined as part of the fourth generation of the ARM Advanced Microcontroler Bus Architectrue (AMBA) standard. AXI was first introduced with the third generation of AMBA, as AXI3, in 1996.
+
+**The AMBA specification defines 3 AXI4 protocols:**
+
+**AXI4:** A high performance memory mapped data and address interface. Capable of Burst access to memory mapped devices.
+
+**AXI4-Lite:** A subset of AXI, lacking burst access capability. Has a simpler interface than the full AXI4 interface.
+
+**AXI4-Stream:** A fast unidirectional protocol for transfering data from master to slave.
+
+**Use in Xilinx-Based designs**
+
+Xilinx Vivado helps in the creation of custom IP with AXI4 interfaces. These can be connected to the Zynq’s Proccessing System or to other devices. This Document will cover the operation of the AXI4-Lite interface, which is convenient for implementing memory mapped registers.
+
+**AXI4-Lite Interface Signals**
+
+The AXI4-Lite interface consists of five channels: Read Address, Read Data, Write Address, Write Data, and Write Response. An AXI4 read transaction using the Read Address and Data channels is shown in figure 1. Similarly an AXI4 write transaction using the Write Address, Data, and Response channels is shown in figure 2. Note that these figures depict burst transfers, which AXI4-Lite is incapable of.
+<img src="https://github.com/arhamhashmi01/Axi4-lite/blob/main/block-diagram.png" alt="block diagram of axi4-lite transaction">
+
+### Clock and Reset
+Any AXI component has two global signals: the clock ACLK and an active-low asynchronous reset ARESETN. All AXI4 signals are sampled on the rising edge of the clock and all signal changes must occur aftert the rising edge.
+
+### Handshake Process
+All five transaction channels use the same VALID/READY handshake process to transfer address, data, and control information. This two-way flow control machanism means both the master and slave can control the rate at which the information moves between master and slave. The information source generates the VALID signal to indicate when the address, data or control information is available. The information destination generates the READY signal to indicate that it can accept the information. The handshake completes if both VALID and READY signals in a channel are asserted during a rising clock edge.
+
+## AXI4-Lite Read Transaction
+Below, the sequence for an AXI4-Lite read is shown:
+
+A description of the events in figure 3 follows:
+
+The Master puts an address on the Read Address channel as well as asserting ARVALID,indicating the address is valid, and RREADY, indicating the master is ready to receive data from the slave.
+The Slave asserts ARREADY, indicating that it is ready to receive the address on the bus.
+Since both ARVALID and ARREADY are asserted, on the next rising clock edge the handshake occurs, after this the master and slave deassert ARVALID and the ARREADY, respectively. (At this point, the slave has received the requested address).
+The Slave puts the requested data on the Read Data channel and asserts RVALID, indicating the data in the channel is valid. The slave can also put a response on RRESP, though this does not occur here.
+Since both RREADY and RVALID are asserted, the next rising clock edge completes the transaction. RREADY and RVALID can now be deasserted.
+
+## AXI4-Lite Write Transaction
+Below, the sequence for an AXI4-Lite write is shown:
+
+A description of the events in figure 4 follows:
+
+The Master puts an address on the Write Address channel and data on the Write data channel. At the same time it asserts AWVALID and WVALID indicating the address and data on the respective channels is valid. BREADY is also asserted by the Master, indicating it is ready to receive a response.
+The Slave asserts AWREADY and WREADY on the Write Address and Write Data channels, respectively.
+Since Valid and Ready signals are present on both the Write Address and Write Data channels, the handshakes on those channels occur and the associated Valid and Ready signals can be deasserted. (After both handshakes occur, the slave has the write address and data)
+The Slave asserts BVALID, indicating there is a valid reponse on the Write response channel. (in this case the response is 2’b00, that being ‘OKAY’).
+The next rising clock edge completes the transaction, with both the Ready and Valid signals on the write response channel high.
+
+### RTL-View Of AXI4_Lite
+<img src="https://github.com/arhamhashmi01/Axi4-lite/blob/main/rtl_view.jpg" alt="axi4-lite rtl">
+
+### GTKWAVE
+**Simulation using Vivado**
+<img src="https://github.com/arhamhashmi01/Axi4-lite/blob/main/gtkwave.png" alt="axi4-lite gtkwave">
+
+## Getting Started
+
+To begin exploring the AXI4-Lite interface protocol:
+
+  **1)** Clone this repository to your local machine:
+
+     git clone https://github.com/arhamhashmi01/Axi4-lite.git
+
+  **2)** Navigate to the project directory:
+
+     cd Axi4-lite
+
+  **3)** **For Verilaor:**
+      Run make -> then 
+      make wave
+
+  **4)** **For Vivado:** You can directly get access by the folder by opning it on vivado 
+
+  **4)** Refer to the documentation provided in the repository to build, simulate, or test the processor implementation.
+
+  **5)** Experiment with the design, explore optimizations, or integrate additional features to further enhance the processor's capabilities.
+
+## Contribution
+Contributions to this project are highly encouraged and appreciated! Whether it's bug fixes, feature enhancements, or optimizations, your contributions can help improve the overall quality and functionality of the AXI4-Lite interface protocol.

arhamhashmi01_Axi4-lite/testbenches.json

@@ -0,0 +1,14 @@
+[
+  {
+    "file_path": "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sim_1/new/axi4_lite_top_tb.sv",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "axi4_lite_top",
+    "rtl_files": [
+      "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv",
+      "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_master.sv",
+      "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv"
+    ]
+  }
+]

arhamhashmi01_Axi4-lite/waveform_map.json

@@ -0,0 +1,3 @@
+{
+  "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sim_1/new/axi4_lite_top_tb.sv": "wave_axi4_lite_top.fst"
+}

completed.json

@@ -1,6 +1,6 @@
 {
   "version": 2,
-  "generated_at": "2026-04-06T01:07:53.135451+00:00",
+  "generated_at": "2026-04-06T01:37:45.770173+00:00",
   "entries": {
     "chili-chips-ba_wireguard-fpga/led_test__led_test/blocking_nonblocking": {
       "status": "sim_ok",
@@ -942,7 +942,7 @@
       "status": "waveform_identical"
     },
     "JN513_Risco-5/ClkDivider__clk_divider/missing_enable": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
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     "JN513_Risco-5/ClkDivider__clk_divider/missing_reset": {
       "status": "waveform_identical"
@@ -954,16 +954,16 @@
       "status": "waveform_identical"
     },
     "JN513_Risco-5/Core__alu/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__alu/operator_typo": {
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__alu_control/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__alu_control/inverted_condition": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__alu_control/operator_typo": {
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@@ -972,16 +972,16 @@
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__control_unit/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__control_unit/inverted_condition": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__control_unit/missing_enable": {
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__control_unit/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__control_unit/operator_typo": {
       "status": "sim_failed"
@@ -993,13 +993,13 @@
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__core/inverted_condition": {
-      "status": "sim_ok"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__core/missing_enable": {
-      "status": "sim_ok"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__core/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__core/operator_typo": {
       "status": "sim_failed"
@@ -1011,19 +1011,19 @@
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__csr_unit/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__csr_unit/concat_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__csr_unit/inverted_condition": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__csr_unit/missing_enable": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__csr_unit/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__csr_unit/operator_typo": {
       "status": "sim_failed"
@@ -1032,16 +1032,16 @@
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__immediate_generator/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__immediate_generator/concat_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__leds/missing_enable": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__leds/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__leds/operator_typo": {
       "status": "sim_failed"
@@ -1050,13 +1050,13 @@
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__mdu/inverted_condition": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__mdu/missing_enable": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__mdu/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__mdu/operator_typo": {
       "status": "sim_failed"
@@ -1068,16 +1068,16 @@
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__memory/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__memory/concat_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__memory/inverted_condition": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__memory/missing_enable": {
-      "status": "sim_ok"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__memory/operator_typo": {
       "status": "sim_failed"
@@ -1086,22 +1086,22 @@
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__mux/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__pc/missing_enable": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__pc/missing_reset": {
-      "status": "sim_ok"
+      "status": "sim_failed"
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     "JN513_Risco-5/Core__pc/operator_typo": {
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__registers/missing_enable": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__registers/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__registers/operator_typo": {
       "status": "sim_failed"
@@ -1116,7 +1116,7 @@
       "status": "waveform_identical"
     },
     "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Master/state_transition": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Slave/case_swap": {
       "status": "waveform_identical"
@@ -1140,7 +1140,7 @@
       "status": "waveform_identical"
     },
     "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Wrapper/unconnected_port": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__RAM/case_swap": {
       "status": "sim_ok"
@@ -1158,7 +1158,7 @@
       "status": "sim_ok"
     },
     "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/inverted_condition": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/missing_enable": {
       "status": "sim_ok"
@@ -1230,7 +1230,7 @@
       "status": "waveform_identical"
     },
     "Weiyet_RTLStructLib/dual_edge_ff__dual_edge_ff/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "Weiyet_RTLStructLib/dual_edge_ff__dual_edge_ff/missing_enable": {
       "status": "sim_ok"
@@ -1245,7 +1245,7 @@
       "status": "sim_ok"
     },
     "Weiyet_RTLStructLib/fifo__fifo/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
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       "status": "sim_ok"
@@ -1257,7 +1257,7 @@
       "status": "sim_ok"
     },
     "Weiyet_RTLStructLib/hash_table__hash_table/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
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@@ -1305,7 +1305,7 @@
       "status": "sim_ok"
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     "Weiyet_RTLStructLib/list__list/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
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@@ -1326,7 +1326,7 @@
       "status": "sim_ok"
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-      "status": "compile_error"
+      "status": "sim_ok"
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       "status": "sim_ok"
@@ -1341,7 +1341,7 @@
       "status": "sim_ok"
     },
     "Weiyet_RTLStructLib/singly_linked_list__singly_linked_list/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
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       "status": "sim_ok"
@@ -1362,7 +1362,7 @@
       "status": "waveform_identical"
     },
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-      "status": "waveform_identical"
+      "status": "sim_ok"
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     "accomdemy_accomdemy_rv32i/cpu__alu/operator_typo": {
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@@ -1371,7 +1371,7 @@
       "status": "waveform_identical"
     },
     "accomdemy_accomdemy_rv32i/cpu__branch/missing_enable": {
-      "status": "waveform_identical"
+      "status": "sim_ok"
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     "accomdemy_accomdemy_rv32i/cpu__branch/operator_typo": {
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@@ -1404,19 +1404,19 @@
       "status": "waveform_identical"
     },
     "accomdemy_accomdemy_rv32i/cpu__instr_memory/concat_swap": {
-      "status": "waveform_identical"
+      "status": "sim_ok"
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-      "status": "sim_ok"
+      "status": "waveform_identical"
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       "status": "sim_ok"
     },
     "accomdemy_accomdemy_rv32i/cpu__pc/missing_reset": {
-      "status": "compile_error"
+      "status": "sim_ok"
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+      "status": "sim_ok"
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@@ -1431,160 +1431,160 @@
       "status": "waveform_identical"
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+      "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__LDU/concat_swap": {
       "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__MEM_WB/missing_reset": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC/missing_reset": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC_Adderr/missing_enable": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/missing_enable": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/missing_reset": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/operator_typo": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/wrong_bitwidth": {
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RISCV_CPU/operator_typo": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RISCV_CPU/unconnected_port": {
       "status": "sim_ok"
@@ -1596,28 +1596,28 @@
       "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/concat_swap": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/delayed_signal": {
       "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/inverted_condition": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/missing_enable": {
-      "status": "compile_error"
+      "status": "timeout"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/missing_reset": {
       "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/off_by_one_counter": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/operator_typo": {
       "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/wrong_bitwidth": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/case_swap": {
       "status": "llm_failed"
@@ -1656,19 +1656,19 @@
       "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/transpose__delayline/wrong_bitwidth": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/transpose__transpose/delayed_signal": {
       "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/transpose__transpose/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/transpose__transpose/missing_enable": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/transpose__transpose/off_by_one_counter": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/transpose__transpose/operator_typo": {
       "status": "sim_ok"
@@ -1797,13 +1797,13 @@
       "status": "timeout"
     },
     "defano_digital-design/uart__uart/operator_typo": {
-      "status": "llm_failed"
+      "status": "sim_ok"
     },
     "defano_digital-design/uart__uart/unconnected_port": {
       "status": "sim_ok"
     },
     "defano_digital-design/uart__uart/wrong_bitwidth": {
-      "status": "llm_failed"
+      "status": "timeout"
     },
     "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/inverted_condition": {
       "status": "waveform_identical"
@@ -1929,7 +1929,7 @@
       "status": "sim_ok"
     },
     "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/missing_reset": {
-      "status": "timeout"
+      "status": "sim_ok"
     },
     "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/operator_typo": {
       "status": "waveform_identical"
@@ -1947,10 +1947,10 @@
       "status": "waveform_identical"
     },
     "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/state_transition": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "mnmhdanas_Router-1-x-3-/router_reg__router_reg/inverted_condition": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "mnmhdanas_Router-1-x-3-/router_reg__router_reg/missing_enable": {
       "status": "waveform_identical"
@@ -1986,7 +1986,7 @@
       "status": "sim_ok"
     },
     "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/missing_reset": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/state_transition": {
       "status": "sim_ok"
@@ -2361,7 +2361,7 @@
       "status": "sim_ok"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__accelerator/unconnected_port": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__comparator2/concat_swap": {
       "status": "waveform_identical"
@@ -2397,7 +2397,7 @@
       "status": "waveform_identical"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/missing_reset": {
-      "status": "timeout"
+      "status": "waveform_identical"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/operator_typo": {
       "status": "waveform_identical"
@@ -2415,13 +2415,13 @@
       "status": "waveform_identical"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/missing_reset": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/operator_typo": {
       "status": "waveform_identical"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/unconnected_port": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/wrong_bitwidth": {
       "status": "sim_ok"
@@ -2457,7 +2457,7 @@
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__code_defs_pkg/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__code_defs_pkg/operator_typo": {
       "status": "waveform_identical"
@@ -2466,43 +2466,43 @@
       "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__mac/missing_reset": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__mac/unconnected_port": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/concat_swap": {
       "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/missing_enable": {
       "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/missing_reset": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/operator_typo": {
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/unconnected_port": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/wrong_bitwidth": {
       "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/case_swap": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/concat_swap": {
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/missing_enable": {
       "status": "waveform_identical"
@@ -2511,7 +2511,7 @@
       "status": "compile_error"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/off_by_one_counter": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/operator_typo": {
       "status": "llm_failed"
@@ -2520,25 +2520,25 @@
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/unconnected_port": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/wrong_bitwidth": {
       "status": "timeout"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/case_swap": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/concat_swap": {
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/missing_enable": {
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/missing_reset": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/operator_typo": {
       "status": "sim_ok"
@@ -2550,13 +2550,13 @@
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/missing_enable": {
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/missing_reset": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/operator_typo": {
       "status": "sim_ok"
@@ -2565,25 +2565,25 @@
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/missing_reset": {
-      "status": "compile_error"
+      "status": "timeout"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/off_by_one_counter": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/operator_typo": {
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/missing_reset": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/off_by_one_counter": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/operator_typo": {
       "status": "sim_ok"
@@ -2595,16 +2595,16 @@
       "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__mac_pcs/unconnected_port": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/missing_reset": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/operator_typo": {
       "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/unconnected_port": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/wrong_bitwidth": {
       "status": "waveform_identical"
@@ -2616,7 +2616,7 @@
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/missing_reset": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/operator_typo": {
       "status": "sim_ok"
@@ -2625,13 +2625,13 @@
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/missing_reset": {
       "status": "compile_error"
     },
     "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/off_by_one_counter": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/operator_typo": {
       "status": "sim_ok"
@@ -2643,13 +2643,13 @@
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/inverted_condition": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/missing_enable": {
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/missing_reset": {
-      "status": "compile_error"
+      "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/operator_typo": {
       "status": "sim_ok"
@@ -2688,7 +2688,7 @@
       "status": "sim_ok"
     },
     "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/off_by_one_counter": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/operator_typo": {
       "status": "sim_ok"
@@ -2697,7 +2697,7 @@
       "status": "sim_ok"
     },
     "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/unconnected_port": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/wrong_bitwidth": {
       "status": "sim_ok"
@@ -3790,10 +3790,43 @@
     },
     "yaseensalah_Digital-Design-of-FIR-Filter/fir_filter__fir_filter/wrong_bitwidth": {
       "status": "waveform_identical"
+    },
+    "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_master/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_master/missing_reset": {
+      "status": "waveform_identical"
+    },
+    "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_master/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_master/state_transition": {
+      "status": "sim_ok"
+    },
+    "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_slave/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_slave/missing_reset": {
+      "status": "sim_ok"
+    },
+    "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_slave/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_slave/state_transition": {
+      "status": "sim_ok"
+    },
+    "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_slave/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_top/unconnected_port": {
+      "status": "waveform_identical"
+    },
+    "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_top/wrong_bitwidth": {
+      "status": "waveform_identical"
     }
   },
   "bug_types_attempted": {
-    "scarv_xcrypto": [
+    "accomdemy_accomdemy_rv32i": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -3810,7 +3843,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "fcayci_sv-digital-design": [
+    "MohamedHussein27_SPI_Slave_With_Single_Port_Memory": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -3827,7 +3860,20 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "OrsuVenkataKrishnaiah1235_RTL-Coding": [
+    "erihsu_INT_FP_MAC": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "lucky-wfw_IC_System_Design": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -3844,7 +3890,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "JN513_Risco-5": [
+    "defano_digital-design": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -3861,7 +3907,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "nimanaqavi_Verilog-MathFunctions": [
+    "akira2963753_Pipelined-RV32-SoC": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -3878,7 +3924,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "thejefflarson_little-cpu": [
+    "MohamedHussein27_AMPA_APB4_Protocol": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -3895,7 +3941,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "aditeyabaral_DDCO-Lab-UE18CS207": [
+    "0thbit_CRC_parallel": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -3908,7 +3954,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "biren15_Design-and-Verification-of-LDPC-Decoder": [
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -3921,7 +3967,17 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "meiniKi_FazyRV": [
+    "chili-chips-ba_wireguard-fpga": [
+      "blocking_nonblocking",
+      "inverted_condition",
+      "missing_else_latch",
+      "missing_reset",
+      "operator_typo",
+      "signal_typo",
+      "unconnected_port",
+      "wrong_bitwidth"
+    ],
+    "selimsandal_OneShotNPU": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -3938,24 +3994,21 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "ttchisholm_10g-low-latency-ethernet": [
+    "zhangxin6_iverilog_testbench": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3": [
+    "dpretet_async_fifo": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -3968,7 +4021,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "selimsandal_OneShotNPU": [
+    "mnmhdanas_Router-1-x-3-": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -3985,7 +4038,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "qossayrida_PipelineProcessorDesign": [
+    "projf_isle": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -3998,24 +4051,20 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "MohamedHussein27_AMPA_APB4_Protocol": [
-      "blocking_nonblocking",
+    "srpoyrek_RISC-V": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "erihsu_INT_FP_MAC": [
+    "Weiyet_RTLStructLib": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4028,34 +4077,41 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "thedatabusdotio_fpga-ml-accelerator": [
+    "nimanaqavi_Verilog-MathFunctions": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM": [
+    "apfaudio_eurorack-pmod": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "zhangxin6_iverilog_testbench": [
-      "blocking_nonblocking",
+    "yaseensalah_Digital-Design-of-FIR-Filter": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4068,23 +4124,24 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "phoeniX-Digital-Design_phoeniX": [
-      "blocking_nonblocking"
-    ],
-    "MohamedHussein27_RISC-V-Single-Cycle-Implementation": [
+    "fcayci_sv-digital-design": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Mr-Bossman_KISC-V": [
+    "ttchisholm_10g-low-latency-ethernet": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4118,47 +4175,58 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "shahsaumya00_Floating-Point-Adder": [
-      "blocking_nonblocking",
+    "biren15_Design-and-Verification-of-LDPC-Decoder": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "chili-chips-ba_wireguard-fpga": [
+    "thejefflarson_little-cpu": [
       "blocking_nonblocking",
+      "case_swap",
+      "concat_swap",
+      "delayed_signal",
       "inverted_condition",
       "missing_else_latch",
+      "missing_enable",
       "missing_reset",
+      "off_by_one_counter",
       "operator_typo",
       "signal_typo",
+      "state_transition",
       "unconnected_port",
+      "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "dpretet_async_fifo": [
+    "OrsuVenkataKrishnaiah1235_RTL-Coding": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "lucky-wfw_IC_System_Design": [
+    "alexforencich_verilog-axi": [
+      "case_swap",
+      "concat_swap"
+    ],
+    "scarv_xcrypto": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4175,7 +4243,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "apfaudio_eurorack-pmod": [
+    "meiniKi_FazyRV": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4192,20 +4260,24 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "yaseensalah_Digital-Design-of-FIR-Filter": [
+    "shahsaumya00_Floating-Point-Adder": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "projf_isle": [
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4218,7 +4290,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "accomdemy_accomdemy_rv32i": [
+    "meiniKi_RV32I_SC_Logisim": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4235,7 +4307,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "0thbit_CRC_parallel": [
+    "roo16kie_MAC_Verilog": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4248,11 +4320,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "alexforencich_verilog-axi": [
-      "case_swap",
-      "concat_swap"
-    ],
-    "srpoyrek_RISC-V": [
+    "arhamhashmi01_Axi4-lite": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4265,24 +4333,20 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "mnmhdanas_Router-1-x-3-": [
-      "blocking_nonblocking",
+    "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "akira2963753_Pipelined-RV32-SoC": [
+    "Fraunhofer-IMS_airisc_core_complex": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4299,7 +4363,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Weiyet_RTLStructLib": [
+    "thedatabusdotio_fpga-ml-accelerator": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4312,7 +4376,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Vaibhav-Gunthe_Verilog-Projects": [
+    "MohamedHussein27_RISC-V-Single-Cycle-Implementation": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4325,7 +4389,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "mnmhdanas_UART-protocol": [
+    "JN513_Risco-5": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4342,58 +4406,36 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Fraunhofer-IMS_airisc_core_complex": [
-      "blocking_nonblocking",
+    "Vaibhav-Gunthe_Verilog-Projects": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "MohamedHussein27_SPI_Slave_With_Single_Port_Memory": [
-      "blocking_nonblocking",
-      "case_swap",
-      "concat_swap",
-      "delayed_signal",
-      "inverted_condition",
-      "missing_else_latch",
-      "missing_enable",
-      "missing_reset",
-      "off_by_one_counter",
-      "operator_typo",
-      "signal_typo",
-      "state_transition",
-      "unconnected_port",
-      "width_bit_cutoff",
-      "wrong_bitwidth"
+    "phoeniX-Digital-Design_phoeniX": [
+      "blocking_nonblocking"
     ],
-    "meiniKi_RV32I_SC_Logisim": [
-      "blocking_nonblocking",
+    "aditeyabaral_DDCO-Lab-UE18CS207": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules": [
+    "qossayrida_PipelineProcessorDesign": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4406,7 +4448,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "defano_digital-design": [
+    "mnmhdanas_UART-protocol": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4423,14 +4465,18 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "roo16kie_MAC_Verilog": [
+    "Mr-Bossman_KISC-V": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",

manifest.json

@@ -147,112 +147,7 @@
     "repo": "JN513/Risco-5",
     "clone_url": "https://github.com/JN513/Risco-5.git",
     "commit_sha": "12a570c7124f5f78f2c9513248f8e6bd85137068",
-    "testbenches": [
-      {
-        "file_path": "tests/core_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Core",
-        "rtl_files": [
-          "src/core/core.v",
-          "src/core/pc.v",
-          "src/core/mux.v",
-          "src/core/registers.v",
-          "src/core/control_unit.v",
-          "src/core/alu_control.v",
-          "src/core/alu.v",
-          "src/core/immediate_generator.v",
-          "src/core/csr_unit.v",
-          "src/core/mdu.v",
-          "src/peripheral/memory.v",
-          "src/peripheral/bus.v",
-          "src/peripheral/leds.v"
-        ]
-      },
-      {
-        "file_path": "tests/registers_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Registers",
-        "rtl_files": [
-          "src/core/registers.v"
-        ]
-      },
-      {
-        "file_path": "tests/soc_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Risco_5_SOC",
-        "rtl_files": [
-          "src/peripheral/soc.v",
-          "src/core/core.v",
-          "src/core/pc.v",
-          "src/core/mux.v",
-          "src/core/registers.v",
-          "src/core/control_unit.v",
-          "src/core/alu_control.v",
-          "src/core/alu.v",
-          "src/core/immediate_generator.v",
-          "src/core/csr_unit.v",
-          "src/core/mdu.v",
-          "src/peripheral/memory.v",
-          "src/peripheral/bus.v",
-          "src/peripheral/leds.v",
-          "src/peripheral/uart.v",
-          "src/peripheral/uart_rx.v",
-          "src/peripheral/uart_tx.v",
-          "src/peripheral/fifo.v",
-          "src/peripheral/gpios.v",
-          "src/peripheral/gpio.v",
-          "src/peripheral/pwm.v"
-        ]
-      },
-      {
-        "file_path": "tests/gpio_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "GPIOS",
-        "rtl_files": [
-          "src/peripheral/gpios.v",
-          "src/peripheral/gpio.v",
-          "src/peripheral/pwm.v"
-        ]
-      },
-      {
-        "file_path": "tests/pc_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "PC",
-        "rtl_files": [
-          "src/core/pc.v"
-        ]
-      },
-      {
-        "file_path": "tests/clk_divider.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "ClkDivider",
-        "rtl_files": [
-          "debug/clk_divider.v"
-        ]
-      },
-      {
-        "file_path": "tests/reset_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "ResetBootSystem",
-        "rtl_files": [
-          "debug/reset.v"
-        ]
-      }
-    ]
+    "testbenches": []
   },
   "Mr-Bossman_KISC-V": {
     "repo": "Mr-Bossman/KISC-V",
@@ -331,133 +226,13 @@
     "repo": "accomdemy/accomdemy_rv32i",
     "clone_url": "https://github.com/accomdemy/accomdemy_rv32i.git",
     "commit_sha": "4f75b555a0e0419e2417294f85df202ba0415e4b",
-    "testbenches": [
-      {
-        "file_path": "sim/cpu_tb.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "cpu",
-        "rtl_files": [
-          "src/cpu.v",
-          "src/alu.v",
-          "src/branch.v",
-          "src/decoder.v",
-          "src/dm_control.v",
-          "src/instr_memory.v",
-          "src/MUX2to1_32bit.v",
-          "src/MUX4to1_32bit.v",
-          "src/pc.v",
-          "src/regfile.v"
-        ]
-      }
-    ]
+    "testbenches": []
   },
   "akira2963753_Pipelined-RV32-SoC": {
     "repo": "akira2963753/Pipelined-RV32-SoC",
     "clone_url": "https://github.com/akira2963753/Pipelined-RV32-SoC.git",
     "commit_sha": "ded74adc6a29ef5bbdac56a5eac5b99328064371",
-    "testbenches": [
-      {
-        "file_path": "source/Five-Stage-Pipelined-CPU/RTL/RISCV_CPU_tb.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "RISCV_CPU",
-        "rtl_files": [
-          "source/Five-Stage-Pipelined-CPU/RTL/ALU.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/ALU_Control.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/BHT.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/BPU.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/BTB.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/CSR.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/Control.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/D_Mem.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/EX_MEM.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/Forwarding_Unit.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/Hazard_Unit.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/ID_EX.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/IF_ID.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/I_Mem.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/ImmGen.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/LDU.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/MEM_WB.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/PC.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/PC_Adderr.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/RF.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/RISCV_CPU.v"
-        ]
-      },
-      {
-        "file_path": "source/RISC-V-Processor/RTL/RISCV_PROCESSOR_tb.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "RISCV_PROCESSOR",
-        "rtl_files": [
-          "source/RISC-V-Processor/RTL/ALU.v",
-          "source/RISC-V-Processor/RTL/ALU_Control.v",
-          "source/RISC-V-Processor/RTL/AXI4_Lite_Bus.v",
-          "source/RISC-V-Processor/RTL/BHT.v",
-          "source/RISC-V-Processor/RTL/BPU.v",
-          "source/RISC-V-Processor/RTL/BTB.v",
-          "source/RISC-V-Processor/RTL/CSR.v",
-          "source/RISC-V-Processor/RTL/Control.v",
-          "source/RISC-V-Processor/RTL/D_BRAM.v",
-          "source/RISC-V-Processor/RTL/D_Cache.v",
-          "source/RISC-V-Processor/RTL/D_Mem.v",
-          "source/RISC-V-Processor/RTL/EX_MEM.v",
-          "source/RISC-V-Processor/RTL/Forwarding_Unit.v",
-          "source/RISC-V-Processor/RTL/Hazard_Unit.v",
-          "source/RISC-V-Processor/RTL/ID_EX.v",
-          "source/RISC-V-Processor/RTL/IF_ID.v",
-          "source/RISC-V-Processor/RTL/I_Cache.v",
-          "source/RISC-V-Processor/RTL/ImmGen.v",
-          "source/RISC-V-Processor/RTL/LDU.v",
-          "source/RISC-V-Processor/RTL/MEM_WB.v",
-          "source/RISC-V-Processor/RTL/PC.v",
-          "source/RISC-V-Processor/RTL/PC_Adder.v",
-          "source/RISC-V-Processor/RTL/RF.v",
-          "source/RISC-V-Processor/RTL/RISCV_CPU.v",
-          "source/RISC-V-Processor/RTL/RISCV_PROCESSOR.v"
-        ]
-      },
-      {
-        "file_path": "source/CACHE/AXI4-LITE/Pattern.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Tested",
-        "rtl_files": [
-          "source/CACHE/AXI4-LITE/Tested.v",
-          "source/CACHE/AXI4-LITE/AXI4_Lite_Bus.v"
-        ]
-      },
-      {
-        "file_path": "source/CACHE/I-CACHE/Pattern.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Tested",
-        "rtl_files": [
-          "source/CACHE/I-CACHE/Tested.v",
-          "source/CACHE/I-CACHE/Cache.v",
-          "source/CACHE/I-CACHE/AXI4_Lite_Bus.v"
-        ]
-      },
-      {
-        "file_path": "source/CACHE/D-CACHE/Pattern.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Tested",
-        "rtl_files": [
-          "source/CACHE/D-CACHE/Tested.v",
-          "source/CACHE/D-CACHE/D_Cache.v",
-          "source/CACHE/D-CACHE/AXI4_Lite_Bus.v"
-        ]
-      }
-    ]
+    "testbenches": []
   },
   "thejefflarson_little-cpu": {
     "repo": "thejefflarson/little-cpu",
@@ -487,244 +262,19 @@
     "repo": "Abdelrahman1810/SPI_Slave_with_Single_Port_RAM",
     "clone_url": "https://github.com/Abdelrahman1810/SPI_Slave_with_Single_Port_RAM.git",
     "commit_sha": "6233b161a0428ec0a0e22b6e74373c4d8d98d972",
-    "testbenches": [
-      {
-        "file_path": "Codes/testbench/tb_SPI.sv",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "SPI",
-        "rtl_files": [
-          "Codes/RTL/SPI.v"
-        ]
-      },
-      {
-        "file_path": "Codes/testbench/tb_instantiation.sv",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "instantiation",
-        "rtl_files": [
-          "Codes/RTL/instantiation.v",
-          "Codes/RTL/SPI.v",
-          "Codes/RTL/RAM.v"
-        ]
-      },
-      {
-        "file_path": "Codes/testbench/tb_ram.sv",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "RAM",
-        "rtl_files": [
-          "Codes/RTL/RAM.v"
-        ]
-      }
-    ]
+    "testbenches": []
   },
   "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules": {
     "repo": "daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules",
     "clone_url": "https://github.com/daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules.git",
     "commit_sha": "0da4e865fb717d6221977ba285118f9a97c6158b",
-    "testbenches": [
-      {
-        "file_path": "tb.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "spi_top",
-        "rtl_files": [
-          "spi_top.v",
-          "spi_clgen.v",
-          "spi_shift_reg.v",
-          "spi_slave.v",
-          "spi_defines.v",
-          "wishbone_master.v"
-        ]
-      }
-    ]
+    "testbenches": []
   },
   "projf_isle": {
     "repo": "projf/isle",
     "clone_url": "https://github.com/projf/isle.git",
     "commit_sha": "ff248e1db8cd70c4a52399c96dee1554bf5baeac",
-    "testbenches": [
-      {
-        "file_path": "hardware/tests/book/ch01.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/book/ch01.mk",
-        "top_module": "ch01",
-        "rtl_files": [
-          "hardware/book/ch01/ch01.v",
-          "hardware/gfx/display.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/book/ch02.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/book/ch02.mk",
-        "top_module": "ch02",
-        "rtl_files": [
-          "hardware/book/ch02/ch02.v",
-          "hardware/gfx/canv_disp_agu.v",
-          "hardware/gfx/display.v",
-          "hardware/mem/clut.v",
-          "hardware/mem/vram.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/book/ch03.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/book/ch03.mk",
-        "top_module": "ch03",
-        "rtl_files": [
-          "hardware/book/ch03/ch03.v",
-          "hardware/gfx/canv_disp_agu.v",
-          "hardware/gfx/canv_draw_agu.v",
-          "hardware/gfx/circle.v",
-          "hardware/gfx/display.v",
-          "hardware/gfx/earthrise.v",
-          "hardware/gfx/fline.v",
-          "hardware/gfx/line.v",
-          "hardware/mem/clut.v",
-          "hardware/mem/erlist.v",
-          "hardware/mem/vram.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/book/ch04.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/book/ch04.mk",
-        "top_module": "ch04",
-        "rtl_files": [
-          "hardware/book/ch04/ch04.v",
-          "hardware/gfx/display.v",
-          "hardware/gfx/font_glyph.v",
-          "hardware/gfx/textmode.v",
-          "hardware/mem/clut.v",
-          "hardware/mem/rom_sync.v",
-          "hardware/mem/tram.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/book/ch05.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/book/ch05.mk",
-        "top_module": "ch05",
-        "rtl_files": [
-          "hardware/book/ch05/ch05.v",
-          "hardware/cpu/FemtoRV32.v",
-          "hardware/gfx/display.v",
-          "hardware/gfx/font_glyph.v",
-          "hardware/gfx/textmode.v",
-          "hardware/mem/clut.v",
-          "hardware/mem/rom_sync.v",
-          "hardware/mem/sysram.v",
-          "hardware/mem/tram.v",
-          "hardware/sys/xd.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/book/ch06.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/book/ch06.mk",
-        "top_module": "ch06",
-        "rtl_files": [
-          "hardware/book/ch06/ch06.v",
-          "hardware/cpu/FemtoRV32.v",
-          "hardware/devs/gfx_dev.v",
-          "hardware/devs/sys_dev.v",
-          "hardware/devs/uart_dev.v",
-          "hardware/gfx/display.v",
-          "hardware/gfx/font_glyph.v",
-          "hardware/gfx/textmode.v",
-          "hardware/io/uart_rx.v",
-          "hardware/math/lfsr.v",
-          "hardware/mem/clut.v",
-          "hardware/mem/fifo_sync.v",
-          "hardware/mem/rom_sync.v",
-          "hardware/mem/sysram.v",
-          "hardware/mem/tram.v",
-          "hardware/sys/xd.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/gfx/canv_disp_agu.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/gfx/canv_disp_agu.mk",
-        "top_module": "canv_disp_agu",
-        "rtl_files": [
-          "hardware/gfx/canv_disp_agu.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/gfx/display.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/gfx/display.mk",
-        "top_module": "display",
-        "rtl_files": [
-          "hardware/gfx/display.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/gfx/tmds_encoder.py",
-        "tb_type": "cocotb",
-        "simulator": "verilator",
-        "makefile_path": "hardware/tests/gfx/tmds_encoder.mk",
-        "top_module": "tmds_encoder",
-        "rtl_files": [
-          "hardware/gfx/tmds_encoder.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/io/uart_rx.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/io/uart_rx.mk",
-        "top_module": "uart_rx",
-        "rtl_files": [
-          "hardware/io/uart_rx.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/io/uart_tx.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/io/uart_tx.mk",
-        "top_module": "uart_tx",
-        "rtl_files": [
-          "hardware/io/uart_tx.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/mem/clut.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/mem/clut.mk",
-        "top_module": "clut",
-        "rtl_files": [
-          "hardware/mem/clut.v"
-        ]
-      },
-      {
-        "file_path": "hardware/tests/mem/vram.py",
-        "tb_type": "cocotb",
-        "simulator": "icarus",
-        "makefile_path": "hardware/tests/mem/vram.mk",
-        "top_module": "vram",
-        "rtl_files": [
-          "hardware/mem/vram.v"
-        ]
-      }
-    ]
+    "testbenches": []
   },
   "MohamedHussein27_RISC-V-Single-Cycle-Implementation": {
     "repo": "MohamedHussein27/RISC-V-Single-Cycle-Implementation",
@@ -850,88 +400,7 @@
     "repo": "circuitvalley/USB_C_Industrial_Camera_FPGA_USB3",
     "clone_url": "https://github.com/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3.git",
     "commit_sha": "f870a4f4afb68a6a32e525b23f479d8d98161576",
-    "testbenches": [
-      {
-        "file_path": "FPGA_Firmware/Source/Testblocks/tb_camera_controller.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "camera_controller",
-        "rtl_files": [
-          "FPGA_Firmware/Source/src/camera_controller.v"
-        ]
-      },
-      {
-        "file_path": "FPGA_Firmware/Source/Testblocks/tb_mipi_rx_raw_depacker.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "mipi_csi_rx_raw_depacker_8b2lane_2ppc",
-        "rtl_files": [
-          "FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_8b2lane_2ppc.v"
-        ]
-      },
-      {
-        "file_path": "FPGA_Firmware/Source/Testblocks/tb_mipi_rx_raw_depacker8b4_10bit.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "mipi_csi_rx_raw_depacker_8b4lane",
-        "rtl_files": [
-          "FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_8b4lane.v"
-        ]
-      },
-      {
-        "file_path": "FPGA_Firmware/Source/Testblocks/tb_mipi_rx_raw_depacker8b4_12bit.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "mipi_csi_rx_raw_depacker_8b4lane",
-        "rtl_files": [
-          "FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_8b4lane.v"
-        ]
-      },
-      {
-        "file_path": "FPGA_Firmware/Source/Testblocks/tb_mipi_rx_raw_depacker8b4_14bit.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "mipi_csi_rx_raw_depacker_8b4lane",
-        "rtl_files": [
-          "FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_8b4lane.v"
-        ]
-      },
-      {
-        "file_path": "FPGA_Firmware/Source/Testblocks/tb_mipi_rx_raw_depacker_12bit2.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "mipi_csi_rx_raw_depacker_8b2lane_2ppc",
-        "rtl_files": [
-          "FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_8b2lane_2ppc.v"
-        ]
-      },
-      {
-        "file_path": "FPGA_Firmware/Source/Testblocks/tb_mipi_rx_raw_depacker_14bit2.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "mipi_csi_rx_raw_depacker_8b2lane_2ppc",
-        "rtl_files": [
-          "FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_8b2lane_2ppc.v"
-        ]
-      },
-      {
-        "file_path": "FPGA_Firmware/Source/Testblocks/tb_rx_raw_depacker_8b2lane_10bit.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "mipi_csi_rx_raw_depacker_8b2lane",
-        "rtl_files": [
-          "FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_8b2lane.v"
-        ]
-      }
-    ]
+    "testbenches": []
   },
   "biren15_Design-and-Verification-of-LDPC-Decoder": {
     "repo": "biren15/Design-and-Verification-of-LDPC-Decoder",
@@ -1183,5 +652,24 @@
         ]
       }
     ]
+  },
+  "arhamhashmi01_Axi4-lite": {
+    "repo": "arhamhashmi01/Axi4-lite",
+    "clone_url": "https://github.com/arhamhashmi01/Axi4-lite.git",
+    "commit_sha": "bc334fa7118f49e88d20dc53bfa887d5db293620",
+    "testbenches": [
+      {
+        "file_path": "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sim_1/new/axi4_lite_top_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "axi4_lite_top",
+        "rtl_files": [
+          "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_top.sv",
+          "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_master.sv",
+          "Axi4-lite-vivado/Axi4-lite-vivado.srcs/sources_1/new/axi4_lite_slave.sv"
+        ]
+      }
+    ]
   }
 }