Add files using upload-large-folder tool

WilliamZhang20_ECE298A-TPU/sim_script_map.json

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+{
+  "test/control_unit/test_control_unit.py": "control_unit_tb_sim.sh",
+  "test/memory/test_memory.py": "memory_tb_sim.sh",
+  "test/mmu_feeder/test_mmu_feeder.py": "mmu_feeder_tb_sim.sh",
+  "test/systolic_array/test_systolic_array.py": "systolic_array_tb_sim.sh"
+}

WilliamZhang20_ECE298A-TPU/simulations.jsonl

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+{"tb_file_path": "test/control_unit/test_control_unit.py", "simulator": "cocotb", "top_module": "control_unit_tb", "work_subdir": "test", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "control_unit_tb", "MODULE": "test_control_unit"}, "target": "test-control-unit", "clean_first": false}}
+{"tb_file_path": "test/memory/test_memory.py", "simulator": "cocotb", "top_module": "memory_tb", "work_subdir": "test", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "memory_tb", "MODULE": "test_memory"}, "target": "test-memory", "clean_first": false}}
+{"tb_file_path": "test/mmu_feeder/test_mmu_feeder.py", "simulator": "cocotb", "top_module": "mmu_feeder_tb", "work_subdir": "test", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "mmu_feeder_tb", "MODULE": "test_mmu_feeder"}, "target": "test-mmu-feeder", "clean_first": false}}
+{"tb_file_path": "test/systolic_array/test_systolic_array.py", "simulator": "cocotb", "top_module": "systolic_array_tb", "work_subdir": "test", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "systolic_array_tb", "MODULE": "test_systolic_array"}, "target": "test-systolic-array", "clean_first": false}}

WilliamZhang20_ECE298A-TPU/source/.devcontainer/Dockerfile

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+ARG VARIANT=ubuntu-22.04
+FROM mcr.microsoft.com/vscode/devcontainers/base:${VARIANT}
+
+ENV DEBIAN_FRONTEND=noninteractive
+ENV PDK_ROOT=/home/vscode/ttsetup/pdk
+ENV PDK=sky130A
+
+RUN apt update
+RUN apt install -y iverilog gtkwave python3 python3-pip python3-venv python3-tk python-is-python3 libcairo2 verilator libpng-dev libqhull-dev
+
+# Clone tt-support-tools
+RUN mkdir -p /ttsetup
+RUN git clone -b ttsky25a https://github.com/TinyTapeout/tt-support-tools /ttsetup/tt-support-tools
+
+COPY test/requirements.txt /ttsetup/test_requirements.txt
+COPY .devcontainer/copy_tt_support_tools.sh /ttsetup
+
+RUN pip3 install -r /ttsetup/test_requirements.txt -r /ttsetup/tt-support-tools/requirements.txt
+
+# Install verible (for formatting)
+RUN umask 022 && \
+    curl -L https://github.com/chipsalliance/verible/releases/download/v0.0-3795-gf4d72375/verible-v0.0-3795-gf4d72375-linux-static-x86_64.tar.gz | \
+    tar zxf - -C /usr/local --strip-components=1 && \
+    chmod 755 /usr/local/bin
+
+# Install openlane
+RUN pip3 install openlane==2.2.9

WilliamZhang20_ECE298A-TPU/source/.devcontainer/copy_tt_support_tools.sh

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+#! /bin/sh
+
+if [ ! -L tt ]; then
+    cp -R /ttsetup/tt-support-tools tt
+    cd tt && git pull && cd ..
+fi

WilliamZhang20_ECE298A-TPU/source/.devcontainer/devcontainer.json

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+// For format details, see https://aka.ms/devcontainer.json. For config options, see the README at:
+// https://github.com/microsoft/vscode-dev-containers/tree/v0.183.0/containers/ubuntu
+{
+  "name": "Tiny Tapeout Dev Container",
+  "build": {
+    "dockerfile": "Dockerfile",
+    "context": ".."
+  },
+  "runArgs": [
+    "--memory=10GB"
+  ],
+  "customizations": {
+    "vscode": {
+      "settings": {
+        "terminal.integrated.defaultProfile.linux": "bash"
+      },
+      "extensions": ["mshr-h.veriloghdl", "surfer-project.surfer"]
+    }
+  },
+  "features": {
+    "ghcr.io/devcontainers/features/docker-in-docker:2": {
+      "moby": true,
+      "azureDnsAutoDetection": true,
+      "version": "latest",
+      "dockerDashComposeVersion": "none"
+    }
+  },
+  "postStartCommand": "/ttsetup/copy_tt_support_tools.sh"
+}

WilliamZhang20_ECE298A-TPU/source/.gitignore

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+.DS_Store
+.idea
+*.vcd
+runs
+tt_submission
+src/user_config.json
+src/config_merged.json
+test/sim_build
+test/*/__pycache__/
+test/__pycache__/
+test/results.xml
+test/gate_level_netlist.v
+test/tpu/data
+test/data

WilliamZhang20_ECE298A-TPU/source/.vscode/extensions.json

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+{
+  "recommendations": [
+    "mshr-h.veriloghdl",
+    "surfer-project.surfer"
+  ]
+}

WilliamZhang20_ECE298A-TPU/source/.vscode/settings.json

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+{
+  "verilog.linting.linter": "verilator",
+  "verilog.formatting.verilogHDL.formatter": "verible-verilog-format"
+}

WilliamZhang20_ECE298A-TPU/source/LICENSE

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WilliamZhang20_ECE298A-TPU/source/README.md

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+![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg)
+
+# Tiny Tapeout Tensor Processing Unit
+
+- [Read the documentation for project](docs/info.md)
+- To see an architectural redesign, please visit [this](https://github.com/WilliamZhang20/TPUv2) repository.
+
+## Overview
+
+This project implements a small-scale, hardware-efficient Tensor Processing Unit (TPU) that performs 2×2 matrix multiplications using a systolic array of Multiply-Accumulate (MAC) units. It is designed in Verilog and deployable via the Tiny Tapeout ASIC flow.
+
+Hardware design files are in the `./src` folder, while the ML inference setup is inside `./test/tpu`.
+
+## Hardware Features
+
+- **Systolic Array:** A 2×2 grid of MAC units propagates data left-to-right and top-to-bottom, emulating a systolic matrix multiplication engine.
+- **Signed 8-bit Inputs, 16-bit Outputs:** Handles signed integers (-128 to 127) and accumulates products in 16-bit precision.
+- **Streaming Input/Output:** Supports pipelined loading and output to achieve >99.8M operations/sec.
+- **Control FSM:** Automates input loading, matrix multiplication timing, and result collection.
+- **Optional Features:** On-chip fused matrix transpose (`Bᵀ`) and ReLU activation.
+
+## Machine Learning Ecosystem
+
+- **Accurate Low-Precision Training**: since the chip only runs on 8-bit arithmetic but training needs higher precision, I run Quantization-Aware Training, simulating the quantization noise from 32-bit float to 8-bit integer during the training process. This allows minimal accuracy loss during inference.
+  - The process is made easier with TorchAO inserting quantization stubs automatically, and ExecuTorch handling fast quantization into INT8 XNNPack operators and low-precision training.
+- **Simplified Model Deployment**: rather than run inference by calling the chip's `matmul` kernel manually while training in a separate `torch.nn` module, a PyTorch compiler backend unifies the process in `torch.nn`. One can train the model using the module, call `torch.compile` with a custom backend, and run inference with `model(input)`. 
+
+---
+
+## System Architecture
+
+Notice in the diagram that data flows from the input through the blue, yellow, red, purple, and green arrows to go from two input matrices to an output matrix.
+
+![Block Diagram](docs/ECE298A-TPU.png)
+
+**Subsystems:**
+- **Processing Element (PE):** Executes MAC operations and propagates intermediate values.
+- **Systolic Array (MMU):** A mesh of 4 PEs wired in systolic fashion.
+- **Unified Memory:** 8-byte register bank storing both input and weight matrices.
+- **Control Unit:** Finite-state machine (FSM) handles sequencing and pipelined computation.
+- **MMU Feeder:** Schedules data flow between memory, computation, and output.
+
+## Pin Configuration
+
+### Dedicated Input Pins ui_in[7:0]
+
+Is the primary port for inputting matrices used as operands in the product.
+
+### Dedicated Output Pins uo_out[7:0]
+
+8-bit half-sections of signed 16-bit elements of the 2x2 output matrix.
+
+### Bidirectional GPIO Pins
+
+- Index 0 - enabling the loading of elements at dedicated inputs into memory for computation
+- Index 1 - enabling fused transpose of second operand in the product.
+- Index 2 - enabling the application of Rectified Linear Unit (ReLU) activation at the output
+
+### Control Signals
+- Reset rst_n: Active low reset
+- Clock clk: System timing (50 MHz)
+
+## Operation
+1. Initial Load: loading two 2x2 matrices (8 cycles)
+2. Continuous streaming: while taking output of the matrices input in 1, the chip allows overlapped input of the next matrices
+
+## How to test
+
+See the test directory README for detailed instructions on running pre-silicon tests.
+
+### Available test targets
+
+```bash
+cd test
+
+# Run individual module tests
+make test-top     # complete system
+make test-memory  # memory unit
+make test-systolic-array  # systolic array integrity
+make test-control-unit  # control unit
+make test-mmu-feeder  # matrix unit feeder
+make test-nn # test neural network inference through the chip!!!
+
+# Run all tests
+make
+```

WilliamZhang20_ECE298A-TPU/source/docs/info.md

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+<!---
+
+This file is used to generate your project datasheet. Please fill in the information below and delete any unused
+sections.
+
+You can also include images in this folder and reference them in the markdown. Each image must be less than
+512 kb in size, and the combined size of all images must be less than 1 MB.
+-->
+
+## How it works
+
+This project is a small-scale matrix multiplier inspired by the Tensor Processing Unit (TPU), an AI inference accelerator ASIC developed by Google.
+
+It multiplies two 2x2 matrices with signed 8-bit (1 byte) elements to an output matrix with signed 16-bit (2-byte) elements. It does so in a systolic array circuit, where flow of data is facilitated through the connections between a grid of 4 Multiply-Add-Accumulate (MAC) Processing Elements (PEs).
+
+To store inputs prior to computation, it contains 2 matrices in memory registers, which occupy a total of 8 bytes.
+
+To orchestrate the flow of data between inputs, memory, and outputs, a control unit coordinates state transitions, loads, and stores automatically.
+
+Finally, a feeder module interfaces with the matrix multiplier to schedule the inputs and outputs to and from the systolic array.
+
+It is capable of running over 99.8 Million Operations Per Second when using a maximum throughput streamed processing pattern to multiply big matrices in 2x2 blocks.
+
+## System Architecture
+
+![Alt text](ECE298A-TPU.png)
+
+### The Processing Element
+
+Let's start from the most atomic element of the matrix multiplier unit (MMU): its processing element (PE). The value stored within each PE contributes an element to the output.
+
+|Signal Name        | Direction     |Width    | Description       |
+|-------------------|---------------|---------|-------------------|
+|clk                | input         |1        | The clock!        |
+|rst                | input         |1        | Reset             |
+|clear              | input         |1        | Clear PE          |
+|a_in               | input         |8        | Input value       |
+|a_out              | output        |8        | Pass-on of input  |
+|b_in               | input         |8        | Weight value      |
+|b_out              | output        |8        | Pass-on of weight |
+|c_out              | output        |16       | Accumulation      |
+
+Since each output element of a matrix multiplication is a sum of products, the PE's primary operation is a multiply-add-accumulate.
+
+It will take input terms `a_in` and `b_in`, multiply them, and then add them to the accumulator value `c_out`. Due to the larger values induced by multiplication, the accumulator holds more bits.
+
+Since adjacent PEs corresponding to adjacent elements of the output matrix need the same input and weight values, these input terms are sent to `a_out` and `b_out` respectively, which are connected to other PEs by the systolic array.
+
+Once the multiplication is done, the control unit will want to clear the PEs so that they can reset the accumulation for the next matrix product, which is facilitated via the automatic `clear` signal. 
+
+On the other hand, it is non-ideal to reset the entire chip, as it wastes time (an entire clock cycle) and is unnecessary to reset other elements such as memory.
+
+The output is 16 bits for the 8-bit inputs, to account for the property of multiplication.
+
+### The Systolic Array
+
+|Signal Name        | Direction     |Width    | Description                     |
+|-------------------|---------------|---------|---------------------------------|
+|clk                | input         |1        | The clock!                      |
+|rst                | input         |1        | Reset                           |
+|clear              | input         |1        | Forwarded to PEs                |
+|activation         | input         |1        | Enables ReLU                    |
+|a_data0            | input         |8        | Input value of top-left PE      |
+|a_data1            | input         |8        | Input value of bottom-left PE   |
+|b_data0            | input         |8        | Input value of top-left PE      |
+|b_data1            | input         |8        | Input value of top-right PE     |
+|c00                | output        |16       | Top-left output value           |
+|c01                | output        |16       | Top-right output value          |
+|c10                | output        |16       | Bottom-left output value        |
+|c11                | output        |16       | Bottom-right output value       |
+
+The systolic array is a network, or grid, of PEs. In this 2x2 multiplier, the result is a 4-element square matrix, so there are 4 PEs.
+
+Internally, the systolic array maintains internal registers and a matrix of accumulators that are read by and written into by the PEs.
+
+This includes a 2x3 matrix for the input matrix values, a 3x2 matrix for the weight matrix values, and a 2x2 for the final output.
+
+The extra values beyond 2x2 for input & weight matrix values are to allow the PEs at the edge of the grid to send their input/weight values to a register to a "garbage".
+
+At each clock cycle, elements will flow between the PEs. The inputs will flow from "left to right", and the weights will flow from "top to bottom". To add new values, inputs have to be provided to the ports at the "left", and weights have to be provided to the ports at the "top".
+
+Then, the PEs are instantiated using the Verilog compile-time construct of `genvar`, in which signals of the PE are connected to specified indices of the internal systolic array signals. Makes the code clean and easy to write!
+
+Diagram of PE arrangement below:
+
+![Alt text](systolic_array_diagram.png)
+
+### Unified Memory
+
+The unified memory module (`memory.v`) is an on-chip store that holds both weight and input matrices for quick access to both values during computations.
+
+|Signal Name        | Direction | Width | Description                           |
+|-------------------|-----------|-------|---------------------------------------|
+|clk                | input     | 1     | System clock                          |
+|rst                | input     | 1     | Active-high reset                     |
+|load_en            | input     | 1     | Enable signal for matrix loading      |
+|addr               | input     | 3     | Memory address for matrix elements    |
+|in_data            | input     | 8     | Current input matrix                  |
+|weight[0,1,2,3]    | output    | 8     | Weight matrix elements                |
+|input[0,1,2,3]     | output    | 8     | Input matrix elements                 |
+
+The only source of the memory will come from `ui_in` ports directly. When `load_en` goes high, the current element (`in_data`) connected to all bits at the dedicated input `ui_in` is loaded into memory at its specified byte address, on the next rising edge. 
+
+Matrix elements are held internally within an 8x8 register (`sram`). In terms of outputs, `sram[0..3]` maps to `weight[0..3]`, `sram[4..7]` maps to `input[0..3]`. An address (`addr`) is generated by the control unit to correctly load elements into the internal register.
+
+The entire memory space of 8 bytes is visible at the output ports asynchronously.
+
+### Control Unit
+
+The control unit (`control_unit.v`) serves as the central orchestrator for the entire TPU, coordinating the flow of data between memory, the systolic array, and output collection through a carefully designed finite state machine (FSM).
+
+|Signal Name        | Direction | Width | Description                           |
+|-------------------|-----------|-------|---------------------------------------|
+|clk                | input     | 1     | System clock                          |
+|rst                | input     | 1     | Active-high reset                     |
+|load_en            | input     | 1     | Enable signal for matrix loading      |
+|mem_addr           | output    | 3     | Memory address for matrix elements    |
+|mmu_en             | output    | 1     | Enable signal for MMU operations      |
+|mmu_cycle          | output    | 3     | Current cycle count for MMU timing    |
+
+#### State Machine Architecture
+
+The control unit implements a 3-state FSM that manages the complete matrix multiplication pipeline:
+
+1. **S_IDLE (2'b00)**: The default waiting state where the system remains until a matrix multiplication operation is requested via the `load_en` signal.
+
+2. **S_LOAD_MATS (2'b01)**: The matrix loading phase when 8 matrix elements (4 for each 2x2 matrix) are sequentially loaded into memory. Because the order is already assumed to be row-major order, left matrix first, then the address value tracked in `mem_addr` will only increment when `load_en` is asserted, from 0 up until 7 when it resets to get ready for future input matrices.
+
+3. **S_MMU_FEED_COMPUTE_WB (2'b10)**: The computation and output phase, taking 8 cycles total when the systolic array performs the last few operations of matrix multiplication, and makes the 4 outputs available in 16 bits each, 1 every 2 cycles. At the same time, the chip is available for streamed processing so that 8 new elements, representing 2 new 2x2 matrices, can be input for the next round of outputs occurring right after the current round. 
+
+#### Orchestration Logic
+
+The control unit coordinates several critical functions:
+
+- **Memory Interface Management**: Through the `mem_addr` output (`control_unit.v:9`), it generates sequential memory addresses (0-7) during the loading and streaming phase, ensuring matrix elements are stored in the correct memory locations for later retrieval.
+
+- **MMU Timing Control**: The `mmu_cycle` signal (`control_unit.v:13`) provides precise timing information to the MMU feeder module, enabling it to:
+- Feed correct matrix elements to the systolic array at appropriate cycles
+- Determine when computation results are ready for output
+- Clear processing elements after computation completion
+
+- **Pipeline Coordination**: The `mmu_en` signal (`control_unit.v:12`) acts as the master enable for the entire computation pipeline, transitioning from low during loading to high during computation phases. This is to ensure that elements are only loaded into the systolic array during the first round of set up inputs when all inputs are ready. Otherwise, if the chip is not initialized with all inputs in memory, it cannot complete computation and hence should not start it. 
+    - However, for maximum throughput, the `mmu_en` signal is asserted when 6 of the 8 elements making up 2 matrices are input, so that computation begins when we have the elements to produce enough outputs, and is overlapped with matrix loads, and completes in the middle of the output cycle.
+
+- **Streamed Processing**: During the 8-cycle output phase, the chip is available to take in 8 new input bytes provided at the `ui_in` ports. This is a streamlined flow of execution, as the input and output ports will henceforth be constantly used. After this 8-cycle output phase, the input bytes input during that phase can now begin outputting, while subsequent inputs can be further written.
+
+    - However, if the user chooses not to write new inputs during the output phase, the outputs continue unabated, and the systolic array matrix accumulators automatically reset once the outputs are complete.
+
+#### Critical Timing Relationships
+
+The control unit implements sophisticated timing logic based on the systolic array's computational pipeline:
+
+- **Cycle 0**: Initial data feeding begins (a00×b00 starts)
+- **Cycle 1**: First partial products computed, additional data fed
+- **Cycle 2**: First result (c00) becomes available, Next input group can begin.
+    - Future value of A00 expected at input during streamed processing
+- **Cycle 3**: Second and third results (c01, c10) become available simultaneously
+    - Future value of A01 expected at input
+- **Cycle 4**: Final result (c11) becomes available
+    - Future value of A10 expected at input
+- **Cycle 5**: All outputs remain stable.
+    - Future value of A11 expected at input
+- **Cycle 6**: Output continues
+    - Future value of B00 expected at input
+- **Cycle 7**: Output continues
+    - Future value of B01 expected at input
+- **Back to Cycle 0**: Output continues. Since 6 of 8 of the next input elements would be on chip, the next cycle of data feeding begins
+    - Future value of B10 expected at input
+- **Cycle 1 again**: Last output element, first partial products of next output are computed.
+    - Future value of B11 expected at input
+- **Cycle 2 again**: Repeat of description above, etc.
+
+#### State Transition Logic
+
+State transitions are triggered by specific conditions:
+- `S_IDLE → S_LOAD_MATS`: When `load_en` is asserted (`control_unit.v:30-32`)
+- `S_LOAD_MATS → S_MMU_FEED_COMPUTE_WB`: When all 8 elements are loaded (`mem_addr == 3'b111`) (`control_unit.v:37-38`)
+- `S_LOAD_MATS → S_MMU_FEED_COMPUTE_WB`: When all 8 elements are loaded (`mat_elems_loaded == 3'b111`) (`control_unit.v:37-38`)
+- Afterwards, the state machine stays in `S_MMU_FEED_COMPUTE_WB`, but essentially cycles through counts of `mem_addr` and `mmu_cycle` to keep track of the memory address writing for streamed processing and maintain a rhythm for the Matrix Unit Feeder.
+
+#### Integration with Other Modules
+
+The control unit interfaces with all major TPU components:
+- **Memory Module**: Provides addressing (`mem_addr`) and coordinates write operations during loading
+- **MMU Feeder**: Supplies enable signal (`mmu_en`) and cycle timing (`mmu_cycle`) for data routing and output selection
+- **Top-level TPU**: Receives external `load_en` control signal and coordinates the entire operation sequence
+
+This design ensures that matrix multiplication operations proceed automatically once initiated, with the control unit handling all timing dependencies and data flow coordination between the TPU's constituent modules.
+
+### The Matrix Unit Feeder
+
+The Matrix Unit Feeder (in `mmu_feeder.v`) is the interface between the control unit and the computational unit (MMU), facilitating smooth data flow between the internal components of the TPU and outputs to the host. When enabled, its role is to either feed the expected matrix data from host to MMU, or to direct computed matrix outputs from MMU to host; this is decided based on the mmu_cycle defined and cycled through (0-7 repeating constantly) by the control unit.
+
+|Signal Name        | Direction | Width | Description                           |
+|-------------------|-----------|-------|---------------------------------------|
+|clk                | input     | 1     | System clock                          |
+|rst                | input     | 1     | Active-high reset                     |
+|en                 | input     | 1     | Enable signal for MMU operations      |
+|mmu_cycle          | input     | 3     | Current cycle count for timing        |
+|weight[0,1,2,3]    | input     | 8     | Weight matrix from memory             |
+|input[0,1,2,3]     | input     | 8     | Input matrix from memory              |
+|c[00,01,10,11]     | input     | 8     | Computed element output from MMU      |
+|done               | output    | 1     | Signal to host that output is ready   |
+|host_outdata       | output    | 8     | Data register to output to host       |
+|a_data[0,1]        | output    | 8     | Output A to MMU for computation       |
+|b_data[0,1]        | output    | 8     | Output B to MMU for computation       |
+
+The weight and input matrices are taken from memory. The feeder will set the expected values of a_data0/1 and b_data0/1 depending on the value of mmu_cycle. Output values are 16 bits, but the maximum data width of the output ports is 8-bit so we have to feed half an element a cycle!
+- **Cycle 0**:
+    - Blank data is sent to the output port. a_data0 = weight[0], b_data0 = input[0], done = 0
+- **Cycle 1**: 
+    - During the initial cycle when the memory is first populated, cycle 1 occurs during the input of the second matrix, which also overlaps with compute as the counter has already incremented.
+    - This module will send a value to its output that is equal to the lower 8 bits of the product of the A00 and B00, which are the top-left elements of the matrices. This is due to the settings that enable streamed processing. The chip should therefore ignore that output.
+    - In terms of feeding the systolic array, if fused transpose is disabled, then a_data0 = weight[1], a_data1 = weight[2], b_data0 = input[2], b_data1 = input[1].
+    - If fused transpose is enabled, the b_data0 and b_data1 values are swapped.
+- **Cycle 2**:
+    - In this cycle, the output counter is 0. The output sends the upper 8 bits of C00, the top-left output element.
+    - To signal that the outputs are coming, the done signal is asserted, which is visible from the user.
+    - The values given to the systolic array are a_data1 = weight[3], b_data1 = input[3].
+- **Cycle 3**: 
+    - In this cycle, the output counter is 1. The output sends the lower 8 bits of C00, the top-left output element.
+    - Since we have finished sending all the last input values to the systolic array, intermediate feeds will have a value of 0, having no effect on the operation of MAC units.
+- **Cycle 4**: 
+    - In this cycle, the output counter is 2. The output sends the upper 8 bits of C01, the top-right output element.
+- **Cycle 5**: 
+    - In this cycle, the output counter is 3. The output sends the lower 8 bits of C01, the top-right output element.
+- **Cycle 6**: 
+    - In this cycle, the output counter is 4. The output sends the upper 8 bits of C10, the bottom-left output element.
+- **Cycle 7**: 
+    - In this cycle, the output counter is 5. The output sends the lower 8 bits of C10, the bottom-left output element.
+- **Back to Cycle 0**: (set by control unit) 
+    - In this cycle, the output counter is 6. The output sends the upper 8 bits of C11, the bottom-right output element.
+    - The clear signal is asserted to make way for the computation of the next input to accumulate from 0.
+    - Therefore, to preserve the lower 8 bits of C11 output in the next cycle, we assign the value to a "pipeline register", aptly named `tail_hold` as it holds the tail of the output.
+    - The systolic array feeding pattern is the exact same as was shown above.
+- **Cycle 1 Again**:
+    - In this cycle, the output counter is 7. The output sends the lower 8 bits of C11, the bottom-right output element.
+    - The output count resets to 0 automatically.
+
+For similar details on timing relationships, see **Critical Timing Relationships** above, in the Control Unit section.
+
+## How to test
+
+Notation: the matrix element A_xy denotes a value in the xth row and yth column of the matrix A.
+
+The module will assume an order of input of A matrix values and B matrix values, and outputs. That is, it is expected that inputs come in order of A00, A01, A10, A11, B00, B01, B10, B11, and the outputs will come in the order of C00, C01, C10, C11. This keeps the chip simple and avoids extra logic/user input.
+
+### Setup
+
+1. Power Supply: Connect the chip to a stable power supply as per the voltage specifications.
+2. Clock Signal: Provide a stable clock signal to the clk pin.
+3. Reset: Ensure the rst_n pin is properly connected to allow resetting the chip.
+
+### A Matrix Multiplication Round
+
+1. Initial Reset
+    - Perform a reset by pulling the `rst_n` pin low to 0, and waiting for a single clock signal before pulling it back high to 1. This sets initial state values.
+2. Initial Matrix Load
+    - Load 8 matrix elements into the chip, one per cycle. For example, if your matrices are [[1, 2], [3, 4]], [[5, 6], [7, 8]], you would load in the row-major-first-matrix-first order of 1, 2, 3, 4, 5, 6, 7, 8. This occurs by setting the 8 `ui_in` pins to the 8-bit value of the set matrix element, and waiting one clock cycle before the next can be loaded.
+3. Collect Output & Send Next Inputs
+    - Thanks to the aggressive pipelining implemented in the chip, once the matrices are loaded, you can already start collecting output!
+    - Output elements will be 16 bits each, but since the output port is only 8 bits, one element is output in 2 cycles, with the upper half (bits 15 - 8) in the first cycle, and the lower half (bits 7 - 0) in the second cycle.
+    - To collect outputs, wait for a single clock edge, and then read the `uo_out` pin for the 8-bit value. Repeat again to get the full 16-bit value. Overall, the matrix output at `uo_out` will be in the order of c_00, c_01, c_10, c_11, taking 8 cycles to output 4 elements.
+    - For the above example, the output would be in the order of [19, 22, 43, 50], starting from the cycle right after you finish your last load, and ending 8 cycles afterwards.
+    - It is also recommended that in those same 8 cycles, the next 2 input matrices are sent to the `ui_in` pin. That will be 1 element per cycle for 2 serial, row-major 2x2 matrix inputs, for 8 cycles total.
+4. Repeat
+5. Input Options
+    - Note that if new matrices are not input during the output cycle, i.e. the `ui_in` pin is set to 0, then it is the equivalent of     "flushing the pipeline", as once the output is complete, it is the equivalent of starting at step 2.
+
+
+Below is a visual of an example matrix multiplication round through the systolic array. Note that while it behaves similarly to the chip, the chip's matrix inputs to the systolic array are the diagram's order inverted across the matrix diagonal.
+
+![Alt text](Matrix-Multiplication-Round-Systolic.png)
+
+### Matrix Multiplication Options
+
+The example shown above is a very simple and plain 2x2 matrix multiplication. However, this TPU chip offers additional options. 
+
+The first is the ability to compute the product $AB^T$, which is the first matrix multiplied by the transpose of the second. This saves time computing a transpose taken by a CPU instruction in $O(n^2)$ time, where n is a rough measure of the matrix dimension. Instead, it is fused with the entire process, taking no extra time.
+
+The second is the ability to run the Rectified Linear Unit (ReLU) activation function, commonly seen in neural networks for approximating non-linear patterns in data. 
+
+The third, which is provided as a software interface option, is the ability to multiply bigger matrices, of all compatible dimensions, in 2x2 blocks.
+
+### Example Result
+
+Below is a timing diagram showing signal progression for a streamed processing pattern of the TPU chip, generated by GTKWave:
+
+![Alt text](TPU-GTKWave.png)
+
+The part highlighting Input/Output streaming is the fact that `mem_addr`, which increments whenever load is enabled, keeps incrementing like 0-7, 0-7, etc, and so is the output count, albeit slightly offset in time.
+
+One can also observe the pattern in which elements are fed into the systolic array, as seen by `a_data0`, `a_data1`, `b_data0`, `b_data1` signals, and the output "waterfall" flow of output appearances seen inside `c00`, `c01`, `c10`, `c11`. 
+
+### Scaling it up
+
+Earlier, it was mentioned that you could scale the multiplication up to any dimension. What else does this mean? AI inference! We are able to run forward inference of a Quantization-Aware-Trained (QAT) machine learning model using the chip's logic. 
+
+The model is trained to recognize black-and-white images of single handwritten digits from the MNIST dataset.
+
+In the demonstration, which is kept simple, I run QAT on the local PC, and then run forward inference with this model on the chip. It was able to successfully recognize 2 out of 3 images in a test batch, which is far superior to a coin flip.
+
+## External hardware
+
+An external microcontroller will send signals over the chip interface, including the clock signal, which will allow it to coordinate I/O on clock edges.
+
+## Acknowledgements
+
+* William Zhang: Processing Elements, Systolic Array, Module Compilation & Integration, Pipelining Optimization
+* Ethan Leung: Matrix Unit Feeder
+* Guhan Iyer: Unified Memory
+* Yash Karthik: Control Unit
+* ECE 298A Course Staff: Prof. John Long, Prof. Vincent Gaudet, Refik Yalcin
+
+An earlier iteration of this project is located at [this](https://github.com/YashKarthik/tpu) repository, in which the original plan was to submit to the IHP25B shuttle.

WilliamZhang20_ECE298A-TPU/source/info.yaml

@@ -0,0 +1,62 @@
+# Tiny Tapeout project information
+project:
+  title:        "Tiny Tapeout Tensor Processing Unit"      # Project title
+  author:       "William Zhang, Yash Karthik, Guhan Iyer, Ethan Leung"      # Your name
+  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "multiplies matrices"      # One line description of what your project does
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     50000000       # Clock frequency in Hz (or 0 if not applicable)
+
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_tpu"
+
+  # List your project's source files here.
+  # Source files must be in ./src and you must list each source file separately, one per line.
+  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
+  source_files:
+    - "tpu.v"
+    - "systolic_array_2x2.v"
+    - "PE.v"
+    - "memory.v"
+    - "control_unit.v"
+    - "mmu_feeder.v"
+    - "delay_cell.v"
+
+# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
+# This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).
+pinout:
+  # Inputs
+  ui[0]: "IN0"
+  ui[1]: "IN1"
+  ui[2]: "IN2"
+  ui[3]: "IN3"
+  ui[4]: "IN4"
+  ui[5]: "IN5"
+  ui[6]: "IN6"
+  ui[7]: "IN7"
+
+  # Outputs
+  uo[0]: "OUT0"
+  uo[1]: "OUT1"
+  uo[2]: "OUT2"
+  uo[3]: "OUT3"
+  uo[4]: "OUT4"
+  uo[5]: "OUT5"
+  uo[6]: "OUT6"
+  uo[7]: "OUT7"
+
+  # Bidirectional pins
+  uio[0]: "LOAD_EN (input)"
+  uio[1]: "TRANSPOSE (input)"
+  uio[2]: "ACTIVATION (input)"
+  uio[3]: "Unused"
+  uio[4]: "Unused"
+  uio[5]: "Unused"
+  uio[6]: "Unused"
+  uio[7]: "DONE (output)"
+
+# Do not change!
+yaml_version: 6

WilliamZhang20_ECE298A-TPU/source/src/PE.v

@@ -0,0 +1,30 @@
+module PE #(
+    parameter WIDTH = 8
+)(
+    input wire clk,
+    input wire rst,
+    input wire clear,
+    input wire signed [WIDTH-1:0] a_in,
+    input wire signed [WIDTH-1:0] b_in,
+
+    output reg signed [WIDTH-1:0] a_out,
+    output reg signed [WIDTH-1:0] b_out,
+
+    output reg signed [WIDTH*2-1:0] c_out
+);
+
+    always @(posedge clk) begin
+        a_out <= a_in;
+        b_out <= b_in;
+        if (rst) begin
+            c_out <= 0;
+            a_out <= 0;
+            b_out <= 0;
+        end else if (clear) begin
+            c_out <= a_in * b_in;
+        end else begin
+            c_out <= c_out + (a_in * b_in);
+        end
+    end
+
+endmodule

WilliamZhang20_ECE298A-TPU/source/src/config.json

@@ -0,0 +1,86 @@
+{
+  "//": "DO NOT EDIT THIS FILE before reading the comments below:",
+
+  "//": "This is the default configuration for Tiny Tapeout projects. It should fit most designs.",
+  "//": "If you change it, please make sure you understand what you are doing. We are not responsible",
+  "//": "if your project fails because of a bad configuration.",
+
+  "//": "!!! DO NOT EDIT THIS FILE unless you know what you are doing !!!",
+
+  "//": "If you get stuck with this config, please open an issue or get in touch via the discord.",
+
+  "//": "Here are some of the variables you may want to change:",
+
+  "//": "PL_TARGET_DENSITY_PCT - You can increase this if Global Placement fails with error GPL-0302.",
+  "//": "Users have reported that values up to 80 worked well for them.",
+  "PL_TARGET_DENSITY_PCT": 80,
+
+  "//": "CLOCK_PERIOD - Increase this in case you are getting setup time violations.",
+  "//": "The value is in nanoseconds, so 20ns == 50MHz.",
+  "CLOCK_PERIOD": 20,
+
+  "//": "Hold slack margin - Increase them in case you are getting hold violations.",
+  "PL_RESIZER_HOLD_SLACK_MARGIN": 0.2,
+  "GRT_RESIZER_HOLD_SLACK_MARGIN": 0.1,
+
+  "//": "Enable core optimization (buffering/sizing) during placement and routing.",
+  "PL_RESIZER_DESIGN_OPTIMIZATIONS": 1,
+  "GRT_RESIZER_DESIGN_OPTIMIZATIONS": 1,
+
+  "//": "Increase setup margin to encourage Resizer to be more aggressive with upsizing/buffering.",
+  "PL_RESIZER_SETUP_SLACK_MARGIN": 0.5,
+
+  "//": "Enable antenna diode insertion for fixing antenna ratio violations",
+  "DIODE_INSERTION_STRATEGY": 4,
+  "ANTENNA_DIODE_CELL": "sky130_fd_sc_hd__diode_2",
+
+  "//": "RUN_LINTER, LINTER_INCLUDE_PDK_MODELS - Disabling the linter is not recommended!",
+  "RUN_LINTER": 1,
+  "LINTER_INCLUDE_PDK_MODELS": 1,
+
+  "//": "If you need a custom clock configuration, read the following documentation first:",
+  "//": "https://tinytapeout.com/faq/#how-can-i-map-an-additional-external-clock-to-one-of-the-gpios",
+  "CLOCK_PORT": "clk",
+
+  "//": "Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html",
+
+  "//": "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!",
+  "//": "!!! DO NOT CHANGE ANYTHING BELOW THIS POINT !!!",
+  "//": "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!",
+
+  "//": "Save some time",
+  "RUN_KLAYOUT_XOR": 0,
+  "RUN_KLAYOUT_DRC": 0,
+
+  "//": "Don't put clock buffers on the outputs",
+  "DESIGN_REPAIR_BUFFER_OUTPUT_PORTS": 0,
+
+  "//": "Reduce wasted space",
+  "TOP_MARGIN_MULT": 1,
+  "BOTTOM_MARGIN_MULT": 1,
+  "LEFT_MARGIN_MULT": 6,
+  "RIGHT_MARGIN_MULT": 6,
+
+  "//": "Absolute die size",
+  "FP_SIZING": "absolute",
+
+  "GRT_ALLOW_CONGESTION": 1,
+
+  "FP_IO_HLENGTH": 2,
+  "FP_IO_VLENGTH": 2,
+
+  "FP_PDN_VPITCH": 38.87,
+
+  "//": "Clock",
+  "RUN_CTS": 1,
+
+  "//": "Don't use power rings or met5 layer",
+  "FP_PDN_MULTILAYER": 0,
+  "RT_MAX_LAYER": "met4",
+
+  "//": "MAGIC_DEF_LABELS may cause issues with LVS",
+  "MAGIC_DEF_LABELS": 0,
+
+  "//": "Only export pin area in LEF (without any connected nets)",
+  "MAGIC_WRITE_LEF_PINONLY": 1
+}

WilliamZhang20_ECE298A-TPU/source/src/control_unit.v

@@ -0,0 +1,129 @@
+`default_nettype none
+
+module control_unit (
+    input wire clk,
+    input wire rst,
+    input wire load_en,
+
+    // Memory interface  
+    output reg [2:0] mem_addr,
+
+    // MMU feeding control
+    output reg mmu_en,
+    output reg [2:0] mmu_cycle,
+
+    // For debugging
+    output wire [1:0] state_out
+);
+
+    // STATES
+    localparam [1:0] S_IDLE                  = 2'b00;
+    localparam [1:0] S_LOAD_MATS             = 2'b01;
+    localparam [1:0] S_MMU_FEED_COMPUTE_WB   = 2'b10;
+
+    reg [1:0] state, next_state;
+
+    assign state_out = state;
+
+    // Next state logic
+    always @(*) begin
+        next_state = state;
+
+        case (state)
+            S_IDLE: begin
+                if (load_en) begin
+                    next_state = S_LOAD_MATS;
+                end
+            end
+            
+            S_LOAD_MATS: begin
+                // All 8 elements loaded (4 for each matrix)
+                if (mem_addr == 3'b111) begin 
+                    next_state = S_MMU_FEED_COMPUTE_WB;
+                end
+            end
+            
+            S_MMU_FEED_COMPUTE_WB:
+                next_state = S_MMU_FEED_COMPUTE_WB;
+               /* MMU CYCLE PATTERN
+                * Cycle 0: Start feeding data (a00×b00 starts)
+                * Cycle 1: First partial products computed, more data fed
+                * Cycle 2: c00 ready (a00×b00 + a01×b10), is output, while take in next a00
+                * Cycle 3: c01 and c10 ready simultaneously, read next a01:
+                *          c01 = a00×b01 + a01×b11
+                *          c10 = a10×b00 + a11×b10
+                * Cycle 4: c11 ready (a10×b01 + a11×b11), read next a10
+                * Cycle 5: All outputs remain valid, read next a11
+                * Cycle 6: Keep outputting, read next b00
+                * Cycle 7: Keep outputting, read next b01
+                * Back to cycle 0: Start feeding data (a00×b00 starts), keep outputting, read next b10
+                * Cycle 1: First partial products computed, keep outputting, read next b01
+                * Cycle 2: c00 ready, begin output, take in next a00, pattern continues...
+                */
+
+			default: begin
+				next_state = S_IDLE;
+			end
+        endcase
+    end
+
+    // State Machine
+    always @(posedge clk) begin
+        if (rst) begin
+            state <= S_IDLE;
+            mmu_cycle <= 0;
+            mmu_en <= 0;
+            mem_addr <= 0;
+        end else begin
+            state <= next_state;
+            mem_addr <= 0;
+            case (state)
+                S_IDLE: begin
+                    mmu_cycle <= 0;
+                    mmu_en <= 0;
+                    if (load_en) begin
+                        mem_addr <= mem_addr + 1;
+                    end
+                end
+
+                S_LOAD_MATS: begin
+                    if (load_en) begin
+                        mem_addr <= mem_addr + 1;
+                    end
+
+                    if (mem_addr == 3'b101) begin
+                        mmu_en <= 1;
+                    end else if (mem_addr >= 3'b110) begin
+                        mmu_en <= 1;
+                        mmu_cycle <= mmu_cycle + 1;
+                        if (mem_addr == 3'b111) begin 
+                            mem_addr <= 0;
+                        end
+                    end
+                end
+
+                S_MMU_FEED_COMPUTE_WB: begin
+                    // Now: the TPU will be forever stuck in this cycle...
+                    // Cycles through counter of 8...
+                    // In each cycle of 8 counts, it will: output 4 16-bit output elements the result of the previous matmul,
+                    // and take in 8 new 8-bit elements
+                    if (load_en) begin
+                        mem_addr <= mem_addr + 1;
+                    end
+					mmu_cycle <= mmu_cycle + 1; // allow mmu_cycle to continue incrementing, permitting a pipeline flush
+                    if (mmu_cycle == 3'b111) begin
+                        mmu_cycle <= 0;
+                    end else if (mmu_cycle == 1) begin
+                        mem_addr <= 0;
+                    end
+                end
+				
+				default: begin
+                    mmu_cycle <= 0;
+                    mmu_en <= 0;
+				end
+            endcase
+        end
+    end
+
+endmodule

WilliamZhang20_ECE298A-TPU/source/src/delay_cell.v

@@ -0,0 +1,15 @@
+module buffer (
+    output wire X   ,
+    input  wire A   ,
+    input  wire VPWR,
+    input  wire VGND,
+    input  wire VPB ,
+    input  wire VNB
+);
+
+    assign X = A;
+
+    wire _unused;
+    assign _unused = &{ 1'b0, VPWR, VGND, VPB, VNB };
+
+endmodule

WilliamZhang20_ECE298A-TPU/source/src/memory.v

@@ -0,0 +1,36 @@
+`default_nettype none
+
+module memory (
+    input wire clk,
+    input wire rst,
+    input wire load_en,
+    input wire [2:0] addr, // MSB selects matrix (0: weights, 1: inputs), [1:0] selects element
+    input wire [7:0] in_data, // Fixed from reg to wire to match tt_um_tpu.v
+    output wire [7:0] weight0, weight1, weight2, weight3, // 2x2 matrix A elements, 1 byte each
+    output wire [7:0] input0, input1, input2, input3 // 2x2 matrix B elements, 1 byte each
+);
+
+    reg [7:0] sram [0:7]; // 8 locations: 0-3 for weights, 4-7 for inputs
+    integer i;
+
+    always @(posedge clk) begin
+        if (rst) begin
+            for (i = 0; i < 8; i = i + 1) begin
+                sram[i] <= 8'b0;
+            end
+        end else if (load_en) begin
+            sram[addr] <= in_data;
+        end
+    end
+
+    // asynchronous read
+    assign weight0 = sram[0];
+    assign weight1 = sram[1];
+    assign weight2 = sram[2];
+    assign weight3 = sram[3];
+    assign input0 = sram[4];
+    assign input1 = sram[5];
+    assign input2 = sram[6];
+    assign input3 = sram[7];
+
+endmodule

WilliamZhang20_ECE298A-TPU/source/src/mmu_feeder.v

@@ -0,0 +1,94 @@
+`default_nettype none
+
+module mmu_feeder (
+    input wire clk,
+    input wire rst,
+    input wire en,
+    input wire [2:0] mmu_cycle,
+
+    input wire transpose,
+
+    /* Memory module interface */
+    input wire [7:0] weight0, weight1, weight2, weight3,
+    input wire [7:0] input0, input1, input2, input3,
+
+    /* systolic array -> feeder */
+    input wire signed [15:0] c00, c01, c10, c11,
+
+    /* feeder -> mmu */
+    output wire clear,
+    output wire [7:0] a_data0,
+    output wire [7:0] a_data1,
+    output wire [7:0] b_data0,
+    output wire [7:0] b_data1,
+
+    /* feeder -> rpi */
+    output wire done,
+    output reg [7:0] host_outdata
+);
+
+    // Done signal for output phase
+    assign done = en && (mmu_cycle >= 3'b010);
+    assign clear = (mmu_cycle == 3'b000);
+
+    // Output counter for selecting c_out
+    reg [2:0] output_count;
+
+    assign a_data0 = en ?
+                     (mmu_cycle == 3'd0) ? weight0 : 
+                     (mmu_cycle == 3'd1) ? weight1 : 0 : 0;
+
+    assign a_data1 = en ?
+                     (mmu_cycle == 3'd1) ? weight2 : 
+                     (mmu_cycle == 3'd2) ? weight3 : 0 : 0;
+
+    assign b_data0 = en ? 
+                     (mmu_cycle == 3'd0) ? input0 : 
+                     (mmu_cycle == 3'd1) ? 
+                     transpose ? input1 : input2 : 0 : 0;
+
+    assign b_data1 = en ?
+                     (mmu_cycle == 3'd1) ? 
+                     transpose ? input2 : input1 :
+                     (mmu_cycle == 3'd2) ? input3 : 0 : 0;
+
+    reg [7:0] tail_hold; // since clear occurs at output of 4th element we want to preserve it... :)
+
+    // Sequential logic for control and data outputs
+    always @(posedge clk) begin
+        if (rst) begin
+            output_count <= 0;
+            tail_hold <= 8'b0;
+        end else begin
+            if (en) begin
+                // Update output_count during output phase
+                if (mmu_cycle == 1) begin
+                    output_count <= 0;
+                end else if (mmu_cycle == 7) begin
+                    tail_hold <= c11[7:0];
+                    output_count <= output_count + 1;
+                end else begin
+                    output_count <= output_count + 1;
+                end
+            end
+        end
+    end
+
+    // Combinational logic for host_outdata with corrected saturation
+    always @(*) begin
+        host_outdata = 8'b0; // Default to avoid latch
+        if (en) begin
+            case (output_count)
+                3'b000: host_outdata = c00[15:8];
+                3'b001: host_outdata = c00[7:0];
+                3'b010: host_outdata = c01[15:8];
+                3'b011: host_outdata = c01[7:0];
+                3'b100: host_outdata = c10[15:8];
+                3'b101: host_outdata = c10[7:0];
+                3'b110: host_outdata = c11[15:8];
+                3'b111: host_outdata = tail_hold;
+            endcase
+        end
+    end
+
+endmodule

WilliamZhang20_ECE298A-TPU/source/src/systolic_array_2x2.v

@@ -0,0 +1,55 @@
+module systolic_array_2x2 #(
+    parameter WIDTH = 8
+)(
+    input wire clk,
+    input wire rst,
+    input wire clear,
+    input wire activation,
+
+    input wire [WIDTH-1:0] a_data0,
+    input wire [WIDTH-1:0] a_data1,
+    input wire [WIDTH-1:0] b_data0,
+    input wire [WIDTH-1:0] b_data1,
+
+    output wire [WIDTH*2-1:0] c00,
+    output wire [WIDTH*2-1:0] c01,
+    output wire [WIDTH*2-1:0] c10,
+    output wire [WIDTH*2-1:0] c11
+);
+
+    // Internal signals between PEs
+    wire [WIDTH-1:0] a_wire [0:1][0:2];
+    wire [WIDTH-1:0] b_wire [0:2][0:1];
+    wire signed [WIDTH*2-1:0] c_array [0:1][0:1];
+
+    // Input loading at top-left
+    assign a_wire[0][0] = a_data0;
+    assign a_wire[1][0] = a_data1;
+    assign b_wire[0][0] = b_data0;
+    assign b_wire[0][1] = b_data1;
+
+    genvar i, j;
+    generate
+        for (i = 0; i < 2; i = i + 1) begin : row
+            for (j = 0; j < 2; j = j + 1) begin : col
+                PE #(.WIDTH(WIDTH)) pe_inst (
+                    .clk(clk),
+                    .rst(rst),
+                    .clear(clear),
+                    .a_in(a_wire[i][j]),
+                    .b_in(b_wire[i][j]),
+                    .a_out(a_wire[i][j+1]),
+                    .b_out(b_wire[i+1][j]),
+                    .c_out(c_array[i][j])
+                );
+            end
+        end
+    endgenerate
+
+    // Combinational logic for output with optional ReLU
+    assign c00 = activation ? (c_array[0][0] < 0 ? 0 : c_array[0][0]) : c_array[0][0];
+    assign c01 = activation ? (c_array[0][1] < 0 ? 0 : c_array[0][1]) : c_array[0][1];
+    assign c10 = activation ? (c_array[1][0] < 0 ? 0 : c_array[1][0]) : c_array[1][0];
+    assign c11 = activation ? (c_array[1][1] < 0 ? 0 : c_array[1][1]) : c_array[1][1];
+
+endmodule

WilliamZhang20_ECE298A-TPU/source/src/tpu.v

@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2025 William
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`default_nettype none
+
+module tt_um_tpu (
+    input  wire [7:0] ui_in,      // data input
+    output wire [7:0] uo_out,     // data output (lower 8 bits of result)
+    input  wire [7:0] uio_in,     // control input
+    output wire [7:0] uio_out,    // done signal on uio_out[7]
+    output wire [7:0] uio_oe,     // only uio_out[7] driven
+    input  wire       ena,
+    input  wire       clk,
+    input  wire       rst_n
+);
+
+    wire load_en = uio_in[0];
+    wire transpose = uio_in[1];
+    wire activation = uio_in[2];
+
+    wire mmu_en; // internal signal
+    reg clear; // reset of PEs only
+    wire [2:0] mem_addr; // 3-bit address for matrix and element selection
+    
+    wire [2:0] mmu_cycle; // compute/output cycle count - 3 bit
+
+    wire [7:0] weight0, weight1, weight2, weight3;
+    wire [7:0] input0, input1, input2, input3;
+
+    wire [15:0] outputs [0:3]; // raw accumulations (16-bit)
+    wire [7:0] out_data; // sent to CPU
+    // Ports of the systolic Array
+    wire [7:0] a_data0, b_data0, a_data1, b_data1;
+
+    wire done;
+    wire [1:0] state;
+
+    wire [7:0] stage1, stage2, stage3;
+
+    wire [7:0] uio_s1, uio_s2, uio_s3, uio_s4;
+
+    // Module Instantiations
+    memory mem (
+        .clk(clk),
+        .rst(~rst_n),
+        .load_en(load_en),
+        .addr(mem_addr),
+        .in_data(ui_in),
+        .weight0(weight0), .weight1(weight1), .weight2(weight2), .weight3(weight3),
+        .input0(input0), .input1(input1), .input2(input2), .input3(input3)
+    );
+
+    control_unit central_ctrl (
+        .clk(clk),
+        .rst(~rst_n),
+        .load_en(load_en),
+        .mem_addr(mem_addr),
+        .mmu_en(mmu_en),
+        .mmu_cycle(mmu_cycle),
+        .state_out(state)
+    );
+
+    systolic_array_2x2 mmu (
+        .clk(clk),
+        .rst(~rst_n),
+        .clear(clear),
+        .activation(activation),
+        .a_data0(a_data0),
+        .a_data1(a_data1),
+        .b_data0(b_data0),
+        .b_data1(b_data1),
+        .c00(outputs[0]), 
+        .c01(outputs[1]), 
+        .c10(outputs[2]), 
+        .c11(outputs[3])
+    );
+
+    mmu_feeder compute_ctrl (
+        .clk(clk),
+        .rst(~rst_n),
+        .en(mmu_en),
+        .mmu_cycle(mmu_cycle),
+        .transpose(transpose),
+        .weight0(weight0), .weight1(weight1), .weight2(weight2), .weight3(weight3),
+        .input0(input0), .input1(input1), .input2(input2), .input3(input3),
+        .c00(outputs[0]), 
+        .c01(outputs[1]), 
+        .c10(outputs[2]), 
+        .c11(outputs[3]),
+        .clear(clear),
+        .a_data0(a_data0),
+        .a_data1(a_data1),
+        .b_data0(b_data0),
+        .b_data1(b_data1),
+        .done(done),
+        .host_outdata(out_data)
+    );
+
+    genvar i;
+    generate
+        for (i = 0; i < 8; i = i + 1) begin : buf_loop
+            (* keep *) buffer buf1 (.A(out_data[i]), .X(stage1[i]));
+            (* keep *) buffer buf2 (.A(stage1[i]), .X(stage2[i]));
+            (* keep *) buffer buf3 (.A(stage2[i]), .X(stage3[i]));
+        end
+    endgenerate
+    assign uo_out = stage3;
+
+    assign uio_s1 = {done, state, 5'b0};
+
+    genvar j;
+    generate
+        for (j = 0; j < 8; j = j + 1) begin : uio_bufs
+            (* keep *) buffer buf21 (.A(uio_s1[j]), .X(uio_s2[j]));
+            (* keep *) buffer buf22 (.A(uio_s2[j]), .X(uio_s3[j]));
+            (* keep *) buffer buf23 (.A(uio_s3[j]), .X(uio_s4[j]));
+        end
+    endgenerate
+    assign uio_out = uio_s4;
+    assign uio_oe = 8'b11100000;
+
+    wire _unused = &{ena, uio_in[7:3]};
+
+endmodule

WilliamZhang20_ECE298A-TPU/source/test/Makefile

@@ -0,0 +1,134 @@
+# Makefile
+# See https://docs.cocotb.org/en/stable/quickstart.html for more info
+
+# defaults
+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+SRC_DIR = $(PWD)/../src
+
+TIMESTAMP = $(shell TZ=US/Eastern date +%Y%m%d_%H:%M:%S)
+WAVES_ROOT = $(PWD)
+COMPILE_ARGS += -DTIMESTAMP=\"$(TIMESTAMP)\"
+
+PROJECT_SOURCES = tpu.v \
+					systolic_array_2x2.v \
+					control_unit.v \
+					PE.v \
+					delay_cell.v \
+					mmu_feeder.v \
+					memory.v
+
+ifneq ($(GATES),yes)
+
+# RTL simulation:
+SIM_BUILD				= sim_build/rtl
+VERILOG_SOURCES += $(addprefix $(SRC_DIR)/,$(PROJECT_SOURCES))
+
+else
+
+# Gate level simulation:
+SIM_BUILD				= sim_build/gl
+COMPILE_ARGS    += -DGL_TEST
+COMPILE_ARGS    += -DFUNCTIONAL
+COMPILE_ARGS    += -DUSE_POWER_PINS
+COMPILE_ARGS    += -DSIM
+COMPILE_ARGS    += -DUNIT_DELAY=\#1
+VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+
+# this gets copied in by the GDS action workflow
+VERILOG_SOURCES += $(PWD)/gate_level_netlist.v
+
+endif
+
+# Allow sharing configuration between design and testbench via `include`:
+COMPILE_ARGS 		+= -I$(SRC_DIR)
+
+.PHONY: all test-uvm test-memory test-systolic-array test-control-unit test-nn test-mmu-feeder test-top
+
+all:
+	$(MAKE) test-uvm
+	$(MAKE) test-memory
+	$(MAKE) test-systolic-array
+	$(MAKE) test-control-unit
+	$(MAKE) test-mmu-feeder
+	$(MAKE) test-nn
+	$(MAKE) test-top
+
+test-uvm:
+	$(MAKE) clean
+	$(MAKE) sim \
+		TOPLEVEL=tb \
+		MODULE=test_uvm \
+		VERILOG_SOURCES="$(WAVES_ROOT)/uvm_test/tb.v $(addprefix $(SRC_DIR)/,tpu.v delay_cell.v systolic_array_2x2.v PE.v mmu_feeder.v control_unit.v memory.v)" \
+		PYTHONPATH=$(WAVES_ROOT)/uvm_test \
+		WAVES_DIR=$(WAVES_ROOT)/uvm_test/wave \
+		COMPILE_ARGS='$(COMPILE_ARGS) -DVCD_PATH="\"$(WAVES_ROOT)/uvm_test/wave/uvm_tb_$(TIMESTAMP).vcd\""'
+
+test-top:
+	$(MAKE) clean
+	$(MAKE) sim \
+		TOPLEVEL=tb \
+		MODULE=test_tpu \
+		VERILOG_SOURCES="$(WAVES_ROOT)/tpu/tb.v $(addprefix $(SRC_DIR)/,tpu.v delay_cell.v systolic_array_2x2.v PE.v mmu_feeder.v control_unit.v memory.v)" \
+		PYTHONPATH=$(WAVES_ROOT)/tpu \
+		WAVES_DIR=$(WAVES_ROOT)/tpu/wave \
+		COMPILE_ARGS='$(COMPILE_ARGS) -DVCD_PATH="\"$(WAVES_ROOT)/tpu/wave/tpu_tb_$(TIMESTAMP).vcd\""'
+
+test-nn:
+	$(MAKE) clean
+	$(MAKE) sim \
+		TOPLEVEL=tb \
+		MODULE=train_qat_model \
+		VERILOG_SOURCES="$(WAVES_ROOT)/tpu/tb.v $(addprefix $(SRC_DIR)/,tpu.v delay_cell.v systolic_array_2x2.v PE.v mmu_feeder.v control_unit.v memory.v)" \
+		PYTHONPATH=$(WAVES_ROOT)/tpu \
+		WAVES_DIR=$(WAVES_ROOT)/tpu/wave \
+		COMPILE_ARGS='$(COMPILE_ARGS) -DVCD_PATH="\"$(WAVES_ROOT)/tpu/wave/tpu_tb_$(TIMESTAMP).vcd\""'
+
+test-systolic-array:
+	$(MAKE) clean
+	$(MAKE) sim \
+        TOPLEVEL=systolic_array_tb \
+        MODULE=test_systolic_array \
+        VERILOG_SOURCES="$(WAVES_ROOT)/systolic_array/systolic_array_tb.v $(SRC_DIR)/systolic_array_2x2.v $(SRC_DIR)/PE.v" \
+        PYTHONPATH=$(WAVES_ROOT)/systolic_array \
+        WAVES_DIR=$(WAVES_ROOT)/systolic_array/wave \
+        COMPILE_ARGS='$(COMPILE_ARGS) -DVCD_PATH="\"$(WAVES_ROOT)/systolic_array/wave/systolic_array_tb_$(TIMESTAMP).vcd\""'
+
+test-memory:
+	$(MAKE) clean
+	$(MAKE) sim \
+		TOPLEVEL=memory_tb \
+		MODULE=test_memory \
+		VERILOG_SOURCES="$(WAVES_ROOT)/memory/memory_tb.v $(SRC_DIR)/memory.v" \
+		PYTHONPATH=$(WAVES_ROOT)/memory \
+		WAVES_DIR=$(WAVES_ROOT)/memory/wave \
+		COMPILE_ARGS='$(COMPILE_ARGS) -DVCD_PATH="\"$(WAVES_ROOT)/memory/wave/memory_tb_$(TIMESTAMP).vcd\""'
+
+test-control-unit:
+	$(MAKE) clean
+	$(MAKE) sim \
+		TOPLEVEL=control_unit_tb \
+		MODULE=test_control_unit \
+		VERILOG_SOURCES="$(WAVES_ROOT)/control_unit/control_unit_tb.v $(SRC_DIR)/control_unit.v" \
+		PYTHONPATH=$(WAVES_ROOT)/control_unit \
+		WAVES_DIR=$(WAVES_ROOT)/control_unit/wave \
+		COMPILE_ARGS='$(COMPILE_ARGS) -DVCD_PATH="\"$(WAVES_ROOT)/control_unit/wave/control_unit_tb_$(TIMESTAMP).vcd\""'
+
+test-mmu-feeder:
+	$(MAKE) clean
+	$(MAKE) sim \
+		TOPLEVEL=mmu_feeder_tb \
+		MODULE=test_mmu_feeder \
+		VERILOG_SOURCES="$(WAVES_ROOT)/mmu_feeder/mmu_feeder_tb.v $(SRC_DIR)/mmu_feeder.v" \
+		PYTHONPATH=$(WAVES_ROOT)/mmu_feeder \
+		WAVES_DIR=$(WAVES_ROOT)/mmu_feeder/wave \
+		COMPILE_ARGS='$(COMPILE_ARGS) -DVCD_PATH="\"$(WAVES_ROOT)/mmu_feeder/wave/mmu_feeder_tb_$(TIMESTAMP).vcd\""'
+
+# Phony target for cleaning up
+.PHONY: clean
+clean::
+	rm -rf sim_build* results.xml
+
+# include cocotb's make rules to take care of the simulator setup
+include $(shell cocotb-config --makefiles)/Makefile.sim

WilliamZhang20_ECE298A-TPU/source/test/README.md

@@ -0,0 +1,148 @@
+# TPU Test Suite
+
+This directory encompasses the test suite for our 2x2 TPU.
+
+## Structure
+
+The test suite contains both per-module and system integration tests within their own directories:
+
+* `control_unit/`: Control unit tests
+* `memory/`: Unified memory tests
+* `mmu_feeder/`: Matrix Unit Feeder tests
+* `systolic_array/`: Systolic Array tests
+* `tpu/`: Top-level system integration tests
+
+## Setting up
+
+### Local environment
+
+If you are running these tests locally, you will need:
+
+ * Python
+ * Icarus Verilog
+
+Both can be installed with your package manager of choice.
+
+From the `test` directory, create a Python virtual environment:
+
+```python
+python -m venv <ENV_NAME>
+
+# Linux/macOS
+source <ENV_NAME>/bin/activate
+
+# Windows
+<ENV_NAME>\Scripts\activate
+```
+
+Regardless of whether you require a virtual environment or are running the tests on a pre-configured server, there are some necessary packages that must be installed:
+
+```python
+pip install -r requirements.txt
+```
+
+## How to run
+
+The `Makefile` in the test directory has been set up with targets for each module and the top-level:
+
+```c
+// Per-module tests
+make test-top // System integration
+make test-memory
+make test-systolic-array
+make test-control-unit
+make test-mmu-feeder
+
+// Run all tests 
+make all
+
+// Cleanup build artifacts
+make clean
+```
+
+To run gate-level simulations, specify the `GATES` flag for `test-top`:
+
+```c
+make test-top GATES=yes
+```
+
+## Test Information
+
+### Control Unit Tests
+
+**File:** `test_control_unit.py`
+
+**Test Cases**:
+
+* **Reset**: verifies all control signals (mem_addr, mmu_en, mmu_cycle) are properly zeroed when reset is asserted
+* **Idle State**: ensures control unit remains in idle state with all outputs at zero when load_en is not asserted for multiple cycles
+* **Matrix Loading**: tests 8-cycle matrix loading phase with proper memory address incrementing (0-7) and MMU enable assertion when sufficient elements are loaded
+* **MMU Compute Phase**: validates MMU enable signals remain high and mmu_cycle counter increments correctly (2-7) during computation and writeback
+* **Full Cycle**: tests complete operation sequence from idle → matrix loading → MMU computation → back to compute state with proper signal transitions
+* **Load Enable Handling**: verifies load_en signal toggling is properly ignored during MMU compute phase while mmu_cycle continues incrementing normally
+* **Multiple Operations**: stress tests control unit with 100 consecutive operation cycles to ensure state machine reliability and proper signal timing
+
+### Unified Memory Tests
+
+**File:** `test_memory.py`
+
+**Test Cases**:
+
+* **Reset**: check if all values are zeroed when `rst` is asserted.
+* **Sequential Read/Write**: write to all `sram` addresses and check the outputs at each address.
+* **Load Enable Writes**: verify that writes only occur with `load_en` high.
+* **Overwrite Addresses**: write two values to an address; second value should overwrite the first one.
+* **Write During Reset**: ensure the validity of a reset if `rst` and `load_en` are asserted in the same cycle.
+* **Randomized Burst**: randomized addresses and data are generated within a valid range, written, and read for verification.
+
+### Matrix Unit Feeder Tests
+
+**File:** `test_mmu_feeder.py`
+
+**Test Cases**:
+
+* **Regular, Edge Case, and Transpose**: Test mmu_feeder with regular matrix inputs (minimal functionality), edge case matrix input (check expected behavior with extreme inputs), and regular matrix inputs with tranpose enabled (check transpose functionality).
+* **Random Test Vectors**: Generates 10 random Input/Weight matrix pairs and processes them sequentially, checking output against expected values.
+
+**Note**: Expected output control signal values from mmu_feeder (i.e clear and done) are asserted at each mmu_cycle, covering all mmu_feeder functionality.
+
+### Systolic Array Tests
+
+**File:** `test_systolic_array.py`
+
+**Test Cases**:
+
+* **Basic 2x2 Matrix Multiplication**: validates core systolic array functionality with predefined 2x2 matrices, testing proper data flow through processing elements and correct computation of matrix multiplication (A=[[1,2],[3,4]], B=[[5,6],[7,8]], expected C=[[19,22],[43,50]])
+
+### Top-level Tests
+
+**File:** `test_tpu.py`
+
+**Test Cases**:
+
+* **ReLU and Transpose Operations**: tests ReLU activation function and matrix transpose functionality with pipelined loading and reading, validating correct handling of negative values and matrix orientation changes
+* **Large Matrix Operations**: stress tests with randomly generated matrices up to 20x20, measuring operations per second and testing all combinations of transpose/ReLU flags to ensure scalability and performance
+* **Project Integration Test**: comprehensive end-to-end test simulating full TPU operation with sequential matrix operations
+  - Tests signed arithmetic edge cases with values ranging from -128 to 127
+  - Validates pipeline clearing between consecutive matrix operations
+  - Verifies proper output sequencing across multiple matrix computations
+  - Tests extreme value combinations (-128 × 127, -128 × -128)
+  - Ensures correct handling of result overflow and saturation
+
+* **Verification Correctness**: output results were validated using commerically and popularly proven tools like NumPy, allowing us to verify that the logic of the circuit is correct. Similarly, when block multiplication was performed in bigger matrices, in which special algorithms were applied to break down the matrices, the NumPy validation was applied outside the hardware's required matrix breakdown, which validates the entire process at both ends.
+
+## Viewing waveforms
+
+Each module's test directory has a `wave` directory, which contains `.vcd` waveforms generated after each test. These can be viewed with either `surfer` or `GTKWave`:
+
+```sh
+# GTKWave
+gtkwave tb.vcd
+
+# Surfer
+surfer tb.vcd
+```
+
+## Post-Silicon Tests
+
+A future Python script that interfaces with the chip via the Caravel SoC can feed data and read outputs.

WilliamZhang20_ECE298A-TPU/source/test/control_unit/control_unit_tb.v

@@ -0,0 +1,38 @@
+`default_nettype none
+`timescale 1ns / 1ps
+
+module control_unit_tb ();
+
+    // Dump the signals to a VCD file. You can view it with gtkwave or surfer.
+    initial begin
+`ifdef VCD_PATH
+        $dumpfile(`VCD_PATH);
+`else
+        $dumpfile("control_unit_tb.vcd");
+`endif
+        $dumpvars(0, control_unit_tb);
+        #1;
+    end
+
+    // Inputs
+    reg clk;
+    reg rst;
+    reg load_en;
+    reg[1:0] state_out;
+
+    // Outputs
+    reg [2:0] mem_addr;
+    reg mmu_en;
+    reg [2:0] mmu_cycle;
+
+    control_unit dut (
+        .clk(clk),
+		.rst(rst),
+        .load_en(load_en),
+        .mem_addr(mem_addr),
+        .mmu_en(mmu_en),
+        .mmu_cycle(mmu_cycle),
+        .state_out(state_out)
+    );
+
+endmodule

WilliamZhang20_ECE298A-TPU/source/test/control_unit/test_control_unit.py

@@ -0,0 +1,243 @@
+import cocotb
+from cocotb.triggers import RisingEdge, ClockCycles
+from cocotb.clock import Clock
+
+@cocotb.test()
+async def test_control_unit_reset(dut):
+    """Test control unit reset functionality"""
+    clock = Clock(dut.clk, 20, units="ns")
+    cocotb.start_soon(clock.start())
+
+    # Apply reset
+    dut.rst.value = 1
+    dut.load_en.value = 0
+    await ClockCycles(dut.clk, 2)
+    
+    # Check reset state
+    assert dut.mem_addr.value == 0, f"mem_addr should be 0 after reset, got {dut.mem_addr.value}"
+    assert dut.mmu_en.value == 0, f"mmu_en should be 0 after reset, got {dut.mmu_en.value}"
+    assert dut.mmu_cycle.value == 0, f"mmu_cycle should be 0 after reset, got {dut.mmu_cycle.value}"
+    
+    dut.rst.value = 0
+    await ClockCycles(dut.clk, 1)
+    
+    dut._log.info("Reset test passed")
+
+@cocotb.test()
+async def test_control_unit_idle_state(dut):
+    """Test control unit stays in IDLE when load_en is not asserted"""
+    clock = Clock(dut.clk, 20, units="ns")
+    cocotb.start_soon(clock.start())
+
+    # Reset
+    dut.rst.value = 1
+    dut.load_en.value = 0
+    await ClockCycles(dut.clk, 2)
+    dut.rst.value = 0
+    await ClockCycles(dut.clk, 1)
+
+    # Stay in idle for several cycles
+    for _ in range(5):
+        assert dut.mem_addr.value == 0, f"mem_addr should remain 0 in idle, got {dut.mem_addr.value}"
+        assert dut.mmu_en.value == 0, f"mmu_en should remain 0 in idle, got {dut.mmu_en.value}"
+        assert dut.mmu_cycle.value == 0, f"mmu_cycle should remain 0 in idle, got {dut.mmu_cycle.value}"
+        await ClockCycles(dut.clk, 1)
+    
+    dut._log.info("Idle state test passed")
+
+@cocotb.test()
+async def test_control_unit_load_matrices(dut):
+    """Test control unit matrix loading phase"""
+    clock = Clock(dut.clk, 20, units="ns")
+    cocotb.start_soon(clock.start())
+
+    # Reset
+    dut.rst.value = 1
+    dut.load_en.value = 0
+    await ClockCycles(dut.clk, 2)
+    dut.rst.value = 0
+    await ClockCycles(dut.clk, 1)
+
+    # Start loading - first load_en pulse should trigger transition to LOAD_MATS
+    dut.load_en.value = 1
+    await ClockCycles(dut.clk, 1)
+
+    # Check memory address increments correctly during loading
+    expected_addrs = [0, 1, 2, 3, 4, 5, 6, 7]
+    for i, expected_addr in enumerate(expected_addrs):
+        # Check current state BEFORE the clock edge
+        assert int(dut.mem_addr.value) == expected_addr, f"Cycle {i+1}: mem_addr should be {expected_addr}, got {dut.mem_addr.value}"
+
+        current_loaded = int(dut.mem_addr.value)
+        # We check when loaded = 6 and not when =5
+        # The value is "set" when =5
+        # Sequential regs capture the value on the next clock edge
+        # So we need to wait another cycle
+        if current_loaded >= 6:
+            assert dut.mmu_en.value == 1, f"Cycle {i+1}: mmu_en should be 1 when mat_elems_loaded >= 6"
+        else:
+            assert dut.mmu_en.value == 0, f"Cycle {i+1}: mmu_en should be 0 when mat_elems_loaded < 5"
+
+        # Wait for next clock edge (this is when assignments happen)
+        await ClockCycles(dut.clk, 1)
+
+    # After the loop, we've had 8 clock cycles
+    # Check final state after all loading is complete
+    # At this point, mat_elems_loaded should have been reset to 0 (from the == 7 condition)
+    assert dut.mem_addr.value == 0, "mem_addr should be 0 after loading all 8 elements"
+    assert dut.mmu_en.value == 1, "mmu_en should be 1 after loading all 8 elements"
+    dut.load_en.value = 0
+
+    # mmu_cycle should have incremented - check based on your logic
+    # If it starts at 0 and increments when mat_elems_loaded >= 6, 
+    # it should be incremented multiple times during the loading
+    print(f"Final state: mmu_cycle = {dut.mmu_cycle.value}")
+
+    dut._log.info("Matrix loading test passed")
+
+@cocotb.test()
+async def test_control_unit_mmu_compute_phase(dut):
+    """Test control unit MMU compute and writeback phase"""
+    clock = Clock(dut.clk, 20, units="ns")
+    cocotb.start_soon(clock.start())
+
+    # Reset
+    dut.rst.value = 1
+    dut.load_en.value = 0
+    await ClockCycles(dut.clk, 2)
+    dut.rst.value = 0
+    await ClockCycles(dut.clk, 1)
+
+    # Load all 8 elements quickly
+    dut.load_en.value = 1
+    print("State: ", int(dut.state_out))
+    for _ in range(8):
+        print("State: ", int(dut.state_out))
+        await ClockCycles(dut.clk, 1)
+    dut.load_en.value = 0
+    print("State: ", int(dut.state_out))
+    
+    # Now in MMU_FEED_COMPUTE_WB state
+    # mmu_cycle should increment from 2 to 7 (0 -> 1 done in S_LOAD_MATS state)
+    for expected_cycle in range(2, 8):
+        print("State: ", int(dut.state_out))
+        await ClockCycles(dut.clk, 1)
+        assert dut.mmu_en.value == 1, f"mmu_en should remain 1 during compute phase"
+        assert dut.mmu_cycle.value.integer == expected_cycle, f"mmu_cycle should be {expected_cycle}, got {dut.mmu_cycle.value}"
+
+        assert dut.load_en.value == 0, f"load_en should remain 0 during compute phase"
+        assert dut.mem_addr.value == 0, f"mem_addr should be 0 during compute phase"
+    
+    # After mmu_cycle reaches 5, should return to IDLE
+    # print("State: ", int(dut.state_out))
+    await ClockCycles(dut.clk, 1)
+    assert dut.mmu_en.value == 1, "mmu_en should be 1 while kept in COMPUTE"
+    assert dut.mmu_cycle.value.integer == 0, "mmu_cycle should reset to 0 in COMPUTE"
+    assert dut.mem_addr.value == 0, "mem_addr should be 0 in COMPUTE with no LOAD_EN"
+
+    await ClockCycles(dut.clk, 1) 
+
+    # MMU cycle continues cycling although we are not sending anything over....
+    
+    assert dut.mmu_cycle.value.integer == 1, "mmu_cycle should cycle in compute"
+    
+    dut._log.info("MMU compute phase test passed")
+
+@cocotb.test()
+async def test_control_unit_full_cycle(dut):
+    """Test complete control unit operation cycle"""
+    clock = Clock(dut.clk, 20, units="ns")
+    cocotb.start_soon(clock.start())
+
+    # Reset
+    dut.rst.value = 1
+    dut.load_en.value = 0
+    await ClockCycles(dut.clk, 2)
+    dut.rst.value = 0
+    await ClockCycles(dut.clk, 1)
+
+    # Full cycle: IDLE -> LOAD_MATS -> MMU_FEED_COMPUTE_WB -> IDLE
+    
+    # Phase 1: Load matrices (8 cycles)
+    dut.load_en.value = 1
+    for cycle in range(8):
+        await ClockCycles(dut.clk, 1)
+        if cycle < 7:  # During loading
+            assert dut.mem_addr.value.integer == cycle, f"mem_addr should be {cycle} during loading cycle {cycle}"
+    
+    # Phase 2: MMU compute (7 cycles: mmu_cycle 2->7->0)
+    for cycle in range(2, 8):
+        await ClockCycles(dut.clk, 1)
+        assert dut.mmu_en.value == 1, f"mmu_en should be 1 during MMU cycle {cycle}"
+        assert dut.mem_addr.value == cycle-2, f"mem_addr should be {cycle-2} during MMU cycle {dut.mmu_cycle.value.integer}"
+    
+    # Phase 3: pretending that we are continuing to load future matrice with load_en high... and mem_addr going up
+    await ClockCycles(dut.clk, 1)
+    assert dut.mmu_en.value == 1, "mmu_en should be 1 while kept in COMPUTE"
+    assert dut.mmu_cycle.value.integer == 0, "mmu_cycle should reset to 0 in COMPUTE"
+    assert dut.mem_addr.value.integer == 6, "mem_addr should be 0 in COMPUTE with no LOAD_EN"
+    
+    dut._log.info("Full cycle test passed")
+
+@cocotb.test()
+async def test_control_unit_shaky_load_en(dut):
+    """Test that load_en is ignored during MMU compute phase"""
+    clock = Clock(dut.clk, 20, units="ns")
+    cocotb.start_soon(clock.start())
+
+    # Reset
+    dut.rst.value = 1
+    dut.load_en.value = 0
+    await ClockCycles(dut.clk, 2)
+    dut.rst.value = 0
+    await ClockCycles(dut.clk, 1)
+
+    # Load matrices, toggle load_en, should only proceed on load_en
+    for cycle in range(8):
+        dut.load_en.value = 1
+        await ClockCycles(dut.clk, 1)
+        assert dut.mem_addr.value.integer == cycle
+
+    # Now in MMU compute phase
+    for cycle in range(2, 8):
+        dut.load_en.value = 1 if cycle % 2 == 0 else 0
+        await ClockCycles(dut.clk, 1)
+        # mmu_cycle should still increment normally regardless of load_en
+        assert dut.mmu_cycle.value.integer == cycle, f"mmu_cycle should increment normally during compute phase"
+    
+    dut._log.info("Shaky load enable during compute test passed")
+
+@cocotb.test()
+async def test_control_unit_multiple_operations(dut):
+    """Test multiple complete operation cycles"""
+    clock = Clock(dut.clk, 20, units="ns")
+    cocotb.start_soon(clock.start())
+
+    # Reset
+    dut.rst.value = 1
+    dut.load_en.value = 0
+    await ClockCycles(dut.clk, 2)
+    dut.rst.value = 0
+    await ClockCycles(dut.clk, 1)
+
+    # Init Load phase
+    dut.load_en.value = 1
+    for _ in range(8):
+        await ClockCycles(dut.clk, 1)
+
+    # Run 100 complete cycles
+    for operation in range(100):
+        # Commented below line for clarity of test action
+        # dut._log.info(f"Starting operation {operation + 1}")
+        
+        # output/input phase
+        # Note that load_en is still asserted high
+        for val in range(8):
+            await ClockCycles(dut.clk, 1)
+            assert dut.mmu_en.value == 1, f"Operation {operation + 1}: mmu_en should be 1 during MMU phase"
+            assert dut.mmu_cycle.value.integer == (val + 2) % 8, f"MMU Cycle not running properly as it should be {val}"
+    
+        # Wait in idle before next operation
+        dut.load_en.value = 0
+    
+    dut._log.info("Multiple operations test passed")

WilliamZhang20_ECE298A-TPU/source/test/requirements.txt

@@ -0,0 +1,8 @@
+pytest==8.3.4
+cocotb==1.9.2
+numpy==2.1.3
+torch
+torchvision
+pyuvm
+torchao
+executorch

WilliamZhang20_ECE298A-TPU/testbenches.json

@@ -0,0 +1,98 @@
+[
+  {
+    "file_path": "test/control_unit/test_control_unit.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "test/Makefile",
+    "top_module": "control_unit_tb",
+    "rtl_files": [
+      "test/control_unit/control_unit_tb.v",
+      "src/control_unit.v"
+    ]
+  },
+  {
+    "file_path": "test/memory/test_memory.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "test/Makefile",
+    "top_module": "memory_tb",
+    "rtl_files": [
+      "test/memory/memory_tb.v",
+      "src/memory.v"
+    ]
+  },
+  {
+    "file_path": "test/mmu_feeder/test_mmu_feeder.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "test/Makefile",
+    "top_module": "mmu_feeder_tb",
+    "rtl_files": [
+      "test/mmu_feeder/mmu_feeder_tb.v",
+      "src/mmu_feeder.v"
+    ]
+  },
+  {
+    "file_path": "test/systolic_array/test_systolic_array.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "test/Makefile",
+    "top_module": "systolic_array_tb",
+    "rtl_files": [
+      "test/systolic_array/systolic_array_tb.v",
+      "src/systolic_array_2x2.v",
+      "src/PE.v"
+    ]
+  },
+  {
+    "file_path": "test/tpu/test_tpu.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "test/Makefile",
+    "top_module": "tb",
+    "rtl_files": [
+      "test/tpu/tb.v",
+      "src/tpu.v",
+      "src/delay_cell.v",
+      "src/systolic_array_2x2.v",
+      "src/PE.v",
+      "src/mmu_feeder.v",
+      "src/control_unit.v",
+      "src/memory.v"
+    ]
+  },
+  {
+    "file_path": "test/tpu/train_qat_model.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "test/Makefile",
+    "top_module": "tb",
+    "rtl_files": [
+      "test/tpu/tb.v",
+      "src/tpu.v",
+      "src/delay_cell.v",
+      "src/systolic_array_2x2.v",
+      "src/PE.v",
+      "src/mmu_feeder.v",
+      "src/control_unit.v",
+      "src/memory.v"
+    ]
+  },
+  {
+    "file_path": "test/uvm_test/test_uvm.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "test/Makefile",
+    "top_module": "tb",
+    "rtl_files": [
+      "test/uvm_test/tb.v",
+      "src/tpu.v",
+      "src/delay_cell.v",
+      "src/systolic_array_2x2.v",
+      "src/PE.v",
+      "src/mmu_feeder.v",
+      "src/control_unit.v",
+      "src/memory.v"
+    ]
+  }
+]

completed.json

@@ -1,6 +1,6 @@
 {
   "version": 2,
-  "generated_at": "2026-04-07T07:23:03.015881+00:00",
+  "generated_at": "2026-04-07T19:17:08.564998+00:00",
   "entries": {
     "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_mealy/missing_reset": {
       "status": "sim_ok"
@@ -136,7 +136,7 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__leds/missing_enable": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "Mr-Bossman_KISC-V/soc_top__uart/blocking_nonblocking": {
       "status": "waveform_identical"
@@ -191,7 +191,7 @@
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Main_Decoder/inverted_condition": {
       "status": "sim_ok"
@@ -303,7 +303,7 @@
       "status": "waveform_identical"
     },
     "JN513_Risco-5/Core__alu_control/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "Weiyet_RTLStructLib/singly_linked_list__singly_linked_list/inverted_condition": {
       "status": "sim_ok"
@@ -367,7 +367,7 @@
       "status": "compile_error"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/missing_enable": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "Vaibhav-Gunthe_Verilog-Projects/alu_8bit__8bit-ALU/case_swap": {
       "status": "sim_ok"
@@ -419,7 +419,7 @@
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__registers/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "projf_isle/ch06__uart_dev/missing_reset": {
       "status": "waveform_identical"
@@ -594,7 +594,7 @@
       "examples_count": 0
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ImmGen/concat_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__PC/blocking_nonblocking": {
       "status": "sim_ok"
@@ -606,7 +606,7 @@
       "status": "compile_error"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/missing_reset": {
-      "status": "timeout"
+      "status": "waveform_identical"
     },
     "alexforencich_verilog-axi/axi_crossbar_wrap_4x4__arbiter/inverted_condition": {
       "status": "timeout"
@@ -618,7 +618,7 @@
       "status": "compile_error"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__code_defs_pkg/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "qossayrida_PipelineProcessorDesign/IFStage__IFStage/wrong_bitwidth": {
       "status": "waveform_identical"
@@ -627,7 +627,7 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__core/missing_enable": {
-      "status": "sim_ok"
+      "status": "sim_failed"
     },
     "mnmhdanas_Router-1-x-3-/router_reg__router_reg/wrong_bitwidth": {
       "status": "sim_ok"
@@ -645,7 +645,7 @@
       "status": "sim_ok"
     },
     "aditeyabaral_DDCO-Lab-UE18CS207/reg_alu__lib/operator_typo": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "erihsu_INT_FP_MAC/int_fp_add__int_fp_add/operator_typo": {
       "status": "sim_failed"
@@ -663,7 +663,7 @@
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/inverted_condition": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "projf_isle/ch04__textmode/missing_reset": {
       "status": "waveform_identical"
@@ -681,7 +681,7 @@
       "status": "compile_error"
     },
     "JN513_Risco-5/Core__memory/missing_enable": {
-      "status": "sim_ok"
+      "status": "sim_failed"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/concat_swap": {
       "status": "waveform_identical"
@@ -711,7 +711,7 @@
       "status": "sim_failed"
     },
     "aditeyabaral_DDCO-Lab-UE18CS207/mproc_mem__mproc_mem/wrong_bitwidth": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "fcayci_sv-digital-design/fsm_tick__fsm_tick_en/inverted_condition": {
       "status": "sim_ok"
@@ -837,10 +837,10 @@
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/inverted_condition": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "Weiyet_RTLStructLib/list__sorter/inverted_condition": {
       "status": "sim_ok"
@@ -873,20 +873,20 @@
       "status": "sim_ok"
     },
     "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/unconnected_port": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "biren15_Design-and-Implementation-of-a-Cruise-Control-System/cruisecontrol__cruisecontrol/operator_typo": {
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__pc/missing_enable": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "mnmhdanas_UART-protocol/UARTtb__counter_tx/blocking_nonblocking": {
       "status": "sim_ok",
       "examples_count": 0
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Sign_Extend/operator_typo": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/signal_typo": {
       "status": "compile_error"
@@ -934,7 +934,7 @@
       "status": "sim_ok"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Register_File/missing_enable": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "mnmhdanas_UART-protocol/UARTtb__piso_tx/blocking_nonblocking": {
       "status": "sim_ok",
@@ -950,7 +950,7 @@
       "status": "compile_error"
     },
     "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/state_transition": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "mnmhdanas_UART-protocol/UARTtb__piso_tx/wrong_bitwidth": {
       "status": "sim_ok"
@@ -980,7 +980,7 @@
       "status": "compile_error"
     },
     "JN513_Risco-5/Core__memory/concat_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "mnmhdanas_UART-protocol/UARTtb__transmitter/blocking_nonblocking": {
       "status": "sim_ok",
@@ -1051,10 +1051,10 @@
       "status": "sim_ok"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Execute_Cycle/missing_reset": {
-      "status": "sim_ok"
+      "status": "compile_error"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Hazard_Unit/operator_typo": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU_Control/case_swap": {
       "status": "sim_ok"
@@ -1120,7 +1120,7 @@
       "status": "sim_ok"
     },
     "aditeyabaral_DDCO-Lab-UE18CS207/pc__lib/operator_typo": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b4lane__mipi_csi_rx_raw_depacker_8b4lane/width_bit_cutoff": {
       "status": "sim_failed"
@@ -1160,7 +1160,7 @@
       "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/delayed_signal": {
       "status": "compile_error"
@@ -1227,7 +1227,7 @@
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC_Adderr/missing_enable": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "defano_digital-design/konamiacceptor__debouncer/operator_typo": {
       "status": "sim_ok"
@@ -1273,7 +1273,7 @@
       "status": "waveform_identical"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/missing_reset": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b4lane__mipi_csi_rx_raw_depacker_8b4lane/off_by_one_counter": {
       "status": "sim_failed"
@@ -1285,7 +1285,7 @@
       "status": "sim_ok"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Memory_Cycle/wrong_bitwidth": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/missing_reset": {
       "status": "sim_ok"
@@ -1300,13 +1300,13 @@
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__IF_ID/missing_enable": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "JN513_Risco-5/Core__memory/blocking_nonblocking": {
       "status": "waveform_identical"
     },
     "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/off_by_one_counter": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "defano_digital-design/sevensegment__displaydriver/width_bit_cutoff": {
       "status": "sim_ok"
@@ -1369,10 +1369,10 @@
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/missing_reset": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "JN513_Risco-5/Core__core/inverted_condition": {
-      "status": "sim_ok"
+      "status": "sim_failed"
     },
     "fcayci_sv-digital-design/fsm_tick__fsm_tick_en/delayed_signal": {
       "status": "sim_ok"
@@ -1381,7 +1381,7 @@
       "status": "compile_error"
     },
     "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Wrapper/unconnected_port": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "alexforencich_verilog-axi/axi_fifo__axi_fifo_wr/inverted_condition": {
       "status": "sim_failed"
@@ -1438,7 +1438,7 @@
       "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BTB/missing_reset": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "JN513_Risco-5/Core__mdu/delayed_signal": {
       "status": "waveform_identical"
@@ -1474,7 +1474,7 @@
       "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/inverted_condition": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_moore/missing_else_latch": {
       "status": "sim_ok"
@@ -1549,7 +1549,7 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/ClkDivider__clk_divider/missing_enable": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "projf_isle/ch02__canv_disp_agu/missing_reset": {
       "status": "sim_ok"
@@ -1579,10 +1579,10 @@
       "status": "compile_error"
     },
     "JN513_Risco-5/Core__leds/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/off_by_one_counter": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/wrong_bitwidth": {
       "status": "sim_ok"
@@ -1600,10 +1600,10 @@
       "status": "waveform_identical"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Execute_Cycle/unconnected_port": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "JN513_Risco-5/Core__memory/inverted_condition": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/operator_typo": {
       "status": "sim_ok"
@@ -1630,7 +1630,7 @@
       "status": "waveform_identical"
     },
     "JN513_Risco-5/Core__pc/missing_reset": {
-      "status": "sim_ok"
+      "status": "sim_failed"
     },
     "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/signal_typo": {
       "status": "compile_error"
@@ -1654,10 +1654,10 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__control_unit/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/operator_typo": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/blocking_nonblocking": {
       "status": "compile_error"
@@ -1726,13 +1726,13 @@
       "status": "sim_ok"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Sign_Extend/inverted_condition": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/signal_typo": {
       "status": "compile_error"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/missing_reset": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "defano_digital-design/uart__uart/blocking_nonblocking": {
       "status": "llm_failed"
@@ -1765,7 +1765,7 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__immediate_generator/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "biren15_Design-and-Implementation-of-a-Cruise-Control-System/cruisecontrol__cruisecontrol/inverted_condition": {
       "status": "sim_ok"
@@ -1784,13 +1784,13 @@
       "examples_count": 0
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/concat_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "accomdemy_accomdemy_rv32i/cpu__instr_memory/wrong_bitwidth": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "JN513_Risco-5/Core__core/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/operator_typo": {
       "status": "sim_ok"
@@ -1884,7 +1884,7 @@
       "status": "waveform_identical"
     },
     "mnmhdanas_Router-1-x-3-/router_reg__router_reg/inverted_condition": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__mac_pcs/signal_typo": {
       "status": "compile_error"
@@ -1924,7 +1924,7 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__csr_unit/missing_enable": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/signal_typo": {
       "status": "compile_error"
@@ -2042,7 +2042,7 @@
       "status": "sim_failed"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Forwarding_Unit/operator_typo": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "shahsaumya00_Floating-Point-Adder/adder__adder_pipeline/operator_typo": {
       "status": "sim_ok"
@@ -2069,7 +2069,7 @@
       "status": "compile_error"
     },
     "JN513_Risco-5/Core__mdu/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "Weiyet_RTLStructLib/hash_table__hash_table/wrong_bitwidth": {
       "status": "waveform_identical"
@@ -2087,7 +2087,7 @@
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/wrong_bitwidth": {
       "status": "sim_ok"
@@ -2139,7 +2139,7 @@
       "status": "compile_error"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU/operator_typo": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "dpretet_async_fifo/async_fifo__wptr_full/missing_reset": {
       "status": "sim_ok"
@@ -2217,7 +2217,7 @@
       "status": "compile_error"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "projf_isle/ch02__ch02/case_swap": {
       "status": "sim_ok"
@@ -2283,10 +2283,10 @@
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/missing_reset": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/missing_reset": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "Mr-Bossman_KISC-V/soc_top__timer/blocking_nonblocking": {
       "status": "waveform_identical"
@@ -2301,10 +2301,10 @@
       "status": "sim_failed"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/missing_enable": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/operator_typo": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_moore/missing_reset": {
       "status": "sim_ok"
@@ -2325,7 +2325,7 @@
       "status": "sim_ok"
     },
     "defano_digital-design/uart__uart/wrong_bitwidth": {
-      "status": "llm_failed"
+      "status": "timeout"
     },
     "JN513_Risco-5/Core__core/delayed_signal": {
       "status": "llm_failed"
@@ -2374,7 +2374,7 @@
       "status": "sim_failed"
     },
     "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/missing_reset": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "erihsu_INT_FP_MAC/int_fp_add__add_normalizer/operator_typo": {
       "status": "sim_failed"
@@ -2404,7 +2404,7 @@
       "status": "waveform_identical"
     },
     "JN513_Risco-5/Core__csr_unit/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "alexforencich_verilog-axi/axi_dma__axi_dma_wr/inverted_condition": {
       "status": "llm_failed"
@@ -2473,7 +2473,7 @@
       "status": "compile_error"
     },
     "JN513_Risco-5/Core__alu_control/inverted_condition": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/delayed_signal": {
       "status": "sim_ok"
@@ -2546,16 +2546,16 @@
       "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ImmGen/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Sign_Extend/concat_swap": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "apfaudio_eurorack-pmod/vca__vca/operator_typo": {
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__csr_unit/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__mac/missing_enable": {
       "status": "waveform_identical"
@@ -2579,7 +2579,7 @@
       "status": "compile_error"
     },
     "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/inverted_condition": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Master/case_swap": {
       "status": "sim_ok"
@@ -2597,7 +2597,7 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__control_unit/missing_reset": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/delayed_signal": {
       "status": "sim_ok"
@@ -2709,7 +2709,7 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__csr_unit/inverted_condition": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "Mr-Bossman_KISC-V/soc_top__cpu/blocking_nonblocking": {
       "status": "waveform_identical"
@@ -2742,7 +2742,7 @@
       "status": "compile_error"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/unconnected_port": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "defano_digital-design/sevensegment__sevensegment/wrong_bitwidth": {
       "status": "sim_ok"
@@ -2799,10 +2799,10 @@
       "status": "waveform_identical"
     },
     "JN513_Risco-5/Core__registers/missing_enable": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "aditeyabaral_DDCO-Lab-UE18CS207/mproc_mem__lib/operator_typo": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "projf_isle/ch05__xd/wrong_bitwidth": {
       "status": "sim_ok"
@@ -2811,7 +2811,7 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__mdu/missing_enable": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "Weiyet_RTLStructLib/list__list/missing_enable": {
       "status": "sim_ok"
@@ -2859,7 +2859,7 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__control_unit/inverted_condition": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC_Adderr/missing_else_latch": {
       "status": "compile_error"
@@ -2883,7 +2883,7 @@
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/operator_typo": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "Mr-Bossman_KISC-V/soc_top__intctrl/delayed_signal": {
       "status": "waveform_identical"
@@ -2933,7 +2933,7 @@
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__I_Mem/concat_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "alexforencich_verilog-axi/axil_adapter__axil_adapter_rd/inverted_condition": {
       "status": "sim_failed"
@@ -2954,7 +2954,7 @@
       "status": "waveform_identical"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__ALU_Decoder/operator_typo": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "accomdemy_accomdemy_rv32i/cpu__regfile/inverted_condition": {
       "status": "waveform_identical"
@@ -2963,7 +2963,7 @@
       "status": "waveform_identical"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/off_by_one_counter": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "roo16kie_MAC_Verilog/mac__mac/missing_reset": {
       "status": "sim_ok"
@@ -3026,7 +3026,7 @@
       "status": "sim_ok"
     },
     "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Master/state_transition": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "yaseensalah_Digital-Design-of-FIR-Filter/fir_filter__fir_filter/wrong_bitwidth": {
       "status": "waveform_identical"
@@ -3096,7 +3096,7 @@
       "status": "waveform_identical"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__accelerator/unconnected_port": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "alexforencich_verilog-axi/axi_fifo__axi_fifo_rd/inverted_condition": {
       "status": "sim_failed"
@@ -3109,7 +3109,7 @@
       "status": "sim_failed"
     },
     "JN513_Risco-5/Core__mdu/inverted_condition": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "accomdemy_accomdemy_rv32i/cpu__regfile/operator_typo": {
       "status": "waveform_identical"
@@ -3170,7 +3170,7 @@
       "status": "compile_error"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__mac/unconnected_port": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/state_transition": {
       "status": "compile_error"
@@ -3278,7 +3278,7 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__immediate_generator/concat_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "mnmhdanas_UART-protocol/UARTtb__counter_rx/wrong_bitwidth": {
       "status": "sim_ok",
@@ -3330,7 +3330,7 @@
       "status": "sim_ok"
     },
     "aditeyabaral_DDCO-Lab-UE18CS207/fa4__lib/operator_typo": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "defano_digital-design/knightrider__knight-rider/missing_reset": {
       "status": "sim_ok"
@@ -3405,7 +3405,7 @@
       "status": "compile_error"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__ALU/inverted_condition": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "ayushc13_32-bit-RISC-processor-using-HDL-Verilog/mips32__mips32/concat_swap": {
       "status": "sim_ok"
@@ -3435,7 +3435,7 @@
       "status": "compile_error"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Data_Memory/missing_enable": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/operator_typo": {
       "status": "compile_error"
@@ -3456,7 +3456,7 @@
       "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__LDU/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/signal_typo": {
       "status": "compile_error"
@@ -3480,7 +3480,7 @@
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/missing_reset": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/concat_swap": {
       "status": "waveform_identical"
@@ -3489,7 +3489,7 @@
       "status": "sim_failed"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Forwarding_Unit/inverted_condition": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "fcayci_sv-digital-design/fsm_counter__fsm_counter/missing_reset": {
       "status": "sim_ok"
@@ -3499,7 +3499,7 @@
       "examples_count": 0
     },
     "JN513_Risco-5/Core__mux/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "mnmhdanas_UART-protocol/UARTtb__bitchecker_rx/concat_swap": {
       "status": "sim_ok",
@@ -3509,7 +3509,7 @@
       "status": "sim_ok"
     },
     "aditeyabaral_DDCO-Lab-UE18CS207/alu__lib/operator_typo": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "Weiyet_RTLStructLib/fifo__fifo/wrong_bitwidth": {
       "status": "sim_ok"
@@ -3560,7 +3560,7 @@
       "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/missing_enable": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Slave/inverted_condition": {
       "status": "sim_ok"
@@ -3620,7 +3620,7 @@
       "status": "sim_ok"
     },
     "apfaudio_eurorack-pmod/ak4619__ak4619/missing_enable": {
-      "status": "compile_error"
+      "status": "timeout"
     },
     "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b4lane__mipi_csi_rx_raw_depacker_8b4lane/wrong_bitwidth": {
       "status": "sim_failed"
@@ -3644,7 +3644,7 @@
       "status": "sim_ok"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BPU/case_swap": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "scarv_xcrypto/xc_malu__xc_malu_divrem/operator_typo": {
       "status": "sim_ok"
@@ -3653,16 +3653,16 @@
       "status": "waveform_identical"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Execute_Cycle/wrong_bitwidth": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/off_by_one_counter": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "JN513_Risco-5/Core__alu/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "JN513_Risco-5/Core__csr_unit/concat_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "apfaudio_eurorack-pmod/top__eurorack_pmod/wrong_bitwidth": {
       "status": "compile_error"
@@ -3713,7 +3713,7 @@
       "status": "sim_ok"
     },
     "JN513_Risco-5/Core__memory/case_swap": {
-      "status": "waveform_identical"
+      "status": "sim_failed"
     },
     "defano_digital-design/knightrider__knight-rider/delayed_signal": {
       "status": "sim_ok"
@@ -3752,10 +3752,10 @@
       "status": "waveform_identical"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Main_Decoder/operator_typo": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BHT/operator_typo": {
-      "status": "compile_error"
+      "status": "waveform_identical"
     },
     "fcayci_sv-digital-design/adder_str__adder_str/unconnected_port": {
       "status": "sim_ok"
@@ -3777,7 +3777,7 @@
       "status": "sim_ok"
     },
     "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/missing_reset": {
-      "status": "compile_error"
+      "status": "timeout"
     },
     "zhangxin6_iverilog_testbench/display_pal__display_pal/operator_typo": {
       "status": "sim_ok"
@@ -3795,7 +3795,7 @@
       "status": "sim_ok"
     },
     "Mr-Bossman_KISC-V/AXI4Lite_translator__axi/inverted_condition": {
-      "status": "waveform_identical"
+      "status": "sim_ok"
     },
     "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/inverted_condition": {
       "status": "sim_ok"
@@ -3878,7 +3878,7 @@
       "status": "sim_ok"
     },
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__ALU/operator_typo": {
-      "status": "sim_ok"
+      "status": "waveform_identical"
     },
     "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__ALU/case_swap": {
       "status": "sim_ok"
@@ -3910,52 +3910,540 @@
     },
     "scarv_xcrypto/p_mul__p_mul/missing_reset": {
       "status": "waveform_identical"
-    }
-  },
-  "bug_types_attempted": {
-    "projf_isle": [
-      "case_swap",
-      "concat_swap",
-      "inverted_condition",
-      "missing_enable",
-      "missing_reset",
-      "off_by_one_counter",
-      "operator_typo",
-      "state_transition",
-      "unconnected_port",
-      "width_bit_cutoff",
-      "wrong_bitwidth"
-    ],
-    "accomdemy_accomdemy_rv32i": [
-      "blocking_nonblocking",
-      "case_swap",
-      "concat_swap",
-      "delayed_signal",
-      "inverted_condition",
-      "missing_else_latch",
-      "missing_enable",
-      "missing_reset",
-      "off_by_one_counter",
-      "operator_typo",
-      "signal_typo",
-      "state_transition",
-      "unconnected_port",
-      "width_bit_cutoff",
-      "wrong_bitwidth"
-    ],
-    "chili-chips-ba_wireguard-fpga": [
-      "blocking_nonblocking",
-      "inverted_condition",
-      "missing_else_latch",
-      "missing_reset",
-      "operator_typo",
-      "signal_typo",
-      "unconnected_port",
-      "wrong_bitwidth"
-    ],
-    "roo16kie_MAC_Verilog": [
-      "case_swap",
-      "concat_swap",
+    },
+    "Mr-Bossman_KISC-V/AXI4Lite_translator__axi/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__ALU/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Data_Memory/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Instruction_Memory/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Register_File/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/missing_reset": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/off_by_one_counter": {
+      "status": "waveform_identical"
+    },
+    "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/operator_typo": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/state_transition": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit_tb/unconnected_port": {
+      "status": "sim_failed"
+    },
+    "WilliamZhang20_ECE298A-TPU/memory_tb__memory/missing_enable": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/memory_tb__memory/missing_reset": {
+      "status": "sim_failed"
+    },
+    "WilliamZhang20_ECE298A-TPU/memory_tb__memory/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/memory_tb__memory_tb/unconnected_port": {
+      "status": "sim_failed"
+    },
+    "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/case_swap": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/missing_enable": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/missing_reset": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/operator_typo": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder_tb/unconnected_port": {
+      "status": "sim_failed"
+    },
+    "WilliamZhang20_ECE298A-TPU/systolic_array_tb__PE/missing_reset": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/systolic_array_tb__PE/operator_typo": {
+      "status": "sim_ok"
+    },
+    "WilliamZhang20_ECE298A-TPU/systolic_array_tb__systolic_array_2x2/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "WilliamZhang20_ECE298A-TPU/systolic_array_tb__systolic_array_2x2/unconnected_port": {
+      "status": "sim_failed"
+    },
+    "WilliamZhang20_ECE298A-TPU/systolic_array_tb__systolic_array_tb/unconnected_port": {
+      "status": "sim_failed"
+    },
+    "WilliamZhang20_ECE298A-TPU/tb__tb/unconnected_port": {
+      "status": "waveform_identical"
+    },
+    "WilliamZhang20_ECE298A-TPU/tb__tpu/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "WilliamZhang20_ECE298A-TPU/tb__tpu/unconnected_port": {
+      "status": "waveform_identical"
+    },
+    "cocotb_cocotb-bus/array_buses__array_buses/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "cocotb_cocotb-bus/avalon_streaming__avalon_streaming/inverted_condition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/avalon_streaming__avalon_streaming/missing_enable": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/avalon_streaming__avalon_streaming/off_by_one_counter": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/avalon_streaming__avalon_streaming/operator_typo": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/avalon_streaming__avalon_streaming/wrong_bitwidth": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/burst_read_master__burst_read_master/inverted_condition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/burst_read_master__burst_read_master/missing_enable": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/burst_read_master__burst_read_master/operator_typo": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/burst_read_master__burst_read_master/unconnected_port": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/burst_read_master__burst_read_master/wrong_bitwidth": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/case_swap": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/concat_swap": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/inverted_condition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/missing_enable": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/operator_typo": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/wrong_bitwidth": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/mean__mean/inverted_condition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/mean__mean/missing_enable": {
+      "status": "sim_ok"
+    },
+    "cocotb_cocotb-bus/mean__mean/missing_reset": {
+      "status": "sim_ok"
+    },
+    "cocotb_cocotb-bus/mean__mean/operator_typo": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/mean__mean/wrong_bitwidth": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__arbiter/inverted_condition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__arbiter/missing_enable": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__arbiter/missing_reset": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__arbiter/operator_typo": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__arbiter/unconnected_port": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__arbiter/wrong_bitwidth": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_interconnect/inverted_condition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_interconnect/missing_enable": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_interconnect/missing_reset": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_interconnect/operator_typo": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_interconnect/state_transition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_interconnect/unconnected_port": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_interconnect/wrong_bitwidth": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_ram/inverted_condition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_ram/missing_enable": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_ram/missing_reset": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_ram/off_by_one_counter": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_ram/operator_typo": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_ram/state_transition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_ram/wrong_bitwidth": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_register/unconnected_port": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_register_rd/inverted_condition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_register_rd/missing_enable": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_register_rd/missing_reset": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_register_rd/operator_typo": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_register_rd/wrong_bitwidth": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_register_wr/inverted_condition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_register_wr/missing_enable": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_register_wr/missing_reset": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_register_wr/operator_typo": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__axi_register_wr/wrong_bitwidth": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__priority_encoder/concat_swap": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__priority_encoder/inverted_condition": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__priority_encoder/operator_typo": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__top/operator_typo": {
+      "status": "sim_failed"
+    },
+    "cocotb_cocotb-bus/top__top/unconnected_port": {
+      "status": "sim_failed"
+    },
+    "mciepluc_cocotb-coverage/fifo_mem__fifo/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "mciepluc_cocotb-coverage/fifo_mem__fifo/missing_enable": {
+      "status": "sim_ok"
+    },
+    "mciepluc_cocotb-coverage/fifo_mem__fifo/missing_reset": {
+      "status": "sim_ok"
+    },
+    "mciepluc_cocotb-coverage/fifo_mem__fifo/operator_typo": {
+      "status": "sim_ok"
+    },
+    "mciepluc_cocotb-coverage/fifo_mem__fifo/wrong_bitwidth": {
+      "status": "sim_failed"
+    },
+    "mciepluc_cocotb-coverage/pkt_switch__pkt_switch/inverted_condition": {
+      "status": "sim_failed"
+    },
+    "mciepluc_cocotb-coverage/pkt_switch__pkt_switch/missing_enable": {
+      "status": "sim_ok"
+    },
+    "mciepluc_cocotb-coverage/pkt_switch__pkt_switch/missing_reset": {
+      "status": "sim_ok"
+    },
+    "mciepluc_cocotb-coverage/pkt_switch__pkt_switch/operator_typo": {
+      "status": "sim_failed"
+    },
+    "mciepluc_cocotb-coverage/pkt_switch__pkt_switch/wrong_bitwidth": {
+      "status": "sim_failed"
+    },
+    "semify-eda_go.debug/ste_shift_reg__ste_shift_reg/concat_swap": {
+      "status": "compile_error"
+    },
+    "semify-eda_go.debug/ste_shift_reg__ste_shift_reg/inverted_condition": {
+      "status": "compile_error"
+    },
+    "semify-eda_go.debug/ste_shift_reg__ste_shift_reg/missing_enable": {
+      "status": "compile_error"
+    },
+    "semify-eda_go.debug/ste_shift_reg__ste_shift_reg/missing_reset": {
+      "status": "compile_error"
+    },
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+    "snbk001_100DaysofRTL/seqmultiplier__seqmultiplier/missing_enable": {
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+    "snbk001_100DaysofRTL/sipo__sipo/missing_reset": {
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+    "snbk001_100DaysofRTL/tff__jkff/operator_typo": {
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+    "snbk001_100DaysofRTL/updowncntr__updowncntr/missing_reset": {
+      "status": "sim_ok"
+    },
+    "snbk001_100DaysofRTL/updowncntr__updowncntr/operator_typo": {
+      "status": "sim_ok"
+    },
+    "sumukhathrey_Verilog_ASIC_Design/RegisterFile__RegisterFile/missing_enable": {
+      "status": "sim_ok"
+    },
+    "sumukhathrey_Verilog_ASIC_Design/RegisterFile__RegisterFile/missing_reset": {
+      "status": "sim_ok"
+    },
+    "sumukhathrey_Verilog_ASIC_Design/RegisterFile__RegisterFile/operator_typo": {
+      "status": "sim_ok"
+    },
+    "sumukhathrey_Verilog_ASIC_Design/RegisterFile__RegisterFile/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "ultraembedded_biriscv/riscv_core__biriscv_alu/case_swap": {
+      "status": "timeout"
+    },
+    "ultraembedded_biriscv/riscv_core__biriscv_csr_regfile/case_swap": {
+      "status": "timeout"
+    },
+    "ultraembedded_biriscv/riscv_core__biriscv_lsu/case_swap": {
+      "status": "timeout"
+    },
+    "ultraembedded_biriscv/riscv_core__biriscv_regfile/case_swap": {
+      "status": "timeout"
+    }
+  },
+  "bug_types_attempted": {
+    "zhangxin6_iverilog_testbench": [
+      "blocking_nonblocking",
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "snbk001_100DaysofRTL": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "aditeyabaral_DDCO-Lab-UE18CS207": [
+      "case_swap",
+      "concat_swap",
       "inverted_condition",
       "missing_enable",
       "missing_reset",
@@ -3966,7 +4454,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "0thbit_CRC_parallel": [
+    "cocotb_cocotb-bus": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -3979,27 +4467,20 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "phoeniX-Digital-Design_phoeniX": [
-      "blocking_nonblocking"
-    ],
-    "Fraunhofer-IMS_airisc_core_complex": [
-      "blocking_nonblocking",
+    "projf_isle": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "nimanaqavi_Verilog-MathFunctions": [
+    "apfaudio_eurorack-pmod": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4016,20 +4497,24 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Vaibhav-Gunthe_Verilog-Projects": [
+    "Mr-Bossman_KISC-V": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3": [
+    "semify-eda_go.debug": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4042,20 +4527,24 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM": [
+    "shahsaumya00_Floating-Point-Adder": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "JN513_Risco-5": [
+    "meiniKi_RV32I_SC_Logisim": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4072,7 +4561,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "OrsuVenkataKrishnaiah1235_RTL-Coding": [
+    "MohamedHussein27_SPI_Slave_With_Single_Port_Memory": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4102,24 +4591,52 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "apfaudio_eurorack-pmod": [
-      "blocking_nonblocking",
+    "saivittalb_simd-processor-verification": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable"
+    ],
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "mnmhdanas_UART-protocol": [
+    "qossayrida_PipelineProcessorDesign": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "WilliamZhang20_ECE298A-TPU": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "selimsandal_OneShotNPU": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4136,7 +4653,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "selimsandal_OneShotNPU": [
+    "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4153,7 +4670,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules": [
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4166,18 +4683,18 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "alexforencich_verilog-axi": [
-      "case_swap",
-      "concat_swap"
-    ],
-    "Crimsonninja_senior_design_puf": [
+    "meiniKi_FazyRV": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
@@ -4196,24 +4713,20 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "ttchisholm_10g-low-latency-ethernet": [
-      "blocking_nonblocking",
+    "0thbit_CRC_parallel": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "qossayrida_PipelineProcessorDesign": [
+    "Vaibhav-Gunthe_Verilog-Projects": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4226,7 +4739,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Weiyet_RTLStructLib": [
+    "CharanK-glitch_RV32I": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4239,7 +4752,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "MohamedHussein27_AMPA_APB4_Protocol": [
+    "scarv_xcrypto": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4256,7 +4769,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "MohamedHussein27_SPI_Slave_With_Single_Port_Memory": [
+    "nimanaqavi_Verilog-MathFunctions": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4273,24 +4786,46 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "meiniKi_FazyRV": [
-      "blocking_nonblocking",
+    "dpretet_async_fifo": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Mr-Bossman_KISC-V": [
+    "roo16kie_MAC_Verilog": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "yaseensalah_Digital-Design-of-FIR-Filter": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "JN513_Risco-5": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4307,7 +4842,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "erihsu_INT_FP_MAC": [
+    "ayushc13_32-bit-RISC-processor-using-HDL-Verilog": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4317,10 +4852,9 @@
       "operator_typo",
       "state_transition",
       "unconnected_port",
-      "width_bit_cutoff",
-      "wrong_bitwidth"
+      "width_bit_cutoff"
     ],
-    "biren15_Design-and-Verification-of-LDPC-Decoder": [
+    "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4333,7 +4867,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "defano_digital-design": [
+    "mnmhdanas_Router-1-x-3-": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4350,24 +4884,30 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "lucky-wfw_IC_System_Design": [
+    "chili-chips-ba_wireguard-fpga": [
       "blocking_nonblocking",
+      "inverted_condition",
+      "missing_else_latch",
+      "missing_reset",
+      "operator_typo",
+      "signal_typo",
+      "unconnected_port",
+      "wrong_bitwidth"
+    ],
+    "biren15_Design-and-Verification-of-LDPC-Decoder": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core": [
+    "accomdemy_accomdemy_rv32i": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4384,7 +4924,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "dpretet_async_fifo": [
+    "erihsu_INT_FP_MAC": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4397,24 +4937,33 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "thejefflarson_little-cpu": [
-      "blocking_nonblocking",
+    "Weiyet_RTLStructLib": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "shahsaumya00_Floating-Point-Adder": [
+    "arhamhashmi01_Axi4-lite": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "defano_digital-design": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4431,7 +4980,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "mnmhdanas_Router-1-x-3-": [
+    "MohamedHussein27_AMPA_APB4_Protocol": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4448,7 +4997,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "scarv_xcrypto": [
+    "lucky-wfw_IC_System_Design": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4465,7 +5014,10 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "aditeyabaral_DDCO-Lab-UE18CS207": [
+    "phoeniX-Digital-Design_phoeniX": [
+      "blocking_nonblocking"
+    ],
+    "mciepluc_cocotb-coverage": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4478,7 +5030,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "meiniKi_RV32I_SC_Logisim": [
+    "mnmhdanas_UART-protocol": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -4495,81 +5047,84 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "zhangxin6_iverilog_testbench": [
+    "fcayci_sv-digital-design": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "fcayci_sv-digital-design": [
-      "blocking_nonblocking",
+    "Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "akira2963753_Pipelined-RV32-SoC": [
-      "blocking_nonblocking",
+    "Crimsonninja_senior_design_puf": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "arhamhashmi01_Axi4-lite": [
+    "ttchisholm_10g-low-latency-ethernet": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "MohamedHussein27_RISC-V-Single-Cycle-Implementation": [
+    "akira2963753_Pipelined-RV32-SoC": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "yaseensalah_Digital-Design-of-FIR-Filter": [
+    "sumukhathrey_Verilog_ASIC_Design": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4582,20 +5137,24 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog": [
+    "thejefflarson_little-cpu": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "CharanK-glitch_RV32I": [
+    "MohamedHussein27_RISC-V-Single-Cycle-Implementation": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -4617,23 +5176,43 @@
       "off_by_one_counter",
       "operator_typo"
     ],
-    "ayushc13_32-bit-RISC-processor-using-HDL-Verilog": [
+    "OrsuVenkataKrishnaiah1235_RTL-Coding": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
+      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
+      "signal_typo",
       "state_transition",
       "unconnected_port",
-      "width_bit_cutoff"
+      "width_bit_cutoff",
+      "wrong_bitwidth"
     ],
-    "saivittalb_simd-processor-verification": [
+    "alexforencich_verilog-axi": [
+      "case_swap",
+      "concat_swap"
+    ],
+    "Fraunhofer-IMS_airisc_core_complex": [
+      "blocking_nonblocking",
       "case_swap",
       "concat_swap",
+      "delayed_signal",
       "inverted_condition",
-      "missing_enable"
+      "missing_else_latch",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "signal_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
     ]
   }
 }

manifest.json

@@ -147,112 +147,7 @@
     "repo": "JN513/Risco-5",
     "clone_url": "https://github.com/JN513/Risco-5.git",
     "commit_sha": "12a570c7124f5f78f2c9513248f8e6bd85137068",
-    "testbenches": [
-      {
-        "file_path": "tests/core_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Core",
-        "rtl_files": [
-          "src/core/core.v",
-          "src/core/pc.v",
-          "src/core/mux.v",
-          "src/core/registers.v",
-          "src/core/control_unit.v",
-          "src/core/alu_control.v",
-          "src/core/alu.v",
-          "src/core/immediate_generator.v",
-          "src/core/csr_unit.v",
-          "src/core/mdu.v",
-          "src/peripheral/memory.v",
-          "src/peripheral/bus.v",
-          "src/peripheral/leds.v"
-        ]
-      },
-      {
-        "file_path": "tests/registers_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Registers",
-        "rtl_files": [
-          "src/core/registers.v"
-        ]
-      },
-      {
-        "file_path": "tests/soc_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Risco_5_SOC",
-        "rtl_files": [
-          "src/peripheral/soc.v",
-          "src/core/core.v",
-          "src/core/pc.v",
-          "src/core/mux.v",
-          "src/core/registers.v",
-          "src/core/control_unit.v",
-          "src/core/alu_control.v",
-          "src/core/alu.v",
-          "src/core/immediate_generator.v",
-          "src/core/csr_unit.v",
-          "src/core/mdu.v",
-          "src/peripheral/memory.v",
-          "src/peripheral/bus.v",
-          "src/peripheral/leds.v",
-          "src/peripheral/uart.v",
-          "src/peripheral/uart_rx.v",
-          "src/peripheral/uart_tx.v",
-          "src/peripheral/fifo.v",
-          "src/peripheral/gpios.v",
-          "src/peripheral/gpio.v",
-          "src/peripheral/pwm.v"
-        ]
-      },
-      {
-        "file_path": "tests/gpio_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "GPIOS",
-        "rtl_files": [
-          "src/peripheral/gpios.v",
-          "src/peripheral/gpio.v",
-          "src/peripheral/pwm.v"
-        ]
-      },
-      {
-        "file_path": "tests/pc_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "PC",
-        "rtl_files": [
-          "src/core/pc.v"
-        ]
-      },
-      {
-        "file_path": "tests/clk_divider.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "ClkDivider",
-        "rtl_files": [
-          "debug/clk_divider.v"
-        ]
-      },
-      {
-        "file_path": "tests/reset_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "ResetBootSystem",
-        "rtl_files": [
-          "debug/reset.v"
-        ]
-      }
-    ]
+    "testbenches": []
   },
   "Mr-Bossman_KISC-V": {
     "repo": "Mr-Bossman/KISC-V",
@@ -268,28 +163,6 @@
         "rtl_files": [
           "hdl/axi.v"
         ]
-      },
-      {
-        "file_path": "hdl/soc_top_iverilog.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": "Makefile",
-        "top_module": "soc_top",
-        "rtl_files": [
-          "hdl/sram.v",
-          "hdl/apb_align.v",
-          "hdl/cpu.v",
-          "hdl/alu.v",
-          "hdl/APB.v",
-          "hdl/uart.v",
-          "hdl/intctrl.v",
-          "hdl/timer.v",
-          "hdl/control_unit.v",
-          "hdl/datapath.v",
-          "hdl/regfile.v",
-          "hdl/programcounter.v",
-          "hdl/sys.v"
-        ]
       }
     ]
   },
@@ -331,133 +204,13 @@
     "repo": "accomdemy/accomdemy_rv32i",
     "clone_url": "https://github.com/accomdemy/accomdemy_rv32i.git",
     "commit_sha": "4f75b555a0e0419e2417294f85df202ba0415e4b",
-    "testbenches": [
-      {
-        "file_path": "sim/cpu_tb.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "cpu",
-        "rtl_files": [
-          "src/cpu.v",
-          "src/alu.v",
-          "src/branch.v",
-          "src/decoder.v",
-          "src/dm_control.v",
-          "src/instr_memory.v",
-          "src/MUX2to1_32bit.v",
-          "src/MUX4to1_32bit.v",
-          "src/pc.v",
-          "src/regfile.v"
-        ]
-      }
-    ]
+    "testbenches": []
   },
   "akira2963753_Pipelined-RV32-SoC": {
     "repo": "akira2963753/Pipelined-RV32-SoC",
     "clone_url": "https://github.com/akira2963753/Pipelined-RV32-SoC.git",
     "commit_sha": "ded74adc6a29ef5bbdac56a5eac5b99328064371",
-    "testbenches": [
-      {
-        "file_path": "source/Five-Stage-Pipelined-CPU/RTL/RISCV_CPU_tb.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "RISCV_CPU",
-        "rtl_files": [
-          "source/Five-Stage-Pipelined-CPU/RTL/ALU.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/ALU_Control.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/BHT.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/BPU.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/BTB.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/CSR.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/Control.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/D_Mem.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/EX_MEM.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/Forwarding_Unit.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/Hazard_Unit.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/ID_EX.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/IF_ID.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/I_Mem.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/ImmGen.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/LDU.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/MEM_WB.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/PC.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/PC_Adderr.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/RF.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/RISCV_CPU.v"
-        ]
-      },
-      {
-        "file_path": "source/RISC-V-Processor/RTL/RISCV_PROCESSOR_tb.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "RISCV_PROCESSOR",
-        "rtl_files": [
-          "source/RISC-V-Processor/RTL/ALU.v",
-          "source/RISC-V-Processor/RTL/ALU_Control.v",
-          "source/RISC-V-Processor/RTL/AXI4_Lite_Bus.v",
-          "source/RISC-V-Processor/RTL/BHT.v",
-          "source/RISC-V-Processor/RTL/BPU.v",
-          "source/RISC-V-Processor/RTL/BTB.v",
-          "source/RISC-V-Processor/RTL/CSR.v",
-          "source/RISC-V-Processor/RTL/Control.v",
-          "source/RISC-V-Processor/RTL/D_BRAM.v",
-          "source/RISC-V-Processor/RTL/D_Cache.v",
-          "source/RISC-V-Processor/RTL/D_Mem.v",
-          "source/RISC-V-Processor/RTL/EX_MEM.v",
-          "source/RISC-V-Processor/RTL/Forwarding_Unit.v",
-          "source/RISC-V-Processor/RTL/Hazard_Unit.v",
-          "source/RISC-V-Processor/RTL/ID_EX.v",
-          "source/RISC-V-Processor/RTL/IF_ID.v",
-          "source/RISC-V-Processor/RTL/I_Cache.v",
-          "source/RISC-V-Processor/RTL/ImmGen.v",
-          "source/RISC-V-Processor/RTL/LDU.v",
-          "source/RISC-V-Processor/RTL/MEM_WB.v",
-          "source/RISC-V-Processor/RTL/PC.v",
-          "source/RISC-V-Processor/RTL/PC_Adder.v",
-          "source/RISC-V-Processor/RTL/RF.v",
-          "source/RISC-V-Processor/RTL/RISCV_CPU.v",
-          "source/RISC-V-Processor/RTL/RISCV_PROCESSOR.v"
-        ]
-      },
-      {
-        "file_path": "source/CACHE/AXI4-LITE/Pattern.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Tested",
-        "rtl_files": [
-          "source/CACHE/AXI4-LITE/Tested.v",
-          "source/CACHE/AXI4-LITE/AXI4_Lite_Bus.v"
-        ]
-      },
-      {
-        "file_path": "source/CACHE/I-CACHE/Pattern.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Tested",
-        "rtl_files": [
-          "source/CACHE/I-CACHE/Tested.v",
-          "source/CACHE/I-CACHE/Cache.v",
-          "source/CACHE/I-CACHE/AXI4_Lite_Bus.v"
-        ]
-      },
-      {
-        "file_path": "source/CACHE/D-CACHE/Pattern.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Tested",
-        "rtl_files": [
-          "source/CACHE/D-CACHE/Tested.v",
-          "source/CACHE/D-CACHE/D_Cache.v",
-          "source/CACHE/D-CACHE/AXI4_Lite_Bus.v"
-        ]
-      }
-    ]
+    "testbenches": []
   },
   "thejefflarson_little-cpu": {
     "repo": "thejefflarson/little-cpu",
@@ -1230,5 +983,644 @@
         ]
       }
     ]
+  },
+  "WilliamZhang20_ECE298A-TPU": {
+    "repo": "WilliamZhang20/ECE298A-TPU",
+    "clone_url": "https://github.com/WilliamZhang20/ECE298A-TPU.git",
+    "commit_sha": "24d9cb1fb86b8f0f9d800fcbb5fd3dfa49638400",
+    "testbenches": [
+      {
+        "file_path": "test/control_unit/test_control_unit.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "test/Makefile",
+        "top_module": "control_unit_tb",
+        "rtl_files": [
+          "test/control_unit/control_unit_tb.v",
+          "src/control_unit.v"
+        ]
+      },
+      {
+        "file_path": "test/memory/test_memory.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "test/Makefile",
+        "top_module": "memory_tb",
+        "rtl_files": [
+          "test/memory/memory_tb.v",
+          "src/memory.v"
+        ]
+      },
+      {
+        "file_path": "test/mmu_feeder/test_mmu_feeder.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "test/Makefile",
+        "top_module": "mmu_feeder_tb",
+        "rtl_files": [
+          "test/mmu_feeder/mmu_feeder_tb.v",
+          "src/mmu_feeder.v"
+        ]
+      },
+      {
+        "file_path": "test/systolic_array/test_systolic_array.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "test/Makefile",
+        "top_module": "systolic_array_tb",
+        "rtl_files": [
+          "test/systolic_array/systolic_array_tb.v",
+          "src/systolic_array_2x2.v",
+          "src/PE.v"
+        ]
+      },
+      {
+        "file_path": "test/tpu/test_tpu.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "test/Makefile",
+        "top_module": "tb",
+        "rtl_files": [
+          "test/tpu/tb.v",
+          "src/tpu.v",
+          "src/delay_cell.v",
+          "src/systolic_array_2x2.v",
+          "src/PE.v",
+          "src/mmu_feeder.v",
+          "src/control_unit.v",
+          "src/memory.v"
+        ]
+      },
+      {
+        "file_path": "test/tpu/train_qat_model.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "test/Makefile",
+        "top_module": "tb",
+        "rtl_files": [
+          "test/tpu/tb.v",
+          "src/tpu.v",
+          "src/delay_cell.v",
+          "src/systolic_array_2x2.v",
+          "src/PE.v",
+          "src/mmu_feeder.v",
+          "src/control_unit.v",
+          "src/memory.v"
+        ]
+      },
+      {
+        "file_path": "test/uvm_test/test_uvm.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "test/Makefile",
+        "top_module": "tb",
+        "rtl_files": [
+          "test/uvm_test/tb.v",
+          "src/tpu.v",
+          "src/delay_cell.v",
+          "src/systolic_array_2x2.v",
+          "src/PE.v",
+          "src/mmu_feeder.v",
+          "src/control_unit.v",
+          "src/memory.v"
+        ]
+      }
+    ]
+  },
+  "cocotb_cocotb-bus": {
+    "repo": "cocotb/cocotb-bus",
+    "clone_url": "https://github.com/cocotb/cocotb-bus.git",
+    "commit_sha": "3c1018f86c842b8873b4d8635d8a67bb8807f62e",
+    "testbenches": [
+      {
+        "file_path": "examples/axi_lite_slave/tests/test_axi_lite_slave.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "examples/axi_lite_slave/tests/Makefile",
+        "top_module": "tb_axi_lite_slave",
+        "rtl_files": [
+          "examples/axi_lite_slave/hdl/axi_lite_slave.v",
+          "examples/axi_lite_slave/hdl/axi_lite_demo.v",
+          "examples/axi_lite_slave/hdl/tb_axi_lite_slave.v"
+        ]
+      },
+      {
+        "file_path": "examples/dff/tests/dff_cocotb.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "examples/dff/tests/Makefile",
+        "top_module": "dff",
+        "rtl_files": [
+          "examples/dff/hdl/dff.v"
+        ]
+      },
+      {
+        "file_path": "examples/endian_swapper/tests/test_endian_swapper.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "examples/endian_swapper/tests/Makefile",
+        "top_module": "endian_swapper_sv",
+        "rtl_files": [
+          "examples/endian_swapper/hdl/endian_swapper.sv"
+        ]
+      },
+      {
+        "file_path": "examples/endian_swapper/hal_tests/test_endian_swapper_hal.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "examples/endian_swapper/hal_tests/Makefile",
+        "top_module": "endian_swapper_sv",
+        "rtl_files": [
+          "examples/endian_swapper/hdl/endian_swapper.sv"
+        ]
+      },
+      {
+        "file_path": "examples/mean/tests/test_mean.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "examples/mean/tests/Makefile",
+        "top_module": "mean",
+        "rtl_files": [
+          "examples/mean/hdl/mean.sv"
+        ]
+      },
+      {
+        "file_path": "tests/test_cases/test_array_buses/test_array_buses.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "tests/test_cases/test_array_buses/Makefile",
+        "top_module": "array_buses",
+        "rtl_files": [
+          "tests/test_cases/test_array_buses/array_buses.sv"
+        ]
+      },
+      {
+        "file_path": "tests/test_cases/test_avalon/test_avalon.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "tests/test_cases/test_avalon/Makefile",
+        "top_module": "burst_read_master",
+        "rtl_files": [
+          "tests/designs/avalon_module/burst_read_master.v"
+        ]
+      },
+      {
+        "file_path": "tests/test_cases/test_avalon_interface/test_avalon_interface.py",
+        "tb_type": "cocotb",
+        "simulator": "verilator",
+        "makefile_path": "tests/test_cases/test_avalon_interface/Makefile",
+        "top_module": "avl_feedback",
+        "rtl_files": [
+          "tests/designs/avalon_interface_module/avl_mm_mini_if.sv",
+          "tests/designs/avalon_interface_module/avl_st_mini_if.sv",
+          "tests/designs/avalon_interface_module/st_feedback.sv",
+          "tests/designs/avalon_interface_module/mm_reader.sv",
+          "tests/designs/avalon_interface_module/avl_feedback.sv"
+        ]
+      },
+      {
+        "file_path": "tests/test_cases/test_avalon_stream/test_avalon_stream.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "tests/test_cases/test_avalon_stream/Makefile",
+        "top_module": "avalon_streaming",
+        "rtl_files": [
+          "tests/designs/avalon_streaming_module/avalon_streaming.sv"
+        ]
+      },
+      {
+        "file_path": "tests/test_cases/test_axi4/test_axi4.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "tests/test_cases/test_axi4/Makefile",
+        "top_module": "top",
+        "rtl_files": [
+          "tests/designs/axi4_ram/axi_register_rd.v",
+          "tests/designs/axi4_ram/axi_register_wr.v",
+          "tests/designs/axi4_ram/axi_register.v",
+          "tests/designs/axi4_ram/priority_encoder.v",
+          "tests/designs/axi4_ram/arbiter.v",
+          "tests/designs/axi4_ram/axi_interconnect.v",
+          "tests/designs/axi4_ram/axi_ram.v",
+          "tests/designs/axi4_ram/top.v"
+        ]
+      },
+      {
+        "file_path": "tests/test_cases/test_case_insensitive/case_insensitive.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "tests/test_cases/test_case_insensitive/Makefile",
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+          "tests/test_cases/test_case_insensitive/case_insensitive.v"
+        ]
+      },
+      {
+        "file_path": "tests/test_cases/test_cocotb_bus/test_ci.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "tests/test_cases/test_cocotb_bus/Makefile",
+        "top_module": "top",
+        "rtl_files": [
+          "tests/designs/axi4_ram/axi_register_rd.v",
+          "tests/designs/axi4_ram/axi_register_wr.v",
+          "tests/designs/axi4_ram/axi_register.v",
+          "tests/designs/axi4_ram/priority_encoder.v",
+          "tests/designs/axi4_ram/arbiter.v",
+          "tests/designs/axi4_ram/axi_interconnect.v",
+          "tests/designs/axi4_ram/axi_ram.v",
+          "tests/designs/axi4_ram/top.v"
+        ]
+      }
+    ]
+  },
+  "mciepluc_cocotb-coverage": {
+    "repo": "mciepluc/cocotb-coverage",
+    "clone_url": "https://github.com/mciepluc/cocotb-coverage.git",
+    "commit_sha": "201c6e19761528eb9c03f876666c485027abb7fb",
+    "testbenches": [
+      {
+        "file_path": "examples/fifo/tests/test_fifo.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "examples/fifo/tests/Makefile",
+        "top_module": "fifo_mem",
+        "rtl_files": [
+          "examples/fifo/hdl/fifo.v"
+        ]
+      },
+      {
+        "file_path": "examples/pkt_switch/tests/test_pkt_switch.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "examples/pkt_switch/tests/Makefile",
+        "top_module": "pkt_switch",
+        "rtl_files": [
+          "examples/pkt_switch/hdl/pkt_switch.v"
+        ]
+      },
+      {
+        "file_path": "tests/test_coverage/coverage_test_main.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "tests/test_coverage/Makefile",
+        "top_module": "sample_module",
+        "rtl_files": [
+          "tests/sample_module.sv"
+        ]
+      },
+      {
+        "file_path": "tests/test_crv/crv_test_main.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "tests/test_crv/Makefile",
+        "top_module": "sample_module",
+        "rtl_files": [
+          "tests/sample_module.sv"
+        ]
+      }
+    ]
+  },
+  "semify-eda_go.debug": {
+    "repo": "semify-eda/go.debug",
+    "clone_url": "https://github.com/semify-eda/go.debug.git",
+    "commit_sha": "b04c7779e50881ad4ea1832b34d82a0b897fba2f",
+    "testbenches": [
+      {
+        "file_path": "example/division/testbench/test_div_int.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "example/division/sim.cocotb/Makefile",
+        "top_module": "top",
+        "rtl_files": [
+          "example/division/rtl/div_int.sv",
+          "example/division/testbench/top.cocotb.sv"
+        ]
+      },
+      {
+        "file_path": "example/sqrt/testbench/test_sqrt_int.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "example/sqrt/sim.cocotb/Makefile",
+        "top_module": "top",
+        "rtl_files": [
+          "example/sqrt/rtl/sqrt.sv",
+          "example/sqrt/testbench/top.cocotb.sv"
+        ]
+      },
+      {
+        "file_path": "example/sine/testbench/wfg_stim_sine_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": "example/sine/sim.icarus/Makefile",
+        "top_module": "wfg_stim_sine",
+        "rtl_files": [
+          "example/sine/rtl/wfg_stim_sine.sv"
+        ]
+      },
+      {
+        "file_path": "example/shiftreg/testbench/top_system.icarus.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": "example/shiftreg/sim.icarus/Makefile",
+        "top_module": "ste_shift_reg",
+        "rtl_files": [
+          "example/shiftreg/rtl/ste_shift_reg.sv"
+        ]
+      }
+    ]
+  },
+  "snbk001_100DaysofRTL": {
+    "repo": "snbk001/100DaysofRTL",
+    "clone_url": "https://github.com/snbk001/100DaysofRTL.git",
+    "commit_sha": "3cc8e302d836b2d8527cb2550342b9fbfe2e6464",
+    "testbenches": [
+      {
+        "file_path": "day5/dff_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "dff",
+        "rtl_files": [
+          "day5/dff.sv"
+        ]
+      },
+      {
+        "file_path": "day6/counter8bit_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "counter8bit",
+        "rtl_files": [
+          "day6/counter8bit.sv"
+        ]
+      },
+      {
+        "file_path": "day8/lfsr_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "lfsr",
+        "rtl_files": [
+          "day8/lfsr.sv"
+        ]
+      },
+      {
+        "file_path": "day9/custcounter_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "custcounter",
+        "rtl_files": [
+          "day9/custcounter.sv"
+        ]
+      },
+      {
+        "file_path": "day10/muxcond_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "muxcond",
+        "rtl_files": [
+          "day10/muxcond.sv"
+        ]
+      },
+      {
+        "file_path": "day11/jkff_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "jkff",
+        "rtl_files": [
+          "day11/jkff.sv"
+        ]
+      },
+      {
+        "file_path": "day12/tff_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "tff",
+        "rtl_files": [
+          "day12/tff.sv",
+          "day12/jkff.sv"
+        ]
+      },
+      {
+        "file_path": "day13/pedge_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "pedge",
+        "rtl_files": [
+          "day13/pedge.sv"
+        ]
+      },
+      {
+        "file_path": "day17/free_run_countr_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "free_run_countr",
+        "rtl_files": [
+          "day17/free_run_countr.sv"
+        ]
+      },
+      {
+        "file_path": "day18/modmcountr_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "modmcountr",
+        "rtl_files": [
+          "day18/modmcountr.sv"
+        ]
+      },
+      {
+        "file_path": "day19/edgedet_moore_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "edgedet_moore",
+        "rtl_files": [
+          "day19/edgedet_moore.sv"
+        ]
+      },
+      {
+        "file_path": "day20/edgedet_mealy_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "edgedet_mealy",
+        "rtl_files": [
+          "day20/edgedet_mealy.sv"
+        ]
+      },
+      {
+        "file_path": "day22/dualedge_det_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "dualedge_det",
+        "rtl_files": [
+          "day22/dualedge_det.sv"
+        ]
+      },
+      {
+        "file_path": "day24/seqdet_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "seqdet",
+        "rtl_files": [
+          "day24/seqdet.sv"
+        ]
+      },
+      {
+        "file_path": "day25/seqdet_ol_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "seqdet_ol",
+        "rtl_files": [
+          "day25/seqdet_ol.sv"
+        ]
+      },
+      {
+        "file_path": "day26/seqdetmoore_nol_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "seqdetmoore_nol",
+        "rtl_files": [
+          "day26/seqdetmoore_nol.sv"
+        ]
+      },
+      {
+        "file_path": "day27/seqdetmoore_ol_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "seqdetmoore_ol",
+        "rtl_files": [
+          "day27/seqdetmoore_ol.sv"
+        ]
+      },
+      {
+        "file_path": "day29/seqmultiplier_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "seqmultiplier",
+        "rtl_files": [
+          "day29/seqmultiplier.sv"
+        ]
+      },
+      {
+        "file_path": "day30/singleport_ram_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "singleport_ram",
+        "rtl_files": [
+          "day30/singleport_ram.sv"
+        ]
+      },
+      {
+        "file_path": "day31/updowncntr_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "updowncntr",
+        "rtl_files": [
+          "day31/updowncntr.sv"
+        ]
+      },
+      {
+        "file_path": "day32/pipo_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "pipo",
+        "rtl_files": [
+          "day32/pipo.sv"
+        ]
+      },
+      {
+        "file_path": "day33/piso_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "piso",
+        "rtl_files": [
+          "day33/piso.sv"
+        ]
+      },
+      {
+        "file_path": "day34/sipo_tb.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "sipo",
+        "rtl_files": [
+          "day34/sipo.sv"
+        ]
+      }
+    ]
+  },
+  "sumukhathrey_Verilog_ASIC_Design": {
+    "repo": "sumukhathrey/Verilog_ASIC_Design",
+    "clone_url": "https://github.com/sumukhathrey/Verilog_ASIC_Design.git",
+    "commit_sha": "77dff213c25c8d4228254d4eb3d9e0e349b2a420",
+    "testbenches": [
+      {
+        "file_path": "Register_File/RegisterFile_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "RegisterFile",
+        "rtl_files": [
+          "Register_File/RegisterFile.v"
+        ]
+      }
+    ]
+  },
+  "ultraembedded_biriscv": {
+    "repo": "ultraembedded/biriscv",
+    "clone_url": "https://github.com/ultraembedded/biriscv.git",
+    "commit_sha": "6af9c4be5a0807d368eaad5e49af52322e31d073",
+    "testbenches": [
+      {
+        "file_path": "tb/tb_core_icarus/tb_top.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": "tb/tb_core_icarus/makefile",
+        "top_module": "riscv_core",
+        "rtl_files": [
+          "src/core/biriscv_alu.v",
+          "src/core/biriscv_csr.v",
+          "src/core/biriscv_csr_regfile.v",
+          "src/core/biriscv_decode.v",
+          "src/core/biriscv_decoder.v",
+          "src/core/biriscv_defs.v",
+          "src/core/biriscv_divider.v",
+          "src/core/biriscv_exec.v",
+          "src/core/biriscv_fetch.v",
+          "src/core/biriscv_frontend.v",
+          "src/core/biriscv_issue.v",
+          "src/core/biriscv_lsu.v",
+          "src/core/biriscv_mmu.v",
+          "src/core/biriscv_multiplier.v",
+          "src/core/biriscv_npc.v",
+          "src/core/biriscv_pipe_ctrl.v",
+          "src/core/biriscv_regfile.v",
+          "src/core/biriscv_trace_sim.v",
+          "src/core/biriscv_xilinx_2r1w.v",
+          "src/core/riscv_core.v",
+          "tb/tb_core_icarus/tcm_mem.v",
+          "tb/tb_core_icarus/tcm_mem_ram.v"
+        ]
+      }
+    ]
   }
 }

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/inverted_condition/diff.patch

@@ -0,0 +1,17 @@
+--- a/examples/fifo/hdl/fifo.v
++++ b/examples/fifo/hdl/fifo.v
+@@ -75,7 +75,7 @@
+   always @(posedge clk or negedge rst_n)  
+   begin  
+   if(~rst_n) fifo_overflow <=0;  
+-  else if((overflow_set==1)&&(fifo_rd==0))  
++  else if((overflow_set==1)&&(fifo_rd==1))  
+    fifo_overflow <=1;  
+    else if(fifo_rd)  
+     fifo_overflow <=0;  
+@@ -110,4 +110,4 @@
+    else  
+     wptr <= wptr;  
+   end  
+- endmodule  
++ endmodule

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/inverted_condition/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "inverted_condition",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "examples/fifo/hdl/fifo.v"
+  ],
+  "bug_description": "Inverted 'fifo_rd==0' condition in overflow detection \u2014 fifo_overflow now sets when a read is active instead of when no read is occurring, masking overflow state during reads",
+  "signals_affected": [
+    "fifo_rd"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "During FIFO verification, we observed that the overflow detection is behaving inversely to the expected behavior. When testing scenarios where the FIFO should detect overflow conditions while reads are inactive (fifo_rd=0 at t=2500), the fifo_overflow flag does not assert as expected according to the FIFO specification. Conversely, the overflow signal appears to trigger incorrectly when read operations are active. This inconsistency suggests the overflow detection logic is inverted relative to the read signal activity, causing legitimate overflow conditions to be masked during periods when reads are not occurring. The issue becomes particularly apparent when the FIFO is being filled (around t=2100 with fifo_we activity ceasing) and overflow conditions should be detected, but the flag behavior does not align with the protocol requirements for overflow signaling.",
+  "diff_summary": "6 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/inverted_condition/sim_log.txt

@@ -0,0 +1,178 @@
+rm -f results.xml
+"make" -f Makefile results.xml
+make[1]: Entering directory '/tmp/sim4_simsh_rwlbuymr/source/examples/fifo/tests'
+mkdir -p sim_build
+/usr/bin/iverilog -o sim_build/sim.vvp -s fifo_mem -g2012 -f sim_build/cmds.f -s cocotb_iverilog_dump  /tmp/sim4_simsh_rwlbuymr/source/examples/fifo/tests/../hdl/fifo.v sim_build/cocotb_iverilog_dump.v
+rm -f results.xml
+COCOTB_TEST_MODULES=test_fifo COCOTB_TESTCASE= COCOTB_TEST_FILTER= COCOTB_TOPLEVEL=fifo_mem TOPLEVEL_LANG=verilog \
+         /usr/bin/vvp -M /mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb/libs -m libcocotbvpi_icarus   sim_build/sim.vvp -fst  
+     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:93   in _embed_init_python              Using Python 3.13.0rc1 interpreter at /mnt/d/ubc-capstone-26/data-pipeline/.venv/bin/python
+     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:79   in gpi_print_registered_impl       VPI registered
+     0.00ns INFO     cocotb                             Running on Icarus Verilog version 11.0 (stable)
+     0.00ns WARNING  gpi                                vpi_iterate returned NULL for type vpiInstance for object NULL
+     0.00ns INFO     cocotb                             Seeding Python random module with 1775587884
+     0.00ns INFO     cocotb                             Initialized cocotb v2.0.1 from /mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb
+     0.00ns INFO     cocotb                             Running tests
+     0.00ns INFO     cocotb.regression                  running test_fifo.fifo_test (1/1)
+                                                            FIFO Test 
+     2.20ns INFO     test                               Data NOT read, fifo EMPTY!
+     2.40ns INFO     test                               Data written to fifo: C1
+     2.60ns INFO     test                               Data written to fifo: E8
+     2.80ns INFO     test                               Data written to fifo: 37
+     3.00ns INFO     test                               Data written to fifo: 87
+     3.20ns INFO     test                               Data written to fifo: F6
+     3.40ns INFO     test                               Data read from fifo: C1
+     3.60ns INFO     test                               Data written to fifo: 75
+     3.80ns INFO     test                               Data read from fifo: E8
+     4.00ns INFO     test                               Data read from fifo: 37
+     4.20ns INFO     test                               Data read from fifo: 87
+     4.40ns INFO     test                               Data read from fifo: F6
+     4.60ns INFO     test                               Data read from fifo: 75
+     4.80ns INFO     test                               Data written to fifo: 66
+     5.00ns INFO     test                               Data read from fifo: 66
+     5.20ns INFO     test                               Data written to fifo: 29
+     5.40ns INFO     test                               Data read from fifo: 29
+     5.60ns INFO     test                               Data NOT read, fifo EMPTY!
+     5.80ns INFO     test                               Data written to fifo: 1B
+     6.00ns INFO     test                               Data written to fifo: 22
+     6.20ns INFO     test                               Data read from fifo: 1B
+     6.40ns INFO     test                               Data read from fifo: 22
+     6.60ns INFO     test                               Data NOT read, fifo EMPTY!
+     6.80ns INFO     test                               Data written to fifo: C7
+     7.00ns INFO     test                               Data read from fifo: C7
+     7.20ns INFO     test                               Data written to fifo: 77
+     7.40ns INFO     test                               Data written to fifo: CC
+     7.60ns INFO     test                               Data read from fifo: 77
+     7.80ns INFO     test                               Data read from fifo: CC
+     8.00ns INFO     test                               Data written to fifo: 4
+     8.20ns INFO     test                               Data read from fifo: 4
+     8.40ns INFO     test                               Data written to fifo: F8
+     8.60ns INFO     test                               Data read from fifo: F8
+     8.80ns INFO     test                               Data written to fifo: E7
+     9.00ns INFO     test                               Data written to fifo: 59
+     9.20ns INFO     test                               Data read from fifo: E7
+     9.40ns INFO     test                               Data read from fifo: 59
+     9.60ns INFO     test                               Data written to fifo: 3
+     9.80ns INFO     test                               Data read from fifo: 3
+    10.00ns INFO     test                               Data written to fifo: 27
+    10.20ns INFO     test                               Data read from fifo: 27
+    10.40ns INFO     test                               Data NOT read, fifo EMPTY!
+    10.60ns INFO     test                               Data NOT read, fifo EMPTY!
+    10.80ns INFO     test                               Data NOT read, fifo EMPTY!
+    11.00ns INFO     test                               Data NOT read, fifo EMPTY!
+    11.20ns INFO     test                               Data written to fifo: 65
+    11.40ns INFO     test                               Data written to fifo: 5D
+    11.60ns INFO     test                               Data read from fifo: 65
+    11.80ns INFO     test                               Data read from fifo: 5D
+    12.00ns INFO     test                               Data written to fifo: 82
+    12.20ns INFO     test                               Data written to fifo: 10
+    12.40ns INFO     test                               Data written to fifo: 56
+    12.60ns INFO     test                               Data written to fifo: 3E
+    12.80ns INFO     test                               Data written to fifo: 95
+    13.00ns INFO     test                               Data read from fifo: 82
+    13.20ns INFO     test                               Data written to fifo: 11
+    13.40ns INFO     test                               Data written to fifo: FD
+    13.60ns INFO     test                               Data read from fifo: 10
+    13.80ns INFO     test                               Data read from fifo: 56
+    14.00ns INFO     test                               Data written to fifo: E2
+    14.20ns INFO     test                               Data written to fifo: EA
+    14.40ns INFO     test                               Data written to fifo: 2A
+    14.60ns INFO     test                               Data read from fifo: 3E
+    14.80ns INFO     test                               Data read from fifo: 95
+    15.00ns INFO     test                               Data read from fifo: 11
+    15.20ns INFO     test                               Data read from fifo: FD
+    15.40ns INFO     test                               Data written to fifo: BB
+    15.60ns INFO     test                               Data written to fifo: F7
+    15.80ns INFO     test                               Data written to fifo: 76
+    16.00ns INFO     test                               Data written to fifo: 1D
+    16.20ns INFO     test                               Data read from fifo: E2
+    16.40ns INFO     test                               Data written to fifo: 1B
+    16.60ns INFO     test                               Data written to fifo: B
+    16.80ns INFO     test                               Data read from fifo: EA
+    17.00ns INFO     test                               Data read from fifo: 2A
+    17.20ns INFO     test                               Data read from fifo: BB
+    17.40ns INFO     test                               Data read from fifo: F7
+    17.60ns INFO     test                               Data read from fifo: 76
+    17.80ns INFO     test                               Data read from fifo: 1D
+    18.00ns INFO     test                               Data written to fifo: D4
+    18.20ns INFO     test                               Data read from fifo: 1B
+    18.40ns INFO     test                               Data written to fifo: 2E
+    18.60ns INFO     test                               Data read from fifo: B
+    18.80ns INFO     test                               Data written to fifo: AF
+    19.00ns INFO     test                               Data written to fifo: EC
+    19.20ns INFO     test                               Data read from fifo: D4
+    19.40ns INFO     test                               Data read from fifo: 2E
+    19.60ns INFO     test                               Data written to fifo: E7
+    19.80ns INFO     test                               Data read from fifo: AF
+    20.00ns INFO     test                               Data read from fifo: EC
+    20.20ns INFO     test                               Data read from fifo: E7
+    20.40ns INFO     test                               Data written to fifo: E
+    20.60ns INFO     test                               Data read from fifo: E
+    20.80ns INFO     test                               Data NOT read, fifo EMPTY!
+    21.00ns INFO     test                               Data NOT read, fifo EMPTY!
+    21.20ns INFO     test                               Data NOT read, fifo EMPTY!
+    21.40ns INFO     test                               Data NOT read, fifo EMPTY!
+    21.60ns INFO     test                               Data NOT read, fifo EMPTY!
+    21.80ns INFO     test                               Data written to fifo: B2
+    22.00ns INFO     test                               Data written to fifo: 74
+    22.00ns INFO     test                               top : <cocotb_coverage.coverage.CoverItem object at 0x7cabb0d4eba0>, coverage=25, size=32 
+    22.00ns INFO     test                                  top.fifo_empty : <cocotb_coverage.coverage.CoverPoint object at 0x7cabb0dc4910>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 27
+    22.00ns INFO     test                                     BIN False : 73
+    22.00ns INFO     test                                  top.fifo_full : <cocotb_coverage.coverage.CoverPoint object at 0x7cabb0dc47d0>, coverage=1, size=2 
+    22.00ns INFO     test                                     BIN True : 0
+    22.00ns INFO     test                                     BIN False : 100
+    22.00ns INFO     test                                  top.fifo_overflow : <cocotb_coverage.coverage.CoverPoint object at 0x7cabb0d72d70>, coverage=1, size=2 
+    22.00ns INFO     test                                     BIN True : 0
+    22.00ns INFO     test                                     BIN False : 100
+    22.00ns INFO     test                                  top.fifo_threshold : <cocotb_coverage.coverage.CoverPoint object at 0x7cabb0d72b10>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 1
+    22.00ns INFO     test                                     BIN False : 99
+    22.00ns INFO     test                                  top.fifo_underflow : <cocotb_coverage.coverage.CoverPoint object at 0x7cabb0d967b0>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 12
+    22.00ns INFO     test                                     BIN False : 88
+    22.00ns INFO     test                                  top.rw : <cocotb_coverage.coverage.CoverPoint object at 0x7cabb0d4ef90>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 55
+    22.00ns INFO     test                                     BIN False : 45
+    22.00ns INFO     test                                  top.rwXempty : <cocotb_coverage.coverage.CoverCross object at 0x7cabb0d4ee40>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 12
+    22.00ns INFO     test                                     BIN (True, False) : 43
+    22.00ns INFO     test                                     BIN (False, True) : 15
+    22.00ns INFO     test                                     BIN (False, False) : 30
+    22.00ns INFO     test                                  top.rwXfull : <cocotb_coverage.coverage.CoverCross object at 0x7cabb0dc4f50>, coverage=2, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 0
+    22.00ns INFO     test                                     BIN (True, False) : 55
+    22.00ns INFO     test                                     BIN (False, True) : 0
+    22.00ns INFO     test                                     BIN (False, False) : 45
+    22.00ns INFO     test                                  top.rwXoverflow : <cocotb_coverage.coverage.CoverCross object at 0x7cabb0d73490>, coverage=2, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 0
+    22.00ns INFO     test                                     BIN (True, False) : 55
+    22.00ns INFO     test                                     BIN (False, True) : 0
+    22.00ns INFO     test                                     BIN (False, False) : 45
+    22.00ns INFO     test                                  top.rwXthreshold : <cocotb_coverage.coverage.CoverCross object at 0x7cabb0dc5090>, coverage=3, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 1
+    22.00ns INFO     test                                     BIN (True, False) : 54
+    22.00ns INFO     test                                     BIN (False, True) : 0
+    22.00ns INFO     test                                     BIN (False, False) : 45
+    22.00ns INFO     test                                  top.rwXunderflow : <cocotb_coverage.coverage.CoverCross object at 0x7cabb0d72ea0>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 7
+    22.00ns INFO     test                                     BIN (True, False) : 48
+    22.00ns INFO     test                                     BIN (False, True) : 5
+    22.00ns INFO     test                                     BIN (False, False) : 40
+    22.00ns INFO     cocotb.regression                  test_fifo.fifo_test passed
+    22.00ns INFO     cocotb.regression                  **************************************************************************************
+                                                        ** TEST                          STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
+                                                        **************************************************************************************
+                                                        ** test_fifo.fifo_test            PASS          22.00           0.24         90.36  **
+                                                        **************************************************************************************
+                                                        ** TESTS=1 PASS=1 FAIL=0 SKIP=0                 22.00           0.25         89.64  **
+                                                        **************************************************************************************
+FST info: dumpfile sim_build/fifo_mem.fst opened for output.
+make[1]: Leaving directory '/tmp/sim4_simsh_rwlbuymr/source/examples/fifo/tests'
+
+--- STDERR ---
+/tmp/sim4_simsh_rwlbuymr/source/examples/fifo/tests/../hdl/fifo.v:46: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_rwlbuymr/source/examples/fifo/tests/../hdl/fifo.v:48: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_rwlbuymr/source/examples/fifo/tests/../hdl/fifo.v:107: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_rwlbuymr/source/examples/fifo/tests/../hdl/fifo.v:109: warning: extra digits given for sized binary constant.
+/mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb_tools/makefiles/simulators/Makefile.icarus:66: Using MODULE is deprecated, please use COCOTB_TEST_MODULES instead.

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/missing_enable/diff.patch

@@ -0,0 +1,18 @@
+--- a/examples/fifo/hdl/fifo.v
++++ b/examples/fifo/hdl/fifo.v
+@@ -27,8 +27,7 @@
+   wire[7:0] data_out;  
+   always @(posedge clk)  
+   begin  
+-   if(fifo_we)   
+-      data_out2[wptr[3:0]] <=data_in ;  
++   data_out2[wptr[3:0]] <=data_in ;  
+   end  
+   assign data_out = data_out2[rptr[3:0]];  
+  endmodule  
+@@ -110,4 +109,4 @@
+    else  
+     wptr <= wptr;  
+   end  
+- endmodule  
++ endmodule

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/missing_enable/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "missing_enable",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "examples/fifo/hdl/fifo.v"
+  ],
+  "bug_description": "Removed 'fifo_we' enable condition from memory_array sequential block \u2014 data_out2[wptr[3:0]] now updates on every clock edge instead of only when fifo_we is high",
+  "signals_affected": [
+    "data_out2"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "The FIFO memory is being corrupted during read operations. When fifo_we is low (not asserted), the data memory should remain stable, but data_out2 is unexpectedly updating on every clock edge regardless of the write enable signal. At t=2100, with fifo_we=0, the output data continues to change when no write should be occurring. This incorrect behavior cascades to the read path\u2014at t=2300 when fifo_rd=1, the read data is corrupted because the memory contents were overwritten when they should have been protected by the fifo_we gating. The fifo_full flag is also behaving unexpectedly, diverging at t=1000, suggesting the write pointer is advancing uncontrollably. The FIFO write and read protocols are not properly isolated, causing data integrity failures whenever reads and uncontrolled writes overlap.",
+  "diff_summary": "7 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/missing_enable/sim_log.txt

@@ -0,0 +1,178 @@
+rm -f results.xml
+"make" -f Makefile results.xml
+make[1]: Entering directory '/tmp/sim4_simsh_2yqv8q4j/source/examples/fifo/tests'
+mkdir -p sim_build
+/usr/bin/iverilog -o sim_build/sim.vvp -s fifo_mem -g2012 -f sim_build/cmds.f -s cocotb_iverilog_dump  /tmp/sim4_simsh_2yqv8q4j/source/examples/fifo/tests/../hdl/fifo.v sim_build/cocotb_iverilog_dump.v
+rm -f results.xml
+COCOTB_TEST_MODULES=test_fifo COCOTB_TESTCASE= COCOTB_TEST_FILTER= COCOTB_TOPLEVEL=fifo_mem TOPLEVEL_LANG=verilog \
+         /usr/bin/vvp -M /mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb/libs -m libcocotbvpi_icarus   sim_build/sim.vvp -fst  
+     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:93   in _embed_init_python              Using Python 3.13.0rc1 interpreter at /mnt/d/ubc-capstone-26/data-pipeline/.venv/bin/python
+     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:79   in gpi_print_registered_impl       VPI registered
+     0.00ns INFO     cocotb                             Running on Icarus Verilog version 11.0 (stable)
+     0.00ns WARNING  gpi                                vpi_iterate returned NULL for type vpiInstance for object NULL
+     0.00ns INFO     cocotb                             Seeding Python random module with 1775588215
+     0.00ns INFO     cocotb                             Initialized cocotb v2.0.1 from /mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb
+     0.00ns INFO     cocotb                             Running tests
+     0.00ns INFO     cocotb.regression                  running test_fifo.fifo_test (1/1)
+                                                            FIFO Test 
+     2.20ns INFO     test                               Data written to fifo: 10
+     2.40ns INFO     test                               Data read from fifo: 10
+     2.60ns INFO     test                               Data NOT read, fifo EMPTY!
+     2.80ns INFO     test                               Data NOT read, fifo EMPTY!
+     3.00ns INFO     test                               Data NOT read, fifo EMPTY!
+     3.20ns INFO     test                               Data NOT read, fifo EMPTY!
+     3.40ns INFO     test                               Data written to fifo: CC
+     3.60ns INFO     test                               Data written to fifo: 40
+     3.80ns INFO     test                               Data written to fifo: FC
+     4.00ns INFO     test                               Data read from fifo: CC
+     4.20ns INFO     test                               Data written to fifo: 60
+     4.40ns INFO     test                               Data written to fifo: 56
+     4.60ns INFO     test                               Data written to fifo: 9C
+     4.80ns INFO     test                               Data written to fifo: B6
+     5.00ns INFO     test                               Data read from fifo: 40
+     5.20ns INFO     test                               Data written to fifo: 8E
+     5.40ns INFO     test                               Data written to fifo: D4
+     5.60ns INFO     test                               Data read from fifo: FC
+     5.80ns INFO     test                               Data written to fifo: B
+     6.00ns INFO     test                               Data written to fifo: 5C
+     6.20ns INFO     test                               Data written to fifo: 98
+     6.40ns INFO     test                               Data written to fifo: E9
+     6.60ns INFO     test                               Data written to fifo: 9E
+     6.80ns INFO     test                               Data read from fifo: 60
+     7.00ns INFO     test                               Data written to fifo: 6E
+     7.20ns INFO     test                               Data written to fifo: 76
+     7.40ns INFO     test                               Data written to fifo: 29
+     7.60ns INFO     test                               Data read from fifo: 56
+     7.80ns INFO     test                               Data written to fifo: 1C
+     8.00ns INFO     test                               Data written to fifo: 5C
+     8.20ns INFO     test                               Data written to fifo: ED
+     8.40ns INFO     test                               Data written to fifo: 40
+     8.60ns INFO     test                               Data NOT written, fifo FULL!
+     8.80ns INFO     test                               Data NOT written, fifo FULL!
+     9.00ns INFO     test                               Data read from fifo: 37
+     9.20ns INFO     test                               Data read from fifo: B6
+     9.40ns INFO     test                               Data read from fifo: 8E
+     9.60ns INFO     test                               Data read from fifo: D4
+     9.80ns INFO     test                               Data read from fifo: B
+    10.00ns INFO     test                               Data read from fifo: 5C
+    10.20ns INFO     test                               Data written to fifo: 79
+    10.40ns INFO     test                               Data written to fifo: A
+    10.60ns INFO     test                               Data read from fifo: 98
+    10.80ns INFO     test                               Data read from fifo: E9
+    11.00ns INFO     test                               Data written to fifo: 37
+    11.20ns INFO     test                               Data read from fifo: 9E
+    11.40ns INFO     test                               Data written to fifo: 0
+    11.60ns INFO     test                               Data written to fifo: B
+    11.80ns INFO     test                               Data read from fifo: 6E
+    12.00ns INFO     test                               Data written to fifo: 40
+    12.20ns INFO     test                               Data written to fifo: 7F
+    12.40ns INFO     test                               Data read from fifo: 76
+    12.60ns INFO     test                               Data read from fifo: 29
+    12.80ns INFO     test                               Data read from fifo: 1C
+    13.00ns INFO     test                               Data written to fifo: E8
+    13.20ns INFO     test                               Data read from fifo: 5C
+    13.40ns INFO     test                               Data read from fifo: ED
+    13.60ns INFO     test                               Data read from fifo: 40
+    13.80ns INFO     test                               Data written to fifo: 5C
+    14.00ns INFO     test                               Data written to fifo: AA
+    14.20ns INFO     test                               Data written to fifo: 1A
+    14.40ns INFO     test                               Data written to fifo: 1F
+    14.60ns INFO     test                               Data read from fifo: 79
+    14.80ns INFO     test                               Data read from fifo: A
+    15.00ns INFO     test                               Data written to fifo: C5
+    15.20ns INFO     test                               Data read from fifo: 37
+    15.40ns INFO     test                               Data written to fifo: 5A
+    15.60ns INFO     test                               Data written to fifo: 8
+    15.80ns INFO     test                               Data written to fifo: 6A
+    16.00ns INFO     test                               Data read from fifo: 0
+    16.20ns INFO     test                               Data written to fifo: 74
+    16.40ns INFO     test                               Data read from fifo: B
+    16.60ns INFO     test                               Data written to fifo: FD
+    16.80ns INFO     test                               Data written to fifo: F9
+    17.00ns INFO     test                               Data written to fifo: C6
+    17.20ns INFO     test                               Data read from fifo: 40
+    17.40ns INFO     test                               Data read from fifo: 7F
+    17.60ns INFO     test                               Data written to fifo: 42
+    17.80ns INFO     test                               Data written to fifo: B9
+    18.00ns INFO     test                               Data read from fifo: E8
+    18.20ns INFO     test                               Data written to fifo: 98
+    18.40ns INFO     test                               Data written to fifo: B4
+    18.60ns INFO     test                               Data read from fifo: 5C
+    18.80ns INFO     test                               Data read from fifo: AA
+    19.00ns INFO     test                               Data written to fifo: 1F
+    19.20ns INFO     test                               Data read from fifo: 1A
+    19.40ns INFO     test                               Data written to fifo: 9C
+    19.60ns INFO     test                               Data written to fifo: 65
+    19.80ns INFO     test                               Data NOT written, fifo FULL!
+    20.00ns INFO     test                               Data NOT written, fifo FULL!
+    20.20ns INFO     test                               Data NOT written, fifo FULL!
+    20.40ns INFO     test                               Data NOT written, fifo FULL!
+    20.60ns INFO     test                               Data NOT written, fifo FULL!
+    20.80ns INFO     test                               Data read from fifo: 36
+    21.00ns INFO     test                               Data read from fifo: C5
+    21.20ns INFO     test                               Data read from fifo: 5A
+    21.40ns INFO     test                               Data written to fifo: 62
+    21.60ns INFO     test                               Data read from fifo: 8
+    21.80ns INFO     test                               Data written to fifo: B
+    22.00ns INFO     test                               Data written to fifo: 38
+    22.00ns INFO     test                               top : <cocotb_coverage.coverage.CoverItem object at 0x70bcdca4eba0>, coverage=32, size=32 
+    22.00ns INFO     test                                  top.fifo_empty : <cocotb_coverage.coverage.CoverPoint object at 0x70bcdcac8910>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 6
+    22.00ns INFO     test                                     BIN False : 94
+    22.00ns INFO     test                                  top.fifo_full : <cocotb_coverage.coverage.CoverPoint object at 0x70bcdcac87d0>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 10
+    22.00ns INFO     test                                     BIN False : 90
+    22.00ns INFO     test                                  top.fifo_overflow : <cocotb_coverage.coverage.CoverPoint object at 0x70bcdca76d70>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 7
+    22.00ns INFO     test                                     BIN False : 93
+    22.00ns INFO     test                                  top.fifo_threshold : <cocotb_coverage.coverage.CoverPoint object at 0x70bcdca76b10>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 80
+    22.00ns INFO     test                                     BIN False : 20
+    22.00ns INFO     test                                  top.fifo_underflow : <cocotb_coverage.coverage.CoverPoint object at 0x70bcdca9a7b0>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 4
+    22.00ns INFO     test                                     BIN False : 96
+    22.00ns INFO     test                                  top.rw : <cocotb_coverage.coverage.CoverPoint object at 0x70bcdca4ef90>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 41
+    22.00ns INFO     test                                     BIN False : 59
+    22.00ns INFO     test                                  top.rwXempty : <cocotb_coverage.coverage.CoverCross object at 0x70bcdca4ee40>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 4
+    22.00ns INFO     test                                     BIN (True, False) : 37
+    22.00ns INFO     test                                     BIN (False, True) : 2
+    22.00ns INFO     test                                     BIN (False, False) : 57
+    22.00ns INFO     test                                  top.rwXfull : <cocotb_coverage.coverage.CoverCross object at 0x70bcdcac8f50>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 3
+    22.00ns INFO     test                                     BIN (True, False) : 38
+    22.00ns INFO     test                                     BIN (False, True) : 7
+    22.00ns INFO     test                                     BIN (False, False) : 52
+    22.00ns INFO     test                                  top.rwXoverflow : <cocotb_coverage.coverage.CoverCross object at 0x70bcdca77490>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 2
+    22.00ns INFO     test                                     BIN (True, False) : 39
+    22.00ns INFO     test                                     BIN (False, True) : 5
+    22.00ns INFO     test                                     BIN (False, False) : 54
+    22.00ns INFO     test                                  top.rwXthreshold : <cocotb_coverage.coverage.CoverCross object at 0x70bcdcac9090>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 33
+    22.00ns INFO     test                                     BIN (True, False) : 8
+    22.00ns INFO     test                                     BIN (False, True) : 47
+    22.00ns INFO     test                                     BIN (False, False) : 12
+    22.00ns INFO     test                                  top.rwXunderflow : <cocotb_coverage.coverage.CoverCross object at 0x70bcdca76ea0>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 3
+    22.00ns INFO     test                                     BIN (True, False) : 38
+    22.00ns INFO     test                                     BIN (False, True) : 1
+    22.00ns INFO     test                                     BIN (False, False) : 58
+    22.00ns INFO     cocotb.regression                  test_fifo.fifo_test passed
+    22.00ns INFO     cocotb.regression                  **************************************************************************************
+                                                        ** TEST                          STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
+                                                        **************************************************************************************
+                                                        ** test_fifo.fifo_test            PASS          22.00           0.23         96.43  **
+                                                        **************************************************************************************
+                                                        ** TESTS=1 PASS=1 FAIL=0 SKIP=0                 22.00           0.23         95.99  **
+                                                        **************************************************************************************
+FST info: dumpfile sim_build/fifo_mem.fst opened for output.
+make[1]: Leaving directory '/tmp/sim4_simsh_2yqv8q4j/source/examples/fifo/tests'
+
+--- STDERR ---
+/tmp/sim4_simsh_2yqv8q4j/source/examples/fifo/tests/../hdl/fifo.v:45: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_2yqv8q4j/source/examples/fifo/tests/../hdl/fifo.v:47: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_2yqv8q4j/source/examples/fifo/tests/../hdl/fifo.v:106: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_2yqv8q4j/source/examples/fifo/tests/../hdl/fifo.v:108: warning: extra digits given for sized binary constant.
+/mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb_tools/makefiles/simulators/Makefile.icarus:66: Using MODULE is deprecated, please use COCOTB_TEST_MODULES instead.

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/missing_reset/diff.patch

@@ -0,0 +1,29 @@
+--- a/examples/fifo/hdl/fifo.v
++++ b/examples/fifo/hdl/fifo.v
+@@ -72,6 +72,7 @@
+    fifo_empty = (~fbit_comp) & pointer_equal;  
+    fifo_threshold = (pointer_result[4]||pointer_result[3]) ? 1:0;  
+   end  
++  initial fifo_overflow = 1'bx;
+   always @(posedge clk or negedge rst_n)  
+   begin  
+   if(~rst_n) fifo_overflow <=0;  
+@@ -82,10 +83,10 @@
+     else  
+      fifo_overflow <= fifo_overflow;  
+   end  
++  initial fifo_underflow = 1'bx;
+   always @(posedge clk or negedge rst_n)  
+   begin  
+-  if(~rst_n) fifo_underflow <=0;  
+-  else if((underflow_set==1)&&(fifo_we==0))  
++  if((underflow_set==1)&&(fifo_we==0))  
+    fifo_underflow <=1;  
+    else if(fifo_we)  
+     fifo_underflow <=0;  
+@@ -110,4 +111,4 @@
+    else  
+     wptr <= wptr;  
+   end  
+- endmodule  
++ endmodule

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/missing_reset/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "missing_reset",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "examples/fifo/hdl/fifo.v"
+  ],
+  "bug_description": "Removed reset logic for 'fifo_underflow' register in status_signal module; the reset branch for fifo_underflow is removed entirely and an initial block sets it to x to make the missing reset observable in simulation",
+  "signals_affected": [
+    "fifo_underflow"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "After reset de-assertion, the fifo_underflow status signal is not properly cleared to a known state, remaining in an undefined condition. This causes downstream FIFO control logic to malfunction: at t=2100ns, fifo_we fails to respond correctly to write requests and remains stuck at 0, and at t=2300ns, fifo_rd incorrectly asserts to 1 when the FIFO should not be readable. The undefined fifo_underflow state is propagating through the control path, preventing reliable FIFO operation and making it impossible to verify underflow detection functionality. Initialization of the status signal module appears incomplete, as the underflow condition is not being reset along with other module state during the power-up sequence.",
+  "diff_summary": "9 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/missing_reset/sim_log.txt

@@ -0,0 +1,178 @@
+rm -f results.xml
+"make" -f Makefile results.xml
+make[1]: Entering directory '/tmp/sim4_simsh__rjzbs3b/source/examples/fifo/tests'
+mkdir -p sim_build
+/usr/bin/iverilog -o sim_build/sim.vvp -s fifo_mem -g2012 -f sim_build/cmds.f -s cocotb_iverilog_dump  /tmp/sim4_simsh__rjzbs3b/source/examples/fifo/tests/../hdl/fifo.v sim_build/cocotb_iverilog_dump.v
+rm -f results.xml
+COCOTB_TEST_MODULES=test_fifo COCOTB_TESTCASE= COCOTB_TEST_FILTER= COCOTB_TOPLEVEL=fifo_mem TOPLEVEL_LANG=verilog \
+         /usr/bin/vvp -M /mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb/libs -m libcocotbvpi_icarus   sim_build/sim.vvp -fst  
+     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:93   in _embed_init_python              Using Python 3.13.0rc1 interpreter at /mnt/d/ubc-capstone-26/data-pipeline/.venv/bin/python
+     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:79   in gpi_print_registered_impl       VPI registered
+     0.00ns INFO     cocotb                             Running on Icarus Verilog version 11.0 (stable)
+     0.00ns WARNING  gpi                                vpi_iterate returned NULL for type vpiInstance for object NULL
+     0.00ns INFO     cocotb                             Seeding Python random module with 1775588272
+     0.00ns INFO     cocotb                             Initialized cocotb v2.0.1 from /mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb
+     0.00ns INFO     cocotb                             Running tests
+     0.00ns INFO     cocotb.regression                  running test_fifo.fifo_test (1/1)
+                                                            FIFO Test 
+     2.20ns INFO     test                               Data written to fifo: 35
+     2.40ns INFO     test                               Data read from fifo: 35
+     2.60ns INFO     test                               Data NOT read, fifo EMPTY!
+     2.80ns INFO     test                               Data NOT read, fifo EMPTY!
+     3.00ns INFO     test                               Data NOT read, fifo EMPTY!
+     3.20ns INFO     test                               Data written to fifo: 48
+     3.40ns INFO     test                               Data read from fifo: 48
+     3.60ns INFO     test                               Data NOT read, fifo EMPTY!
+     3.80ns INFO     test                               Data NOT read, fifo EMPTY!
+     4.00ns INFO     test                               Data NOT read, fifo EMPTY!
+     4.20ns INFO     test                               Data written to fifo: 19
+     4.40ns INFO     test                               Data read from fifo: 19
+     4.60ns INFO     test                               Data written to fifo: 4C
+     4.80ns INFO     test                               Data read from fifo: 4C
+     5.00ns INFO     test                               Data written to fifo: D8
+     5.20ns INFO     test                               Data written to fifo: A5
+     5.40ns INFO     test                               Data written to fifo: 22
+     5.60ns INFO     test                               Data read from fifo: D8
+     5.80ns INFO     test                               Data written to fifo: 8
+     6.00ns INFO     test                               Data read from fifo: A5
+     6.20ns INFO     test                               Data read from fifo: 22
+     6.40ns INFO     test                               Data read from fifo: 8
+     6.60ns INFO     test                               Data NOT read, fifo EMPTY!
+     6.80ns INFO     test                               Data NOT read, fifo EMPTY!
+     7.00ns INFO     test                               Data written to fifo: CB
+     7.20ns INFO     test                               Data read from fifo: CB
+     7.40ns INFO     test                               Data NOT read, fifo EMPTY!
+     7.60ns INFO     test                               Data NOT read, fifo EMPTY!
+     7.80ns INFO     test                               Data NOT read, fifo EMPTY!
+     8.00ns INFO     test                               Data written to fifo: 59
+     8.20ns INFO     test                               Data read from fifo: 59
+     8.40ns INFO     test                               Data written to fifo: CA
+     8.60ns INFO     test                               Data read from fifo: CA
+     8.80ns INFO     test                               Data written to fifo: 93
+     9.00ns INFO     test                               Data written to fifo: 3
+     9.20ns INFO     test                               Data read from fifo: 93
+     9.40ns INFO     test                               Data read from fifo: 3
+     9.60ns INFO     test                               Data NOT read, fifo EMPTY!
+     9.80ns INFO     test                               Data written to fifo: F5
+    10.00ns INFO     test                               Data written to fifo: 2C
+    10.20ns INFO     test                               Data read from fifo: F5
+    10.40ns INFO     test                               Data written to fifo: 9C
+    10.60ns INFO     test                               Data read from fifo: 2C
+    10.80ns INFO     test                               Data written to fifo: 5B
+    11.00ns INFO     test                               Data read from fifo: 9C
+    11.20ns INFO     test                               Data written to fifo: 8E
+    11.40ns INFO     test                               Data read from fifo: 5B
+    11.60ns INFO     test                               Data written to fifo: BE
+    11.80ns INFO     test                               Data read from fifo: 8E
+    12.00ns INFO     test                               Data written to fifo: FF
+    12.20ns INFO     test                               Data written to fifo: 1C
+    12.40ns INFO     test                               Data written to fifo: 6F
+    12.60ns INFO     test                               Data written to fifo: AC
+    12.80ns INFO     test                               Data written to fifo: D0
+    13.00ns INFO     test                               Data written to fifo: 13
+    13.20ns INFO     test                               Data written to fifo: 51
+    13.40ns INFO     test                               Data read from fifo: BE
+    13.60ns INFO     test                               Data read from fifo: FF
+    13.80ns INFO     test                               Data read from fifo: 1C
+    14.00ns INFO     test                               Data read from fifo: 6F
+    14.20ns INFO     test                               Data written to fifo: BE
+    14.40ns INFO     test                               Data written to fifo: B7
+    14.60ns INFO     test                               Data written to fifo: 28
+    14.80ns INFO     test                               Data written to fifo: 53
+    15.00ns INFO     test                               Data written to fifo: A0
+    15.20ns INFO     test                               Data read from fifo: AC
+    15.40ns INFO     test                               Data read from fifo: D0
+    15.60ns INFO     test                               Data written to fifo: 14
+    15.80ns INFO     test                               Data read from fifo: 13
+    16.00ns INFO     test                               Data written to fifo: 47
+    16.20ns INFO     test                               Data read from fifo: 51
+    16.40ns INFO     test                               Data written to fifo: 6C
+    16.60ns INFO     test                               Data read from fifo: BE
+    16.80ns INFO     test                               Data written to fifo: 91
+    17.00ns INFO     test                               Data written to fifo: C9
+    17.20ns INFO     test                               Data read from fifo: B7
+    17.40ns INFO     test                               Data read from fifo: 28
+    17.60ns INFO     test                               Data read from fifo: 53
+    17.80ns INFO     test                               Data written to fifo: 65
+    18.00ns INFO     test                               Data written to fifo: 2D
+    18.20ns INFO     test                               Data written to fifo: C8
+    18.40ns INFO     test                               Data written to fifo: 96
+    18.60ns INFO     test                               Data read from fifo: A0
+    18.80ns INFO     test                               Data read from fifo: 14
+    19.00ns INFO     test                               Data written to fifo: 52
+    19.20ns INFO     test                               Data written to fifo: 90
+    19.40ns INFO     test                               Data written to fifo: 1A
+    19.60ns INFO     test                               Data read from fifo: 47
+    19.80ns INFO     test                               Data written to fifo: 8E
+    20.00ns INFO     test                               Data read from fifo: 6C
+    20.20ns INFO     test                               Data read from fifo: 91
+    20.40ns INFO     test                               Data written to fifo: 17
+    20.60ns INFO     test                               Data read from fifo: C9
+    20.80ns INFO     test                               Data read from fifo: 65
+    21.00ns INFO     test                               Data written to fifo: C3
+    21.20ns INFO     test                               Data written to fifo: 55
+    21.40ns INFO     test                               Data written to fifo: 24
+    21.60ns INFO     test                               Data read from fifo: 2D
+    21.80ns INFO     test                               Data read from fifo: C8
+    22.00ns INFO     test                               Data written to fifo: 8F
+    22.00ns INFO     test                               top : <cocotb_coverage.coverage.CoverItem object at 0x73f5c82faba0>, coverage=26, size=32 
+    22.00ns INFO     test                                  top.fifo_empty : <cocotb_coverage.coverage.CoverPoint object at 0x73f5c8370910>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 22
+    22.00ns INFO     test                                     BIN False : 78
+    22.00ns INFO     test                                  top.fifo_full : <cocotb_coverage.coverage.CoverPoint object at 0x73f5c83707d0>, coverage=1, size=2 
+    22.00ns INFO     test                                     BIN True : 0
+    22.00ns INFO     test                                     BIN False : 100
+    22.00ns INFO     test                                  top.fifo_overflow : <cocotb_coverage.coverage.CoverPoint object at 0x73f5c831ed70>, coverage=1, size=2 
+    22.00ns INFO     test                                     BIN True : 0
+    22.00ns INFO     test                                     BIN False : 100
+    22.00ns INFO     test                                  top.fifo_threshold : <cocotb_coverage.coverage.CoverPoint object at 0x73f5c831eb10>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 30
+    22.00ns INFO     test                                     BIN False : 70
+    22.00ns INFO     test                                  top.fifo_underflow : <cocotb_coverage.coverage.CoverPoint object at 0x73f5c833a7b0>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 12
+    22.00ns INFO     test                                     BIN False : 88
+    22.00ns INFO     test                                  top.rw : <cocotb_coverage.coverage.CoverPoint object at 0x73f5c82faf90>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 51
+    22.00ns INFO     test                                     BIN False : 49
+    22.00ns INFO     test                                  top.rwXempty : <cocotb_coverage.coverage.CoverCross object at 0x73f5c82fae40>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 12
+    22.00ns INFO     test                                     BIN (True, False) : 39
+    22.00ns INFO     test                                     BIN (False, True) : 10
+    22.00ns INFO     test                                     BIN (False, False) : 39
+    22.00ns INFO     test                                  top.rwXfull : <cocotb_coverage.coverage.CoverCross object at 0x73f5c8370f50>, coverage=2, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 0
+    22.00ns INFO     test                                     BIN (True, False) : 51
+    22.00ns INFO     test                                     BIN (False, True) : 0
+    22.00ns INFO     test                                     BIN (False, False) : 49
+    22.00ns INFO     test                                  top.rwXoverflow : <cocotb_coverage.coverage.CoverCross object at 0x73f5c831f490>, coverage=2, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 0
+    22.00ns INFO     test                                     BIN (True, False) : 51
+    22.00ns INFO     test                                     BIN (False, True) : 0
+    22.00ns INFO     test                                     BIN (False, False) : 49
+    22.00ns INFO     test                                  top.rwXthreshold : <cocotb_coverage.coverage.CoverCross object at 0x73f5c8371090>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 17
+    22.00ns INFO     test                                     BIN (True, False) : 34
+    22.00ns INFO     test                                     BIN (False, True) : 13
+    22.00ns INFO     test                                     BIN (False, False) : 36
+    22.00ns INFO     test                                  top.rwXunderflow : <cocotb_coverage.coverage.CoverCross object at 0x73f5c831eea0>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 7
+    22.00ns INFO     test                                     BIN (True, False) : 44
+    22.00ns INFO     test                                     BIN (False, True) : 5
+    22.00ns INFO     test                                     BIN (False, False) : 44
+    22.00ns INFO     cocotb.regression                  test_fifo.fifo_test passed
+    22.00ns INFO     cocotb.regression                  **************************************************************************************
+                                                        ** TEST                          STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
+                                                        **************************************************************************************
+                                                        ** test_fifo.fifo_test            PASS          22.00           0.17        128.80  **
+                                                        **************************************************************************************
+                                                        ** TESTS=1 PASS=1 FAIL=0 SKIP=0                 22.00           0.17        128.13  **
+                                                        **************************************************************************************
+FST info: dumpfile sim_build/fifo_mem.fst opened for output.
+make[1]: Leaving directory '/tmp/sim4_simsh__rjzbs3b/source/examples/fifo/tests'
+
+--- STDERR ---
+/tmp/sim4_simsh__rjzbs3b/source/examples/fifo/tests/../hdl/fifo.v:46: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh__rjzbs3b/source/examples/fifo/tests/../hdl/fifo.v:48: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh__rjzbs3b/source/examples/fifo/tests/../hdl/fifo.v:108: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh__rjzbs3b/source/examples/fifo/tests/../hdl/fifo.v:110: warning: extra digits given for sized binary constant.
+/mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb_tools/makefiles/simulators/Makefile.icarus:66: Using MODULE is deprecated, please use COCOTB_TEST_MODULES instead.

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/operator_typo/diff.patch

@@ -0,0 +1,17 @@
+--- a/examples/fifo/hdl/fifo.v
++++ b/examples/fifo/hdl/fifo.v
+@@ -63,7 +63,7 @@
+   reg fifo_full, fifo_empty, fifo_threshold, fifo_overflow, fifo_underflow;  
+   assign fbit_comp = wptr[4] ^ rptr[4];  
+   assign pointer_equal = (wptr[3:0] - rptr[3:0]) ? 0:1;  
+-  assign pointer_result = wptr[4:0] - rptr[4:0];  
++  assign pointer_result = wptr[4:0] + rptr[4:0];  
+   assign overflow_set = fifo_full & wr;  
+   assign underflow_set = fifo_empty&rd;  
+   always @(*)  
+@@ -110,4 +110,4 @@
+    else  
+     wptr <= wptr;  
+   end  
+- endmodule  
++ endmodule

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/operator_typo/metadata.json

@@ -0,0 +1,17 @@
+{
+  "bug_type": "operator_typo",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "examples/fifo/hdl/fifo.v"
+  ],
+  "bug_description": "Changed '-' to '+' in pointer_result computation \u2014 wptr and rptr are added instead of subtracted, causing fifo_threshold to be incorrectly asserted",
+  "signals_affected": [
+    "pointer_result",
+    "fifo_threshold"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "During verification, the FIFO threshold control logic is not functioning correctly. At t=2100, fifo_we unexpectedly remains deasserted (0) when a write should be allowed based on FIFO occupancy, and at t=2500, fifo_rd similarly remains deasserted (0) when read data should be available. The threshold signal is being incorrectly asserted regardless of the actual relationship between the write and read pointer positions. This prevents the FIFO from correctly signaling when space is available for writes or when data is available for reads, blocking normal operation. The issue appears to originate in the pointer_result computation that calculates FIFO fill level to determine the threshold assertion.",
+  "diff_summary": "6 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/operator_typo/sim_log.txt

@@ -0,0 +1,178 @@
+rm -f results.xml
+"make" -f Makefile results.xml
+make[1]: Entering directory '/tmp/sim4_simsh_3_2qp09q/source/examples/fifo/tests'
+mkdir -p sim_build
+/usr/bin/iverilog -o sim_build/sim.vvp -s fifo_mem -g2012 -f sim_build/cmds.f -s cocotb_iverilog_dump  /tmp/sim4_simsh_3_2qp09q/source/examples/fifo/tests/../hdl/fifo.v sim_build/cocotb_iverilog_dump.v
+rm -f results.xml
+COCOTB_TEST_MODULES=test_fifo COCOTB_TESTCASE= COCOTB_TEST_FILTER= COCOTB_TOPLEVEL=fifo_mem TOPLEVEL_LANG=verilog \
+         /usr/bin/vvp -M /mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb/libs -m libcocotbvpi_icarus   sim_build/sim.vvp -fst  
+     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:93   in _embed_init_python              Using Python 3.13.0rc1 interpreter at /mnt/d/ubc-capstone-26/data-pipeline/.venv/bin/python
+     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:79   in gpi_print_registered_impl       VPI registered
+     0.00ns INFO     cocotb                             Running on Icarus Verilog version 11.0 (stable)
+     0.00ns WARNING  gpi                                vpi_iterate returned NULL for type vpiInstance for object NULL
+     0.00ns INFO     cocotb                             Seeding Python random module with 1775588361
+     0.00ns INFO     cocotb                             Initialized cocotb v2.0.1 from /mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb
+     0.00ns INFO     cocotb                             Running tests
+     0.00ns INFO     cocotb.regression                  running test_fifo.fifo_test (1/1)
+                                                            FIFO Test 
+     2.20ns INFO     test                               Data NOT read, fifo EMPTY!
+     2.40ns INFO     test                               Data NOT read, fifo EMPTY!
+     2.60ns INFO     test                               Data NOT read, fifo EMPTY!
+     2.80ns INFO     test                               Data written to fifo: 8D
+     3.00ns INFO     test                               Data written to fifo: 3
+     3.20ns INFO     test                               Data read from fifo: 8D
+     3.40ns INFO     test                               Data read from fifo: 3
+     3.60ns INFO     test                               Data NOT read, fifo EMPTY!
+     3.80ns INFO     test                               Data written to fifo: 82
+     4.00ns INFO     test                               Data written to fifo: 18
+     4.20ns INFO     test                               Data read from fifo: 82
+     4.40ns INFO     test                               Data written to fifo: 69
+     4.60ns INFO     test                               Data read from fifo: 18
+     4.80ns INFO     test                               Data written to fifo: 3
+     5.00ns INFO     test                               Data read from fifo: 69
+     5.20ns INFO     test                               Data read from fifo: 3
+     5.40ns INFO     test                               Data written to fifo: 9C
+     5.60ns INFO     test                               Data written to fifo: E1
+     5.80ns INFO     test                               Data read from fifo: 9C
+     6.00ns INFO     test                               Data written to fifo: 38
+     6.20ns INFO     test                               Data read from fifo: E1
+     6.40ns INFO     test                               Data written to fifo: 4E
+     6.60ns INFO     test                               Data read from fifo: 38
+     6.80ns INFO     test                               Data read from fifo: 4E
+     7.00ns INFO     test                               Data NOT read, fifo EMPTY!
+     7.20ns INFO     test                               Data written to fifo: F3
+     7.40ns INFO     test                               Data read from fifo: F3
+     7.60ns INFO     test                               Data NOT read, fifo EMPTY!
+     7.80ns INFO     test                               Data NOT read, fifo EMPTY!
+     8.00ns INFO     test                               Data NOT read, fifo EMPTY!
+     8.20ns INFO     test                               Data written to fifo: 38
+     8.40ns INFO     test                               Data written to fifo: 57
+     8.60ns INFO     test                               Data read from fifo: 38
+     8.80ns INFO     test                               Data written to fifo: AA
+     9.00ns INFO     test                               Data written to fifo: 83
+     9.20ns INFO     test                               Data read from fifo: 57
+     9.40ns INFO     test                               Data written to fifo: 2C
+     9.60ns INFO     test                               Data read from fifo: AA
+     9.80ns INFO     test                               Data read from fifo: 83
+    10.00ns INFO     test                               Data written to fifo: 47
+    10.20ns INFO     test                               Data written to fifo: 4B
+    10.40ns INFO     test                               Data written to fifo: 31
+    10.60ns INFO     test                               Data written to fifo: AB
+    10.80ns INFO     test                               Data written to fifo: E2
+    11.00ns INFO     test                               Data written to fifo: A0
+    11.20ns INFO     test                               Data read from fifo: 2C
+    11.40ns INFO     test                               Data read from fifo: 47
+    11.60ns INFO     test                               Data read from fifo: 4B
+    11.80ns INFO     test                               Data read from fifo: 31
+    12.00ns INFO     test                               Data read from fifo: AB
+    12.20ns INFO     test                               Data written to fifo: E
+    12.40ns INFO     test                               Data written to fifo: F
+    12.60ns INFO     test                               Data read from fifo: E2
+    12.80ns INFO     test                               Data written to fifo: 39
+    13.00ns INFO     test                               Data read from fifo: A0
+    13.20ns INFO     test                               Data written to fifo: 4F
+    13.40ns INFO     test                               Data written to fifo: 3E
+    13.60ns INFO     test                               Data read from fifo: E
+    13.80ns INFO     test                               Data read from fifo: F
+    14.00ns INFO     test                               Data read from fifo: 39
+    14.20ns INFO     test                               Data read from fifo: 4F
+    14.40ns INFO     test                               Data written to fifo: B1
+    14.60ns INFO     test                               Data read from fifo: 3E
+    14.80ns INFO     test                               Data read from fifo: B1
+    15.00ns INFO     test                               Data written to fifo: 52
+    15.20ns INFO     test                               Data read from fifo: 52
+    15.40ns INFO     test                               Data written to fifo: C4
+    15.60ns INFO     test                               Data written to fifo: F8
+    15.80ns INFO     test                               Data read from fifo: C4
+    16.00ns INFO     test                               Data read from fifo: F8
+    16.20ns INFO     test                               Data NOT read, fifo EMPTY!
+    16.40ns INFO     test                               Data NOT read, fifo EMPTY!
+    16.60ns INFO     test                               Data written to fifo: 7E
+    16.80ns INFO     test                               Data written to fifo: 80
+    17.00ns INFO     test                               Data read from fifo: 7E
+    17.20ns INFO     test                               Data read from fifo: 80
+    17.40ns INFO     test                               Data NOT read, fifo EMPTY!
+    17.60ns INFO     test                               Data NOT read, fifo EMPTY!
+    17.80ns INFO     test                               Data NOT read, fifo EMPTY!
+    18.00ns INFO     test                               Data NOT read, fifo EMPTY!
+    18.20ns INFO     test                               Data NOT read, fifo EMPTY!
+    18.40ns INFO     test                               Data written to fifo: D9
+    18.60ns INFO     test                               Data read from fifo: D9
+    18.80ns INFO     test                               Data written to fifo: 38
+    19.00ns INFO     test                               Data written to fifo: 74
+    19.20ns INFO     test                               Data written to fifo: 18
+    19.40ns INFO     test                               Data read from fifo: 38
+    19.60ns INFO     test                               Data read from fifo: 74
+    19.80ns INFO     test                               Data read from fifo: 18
+    20.00ns INFO     test                               Data written to fifo: 86
+    20.20ns INFO     test                               Data read from fifo: 86
+    20.40ns INFO     test                               Data NOT read, fifo EMPTY!
+    20.60ns INFO     test                               Data written to fifo: A3
+    20.80ns INFO     test                               Data written to fifo: 8E
+    21.00ns INFO     test                               Data read from fifo: A3
+    21.20ns INFO     test                               Data read from fifo: 8E
+    21.40ns INFO     test                               Data written to fifo: A7
+    21.60ns INFO     test                               Data written to fifo: FC
+    21.80ns INFO     test                               Data written to fifo: 90
+    22.00ns INFO     test                               Data read from fifo: A7
+    22.00ns INFO     test                               top : <cocotb_coverage.coverage.CoverItem object at 0x77e07584eba0>, coverage=26, size=32 
+    22.00ns INFO     test                                  top.fifo_empty : <cocotb_coverage.coverage.CoverPoint object at 0x77e0758c4910>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 29
+    22.00ns INFO     test                                     BIN False : 71
+    22.00ns INFO     test                                  top.fifo_full : <cocotb_coverage.coverage.CoverPoint object at 0x77e0758c47d0>, coverage=1, size=2 
+    22.00ns INFO     test                                     BIN True : 0
+    22.00ns INFO     test                                     BIN False : 100
+    22.00ns INFO     test                                  top.fifo_overflow : <cocotb_coverage.coverage.CoverPoint object at 0x77e075872d70>, coverage=1, size=2 
+    22.00ns INFO     test                                     BIN True : 0
+    22.00ns INFO     test                                     BIN False : 100
+    22.00ns INFO     test                                  top.fifo_threshold : <cocotb_coverage.coverage.CoverPoint object at 0x77e075872b10>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 67
+    22.00ns INFO     test                                     BIN False : 33
+    22.00ns INFO     test                                  top.fifo_underflow : <cocotb_coverage.coverage.CoverPoint object at 0x77e0758967b0>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 16
+    22.00ns INFO     test                                     BIN False : 84
+    22.00ns INFO     test                                  top.rw : <cocotb_coverage.coverage.CoverPoint object at 0x77e07584ef90>, coverage=2, size=2 
+    22.00ns INFO     test                                     BIN True : 57
+    22.00ns INFO     test                                     BIN False : 43
+    22.00ns INFO     test                                  top.rwXempty : <cocotb_coverage.coverage.CoverCross object at 0x77e07584ee40>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 16
+    22.00ns INFO     test                                     BIN (True, False) : 41
+    22.00ns INFO     test                                     BIN (False, True) : 13
+    22.00ns INFO     test                                     BIN (False, False) : 30
+    22.00ns INFO     test                                  top.rwXfull : <cocotb_coverage.coverage.CoverCross object at 0x77e0758c4f50>, coverage=2, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 0
+    22.00ns INFO     test                                     BIN (True, False) : 57
+    22.00ns INFO     test                                     BIN (False, True) : 0
+    22.00ns INFO     test                                     BIN (False, False) : 43
+    22.00ns INFO     test                                  top.rwXoverflow : <cocotb_coverage.coverage.CoverCross object at 0x77e075873490>, coverage=2, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 0
+    22.00ns INFO     test                                     BIN (True, False) : 57
+    22.00ns INFO     test                                     BIN (False, True) : 0
+    22.00ns INFO     test                                     BIN (False, False) : 43
+    22.00ns INFO     test                                  top.rwXthreshold : <cocotb_coverage.coverage.CoverCross object at 0x77e0758c5090>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 38
+    22.00ns INFO     test                                     BIN (True, False) : 19
+    22.00ns INFO     test                                     BIN (False, True) : 29
+    22.00ns INFO     test                                     BIN (False, False) : 14
+    22.00ns INFO     test                                  top.rwXunderflow : <cocotb_coverage.coverage.CoverCross object at 0x77e075872ea0>, coverage=4, size=4 
+    22.00ns INFO     test                                     BIN (True, True) : 9
+    22.00ns INFO     test                                     BIN (True, False) : 48
+    22.00ns INFO     test                                     BIN (False, True) : 7
+    22.00ns INFO     test                                     BIN (False, False) : 36
+    22.00ns INFO     cocotb.regression                  test_fifo.fifo_test passed
+    22.00ns INFO     cocotb.regression                  **************************************************************************************
+                                                        ** TEST                          STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
+                                                        **************************************************************************************
+                                                        ** test_fifo.fifo_test            PASS          22.00           0.14        152.02  **
+                                                        **************************************************************************************
+                                                        ** TESTS=1 PASS=1 FAIL=0 SKIP=0                 22.00           0.15        151.03  **
+                                                        **************************************************************************************
+FST info: dumpfile sim_build/fifo_mem.fst opened for output.
+make[1]: Leaving directory '/tmp/sim4_simsh_3_2qp09q/source/examples/fifo/tests'
+
+--- STDERR ---
+/tmp/sim4_simsh_3_2qp09q/source/examples/fifo/tests/../hdl/fifo.v:46: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_3_2qp09q/source/examples/fifo/tests/../hdl/fifo.v:48: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_3_2qp09q/source/examples/fifo/tests/../hdl/fifo.v:107: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_3_2qp09q/source/examples/fifo/tests/../hdl/fifo.v:109: warning: extra digits given for sized binary constant.
+/mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb_tools/makefiles/simulators/Makefile.icarus:66: Using MODULE is deprecated, please use COCOTB_TEST_MODULES instead.

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/wrong_bitwidth/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "wrong_bitwidth",
+  "task_type": "compile_error",
+  "files_modified": [
+    "examples/fifo/hdl/fifo.v"
+  ],
+  "bug_description": "Truncated 'rptr' register in read_pointer module from 5 bits to 4 bits, causing the MSB (wrap-around bit) to be lost, which breaks full/empty detection logic",
+  "signals_affected": [
+    "rptr"
+  ],
+  "simulation_status": "sim_failed",
+  "problem_statement": null,
+  "diff_summary": "6 changed lines",
+  "buggy_waveform": null,
+  "golden_waveform": "golden_waveform.fst"
+}

mciepluc_cocotb-coverage/candidates/fifo_mem__fifo/bugs/wrong_bitwidth/sim_log.txt

@@ -0,0 +1,20 @@
+rm -f results.xml
+"make" -f Makefile results.xml
+make[1]: Entering directory '/tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests'
+mkdir -p sim_build
+/usr/bin/iverilog -o sim_build/sim.vvp -s fifo_mem -g2012 -f sim_build/cmds.f -s cocotb_iverilog_dump  /tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests/../hdl/fifo.v sim_build/cocotb_iverilog_dump.v
+make[1]: Leaving directory '/tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests'
+
+--- STDERR ---
+/tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests/../hdl/fifo.v:46: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests/../hdl/fifo.v:48: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests/../hdl/fifo.v:107: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests/../hdl/fifo.v:109: warning: extra digits given for sized binary constant.
+/tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests/../hdl/fifo.v:40: error: Vectored port ``rptr'' [4:0] has a net declaration [3:0] at /tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests/../hdl/fifo.v:42 that does not match.
+/tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests/../hdl/fifo.v:46: error: Could not find variable ``rptr'' in ``fifo_mem.top2''
+/tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests/../hdl/fifo.v:48: error: Could not find variable ``rptr'' in ``fifo_mem.top2''
+/tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests/../hdl/fifo.v:50: error: Could not find variable ``rptr'' in ``fifo_mem.top2''
+/tmp/sim4_simsh_zgnrbcs_/source/examples/fifo/tests/../hdl/fifo.v:38: error: no wire/reg rptr in module fifo_mem.top2.
+5 error(s) during elaboration.
+make[1]: *** [/mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb_tools/makefiles/simulators/Makefile.icarus:52: sim_build/sim.vvp] Error 5
+make: *** [/mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb_tools/makefiles/Makefile.inc:17: sim] Error 2

mciepluc_cocotb-coverage/candidates/pkt_switch__pkt_switch/bugs/wrong_bitwidth/sim_log.txt

@@ -0,0 +1,64 @@
+rm -f results.xml
+"make" -f Makefile results.xml
+make[1]: Entering directory '/tmp/sim4_simsh_d2w5vu01/source/examples/pkt_switch/tests'
+mkdir -p sim_build
+/usr/bin/iverilog -o sim_build/sim.vvp -s pkt_switch -g2012 -f sim_build/cmds.f -s cocotb_iverilog_dump  /tmp/sim4_simsh_d2w5vu01/source/examples/pkt_switch/tests/../hdl/pkt_switch.v sim_build/cocotb_iverilog_dump.v
+rm -f results.xml
+COCOTB_TEST_MODULES=test_pkt_switch COCOTB_TESTCASE= COCOTB_TEST_FILTER= COCOTB_TOPLEVEL=pkt_switch TOPLEVEL_LANG=verilog \
+         /usr/bin/vvp -M /mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb/libs -m libcocotbvpi_icarus   sim_build/sim.vvp -fst  
+     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:93   in _embed_init_python              Using Python 3.13.0rc1 interpreter at /mnt/d/ubc-capstone-26/data-pipeline/.venv/bin/python
+     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:79   in gpi_print_registered_impl       VPI registered
+     0.00ns INFO     cocotb                             Running on Icarus Verilog version 11.0 (stable)
+     0.00ns WARNING  gpi                                vpi_iterate returned NULL for type vpiInstance for object NULL
+     0.00ns INFO     cocotb                             Seeding Python random module with 1775588443
+     0.00ns INFO     cocotb                             Initialized cocotb v2.0.1 from /mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb
+     0.00ns INFO     cocotb                             Running tests
+     0.00ns INFO     cocotb.regression                  running test_pkt_switch.pkt_switch_test (1/1)
+                                                            PKT_SWITCH Test 
+     2.80ns INFO     test                               Processing packet:
+     2.80ns INFO     test                                 ADDRESS: AF
+     2.80ns INFO     test                                 LENGTH: 5
+     2.80ns INFO     test                                 PAYLOAD: [39, 49, 197]
+     2.80ns INFO     test                               Filtering disabled
+     2.80ns INFO     test                               MONITOR0: Receiving packet on interface 0 (packet not filtered)
+     6.20ns INFO     test                               Processing packet:
+     6.20ns INFO     test                                 ADDRESS: 4
+     6.20ns INFO     test                                 LENGTH: 30
+     6.20ns INFO     test                                 PAYLOAD: [235, 32, 25, 130, 113, 254, 55, 178, 232, 86, 61, 114, 80, 23, 33, 217, 26, 62, 157, 207, 6, 225, 36, 37, 143, 96, 206, 178]
+     6.20ns INFO     test                               Filtering disabled
+     6.20ns INFO     test                               MONITOR0: Receiving packet on interface 0 (packet not filtered)
+     7.40ns INFO     test                               Processing packet:
+     7.40ns INFO     test                                 ADDRESS: 80
+     7.40ns INFO     test                                 LENGTH: 6
+     7.40ns INFO     test                                 PAYLOAD: [232, 187, 128, 245]
+     7.40ns INFO     test                               Address filtering, address: 09, mask: 92
+     7.40ns WARNING  ..b.Task 4.PacketIFMonitor.receive pop from empty list
+                                                        Traceback (most recent call last):
+                                                          File "/tmp/sim4_simsh_d2w5vu01/source/examples/pkt_switch/tests/test_pkt_switch.py", line 111, in receive
+                                                            self._recv(pkt)
+                                                            ~~~~~~~~~~^^^^^
+                                                          File "/tmp/sim4_simsh_d2w5vu01/source/examples/pkt_switch/tests/test_pkt_switch.py", line 98, in _recv
+                                                            callback(pkt)
+                                                            ~~~~~~~~^^^^^
+                                                          File "/tmp/sim4_simsh_d2w5vu01/source/examples/pkt_switch/tests/test_pkt_switch.py", line 170, in <lambda>
+                                                            monitor1.add_callback(lambda _ : scoreboarding(_, expected_data1))
+                                                                                             ~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^
+                                                          File "/tmp/sim4_simsh_d2w5vu01/source/examples/pkt_switch/tests/test_pkt_switch.py", line 167, in scoreboarding
+                                                            queue_expected.pop()
+                                                            ~~~~~~~~~~~~~~~~~~^^
+                                                        IndexError: pop from empty list
+     7.40ns WARNING  cocotb.regression                  test_pkt_switch.pkt_switch_test failed
+     7.40ns INFO     cocotb.regression                  *****************************************************************************************
+                                                        ** TEST                             STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
+                                                        *****************************************************************************************
+                                                        ** test_pkt_switch.pkt_switch_test   FAIL           7.40           0.23         32.33  **
+                                                        *****************************************************************************************
+                                                        ** TESTS=1 PASS=0 FAIL=1 SKIP=0                     7.40           0.24         31.25  **
+                                                        *****************************************************************************************
+FST info: dumpfile sim_build/pkt_switch.fst opened for output.
+make[1]: Leaving directory '/tmp/sim4_simsh_d2w5vu01/source/examples/pkt_switch/tests'
+
+--- STDERR ---
+/mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb_tools/makefiles/simulators/Makefile.icarus:66: Using MODULE is deprecated, please use COCOTB_TEST_MODULES instead.
+make[1]: *** [/mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb_tools/makefiles/simulators/Makefile.icarus:67: results.xml] Error 1
+make: *** [/mnt/d/ubc-capstone-26/data-pipeline/.venv/lib/python3.13/site-packages/cocotb_tools/makefiles/Makefile.inc:17: sim] Error 2

mciepluc_cocotb-coverage/sim_script_map.json

@@ -0,0 +1,6 @@
+{
+  "examples/fifo/tests/test_fifo.py": "fifo_mem_sim.sh",
+  "examples/pkt_switch/tests/test_pkt_switch.py": "pkt_switch_sim.sh",
+  "tests/test_coverage/coverage_test_main.py": "sample_module_sim.sh",
+  "tests/test_crv/crv_test_main.py": "sample_module_sim.sh"
+}

mciepluc_cocotb-coverage/simulations.jsonl

@@ -0,0 +1,4 @@
+{"tb_file_path": "examples/fifo/tests/test_fifo.py", "simulator": "cocotb", "top_module": "fifo_mem", "work_subdir": "examples/fifo/tests", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "fifo_mem", "MODULE": "test_fifo", "WAVES": "1", "PYTHONPATH": "../../.."}, "target": "", "clean_first": false}}
+{"tb_file_path": "examples/pkt_switch/tests/test_pkt_switch.py", "simulator": "cocotb", "top_module": "pkt_switch", "work_subdir": "examples/pkt_switch/tests", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "pkt_switch", "MODULE": "test_pkt_switch", "WAVES": "1", "PYTHONPATH": "../../.."}, "target": "", "clean_first": false}}
+{"tb_file_path": "tests/test_coverage/coverage_test_main.py", "simulator": "cocotb", "top_module": "sample_module", "work_subdir": "tests/test_coverage", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "sample_module", "MODULE": "coverage_test_main", "WAVES": "1", "PYTHONPATH": "../.."}, "target": "", "clean_first": false}}
+{"tb_file_path": "tests/test_crv/crv_test_main.py", "simulator": "cocotb", "top_module": "sample_module", "work_subdir": "tests/test_crv", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "sample_module", "MODULE": "crv_test_main", "WAVES": "1", "PYTHONPATH": "../.."}, "target": "", "clean_first": false}}

mciepluc_cocotb-coverage/testbenches.json

@@ -0,0 +1,42 @@
+[
+  {
+    "file_path": "examples/fifo/tests/test_fifo.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "examples/fifo/tests/Makefile",
+    "top_module": "fifo_mem",
+    "rtl_files": [
+      "examples/fifo/hdl/fifo.v"
+    ]
+  },
+  {
+    "file_path": "examples/pkt_switch/tests/test_pkt_switch.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "examples/pkt_switch/tests/Makefile",
+    "top_module": "pkt_switch",
+    "rtl_files": [
+      "examples/pkt_switch/hdl/pkt_switch.v"
+    ]
+  },
+  {
+    "file_path": "tests/test_coverage/coverage_test_main.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "tests/test_coverage/Makefile",
+    "top_module": "sample_module",
+    "rtl_files": [
+      "tests/sample_module.sv"
+    ]
+  },
+  {
+    "file_path": "tests/test_crv/crv_test_main.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "tests/test_crv/Makefile",
+    "top_module": "sample_module",
+    "rtl_files": [
+      "tests/sample_module.sv"
+    ]
+  }
+]