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0thbit_CRC_parallel/sim_script_map.json

@@ -0,0 +1,3 @@
+{
+  "CRC_tb.v": "tb_sim.sh"
+}

0thbit_CRC_parallel/simulations.jsonl

@@ -0,0 +1 @@
+{"tb_file_path": "CRC_tb.v", "simulator": "iverilog", "top_module": "tb", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["CRC.v", "CRC_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_crc.fst"}

0thbit_CRC_parallel/testbenches.json

@@ -0,0 +1,12 @@
+[
+  {
+    "file_path": "CRC_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "crc",
+    "rtl_files": [
+      "CRC.v"
+    ]
+  }
+]

0thbit_CRC_parallel/waveform_map.json

@@ -0,0 +1,3 @@
+{
+  "CRC_tb.v": "wave_crc.fst"
+}

Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/sim_script_map.json

@@ -0,0 +1,5 @@
+{
+  "Codes/testbench/tb_SPI.sv": "SPI_sim.sh",
+  "Codes/testbench/tb_instantiation.sv": "instantiation_sim.sh",
+  "Codes/testbench/tb_ram.sv": "RAM_sim.sh"
+}

Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/simulations.jsonl

@@ -0,0 +1,3 @@
+{"tb_file_path": "Codes/testbench/tb_SPI.sv", "simulator": "iverilog", "top_module": "SPI", "work_subdir": "Codes/testbench", "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Codes/testbench/tb_SPI.sv", "Codes/RTL/SPI.v"]}, "run": {"args": ["-fst"]}, "waveform": "Codes/testbench/wave_SPI.fst"}
+{"tb_file_path": "Codes/testbench/tb_instantiation.sv", "simulator": "iverilog", "top_module": "instantiation", "work_subdir": "Codes/testbench", "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Codes/testbench/tb_instantiation.sv", "Codes/RTL/instantiation.v", "Codes/RTL/SPI.v", "Codes/RTL/RAM.v"]}, "run": {"args": ["-fst"]}, "waveform": "Codes/testbench/wave_instantiation.fst"}
+{"tb_file_path": "Codes/testbench/tb_ram.sv", "simulator": "iverilog", "top_module": "RAM", "work_subdir": "Codes/testbench", "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Codes/testbench/tb_ram.sv", "Codes/RTL/RAM.v"]}, "run": {"args": ["-fst"]}, "waveform": "Codes/testbench/wave_RAM.fst"}

Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/testbenches.json

@@ -0,0 +1,34 @@
+[
+  {
+    "file_path": "Codes/testbench/tb_SPI.sv",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "SPI",
+    "rtl_files": [
+      "Codes/RTL/SPI.v"
+    ]
+  },
+  {
+    "file_path": "Codes/testbench/tb_instantiation.sv",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "instantiation",
+    "rtl_files": [
+      "Codes/RTL/instantiation.v",
+      "Codes/RTL/SPI.v",
+      "Codes/RTL/RAM.v"
+    ]
+  },
+  {
+    "file_path": "Codes/testbench/tb_ram.sv",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "RAM",
+    "rtl_files": [
+      "Codes/RTL/RAM.v"
+    ]
+  }
+]

Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/waveform_map.json

@@ -0,0 +1,5 @@
+{
+  "Codes/testbench/tb_SPI.sv": "Codes_testbench_wave_SPI.fst",
+  "Codes/testbench/tb_instantiation.sv": "Codes_testbench_wave_instantiation.fst",
+  "Codes/testbench/tb_ram.sv": "Codes_testbench_wave_RAM.fst"
+}

Vaibhav-Gunthe_Verilog-Projects/sim_script_map.json

@@ -0,0 +1,22 @@
+{
+  "ALU/alu_8bit_tb.v": "alu_8bit_sim.sh",
+  "Combinational-Circuits/4bit_Ripple-CarryAdder/Ripple_Carryadder_tb.v": "Ripple_carryadder_sim.sh",
+  "Combinational-Circuits/4x1_Mux/mux4x1_tb.v": "mux4x1_sim.sh",
+  "Combinational-Circuits/8bit-Barrel_Shifter/barrel_shifter8bit_tb.v": "barrel_shifter_8bit_sim.sh",
+  "Combinational-Circuits/Encoder_4x2/encoder4x2_tb.v": "encoder4x2_sim.sh",
+  "Combinational-Circuits/Full_Adder/tb_FullAdder.v": "Full_Adder_sim.sh",
+  "Combinational-Circuits/Full_Subtractor/Full_Subtractor_tb.v": "full_subtractor_sim.sh",
+  "Combinational-Circuits/Half_Adder/tb_HalfAdder.v": "Half_Adder_sim.sh",
+  "Combinational-Circuits/Half_Subtractor/Half_Subtractor_tb.v": "Half_subtractor_sim.sh",
+  "Combinational-Circuits/Multiplexer/Mux2x1_tb.v": "Mux2x1_sim.sh",
+  "Logic-Gates/And_Gate/testbench-And_Gate.v": "And_Gate_sim.sh",
+  "Logic-Gates/Nand_Gate/tb_Nand.v": "Nand_Gate_sim.sh",
+  "Logic-Gates/Nor_Gate/tb_Nor.v": "Nor_Gate_sim.sh",
+  "Logic-Gates/Not_Gate/tb_Not.v": "Not_Gate_sim.sh",
+  "Logic-Gates/OR_Gate/testbench-OR_Gate.v": "OR_Gate_sim.sh",
+  "Logic-Gates/X-NOR_Gate/tb_XNOR.v": "XNOR_Gate_sim.sh",
+  "Logic-Gates/X-OR_Gate/tb_XOR.v": "XOR_Gate_sim.sh",
+  "Sequential Circuits/8 bit twin register/twin_reg_8bit_tb.v": "twin_reg_8bit_sim.sh",
+  "Sequential Circuits/D_Flipflop/d_ff_asynchronous_reset_tb.v": "D_ff_basic_sim.sh",
+  "Sequential Circuits/D_Flipflop/d_ff_synchronous_reset_tb.v": "D_ff_synchronous_reset_sim.sh"
+}

Vaibhav-Gunthe_Verilog-Projects/simulations.jsonl

@@ -0,0 +1,20 @@
+{"tb_file_path": "ALU/alu_8bit_tb.v", "simulator": "iverilog", "top_module": "alu_8bit", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["ALU/8bit-ALU.v", "ALU/alu_8bit_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_alu_8bit.fst"}
+{"tb_file_path": "Combinational-Circuits/4bit_Ripple-CarryAdder/Ripple_Carryadder_tb.v", "simulator": "iverilog", "top_module": "Ripple_carryadder", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Combinational-Circuits/4bit_Ripple-CarryAdder/4bit_Ripple-CarryAdder.v", "Combinational-Circuits/4bit_Ripple-CarryAdder/Ripple_Carryadder_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "waveform.fst"}
+{"tb_file_path": "Combinational-Circuits/4x1_Mux/mux4x1_tb.v", "simulator": "iverilog", "top_module": "mux4x1", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Combinational-Circuits/4x1_Mux/4x1_mux.v", "Combinational-Circuits/4x1_Mux/mux4x1_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "waveform.fst"}
+{"tb_file_path": "Combinational-Circuits/8bit-Barrel_Shifter/barrel_shifter8bit_tb.v", "simulator": "iverilog", "top_module": "barrel_shifter_8bit", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Combinational-Circuits/8bit-Barrel_Shifter/8bit-Barrel_Shifter.v", "Combinational-Circuits/8bit-Barrel_Shifter/barrel_shifter8bit_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_barrel_shifter_8bit.fst"}
+{"tb_file_path": "Combinational-Circuits/Encoder_4x2/encoder4x2_tb.v", "simulator": "iverilog", "top_module": "encoder4x2", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Combinational-Circuits/Encoder_4x2/encoder4x2.v", "Combinational-Circuits/Encoder_4x2/encoder4x2_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_encoder4x2.fst"}
+{"tb_file_path": "Combinational-Circuits/Full_Adder/tb_FullAdder.v", "simulator": "iverilog", "top_module": "Full_Adder", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Combinational-Circuits/Full_Adder/Full_Adder.v", "Combinational-Circuits/Full_Adder/tb_FullAdder.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Combinational-Circuits/Full_Subtractor/Full_Subtractor_tb.v", "simulator": "iverilog", "top_module": "full_subtractor", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Combinational-Circuits/Full_Subtractor/full_subtractor.v", "Combinational-Circuits/Full_Subtractor/Full_Subtractor_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Combinational-Circuits/Half_Adder/tb_HalfAdder.v", "simulator": "iverilog", "top_module": "Half_Adder", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Combinational-Circuits/Half_Adder/Half-Adder.v", "Combinational-Circuits/Half_Adder/tb_HalfAdder.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Combinational-Circuits/Half_Subtractor/Half_Subtractor_tb.v", "simulator": "iverilog", "top_module": "Half_subtractor", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Combinational-Circuits/Half_Subtractor/Half_subtractor.v", "Combinational-Circuits/Half_Subtractor/Half_Subtractor_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Combinational-Circuits/Multiplexer/Mux2x1_tb.v", "simulator": "iverilog", "top_module": "Mux2x1", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Combinational-Circuits/Multiplexer/Mux2x1.v", "Combinational-Circuits/Multiplexer/Mux2x1_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Logic-Gates/And_Gate/testbench-And_Gate.v", "simulator": "iverilog", "top_module": "And_Gate", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Logic-Gates/And_Gate/And_Gate.v", "Logic-Gates/And_Gate/testbench-And_Gate.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Logic-Gates/Nand_Gate/tb_Nand.v", "simulator": "iverilog", "top_module": "Nand_Gate", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Logic-Gates/Nand_Gate/Nand_Gate.v", "Logic-Gates/Nand_Gate/tb_Nand.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Logic-Gates/Nor_Gate/tb_Nor.v", "simulator": "iverilog", "top_module": "Nor_Gate", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Logic-Gates/Nor_Gate/Nor_Gate.v", "Logic-Gates/Nor_Gate/tb_Nor.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Logic-Gates/Not_Gate/tb_Not.v", "simulator": "iverilog", "top_module": "Not_Gate", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Logic-Gates/Not_Gate/Not_Gate.v", "Logic-Gates/Not_Gate/tb_Not.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Logic-Gates/OR_Gate/testbench-OR_Gate.v", "simulator": "iverilog", "top_module": "OR_Gate", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Logic-Gates/OR_Gate/OR_Gate.v", "Logic-Gates/OR_Gate/testbench-OR_Gate.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Logic-Gates/X-NOR_Gate/tb_XNOR.v", "simulator": "iverilog", "top_module": "XNOR_Gate", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Logic-Gates/X-NOR_Gate/XNOR_Gate.v", "Logic-Gates/X-NOR_Gate/tb_XNOR.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Logic-Gates/X-OR_Gate/tb_XOR.v", "simulator": "iverilog", "top_module": "XOR_Gate", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Logic-Gates/X-OR_Gate/XOR_Gate.v", "Logic-Gates/X-OR_Gate/tb_XOR.v"]}, "run": {"args": ["-fst"]}, "waveform": "dump.fst"}
+{"tb_file_path": "Sequential Circuits/8 bit twin register/twin_reg_8bit_tb.v", "simulator": "iverilog", "top_module": "twin_reg_8bit", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Sequential Circuits/8 bit twin register/twin_reg_8bit.v", "Sequential Circuits/8 bit twin register/twin_reg_8bit_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_twin_reg_8bit.fst"}
+{"tb_file_path": "Sequential Circuits/D_Flipflop/d_ff_asynchronous_reset_tb.v", "simulator": "iverilog", "top_module": "D_ff_basic", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Sequential Circuits/D_Flipflop/d_ff_asynchronous_reset.v", "Sequential Circuits/D_Flipflop/d_ff_asynchronous_reset_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_D_ff_basic.fst"}
+{"tb_file_path": "Sequential Circuits/D_Flipflop/d_ff_synchronous_reset_tb.v", "simulator": "iverilog", "top_module": "D_ff_synchronous_reset", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Sequential Circuits/D_Flipflop/d_ff_synchronous_reset.v", "Sequential Circuits/D_Flipflop/d_ff_synchronous_reset_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_D_ff_synchronous_reset.fst"}

Vaibhav-Gunthe_Verilog-Projects/source/ALU/8bit-ALU.v

@@ -0,0 +1,32 @@
+`timescale 1ns / 1ps
+
+module alu_8bit(
+input [7:0]a,b,
+input[3:0]opcode,
+output reg [7:0]x,y
+    );
+    always@(a,b,opcode)
+    begin
+    x=8'b0;
+    y=8'b0;
+    case(opcode)
+    4'b0000 : x= {7'b0,&a};
+    4'b0001 : x= {7'b0,|a};
+    4'b0010 : x= {7'b0,^a};
+    4'b0011 : x= a&b;
+    4'b0100 : x= a|b;
+    4'b0101 : x= a^b;
+    4'b0110 : {y[0],x}= a+b;
+    4'b0111 : x= a-b;
+    4'b1000 : x= {7'b0,a>b};
+    4'b1001 : x= {7'b0,a<b};
+    4'b1010 : x[0]= !a;
+    4'b1011 : x[0]= a==b;
+    4'b1100 : {y,x}= a*b;
+    4'b1101 : {y,x}= a>>b;
+    4'b1110 : {y,x}= a<<b;
+    4'b1111 :  x = ~a;
+    default : $display("error");
+    endcase
+    end
+endmodule

Vaibhav-Gunthe_Verilog-Projects/source/ALU/alu_8bit_tb.v

@@ -0,0 +1,24 @@
+`timescale 1ns / 1ps
+
+
+module alu_8bit_tb;
+reg [7:0]a,b;
+reg [3:0]opcode;
+wire [7:0]x,y;
+
+alu_8bit dut(a,b,opcode,x,y);
+
+integer k;
+    initial begin 
+    $monitor("time=%0t a=%b b=%b opcode=%b x=%b y=%b",$time,a,b,opcode,x,y);
+       
+       a=8'b01010101;
+       b=8'b11000011;
+                for (k = 0; k < 16; k = k + 1) begin
+                    opcode = k [3:0] ;
+                    #10;
+        end
+        $finish;
+    end
+
+endmodule

Vaibhav-Gunthe_Verilog-Projects/source/Logic-Gates/And_Gate/And_Gate.v

@@ -0,0 +1,27 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 02/22/2025 09:47:52 AM
+// Design Name: 
+// Module Name: And_Gate
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module And_Gate(a,b,Y);
+input wire a,b;
+output wire Y;
+assign Y = a & b;
+endmodule

Vaibhav-Gunthe_Verilog-Projects/source/Logic-Gates/And_Gate/testbench-And_Gate.v

@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 02/22/2025 10:11:45 AM
+// Design Name: 
+// Module Name: testbench
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module testbench;
+reg a,b;
+wire Y;
+
+And_Gate uut(
+.a(a),
+.b(b),
+.Y(Y)
+);
+
+initial begin
+$dumpfile("dump.vcd");
+$dumpvars(0,testbench);
+
+$monitor("Time=%0t: a=%b b=%b Y=%b",$time,a,b,Y);
+
+a=0; b=0; #10;
+a=0; b=1; #10;
+a=1; b=0; #10;
+a=1; b=1; #10;
+
+$finish;
+end
+endmodule
+

Vaibhav-Gunthe_Verilog-Projects/source/Logic-Gates/Nand_Gate/Nand_Gate.v

@@ -0,0 +1,9 @@
+`timescale 1ns / 1ps
+
+
+module Nand_Gate(
+input a,b,
+output wire Y
+    );
+    assign Y=~(a&b);
+endmodule

Vaibhav-Gunthe_Verilog-Projects/source/README.md

@@ -0,0 +1,15 @@
+This repository contains a collection of Verilog-based digital design projects, ranging from fundamental logic gates to complex hardware modules.
+Ideal for learning RTL design, synthesis, and FPGA implementation.
+
+Projects Included  
+✔️ Basic Logic Gates  
+✔️ Multiplexers & Demultiplexers  
+✔️ Flip-Flops & Registers  
+✔️ ALU (Arithmetic Logic Unit)  
+✔️ FSM (Finite State Machines)  
+✔️ Memory Modules & More!  
+
+🔹 Tools Used: Icarus Verilog, ModelSim, Xilinx Vivado, GTKWave  
+🔹 For Beginners & Enthusiasts  
+
+💡 Contributions are welcome! 

Vaibhav-Gunthe_Verilog-Projects/source/Sequential Circuits/8 bit twin register/twin_reg_8bit.v

@@ -0,0 +1,19 @@
+`timescale 1ns / 1ps
+
+module twin_reg_8bit(
+input clk,rst,
+input [7:0]d1,
+input [7:0]d2,
+output reg[7:0]q1,
+output reg[7:0]q2 );
+
+always @(posedge clk)
+if (rst)begin
+q1 <=0;
+q2 <=0;
+end
+else begin 
+q1<=d1;
+q2<=d2;
+end
+endmodule

Vaibhav-Gunthe_Verilog-Projects/source/Sequential Circuits/8 bit twin register/twin_reg_8bit_tb.v

@@ -0,0 +1,23 @@
+`timescale 1ns / 1ps
+
+
+module twin_reg_8bit_tb;
+reg clk,rst;
+reg [7:0]d1,d2;
+wire[7:0]q1,q2;
+
+twin_reg_8bit dut(clk,rst,d1,d2,q1,q2);
+always #5 clk=~clk;
+initial begin
+clk=0; d1=0; d2=0; rst=1;
+$display("time clk rst d1 d2 q1 q2");
+$monitor("%0t clk=%b rst=%b d1=%b d2=%b q1=%b q2=%b",$time,clk,rst,d1,d2,q1,q2);
+#10 rst=0; 
+        #10 d1 = 8'b00000000; d2 = 8'b00000000;
+        #10 d1 = 8'b00000000; d2 = 8'b00000001;
+        #10 d1 = 8'b00000001; d2 = 8'b00000000;
+        #10 d1 = 8'b00000001; d2 = 8'b00000001;
+$finish;
+
+end
+endmodule

Vaibhav-Gunthe_Verilog-Projects/source/Sequential Circuits/D_Flipflop/d_ff_asynchronous_reset.v

@@ -0,0 +1,13 @@
+`timescale 1ns / 1ps
+
+module D_ff_basic(
+input d,clk,rst,
+output reg q
+    );
+    always @(posedge clk or posedge rst)
+    if(rst)
+    q<=0;
+    else 
+    q<=d;
+    
+endmodule

Vaibhav-Gunthe_Verilog-Projects/source/Sequential Circuits/D_Flipflop/d_ff_asynchronous_reset_tb.v

@@ -0,0 +1,25 @@
+`timescale 1ns / 1ps
+
+
+module D_ff_basic_tb;
+reg d,clk,rst;
+wire q;
+
+D_ff_basic dut(d,clk,rst,q);
+always #5 clk=~clk;
+
+initial begin
+d=0; clk=0; rst=1;
+$display("time d clk rst q ");
+$monitor("time d clk rst q",$time,d,clk,rst,q);
+
+#10 rst=0;
+  #10 d = 1;
+  #10 d = 0;
+  #10 d = 1;
+  #10 d = 0;
+  #10;
+
+$finish;
+end
+endmodule

Vaibhav-Gunthe_Verilog-Projects/source/Sequential Circuits/D_Flipflop/d_ff_synchronous_reset.v

@@ -0,0 +1,13 @@
+`timescale 1ns / 1ps
+
+module D_ff_synchronous_reset(
+input d,clk,rst,
+output reg q
+    );
+    always @(posedge clk )
+    if(rst)
+    q<=0;
+    else 
+    q<=d;
+    
+endmodule

Vaibhav-Gunthe_Verilog-Projects/source/Sequential Circuits/D_Flipflop/d_ff_synchronous_reset_tb.v

@@ -0,0 +1,25 @@
+`timescale 1ns / 1ps
+
+
+module d_ff_synchronous_tb;
+reg d,clk,rst;
+wire q;
+
+D_ff_synchronous_reset dut(d,clk,rst,q);
+always #5 clk=~clk;
+
+initial begin
+d=0; clk=0; rst=1;
+$display("time d clk rst q ");
+$monitor("time d clk rst q",$time,d,clk,rst,q);
+
+#10 rst=0;
+  #10 d = 1;
+  #10 d = 0;
+  #10 d = 1;
+  #10 d = 0;
+  #10;
+
+$finish;
+end
+endmodule

Vaibhav-Gunthe_Verilog-Projects/source/Sequential Circuits/T_Flipflop/T_ff_asynchronousReset.v

@@ -0,0 +1 @@
+T

Vaibhav-Gunthe_Verilog-Projects/testbenches.json

@@ -0,0 +1,202 @@
+[
+  {
+    "file_path": "ALU/alu_8bit_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "alu_8bit",
+    "rtl_files": [
+      "ALU/8bit-ALU.v"
+    ]
+  },
+  {
+    "file_path": "Combinational-Circuits/4bit_Ripple-CarryAdder/Ripple_Carryadder_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "Ripple_carryadder",
+    "rtl_files": [
+      "Combinational-Circuits/4bit_Ripple-CarryAdder/4bit_Ripple-CarryAdder.v"
+    ]
+  },
+  {
+    "file_path": "Combinational-Circuits/4x1_Mux/mux4x1_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "mux4x1",
+    "rtl_files": [
+      "Combinational-Circuits/4x1_Mux/4x1_mux.v"
+    ]
+  },
+  {
+    "file_path": "Combinational-Circuits/8bit-Barrel_Shifter/barrel_shifter8bit_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "barrel_shifter_8bit",
+    "rtl_files": [
+      "Combinational-Circuits/8bit-Barrel_Shifter/8bit-Barrel_Shifter.v"
+    ]
+  },
+  {
+    "file_path": "Combinational-Circuits/Encoder_4x2/encoder4x2_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "encoder4x2",
+    "rtl_files": [
+      "Combinational-Circuits/Encoder_4x2/encoder4x2.v"
+    ]
+  },
+  {
+    "file_path": "Combinational-Circuits/Full_Adder/tb_FullAdder.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "Full_Adder",
+    "rtl_files": [
+      "Combinational-Circuits/Full_Adder/Full_Adder.v"
+    ]
+  },
+  {
+    "file_path": "Combinational-Circuits/Full_Subtractor/Full_Subtractor_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "full_subtractor",
+    "rtl_files": [
+      "Combinational-Circuits/Full_Subtractor/full_subtractor.v"
+    ]
+  },
+  {
+    "file_path": "Combinational-Circuits/Half_Adder/tb_HalfAdder.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "Half_Adder",
+    "rtl_files": [
+      "Combinational-Circuits/Half_Adder/Half-Adder.v"
+    ]
+  },
+  {
+    "file_path": "Combinational-Circuits/Half_Subtractor/Half_Subtractor_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "Half_subtractor",
+    "rtl_files": [
+      "Combinational-Circuits/Half_Subtractor/Half_subtractor.v"
+    ]
+  },
+  {
+    "file_path": "Combinational-Circuits/Multiplexer/Mux2x1_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "Mux2x1",
+    "rtl_files": [
+      "Combinational-Circuits/Multiplexer/Mux2x1.v"
+    ]
+  },
+  {
+    "file_path": "Logic-Gates/And_Gate/testbench-And_Gate.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "And_Gate",
+    "rtl_files": [
+      "Logic-Gates/And_Gate/And_Gate.v"
+    ]
+  },
+  {
+    "file_path": "Logic-Gates/Nand_Gate/tb_Nand.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "Nand_Gate",
+    "rtl_files": [
+      "Logic-Gates/Nand_Gate/Nand_Gate.v"
+    ]
+  },
+  {
+    "file_path": "Logic-Gates/Nor_Gate/tb_Nor.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "Nor_Gate",
+    "rtl_files": [
+      "Logic-Gates/Nor_Gate/Nor_Gate.v"
+    ]
+  },
+  {
+    "file_path": "Logic-Gates/Not_Gate/tb_Not.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "Not_Gate",
+    "rtl_files": [
+      "Logic-Gates/Not_Gate/Not_Gate.v"
+    ]
+  },
+  {
+    "file_path": "Logic-Gates/OR_Gate/testbench-OR_Gate.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "OR_Gate",
+    "rtl_files": [
+      "Logic-Gates/OR_Gate/OR_Gate.v"
+    ]
+  },
+  {
+    "file_path": "Logic-Gates/X-NOR_Gate/tb_XNOR.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "XNOR_Gate",
+    "rtl_files": [
+      "Logic-Gates/X-NOR_Gate/XNOR_Gate.v"
+    ]
+  },
+  {
+    "file_path": "Logic-Gates/X-OR_Gate/tb_XOR.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "XOR_Gate",
+    "rtl_files": [
+      "Logic-Gates/X-OR_Gate/XOR_Gate.v"
+    ]
+  },
+  {
+    "file_path": "Sequential Circuits/8 bit twin register/twin_reg_8bit_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "twin_reg_8bit",
+    "rtl_files": [
+      "Sequential Circuits/8 bit twin register/twin_reg_8bit.v"
+    ]
+  },
+  {
+    "file_path": "Sequential Circuits/D_Flipflop/d_ff_asynchronous_reset_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "D_ff_basic",
+    "rtl_files": [
+      "Sequential Circuits/D_Flipflop/d_ff_asynchronous_reset.v"
+    ]
+  },
+  {
+    "file_path": "Sequential Circuits/D_Flipflop/d_ff_synchronous_reset_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "D_ff_synchronous_reset",
+    "rtl_files": [
+      "Sequential Circuits/D_Flipflop/d_ff_synchronous_reset.v"
+    ]
+  }
+]

Vaibhav-Gunthe_Verilog-Projects/waveform_map.json

@@ -0,0 +1,22 @@
+{
+  "ALU/alu_8bit_tb.v": "wave_alu_8bit.fst",
+  "Combinational-Circuits/4bit_Ripple-CarryAdder/Ripple_Carryadder_tb.v": "waveform.fst",
+  "Combinational-Circuits/4x1_Mux/mux4x1_tb.v": "waveform.fst",
+  "Combinational-Circuits/8bit-Barrel_Shifter/barrel_shifter8bit_tb.v": "wave_barrel_shifter_8bit.fst",
+  "Combinational-Circuits/Encoder_4x2/encoder4x2_tb.v": "wave_encoder4x2.fst",
+  "Combinational-Circuits/Full_Adder/tb_FullAdder.v": "dump.fst",
+  "Combinational-Circuits/Full_Subtractor/Full_Subtractor_tb.v": "dump.fst",
+  "Combinational-Circuits/Half_Adder/tb_HalfAdder.v": "dump.fst",
+  "Combinational-Circuits/Half_Subtractor/Half_Subtractor_tb.v": "dump.fst",
+  "Combinational-Circuits/Multiplexer/Mux2x1_tb.v": "dump.fst",
+  "Logic-Gates/And_Gate/testbench-And_Gate.v": "dump.fst",
+  "Logic-Gates/Nand_Gate/tb_Nand.v": "dump.fst",
+  "Logic-Gates/Nor_Gate/tb_Nor.v": "dump.fst",
+  "Logic-Gates/Not_Gate/tb_Not.v": "dump.fst",
+  "Logic-Gates/OR_Gate/testbench-OR_Gate.v": "dump.fst",
+  "Logic-Gates/X-NOR_Gate/tb_XNOR.v": "dump.fst",
+  "Logic-Gates/X-OR_Gate/tb_XOR.v": "dump.fst",
+  "Sequential Circuits/8 bit twin register/twin_reg_8bit_tb.v": "wave_twin_reg_8bit.fst",
+  "Sequential Circuits/D_Flipflop/d_ff_asynchronous_reset_tb.v": "wave_D_ff_basic.fst",
+  "Sequential Circuits/D_Flipflop/d_ff_synchronous_reset_tb.v": "wave_D_ff_synchronous_reset.fst"
+}

accomdemy_accomdemy_rv32i/sim_script_map.json

@@ -0,0 +1,3 @@
+{
+  "sim/cpu_tb.v": "cpu_sim.sh"
+}

accomdemy_accomdemy_rv32i/simulations.jsonl

@@ -0,0 +1 @@
+{"tb_file_path": "sim/cpu_tb.v", "simulator": "iverilog", "top_module": "cpu", "work_subdir": "sim", "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["src/cpu.v", "src/MUX2to1_32bit.v", "src/MUX4to1_32bit.v", "src/alu.v", "src/branch.v", "src/decoder.v", "src/dm_control.v", "src/instr_memory.v", "src/pc.v", "src/regfile.v", "sim/cpu_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "sim/wave_cpu.fst"}

accomdemy_accomdemy_rv32i/testbenches.json

@@ -0,0 +1,21 @@
+[
+  {
+    "file_path": "sim/cpu_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "cpu",
+    "rtl_files": [
+      "src/cpu.v",
+      "src/MUX2to1_32bit.v",
+      "src/MUX4to1_32bit.v",
+      "src/alu.v",
+      "src/branch.v",
+      "src/decoder.v",
+      "src/dm_control.v",
+      "src/instr_memory.v",
+      "src/pc.v",
+      "src/regfile.v"
+    ]
+  }
+]

accomdemy_accomdemy_rv32i/waveform_map.json

@@ -0,0 +1,3 @@
+{
+  "sim/cpu_tb.v": "sim_wave_cpu.fst"
+}

akira2963753_Pipelined-RV32-SoC/sim_script_map.json

@@ -0,0 +1,3 @@
+{
+  "Five-Stage-Pipelined-CPU/RTL/RISCV_CPU_tb.v": "RISCV_CPU_sim.sh"
+}

akira2963753_Pipelined-RV32-SoC/simulations.jsonl

@@ -0,0 +1 @@
+{"tb_file_path": "Five-Stage-Pipelined-CPU/RTL/RISCV_CPU_tb.v", "simulator": "iverilog", "top_module": "RISCV_CPU", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012", "-I", "Five-Stage-Pipelined-CPU/RTL"], "sources": ["Five-Stage-Pipelined-CPU/RTL/RISCV_CPU_tb.v", "Five-Stage-Pipelined-CPU/RTL/RISCV_CPU.v", "Five-Stage-Pipelined-CPU/RTL/ALU.v", "Five-Stage-Pipelined-CPU/RTL/ALU_Control.v", "Five-Stage-Pipelined-CPU/RTL/BHT.v", "Five-Stage-Pipelined-CPU/RTL/BPU.v", "Five-Stage-Pipelined-CPU/RTL/BTB.v", "Five-Stage-Pipelined-CPU/RTL/CSR.v", "Five-Stage-Pipelined-CPU/RTL/Control.v", "Five-Stage-Pipelined-CPU/RTL/D_Mem.v", "Five-Stage-Pipelined-CPU/RTL/EX_MEM.v", "Five-Stage-Pipelined-CPU/RTL/Forwarding_Unit.v", "Five-Stage-Pipelined-CPU/RTL/Hazard_Unit.v", "Five-Stage-Pipelined-CPU/RTL/ID_EX.v", "Five-Stage-Pipelined-CPU/RTL/IF_ID.v", "Five-Stage-Pipelined-CPU/RTL/I_Mem.v", "Five-Stage-Pipelined-CPU/RTL/ImmGen.v", "Five-Stage-Pipelined-CPU/RTL/LDU.v", "Five-Stage-Pipelined-CPU/RTL/MEM_WB.v", "Five-Stage-Pipelined-CPU/RTL/PC.v", "Five-Stage-Pipelined-CPU/RTL/PC_Adderr.v", "Five-Stage-Pipelined-CPU/RTL/RF.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_RISCV_CPU.fst"}

akira2963753_Pipelined-RV32-SoC/testbenches.json

@@ -0,0 +1,101 @@
+[
+  {
+    "file_path": "Five-Stage-Pipelined-CPU/RTL/RISCV_CPU_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "RISCV_CPU",
+    "rtl_files": [
+      "Five-Stage-Pipelined-CPU/RTL/RISCV_CPU.v",
+      "Five-Stage-Pipelined-CPU/RTL/ALU.v",
+      "Five-Stage-Pipelined-CPU/RTL/ALU_Control.v",
+      "Five-Stage-Pipelined-CPU/RTL/BHT.v",
+      "Five-Stage-Pipelined-CPU/RTL/BPU.v",
+      "Five-Stage-Pipelined-CPU/RTL/BTB.v",
+      "Five-Stage-Pipelined-CPU/RTL/CSR.v",
+      "Five-Stage-Pipelined-CPU/RTL/Control.v",
+      "Five-Stage-Pipelined-CPU/RTL/D_Mem.v",
+      "Five-Stage-Pipelined-CPU/RTL/EX_MEM.v",
+      "Five-Stage-Pipelined-CPU/RTL/Forwarding_Unit.v",
+      "Five-Stage-Pipelined-CPU/RTL/Hazard_Unit.v",
+      "Five-Stage-Pipelined-CPU/RTL/ID_EX.v",
+      "Five-Stage-Pipelined-CPU/RTL/IF_ID.v",
+      "Five-Stage-Pipelined-CPU/RTL/I_Mem.v",
+      "Five-Stage-Pipelined-CPU/RTL/ImmGen.v",
+      "Five-Stage-Pipelined-CPU/RTL/LDU.v",
+      "Five-Stage-Pipelined-CPU/RTL/MEM_WB.v",
+      "Five-Stage-Pipelined-CPU/RTL/PC.v",
+      "Five-Stage-Pipelined-CPU/RTL/PC_Adderr.v",
+      "Five-Stage-Pipelined-CPU/RTL/RF.v"
+    ]
+  },
+  {
+    "file_path": "RISC-V-Processor/RTL/RISCV_PROCESSOR_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "RISCV_PROCESSOR",
+    "rtl_files": [
+      "RISC-V-Processor/RTL/RISCV_PROCESSOR.v",
+      "RISC-V-Processor/RTL/RISCV_CPU.v",
+      "RISC-V-Processor/RTL/ALU.v",
+      "RISC-V-Processor/RTL/ALU_Control.v",
+      "RISC-V-Processor/RTL/AXI4_Lite_Bus.v",
+      "RISC-V-Processor/RTL/BHT.v",
+      "RISC-V-Processor/RTL/BPU.v",
+      "RISC-V-Processor/RTL/BTB.v",
+      "RISC-V-Processor/RTL/CSR.v",
+      "RISC-V-Processor/RTL/Control.v",
+      "RISC-V-Processor/RTL/D_BRAM.v",
+      "RISC-V-Processor/RTL/D_Cache.v",
+      "RISC-V-Processor/RTL/D_Mem.v",
+      "RISC-V-Processor/RTL/EX_MEM.v",
+      "RISC-V-Processor/RTL/Forwarding_Unit.v",
+      "RISC-V-Processor/RTL/Hazard_Unit.v",
+      "RISC-V-Processor/RTL/ID_EX.v",
+      "RISC-V-Processor/RTL/IF_ID.v",
+      "RISC-V-Processor/RTL/I_Cache.v",
+      "RISC-V-Processor/RTL/ImmGen.v",
+      "RISC-V-Processor/RTL/LDU.v",
+      "RISC-V-Processor/RTL/MEM_WB.v",
+      "RISC-V-Processor/RTL/PC.v",
+      "RISC-V-Processor/RTL/PC_Adder.v",
+      "RISC-V-Processor/RTL/RF.v"
+    ]
+  },
+  {
+    "file_path": "CACHE/AXI4-LITE/Pattern.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "Tested",
+    "rtl_files": [
+      "CACHE/AXI4-LITE/Tested.v",
+      "CACHE/AXI4-LITE/AXI4_Lite_Bus.v"
+    ]
+  },
+  {
+    "file_path": "CACHE/D-CACHE/Pattern.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "Tested",
+    "rtl_files": [
+      "CACHE/D-CACHE/Tested.v",
+      "CACHE/D-CACHE/D_Cache.v",
+      "CACHE/D-CACHE/AXI4_Lite_Bus.v"
+    ]
+  },
+  {
+    "file_path": "CACHE/I-CACHE/Pattern.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "Tested",
+    "rtl_files": [
+      "CACHE/I-CACHE/Tested.v",
+      "CACHE/I-CACHE/Cache.v",
+      "CACHE/I-CACHE/AXI4_Lite_Bus.v"
+    ]
+  }
+]

akira2963753_Pipelined-RV32-SoC/waveform_map.json

@@ -0,0 +1,3 @@
+{
+  "Five-Stage-Pipelined-CPU/RTL/RISCV_CPU_tb.v": "wave_RISCV_CPU.fst"
+}

completed.json

@@ -1,10 +1,7 @@
 {
   "version": 2,
-  "generated_at": "2026-04-03T17:33:26.562108+00:00",
+  "generated_at": "2026-04-05T06:13:41.879376+00:00",
   "entries": {
-    "0thbit_CRC_parallel/crc__CRC/operator_typo": {
-      "status": "sim_ok"
-    },
     "chili-chips-ba_wireguard-fpga/led_test__led_test/blocking_nonblocking": {
       "status": "sim_ok",
       "examples_count": 0
@@ -362,19 +359,6 @@
     "mnmhdanas_UART-protocol/UARTtb__transmitter/unconnected_port": {
       "status": "sim_ok"
     },
-    "Vaibhav-Gunthe_Verilog-Projects/D_ff_synchronous_reset__d_ff_synchronous_reset/blocking_nonblocking": {
-      "status": "sim_ok",
-      "examples_count": 0
-    },
-    "Vaibhav-Gunthe_Verilog-Projects/alu_8bit__8bit-ALU/case_swap": {
-      "status": "sim_ok"
-    },
-    "Vaibhav-Gunthe_Verilog-Projects/alu_8bit__8bit-ALU/concat_swap": {
-      "status": "sim_ok"
-    },
-    "Vaibhav-Gunthe_Verilog-Projects/twin_reg_8bit__twin_reg_8bit/blocking_nonblocking": {
-      "status": "sim_ok"
-    },
     "Fraunhofer-IMS_airisc_core_complex/airi5c_spi__airi5c_spi/case_swap": {
       "status": "llm_failed"
     },
@@ -561,225 +545,6 @@
     "meiniKi_FazyRV/fazyrv_top__fazyrv_rf/missing_reset": {
       "status": "sim_failed"
     },
-    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/delayed_signal": {
-      "status": "sim_ok"
-    },
-    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/inverted_condition": {
-      "status": "sim_ok"
-    },
-    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/missing_reset": {
-      "status": "sim_ok"
-    },
-    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/state_transition": {
-      "status": "sim_ok"
-    },
-    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/case_swap": {
-      "status": "sim_ok"
-    },
-    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/concat_swap": {
-      "status": "sim_ok"
-    },
-    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/delayed_signal": {
-      "status": "sim_ok"
-    },
-    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/inverted_condition": {
-      "status": "sim_ok"
-    },
-    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/missing_reset": {
-      "status": "sim_ok"
-    },
-    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/operator_typo": {
-      "status": "sim_ok"
-    },
-    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/signal_typo": {
-      "status": "compile_error"
-    },
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-    "JN513_Risco-5/Core__core/missing_reset": {
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-    "JN513_Risco-5/Core__csr_unit/missing_enable": {
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-    },
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-    },
-    "JN513_Risco-5/Core__mdu/concat_swap": {
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-    },
-    "JN513_Risco-5/Core__mdu/delayed_signal": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__mdu/inverted_condition": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__mdu/missing_enable": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__mdu/missing_reset": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__memory/blocking_nonblocking": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__memory/case_swap": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__memory/concat_swap": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__memory/delayed_signal": {
-      "status": "llm_failed"
-    },
-    "JN513_Risco-5/Core__memory/inverted_condition": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__memory/missing_enable": {
-      "status": "sim_ok"
-    },
-    "JN513_Risco-5/Core__mux/case_swap": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__mux/delayed_signal": {
-      "status": "llm_failed"
-    },
-    "JN513_Risco-5/Core__pc/blocking_nonblocking": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__pc/delayed_signal": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__pc/missing_enable": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__pc/missing_reset": {
-      "status": "sim_ok"
-    },
-    "JN513_Risco-5/Core__registers/blocking_nonblocking": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__registers/delayed_signal": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__registers/missing_enable": {
-      "status": "waveform_identical"
-    },
-    "JN513_Risco-5/Core__registers/missing_reset": {
-      "status": "waveform_identical"
-    },
     "Mr-Bossman_KISC-V/AXI4Lite_translator__axi/blocking_nonblocking": {
       "status": "waveform_identical"
     },
@@ -1107,293 +872,242 @@
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Writeback_Cycle/unconnected_port": {
       "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__MUX2to1_32bit/delayed_signal": {
+    "thejefflarson_little-cpu/littlecpu__accessor/blocking_nonblocking": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__MUX4to1_32bit/case_swap": {
+    "thejefflarson_little-cpu/littlecpu__accessor/case_swap": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__MUX4to1_32bit/delayed_signal": {
-      "status": "waveform_identical"
+    "thejefflarson_little-cpu/littlecpu__decoder/blocking_nonblocking": {
+      "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__alu/case_swap": {
+    "thejefflarson_little-cpu/littlecpu__decoder/case_swap": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__alu/delayed_signal": {
+    "thejefflarson_little-cpu/littlecpu__executor/blocking_nonblocking": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__alu/operator_typo": {
+    "thejefflarson_little-cpu/littlecpu__executor/case_swap": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__branch/case_swap": {
-      "status": "waveform_identical"
+    "thejefflarson_little-cpu/littlecpu__regfile/blocking_nonblocking": {
+      "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__branch/delayed_signal": {
-      "status": "compile_error"
+    "0thbit_CRC_parallel/crc__CRC/operator_typo": {
+      "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__branch/missing_else_latch": {
-      "status": "waveform_identical"
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/concat_swap": {
+      "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__branch/missing_enable": {
-      "status": "waveform_identical"
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/inverted_condition": {
+      "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__branch/operator_typo": {
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/missing_enable": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__cpu/signal_typo": {
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/missing_reset": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__cpu/unconnected_port": {
-      "status": "waveform_identical"
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/off_by_one_counter": {
+      "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__decoder/case_swap": {
-      "status": "waveform_identical"
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/operator_typo": {
+      "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__decoder/concat_swap": {
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/state_transition": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__decoder/delayed_signal": {
-      "status": "llm_failed"
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/wrong_bitwidth": {
+      "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__dm_control/case_swap": {
-      "status": "waveform_identical"
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__RAM/inverted_condition": {
+      "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__dm_control/concat_swap": {
-      "status": "waveform_identical"
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__RAM/missing_enable": {
+      "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__dm_control/delayed_signal": {
-      "status": "waveform_identical"
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__RAM/missing_reset": {
+      "status": "sim_ok"
     },
-    "accomdemy_accomdemy_rv32i/cpu__dm_control/inverted_condition": {
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__RAM/operator_typo": {
+      "status": "sim_ok"
+    },
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__RAM/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__instantiation/unconnected_port": {
+      "status": "sim_ok"
+    },
+    "JN513_Risco-5/ClkDivider__clk_divider/inverted_condition": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__dm_control/missing_else_latch": {
+    "JN513_Risco-5/ClkDivider__clk_divider/missing_enable": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__dm_control/missing_enable": {
+    "JN513_Risco-5/ClkDivider__clk_divider/missing_reset": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__dm_control/signal_typo": {
-      "status": "compile_error"
+    "JN513_Risco-5/ClkDivider__clk_divider/operator_typo": {
+      "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__dm_control/unconnected_port": {
+    "JN513_Risco-5/ClkDivider__clk_divider/wrong_bitwidth": {
       "status": "waveform_identical"
     },
-    "accomdemy_accomdemy_rv32i/cpu__dm_control/wrong_bitwidth": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__instr_memory/concat_swap": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__instr_memory/delayed_signal": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__instr_memory/wrong_bitwidth": {
-      "status": "sim_ok"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__pc/blocking_nonblocking": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__pc/delayed_signal": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__pc/missing_reset": {
-      "status": "compile_error"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__pc/operator_typo": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__regfile/delayed_signal": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__regfile/inverted_condition": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__regfile/missing_else_latch": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__regfile/missing_enable": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__regfile/missing_reset": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__regfile/operator_typo": {
-      "status": "waveform_identical"
-    },
-    "accomdemy_accomdemy_rv32i/cpu__regfile/wrong_bitwidth": {
-      "status": "waveform_identical"
-    },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU/case_swap": {
-      "status": "compile_error"
-    },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU/operator_typo": {
-      "status": "compile_error"
-    },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU_Control/case_swap": {
-      "status": "compile_error"
-    },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BHT/blocking_nonblocking": {
-      "status": "compile_error"
-    },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BHT/missing_reset": {
-      "status": "compile_error"
-    },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BHT/operator_typo": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__alu/case_swap": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BPU/case_swap": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__alu/operator_typo": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BTB/blocking_nonblocking": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__alu_control/case_swap": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BTB/missing_reset": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__alu_control/inverted_condition": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/blocking_nonblocking": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__alu_control/operator_typo": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/case_swap": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__bus/operator_typo": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/missing_enable": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__control_unit/case_swap": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/missing_reset": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__control_unit/inverted_condition": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/operator_typo": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__control_unit/missing_enable": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/case_swap": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__control_unit/missing_reset": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/inverted_condition": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__control_unit/operator_typo": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/missing_else_latch": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__control_unit/state_transition": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/operator_typo": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__control_unit/wrong_bitwidth": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/blocking_nonblocking": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__core/inverted_condition": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/concat_swap": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__core/missing_enable": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/inverted_condition": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__core/missing_reset": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/missing_enable": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__core/operator_typo": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__EX_MEM/blocking_nonblocking": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__core/unconnected_port": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__EX_MEM/missing_reset": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__core/wrong_bitwidth": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Forwarding_Unit/inverted_condition": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__csr_unit/case_swap": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Forwarding_Unit/missing_else_latch": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__csr_unit/concat_swap": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Forwarding_Unit/operator_typo": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__csr_unit/inverted_condition": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Hazard_Unit/missing_else_latch": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__csr_unit/missing_enable": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Hazard_Unit/operator_typo": {
-      "status": "compile_error"
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     },
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     },
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     },
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     },
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     },
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     },
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     },
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     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__LDU/case_swap": {
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     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__MEM_WB/blocking_nonblocking": {
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     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__MEM_WB/missing_reset": {
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     },
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     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC/case_swap": {
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     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC/missing_reset": {
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     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC_Adderr/missing_else_latch": {
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     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/blocking_nonblocking": {
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     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/missing_enable": {
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+    "JN513_Risco-5/Core__memory/missing_enable": {
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     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/missing_reset": {
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+    "JN513_Risco-5/Core__memory/operator_typo": {
+      "status": "sim_failed"
     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/operator_typo": {
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+    "JN513_Risco-5/Core__memory/wrong_bitwidth": {
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     },
-    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RISCV_CPU/operator_typo": {
-      "status": "compile_error"
+    "JN513_Risco-5/Core__mux/case_swap": {
+      "status": "sim_failed"
     },
-    "thejefflarson_little-cpu/littlecpu__accessor/blocking_nonblocking": {
-      "status": "waveform_identical"
+    "JN513_Risco-5/Core__pc/missing_enable": {
+      "status": "sim_failed"
     },
-    "thejefflarson_little-cpu/littlecpu__accessor/case_swap": {
-      "status": "waveform_identical"
+    "JN513_Risco-5/Core__pc/missing_reset": {
+      "status": "sim_failed"
     },
-    "thejefflarson_little-cpu/littlecpu__decoder/blocking_nonblocking": {
-      "status": "sim_ok"
+    "JN513_Risco-5/Core__pc/operator_typo": {
+      "status": "sim_failed"
     },
-    "thejefflarson_little-cpu/littlecpu__decoder/case_swap": {
-      "status": "waveform_identical"
+    "JN513_Risco-5/Core__registers/missing_enable": {
+      "status": "sim_failed"
     },
-    "thejefflarson_little-cpu/littlecpu__executor/blocking_nonblocking": {
-      "status": "waveform_identical"
+    "JN513_Risco-5/Core__registers/missing_reset": {
+      "status": "sim_failed"
     },
-    "thejefflarson_little-cpu/littlecpu__executor/case_swap": {
-      "status": "waveform_identical"
+    "JN513_Risco-5/Core__registers/operator_typo": {
+      "status": "sim_failed"
     },
-    "thejefflarson_little-cpu/littlecpu__regfile/blocking_nonblocking": {
-      "status": "sim_ok"
+    "JN513_Risco-5/Core__registers/wrong_bitwidth": {
+      "status": "sim_failed"
     },
     "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Master/inverted_condition": {
       "status": "sim_ok"
@@ -1476,6 +1190,27 @@
     "OrsuVenkataKrishnaiah1235_RTL-Coding/srff__srff/operator_typo": {
       "status": "waveform_identical"
     },
+    "Vaibhav-Gunthe_Verilog-Projects/D_ff_synchronous_reset__d_ff_synchronous_reset/missing_reset": {
+      "status": "waveform_identical"
+    },
+    "Vaibhav-Gunthe_Verilog-Projects/alu_8bit__8bit-ALU/case_swap": {
+      "status": "sim_ok"
+    },
+    "Vaibhav-Gunthe_Verilog-Projects/alu_8bit__8bit-ALU/concat_swap": {
+      "status": "sim_ok"
+    },
+    "Vaibhav-Gunthe_Verilog-Projects/alu_8bit__8bit-ALU/operator_typo": {
+      "status": "sim_ok"
+    },
+    "Vaibhav-Gunthe_Verilog-Projects/barrel_shifter_8bit__8bit-Barrel_Shifter/operator_typo": {
+      "status": "sim_ok"
+    },
+    "Vaibhav-Gunthe_Verilog-Projects/encoder4x2__encoder4x2/operator_typo": {
+      "status": "sim_ok"
+    },
+    "Vaibhav-Gunthe_Verilog-Projects/twin_reg_8bit__twin_reg_8bit/missing_reset": {
+      "status": "sim_ok"
+    },
     "Weiyet_RTLStructLib/doubly_linked_list__doubly_linked_list/inverted_condition": {
       "status": "sim_ok"
     },
@@ -1623,24 +1358,240 @@
     "Weiyet_RTLStructLib/singly_linked_list__singly_linked_list/wrong_bitwidth": {
       "status": "waveform_identical"
     },
-    "aditeyabaral_DDCO-Lab-UE18CS207/alu__lib/operator_typo": {
+    "accomdemy_accomdemy_rv32i/cpu__MUX4to1_32bit/case_swap": {
       "status": "waveform_identical"
     },
-    "aditeyabaral_DDCO-Lab-UE18CS207/fa4__lib/operator_typo": {
-      "status": "waveform_identical"
+    "accomdemy_accomdemy_rv32i/cpu__alu/case_swap": {
+      "status": "sim_ok"
     },
-    "aditeyabaral_DDCO-Lab-UE18CS207/mproc_mem__lib/operator_typo": {
+    "accomdemy_accomdemy_rv32i/cpu__alu/operator_typo": {
       "status": "waveform_identical"
     },
-    "aditeyabaral_DDCO-Lab-UE18CS207/mproc_mem__mproc_mem/wrong_bitwidth": {
+    "accomdemy_accomdemy_rv32i/cpu__branch/case_swap": {
       "status": "waveform_identical"
     },
-    "aditeyabaral_DDCO-Lab-UE18CS207/pc__lib/operator_typo": {
-      "status": "waveform_identical"
+    "accomdemy_accomdemy_rv32i/cpu__branch/missing_enable": {
+      "status": "sim_ok"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__branch/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__cpu/unconnected_port": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__decoder/case_swap": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__decoder/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__dm_control/case_swap": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__dm_control/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__dm_control/inverted_condition": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__dm_control/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__dm_control/unconnected_port": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__dm_control/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__instr_memory/concat_swap": {
+      "status": "sim_ok"
+    },
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+      "status": "waveform_identical"
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+      "status": "sim_ok"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__pc/missing_reset": {
+      "status": "sim_ok"
+    },
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+      "status": "sim_ok"
+    },
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+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__regfile/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__regfile/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "accomdemy_accomdemy_rv32i/cpu__regfile/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "aditeyabaral_DDCO-Lab-UE18CS207/alu__lib/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "aditeyabaral_DDCO-Lab-UE18CS207/fa4__lib/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "aditeyabaral_DDCO-Lab-UE18CS207/mproc_mem__lib/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "aditeyabaral_DDCO-Lab-UE18CS207/mproc_mem__mproc_mem/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "aditeyabaral_DDCO-Lab-UE18CS207/pc__lib/operator_typo": {
+      "status": "waveform_identical"
     },
     "aditeyabaral_DDCO-Lab-UE18CS207/reg_alu__lib/operator_typo": {
       "status": "waveform_identical"
     },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU/case_swap": {
+      "status": "waveform_identical"
+    },
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+      "status": "waveform_identical"
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+    },
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+      "status": "waveform_identical"
+    },
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+      "status": "sim_ok"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BHT/missing_reset": {
+      "status": "sim_ok"
+    },
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+      "status": "waveform_identical"
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+      "status": "sim_ok"
+    },
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+      "status": "waveform_identical"
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+      "status": "waveform_identical"
+    },
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+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/missing_reset": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
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+      "status": "waveform_identical"
+    },
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+      "status": "waveform_identical"
+    },
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+      "status": "waveform_identical"
+    },
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+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/inverted_condition": {
+      "status": "waveform_identical"
+    },
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+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__EX_MEM/missing_reset": {
+      "status": "sim_ok"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Forwarding_Unit/inverted_condition": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Forwarding_Unit/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Hazard_Unit/operator_typo": {
+      "status": "waveform_identical"
+    },
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+      "status": "sim_ok"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__IF_ID/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__IF_ID/missing_reset": {
+      "status": "sim_ok"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__I_Mem/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__I_Mem/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ImmGen/case_swap": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ImmGen/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__LDU/case_swap": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__LDU/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__MEM_WB/missing_reset": {
+      "status": "sim_ok"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC/case_swap": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC/missing_reset": {
+      "status": "sim_ok"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC_Adderr/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/missing_reset": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RISCV_CPU/operator_typo": {
+      "status": "sim_ok"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RISCV_CPU/unconnected_port": {
+      "status": "sim_ok"
+    },
+    "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RISCV_CPU/width_bit_cutoff": {
+      "status": "waveform_identical"
+    },
     "apfaudio_eurorack-pmod/ak4619__ak4619/case_swap": {
       "status": "sim_ok"
     },
@@ -1734,6 +1685,78 @@
     "apfaudio_eurorack-pmod/vca__vca/wrong_bitwidth": {
       "status": "sim_ok"
     },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_clgen/concat_swap": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_clgen/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_clgen/missing_enable": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_clgen/missing_reset": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_clgen/operator_typo": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/missing_reset": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_slave/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_slave/inverted_condition": {
+      "status": "waveform_identical"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_slave/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_slave/operator_typo": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_slave/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/case_swap": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/missing_enable": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/missing_reset": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__wishbone_master/missing_reset": {
+      "status": "waveform_identical"
+    },
     "defano_digital-design/uart__rx/inverted_condition": {
       "status": "sim_ok"
     },
@@ -1773,193 +1796,568 @@
     "defano_digital-design/uart__uart/missing_reset": {
       "status": "timeout"
     },
-    "defano_digital-design/uart__uart/operator_typo": {
-      "status": "sim_ok"
+    "defano_digital-design/uart__uart/operator_typo": {
+      "status": "sim_ok"
+    },
+    "defano_digital-design/uart__uart/unconnected_port": {
+      "status": "sim_ok"
+    },
+    "defano_digital-design/uart__uart/wrong_bitwidth": {
+      "status": "timeout"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/inverted_condition": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/missing_reset": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__mcu/missing_reset": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__mcu/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__mcu/unconnected_port": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__mcu/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__ram/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__ram/inverted_condition": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__ram/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__ram/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__ram/unconnected_port": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__ram/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__ram_byte/inverted_condition": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__ram_byte/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__ram_byte/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i/missing_reset": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i/unconnected_port": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_alu/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_alu/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_aludec/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_imm/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/unconnected_port": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_lsu/concat_swap": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_lsu/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/missing_reset": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regfile/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regfile/unconnected_port": {
+      "status": "waveform_identical"
+    },
+    "meiniKi_RV32I_SC_Logisim/mcu__sc_bus/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/concat_swap": {
+      "status": "sim_ok"
+    },
+    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/missing_enable": {
+      "status": "sim_ok"
+    },
+    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/missing_reset": {
+      "status": "sim_ok"
+    },
+    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/missing_reset": {
+      "status": "sim_ok"
+    },
+    "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/state_transition": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_reg__router_reg/inverted_condition": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_reg__router_reg/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_reg__router_reg/missing_reset": {
+      "status": "sim_ok"
+    },
+    "mnmhdanas_Router-1-x-3-/router_reg__router_reg/operator_typo": {
+      "status": "sim_ok"
+    },
+    "mnmhdanas_Router-1-x-3-/router_reg__router_reg/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/case_swap": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/inverted_condition": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/missing_reset": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "mnmhdanas_Router-1-x-3-/router_top__router_top/unconnected_port": {
+      "status": "sim_ok"
+    },
+    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/missing_reset": {
+      "status": "waveform_identical"
+    },
+    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/state_transition": {
+      "status": "sim_ok"
+    },
+    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/case_swap": {
+      "status": "sim_ok"
+    },
+    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/concat_swap": {
+      "status": "sim_ok"
+    },
+    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/missing_reset": {
+      "status": "sim_ok"
+    },
+    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/operator_typo": {
+      "status": "sim_ok"
+    },
+    "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch01__ch01/unconnected_port": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch01__display/case_swap": {
+      "status": "waveform_identical"
+    },
+    "projf_isle/ch01__display/missing_reset": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch01__display/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "projf_isle/ch02__canv_disp_agu/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch02__canv_disp_agu/missing_reset": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch02__canv_disp_agu/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch02__ch02/case_swap": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch02__ch02/unconnected_port": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch02__ch02/wrong_bitwidth": {
+      "status": "waveform_identical"
+    },
+    "projf_isle/ch02__clut/inverted_condition": {
+      "status": "waveform_identical"
+    },
+    "projf_isle/ch02__clut/missing_enable": {
+      "status": "waveform_identical"
+    },
+    "projf_isle/ch02__clut/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch02__vram/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch02__vram/missing_enable": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch02__vram/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch04__ch04/concat_swap": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch04__ch04/unconnected_port": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch04__ch04/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch04__font_glyph/case_swap": {
+      "status": "waveform_identical"
+    },
+    "projf_isle/ch04__font_glyph/unconnected_port": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch04__font_glyph/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch04__textmode/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch04__textmode/missing_reset": {
+      "status": "waveform_identical"
+    },
+    "projf_isle/ch04__textmode/off_by_one_counter": {
+      "status": "waveform_identical"
+    },
+    "projf_isle/ch04__textmode/state_transition": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch04__textmode/unconnected_port": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch04__textmode/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch04__tram/inverted_condition": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch04__tram/missing_enable": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch05__FemtoRV32/case_swap": {
+      "status": "llm_failed"
+    },
+    "projf_isle/ch05__FemtoRV32/concat_swap": {
+      "status": "llm_failed"
+    },
+    "projf_isle/ch05__FemtoRV32/inverted_condition": {
+      "status": "llm_failed"
+    },
+    "projf_isle/ch05__FemtoRV32/missing_enable": {
+      "status": "llm_failed"
+    },
+    "projf_isle/ch05__FemtoRV32/missing_reset": {
+      "status": "llm_failed"
+    },
+    "projf_isle/ch05__FemtoRV32/state_transition": {
+      "status": "llm_failed"
     },
-    "defano_digital-design/uart__uart/unconnected_port": {
-      "status": "sim_ok"
+    "projf_isle/ch05__FemtoRV32/wrong_bitwidth": {
+      "status": "llm_failed"
     },
-    "defano_digital-design/uart__uart/wrong_bitwidth": {
-      "status": "timeout"
+    "projf_isle/ch05__ch05/case_swap": {
+      "status": "sim_ok"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/inverted_condition": {
+    "projf_isle/ch05__ch05/concat_swap": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/missing_enable": {
+    "projf_isle/ch05__ch05/inverted_condition": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/missing_reset": {
+    "projf_isle/ch05__ch05/missing_enable": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/operator_typo": {
+    "projf_isle/ch05__ch05/missing_reset": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/wrong_bitwidth": {
+    "projf_isle/ch05__ch05/unconnected_port": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__mcu/missing_reset": {
+    "projf_isle/ch05__ch05/wrong_bitwidth": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__mcu/operator_typo": {
-      "status": "waveform_identical"
+    "projf_isle/ch05__sysram/inverted_condition": {
+      "status": "sim_ok"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__mcu/unconnected_port": {
-      "status": "waveform_identical"
+    "projf_isle/ch05__sysram/missing_enable": {
+      "status": "sim_ok"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__mcu/wrong_bitwidth": {
-      "status": "waveform_identical"
+    "projf_isle/ch05__xd/concat_swap": {
+      "status": "sim_ok"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__ram/concat_swap": {
+    "projf_isle/ch05__xd/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch06__ch06/case_swap": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__ram/inverted_condition": {
+    "projf_isle/ch06__ch06/concat_swap": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__ram/missing_enable": {
+    "projf_isle/ch06__ch06/unconnected_port": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__ram/operator_typo": {
+    "projf_isle/ch06__ch06/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch06__fifo_sync/inverted_condition": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__ram/unconnected_port": {
+    "projf_isle/ch06__fifo_sync/missing_enable": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__ram/wrong_bitwidth": {
+    "projf_isle/ch06__fifo_sync/missing_reset": {
       "status": "sim_ok"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__ram_byte/inverted_condition": {
+    "projf_isle/ch06__fifo_sync/wrong_bitwidth": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__ram_byte/missing_enable": {
+    "projf_isle/ch06__gfx_dev/case_swap": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__ram_byte/wrong_bitwidth": {
+    "projf_isle/ch06__gfx_dev/concat_swap": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i/concat_swap": {
+    "projf_isle/ch06__gfx_dev/inverted_condition": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i/missing_reset": {
+    "projf_isle/ch06__gfx_dev/missing_enable": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i/operator_typo": {
+    "projf_isle/ch06__gfx_dev/missing_reset": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i/unconnected_port": {
+    "projf_isle/ch06__lfsr/missing_enable": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i/wrong_bitwidth": {
+    "projf_isle/ch06__lfsr/missing_reset": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch06__sys_dev/case_swap": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_alu/concat_swap": {
+    "projf_isle/ch06__sys_dev/inverted_condition": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_alu/operator_typo": {
+    "projf_isle/ch06__sys_dev/missing_enable": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_aludec/operator_typo": {
+    "projf_isle/ch06__sys_dev/missing_reset": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_imm/concat_swap": {
+    "projf_isle/ch06__sys_dev/unconnected_port": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/concat_swap": {
+    "projf_isle/ch06__sys_dev/wrong_bitwidth": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/operator_typo": {
+    "projf_isle/ch06__uart_dev/case_swap": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/unconnected_port": {
+    "projf_isle/ch06__uart_dev/concat_swap": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_lsu/concat_swap": {
+    "projf_isle/ch06__uart_dev/inverted_condition": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_lsu/operator_typo": {
+    "projf_isle/ch06__uart_dev/missing_enable": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/missing_reset": {
+    "projf_isle/ch06__uart_dev/missing_reset": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/operator_typo": {
+    "projf_isle/ch06__uart_dev/unconnected_port": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/wrong_bitwidth": {
+    "projf_isle/ch06__uart_rx/inverted_condition": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regfile/operator_typo": {
+    "projf_isle/ch06__uart_rx/missing_enable": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regfile/unconnected_port": {
+    "projf_isle/ch06__uart_rx/missing_reset": {
+      "status": "sim_ok"
+    },
+    "projf_isle/ch06__uart_rx/state_transition": {
       "status": "waveform_identical"
     },
-    "meiniKi_RV32I_SC_Logisim/mcu__sc_bus/operator_typo": {
+    "projf_isle/ch06__uart_rx/wrong_bitwidth": {
       "status": "waveform_identical"
     },
-    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/concat_swap": {
+    "projf_isle/uart_tx__uart_tx/inverted_condition": {
       "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/inverted_condition": {
+    "projf_isle/uart_tx__uart_tx/missing_enable": {
       "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/missing_enable": {
+    "projf_isle/uart_tx__uart_tx/missing_reset": {
       "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/missing_reset": {
+    "projf_isle/uart_tx__uart_tx/state_transition": {
       "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/operator_typo": {
+    "projf_isle/uart_tx__uart_tx/wrong_bitwidth": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/p_mul__p_addsub/operator_typo": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/p_mul__p_mul/concat_swap": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/p_mul__p_mul/inverted_condition": {
       "status": "waveform_identical"
     },
-    "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/wrong_bitwidth": {
+    "scarv_xcrypto/p_mul__p_mul/missing_enable": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/p_mul__p_mul/missing_reset": {
       "status": "waveform_identical"
     },
-    "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/inverted_condition": {
+    "scarv_xcrypto/p_mul__p_mul/operator_typo": {
+      "status": "waveform_identical"
+    },
+    "scarv_xcrypto/p_mul__p_mul/unconnected_port": {
       "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/missing_reset": {
+    "scarv_xcrypto/p_mul__p_mul/wrong_bitwidth": {
       "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/operator_typo": {
+    "scarv_xcrypto/p_mul__p_shfrot/concat_swap": {
       "status": "waveform_identical"
     },
-    "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/state_transition": {
+    "scarv_xcrypto/p_mul__p_shfrot/operator_typo": {
       "status": "waveform_identical"
     },
-    "mnmhdanas_Router-1-x-3-/router_reg__router_reg/inverted_condition": {
+    "scarv_xcrypto/xc_malu__xc_malu/inverted_condition": {
       "status": "waveform_identical"
     },
-    "mnmhdanas_Router-1-x-3-/router_reg__router_reg/missing_enable": {
-      "status": "waveform_identical"
+    "scarv_xcrypto/xc_malu__xc_malu/missing_enable": {
+      "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_reg__router_reg/missing_reset": {
+    "scarv_xcrypto/xc_malu__xc_malu/missing_reset": {
       "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_reg__router_reg/operator_typo": {
+    "scarv_xcrypto/xc_malu__xc_malu/operator_typo": {
       "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_reg__router_reg/wrong_bitwidth": {
+    "scarv_xcrypto/xc_malu__xc_malu/state_transition": {
       "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/case_swap": {
-      "status": "waveform_identical"
+    "scarv_xcrypto/xc_malu__xc_malu/unconnected_port": {
+      "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/inverted_condition": {
-      "status": "waveform_identical"
+    "scarv_xcrypto/xc_malu__xc_malu/wrong_bitwidth": {
+      "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/missing_enable": {
-      "status": "waveform_identical"
+    "scarv_xcrypto/xc_malu__xc_malu_divrem/concat_swap": {
+      "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/missing_reset": {
-      "status": "waveform_identical"
+    "scarv_xcrypto/xc_malu__xc_malu_divrem/inverted_condition": {
+      "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/operator_typo": {
-      "status": "waveform_identical"
+    "scarv_xcrypto/xc_malu__xc_malu_divrem/missing_enable": {
+      "status": "sim_ok"
     },
-    "mnmhdanas_Router-1-x-3-/router_sync__router_sync/wrong_bitwidth": {
+    "scarv_xcrypto/xc_malu__xc_malu_divrem/missing_reset": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/xc_malu__xc_malu_divrem/operator_typo": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/xc_malu__xc_malu_long/concat_swap": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/xc_malu__xc_malu_long/operator_typo": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/xc_malu__xc_malu_mul/concat_swap": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/xc_malu__xc_malu_mul/operator_typo": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/xc_malu__xc_malu_muldivrem/operator_typo": {
       "status": "waveform_identical"
     },
-    "mnmhdanas_Router-1-x-3-/router_top__router_top/unconnected_port": {
+    "scarv_xcrypto/xc_malu__xc_malu_muldivrem/unconnected_port": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/xc_malu__xc_malu_pmul/concat_swap": {
+      "status": "sim_ok"
+    },
+    "scarv_xcrypto/xc_malu__xc_malu_pmul/operator_typo": {
       "status": "sim_ok"
     },
     "thedatabusdotio_fpga-ml-accelerator/acclerator__accelerator/unconnected_port": {
@@ -2306,11 +2704,6 @@
     }
   },
   "bug_types_attempted": {
-    "Vaibhav-Gunthe_Verilog-Projects": [
-      "blocking_nonblocking",
-      "case_swap",
-      "concat_swap"
-    ],
     "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core": [
       "blocking_nonblocking",
       "case_swap",
@@ -2416,7 +2809,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "akira2963753_Pipelined-RV32-SoC": [
+    "fcayci_sv-digital-design": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -2433,7 +2826,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "fcayci_sv-digital-design": [
+    "Fraunhofer-IMS_airisc_core_complex": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -2450,7 +2843,17 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Fraunhofer-IMS_airisc_core_complex": [
+    "chili-chips-ba_wireguard-fpga": [
+      "blocking_nonblocking",
+      "inverted_condition",
+      "missing_else_latch",
+      "missing_reset",
+      "operator_typo",
+      "signal_typo",
+      "unconnected_port",
+      "wrong_bitwidth"
+    ],
+    "shahsaumya00_Floating-Point-Adder": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -2467,7 +2870,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "nimanaqavi_Verilog-MathFunctions": [
+    "Mr-Bossman_KISC-V": [
       "blocking_nonblocking",
       "case_swap",
       "concat_swap",
@@ -2484,105 +2887,88 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "scarv_xcrypto": [
-      "blocking_nonblocking",
+    "apfaudio_eurorack-pmod": [
       "case_swap",
       "concat_swap",
       "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "JN513_Risco-5": [
-      "blocking_nonblocking",
+    "ttchisholm_10g-low-latency-ethernet": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "accomdemy_accomdemy_rv32i": [
-      "blocking_nonblocking",
+    "Weiyet_RTLStructLib": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "chili-chips-ba_wireguard-fpga": [
-      "blocking_nonblocking",
+    "zhangxin6_iverilog_testbench": [
+      "case_swap",
+      "concat_swap",
       "inverted_condition",
-      "missing_else_latch",
+      "missing_enable",
       "missing_reset",
+      "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
+      "state_transition",
       "unconnected_port",
+      "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "shahsaumya00_Floating-Point-Adder": [
-      "blocking_nonblocking",
+    "OrsuVenkataKrishnaiah1235_RTL-Coding": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Mr-Bossman_KISC-V": [
-      "blocking_nonblocking",
+    "thedatabusdotio_fpga-ml-accelerator": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
-      "missing_else_latch",
       "missing_enable",
       "missing_reset",
       "off_by_one_counter",
       "operator_typo",
-      "signal_typo",
       "state_transition",
       "unconnected_port",
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "apfaudio_eurorack-pmod": [
+    "aditeyabaral_DDCO-Lab-UE18CS207": [
       "case_swap",
       "concat_swap",
-      "delayed_signal",
       "inverted_condition",
       "missing_enable",
       "missing_reset",
@@ -2593,7 +2979,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "ttchisholm_10g-low-latency-ethernet": [
+    "mnmhdanas_Router-1-x-3-": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -2606,7 +2992,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "Weiyet_RTLStructLib": [
+    "meiniKi_RV32I_SC_Logisim": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -2619,7 +3005,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "zhangxin6_iverilog_testbench": [
+    "defano_digital-design": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -2632,7 +3018,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "OrsuVenkataKrishnaiah1235_RTL-Coding": [
+    "MohamedHussein27_AMPA_APB4_Protocol": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -2645,7 +3031,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "thedatabusdotio_fpga-ml-accelerator": [
+    "MohamedHussein27_SPI_Slave_With_Single_Port_Memory": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -2658,7 +3044,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "aditeyabaral_DDCO-Lab-UE18CS207": [
+    "Vaibhav-Gunthe_Verilog-Projects": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -2671,7 +3057,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "mnmhdanas_Router-1-x-3-": [
+    "nimanaqavi_Verilog-MathFunctions": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -2684,7 +3070,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "meiniKi_RV32I_SC_Logisim": [
+    "scarv_xcrypto": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -2697,7 +3083,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "defano_digital-design": [
+    "projf_isle": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -2710,7 +3096,7 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "MohamedHussein27_AMPA_APB4_Protocol": [
+    "accomdemy_accomdemy_rv32i": [
       "case_swap",
       "concat_swap",
       "inverted_condition",
@@ -2723,7 +3109,59 @@
       "width_bit_cutoff",
       "wrong_bitwidth"
     ],
-    "MohamedHussein27_SPI_Slave_With_Single_Port_Memory": [
+    "JN513_Risco-5": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "akira2963753_Pipelined-RV32-SoC": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM": [
+      "case_swap",
+      "concat_swap",
+      "inverted_condition",
+      "missing_enable",
+      "missing_reset",
+      "off_by_one_counter",
+      "operator_typo",
+      "state_transition",
+      "unconnected_port",
+      "width_bit_cutoff",
+      "wrong_bitwidth"
+    ],
+    "0thbit_CRC_parallel": [
       "case_swap",
       "concat_swap",
       "inverted_condition",

daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/sim_script_map.json

@@ -0,0 +1,3 @@
+{
+  "tb.v": "spi_top_sim.sh"
+}

daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/simulations.jsonl

@@ -0,0 +1 @@
+{"tb_file_path": "tb.v", "simulator": "iverilog", "top_module": "spi_top", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["spi_top.v", "spi_clgen.v", "spi_shift_reg.v", "spi_slave.v", "spi_defines.v", "wishbone_master.v", "tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_spi_top.fst"}

daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/testbenches.json

@@ -0,0 +1,17 @@
+[
+  {
+    "file_path": "tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "spi_top",
+    "rtl_files": [
+      "spi_top.v",
+      "spi_clgen.v",
+      "spi_shift_reg.v",
+      "spi_slave.v",
+      "spi_defines.v",
+      "wishbone_master.v"
+    ]
+  }
+]

daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/waveform_map.json

@@ -0,0 +1,3 @@
+{
+  "tb.v": "wave_spi_top.fst"
+}

manifest.json

@@ -3,7 +3,18 @@
     "repo": "0thbit/CRC_parallel",
     "clone_url": "https://github.com/0thbit/CRC_parallel.git",
     "commit_sha": "3a1578cd96929f8f856dcb9c309fa6ab1eb1e428",
-    "testbenches": []
+    "testbenches": [
+      {
+        "file_path": "CRC_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "crc",
+        "rtl_files": [
+          "CRC.v"
+        ]
+      }
+    ]
   },
   "MohamedHussein27_AMPA_APB4_Protocol": {
     "repo": "MohamedHussein27/AMPA_APB4_Protocol",
@@ -74,7 +85,208 @@
     "repo": "Vaibhav-Gunthe/Verilog-Projects",
     "clone_url": "https://github.com/Vaibhav-Gunthe/Verilog-Projects.git",
     "commit_sha": "10cbd766eebb8bd12800a589bc4c5fa4f0f4b7ba",
-    "testbenches": []
+    "testbenches": [
+      {
+        "file_path": "ALU/alu_8bit_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "alu_8bit",
+        "rtl_files": [
+          "ALU/8bit-ALU.v"
+        ]
+      },
+      {
+        "file_path": "Combinational-Circuits/4bit_Ripple-CarryAdder/Ripple_Carryadder_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "Ripple_carryadder",
+        "rtl_files": [
+          "Combinational-Circuits/4bit_Ripple-CarryAdder/4bit_Ripple-CarryAdder.v"
+        ]
+      },
+      {
+        "file_path": "Combinational-Circuits/4x1_Mux/mux4x1_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "mux4x1",
+        "rtl_files": [
+          "Combinational-Circuits/4x1_Mux/4x1_mux.v"
+        ]
+      },
+      {
+        "file_path": "Combinational-Circuits/8bit-Barrel_Shifter/barrel_shifter8bit_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "barrel_shifter_8bit",
+        "rtl_files": [
+          "Combinational-Circuits/8bit-Barrel_Shifter/8bit-Barrel_Shifter.v"
+        ]
+      },
+      {
+        "file_path": "Combinational-Circuits/Encoder_4x2/encoder4x2_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "encoder4x2",
+        "rtl_files": [
+          "Combinational-Circuits/Encoder_4x2/encoder4x2.v"
+        ]
+      },
+      {
+        "file_path": "Combinational-Circuits/Full_Adder/tb_FullAdder.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "Full_Adder",
+        "rtl_files": [
+          "Combinational-Circuits/Full_Adder/Full_Adder.v"
+        ]
+      },
+      {
+        "file_path": "Combinational-Circuits/Full_Subtractor/Full_Subtractor_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "full_subtractor",
+        "rtl_files": [
+          "Combinational-Circuits/Full_Subtractor/full_subtractor.v"
+        ]
+      },
+      {
+        "file_path": "Combinational-Circuits/Half_Adder/tb_HalfAdder.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "Half_Adder",
+        "rtl_files": [
+          "Combinational-Circuits/Half_Adder/Half-Adder.v"
+        ]
+      },
+      {
+        "file_path": "Combinational-Circuits/Half_Subtractor/Half_Subtractor_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "Half_subtractor",
+        "rtl_files": [
+          "Combinational-Circuits/Half_Subtractor/Half_subtractor.v"
+        ]
+      },
+      {
+        "file_path": "Combinational-Circuits/Multiplexer/Mux2x1_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "Mux2x1",
+        "rtl_files": [
+          "Combinational-Circuits/Multiplexer/Mux2x1.v"
+        ]
+      },
+      {
+        "file_path": "Logic-Gates/And_Gate/testbench-And_Gate.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "And_Gate",
+        "rtl_files": [
+          "Logic-Gates/And_Gate/And_Gate.v"
+        ]
+      },
+      {
+        "file_path": "Logic-Gates/Nand_Gate/tb_Nand.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "Nand_Gate",
+        "rtl_files": [
+          "Logic-Gates/Nand_Gate/Nand_Gate.v"
+        ]
+      },
+      {
+        "file_path": "Logic-Gates/Nor_Gate/tb_Nor.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "Nor_Gate",
+        "rtl_files": [
+          "Logic-Gates/Nor_Gate/Nor_Gate.v"
+        ]
+      },
+      {
+        "file_path": "Logic-Gates/Not_Gate/tb_Not.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "Not_Gate",
+        "rtl_files": [
+          "Logic-Gates/Not_Gate/Not_Gate.v"
+        ]
+      },
+      {
+        "file_path": "Logic-Gates/OR_Gate/testbench-OR_Gate.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "OR_Gate",
+        "rtl_files": [
+          "Logic-Gates/OR_Gate/OR_Gate.v"
+        ]
+      },
+      {
+        "file_path": "Logic-Gates/X-NOR_Gate/tb_XNOR.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "XNOR_Gate",
+        "rtl_files": [
+          "Logic-Gates/X-NOR_Gate/XNOR_Gate.v"
+        ]
+      },
+      {
+        "file_path": "Logic-Gates/X-OR_Gate/tb_XOR.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "XOR_Gate",
+        "rtl_files": [
+          "Logic-Gates/X-OR_Gate/XOR_Gate.v"
+        ]
+      },
+      {
+        "file_path": "Sequential Circuits/8 bit twin register/twin_reg_8bit_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "twin_reg_8bit",
+        "rtl_files": [
+          "Sequential Circuits/8 bit twin register/twin_reg_8bit.v"
+        ]
+      },
+      {
+        "file_path": "Sequential Circuits/D_Flipflop/d_ff_asynchronous_reset_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "D_ff_basic",
+        "rtl_files": [
+          "Sequential Circuits/D_Flipflop/d_ff_asynchronous_reset.v"
+        ]
+      },
+      {
+        "file_path": "Sequential Circuits/D_Flipflop/d_ff_synchronous_reset_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "D_ff_synchronous_reset",
+        "rtl_files": [
+          "Sequential Circuits/D_Flipflop/d_ff_synchronous_reset.v"
+        ]
+      }
+    ]
   },
   "Weiyet_RTLStructLib": {
     "repo": "Weiyet/RTLStructLib",
@@ -864,13 +1076,67 @@
     "repo": "nimanaqavi/Verilog-MathFunctions",
     "clone_url": "https://github.com/nimanaqavi/Verilog-MathFunctions.git",
     "commit_sha": "002eb114fe7f21013149455894df91b3553934cd",
-    "testbenches": []
+    "testbenches": [
+      {
+        "file_path": "Verilog-MathFunctions/Test_Bench/Ln_Tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "part_Ln_TOP",
+        "rtl_files": [
+          "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/Ln_TOP.v",
+          "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/Ln_CO.v",
+          "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/Ln_DP.v"
+        ]
+      },
+      {
+        "file_path": "Verilog-MathFunctions/Test_Bench/Tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "part_1_TOP",
+        "rtl_files": [
+          "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/part1TOP.v",
+          "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/part1CO.v",
+          "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/part1Dp.v"
+        ]
+      }
+    ]
   },
   "scarv_xcrypto": {
     "repo": "scarv/xcrypto",
     "clone_url": "https://github.com/scarv/xcrypto.git",
     "commit_sha": "9ff3426a9d498bf41880caca4bc3769eec0e5093",
-    "testbenches": []
+    "testbenches": [
+      {
+        "file_path": "rtl/p_mul/p_mul_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "p_mul",
+        "rtl_files": [
+          "rtl/p_mul/p_mul.v",
+          "rtl/p_addsub/p_addsub.v",
+          "rtl/p_shfrot/p_shfrot.v"
+        ]
+      },
+      {
+        "file_path": "rtl/xc_malu/xc_malu_tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "xc_malu",
+        "rtl_files": [
+          "rtl/xc_malu/xc_malu.v",
+          "rtl/xc_malu/xc_malu_muldivrem.v",
+          "rtl/xc_malu/xc_malu_divrem.v",
+          "rtl/xc_malu/xc_malu_mul.v",
+          "rtl/xc_malu/xc_malu_pmul.v",
+          "rtl/xc_malu/xc_malu_long.v",
+          "rtl/p_addsub/p_addsub.v"
+        ]
+      }
+    ]
   },
   "selimsandal_OneShotNPU": {
     "repo": "selimsandal/OneShotNPU",
@@ -884,65 +1150,35 @@
     "commit_sha": "12a570c7124f5f78f2c9513248f8e6bd85137068",
     "testbenches": [
       {
-        "file_path": "tests/core_test.v",
-        "tb_type": "verilog",
-        "simulator": "icarus",
-        "makefile_path": null,
-        "top_module": "Core",
-        "rtl_files": [
-          "src/core/core.v",
-          "src/core/pc.v",
-          "src/core/mux.v",
-          "src/core/registers.v",
-          "src/core/control_unit.v",
-          "src/core/alu_control.v",
-          "src/core/alu.v",
-          "src/core/immediate_generator.v",
-          "src/core/csr_unit.v",
-          "src/core/mdu.v",
-          "src/peripheral/memory.v",
-          "src/peripheral/bus.v",
-          "src/peripheral/leds.v"
-        ]
-      },
-      {
-        "file_path": "tests/registers_test.v",
+        "file_path": "tests/clk_divider.v",
         "tb_type": "verilog",
         "simulator": "icarus",
         "makefile_path": null,
-        "top_module": "Registers",
+        "top_module": "ClkDivider",
         "rtl_files": [
-          "src/core/registers.v"
+          "debug/clk_divider.v"
         ]
       },
       {
-        "file_path": "tests/soc_test.v",
+        "file_path": "tests/core_test.v",
         "tb_type": "verilog",
         "simulator": "icarus",
         "makefile_path": null,
-        "top_module": "Risco_5_SOC",
+        "top_module": "Core",
         "rtl_files": [
-          "src/peripheral/soc.v",
-          "src/core/core.v",
-          "src/core/pc.v",
-          "src/core/mux.v",
-          "src/core/registers.v",
-          "src/core/control_unit.v",
-          "src/core/alu_control.v",
           "src/core/alu.v",
-          "src/core/immediate_generator.v",
+          "src/core/alu_control.v",
+          "src/core/control_unit.v",
           "src/core/csr_unit.v",
+          "src/core/immediate_generator.v",
           "src/core/mdu.v",
+          "src/core/mux.v",
+          "src/core/pc.v",
+          "src/core/registers.v",
+          "src/core/core.v",
           "src/peripheral/memory.v",
           "src/peripheral/bus.v",
-          "src/peripheral/leds.v",
-          "src/peripheral/uart.v",
-          "src/peripheral/uart_rx.v",
-          "src/peripheral/uart_tx.v",
-          "src/peripheral/fifo.v",
-          "src/peripheral/gpios.v",
-          "src/peripheral/gpio.v",
-          "src/peripheral/pwm.v"
+          "src/peripheral/leds.v"
         ]
       },
       {
@@ -952,8 +1188,8 @@
         "makefile_path": null,
         "top_module": "GPIOS",
         "rtl_files": [
-          "src/peripheral/gpios.v",
           "src/peripheral/gpio.v",
+          "src/peripheral/gpios.v",
           "src/peripheral/pwm.v"
         ]
       },
@@ -968,13 +1204,13 @@
         ]
       },
       {
-        "file_path": "tests/clk_divider.v",
+        "file_path": "tests/registers_test.v",
         "tb_type": "verilog",
         "simulator": "icarus",
         "makefile_path": null,
-        "top_module": "ClkDivider",
+        "top_module": "Registers",
         "rtl_files": [
-          "debug/clk_divider.v"
+          "src/core/registers.v"
         ]
       },
       {
@@ -986,6 +1222,36 @@
         "rtl_files": [
           "debug/reset.v"
         ]
+      },
+      {
+        "file_path": "tests/soc_test.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "Risco_5_SOC",
+        "rtl_files": [
+          "src/core/alu.v",
+          "src/core/alu_control.v",
+          "src/core/control_unit.v",
+          "src/core/csr_unit.v",
+          "src/core/immediate_generator.v",
+          "src/core/mdu.v",
+          "src/core/mux.v",
+          "src/core/pc.v",
+          "src/core/registers.v",
+          "src/core/core.v",
+          "src/peripheral/bus.v",
+          "src/peripheral/fifo.v",
+          "src/peripheral/gpio.v",
+          "src/peripheral/gpios.v",
+          "src/peripheral/leds.v",
+          "src/peripheral/memory.v",
+          "src/peripheral/pwm.v",
+          "src/peripheral/soc.v",
+          "src/peripheral/uart.v",
+          "src/peripheral/uart_rx.v",
+          "src/peripheral/uart_tx.v"
+        ]
       }
     ]
   },
@@ -1075,13 +1341,13 @@
         "top_module": "cpu",
         "rtl_files": [
           "src/cpu.v",
+          "src/MUX2to1_32bit.v",
+          "src/MUX4to1_32bit.v",
           "src/alu.v",
           "src/branch.v",
           "src/decoder.v",
           "src/dm_control.v",
           "src/instr_memory.v",
-          "src/MUX2to1_32bit.v",
-          "src/MUX4to1_32bit.v",
           "src/pc.v",
           "src/regfile.v"
         ]
@@ -1094,102 +1360,102 @@
     "commit_sha": "ded74adc6a29ef5bbdac56a5eac5b99328064371",
     "testbenches": [
       {
-        "file_path": "source/Five-Stage-Pipelined-CPU/RTL/RISCV_CPU_tb.v",
+        "file_path": "Five-Stage-Pipelined-CPU/RTL/RISCV_CPU_tb.v",
         "tb_type": "verilog",
         "simulator": "icarus",
         "makefile_path": null,
         "top_module": "RISCV_CPU",
         "rtl_files": [
-          "source/Five-Stage-Pipelined-CPU/RTL/ALU.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/ALU_Control.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/BHT.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/BPU.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/BTB.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/CSR.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/Control.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/D_Mem.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/EX_MEM.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/Forwarding_Unit.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/Hazard_Unit.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/ID_EX.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/IF_ID.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/I_Mem.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/ImmGen.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/LDU.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/MEM_WB.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/PC.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/PC_Adderr.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/RF.v",
-          "source/Five-Stage-Pipelined-CPU/RTL/RISCV_CPU.v"
+          "Five-Stage-Pipelined-CPU/RTL/RISCV_CPU.v",
+          "Five-Stage-Pipelined-CPU/RTL/ALU.v",
+          "Five-Stage-Pipelined-CPU/RTL/ALU_Control.v",
+          "Five-Stage-Pipelined-CPU/RTL/BHT.v",
+          "Five-Stage-Pipelined-CPU/RTL/BPU.v",
+          "Five-Stage-Pipelined-CPU/RTL/BTB.v",
+          "Five-Stage-Pipelined-CPU/RTL/CSR.v",
+          "Five-Stage-Pipelined-CPU/RTL/Control.v",
+          "Five-Stage-Pipelined-CPU/RTL/D_Mem.v",
+          "Five-Stage-Pipelined-CPU/RTL/EX_MEM.v",
+          "Five-Stage-Pipelined-CPU/RTL/Forwarding_Unit.v",
+          "Five-Stage-Pipelined-CPU/RTL/Hazard_Unit.v",
+          "Five-Stage-Pipelined-CPU/RTL/ID_EX.v",
+          "Five-Stage-Pipelined-CPU/RTL/IF_ID.v",
+          "Five-Stage-Pipelined-CPU/RTL/I_Mem.v",
+          "Five-Stage-Pipelined-CPU/RTL/ImmGen.v",
+          "Five-Stage-Pipelined-CPU/RTL/LDU.v",
+          "Five-Stage-Pipelined-CPU/RTL/MEM_WB.v",
+          "Five-Stage-Pipelined-CPU/RTL/PC.v",
+          "Five-Stage-Pipelined-CPU/RTL/PC_Adderr.v",
+          "Five-Stage-Pipelined-CPU/RTL/RF.v"
         ]
       },
       {
-        "file_path": "source/RISC-V-Processor/RTL/RISCV_PROCESSOR_tb.v",
+        "file_path": "RISC-V-Processor/RTL/RISCV_PROCESSOR_tb.v",
         "tb_type": "verilog",
         "simulator": "icarus",
         "makefile_path": null,
         "top_module": "RISCV_PROCESSOR",
         "rtl_files": [
-          "source/RISC-V-Processor/RTL/ALU.v",
-          "source/RISC-V-Processor/RTL/ALU_Control.v",
-          "source/RISC-V-Processor/RTL/AXI4_Lite_Bus.v",
-          "source/RISC-V-Processor/RTL/BHT.v",
-          "source/RISC-V-Processor/RTL/BPU.v",
-          "source/RISC-V-Processor/RTL/BTB.v",
-          "source/RISC-V-Processor/RTL/CSR.v",
-          "source/RISC-V-Processor/RTL/Control.v",
-          "source/RISC-V-Processor/RTL/D_BRAM.v",
-          "source/RISC-V-Processor/RTL/D_Cache.v",
-          "source/RISC-V-Processor/RTL/D_Mem.v",
-          "source/RISC-V-Processor/RTL/EX_MEM.v",
-          "source/RISC-V-Processor/RTL/Forwarding_Unit.v",
-          "source/RISC-V-Processor/RTL/Hazard_Unit.v",
-          "source/RISC-V-Processor/RTL/ID_EX.v",
-          "source/RISC-V-Processor/RTL/IF_ID.v",
-          "source/RISC-V-Processor/RTL/I_Cache.v",
-          "source/RISC-V-Processor/RTL/ImmGen.v",
-          "source/RISC-V-Processor/RTL/LDU.v",
-          "source/RISC-V-Processor/RTL/MEM_WB.v",
-          "source/RISC-V-Processor/RTL/PC.v",
-          "source/RISC-V-Processor/RTL/PC_Adder.v",
-          "source/RISC-V-Processor/RTL/RF.v",
-          "source/RISC-V-Processor/RTL/RISCV_CPU.v",
-          "source/RISC-V-Processor/RTL/RISCV_PROCESSOR.v"
-        ]
-      },
-      {
-        "file_path": "source/CACHE/AXI4-LITE/Pattern.v",
+          "RISC-V-Processor/RTL/RISCV_PROCESSOR.v",
+          "RISC-V-Processor/RTL/RISCV_CPU.v",
+          "RISC-V-Processor/RTL/ALU.v",
+          "RISC-V-Processor/RTL/ALU_Control.v",
+          "RISC-V-Processor/RTL/AXI4_Lite_Bus.v",
+          "RISC-V-Processor/RTL/BHT.v",
+          "RISC-V-Processor/RTL/BPU.v",
+          "RISC-V-Processor/RTL/BTB.v",
+          "RISC-V-Processor/RTL/CSR.v",
+          "RISC-V-Processor/RTL/Control.v",
+          "RISC-V-Processor/RTL/D_BRAM.v",
+          "RISC-V-Processor/RTL/D_Cache.v",
+          "RISC-V-Processor/RTL/D_Mem.v",
+          "RISC-V-Processor/RTL/EX_MEM.v",
+          "RISC-V-Processor/RTL/Forwarding_Unit.v",
+          "RISC-V-Processor/RTL/Hazard_Unit.v",
+          "RISC-V-Processor/RTL/ID_EX.v",
+          "RISC-V-Processor/RTL/IF_ID.v",
+          "RISC-V-Processor/RTL/I_Cache.v",
+          "RISC-V-Processor/RTL/ImmGen.v",
+          "RISC-V-Processor/RTL/LDU.v",
+          "RISC-V-Processor/RTL/MEM_WB.v",
+          "RISC-V-Processor/RTL/PC.v",
+          "RISC-V-Processor/RTL/PC_Adder.v",
+          "RISC-V-Processor/RTL/RF.v"
+        ]
+      },
+      {
+        "file_path": "CACHE/AXI4-LITE/Pattern.v",
         "tb_type": "verilog",
         "simulator": "icarus",
         "makefile_path": null,
         "top_module": "Tested",
         "rtl_files": [
-          "source/CACHE/AXI4-LITE/Tested.v",
-          "source/CACHE/AXI4-LITE/AXI4_Lite_Bus.v"
+          "CACHE/AXI4-LITE/Tested.v",
+          "CACHE/AXI4-LITE/AXI4_Lite_Bus.v"
         ]
       },
       {
-        "file_path": "source/CACHE/I-CACHE/Pattern.v",
+        "file_path": "CACHE/D-CACHE/Pattern.v",
         "tb_type": "verilog",
         "simulator": "icarus",
         "makefile_path": null,
         "top_module": "Tested",
         "rtl_files": [
-          "source/CACHE/I-CACHE/Tested.v",
-          "source/CACHE/I-CACHE/Cache.v",
-          "source/CACHE/I-CACHE/AXI4_Lite_Bus.v"
+          "CACHE/D-CACHE/Tested.v",
+          "CACHE/D-CACHE/D_Cache.v",
+          "CACHE/D-CACHE/AXI4_Lite_Bus.v"
         ]
       },
       {
-        "file_path": "source/CACHE/D-CACHE/Pattern.v",
+        "file_path": "CACHE/I-CACHE/Pattern.v",
         "tb_type": "verilog",
         "simulator": "icarus",
         "makefile_path": null,
         "top_module": "Tested",
         "rtl_files": [
-          "source/CACHE/D-CACHE/Tested.v",
-          "source/CACHE/D-CACHE/D_Cache.v",
-          "source/CACHE/D-CACHE/AXI4_Lite_Bus.v"
+          "CACHE/I-CACHE/Tested.v",
+          "CACHE/I-CACHE/Cache.v",
+          "CACHE/I-CACHE/AXI4_Lite_Bus.v"
         ]
       }
     ]
@@ -1217,5 +1483,248 @@
         ]
       }
     ]
+  },
+  "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM": {
+    "repo": "Abdelrahman1810/SPI_Slave_with_Single_Port_RAM",
+    "clone_url": "https://github.com/Abdelrahman1810/SPI_Slave_with_Single_Port_RAM.git",
+    "commit_sha": "6233b161a0428ec0a0e22b6e74373c4d8d98d972",
+    "testbenches": [
+      {
+        "file_path": "Codes/testbench/tb_SPI.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "SPI",
+        "rtl_files": [
+          "Codes/RTL/SPI.v"
+        ]
+      },
+      {
+        "file_path": "Codes/testbench/tb_instantiation.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "instantiation",
+        "rtl_files": [
+          "Codes/RTL/instantiation.v",
+          "Codes/RTL/SPI.v",
+          "Codes/RTL/RAM.v"
+        ]
+      },
+      {
+        "file_path": "Codes/testbench/tb_ram.sv",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "RAM",
+        "rtl_files": [
+          "Codes/RTL/RAM.v"
+        ]
+      }
+    ]
+  },
+  "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules": {
+    "repo": "daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules",
+    "clone_url": "https://github.com/daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules.git",
+    "commit_sha": "0da4e865fb717d6221977ba285118f9a97c6158b",
+    "testbenches": [
+      {
+        "file_path": "tb.v",
+        "tb_type": "verilog",
+        "simulator": "icarus",
+        "makefile_path": null,
+        "top_module": "spi_top",
+        "rtl_files": [
+          "spi_top.v",
+          "spi_clgen.v",
+          "spi_shift_reg.v",
+          "spi_slave.v",
+          "spi_defines.v",
+          "wishbone_master.v"
+        ]
+      }
+    ]
+  },
+  "projf_isle": {
+    "repo": "projf/isle",
+    "clone_url": "https://github.com/projf/isle.git",
+    "commit_sha": "ff248e1db8cd70c4a52399c96dee1554bf5baeac",
+    "testbenches": [
+      {
+        "file_path": "hardware/tests/book/ch01.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/book/ch01.mk",
+        "top_module": "ch01",
+        "rtl_files": [
+          "hardware/book/ch01/ch01.v",
+          "hardware/gfx/display.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/book/ch02.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/book/ch02.mk",
+        "top_module": "ch02",
+        "rtl_files": [
+          "hardware/book/ch02/ch02.v",
+          "hardware/gfx/canv_disp_agu.v",
+          "hardware/gfx/display.v",
+          "hardware/mem/clut.v",
+          "hardware/mem/vram.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/book/ch03.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/book/ch03.mk",
+        "top_module": "ch03",
+        "rtl_files": [
+          "hardware/book/ch03/ch03.v",
+          "hardware/gfx/canv_disp_agu.v",
+          "hardware/gfx/canv_draw_agu.v",
+          "hardware/gfx/circle.v",
+          "hardware/gfx/display.v",
+          "hardware/gfx/earthrise.v",
+          "hardware/gfx/fline.v",
+          "hardware/gfx/line.v",
+          "hardware/mem/clut.v",
+          "hardware/mem/erlist.v",
+          "hardware/mem/vram.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/book/ch04.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/book/ch04.mk",
+        "top_module": "ch04",
+        "rtl_files": [
+          "hardware/book/ch04/ch04.v",
+          "hardware/gfx/display.v",
+          "hardware/gfx/font_glyph.v",
+          "hardware/gfx/textmode.v",
+          "hardware/mem/clut.v",
+          "hardware/mem/rom_sync.v",
+          "hardware/mem/tram.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/book/ch05.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/book/ch05.mk",
+        "top_module": "ch05",
+        "rtl_files": [
+          "hardware/book/ch05/ch05.v",
+          "hardware/cpu/FemtoRV32.v",
+          "hardware/gfx/display.v",
+          "hardware/gfx/font_glyph.v",
+          "hardware/gfx/textmode.v",
+          "hardware/mem/clut.v",
+          "hardware/mem/rom_sync.v",
+          "hardware/mem/sysram.v",
+          "hardware/mem/tram.v",
+          "hardware/sys/xd.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/book/ch06.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/book/ch06.mk",
+        "top_module": "ch06",
+        "rtl_files": [
+          "hardware/book/ch06/ch06.v",
+          "hardware/cpu/FemtoRV32.v",
+          "hardware/devs/gfx_dev.v",
+          "hardware/devs/sys_dev.v",
+          "hardware/devs/uart_dev.v",
+          "hardware/gfx/display.v",
+          "hardware/gfx/font_glyph.v",
+          "hardware/gfx/textmode.v",
+          "hardware/io/uart_rx.v",
+          "hardware/math/lfsr.v",
+          "hardware/mem/clut.v",
+          "hardware/mem/fifo_sync.v",
+          "hardware/mem/rom_sync.v",
+          "hardware/mem/sysram.v",
+          "hardware/mem/tram.v",
+          "hardware/sys/xd.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/gfx/canv_disp_agu.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/gfx/canv_disp_agu.mk",
+        "top_module": "canv_disp_agu",
+        "rtl_files": [
+          "hardware/gfx/canv_disp_agu.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/gfx/display.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/gfx/display.mk",
+        "top_module": "display",
+        "rtl_files": [
+          "hardware/gfx/display.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/gfx/tmds_encoder.py",
+        "tb_type": "cocotb",
+        "simulator": "verilator",
+        "makefile_path": "hardware/tests/gfx/tmds_encoder.mk",
+        "top_module": "tmds_encoder",
+        "rtl_files": [
+          "hardware/gfx/tmds_encoder.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/io/uart_rx.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/io/uart_rx.mk",
+        "top_module": "uart_rx",
+        "rtl_files": [
+          "hardware/io/uart_rx.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/io/uart_tx.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/io/uart_tx.mk",
+        "top_module": "uart_tx",
+        "rtl_files": [
+          "hardware/io/uart_tx.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/mem/clut.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/mem/clut.mk",
+        "top_module": "clut",
+        "rtl_files": [
+          "hardware/mem/clut.v"
+        ]
+      },
+      {
+        "file_path": "hardware/tests/mem/vram.py",
+        "tb_type": "cocotb",
+        "simulator": "icarus",
+        "makefile_path": "hardware/tests/mem/vram.mk",
+        "top_module": "vram",
+        "rtl_files": [
+          "hardware/mem/vram.v"
+        ]
+      }
+    ]
   }
 }

nimanaqavi_Verilog-MathFunctions/sim_script_map.json

@@ -0,0 +1,3 @@
+{
+  "Verilog-MathFunctions/Test_Bench/Ln_Tb.v": "part_Ln_TOP_sim.sh"
+}

nimanaqavi_Verilog-MathFunctions/simulations.jsonl

@@ -0,0 +1 @@
+{"tb_file_path": "Verilog-MathFunctions/Test_Bench/Ln_Tb.v", "simulator": "iverilog", "top_module": "part_Ln_TOP", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Verilog-MathFunctions/Test_Bench/Ln_Tb.v", "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/Ln_TOP.v", "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/Ln_CO.v", "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/Ln_DP.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_part_Ln_TOP.fst"}

nimanaqavi_Verilog-MathFunctions/testbenches.json

@@ -0,0 +1,26 @@
+[
+  {
+    "file_path": "Verilog-MathFunctions/Test_Bench/Ln_Tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "part_Ln_TOP",
+    "rtl_files": [
+      "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/Ln_TOP.v",
+      "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/Ln_CO.v",
+      "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/Ln_DP.v"
+    ]
+  },
+  {
+    "file_path": "Verilog-MathFunctions/Test_Bench/Tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "part_1_TOP",
+    "rtl_files": [
+      "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/part1TOP.v",
+      "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/part1CO.v",
+      "Verilog-MathFunctions/sin_cos_Ln_exp_SRC/part1Dp.v"
+    ]
+  }
+]

nimanaqavi_Verilog-MathFunctions/waveform_map.json

@@ -0,0 +1,3 @@
+{
+  "Verilog-MathFunctions/Test_Bench/Ln_Tb.v": "wave_part_Ln_TOP.fst"
+}

projf_isle/sim_script_map.json

@@ -0,0 +1,13 @@
+{
+  "hardware/tests/book/ch01.py": "ch01_sim.sh",
+  "hardware/tests/book/ch02.py": "ch02_sim.sh",
+  "hardware/tests/book/ch04.py": "ch04_sim.sh",
+  "hardware/tests/book/ch05.py": "ch05_sim.sh",
+  "hardware/tests/book/ch06.py": "ch06_sim.sh",
+  "hardware/tests/gfx/canv_disp_agu.py": "canv_disp_agu_sim.sh",
+  "hardware/tests/gfx/display.py": "display_sim.sh",
+  "hardware/tests/io/uart_rx.py": "uart_rx_sim.sh",
+  "hardware/tests/io/uart_tx.py": "uart_tx_sim.sh",
+  "hardware/tests/mem/clut.py": "clut_sim.sh",
+  "hardware/tests/mem/vram.py": "vram_sim.sh"
+}

projf_isle/simulations.jsonl

@@ -0,0 +1,11 @@
+{"tb_file_path": "hardware/tests/book/ch01.py", "simulator": "cocotb", "top_module": "ch01", "work_subdir": "hardware/tests/book", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "ch01", "MODULE": "ch01", "WAVES": "1"}, "target": "ch01", "clean_first": false}}
+{"tb_file_path": "hardware/tests/book/ch02.py", "simulator": "cocotb", "top_module": "ch02", "work_subdir": "hardware/tests/book", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "ch02", "MODULE": "ch02", "WAVES": "1"}, "target": "ch02", "clean_first": false}}
+{"tb_file_path": "hardware/tests/book/ch04.py", "simulator": "cocotb", "top_module": "ch04", "work_subdir": "hardware/tests/book", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "ch04", "MODULE": "ch04", "WAVES": "1"}, "target": "ch04", "clean_first": false}}
+{"tb_file_path": "hardware/tests/book/ch05.py", "simulator": "cocotb", "top_module": "ch05", "work_subdir": "hardware/tests/book", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "ch05", "MODULE": "ch05", "WAVES": "1"}, "target": "ch05", "clean_first": false}}
+{"tb_file_path": "hardware/tests/book/ch06.py", "simulator": "cocotb", "top_module": "ch06", "work_subdir": "hardware/tests/book", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "ch06", "MODULE": "ch06", "WAVES": "1"}, "target": "ch06", "clean_first": false}}
+{"tb_file_path": "hardware/tests/gfx/canv_disp_agu.py", "simulator": "cocotb", "top_module": "canv_disp_agu", "work_subdir": "hardware/tests/gfx", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "canv_disp_agu", "MODULE": "canv_disp_agu", "WAVES": "1"}, "target": "canv_disp_agu", "clean_first": false}}
+{"tb_file_path": "hardware/tests/gfx/display.py", "simulator": "cocotb", "top_module": "display", "work_subdir": "hardware/tests/gfx", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "display", "MODULE": "display", "WAVES": "1", "DISPLAY_MODE": "3"}, "target": "display_mode_3", "clean_first": false}}
+{"tb_file_path": "hardware/tests/io/uart_rx.py", "simulator": "cocotb", "top_module": "uart_rx", "work_subdir": "hardware/tests/io", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "uart_rx", "MODULE": "uart_rx", "WAVES": "1"}, "target": "uart_rx", "clean_first": false}}
+{"tb_file_path": "hardware/tests/io/uart_tx.py", "simulator": "cocotb", "top_module": "uart_tx", "work_subdir": "hardware/tests/io", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "uart_tx", "MODULE": "uart_tx", "WAVES": "1"}, "target": "uart_tx", "clean_first": false}}
+{"tb_file_path": "hardware/tests/mem/clut.py", "simulator": "cocotb", "top_module": "clut", "work_subdir": "hardware/tests/mem", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "clut", "MODULE": "clut", "WAVES": "1"}, "target": "clut", "clean_first": false}}
+{"tb_file_path": "hardware/tests/mem/vram.py", "simulator": "cocotb", "top_module": "vram", "work_subdir": "hardware/tests/mem", "requires_submodules": false, "make": {"env": {"TOPLEVEL": "vram", "MODULE": "vram", "WAVES": "1"}, "target": "vram", "clean_first": false}}

projf_isle/testbenches.json

@@ -0,0 +1,177 @@
+[
+  {
+    "file_path": "hardware/tests/book/ch01.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/book/ch01.mk",
+    "top_module": "ch01",
+    "rtl_files": [
+      "hardware/book/ch01/ch01.v",
+      "hardware/gfx/display.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/book/ch02.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/book/ch02.mk",
+    "top_module": "ch02",
+    "rtl_files": [
+      "hardware/book/ch02/ch02.v",
+      "hardware/gfx/canv_disp_agu.v",
+      "hardware/gfx/display.v",
+      "hardware/mem/clut.v",
+      "hardware/mem/vram.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/book/ch03.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/book/ch03.mk",
+    "top_module": "ch03",
+    "rtl_files": [
+      "hardware/book/ch03/ch03.v",
+      "hardware/gfx/canv_disp_agu.v",
+      "hardware/gfx/canv_draw_agu.v",
+      "hardware/gfx/circle.v",
+      "hardware/gfx/display.v",
+      "hardware/gfx/earthrise.v",
+      "hardware/gfx/fline.v",
+      "hardware/gfx/line.v",
+      "hardware/mem/clut.v",
+      "hardware/mem/erlist.v",
+      "hardware/mem/vram.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/book/ch04.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/book/ch04.mk",
+    "top_module": "ch04",
+    "rtl_files": [
+      "hardware/book/ch04/ch04.v",
+      "hardware/gfx/display.v",
+      "hardware/gfx/font_glyph.v",
+      "hardware/gfx/textmode.v",
+      "hardware/mem/clut.v",
+      "hardware/mem/rom_sync.v",
+      "hardware/mem/tram.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/book/ch05.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/book/ch05.mk",
+    "top_module": "ch05",
+    "rtl_files": [
+      "hardware/book/ch05/ch05.v",
+      "hardware/cpu/FemtoRV32.v",
+      "hardware/gfx/display.v",
+      "hardware/gfx/font_glyph.v",
+      "hardware/gfx/textmode.v",
+      "hardware/mem/clut.v",
+      "hardware/mem/rom_sync.v",
+      "hardware/mem/sysram.v",
+      "hardware/mem/tram.v",
+      "hardware/sys/xd.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/book/ch06.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/book/ch06.mk",
+    "top_module": "ch06",
+    "rtl_files": [
+      "hardware/book/ch06/ch06.v",
+      "hardware/cpu/FemtoRV32.v",
+      "hardware/devs/gfx_dev.v",
+      "hardware/devs/sys_dev.v",
+      "hardware/devs/uart_dev.v",
+      "hardware/gfx/display.v",
+      "hardware/gfx/font_glyph.v",
+      "hardware/gfx/textmode.v",
+      "hardware/io/uart_rx.v",
+      "hardware/math/lfsr.v",
+      "hardware/mem/clut.v",
+      "hardware/mem/fifo_sync.v",
+      "hardware/mem/rom_sync.v",
+      "hardware/mem/sysram.v",
+      "hardware/mem/tram.v",
+      "hardware/sys/xd.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/gfx/canv_disp_agu.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/gfx/canv_disp_agu.mk",
+    "top_module": "canv_disp_agu",
+    "rtl_files": [
+      "hardware/gfx/canv_disp_agu.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/gfx/display.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/gfx/display.mk",
+    "top_module": "display",
+    "rtl_files": [
+      "hardware/gfx/display.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/gfx/tmds_encoder.py",
+    "tb_type": "cocotb",
+    "simulator": "verilator",
+    "makefile_path": "hardware/tests/gfx/tmds_encoder.mk",
+    "top_module": "tmds_encoder",
+    "rtl_files": [
+      "hardware/gfx/tmds_encoder.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/io/uart_rx.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/io/uart_rx.mk",
+    "top_module": "uart_rx",
+    "rtl_files": [
+      "hardware/io/uart_rx.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/io/uart_tx.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/io/uart_tx.mk",
+    "top_module": "uart_tx",
+    "rtl_files": [
+      "hardware/io/uart_tx.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/mem/clut.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/mem/clut.mk",
+    "top_module": "clut",
+    "rtl_files": [
+      "hardware/mem/clut.v"
+    ]
+  },
+  {
+    "file_path": "hardware/tests/mem/vram.py",
+    "tb_type": "cocotb",
+    "simulator": "icarus",
+    "makefile_path": "hardware/tests/mem/vram.mk",
+    "top_module": "vram",
+    "rtl_files": [
+      "hardware/mem/vram.v"
+    ]
+  }
+]

scarv_xcrypto/sim_script_map.json

@@ -0,0 +1,4 @@
+{
+  "rtl/p_mul/p_mul_tb.v": "p_mul_tb_sim.sh",
+  "rtl/xc_malu/xc_malu_tb.v": "xc_malu_tb_sim.sh"
+}

scarv_xcrypto/simulations.jsonl

@@ -0,0 +1,2 @@
+{"tb_file_path": "rtl/p_mul/p_mul_tb.v", "simulator": "iverilog", "top_module": "p_mul_tb", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["rtl/p_mul/p_mul_tb.v", "rtl/p_mul/p_mul.v", "rtl/p_mul/p_mul_checker.v", "rtl/p_addsub/p_addsub.v", "rtl/p_shfrot/p_shfrot.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_p_mul.fst"}
+{"tb_file_path": "rtl/xc_malu/xc_malu_tb.v", "simulator": "iverilog", "top_module": "xc_malu_tb", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["rtl/xc_malu/xc_malu_tb.v", "rtl/xc_malu/xc_malu.v", "rtl/xc_malu/xc_malu_muldivrem.v", "rtl/xc_malu/xc_malu_divrem.v", "rtl/xc_malu/xc_malu_mul.v", "rtl/xc_malu/xc_malu_pmul.v", "rtl/xc_malu/xc_malu_long.v", "rtl/p_addsub/p_addsub.v", "rtl/p_mul/p_mul_checker.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_xc_malu.fst"}

scarv_xcrypto/testbenches.json

@@ -0,0 +1,30 @@
+[
+  {
+    "file_path": "rtl/p_mul/p_mul_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "p_mul",
+    "rtl_files": [
+      "rtl/p_mul/p_mul.v",
+      "rtl/p_addsub/p_addsub.v",
+      "rtl/p_shfrot/p_shfrot.v"
+    ]
+  },
+  {
+    "file_path": "rtl/xc_malu/xc_malu_tb.v",
+    "tb_type": "verilog",
+    "simulator": "icarus",
+    "makefile_path": null,
+    "top_module": "xc_malu",
+    "rtl_files": [
+      "rtl/xc_malu/xc_malu.v",
+      "rtl/xc_malu/xc_malu_muldivrem.v",
+      "rtl/xc_malu/xc_malu_divrem.v",
+      "rtl/xc_malu/xc_malu_mul.v",
+      "rtl/xc_malu/xc_malu_pmul.v",
+      "rtl/xc_malu/xc_malu_long.v",
+      "rtl/p_addsub/p_addsub.v"
+    ]
+  }
+]

scarv_xcrypto/waveform_map.json

@@ -0,0 +1,4 @@
+{
+  "rtl/p_mul/p_mul_tb.v": "wave_p_mul.fst",
+  "rtl/xc_malu/xc_malu_tb.v": "wave_xc_malu.fst"
+}