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JN513_Risco-5/source/src/peripheral/gpios.v JN513_Risco-5/source/src/peripheral/leds.v JN513_Risco-5/source/src/peripheral/memory.v JN513_Risco-5/source/src/peripheral/pwm.v JN513_Risco-5/source/src/peripheral/soc.v JN513_Risco-5/source/src/peripheral/uart.v JN513_Risco-5/source/src/peripheral/uart_rx.v JN513_Risco-5/source/src/peripheral/uart_tx.v JN513_Risco-5/source/tests/alu_test.v JN513_Risco-5/source/tests/clk_divider.v JN513_Risco-5/source/tests/core_test.v JN513_Risco-5/source/tests/fifo_test.v JN513_Risco-5/source/tests/gpio_test.v JN513_Risco-5/source/tests/immediate_generator_test.v JN513_Risco-5/source/tests/mux_test.v JN513_Risco-5/source/tests/pc_test.v JN513_Risco-5/source/tests/registers_test.v JN513_Risco-5/source/tests/reset_test.v JN513_Risco-5/source/tests/soc_test.v MohamedHussein27_AMPA_APB4_Protocol/candidates/APB_Wrapper__APB_Master/bugs/inverted_condition/buggy_waveform.fst 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MohamedHussein27_AMPA_APB4_Protocol/candidates/APB_Wrapper__APB_Slave/bugs/wrong_bitwidth/buggy_waveform.fst MohamedHussein27_AMPA_APB4_Protocol/candidates/APB_Wrapper__APB_Slave/bugs/wrong_bitwidth/diff.patch MohamedHussein27_AMPA_APB4_Protocol/candidates/APB_Wrapper__APB_Slave/bugs/wrong_bitwidth/metadata.json MohamedHussein27_AMPA_APB4_Protocol/candidates/APB_Wrapper__APB_Slave/bugs/wrong_bitwidth/sim_log.txt MohamedHussein27_AMPA_APB4_Protocol/candidates/APB_Wrapper__APB_Slave/golden_waveform.fst MohamedHussein27_AMPA_APB4_Protocol/candidates/APB_Wrapper__APB_Slave/sim.sh MohamedHussein27_AMPA_APB4_Protocol/candidates/APB_Wrapper__APB_Wrapper/bugs/unconnected_port/buggy_waveform.fst MohamedHussein27_AMPA_APB4_Protocol/candidates/APB_Wrapper__APB_Wrapper/bugs/unconnected_port/diff.patch MohamedHussein27_AMPA_APB4_Protocol/candidates/APB_Wrapper__APB_Wrapper/bugs/unconnected_port/metadata.json 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MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/inverted_condition/buggy_waveform.fst MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/inverted_condition/diff.patch MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/inverted_condition/metadata.json MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/inverted_condition/sim_log.txt MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/missing_enable/buggy_waveform.fst MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/missing_enable/diff.patch MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/missing_enable/metadata.json MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/missing_enable/sim_log.txt MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/missing_reset/buggy_waveform.fst MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/missing_reset/diff.patch MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/missing_reset/metadata.json MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/missing_reset/sim_log.txt MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/wrong_bitwidth/buggy_waveform.fst MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/wrong_bitwidth/diff.patch MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/wrong_bitwidth/metadata.json MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/bugs/wrong_bitwidth/sim_log.txt MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/golden_waveform.fst MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__RAM/sim.sh MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/inverted_condition/buggy_waveform.fst MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/inverted_condition/diff.patch MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/inverted_condition/metadata.json MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/inverted_condition/sim_log.txt MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/missing_enable/buggy_waveform.fst MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/missing_enable/diff.patch MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/missing_enable/metadata.json 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thedatabusdotio_fpga-ml-accelerator/candidates/acclerator__variable_shift_reg/bugs/wrong_bitwidth/metadata.json thedatabusdotio_fpga-ml-accelerator/candidates/acclerator__variable_shift_reg/bugs/wrong_bitwidth/sim_log.txt thedatabusdotio_fpga-ml-accelerator/candidates/acclerator__variable_shift_reg/golden_waveform.fst thedatabusdotio_fpga-ml-accelerator/candidates/acclerator__variable_shift_reg/sim.sh thedatabusdotio_fpga-ml-accelerator/sim_script_map.json thedatabusdotio_fpga-ml-accelerator/simulations.jsonl thedatabusdotio_fpga-ml-accelerator/source/README.md thedatabusdotio_fpga-ml-accelerator/source/accelerator.v thedatabusdotio_fpga-ml-accelerator/source/accelerator_tb.v thedatabusdotio_fpga-ml-accelerator/source/comparator2.v thedatabusdotio_fpga-ml-accelerator/source/control_logic2.v thedatabusdotio_fpga-ml-accelerator/source/convolver.v thedatabusdotio_fpga-ml-accelerator/source/convolver_tb.v thedatabusdotio_fpga-ml-accelerator/source/input_mux.v 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zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/operator_typo/diff.patch zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/operator_typo/metadata.json zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/operator_typo/sim_log.txt zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/wrong_bitwidth/buggy_waveform.fst zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/wrong_bitwidth/diff.patch zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/wrong_bitwidth/metadata.json zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/wrong_bitwidth/sim_log.txt zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/golden_waveform.fst zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/sim.sh zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/concat_swap/buggy_waveform.fst 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zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/sim.sh zhangxin6_iverilog_testbench/sim_script_map.json zhangxin6_iverilog_testbench/simulations.jsonl zhangxin6_iverilog_testbench/source/bat/display_pal_testbench.bat zhangxin6_iverilog_testbench/source/bat/display_pal_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/display_pal_testbench.vcd zhangxin6_iverilog_testbench/source/bat/display_pal_testbench.vvp zhangxin6_iverilog_testbench/source/bat/dsp_hdlc_ctrl_testbench.bat zhangxin6_iverilog_testbench/source/bat/dsp_hdlc_ctrl_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/dsp_hdlc_ctrl_testbench.vcd zhangxin6_iverilog_testbench/source/bat/dsp_hdlc_ctrl_testbench.vvp zhangxin6_iverilog_testbench/source/bat/emif_intf_z_testbench.bat zhangxin6_iverilog_testbench/source/bat/emif_intf_z_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/emif_intf_z_testbench.vcd zhangxin6_iverilog_testbench/source/bat/emif_intf_z_testbench.vvp zhangxin6_iverilog_testbench/source/bat/file_io_testbench.bat zhangxin6_iverilog_testbench/source/bat/file_io_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/file_io_testbench.vcd zhangxin6_iverilog_testbench/source/bat/file_io_testbench.vvp zhangxin6_iverilog_testbench/source/bat/hdlcrev_testbench.bat zhangxin6_iverilog_testbench/source/bat/hdlcrev_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/hdlcrev_testbench.vcd zhangxin6_iverilog_testbench/source/bat/hdlcrev_testbench.vvp zhangxin6_iverilog_testbench/source/bat/hdlctra_testbench.bat zhangxin6_iverilog_testbench/source/bat/hdlctra_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/hdlctra_testbench.vcd zhangxin6_iverilog_testbench/source/bat/hdlctra_testbench.vvp zhangxin6_iverilog_testbench/source/bat/insert0_testbench.bat zhangxin6_iverilog_testbench/source/bat/insert0_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/insert0_testbench.vcd zhangxin6_iverilog_testbench/source/bat/insert0_testbench.vvp zhangxin6_iverilog_testbench/source/connect_domain_get.v zhangxin6_iverilog_testbench/source/cpld_top.v zhangxin6_iverilog_testbench/source/data_gen.v zhangxin6_iverilog_testbench/source/display_pal.v zhangxin6_iverilog_testbench/source/display_pal_testbench.v zhangxin6_iverilog_testbench/source/dsp_hdlc_ctrl.v zhangxin6_iverilog_testbench/source/dsp_hdlc_ctrl_testbench.v zhangxin6_iverilog_testbench/source/emif_intf_z.v zhangxin6_iverilog_testbench/source/emif_intf_z_testbench.v zhangxin6_iverilog_testbench/source/file_io/1.txt zhangxin6_iverilog_testbench/source/file_io/1.txt.png zhangxin6_iverilog_testbench/source/file_io/2.txt zhangxin6_iverilog_testbench/source/file_io/2.txt.png zhangxin6_iverilog_testbench/source/file_io/3.txt zhangxin6_iverilog_testbench/source/file_io/4.txt zhangxin6_iverilog_testbench/source/file_io/4.txt.png zhangxin6_iverilog_testbench/source/file_io/5.txt zhangxin6_iverilog_testbench/source/file_io/5.txt.png zhangxin6_iverilog_testbench/source/file_io/convert.m zhangxin6_iverilog_testbench/source/file_io/lena_32.jpg zhangxin6_iverilog_testbench/source/file_io_testbench.v zhangxin6_iverilog_testbench/source/flag_i0.v zhangxin6_iverilog_testbench/source/gpio_intf.v zhangxin6_iverilog_testbench/source/gpio_intr_gen.v zhangxin6_iverilog_testbench/source/hdlcrev.v zhangxin6_iverilog_testbench/source/hdlcrev_testbench.v zhangxin6_iverilog_testbench/source/hdlctra.v zhangxin6_iverilog_testbench/source/hdlctra_testbench.v zhangxin6_iverilog_testbench/source/insert0.v zhangxin6_iverilog_testbench/source/insert0_testbench.v zhangxin6_iverilog_testbench/testbenches.json with huggingface_hub

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MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/blocking_nonblocking/buggy_waveform.fst MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/blocking_nonblocking/diff.patch MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/blocking_nonblocking/metadata.json MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/blocking_nonblocking/sim_log.txt MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/delayed_signal/buggy_waveform.fst MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/delayed_signal/diff.patch MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/delayed_signal/metadata.json MohamedHussein27_SPI_Slave_With_Single_Port_Memory/candidates/SPI_Wrapper__SPI_SLAVE/bugs/delayed_signal/sim_log.txt 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MohamedHussein27_SPI_Slave_With_Single_Port_Memory/source/Simulation/SPI_Wrapper_tb.v OrsuVenkataKrishnaiah1235_RTL-Coding/candidates/Graytobinary__Graytobinary/bugs/operator_typo/buggy_waveform.fst OrsuVenkataKrishnaiah1235_RTL-Coding/candidates/Graytobinary__Graytobinary/bugs/operator_typo/diff.patch OrsuVenkataKrishnaiah1235_RTL-Coding/candidates/Graytobinary__Graytobinary/bugs/operator_typo/metadata.json OrsuVenkataKrishnaiah1235_RTL-Coding/candidates/Graytobinary__Graytobinary/bugs/operator_typo/sim_log.txt OrsuVenkataKrishnaiah1235_RTL-Coding/candidates/Graytobinary__Graytobinary/golden_waveform.fst OrsuVenkataKrishnaiah1235_RTL-Coding/candidates/Graytobinary__Graytobinary/sim.sh OrsuVenkataKrishnaiah1235_RTL-Coding/candidates/srff__srff/bugs/blocking_nonblocking/buggy_waveform.fst OrsuVenkataKrishnaiah1235_RTL-Coding/candidates/srff__srff/bugs/blocking_nonblocking/diff.patch OrsuVenkataKrishnaiah1235_RTL-Coding/candidates/srff__srff/bugs/blocking_nonblocking/metadata.json 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Adder Using Half Adder/Full Adder Waveform.png OrsuVenkataKrishnaiah1235_RTL-Coding/source/11.Full Adder Using Half Adder/Full_Adder.v OrsuVenkataKrishnaiah1235_RTL-Coding/source/11.Full Adder Using Half Adder/Full_Adder_Tb.v OrsuVenkataKrishnaiah1235_RTL-Coding/source/12,Full Subtractor/Full_Substractor.v OrsuVenkataKrishnaiah1235_RTL-Coding/source/12,Full Subtractor/Full_Subtractor_tb.v OrsuVenkataKrishnaiah1235_RTL-Coding/source/12,Full Subtractor/Screenshot from 2022-12-12 22-05-35.png OrsuVenkataKrishnaiah1235_RTL-Coding/source/12,Full Subtractor/Screenshot from 2022-12-12 22-05-52.png OrsuVenkataKrishnaiah1235_RTL-Coding/source/13.Full Subtractor using Half Substractor/Full_Subtractor.v OrsuVenkataKrishnaiah1235_RTL-Coding/source/13.Full Subtractor using Half Substractor/Full_Subtractor_Tb.v OrsuVenkataKrishnaiah1235_RTL-Coding/source/13.Full Subtractor using Half Substractor/Screenshot from 2022-12-12 22-05-35.png OrsuVenkataKrishnaiah1235_RTL-Coding/source/13.Full Subtractor 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thedatabusdotio_fpga-ml-accelerator/candidates/acclerator__variable_shift_reg/sim.sh thedatabusdotio_fpga-ml-accelerator/source/README.md thedatabusdotio_fpga-ml-accelerator/source/accelerator.v thedatabusdotio_fpga-ml-accelerator/source/accelerator_tb.v thedatabusdotio_fpga-ml-accelerator/source/comparator2.v thedatabusdotio_fpga-ml-accelerator/source/control_logic2.v thedatabusdotio_fpga-ml-accelerator/source/convolver.v thedatabusdotio_fpga-ml-accelerator/source/convolver_tb.v thedatabusdotio_fpga-ml-accelerator/source/input_mux.v thedatabusdotio_fpga-ml-accelerator/source/mac_manual.v thedatabusdotio_fpga-ml-accelerator/source/max_reg.v thedatabusdotio_fpga-ml-accelerator/source/pooler.v thedatabusdotio_fpga-ml-accelerator/source/qadd.v thedatabusdotio_fpga-ml-accelerator/source/qmult.v thedatabusdotio_fpga-ml-accelerator/source/relu.v thedatabusdotio_fpga-ml-accelerator/source/tanh_data.mem thedatabusdotio_fpga-ml-accelerator/source/tanh_lut.v thedatabusdotio_fpga-ml-accelerator/source/variable_shift_reg.v zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/case_swap/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/case_swap/diff.patch zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/case_swap/metadata.json zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/case_swap/sim_log.txt zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/delayed_signal/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/delayed_signal/diff.patch zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/delayed_signal/metadata.json zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/delayed_signal/sim_log.txt zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/inverted_condition/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/inverted_condition/diff.patch zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/inverted_condition/metadata.json zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/inverted_condition/sim_log.txt zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/missing_enable/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/missing_enable/diff.patch zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/missing_enable/metadata.json zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/missing_enable/sim_log.txt zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/missing_reset/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/missing_reset/diff.patch zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/missing_reset/metadata.json zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/missing_reset/sim_log.txt zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/off_by_one_counter/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/off_by_one_counter/diff.patch zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/off_by_one_counter/metadata.json zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/off_by_one_counter/sim_log.txt zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/operator_typo/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/operator_typo/diff.patch zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/operator_typo/metadata.json zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/operator_typo/sim_log.txt zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/signal_typo/diff.patch zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/signal_typo/metadata.json zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/signal_typo/sim_log.txt zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/wrong_bitwidth/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/wrong_bitwidth/diff.patch zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/wrong_bitwidth/metadata.json zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/wrong_bitwidth/sim_log.txt zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/golden_waveform.fst zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/sim.sh zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/concat_swap/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/concat_swap/diff.patch zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/concat_swap/metadata.json zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/concat_swap/sim_log.txt zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/delayed_signal/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/delayed_signal/diff.patch zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/delayed_signal/metadata.json zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/delayed_signal/sim_log.txt zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/inverted_condition/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/inverted_condition/diff.patch zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/inverted_condition/metadata.json zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/inverted_condition/sim_log.txt zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/missing_reset/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/missing_reset/diff.patch zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/missing_reset/metadata.json zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/missing_reset/sim_log.txt zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/off_by_one_counter/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/off_by_one_counter/diff.patch zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/off_by_one_counter/metadata.json zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/off_by_one_counter/sim_log.txt zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/operator_typo/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/operator_typo/diff.patch zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/operator_typo/metadata.json zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/operator_typo/sim_log.txt zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/signal_typo/diff.patch zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/signal_typo/metadata.json zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/signal_typo/sim_log.txt zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/state_transition/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/state_transition/diff.patch zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/state_transition/metadata.json zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/state_transition/sim_log.txt zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/unconnected_port/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/unconnected_port/diff.patch zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/unconnected_port/metadata.json zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/unconnected_port/sim_log.txt zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/wrong_bitwidth/buggy_waveform.vcd zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/wrong_bitwidth/diff.patch zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/wrong_bitwidth/metadata.json zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/wrong_bitwidth/sim_log.txt zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/golden_waveform.fst zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/sim.sh zhangxin6_iverilog_testbench/source/bat/display_pal_testbench.bat zhangxin6_iverilog_testbench/source/bat/display_pal_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/display_pal_testbench.vcd zhangxin6_iverilog_testbench/source/bat/display_pal_testbench.vvp zhangxin6_iverilog_testbench/source/bat/dsp_hdlc_ctrl_testbench.bat zhangxin6_iverilog_testbench/source/bat/dsp_hdlc_ctrl_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/dsp_hdlc_ctrl_testbench.vcd zhangxin6_iverilog_testbench/source/bat/dsp_hdlc_ctrl_testbench.vvp zhangxin6_iverilog_testbench/source/bat/emif_intf_z_testbench.bat zhangxin6_iverilog_testbench/source/bat/emif_intf_z_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/emif_intf_z_testbench.vcd zhangxin6_iverilog_testbench/source/bat/emif_intf_z_testbench.vvp zhangxin6_iverilog_testbench/source/bat/file_io_testbench.bat zhangxin6_iverilog_testbench/source/bat/file_io_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/file_io_testbench.vcd zhangxin6_iverilog_testbench/source/bat/file_io_testbench.vvp zhangxin6_iverilog_testbench/source/bat/hdlcrev_testbench.bat zhangxin6_iverilog_testbench/source/bat/hdlcrev_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/hdlcrev_testbench.vcd zhangxin6_iverilog_testbench/source/bat/hdlcrev_testbench.vvp zhangxin6_iverilog_testbench/source/bat/hdlctra_testbench.bat zhangxin6_iverilog_testbench/source/bat/hdlctra_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/hdlctra_testbench.vcd zhangxin6_iverilog_testbench/source/bat/hdlctra_testbench.vvp zhangxin6_iverilog_testbench/source/bat/insert0_testbench.bat zhangxin6_iverilog_testbench/source/bat/insert0_testbench.gtkw zhangxin6_iverilog_testbench/source/bat/insert0_testbench.vcd zhangxin6_iverilog_testbench/source/bat/insert0_testbench.vvp zhangxin6_iverilog_testbench/source/connect_domain_get.v zhangxin6_iverilog_testbench/source/cpld_top.v zhangxin6_iverilog_testbench/source/data_gen.v zhangxin6_iverilog_testbench/source/display_pal.v zhangxin6_iverilog_testbench/source/display_pal_testbench.v zhangxin6_iverilog_testbench/source/dsp_hdlc_ctrl.v zhangxin6_iverilog_testbench/source/dsp_hdlc_ctrl_testbench.v zhangxin6_iverilog_testbench/source/emif_intf_z.v zhangxin6_iverilog_testbench/source/emif_intf_z_testbench.v zhangxin6_iverilog_testbench/source/file_io/1.txt zhangxin6_iverilog_testbench/source/file_io/1.txt.png zhangxin6_iverilog_testbench/source/file_io/2.txt zhangxin6_iverilog_testbench/source/file_io/2.txt.png zhangxin6_iverilog_testbench/source/file_io/3.txt zhangxin6_iverilog_testbench/source/file_io/4.txt zhangxin6_iverilog_testbench/source/file_io/4.txt.png zhangxin6_iverilog_testbench/source/file_io/5.txt zhangxin6_iverilog_testbench/source/file_io/5.txt.png zhangxin6_iverilog_testbench/source/file_io/convert.m zhangxin6_iverilog_testbench/source/file_io/lena_32.jpg zhangxin6_iverilog_testbench/source/file_io_testbench.v zhangxin6_iverilog_testbench/source/flag_i0.v zhangxin6_iverilog_testbench/source/gpio_intf.v zhangxin6_iverilog_testbench/source/gpio_intr_gen.v zhangxin6_iverilog_testbench/source/hdlcrev.v zhangxin6_iverilog_testbench/source/hdlcrev_testbench.v zhangxin6_iverilog_testbench/source/hdlctra.v zhangxin6_iverilog_testbench/source/hdlctra_testbench.v zhangxin6_iverilog_testbench/source/insert0.v zhangxin6_iverilog_testbench/source/insert0_testbench.v with huggingface_hub

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