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Datasets:
architect-ubc-capstone
/
rtl-augmented-v3
like
0
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ubc-capstone
5
Tasks:
Text Generation
Size:
1K<n<10K
Tags:
rtl
verilog
bug-fix
sft
License:
mit
Dataset card
Files
Files and versions
xet
Community
1
main
rtl-augmented-v3
/
wicker_SystemVerilog-FSM
/
sim_script_map.json
Commit History
Add files using upload-large-folder tool
9189c48
verified
googhieman
commited on
Apr 7
googhieman commited on 
