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Datasets:
architect-ubc-capstone
/
rtl-augmented-v3
like
0
Follow
ubc-capstone
5
Tasks:
Text Generation
Size:
1K<n<10K
Tags:
rtl
verilog
bug-fix
sft
License:
mit
Dataset card
Files
Files and versions
xet
Community
1
main
rtl-augmented-v3
/
daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules
/
source
37.6 kB
4 contributors
History:
1 commit
AveryWong03
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LICENSE
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README.md
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spi_clgen.v
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spi_clgen_tb.v
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spi_defines.v
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spi_shift_reg.v
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spi_shift_reg_tb.v
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spi_slave.v
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spi_top.v
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tb.v
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wishbone_master.v
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