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Datasets:
architect-ubc-capstone
/
rtl-augmented-v3
like
0
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ubc-capstone
5
Tasks:
Text Generation
Size:
1K<n<10K
Tags:
rtl
verilog
bug-fix
sft
License:
mit
Dataset card
Files
Files and versions
xet
Community
1
main
rtl-augmented-v3
/
qossayrida_PipelineProcessorDesign
/
source
96.3 MB
4 contributors
History:
3 commits
googhieman
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9381ef5
verified
2 months ago
PipelineProcessor
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2 months ago
PipelineProcessorDesign-master.rar
8.91 MB
xet
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2 months ago
PipelineProcessorDesign.aws
169 Bytes
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PipelineProcessorDesign.wsw
452 Bytes
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2 months ago
README.md
6.45 kB
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2 months ago
Report.pdf
2.59 MB
xet
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2 months ago
library.cfg
127 Bytes
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2 months ago
