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Datasets:
architect-ubc-capstone
/
rtl-augmented-v3
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ubc-capstone
5
Tasks:
Text Generation
Size:
1K<n<10K
Tags:
rtl
verilog
bug-fix
sft
License:
mit
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xet
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rtl-augmented-v3
/
thedatabusdotio_fpga-ml-accelerator
393 kB
4 contributors
History:
10 commits
AveryWong03
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candidates
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source
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sim_script_map.json
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simulations.jsonl
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testbenches.json
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waveform_map.json
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