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The dataset generation failed
Error code: DatasetGenerationError
Exception: IndexError
Message: list index out of range
Traceback: Traceback (most recent call last):
File "/usr/local/lib/python3.12/site-packages/datasets/builder.py", line 1901, in _prepare_split_single
original_shard_lengths[original_shard_id] += len(table)
~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^
IndexError: list index out of range
The above exception was the direct cause of the following exception:
Traceback (most recent call last):
File "/src/services/worker/src/worker/job_runners/config/parquet_and_info.py", line 1347, in compute_config_parquet_and_info_response
parquet_operations = convert_to_parquet(builder)
^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/src/services/worker/src/worker/job_runners/config/parquet_and_info.py", line 980, in convert_to_parquet
builder.download_and_prepare(
File "/usr/local/lib/python3.12/site-packages/datasets/builder.py", line 884, in download_and_prepare
self._download_and_prepare(
File "/usr/local/lib/python3.12/site-packages/datasets/builder.py", line 947, in _download_and_prepare
self._prepare_split(split_generator, **prepare_split_kwargs)
File "/usr/local/lib/python3.12/site-packages/datasets/builder.py", line 1739, in _prepare_split
for job_id, done, content in self._prepare_split_single(
^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/usr/local/lib/python3.12/site-packages/datasets/builder.py", line 1922, in _prepare_split_single
raise DatasetGenerationError("An error occurred while generating the dataset") from e
datasets.exceptions.DatasetGenerationError: An error occurred while generating the datasetNeed help to make the dataset viewer work? Make sure to review how to configure the dataset viewer, and open a discussion for direct support.
messages list |
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[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"singly_linked_list.... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"hash_table.sv\">\n`... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"counter_tx.v\">\n \... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"i2c_slave_axil_mast... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"singly_linked_list.... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"i2c_master.v\">\n/*... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"cal.sv\">\n// Calib... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"lifo.sv\">\nmodule ... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"i2c_master.v\">\n/*... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"transmitter.v\">\n\... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"i2c_master.v\">\n/*... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"bfu_internal.v\">\n... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"i2c_master.v\">\n/*... |
[
{
"role": "system",
"content": "You are an expert RTL debugger specializing in SystemVerilog and Verilog. Given buggy RTL source code, identify the bug and output only a unified diff that fixes it. Output nothing except the diff."
},
{
"role": "user",
"content": "<file name=\"fifo.sv\">\nmodule ... |
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