| {"repo": "mnasser431998/bfu_dif_fft_rtl", "bug_type": "missing_else_latch", "files_modified": ["src/cos_lut.v"], "signals_affected": ["data"], "bug_dir": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__cos_lut/missing_else_latch", "diff": "--- a/src/cos_lut.v\n+++ b/src/cos_lut.v\n@@ -39,6 +39,4 @@\n \t\t\tdata = {2 * ROM_WIDTH {1'b0}};\n \t\telse if ((quad == 'd3) || (quad == 'd0))\n \t\t\tdata = {{ROM_WIDTH {1'b0}}, tab_data};\n-\t\telse\n-\t\t\tdata = {2 * ROM_WIDTH {1'b0}} - {{ROM_WIDTH {1'b0}}, tab_data};\n-endmodule+endmodule\n", "original_path": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__cos_lut/missing_else_latch/original_cos_lut.v"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "missing_reset", "files_modified": ["rtl/i2c_slave_wbm.v"], "signals_affected": ["wb_stb_o_reg", "wb_cyc_o_reg"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_slave_wbm__i2c_slave_wbm/missing_reset", "diff": "--- a/rtl/i2c_slave_wbm.v\n+++ b/rtl/i2c_slave_wbm.v\n@@ -256,6 +256,10 @@\n assign wb_cyc_o = wb_cyc_o_reg;\n \n assign busy = busy_reg;\n+\n+// Force unknown initial state \u2014 makes missing reset observable\n+initial wb_stb_o_reg = 1'bx;\n+initial wb_cyc_o_reg = 1'bx;\n \n always @* begin\n state_next = STATE_IDLE;\n@@ -443,8 +447,6 @@\n state_reg <= STATE_IDLE;\n data_in_valid_reg <= 1'b0;\n data_out_ready_reg <= 1'b0;\n- wb_stb_o_reg <= 1'b0;\n- wb_cyc_o_reg <= 1'b0;\n busy_reg <= 1'b0;\n end\n end\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_slave_wbm__i2c_slave_wbm/missing_reset/original_i2c_slave_wbm.v"} |
| {"repo": "apfaudio/eurorack-pmod", "bug_type": "operator_typo", "files_modified": ["gateware/cores/vca.sv"], "signals_affected": ["sample_out1"], "bug_dir": "../data-pipeline/repos_augmented/apfaudio_eurorack-pmod/vca__vca/operator_typo", "diff": "--- a/gateware/cores/vca.sv\n+++ b/gateware/cores/vca.sv\n@@ -38,7 +38,7 @@\n assign vca2 = sample_in2 * sample_in3;\n \n assign sample_out0 = sample_in0;\n-assign sample_out1 = W'(vca1 >>> W);\n+assign sample_out1 = W'(vca1 <<< W);\n assign sample_out2 = sample_in2;\n assign sample_out3 = W'(vca2 >>> W);\n \n", "original_path": "../data-pipeline/repos_augmented/apfaudio_eurorack-pmod/vca__vca/operator_typo/original_vca.sv"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "operator_typo", "files_modified": ["rtl/i2c_slave.v"], "signals_affected": ["bus_addressed", "addr_reg", "state_next"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_slave__i2c_slave/operator_typo", "diff": "--- a/rtl/i2c_slave.v\n+++ b/rtl/i2c_slave.v\n@@ -83,7 +83,7 @@\n Read\n __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __\n sda \\__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\\_A____/\n- ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____\n+ ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____\n scl ST \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ SP\n \n Write\n@@ -297,7 +297,7 @@\n state_next = STATE_ADDRESS;\n end else begin\n // check address\n- if (enable && (device_address & device_address_mask) == (data_reg[6:0] & device_address_mask)) begin\n+ if (enable && (device_address | device_address_mask) == (data_reg[6:0] & device_address_mask)) begin\n // it's a match, save read/write bit and send ACK\n addr_next = data_reg[6:0];\n mode_read_next = sda_i_reg;\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_slave__i2c_slave/operator_typo/original_i2c_slave.v"} |
| {"repo": "ttchisholm/10g-low-latency-ethernet", "bug_type": "inverted_condition", "files_modified": ["src/hdl/pcs/tx_gearbox.sv"], "signals_affected": ["load_header"], "bug_dir": "../data-pipeline/repos_augmented/ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/inverted_condition", "diff": "--- a/src/hdl/pcs/tx_gearbox.sv\n+++ b/src/hdl/pcs/tx_gearbox.sv\n@@ -105,7 +105,7 @@\n end\n \n if (!i_pause) begin // Source 1\n- if (load_header) begin\n+ if (!load_header) begin\n if (gi >= header_idx && gi < header_idx + 2) begin\n next_obuf[gi] = i_header[gi-header_idx];\n end\n", "original_path": "../data-pipeline/repos_augmented/ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/inverted_condition/original_tx_gearbox.sv"} |
| {"repo": "Weiyet/RTLStructLib", "bug_type": "inverted_condition", "files_modified": ["Doubly_Linked_List/src/doubly_linked_list.sv"], "signals_affected": ["data_rd_buf", "data_in"], "bug_dir": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/doubly_linked_list__doubly_linked_list/inverted_condition", "diff": "--- a/Doubly_Linked_List/src/doubly_linked_list.sv\n+++ b/Doubly_Linked_List/src/doubly_linked_list.sv\n@@ -294,7 +294,7 @@\n end\n end\n FIND_VALUE: begin \n- if(data_rd_buf == data_in) begin \n+ if(data_rd_buf != data_in) begin // Was data_rd_buf == data_in, now inverted\n // update curr pos to invalid\n wr_req <= 1'b1;\n target_idx <= cur_ptr;\n", "original_path": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/doubly_linked_list__doubly_linked_list/inverted_condition/original_doubly_linked_list.sv"} |
| {"repo": "mnasser431998/bfu_dif_fft_rtl", "bug_type": "missing_reset", "files_modified": ["src/cmx_mult.v"], "signals_affected": ["ar_ddd", "ar_dddd", "addr", "multr", "commonr1", "pr_int"], "bug_dir": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__cmx_mult/missing_reset", "diff": "--- a/src/cmx_mult.v\n+++ b/src/cmx_mult.v\n@@ -39,6 +39,12 @@\n \n reg signed [AWIDTH+BWIDTH:0] common, commonr1, commonr2 ;\n \n+ initial ar_ddd = {AWIDTH{1'bx}};\n+ initial ar_dddd = {AWIDTH{1'bx}};\n+ initial addr = {(BWIDTH+1){1'bx}};\n+ initial multr = {(AWIDTH+BWIDTH+1){1'bx}};\n+ initial commonr1 = {(AWIDTH+BWIDTH+1){1'bx}};\n+ initial pr_int = {(AWIDTH+BWIDTH+1){1'bx}};\n \n always @(posedge clk or negedge reset_n)\n begin\n@@ -132,17 +138,6 @@\n \n if (!reset_n)\n begin\n- ar_ddd <= 'h0;\n-\n- ar_dddd <= 'h0;\n-\n- addr <= 'h0;\n-\n- multr <= 'h0;\n-\n- commonr1 <= 'h0;\n-\n- pr_int <= 'h0;\n end\n else\n begin\n", "original_path": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__cmx_mult/missing_reset/original_cmx_mult.v"} |
| {"repo": "Weiyet/RTLStructLib", "bug_type": "inverted_condition", "files_modified": ["List/src/sorter.sv"], "signals_affected": ["temp", "data_sorted_unpacked", "sort_order"], "bug_dir": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/list__sorter/inverted_condition", "diff": "--- a/List/src/sorter.sv\n+++ b/List/src/sorter.sv\n@@ -125,12 +125,12 @@\n current_state <= NEXT_KEY;\n end \n end else begin\n- if(data_sorted_unpacked[cur_ptr] < temp) begin\n+ if(data_sorted_unpacked[cur_ptr] >= temp) begin\n data_sorted_unpacked[cur_ptr+1] <= data_sorted_unpacked[cur_ptr];\n data_sorted_unpacked[cur_ptr] <= temp;\n cur_ptr <= cur_ptr - 'b1;\n current_state <= (cur_ptr > 'd0) ? COMP_AND_SWAP : NEXT_KEY;\n- end else if(data_sorted_unpacked[cur_ptr] >= temp | cur_ptr == 'b0) begin\n+ end else if(data_sorted_unpacked[cur_ptr] < temp | cur_ptr == 'b0) begin\n data_sorted_unpacked[cur_ptr+1] <= temp;\n current_state <= NEXT_KEY;\n end\n@@ -146,4 +146,4 @@\n end\n end\n \n-endmodule+endmodule\n", "original_path": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/list__sorter/inverted_condition/original_sorter.sv"} |
| {"repo": "mnasser431998/bfu_dif_fft_rtl", "bug_type": "blocking_nonblocking", "files_modified": ["src/cmx_mult.v"], "signals_affected": ["mult0", "multr"], "bug_dir": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__cmx_mult/blocking_nonblocking", "diff": "--- a/src/cmx_mult.v\n+++ b/src/cmx_mult.v\n@@ -113,7 +113,7 @@\n begin\n addcommon <= ar_d - ai_d;\n \n- mult0 <= addcommon * bi_dd;\n+ mult0 = addcommon * bi_dd;\n \n common <= mult0;\n end\n@@ -152,7 +152,7 @@\n \n addr <= br_ddd - bi_ddd;\n \n- multr <= addr * ar_dddd;\n+ multr = addr * ar_dddd;\n \n commonr1 <= common;\n \n", "original_path": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__cmx_mult/blocking_nonblocking/original_cmx_mult.v"} |
| {"repo": "mnmhdanas/UART-protocol", "bug_type": "operator_typo", "files_modified": ["rtl/Transmitter/fsm_tx.v"], "signals_affected": ["o_startcounter", "o_shift"], "bug_dir": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/transmitter__fsm_tx/operator_typo", "diff": "--- a/rtl/Transmitter/fsm_tx.v\n+++ b/rtl/Transmitter/fsm_tx.v\n@@ -54,7 +54,7 @@\n \t\t\t\t\t\t begin\n \t\t\t\t\t\t\t o_resetcounter = 1'b1;\n o_load = 1'b1;\n- end\t\t\t\t\t\t\t\t\n+ end\t\t\t\t\t\t\t\n \t\t\t end\n \t\t\t\n \t\t\tSTART : begin\n@@ -69,7 +69,7 @@\n \t\t\tDATA : begin\n \t\t\t o_sel_1 = 1'b0;\n o_sel_0 = 1'b1; // to assign data to output\t\n-\t\t\t if(!i_countreached)\n+\t\t\t if(i_countreached)\n \t\t\t\t\t\t begin\n \t\t\t\t\t\t o_startcounter = 1'b1;\n \t\t\t\t\t\t\t o_shift = 1'b1;\n@@ -98,4 +98,3 @@\n \t\tend\n \t\t\n endmodule\n-\t\t", "original_path": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/transmitter__fsm_tx/operator_typo/original_fsm_tx.v"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "missing_reset", "files_modified": ["rtl/i2c_master_wbs_16.v"], "signals_affected": ["prescale_reg"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_wbs_16__i2c_master_wbs_16/missing_reset", "diff": "--- a/rtl/i2c_master_wbs_16.v\n+++ b/rtl/i2c_master_wbs_16.v\n@@ -66,191 +66,6 @@\n output wire i2c_sda_o,\n output wire i2c_sda_t\n );\n-/*\n-\n-I2C\n-\n-Read\n- __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __\n-sda \\__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\\_A____/\n- ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____\n-scl ST \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ SP\n-\n-Write\n- __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __\n-sda \\__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ W \\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \\__/\n- ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____\n-scl ST \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ SP\n-\n-Registers:\n-\n-| Addr | Name |\n-|-------|---------------|\n-| 0x00 | Status |\n-| 0x02 | Command |\n-| 0x04 | Data |\n-| 0x06 | Prescale |\n-\n-Status register:\n-\n-| Addr | Name | Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 |\n-|-------|---------------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|\n-| 0x00 | Status | rd_full | rd_empty | wr_ovf | wr_full | wr_empty | cmd_ovf | cmd_full | cmd_empty |\n-\n-| Addr | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |\n-|-------|---------------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|\n-| 0x00 | Status | - | - | - | - | miss_ack | bus_act | bus_cont | busy |\n-\n-busy: high when module is performing an I2C operation\n-bus_cont: high when module has control of active bus\n-bus_act: high when bus is active\n-miss_ack: set high when an ACK pulse from a slave device is not seen; write 1 to clear\n-cmd_empty: command FIFO empty\n-cmd_full: command FIFO full\n-cmd_ovf: command FIFO overflow; write 1 to clear\n-wr_empty: write data FIFO empty\n-wr_full: write data FIFO full\n-wr_ovf: write data FIFO overflow; write 1 to clear\n-rd_empty: read data FIFO is empty\n-rd_full: read data FIFO is full\n-\n-Command register:\n-\n-| Addr | Name | Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 |\n-|-------|---------------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|\n-| 0x02 | Command | - | - | - | cmd_stop | cmd_wr_m | cmd_write | cmd_read | cmd_start |\n-\n-| Addr | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |\n-|-------|---------------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|\n-| 0x02 | Command | - | cmd_address[6:0] |\n-\n-cmd_address: I2C address for command\n-cmd_start: set high to issue I2C start, write to push on command FIFO\n-cmd_read: set high to start read, write to push on command FIFO\n-cmd_write: set high to start write, write to push on command FIFO\n-cmd_write_multiple: set high to start block write, write to push on command FIFO\n-cmd_stop: set high to issue I2C stop, write to push on command FIFO\n-\n-Setting more than one command bit is allowed. Start or repeated start\n-will be issued first, followed by read or write, followed by stop. Note\n-that setting read and write at the same time is not allowed, this will\n-result in the command being ignored. \n-\n-Data register:\n-\n-| Addr | Name | Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 |\n-|-------|---------------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|\n-| 0x04 | Data | - | - | - | - | - | - | data_last | data_valid|\n-\n-| Addr | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |\n-|-------|---------------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|\n-| 0x04 | Data | data[7:0] |\n-\n-data: I2C data, write to push on write data FIFO, read to pull from read data FIFO\n-data_valid: indicates valid read data, must be accessed with atomic 16 bit reads and writes\n-data_last: indicate last byte of block write (write_multiple), must be accessed with atomic 16 bit reads and writes\n-\n-Prescale register:\n-\n-| Addr | Name | Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 |\n-|-------|---------------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|\n-| 0x06 | Prescale | prescale[15:8] |\n-\n-| Addr | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |\n-|-------|---------------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|\n-| 0x06 | Prescale | prescale[7:0] |\n-\n-prescale: set prescale value\n-\n-set prescale to 1/4 of the minimum clock period in units of input clk cycles\n-\n-prescale = Fclk / (FI2Cclk * 4)\n-\n-Commands:\n-\n-read\n- read data byte\n- set start to force generation of a start condition\n- start is implied when bus is inactive or active with write or different address\n- set stop to issue a stop condition after reading current byte\n- if stop is set with read command, then data_out_last will be set\n-\n-write\n- write data byte\n- set start to force generation of a start condition\n- start is implied when bus is inactive or active with read or different address\n- set stop to issue a stop condition after writing current byte\n-\n-write multiple\n- write multiple data bytes (until data_in_last)\n- set start to force generation of a start condition\n- start is implied when bus is inactive or active with read or different address\n- set stop to issue a stop condition after writing block\n-\n-stop\n- issue stop condition if bus is active\n-\n-Status:\n-\n-busy\n- module is communicating over the bus\n-\n-bus_control\n- module has control of bus in active state\n-\n-bus_active\n- bus is active, not necessarily controlled by this module\n-\n-missed_ack\n- strobed when a slave ack is missed\n-\n-Parameters:\n-\n-prescale\n- set prescale to 1/4 of the minimum clock period in units\n- of input clk cycles (prescale = Fclk / (FI2Cclk * 4))\n-\n-stop_on_idle\n- automatically issue stop when command input is not valid\n-\n-Example of interfacing with tristate pins:\n-(this will work for any tristate bus)\n-\n-assign scl_i = scl_pin;\n-assign scl_pin = scl_t ? 1'bz : scl_o;\n-assign sda_i = sda_pin;\n-assign sda_pin = sda_t ? 1'bz : sda_o;\n-\n-Equivalent code that does not use *_t connections:\n-(we can get away with this because I2C is open-drain)\n-\n-assign scl_i = scl_pin;\n-assign scl_pin = scl_o ? 1'bz : 1'b0;\n-assign sda_i = sda_pin;\n-assign sda_pin = sda_o ? 1'bz : 1'b0;\n-\n-Example of two interconnected I2C devices:\n-\n-assign scl_1_i = scl_1_o & scl_2_o;\n-assign scl_2_i = scl_1_o & scl_2_o;\n-assign sda_1_i = sda_1_o & sda_2_o;\n-assign sda_2_i = sda_1_o & sda_2_o;\n-\n-Example of two I2C devices sharing the same pins:\n-\n-assign scl_1_i = scl_pin;\n-assign scl_2_i = scl_pin;\n-assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0;\n-assign sda_1_i = sda_pin;\n-assign sda_2_i = sda_pin;\n-assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0;\n-\n-Notes:\n-\n-scl_o should not be connected directly to scl_i, only via AND logic or a tristate\n-I/O pin. This would prevent devices from stretching the clock period.\n-\n-*/\n \n reg [15:0] wbs_dat_o_reg = 16'd0, wbs_dat_o_next;\n reg wbs_ack_o_reg = 1'b0, wbs_ack_o_next;\n@@ -314,6 +129,9 @@\n \n reg cmd_fifo_overflow_reg = 1'b0, cmd_fifo_overflow_next;\n reg write_fifo_overflow_reg = 1'b0, write_fifo_overflow_next;\n+\n+// Force unknown \u2014 makes missing reset observable\n+initial prescale_reg = 16'hxxxx;\n \n generate\n \n@@ -619,7 +437,6 @@\n cmd_valid_reg <= 1'b0;\n data_in_valid_reg <= 1'b0;\n data_out_ready_reg <= 1'b0;\n- prescale_reg <= DEFAULT_PRESCALE;\n missed_ack_reg <= 1'b0;\n cmd_fifo_overflow_reg <= 0;\n write_fifo_overflow_reg <= 0;\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_wbs_16__i2c_master_wbs_16/missing_reset/original_i2c_master_wbs_16.v"} |
| {"repo": "mnmhdanas/UART-protocol", "bug_type": "inverted_condition", "files_modified": ["rtl/Transmitter/piso_tx.v"], "signals_affected": ["i_shift"], "bug_dir": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/transmitter__piso_tx/inverted_condition", "diff": "--- a/rtl/Transmitter/piso_tx.v\n+++ b/rtl/Transmitter/piso_tx.v\n@@ -13,11 +13,10 @@\n \t\t begin\n \t\t if(i_load)\n \t\t\t tempreg <= i_datain;\n-\t\t else if(i_shift)\n+\t\t else if(!i_shift)\n begin\n \t\t\t\t o_serialdata <= tempreg[0];\n \t\t\t\t tempreg <= tempreg >> 1;\n end\t\t\t\t\n \t\t end\n \tendmodule\n-\t", "original_path": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/transmitter__piso_tx/inverted_condition/original_piso_tx.v"} |
| {"repo": "apfaudio/eurorack-pmod", "bug_type": "missing_reset", "files_modified": ["gateware/cal/cal.sv"], "signals_affected": ["out[0]", "out[1]", "out[2]", "out[3]"], "bug_dir": "../data-pipeline/repos_augmented/apfaudio_eurorack-pmod/cal__cal/missing_reset", "diff": "--- a/gateware/cal/cal.sv\n+++ b/gateware/cal/cal.sv\n@@ -71,15 +71,16 @@\n // 2 bytes shift, 2 bytes multiply * 8 channels.\n initial $readmemh(CAL_MEM_FILE, cal_mem);\n \n+initial out[0] = 'hx; // Force unknown \u2014 makes missing reset observable\n+initial out[1] = 'hx; // Force unknown \u2014 makes missing reset observable\n+initial out[2] = 'hx; // Force unknown \u2014 makes missing reset observable\n+initial out[3] = 'hx; // Force unknown \u2014 makes missing reset observable\n+\n always_ff @(posedge clk_256fs) begin\n \n if (rst) begin\n ch <= 0;\n state <= CAL_ST_LATCH;\n- out[0] <= 0;\n- out[1] <= 0;\n- out[2] <= 0;\n- out[3] <= 0;\n out[4] <= 0;\n out[5] <= 0;\n out[6] <= 0;\n", "original_path": "../data-pipeline/repos_augmented/apfaudio_eurorack-pmod/cal__cal/missing_reset/original_cal.sv"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "missing_reset", "files_modified": ["rtl/i2c_slave.v"], "signals_affected": ["m_axis_data_tvalid_reg"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_slave_axil_master__i2c_slave/missing_reset", "diff": "--- a/rtl/i2c_slave.v\n+++ b/rtl/i2c_slave.v\n@@ -76,97 +76,6 @@\n input wire [6:0] device_address,\n input wire [6:0] device_address_mask\n );\n-/*\n-\n-I2C\n-\n-Read\n- __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __\n-sda \\__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\\_A____/\n- ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____\n-scl ST \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ SP\n-\n-Write\n- __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __\n-sda \\__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ W \\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \\__/\n- ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____\n-scl ST \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ SP\n-\n-\n-Operation:\n-\n-This module translates I2C read and write operations into AXI stream transfers.\n-Bytes written over I2C will be delayed by one byte time so that the last byte\n-in a write operation can be accurately marked. When reading, the module will\n-stretch SCL by holding it low until a data byte is presented at the AXI stream\n-input. \n-\n-Control:\n-\n-release_bus\n- releases control over bus\n-\n-Status:\n-\n-busy\n- module is communicating over the bus\n-\n-bus_address\n- active address on bus when module is addressed\n-\n-bus_addressed\n- module is currently addressed on the bus\n-\n-bus_active\n- bus is active, not necessarily controlled by this module\n-\n-Parameters:\n-\n-device_address\n- address of slave device\n-\n-device_address_mask\n- select which bits of device address to compare, set to 7'h7f\n- to check all bits (single address device)\n-\n-Example of interfacing with tristate pins:\n-(this will work for any tristate bus)\n-\n-assign scl_i = scl_pin;\n-assign scl_pin = scl_t ? 1'bz : scl_o;\n-assign sda_i = sda_pin;\n-assign sda_pin = sda_t ? 1'bz : sda_o;\n-\n-Equivalent code that does not use *_t connections:\n-(we can get away with this because I2C is open-drain)\n-\n-assign scl_i = scl_pin;\n-assign scl_pin = scl_o ? 1'bz : 1'b0;\n-assign sda_i = sda_pin;\n-assign sda_pin = sda_o ? 1'bz : 1'b0;\n-\n-Example of two interconnected I2C devices:\n-\n-assign scl_1_i = scl_1_o & scl_2_o;\n-assign scl_2_i = scl_1_o & scl_2_o;\n-assign sda_1_i = sda_1_o & sda_2_o;\n-assign sda_2_i = sda_1_o & sda_2_o;\n-\n-Example of two I2C devices sharing the same pins:\n-\n-assign scl_1_i = scl_pin;\n-assign scl_2_i = scl_pin;\n-assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0;\n-assign sda_1_i = sda_pin;\n-assign sda_2_i = sda_pin;\n-assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0;\n-\n-Notes:\n-\n-scl_o should not be connected directly to scl_i, only via AND logic or a tristate\n-I/O pin. This would prevent devices from stretching the clock period.\n-\n-*/\n \n localparam [4:0]\n STATE_IDLE = 4'd0,\n@@ -211,6 +120,8 @@\n reg busy_reg = 1'b0;\n reg bus_active_reg = 1'b0;\n reg bus_addressed_reg = 1'b0, bus_addressed_next;\n+\n+initial m_axis_data_tvalid_reg = 1'bx; // Force unknown \u2014 makes missing reset observable\n \n assign bus_address = addr_reg;\n \n@@ -491,7 +402,6 @@\n if (rst) begin\n state_reg <= STATE_IDLE;\n s_axis_data_tready_reg <= 1'b0;\n- m_axis_data_tvalid_reg <= 1'b0;\n scl_o_reg <= 1'b1;\n sda_o_reg <= 1'b1;\n busy_reg <= 1'b0;\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_slave_axil_master__i2c_slave/missing_reset/original_i2c_slave.v"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "unconnected_port", "files_modified": ["rtl/i2c_master_wbs_16.v"], "signals_affected": ["data_out_last_int"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_wbs_16__i2c_master_wbs_16/unconnected_port", "diff": "--- a/rtl/i2c_master_wbs_16.v\n+++ b/rtl/i2c_master_wbs_16.v\n@@ -649,7 +649,7 @@\n .m_axis_data_tdata(data_out_int),\n .m_axis_data_tvalid(data_out_valid_int),\n .m_axis_data_tready(data_out_ready_int),\n- .m_axis_data_tlast(data_out_last_int),\n+ .m_axis_data_tlast(),\n \n // I2C interface\n .scl_i(i2c_scl_i),\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_wbs_16__i2c_master_wbs_16/unconnected_port/original_i2c_master_wbs_16.v"} |
| {"repo": "Weiyet/RTLStructLib", "bug_type": "missing_reset", "files_modified": ["List/src/list.sv"], "signals_affected": ["data_out", "op_done", "op_error"], "bug_dir": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/list__list/missing_reset", "diff": "--- a/List/src/list.sv\n+++ b/List/src/list.sv\n@@ -69,6 +69,11 @@\n reg [DATA_WIDTH-1:0] data_sorted [LENGTH-1:0];\n \n integer i;\n+\n+ // Force unknown \u2014 makes missing reset observable\n+ initial data_out = 'hx;\n+ initial op_done = 1'hx;\n+ initial op_error = 1'hx;\n \n assign op_is_read = (op_sel == 3'b000) & op_en;\n assign op_is_insert = (op_sel == 3'b001) & op_en;\n@@ -131,10 +136,7 @@\n if(rst) begin\n current_state <= IDLE;\n sum_en <= 1'b0;\n- op_done <= 1'b0;\n op_in_progress <= 1'b0;\n- op_error <= 1'b0;\n- data_out <= 'd0;\n cur_ptr <= 'b0;\n found <= 1'b0;\n data_count <= {(LENGTH_WIDTH){1'b0}};\n", "original_path": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/list__list/missing_reset/original_list.sv"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "blocking_nonblocking", "files_modified": ["rtl/i2c_master_axil.v"], "signals_affected": ["data_in_reg"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_axil__i2c_master_axil/blocking_nonblocking", "diff": "--- a/rtl/i2c_master_axil.v\n+++ b/rtl/i2c_master_axil.v\n@@ -663,7 +663,7 @@\n cmd_stop_reg <= cmd_stop_next;\n cmd_valid_reg <= cmd_valid_next;\n \n- data_in_reg <= data_in_next;\n+ data_in_reg = data_in_next;\n data_in_valid_reg <= data_in_valid_next;\n data_in_last_reg <= data_in_last_next;\n \n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_axil__i2c_master_axil/blocking_nonblocking/original_i2c_master_axil.v"} |
| {"repo": "mnasser431998/bfu_dif_fft_rtl", "bug_type": "operator_typo", "files_modified": ["src/bfu_dif_top.v"], "signals_affected": ["scaled_mult_real", "c_minus"], "bug_dir": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__bfu_dif_top/operator_typo", "diff": "--- a/src/bfu_dif_top.v\n+++ b/src/bfu_dif_top.v\n@@ -78,7 +78,7 @@\n \n );\n \n- wire signed [32:0] scaled_mult_real = (mult_result_real>>Q_POINT);\n+ wire signed [32:0] scaled_mult_real = (mult_result_real<<Q_POINT);\n wire signed [32:0] scaled_mult_img = (mult_result_img>>Q_POINT);\n assign c_minus = { scaled_mult_img[15:0], scaled_mult_real[15:0]};\n \n", "original_path": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__bfu_dif_top/operator_typo/original_bfu_dif_top.v"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "operator_typo", "files_modified": ["rtl/axis_fifo.v"], "signals_affected": ["wr_ptr_reg"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_wbs_8__axis_fifo/operator_typo", "diff": "--- a/rtl/axis_fifo.v\n+++ b/rtl/axis_fifo.v\n@@ -234,7 +234,7 @@\n bad_frame_reg <= 1'b1;\n end else begin\n // good packet, update write pointer\n- wr_ptr_reg <= wr_ptr_cur_reg + 1;\n+ wr_ptr_reg <= wr_ptr_cur_reg - 1;\n good_frame_reg <= 1'b1;\n end\n end\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_wbs_8__axis_fifo/operator_typo/original_axis_fifo.v"} |
| {"repo": "mnmhdanas/UART-protocol", "bug_type": "wrong_bitwidth", "files_modified": ["rtl/Receiver/counter_rx.v"], "signals_affected": ["count"], "bug_dir": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/receiver__counter_rx/wrong_bitwidth", "diff": "--- a/rtl/Receiver/counter_rx.v\n+++ b/rtl/Receiver/counter_rx.v\n@@ -1,11 +1,11 @@\n \n \t module counter_rx(i_reset,i_clk,i_up,\n \t o_countreached);\n-\t\t\t\t\t\t\n+\t\t\t\t\t\n \t input i_clk,i_reset,i_up;\n output o_countreached;\n \n-\t reg [3:0] count;\n+\t reg [2:0] count;\n \t assign o_countreached = !count[3]&(count[2])&(count[1])&(count[0]); //8 - 1000\n always@(posedge i_clk,posedge i_reset)\n begin\n@@ -14,4 +14,4 @@\n \t\t\t else if(i_up)\n count <= count + 1'b1;\t\t \n \t\t\tend\t\t\t\n-\t endmodule\t\t\t\t\t+\t endmodule\n", "original_path": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/receiver__counter_rx/wrong_bitwidth/original_counter_rx.v"} |
| {"repo": "mnmhdanas/UART-protocol", "bug_type": "wrong_bitwidth", "files_modified": ["rtl/Transmitter/counter_tx.v"], "signals_affected": ["count"], "bug_dir": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/transmitter__counter_tx/wrong_bitwidth", "diff": "--- a/rtl/Transmitter/counter_tx.v\n+++ b/rtl/Transmitter/counter_tx.v\n@@ -4,8 +4,8 @@\n \t\t\t\t\t\n \tinput i_clk,i_reset,i_up;\n output o_countreached;\t\n-\t\t\t\t\t\n- reg [3:0] count;\n+\t\t\t\t\n+ reg [2:0] count;\n \t assign o_countreached = !count[3]&(count[2])&(count[1])&(count[0]); //8 - 1000\n \t always@(posedge i_clk, posedge i_reset) //for counter module ,reset is active high\n \t begin\n@@ -15,4 +15,3 @@\n \t count <= count + 1'b1;\t\t\t\n \t\tend\n endmodule\n- ", "original_path": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/transmitter__counter_tx/wrong_bitwidth/original_counter_tx.v"} |
| {"repo": "mnmhdanas/UART-protocol", "bug_type": "signal_typo", "files_modified": ["rtl/Receiver/receiver.v"], "signals_affected": ["pardataout"], "bug_dir": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/receiver__receiver/signal_typo", "diff": "--- a/rtl/Receiver/receiver.v\n+++ b/rtl/Receiver/receiver.v\n@@ -45,7 +45,7 @@\n \t\t\t\t\t.i_shift(shift),\n \t .o_parallelout(pardataout));\n \t\t\t\t\t\n-\t\t\t\t\t\n+\t\t\t\t\n \tbitchecker_rx BITCHK_r(.i_data(i_datain),\n \t .i_clk(i_clk),\n \t\t\t\t\t\t\t.i_baudclk(baud_clk),\n@@ -58,10 +58,9 @@\n \t\t\t\t\t\t .i_up(startcount),\n \t .o_countreached(countreached));\t\n \t\t\t\t\t\t \n- paritychecker PARCHK_r( .i_datain(pardataout),\n+ paritychecker PARCHK_r( .i_datain(pardatout),\n \t .i_zerodetected(zerodetected),\n \t\t\t\t\t\t\t.i_onedetected(onedetected),\n .o_parityerror(parityerror) );\n \t\t\t\t\t\t\t\n \tendmodule\n-\t\n", "original_path": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/receiver__receiver/signal_typo/original_receiver.v"} |
| {"repo": "mnasser431998/bfu_dif_fft_rtl", "bug_type": "inverted_condition", "files_modified": ["src/sin_lut.v"], "signals_affected": ["quad"], "bug_dir": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__sin_lut/inverted_condition", "diff": "--- a/src/sin_lut.v\n+++ b/src/sin_lut.v\n@@ -33,8 +33,8 @@\n \t\t\tdata = {{ROM_WIDTH - 1 {1'b0}}, 1'b1, {ROM_WIDTH {1'b0}}};\n \t\telse if (id == (3 * ROM_DEPTH))\n \t\t\tdata = {{ROM_WIDTH {1'b1}}, {ROM_WIDTH {1'b0}}};\n-\t\telse if (quad[1] == 0)\n+\t\telse if (quad[1] != 0)\n \t\t\tdata = {{ROM_WIDTH {1'b0}}, tab_data};\n \t\telse\n \t\t\tdata = {2 * ROM_WIDTH {1'b0}} - {{ROM_WIDTH {1'b0}}, tab_data};\n-endmodule+endmodule\n", "original_path": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__sin_lut/inverted_condition/original_sin_lut.v"} |
| {"repo": "mnmhdanas/UART-protocol", "bug_type": "operator_typo", "files_modified": ["rtl/Receiver/receiver.v"], "signals_affected": ["count_clk", "baud_clk"], "bug_dir": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/receiver__receiver/operator_typo", "diff": "--- a/rtl/Receiver/receiver.v\n+++ b/rtl/Receiver/receiver.v\n@@ -21,7 +21,7 @@\n \t if(!i_reset)\n \t\t count_clk <= 1'b0;\n \t\t else \n- count_clk <= count_clk + 1'b1;\t\t \n+ count_clk <= count_clk - 1'b1;\t\t \n \t end\n \t \t\t\n \t// ---------- Module instantiations -------------------------\n@@ -45,7 +45,7 @@\n \t\t\t\t\t.i_shift(shift),\n \t .o_parallelout(pardataout));\n \t\t\t\t\t\n-\t\t\t\t\t\n+\t\t\t\t\n \tbitchecker_rx BITCHK_r(.i_data(i_datain),\n \t .i_clk(i_clk),\n \t\t\t\t\t\t\t.i_baudclk(baud_clk),\n@@ -64,4 +64,3 @@\n .o_parityerror(parityerror) );\n \t\t\t\t\t\t\t\n \tendmodule\n-\t\n", "original_path": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/receiver__receiver/operator_typo/original_receiver.v"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "inverted_condition", "files_modified": ["rtl/i2c_master.v"], "signals_affected": ["mode_stop_reg"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_wbs_8__i2c_master/inverted_condition", "diff": "--- a/rtl/i2c_master.v\n+++ b/rtl/i2c_master.v\n@@ -575,7 +575,7 @@\n m_axis_data_tdata_next = data_next;\n m_axis_data_tvalid_next = 1'b1;\n m_axis_data_tlast_next = 1'b0;\n- if (mode_stop_reg) begin\n+ if (!mode_stop_reg) begin\n // send nack and stop\n m_axis_data_tlast_next = 1'b1;\n phy_write_bit = 1'b1;\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_wbs_8__i2c_master/inverted_condition/original_i2c_master.v"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "missing_reset", "files_modified": ["rtl/i2c_init.v"], "signals_affected": ["m_axis_cmd_valid_reg", "m_axis_data_tvalid_reg"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_init__i2c_init/missing_reset", "diff": "--- a/rtl/i2c_init.v\n+++ b/rtl/i2c_init.v\n@@ -60,79 +60,6 @@\n */\n input wire start\n );\n-\n-/*\n-\n-Generic module for I2C bus initialization. Good for use when multiple devices\n-on an I2C bus must be initialized on system start without intervention of a\n-general-purpose processor.\n-\n-Copy this file and change init_data and INIT_DATA_LEN as needed.\n-\n-This module can be used in two modes: simple device initialization, or multiple\n-device initialization. In multiple device mode, the same initialization sequence\n-can be performed on multiple different device addresses.\n-\n-To use single device mode, only use the start write to address and write data commands.\n-The module will generate the I2C commands in sequential order. Terminate the list\n-with a 0 entry.\n-\n-To use the multiple device mode, use the start data and start address block commands\n-to set up lists of initialization data and device addresses. The module enters\n-multiple device mode upon seeing a start data block command. The module stores the\n-offset of the start of the data block and then skips ahead until it reaches a start\n-address block command. The module will store the offset to the address block and\n-read the first address in the block. Then it will jump back to the data block\n-and execute it, substituting the stored address for each current address write\n-command. Upon reaching the start address block command, the module will read out the\n-next address and start again at the top of the data block. If the module encounters\n-a start data block command while looking for an address, then it will store a new data\n-offset and then look for a start address block command. Terminate the list with a 0\n-entry. Normal address commands will operate normally inside a data block.\n-\n-Commands:\n-\n-00 0000000 : stop\n-00 0000001 : exit multiple device mode\n-00 0000011 : start write to current address\n-00 0001000 : start address block\n-00 0001001 : start data block\n-00 001dddd : delay 2**(16+d) cycles\n-00 1000001 : send I2C stop\n-01 aaaaaaa : start write to address\n-1 dddddddd : write 8-bit data\n-\n-Examples\n-\n-write 0x11223344 to register 0x0004 on device at 0x50\n-\n-01 1010000 start write to 0x50\n-1 00000000 write address 0x0004\n-1 00000100\n-1 00010001 write data 0x11223344\n-1 00100010\n-1 00110011\n-1 01000100\n-0 00000000 stop\n-\n-write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53\n-\n-00 0001001 start data block\n-00 0000011 start write to current address\n-1 00000000 write address 0x0004\n-1 00000100\n-1 00010001 write data 0x11223344\n-1 00100010\n-1 00110011\n-1 01000100\n-00 0001000 start address block\n-01 1010000 address 0x50\n-01 1010001 address 0x51\n-01 1010010 address 0x52\n-01 1010011 address 0x53\n-00 0000000 stop\n-\n-*/\n \n // init_data ROM\n localparam INIT_DATA_LEN = 22;\n@@ -200,6 +127,9 @@\n \n reg busy_reg = 1'b0;\n \n+initial m_axis_cmd_valid_reg = 1'bx; // Force unknown \u2014 makes missing reset observable\n+initial m_axis_data_tvalid_reg = 1'bx; // Force unknown \u2014 makes missing reset observable\n+\n assign m_axis_cmd_address = m_axis_cmd_address_reg;\n assign m_axis_cmd_start = m_axis_cmd_start_reg;\n assign m_axis_cmd_read = 1'b0;\n@@ -486,10 +416,6 @@\n \n delay_counter_reg <= 32'd0;\n \n- m_axis_cmd_valid_reg <= 1'b0;\n-\n- m_axis_data_tvalid_reg <= 1'b0;\n-\n start_flag_reg <= 1'b0;\n \n busy_reg <= 1'b0;\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_init__i2c_init/missing_reset/original_i2c_init.v"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "blocking_nonblocking", "files_modified": ["rtl/i2c_slave.v"], "signals_affected": ["scl_i_filter", "scl_i_reg"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_slave_wbm__i2c_slave/blocking_nonblocking", "diff": "--- a/rtl/i2c_slave.v\n+++ b/rtl/i2c_slave.v\n@@ -455,13 +455,13 @@\n m_axis_data_tvalid_reg <= m_axis_data_tvalid_next;\n m_axis_data_tlast_reg <= m_axis_data_tlast_next;\n \n- scl_i_filter <= (scl_i_filter << 1) | scl_i;\n+ scl_i_filter = (scl_i_filter << 1) | scl_i;\n sda_i_filter <= (sda_i_filter << 1) | sda_i;\n \n if (scl_i_filter == {FILTER_LEN{1'b1}}) begin\n- scl_i_reg <= 1'b1;\n+ scl_i_reg = 1'b1;\n end else if (scl_i_filter == {FILTER_LEN{1'b0}}) begin\n- scl_i_reg <= 1'b0;\n+ scl_i_reg = 1'b0;\n end\n \n if (sda_i_filter == {FILTER_LEN{1'b1}}) begin\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_slave_wbm__i2c_slave/blocking_nonblocking/original_i2c_slave.v"} |
| {"repo": "ttchisholm/10g-low-latency-ethernet", "bug_type": "missing_reset", "files_modified": ["src/hdl/pcs/tx_gearbox.sv"], "signals_affected": ["obuf"], "bug_dir": "../data-pipeline/repos_augmented/ttchisholm_10g-low-latency-ethernet/tx_gearbox__tx_gearbox/missing_reset", "diff": "--- a/src/hdl/pcs/tx_gearbox.sv\n+++ b/src/hdl/pcs/tx_gearbox.sv\n@@ -120,10 +120,10 @@\n \n end endgenerate\n \n+ initial obuf = {BUF_SIZE{1'bx}}; // Force unknown \u2014 makes missing reset observable\n+\n always_ff @(posedge i_clk)\n- if (i_reset) begin\n- obuf <= '0;\n- end else begin\n+ begin\n obuf <= next_obuf;\n end\n \n", "original_path": "../data-pipeline/repos_augmented/ttchisholm_10g-low-latency-ethernet/tx_gearbox__tx_gearbox/missing_reset/original_tx_gearbox.sv"} |
| {"repo": "Weiyet/RTLStructLib", "bug_type": "inverted_condition", "files_modified": ["Singly_Linked_List/src/singly_linked_list.sv"], "signals_affected": ["data_rd_buf", "data_in"], "bug_dir": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/singly_linked_list__singly_linked_list/inverted_condition", "diff": "--- a/Singly_Linked_List/src/singly_linked_list.sv\n+++ b/Singly_Linked_List/src/singly_linked_list.sv\n@@ -237,7 +237,7 @@\n FIND_VALUE: begin\n // if (!valid_rd_buf) begin\n // next_state <= FAULT; \n- if(data_rd_buf == data_in) begin \n+ if(data_rd_buf != data_in) begin \n // update curr pos to invalid\n wr_req <= 1'b1;\n target_idx <= cur_ptr;\n", "original_path": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/singly_linked_list__singly_linked_list/inverted_condition/original_singly_linked_list.sv"} |
| {"repo": "Weiyet/RTLStructLib", "bug_type": "blocking_nonblocking", "files_modified": ["List/src/list.sv"], "signals_affected": ["op_done", "op_error"], "bug_dir": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/list__list/blocking_nonblocking", "diff": "--- a/List/src/list.sv\n+++ b/List/src/list.sv\n@@ -279,8 +279,8 @@\n end else begin // else if(cur_ptr <= (data_count-1)) begin\n if(data_stored[cur_ptr] == data_in) begin\n data_out <= {{DATA_WIDTH{1'b0}},cur_ptr};\n- op_done <= 1'b1;\n- op_error <= 1'b0;\n+ op_done = 1'b1;\n+ op_error = 1'b0;\n found <= 1'b1;\n cur_ptr <= cur_ptr + 'b1;\n last_key_done <= (cur_ptr == (data_count-1));\n", "original_path": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/list__list/blocking_nonblocking/original_list.sv"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "blocking_nonblocking", "files_modified": ["rtl/i2c_slave.v"], "signals_affected": ["last_scl_i_reg", "last_sda_i_reg"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_slave_axil_master__i2c_slave/blocking_nonblocking", "diff": "--- a/rtl/i2c_slave.v\n+++ b/rtl/i2c_slave.v\n@@ -473,8 +473,8 @@\n scl_o_reg <= scl_o_next;\n sda_o_reg <= sda_o_next;\n \n- last_scl_i_reg <= scl_i_reg;\n- last_sda_i_reg <= sda_i_reg;\n+ last_scl_i_reg = scl_i_reg;\n+ last_sda_i_reg = sda_i_reg;\n \n busy_reg <= !(state_reg == STATE_IDLE);\n \n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_slave_axil_master__i2c_slave/blocking_nonblocking/original_i2c_slave.v"} |
| {"repo": "ttchisholm/10g-low-latency-ethernet", "bug_type": "missing_else_latch", "files_modified": ["src/hdl/pcs/tx_gearbox.sv"], "signals_affected": ["next_obuf"], "bug_dir": "../data-pipeline/repos_augmented/ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/missing_else_latch", "diff": "--- a/src/hdl/pcs/tx_gearbox.sv\n+++ b/src/hdl/pcs/tx_gearbox.sv\n@@ -98,8 +98,6 @@\n \n always @(*) begin\n \n- next_obuf[gi] = obuf[gi]; // Source 3\n-\n if (gi < DATA_WIDTH) begin // Source 2\n next_obuf[gi] = shifted_obuf[gi];\n end\n", "original_path": "../data-pipeline/repos_augmented/ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/missing_else_latch/original_tx_gearbox.sv"} |
| {"repo": "Weiyet/RTLStructLib", "bug_type": "operator_typo", "files_modified": ["FIFO/src/fifo.sv"], "signals_affected": ["rd_gray_pointer", "wr_gray_pointer", "fifo_empty", "fifo_full", "rdptr_eq_next_wrptr"], "bug_dir": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/fifo__fifo/operator_typo", "diff": "--- a/FIFO/src/fifo.sv\n+++ b/FIFO/src/fifo.sv\n@@ -154,7 +154,7 @@\n \n function [CNTR_WIDTH-1:0] bin_to_gray;\n input [CNTR_WIDTH-1:0] bin;\n- bin_to_gray = bin[CNTR_WIDTH-1:0] ^ (bin[CNTR_WIDTH-1:0] >> 1); \n+ bin_to_gray = bin[CNTR_WIDTH-1:0] ^ (bin[CNTR_WIDTH-1:0] << 1); \n endfunction\n \n endmodule\n", "original_path": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/fifo__fifo/operator_typo/original_fifo.sv"} |
| {"repo": "dpretet/async_fifo", "bug_type": "blocking_nonblocking", "files_modified": ["rtl/wptr_full.v"], "signals_affected": ["awfull"], "bug_dir": "../data-pipeline/repos_augmented/dpretet_async_fifo/async_fifo__wptr_full/blocking_nonblocking", "diff": "--- a/rtl/wptr_full.v\n+++ b/rtl/wptr_full.v\n@@ -55,7 +55,7 @@\n awfull <= 1'b0;\n wfull <= 1'b0;\n end else begin\n- awfull <= awfull_val;\n+ awfull = awfull_val;\n wfull <= wfull_val;\n end\n end\n", "original_path": "../data-pipeline/repos_augmented/dpretet_async_fifo/async_fifo__wptr_full/blocking_nonblocking/original_wptr_full.v"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "blocking_nonblocking", "files_modified": ["rtl/i2c_master.v"], "signals_affected": ["last_scl_i_reg"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master__i2c_master/blocking_nonblocking", "diff": "--- a/rtl/i2c_master.v\n+++ b/rtl/i2c_master.v\n@@ -860,7 +860,7 @@\n scl_o_reg <= scl_o_next;\n sda_o_reg <= sda_o_next;\n \n- last_scl_i_reg <= scl_i_reg;\n+ last_scl_i_reg = scl_i_reg;\n last_sda_i_reg <= sda_i_reg;\n \n busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE);\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master__i2c_master/blocking_nonblocking/original_i2c_master.v"} |
| {"repo": "lzzsG/v-project-gen", "bug_type": "wrong_bitwidth", "files_modified": ["src_rtl/alu.v"], "signals_affected": ["alu_out"], "bug_dir": "../data-pipeline/repos_augmented/lzzsG_v-project-gen/top__alu/wrong_bitwidth", "diff": "--- a/src_rtl/alu.v\n+++ b/src_rtl/alu.v\n@@ -4,13 +4,16 @@\n input [1:0] opcode,\n output reg [3:0] result\n );\n+ reg [2:0] alu_out;\n+\n always @(*) begin\n case (opcode)\n- 2'b00: result = a + b; // \u52a0\u6cd5\n- 2'b01: result = a - b; // \u51cf\u6cd5\n- 2'b10: result = a & b; // \u6309\u4f4d\u4e0e\n- 2'b11: result = a | b; // \u6309\u4f4d\u6216\n- default: result = 4'b0000;\n+ 2'b00: alu_out = a + b; // \u52a0\u6cd5\n+ 2'b01: alu_out = a - b; // \u51cf\u6cd5\n+ 2'b10: alu_out = a & b; // \u6309\u4f4d\u4e0e\n+ 2'b11: alu_out = a | b; // \u6309\u4f4d\u6216\n+ default: alu_out = 4'b0000;\n endcase\n+ result = alu_out;\n end\n endmodule\n", "original_path": "../data-pipeline/repos_augmented/lzzsG_v-project-gen/top__alu/wrong_bitwidth/original_alu.v"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "operator_typo", "files_modified": ["rtl/i2c_master.v"], "signals_affected": ["delay_next"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master__i2c_master/operator_typo", "diff": "--- a/rtl/i2c_master.v\n+++ b/rtl/i2c_master.v\n@@ -723,7 +723,7 @@\n \n scl_o_next = 1'b1;\n delay_scl_next = 1'b1;\n- delay_next = prescale << 1;\n+ delay_next = prescale >> 1;\n phy_state_next = PHY_STATE_WRITE_BIT_2;\n end\n PHY_STATE_WRITE_BIT_2: begin\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master__i2c_master/operator_typo/original_i2c_master.v"} |
| {"repo": "ttchisholm/10g-low-latency-ethernet", "bug_type": "operator_typo", "files_modified": ["src/hdl/pcs/rx_gearbox.sv"], "signals_affected": ["next_obuf", "obuf", "o_data", "odata_int"], "bug_dir": "../data-pipeline/repos_augmented/ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/operator_typo", "diff": "--- a/src/hdl/pcs/rx_gearbox.sv\n+++ b/src/hdl/pcs/rx_gearbox.sv\n@@ -111,7 +111,7 @@\n if (frame_word) begin\n if (gearbox_seq != 0 && gi >= current_data_idx) begin\n next_obuf[gi] = i_data[gi - current_data_idx];\n- end else if (gi < DATA_WIDTH - gearbox_seq) begin\n+ end else if (gi < DATA_WIDTH + gearbox_seq) begin\n next_obuf[gi] = i_data[gi + gearbox_seq];\n end\n \n", "original_path": "../data-pipeline/repos_augmented/ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/operator_typo/original_rx_gearbox.sv"} |
| {"repo": "Weiyet/RTLStructLib", "bug_type": "missing_else_latch", "files_modified": ["Doubly_Linked_List/src/doubly_linked_list.sv"], "signals_affected": ["rd_req", "target_idx", "next_state"], "bug_dir": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/doubly_linked_list__doubly_linked_list/missing_else_latch", "diff": "--- a/Doubly_Linked_List/src/doubly_linked_list.sv\n+++ b/Doubly_Linked_List/src/doubly_linked_list.sv\n@@ -287,11 +287,10 @@\n end \n end else if ((ascending & index >= (length - 1)) | (!ascending & index == 0)) begin\n next_state <= FAULT; \n- end else begin\n- rd_req <= 1'b1;\n- target_idx <= ascending ? next_addr_rd_buf : pre_addr_rd_buf;\n- next_state <= FIND_INDEX; \n end\n+ // else branch removed \u2014 when traversal should continue to next node,\n+ // rd_req and target_idx retain previous values instead of being\n+ // updated (latch behavior), causing FIND_INDEX traversal to stall\n end\n FIND_VALUE: begin \n if(data_rd_buf == data_in) begin \n", "original_path": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/doubly_linked_list__doubly_linked_list/missing_else_latch/original_doubly_linked_list.sv"} |
| {"repo": "alexforencich/verilog-i2c", "bug_type": "wrong_bitwidth", "files_modified": ["rtl/i2c_master_axil.v"], "signals_affected": ["prescale_reg"], "bug_dir": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_axil__i2c_master_axil/wrong_bitwidth", "diff": "--- a/rtl/i2c_master_axil.v\n+++ b/rtl/i2c_master_axil.v\n@@ -321,7 +321,7 @@\n reg data_out_ready_reg = 1'b0, data_out_ready_next;\n wire data_out_last;\n \n-reg [15:0] prescale_reg = DEFAULT_PRESCALE, prescale_next;\n+reg [13:0] prescale_reg = DEFAULT_PRESCALE, prescale_next; // Was [15:0] \u2014 upper 2 bits now always 0\n \n reg missed_ack_reg = 1'b0, missed_ack_next;\n \n@@ -587,7 +587,7 @@\n prescale_next[7:0] = s_axil_wdata[7:0];\n end\n if (!FIXED_PRESCALE && s_axil_wstrb[1]) begin\n- prescale_next[15:8] = s_axil_wdata[15:8];\n+ prescale_next[13:8] = s_axil_wdata[13:8];\n end\n end\n endcase\n", "original_path": "../data-pipeline/repos_augmented/alexforencich_verilog-i2c/i2c_master_axil__i2c_master_axil/wrong_bitwidth/original_i2c_master_axil.v"} |
| {"repo": "Weiyet/RTLStructLib", "bug_type": "missing_reset", "files_modified": ["List/src/adder.sv"], "signals_affected": ["sum_result"], "bug_dir": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/list__adder/missing_reset", "diff": "--- a/List/src/adder.sv\n+++ b/List/src/adder.sv\n@@ -36,6 +36,8 @@\n reg [DATA_WIDTH-1:0] output_stage [NO_OF_STAGE-1:0][TOTAL_INPUT_INT-1:0];\n integer i,j;\n \n+ initial sum_result = 'hx; // Force unknown \u2014 makes missing reset observable\n+\n // icarus does not support stream unpacking, so we need to do it mannually\n // always @ (*) begin\n // data_in_unpacked = { >> DATA_WIDTH {data_in}};\n@@ -62,7 +64,6 @@\n end else if(SUM_METHOD == 1) begin //: sequential sum (\n always @(posedge clk, posedge rst) begin\n if(rst) begin\n- sum_result <= 'd0;\n cur_ptr <= 'b0;\n sum_done <= 1'b0;\n sum_in_progress <= 1'b0;\n@@ -112,7 +113,6 @@\n always @ (posedge clk, posedge rst) begin\n if(rst) begin\n stg_ptr <= 'b0;\n- sum_result <= 'd0;\n sum_done <= 1'b0;\n sum_in_progress <= 1'b0;\n end else if(!sum_en) begin\n@@ -131,4 +131,4 @@\n end\n endgenerate\n \n-endmodule+endmodule\n", "original_path": "../data-pipeline/repos_augmented/Weiyet_RTLStructLib/list__adder/missing_reset/original_adder.sv"} |
| {"repo": "mnasser431998/bfu_dif_fft_rtl", "bug_type": "inverted_condition", "files_modified": ["src/cos_lut.v"], "signals_affected": ["quad"], "bug_dir": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__cos_lut/inverted_condition", "diff": "--- a/src/cos_lut.v\n+++ b/src/cos_lut.v\n@@ -37,8 +37,8 @@\n \t\t\tdata = {2 * ROM_WIDTH {1'b0}};\n \t\telse if (id == (3 * ROM_DEPTH))\n \t\t\tdata = {2 * ROM_WIDTH {1'b0}};\n-\t\telse if ((quad == 'd3) || (quad == 'd0))\n+\t\telse if (!((quad == 'd3) || (quad == 'd0)))\n \t\t\tdata = {{ROM_WIDTH {1'b0}}, tab_data};\n \t\telse\n \t\t\tdata = {2 * ROM_WIDTH {1'b0}} - {{ROM_WIDTH {1'b0}}, tab_data};\n-endmodule+endmodule\n", "original_path": "../data-pipeline/repos_augmented/mnasser431998_bfu_dif_fft_rtl/bfu_dif_top__cos_lut/inverted_condition/original_cos_lut.v"} |
| {"repo": "mnmhdanas/UART-protocol", "bug_type": "unconnected_port", "files_modified": ["rtl/Receiver/receiver.v"], "signals_affected": ["pardataout"], "bug_dir": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/receiver__receiver/unconnected_port", "diff": "--- a/rtl/Receiver/receiver.v\n+++ b/rtl/Receiver/receiver.v\n@@ -43,7 +43,7 @@\n \t .i_zerodetected(zerodetected),\n \t\t\t\t\t.i_baudclk(baud_clk),\n \t\t\t\t\t.i_shift(shift),\n-\t .o_parallelout(pardataout));\n+\t .o_parallelout()); // Disconnected \u2014 pardataout is now floating\n \t\t\t\t\t\n \t\t\t\t\t\n \tbitchecker_rx BITCHK_r(.i_data(i_datain),\n@@ -64,4 +64,3 @@\n .o_parityerror(parityerror) );\n \t\t\t\t\t\t\t\n \tendmodule\n-\t\n", "original_path": "../data-pipeline/repos_augmented/mnmhdanas_UART-protocol/receiver__receiver/unconnected_port/original_receiver.v"} |
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