hexsha stringlengths 40 40 | size int64 5 1.05M | ext stringclasses 588 values | lang stringclasses 305 values | max_stars_repo_path stringlengths 3 363 | max_stars_repo_name stringlengths 5 118 | max_stars_repo_head_hexsha stringlengths 40 40 | max_stars_repo_licenses listlengths 1 10 | max_stars_count float64 1 191k ⌀ | max_stars_repo_stars_event_min_datetime stringdate 2015-01-01 00:00:35 2022-03-31 23:43:49 ⌀ | max_stars_repo_stars_event_max_datetime stringdate 2015-01-01 12:37:38 2022-03-31 23:59:52 ⌀ | max_issues_repo_path stringlengths 3 363 | max_issues_repo_name stringlengths 5 118 | max_issues_repo_head_hexsha stringlengths 40 40 | max_issues_repo_licenses listlengths 1 10 | max_issues_count float64 1 134k ⌀ | max_issues_repo_issues_event_min_datetime stringlengths 24 24 ⌀ | max_issues_repo_issues_event_max_datetime stringlengths 24 24 ⌀ | max_forks_repo_path stringlengths 3 363 | max_forks_repo_name stringlengths 5 135 | max_forks_repo_head_hexsha stringlengths 40 40 | max_forks_repo_licenses listlengths 1 10 | max_forks_count float64 1 105k ⌀ | max_forks_repo_forks_event_min_datetime stringdate 2015-01-01 00:01:02 2022-03-31 23:27:27 ⌀ | max_forks_repo_forks_event_max_datetime stringdate 2015-01-03 08:55:07 2022-03-31 23:59:24 ⌀ | content stringlengths 5 1.05M | avg_line_length float64 1.13 1.04M | max_line_length int64 1 1.05M | alphanum_fraction float64 0 1 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
e86196f33c9a2dff3d1e20aea75193cdf96cd239 | 41,816 | asm | Assembly | rm.asm | bhavesh01shukla/Modified-XV-6 | 07949fd2275684cc57d29865e002099dd24f2dcc | [
"MIT-0"
] | null | null | null | rm.asm | bhavesh01shukla/Modified-XV-6 | 07949fd2275684cc57d29865e002099dd24f2dcc | [
"MIT-0"
] | null | null | null | rm.asm | bhavesh01shukla/Modified-XV-6 | 07949fd2275684cc57d29865e002099dd24f2dcc | [
"MIT-0"
] | null | null | null |
_rm: file format elf32-i386
Disassembly of section .text:
00000000 <main>:
#include "stat.h"
#include "user.h"
int
main(int argc, char *argv[])
{
0: 8d 4c 24 04 lea 0x4(%esp),%ecx
4: 83 e4 f0 and $0xfffffff0,%esp
7: ff 71 fc pushl -0x4(%ecx)
a: 55 push %ebp
b: 89 e5 mov %esp,%ebp
d: 57 push %edi
e: bf 01 00 00 00 mov $0x1,%edi
13: 56 push %esi
14: 53 push %ebx
15: 51 push %ecx
16: 83 ec 08 sub $0x8,%esp
19: 8b 59 04 mov 0x4(%ecx),%ebx
1c: 8b 31 mov (%ecx),%esi
1e: 83 c3 04 add $0x4,%ebx
int i;
if(argc < 2){
21: 83 fe 01 cmp $0x1,%esi
24: 7e 3e jle 64 <main+0x64>
26: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
2d: 8d 76 00 lea 0x0(%esi),%esi
printf(2, "Usage: rm files...\n");
exit();
}
for(i = 1; i < argc; i++){
if(unlink(argv[i]) < 0){
30: 83 ec 0c sub $0xc,%esp
33: ff 33 pushl (%ebx)
35: e8 e7 02 00 00 call 321 <unlink>
3a: 83 c4 10 add $0x10,%esp
3d: 85 c0 test %eax,%eax
3f: 78 0f js 50 <main+0x50>
for(i = 1; i < argc; i++){
41: 83 c7 01 add $0x1,%edi
44: 83 c3 04 add $0x4,%ebx
47: 39 fe cmp %edi,%esi
49: 75 e5 jne 30 <main+0x30>
printf(2, "rm: %s failed to delete\n", argv[i]);
break;
}
}
exit();
4b: e8 81 02 00 00 call 2d1 <exit>
printf(2, "rm: %s failed to delete\n", argv[i]);
50: 50 push %eax
51: ff 33 pushl (%ebx)
53: 68 dc 07 00 00 push $0x7dc
58: 6a 02 push $0x2
5a: e8 01 04 00 00 call 460 <printf>
break;
5f: 83 c4 10 add $0x10,%esp
62: eb e7 jmp 4b <main+0x4b>
printf(2, "Usage: rm files...\n");
64: 52 push %edx
65: 52 push %edx
66: 68 c8 07 00 00 push $0x7c8
6b: 6a 02 push $0x2
6d: e8 ee 03 00 00 call 460 <printf>
exit();
72: e8 5a 02 00 00 call 2d1 <exit>
77: 66 90 xchg %ax,%ax
79: 66 90 xchg %ax,%ax
7b: 66 90 xchg %ax,%ax
7d: 66 90 xchg %ax,%ax
7f: 90 nop
00000080 <strcpy>:
#include "user.h"
#include "x86.h"
char*
strcpy(char *s, const char *t)
{
80: 55 push %ebp
char *os;
os = s;
while((*s++ = *t++) != 0)
81: 31 d2 xor %edx,%edx
{
83: 89 e5 mov %esp,%ebp
85: 53 push %ebx
86: 8b 45 08 mov 0x8(%ebp),%eax
89: 8b 5d 0c mov 0xc(%ebp),%ebx
8c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
while((*s++ = *t++) != 0)
90: 0f b6 0c 13 movzbl (%ebx,%edx,1),%ecx
94: 88 0c 10 mov %cl,(%eax,%edx,1)
97: 83 c2 01 add $0x1,%edx
9a: 84 c9 test %cl,%cl
9c: 75 f2 jne 90 <strcpy+0x10>
;
return os;
}
9e: 5b pop %ebx
9f: 5d pop %ebp
a0: c3 ret
a1: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
a8: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
af: 90 nop
000000b0 <strcmp>:
int
strcmp(const char *p, const char *q)
{
b0: 55 push %ebp
b1: 89 e5 mov %esp,%ebp
b3: 56 push %esi
b4: 53 push %ebx
b5: 8b 5d 08 mov 0x8(%ebp),%ebx
b8: 8b 75 0c mov 0xc(%ebp),%esi
while(*p && *p == *q)
bb: 0f b6 13 movzbl (%ebx),%edx
be: 0f b6 0e movzbl (%esi),%ecx
c1: 84 d2 test %dl,%dl
c3: 74 1e je e3 <strcmp+0x33>
c5: b8 01 00 00 00 mov $0x1,%eax
ca: 38 ca cmp %cl,%dl
cc: 74 09 je d7 <strcmp+0x27>
ce: eb 20 jmp f0 <strcmp+0x40>
d0: 83 c0 01 add $0x1,%eax
d3: 38 ca cmp %cl,%dl
d5: 75 19 jne f0 <strcmp+0x40>
d7: 0f b6 14 03 movzbl (%ebx,%eax,1),%edx
db: 0f b6 0c 06 movzbl (%esi,%eax,1),%ecx
df: 84 d2 test %dl,%dl
e1: 75 ed jne d0 <strcmp+0x20>
e3: 31 c0 xor %eax,%eax
p++, q++;
return (uchar)*p - (uchar)*q;
}
e5: 5b pop %ebx
e6: 5e pop %esi
return (uchar)*p - (uchar)*q;
e7: 29 c8 sub %ecx,%eax
}
e9: 5d pop %ebp
ea: c3 ret
eb: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
ef: 90 nop
f0: 0f b6 c2 movzbl %dl,%eax
f3: 5b pop %ebx
f4: 5e pop %esi
return (uchar)*p - (uchar)*q;
f5: 29 c8 sub %ecx,%eax
}
f7: 5d pop %ebp
f8: c3 ret
f9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
00000100 <strlen>:
uint
strlen(const char *s)
{
100: 55 push %ebp
101: 89 e5 mov %esp,%ebp
103: 8b 4d 08 mov 0x8(%ebp),%ecx
int n;
for(n = 0; s[n]; n++)
106: 80 39 00 cmpb $0x0,(%ecx)
109: 74 15 je 120 <strlen+0x20>
10b: 31 d2 xor %edx,%edx
10d: 8d 76 00 lea 0x0(%esi),%esi
110: 83 c2 01 add $0x1,%edx
113: 80 3c 11 00 cmpb $0x0,(%ecx,%edx,1)
117: 89 d0 mov %edx,%eax
119: 75 f5 jne 110 <strlen+0x10>
;
return n;
}
11b: 5d pop %ebp
11c: c3 ret
11d: 8d 76 00 lea 0x0(%esi),%esi
for(n = 0; s[n]; n++)
120: 31 c0 xor %eax,%eax
}
122: 5d pop %ebp
123: c3 ret
124: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
12b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
12f: 90 nop
00000130 <memset>:
void*
memset(void *dst, int c, uint n)
{
130: 55 push %ebp
131: 89 e5 mov %esp,%ebp
133: 57 push %edi
134: 8b 55 08 mov 0x8(%ebp),%edx
}
static inline void
stosb(void *addr, int data, int cnt)
{
asm volatile("cld; rep stosb" :
137: 8b 4d 10 mov 0x10(%ebp),%ecx
13a: 8b 45 0c mov 0xc(%ebp),%eax
13d: 89 d7 mov %edx,%edi
13f: fc cld
140: f3 aa rep stos %al,%es:(%edi)
stosb(dst, c, n);
return dst;
}
142: 89 d0 mov %edx,%eax
144: 5f pop %edi
145: 5d pop %ebp
146: c3 ret
147: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
14e: 66 90 xchg %ax,%ax
00000150 <strchr>:
char*
strchr(const char *s, char c)
{
150: 55 push %ebp
151: 89 e5 mov %esp,%ebp
153: 53 push %ebx
154: 8b 45 08 mov 0x8(%ebp),%eax
157: 8b 55 0c mov 0xc(%ebp),%edx
for(; *s; s++)
15a: 0f b6 18 movzbl (%eax),%ebx
15d: 84 db test %bl,%bl
15f: 74 1d je 17e <strchr+0x2e>
161: 89 d1 mov %edx,%ecx
if(*s == c)
163: 38 d3 cmp %dl,%bl
165: 75 0d jne 174 <strchr+0x24>
167: eb 17 jmp 180 <strchr+0x30>
169: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
170: 38 ca cmp %cl,%dl
172: 74 0c je 180 <strchr+0x30>
for(; *s; s++)
174: 83 c0 01 add $0x1,%eax
177: 0f b6 10 movzbl (%eax),%edx
17a: 84 d2 test %dl,%dl
17c: 75 f2 jne 170 <strchr+0x20>
return (char*)s;
return 0;
17e: 31 c0 xor %eax,%eax
}
180: 5b pop %ebx
181: 5d pop %ebp
182: c3 ret
183: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
18a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
00000190 <gets>:
char*
gets(char *buf, int max)
{
190: 55 push %ebp
191: 89 e5 mov %esp,%ebp
193: 57 push %edi
194: 56 push %esi
int i, cc;
char c;
for(i=0; i+1 < max; ){
195: 31 f6 xor %esi,%esi
{
197: 53 push %ebx
198: 89 f3 mov %esi,%ebx
19a: 83 ec 1c sub $0x1c,%esp
19d: 8b 7d 08 mov 0x8(%ebp),%edi
for(i=0; i+1 < max; ){
1a0: eb 2f jmp 1d1 <gets+0x41>
1a2: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
cc = read(0, &c, 1);
1a8: 83 ec 04 sub $0x4,%esp
1ab: 8d 45 e7 lea -0x19(%ebp),%eax
1ae: 6a 01 push $0x1
1b0: 50 push %eax
1b1: 6a 00 push $0x0
1b3: e8 31 01 00 00 call 2e9 <read>
if(cc < 1)
1b8: 83 c4 10 add $0x10,%esp
1bb: 85 c0 test %eax,%eax
1bd: 7e 1c jle 1db <gets+0x4b>
break;
buf[i++] = c;
1bf: 0f b6 45 e7 movzbl -0x19(%ebp),%eax
1c3: 83 c7 01 add $0x1,%edi
1c6: 88 47 ff mov %al,-0x1(%edi)
if(c == '\n' || c == '\r')
1c9: 3c 0a cmp $0xa,%al
1cb: 74 23 je 1f0 <gets+0x60>
1cd: 3c 0d cmp $0xd,%al
1cf: 74 1f je 1f0 <gets+0x60>
for(i=0; i+1 < max; ){
1d1: 83 c3 01 add $0x1,%ebx
1d4: 89 fe mov %edi,%esi
1d6: 3b 5d 0c cmp 0xc(%ebp),%ebx
1d9: 7c cd jl 1a8 <gets+0x18>
1db: 89 f3 mov %esi,%ebx
break;
}
buf[i] = '\0';
return buf;
}
1dd: 8b 45 08 mov 0x8(%ebp),%eax
buf[i] = '\0';
1e0: c6 03 00 movb $0x0,(%ebx)
}
1e3: 8d 65 f4 lea -0xc(%ebp),%esp
1e6: 5b pop %ebx
1e7: 5e pop %esi
1e8: 5f pop %edi
1e9: 5d pop %ebp
1ea: c3 ret
1eb: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
1ef: 90 nop
1f0: 8b 75 08 mov 0x8(%ebp),%esi
1f3: 8b 45 08 mov 0x8(%ebp),%eax
1f6: 01 de add %ebx,%esi
1f8: 89 f3 mov %esi,%ebx
buf[i] = '\0';
1fa: c6 03 00 movb $0x0,(%ebx)
}
1fd: 8d 65 f4 lea -0xc(%ebp),%esp
200: 5b pop %ebx
201: 5e pop %esi
202: 5f pop %edi
203: 5d pop %ebp
204: c3 ret
205: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
20c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
00000210 <stat>:
int
stat(const char *n, struct stat *st)
{
210: 55 push %ebp
211: 89 e5 mov %esp,%ebp
213: 56 push %esi
214: 53 push %ebx
int fd;
int r;
fd = open(n, O_RDONLY);
215: 83 ec 08 sub $0x8,%esp
218: 6a 00 push $0x0
21a: ff 75 08 pushl 0x8(%ebp)
21d: e8 ef 00 00 00 call 311 <open>
if(fd < 0)
222: 83 c4 10 add $0x10,%esp
225: 85 c0 test %eax,%eax
227: 78 27 js 250 <stat+0x40>
return -1;
r = fstat(fd, st);
229: 83 ec 08 sub $0x8,%esp
22c: ff 75 0c pushl 0xc(%ebp)
22f: 89 c3 mov %eax,%ebx
231: 50 push %eax
232: e8 f2 00 00 00 call 329 <fstat>
close(fd);
237: 89 1c 24 mov %ebx,(%esp)
r = fstat(fd, st);
23a: 89 c6 mov %eax,%esi
close(fd);
23c: e8 b8 00 00 00 call 2f9 <close>
return r;
241: 83 c4 10 add $0x10,%esp
}
244: 8d 65 f8 lea -0x8(%ebp),%esp
247: 89 f0 mov %esi,%eax
249: 5b pop %ebx
24a: 5e pop %esi
24b: 5d pop %ebp
24c: c3 ret
24d: 8d 76 00 lea 0x0(%esi),%esi
return -1;
250: be ff ff ff ff mov $0xffffffff,%esi
255: eb ed jmp 244 <stat+0x34>
257: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
25e: 66 90 xchg %ax,%ax
00000260 <atoi>:
int
atoi(const char *s)
{
260: 55 push %ebp
261: 89 e5 mov %esp,%ebp
263: 53 push %ebx
264: 8b 4d 08 mov 0x8(%ebp),%ecx
int n;
n = 0;
while('0' <= *s && *s <= '9')
267: 0f be 11 movsbl (%ecx),%edx
26a: 8d 42 d0 lea -0x30(%edx),%eax
26d: 3c 09 cmp $0x9,%al
n = 0;
26f: b8 00 00 00 00 mov $0x0,%eax
while('0' <= *s && *s <= '9')
274: 77 1f ja 295 <atoi+0x35>
276: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
27d: 8d 76 00 lea 0x0(%esi),%esi
n = n*10 + *s++ - '0';
280: 83 c1 01 add $0x1,%ecx
283: 8d 04 80 lea (%eax,%eax,4),%eax
286: 8d 44 42 d0 lea -0x30(%edx,%eax,2),%eax
while('0' <= *s && *s <= '9')
28a: 0f be 11 movsbl (%ecx),%edx
28d: 8d 5a d0 lea -0x30(%edx),%ebx
290: 80 fb 09 cmp $0x9,%bl
293: 76 eb jbe 280 <atoi+0x20>
return n;
}
295: 5b pop %ebx
296: 5d pop %ebp
297: c3 ret
298: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
29f: 90 nop
000002a0 <memmove>:
void*
memmove(void *vdst, const void *vsrc, int n)
{
2a0: 55 push %ebp
2a1: 89 e5 mov %esp,%ebp
2a3: 57 push %edi
2a4: 8b 55 10 mov 0x10(%ebp),%edx
2a7: 8b 45 08 mov 0x8(%ebp),%eax
2aa: 56 push %esi
2ab: 8b 75 0c mov 0xc(%ebp),%esi
char *dst;
const char *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
2ae: 85 d2 test %edx,%edx
2b0: 7e 13 jle 2c5 <memmove+0x25>
2b2: 01 c2 add %eax,%edx
dst = vdst;
2b4: 89 c7 mov %eax,%edi
2b6: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
2bd: 8d 76 00 lea 0x0(%esi),%esi
*dst++ = *src++;
2c0: a4 movsb %ds:(%esi),%es:(%edi)
while(n-- > 0)
2c1: 39 fa cmp %edi,%edx
2c3: 75 fb jne 2c0 <memmove+0x20>
return vdst;
}
2c5: 5e pop %esi
2c6: 5f pop %edi
2c7: 5d pop %ebp
2c8: c3 ret
000002c9 <fork>:
name: \
movl $SYS_ ## name, %eax; \
int $T_SYSCALL; \
ret
SYSCALL(fork)
2c9: b8 01 00 00 00 mov $0x1,%eax
2ce: cd 40 int $0x40
2d0: c3 ret
000002d1 <exit>:
SYSCALL(exit)
2d1: b8 02 00 00 00 mov $0x2,%eax
2d6: cd 40 int $0x40
2d8: c3 ret
000002d9 <wait>:
SYSCALL(wait)
2d9: b8 03 00 00 00 mov $0x3,%eax
2de: cd 40 int $0x40
2e0: c3 ret
000002e1 <pipe>:
SYSCALL(pipe)
2e1: b8 04 00 00 00 mov $0x4,%eax
2e6: cd 40 int $0x40
2e8: c3 ret
000002e9 <read>:
SYSCALL(read)
2e9: b8 05 00 00 00 mov $0x5,%eax
2ee: cd 40 int $0x40
2f0: c3 ret
000002f1 <write>:
SYSCALL(write)
2f1: b8 10 00 00 00 mov $0x10,%eax
2f6: cd 40 int $0x40
2f8: c3 ret
000002f9 <close>:
SYSCALL(close)
2f9: b8 15 00 00 00 mov $0x15,%eax
2fe: cd 40 int $0x40
300: c3 ret
00000301 <kill>:
SYSCALL(kill)
301: b8 06 00 00 00 mov $0x6,%eax
306: cd 40 int $0x40
308: c3 ret
00000309 <exec>:
SYSCALL(exec)
309: b8 07 00 00 00 mov $0x7,%eax
30e: cd 40 int $0x40
310: c3 ret
00000311 <open>:
SYSCALL(open)
311: b8 0f 00 00 00 mov $0xf,%eax
316: cd 40 int $0x40
318: c3 ret
00000319 <mknod>:
SYSCALL(mknod)
319: b8 11 00 00 00 mov $0x11,%eax
31e: cd 40 int $0x40
320: c3 ret
00000321 <unlink>:
SYSCALL(unlink)
321: b8 12 00 00 00 mov $0x12,%eax
326: cd 40 int $0x40
328: c3 ret
00000329 <fstat>:
SYSCALL(fstat)
329: b8 08 00 00 00 mov $0x8,%eax
32e: cd 40 int $0x40
330: c3 ret
00000331 <link>:
SYSCALL(link)
331: b8 13 00 00 00 mov $0x13,%eax
336: cd 40 int $0x40
338: c3 ret
00000339 <mkdir>:
SYSCALL(mkdir)
339: b8 14 00 00 00 mov $0x14,%eax
33e: cd 40 int $0x40
340: c3 ret
00000341 <chdir>:
SYSCALL(chdir)
341: b8 09 00 00 00 mov $0x9,%eax
346: cd 40 int $0x40
348: c3 ret
00000349 <dup>:
SYSCALL(dup)
349: b8 0a 00 00 00 mov $0xa,%eax
34e: cd 40 int $0x40
350: c3 ret
00000351 <getpid>:
SYSCALL(getpid)
351: b8 0b 00 00 00 mov $0xb,%eax
356: cd 40 int $0x40
358: c3 ret
00000359 <sbrk>:
SYSCALL(sbrk)
359: b8 0c 00 00 00 mov $0xc,%eax
35e: cd 40 int $0x40
360: c3 ret
00000361 <sleep>:
SYSCALL(sleep)
361: b8 0d 00 00 00 mov $0xd,%eax
366: cd 40 int $0x40
368: c3 ret
00000369 <uptime>:
SYSCALL(uptime)
369: b8 0e 00 00 00 mov $0xe,%eax
36e: cd 40 int $0x40
370: c3 ret
00000371 <waitx>:
SYSCALL(waitx)
371: b8 16 00 00 00 mov $0x16,%eax
376: cd 40 int $0x40
378: c3 ret
00000379 <cps>:
SYSCALL(cps)
379: b8 17 00 00 00 mov $0x17,%eax
37e: cd 40 int $0x40
380: c3 ret
00000381 <set_priority>:
SYSCALL(set_priority)
381: b8 18 00 00 00 mov $0x18,%eax
386: cd 40 int $0x40
388: c3 ret
00000389 <getpinfo>:
389: b8 19 00 00 00 mov $0x19,%eax
38e: cd 40 int $0x40
390: c3 ret
391: 66 90 xchg %ax,%ax
393: 66 90 xchg %ax,%ax
395: 66 90 xchg %ax,%ax
397: 66 90 xchg %ax,%ax
399: 66 90 xchg %ax,%ax
39b: 66 90 xchg %ax,%ax
39d: 66 90 xchg %ax,%ax
39f: 90 nop
000003a0 <printint>:
write(fd, &c, 1);
}
static void
printint(int fd, int xx, int base, int sgn)
{
3a0: 55 push %ebp
3a1: 89 e5 mov %esp,%ebp
3a3: 57 push %edi
3a4: 56 push %esi
3a5: 53 push %ebx
uint x;
neg = 0;
if(sgn && xx < 0){
neg = 1;
x = -xx;
3a6: 89 d3 mov %edx,%ebx
{
3a8: 83 ec 3c sub $0x3c,%esp
3ab: 89 45 bc mov %eax,-0x44(%ebp)
if(sgn && xx < 0){
3ae: 85 d2 test %edx,%edx
3b0: 0f 89 92 00 00 00 jns 448 <printint+0xa8>
3b6: f6 45 08 01 testb $0x1,0x8(%ebp)
3ba: 0f 84 88 00 00 00 je 448 <printint+0xa8>
neg = 1;
3c0: c7 45 c0 01 00 00 00 movl $0x1,-0x40(%ebp)
x = -xx;
3c7: f7 db neg %ebx
} else {
x = xx;
}
i = 0;
3c9: c7 45 c4 00 00 00 00 movl $0x0,-0x3c(%ebp)
3d0: 8d 75 d7 lea -0x29(%ebp),%esi
3d3: eb 08 jmp 3dd <printint+0x3d>
3d5: 8d 76 00 lea 0x0(%esi),%esi
do{
buf[i++] = digits[x % base];
3d8: 89 7d c4 mov %edi,-0x3c(%ebp)
}while((x /= base) != 0);
3db: 89 c3 mov %eax,%ebx
buf[i++] = digits[x % base];
3dd: 89 d8 mov %ebx,%eax
3df: 31 d2 xor %edx,%edx
3e1: 8b 7d c4 mov -0x3c(%ebp),%edi
3e4: f7 f1 div %ecx
3e6: 83 c7 01 add $0x1,%edi
3e9: 0f b6 92 fc 07 00 00 movzbl 0x7fc(%edx),%edx
3f0: 88 14 3e mov %dl,(%esi,%edi,1)
}while((x /= base) != 0);
3f3: 39 d9 cmp %ebx,%ecx
3f5: 76 e1 jbe 3d8 <printint+0x38>
if(neg)
3f7: 8b 45 c0 mov -0x40(%ebp),%eax
3fa: 85 c0 test %eax,%eax
3fc: 74 0d je 40b <printint+0x6b>
buf[i++] = '-';
3fe: c6 44 3d d8 2d movb $0x2d,-0x28(%ebp,%edi,1)
403: ba 2d 00 00 00 mov $0x2d,%edx
buf[i++] = digits[x % base];
408: 89 7d c4 mov %edi,-0x3c(%ebp)
40b: 8b 45 c4 mov -0x3c(%ebp),%eax
40e: 8b 7d bc mov -0x44(%ebp),%edi
411: 8d 5c 05 d7 lea -0x29(%ebp,%eax,1),%ebx
415: eb 0f jmp 426 <printint+0x86>
417: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
41e: 66 90 xchg %ax,%ax
420: 0f b6 13 movzbl (%ebx),%edx
423: 83 eb 01 sub $0x1,%ebx
write(fd, &c, 1);
426: 83 ec 04 sub $0x4,%esp
429: 88 55 d7 mov %dl,-0x29(%ebp)
42c: 6a 01 push $0x1
42e: 56 push %esi
42f: 57 push %edi
430: e8 bc fe ff ff call 2f1 <write>
while(--i >= 0)
435: 83 c4 10 add $0x10,%esp
438: 39 de cmp %ebx,%esi
43a: 75 e4 jne 420 <printint+0x80>
putc(fd, buf[i]);
}
43c: 8d 65 f4 lea -0xc(%ebp),%esp
43f: 5b pop %ebx
440: 5e pop %esi
441: 5f pop %edi
442: 5d pop %ebp
443: c3 ret
444: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
neg = 0;
448: c7 45 c0 00 00 00 00 movl $0x0,-0x40(%ebp)
44f: e9 75 ff ff ff jmp 3c9 <printint+0x29>
454: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
45b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
45f: 90 nop
00000460 <printf>:
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, const char *fmt, ...)
{
460: 55 push %ebp
461: 89 e5 mov %esp,%ebp
463: 57 push %edi
464: 56 push %esi
465: 53 push %ebx
466: 83 ec 2c sub $0x2c,%esp
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
469: 8b 75 0c mov 0xc(%ebp),%esi
46c: 0f b6 1e movzbl (%esi),%ebx
46f: 84 db test %bl,%bl
471: 0f 84 b9 00 00 00 je 530 <printf+0xd0>
ap = (uint*)(void*)&fmt + 1;
477: 8d 45 10 lea 0x10(%ebp),%eax
47a: 83 c6 01 add $0x1,%esi
write(fd, &c, 1);
47d: 8d 7d e7 lea -0x19(%ebp),%edi
state = 0;
480: 31 d2 xor %edx,%edx
ap = (uint*)(void*)&fmt + 1;
482: 89 45 d0 mov %eax,-0x30(%ebp)
485: eb 38 jmp 4bf <printf+0x5f>
487: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
48e: 66 90 xchg %ax,%ax
490: 89 55 d4 mov %edx,-0x2c(%ebp)
c = fmt[i] & 0xff;
if(state == 0){
if(c == '%'){
state = '%';
493: ba 25 00 00 00 mov $0x25,%edx
if(c == '%'){
498: 83 f8 25 cmp $0x25,%eax
49b: 74 17 je 4b4 <printf+0x54>
write(fd, &c, 1);
49d: 83 ec 04 sub $0x4,%esp
4a0: 88 5d e7 mov %bl,-0x19(%ebp)
4a3: 6a 01 push $0x1
4a5: 57 push %edi
4a6: ff 75 08 pushl 0x8(%ebp)
4a9: e8 43 fe ff ff call 2f1 <write>
4ae: 8b 55 d4 mov -0x2c(%ebp),%edx
} else {
putc(fd, c);
4b1: 83 c4 10 add $0x10,%esp
4b4: 83 c6 01 add $0x1,%esi
for(i = 0; fmt[i]; i++){
4b7: 0f b6 5e ff movzbl -0x1(%esi),%ebx
4bb: 84 db test %bl,%bl
4bd: 74 71 je 530 <printf+0xd0>
c = fmt[i] & 0xff;
4bf: 0f be cb movsbl %bl,%ecx
4c2: 0f b6 c3 movzbl %bl,%eax
if(state == 0){
4c5: 85 d2 test %edx,%edx
4c7: 74 c7 je 490 <printf+0x30>
}
} else if(state == '%'){
4c9: 83 fa 25 cmp $0x25,%edx
4cc: 75 e6 jne 4b4 <printf+0x54>
if(c == 'd'){
4ce: 83 f8 64 cmp $0x64,%eax
4d1: 0f 84 99 00 00 00 je 570 <printf+0x110>
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
4d7: 81 e1 f7 00 00 00 and $0xf7,%ecx
4dd: 83 f9 70 cmp $0x70,%ecx
4e0: 74 5e je 540 <printf+0xe0>
printint(fd, *ap, 16, 0);
ap++;
} else if(c == 's'){
4e2: 83 f8 73 cmp $0x73,%eax
4e5: 0f 84 d5 00 00 00 je 5c0 <printf+0x160>
s = "(null)";
while(*s != 0){
putc(fd, *s);
s++;
}
} else if(c == 'c'){
4eb: 83 f8 63 cmp $0x63,%eax
4ee: 0f 84 8c 00 00 00 je 580 <printf+0x120>
putc(fd, *ap);
ap++;
} else if(c == '%'){
4f4: 83 f8 25 cmp $0x25,%eax
4f7: 0f 84 b3 00 00 00 je 5b0 <printf+0x150>
write(fd, &c, 1);
4fd: 83 ec 04 sub $0x4,%esp
500: c6 45 e7 25 movb $0x25,-0x19(%ebp)
504: 6a 01 push $0x1
506: 57 push %edi
507: ff 75 08 pushl 0x8(%ebp)
50a: e8 e2 fd ff ff call 2f1 <write>
putc(fd, c);
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
putc(fd, c);
50f: 88 5d e7 mov %bl,-0x19(%ebp)
write(fd, &c, 1);
512: 83 c4 0c add $0xc,%esp
515: 6a 01 push $0x1
517: 83 c6 01 add $0x1,%esi
51a: 57 push %edi
51b: ff 75 08 pushl 0x8(%ebp)
51e: e8 ce fd ff ff call 2f1 <write>
for(i = 0; fmt[i]; i++){
523: 0f b6 5e ff movzbl -0x1(%esi),%ebx
putc(fd, c);
527: 83 c4 10 add $0x10,%esp
}
state = 0;
52a: 31 d2 xor %edx,%edx
for(i = 0; fmt[i]; i++){
52c: 84 db test %bl,%bl
52e: 75 8f jne 4bf <printf+0x5f>
}
}
}
530: 8d 65 f4 lea -0xc(%ebp),%esp
533: 5b pop %ebx
534: 5e pop %esi
535: 5f pop %edi
536: 5d pop %ebp
537: c3 ret
538: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
53f: 90 nop
printint(fd, *ap, 16, 0);
540: 83 ec 0c sub $0xc,%esp
543: b9 10 00 00 00 mov $0x10,%ecx
548: 6a 00 push $0x0
54a: 8b 5d d0 mov -0x30(%ebp),%ebx
54d: 8b 45 08 mov 0x8(%ebp),%eax
550: 8b 13 mov (%ebx),%edx
552: e8 49 fe ff ff call 3a0 <printint>
ap++;
557: 89 d8 mov %ebx,%eax
559: 83 c4 10 add $0x10,%esp
state = 0;
55c: 31 d2 xor %edx,%edx
ap++;
55e: 83 c0 04 add $0x4,%eax
561: 89 45 d0 mov %eax,-0x30(%ebp)
564: e9 4b ff ff ff jmp 4b4 <printf+0x54>
569: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
printint(fd, *ap, 10, 1);
570: 83 ec 0c sub $0xc,%esp
573: b9 0a 00 00 00 mov $0xa,%ecx
578: 6a 01 push $0x1
57a: eb ce jmp 54a <printf+0xea>
57c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
putc(fd, *ap);
580: 8b 5d d0 mov -0x30(%ebp),%ebx
write(fd, &c, 1);
583: 83 ec 04 sub $0x4,%esp
putc(fd, *ap);
586: 8b 03 mov (%ebx),%eax
write(fd, &c, 1);
588: 6a 01 push $0x1
ap++;
58a: 83 c3 04 add $0x4,%ebx
write(fd, &c, 1);
58d: 57 push %edi
58e: ff 75 08 pushl 0x8(%ebp)
putc(fd, *ap);
591: 88 45 e7 mov %al,-0x19(%ebp)
write(fd, &c, 1);
594: e8 58 fd ff ff call 2f1 <write>
ap++;
599: 89 5d d0 mov %ebx,-0x30(%ebp)
59c: 83 c4 10 add $0x10,%esp
state = 0;
59f: 31 d2 xor %edx,%edx
5a1: e9 0e ff ff ff jmp 4b4 <printf+0x54>
5a6: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
5ad: 8d 76 00 lea 0x0(%esi),%esi
putc(fd, c);
5b0: 88 5d e7 mov %bl,-0x19(%ebp)
write(fd, &c, 1);
5b3: 83 ec 04 sub $0x4,%esp
5b6: e9 5a ff ff ff jmp 515 <printf+0xb5>
5bb: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
5bf: 90 nop
s = (char*)*ap;
5c0: 8b 45 d0 mov -0x30(%ebp),%eax
5c3: 8b 18 mov (%eax),%ebx
ap++;
5c5: 83 c0 04 add $0x4,%eax
5c8: 89 45 d0 mov %eax,-0x30(%ebp)
if(s == 0)
5cb: 85 db test %ebx,%ebx
5cd: 74 17 je 5e6 <printf+0x186>
while(*s != 0){
5cf: 0f b6 03 movzbl (%ebx),%eax
state = 0;
5d2: 31 d2 xor %edx,%edx
while(*s != 0){
5d4: 84 c0 test %al,%al
5d6: 0f 84 d8 fe ff ff je 4b4 <printf+0x54>
5dc: 89 75 d4 mov %esi,-0x2c(%ebp)
5df: 89 de mov %ebx,%esi
5e1: 8b 5d 08 mov 0x8(%ebp),%ebx
5e4: eb 1a jmp 600 <printf+0x1a0>
s = "(null)";
5e6: bb f5 07 00 00 mov $0x7f5,%ebx
while(*s != 0){
5eb: 89 75 d4 mov %esi,-0x2c(%ebp)
5ee: b8 28 00 00 00 mov $0x28,%eax
5f3: 89 de mov %ebx,%esi
5f5: 8b 5d 08 mov 0x8(%ebp),%ebx
5f8: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
5ff: 90 nop
write(fd, &c, 1);
600: 83 ec 04 sub $0x4,%esp
s++;
603: 83 c6 01 add $0x1,%esi
606: 88 45 e7 mov %al,-0x19(%ebp)
write(fd, &c, 1);
609: 6a 01 push $0x1
60b: 57 push %edi
60c: 53 push %ebx
60d: e8 df fc ff ff call 2f1 <write>
while(*s != 0){
612: 0f b6 06 movzbl (%esi),%eax
615: 83 c4 10 add $0x10,%esp
618: 84 c0 test %al,%al
61a: 75 e4 jne 600 <printf+0x1a0>
61c: 8b 75 d4 mov -0x2c(%ebp),%esi
state = 0;
61f: 31 d2 xor %edx,%edx
621: e9 8e fe ff ff jmp 4b4 <printf+0x54>
626: 66 90 xchg %ax,%ax
628: 66 90 xchg %ax,%ax
62a: 66 90 xchg %ax,%ax
62c: 66 90 xchg %ax,%ax
62e: 66 90 xchg %ax,%ax
00000630 <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
630: 55 push %ebp
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
631: a1 b4 0a 00 00 mov 0xab4,%eax
{
636: 89 e5 mov %esp,%ebp
638: 57 push %edi
639: 56 push %esi
63a: 53 push %ebx
63b: 8b 5d 08 mov 0x8(%ebp),%ebx
63e: 8b 10 mov (%eax),%edx
bp = (Header*)ap - 1;
640: 8d 4b f8 lea -0x8(%ebx),%ecx
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
643: 39 c8 cmp %ecx,%eax
645: 73 19 jae 660 <free+0x30>
647: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
64e: 66 90 xchg %ax,%ax
650: 39 d1 cmp %edx,%ecx
652: 72 14 jb 668 <free+0x38>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
654: 39 d0 cmp %edx,%eax
656: 73 10 jae 668 <free+0x38>
{
658: 89 d0 mov %edx,%eax
65a: 8b 10 mov (%eax),%edx
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
65c: 39 c8 cmp %ecx,%eax
65e: 72 f0 jb 650 <free+0x20>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
660: 39 d0 cmp %edx,%eax
662: 72 f4 jb 658 <free+0x28>
664: 39 d1 cmp %edx,%ecx
666: 73 f0 jae 658 <free+0x28>
break;
if(bp + bp->s.size == p->s.ptr){
668: 8b 73 fc mov -0x4(%ebx),%esi
66b: 8d 3c f1 lea (%ecx,%esi,8),%edi
66e: 39 fa cmp %edi,%edx
670: 74 1e je 690 <free+0x60>
bp->s.size += p->s.ptr->s.size;
bp->s.ptr = p->s.ptr->s.ptr;
} else
bp->s.ptr = p->s.ptr;
672: 89 53 f8 mov %edx,-0x8(%ebx)
if(p + p->s.size == bp){
675: 8b 50 04 mov 0x4(%eax),%edx
678: 8d 34 d0 lea (%eax,%edx,8),%esi
67b: 39 f1 cmp %esi,%ecx
67d: 74 28 je 6a7 <free+0x77>
p->s.size += bp->s.size;
p->s.ptr = bp->s.ptr;
} else
p->s.ptr = bp;
67f: 89 08 mov %ecx,(%eax)
freep = p;
}
681: 5b pop %ebx
freep = p;
682: a3 b4 0a 00 00 mov %eax,0xab4
}
687: 5e pop %esi
688: 5f pop %edi
689: 5d pop %ebp
68a: c3 ret
68b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
68f: 90 nop
bp->s.size += p->s.ptr->s.size;
690: 03 72 04 add 0x4(%edx),%esi
693: 89 73 fc mov %esi,-0x4(%ebx)
bp->s.ptr = p->s.ptr->s.ptr;
696: 8b 10 mov (%eax),%edx
698: 8b 12 mov (%edx),%edx
69a: 89 53 f8 mov %edx,-0x8(%ebx)
if(p + p->s.size == bp){
69d: 8b 50 04 mov 0x4(%eax),%edx
6a0: 8d 34 d0 lea (%eax,%edx,8),%esi
6a3: 39 f1 cmp %esi,%ecx
6a5: 75 d8 jne 67f <free+0x4f>
p->s.size += bp->s.size;
6a7: 03 53 fc add -0x4(%ebx),%edx
freep = p;
6aa: a3 b4 0a 00 00 mov %eax,0xab4
p->s.size += bp->s.size;
6af: 89 50 04 mov %edx,0x4(%eax)
p->s.ptr = bp->s.ptr;
6b2: 8b 53 f8 mov -0x8(%ebx),%edx
6b5: 89 10 mov %edx,(%eax)
}
6b7: 5b pop %ebx
6b8: 5e pop %esi
6b9: 5f pop %edi
6ba: 5d pop %ebp
6bb: c3 ret
6bc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
000006c0 <malloc>:
return freep;
}
void*
malloc(uint nbytes)
{
6c0: 55 push %ebp
6c1: 89 e5 mov %esp,%ebp
6c3: 57 push %edi
6c4: 56 push %esi
6c5: 53 push %ebx
6c6: 83 ec 1c sub $0x1c,%esp
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
6c9: 8b 45 08 mov 0x8(%ebp),%eax
if((prevp = freep) == 0){
6cc: 8b 3d b4 0a 00 00 mov 0xab4,%edi
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
6d2: 8d 70 07 lea 0x7(%eax),%esi
6d5: c1 ee 03 shr $0x3,%esi
6d8: 83 c6 01 add $0x1,%esi
if((prevp = freep) == 0){
6db: 85 ff test %edi,%edi
6dd: 0f 84 ad 00 00 00 je 790 <malloc+0xd0>
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
6e3: 8b 17 mov (%edi),%edx
if(p->s.size >= nunits){
6e5: 8b 4a 04 mov 0x4(%edx),%ecx
6e8: 39 f1 cmp %esi,%ecx
6ea: 73 72 jae 75e <malloc+0x9e>
6ec: 81 fe 00 10 00 00 cmp $0x1000,%esi
6f2: bb 00 10 00 00 mov $0x1000,%ebx
6f7: 0f 43 de cmovae %esi,%ebx
p = sbrk(nu * sizeof(Header));
6fa: 8d 04 dd 00 00 00 00 lea 0x0(,%ebx,8),%eax
701: 89 45 e4 mov %eax,-0x1c(%ebp)
704: eb 1b jmp 721 <malloc+0x61>
706: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
70d: 8d 76 00 lea 0x0(%esi),%esi
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
710: 8b 02 mov (%edx),%eax
if(p->s.size >= nunits){
712: 8b 48 04 mov 0x4(%eax),%ecx
715: 39 f1 cmp %esi,%ecx
717: 73 4f jae 768 <malloc+0xa8>
719: 8b 3d b4 0a 00 00 mov 0xab4,%edi
71f: 89 c2 mov %eax,%edx
p->s.size = nunits;
}
freep = prevp;
return (void*)(p + 1);
}
if(p == freep)
721: 39 d7 cmp %edx,%edi
723: 75 eb jne 710 <malloc+0x50>
p = sbrk(nu * sizeof(Header));
725: 83 ec 0c sub $0xc,%esp
728: ff 75 e4 pushl -0x1c(%ebp)
72b: e8 29 fc ff ff call 359 <sbrk>
if(p == (char*)-1)
730: 83 c4 10 add $0x10,%esp
733: 83 f8 ff cmp $0xffffffff,%eax
736: 74 1c je 754 <malloc+0x94>
hp->s.size = nu;
738: 89 58 04 mov %ebx,0x4(%eax)
free((void*)(hp + 1));
73b: 83 ec 0c sub $0xc,%esp
73e: 83 c0 08 add $0x8,%eax
741: 50 push %eax
742: e8 e9 fe ff ff call 630 <free>
return freep;
747: 8b 15 b4 0a 00 00 mov 0xab4,%edx
if((p = morecore(nunits)) == 0)
74d: 83 c4 10 add $0x10,%esp
750: 85 d2 test %edx,%edx
752: 75 bc jne 710 <malloc+0x50>
return 0;
}
}
754: 8d 65 f4 lea -0xc(%ebp),%esp
return 0;
757: 31 c0 xor %eax,%eax
}
759: 5b pop %ebx
75a: 5e pop %esi
75b: 5f pop %edi
75c: 5d pop %ebp
75d: c3 ret
if(p->s.size >= nunits){
75e: 89 d0 mov %edx,%eax
760: 89 fa mov %edi,%edx
762: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
if(p->s.size == nunits)
768: 39 ce cmp %ecx,%esi
76a: 74 54 je 7c0 <malloc+0x100>
p->s.size -= nunits;
76c: 29 f1 sub %esi,%ecx
76e: 89 48 04 mov %ecx,0x4(%eax)
p += p->s.size;
771: 8d 04 c8 lea (%eax,%ecx,8),%eax
p->s.size = nunits;
774: 89 70 04 mov %esi,0x4(%eax)
freep = prevp;
777: 89 15 b4 0a 00 00 mov %edx,0xab4
}
77d: 8d 65 f4 lea -0xc(%ebp),%esp
return (void*)(p + 1);
780: 83 c0 08 add $0x8,%eax
}
783: 5b pop %ebx
784: 5e pop %esi
785: 5f pop %edi
786: 5d pop %ebp
787: c3 ret
788: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
78f: 90 nop
base.s.ptr = freep = prevp = &base;
790: c7 05 b4 0a 00 00 b8 movl $0xab8,0xab4
797: 0a 00 00
base.s.size = 0;
79a: bf b8 0a 00 00 mov $0xab8,%edi
base.s.ptr = freep = prevp = &base;
79f: c7 05 b8 0a 00 00 b8 movl $0xab8,0xab8
7a6: 0a 00 00
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
7a9: 89 fa mov %edi,%edx
base.s.size = 0;
7ab: c7 05 bc 0a 00 00 00 movl $0x0,0xabc
7b2: 00 00 00
if(p->s.size >= nunits){
7b5: e9 32 ff ff ff jmp 6ec <malloc+0x2c>
7ba: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
prevp->s.ptr = p->s.ptr;
7c0: 8b 08 mov (%eax),%ecx
7c2: 89 0a mov %ecx,(%edx)
7c4: eb b1 jmp 777 <malloc+0xb7>
| 33.914031 | 60 | 0.410584 |
782c2728cae7ccb50181d7c39d5c69e72b59c8ef | 136 | asm | Assembly | LAB 2/hello.asm | Mawlong/Computer-Organization-and-Architecture | 3a7db2a07eea9d30ba385553cdfdb3d0fcb29a80 | [
"MIT"
] | null | null | null | LAB 2/hello.asm | Mawlong/Computer-Organization-and-Architecture | 3a7db2a07eea9d30ba385553cdfdb3d0fcb29a80 | [
"MIT"
] | null | null | null | LAB 2/hello.asm | Mawlong/Computer-Organization-and-Architecture | 3a7db2a07eea9d30ba385553cdfdb3d0fcb29a80 | [
"MIT"
] | null | null | null | .data
.text
.globl main
main:
li $t0,1
li $t1,2
li $t2,3
li $t3,4
li $t0,5
li $t1,6
li $t2,7
li $t3,8
li $v0,10
syscall | 8.5 | 12 | 0.544118 |
364f2858f798d6eb92bde31d90aa6d1a16934788 | 3,804 | asm | Assembly | coverage/IN_CTS/0507-COVERAGE-spirv-reader-7046-7059/work/variant/1_spirv_asm/shader.frag.asm | asuonpaa/ShaderTests | 6a3672040dcfa0d164d313224446496d1775a15e | [
"Apache-2.0"
] | null | null | null | coverage/IN_CTS/0507-COVERAGE-spirv-reader-7046-7059/work/variant/1_spirv_asm/shader.frag.asm | asuonpaa/ShaderTests | 6a3672040dcfa0d164d313224446496d1775a15e | [
"Apache-2.0"
] | 47 | 2021-03-11T07:42:51.000Z | 2022-03-14T06:30:14.000Z | coverage/IN_CTS/0507-COVERAGE-spirv-reader-7046-7059/work/variant/1_spirv_asm/shader.frag.asm | asuonpaa/ShaderTests | 6a3672040dcfa0d164d313224446496d1775a15e | [
"Apache-2.0"
] | 4 | 2021-03-09T13:37:19.000Z | 2022-02-25T07:32:11.000Z | ; SPIR-V
; Version: 1.0
; Generator: Khronos Glslang Reference Front End; 10
; Bound: 61
; Schema: 0
OpCapability Shader
%1 = OpExtInstImport "GLSL.std.450"
OpMemoryModel Logical GLSL450
OpEntryPoint Fragment %4 "main" %41
OpExecutionMode %4 OriginUpperLeft
OpSource ESSL 320
OpName %4 "main"
OpName %9 "buf_push"
OpMemberName %9 0 "m"
OpName %11 ""
OpName %17 "buf0"
OpMemberName %17 0 "_GLF_uniform_int_values"
OpName %19 ""
OpName %30 "buf1"
OpMemberName %30 0 "_GLF_uniform_float_values"
OpName %32 ""
OpName %41 "_GLF_color"
OpMemberDecorate %9 0 ColMajor
OpMemberDecorate %9 0 Offset 0
OpMemberDecorate %9 0 MatrixStride 16
OpDecorate %9 Block
OpDecorate %16 ArrayStride 16
OpMemberDecorate %17 0 Offset 0
OpDecorate %17 Block
OpDecorate %19 DescriptorSet 0
OpDecorate %19 Binding 0
OpDecorate %29 ArrayStride 16
OpMemberDecorate %30 0 Offset 0
OpDecorate %30 Block
OpDecorate %32 DescriptorSet 0
OpDecorate %32 Binding 1
OpDecorate %41 Location 0
%2 = OpTypeVoid
%3 = OpTypeFunction %2
%6 = OpTypeFloat 32
%7 = OpTypeVector %6 4
%8 = OpTypeMatrix %7 4
%9 = OpTypeStruct %8
%10 = OpTypePointer PushConstant %9
%11 = OpVariable %10 PushConstant
%12 = OpTypeInt 32 1
%13 = OpConstant %12 0
%14 = OpTypeInt 32 0
%15 = OpConstant %14 2
%16 = OpTypeArray %12 %15
%17 = OpTypeStruct %16
%18 = OpTypePointer Uniform %17
%19 = OpVariable %18 Uniform
%20 = OpTypePointer Uniform %12
%25 = OpTypePointer PushConstant %6
%28 = OpConstant %14 1
%29 = OpTypeArray %6 %28
%30 = OpTypeStruct %29
%31 = OpTypePointer Uniform %30
%32 = OpVariable %31 Uniform
%33 = OpTypePointer Uniform %6
%36 = OpTypeBool
%40 = OpTypePointer Output %7
%41 = OpVariable %40 Output
%42 = OpConstant %12 1
%4 = OpFunction %2 None %3
%5 = OpLabel
%21 = OpAccessChain %20 %19 %13 %13
%22 = OpLoad %12 %21
%23 = OpAccessChain %20 %19 %13 %13
%24 = OpLoad %12 %23
%26 = OpAccessChain %25 %11 %13 %22 %24
%27 = OpLoad %6 %26
%34 = OpAccessChain %33 %32 %13 %13
%35 = OpLoad %6 %34
%37 = OpFOrdEqual %36 %27 %35
OpSelectionMerge %39 None
OpBranchConditional %37 %38 %56
%38 = OpLabel
%43 = OpAccessChain %20 %19 %13 %42
%44 = OpLoad %12 %43
%45 = OpConvertSToF %6 %44
%46 = OpAccessChain %20 %19 %13 %13
%47 = OpLoad %12 %46
%48 = OpConvertSToF %6 %47
%49 = OpAccessChain %20 %19 %13 %13
%50 = OpLoad %12 %49
%51 = OpConvertSToF %6 %50
%52 = OpAccessChain %20 %19 %13 %42
%53 = OpLoad %12 %52
%54 = OpConvertSToF %6 %53
%55 = OpCompositeConstruct %7 %45 %48 %51 %54
OpStore %41 %55
OpBranch %39
%56 = OpLabel
%57 = OpAccessChain %20 %19 %13 %13
%58 = OpLoad %12 %57
%59 = OpConvertSToF %6 %58
%60 = OpCompositeConstruct %7 %59 %59 %59 %59
OpStore %41 %60
OpBranch %39
%39 = OpLabel
OpReturn
OpFunctionEnd
| 36.228571 | 61 | 0.501052 |
853890410143c68073468bc44163a062e8b51476 | 244 | asm | Assembly | libsrc/_DEVELOPMENT/arch/zxn/esxdos/c/sccz80/esx_f_ftrunc_callee.asm | Toysoft/z88dk | f930bef9ac4feeec91a07303b79ddd9071131a24 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/arch/zxn/esxdos/c/sccz80/esx_f_ftrunc_callee.asm | Toysoft/z88dk | f930bef9ac4feeec91a07303b79ddd9071131a24 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/arch/zxn/esxdos/c/sccz80/esx_f_ftrunc_callee.asm | Toysoft/z88dk | f930bef9ac4feeec91a07303b79ddd9071131a24 | [
"ClArtistic"
] | null | null | null | ; unsigned char esx_f_ftrunc(unsigned char handle, uint32_t size)
SECTION code_esxdos
PUBLIC esx_f_ftrunc_callee
EXTERN asm_esx_f_ftrunc
esx_f_ftrunc_callee:
pop hl
pop de
pop bc
ex (sp),hl
ld a,l
jp asm_esx_f_ftrunc
| 13.555556 | 65 | 0.741803 |
be34c7005d3c2b04576649a2201045ee49af6da2 | 558 | asm | Assembly | oeis/033/A033191.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/033/A033191.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/033/A033191.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A033191: Binomial transform of [ 1, 0, 1, 1, 3, 6, 15, 36, 91, 231, 595,... ], which is essentially binomial(fibonacci(k) + 1, 2).
; Submitted by Jon Maiga
; 1,1,2,5,14,42,132,429,1430,4861,16778,58598,206516,732825,2613834,9358677,33602822,120902914,435668420,1571649221,5674201118,20497829133,74079051906,267803779710,968355724724,3502058316337,12666676646162,45818284122149
mov $1,1
mov $5,1
lpb $0
sub $0,1
add $1,$3
sub $2,1
sub $3,$4
sub $2,$3
mov $3,$5
add $4,1
add $4,$1
add $4,$2
sub $4,1
mul $5,4
add $5,$2
lpe
mov $0,$1
| 25.363636 | 220 | 0.670251 |
623ce06e30d97d851f39531d698426b5e43fae1c | 495,370 | asm | Assembly | registers/sfr_f30x.asm | MightyPork/stm32-asm-examples | ca19635a457bffad8b3e3d346da85e12ed7629ed | [
"MIT"
] | 12 | 2016-12-12T02:28:59.000Z | 2021-11-11T03:55:12.000Z | registers/sfr_f30x.asm | MightyPork/stm32-asm-examples | ca19635a457bffad8b3e3d346da85e12ed7629ed | [
"MIT"
] | null | null | null | registers/sfr_f30x.asm | MightyPork/stm32-asm-examples | ca19635a457bffad8b3e3d346da85e12ed7629ed | [
"MIT"
] | 5 | 2016-10-27T22:41:42.000Z | 2021-12-02T09:27:52.000Z |
; ==== STM32F30x PERIPHERALS =================================
;
; CTU Prague, FEL, Department of Measurement
;
; ------------------------------------------------------------
;
; Generated from "STM32F30x.svd"
;
; SVD parsing library (c) Paul Osborne, 2015-2016
; https://github.com/posborne/cmsis-svd
; ASM building script (c) Ondrej Hruska, 2016
;
; ============================================================
; ---- GPIOA -------------------------------------------------
; Desc: General-purpose I/Os
; GPIOA base address:
GPIOA_BASE EQU 0x48000000
; GPIOA registers:
GPIOA_MODER EQU (GPIOA_BASE + 0x0) ; GPIO port mode register
GPIOA_OTYPER EQU (GPIOA_BASE + 0x4) ; GPIO port output type register
GPIOA_OSPEEDR EQU (GPIOA_BASE + 0x8) ; GPIO port output speed register
GPIOA_PUPDR EQU (GPIOA_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOA_IDR EQU (GPIOA_BASE + 0x10) ; GPIO port input data register
GPIOA_ODR EQU (GPIOA_BASE + 0x14) ; GPIO port output data register
GPIOA_BSRR EQU (GPIOA_BASE + 0x18) ; GPIO port bit set/reset register
GPIOA_LCKR EQU (GPIOA_BASE + 0x1c) ; GPIO port configuration lock register
GPIOA_AFRL EQU (GPIOA_BASE + 0x20) ; GPIO alternate function low register
GPIOA_AFRH EQU (GPIOA_BASE + 0x24) ; GPIO alternate function high register
GPIOA_BRR EQU (GPIOA_BASE + 0x28) ; Port bit reset register
; GPIOA_MODER fields:
GPIO_MODER_MODER15 EQU 0xc0000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER15_ofs EQU 30
GPIO_MODER_MODER15_len EQU 2
GPIO_MODER_MODER14 EQU 0x30000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER14_ofs EQU 28
GPIO_MODER_MODER14_len EQU 2
GPIO_MODER_MODER13 EQU 0x0c000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER13_ofs EQU 26
GPIO_MODER_MODER13_len EQU 2
GPIO_MODER_MODER12 EQU 0x03000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER12_ofs EQU 24
GPIO_MODER_MODER12_len EQU 2
GPIO_MODER_MODER11 EQU 0x00c00000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER11_ofs EQU 22
GPIO_MODER_MODER11_len EQU 2
GPIO_MODER_MODER10 EQU 0x00300000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER10_ofs EQU 20
GPIO_MODER_MODER10_len EQU 2
GPIO_MODER_MODER9 EQU 0x000c0000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER9_ofs EQU 18
GPIO_MODER_MODER9_len EQU 2
GPIO_MODER_MODER8 EQU 0x00030000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER8_ofs EQU 16
GPIO_MODER_MODER8_len EQU 2
GPIO_MODER_MODER7 EQU 0x0000c000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER7_ofs EQU 14
GPIO_MODER_MODER7_len EQU 2
GPIO_MODER_MODER6 EQU 0x00003000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER6_ofs EQU 12
GPIO_MODER_MODER6_len EQU 2
GPIO_MODER_MODER5 EQU 0x00000c00 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER5_ofs EQU 10
GPIO_MODER_MODER5_len EQU 2
GPIO_MODER_MODER4 EQU 0x00000300 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER4_ofs EQU 8
GPIO_MODER_MODER4_len EQU 2
GPIO_MODER_MODER3 EQU 0x000000c0 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER3_ofs EQU 6
GPIO_MODER_MODER3_len EQU 2
GPIO_MODER_MODER2 EQU 0x00000030 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER2_ofs EQU 4
GPIO_MODER_MODER2_len EQU 2
GPIO_MODER_MODER1 EQU 0x0000000c ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER1_ofs EQU 2
GPIO_MODER_MODER1_len EQU 2
GPIO_MODER_MODER0 EQU 0x00000003 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER0_ofs EQU 0
GPIO_MODER_MODER0_len EQU 2
; GPIOA_OTYPER fields:
GPIO_OTYPER_OT15 EQU 0x00008000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT15_ofs EQU 15
GPIO_OTYPER_OT15_len EQU 1
GPIO_OTYPER_OT14 EQU 0x00004000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT14_ofs EQU 14
GPIO_OTYPER_OT14_len EQU 1
GPIO_OTYPER_OT13 EQU 0x00002000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT13_ofs EQU 13
GPIO_OTYPER_OT13_len EQU 1
GPIO_OTYPER_OT12 EQU 0x00001000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT12_ofs EQU 12
GPIO_OTYPER_OT12_len EQU 1
GPIO_OTYPER_OT11 EQU 0x00000800 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT11_ofs EQU 11
GPIO_OTYPER_OT11_len EQU 1
GPIO_OTYPER_OT10 EQU 0x00000400 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT10_ofs EQU 10
GPIO_OTYPER_OT10_len EQU 1
GPIO_OTYPER_OT9 EQU 0x00000200 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT9_ofs EQU 9
GPIO_OTYPER_OT9_len EQU 1
GPIO_OTYPER_OT8 EQU 0x00000100 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT8_ofs EQU 8
GPIO_OTYPER_OT8_len EQU 1
GPIO_OTYPER_OT7 EQU 0x00000080 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT7_ofs EQU 7
GPIO_OTYPER_OT7_len EQU 1
GPIO_OTYPER_OT6 EQU 0x00000040 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT6_ofs EQU 6
GPIO_OTYPER_OT6_len EQU 1
GPIO_OTYPER_OT5 EQU 0x00000020 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT5_ofs EQU 5
GPIO_OTYPER_OT5_len EQU 1
GPIO_OTYPER_OT4 EQU 0x00000010 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT4_ofs EQU 4
GPIO_OTYPER_OT4_len EQU 1
GPIO_OTYPER_OT3 EQU 0x00000008 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT3_ofs EQU 3
GPIO_OTYPER_OT3_len EQU 1
GPIO_OTYPER_OT2 EQU 0x00000004 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT2_ofs EQU 2
GPIO_OTYPER_OT2_len EQU 1
GPIO_OTYPER_OT1 EQU 0x00000002 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT1_ofs EQU 1
GPIO_OTYPER_OT1_len EQU 1
GPIO_OTYPER_OT0 EQU 0x00000001 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT0_ofs EQU 0
GPIO_OTYPER_OT0_len EQU 1
; GPIOA_OSPEEDR fields:
GPIO_OSPEEDR_OSPEEDR15 EQU 0xc0000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR15_ofs EQU 30
GPIO_OSPEEDR_OSPEEDR15_len EQU 2
GPIO_OSPEEDR_OSPEEDR14 EQU 0x30000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR14_ofs EQU 28
GPIO_OSPEEDR_OSPEEDR14_len EQU 2
GPIO_OSPEEDR_OSPEEDR13 EQU 0x0c000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR13_ofs EQU 26
GPIO_OSPEEDR_OSPEEDR13_len EQU 2
GPIO_OSPEEDR_OSPEEDR12 EQU 0x03000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR12_ofs EQU 24
GPIO_OSPEEDR_OSPEEDR12_len EQU 2
GPIO_OSPEEDR_OSPEEDR11 EQU 0x00c00000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR11_ofs EQU 22
GPIO_OSPEEDR_OSPEEDR11_len EQU 2
GPIO_OSPEEDR_OSPEEDR10 EQU 0x00300000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR10_ofs EQU 20
GPIO_OSPEEDR_OSPEEDR10_len EQU 2
GPIO_OSPEEDR_OSPEEDR9 EQU 0x000c0000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR9_ofs EQU 18
GPIO_OSPEEDR_OSPEEDR9_len EQU 2
GPIO_OSPEEDR_OSPEEDR8 EQU 0x00030000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR8_ofs EQU 16
GPIO_OSPEEDR_OSPEEDR8_len EQU 2
GPIO_OSPEEDR_OSPEEDR7 EQU 0x0000c000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR7_ofs EQU 14
GPIO_OSPEEDR_OSPEEDR7_len EQU 2
GPIO_OSPEEDR_OSPEEDR6 EQU 0x00003000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR6_ofs EQU 12
GPIO_OSPEEDR_OSPEEDR6_len EQU 2
GPIO_OSPEEDR_OSPEEDR5 EQU 0x00000c00 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR5_ofs EQU 10
GPIO_OSPEEDR_OSPEEDR5_len EQU 2
GPIO_OSPEEDR_OSPEEDR4 EQU 0x00000300 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR4_ofs EQU 8
GPIO_OSPEEDR_OSPEEDR4_len EQU 2
GPIO_OSPEEDR_OSPEEDR3 EQU 0x000000c0 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR3_ofs EQU 6
GPIO_OSPEEDR_OSPEEDR3_len EQU 2
GPIO_OSPEEDR_OSPEEDR2 EQU 0x00000030 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR2_ofs EQU 4
GPIO_OSPEEDR_OSPEEDR2_len EQU 2
GPIO_OSPEEDR_OSPEEDR1 EQU 0x0000000c ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR1_ofs EQU 2
GPIO_OSPEEDR_OSPEEDR1_len EQU 2
GPIO_OSPEEDR_OSPEEDR0 EQU 0x00000003 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR0_ofs EQU 0
GPIO_OSPEEDR_OSPEEDR0_len EQU 2
; GPIOA_PUPDR fields:
GPIO_PUPDR_PUPDR15 EQU 0xc0000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR15_ofs EQU 30
GPIO_PUPDR_PUPDR15_len EQU 2
GPIO_PUPDR_PUPDR14 EQU 0x30000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR14_ofs EQU 28
GPIO_PUPDR_PUPDR14_len EQU 2
GPIO_PUPDR_PUPDR13 EQU 0x0c000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR13_ofs EQU 26
GPIO_PUPDR_PUPDR13_len EQU 2
GPIO_PUPDR_PUPDR12 EQU 0x03000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR12_ofs EQU 24
GPIO_PUPDR_PUPDR12_len EQU 2
GPIO_PUPDR_PUPDR11 EQU 0x00c00000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR11_ofs EQU 22
GPIO_PUPDR_PUPDR11_len EQU 2
GPIO_PUPDR_PUPDR10 EQU 0x00300000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR10_ofs EQU 20
GPIO_PUPDR_PUPDR10_len EQU 2
GPIO_PUPDR_PUPDR9 EQU 0x000c0000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR9_ofs EQU 18
GPIO_PUPDR_PUPDR9_len EQU 2
GPIO_PUPDR_PUPDR8 EQU 0x00030000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR8_ofs EQU 16
GPIO_PUPDR_PUPDR8_len EQU 2
GPIO_PUPDR_PUPDR7 EQU 0x0000c000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR7_ofs EQU 14
GPIO_PUPDR_PUPDR7_len EQU 2
GPIO_PUPDR_PUPDR6 EQU 0x00003000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR6_ofs EQU 12
GPIO_PUPDR_PUPDR6_len EQU 2
GPIO_PUPDR_PUPDR5 EQU 0x00000c00 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR5_ofs EQU 10
GPIO_PUPDR_PUPDR5_len EQU 2
GPIO_PUPDR_PUPDR4 EQU 0x00000300 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR4_ofs EQU 8
GPIO_PUPDR_PUPDR4_len EQU 2
GPIO_PUPDR_PUPDR3 EQU 0x000000c0 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR3_ofs EQU 6
GPIO_PUPDR_PUPDR3_len EQU 2
GPIO_PUPDR_PUPDR2 EQU 0x00000030 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR2_ofs EQU 4
GPIO_PUPDR_PUPDR2_len EQU 2
GPIO_PUPDR_PUPDR1 EQU 0x0000000c ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR1_ofs EQU 2
GPIO_PUPDR_PUPDR1_len EQU 2
GPIO_PUPDR_PUPDR0 EQU 0x00000003 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR0_ofs EQU 0
GPIO_PUPDR_PUPDR0_len EQU 2
; GPIOA_IDR fields:
GPIO_IDR_IDR15 EQU 0x00008000 ; Port input data (y = 0..15)
GPIO_IDR_IDR15_ofs EQU 15
GPIO_IDR_IDR15_len EQU 1
GPIO_IDR_IDR14 EQU 0x00004000 ; Port input data (y = 0..15)
GPIO_IDR_IDR14_ofs EQU 14
GPIO_IDR_IDR14_len EQU 1
GPIO_IDR_IDR13 EQU 0x00002000 ; Port input data (y = 0..15)
GPIO_IDR_IDR13_ofs EQU 13
GPIO_IDR_IDR13_len EQU 1
GPIO_IDR_IDR12 EQU 0x00001000 ; Port input data (y = 0..15)
GPIO_IDR_IDR12_ofs EQU 12
GPIO_IDR_IDR12_len EQU 1
GPIO_IDR_IDR11 EQU 0x00000800 ; Port input data (y = 0..15)
GPIO_IDR_IDR11_ofs EQU 11
GPIO_IDR_IDR11_len EQU 1
GPIO_IDR_IDR10 EQU 0x00000400 ; Port input data (y = 0..15)
GPIO_IDR_IDR10_ofs EQU 10
GPIO_IDR_IDR10_len EQU 1
GPIO_IDR_IDR9 EQU 0x00000200 ; Port input data (y = 0..15)
GPIO_IDR_IDR9_ofs EQU 9
GPIO_IDR_IDR9_len EQU 1
GPIO_IDR_IDR8 EQU 0x00000100 ; Port input data (y = 0..15)
GPIO_IDR_IDR8_ofs EQU 8
GPIO_IDR_IDR8_len EQU 1
GPIO_IDR_IDR7 EQU 0x00000080 ; Port input data (y = 0..15)
GPIO_IDR_IDR7_ofs EQU 7
GPIO_IDR_IDR7_len EQU 1
GPIO_IDR_IDR6 EQU 0x00000040 ; Port input data (y = 0..15)
GPIO_IDR_IDR6_ofs EQU 6
GPIO_IDR_IDR6_len EQU 1
GPIO_IDR_IDR5 EQU 0x00000020 ; Port input data (y = 0..15)
GPIO_IDR_IDR5_ofs EQU 5
GPIO_IDR_IDR5_len EQU 1
GPIO_IDR_IDR4 EQU 0x00000010 ; Port input data (y = 0..15)
GPIO_IDR_IDR4_ofs EQU 4
GPIO_IDR_IDR4_len EQU 1
GPIO_IDR_IDR3 EQU 0x00000008 ; Port input data (y = 0..15)
GPIO_IDR_IDR3_ofs EQU 3
GPIO_IDR_IDR3_len EQU 1
GPIO_IDR_IDR2 EQU 0x00000004 ; Port input data (y = 0..15)
GPIO_IDR_IDR2_ofs EQU 2
GPIO_IDR_IDR2_len EQU 1
GPIO_IDR_IDR1 EQU 0x00000002 ; Port input data (y = 0..15)
GPIO_IDR_IDR1_ofs EQU 1
GPIO_IDR_IDR1_len EQU 1
GPIO_IDR_IDR0 EQU 0x00000001 ; Port input data (y = 0..15)
GPIO_IDR_IDR0_ofs EQU 0
GPIO_IDR_IDR0_len EQU 1
; GPIOA_ODR fields:
GPIO_ODR_ODR15 EQU 0x00008000 ; Port output data (y = 0..15)
GPIO_ODR_ODR15_ofs EQU 15
GPIO_ODR_ODR15_len EQU 1
GPIO_ODR_ODR14 EQU 0x00004000 ; Port output data (y = 0..15)
GPIO_ODR_ODR14_ofs EQU 14
GPIO_ODR_ODR14_len EQU 1
GPIO_ODR_ODR13 EQU 0x00002000 ; Port output data (y = 0..15)
GPIO_ODR_ODR13_ofs EQU 13
GPIO_ODR_ODR13_len EQU 1
GPIO_ODR_ODR12 EQU 0x00001000 ; Port output data (y = 0..15)
GPIO_ODR_ODR12_ofs EQU 12
GPIO_ODR_ODR12_len EQU 1
GPIO_ODR_ODR11 EQU 0x00000800 ; Port output data (y = 0..15)
GPIO_ODR_ODR11_ofs EQU 11
GPIO_ODR_ODR11_len EQU 1
GPIO_ODR_ODR10 EQU 0x00000400 ; Port output data (y = 0..15)
GPIO_ODR_ODR10_ofs EQU 10
GPIO_ODR_ODR10_len EQU 1
GPIO_ODR_ODR9 EQU 0x00000200 ; Port output data (y = 0..15)
GPIO_ODR_ODR9_ofs EQU 9
GPIO_ODR_ODR9_len EQU 1
GPIO_ODR_ODR8 EQU 0x00000100 ; Port output data (y = 0..15)
GPIO_ODR_ODR8_ofs EQU 8
GPIO_ODR_ODR8_len EQU 1
GPIO_ODR_ODR7 EQU 0x00000080 ; Port output data (y = 0..15)
GPIO_ODR_ODR7_ofs EQU 7
GPIO_ODR_ODR7_len EQU 1
GPIO_ODR_ODR6 EQU 0x00000040 ; Port output data (y = 0..15)
GPIO_ODR_ODR6_ofs EQU 6
GPIO_ODR_ODR6_len EQU 1
GPIO_ODR_ODR5 EQU 0x00000020 ; Port output data (y = 0..15)
GPIO_ODR_ODR5_ofs EQU 5
GPIO_ODR_ODR5_len EQU 1
GPIO_ODR_ODR4 EQU 0x00000010 ; Port output data (y = 0..15)
GPIO_ODR_ODR4_ofs EQU 4
GPIO_ODR_ODR4_len EQU 1
GPIO_ODR_ODR3 EQU 0x00000008 ; Port output data (y = 0..15)
GPIO_ODR_ODR3_ofs EQU 3
GPIO_ODR_ODR3_len EQU 1
GPIO_ODR_ODR2 EQU 0x00000004 ; Port output data (y = 0..15)
GPIO_ODR_ODR2_ofs EQU 2
GPIO_ODR_ODR2_len EQU 1
GPIO_ODR_ODR1 EQU 0x00000002 ; Port output data (y = 0..15)
GPIO_ODR_ODR1_ofs EQU 1
GPIO_ODR_ODR1_len EQU 1
GPIO_ODR_ODR0 EQU 0x00000001 ; Port output data (y = 0..15)
GPIO_ODR_ODR0_ofs EQU 0
GPIO_ODR_ODR0_len EQU 1
; GPIOA_BSRR fields:
GPIO_BSRR_BR15 EQU 0x80000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR15_ofs EQU 31
GPIO_BSRR_BR15_len EQU 1
GPIO_BSRR_BR14 EQU 0x40000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR14_ofs EQU 30
GPIO_BSRR_BR14_len EQU 1
GPIO_BSRR_BR13 EQU 0x20000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR13_ofs EQU 29
GPIO_BSRR_BR13_len EQU 1
GPIO_BSRR_BR12 EQU 0x10000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR12_ofs EQU 28
GPIO_BSRR_BR12_len EQU 1
GPIO_BSRR_BR11 EQU 0x08000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR11_ofs EQU 27
GPIO_BSRR_BR11_len EQU 1
GPIO_BSRR_BR10 EQU 0x04000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR10_ofs EQU 26
GPIO_BSRR_BR10_len EQU 1
GPIO_BSRR_BR9 EQU 0x02000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR9_ofs EQU 25
GPIO_BSRR_BR9_len EQU 1
GPIO_BSRR_BR8 EQU 0x01000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR8_ofs EQU 24
GPIO_BSRR_BR8_len EQU 1
GPIO_BSRR_BR7 EQU 0x00800000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR7_ofs EQU 23
GPIO_BSRR_BR7_len EQU 1
GPIO_BSRR_BR6 EQU 0x00400000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR6_ofs EQU 22
GPIO_BSRR_BR6_len EQU 1
GPIO_BSRR_BR5 EQU 0x00200000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR5_ofs EQU 21
GPIO_BSRR_BR5_len EQU 1
GPIO_BSRR_BR4 EQU 0x00100000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR4_ofs EQU 20
GPIO_BSRR_BR4_len EQU 1
GPIO_BSRR_BR3 EQU 0x00080000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR3_ofs EQU 19
GPIO_BSRR_BR3_len EQU 1
GPIO_BSRR_BR2 EQU 0x00040000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR2_ofs EQU 18
GPIO_BSRR_BR2_len EQU 1
GPIO_BSRR_BR1 EQU 0x00020000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR1_ofs EQU 17
GPIO_BSRR_BR1_len EQU 1
GPIO_BSRR_BR0 EQU 0x00010000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BR0_ofs EQU 16
GPIO_BSRR_BR0_len EQU 1
GPIO_BSRR_BS15 EQU 0x00008000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS15_ofs EQU 15
GPIO_BSRR_BS15_len EQU 1
GPIO_BSRR_BS14 EQU 0x00004000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS14_ofs EQU 14
GPIO_BSRR_BS14_len EQU 1
GPIO_BSRR_BS13 EQU 0x00002000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS13_ofs EQU 13
GPIO_BSRR_BS13_len EQU 1
GPIO_BSRR_BS12 EQU 0x00001000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS12_ofs EQU 12
GPIO_BSRR_BS12_len EQU 1
GPIO_BSRR_BS11 EQU 0x00000800 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS11_ofs EQU 11
GPIO_BSRR_BS11_len EQU 1
GPIO_BSRR_BS10 EQU 0x00000400 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS10_ofs EQU 10
GPIO_BSRR_BS10_len EQU 1
GPIO_BSRR_BS9 EQU 0x00000200 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS9_ofs EQU 9
GPIO_BSRR_BS9_len EQU 1
GPIO_BSRR_BS8 EQU 0x00000100 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS8_ofs EQU 8
GPIO_BSRR_BS8_len EQU 1
GPIO_BSRR_BS7 EQU 0x00000080 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS7_ofs EQU 7
GPIO_BSRR_BS7_len EQU 1
GPIO_BSRR_BS6 EQU 0x00000040 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS6_ofs EQU 6
GPIO_BSRR_BS6_len EQU 1
GPIO_BSRR_BS5 EQU 0x00000020 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS5_ofs EQU 5
GPIO_BSRR_BS5_len EQU 1
GPIO_BSRR_BS4 EQU 0x00000010 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS4_ofs EQU 4
GPIO_BSRR_BS4_len EQU 1
GPIO_BSRR_BS3 EQU 0x00000008 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS3_ofs EQU 3
GPIO_BSRR_BS3_len EQU 1
GPIO_BSRR_BS2 EQU 0x00000004 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS2_ofs EQU 2
GPIO_BSRR_BS2_len EQU 1
GPIO_BSRR_BS1 EQU 0x00000002 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS1_ofs EQU 1
GPIO_BSRR_BS1_len EQU 1
GPIO_BSRR_BS0 EQU 0x00000001 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS0_ofs EQU 0
GPIO_BSRR_BS0_len EQU 1
; GPIOA_LCKR fields:
GPIO_LCKR_LCKK EQU 0x00010000 ; Lok Key
GPIO_LCKR_LCKK_ofs EQU 16
GPIO_LCKR_LCKK_len EQU 1
GPIO_LCKR_LCK15 EQU 0x00008000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK15_ofs EQU 15
GPIO_LCKR_LCK15_len EQU 1
GPIO_LCKR_LCK14 EQU 0x00004000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK14_ofs EQU 14
GPIO_LCKR_LCK14_len EQU 1
GPIO_LCKR_LCK13 EQU 0x00002000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK13_ofs EQU 13
GPIO_LCKR_LCK13_len EQU 1
GPIO_LCKR_LCK12 EQU 0x00001000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK12_ofs EQU 12
GPIO_LCKR_LCK12_len EQU 1
GPIO_LCKR_LCK11 EQU 0x00000800 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK11_ofs EQU 11
GPIO_LCKR_LCK11_len EQU 1
GPIO_LCKR_LCK10 EQU 0x00000400 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK10_ofs EQU 10
GPIO_LCKR_LCK10_len EQU 1
GPIO_LCKR_LCK9 EQU 0x00000200 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK9_ofs EQU 9
GPIO_LCKR_LCK9_len EQU 1
GPIO_LCKR_LCK8 EQU 0x00000100 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK8_ofs EQU 8
GPIO_LCKR_LCK8_len EQU 1
GPIO_LCKR_LCK7 EQU 0x00000080 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK7_ofs EQU 7
GPIO_LCKR_LCK7_len EQU 1
GPIO_LCKR_LCK6 EQU 0x00000040 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK6_ofs EQU 6
GPIO_LCKR_LCK6_len EQU 1
GPIO_LCKR_LCK5 EQU 0x00000020 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK5_ofs EQU 5
GPIO_LCKR_LCK5_len EQU 1
GPIO_LCKR_LCK4 EQU 0x00000010 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK4_ofs EQU 4
GPIO_LCKR_LCK4_len EQU 1
GPIO_LCKR_LCK3 EQU 0x00000008 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK3_ofs EQU 3
GPIO_LCKR_LCK3_len EQU 1
GPIO_LCKR_LCK2 EQU 0x00000004 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK2_ofs EQU 2
GPIO_LCKR_LCK2_len EQU 1
GPIO_LCKR_LCK1 EQU 0x00000002 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK1_ofs EQU 1
GPIO_LCKR_LCK1_len EQU 1
GPIO_LCKR_LCK0 EQU 0x00000001 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK0_ofs EQU 0
GPIO_LCKR_LCK0_len EQU 1
; GPIOA_AFRL fields:
GPIO_AFRL_AFRL7 EQU 0xf0000000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL7_ofs EQU 28
GPIO_AFRL_AFRL7_len EQU 4
GPIO_AFRL_AFRL6 EQU 0x0f000000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL6_ofs EQU 24
GPIO_AFRL_AFRL6_len EQU 4
GPIO_AFRL_AFRL5 EQU 0x00f00000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL5_ofs EQU 20
GPIO_AFRL_AFRL5_len EQU 4
GPIO_AFRL_AFRL4 EQU 0x000f0000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL4_ofs EQU 16
GPIO_AFRL_AFRL4_len EQU 4
GPIO_AFRL_AFRL3 EQU 0x0000f000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL3_ofs EQU 12
GPIO_AFRL_AFRL3_len EQU 4
GPIO_AFRL_AFRL2 EQU 0x00000f00 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL2_ofs EQU 8
GPIO_AFRL_AFRL2_len EQU 4
GPIO_AFRL_AFRL1 EQU 0x000000f0 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL1_ofs EQU 4
GPIO_AFRL_AFRL1_len EQU 4
GPIO_AFRL_AFRL0 EQU 0x0000000f ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL0_ofs EQU 0
GPIO_AFRL_AFRL0_len EQU 4
; GPIOA_AFRH fields:
GPIO_AFRH_AFRH15 EQU 0xf0000000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH15_ofs EQU 28
GPIO_AFRH_AFRH15_len EQU 4
GPIO_AFRH_AFRH14 EQU 0x0f000000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH14_ofs EQU 24
GPIO_AFRH_AFRH14_len EQU 4
GPIO_AFRH_AFRH13 EQU 0x00f00000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH13_ofs EQU 20
GPIO_AFRH_AFRH13_len EQU 4
GPIO_AFRH_AFRH12 EQU 0x000f0000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH12_ofs EQU 16
GPIO_AFRH_AFRH12_len EQU 4
GPIO_AFRH_AFRH11 EQU 0x0000f000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH11_ofs EQU 12
GPIO_AFRH_AFRH11_len EQU 4
GPIO_AFRH_AFRH10 EQU 0x00000f00 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH10_ofs EQU 8
GPIO_AFRH_AFRH10_len EQU 4
GPIO_AFRH_AFRH9 EQU 0x000000f0 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH9_ofs EQU 4
GPIO_AFRH_AFRH9_len EQU 4
GPIO_AFRH_AFRH8 EQU 0x0000000f ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH8_ofs EQU 0
GPIO_AFRH_AFRH8_len EQU 4
; GPIOA_BRR fields:
GPIO_BRR_BR0 EQU 0x00000001 ; Port x Reset bit y
GPIO_BRR_BR0_ofs EQU 0
GPIO_BRR_BR0_len EQU 1
GPIO_BRR_BR1 EQU 0x00000002 ; Port x Reset bit y
GPIO_BRR_BR1_ofs EQU 1
GPIO_BRR_BR1_len EQU 1
GPIO_BRR_BR2 EQU 0x00000004 ; Port x Reset bit y
GPIO_BRR_BR2_ofs EQU 2
GPIO_BRR_BR2_len EQU 1
GPIO_BRR_BR3 EQU 0x00000008 ; Port x Reset bit y
GPIO_BRR_BR3_ofs EQU 3
GPIO_BRR_BR3_len EQU 1
GPIO_BRR_BR4 EQU 0x00000010 ; Port x Reset bit y
GPIO_BRR_BR4_ofs EQU 4
GPIO_BRR_BR4_len EQU 1
GPIO_BRR_BR5 EQU 0x00000020 ; Port x Reset bit y
GPIO_BRR_BR5_ofs EQU 5
GPIO_BRR_BR5_len EQU 1
GPIO_BRR_BR6 EQU 0x00000040 ; Port x Reset bit y
GPIO_BRR_BR6_ofs EQU 6
GPIO_BRR_BR6_len EQU 1
GPIO_BRR_BR7 EQU 0x00000080 ; Port x Reset bit y
GPIO_BRR_BR7_ofs EQU 7
GPIO_BRR_BR7_len EQU 1
GPIO_BRR_BR8 EQU 0x00000100 ; Port x Reset bit y
GPIO_BRR_BR8_ofs EQU 8
GPIO_BRR_BR8_len EQU 1
GPIO_BRR_BR9 EQU 0x00000200 ; Port x Reset bit y
GPIO_BRR_BR9_ofs EQU 9
GPIO_BRR_BR9_len EQU 1
GPIO_BRR_BR10 EQU 0x00000400 ; Port x Reset bit y
GPIO_BRR_BR10_ofs EQU 10
GPIO_BRR_BR10_len EQU 1
GPIO_BRR_BR11 EQU 0x00000800 ; Port x Reset bit y
GPIO_BRR_BR11_ofs EQU 11
GPIO_BRR_BR11_len EQU 1
GPIO_BRR_BR12 EQU 0x00001000 ; Port x Reset bit y
GPIO_BRR_BR12_ofs EQU 12
GPIO_BRR_BR12_len EQU 1
GPIO_BRR_BR13 EQU 0x00002000 ; Port x Reset bit y
GPIO_BRR_BR13_ofs EQU 13
GPIO_BRR_BR13_len EQU 1
GPIO_BRR_BR14 EQU 0x00004000 ; Port x Reset bit y
GPIO_BRR_BR14_ofs EQU 14
GPIO_BRR_BR14_len EQU 1
GPIO_BRR_BR15 EQU 0x00008000 ; Port x Reset bit y
GPIO_BRR_BR15_ofs EQU 15
GPIO_BRR_BR15_len EQU 1
; ---- GPIOB -------------------------------------------------
; Desc: General-purpose I/Os
; GPIOB base address:
GPIOB_BASE EQU 0x48000400
; GPIOB registers:
GPIOB_MODER EQU (GPIOB_BASE + 0x0) ; GPIO port mode register
GPIOB_OTYPER EQU (GPIOB_BASE + 0x4) ; GPIO port output type register
GPIOB_OSPEEDR EQU (GPIOB_BASE + 0x8) ; GPIO port output speed register
GPIOB_PUPDR EQU (GPIOB_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOB_IDR EQU (GPIOB_BASE + 0x10) ; GPIO port input data register
GPIOB_ODR EQU (GPIOB_BASE + 0x14) ; GPIO port output data register
GPIOB_BSRR EQU (GPIOB_BASE + 0x18) ; GPIO port bit set/reset register
GPIOB_LCKR EQU (GPIOB_BASE + 0x1c) ; GPIO port configuration lock register
GPIOB_AFRL EQU (GPIOB_BASE + 0x20) ; GPIO alternate function low register
GPIOB_AFRH EQU (GPIOB_BASE + 0x24) ; GPIO alternate function high register
GPIOB_BRR EQU (GPIOB_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOC -------------------------------------------------
; Desc: None
; GPIOC base address:
GPIOC_BASE EQU 0x48000800
; GPIOC registers:
GPIOC_MODER EQU (GPIOC_BASE + 0x0) ; GPIO port mode register
GPIOC_OTYPER EQU (GPIOC_BASE + 0x4) ; GPIO port output type register
GPIOC_OSPEEDR EQU (GPIOC_BASE + 0x8) ; GPIO port output speed register
GPIOC_PUPDR EQU (GPIOC_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOC_IDR EQU (GPIOC_BASE + 0x10) ; GPIO port input data register
GPIOC_ODR EQU (GPIOC_BASE + 0x14) ; GPIO port output data register
GPIOC_BSRR EQU (GPIOC_BASE + 0x18) ; GPIO port bit set/reset register
GPIOC_LCKR EQU (GPIOC_BASE + 0x1c) ; GPIO port configuration lock register
GPIOC_AFRL EQU (GPIOC_BASE + 0x20) ; GPIO alternate function low register
GPIOC_AFRH EQU (GPIOC_BASE + 0x24) ; GPIO alternate function high register
GPIOC_BRR EQU (GPIOC_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOD -------------------------------------------------
; Desc: None
; GPIOD base address:
GPIOD_BASE EQU 0x48000c00
; GPIOD registers:
GPIOD_MODER EQU (GPIOD_BASE + 0x0) ; GPIO port mode register
GPIOD_OTYPER EQU (GPIOD_BASE + 0x4) ; GPIO port output type register
GPIOD_OSPEEDR EQU (GPIOD_BASE + 0x8) ; GPIO port output speed register
GPIOD_PUPDR EQU (GPIOD_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOD_IDR EQU (GPIOD_BASE + 0x10) ; GPIO port input data register
GPIOD_ODR EQU (GPIOD_BASE + 0x14) ; GPIO port output data register
GPIOD_BSRR EQU (GPIOD_BASE + 0x18) ; GPIO port bit set/reset register
GPIOD_LCKR EQU (GPIOD_BASE + 0x1c) ; GPIO port configuration lock register
GPIOD_AFRL EQU (GPIOD_BASE + 0x20) ; GPIO alternate function low register
GPIOD_AFRH EQU (GPIOD_BASE + 0x24) ; GPIO alternate function high register
GPIOD_BRR EQU (GPIOD_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOE -------------------------------------------------
; Desc: None
; GPIOE base address:
GPIOE_BASE EQU 0x48001000
; GPIOE registers:
GPIOE_MODER EQU (GPIOE_BASE + 0x0) ; GPIO port mode register
GPIOE_OTYPER EQU (GPIOE_BASE + 0x4) ; GPIO port output type register
GPIOE_OSPEEDR EQU (GPIOE_BASE + 0x8) ; GPIO port output speed register
GPIOE_PUPDR EQU (GPIOE_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOE_IDR EQU (GPIOE_BASE + 0x10) ; GPIO port input data register
GPIOE_ODR EQU (GPIOE_BASE + 0x14) ; GPIO port output data register
GPIOE_BSRR EQU (GPIOE_BASE + 0x18) ; GPIO port bit set/reset register
GPIOE_LCKR EQU (GPIOE_BASE + 0x1c) ; GPIO port configuration lock register
GPIOE_AFRL EQU (GPIOE_BASE + 0x20) ; GPIO alternate function low register
GPIOE_AFRH EQU (GPIOE_BASE + 0x24) ; GPIO alternate function high register
GPIOE_BRR EQU (GPIOE_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOF -------------------------------------------------
; Desc: None
; GPIOF base address:
GPIOF_BASE EQU 0x48001400
; GPIOF registers:
GPIOF_MODER EQU (GPIOF_BASE + 0x0) ; GPIO port mode register
GPIOF_OTYPER EQU (GPIOF_BASE + 0x4) ; GPIO port output type register
GPIOF_OSPEEDR EQU (GPIOF_BASE + 0x8) ; GPIO port output speed register
GPIOF_PUPDR EQU (GPIOF_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOF_IDR EQU (GPIOF_BASE + 0x10) ; GPIO port input data register
GPIOF_ODR EQU (GPIOF_BASE + 0x14) ; GPIO port output data register
GPIOF_BSRR EQU (GPIOF_BASE + 0x18) ; GPIO port bit set/reset register
GPIOF_LCKR EQU (GPIOF_BASE + 0x1c) ; GPIO port configuration lock register
GPIOF_AFRL EQU (GPIOF_BASE + 0x20) ; GPIO alternate function low register
GPIOF_AFRH EQU (GPIOF_BASE + 0x24) ; GPIO alternate function high register
GPIOF_BRR EQU (GPIOF_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- TSC ---------------------------------------------------
; Desc: Touch sensing controller
; TSC base address:
TSC_BASE EQU 0x40024000
; TSC registers:
TSC_CR EQU (TSC_BASE + 0x0) ; control register
TSC_IER EQU (TSC_BASE + 0x4) ; interrupt enable register
TSC_ICR EQU (TSC_BASE + 0x8) ; interrupt clear register
TSC_ISR EQU (TSC_BASE + 0xc) ; interrupt status register
TSC_IOHCR EQU (TSC_BASE + 0x10) ; I/O hysteresis control register
TSC_IOASCR EQU (TSC_BASE + 0x18) ; I/O analog switch control register
TSC_IOSCR EQU (TSC_BASE + 0x20) ; I/O sampling control register
TSC_IOCCR EQU (TSC_BASE + 0x28) ; I/O channel control register
TSC_IOGCSR EQU (TSC_BASE + 0x30) ; I/O group control status register
TSC_IOG1CR EQU (TSC_BASE + 0x34) ; I/O group x counter register
TSC_IOG2CR EQU (TSC_BASE + 0x38) ; I/O group x counter register
TSC_IOG3CR EQU (TSC_BASE + 0x3c) ; I/O group x counter register
TSC_IOG4CR EQU (TSC_BASE + 0x40) ; I/O group x counter register
TSC_IOG5CR EQU (TSC_BASE + 0x44) ; I/O group x counter register
TSC_IOG6CR EQU (TSC_BASE + 0x48) ; I/O group x counter register
TSC_IOG7CR EQU (TSC_BASE + 0x4c) ; I/O group x counter register
TSC_IOG8CR EQU (TSC_BASE + 0x50) ; I/O group x counter register
; TSC_CR fields:
TSC_CR_CTPH EQU 0xf0000000 ; Charge transfer pulse high
TSC_CR_CTPH_ofs EQU 28
TSC_CR_CTPH_len EQU 4
TSC_CR_CTPL EQU 0x0f000000 ; Charge transfer pulse low
TSC_CR_CTPL_ofs EQU 24
TSC_CR_CTPL_len EQU 4
TSC_CR_SSD EQU 0x00fe0000 ; Spread spectrum deviation
TSC_CR_SSD_ofs EQU 17
TSC_CR_SSD_len EQU 7
TSC_CR_SSE EQU 0x00010000 ; Spread spectrum enable
TSC_CR_SSE_ofs EQU 16
TSC_CR_SSE_len EQU 1
TSC_CR_SSPSC EQU 0x00008000 ; Spread spectrum prescaler
TSC_CR_SSPSC_ofs EQU 15
TSC_CR_SSPSC_len EQU 1
TSC_CR_PGPSC EQU 0x00007000 ; pulse generator prescaler
TSC_CR_PGPSC_ofs EQU 12
TSC_CR_PGPSC_len EQU 3
TSC_CR_MCV EQU 0x000000e0 ; Max count value
TSC_CR_MCV_ofs EQU 5
TSC_CR_MCV_len EQU 3
TSC_CR_IODEF EQU 0x00000010 ; I/O Default mode
TSC_CR_IODEF_ofs EQU 4
TSC_CR_IODEF_len EQU 1
TSC_CR_SYNCPOL EQU 0x00000008 ; Synchronization pin polarity
TSC_CR_SYNCPOL_ofs EQU 3
TSC_CR_SYNCPOL_len EQU 1
TSC_CR_AM EQU 0x00000004 ; Acquisition mode
TSC_CR_AM_ofs EQU 2
TSC_CR_AM_len EQU 1
TSC_CR_START EQU 0x00000002 ; Start a new acquisition
TSC_CR_START_ofs EQU 1
TSC_CR_START_len EQU 1
TSC_CR_TSCE EQU 0x00000001 ; Touch sensing controller enable
TSC_CR_TSCE_ofs EQU 0
TSC_CR_TSCE_len EQU 1
; TSC_IER fields:
TSC_IER_MCEIE EQU 0x00000002 ; Max count error interrupt enable
TSC_IER_MCEIE_ofs EQU 1
TSC_IER_MCEIE_len EQU 1
TSC_IER_EOAIE EQU 0x00000001 ; End of acquisition interrupt enable
TSC_IER_EOAIE_ofs EQU 0
TSC_IER_EOAIE_len EQU 1
; TSC_ICR fields:
TSC_ICR_MCEIC EQU 0x00000002 ; Max count error interrupt clear
TSC_ICR_MCEIC_ofs EQU 1
TSC_ICR_MCEIC_len EQU 1
TSC_ICR_EOAIC EQU 0x00000001 ; End of acquisition interrupt clear
TSC_ICR_EOAIC_ofs EQU 0
TSC_ICR_EOAIC_len EQU 1
; TSC_ISR fields:
TSC_ISR_MCEF EQU 0x00000002 ; Max count error flag
TSC_ISR_MCEF_ofs EQU 1
TSC_ISR_MCEF_len EQU 1
TSC_ISR_EOAF EQU 0x00000001 ; End of acquisition flag
TSC_ISR_EOAF_ofs EQU 0
TSC_ISR_EOAF_len EQU 1
; TSC_IOHCR fields:
TSC_IOHCR_G1_IO1 EQU 0x00000001 ; G1_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO1_ofs EQU 0
TSC_IOHCR_G1_IO1_len EQU 1
TSC_IOHCR_G1_IO2 EQU 0x00000002 ; G1_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO2_ofs EQU 1
TSC_IOHCR_G1_IO2_len EQU 1
TSC_IOHCR_G1_IO3 EQU 0x00000004 ; G1_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO3_ofs EQU 2
TSC_IOHCR_G1_IO3_len EQU 1
TSC_IOHCR_G1_IO4 EQU 0x00000008 ; G1_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO4_ofs EQU 3
TSC_IOHCR_G1_IO4_len EQU 1
TSC_IOHCR_G2_IO1 EQU 0x00000010 ; G2_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO1_ofs EQU 4
TSC_IOHCR_G2_IO1_len EQU 1
TSC_IOHCR_G2_IO2 EQU 0x00000020 ; G2_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO2_ofs EQU 5
TSC_IOHCR_G2_IO2_len EQU 1
TSC_IOHCR_G2_IO3 EQU 0x00000040 ; G2_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO3_ofs EQU 6
TSC_IOHCR_G2_IO3_len EQU 1
TSC_IOHCR_G2_IO4 EQU 0x00000080 ; G2_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO4_ofs EQU 7
TSC_IOHCR_G2_IO4_len EQU 1
TSC_IOHCR_G3_IO1 EQU 0x00000100 ; G3_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO1_ofs EQU 8
TSC_IOHCR_G3_IO1_len EQU 1
TSC_IOHCR_G3_IO2 EQU 0x00000200 ; G3_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO2_ofs EQU 9
TSC_IOHCR_G3_IO2_len EQU 1
TSC_IOHCR_G3_IO3 EQU 0x00000400 ; G3_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO3_ofs EQU 10
TSC_IOHCR_G3_IO3_len EQU 1
TSC_IOHCR_G3_IO4 EQU 0x00000800 ; G3_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO4_ofs EQU 11
TSC_IOHCR_G3_IO4_len EQU 1
TSC_IOHCR_G4_IO1 EQU 0x00001000 ; G4_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO1_ofs EQU 12
TSC_IOHCR_G4_IO1_len EQU 1
TSC_IOHCR_G4_IO2 EQU 0x00002000 ; G4_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO2_ofs EQU 13
TSC_IOHCR_G4_IO2_len EQU 1
TSC_IOHCR_G4_IO3 EQU 0x00004000 ; G4_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO3_ofs EQU 14
TSC_IOHCR_G4_IO3_len EQU 1
TSC_IOHCR_G4_IO4 EQU 0x00008000 ; G4_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO4_ofs EQU 15
TSC_IOHCR_G4_IO4_len EQU 1
TSC_IOHCR_G5_IO1 EQU 0x00010000 ; G5_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO1_ofs EQU 16
TSC_IOHCR_G5_IO1_len EQU 1
TSC_IOHCR_G5_IO2 EQU 0x00020000 ; G5_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO2_ofs EQU 17
TSC_IOHCR_G5_IO2_len EQU 1
TSC_IOHCR_G5_IO3 EQU 0x00040000 ; G5_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO3_ofs EQU 18
TSC_IOHCR_G5_IO3_len EQU 1
TSC_IOHCR_G5_IO4 EQU 0x00080000 ; G5_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO4_ofs EQU 19
TSC_IOHCR_G5_IO4_len EQU 1
TSC_IOHCR_G6_IO1 EQU 0x00100000 ; G6_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO1_ofs EQU 20
TSC_IOHCR_G6_IO1_len EQU 1
TSC_IOHCR_G6_IO2 EQU 0x00200000 ; G6_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO2_ofs EQU 21
TSC_IOHCR_G6_IO2_len EQU 1
TSC_IOHCR_G6_IO3 EQU 0x00400000 ; G6_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO3_ofs EQU 22
TSC_IOHCR_G6_IO3_len EQU 1
TSC_IOHCR_G6_IO4 EQU 0x00800000 ; G6_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO4_ofs EQU 23
TSC_IOHCR_G6_IO4_len EQU 1
TSC_IOHCR_G7_IO1 EQU 0x01000000 ; G7_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO1_ofs EQU 24
TSC_IOHCR_G7_IO1_len EQU 1
TSC_IOHCR_G7_IO2 EQU 0x02000000 ; G7_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO2_ofs EQU 25
TSC_IOHCR_G7_IO2_len EQU 1
TSC_IOHCR_G7_IO3 EQU 0x04000000 ; G7_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO3_ofs EQU 26
TSC_IOHCR_G7_IO3_len EQU 1
TSC_IOHCR_G7_IO4 EQU 0x08000000 ; G7_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO4_ofs EQU 27
TSC_IOHCR_G7_IO4_len EQU 1
TSC_IOHCR_G8_IO1 EQU 0x10000000 ; G8_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO1_ofs EQU 28
TSC_IOHCR_G8_IO1_len EQU 1
TSC_IOHCR_G8_IO2 EQU 0x20000000 ; G8_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO2_ofs EQU 29
TSC_IOHCR_G8_IO2_len EQU 1
TSC_IOHCR_G8_IO3 EQU 0x40000000 ; G8_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO3_ofs EQU 30
TSC_IOHCR_G8_IO3_len EQU 1
TSC_IOHCR_G8_IO4 EQU 0x80000000 ; G8_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO4_ofs EQU 31
TSC_IOHCR_G8_IO4_len EQU 1
; TSC_IOASCR fields:
TSC_IOASCR_G1_IO1 EQU 0x00000001 ; G1_IO1 analog switch enable
TSC_IOASCR_G1_IO1_ofs EQU 0
TSC_IOASCR_G1_IO1_len EQU 1
TSC_IOASCR_G1_IO2 EQU 0x00000002 ; G1_IO2 analog switch enable
TSC_IOASCR_G1_IO2_ofs EQU 1
TSC_IOASCR_G1_IO2_len EQU 1
TSC_IOASCR_G1_IO3 EQU 0x00000004 ; G1_IO3 analog switch enable
TSC_IOASCR_G1_IO3_ofs EQU 2
TSC_IOASCR_G1_IO3_len EQU 1
TSC_IOASCR_G1_IO4 EQU 0x00000008 ; G1_IO4 analog switch enable
TSC_IOASCR_G1_IO4_ofs EQU 3
TSC_IOASCR_G1_IO4_len EQU 1
TSC_IOASCR_G2_IO1 EQU 0x00000010 ; G2_IO1 analog switch enable
TSC_IOASCR_G2_IO1_ofs EQU 4
TSC_IOASCR_G2_IO1_len EQU 1
TSC_IOASCR_G2_IO2 EQU 0x00000020 ; G2_IO2 analog switch enable
TSC_IOASCR_G2_IO2_ofs EQU 5
TSC_IOASCR_G2_IO2_len EQU 1
TSC_IOASCR_G2_IO3 EQU 0x00000040 ; G2_IO3 analog switch enable
TSC_IOASCR_G2_IO3_ofs EQU 6
TSC_IOASCR_G2_IO3_len EQU 1
TSC_IOASCR_G2_IO4 EQU 0x00000080 ; G2_IO4 analog switch enable
TSC_IOASCR_G2_IO4_ofs EQU 7
TSC_IOASCR_G2_IO4_len EQU 1
TSC_IOASCR_G3_IO1 EQU 0x00000100 ; G3_IO1 analog switch enable
TSC_IOASCR_G3_IO1_ofs EQU 8
TSC_IOASCR_G3_IO1_len EQU 1
TSC_IOASCR_G3_IO2 EQU 0x00000200 ; G3_IO2 analog switch enable
TSC_IOASCR_G3_IO2_ofs EQU 9
TSC_IOASCR_G3_IO2_len EQU 1
TSC_IOASCR_G3_IO3 EQU 0x00000400 ; G3_IO3 analog switch enable
TSC_IOASCR_G3_IO3_ofs EQU 10
TSC_IOASCR_G3_IO3_len EQU 1
TSC_IOASCR_G3_IO4 EQU 0x00000800 ; G3_IO4 analog switch enable
TSC_IOASCR_G3_IO4_ofs EQU 11
TSC_IOASCR_G3_IO4_len EQU 1
TSC_IOASCR_G4_IO1 EQU 0x00001000 ; G4_IO1 analog switch enable
TSC_IOASCR_G4_IO1_ofs EQU 12
TSC_IOASCR_G4_IO1_len EQU 1
TSC_IOASCR_G4_IO2 EQU 0x00002000 ; G4_IO2 analog switch enable
TSC_IOASCR_G4_IO2_ofs EQU 13
TSC_IOASCR_G4_IO2_len EQU 1
TSC_IOASCR_G4_IO3 EQU 0x00004000 ; G4_IO3 analog switch enable
TSC_IOASCR_G4_IO3_ofs EQU 14
TSC_IOASCR_G4_IO3_len EQU 1
TSC_IOASCR_G4_IO4 EQU 0x00008000 ; G4_IO4 analog switch enable
TSC_IOASCR_G4_IO4_ofs EQU 15
TSC_IOASCR_G4_IO4_len EQU 1
TSC_IOASCR_G5_IO1 EQU 0x00010000 ; G5_IO1 analog switch enable
TSC_IOASCR_G5_IO1_ofs EQU 16
TSC_IOASCR_G5_IO1_len EQU 1
TSC_IOASCR_G5_IO2 EQU 0x00020000 ; G5_IO2 analog switch enable
TSC_IOASCR_G5_IO2_ofs EQU 17
TSC_IOASCR_G5_IO2_len EQU 1
TSC_IOASCR_G5_IO3 EQU 0x00040000 ; G5_IO3 analog switch enable
TSC_IOASCR_G5_IO3_ofs EQU 18
TSC_IOASCR_G5_IO3_len EQU 1
TSC_IOASCR_G5_IO4 EQU 0x00080000 ; G5_IO4 analog switch enable
TSC_IOASCR_G5_IO4_ofs EQU 19
TSC_IOASCR_G5_IO4_len EQU 1
TSC_IOASCR_G6_IO1 EQU 0x00100000 ; G6_IO1 analog switch enable
TSC_IOASCR_G6_IO1_ofs EQU 20
TSC_IOASCR_G6_IO1_len EQU 1
TSC_IOASCR_G6_IO2 EQU 0x00200000 ; G6_IO2 analog switch enable
TSC_IOASCR_G6_IO2_ofs EQU 21
TSC_IOASCR_G6_IO2_len EQU 1
TSC_IOASCR_G6_IO3 EQU 0x00400000 ; G6_IO3 analog switch enable
TSC_IOASCR_G6_IO3_ofs EQU 22
TSC_IOASCR_G6_IO3_len EQU 1
TSC_IOASCR_G6_IO4 EQU 0x00800000 ; G6_IO4 analog switch enable
TSC_IOASCR_G6_IO4_ofs EQU 23
TSC_IOASCR_G6_IO4_len EQU 1
TSC_IOASCR_G7_IO1 EQU 0x01000000 ; G7_IO1 analog switch enable
TSC_IOASCR_G7_IO1_ofs EQU 24
TSC_IOASCR_G7_IO1_len EQU 1
TSC_IOASCR_G7_IO2 EQU 0x02000000 ; G7_IO2 analog switch enable
TSC_IOASCR_G7_IO2_ofs EQU 25
TSC_IOASCR_G7_IO2_len EQU 1
TSC_IOASCR_G7_IO3 EQU 0x04000000 ; G7_IO3 analog switch enable
TSC_IOASCR_G7_IO3_ofs EQU 26
TSC_IOASCR_G7_IO3_len EQU 1
TSC_IOASCR_G7_IO4 EQU 0x08000000 ; G7_IO4 analog switch enable
TSC_IOASCR_G7_IO4_ofs EQU 27
TSC_IOASCR_G7_IO4_len EQU 1
TSC_IOASCR_G8_IO1 EQU 0x10000000 ; G8_IO1 analog switch enable
TSC_IOASCR_G8_IO1_ofs EQU 28
TSC_IOASCR_G8_IO1_len EQU 1
TSC_IOASCR_G8_IO2 EQU 0x20000000 ; G8_IO2 analog switch enable
TSC_IOASCR_G8_IO2_ofs EQU 29
TSC_IOASCR_G8_IO2_len EQU 1
TSC_IOASCR_G8_IO3 EQU 0x40000000 ; G8_IO3 analog switch enable
TSC_IOASCR_G8_IO3_ofs EQU 30
TSC_IOASCR_G8_IO3_len EQU 1
TSC_IOASCR_G8_IO4 EQU 0x80000000 ; G8_IO4 analog switch enable
TSC_IOASCR_G8_IO4_ofs EQU 31
TSC_IOASCR_G8_IO4_len EQU 1
; TSC_IOSCR fields:
TSC_IOSCR_G1_IO1 EQU 0x00000001 ; G1_IO1 sampling mode
TSC_IOSCR_G1_IO1_ofs EQU 0
TSC_IOSCR_G1_IO1_len EQU 1
TSC_IOSCR_G1_IO2 EQU 0x00000002 ; G1_IO2 sampling mode
TSC_IOSCR_G1_IO2_ofs EQU 1
TSC_IOSCR_G1_IO2_len EQU 1
TSC_IOSCR_G1_IO3 EQU 0x00000004 ; G1_IO3 sampling mode
TSC_IOSCR_G1_IO3_ofs EQU 2
TSC_IOSCR_G1_IO3_len EQU 1
TSC_IOSCR_G1_IO4 EQU 0x00000008 ; G1_IO4 sampling mode
TSC_IOSCR_G1_IO4_ofs EQU 3
TSC_IOSCR_G1_IO4_len EQU 1
TSC_IOSCR_G2_IO1 EQU 0x00000010 ; G2_IO1 sampling mode
TSC_IOSCR_G2_IO1_ofs EQU 4
TSC_IOSCR_G2_IO1_len EQU 1
TSC_IOSCR_G2_IO2 EQU 0x00000020 ; G2_IO2 sampling mode
TSC_IOSCR_G2_IO2_ofs EQU 5
TSC_IOSCR_G2_IO2_len EQU 1
TSC_IOSCR_G2_IO3 EQU 0x00000040 ; G2_IO3 sampling mode
TSC_IOSCR_G2_IO3_ofs EQU 6
TSC_IOSCR_G2_IO3_len EQU 1
TSC_IOSCR_G2_IO4 EQU 0x00000080 ; G2_IO4 sampling mode
TSC_IOSCR_G2_IO4_ofs EQU 7
TSC_IOSCR_G2_IO4_len EQU 1
TSC_IOSCR_G3_IO1 EQU 0x00000100 ; G3_IO1 sampling mode
TSC_IOSCR_G3_IO1_ofs EQU 8
TSC_IOSCR_G3_IO1_len EQU 1
TSC_IOSCR_G3_IO2 EQU 0x00000200 ; G3_IO2 sampling mode
TSC_IOSCR_G3_IO2_ofs EQU 9
TSC_IOSCR_G3_IO2_len EQU 1
TSC_IOSCR_G3_IO3 EQU 0x00000400 ; G3_IO3 sampling mode
TSC_IOSCR_G3_IO3_ofs EQU 10
TSC_IOSCR_G3_IO3_len EQU 1
TSC_IOSCR_G3_IO4 EQU 0x00000800 ; G3_IO4 sampling mode
TSC_IOSCR_G3_IO4_ofs EQU 11
TSC_IOSCR_G3_IO4_len EQU 1
TSC_IOSCR_G4_IO1 EQU 0x00001000 ; G4_IO1 sampling mode
TSC_IOSCR_G4_IO1_ofs EQU 12
TSC_IOSCR_G4_IO1_len EQU 1
TSC_IOSCR_G4_IO2 EQU 0x00002000 ; G4_IO2 sampling mode
TSC_IOSCR_G4_IO2_ofs EQU 13
TSC_IOSCR_G4_IO2_len EQU 1
TSC_IOSCR_G4_IO3 EQU 0x00004000 ; G4_IO3 sampling mode
TSC_IOSCR_G4_IO3_ofs EQU 14
TSC_IOSCR_G4_IO3_len EQU 1
TSC_IOSCR_G4_IO4 EQU 0x00008000 ; G4_IO4 sampling mode
TSC_IOSCR_G4_IO4_ofs EQU 15
TSC_IOSCR_G4_IO4_len EQU 1
TSC_IOSCR_G5_IO1 EQU 0x00010000 ; G5_IO1 sampling mode
TSC_IOSCR_G5_IO1_ofs EQU 16
TSC_IOSCR_G5_IO1_len EQU 1
TSC_IOSCR_G5_IO2 EQU 0x00020000 ; G5_IO2 sampling mode
TSC_IOSCR_G5_IO2_ofs EQU 17
TSC_IOSCR_G5_IO2_len EQU 1
TSC_IOSCR_G5_IO3 EQU 0x00040000 ; G5_IO3 sampling mode
TSC_IOSCR_G5_IO3_ofs EQU 18
TSC_IOSCR_G5_IO3_len EQU 1
TSC_IOSCR_G5_IO4 EQU 0x00080000 ; G5_IO4 sampling mode
TSC_IOSCR_G5_IO4_ofs EQU 19
TSC_IOSCR_G5_IO4_len EQU 1
TSC_IOSCR_G6_IO1 EQU 0x00100000 ; G6_IO1 sampling mode
TSC_IOSCR_G6_IO1_ofs EQU 20
TSC_IOSCR_G6_IO1_len EQU 1
TSC_IOSCR_G6_IO2 EQU 0x00200000 ; G6_IO2 sampling mode
TSC_IOSCR_G6_IO2_ofs EQU 21
TSC_IOSCR_G6_IO2_len EQU 1
TSC_IOSCR_G6_IO3 EQU 0x00400000 ; G6_IO3 sampling mode
TSC_IOSCR_G6_IO3_ofs EQU 22
TSC_IOSCR_G6_IO3_len EQU 1
TSC_IOSCR_G6_IO4 EQU 0x00800000 ; G6_IO4 sampling mode
TSC_IOSCR_G6_IO4_ofs EQU 23
TSC_IOSCR_G6_IO4_len EQU 1
TSC_IOSCR_G7_IO1 EQU 0x01000000 ; G7_IO1 sampling mode
TSC_IOSCR_G7_IO1_ofs EQU 24
TSC_IOSCR_G7_IO1_len EQU 1
TSC_IOSCR_G7_IO2 EQU 0x02000000 ; G7_IO2 sampling mode
TSC_IOSCR_G7_IO2_ofs EQU 25
TSC_IOSCR_G7_IO2_len EQU 1
TSC_IOSCR_G7_IO3 EQU 0x04000000 ; G7_IO3 sampling mode
TSC_IOSCR_G7_IO3_ofs EQU 26
TSC_IOSCR_G7_IO3_len EQU 1
TSC_IOSCR_G7_IO4 EQU 0x08000000 ; G7_IO4 sampling mode
TSC_IOSCR_G7_IO4_ofs EQU 27
TSC_IOSCR_G7_IO4_len EQU 1
TSC_IOSCR_G8_IO1 EQU 0x10000000 ; G8_IO1 sampling mode
TSC_IOSCR_G8_IO1_ofs EQU 28
TSC_IOSCR_G8_IO1_len EQU 1
TSC_IOSCR_G8_IO2 EQU 0x20000000 ; G8_IO2 sampling mode
TSC_IOSCR_G8_IO2_ofs EQU 29
TSC_IOSCR_G8_IO2_len EQU 1
TSC_IOSCR_G8_IO3 EQU 0x40000000 ; G8_IO3 sampling mode
TSC_IOSCR_G8_IO3_ofs EQU 30
TSC_IOSCR_G8_IO3_len EQU 1
TSC_IOSCR_G8_IO4 EQU 0x80000000 ; G8_IO4 sampling mode
TSC_IOSCR_G8_IO4_ofs EQU 31
TSC_IOSCR_G8_IO4_len EQU 1
; TSC_IOCCR fields:
TSC_IOCCR_G1_IO1 EQU 0x00000001 ; G1_IO1 channel mode
TSC_IOCCR_G1_IO1_ofs EQU 0
TSC_IOCCR_G1_IO1_len EQU 1
TSC_IOCCR_G1_IO2 EQU 0x00000002 ; G1_IO2 channel mode
TSC_IOCCR_G1_IO2_ofs EQU 1
TSC_IOCCR_G1_IO2_len EQU 1
TSC_IOCCR_G1_IO3 EQU 0x00000004 ; G1_IO3 channel mode
TSC_IOCCR_G1_IO3_ofs EQU 2
TSC_IOCCR_G1_IO3_len EQU 1
TSC_IOCCR_G1_IO4 EQU 0x00000008 ; G1_IO4 channel mode
TSC_IOCCR_G1_IO4_ofs EQU 3
TSC_IOCCR_G1_IO4_len EQU 1
TSC_IOCCR_G2_IO1 EQU 0x00000010 ; G2_IO1 channel mode
TSC_IOCCR_G2_IO1_ofs EQU 4
TSC_IOCCR_G2_IO1_len EQU 1
TSC_IOCCR_G2_IO2 EQU 0x00000020 ; G2_IO2 channel mode
TSC_IOCCR_G2_IO2_ofs EQU 5
TSC_IOCCR_G2_IO2_len EQU 1
TSC_IOCCR_G2_IO3 EQU 0x00000040 ; G2_IO3 channel mode
TSC_IOCCR_G2_IO3_ofs EQU 6
TSC_IOCCR_G2_IO3_len EQU 1
TSC_IOCCR_G2_IO4 EQU 0x00000080 ; G2_IO4 channel mode
TSC_IOCCR_G2_IO4_ofs EQU 7
TSC_IOCCR_G2_IO4_len EQU 1
TSC_IOCCR_G3_IO1 EQU 0x00000100 ; G3_IO1 channel mode
TSC_IOCCR_G3_IO1_ofs EQU 8
TSC_IOCCR_G3_IO1_len EQU 1
TSC_IOCCR_G3_IO2 EQU 0x00000200 ; G3_IO2 channel mode
TSC_IOCCR_G3_IO2_ofs EQU 9
TSC_IOCCR_G3_IO2_len EQU 1
TSC_IOCCR_G3_IO3 EQU 0x00000400 ; G3_IO3 channel mode
TSC_IOCCR_G3_IO3_ofs EQU 10
TSC_IOCCR_G3_IO3_len EQU 1
TSC_IOCCR_G3_IO4 EQU 0x00000800 ; G3_IO4 channel mode
TSC_IOCCR_G3_IO4_ofs EQU 11
TSC_IOCCR_G3_IO4_len EQU 1
TSC_IOCCR_G4_IO1 EQU 0x00001000 ; G4_IO1 channel mode
TSC_IOCCR_G4_IO1_ofs EQU 12
TSC_IOCCR_G4_IO1_len EQU 1
TSC_IOCCR_G4_IO2 EQU 0x00002000 ; G4_IO2 channel mode
TSC_IOCCR_G4_IO2_ofs EQU 13
TSC_IOCCR_G4_IO2_len EQU 1
TSC_IOCCR_G4_IO3 EQU 0x00004000 ; G4_IO3 channel mode
TSC_IOCCR_G4_IO3_ofs EQU 14
TSC_IOCCR_G4_IO3_len EQU 1
TSC_IOCCR_G4_IO4 EQU 0x00008000 ; G4_IO4 channel mode
TSC_IOCCR_G4_IO4_ofs EQU 15
TSC_IOCCR_G4_IO4_len EQU 1
TSC_IOCCR_G5_IO1 EQU 0x00010000 ; G5_IO1 channel mode
TSC_IOCCR_G5_IO1_ofs EQU 16
TSC_IOCCR_G5_IO1_len EQU 1
TSC_IOCCR_G5_IO2 EQU 0x00020000 ; G5_IO2 channel mode
TSC_IOCCR_G5_IO2_ofs EQU 17
TSC_IOCCR_G5_IO2_len EQU 1
TSC_IOCCR_G5_IO3 EQU 0x00040000 ; G5_IO3 channel mode
TSC_IOCCR_G5_IO3_ofs EQU 18
TSC_IOCCR_G5_IO3_len EQU 1
TSC_IOCCR_G5_IO4 EQU 0x00080000 ; G5_IO4 channel mode
TSC_IOCCR_G5_IO4_ofs EQU 19
TSC_IOCCR_G5_IO4_len EQU 1
TSC_IOCCR_G6_IO1 EQU 0x00100000 ; G6_IO1 channel mode
TSC_IOCCR_G6_IO1_ofs EQU 20
TSC_IOCCR_G6_IO1_len EQU 1
TSC_IOCCR_G6_IO2 EQU 0x00200000 ; G6_IO2 channel mode
TSC_IOCCR_G6_IO2_ofs EQU 21
TSC_IOCCR_G6_IO2_len EQU 1
TSC_IOCCR_G6_IO3 EQU 0x00400000 ; G6_IO3 channel mode
TSC_IOCCR_G6_IO3_ofs EQU 22
TSC_IOCCR_G6_IO3_len EQU 1
TSC_IOCCR_G6_IO4 EQU 0x00800000 ; G6_IO4 channel mode
TSC_IOCCR_G6_IO4_ofs EQU 23
TSC_IOCCR_G6_IO4_len EQU 1
TSC_IOCCR_G7_IO1 EQU 0x01000000 ; G7_IO1 channel mode
TSC_IOCCR_G7_IO1_ofs EQU 24
TSC_IOCCR_G7_IO1_len EQU 1
TSC_IOCCR_G7_IO2 EQU 0x02000000 ; G7_IO2 channel mode
TSC_IOCCR_G7_IO2_ofs EQU 25
TSC_IOCCR_G7_IO2_len EQU 1
TSC_IOCCR_G7_IO3 EQU 0x04000000 ; G7_IO3 channel mode
TSC_IOCCR_G7_IO3_ofs EQU 26
TSC_IOCCR_G7_IO3_len EQU 1
TSC_IOCCR_G7_IO4 EQU 0x08000000 ; G7_IO4 channel mode
TSC_IOCCR_G7_IO4_ofs EQU 27
TSC_IOCCR_G7_IO4_len EQU 1
TSC_IOCCR_G8_IO1 EQU 0x10000000 ; G8_IO1 channel mode
TSC_IOCCR_G8_IO1_ofs EQU 28
TSC_IOCCR_G8_IO1_len EQU 1
TSC_IOCCR_G8_IO2 EQU 0x20000000 ; G8_IO2 channel mode
TSC_IOCCR_G8_IO2_ofs EQU 29
TSC_IOCCR_G8_IO2_len EQU 1
TSC_IOCCR_G8_IO3 EQU 0x40000000 ; G8_IO3 channel mode
TSC_IOCCR_G8_IO3_ofs EQU 30
TSC_IOCCR_G8_IO3_len EQU 1
TSC_IOCCR_G8_IO4 EQU 0x80000000 ; G8_IO4 channel mode
TSC_IOCCR_G8_IO4_ofs EQU 31
TSC_IOCCR_G8_IO4_len EQU 1
; TSC_IOGCSR fields:
TSC_IOGCSR_G8S EQU 0x00800000 ; Analog I/O group x status
TSC_IOGCSR_G8S_ofs EQU 23
TSC_IOGCSR_G8S_len EQU 1
TSC_IOGCSR_G7S EQU 0x00400000 ; Analog I/O group x status
TSC_IOGCSR_G7S_ofs EQU 22
TSC_IOGCSR_G7S_len EQU 1
TSC_IOGCSR_G6S EQU 0x00200000 ; Analog I/O group x status
TSC_IOGCSR_G6S_ofs EQU 21
TSC_IOGCSR_G6S_len EQU 1
TSC_IOGCSR_G5S EQU 0x00100000 ; Analog I/O group x status
TSC_IOGCSR_G5S_ofs EQU 20
TSC_IOGCSR_G5S_len EQU 1
TSC_IOGCSR_G4S EQU 0x00080000 ; Analog I/O group x status
TSC_IOGCSR_G4S_ofs EQU 19
TSC_IOGCSR_G4S_len EQU 1
TSC_IOGCSR_G3S EQU 0x00040000 ; Analog I/O group x status
TSC_IOGCSR_G3S_ofs EQU 18
TSC_IOGCSR_G3S_len EQU 1
TSC_IOGCSR_G2S EQU 0x00020000 ; Analog I/O group x status
TSC_IOGCSR_G2S_ofs EQU 17
TSC_IOGCSR_G2S_len EQU 1
TSC_IOGCSR_G1S EQU 0x00010000 ; Analog I/O group x status
TSC_IOGCSR_G1S_ofs EQU 16
TSC_IOGCSR_G1S_len EQU 1
TSC_IOGCSR_G8E EQU 0x00000080 ; Analog I/O group x enable
TSC_IOGCSR_G8E_ofs EQU 7
TSC_IOGCSR_G8E_len EQU 1
TSC_IOGCSR_G7E EQU 0x00000040 ; Analog I/O group x enable
TSC_IOGCSR_G7E_ofs EQU 6
TSC_IOGCSR_G7E_len EQU 1
TSC_IOGCSR_G6E EQU 0x00000020 ; Analog I/O group x enable
TSC_IOGCSR_G6E_ofs EQU 5
TSC_IOGCSR_G6E_len EQU 1
TSC_IOGCSR_G5E EQU 0x00000010 ; Analog I/O group x enable
TSC_IOGCSR_G5E_ofs EQU 4
TSC_IOGCSR_G5E_len EQU 1
TSC_IOGCSR_G4E EQU 0x00000008 ; Analog I/O group x enable
TSC_IOGCSR_G4E_ofs EQU 3
TSC_IOGCSR_G4E_len EQU 1
TSC_IOGCSR_G3E EQU 0x00000004 ; Analog I/O group x enable
TSC_IOGCSR_G3E_ofs EQU 2
TSC_IOGCSR_G3E_len EQU 1
TSC_IOGCSR_G2E EQU 0x00000002 ; Analog I/O group x enable
TSC_IOGCSR_G2E_ofs EQU 1
TSC_IOGCSR_G2E_len EQU 1
TSC_IOGCSR_G1E EQU 0x00000001 ; Analog I/O group x enable
TSC_IOGCSR_G1E_ofs EQU 0
TSC_IOGCSR_G1E_len EQU 1
; TSC_IOG1CR fields:
TSC_IOG1CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG1CR_CNT_ofs EQU 0
TSC_IOG1CR_CNT_len EQU 14
; TSC_IOG2CR fields:
TSC_IOG2CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG2CR_CNT_ofs EQU 0
TSC_IOG2CR_CNT_len EQU 14
; TSC_IOG3CR fields:
TSC_IOG3CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG3CR_CNT_ofs EQU 0
TSC_IOG3CR_CNT_len EQU 14
; TSC_IOG4CR fields:
TSC_IOG4CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG4CR_CNT_ofs EQU 0
TSC_IOG4CR_CNT_len EQU 14
; TSC_IOG5CR fields:
TSC_IOG5CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG5CR_CNT_ofs EQU 0
TSC_IOG5CR_CNT_len EQU 14
; TSC_IOG6CR fields:
TSC_IOG6CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG6CR_CNT_ofs EQU 0
TSC_IOG6CR_CNT_len EQU 14
; TSC_IOG7CR fields:
TSC_IOG7CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG7CR_CNT_ofs EQU 0
TSC_IOG7CR_CNT_len EQU 14
; TSC_IOG8CR fields:
TSC_IOG8CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG8CR_CNT_ofs EQU 0
TSC_IOG8CR_CNT_len EQU 14
; ---- CRC ---------------------------------------------------
; Desc: cyclic redundancy check calculation unit
; CRC base address:
CRC_BASE EQU 0x40023000
; CRC registers:
CRC_DR EQU (CRC_BASE + 0x0) ; Data register
CRC_IDR EQU (CRC_BASE + 0x4) ; Independent data register
CRC_CR EQU (CRC_BASE + 0x8) ; Control register
CRC_INIT EQU (CRC_BASE + 0x10) ; Initial CRC value
CRC_POL EQU (CRC_BASE + 0x14) ; CRC polynomial
; CRC_DR fields:
CRC_DR_DR EQU 0xffffffff ; Data register bits
CRC_DR_DR_ofs EQU 0
CRC_DR_DR_len EQU 32
; CRC_IDR fields:
CRC_IDR_IDR EQU 0x000000ff ; General-purpose 8-bit data register bits
CRC_IDR_IDR_ofs EQU 0
CRC_IDR_IDR_len EQU 8
; CRC_CR fields:
CRC_CR_RESET EQU 0x00000001 ; reset bit
CRC_CR_RESET_ofs EQU 0
CRC_CR_RESET_len EQU 1
CRC_CR_POLYSIZE EQU 0x00000018 ; Polynomial size
CRC_CR_POLYSIZE_ofs EQU 3
CRC_CR_POLYSIZE_len EQU 2
CRC_CR_REV_IN EQU 0x00000060 ; Reverse input data
CRC_CR_REV_IN_ofs EQU 5
CRC_CR_REV_IN_len EQU 2
CRC_CR_REV_OUT EQU 0x00000080 ; Reverse output data
CRC_CR_REV_OUT_ofs EQU 7
CRC_CR_REV_OUT_len EQU 1
; CRC_INIT fields:
CRC_INIT_INIT EQU 0xffffffff ; Programmable initial CRC value
CRC_INIT_INIT_ofs EQU 0
CRC_INIT_INIT_len EQU 32
; CRC_POL fields:
CRC_POL_POL EQU 0xffffffff ; Programmable polynomial
CRC_POL_POL_ofs EQU 0
CRC_POL_POL_len EQU 32
; ---- Flash -------------------------------------------------
; Desc: Flash
; Flash base address:
FLASH_BASE EQU 0x40022000
; Flash registers:
FLASH_ACR EQU (FLASH_BASE + 0x0) ; Flash access control register
FLASH_KEYR EQU (FLASH_BASE + 0x4) ; Flash key register
FLASH_OPTKEYR EQU (FLASH_BASE + 0x8) ; Flash option key register
FLASH_SR EQU (FLASH_BASE + 0xc) ; Flash status register
FLASH_CR EQU (FLASH_BASE + 0x10) ; Flash control register
FLASH_AR EQU (FLASH_BASE + 0x14) ; Flash address register
FLASH_OBR EQU (FLASH_BASE + 0x1c) ; Option byte register
FLASH_WRPR EQU (FLASH_BASE + 0x20) ; Write protection register
; FLASH_ACR fields:
FLASH_ACR_LATENCY EQU 0x00000007 ; LATENCY
FLASH_ACR_LATENCY_ofs EQU 0
FLASH_ACR_LATENCY_len EQU 3
FLASH_ACR_PRFTBE EQU 0x00000010 ; PRFTBE
FLASH_ACR_PRFTBE_ofs EQU 4
FLASH_ACR_PRFTBE_len EQU 1
FLASH_ACR_PRFTBS EQU 0x00000020 ; PRFTBS
FLASH_ACR_PRFTBS_ofs EQU 5
FLASH_ACR_PRFTBS_len EQU 1
; FLASH_KEYR fields:
FLASH_KEYR_FKEYR EQU 0xffffffff ; Flash Key
FLASH_KEYR_FKEYR_ofs EQU 0
FLASH_KEYR_FKEYR_len EQU 32
; FLASH_OPTKEYR fields:
FLASH_OPTKEYR_OPTKEYR EQU 0xffffffff ; Option byte key
FLASH_OPTKEYR_OPTKEYR_ofs EQU 0
FLASH_OPTKEYR_OPTKEYR_len EQU 32
; FLASH_SR fields:
FLASH_SR_EOP EQU 0x00000020 ; End of operation
FLASH_SR_EOP_ofs EQU 5
FLASH_SR_EOP_len EQU 1
FLASH_SR_WRPRT EQU 0x00000010 ; Write protection error
FLASH_SR_WRPRT_ofs EQU 4
FLASH_SR_WRPRT_len EQU 1
FLASH_SR_PGERR EQU 0x00000004 ; Programming error
FLASH_SR_PGERR_ofs EQU 2
FLASH_SR_PGERR_len EQU 1
FLASH_SR_BSY EQU 0x00000001 ; Busy
FLASH_SR_BSY_ofs EQU 0
FLASH_SR_BSY_len EQU 1
; FLASH_CR fields:
FLASH_CR_FORCE_OPTLOAD EQU 0x00002000 ; Force option byte loading
FLASH_CR_FORCE_OPTLOAD_ofs EQU 13
FLASH_CR_FORCE_OPTLOAD_len EQU 1
FLASH_CR_EOPIE EQU 0x00001000 ; End of operation interrupt enable
FLASH_CR_EOPIE_ofs EQU 12
FLASH_CR_EOPIE_len EQU 1
FLASH_CR_ERRIE EQU 0x00000400 ; Error interrupt enable
FLASH_CR_ERRIE_ofs EQU 10
FLASH_CR_ERRIE_len EQU 1
FLASH_CR_OPTWRE EQU 0x00000200 ; Option bytes write enable
FLASH_CR_OPTWRE_ofs EQU 9
FLASH_CR_OPTWRE_len EQU 1
FLASH_CR_LOCK EQU 0x00000080 ; Lock
FLASH_CR_LOCK_ofs EQU 7
FLASH_CR_LOCK_len EQU 1
FLASH_CR_STRT EQU 0x00000040 ; Start
FLASH_CR_STRT_ofs EQU 6
FLASH_CR_STRT_len EQU 1
FLASH_CR_OPTER EQU 0x00000020 ; Option byte erase
FLASH_CR_OPTER_ofs EQU 5
FLASH_CR_OPTER_len EQU 1
FLASH_CR_OPTPG EQU 0x00000010 ; Option byte programming
FLASH_CR_OPTPG_ofs EQU 4
FLASH_CR_OPTPG_len EQU 1
FLASH_CR_MER EQU 0x00000004 ; Mass erase
FLASH_CR_MER_ofs EQU 2
FLASH_CR_MER_len EQU 1
FLASH_CR_PER EQU 0x00000002 ; Page erase
FLASH_CR_PER_ofs EQU 1
FLASH_CR_PER_len EQU 1
FLASH_CR_PG EQU 0x00000001 ; Programming
FLASH_CR_PG_ofs EQU 0
FLASH_CR_PG_len EQU 1
; FLASH_AR fields:
FLASH_AR_FAR EQU 0xffffffff ; Flash address
FLASH_AR_FAR_ofs EQU 0
FLASH_AR_FAR_len EQU 32
; FLASH_OBR fields:
FLASH_OBR_OPTERR EQU 0x00000001 ; Option byte error
FLASH_OBR_OPTERR_ofs EQU 0
FLASH_OBR_OPTERR_len EQU 1
FLASH_OBR_LEVEL1_PROT EQU 0x00000002 ; Level 1 protection status
FLASH_OBR_LEVEL1_PROT_ofs EQU 1
FLASH_OBR_LEVEL1_PROT_len EQU 1
FLASH_OBR_LEVEL2_PROT EQU 0x00000004 ; Level 2 protection status
FLASH_OBR_LEVEL2_PROT_ofs EQU 2
FLASH_OBR_LEVEL2_PROT_len EQU 1
FLASH_OBR_WDG_SW EQU 0x00000100 ; WDG_SW
FLASH_OBR_WDG_SW_ofs EQU 8
FLASH_OBR_WDG_SW_len EQU 1
FLASH_OBR_nRST_STOP EQU 0x00000200 ; nRST_STOP
FLASH_OBR_nRST_STOP_ofs EQU 9
FLASH_OBR_nRST_STOP_len EQU 1
FLASH_OBR_nRST_STDBY EQU 0x00000400 ; nRST_STDBY
FLASH_OBR_nRST_STDBY_ofs EQU 10
FLASH_OBR_nRST_STDBY_len EQU 1
FLASH_OBR_BOOT1 EQU 0x00001000 ; BOOT1
FLASH_OBR_BOOT1_ofs EQU 12
FLASH_OBR_BOOT1_len EQU 1
FLASH_OBR_VDDA_MONITOR EQU 0x00002000 ; VDDA_MONITOR
FLASH_OBR_VDDA_MONITOR_ofs EQU 13
FLASH_OBR_VDDA_MONITOR_len EQU 1
FLASH_OBR_SRAM_PARITY_CHECK EQU 0x00004000 ; SRAM_PARITY_CHECK
FLASH_OBR_SRAM_PARITY_CHECK_ofs EQU 14
FLASH_OBR_SRAM_PARITY_CHECK_len EQU 1
FLASH_OBR_Data0 EQU 0x00ff0000 ; Data0
FLASH_OBR_Data0_ofs EQU 16
FLASH_OBR_Data0_len EQU 8
FLASH_OBR_Data1 EQU 0xff000000 ; Data1
FLASH_OBR_Data1_ofs EQU 24
FLASH_OBR_Data1_len EQU 8
; FLASH_WRPR fields:
FLASH_WRPR_WRP EQU 0xffffffff ; Write protect
FLASH_WRPR_WRP_ofs EQU 0
FLASH_WRPR_WRP_len EQU 32
; ---- RCC ---------------------------------------------------
; Desc: Reset and clock control
; RCC base address:
RCC_BASE EQU 0x40021000
; RCC registers:
RCC_CR EQU (RCC_BASE + 0x0) ; Clock control register
RCC_CFGR EQU (RCC_BASE + 0x4) ; Clock configuration register (RCC_CFGR)
RCC_CIR EQU (RCC_BASE + 0x8) ; Clock interrupt register (RCC_CIR)
RCC_APB2RSTR EQU (RCC_BASE + 0xc) ; APB2 peripheral reset register (RCC_APB2RSTR)
RCC_APB1RSTR EQU (RCC_BASE + 0x10) ; APB1 peripheral reset register (RCC_APB1RSTR)
RCC_AHBENR EQU (RCC_BASE + 0x14) ; AHB Peripheral Clock enable register (RCC_AHBENR)
RCC_APB2ENR EQU (RCC_BASE + 0x18) ; APB2 peripheral clock enable register (RCC_APB2ENR)
RCC_APB1ENR EQU (RCC_BASE + 0x1c) ; APB1 peripheral clock enable register (RCC_APB1ENR)
RCC_BDCR EQU (RCC_BASE + 0x20) ; Backup domain control register (RCC_BDCR)
RCC_CSR EQU (RCC_BASE + 0x24) ; Control/status register (RCC_CSR)
RCC_AHBRSTR EQU (RCC_BASE + 0x28) ; AHB peripheral reset register
RCC_CFGR2 EQU (RCC_BASE + 0x2c) ; Clock configuration register 2
RCC_CFGR3 EQU (RCC_BASE + 0x30) ; Clock configuration register 3
; RCC_CR fields:
RCC_CR_HSION EQU 0x00000001 ; Internal High Speed clock enable
RCC_CR_HSION_ofs EQU 0
RCC_CR_HSION_len EQU 1
RCC_CR_HSIRDY EQU 0x00000002 ; Internal High Speed clock ready flag
RCC_CR_HSIRDY_ofs EQU 1
RCC_CR_HSIRDY_len EQU 1
RCC_CR_HSITRIM EQU 0x000000f8 ; Internal High Speed clock trimming
RCC_CR_HSITRIM_ofs EQU 3
RCC_CR_HSITRIM_len EQU 5
RCC_CR_HSICAL EQU 0x0000ff00 ; Internal High Speed clock Calibration
RCC_CR_HSICAL_ofs EQU 8
RCC_CR_HSICAL_len EQU 8
RCC_CR_HSEON EQU 0x00010000 ; External High Speed clock enable
RCC_CR_HSEON_ofs EQU 16
RCC_CR_HSEON_len EQU 1
RCC_CR_HSERDY EQU 0x00020000 ; External High Speed clock ready flag
RCC_CR_HSERDY_ofs EQU 17
RCC_CR_HSERDY_len EQU 1
RCC_CR_HSEBYP EQU 0x00040000 ; External High Speed clock Bypass
RCC_CR_HSEBYP_ofs EQU 18
RCC_CR_HSEBYP_len EQU 1
RCC_CR_CSSON EQU 0x00080000 ; Clock Security System enable
RCC_CR_CSSON_ofs EQU 19
RCC_CR_CSSON_len EQU 1
RCC_CR_PLLON EQU 0x01000000 ; PLL enable
RCC_CR_PLLON_ofs EQU 24
RCC_CR_PLLON_len EQU 1
RCC_CR_PLLRDY EQU 0x02000000 ; PLL clock ready flag
RCC_CR_PLLRDY_ofs EQU 25
RCC_CR_PLLRDY_len EQU 1
; RCC_CFGR fields:
RCC_CFGR_SW EQU 0x00000003 ; System clock Switch
RCC_CFGR_SW_ofs EQU 0
RCC_CFGR_SW_len EQU 2
RCC_CFGR_SWS EQU 0x0000000c ; System Clock Switch Status
RCC_CFGR_SWS_ofs EQU 2
RCC_CFGR_SWS_len EQU 2
RCC_CFGR_HPRE EQU 0x000000f0 ; AHB prescaler
RCC_CFGR_HPRE_ofs EQU 4
RCC_CFGR_HPRE_len EQU 4
RCC_CFGR_PPRE1 EQU 0x00000700 ; APB Low speed prescaler (APB1)
RCC_CFGR_PPRE1_ofs EQU 8
RCC_CFGR_PPRE1_len EQU 3
RCC_CFGR_PPRE2 EQU 0x00003800 ; APB high speed prescaler (APB2)
RCC_CFGR_PPRE2_ofs EQU 11
RCC_CFGR_PPRE2_len EQU 3
RCC_CFGR_PLLSRC EQU 0x00010000 ; PLL entry clock source
RCC_CFGR_PLLSRC_ofs EQU 16
RCC_CFGR_PLLSRC_len EQU 1
RCC_CFGR_PLLXTPRE EQU 0x00020000 ; HSE divider for PLL entry
RCC_CFGR_PLLXTPRE_ofs EQU 17
RCC_CFGR_PLLXTPRE_len EQU 1
RCC_CFGR_PLLMUL EQU 0x003c0000 ; PLL Multiplication Factor
RCC_CFGR_PLLMUL_ofs EQU 18
RCC_CFGR_PLLMUL_len EQU 4
RCC_CFGR_USBPRES EQU 0x00400000 ; USB prescaler
RCC_CFGR_USBPRES_ofs EQU 22
RCC_CFGR_USBPRES_len EQU 1
RCC_CFGR_MCO EQU 0x07000000 ; Microcontroller clock output
RCC_CFGR_MCO_ofs EQU 24
RCC_CFGR_MCO_len EQU 3
RCC_CFGR_MCOF EQU 0x10000000 ; Microcontroller Clock Output Flag
RCC_CFGR_MCOF_ofs EQU 28
RCC_CFGR_MCOF_len EQU 1
RCC_CFGR_I2SSRC EQU 0x00800000 ; I2S external clock source selection
RCC_CFGR_I2SSRC_ofs EQU 23
RCC_CFGR_I2SSRC_len EQU 1
; RCC_CIR fields:
RCC_CIR_LSIRDYF EQU 0x00000001 ; LSI Ready Interrupt flag
RCC_CIR_LSIRDYF_ofs EQU 0
RCC_CIR_LSIRDYF_len EQU 1
RCC_CIR_LSERDYF EQU 0x00000002 ; LSE Ready Interrupt flag
RCC_CIR_LSERDYF_ofs EQU 1
RCC_CIR_LSERDYF_len EQU 1
RCC_CIR_HSIRDYF EQU 0x00000004 ; HSI Ready Interrupt flag
RCC_CIR_HSIRDYF_ofs EQU 2
RCC_CIR_HSIRDYF_len EQU 1
RCC_CIR_HSERDYF EQU 0x00000008 ; HSE Ready Interrupt flag
RCC_CIR_HSERDYF_ofs EQU 3
RCC_CIR_HSERDYF_len EQU 1
RCC_CIR_PLLRDYF EQU 0x00000010 ; PLL Ready Interrupt flag
RCC_CIR_PLLRDYF_ofs EQU 4
RCC_CIR_PLLRDYF_len EQU 1
RCC_CIR_CSSF EQU 0x00000080 ; Clock Security System Interrupt flag
RCC_CIR_CSSF_ofs EQU 7
RCC_CIR_CSSF_len EQU 1
RCC_CIR_LSIRDYIE EQU 0x00000100 ; LSI Ready Interrupt Enable
RCC_CIR_LSIRDYIE_ofs EQU 8
RCC_CIR_LSIRDYIE_len EQU 1
RCC_CIR_LSERDYIE EQU 0x00000200 ; LSE Ready Interrupt Enable
RCC_CIR_LSERDYIE_ofs EQU 9
RCC_CIR_LSERDYIE_len EQU 1
RCC_CIR_HSIRDYIE EQU 0x00000400 ; HSI Ready Interrupt Enable
RCC_CIR_HSIRDYIE_ofs EQU 10
RCC_CIR_HSIRDYIE_len EQU 1
RCC_CIR_HSERDYIE EQU 0x00000800 ; HSE Ready Interrupt Enable
RCC_CIR_HSERDYIE_ofs EQU 11
RCC_CIR_HSERDYIE_len EQU 1
RCC_CIR_PLLRDYIE EQU 0x00001000 ; PLL Ready Interrupt Enable
RCC_CIR_PLLRDYIE_ofs EQU 12
RCC_CIR_PLLRDYIE_len EQU 1
RCC_CIR_LSIRDYC EQU 0x00010000 ; LSI Ready Interrupt Clear
RCC_CIR_LSIRDYC_ofs EQU 16
RCC_CIR_LSIRDYC_len EQU 1
RCC_CIR_LSERDYC EQU 0x00020000 ; LSE Ready Interrupt Clear
RCC_CIR_LSERDYC_ofs EQU 17
RCC_CIR_LSERDYC_len EQU 1
RCC_CIR_HSIRDYC EQU 0x00040000 ; HSI Ready Interrupt Clear
RCC_CIR_HSIRDYC_ofs EQU 18
RCC_CIR_HSIRDYC_len EQU 1
RCC_CIR_HSERDYC EQU 0x00080000 ; HSE Ready Interrupt Clear
RCC_CIR_HSERDYC_ofs EQU 19
RCC_CIR_HSERDYC_len EQU 1
RCC_CIR_PLLRDYC EQU 0x00100000 ; PLL Ready Interrupt Clear
RCC_CIR_PLLRDYC_ofs EQU 20
RCC_CIR_PLLRDYC_len EQU 1
RCC_CIR_CSSC EQU 0x00800000 ; Clock security system interrupt clear
RCC_CIR_CSSC_ofs EQU 23
RCC_CIR_CSSC_len EQU 1
; RCC_APB2RSTR fields:
RCC_APB2RSTR_SYSCFGRST EQU 0x00000001 ; SYSCFG and COMP reset
RCC_APB2RSTR_SYSCFGRST_ofs EQU 0
RCC_APB2RSTR_SYSCFGRST_len EQU 1
RCC_APB2RSTR_TIM1RST EQU 0x00000800 ; TIM1 timer reset
RCC_APB2RSTR_TIM1RST_ofs EQU 11
RCC_APB2RSTR_TIM1RST_len EQU 1
RCC_APB2RSTR_SPI1RST EQU 0x00001000 ; SPI 1 reset
RCC_APB2RSTR_SPI1RST_ofs EQU 12
RCC_APB2RSTR_SPI1RST_len EQU 1
RCC_APB2RSTR_TIM8RST EQU 0x00002000 ; TIM8 timer reset
RCC_APB2RSTR_TIM8RST_ofs EQU 13
RCC_APB2RSTR_TIM8RST_len EQU 1
RCC_APB2RSTR_USART1RST EQU 0x00004000 ; USART1 reset
RCC_APB2RSTR_USART1RST_ofs EQU 14
RCC_APB2RSTR_USART1RST_len EQU 1
RCC_APB2RSTR_TIM15RST EQU 0x00010000 ; TIM15 timer reset
RCC_APB2RSTR_TIM15RST_ofs EQU 16
RCC_APB2RSTR_TIM15RST_len EQU 1
RCC_APB2RSTR_TIM16RST EQU 0x00020000 ; TIM16 timer reset
RCC_APB2RSTR_TIM16RST_ofs EQU 17
RCC_APB2RSTR_TIM16RST_len EQU 1
RCC_APB2RSTR_TIM17RST EQU 0x00040000 ; TIM17 timer reset
RCC_APB2RSTR_TIM17RST_ofs EQU 18
RCC_APB2RSTR_TIM17RST_len EQU 1
; RCC_APB1RSTR fields:
RCC_APB1RSTR_TIM2RST EQU 0x00000001 ; Timer 2 reset
RCC_APB1RSTR_TIM2RST_ofs EQU 0
RCC_APB1RSTR_TIM2RST_len EQU 1
RCC_APB1RSTR_TIM3RST EQU 0x00000002 ; Timer 3 reset
RCC_APB1RSTR_TIM3RST_ofs EQU 1
RCC_APB1RSTR_TIM3RST_len EQU 1
RCC_APB1RSTR_TIM4RST EQU 0x00000004 ; Timer 14 reset
RCC_APB1RSTR_TIM4RST_ofs EQU 2
RCC_APB1RSTR_TIM4RST_len EQU 1
RCC_APB1RSTR_TIM6RST EQU 0x00000010 ; Timer 6 reset
RCC_APB1RSTR_TIM6RST_ofs EQU 4
RCC_APB1RSTR_TIM6RST_len EQU 1
RCC_APB1RSTR_TIM7RST EQU 0x00000020 ; Timer 7 reset
RCC_APB1RSTR_TIM7RST_ofs EQU 5
RCC_APB1RSTR_TIM7RST_len EQU 1
RCC_APB1RSTR_WWDGRST EQU 0x00000800 ; Window watchdog reset
RCC_APB1RSTR_WWDGRST_ofs EQU 11
RCC_APB1RSTR_WWDGRST_len EQU 1
RCC_APB1RSTR_SPI2RST EQU 0x00004000 ; SPI2 reset
RCC_APB1RSTR_SPI2RST_ofs EQU 14
RCC_APB1RSTR_SPI2RST_len EQU 1
RCC_APB1RSTR_SPI3RST EQU 0x00008000 ; SPI3 reset
RCC_APB1RSTR_SPI3RST_ofs EQU 15
RCC_APB1RSTR_SPI3RST_len EQU 1
RCC_APB1RSTR_USART2RST EQU 0x00020000 ; USART 2 reset
RCC_APB1RSTR_USART2RST_ofs EQU 17
RCC_APB1RSTR_USART2RST_len EQU 1
RCC_APB1RSTR_USART3RST EQU 0x00040000 ; USART3 reset
RCC_APB1RSTR_USART3RST_ofs EQU 18
RCC_APB1RSTR_USART3RST_len EQU 1
RCC_APB1RSTR_UART4RST EQU 0x00080000 ; UART 4 reset
RCC_APB1RSTR_UART4RST_ofs EQU 19
RCC_APB1RSTR_UART4RST_len EQU 1
RCC_APB1RSTR_UART5RST EQU 0x00100000 ; UART 5 reset
RCC_APB1RSTR_UART5RST_ofs EQU 20
RCC_APB1RSTR_UART5RST_len EQU 1
RCC_APB1RSTR_I2C1RST EQU 0x00200000 ; I2C1 reset
RCC_APB1RSTR_I2C1RST_ofs EQU 21
RCC_APB1RSTR_I2C1RST_len EQU 1
RCC_APB1RSTR_I2C2RST EQU 0x00400000 ; I2C2 reset
RCC_APB1RSTR_I2C2RST_ofs EQU 22
RCC_APB1RSTR_I2C2RST_len EQU 1
RCC_APB1RSTR_USBRST EQU 0x00800000 ; USB reset
RCC_APB1RSTR_USBRST_ofs EQU 23
RCC_APB1RSTR_USBRST_len EQU 1
RCC_APB1RSTR_CANRST EQU 0x02000000 ; CAN reset
RCC_APB1RSTR_CANRST_ofs EQU 25
RCC_APB1RSTR_CANRST_len EQU 1
RCC_APB1RSTR_PWRRST EQU 0x10000000 ; Power interface reset
RCC_APB1RSTR_PWRRST_ofs EQU 28
RCC_APB1RSTR_PWRRST_len EQU 1
RCC_APB1RSTR_DACRST EQU 0x20000000 ; DAC interface reset
RCC_APB1RSTR_DACRST_ofs EQU 29
RCC_APB1RSTR_DACRST_len EQU 1
; RCC_AHBENR fields:
RCC_AHBENR_DMAEN EQU 0x00000001 ; DMA1 clock enable
RCC_AHBENR_DMAEN_ofs EQU 0
RCC_AHBENR_DMAEN_len EQU 1
RCC_AHBENR_DMA2EN EQU 0x00000002 ; DMA2 clock enable
RCC_AHBENR_DMA2EN_ofs EQU 1
RCC_AHBENR_DMA2EN_len EQU 1
RCC_AHBENR_SRAMEN EQU 0x00000004 ; SRAM interface clock enable
RCC_AHBENR_SRAMEN_ofs EQU 2
RCC_AHBENR_SRAMEN_len EQU 1
RCC_AHBENR_FLITFEN EQU 0x00000010 ; FLITF clock enable
RCC_AHBENR_FLITFEN_ofs EQU 4
RCC_AHBENR_FLITFEN_len EQU 1
RCC_AHBENR_CRCEN EQU 0x00000040 ; CRC clock enable
RCC_AHBENR_CRCEN_ofs EQU 6
RCC_AHBENR_CRCEN_len EQU 1
RCC_AHBENR_IOPAEN EQU 0x00020000 ; I/O port A clock enable
RCC_AHBENR_IOPAEN_ofs EQU 17
RCC_AHBENR_IOPAEN_len EQU 1
RCC_AHBENR_IOPBEN EQU 0x00040000 ; I/O port B clock enable
RCC_AHBENR_IOPBEN_ofs EQU 18
RCC_AHBENR_IOPBEN_len EQU 1
RCC_AHBENR_IOPCEN EQU 0x00080000 ; I/O port C clock enable
RCC_AHBENR_IOPCEN_ofs EQU 19
RCC_AHBENR_IOPCEN_len EQU 1
RCC_AHBENR_IOPDEN EQU 0x00100000 ; I/O port D clock enable
RCC_AHBENR_IOPDEN_ofs EQU 20
RCC_AHBENR_IOPDEN_len EQU 1
RCC_AHBENR_IOPEEN EQU 0x00200000 ; I/O port E clock enable
RCC_AHBENR_IOPEEN_ofs EQU 21
RCC_AHBENR_IOPEEN_len EQU 1
RCC_AHBENR_IOPFEN EQU 0x00400000 ; I/O port F clock enable
RCC_AHBENR_IOPFEN_ofs EQU 22
RCC_AHBENR_IOPFEN_len EQU 1
RCC_AHBENR_TSCEN EQU 0x01000000 ; Touch sensing controller clock enable
RCC_AHBENR_TSCEN_ofs EQU 24
RCC_AHBENR_TSCEN_len EQU 1
RCC_AHBENR_ADC12EN EQU 0x10000000 ; ADC1 and ADC2 clock enable
RCC_AHBENR_ADC12EN_ofs EQU 28
RCC_AHBENR_ADC12EN_len EQU 1
RCC_AHBENR_ADC34EN EQU 0x20000000 ; ADC3 and ADC4 clock enable
RCC_AHBENR_ADC34EN_ofs EQU 29
RCC_AHBENR_ADC34EN_len EQU 1
; RCC_APB2ENR fields:
RCC_APB2ENR_SYSCFGEN EQU 0x00000001 ; SYSCFG clock enable
RCC_APB2ENR_SYSCFGEN_ofs EQU 0
RCC_APB2ENR_SYSCFGEN_len EQU 1
RCC_APB2ENR_TIM1EN EQU 0x00000800 ; TIM1 Timer clock enable
RCC_APB2ENR_TIM1EN_ofs EQU 11
RCC_APB2ENR_TIM1EN_len EQU 1
RCC_APB2ENR_SPI1EN EQU 0x00001000 ; SPI 1 clock enable
RCC_APB2ENR_SPI1EN_ofs EQU 12
RCC_APB2ENR_SPI1EN_len EQU 1
RCC_APB2ENR_TIM8EN EQU 0x00002000 ; TIM8 Timer clock enable
RCC_APB2ENR_TIM8EN_ofs EQU 13
RCC_APB2ENR_TIM8EN_len EQU 1
RCC_APB2ENR_USART1EN EQU 0x00004000 ; USART1 clock enable
RCC_APB2ENR_USART1EN_ofs EQU 14
RCC_APB2ENR_USART1EN_len EQU 1
RCC_APB2ENR_TIM15EN EQU 0x00010000 ; TIM15 timer clock enable
RCC_APB2ENR_TIM15EN_ofs EQU 16
RCC_APB2ENR_TIM15EN_len EQU 1
RCC_APB2ENR_TIM16EN EQU 0x00020000 ; TIM16 timer clock enable
RCC_APB2ENR_TIM16EN_ofs EQU 17
RCC_APB2ENR_TIM16EN_len EQU 1
RCC_APB2ENR_TIM17EN EQU 0x00040000 ; TIM17 timer clock enable
RCC_APB2ENR_TIM17EN_ofs EQU 18
RCC_APB2ENR_TIM17EN_len EQU 1
; RCC_APB1ENR fields:
RCC_APB1ENR_TIM2EN EQU 0x00000001 ; Timer 2 clock enable
RCC_APB1ENR_TIM2EN_ofs EQU 0
RCC_APB1ENR_TIM2EN_len EQU 1
RCC_APB1ENR_TIM3EN EQU 0x00000002 ; Timer 3 clock enable
RCC_APB1ENR_TIM3EN_ofs EQU 1
RCC_APB1ENR_TIM3EN_len EQU 1
RCC_APB1ENR_TIM4EN EQU 0x00000004 ; Timer 4 clock enable
RCC_APB1ENR_TIM4EN_ofs EQU 2
RCC_APB1ENR_TIM4EN_len EQU 1
RCC_APB1ENR_TIM6EN EQU 0x00000010 ; Timer 6 clock enable
RCC_APB1ENR_TIM6EN_ofs EQU 4
RCC_APB1ENR_TIM6EN_len EQU 1
RCC_APB1ENR_TIM7EN EQU 0x00000020 ; Timer 7 clock enable
RCC_APB1ENR_TIM7EN_ofs EQU 5
RCC_APB1ENR_TIM7EN_len EQU 1
RCC_APB1ENR_WWDGEN EQU 0x00000800 ; Window watchdog clock enable
RCC_APB1ENR_WWDGEN_ofs EQU 11
RCC_APB1ENR_WWDGEN_len EQU 1
RCC_APB1ENR_SPI2EN EQU 0x00004000 ; SPI 2 clock enable
RCC_APB1ENR_SPI2EN_ofs EQU 14
RCC_APB1ENR_SPI2EN_len EQU 1
RCC_APB1ENR_SPI3EN EQU 0x00008000 ; SPI 3 clock enable
RCC_APB1ENR_SPI3EN_ofs EQU 15
RCC_APB1ENR_SPI3EN_len EQU 1
RCC_APB1ENR_USART2EN EQU 0x00020000 ; USART 2 clock enable
RCC_APB1ENR_USART2EN_ofs EQU 17
RCC_APB1ENR_USART2EN_len EQU 1
RCC_APB1ENR_I2C1EN EQU 0x00200000 ; I2C 1 clock enable
RCC_APB1ENR_I2C1EN_ofs EQU 21
RCC_APB1ENR_I2C1EN_len EQU 1
RCC_APB1ENR_I2C2EN EQU 0x00400000 ; I2C 2 clock enable
RCC_APB1ENR_I2C2EN_ofs EQU 22
RCC_APB1ENR_I2C2EN_len EQU 1
RCC_APB1ENR_USBEN EQU 0x00800000 ; USB clock enable
RCC_APB1ENR_USBEN_ofs EQU 23
RCC_APB1ENR_USBEN_len EQU 1
RCC_APB1ENR_CANEN EQU 0x02000000 ; CAN clock enable
RCC_APB1ENR_CANEN_ofs EQU 25
RCC_APB1ENR_CANEN_len EQU 1
RCC_APB1ENR_PWREN EQU 0x10000000 ; Power interface clock enable
RCC_APB1ENR_PWREN_ofs EQU 28
RCC_APB1ENR_PWREN_len EQU 1
RCC_APB1ENR_DACEN EQU 0x20000000 ; DAC interface clock enable
RCC_APB1ENR_DACEN_ofs EQU 29
RCC_APB1ENR_DACEN_len EQU 1
; RCC_BDCR fields:
RCC_BDCR_LSEON EQU 0x00000001 ; External Low Speed oscillator enable
RCC_BDCR_LSEON_ofs EQU 0
RCC_BDCR_LSEON_len EQU 1
RCC_BDCR_LSERDY EQU 0x00000002 ; External Low Speed oscillator ready
RCC_BDCR_LSERDY_ofs EQU 1
RCC_BDCR_LSERDY_len EQU 1
RCC_BDCR_LSEBYP EQU 0x00000004 ; External Low Speed oscillator bypass
RCC_BDCR_LSEBYP_ofs EQU 2
RCC_BDCR_LSEBYP_len EQU 1
RCC_BDCR_LSEDRV EQU 0x00000018 ; LSE oscillator drive capability
RCC_BDCR_LSEDRV_ofs EQU 3
RCC_BDCR_LSEDRV_len EQU 2
RCC_BDCR_RTCSEL EQU 0x00000300 ; RTC clock source selection
RCC_BDCR_RTCSEL_ofs EQU 8
RCC_BDCR_RTCSEL_len EQU 2
RCC_BDCR_RTCEN EQU 0x00008000 ; RTC clock enable
RCC_BDCR_RTCEN_ofs EQU 15
RCC_BDCR_RTCEN_len EQU 1
RCC_BDCR_BDRST EQU 0x00010000 ; Backup domain software reset
RCC_BDCR_BDRST_ofs EQU 16
RCC_BDCR_BDRST_len EQU 1
; RCC_CSR fields:
RCC_CSR_LSION EQU 0x00000001 ; Internal low speed oscillator enable
RCC_CSR_LSION_ofs EQU 0
RCC_CSR_LSION_len EQU 1
RCC_CSR_LSIRDY EQU 0x00000002 ; Internal low speed oscillator ready
RCC_CSR_LSIRDY_ofs EQU 1
RCC_CSR_LSIRDY_len EQU 1
RCC_CSR_RMVF EQU 0x01000000 ; Remove reset flag
RCC_CSR_RMVF_ofs EQU 24
RCC_CSR_RMVF_len EQU 1
RCC_CSR_OBLRSTF EQU 0x02000000 ; Option byte loader reset flag
RCC_CSR_OBLRSTF_ofs EQU 25
RCC_CSR_OBLRSTF_len EQU 1
RCC_CSR_PINRSTF EQU 0x04000000 ; PIN reset flag
RCC_CSR_PINRSTF_ofs EQU 26
RCC_CSR_PINRSTF_len EQU 1
RCC_CSR_PORRSTF EQU 0x08000000 ; POR/PDR reset flag
RCC_CSR_PORRSTF_ofs EQU 27
RCC_CSR_PORRSTF_len EQU 1
RCC_CSR_SFTRSTF EQU 0x10000000 ; Software reset flag
RCC_CSR_SFTRSTF_ofs EQU 28
RCC_CSR_SFTRSTF_len EQU 1
RCC_CSR_IWDGRSTF EQU 0x20000000 ; Independent watchdog reset flag
RCC_CSR_IWDGRSTF_ofs EQU 29
RCC_CSR_IWDGRSTF_len EQU 1
RCC_CSR_WWDGRSTF EQU 0x40000000 ; Window watchdog reset flag
RCC_CSR_WWDGRSTF_ofs EQU 30
RCC_CSR_WWDGRSTF_len EQU 1
RCC_CSR_LPWRRSTF EQU 0x80000000 ; Low-power reset flag
RCC_CSR_LPWRRSTF_ofs EQU 31
RCC_CSR_LPWRRSTF_len EQU 1
; RCC_AHBRSTR fields:
RCC_AHBRSTR_IOPARST EQU 0x00020000 ; I/O port A reset
RCC_AHBRSTR_IOPARST_ofs EQU 17
RCC_AHBRSTR_IOPARST_len EQU 1
RCC_AHBRSTR_IOPBRST EQU 0x00040000 ; I/O port B reset
RCC_AHBRSTR_IOPBRST_ofs EQU 18
RCC_AHBRSTR_IOPBRST_len EQU 1
RCC_AHBRSTR_IOPCRST EQU 0x00080000 ; I/O port C reset
RCC_AHBRSTR_IOPCRST_ofs EQU 19
RCC_AHBRSTR_IOPCRST_len EQU 1
RCC_AHBRSTR_IOPDRST EQU 0x00100000 ; I/O port D reset
RCC_AHBRSTR_IOPDRST_ofs EQU 20
RCC_AHBRSTR_IOPDRST_len EQU 1
RCC_AHBRSTR_IOPERST EQU 0x00200000 ; I/O port E reset
RCC_AHBRSTR_IOPERST_ofs EQU 21
RCC_AHBRSTR_IOPERST_len EQU 1
RCC_AHBRSTR_IOPFRST EQU 0x00400000 ; I/O port F reset
RCC_AHBRSTR_IOPFRST_ofs EQU 22
RCC_AHBRSTR_IOPFRST_len EQU 1
RCC_AHBRSTR_TSCRST EQU 0x01000000 ; Touch sensing controller reset
RCC_AHBRSTR_TSCRST_ofs EQU 24
RCC_AHBRSTR_TSCRST_len EQU 1
RCC_AHBRSTR_ADC12RST EQU 0x10000000 ; ADC1 and ADC2 reset
RCC_AHBRSTR_ADC12RST_ofs EQU 28
RCC_AHBRSTR_ADC12RST_len EQU 1
RCC_AHBRSTR_ADC34RST EQU 0x20000000 ; ADC3 and ADC4 reset
RCC_AHBRSTR_ADC34RST_ofs EQU 29
RCC_AHBRSTR_ADC34RST_len EQU 1
; RCC_CFGR2 fields:
RCC_CFGR2_PREDIV EQU 0x0000000f ; PREDIV division factor
RCC_CFGR2_PREDIV_ofs EQU 0
RCC_CFGR2_PREDIV_len EQU 4
RCC_CFGR2_ADC12PRES EQU 0x000001f0 ; ADC1 and ADC2 prescaler
RCC_CFGR2_ADC12PRES_ofs EQU 4
RCC_CFGR2_ADC12PRES_len EQU 5
RCC_CFGR2_ADC34PRES EQU 0x00003e00 ; ADC3 and ADC4 prescaler
RCC_CFGR2_ADC34PRES_ofs EQU 9
RCC_CFGR2_ADC34PRES_len EQU 5
; RCC_CFGR3 fields:
RCC_CFGR3_USART1SW EQU 0x00000003 ; USART1 clock source selection
RCC_CFGR3_USART1SW_ofs EQU 0
RCC_CFGR3_USART1SW_len EQU 2
RCC_CFGR3_I2C1SW EQU 0x00000010 ; I2C1 clock source selection
RCC_CFGR3_I2C1SW_ofs EQU 4
RCC_CFGR3_I2C1SW_len EQU 1
RCC_CFGR3_I2C2SW EQU 0x00000020 ; I2C2 clock source selection
RCC_CFGR3_I2C2SW_ofs EQU 5
RCC_CFGR3_I2C2SW_len EQU 1
RCC_CFGR3_USART2SW EQU 0x00030000 ; USART2 clock source selection
RCC_CFGR3_USART2SW_ofs EQU 16
RCC_CFGR3_USART2SW_len EQU 2
RCC_CFGR3_USART3SW EQU 0x000c0000 ; USART3 clock source selection
RCC_CFGR3_USART3SW_ofs EQU 18
RCC_CFGR3_USART3SW_len EQU 2
RCC_CFGR3_TIM1SW EQU 0x00000100 ; Timer1 clock source selection
RCC_CFGR3_TIM1SW_ofs EQU 8
RCC_CFGR3_TIM1SW_len EQU 1
RCC_CFGR3_TIM8SW EQU 0x00000200 ; Timer8 clock source selection
RCC_CFGR3_TIM8SW_ofs EQU 9
RCC_CFGR3_TIM8SW_len EQU 1
RCC_CFGR3_UART4SW EQU 0x00300000 ; UART4 clock source selection
RCC_CFGR3_UART4SW_ofs EQU 20
RCC_CFGR3_UART4SW_len EQU 2
RCC_CFGR3_UART5SW EQU 0x00c00000 ; UART5 clock source selection
RCC_CFGR3_UART5SW_ofs EQU 22
RCC_CFGR3_UART5SW_len EQU 2
; ---- DMA1 --------------------------------------------------
; Desc: DMA controller 1
; DMA1 base address:
DMA1_BASE EQU 0x40020000
; DMA1 registers:
DMA1_ISR EQU (DMA1_BASE + 0x0) ; DMA interrupt status register (DMA_ISR)
DMA1_IFCR EQU (DMA1_BASE + 0x4) ; DMA interrupt flag clear register (DMA_IFCR)
DMA1_CCR1 EQU (DMA1_BASE + 0x8) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR1 EQU (DMA1_BASE + 0xc) ; DMA channel 1 number of data register
DMA1_CPAR1 EQU (DMA1_BASE + 0x10) ; DMA channel 1 peripheral address register
DMA1_CMAR1 EQU (DMA1_BASE + 0x14) ; DMA channel 1 memory address register
DMA1_CCR2 EQU (DMA1_BASE + 0x1c) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR2 EQU (DMA1_BASE + 0x20) ; DMA channel 2 number of data register
DMA1_CPAR2 EQU (DMA1_BASE + 0x24) ; DMA channel 2 peripheral address register
DMA1_CMAR2 EQU (DMA1_BASE + 0x28) ; DMA channel 2 memory address register
DMA1_CCR3 EQU (DMA1_BASE + 0x30) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR3 EQU (DMA1_BASE + 0x34) ; DMA channel 3 number of data register
DMA1_CPAR3 EQU (DMA1_BASE + 0x38) ; DMA channel 3 peripheral address register
DMA1_CMAR3 EQU (DMA1_BASE + 0x3c) ; DMA channel 3 memory address register
DMA1_CCR4 EQU (DMA1_BASE + 0x44) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR4 EQU (DMA1_BASE + 0x48) ; DMA channel 4 number of data register
DMA1_CPAR4 EQU (DMA1_BASE + 0x4c) ; DMA channel 4 peripheral address register
DMA1_CMAR4 EQU (DMA1_BASE + 0x50) ; DMA channel 4 memory address register
DMA1_CCR5 EQU (DMA1_BASE + 0x58) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR5 EQU (DMA1_BASE + 0x5c) ; DMA channel 5 number of data register
DMA1_CPAR5 EQU (DMA1_BASE + 0x60) ; DMA channel 5 peripheral address register
DMA1_CMAR5 EQU (DMA1_BASE + 0x64) ; DMA channel 5 memory address register
DMA1_CCR6 EQU (DMA1_BASE + 0x6c) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR6 EQU (DMA1_BASE + 0x70) ; DMA channel 6 number of data register
DMA1_CPAR6 EQU (DMA1_BASE + 0x74) ; DMA channel 6 peripheral address register
DMA1_CMAR6 EQU (DMA1_BASE + 0x78) ; DMA channel 6 memory address register
DMA1_CCR7 EQU (DMA1_BASE + 0x80) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR7 EQU (DMA1_BASE + 0x84) ; DMA channel 7 number of data register
DMA1_CPAR7 EQU (DMA1_BASE + 0x88) ; DMA channel 7 peripheral address register
DMA1_CMAR7 EQU (DMA1_BASE + 0x8c) ; DMA channel 7 memory address register
; DMA1_ISR fields:
DMA1_ISR_GIF1 EQU 0x00000001 ; Channel 1 Global interrupt flag
DMA1_ISR_GIF1_ofs EQU 0
DMA1_ISR_GIF1_len EQU 1
DMA1_ISR_TCIF1 EQU 0x00000002 ; Channel 1 Transfer Complete flag
DMA1_ISR_TCIF1_ofs EQU 1
DMA1_ISR_TCIF1_len EQU 1
DMA1_ISR_HTIF1 EQU 0x00000004 ; Channel 1 Half Transfer Complete flag
DMA1_ISR_HTIF1_ofs EQU 2
DMA1_ISR_HTIF1_len EQU 1
DMA1_ISR_TEIF1 EQU 0x00000008 ; Channel 1 Transfer Error flag
DMA1_ISR_TEIF1_ofs EQU 3
DMA1_ISR_TEIF1_len EQU 1
DMA1_ISR_GIF2 EQU 0x00000010 ; Channel 2 Global interrupt flag
DMA1_ISR_GIF2_ofs EQU 4
DMA1_ISR_GIF2_len EQU 1
DMA1_ISR_TCIF2 EQU 0x00000020 ; Channel 2 Transfer Complete flag
DMA1_ISR_TCIF2_ofs EQU 5
DMA1_ISR_TCIF2_len EQU 1
DMA1_ISR_HTIF2 EQU 0x00000040 ; Channel 2 Half Transfer Complete flag
DMA1_ISR_HTIF2_ofs EQU 6
DMA1_ISR_HTIF2_len EQU 1
DMA1_ISR_TEIF2 EQU 0x00000080 ; Channel 2 Transfer Error flag
DMA1_ISR_TEIF2_ofs EQU 7
DMA1_ISR_TEIF2_len EQU 1
DMA1_ISR_GIF3 EQU 0x00000100 ; Channel 3 Global interrupt flag
DMA1_ISR_GIF3_ofs EQU 8
DMA1_ISR_GIF3_len EQU 1
DMA1_ISR_TCIF3 EQU 0x00000200 ; Channel 3 Transfer Complete flag
DMA1_ISR_TCIF3_ofs EQU 9
DMA1_ISR_TCIF3_len EQU 1
DMA1_ISR_HTIF3 EQU 0x00000400 ; Channel 3 Half Transfer Complete flag
DMA1_ISR_HTIF3_ofs EQU 10
DMA1_ISR_HTIF3_len EQU 1
DMA1_ISR_TEIF3 EQU 0x00000800 ; Channel 3 Transfer Error flag
DMA1_ISR_TEIF3_ofs EQU 11
DMA1_ISR_TEIF3_len EQU 1
DMA1_ISR_GIF4 EQU 0x00001000 ; Channel 4 Global interrupt flag
DMA1_ISR_GIF4_ofs EQU 12
DMA1_ISR_GIF4_len EQU 1
DMA1_ISR_TCIF4 EQU 0x00002000 ; Channel 4 Transfer Complete flag
DMA1_ISR_TCIF4_ofs EQU 13
DMA1_ISR_TCIF4_len EQU 1
DMA1_ISR_HTIF4 EQU 0x00004000 ; Channel 4 Half Transfer Complete flag
DMA1_ISR_HTIF4_ofs EQU 14
DMA1_ISR_HTIF4_len EQU 1
DMA1_ISR_TEIF4 EQU 0x00008000 ; Channel 4 Transfer Error flag
DMA1_ISR_TEIF4_ofs EQU 15
DMA1_ISR_TEIF4_len EQU 1
DMA1_ISR_GIF5 EQU 0x00010000 ; Channel 5 Global interrupt flag
DMA1_ISR_GIF5_ofs EQU 16
DMA1_ISR_GIF5_len EQU 1
DMA1_ISR_TCIF5 EQU 0x00020000 ; Channel 5 Transfer Complete flag
DMA1_ISR_TCIF5_ofs EQU 17
DMA1_ISR_TCIF5_len EQU 1
DMA1_ISR_HTIF5 EQU 0x00040000 ; Channel 5 Half Transfer Complete flag
DMA1_ISR_HTIF5_ofs EQU 18
DMA1_ISR_HTIF5_len EQU 1
DMA1_ISR_TEIF5 EQU 0x00080000 ; Channel 5 Transfer Error flag
DMA1_ISR_TEIF5_ofs EQU 19
DMA1_ISR_TEIF5_len EQU 1
DMA1_ISR_GIF6 EQU 0x00100000 ; Channel 6 Global interrupt flag
DMA1_ISR_GIF6_ofs EQU 20
DMA1_ISR_GIF6_len EQU 1
DMA1_ISR_TCIF6 EQU 0x00200000 ; Channel 6 Transfer Complete flag
DMA1_ISR_TCIF6_ofs EQU 21
DMA1_ISR_TCIF6_len EQU 1
DMA1_ISR_HTIF6 EQU 0x00400000 ; Channel 6 Half Transfer Complete flag
DMA1_ISR_HTIF6_ofs EQU 22
DMA1_ISR_HTIF6_len EQU 1
DMA1_ISR_TEIF6 EQU 0x00800000 ; Channel 6 Transfer Error flag
DMA1_ISR_TEIF6_ofs EQU 23
DMA1_ISR_TEIF6_len EQU 1
DMA1_ISR_GIF7 EQU 0x01000000 ; Channel 7 Global interrupt flag
DMA1_ISR_GIF7_ofs EQU 24
DMA1_ISR_GIF7_len EQU 1
DMA1_ISR_TCIF7 EQU 0x02000000 ; Channel 7 Transfer Complete flag
DMA1_ISR_TCIF7_ofs EQU 25
DMA1_ISR_TCIF7_len EQU 1
DMA1_ISR_HTIF7 EQU 0x04000000 ; Channel 7 Half Transfer Complete flag
DMA1_ISR_HTIF7_ofs EQU 26
DMA1_ISR_HTIF7_len EQU 1
DMA1_ISR_TEIF7 EQU 0x08000000 ; Channel 7 Transfer Error flag
DMA1_ISR_TEIF7_ofs EQU 27
DMA1_ISR_TEIF7_len EQU 1
; DMA1_IFCR fields:
DMA1_IFCR_CGIF1 EQU 0x00000001 ; Channel 1 Global interrupt clear
DMA1_IFCR_CGIF1_ofs EQU 0
DMA1_IFCR_CGIF1_len EQU 1
DMA1_IFCR_CTCIF1 EQU 0x00000002 ; Channel 1 Transfer Complete clear
DMA1_IFCR_CTCIF1_ofs EQU 1
DMA1_IFCR_CTCIF1_len EQU 1
DMA1_IFCR_CHTIF1 EQU 0x00000004 ; Channel 1 Half Transfer clear
DMA1_IFCR_CHTIF1_ofs EQU 2
DMA1_IFCR_CHTIF1_len EQU 1
DMA1_IFCR_CTEIF1 EQU 0x00000008 ; Channel 1 Transfer Error clear
DMA1_IFCR_CTEIF1_ofs EQU 3
DMA1_IFCR_CTEIF1_len EQU 1
DMA1_IFCR_CGIF2 EQU 0x00000010 ; Channel 2 Global interrupt clear
DMA1_IFCR_CGIF2_ofs EQU 4
DMA1_IFCR_CGIF2_len EQU 1
DMA1_IFCR_CTCIF2 EQU 0x00000020 ; Channel 2 Transfer Complete clear
DMA1_IFCR_CTCIF2_ofs EQU 5
DMA1_IFCR_CTCIF2_len EQU 1
DMA1_IFCR_CHTIF2 EQU 0x00000040 ; Channel 2 Half Transfer clear
DMA1_IFCR_CHTIF2_ofs EQU 6
DMA1_IFCR_CHTIF2_len EQU 1
DMA1_IFCR_CTEIF2 EQU 0x00000080 ; Channel 2 Transfer Error clear
DMA1_IFCR_CTEIF2_ofs EQU 7
DMA1_IFCR_CTEIF2_len EQU 1
DMA1_IFCR_CGIF3 EQU 0x00000100 ; Channel 3 Global interrupt clear
DMA1_IFCR_CGIF3_ofs EQU 8
DMA1_IFCR_CGIF3_len EQU 1
DMA1_IFCR_CTCIF3 EQU 0x00000200 ; Channel 3 Transfer Complete clear
DMA1_IFCR_CTCIF3_ofs EQU 9
DMA1_IFCR_CTCIF3_len EQU 1
DMA1_IFCR_CHTIF3 EQU 0x00000400 ; Channel 3 Half Transfer clear
DMA1_IFCR_CHTIF3_ofs EQU 10
DMA1_IFCR_CHTIF3_len EQU 1
DMA1_IFCR_CTEIF3 EQU 0x00000800 ; Channel 3 Transfer Error clear
DMA1_IFCR_CTEIF3_ofs EQU 11
DMA1_IFCR_CTEIF3_len EQU 1
DMA1_IFCR_CGIF4 EQU 0x00001000 ; Channel 4 Global interrupt clear
DMA1_IFCR_CGIF4_ofs EQU 12
DMA1_IFCR_CGIF4_len EQU 1
DMA1_IFCR_CTCIF4 EQU 0x00002000 ; Channel 4 Transfer Complete clear
DMA1_IFCR_CTCIF4_ofs EQU 13
DMA1_IFCR_CTCIF4_len EQU 1
DMA1_IFCR_CHTIF4 EQU 0x00004000 ; Channel 4 Half Transfer clear
DMA1_IFCR_CHTIF4_ofs EQU 14
DMA1_IFCR_CHTIF4_len EQU 1
DMA1_IFCR_CTEIF4 EQU 0x00008000 ; Channel 4 Transfer Error clear
DMA1_IFCR_CTEIF4_ofs EQU 15
DMA1_IFCR_CTEIF4_len EQU 1
DMA1_IFCR_CGIF5 EQU 0x00010000 ; Channel 5 Global interrupt clear
DMA1_IFCR_CGIF5_ofs EQU 16
DMA1_IFCR_CGIF5_len EQU 1
DMA1_IFCR_CTCIF5 EQU 0x00020000 ; Channel 5 Transfer Complete clear
DMA1_IFCR_CTCIF5_ofs EQU 17
DMA1_IFCR_CTCIF5_len EQU 1
DMA1_IFCR_CHTIF5 EQU 0x00040000 ; Channel 5 Half Transfer clear
DMA1_IFCR_CHTIF5_ofs EQU 18
DMA1_IFCR_CHTIF5_len EQU 1
DMA1_IFCR_CTEIF5 EQU 0x00080000 ; Channel 5 Transfer Error clear
DMA1_IFCR_CTEIF5_ofs EQU 19
DMA1_IFCR_CTEIF5_len EQU 1
DMA1_IFCR_CGIF6 EQU 0x00100000 ; Channel 6 Global interrupt clear
DMA1_IFCR_CGIF6_ofs EQU 20
DMA1_IFCR_CGIF6_len EQU 1
DMA1_IFCR_CTCIF6 EQU 0x00200000 ; Channel 6 Transfer Complete clear
DMA1_IFCR_CTCIF6_ofs EQU 21
DMA1_IFCR_CTCIF6_len EQU 1
DMA1_IFCR_CHTIF6 EQU 0x00400000 ; Channel 6 Half Transfer clear
DMA1_IFCR_CHTIF6_ofs EQU 22
DMA1_IFCR_CHTIF6_len EQU 1
DMA1_IFCR_CTEIF6 EQU 0x00800000 ; Channel 6 Transfer Error clear
DMA1_IFCR_CTEIF6_ofs EQU 23
DMA1_IFCR_CTEIF6_len EQU 1
DMA1_IFCR_CGIF7 EQU 0x01000000 ; Channel 7 Global interrupt clear
DMA1_IFCR_CGIF7_ofs EQU 24
DMA1_IFCR_CGIF7_len EQU 1
DMA1_IFCR_CTCIF7 EQU 0x02000000 ; Channel 7 Transfer Complete clear
DMA1_IFCR_CTCIF7_ofs EQU 25
DMA1_IFCR_CTCIF7_len EQU 1
DMA1_IFCR_CHTIF7 EQU 0x04000000 ; Channel 7 Half Transfer clear
DMA1_IFCR_CHTIF7_ofs EQU 26
DMA1_IFCR_CHTIF7_len EQU 1
DMA1_IFCR_CTEIF7 EQU 0x08000000 ; Channel 7 Transfer Error clear
DMA1_IFCR_CTEIF7_ofs EQU 27
DMA1_IFCR_CTEIF7_len EQU 1
; DMA1_CCR1 fields:
DMA1_CCR1_EN EQU 0x00000001 ; Channel enable
DMA1_CCR1_EN_ofs EQU 0
DMA1_CCR1_EN_len EQU 1
DMA1_CCR1_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR1_TCIE_ofs EQU 1
DMA1_CCR1_TCIE_len EQU 1
DMA1_CCR1_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR1_HTIE_ofs EQU 2
DMA1_CCR1_HTIE_len EQU 1
DMA1_CCR1_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR1_TEIE_ofs EQU 3
DMA1_CCR1_TEIE_len EQU 1
DMA1_CCR1_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR1_DIR_ofs EQU 4
DMA1_CCR1_DIR_len EQU 1
DMA1_CCR1_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR1_CIRC_ofs EQU 5
DMA1_CCR1_CIRC_len EQU 1
DMA1_CCR1_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR1_PINC_ofs EQU 6
DMA1_CCR1_PINC_len EQU 1
DMA1_CCR1_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR1_MINC_ofs EQU 7
DMA1_CCR1_MINC_len EQU 1
DMA1_CCR1_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR1_PSIZE_ofs EQU 8
DMA1_CCR1_PSIZE_len EQU 2
DMA1_CCR1_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR1_MSIZE_ofs EQU 10
DMA1_CCR1_MSIZE_len EQU 2
DMA1_CCR1_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR1_PL_ofs EQU 12
DMA1_CCR1_PL_len EQU 2
DMA1_CCR1_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR1_MEM2MEM_ofs EQU 14
DMA1_CCR1_MEM2MEM_len EQU 1
; DMA1_CNDTR1 fields:
DMA1_CNDTR1_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR1_NDT_ofs EQU 0
DMA1_CNDTR1_NDT_len EQU 16
; DMA1_CPAR1 fields:
DMA1_CPAR1_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR1_PA_ofs EQU 0
DMA1_CPAR1_PA_len EQU 32
; DMA1_CMAR1 fields:
DMA1_CMAR1_MA EQU 0xffffffff ; Memory address
DMA1_CMAR1_MA_ofs EQU 0
DMA1_CMAR1_MA_len EQU 32
; DMA1_CCR2 fields:
DMA1_CCR2_EN EQU 0x00000001 ; Channel enable
DMA1_CCR2_EN_ofs EQU 0
DMA1_CCR2_EN_len EQU 1
DMA1_CCR2_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR2_TCIE_ofs EQU 1
DMA1_CCR2_TCIE_len EQU 1
DMA1_CCR2_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR2_HTIE_ofs EQU 2
DMA1_CCR2_HTIE_len EQU 1
DMA1_CCR2_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR2_TEIE_ofs EQU 3
DMA1_CCR2_TEIE_len EQU 1
DMA1_CCR2_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR2_DIR_ofs EQU 4
DMA1_CCR2_DIR_len EQU 1
DMA1_CCR2_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR2_CIRC_ofs EQU 5
DMA1_CCR2_CIRC_len EQU 1
DMA1_CCR2_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR2_PINC_ofs EQU 6
DMA1_CCR2_PINC_len EQU 1
DMA1_CCR2_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR2_MINC_ofs EQU 7
DMA1_CCR2_MINC_len EQU 1
DMA1_CCR2_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR2_PSIZE_ofs EQU 8
DMA1_CCR2_PSIZE_len EQU 2
DMA1_CCR2_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR2_MSIZE_ofs EQU 10
DMA1_CCR2_MSIZE_len EQU 2
DMA1_CCR2_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR2_PL_ofs EQU 12
DMA1_CCR2_PL_len EQU 2
DMA1_CCR2_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR2_MEM2MEM_ofs EQU 14
DMA1_CCR2_MEM2MEM_len EQU 1
; DMA1_CNDTR2 fields:
DMA1_CNDTR2_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR2_NDT_ofs EQU 0
DMA1_CNDTR2_NDT_len EQU 16
; DMA1_CPAR2 fields:
DMA1_CPAR2_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR2_PA_ofs EQU 0
DMA1_CPAR2_PA_len EQU 32
; DMA1_CMAR2 fields:
DMA1_CMAR2_MA EQU 0xffffffff ; Memory address
DMA1_CMAR2_MA_ofs EQU 0
DMA1_CMAR2_MA_len EQU 32
; DMA1_CCR3 fields:
DMA1_CCR3_EN EQU 0x00000001 ; Channel enable
DMA1_CCR3_EN_ofs EQU 0
DMA1_CCR3_EN_len EQU 1
DMA1_CCR3_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR3_TCIE_ofs EQU 1
DMA1_CCR3_TCIE_len EQU 1
DMA1_CCR3_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR3_HTIE_ofs EQU 2
DMA1_CCR3_HTIE_len EQU 1
DMA1_CCR3_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR3_TEIE_ofs EQU 3
DMA1_CCR3_TEIE_len EQU 1
DMA1_CCR3_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR3_DIR_ofs EQU 4
DMA1_CCR3_DIR_len EQU 1
DMA1_CCR3_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR3_CIRC_ofs EQU 5
DMA1_CCR3_CIRC_len EQU 1
DMA1_CCR3_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR3_PINC_ofs EQU 6
DMA1_CCR3_PINC_len EQU 1
DMA1_CCR3_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR3_MINC_ofs EQU 7
DMA1_CCR3_MINC_len EQU 1
DMA1_CCR3_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR3_PSIZE_ofs EQU 8
DMA1_CCR3_PSIZE_len EQU 2
DMA1_CCR3_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR3_MSIZE_ofs EQU 10
DMA1_CCR3_MSIZE_len EQU 2
DMA1_CCR3_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR3_PL_ofs EQU 12
DMA1_CCR3_PL_len EQU 2
DMA1_CCR3_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR3_MEM2MEM_ofs EQU 14
DMA1_CCR3_MEM2MEM_len EQU 1
; DMA1_CNDTR3 fields:
DMA1_CNDTR3_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR3_NDT_ofs EQU 0
DMA1_CNDTR3_NDT_len EQU 16
; DMA1_CPAR3 fields:
DMA1_CPAR3_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR3_PA_ofs EQU 0
DMA1_CPAR3_PA_len EQU 32
; DMA1_CMAR3 fields:
DMA1_CMAR3_MA EQU 0xffffffff ; Memory address
DMA1_CMAR3_MA_ofs EQU 0
DMA1_CMAR3_MA_len EQU 32
; DMA1_CCR4 fields:
DMA1_CCR4_EN EQU 0x00000001 ; Channel enable
DMA1_CCR4_EN_ofs EQU 0
DMA1_CCR4_EN_len EQU 1
DMA1_CCR4_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR4_TCIE_ofs EQU 1
DMA1_CCR4_TCIE_len EQU 1
DMA1_CCR4_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR4_HTIE_ofs EQU 2
DMA1_CCR4_HTIE_len EQU 1
DMA1_CCR4_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR4_TEIE_ofs EQU 3
DMA1_CCR4_TEIE_len EQU 1
DMA1_CCR4_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR4_DIR_ofs EQU 4
DMA1_CCR4_DIR_len EQU 1
DMA1_CCR4_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR4_CIRC_ofs EQU 5
DMA1_CCR4_CIRC_len EQU 1
DMA1_CCR4_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR4_PINC_ofs EQU 6
DMA1_CCR4_PINC_len EQU 1
DMA1_CCR4_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR4_MINC_ofs EQU 7
DMA1_CCR4_MINC_len EQU 1
DMA1_CCR4_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR4_PSIZE_ofs EQU 8
DMA1_CCR4_PSIZE_len EQU 2
DMA1_CCR4_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR4_MSIZE_ofs EQU 10
DMA1_CCR4_MSIZE_len EQU 2
DMA1_CCR4_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR4_PL_ofs EQU 12
DMA1_CCR4_PL_len EQU 2
DMA1_CCR4_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR4_MEM2MEM_ofs EQU 14
DMA1_CCR4_MEM2MEM_len EQU 1
; DMA1_CNDTR4 fields:
DMA1_CNDTR4_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR4_NDT_ofs EQU 0
DMA1_CNDTR4_NDT_len EQU 16
; DMA1_CPAR4 fields:
DMA1_CPAR4_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR4_PA_ofs EQU 0
DMA1_CPAR4_PA_len EQU 32
; DMA1_CMAR4 fields:
DMA1_CMAR4_MA EQU 0xffffffff ; Memory address
DMA1_CMAR4_MA_ofs EQU 0
DMA1_CMAR4_MA_len EQU 32
; DMA1_CCR5 fields:
DMA1_CCR5_EN EQU 0x00000001 ; Channel enable
DMA1_CCR5_EN_ofs EQU 0
DMA1_CCR5_EN_len EQU 1
DMA1_CCR5_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR5_TCIE_ofs EQU 1
DMA1_CCR5_TCIE_len EQU 1
DMA1_CCR5_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR5_HTIE_ofs EQU 2
DMA1_CCR5_HTIE_len EQU 1
DMA1_CCR5_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR5_TEIE_ofs EQU 3
DMA1_CCR5_TEIE_len EQU 1
DMA1_CCR5_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR5_DIR_ofs EQU 4
DMA1_CCR5_DIR_len EQU 1
DMA1_CCR5_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR5_CIRC_ofs EQU 5
DMA1_CCR5_CIRC_len EQU 1
DMA1_CCR5_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR5_PINC_ofs EQU 6
DMA1_CCR5_PINC_len EQU 1
DMA1_CCR5_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR5_MINC_ofs EQU 7
DMA1_CCR5_MINC_len EQU 1
DMA1_CCR5_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR5_PSIZE_ofs EQU 8
DMA1_CCR5_PSIZE_len EQU 2
DMA1_CCR5_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR5_MSIZE_ofs EQU 10
DMA1_CCR5_MSIZE_len EQU 2
DMA1_CCR5_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR5_PL_ofs EQU 12
DMA1_CCR5_PL_len EQU 2
DMA1_CCR5_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR5_MEM2MEM_ofs EQU 14
DMA1_CCR5_MEM2MEM_len EQU 1
; DMA1_CNDTR5 fields:
DMA1_CNDTR5_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR5_NDT_ofs EQU 0
DMA1_CNDTR5_NDT_len EQU 16
; DMA1_CPAR5 fields:
DMA1_CPAR5_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR5_PA_ofs EQU 0
DMA1_CPAR5_PA_len EQU 32
; DMA1_CMAR5 fields:
DMA1_CMAR5_MA EQU 0xffffffff ; Memory address
DMA1_CMAR5_MA_ofs EQU 0
DMA1_CMAR5_MA_len EQU 32
; DMA1_CCR6 fields:
DMA1_CCR6_EN EQU 0x00000001 ; Channel enable
DMA1_CCR6_EN_ofs EQU 0
DMA1_CCR6_EN_len EQU 1
DMA1_CCR6_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR6_TCIE_ofs EQU 1
DMA1_CCR6_TCIE_len EQU 1
DMA1_CCR6_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR6_HTIE_ofs EQU 2
DMA1_CCR6_HTIE_len EQU 1
DMA1_CCR6_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR6_TEIE_ofs EQU 3
DMA1_CCR6_TEIE_len EQU 1
DMA1_CCR6_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR6_DIR_ofs EQU 4
DMA1_CCR6_DIR_len EQU 1
DMA1_CCR6_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR6_CIRC_ofs EQU 5
DMA1_CCR6_CIRC_len EQU 1
DMA1_CCR6_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR6_PINC_ofs EQU 6
DMA1_CCR6_PINC_len EQU 1
DMA1_CCR6_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR6_MINC_ofs EQU 7
DMA1_CCR6_MINC_len EQU 1
DMA1_CCR6_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR6_PSIZE_ofs EQU 8
DMA1_CCR6_PSIZE_len EQU 2
DMA1_CCR6_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR6_MSIZE_ofs EQU 10
DMA1_CCR6_MSIZE_len EQU 2
DMA1_CCR6_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR6_PL_ofs EQU 12
DMA1_CCR6_PL_len EQU 2
DMA1_CCR6_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR6_MEM2MEM_ofs EQU 14
DMA1_CCR6_MEM2MEM_len EQU 1
; DMA1_CNDTR6 fields:
DMA1_CNDTR6_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR6_NDT_ofs EQU 0
DMA1_CNDTR6_NDT_len EQU 16
; DMA1_CPAR6 fields:
DMA1_CPAR6_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR6_PA_ofs EQU 0
DMA1_CPAR6_PA_len EQU 32
; DMA1_CMAR6 fields:
DMA1_CMAR6_MA EQU 0xffffffff ; Memory address
DMA1_CMAR6_MA_ofs EQU 0
DMA1_CMAR6_MA_len EQU 32
; DMA1_CCR7 fields:
DMA1_CCR7_EN EQU 0x00000001 ; Channel enable
DMA1_CCR7_EN_ofs EQU 0
DMA1_CCR7_EN_len EQU 1
DMA1_CCR7_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR7_TCIE_ofs EQU 1
DMA1_CCR7_TCIE_len EQU 1
DMA1_CCR7_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR7_HTIE_ofs EQU 2
DMA1_CCR7_HTIE_len EQU 1
DMA1_CCR7_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR7_TEIE_ofs EQU 3
DMA1_CCR7_TEIE_len EQU 1
DMA1_CCR7_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR7_DIR_ofs EQU 4
DMA1_CCR7_DIR_len EQU 1
DMA1_CCR7_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR7_CIRC_ofs EQU 5
DMA1_CCR7_CIRC_len EQU 1
DMA1_CCR7_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR7_PINC_ofs EQU 6
DMA1_CCR7_PINC_len EQU 1
DMA1_CCR7_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR7_MINC_ofs EQU 7
DMA1_CCR7_MINC_len EQU 1
DMA1_CCR7_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR7_PSIZE_ofs EQU 8
DMA1_CCR7_PSIZE_len EQU 2
DMA1_CCR7_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR7_MSIZE_ofs EQU 10
DMA1_CCR7_MSIZE_len EQU 2
DMA1_CCR7_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR7_PL_ofs EQU 12
DMA1_CCR7_PL_len EQU 2
DMA1_CCR7_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR7_MEM2MEM_ofs EQU 14
DMA1_CCR7_MEM2MEM_len EQU 1
; DMA1_CNDTR7 fields:
DMA1_CNDTR7_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR7_NDT_ofs EQU 0
DMA1_CNDTR7_NDT_len EQU 16
; DMA1_CPAR7 fields:
DMA1_CPAR7_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR7_PA_ofs EQU 0
DMA1_CPAR7_PA_len EQU 32
; DMA1_CMAR7 fields:
DMA1_CMAR7_MA EQU 0xffffffff ; Memory address
DMA1_CMAR7_MA_ofs EQU 0
DMA1_CMAR7_MA_len EQU 32
; ---- DMA2 --------------------------------------------------
; Desc: None
; DMA2 base address:
DMA2_BASE EQU 0x40020400
; DMA2 registers:
; ---- TIM2 --------------------------------------------------
; Desc: General purpose timer
; TIM2 base address:
TIM2_BASE EQU 0x40000000
; TIM2 registers:
TIM2_CR1 EQU (TIM2_BASE + 0x0) ; control register 1
TIM2_CR2 EQU (TIM2_BASE + 0x4) ; control register 2
TIM2_SMCR EQU (TIM2_BASE + 0x8) ; slave mode control register
TIM2_DIER EQU (TIM2_BASE + 0xc) ; DMA/Interrupt enable register
TIM2_SR EQU (TIM2_BASE + 0x10) ; status register
TIM2_EGR EQU (TIM2_BASE + 0x14) ; event generation register
TIM2_CCMR1_Output EQU (TIM2_BASE + 0x18) ; capture/compare mode register 1 (output mode)
TIM2_CCMR1_Input EQU (TIM2_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM2_CCMR2_Output EQU (TIM2_BASE + 0x1c) ; capture/compare mode register 2 (output mode)
TIM2_CCMR2_Input EQU (TIM2_BASE + 0x1c) ; capture/compare mode register 2 (input mode)
TIM2_CCER EQU (TIM2_BASE + 0x20) ; capture/compare enable register
TIM2_CNT EQU (TIM2_BASE + 0x24) ; counter
TIM2_PSC EQU (TIM2_BASE + 0x28) ; prescaler
TIM2_ARR EQU (TIM2_BASE + 0x2c) ; auto-reload register
TIM2_CCR1 EQU (TIM2_BASE + 0x34) ; capture/compare register 1
TIM2_CCR2 EQU (TIM2_BASE + 0x38) ; capture/compare register 2
TIM2_CCR3 EQU (TIM2_BASE + 0x3c) ; capture/compare register 3
TIM2_CCR4 EQU (TIM2_BASE + 0x40) ; capture/compare register 4
TIM2_DCR EQU (TIM2_BASE + 0x48) ; DMA control register
TIM2_DMAR EQU (TIM2_BASE + 0x4c) ; DMA address for full transfer
; TIM2_CR1 fields:
TIM2_CR1_CEN EQU 0x00000001 ; Counter enable
TIM2_CR1_CEN_ofs EQU 0
TIM2_CR1_CEN_len EQU 1
TIM2_CR1_UDIS EQU 0x00000002 ; Update disable
TIM2_CR1_UDIS_ofs EQU 1
TIM2_CR1_UDIS_len EQU 1
TIM2_CR1_URS EQU 0x00000004 ; Update request source
TIM2_CR1_URS_ofs EQU 2
TIM2_CR1_URS_len EQU 1
TIM2_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM2_CR1_OPM_ofs EQU 3
TIM2_CR1_OPM_len EQU 1
TIM2_CR1_DIR EQU 0x00000010 ; Direction
TIM2_CR1_DIR_ofs EQU 4
TIM2_CR1_DIR_len EQU 1
TIM2_CR1_CMS EQU 0x00000060 ; Center-aligned mode selection
TIM2_CR1_CMS_ofs EQU 5
TIM2_CR1_CMS_len EQU 2
TIM2_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM2_CR1_ARPE_ofs EQU 7
TIM2_CR1_ARPE_len EQU 1
TIM2_CR1_CKD EQU 0x00000300 ; Clock division
TIM2_CR1_CKD_ofs EQU 8
TIM2_CR1_CKD_len EQU 2
TIM2_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM2_CR1_UIFREMAP_ofs EQU 11
TIM2_CR1_UIFREMAP_len EQU 1
; TIM2_CR2 fields:
TIM2_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM2_CR2_TI1S_ofs EQU 7
TIM2_CR2_TI1S_len EQU 1
TIM2_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM2_CR2_MMS_ofs EQU 4
TIM2_CR2_MMS_len EQU 3
TIM2_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM2_CR2_CCDS_ofs EQU 3
TIM2_CR2_CCDS_len EQU 1
; TIM2_SMCR fields:
TIM2_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM2_SMCR_SMS_ofs EQU 0
TIM2_SMCR_SMS_len EQU 3
TIM2_SMCR_OCCS EQU 0x00000008 ; OCREF clear selection
TIM2_SMCR_OCCS_ofs EQU 3
TIM2_SMCR_OCCS_len EQU 1
TIM2_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM2_SMCR_TS_ofs EQU 4
TIM2_SMCR_TS_len EQU 3
TIM2_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM2_SMCR_MSM_ofs EQU 7
TIM2_SMCR_MSM_len EQU 1
TIM2_SMCR_ETF EQU 0x00000f00 ; External trigger filter
TIM2_SMCR_ETF_ofs EQU 8
TIM2_SMCR_ETF_len EQU 4
TIM2_SMCR_ETPS EQU 0x00003000 ; External trigger prescaler
TIM2_SMCR_ETPS_ofs EQU 12
TIM2_SMCR_ETPS_len EQU 2
TIM2_SMCR_ECE EQU 0x00004000 ; External clock enable
TIM2_SMCR_ECE_ofs EQU 14
TIM2_SMCR_ECE_len EQU 1
TIM2_SMCR_ETP EQU 0x00008000 ; External trigger polarity
TIM2_SMCR_ETP_ofs EQU 15
TIM2_SMCR_ETP_len EQU 1
TIM2_SMCR_SMS_3 EQU 0x00010000 ; Slave mode selection bit3
TIM2_SMCR_SMS_3_ofs EQU 16
TIM2_SMCR_SMS_3_len EQU 1
; TIM2_DIER fields:
TIM2_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM2_DIER_TDE_ofs EQU 14
TIM2_DIER_TDE_len EQU 1
TIM2_DIER_CC4DE EQU 0x00001000 ; Capture/Compare 4 DMA request enable
TIM2_DIER_CC4DE_ofs EQU 12
TIM2_DIER_CC4DE_len EQU 1
TIM2_DIER_CC3DE EQU 0x00000800 ; Capture/Compare 3 DMA request enable
TIM2_DIER_CC3DE_ofs EQU 11
TIM2_DIER_CC3DE_len EQU 1
TIM2_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM2_DIER_CC2DE_ofs EQU 10
TIM2_DIER_CC2DE_len EQU 1
TIM2_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM2_DIER_CC1DE_ofs EQU 9
TIM2_DIER_CC1DE_len EQU 1
TIM2_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM2_DIER_UDE_ofs EQU 8
TIM2_DIER_UDE_len EQU 1
TIM2_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM2_DIER_TIE_ofs EQU 6
TIM2_DIER_TIE_len EQU 1
TIM2_DIER_CC4IE EQU 0x00000010 ; Capture/Compare 4 interrupt enable
TIM2_DIER_CC4IE_ofs EQU 4
TIM2_DIER_CC4IE_len EQU 1
TIM2_DIER_CC3IE EQU 0x00000008 ; Capture/Compare 3 interrupt enable
TIM2_DIER_CC3IE_ofs EQU 3
TIM2_DIER_CC3IE_len EQU 1
TIM2_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM2_DIER_CC2IE_ofs EQU 2
TIM2_DIER_CC2IE_len EQU 1
TIM2_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM2_DIER_CC1IE_ofs EQU 1
TIM2_DIER_CC1IE_len EQU 1
TIM2_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM2_DIER_UIE_ofs EQU 0
TIM2_DIER_UIE_len EQU 1
; TIM2_SR fields:
TIM2_SR_CC4OF EQU 0x00001000 ; Capture/Compare 4 overcapture flag
TIM2_SR_CC4OF_ofs EQU 12
TIM2_SR_CC4OF_len EQU 1
TIM2_SR_CC3OF EQU 0x00000800 ; Capture/Compare 3 overcapture flag
TIM2_SR_CC3OF_ofs EQU 11
TIM2_SR_CC3OF_len EQU 1
TIM2_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM2_SR_CC2OF_ofs EQU 10
TIM2_SR_CC2OF_len EQU 1
TIM2_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM2_SR_CC1OF_ofs EQU 9
TIM2_SR_CC1OF_len EQU 1
TIM2_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM2_SR_TIF_ofs EQU 6
TIM2_SR_TIF_len EQU 1
TIM2_SR_CC4IF EQU 0x00000010 ; Capture/Compare 4 interrupt flag
TIM2_SR_CC4IF_ofs EQU 4
TIM2_SR_CC4IF_len EQU 1
TIM2_SR_CC3IF EQU 0x00000008 ; Capture/Compare 3 interrupt flag
TIM2_SR_CC3IF_ofs EQU 3
TIM2_SR_CC3IF_len EQU 1
TIM2_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM2_SR_CC2IF_ofs EQU 2
TIM2_SR_CC2IF_len EQU 1
TIM2_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM2_SR_CC1IF_ofs EQU 1
TIM2_SR_CC1IF_len EQU 1
TIM2_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM2_SR_UIF_ofs EQU 0
TIM2_SR_UIF_len EQU 1
; TIM2_EGR fields:
TIM2_EGR_TG EQU 0x00000040 ; Trigger generation
TIM2_EGR_TG_ofs EQU 6
TIM2_EGR_TG_len EQU 1
TIM2_EGR_CC4G EQU 0x00000010 ; Capture/compare 4 generation
TIM2_EGR_CC4G_ofs EQU 4
TIM2_EGR_CC4G_len EQU 1
TIM2_EGR_CC3G EQU 0x00000008 ; Capture/compare 3 generation
TIM2_EGR_CC3G_ofs EQU 3
TIM2_EGR_CC3G_len EQU 1
TIM2_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM2_EGR_CC2G_ofs EQU 2
TIM2_EGR_CC2G_len EQU 1
TIM2_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM2_EGR_CC1G_ofs EQU 1
TIM2_EGR_CC1G_len EQU 1
TIM2_EGR_UG EQU 0x00000001 ; Update generation
TIM2_EGR_UG_ofs EQU 0
TIM2_EGR_UG_len EQU 1
; TIM2_CCMR1_Output fields:
TIM2_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM2_CCMR1_Output_CC1S_ofs EQU 0
TIM2_CCMR1_Output_CC1S_len EQU 2
TIM2_CCMR1_Output_OC1FE EQU 0x00000004 ; Output compare 1 fast enable
TIM2_CCMR1_Output_OC1FE_ofs EQU 2
TIM2_CCMR1_Output_OC1FE_len EQU 1
TIM2_CCMR1_Output_OC1PE EQU 0x00000008 ; Output compare 1 preload enable
TIM2_CCMR1_Output_OC1PE_ofs EQU 3
TIM2_CCMR1_Output_OC1PE_len EQU 1
TIM2_CCMR1_Output_OC1M EQU 0x00000070 ; Output compare 1 mode
TIM2_CCMR1_Output_OC1M_ofs EQU 4
TIM2_CCMR1_Output_OC1M_len EQU 3
TIM2_CCMR1_Output_OC1CE EQU 0x00000080 ; Output compare 1 clear enable
TIM2_CCMR1_Output_OC1CE_ofs EQU 7
TIM2_CCMR1_Output_OC1CE_len EQU 1
TIM2_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM2_CCMR1_Output_CC2S_ofs EQU 8
TIM2_CCMR1_Output_CC2S_len EQU 2
TIM2_CCMR1_Output_OC2FE EQU 0x00000400 ; Output compare 2 fast enable
TIM2_CCMR1_Output_OC2FE_ofs EQU 10
TIM2_CCMR1_Output_OC2FE_len EQU 1
TIM2_CCMR1_Output_OC2PE EQU 0x00000800 ; Output compare 2 preload enable
TIM2_CCMR1_Output_OC2PE_ofs EQU 11
TIM2_CCMR1_Output_OC2PE_len EQU 1
TIM2_CCMR1_Output_OC2M EQU 0x00007000 ; Output compare 2 mode
TIM2_CCMR1_Output_OC2M_ofs EQU 12
TIM2_CCMR1_Output_OC2M_len EQU 3
TIM2_CCMR1_Output_OC2CE EQU 0x00008000 ; Output compare 2 clear enable
TIM2_CCMR1_Output_OC2CE_ofs EQU 15
TIM2_CCMR1_Output_OC2CE_len EQU 1
TIM2_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output compare 1 mode bit 3
TIM2_CCMR1_Output_OC1M_3_ofs EQU 16
TIM2_CCMR1_Output_OC1M_3_len EQU 1
TIM2_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output compare 2 mode bit 3
TIM2_CCMR1_Output_OC2M_3_ofs EQU 24
TIM2_CCMR1_Output_OC2M_3_len EQU 1
; TIM2_CCMR1_Input fields:
TIM2_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM2_CCMR1_Input_IC2F_ofs EQU 12
TIM2_CCMR1_Input_IC2F_len EQU 4
TIM2_CCMR1_Input_IC2PSC EQU 0x00000c00 ; Input capture 2 prescaler
TIM2_CCMR1_Input_IC2PSC_ofs EQU 10
TIM2_CCMR1_Input_IC2PSC_len EQU 2
TIM2_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/compare 2 selection
TIM2_CCMR1_Input_CC2S_ofs EQU 8
TIM2_CCMR1_Input_CC2S_len EQU 2
TIM2_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM2_CCMR1_Input_IC1F_ofs EQU 4
TIM2_CCMR1_Input_IC1F_len EQU 4
TIM2_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM2_CCMR1_Input_IC1PSC_ofs EQU 2
TIM2_CCMR1_Input_IC1PSC_len EQU 2
TIM2_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM2_CCMR1_Input_CC1S_ofs EQU 0
TIM2_CCMR1_Input_CC1S_len EQU 2
; TIM2_CCMR2_Output fields:
TIM2_CCMR2_Output_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM2_CCMR2_Output_CC3S_ofs EQU 0
TIM2_CCMR2_Output_CC3S_len EQU 2
TIM2_CCMR2_Output_OC3FE EQU 0x00000004 ; Output compare 3 fast enable
TIM2_CCMR2_Output_OC3FE_ofs EQU 2
TIM2_CCMR2_Output_OC3FE_len EQU 1
TIM2_CCMR2_Output_OC3PE EQU 0x00000008 ; Output compare 3 preload enable
TIM2_CCMR2_Output_OC3PE_ofs EQU 3
TIM2_CCMR2_Output_OC3PE_len EQU 1
TIM2_CCMR2_Output_OC3M EQU 0x00000070 ; Output compare 3 mode
TIM2_CCMR2_Output_OC3M_ofs EQU 4
TIM2_CCMR2_Output_OC3M_len EQU 3
TIM2_CCMR2_Output_OC3CE EQU 0x00000080 ; Output compare 3 clear enable
TIM2_CCMR2_Output_OC3CE_ofs EQU 7
TIM2_CCMR2_Output_OC3CE_len EQU 1
TIM2_CCMR2_Output_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM2_CCMR2_Output_CC4S_ofs EQU 8
TIM2_CCMR2_Output_CC4S_len EQU 2
TIM2_CCMR2_Output_OC4FE EQU 0x00000400 ; Output compare 4 fast enable
TIM2_CCMR2_Output_OC4FE_ofs EQU 10
TIM2_CCMR2_Output_OC4FE_len EQU 1
TIM2_CCMR2_Output_OC4PE EQU 0x00000800 ; Output compare 4 preload enable
TIM2_CCMR2_Output_OC4PE_ofs EQU 11
TIM2_CCMR2_Output_OC4PE_len EQU 1
TIM2_CCMR2_Output_OC4M EQU 0x00007000 ; Output compare 4 mode
TIM2_CCMR2_Output_OC4M_ofs EQU 12
TIM2_CCMR2_Output_OC4M_len EQU 3
TIM2_CCMR2_Output_O24CE EQU 0x00008000 ; Output compare 4 clear enable
TIM2_CCMR2_Output_O24CE_ofs EQU 15
TIM2_CCMR2_Output_O24CE_len EQU 1
TIM2_CCMR2_Output_OC3M_3 EQU 0x00010000 ; Output compare 3 mode bit3
TIM2_CCMR2_Output_OC3M_3_ofs EQU 16
TIM2_CCMR2_Output_OC3M_3_len EQU 1
TIM2_CCMR2_Output_OC4M_3 EQU 0x01000000 ; Output compare 4 mode bit3
TIM2_CCMR2_Output_OC4M_3_ofs EQU 24
TIM2_CCMR2_Output_OC4M_3_len EQU 1
; TIM2_CCMR2_Input fields:
TIM2_CCMR2_Input_IC4F EQU 0x0000f000 ; Input capture 4 filter
TIM2_CCMR2_Input_IC4F_ofs EQU 12
TIM2_CCMR2_Input_IC4F_len EQU 4
TIM2_CCMR2_Input_IC4PSC EQU 0x00000c00 ; Input capture 4 prescaler
TIM2_CCMR2_Input_IC4PSC_ofs EQU 10
TIM2_CCMR2_Input_IC4PSC_len EQU 2
TIM2_CCMR2_Input_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM2_CCMR2_Input_CC4S_ofs EQU 8
TIM2_CCMR2_Input_CC4S_len EQU 2
TIM2_CCMR2_Input_IC3F EQU 0x000000f0 ; Input capture 3 filter
TIM2_CCMR2_Input_IC3F_ofs EQU 4
TIM2_CCMR2_Input_IC3F_len EQU 4
TIM2_CCMR2_Input_IC3PSC EQU 0x0000000c ; Input capture 3 prescaler
TIM2_CCMR2_Input_IC3PSC_ofs EQU 2
TIM2_CCMR2_Input_IC3PSC_len EQU 2
TIM2_CCMR2_Input_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM2_CCMR2_Input_CC3S_ofs EQU 0
TIM2_CCMR2_Input_CC3S_len EQU 2
; TIM2_CCER fields:
TIM2_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM2_CCER_CC1E_ofs EQU 0
TIM2_CCER_CC1E_len EQU 1
TIM2_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM2_CCER_CC1P_ofs EQU 1
TIM2_CCER_CC1P_len EQU 1
TIM2_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM2_CCER_CC1NP_ofs EQU 3
TIM2_CCER_CC1NP_len EQU 1
TIM2_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM2_CCER_CC2E_ofs EQU 4
TIM2_CCER_CC2E_len EQU 1
TIM2_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM2_CCER_CC2P_ofs EQU 5
TIM2_CCER_CC2P_len EQU 1
TIM2_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM2_CCER_CC2NP_ofs EQU 7
TIM2_CCER_CC2NP_len EQU 1
TIM2_CCER_CC3E EQU 0x00000100 ; Capture/Compare 3 output enable
TIM2_CCER_CC3E_ofs EQU 8
TIM2_CCER_CC3E_len EQU 1
TIM2_CCER_CC3P EQU 0x00000200 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC3P_ofs EQU 9
TIM2_CCER_CC3P_len EQU 1
TIM2_CCER_CC3NP EQU 0x00000800 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC3NP_ofs EQU 11
TIM2_CCER_CC3NP_len EQU 1
TIM2_CCER_CC4E EQU 0x00001000 ; Capture/Compare 4 output enable
TIM2_CCER_CC4E_ofs EQU 12
TIM2_CCER_CC4E_len EQU 1
TIM2_CCER_CC4P EQU 0x00002000 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC4P_ofs EQU 13
TIM2_CCER_CC4P_len EQU 1
TIM2_CCER_CC4NP EQU 0x00008000 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC4NP_ofs EQU 15
TIM2_CCER_CC4NP_len EQU 1
; TIM2_CNT fields:
TIM2_CNT_CNTL EQU 0x0000ffff ; Low counter value
TIM2_CNT_CNTL_ofs EQU 0
TIM2_CNT_CNTL_len EQU 16
TIM2_CNT_CNTH EQU 0x7fff0000 ; High counter value
TIM2_CNT_CNTH_ofs EQU 16
TIM2_CNT_CNTH_len EQU 15
TIM2_CNT_CNT_or_UIFCPY EQU 0x80000000 ; if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access
TIM2_CNT_CNT_or_UIFCPY_ofs EQU 31
TIM2_CNT_CNT_or_UIFCPY_len EQU 1
; TIM2_PSC fields:
TIM2_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM2_PSC_PSC_ofs EQU 0
TIM2_PSC_PSC_len EQU 16
; TIM2_ARR fields:
TIM2_ARR_ARRL EQU 0x0000ffff ; Low Auto-reload value
TIM2_ARR_ARRL_ofs EQU 0
TIM2_ARR_ARRL_len EQU 16
TIM2_ARR_ARRH EQU 0xffff0000 ; High Auto-reload value
TIM2_ARR_ARRH_ofs EQU 16
TIM2_ARR_ARRH_len EQU 16
; TIM2_CCR1 fields:
TIM2_CCR1_CCR1L EQU 0x0000ffff ; Low Capture/Compare 1 value
TIM2_CCR1_CCR1L_ofs EQU 0
TIM2_CCR1_CCR1L_len EQU 16
TIM2_CCR1_CCR1H EQU 0xffff0000 ; High Capture/Compare 1 value (on TIM2)
TIM2_CCR1_CCR1H_ofs EQU 16
TIM2_CCR1_CCR1H_len EQU 16
; TIM2_CCR2 fields:
TIM2_CCR2_CCR2L EQU 0x0000ffff ; Low Capture/Compare 2 value
TIM2_CCR2_CCR2L_ofs EQU 0
TIM2_CCR2_CCR2L_len EQU 16
TIM2_CCR2_CCR2H EQU 0xffff0000 ; High Capture/Compare 2 value (on TIM2)
TIM2_CCR2_CCR2H_ofs EQU 16
TIM2_CCR2_CCR2H_len EQU 16
; TIM2_CCR3 fields:
TIM2_CCR3_CCR3L EQU 0x0000ffff ; Low Capture/Compare value
TIM2_CCR3_CCR3L_ofs EQU 0
TIM2_CCR3_CCR3L_len EQU 16
TIM2_CCR3_CCR3H EQU 0xffff0000 ; High Capture/Compare value (on TIM2)
TIM2_CCR3_CCR3H_ofs EQU 16
TIM2_CCR3_CCR3H_len EQU 16
; TIM2_CCR4 fields:
TIM2_CCR4_CCR4L EQU 0x0000ffff ; Low Capture/Compare value
TIM2_CCR4_CCR4L_ofs EQU 0
TIM2_CCR4_CCR4L_len EQU 16
TIM2_CCR4_CCR4H EQU 0xffff0000 ; High Capture/Compare value (on TIM2)
TIM2_CCR4_CCR4H_ofs EQU 16
TIM2_CCR4_CCR4H_len EQU 16
; TIM2_DCR fields:
TIM2_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM2_DCR_DBL_ofs EQU 8
TIM2_DCR_DBL_len EQU 5
TIM2_DCR_DBA EQU 0x0000001f ; DMA base address
TIM2_DCR_DBA_ofs EQU 0
TIM2_DCR_DBA_len EQU 5
; TIM2_DMAR fields:
TIM2_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM2_DMAR_DMAB_ofs EQU 0
TIM2_DMAR_DMAB_len EQU 16
; ---- TIM3 --------------------------------------------------
; Desc: None
; TIM3 base address:
TIM3_BASE EQU 0x40000400
; TIM3 registers:
; ---- TIM4 --------------------------------------------------
; Desc: None
; TIM4 base address:
TIM4_BASE EQU 0x40000800
; TIM4 registers:
; ---- TIM15 -------------------------------------------------
; Desc: General purpose timers
; TIM15 base address:
TIM15_BASE EQU 0x40014000
; TIM15 registers:
TIM15_CR1 EQU (TIM15_BASE + 0x0) ; control register 1
TIM15_CR2 EQU (TIM15_BASE + 0x4) ; control register 2
TIM15_SMCR EQU (TIM15_BASE + 0x8) ; slave mode control register
TIM15_DIER EQU (TIM15_BASE + 0xc) ; DMA/Interrupt enable register
TIM15_SR EQU (TIM15_BASE + 0x10) ; status register
TIM15_EGR EQU (TIM15_BASE + 0x14) ; event generation register
TIM15_CCMR1_Output EQU (TIM15_BASE + 0x18) ; capture/compare mode register (output mode)
TIM15_CCMR1_Input EQU (TIM15_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM15_CCER EQU (TIM15_BASE + 0x20) ; capture/compare enable register
TIM15_CNT EQU (TIM15_BASE + 0x24) ; counter
TIM15_PSC EQU (TIM15_BASE + 0x28) ; prescaler
TIM15_ARR EQU (TIM15_BASE + 0x2c) ; auto-reload register
TIM15_RCR EQU (TIM15_BASE + 0x30) ; repetition counter register
TIM15_CCR1 EQU (TIM15_BASE + 0x34) ; capture/compare register 1
TIM15_CCR2 EQU (TIM15_BASE + 0x38) ; capture/compare register 2
TIM15_BDTR EQU (TIM15_BASE + 0x44) ; break and dead-time register
TIM15_DCR EQU (TIM15_BASE + 0x48) ; DMA control register
TIM15_DMAR EQU (TIM15_BASE + 0x4c) ; DMA address for full transfer
; TIM15_CR1 fields:
TIM15_CR1_CEN EQU 0x00000001 ; Counter enable
TIM15_CR1_CEN_ofs EQU 0
TIM15_CR1_CEN_len EQU 1
TIM15_CR1_UDIS EQU 0x00000002 ; Update disable
TIM15_CR1_UDIS_ofs EQU 1
TIM15_CR1_UDIS_len EQU 1
TIM15_CR1_URS EQU 0x00000004 ; Update request source
TIM15_CR1_URS_ofs EQU 2
TIM15_CR1_URS_len EQU 1
TIM15_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM15_CR1_OPM_ofs EQU 3
TIM15_CR1_OPM_len EQU 1
TIM15_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM15_CR1_ARPE_ofs EQU 7
TIM15_CR1_ARPE_len EQU 1
TIM15_CR1_CKD EQU 0x00000300 ; Clock division
TIM15_CR1_CKD_ofs EQU 8
TIM15_CR1_CKD_len EQU 2
TIM15_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM15_CR1_UIFREMAP_ofs EQU 11
TIM15_CR1_UIFREMAP_len EQU 1
; TIM15_CR2 fields:
TIM15_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM15_CR2_CCPC_ofs EQU 0
TIM15_CR2_CCPC_len EQU 1
TIM15_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM15_CR2_CCUS_ofs EQU 2
TIM15_CR2_CCUS_len EQU 1
TIM15_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM15_CR2_CCDS_ofs EQU 3
TIM15_CR2_CCDS_len EQU 1
TIM15_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM15_CR2_MMS_ofs EQU 4
TIM15_CR2_MMS_len EQU 3
TIM15_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM15_CR2_TI1S_ofs EQU 7
TIM15_CR2_TI1S_len EQU 1
TIM15_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM15_CR2_OIS1_ofs EQU 8
TIM15_CR2_OIS1_len EQU 1
TIM15_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM15_CR2_OIS1N_ofs EQU 9
TIM15_CR2_OIS1N_len EQU 1
TIM15_CR2_OIS2 EQU 0x00000400 ; Output Idle state 2
TIM15_CR2_OIS2_ofs EQU 10
TIM15_CR2_OIS2_len EQU 1
; TIM15_SMCR fields:
TIM15_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM15_SMCR_SMS_ofs EQU 0
TIM15_SMCR_SMS_len EQU 3
TIM15_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM15_SMCR_TS_ofs EQU 4
TIM15_SMCR_TS_len EQU 3
TIM15_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM15_SMCR_MSM_ofs EQU 7
TIM15_SMCR_MSM_len EQU 1
TIM15_SMCR_SMS_3 EQU 0x00010000 ; Slave mode selection bit 3
TIM15_SMCR_SMS_3_ofs EQU 16
TIM15_SMCR_SMS_3_len EQU 1
; TIM15_DIER fields:
TIM15_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM15_DIER_UIE_ofs EQU 0
TIM15_DIER_UIE_len EQU 1
TIM15_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM15_DIER_CC1IE_ofs EQU 1
TIM15_DIER_CC1IE_len EQU 1
TIM15_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM15_DIER_CC2IE_ofs EQU 2
TIM15_DIER_CC2IE_len EQU 1
TIM15_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM15_DIER_COMIE_ofs EQU 5
TIM15_DIER_COMIE_len EQU 1
TIM15_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM15_DIER_TIE_ofs EQU 6
TIM15_DIER_TIE_len EQU 1
TIM15_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM15_DIER_BIE_ofs EQU 7
TIM15_DIER_BIE_len EQU 1
TIM15_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM15_DIER_UDE_ofs EQU 8
TIM15_DIER_UDE_len EQU 1
TIM15_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM15_DIER_CC1DE_ofs EQU 9
TIM15_DIER_CC1DE_len EQU 1
TIM15_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM15_DIER_CC2DE_ofs EQU 10
TIM15_DIER_CC2DE_len EQU 1
TIM15_DIER_COMDE EQU 0x00002000 ; COM DMA request enable
TIM15_DIER_COMDE_ofs EQU 13
TIM15_DIER_COMDE_len EQU 1
TIM15_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM15_DIER_TDE_ofs EQU 14
TIM15_DIER_TDE_len EQU 1
; TIM15_SR fields:
TIM15_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM15_SR_CC2OF_ofs EQU 10
TIM15_SR_CC2OF_len EQU 1
TIM15_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM15_SR_CC1OF_ofs EQU 9
TIM15_SR_CC1OF_len EQU 1
TIM15_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM15_SR_BIF_ofs EQU 7
TIM15_SR_BIF_len EQU 1
TIM15_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM15_SR_TIF_ofs EQU 6
TIM15_SR_TIF_len EQU 1
TIM15_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM15_SR_COMIF_ofs EQU 5
TIM15_SR_COMIF_len EQU 1
TIM15_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM15_SR_CC2IF_ofs EQU 2
TIM15_SR_CC2IF_len EQU 1
TIM15_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM15_SR_CC1IF_ofs EQU 1
TIM15_SR_CC1IF_len EQU 1
TIM15_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM15_SR_UIF_ofs EQU 0
TIM15_SR_UIF_len EQU 1
; TIM15_EGR fields:
TIM15_EGR_BG EQU 0x00000080 ; Break generation
TIM15_EGR_BG_ofs EQU 7
TIM15_EGR_BG_len EQU 1
TIM15_EGR_TG EQU 0x00000040 ; Trigger generation
TIM15_EGR_TG_ofs EQU 6
TIM15_EGR_TG_len EQU 1
TIM15_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM15_EGR_COMG_ofs EQU 5
TIM15_EGR_COMG_len EQU 1
TIM15_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM15_EGR_CC2G_ofs EQU 2
TIM15_EGR_CC2G_len EQU 1
TIM15_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM15_EGR_CC1G_ofs EQU 1
TIM15_EGR_CC1G_len EQU 1
TIM15_EGR_UG EQU 0x00000001 ; Update generation
TIM15_EGR_UG_ofs EQU 0
TIM15_EGR_UG_len EQU 1
; TIM15_CCMR1_Output fields:
TIM15_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM15_CCMR1_Output_CC1S_ofs EQU 0
TIM15_CCMR1_Output_CC1S_len EQU 2
TIM15_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM15_CCMR1_Output_OC1FE_ofs EQU 2
TIM15_CCMR1_Output_OC1FE_len EQU 1
TIM15_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM15_CCMR1_Output_OC1PE_ofs EQU 3
TIM15_CCMR1_Output_OC1PE_len EQU 1
TIM15_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM15_CCMR1_Output_OC1M_ofs EQU 4
TIM15_CCMR1_Output_OC1M_len EQU 3
TIM15_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM15_CCMR1_Output_CC2S_ofs EQU 8
TIM15_CCMR1_Output_CC2S_len EQU 2
TIM15_CCMR1_Output_OC2FE EQU 0x00000400 ; Output Compare 2 fast enable
TIM15_CCMR1_Output_OC2FE_ofs EQU 10
TIM15_CCMR1_Output_OC2FE_len EQU 1
TIM15_CCMR1_Output_OC2PE EQU 0x00000800 ; Output Compare 2 preload enable
TIM15_CCMR1_Output_OC2PE_ofs EQU 11
TIM15_CCMR1_Output_OC2PE_len EQU 1
TIM15_CCMR1_Output_OC2M EQU 0x00007000 ; Output Compare 2 mode
TIM15_CCMR1_Output_OC2M_ofs EQU 12
TIM15_CCMR1_Output_OC2M_len EQU 3
TIM15_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode bit 3
TIM15_CCMR1_Output_OC1M_3_ofs EQU 16
TIM15_CCMR1_Output_OC1M_3_len EQU 1
TIM15_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output Compare 2 mode bit 3
TIM15_CCMR1_Output_OC2M_3_ofs EQU 24
TIM15_CCMR1_Output_OC2M_3_len EQU 1
; TIM15_CCMR1_Input fields:
TIM15_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM15_CCMR1_Input_IC2F_ofs EQU 12
TIM15_CCMR1_Input_IC2F_len EQU 4
TIM15_CCMR1_Input_IC2PSC EQU 0x00000c00 ; Input capture 2 prescaler
TIM15_CCMR1_Input_IC2PSC_ofs EQU 10
TIM15_CCMR1_Input_IC2PSC_len EQU 2
TIM15_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM15_CCMR1_Input_CC2S_ofs EQU 8
TIM15_CCMR1_Input_CC2S_len EQU 2
TIM15_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM15_CCMR1_Input_IC1F_ofs EQU 4
TIM15_CCMR1_Input_IC1F_len EQU 4
TIM15_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM15_CCMR1_Input_IC1PSC_ofs EQU 2
TIM15_CCMR1_Input_IC1PSC_len EQU 2
TIM15_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM15_CCMR1_Input_CC1S_ofs EQU 0
TIM15_CCMR1_Input_CC1S_len EQU 2
; TIM15_CCER fields:
TIM15_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM15_CCER_CC2NP_ofs EQU 7
TIM15_CCER_CC2NP_len EQU 1
TIM15_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM15_CCER_CC2P_ofs EQU 5
TIM15_CCER_CC2P_len EQU 1
TIM15_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM15_CCER_CC2E_ofs EQU 4
TIM15_CCER_CC2E_len EQU 1
TIM15_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM15_CCER_CC1NP_ofs EQU 3
TIM15_CCER_CC1NP_len EQU 1
TIM15_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM15_CCER_CC1NE_ofs EQU 2
TIM15_CCER_CC1NE_len EQU 1
TIM15_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM15_CCER_CC1P_ofs EQU 1
TIM15_CCER_CC1P_len EQU 1
TIM15_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM15_CCER_CC1E_ofs EQU 0
TIM15_CCER_CC1E_len EQU 1
; TIM15_CNT fields:
TIM15_CNT_CNT EQU 0x0000ffff ; counter value
TIM15_CNT_CNT_ofs EQU 0
TIM15_CNT_CNT_len EQU 16
TIM15_CNT_UIFCPY EQU 0x80000000 ; UIF copy
TIM15_CNT_UIFCPY_ofs EQU 31
TIM15_CNT_UIFCPY_len EQU 1
; TIM15_PSC fields:
TIM15_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM15_PSC_PSC_ofs EQU 0
TIM15_PSC_PSC_len EQU 16
; TIM15_ARR fields:
TIM15_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM15_ARR_ARR_ofs EQU 0
TIM15_ARR_ARR_len EQU 16
; TIM15_RCR fields:
TIM15_RCR_REP EQU 0x000000ff ; Repetition counter value
TIM15_RCR_REP_ofs EQU 0
TIM15_RCR_REP_len EQU 8
; TIM15_CCR1 fields:
TIM15_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM15_CCR1_CCR1_ofs EQU 0
TIM15_CCR1_CCR1_len EQU 16
; TIM15_CCR2 fields:
TIM15_CCR2_CCR2 EQU 0x0000ffff ; Capture/Compare 2 value
TIM15_CCR2_CCR2_ofs EQU 0
TIM15_CCR2_CCR2_len EQU 16
; TIM15_BDTR fields:
TIM15_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM15_BDTR_MOE_ofs EQU 15
TIM15_BDTR_MOE_len EQU 1
TIM15_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM15_BDTR_AOE_ofs EQU 14
TIM15_BDTR_AOE_len EQU 1
TIM15_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM15_BDTR_BKP_ofs EQU 13
TIM15_BDTR_BKP_len EQU 1
TIM15_BDTR_BKE EQU 0x00001000 ; Break enable
TIM15_BDTR_BKE_ofs EQU 12
TIM15_BDTR_BKE_len EQU 1
TIM15_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM15_BDTR_OSSR_ofs EQU 11
TIM15_BDTR_OSSR_len EQU 1
TIM15_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM15_BDTR_OSSI_ofs EQU 10
TIM15_BDTR_OSSI_len EQU 1
TIM15_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM15_BDTR_LOCK_ofs EQU 8
TIM15_BDTR_LOCK_len EQU 2
TIM15_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM15_BDTR_DTG_ofs EQU 0
TIM15_BDTR_DTG_len EQU 8
TIM15_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM15_BDTR_BKF_ofs EQU 16
TIM15_BDTR_BKF_len EQU 4
; TIM15_DCR fields:
TIM15_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM15_DCR_DBL_ofs EQU 8
TIM15_DCR_DBL_len EQU 5
TIM15_DCR_DBA EQU 0x0000001f ; DMA base address
TIM15_DCR_DBA_ofs EQU 0
TIM15_DCR_DBA_len EQU 5
; TIM15_DMAR fields:
TIM15_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM15_DMAR_DMAB_ofs EQU 0
TIM15_DMAR_DMAB_len EQU 16
; ---- TIM16 -------------------------------------------------
; Desc: General-purpose-timers
; TIM16 base address:
TIM16_BASE EQU 0x40014400
; TIM16 registers:
TIM16_CR1 EQU (TIM16_BASE + 0x0) ; control register 1
TIM16_CR2 EQU (TIM16_BASE + 0x4) ; control register 2
TIM16_DIER EQU (TIM16_BASE + 0xc) ; DMA/Interrupt enable register
TIM16_SR EQU (TIM16_BASE + 0x10) ; status register
TIM16_EGR EQU (TIM16_BASE + 0x14) ; event generation register
TIM16_CCMR1_Output EQU (TIM16_BASE + 0x18) ; capture/compare mode register (output mode)
TIM16_CCMR1_Input EQU (TIM16_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM16_CCER EQU (TIM16_BASE + 0x20) ; capture/compare enable register
TIM16_CNT EQU (TIM16_BASE + 0x24) ; counter
TIM16_PSC EQU (TIM16_BASE + 0x28) ; prescaler
TIM16_ARR EQU (TIM16_BASE + 0x2c) ; auto-reload register
TIM16_RCR EQU (TIM16_BASE + 0x30) ; repetition counter register
TIM16_CCR1 EQU (TIM16_BASE + 0x34) ; capture/compare register 1
TIM16_BDTR EQU (TIM16_BASE + 0x44) ; break and dead-time register
TIM16_DCR EQU (TIM16_BASE + 0x48) ; DMA control register
TIM16_DMAR EQU (TIM16_BASE + 0x4c) ; DMA address for full transfer
TIM16_OR EQU (TIM16_BASE + 0x50) ; option register
; TIM16_CR1 fields:
TIM16_CR1_CEN EQU 0x00000001 ; Counter enable
TIM16_CR1_CEN_ofs EQU 0
TIM16_CR1_CEN_len EQU 1
TIM16_CR1_UDIS EQU 0x00000002 ; Update disable
TIM16_CR1_UDIS_ofs EQU 1
TIM16_CR1_UDIS_len EQU 1
TIM16_CR1_URS EQU 0x00000004 ; Update request source
TIM16_CR1_URS_ofs EQU 2
TIM16_CR1_URS_len EQU 1
TIM16_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM16_CR1_OPM_ofs EQU 3
TIM16_CR1_OPM_len EQU 1
TIM16_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM16_CR1_ARPE_ofs EQU 7
TIM16_CR1_ARPE_len EQU 1
TIM16_CR1_CKD EQU 0x00000300 ; Clock division
TIM16_CR1_CKD_ofs EQU 8
TIM16_CR1_CKD_len EQU 2
TIM16_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM16_CR1_UIFREMAP_ofs EQU 11
TIM16_CR1_UIFREMAP_len EQU 1
; TIM16_CR2 fields:
TIM16_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM16_CR2_OIS1N_ofs EQU 9
TIM16_CR2_OIS1N_len EQU 1
TIM16_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM16_CR2_OIS1_ofs EQU 8
TIM16_CR2_OIS1_len EQU 1
TIM16_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM16_CR2_CCDS_ofs EQU 3
TIM16_CR2_CCDS_len EQU 1
TIM16_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM16_CR2_CCUS_ofs EQU 2
TIM16_CR2_CCUS_len EQU 1
TIM16_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM16_CR2_CCPC_ofs EQU 0
TIM16_CR2_CCPC_len EQU 1
; TIM16_DIER fields:
TIM16_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM16_DIER_UIE_ofs EQU 0
TIM16_DIER_UIE_len EQU 1
TIM16_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM16_DIER_CC1IE_ofs EQU 1
TIM16_DIER_CC1IE_len EQU 1
TIM16_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM16_DIER_COMIE_ofs EQU 5
TIM16_DIER_COMIE_len EQU 1
TIM16_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM16_DIER_TIE_ofs EQU 6
TIM16_DIER_TIE_len EQU 1
TIM16_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM16_DIER_BIE_ofs EQU 7
TIM16_DIER_BIE_len EQU 1
TIM16_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM16_DIER_UDE_ofs EQU 8
TIM16_DIER_UDE_len EQU 1
TIM16_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM16_DIER_CC1DE_ofs EQU 9
TIM16_DIER_CC1DE_len EQU 1
TIM16_DIER_COMDE EQU 0x00002000 ; COM DMA request enable
TIM16_DIER_COMDE_ofs EQU 13
TIM16_DIER_COMDE_len EQU 1
TIM16_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM16_DIER_TDE_ofs EQU 14
TIM16_DIER_TDE_len EQU 1
; TIM16_SR fields:
TIM16_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM16_SR_CC1OF_ofs EQU 9
TIM16_SR_CC1OF_len EQU 1
TIM16_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM16_SR_BIF_ofs EQU 7
TIM16_SR_BIF_len EQU 1
TIM16_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM16_SR_TIF_ofs EQU 6
TIM16_SR_TIF_len EQU 1
TIM16_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM16_SR_COMIF_ofs EQU 5
TIM16_SR_COMIF_len EQU 1
TIM16_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM16_SR_CC1IF_ofs EQU 1
TIM16_SR_CC1IF_len EQU 1
TIM16_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM16_SR_UIF_ofs EQU 0
TIM16_SR_UIF_len EQU 1
; TIM16_EGR fields:
TIM16_EGR_BG EQU 0x00000080 ; Break generation
TIM16_EGR_BG_ofs EQU 7
TIM16_EGR_BG_len EQU 1
TIM16_EGR_TG EQU 0x00000040 ; Trigger generation
TIM16_EGR_TG_ofs EQU 6
TIM16_EGR_TG_len EQU 1
TIM16_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM16_EGR_COMG_ofs EQU 5
TIM16_EGR_COMG_len EQU 1
TIM16_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM16_EGR_CC1G_ofs EQU 1
TIM16_EGR_CC1G_len EQU 1
TIM16_EGR_UG EQU 0x00000001 ; Update generation
TIM16_EGR_UG_ofs EQU 0
TIM16_EGR_UG_len EQU 1
; TIM16_CCMR1_Output fields:
TIM16_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM16_CCMR1_Output_CC1S_ofs EQU 0
TIM16_CCMR1_Output_CC1S_len EQU 2
TIM16_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM16_CCMR1_Output_OC1FE_ofs EQU 2
TIM16_CCMR1_Output_OC1FE_len EQU 1
TIM16_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM16_CCMR1_Output_OC1PE_ofs EQU 3
TIM16_CCMR1_Output_OC1PE_len EQU 1
TIM16_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM16_CCMR1_Output_OC1M_ofs EQU 4
TIM16_CCMR1_Output_OC1M_len EQU 3
TIM16_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode
TIM16_CCMR1_Output_OC1M_3_ofs EQU 16
TIM16_CCMR1_Output_OC1M_3_len EQU 1
; TIM16_CCMR1_Input fields:
TIM16_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM16_CCMR1_Input_IC1F_ofs EQU 4
TIM16_CCMR1_Input_IC1F_len EQU 4
TIM16_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM16_CCMR1_Input_IC1PSC_ofs EQU 2
TIM16_CCMR1_Input_IC1PSC_len EQU 2
TIM16_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM16_CCMR1_Input_CC1S_ofs EQU 0
TIM16_CCMR1_Input_CC1S_len EQU 2
; TIM16_CCER fields:
TIM16_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM16_CCER_CC1NP_ofs EQU 3
TIM16_CCER_CC1NP_len EQU 1
TIM16_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM16_CCER_CC1NE_ofs EQU 2
TIM16_CCER_CC1NE_len EQU 1
TIM16_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM16_CCER_CC1P_ofs EQU 1
TIM16_CCER_CC1P_len EQU 1
TIM16_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM16_CCER_CC1E_ofs EQU 0
TIM16_CCER_CC1E_len EQU 1
; TIM16_CNT fields:
TIM16_CNT_CNT EQU 0x0000ffff ; counter value
TIM16_CNT_CNT_ofs EQU 0
TIM16_CNT_CNT_len EQU 16
TIM16_CNT_UIFCPY EQU 0x80000000 ; UIF Copy
TIM16_CNT_UIFCPY_ofs EQU 31
TIM16_CNT_UIFCPY_len EQU 1
; TIM16_PSC fields:
TIM16_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM16_PSC_PSC_ofs EQU 0
TIM16_PSC_PSC_len EQU 16
; TIM16_ARR fields:
TIM16_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM16_ARR_ARR_ofs EQU 0
TIM16_ARR_ARR_len EQU 16
; TIM16_RCR fields:
TIM16_RCR_REP EQU 0x000000ff ; Repetition counter value
TIM16_RCR_REP_ofs EQU 0
TIM16_RCR_REP_len EQU 8
; TIM16_CCR1 fields:
TIM16_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM16_CCR1_CCR1_ofs EQU 0
TIM16_CCR1_CCR1_len EQU 16
; TIM16_BDTR fields:
TIM16_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM16_BDTR_DTG_ofs EQU 0
TIM16_BDTR_DTG_len EQU 8
TIM16_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM16_BDTR_LOCK_ofs EQU 8
TIM16_BDTR_LOCK_len EQU 2
TIM16_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM16_BDTR_OSSI_ofs EQU 10
TIM16_BDTR_OSSI_len EQU 1
TIM16_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM16_BDTR_OSSR_ofs EQU 11
TIM16_BDTR_OSSR_len EQU 1
TIM16_BDTR_BKE EQU 0x00001000 ; Break enable
TIM16_BDTR_BKE_ofs EQU 12
TIM16_BDTR_BKE_len EQU 1
TIM16_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM16_BDTR_BKP_ofs EQU 13
TIM16_BDTR_BKP_len EQU 1
TIM16_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM16_BDTR_AOE_ofs EQU 14
TIM16_BDTR_AOE_len EQU 1
TIM16_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM16_BDTR_MOE_ofs EQU 15
TIM16_BDTR_MOE_len EQU 1
TIM16_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM16_BDTR_BKF_ofs EQU 16
TIM16_BDTR_BKF_len EQU 4
; TIM16_DCR fields:
TIM16_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM16_DCR_DBL_ofs EQU 8
TIM16_DCR_DBL_len EQU 5
TIM16_DCR_DBA EQU 0x0000001f ; DMA base address
TIM16_DCR_DBA_ofs EQU 0
TIM16_DCR_DBA_len EQU 5
; TIM16_DMAR fields:
TIM16_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM16_DMAR_DMAB_ofs EQU 0
TIM16_DMAR_DMAB_len EQU 16
; TIM16_OR fields:
; ---- TIM17 -------------------------------------------------
; Desc: General purpose timer
; TIM17 base address:
TIM17_BASE EQU 0x40014800
; TIM17 registers:
TIM17_CR1 EQU (TIM17_BASE + 0x0) ; control register 1
TIM17_CR2 EQU (TIM17_BASE + 0x4) ; control register 2
TIM17_DIER EQU (TIM17_BASE + 0xc) ; DMA/Interrupt enable register
TIM17_SR EQU (TIM17_BASE + 0x10) ; status register
TIM17_EGR EQU (TIM17_BASE + 0x14) ; event generation register
TIM17_CCMR1_Output EQU (TIM17_BASE + 0x18) ; capture/compare mode register (output mode)
TIM17_CCMR1_Input EQU (TIM17_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM17_CCER EQU (TIM17_BASE + 0x20) ; capture/compare enable register
TIM17_CNT EQU (TIM17_BASE + 0x24) ; counter
TIM17_PSC EQU (TIM17_BASE + 0x28) ; prescaler
TIM17_ARR EQU (TIM17_BASE + 0x2c) ; auto-reload register
TIM17_RCR EQU (TIM17_BASE + 0x30) ; repetition counter register
TIM17_CCR1 EQU (TIM17_BASE + 0x34) ; capture/compare register 1
TIM17_BDTR EQU (TIM17_BASE + 0x44) ; break and dead-time register
TIM17_DCR EQU (TIM17_BASE + 0x48) ; DMA control register
TIM17_DMAR EQU (TIM17_BASE + 0x4c) ; DMA address for full transfer
; TIM17_CR1 fields:
TIM17_CR1_CEN EQU 0x00000001 ; Counter enable
TIM17_CR1_CEN_ofs EQU 0
TIM17_CR1_CEN_len EQU 1
TIM17_CR1_UDIS EQU 0x00000002 ; Update disable
TIM17_CR1_UDIS_ofs EQU 1
TIM17_CR1_UDIS_len EQU 1
TIM17_CR1_URS EQU 0x00000004 ; Update request source
TIM17_CR1_URS_ofs EQU 2
TIM17_CR1_URS_len EQU 1
TIM17_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM17_CR1_OPM_ofs EQU 3
TIM17_CR1_OPM_len EQU 1
TIM17_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM17_CR1_ARPE_ofs EQU 7
TIM17_CR1_ARPE_len EQU 1
TIM17_CR1_CKD EQU 0x00000300 ; Clock division
TIM17_CR1_CKD_ofs EQU 8
TIM17_CR1_CKD_len EQU 2
TIM17_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM17_CR1_UIFREMAP_ofs EQU 11
TIM17_CR1_UIFREMAP_len EQU 1
; TIM17_CR2 fields:
TIM17_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM17_CR2_OIS1N_ofs EQU 9
TIM17_CR2_OIS1N_len EQU 1
TIM17_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM17_CR2_OIS1_ofs EQU 8
TIM17_CR2_OIS1_len EQU 1
TIM17_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM17_CR2_CCDS_ofs EQU 3
TIM17_CR2_CCDS_len EQU 1
TIM17_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM17_CR2_CCUS_ofs EQU 2
TIM17_CR2_CCUS_len EQU 1
TIM17_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM17_CR2_CCPC_ofs EQU 0
TIM17_CR2_CCPC_len EQU 1
; TIM17_DIER fields:
TIM17_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM17_DIER_UIE_ofs EQU 0
TIM17_DIER_UIE_len EQU 1
TIM17_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM17_DIER_CC1IE_ofs EQU 1
TIM17_DIER_CC1IE_len EQU 1
TIM17_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM17_DIER_COMIE_ofs EQU 5
TIM17_DIER_COMIE_len EQU 1
TIM17_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM17_DIER_TIE_ofs EQU 6
TIM17_DIER_TIE_len EQU 1
TIM17_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM17_DIER_BIE_ofs EQU 7
TIM17_DIER_BIE_len EQU 1
TIM17_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM17_DIER_UDE_ofs EQU 8
TIM17_DIER_UDE_len EQU 1
TIM17_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM17_DIER_CC1DE_ofs EQU 9
TIM17_DIER_CC1DE_len EQU 1
TIM17_DIER_COMDE EQU 0x00002000 ; COM DMA request enable
TIM17_DIER_COMDE_ofs EQU 13
TIM17_DIER_COMDE_len EQU 1
TIM17_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM17_DIER_TDE_ofs EQU 14
TIM17_DIER_TDE_len EQU 1
; TIM17_SR fields:
TIM17_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM17_SR_CC1OF_ofs EQU 9
TIM17_SR_CC1OF_len EQU 1
TIM17_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM17_SR_BIF_ofs EQU 7
TIM17_SR_BIF_len EQU 1
TIM17_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM17_SR_TIF_ofs EQU 6
TIM17_SR_TIF_len EQU 1
TIM17_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM17_SR_COMIF_ofs EQU 5
TIM17_SR_COMIF_len EQU 1
TIM17_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM17_SR_CC1IF_ofs EQU 1
TIM17_SR_CC1IF_len EQU 1
TIM17_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM17_SR_UIF_ofs EQU 0
TIM17_SR_UIF_len EQU 1
; TIM17_EGR fields:
TIM17_EGR_BG EQU 0x00000080 ; Break generation
TIM17_EGR_BG_ofs EQU 7
TIM17_EGR_BG_len EQU 1
TIM17_EGR_TG EQU 0x00000040 ; Trigger generation
TIM17_EGR_TG_ofs EQU 6
TIM17_EGR_TG_len EQU 1
TIM17_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM17_EGR_COMG_ofs EQU 5
TIM17_EGR_COMG_len EQU 1
TIM17_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM17_EGR_CC1G_ofs EQU 1
TIM17_EGR_CC1G_len EQU 1
TIM17_EGR_UG EQU 0x00000001 ; Update generation
TIM17_EGR_UG_ofs EQU 0
TIM17_EGR_UG_len EQU 1
; TIM17_CCMR1_Output fields:
TIM17_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM17_CCMR1_Output_CC1S_ofs EQU 0
TIM17_CCMR1_Output_CC1S_len EQU 2
TIM17_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM17_CCMR1_Output_OC1FE_ofs EQU 2
TIM17_CCMR1_Output_OC1FE_len EQU 1
TIM17_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM17_CCMR1_Output_OC1PE_ofs EQU 3
TIM17_CCMR1_Output_OC1PE_len EQU 1
TIM17_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM17_CCMR1_Output_OC1M_ofs EQU 4
TIM17_CCMR1_Output_OC1M_len EQU 3
TIM17_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode
TIM17_CCMR1_Output_OC1M_3_ofs EQU 16
TIM17_CCMR1_Output_OC1M_3_len EQU 1
; TIM17_CCMR1_Input fields:
TIM17_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM17_CCMR1_Input_IC1F_ofs EQU 4
TIM17_CCMR1_Input_IC1F_len EQU 4
TIM17_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM17_CCMR1_Input_IC1PSC_ofs EQU 2
TIM17_CCMR1_Input_IC1PSC_len EQU 2
TIM17_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM17_CCMR1_Input_CC1S_ofs EQU 0
TIM17_CCMR1_Input_CC1S_len EQU 2
; TIM17_CCER fields:
TIM17_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM17_CCER_CC1NP_ofs EQU 3
TIM17_CCER_CC1NP_len EQU 1
TIM17_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM17_CCER_CC1NE_ofs EQU 2
TIM17_CCER_CC1NE_len EQU 1
TIM17_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM17_CCER_CC1P_ofs EQU 1
TIM17_CCER_CC1P_len EQU 1
TIM17_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM17_CCER_CC1E_ofs EQU 0
TIM17_CCER_CC1E_len EQU 1
; TIM17_CNT fields:
TIM17_CNT_CNT EQU 0x0000ffff ; counter value
TIM17_CNT_CNT_ofs EQU 0
TIM17_CNT_CNT_len EQU 16
TIM17_CNT_UIFCPY EQU 0x80000000 ; UIF Copy
TIM17_CNT_UIFCPY_ofs EQU 31
TIM17_CNT_UIFCPY_len EQU 1
; TIM17_PSC fields:
TIM17_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM17_PSC_PSC_ofs EQU 0
TIM17_PSC_PSC_len EQU 16
; TIM17_ARR fields:
TIM17_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM17_ARR_ARR_ofs EQU 0
TIM17_ARR_ARR_len EQU 16
; TIM17_RCR fields:
TIM17_RCR_REP EQU 0x000000ff ; Repetition counter value
TIM17_RCR_REP_ofs EQU 0
TIM17_RCR_REP_len EQU 8
; TIM17_CCR1 fields:
TIM17_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM17_CCR1_CCR1_ofs EQU 0
TIM17_CCR1_CCR1_len EQU 16
; TIM17_BDTR fields:
TIM17_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM17_BDTR_DTG_ofs EQU 0
TIM17_BDTR_DTG_len EQU 8
TIM17_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM17_BDTR_LOCK_ofs EQU 8
TIM17_BDTR_LOCK_len EQU 2
TIM17_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM17_BDTR_OSSI_ofs EQU 10
TIM17_BDTR_OSSI_len EQU 1
TIM17_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM17_BDTR_OSSR_ofs EQU 11
TIM17_BDTR_OSSR_len EQU 1
TIM17_BDTR_BKE EQU 0x00001000 ; Break enable
TIM17_BDTR_BKE_ofs EQU 12
TIM17_BDTR_BKE_len EQU 1
TIM17_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM17_BDTR_BKP_ofs EQU 13
TIM17_BDTR_BKP_len EQU 1
TIM17_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM17_BDTR_AOE_ofs EQU 14
TIM17_BDTR_AOE_len EQU 1
TIM17_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM17_BDTR_MOE_ofs EQU 15
TIM17_BDTR_MOE_len EQU 1
TIM17_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM17_BDTR_BKF_ofs EQU 16
TIM17_BDTR_BKF_len EQU 4
; TIM17_DCR fields:
TIM17_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM17_DCR_DBL_ofs EQU 8
TIM17_DCR_DBL_len EQU 5
TIM17_DCR_DBA EQU 0x0000001f ; DMA base address
TIM17_DCR_DBA_ofs EQU 0
TIM17_DCR_DBA_len EQU 5
; TIM17_DMAR fields:
TIM17_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM17_DMAR_DMAB_ofs EQU 0
TIM17_DMAR_DMAB_len EQU 16
; ---- USART1 ------------------------------------------------
; Desc: Universal synchronous asynchronous receiver transmitter
; USART1 base address:
USART1_BASE EQU 0x40013800
; USART1 registers:
USART1_CR1 EQU (USART1_BASE + 0x0) ; Control register 1
USART1_CR2 EQU (USART1_BASE + 0x4) ; Control register 2
USART1_CR3 EQU (USART1_BASE + 0x8) ; Control register 3
USART1_BRR EQU (USART1_BASE + 0xc) ; Baud rate register
USART1_GTPR EQU (USART1_BASE + 0x10) ; Guard time and prescaler register
USART1_RTOR EQU (USART1_BASE + 0x14) ; Receiver timeout register
USART1_RQR EQU (USART1_BASE + 0x18) ; Request register
USART1_ISR EQU (USART1_BASE + 0x1c) ; Interrupt & status register
USART1_ICR EQU (USART1_BASE + 0x20) ; Interrupt flag clear register
USART1_RDR EQU (USART1_BASE + 0x24) ; Receive data register
USART1_TDR EQU (USART1_BASE + 0x28) ; Transmit data register
; USART1_CR1 fields:
USART_CR1_EOBIE EQU 0x08000000 ; End of Block interrupt enable
USART_CR1_EOBIE_ofs EQU 27
USART_CR1_EOBIE_len EQU 1
USART_CR1_RTOIE EQU 0x04000000 ; Receiver timeout interrupt enable
USART_CR1_RTOIE_ofs EQU 26
USART_CR1_RTOIE_len EQU 1
USART_CR1_DEAT EQU 0x03e00000 ; Driver Enable assertion time
USART_CR1_DEAT_ofs EQU 21
USART_CR1_DEAT_len EQU 5
USART_CR1_DEDT EQU 0x001f0000 ; Driver Enable deassertion time
USART_CR1_DEDT_ofs EQU 16
USART_CR1_DEDT_len EQU 5
USART_CR1_OVER8 EQU 0x00008000 ; Oversampling mode
USART_CR1_OVER8_ofs EQU 15
USART_CR1_OVER8_len EQU 1
USART_CR1_CMIE EQU 0x00004000 ; Character match interrupt enable
USART_CR1_CMIE_ofs EQU 14
USART_CR1_CMIE_len EQU 1
USART_CR1_MME EQU 0x00002000 ; Mute mode enable
USART_CR1_MME_ofs EQU 13
USART_CR1_MME_len EQU 1
USART_CR1_M EQU 0x00001000 ; Word length
USART_CR1_M_ofs EQU 12
USART_CR1_M_len EQU 1
USART_CR1_WAKE EQU 0x00000800 ; Receiver wakeup method
USART_CR1_WAKE_ofs EQU 11
USART_CR1_WAKE_len EQU 1
USART_CR1_PCE EQU 0x00000400 ; Parity control enable
USART_CR1_PCE_ofs EQU 10
USART_CR1_PCE_len EQU 1
USART_CR1_PS EQU 0x00000200 ; Parity selection
USART_CR1_PS_ofs EQU 9
USART_CR1_PS_len EQU 1
USART_CR1_PEIE EQU 0x00000100 ; PE interrupt enable
USART_CR1_PEIE_ofs EQU 8
USART_CR1_PEIE_len EQU 1
USART_CR1_TXEIE EQU 0x00000080 ; interrupt enable
USART_CR1_TXEIE_ofs EQU 7
USART_CR1_TXEIE_len EQU 1
USART_CR1_TCIE EQU 0x00000040 ; Transmission complete interrupt enable
USART_CR1_TCIE_ofs EQU 6
USART_CR1_TCIE_len EQU 1
USART_CR1_RXNEIE EQU 0x00000020 ; RXNE interrupt enable
USART_CR1_RXNEIE_ofs EQU 5
USART_CR1_RXNEIE_len EQU 1
USART_CR1_IDLEIE EQU 0x00000010 ; IDLE interrupt enable
USART_CR1_IDLEIE_ofs EQU 4
USART_CR1_IDLEIE_len EQU 1
USART_CR1_TE EQU 0x00000008 ; Transmitter enable
USART_CR1_TE_ofs EQU 3
USART_CR1_TE_len EQU 1
USART_CR1_RE EQU 0x00000004 ; Receiver enable
USART_CR1_RE_ofs EQU 2
USART_CR1_RE_len EQU 1
USART_CR1_UESM EQU 0x00000002 ; USART enable in Stop mode
USART_CR1_UESM_ofs EQU 1
USART_CR1_UESM_len EQU 1
USART_CR1_UE EQU 0x00000001 ; USART enable
USART_CR1_UE_ofs EQU 0
USART_CR1_UE_len EQU 1
; USART1_CR2 fields:
USART_CR2_ADD4 EQU 0xf0000000 ; Address of the USART node
USART_CR2_ADD4_ofs EQU 28
USART_CR2_ADD4_len EQU 4
USART_CR2_ADD0 EQU 0x0f000000 ; Address of the USART node
USART_CR2_ADD0_ofs EQU 24
USART_CR2_ADD0_len EQU 4
USART_CR2_RTOEN EQU 0x00800000 ; Receiver timeout enable
USART_CR2_RTOEN_ofs EQU 23
USART_CR2_RTOEN_len EQU 1
USART_CR2_ABRMOD EQU 0x00600000 ; Auto baud rate mode
USART_CR2_ABRMOD_ofs EQU 21
USART_CR2_ABRMOD_len EQU 2
USART_CR2_ABREN EQU 0x00100000 ; Auto baud rate enable
USART_CR2_ABREN_ofs EQU 20
USART_CR2_ABREN_len EQU 1
USART_CR2_MSBFIRST EQU 0x00080000 ; Most significant bit first
USART_CR2_MSBFIRST_ofs EQU 19
USART_CR2_MSBFIRST_len EQU 1
USART_CR2_DATAINV EQU 0x00040000 ; Binary data inversion
USART_CR2_DATAINV_ofs EQU 18
USART_CR2_DATAINV_len EQU 1
USART_CR2_TXINV EQU 0x00020000 ; TX pin active level inversion
USART_CR2_TXINV_ofs EQU 17
USART_CR2_TXINV_len EQU 1
USART_CR2_RXINV EQU 0x00010000 ; RX pin active level inversion
USART_CR2_RXINV_ofs EQU 16
USART_CR2_RXINV_len EQU 1
USART_CR2_SWAP EQU 0x00008000 ; Swap TX/RX pins
USART_CR2_SWAP_ofs EQU 15
USART_CR2_SWAP_len EQU 1
USART_CR2_LINEN EQU 0x00004000 ; LIN mode enable
USART_CR2_LINEN_ofs EQU 14
USART_CR2_LINEN_len EQU 1
USART_CR2_STOP EQU 0x00003000 ; STOP bits
USART_CR2_STOP_ofs EQU 12
USART_CR2_STOP_len EQU 2
USART_CR2_CLKEN EQU 0x00000800 ; Clock enable
USART_CR2_CLKEN_ofs EQU 11
USART_CR2_CLKEN_len EQU 1
USART_CR2_CPOL EQU 0x00000400 ; Clock polarity
USART_CR2_CPOL_ofs EQU 10
USART_CR2_CPOL_len EQU 1
USART_CR2_CPHA EQU 0x00000200 ; Clock phase
USART_CR2_CPHA_ofs EQU 9
USART_CR2_CPHA_len EQU 1
USART_CR2_LBCL EQU 0x00000100 ; Last bit clock pulse
USART_CR2_LBCL_ofs EQU 8
USART_CR2_LBCL_len EQU 1
USART_CR2_LBDIE EQU 0x00000040 ; LIN break detection interrupt enable
USART_CR2_LBDIE_ofs EQU 6
USART_CR2_LBDIE_len EQU 1
USART_CR2_LBDL EQU 0x00000020 ; LIN break detection length
USART_CR2_LBDL_ofs EQU 5
USART_CR2_LBDL_len EQU 1
USART_CR2_ADDM7 EQU 0x00000010 ; 7-bit Address Detection/4-bit Address Detection
USART_CR2_ADDM7_ofs EQU 4
USART_CR2_ADDM7_len EQU 1
; USART1_CR3 fields:
USART_CR3_WUFIE EQU 0x00400000 ; Wakeup from Stop mode interrupt enable
USART_CR3_WUFIE_ofs EQU 22
USART_CR3_WUFIE_len EQU 1
USART_CR3_WUS EQU 0x00300000 ; Wakeup from Stop mode interrupt flag selection
USART_CR3_WUS_ofs EQU 20
USART_CR3_WUS_len EQU 2
USART_CR3_SCARCNT EQU 0x000e0000 ; Smartcard auto-retry count
USART_CR3_SCARCNT_ofs EQU 17
USART_CR3_SCARCNT_len EQU 3
USART_CR3_DEP EQU 0x00008000 ; Driver enable polarity selection
USART_CR3_DEP_ofs EQU 15
USART_CR3_DEP_len EQU 1
USART_CR3_DEM EQU 0x00004000 ; Driver enable mode
USART_CR3_DEM_ofs EQU 14
USART_CR3_DEM_len EQU 1
USART_CR3_DDRE EQU 0x00002000 ; DMA Disable on Reception Error
USART_CR3_DDRE_ofs EQU 13
USART_CR3_DDRE_len EQU 1
USART_CR3_OVRDIS EQU 0x00001000 ; Overrun Disable
USART_CR3_OVRDIS_ofs EQU 12
USART_CR3_OVRDIS_len EQU 1
USART_CR3_ONEBIT EQU 0x00000800 ; One sample bit method enable
USART_CR3_ONEBIT_ofs EQU 11
USART_CR3_ONEBIT_len EQU 1
USART_CR3_CTSIE EQU 0x00000400 ; CTS interrupt enable
USART_CR3_CTSIE_ofs EQU 10
USART_CR3_CTSIE_len EQU 1
USART_CR3_CTSE EQU 0x00000200 ; CTS enable
USART_CR3_CTSE_ofs EQU 9
USART_CR3_CTSE_len EQU 1
USART_CR3_RTSE EQU 0x00000100 ; RTS enable
USART_CR3_RTSE_ofs EQU 8
USART_CR3_RTSE_len EQU 1
USART_CR3_DMAT EQU 0x00000080 ; DMA enable transmitter
USART_CR3_DMAT_ofs EQU 7
USART_CR3_DMAT_len EQU 1
USART_CR3_DMAR EQU 0x00000040 ; DMA enable receiver
USART_CR3_DMAR_ofs EQU 6
USART_CR3_DMAR_len EQU 1
USART_CR3_SCEN EQU 0x00000020 ; Smartcard mode enable
USART_CR3_SCEN_ofs EQU 5
USART_CR3_SCEN_len EQU 1
USART_CR3_NACK EQU 0x00000010 ; Smartcard NACK enable
USART_CR3_NACK_ofs EQU 4
USART_CR3_NACK_len EQU 1
USART_CR3_HDSEL EQU 0x00000008 ; Half-duplex selection
USART_CR3_HDSEL_ofs EQU 3
USART_CR3_HDSEL_len EQU 1
USART_CR3_IRLP EQU 0x00000004 ; IrDA low-power
USART_CR3_IRLP_ofs EQU 2
USART_CR3_IRLP_len EQU 1
USART_CR3_IREN EQU 0x00000002 ; IrDA mode enable
USART_CR3_IREN_ofs EQU 1
USART_CR3_IREN_len EQU 1
USART_CR3_EIE EQU 0x00000001 ; Error interrupt enable
USART_CR3_EIE_ofs EQU 0
USART_CR3_EIE_len EQU 1
; USART1_BRR fields:
USART_BRR_DIV_Mantissa EQU 0x0000fff0 ; mantissa of USARTDIV
USART_BRR_DIV_Mantissa_ofs EQU 4
USART_BRR_DIV_Mantissa_len EQU 12
USART_BRR_DIV_Fraction EQU 0x0000000f ; fraction of USARTDIV
USART_BRR_DIV_Fraction_ofs EQU 0
USART_BRR_DIV_Fraction_len EQU 4
; USART1_GTPR fields:
USART_GTPR_GT EQU 0x0000ff00 ; Guard time value
USART_GTPR_GT_ofs EQU 8
USART_GTPR_GT_len EQU 8
USART_GTPR_PSC EQU 0x000000ff ; Prescaler value
USART_GTPR_PSC_ofs EQU 0
USART_GTPR_PSC_len EQU 8
; USART1_RTOR fields:
USART_RTOR_BLEN EQU 0xff000000 ; Block Length
USART_RTOR_BLEN_ofs EQU 24
USART_RTOR_BLEN_len EQU 8
USART_RTOR_RTO EQU 0x00ffffff ; Receiver timeout value
USART_RTOR_RTO_ofs EQU 0
USART_RTOR_RTO_len EQU 24
; USART1_RQR fields:
USART_RQR_TXFRQ EQU 0x00000010 ; Transmit data flush request
USART_RQR_TXFRQ_ofs EQU 4
USART_RQR_TXFRQ_len EQU 1
USART_RQR_RXFRQ EQU 0x00000008 ; Receive data flush request
USART_RQR_RXFRQ_ofs EQU 3
USART_RQR_RXFRQ_len EQU 1
USART_RQR_MMRQ EQU 0x00000004 ; Mute mode request
USART_RQR_MMRQ_ofs EQU 2
USART_RQR_MMRQ_len EQU 1
USART_RQR_SBKRQ EQU 0x00000002 ; Send break request
USART_RQR_SBKRQ_ofs EQU 1
USART_RQR_SBKRQ_len EQU 1
USART_RQR_ABRRQ EQU 0x00000001 ; Auto baud rate request
USART_RQR_ABRRQ_ofs EQU 0
USART_RQR_ABRRQ_len EQU 1
; USART1_ISR fields:
USART_ISR_REACK EQU 0x00400000 ; Receive enable acknowledge flag
USART_ISR_REACK_ofs EQU 22
USART_ISR_REACK_len EQU 1
USART_ISR_TEACK EQU 0x00200000 ; Transmit enable acknowledge flag
USART_ISR_TEACK_ofs EQU 21
USART_ISR_TEACK_len EQU 1
USART_ISR_WUF EQU 0x00100000 ; Wakeup from Stop mode flag
USART_ISR_WUF_ofs EQU 20
USART_ISR_WUF_len EQU 1
USART_ISR_RWU EQU 0x00080000 ; Receiver wakeup from Mute mode
USART_ISR_RWU_ofs EQU 19
USART_ISR_RWU_len EQU 1
USART_ISR_SBKF EQU 0x00040000 ; Send break flag
USART_ISR_SBKF_ofs EQU 18
USART_ISR_SBKF_len EQU 1
USART_ISR_CMF EQU 0x00020000 ; character match flag
USART_ISR_CMF_ofs EQU 17
USART_ISR_CMF_len EQU 1
USART_ISR_BUSY EQU 0x00010000 ; Busy flag
USART_ISR_BUSY_ofs EQU 16
USART_ISR_BUSY_len EQU 1
USART_ISR_ABRF EQU 0x00008000 ; Auto baud rate flag
USART_ISR_ABRF_ofs EQU 15
USART_ISR_ABRF_len EQU 1
USART_ISR_ABRE EQU 0x00004000 ; Auto baud rate error
USART_ISR_ABRE_ofs EQU 14
USART_ISR_ABRE_len EQU 1
USART_ISR_EOBF EQU 0x00001000 ; End of block flag
USART_ISR_EOBF_ofs EQU 12
USART_ISR_EOBF_len EQU 1
USART_ISR_RTOF EQU 0x00000800 ; Receiver timeout
USART_ISR_RTOF_ofs EQU 11
USART_ISR_RTOF_len EQU 1
USART_ISR_CTS EQU 0x00000400 ; CTS flag
USART_ISR_CTS_ofs EQU 10
USART_ISR_CTS_len EQU 1
USART_ISR_CTSIF EQU 0x00000200 ; CTS interrupt flag
USART_ISR_CTSIF_ofs EQU 9
USART_ISR_CTSIF_len EQU 1
USART_ISR_LBDF EQU 0x00000100 ; LIN break detection flag
USART_ISR_LBDF_ofs EQU 8
USART_ISR_LBDF_len EQU 1
USART_ISR_TXE EQU 0x00000080 ; Transmit data register empty
USART_ISR_TXE_ofs EQU 7
USART_ISR_TXE_len EQU 1
USART_ISR_TC EQU 0x00000040 ; Transmission complete
USART_ISR_TC_ofs EQU 6
USART_ISR_TC_len EQU 1
USART_ISR_RXNE EQU 0x00000020 ; Read data register not empty
USART_ISR_RXNE_ofs EQU 5
USART_ISR_RXNE_len EQU 1
USART_ISR_IDLE EQU 0x00000010 ; Idle line detected
USART_ISR_IDLE_ofs EQU 4
USART_ISR_IDLE_len EQU 1
USART_ISR_ORE EQU 0x00000008 ; Overrun error
USART_ISR_ORE_ofs EQU 3
USART_ISR_ORE_len EQU 1
USART_ISR_NF EQU 0x00000004 ; Noise detected flag
USART_ISR_NF_ofs EQU 2
USART_ISR_NF_len EQU 1
USART_ISR_FE EQU 0x00000002 ; Framing error
USART_ISR_FE_ofs EQU 1
USART_ISR_FE_len EQU 1
USART_ISR_PE EQU 0x00000001 ; Parity error
USART_ISR_PE_ofs EQU 0
USART_ISR_PE_len EQU 1
; USART1_ICR fields:
USART_ICR_WUCF EQU 0x00100000 ; Wakeup from Stop mode clear flag
USART_ICR_WUCF_ofs EQU 20
USART_ICR_WUCF_len EQU 1
USART_ICR_CMCF EQU 0x00020000 ; Character match clear flag
USART_ICR_CMCF_ofs EQU 17
USART_ICR_CMCF_len EQU 1
USART_ICR_EOBCF EQU 0x00001000 ; End of timeout clear flag
USART_ICR_EOBCF_ofs EQU 12
USART_ICR_EOBCF_len EQU 1
USART_ICR_RTOCF EQU 0x00000800 ; Receiver timeout clear flag
USART_ICR_RTOCF_ofs EQU 11
USART_ICR_RTOCF_len EQU 1
USART_ICR_CTSCF EQU 0x00000200 ; CTS clear flag
USART_ICR_CTSCF_ofs EQU 9
USART_ICR_CTSCF_len EQU 1
USART_ICR_LBDCF EQU 0x00000100 ; LIN break detection clear flag
USART_ICR_LBDCF_ofs EQU 8
USART_ICR_LBDCF_len EQU 1
USART_ICR_TCCF EQU 0x00000040 ; Transmission complete clear flag
USART_ICR_TCCF_ofs EQU 6
USART_ICR_TCCF_len EQU 1
USART_ICR_IDLECF EQU 0x00000010 ; Idle line detected clear flag
USART_ICR_IDLECF_ofs EQU 4
USART_ICR_IDLECF_len EQU 1
USART_ICR_ORECF EQU 0x00000008 ; Overrun error clear flag
USART_ICR_ORECF_ofs EQU 3
USART_ICR_ORECF_len EQU 1
USART_ICR_NCF EQU 0x00000004 ; Noise detected clear flag
USART_ICR_NCF_ofs EQU 2
USART_ICR_NCF_len EQU 1
USART_ICR_FECF EQU 0x00000002 ; Framing error clear flag
USART_ICR_FECF_ofs EQU 1
USART_ICR_FECF_len EQU 1
USART_ICR_PECF EQU 0x00000001 ; Parity error clear flag
USART_ICR_PECF_ofs EQU 0
USART_ICR_PECF_len EQU 1
; USART1_RDR fields:
USART_RDR_RDR EQU 0x000001ff ; Receive data value
USART_RDR_RDR_ofs EQU 0
USART_RDR_RDR_len EQU 9
; USART1_TDR fields:
USART_TDR_TDR EQU 0x000001ff ; Transmit data value
USART_TDR_TDR_ofs EQU 0
USART_TDR_TDR_len EQU 9
; ---- USART2 ------------------------------------------------
; Desc: None
; USART2 base address:
USART2_BASE EQU 0x40004400
; USART2 registers:
USART2_CR1 EQU (USART2_BASE + 0x0) ; Control register 1
USART2_CR2 EQU (USART2_BASE + 0x4) ; Control register 2
USART2_CR3 EQU (USART2_BASE + 0x8) ; Control register 3
USART2_BRR EQU (USART2_BASE + 0xc) ; Baud rate register
USART2_GTPR EQU (USART2_BASE + 0x10) ; Guard time and prescaler register
USART2_RTOR EQU (USART2_BASE + 0x14) ; Receiver timeout register
USART2_RQR EQU (USART2_BASE + 0x18) ; Request register
USART2_ISR EQU (USART2_BASE + 0x1c) ; Interrupt & status register
USART2_ICR EQU (USART2_BASE + 0x20) ; Interrupt flag clear register
USART2_RDR EQU (USART2_BASE + 0x24) ; Receive data register
USART2_TDR EQU (USART2_BASE + 0x28) ; Transmit data register
; Fields the same as in the first instance.
; ---- USART3 ------------------------------------------------
; Desc: None
; USART3 base address:
USART3_BASE EQU 0x40004800
; USART3 registers:
USART3_CR1 EQU (USART3_BASE + 0x0) ; Control register 1
USART3_CR2 EQU (USART3_BASE + 0x4) ; Control register 2
USART3_CR3 EQU (USART3_BASE + 0x8) ; Control register 3
USART3_BRR EQU (USART3_BASE + 0xc) ; Baud rate register
USART3_GTPR EQU (USART3_BASE + 0x10) ; Guard time and prescaler register
USART3_RTOR EQU (USART3_BASE + 0x14) ; Receiver timeout register
USART3_RQR EQU (USART3_BASE + 0x18) ; Request register
USART3_ISR EQU (USART3_BASE + 0x1c) ; Interrupt & status register
USART3_ICR EQU (USART3_BASE + 0x20) ; Interrupt flag clear register
USART3_RDR EQU (USART3_BASE + 0x24) ; Receive data register
USART3_TDR EQU (USART3_BASE + 0x28) ; Transmit data register
; Fields the same as in the first instance.
; ---- UART4 -------------------------------------------------
; Desc: None
; UART4 base address:
UART4_BASE EQU 0x40004c00
; UART4 registers:
; ---- UART5 -------------------------------------------------
; Desc: None
; UART5 base address:
UART5_BASE EQU 0x40005000
; UART5 registers:
; ---- SPI1 --------------------------------------------------
; Desc: Serial peripheral interface/Inter-IC sound
; SPI1 base address:
SPI1_BASE EQU 0x40013000
; SPI1 registers:
SPI1_CR1 EQU (SPI1_BASE + 0x0) ; control register 1
SPI1_CR2 EQU (SPI1_BASE + 0x4) ; control register 2
SPI1_SR EQU (SPI1_BASE + 0x8) ; status register
SPI1_DR EQU (SPI1_BASE + 0xc) ; data register
SPI1_CRCPR EQU (SPI1_BASE + 0x10) ; CRC polynomial register
SPI1_RXCRCR EQU (SPI1_BASE + 0x14) ; RX CRC register
SPI1_TXCRCR EQU (SPI1_BASE + 0x18) ; TX CRC register
SPI1_I2SCFGR EQU (SPI1_BASE + 0x1c) ; I2S configuration register
SPI1_I2SPR EQU (SPI1_BASE + 0x20) ; I2S prescaler register
; SPI1_CR1 fields:
SPI1_CR1_BIDIMODE EQU 0x00008000 ; Bidirectional data mode enable
SPI1_CR1_BIDIMODE_ofs EQU 15
SPI1_CR1_BIDIMODE_len EQU 1
SPI1_CR1_BIDIOE EQU 0x00004000 ; Output enable in bidirectional mode
SPI1_CR1_BIDIOE_ofs EQU 14
SPI1_CR1_BIDIOE_len EQU 1
SPI1_CR1_CRCEN EQU 0x00002000 ; Hardware CRC calculation enable
SPI1_CR1_CRCEN_ofs EQU 13
SPI1_CR1_CRCEN_len EQU 1
SPI1_CR1_CRCNEXT EQU 0x00001000 ; CRC transfer next
SPI1_CR1_CRCNEXT_ofs EQU 12
SPI1_CR1_CRCNEXT_len EQU 1
SPI1_CR1_DFF EQU 0x00000800 ; Data frame format
SPI1_CR1_DFF_ofs EQU 11
SPI1_CR1_DFF_len EQU 1
SPI1_CR1_RXONLY EQU 0x00000400 ; Receive only
SPI1_CR1_RXONLY_ofs EQU 10
SPI1_CR1_RXONLY_len EQU 1
SPI1_CR1_SSM EQU 0x00000200 ; Software slave management
SPI1_CR1_SSM_ofs EQU 9
SPI1_CR1_SSM_len EQU 1
SPI1_CR1_SSI EQU 0x00000100 ; Internal slave select
SPI1_CR1_SSI_ofs EQU 8
SPI1_CR1_SSI_len EQU 1
SPI1_CR1_LSBFIRST EQU 0x00000080 ; Frame format
SPI1_CR1_LSBFIRST_ofs EQU 7
SPI1_CR1_LSBFIRST_len EQU 1
SPI1_CR1_SPE EQU 0x00000040 ; SPI enable
SPI1_CR1_SPE_ofs EQU 6
SPI1_CR1_SPE_len EQU 1
SPI1_CR1_BR EQU 0x00000038 ; Baud rate control
SPI1_CR1_BR_ofs EQU 3
SPI1_CR1_BR_len EQU 3
SPI1_CR1_MSTR EQU 0x00000004 ; Master selection
SPI1_CR1_MSTR_ofs EQU 2
SPI1_CR1_MSTR_len EQU 1
SPI1_CR1_CPOL EQU 0x00000002 ; Clock polarity
SPI1_CR1_CPOL_ofs EQU 1
SPI1_CR1_CPOL_len EQU 1
SPI1_CR1_CPHA EQU 0x00000001 ; Clock phase
SPI1_CR1_CPHA_ofs EQU 0
SPI1_CR1_CPHA_len EQU 1
; SPI1_CR2 fields:
SPI1_CR2_RXDMAEN EQU 0x00000001 ; Rx buffer DMA enable
SPI1_CR2_RXDMAEN_ofs EQU 0
SPI1_CR2_RXDMAEN_len EQU 1
SPI1_CR2_TXDMAEN EQU 0x00000002 ; Tx buffer DMA enable
SPI1_CR2_TXDMAEN_ofs EQU 1
SPI1_CR2_TXDMAEN_len EQU 1
SPI1_CR2_SSOE EQU 0x00000004 ; SS output enable
SPI1_CR2_SSOE_ofs EQU 2
SPI1_CR2_SSOE_len EQU 1
SPI1_CR2_NSSP EQU 0x00000008 ; NSS pulse management
SPI1_CR2_NSSP_ofs EQU 3
SPI1_CR2_NSSP_len EQU 1
SPI1_CR2_FRF EQU 0x00000010 ; Frame format
SPI1_CR2_FRF_ofs EQU 4
SPI1_CR2_FRF_len EQU 1
SPI1_CR2_ERRIE EQU 0x00000020 ; Error interrupt enable
SPI1_CR2_ERRIE_ofs EQU 5
SPI1_CR2_ERRIE_len EQU 1
SPI1_CR2_RXNEIE EQU 0x00000040 ; RX buffer not empty interrupt enable
SPI1_CR2_RXNEIE_ofs EQU 6
SPI1_CR2_RXNEIE_len EQU 1
SPI1_CR2_TXEIE EQU 0x00000080 ; Tx buffer empty interrupt enable
SPI1_CR2_TXEIE_ofs EQU 7
SPI1_CR2_TXEIE_len EQU 1
SPI1_CR2_DS EQU 0x00000f00 ; Data size
SPI1_CR2_DS_ofs EQU 8
SPI1_CR2_DS_len EQU 4
SPI1_CR2_FRXTH EQU 0x00001000 ; FIFO reception threshold
SPI1_CR2_FRXTH_ofs EQU 12
SPI1_CR2_FRXTH_len EQU 1
SPI1_CR2_LDMA_RX EQU 0x00002000 ; Last DMA transfer for reception
SPI1_CR2_LDMA_RX_ofs EQU 13
SPI1_CR2_LDMA_RX_len EQU 1
SPI1_CR2_LDMA_TX EQU 0x00004000 ; Last DMA transfer for transmission
SPI1_CR2_LDMA_TX_ofs EQU 14
SPI1_CR2_LDMA_TX_len EQU 1
; SPI1_SR fields:
SPI1_SR_RXNE EQU 0x00000001 ; Receive buffer not empty
SPI1_SR_RXNE_ofs EQU 0
SPI1_SR_RXNE_len EQU 1
SPI1_SR_TXE EQU 0x00000002 ; Transmit buffer empty
SPI1_SR_TXE_ofs EQU 1
SPI1_SR_TXE_len EQU 1
SPI1_SR_CHSIDE EQU 0x00000004 ; Channel side
SPI1_SR_CHSIDE_ofs EQU 2
SPI1_SR_CHSIDE_len EQU 1
SPI1_SR_UDR EQU 0x00000008 ; Underrun flag
SPI1_SR_UDR_ofs EQU 3
SPI1_SR_UDR_len EQU 1
SPI1_SR_CRCERR EQU 0x00000010 ; CRC error flag
SPI1_SR_CRCERR_ofs EQU 4
SPI1_SR_CRCERR_len EQU 1
SPI1_SR_MODF EQU 0x00000020 ; Mode fault
SPI1_SR_MODF_ofs EQU 5
SPI1_SR_MODF_len EQU 1
SPI1_SR_OVR EQU 0x00000040 ; Overrun flag
SPI1_SR_OVR_ofs EQU 6
SPI1_SR_OVR_len EQU 1
SPI1_SR_BSY EQU 0x00000080 ; Busy flag
SPI1_SR_BSY_ofs EQU 7
SPI1_SR_BSY_len EQU 1
SPI1_SR_TIFRFE EQU 0x00000100 ; TI frame format error
SPI1_SR_TIFRFE_ofs EQU 8
SPI1_SR_TIFRFE_len EQU 1
SPI1_SR_FRLVL EQU 0x00000600 ; FIFO reception level
SPI1_SR_FRLVL_ofs EQU 9
SPI1_SR_FRLVL_len EQU 2
SPI1_SR_FTLVL EQU 0x00001800 ; FIFO transmission level
SPI1_SR_FTLVL_ofs EQU 11
SPI1_SR_FTLVL_len EQU 2
; SPI1_DR fields:
SPI1_DR_DR EQU 0x0000ffff ; Data register
SPI1_DR_DR_ofs EQU 0
SPI1_DR_DR_len EQU 16
; SPI1_CRCPR fields:
SPI1_CRCPR_CRCPOLY EQU 0x0000ffff ; CRC polynomial register
SPI1_CRCPR_CRCPOLY_ofs EQU 0
SPI1_CRCPR_CRCPOLY_len EQU 16
; SPI1_RXCRCR fields:
SPI1_RXCRCR_RxCRC EQU 0x0000ffff ; Rx CRC register
SPI1_RXCRCR_RxCRC_ofs EQU 0
SPI1_RXCRCR_RxCRC_len EQU 16
; SPI1_TXCRCR fields:
SPI1_TXCRCR_TxCRC EQU 0x0000ffff ; Tx CRC register
SPI1_TXCRCR_TxCRC_ofs EQU 0
SPI1_TXCRCR_TxCRC_len EQU 16
; SPI1_I2SCFGR fields:
SPI1_I2SCFGR_I2SMOD EQU 0x00000800 ; I2S mode selection
SPI1_I2SCFGR_I2SMOD_ofs EQU 11
SPI1_I2SCFGR_I2SMOD_len EQU 1
SPI1_I2SCFGR_I2SE EQU 0x00000400 ; I2S Enable
SPI1_I2SCFGR_I2SE_ofs EQU 10
SPI1_I2SCFGR_I2SE_len EQU 1
SPI1_I2SCFGR_I2SCFG EQU 0x00000300 ; I2S configuration mode
SPI1_I2SCFGR_I2SCFG_ofs EQU 8
SPI1_I2SCFGR_I2SCFG_len EQU 2
SPI1_I2SCFGR_PCMSYNC EQU 0x00000080 ; PCM frame synchronization
SPI1_I2SCFGR_PCMSYNC_ofs EQU 7
SPI1_I2SCFGR_PCMSYNC_len EQU 1
SPI1_I2SCFGR_I2SSTD EQU 0x00000030 ; I2S standard selection
SPI1_I2SCFGR_I2SSTD_ofs EQU 4
SPI1_I2SCFGR_I2SSTD_len EQU 2
SPI1_I2SCFGR_CKPOL EQU 0x00000008 ; Steady state clock polarity
SPI1_I2SCFGR_CKPOL_ofs EQU 3
SPI1_I2SCFGR_CKPOL_len EQU 1
SPI1_I2SCFGR_DATLEN EQU 0x00000006 ; Data length to be transferred
SPI1_I2SCFGR_DATLEN_ofs EQU 1
SPI1_I2SCFGR_DATLEN_len EQU 2
SPI1_I2SCFGR_CHLEN EQU 0x00000001 ; Channel length (number of bits per audio channel)
SPI1_I2SCFGR_CHLEN_ofs EQU 0
SPI1_I2SCFGR_CHLEN_len EQU 1
; SPI1_I2SPR fields:
SPI1_I2SPR_MCKOE EQU 0x00000200 ; Master clock output enable
SPI1_I2SPR_MCKOE_ofs EQU 9
SPI1_I2SPR_MCKOE_len EQU 1
SPI1_I2SPR_ODD EQU 0x00000100 ; Odd factor for the prescaler
SPI1_I2SPR_ODD_ofs EQU 8
SPI1_I2SPR_ODD_len EQU 1
SPI1_I2SPR_I2SDIV EQU 0x000000ff ; I2S Linear prescaler
SPI1_I2SPR_I2SDIV_ofs EQU 0
SPI1_I2SPR_I2SDIV_len EQU 8
; ---- SPI2 --------------------------------------------------
; Desc: None
; SPI2 base address:
SPI2_BASE EQU 0x40003800
; SPI2 registers:
; ---- SPI3 --------------------------------------------------
; Desc: None
; SPI3 base address:
SPI3_BASE EQU 0x40003c00
; SPI3 registers:
; ---- I2S2ext -----------------------------------------------
; Desc: None
; I2S2ext base address:
I2S2ext_BASE EQU 0x40003400
; I2S2ext registers:
; ---- I2S3ext -----------------------------------------------
; Desc: None
; I2S3ext base address:
I2S3ext_BASE EQU 0x40004000
; I2S3ext registers:
; ---- EXTI --------------------------------------------------
; Desc: External interrupt/event controller
; EXTI base address:
EXTI_BASE EQU 0x40010400
; EXTI registers:
EXTI_IMR1 EQU (EXTI_BASE + 0x0) ; Interrupt mask register
EXTI_EMR1 EQU (EXTI_BASE + 0x4) ; Event mask register
EXTI_RTSR1 EQU (EXTI_BASE + 0x8) ; Rising Trigger selection register
EXTI_FTSR1 EQU (EXTI_BASE + 0xc) ; Falling Trigger selection register
EXTI_SWIER1 EQU (EXTI_BASE + 0x10) ; Software interrupt event register
EXTI_PR1 EQU (EXTI_BASE + 0x14) ; Pending register
EXTI_IMR2 EQU (EXTI_BASE + 0x18) ; Interrupt mask register
EXTI_EMR2 EQU (EXTI_BASE + 0x1c) ; Event mask register
EXTI_RTSR2 EQU (EXTI_BASE + 0x20) ; Rising Trigger selection register
EXTI_FTSR2 EQU (EXTI_BASE + 0x24) ; Falling Trigger selection register
EXTI_SWIER2 EQU (EXTI_BASE + 0x28) ; Software interrupt event register
EXTI_PR2 EQU (EXTI_BASE + 0x2c) ; Pending register
; EXTI_IMR1 fields:
EXTI_IMR1_MR0 EQU 0x00000001 ; Interrupt Mask on line 0
EXTI_IMR1_MR0_ofs EQU 0
EXTI_IMR1_MR0_len EQU 1
EXTI_IMR1_MR1 EQU 0x00000002 ; Interrupt Mask on line 1
EXTI_IMR1_MR1_ofs EQU 1
EXTI_IMR1_MR1_len EQU 1
EXTI_IMR1_MR2 EQU 0x00000004 ; Interrupt Mask on line 2
EXTI_IMR1_MR2_ofs EQU 2
EXTI_IMR1_MR2_len EQU 1
EXTI_IMR1_MR3 EQU 0x00000008 ; Interrupt Mask on line 3
EXTI_IMR1_MR3_ofs EQU 3
EXTI_IMR1_MR3_len EQU 1
EXTI_IMR1_MR4 EQU 0x00000010 ; Interrupt Mask on line 4
EXTI_IMR1_MR4_ofs EQU 4
EXTI_IMR1_MR4_len EQU 1
EXTI_IMR1_MR5 EQU 0x00000020 ; Interrupt Mask on line 5
EXTI_IMR1_MR5_ofs EQU 5
EXTI_IMR1_MR5_len EQU 1
EXTI_IMR1_MR6 EQU 0x00000040 ; Interrupt Mask on line 6
EXTI_IMR1_MR6_ofs EQU 6
EXTI_IMR1_MR6_len EQU 1
EXTI_IMR1_MR7 EQU 0x00000080 ; Interrupt Mask on line 7
EXTI_IMR1_MR7_ofs EQU 7
EXTI_IMR1_MR7_len EQU 1
EXTI_IMR1_MR8 EQU 0x00000100 ; Interrupt Mask on line 8
EXTI_IMR1_MR8_ofs EQU 8
EXTI_IMR1_MR8_len EQU 1
EXTI_IMR1_MR9 EQU 0x00000200 ; Interrupt Mask on line 9
EXTI_IMR1_MR9_ofs EQU 9
EXTI_IMR1_MR9_len EQU 1
EXTI_IMR1_MR10 EQU 0x00000400 ; Interrupt Mask on line 10
EXTI_IMR1_MR10_ofs EQU 10
EXTI_IMR1_MR10_len EQU 1
EXTI_IMR1_MR11 EQU 0x00000800 ; Interrupt Mask on line 11
EXTI_IMR1_MR11_ofs EQU 11
EXTI_IMR1_MR11_len EQU 1
EXTI_IMR1_MR12 EQU 0x00001000 ; Interrupt Mask on line 12
EXTI_IMR1_MR12_ofs EQU 12
EXTI_IMR1_MR12_len EQU 1
EXTI_IMR1_MR13 EQU 0x00002000 ; Interrupt Mask on line 13
EXTI_IMR1_MR13_ofs EQU 13
EXTI_IMR1_MR13_len EQU 1
EXTI_IMR1_MR14 EQU 0x00004000 ; Interrupt Mask on line 14
EXTI_IMR1_MR14_ofs EQU 14
EXTI_IMR1_MR14_len EQU 1
EXTI_IMR1_MR15 EQU 0x00008000 ; Interrupt Mask on line 15
EXTI_IMR1_MR15_ofs EQU 15
EXTI_IMR1_MR15_len EQU 1
EXTI_IMR1_MR16 EQU 0x00010000 ; Interrupt Mask on line 16
EXTI_IMR1_MR16_ofs EQU 16
EXTI_IMR1_MR16_len EQU 1
EXTI_IMR1_MR17 EQU 0x00020000 ; Interrupt Mask on line 17
EXTI_IMR1_MR17_ofs EQU 17
EXTI_IMR1_MR17_len EQU 1
EXTI_IMR1_MR18 EQU 0x00040000 ; Interrupt Mask on line 18
EXTI_IMR1_MR18_ofs EQU 18
EXTI_IMR1_MR18_len EQU 1
EXTI_IMR1_MR19 EQU 0x00080000 ; Interrupt Mask on line 19
EXTI_IMR1_MR19_ofs EQU 19
EXTI_IMR1_MR19_len EQU 1
EXTI_IMR1_MR20 EQU 0x00100000 ; Interrupt Mask on line 20
EXTI_IMR1_MR20_ofs EQU 20
EXTI_IMR1_MR20_len EQU 1
EXTI_IMR1_MR21 EQU 0x00200000 ; Interrupt Mask on line 21
EXTI_IMR1_MR21_ofs EQU 21
EXTI_IMR1_MR21_len EQU 1
EXTI_IMR1_MR22 EQU 0x00400000 ; Interrupt Mask on line 22
EXTI_IMR1_MR22_ofs EQU 22
EXTI_IMR1_MR22_len EQU 1
EXTI_IMR1_MR23 EQU 0x00800000 ; Interrupt Mask on line 23
EXTI_IMR1_MR23_ofs EQU 23
EXTI_IMR1_MR23_len EQU 1
EXTI_IMR1_MR24 EQU 0x01000000 ; Interrupt Mask on line 24
EXTI_IMR1_MR24_ofs EQU 24
EXTI_IMR1_MR24_len EQU 1
EXTI_IMR1_MR25 EQU 0x02000000 ; Interrupt Mask on line 25
EXTI_IMR1_MR25_ofs EQU 25
EXTI_IMR1_MR25_len EQU 1
EXTI_IMR1_MR26 EQU 0x04000000 ; Interrupt Mask on line 26
EXTI_IMR1_MR26_ofs EQU 26
EXTI_IMR1_MR26_len EQU 1
EXTI_IMR1_MR27 EQU 0x08000000 ; Interrupt Mask on line 27
EXTI_IMR1_MR27_ofs EQU 27
EXTI_IMR1_MR27_len EQU 1
EXTI_IMR1_MR28 EQU 0x10000000 ; Interrupt Mask on line 28
EXTI_IMR1_MR28_ofs EQU 28
EXTI_IMR1_MR28_len EQU 1
EXTI_IMR1_MR29 EQU 0x20000000 ; Interrupt Mask on line 29
EXTI_IMR1_MR29_ofs EQU 29
EXTI_IMR1_MR29_len EQU 1
EXTI_IMR1_MR30 EQU 0x40000000 ; Interrupt Mask on line 30
EXTI_IMR1_MR30_ofs EQU 30
EXTI_IMR1_MR30_len EQU 1
EXTI_IMR1_MR31 EQU 0x80000000 ; Interrupt Mask on line 31
EXTI_IMR1_MR31_ofs EQU 31
EXTI_IMR1_MR31_len EQU 1
; EXTI_EMR1 fields:
EXTI_EMR1_MR0 EQU 0x00000001 ; Event Mask on line 0
EXTI_EMR1_MR0_ofs EQU 0
EXTI_EMR1_MR0_len EQU 1
EXTI_EMR1_MR1 EQU 0x00000002 ; Event Mask on line 1
EXTI_EMR1_MR1_ofs EQU 1
EXTI_EMR1_MR1_len EQU 1
EXTI_EMR1_MR2 EQU 0x00000004 ; Event Mask on line 2
EXTI_EMR1_MR2_ofs EQU 2
EXTI_EMR1_MR2_len EQU 1
EXTI_EMR1_MR3 EQU 0x00000008 ; Event Mask on line 3
EXTI_EMR1_MR3_ofs EQU 3
EXTI_EMR1_MR3_len EQU 1
EXTI_EMR1_MR4 EQU 0x00000010 ; Event Mask on line 4
EXTI_EMR1_MR4_ofs EQU 4
EXTI_EMR1_MR4_len EQU 1
EXTI_EMR1_MR5 EQU 0x00000020 ; Event Mask on line 5
EXTI_EMR1_MR5_ofs EQU 5
EXTI_EMR1_MR5_len EQU 1
EXTI_EMR1_MR6 EQU 0x00000040 ; Event Mask on line 6
EXTI_EMR1_MR6_ofs EQU 6
EXTI_EMR1_MR6_len EQU 1
EXTI_EMR1_MR7 EQU 0x00000080 ; Event Mask on line 7
EXTI_EMR1_MR7_ofs EQU 7
EXTI_EMR1_MR7_len EQU 1
EXTI_EMR1_MR8 EQU 0x00000100 ; Event Mask on line 8
EXTI_EMR1_MR8_ofs EQU 8
EXTI_EMR1_MR8_len EQU 1
EXTI_EMR1_MR9 EQU 0x00000200 ; Event Mask on line 9
EXTI_EMR1_MR9_ofs EQU 9
EXTI_EMR1_MR9_len EQU 1
EXTI_EMR1_MR10 EQU 0x00000400 ; Event Mask on line 10
EXTI_EMR1_MR10_ofs EQU 10
EXTI_EMR1_MR10_len EQU 1
EXTI_EMR1_MR11 EQU 0x00000800 ; Event Mask on line 11
EXTI_EMR1_MR11_ofs EQU 11
EXTI_EMR1_MR11_len EQU 1
EXTI_EMR1_MR12 EQU 0x00001000 ; Event Mask on line 12
EXTI_EMR1_MR12_ofs EQU 12
EXTI_EMR1_MR12_len EQU 1
EXTI_EMR1_MR13 EQU 0x00002000 ; Event Mask on line 13
EXTI_EMR1_MR13_ofs EQU 13
EXTI_EMR1_MR13_len EQU 1
EXTI_EMR1_MR14 EQU 0x00004000 ; Event Mask on line 14
EXTI_EMR1_MR14_ofs EQU 14
EXTI_EMR1_MR14_len EQU 1
EXTI_EMR1_MR15 EQU 0x00008000 ; Event Mask on line 15
EXTI_EMR1_MR15_ofs EQU 15
EXTI_EMR1_MR15_len EQU 1
EXTI_EMR1_MR16 EQU 0x00010000 ; Event Mask on line 16
EXTI_EMR1_MR16_ofs EQU 16
EXTI_EMR1_MR16_len EQU 1
EXTI_EMR1_MR17 EQU 0x00020000 ; Event Mask on line 17
EXTI_EMR1_MR17_ofs EQU 17
EXTI_EMR1_MR17_len EQU 1
EXTI_EMR1_MR18 EQU 0x00040000 ; Event Mask on line 18
EXTI_EMR1_MR18_ofs EQU 18
EXTI_EMR1_MR18_len EQU 1
EXTI_EMR1_MR19 EQU 0x00080000 ; Event Mask on line 19
EXTI_EMR1_MR19_ofs EQU 19
EXTI_EMR1_MR19_len EQU 1
EXTI_EMR1_MR20 EQU 0x00100000 ; Event Mask on line 20
EXTI_EMR1_MR20_ofs EQU 20
EXTI_EMR1_MR20_len EQU 1
EXTI_EMR1_MR21 EQU 0x00200000 ; Event Mask on line 21
EXTI_EMR1_MR21_ofs EQU 21
EXTI_EMR1_MR21_len EQU 1
EXTI_EMR1_MR22 EQU 0x00400000 ; Event Mask on line 22
EXTI_EMR1_MR22_ofs EQU 22
EXTI_EMR1_MR22_len EQU 1
EXTI_EMR1_MR23 EQU 0x00800000 ; Event Mask on line 23
EXTI_EMR1_MR23_ofs EQU 23
EXTI_EMR1_MR23_len EQU 1
EXTI_EMR1_MR24 EQU 0x01000000 ; Event Mask on line 24
EXTI_EMR1_MR24_ofs EQU 24
EXTI_EMR1_MR24_len EQU 1
EXTI_EMR1_MR25 EQU 0x02000000 ; Event Mask on line 25
EXTI_EMR1_MR25_ofs EQU 25
EXTI_EMR1_MR25_len EQU 1
EXTI_EMR1_MR26 EQU 0x04000000 ; Event Mask on line 26
EXTI_EMR1_MR26_ofs EQU 26
EXTI_EMR1_MR26_len EQU 1
EXTI_EMR1_MR27 EQU 0x08000000 ; Event Mask on line 27
EXTI_EMR1_MR27_ofs EQU 27
EXTI_EMR1_MR27_len EQU 1
EXTI_EMR1_MR28 EQU 0x10000000 ; Event Mask on line 28
EXTI_EMR1_MR28_ofs EQU 28
EXTI_EMR1_MR28_len EQU 1
EXTI_EMR1_MR29 EQU 0x20000000 ; Event Mask on line 29
EXTI_EMR1_MR29_ofs EQU 29
EXTI_EMR1_MR29_len EQU 1
EXTI_EMR1_MR30 EQU 0x40000000 ; Event Mask on line 30
EXTI_EMR1_MR30_ofs EQU 30
EXTI_EMR1_MR30_len EQU 1
EXTI_EMR1_MR31 EQU 0x80000000 ; Event Mask on line 31
EXTI_EMR1_MR31_ofs EQU 31
EXTI_EMR1_MR31_len EQU 1
; EXTI_RTSR1 fields:
EXTI_RTSR1_TR0 EQU 0x00000001 ; Rising trigger event configuration of line 0
EXTI_RTSR1_TR0_ofs EQU 0
EXTI_RTSR1_TR0_len EQU 1
EXTI_RTSR1_TR1 EQU 0x00000002 ; Rising trigger event configuration of line 1
EXTI_RTSR1_TR1_ofs EQU 1
EXTI_RTSR1_TR1_len EQU 1
EXTI_RTSR1_TR2 EQU 0x00000004 ; Rising trigger event configuration of line 2
EXTI_RTSR1_TR2_ofs EQU 2
EXTI_RTSR1_TR2_len EQU 1
EXTI_RTSR1_TR3 EQU 0x00000008 ; Rising trigger event configuration of line 3
EXTI_RTSR1_TR3_ofs EQU 3
EXTI_RTSR1_TR3_len EQU 1
EXTI_RTSR1_TR4 EQU 0x00000010 ; Rising trigger event configuration of line 4
EXTI_RTSR1_TR4_ofs EQU 4
EXTI_RTSR1_TR4_len EQU 1
EXTI_RTSR1_TR5 EQU 0x00000020 ; Rising trigger event configuration of line 5
EXTI_RTSR1_TR5_ofs EQU 5
EXTI_RTSR1_TR5_len EQU 1
EXTI_RTSR1_TR6 EQU 0x00000040 ; Rising trigger event configuration of line 6
EXTI_RTSR1_TR6_ofs EQU 6
EXTI_RTSR1_TR6_len EQU 1
EXTI_RTSR1_TR7 EQU 0x00000080 ; Rising trigger event configuration of line 7
EXTI_RTSR1_TR7_ofs EQU 7
EXTI_RTSR1_TR7_len EQU 1
EXTI_RTSR1_TR8 EQU 0x00000100 ; Rising trigger event configuration of line 8
EXTI_RTSR1_TR8_ofs EQU 8
EXTI_RTSR1_TR8_len EQU 1
EXTI_RTSR1_TR9 EQU 0x00000200 ; Rising trigger event configuration of line 9
EXTI_RTSR1_TR9_ofs EQU 9
EXTI_RTSR1_TR9_len EQU 1
EXTI_RTSR1_TR10 EQU 0x00000400 ; Rising trigger event configuration of line 10
EXTI_RTSR1_TR10_ofs EQU 10
EXTI_RTSR1_TR10_len EQU 1
EXTI_RTSR1_TR11 EQU 0x00000800 ; Rising trigger event configuration of line 11
EXTI_RTSR1_TR11_ofs EQU 11
EXTI_RTSR1_TR11_len EQU 1
EXTI_RTSR1_TR12 EQU 0x00001000 ; Rising trigger event configuration of line 12
EXTI_RTSR1_TR12_ofs EQU 12
EXTI_RTSR1_TR12_len EQU 1
EXTI_RTSR1_TR13 EQU 0x00002000 ; Rising trigger event configuration of line 13
EXTI_RTSR1_TR13_ofs EQU 13
EXTI_RTSR1_TR13_len EQU 1
EXTI_RTSR1_TR14 EQU 0x00004000 ; Rising trigger event configuration of line 14
EXTI_RTSR1_TR14_ofs EQU 14
EXTI_RTSR1_TR14_len EQU 1
EXTI_RTSR1_TR15 EQU 0x00008000 ; Rising trigger event configuration of line 15
EXTI_RTSR1_TR15_ofs EQU 15
EXTI_RTSR1_TR15_len EQU 1
EXTI_RTSR1_TR16 EQU 0x00010000 ; Rising trigger event configuration of line 16
EXTI_RTSR1_TR16_ofs EQU 16
EXTI_RTSR1_TR16_len EQU 1
EXTI_RTSR1_TR17 EQU 0x00020000 ; Rising trigger event configuration of line 17
EXTI_RTSR1_TR17_ofs EQU 17
EXTI_RTSR1_TR17_len EQU 1
EXTI_RTSR1_TR18 EQU 0x00040000 ; Rising trigger event configuration of line 18
EXTI_RTSR1_TR18_ofs EQU 18
EXTI_RTSR1_TR18_len EQU 1
EXTI_RTSR1_TR19 EQU 0x00080000 ; Rising trigger event configuration of line 19
EXTI_RTSR1_TR19_ofs EQU 19
EXTI_RTSR1_TR19_len EQU 1
EXTI_RTSR1_TR20 EQU 0x00100000 ; Rising trigger event configuration of line 20
EXTI_RTSR1_TR20_ofs EQU 20
EXTI_RTSR1_TR20_len EQU 1
EXTI_RTSR1_TR21 EQU 0x00200000 ; Rising trigger event configuration of line 21
EXTI_RTSR1_TR21_ofs EQU 21
EXTI_RTSR1_TR21_len EQU 1
EXTI_RTSR1_TR22 EQU 0x00400000 ; Rising trigger event configuration of line 22
EXTI_RTSR1_TR22_ofs EQU 22
EXTI_RTSR1_TR22_len EQU 1
EXTI_RTSR1_TR29 EQU 0x20000000 ; Rising trigger event configuration of line 29
EXTI_RTSR1_TR29_ofs EQU 29
EXTI_RTSR1_TR29_len EQU 1
EXTI_RTSR1_TR30 EQU 0x40000000 ; Rising trigger event configuration of line 30
EXTI_RTSR1_TR30_ofs EQU 30
EXTI_RTSR1_TR30_len EQU 1
EXTI_RTSR1_TR31 EQU 0x80000000 ; Rising trigger event configuration of line 31
EXTI_RTSR1_TR31_ofs EQU 31
EXTI_RTSR1_TR31_len EQU 1
; EXTI_FTSR1 fields:
EXTI_FTSR1_TR0 EQU 0x00000001 ; Falling trigger event configuration of line 0
EXTI_FTSR1_TR0_ofs EQU 0
EXTI_FTSR1_TR0_len EQU 1
EXTI_FTSR1_TR1 EQU 0x00000002 ; Falling trigger event configuration of line 1
EXTI_FTSR1_TR1_ofs EQU 1
EXTI_FTSR1_TR1_len EQU 1
EXTI_FTSR1_TR2 EQU 0x00000004 ; Falling trigger event configuration of line 2
EXTI_FTSR1_TR2_ofs EQU 2
EXTI_FTSR1_TR2_len EQU 1
EXTI_FTSR1_TR3 EQU 0x00000008 ; Falling trigger event configuration of line 3
EXTI_FTSR1_TR3_ofs EQU 3
EXTI_FTSR1_TR3_len EQU 1
EXTI_FTSR1_TR4 EQU 0x00000010 ; Falling trigger event configuration of line 4
EXTI_FTSR1_TR4_ofs EQU 4
EXTI_FTSR1_TR4_len EQU 1
EXTI_FTSR1_TR5 EQU 0x00000020 ; Falling trigger event configuration of line 5
EXTI_FTSR1_TR5_ofs EQU 5
EXTI_FTSR1_TR5_len EQU 1
EXTI_FTSR1_TR6 EQU 0x00000040 ; Falling trigger event configuration of line 6
EXTI_FTSR1_TR6_ofs EQU 6
EXTI_FTSR1_TR6_len EQU 1
EXTI_FTSR1_TR7 EQU 0x00000080 ; Falling trigger event configuration of line 7
EXTI_FTSR1_TR7_ofs EQU 7
EXTI_FTSR1_TR7_len EQU 1
EXTI_FTSR1_TR8 EQU 0x00000100 ; Falling trigger event configuration of line 8
EXTI_FTSR1_TR8_ofs EQU 8
EXTI_FTSR1_TR8_len EQU 1
EXTI_FTSR1_TR9 EQU 0x00000200 ; Falling trigger event configuration of line 9
EXTI_FTSR1_TR9_ofs EQU 9
EXTI_FTSR1_TR9_len EQU 1
EXTI_FTSR1_TR10 EQU 0x00000400 ; Falling trigger event configuration of line 10
EXTI_FTSR1_TR10_ofs EQU 10
EXTI_FTSR1_TR10_len EQU 1
EXTI_FTSR1_TR11 EQU 0x00000800 ; Falling trigger event configuration of line 11
EXTI_FTSR1_TR11_ofs EQU 11
EXTI_FTSR1_TR11_len EQU 1
EXTI_FTSR1_TR12 EQU 0x00001000 ; Falling trigger event configuration of line 12
EXTI_FTSR1_TR12_ofs EQU 12
EXTI_FTSR1_TR12_len EQU 1
EXTI_FTSR1_TR13 EQU 0x00002000 ; Falling trigger event configuration of line 13
EXTI_FTSR1_TR13_ofs EQU 13
EXTI_FTSR1_TR13_len EQU 1
EXTI_FTSR1_TR14 EQU 0x00004000 ; Falling trigger event configuration of line 14
EXTI_FTSR1_TR14_ofs EQU 14
EXTI_FTSR1_TR14_len EQU 1
EXTI_FTSR1_TR15 EQU 0x00008000 ; Falling trigger event configuration of line 15
EXTI_FTSR1_TR15_ofs EQU 15
EXTI_FTSR1_TR15_len EQU 1
EXTI_FTSR1_TR16 EQU 0x00010000 ; Falling trigger event configuration of line 16
EXTI_FTSR1_TR16_ofs EQU 16
EXTI_FTSR1_TR16_len EQU 1
EXTI_FTSR1_TR17 EQU 0x00020000 ; Falling trigger event configuration of line 17
EXTI_FTSR1_TR17_ofs EQU 17
EXTI_FTSR1_TR17_len EQU 1
EXTI_FTSR1_TR18 EQU 0x00040000 ; Falling trigger event configuration of line 18
EXTI_FTSR1_TR18_ofs EQU 18
EXTI_FTSR1_TR18_len EQU 1
EXTI_FTSR1_TR19 EQU 0x00080000 ; Falling trigger event configuration of line 19
EXTI_FTSR1_TR19_ofs EQU 19
EXTI_FTSR1_TR19_len EQU 1
EXTI_FTSR1_TR20 EQU 0x00100000 ; Falling trigger event configuration of line 20
EXTI_FTSR1_TR20_ofs EQU 20
EXTI_FTSR1_TR20_len EQU 1
EXTI_FTSR1_TR21 EQU 0x00200000 ; Falling trigger event configuration of line 21
EXTI_FTSR1_TR21_ofs EQU 21
EXTI_FTSR1_TR21_len EQU 1
EXTI_FTSR1_TR22 EQU 0x00400000 ; Falling trigger event configuration of line 22
EXTI_FTSR1_TR22_ofs EQU 22
EXTI_FTSR1_TR22_len EQU 1
EXTI_FTSR1_TR29 EQU 0x20000000 ; Falling trigger event configuration of line 29
EXTI_FTSR1_TR29_ofs EQU 29
EXTI_FTSR1_TR29_len EQU 1
EXTI_FTSR1_TR30 EQU 0x40000000 ; Falling trigger event configuration of line 30.
EXTI_FTSR1_TR30_ofs EQU 30
EXTI_FTSR1_TR30_len EQU 1
EXTI_FTSR1_TR31 EQU 0x80000000 ; Falling trigger event configuration of line 31
EXTI_FTSR1_TR31_ofs EQU 31
EXTI_FTSR1_TR31_len EQU 1
; EXTI_SWIER1 fields:
EXTI_SWIER1_SWIER0 EQU 0x00000001 ; Software Interrupt on line 0
EXTI_SWIER1_SWIER0_ofs EQU 0
EXTI_SWIER1_SWIER0_len EQU 1
EXTI_SWIER1_SWIER1 EQU 0x00000002 ; Software Interrupt on line 1
EXTI_SWIER1_SWIER1_ofs EQU 1
EXTI_SWIER1_SWIER1_len EQU 1
EXTI_SWIER1_SWIER2 EQU 0x00000004 ; Software Interrupt on line 2
EXTI_SWIER1_SWIER2_ofs EQU 2
EXTI_SWIER1_SWIER2_len EQU 1
EXTI_SWIER1_SWIER3 EQU 0x00000008 ; Software Interrupt on line 3
EXTI_SWIER1_SWIER3_ofs EQU 3
EXTI_SWIER1_SWIER3_len EQU 1
EXTI_SWIER1_SWIER4 EQU 0x00000010 ; Software Interrupt on line 4
EXTI_SWIER1_SWIER4_ofs EQU 4
EXTI_SWIER1_SWIER4_len EQU 1
EXTI_SWIER1_SWIER5 EQU 0x00000020 ; Software Interrupt on line 5
EXTI_SWIER1_SWIER5_ofs EQU 5
EXTI_SWIER1_SWIER5_len EQU 1
EXTI_SWIER1_SWIER6 EQU 0x00000040 ; Software Interrupt on line 6
EXTI_SWIER1_SWIER6_ofs EQU 6
EXTI_SWIER1_SWIER6_len EQU 1
EXTI_SWIER1_SWIER7 EQU 0x00000080 ; Software Interrupt on line 7
EXTI_SWIER1_SWIER7_ofs EQU 7
EXTI_SWIER1_SWIER7_len EQU 1
EXTI_SWIER1_SWIER8 EQU 0x00000100 ; Software Interrupt on line 8
EXTI_SWIER1_SWIER8_ofs EQU 8
EXTI_SWIER1_SWIER8_len EQU 1
EXTI_SWIER1_SWIER9 EQU 0x00000200 ; Software Interrupt on line 9
EXTI_SWIER1_SWIER9_ofs EQU 9
EXTI_SWIER1_SWIER9_len EQU 1
EXTI_SWIER1_SWIER10 EQU 0x00000400 ; Software Interrupt on line 10
EXTI_SWIER1_SWIER10_ofs EQU 10
EXTI_SWIER1_SWIER10_len EQU 1
EXTI_SWIER1_SWIER11 EQU 0x00000800 ; Software Interrupt on line 11
EXTI_SWIER1_SWIER11_ofs EQU 11
EXTI_SWIER1_SWIER11_len EQU 1
EXTI_SWIER1_SWIER12 EQU 0x00001000 ; Software Interrupt on line 12
EXTI_SWIER1_SWIER12_ofs EQU 12
EXTI_SWIER1_SWIER12_len EQU 1
EXTI_SWIER1_SWIER13 EQU 0x00002000 ; Software Interrupt on line 13
EXTI_SWIER1_SWIER13_ofs EQU 13
EXTI_SWIER1_SWIER13_len EQU 1
EXTI_SWIER1_SWIER14 EQU 0x00004000 ; Software Interrupt on line 14
EXTI_SWIER1_SWIER14_ofs EQU 14
EXTI_SWIER1_SWIER14_len EQU 1
EXTI_SWIER1_SWIER15 EQU 0x00008000 ; Software Interrupt on line 15
EXTI_SWIER1_SWIER15_ofs EQU 15
EXTI_SWIER1_SWIER15_len EQU 1
EXTI_SWIER1_SWIER16 EQU 0x00010000 ; Software Interrupt on line 16
EXTI_SWIER1_SWIER16_ofs EQU 16
EXTI_SWIER1_SWIER16_len EQU 1
EXTI_SWIER1_SWIER17 EQU 0x00020000 ; Software Interrupt on line 17
EXTI_SWIER1_SWIER17_ofs EQU 17
EXTI_SWIER1_SWIER17_len EQU 1
EXTI_SWIER1_SWIER18 EQU 0x00040000 ; Software Interrupt on line 18
EXTI_SWIER1_SWIER18_ofs EQU 18
EXTI_SWIER1_SWIER18_len EQU 1
EXTI_SWIER1_SWIER19 EQU 0x00080000 ; Software Interrupt on line 19
EXTI_SWIER1_SWIER19_ofs EQU 19
EXTI_SWIER1_SWIER19_len EQU 1
EXTI_SWIER1_SWIER20 EQU 0x00100000 ; Software Interrupt on line 20
EXTI_SWIER1_SWIER20_ofs EQU 20
EXTI_SWIER1_SWIER20_len EQU 1
EXTI_SWIER1_SWIER21 EQU 0x00200000 ; Software Interrupt on line 21
EXTI_SWIER1_SWIER21_ofs EQU 21
EXTI_SWIER1_SWIER21_len EQU 1
EXTI_SWIER1_SWIER22 EQU 0x00400000 ; Software Interrupt on line 22
EXTI_SWIER1_SWIER22_ofs EQU 22
EXTI_SWIER1_SWIER22_len EQU 1
EXTI_SWIER1_SWIER29 EQU 0x20000000 ; Software Interrupt on line 29
EXTI_SWIER1_SWIER29_ofs EQU 29
EXTI_SWIER1_SWIER29_len EQU 1
EXTI_SWIER1_SWIER30 EQU 0x40000000 ; Software Interrupt on line 309
EXTI_SWIER1_SWIER30_ofs EQU 30
EXTI_SWIER1_SWIER30_len EQU 1
EXTI_SWIER1_SWIER31 EQU 0x80000000 ; Software Interrupt on line 319
EXTI_SWIER1_SWIER31_ofs EQU 31
EXTI_SWIER1_SWIER31_len EQU 1
; EXTI_PR1 fields:
EXTI_PR1_PR0 EQU 0x00000001 ; Pending bit 0
EXTI_PR1_PR0_ofs EQU 0
EXTI_PR1_PR0_len EQU 1
EXTI_PR1_PR1 EQU 0x00000002 ; Pending bit 1
EXTI_PR1_PR1_ofs EQU 1
EXTI_PR1_PR1_len EQU 1
EXTI_PR1_PR2 EQU 0x00000004 ; Pending bit 2
EXTI_PR1_PR2_ofs EQU 2
EXTI_PR1_PR2_len EQU 1
EXTI_PR1_PR3 EQU 0x00000008 ; Pending bit 3
EXTI_PR1_PR3_ofs EQU 3
EXTI_PR1_PR3_len EQU 1
EXTI_PR1_PR4 EQU 0x00000010 ; Pending bit 4
EXTI_PR1_PR4_ofs EQU 4
EXTI_PR1_PR4_len EQU 1
EXTI_PR1_PR5 EQU 0x00000020 ; Pending bit 5
EXTI_PR1_PR5_ofs EQU 5
EXTI_PR1_PR5_len EQU 1
EXTI_PR1_PR6 EQU 0x00000040 ; Pending bit 6
EXTI_PR1_PR6_ofs EQU 6
EXTI_PR1_PR6_len EQU 1
EXTI_PR1_PR7 EQU 0x00000080 ; Pending bit 7
EXTI_PR1_PR7_ofs EQU 7
EXTI_PR1_PR7_len EQU 1
EXTI_PR1_PR8 EQU 0x00000100 ; Pending bit 8
EXTI_PR1_PR8_ofs EQU 8
EXTI_PR1_PR8_len EQU 1
EXTI_PR1_PR9 EQU 0x00000200 ; Pending bit 9
EXTI_PR1_PR9_ofs EQU 9
EXTI_PR1_PR9_len EQU 1
EXTI_PR1_PR10 EQU 0x00000400 ; Pending bit 10
EXTI_PR1_PR10_ofs EQU 10
EXTI_PR1_PR10_len EQU 1
EXTI_PR1_PR11 EQU 0x00000800 ; Pending bit 11
EXTI_PR1_PR11_ofs EQU 11
EXTI_PR1_PR11_len EQU 1
EXTI_PR1_PR12 EQU 0x00001000 ; Pending bit 12
EXTI_PR1_PR12_ofs EQU 12
EXTI_PR1_PR12_len EQU 1
EXTI_PR1_PR13 EQU 0x00002000 ; Pending bit 13
EXTI_PR1_PR13_ofs EQU 13
EXTI_PR1_PR13_len EQU 1
EXTI_PR1_PR14 EQU 0x00004000 ; Pending bit 14
EXTI_PR1_PR14_ofs EQU 14
EXTI_PR1_PR14_len EQU 1
EXTI_PR1_PR15 EQU 0x00008000 ; Pending bit 15
EXTI_PR1_PR15_ofs EQU 15
EXTI_PR1_PR15_len EQU 1
EXTI_PR1_PR16 EQU 0x00010000 ; Pending bit 16
EXTI_PR1_PR16_ofs EQU 16
EXTI_PR1_PR16_len EQU 1
EXTI_PR1_PR17 EQU 0x00020000 ; Pending bit 17
EXTI_PR1_PR17_ofs EQU 17
EXTI_PR1_PR17_len EQU 1
EXTI_PR1_PR18 EQU 0x00040000 ; Pending bit 18
EXTI_PR1_PR18_ofs EQU 18
EXTI_PR1_PR18_len EQU 1
EXTI_PR1_PR19 EQU 0x00080000 ; Pending bit 19
EXTI_PR1_PR19_ofs EQU 19
EXTI_PR1_PR19_len EQU 1
EXTI_PR1_PR20 EQU 0x00100000 ; Pending bit 20
EXTI_PR1_PR20_ofs EQU 20
EXTI_PR1_PR20_len EQU 1
EXTI_PR1_PR21 EQU 0x00200000 ; Pending bit 21
EXTI_PR1_PR21_ofs EQU 21
EXTI_PR1_PR21_len EQU 1
EXTI_PR1_PR22 EQU 0x00400000 ; Pending bit 22
EXTI_PR1_PR22_ofs EQU 22
EXTI_PR1_PR22_len EQU 1
EXTI_PR1_PR29 EQU 0x20000000 ; Pending bit 29
EXTI_PR1_PR29_ofs EQU 29
EXTI_PR1_PR29_len EQU 1
EXTI_PR1_PR30 EQU 0x40000000 ; Pending bit 30
EXTI_PR1_PR30_ofs EQU 30
EXTI_PR1_PR30_len EQU 1
EXTI_PR1_PR31 EQU 0x80000000 ; Pending bit 31
EXTI_PR1_PR31_ofs EQU 31
EXTI_PR1_PR31_len EQU 1
; EXTI_IMR2 fields:
EXTI_IMR2_MR32 EQU 0x00000001 ; Interrupt Mask on external/internal line 32
EXTI_IMR2_MR32_ofs EQU 0
EXTI_IMR2_MR32_len EQU 1
EXTI_IMR2_MR33 EQU 0x00000002 ; Interrupt Mask on external/internal line 33
EXTI_IMR2_MR33_ofs EQU 1
EXTI_IMR2_MR33_len EQU 1
EXTI_IMR2_MR34 EQU 0x00000004 ; Interrupt Mask on external/internal line 34
EXTI_IMR2_MR34_ofs EQU 2
EXTI_IMR2_MR34_len EQU 1
EXTI_IMR2_MR35 EQU 0x00000008 ; Interrupt Mask on external/internal line 35
EXTI_IMR2_MR35_ofs EQU 3
EXTI_IMR2_MR35_len EQU 1
; EXTI_EMR2 fields:
EXTI_EMR2_MR32 EQU 0x00000001 ; Event mask on external/internal line 32
EXTI_EMR2_MR32_ofs EQU 0
EXTI_EMR2_MR32_len EQU 1
EXTI_EMR2_MR33 EQU 0x00000002 ; Event mask on external/internal line 33
EXTI_EMR2_MR33_ofs EQU 1
EXTI_EMR2_MR33_len EQU 1
EXTI_EMR2_MR34 EQU 0x00000004 ; Event mask on external/internal line 34
EXTI_EMR2_MR34_ofs EQU 2
EXTI_EMR2_MR34_len EQU 1
EXTI_EMR2_MR35 EQU 0x00000008 ; Event mask on external/internal line 35
EXTI_EMR2_MR35_ofs EQU 3
EXTI_EMR2_MR35_len EQU 1
; EXTI_RTSR2 fields:
EXTI_RTSR2_TR32 EQU 0x00000001 ; Rising trigger event configuration bit of line 32
EXTI_RTSR2_TR32_ofs EQU 0
EXTI_RTSR2_TR32_len EQU 1
EXTI_RTSR2_TR33 EQU 0x00000002 ; Rising trigger event configuration bit of line 33
EXTI_RTSR2_TR33_ofs EQU 1
EXTI_RTSR2_TR33_len EQU 1
; EXTI_FTSR2 fields:
EXTI_FTSR2_TR32 EQU 0x00000001 ; Falling trigger event configuration bit of line 32
EXTI_FTSR2_TR32_ofs EQU 0
EXTI_FTSR2_TR32_len EQU 1
EXTI_FTSR2_TR33 EQU 0x00000002 ; Falling trigger event configuration bit of line 33
EXTI_FTSR2_TR33_ofs EQU 1
EXTI_FTSR2_TR33_len EQU 1
; EXTI_SWIER2 fields:
EXTI_SWIER2_SWIER32 EQU 0x00000001 ; Software interrupt on line 32
EXTI_SWIER2_SWIER32_ofs EQU 0
EXTI_SWIER2_SWIER32_len EQU 1
EXTI_SWIER2_SWIER33 EQU 0x00000002 ; Software interrupt on line 33
EXTI_SWIER2_SWIER33_ofs EQU 1
EXTI_SWIER2_SWIER33_len EQU 1
; EXTI_PR2 fields:
EXTI_PR2_PR32 EQU 0x00000001 ; Pending bit on line 32
EXTI_PR2_PR32_ofs EQU 0
EXTI_PR2_PR32_len EQU 1
EXTI_PR2_PR33 EQU 0x00000002 ; Pending bit on line 33
EXTI_PR2_PR33_ofs EQU 1
EXTI_PR2_PR33_len EQU 1
; ---- COMP --------------------------------------------------
; Desc: Comparator
; COMP base address:
COMP_BASE EQU 0x4001001c
; COMP registers:
COMP_COMP1_CSR EQU (COMP_BASE + 0x0) ; control and status register
COMP_COMP2_CSR EQU (COMP_BASE + 0x4) ; control and status register
COMP_COMP3_CSR EQU (COMP_BASE + 0x8) ; control and status register
COMP_COMP4_CSR EQU (COMP_BASE + 0xc) ; control and status register
COMP_COMP5_CSR EQU (COMP_BASE + 0x10) ; control and status register
COMP_COMP6_CSR EQU (COMP_BASE + 0x14) ; control and status register
COMP_COMP7_CSR EQU (COMP_BASE + 0x18) ; control and status register
; COMP_COMP1_CSR fields:
COMP_COMP1_CSR_COMP1EN EQU 0x00000001 ; Comparator 1 enable
COMP_COMP1_CSR_COMP1EN_ofs EQU 0
COMP_COMP1_CSR_COMP1EN_len EQU 1
COMP_COMP1_CSR_COMP1_INP_DAC EQU 0x00000002 ; COMP1_INP_DAC
COMP_COMP1_CSR_COMP1_INP_DAC_ofs EQU 1
COMP_COMP1_CSR_COMP1_INP_DAC_len EQU 1
COMP_COMP1_CSR_COMP1MODE EQU 0x0000000c ; Comparator 1 mode
COMP_COMP1_CSR_COMP1MODE_ofs EQU 2
COMP_COMP1_CSR_COMP1MODE_len EQU 2
COMP_COMP1_CSR_COMP1INSEL EQU 0x00000070 ; Comparator 1 inverting input selection
COMP_COMP1_CSR_COMP1INSEL_ofs EQU 4
COMP_COMP1_CSR_COMP1INSEL_len EQU 3
COMP_COMP1_CSR_COMP1_OUT_SEL EQU 0x00003c00 ; Comparator 1 output selection
COMP_COMP1_CSR_COMP1_OUT_SEL_ofs EQU 10
COMP_COMP1_CSR_COMP1_OUT_SEL_len EQU 4
COMP_COMP1_CSR_COMP1POL EQU 0x00008000 ; Comparator 1 output polarity
COMP_COMP1_CSR_COMP1POL_ofs EQU 15
COMP_COMP1_CSR_COMP1POL_len EQU 1
COMP_COMP1_CSR_COMP1HYST EQU 0x00030000 ; Comparator 1 hysteresis
COMP_COMP1_CSR_COMP1HYST_ofs EQU 16
COMP_COMP1_CSR_COMP1HYST_len EQU 2
COMP_COMP1_CSR_COMP1_BLANKING EQU 0x001c0000 ; Comparator 1 blanking source
COMP_COMP1_CSR_COMP1_BLANKING_ofs EQU 18
COMP_COMP1_CSR_COMP1_BLANKING_len EQU 3
COMP_COMP1_CSR_COMP1OUT EQU 0x40000000 ; Comparator 1 output
COMP_COMP1_CSR_COMP1OUT_ofs EQU 30
COMP_COMP1_CSR_COMP1OUT_len EQU 1
COMP_COMP1_CSR_COMP1LOCK EQU 0x80000000 ; Comparator 1 lock
COMP_COMP1_CSR_COMP1LOCK_ofs EQU 31
COMP_COMP1_CSR_COMP1LOCK_len EQU 1
; COMP_COMP2_CSR fields:
COMP_COMP2_CSR_COMP2EN EQU 0x00000001 ; Comparator 2 enable
COMP_COMP2_CSR_COMP2EN_ofs EQU 0
COMP_COMP2_CSR_COMP2EN_len EQU 1
COMP_COMP2_CSR_COMP2MODE EQU 0x0000000c ; Comparator 2 mode
COMP_COMP2_CSR_COMP2MODE_ofs EQU 2
COMP_COMP2_CSR_COMP2MODE_len EQU 2
COMP_COMP2_CSR_COMP2INSEL EQU 0x00000070 ; Comparator 2 inverting input selection
COMP_COMP2_CSR_COMP2INSEL_ofs EQU 4
COMP_COMP2_CSR_COMP2INSEL_len EQU 3
COMP_COMP2_CSR_COMP2INPSEL EQU 0x00000080 ; Comparator 2 non inverted input selection
COMP_COMP2_CSR_COMP2INPSEL_ofs EQU 7
COMP_COMP2_CSR_COMP2INPSEL_len EQU 1
COMP_COMP2_CSR_COMP2INMSEL EQU 0x00000200 ; Comparator 1inverting input selection
COMP_COMP2_CSR_COMP2INMSEL_ofs EQU 9
COMP_COMP2_CSR_COMP2INMSEL_len EQU 1
COMP_COMP2_CSR_COMP2_OUT_SEL EQU 0x00003c00 ; Comparator 2 output selection
COMP_COMP2_CSR_COMP2_OUT_SEL_ofs EQU 10
COMP_COMP2_CSR_COMP2_OUT_SEL_len EQU 4
COMP_COMP2_CSR_COMP2POL EQU 0x00008000 ; Comparator 2 output polarity
COMP_COMP2_CSR_COMP2POL_ofs EQU 15
COMP_COMP2_CSR_COMP2POL_len EQU 1
COMP_COMP2_CSR_COMP2HYST EQU 0x00030000 ; Comparator 2 hysteresis
COMP_COMP2_CSR_COMP2HYST_ofs EQU 16
COMP_COMP2_CSR_COMP2HYST_len EQU 2
COMP_COMP2_CSR_COMP2_BLANKING EQU 0x001c0000 ; Comparator 2 blanking source
COMP_COMP2_CSR_COMP2_BLANKING_ofs EQU 18
COMP_COMP2_CSR_COMP2_BLANKING_len EQU 3
COMP_COMP2_CSR_COMP2OUT EQU 0x40000000 ; Comparator 2 output
COMP_COMP2_CSR_COMP2OUT_ofs EQU 30
COMP_COMP2_CSR_COMP2OUT_len EQU 1
COMP_COMP2_CSR_COMP2LOCK EQU 0x80000000 ; Comparator 2 lock
COMP_COMP2_CSR_COMP2LOCK_ofs EQU 31
COMP_COMP2_CSR_COMP2LOCK_len EQU 1
; COMP_COMP3_CSR fields:
COMP_COMP3_CSR_COMP3EN EQU 0x00000001 ; Comparator 3 enable
COMP_COMP3_CSR_COMP3EN_ofs EQU 0
COMP_COMP3_CSR_COMP3EN_len EQU 1
COMP_COMP3_CSR_COMP3MODE EQU 0x0000000c ; Comparator 3 mode
COMP_COMP3_CSR_COMP3MODE_ofs EQU 2
COMP_COMP3_CSR_COMP3MODE_len EQU 2
COMP_COMP3_CSR_COMP3INSEL EQU 0x00000070 ; Comparator 3 inverting input selection
COMP_COMP3_CSR_COMP3INSEL_ofs EQU 4
COMP_COMP3_CSR_COMP3INSEL_len EQU 3
COMP_COMP3_CSR_COMP3INPSEL EQU 0x00000080 ; Comparator 3 non inverted input selection
COMP_COMP3_CSR_COMP3INPSEL_ofs EQU 7
COMP_COMP3_CSR_COMP3INPSEL_len EQU 1
COMP_COMP3_CSR_COMP3_OUT_SEL EQU 0x00003c00 ; Comparator 3 output selection
COMP_COMP3_CSR_COMP3_OUT_SEL_ofs EQU 10
COMP_COMP3_CSR_COMP3_OUT_SEL_len EQU 4
COMP_COMP3_CSR_COMP3POL EQU 0x00008000 ; Comparator 3 output polarity
COMP_COMP3_CSR_COMP3POL_ofs EQU 15
COMP_COMP3_CSR_COMP3POL_len EQU 1
COMP_COMP3_CSR_COMP3HYST EQU 0x00030000 ; Comparator 3 hysteresis
COMP_COMP3_CSR_COMP3HYST_ofs EQU 16
COMP_COMP3_CSR_COMP3HYST_len EQU 2
COMP_COMP3_CSR_COMP3_BLANKING EQU 0x001c0000 ; Comparator 3 blanking source
COMP_COMP3_CSR_COMP3_BLANKING_ofs EQU 18
COMP_COMP3_CSR_COMP3_BLANKING_len EQU 3
COMP_COMP3_CSR_COMP3OUT EQU 0x40000000 ; Comparator 3 output
COMP_COMP3_CSR_COMP3OUT_ofs EQU 30
COMP_COMP3_CSR_COMP3OUT_len EQU 1
COMP_COMP3_CSR_COMP3LOCK EQU 0x80000000 ; Comparator 3 lock
COMP_COMP3_CSR_COMP3LOCK_ofs EQU 31
COMP_COMP3_CSR_COMP3LOCK_len EQU 1
; COMP_COMP4_CSR fields:
COMP_COMP4_CSR_COMP4EN EQU 0x00000001 ; Comparator 4 enable
COMP_COMP4_CSR_COMP4EN_ofs EQU 0
COMP_COMP4_CSR_COMP4EN_len EQU 1
COMP_COMP4_CSR_COMP4MODE EQU 0x0000000c ; Comparator 4 mode
COMP_COMP4_CSR_COMP4MODE_ofs EQU 2
COMP_COMP4_CSR_COMP4MODE_len EQU 2
COMP_COMP4_CSR_COMP4INSEL EQU 0x00000070 ; Comparator 4 inverting input selection
COMP_COMP4_CSR_COMP4INSEL_ofs EQU 4
COMP_COMP4_CSR_COMP4INSEL_len EQU 3
COMP_COMP4_CSR_COMP4INPSEL EQU 0x00000080 ; Comparator 4 non inverted input selection
COMP_COMP4_CSR_COMP4INPSEL_ofs EQU 7
COMP_COMP4_CSR_COMP4INPSEL_len EQU 1
COMP_COMP4_CSR_COM4WINMODE EQU 0x00000200 ; Comparator 4 window mode
COMP_COMP4_CSR_COM4WINMODE_ofs EQU 9
COMP_COMP4_CSR_COM4WINMODE_len EQU 1
COMP_COMP4_CSR_COMP4_OUT_SEL EQU 0x00003c00 ; Comparator 4 output selection
COMP_COMP4_CSR_COMP4_OUT_SEL_ofs EQU 10
COMP_COMP4_CSR_COMP4_OUT_SEL_len EQU 4
COMP_COMP4_CSR_COMP4POL EQU 0x00008000 ; Comparator 4 output polarity
COMP_COMP4_CSR_COMP4POL_ofs EQU 15
COMP_COMP4_CSR_COMP4POL_len EQU 1
COMP_COMP4_CSR_COMP4HYST EQU 0x00030000 ; Comparator 4 hysteresis
COMP_COMP4_CSR_COMP4HYST_ofs EQU 16
COMP_COMP4_CSR_COMP4HYST_len EQU 2
COMP_COMP4_CSR_COMP4_BLANKING EQU 0x001c0000 ; Comparator 4 blanking source
COMP_COMP4_CSR_COMP4_BLANKING_ofs EQU 18
COMP_COMP4_CSR_COMP4_BLANKING_len EQU 3
COMP_COMP4_CSR_COMP4OUT EQU 0x40000000 ; Comparator 4 output
COMP_COMP4_CSR_COMP4OUT_ofs EQU 30
COMP_COMP4_CSR_COMP4OUT_len EQU 1
COMP_COMP4_CSR_COMP4LOCK EQU 0x80000000 ; Comparator 4 lock
COMP_COMP4_CSR_COMP4LOCK_ofs EQU 31
COMP_COMP4_CSR_COMP4LOCK_len EQU 1
; COMP_COMP5_CSR fields:
COMP_COMP5_CSR_COMP5EN EQU 0x00000001 ; Comparator 5 enable
COMP_COMP5_CSR_COMP5EN_ofs EQU 0
COMP_COMP5_CSR_COMP5EN_len EQU 1
COMP_COMP5_CSR_COMP5MODE EQU 0x0000000c ; Comparator 5 mode
COMP_COMP5_CSR_COMP5MODE_ofs EQU 2
COMP_COMP5_CSR_COMP5MODE_len EQU 2
COMP_COMP5_CSR_COMP5INSEL EQU 0x00000070 ; Comparator 5 inverting input selection
COMP_COMP5_CSR_COMP5INSEL_ofs EQU 4
COMP_COMP5_CSR_COMP5INSEL_len EQU 3
COMP_COMP5_CSR_COMP5INPSEL EQU 0x00000080 ; Comparator 5 non inverted input selection
COMP_COMP5_CSR_COMP5INPSEL_ofs EQU 7
COMP_COMP5_CSR_COMP5INPSEL_len EQU 1
COMP_COMP5_CSR_COMP5_OUT_SEL EQU 0x00003c00 ; Comparator 5 output selection
COMP_COMP5_CSR_COMP5_OUT_SEL_ofs EQU 10
COMP_COMP5_CSR_COMP5_OUT_SEL_len EQU 4
COMP_COMP5_CSR_COMP5POL EQU 0x00008000 ; Comparator 5 output polarity
COMP_COMP5_CSR_COMP5POL_ofs EQU 15
COMP_COMP5_CSR_COMP5POL_len EQU 1
COMP_COMP5_CSR_COMP5HYST EQU 0x00030000 ; Comparator 5 hysteresis
COMP_COMP5_CSR_COMP5HYST_ofs EQU 16
COMP_COMP5_CSR_COMP5HYST_len EQU 2
COMP_COMP5_CSR_COMP5_BLANKING EQU 0x001c0000 ; Comparator 5 blanking source
COMP_COMP5_CSR_COMP5_BLANKING_ofs EQU 18
COMP_COMP5_CSR_COMP5_BLANKING_len EQU 3
COMP_COMP5_CSR_COMP5OUT EQU 0x40000000 ; Comparator51 output
COMP_COMP5_CSR_COMP5OUT_ofs EQU 30
COMP_COMP5_CSR_COMP5OUT_len EQU 1
COMP_COMP5_CSR_COMP5LOCK EQU 0x80000000 ; Comparator 5 lock
COMP_COMP5_CSR_COMP5LOCK_ofs EQU 31
COMP_COMP5_CSR_COMP5LOCK_len EQU 1
; COMP_COMP6_CSR fields:
COMP_COMP6_CSR_COMP6EN EQU 0x00000001 ; Comparator 6 enable
COMP_COMP6_CSR_COMP6EN_ofs EQU 0
COMP_COMP6_CSR_COMP6EN_len EQU 1
COMP_COMP6_CSR_COMP6MODE EQU 0x0000000c ; Comparator 6 mode
COMP_COMP6_CSR_COMP6MODE_ofs EQU 2
COMP_COMP6_CSR_COMP6MODE_len EQU 2
COMP_COMP6_CSR_COMP6INSEL EQU 0x00000070 ; Comparator 6 inverting input selection
COMP_COMP6_CSR_COMP6INSEL_ofs EQU 4
COMP_COMP6_CSR_COMP6INSEL_len EQU 3
COMP_COMP6_CSR_COMP6INPSEL EQU 0x00000080 ; Comparator 6 non inverted input selection
COMP_COMP6_CSR_COMP6INPSEL_ofs EQU 7
COMP_COMP6_CSR_COMP6INPSEL_len EQU 1
COMP_COMP6_CSR_COM6WINMODE EQU 0x00000200 ; Comparator 6 window mode
COMP_COMP6_CSR_COM6WINMODE_ofs EQU 9
COMP_COMP6_CSR_COM6WINMODE_len EQU 1
COMP_COMP6_CSR_COMP6_OUT_SEL EQU 0x00003c00 ; Comparator 6 output selection
COMP_COMP6_CSR_COMP6_OUT_SEL_ofs EQU 10
COMP_COMP6_CSR_COMP6_OUT_SEL_len EQU 4
COMP_COMP6_CSR_COMP6POL EQU 0x00008000 ; Comparator 6 output polarity
COMP_COMP6_CSR_COMP6POL_ofs EQU 15
COMP_COMP6_CSR_COMP6POL_len EQU 1
COMP_COMP6_CSR_COMP6HYST EQU 0x00030000 ; Comparator 6 hysteresis
COMP_COMP6_CSR_COMP6HYST_ofs EQU 16
COMP_COMP6_CSR_COMP6HYST_len EQU 2
COMP_COMP6_CSR_COMP6_BLANKING EQU 0x001c0000 ; Comparator 6 blanking source
COMP_COMP6_CSR_COMP6_BLANKING_ofs EQU 18
COMP_COMP6_CSR_COMP6_BLANKING_len EQU 3
COMP_COMP6_CSR_COMP6OUT EQU 0x40000000 ; Comparator 6 output
COMP_COMP6_CSR_COMP6OUT_ofs EQU 30
COMP_COMP6_CSR_COMP6OUT_len EQU 1
COMP_COMP6_CSR_COMP6LOCK EQU 0x80000000 ; Comparator 6 lock
COMP_COMP6_CSR_COMP6LOCK_ofs EQU 31
COMP_COMP6_CSR_COMP6LOCK_len EQU 1
; COMP_COMP7_CSR fields:
COMP_COMP7_CSR_COMP7EN EQU 0x00000001 ; Comparator 7 enable
COMP_COMP7_CSR_COMP7EN_ofs EQU 0
COMP_COMP7_CSR_COMP7EN_len EQU 1
COMP_COMP7_CSR_COMP7MODE EQU 0x0000000c ; Comparator 7 mode
COMP_COMP7_CSR_COMP7MODE_ofs EQU 2
COMP_COMP7_CSR_COMP7MODE_len EQU 2
COMP_COMP7_CSR_COMP7INSEL EQU 0x00000070 ; Comparator 7 inverting input selection
COMP_COMP7_CSR_COMP7INSEL_ofs EQU 4
COMP_COMP7_CSR_COMP7INSEL_len EQU 3
COMP_COMP7_CSR_COMP7INPSEL EQU 0x00000080 ; Comparator 7 non inverted input selection
COMP_COMP7_CSR_COMP7INPSEL_ofs EQU 7
COMP_COMP7_CSR_COMP7INPSEL_len EQU 1
COMP_COMP7_CSR_COMP7_OUT_SEL EQU 0x00003c00 ; Comparator 7 output selection
COMP_COMP7_CSR_COMP7_OUT_SEL_ofs EQU 10
COMP_COMP7_CSR_COMP7_OUT_SEL_len EQU 4
COMP_COMP7_CSR_COMP7POL EQU 0x00008000 ; Comparator 7 output polarity
COMP_COMP7_CSR_COMP7POL_ofs EQU 15
COMP_COMP7_CSR_COMP7POL_len EQU 1
COMP_COMP7_CSR_COMP7HYST EQU 0x00030000 ; Comparator 7 hysteresis
COMP_COMP7_CSR_COMP7HYST_ofs EQU 16
COMP_COMP7_CSR_COMP7HYST_len EQU 2
COMP_COMP7_CSR_COMP7_BLANKING EQU 0x001c0000 ; Comparator 7 blanking source
COMP_COMP7_CSR_COMP7_BLANKING_ofs EQU 18
COMP_COMP7_CSR_COMP7_BLANKING_len EQU 3
COMP_COMP7_CSR_COMP7OUT EQU 0x40000000 ; Comparator 7 output
COMP_COMP7_CSR_COMP7OUT_ofs EQU 30
COMP_COMP7_CSR_COMP7OUT_len EQU 1
COMP_COMP7_CSR_COMP7LOCK EQU 0x80000000 ; Comparator 7 lock
COMP_COMP7_CSR_COMP7LOCK_ofs EQU 31
COMP_COMP7_CSR_COMP7LOCK_len EQU 1
; ---- PWR ---------------------------------------------------
; Desc: Power control
; PWR base address:
PWR_BASE EQU 0x40007000
; PWR registers:
PWR_CR EQU (PWR_BASE + 0x0) ; power control register
PWR_CSR EQU (PWR_BASE + 0x4) ; power control/status register
; PWR_CR fields:
PWR_CR_LPDS EQU 0x00000001 ; Low-power deep sleep
PWR_CR_LPDS_ofs EQU 0
PWR_CR_LPDS_len EQU 1
PWR_CR_PDDS EQU 0x00000002 ; Power down deepsleep
PWR_CR_PDDS_ofs EQU 1
PWR_CR_PDDS_len EQU 1
PWR_CR_CWUF EQU 0x00000004 ; Clear wakeup flag
PWR_CR_CWUF_ofs EQU 2
PWR_CR_CWUF_len EQU 1
PWR_CR_CSBF EQU 0x00000008 ; Clear standby flag
PWR_CR_CSBF_ofs EQU 3
PWR_CR_CSBF_len EQU 1
PWR_CR_PVDE EQU 0x00000010 ; Power voltage detector enable
PWR_CR_PVDE_ofs EQU 4
PWR_CR_PVDE_len EQU 1
PWR_CR_PLS EQU 0x000000e0 ; PVD level selection
PWR_CR_PLS_ofs EQU 5
PWR_CR_PLS_len EQU 3
PWR_CR_DBP EQU 0x00000100 ; Disable backup domain write protection
PWR_CR_DBP_ofs EQU 8
PWR_CR_DBP_len EQU 1
; PWR_CSR fields:
PWR_CSR_WUF EQU 0x00000001 ; Wakeup flag
PWR_CSR_WUF_ofs EQU 0
PWR_CSR_WUF_len EQU 1
PWR_CSR_SBF EQU 0x00000002 ; Standby flag
PWR_CSR_SBF_ofs EQU 1
PWR_CSR_SBF_len EQU 1
PWR_CSR_PVDO EQU 0x00000004 ; PVD output
PWR_CSR_PVDO_ofs EQU 2
PWR_CSR_PVDO_len EQU 1
PWR_CSR_EWUP1 EQU 0x00000100 ; Enable WKUP1 pin
PWR_CSR_EWUP1_ofs EQU 8
PWR_CSR_EWUP1_len EQU 1
PWR_CSR_EWUP2 EQU 0x00000200 ; Enable WKUP2 pin
PWR_CSR_EWUP2_ofs EQU 9
PWR_CSR_EWUP2_len EQU 1
; ---- CAN ---------------------------------------------------
; Desc: Controller area network
; CAN base address:
CAN_BASE EQU 0x40006400
; CAN registers:
CAN_MCR EQU (CAN_BASE + 0x0) ; master control register
CAN_MSR EQU (CAN_BASE + 0x4) ; master status register
CAN_TSR EQU (CAN_BASE + 0x8) ; transmit status register
CAN_RF0R EQU (CAN_BASE + 0xc) ; receive FIFO 0 register
CAN_RF1R EQU (CAN_BASE + 0x10) ; receive FIFO 1 register
CAN_IER EQU (CAN_BASE + 0x14) ; interrupt enable register
CAN_ESR EQU (CAN_BASE + 0x18) ; error status register
CAN_BTR EQU (CAN_BASE + 0x1c) ; bit timing register
CAN_TI0R EQU (CAN_BASE + 0x180) ; TX mailbox identifier register
CAN_TDT0R EQU (CAN_BASE + 0x184) ; mailbox data length control and time stamp register
CAN_TDL0R EQU (CAN_BASE + 0x188) ; mailbox data low register
CAN_TDH0R EQU (CAN_BASE + 0x18c) ; mailbox data high register
CAN_TI1R EQU (CAN_BASE + 0x190) ; TX mailbox identifier register
CAN_TDT1R EQU (CAN_BASE + 0x194) ; mailbox data length control and time stamp register
CAN_TDL1R EQU (CAN_BASE + 0x198) ; mailbox data low register
CAN_TDH1R EQU (CAN_BASE + 0x19c) ; mailbox data high register
CAN_TI2R EQU (CAN_BASE + 0x1a0) ; TX mailbox identifier register
CAN_TDT2R EQU (CAN_BASE + 0x1a4) ; mailbox data length control and time stamp register
CAN_TDL2R EQU (CAN_BASE + 0x1a8) ; mailbox data low register
CAN_TDH2R EQU (CAN_BASE + 0x1ac) ; mailbox data high register
CAN_RI0R EQU (CAN_BASE + 0x1b0) ; receive FIFO mailbox identifier register
CAN_RDT0R EQU (CAN_BASE + 0x1b4) ; receive FIFO mailbox data length control and time stamp register
CAN_RDL0R EQU (CAN_BASE + 0x1b8) ; receive FIFO mailbox data low register
CAN_RDH0R EQU (CAN_BASE + 0x1bc) ; receive FIFO mailbox data high register
CAN_RI1R EQU (CAN_BASE + 0x1c0) ; receive FIFO mailbox identifier register
CAN_RDT1R EQU (CAN_BASE + 0x1c4) ; receive FIFO mailbox data length control and time stamp register
CAN_RDL1R EQU (CAN_BASE + 0x1c8) ; receive FIFO mailbox data low register
CAN_RDH1R EQU (CAN_BASE + 0x1cc) ; receive FIFO mailbox data high register
CAN_FMR EQU (CAN_BASE + 0x200) ; filter master register
CAN_FM1R EQU (CAN_BASE + 0x204) ; filter mode register
CAN_FS1R EQU (CAN_BASE + 0x20c) ; filter scale register
CAN_FFA1R EQU (CAN_BASE + 0x214) ; filter FIFO assignment register
CAN_FA1R EQU (CAN_BASE + 0x21c) ; CAN filter activation register
CAN_F0R1 EQU (CAN_BASE + 0x240) ; Filter bank 0 register 1
CAN_F0R2 EQU (CAN_BASE + 0x244) ; Filter bank 0 register 2
CAN_F1R1 EQU (CAN_BASE + 0x248) ; Filter bank 1 register 1
CAN_F1R2 EQU (CAN_BASE + 0x24c) ; Filter bank 1 register 2
CAN_F2R1 EQU (CAN_BASE + 0x250) ; Filter bank 2 register 1
CAN_F2R2 EQU (CAN_BASE + 0x254) ; Filter bank 2 register 2
CAN_F3R1 EQU (CAN_BASE + 0x258) ; Filter bank 3 register 1
CAN_F3R2 EQU (CAN_BASE + 0x25c) ; Filter bank 3 register 2
CAN_F4R1 EQU (CAN_BASE + 0x260) ; Filter bank 4 register 1
CAN_F4R2 EQU (CAN_BASE + 0x264) ; Filter bank 4 register 2
CAN_F5R1 EQU (CAN_BASE + 0x268) ; Filter bank 5 register 1
CAN_F5R2 EQU (CAN_BASE + 0x26c) ; Filter bank 5 register 2
CAN_F6R1 EQU (CAN_BASE + 0x270) ; Filter bank 6 register 1
CAN_F6R2 EQU (CAN_BASE + 0x274) ; Filter bank 6 register 2
CAN_F7R1 EQU (CAN_BASE + 0x278) ; Filter bank 7 register 1
CAN_F7R2 EQU (CAN_BASE + 0x27c) ; Filter bank 7 register 2
CAN_F8R1 EQU (CAN_BASE + 0x280) ; Filter bank 8 register 1
CAN_F8R2 EQU (CAN_BASE + 0x284) ; Filter bank 8 register 2
CAN_F9R1 EQU (CAN_BASE + 0x288) ; Filter bank 9 register 1
CAN_F9R2 EQU (CAN_BASE + 0x28c) ; Filter bank 9 register 2
CAN_F10R1 EQU (CAN_BASE + 0x290) ; Filter bank 10 register 1
CAN_F10R2 EQU (CAN_BASE + 0x294) ; Filter bank 10 register 2
CAN_F11R1 EQU (CAN_BASE + 0x298) ; Filter bank 11 register 1
CAN_F11R2 EQU (CAN_BASE + 0x29c) ; Filter bank 11 register 2
CAN_F12R1 EQU (CAN_BASE + 0x2a0) ; Filter bank 4 register 1
CAN_F12R2 EQU (CAN_BASE + 0x2a4) ; Filter bank 12 register 2
CAN_F13R1 EQU (CAN_BASE + 0x2a8) ; Filter bank 13 register 1
CAN_F13R2 EQU (CAN_BASE + 0x2ac) ; Filter bank 13 register 2
CAN_F14R1 EQU (CAN_BASE + 0x2b0) ; Filter bank 14 register 1
CAN_F14R2 EQU (CAN_BASE + 0x2b4) ; Filter bank 14 register 2
CAN_F15R1 EQU (CAN_BASE + 0x2b8) ; Filter bank 15 register 1
CAN_F15R2 EQU (CAN_BASE + 0x2bc) ; Filter bank 15 register 2
CAN_F16R1 EQU (CAN_BASE + 0x2c0) ; Filter bank 16 register 1
CAN_F16R2 EQU (CAN_BASE + 0x2c4) ; Filter bank 16 register 2
CAN_F17R1 EQU (CAN_BASE + 0x2c8) ; Filter bank 17 register 1
CAN_F17R2 EQU (CAN_BASE + 0x2cc) ; Filter bank 17 register 2
CAN_F18R1 EQU (CAN_BASE + 0x2d0) ; Filter bank 18 register 1
CAN_F18R2 EQU (CAN_BASE + 0x2d4) ; Filter bank 18 register 2
CAN_F19R1 EQU (CAN_BASE + 0x2d8) ; Filter bank 19 register 1
CAN_F19R2 EQU (CAN_BASE + 0x2dc) ; Filter bank 19 register 2
CAN_F20R1 EQU (CAN_BASE + 0x2e0) ; Filter bank 20 register 1
CAN_F20R2 EQU (CAN_BASE + 0x2e4) ; Filter bank 20 register 2
CAN_F21R1 EQU (CAN_BASE + 0x2e8) ; Filter bank 21 register 1
CAN_F21R2 EQU (CAN_BASE + 0x2ec) ; Filter bank 21 register 2
CAN_F22R1 EQU (CAN_BASE + 0x2f0) ; Filter bank 22 register 1
CAN_F22R2 EQU (CAN_BASE + 0x2f4) ; Filter bank 22 register 2
CAN_F23R1 EQU (CAN_BASE + 0x2f8) ; Filter bank 23 register 1
CAN_F23R2 EQU (CAN_BASE + 0x2fc) ; Filter bank 23 register 2
CAN_F24R1 EQU (CAN_BASE + 0x300) ; Filter bank 24 register 1
CAN_F24R2 EQU (CAN_BASE + 0x304) ; Filter bank 24 register 2
CAN_F25R1 EQU (CAN_BASE + 0x308) ; Filter bank 25 register 1
CAN_F25R2 EQU (CAN_BASE + 0x30c) ; Filter bank 25 register 2
CAN_F26R1 EQU (CAN_BASE + 0x310) ; Filter bank 26 register 1
CAN_F26R2 EQU (CAN_BASE + 0x314) ; Filter bank 26 register 2
CAN_F27R1 EQU (CAN_BASE + 0x318) ; Filter bank 27 register 1
CAN_F27R2 EQU (CAN_BASE + 0x31c) ; Filter bank 27 register 2
; CAN_MCR fields:
CAN_MCR_DBF EQU 0x00010000 ; DBF
CAN_MCR_DBF_ofs EQU 16
CAN_MCR_DBF_len EQU 1
CAN_MCR_RESET EQU 0x00008000 ; RESET
CAN_MCR_RESET_ofs EQU 15
CAN_MCR_RESET_len EQU 1
CAN_MCR_TTCM EQU 0x00000080 ; TTCM
CAN_MCR_TTCM_ofs EQU 7
CAN_MCR_TTCM_len EQU 1
CAN_MCR_ABOM EQU 0x00000040 ; ABOM
CAN_MCR_ABOM_ofs EQU 6
CAN_MCR_ABOM_len EQU 1
CAN_MCR_AWUM EQU 0x00000020 ; AWUM
CAN_MCR_AWUM_ofs EQU 5
CAN_MCR_AWUM_len EQU 1
CAN_MCR_NART EQU 0x00000010 ; NART
CAN_MCR_NART_ofs EQU 4
CAN_MCR_NART_len EQU 1
CAN_MCR_RFLM EQU 0x00000008 ; RFLM
CAN_MCR_RFLM_ofs EQU 3
CAN_MCR_RFLM_len EQU 1
CAN_MCR_TXFP EQU 0x00000004 ; TXFP
CAN_MCR_TXFP_ofs EQU 2
CAN_MCR_TXFP_len EQU 1
CAN_MCR_SLEEP EQU 0x00000002 ; SLEEP
CAN_MCR_SLEEP_ofs EQU 1
CAN_MCR_SLEEP_len EQU 1
CAN_MCR_INRQ EQU 0x00000001 ; INRQ
CAN_MCR_INRQ_ofs EQU 0
CAN_MCR_INRQ_len EQU 1
; CAN_MSR fields:
CAN_MSR_RX EQU 0x00000800 ; RX
CAN_MSR_RX_ofs EQU 11
CAN_MSR_RX_len EQU 1
CAN_MSR_SAMP EQU 0x00000400 ; SAMP
CAN_MSR_SAMP_ofs EQU 10
CAN_MSR_SAMP_len EQU 1
CAN_MSR_RXM EQU 0x00000200 ; RXM
CAN_MSR_RXM_ofs EQU 9
CAN_MSR_RXM_len EQU 1
CAN_MSR_TXM EQU 0x00000100 ; TXM
CAN_MSR_TXM_ofs EQU 8
CAN_MSR_TXM_len EQU 1
CAN_MSR_SLAKI EQU 0x00000010 ; SLAKI
CAN_MSR_SLAKI_ofs EQU 4
CAN_MSR_SLAKI_len EQU 1
CAN_MSR_WKUI EQU 0x00000008 ; WKUI
CAN_MSR_WKUI_ofs EQU 3
CAN_MSR_WKUI_len EQU 1
CAN_MSR_ERRI EQU 0x00000004 ; ERRI
CAN_MSR_ERRI_ofs EQU 2
CAN_MSR_ERRI_len EQU 1
CAN_MSR_SLAK EQU 0x00000002 ; SLAK
CAN_MSR_SLAK_ofs EQU 1
CAN_MSR_SLAK_len EQU 1
CAN_MSR_INAK EQU 0x00000001 ; INAK
CAN_MSR_INAK_ofs EQU 0
CAN_MSR_INAK_len EQU 1
; CAN_TSR fields:
CAN_TSR_LOW2 EQU 0x80000000 ; Lowest priority flag for mailbox 2
CAN_TSR_LOW2_ofs EQU 31
CAN_TSR_LOW2_len EQU 1
CAN_TSR_LOW1 EQU 0x40000000 ; Lowest priority flag for mailbox 1
CAN_TSR_LOW1_ofs EQU 30
CAN_TSR_LOW1_len EQU 1
CAN_TSR_LOW0 EQU 0x20000000 ; Lowest priority flag for mailbox 0
CAN_TSR_LOW0_ofs EQU 29
CAN_TSR_LOW0_len EQU 1
CAN_TSR_TME2 EQU 0x10000000 ; Lowest priority flag for mailbox 2
CAN_TSR_TME2_ofs EQU 28
CAN_TSR_TME2_len EQU 1
CAN_TSR_TME1 EQU 0x08000000 ; Lowest priority flag for mailbox 1
CAN_TSR_TME1_ofs EQU 27
CAN_TSR_TME1_len EQU 1
CAN_TSR_TME0 EQU 0x04000000 ; Lowest priority flag for mailbox 0
CAN_TSR_TME0_ofs EQU 26
CAN_TSR_TME0_len EQU 1
CAN_TSR_CODE EQU 0x03000000 ; CODE
CAN_TSR_CODE_ofs EQU 24
CAN_TSR_CODE_len EQU 2
CAN_TSR_ABRQ2 EQU 0x00800000 ; ABRQ2
CAN_TSR_ABRQ2_ofs EQU 23
CAN_TSR_ABRQ2_len EQU 1
CAN_TSR_TERR2 EQU 0x00080000 ; TERR2
CAN_TSR_TERR2_ofs EQU 19
CAN_TSR_TERR2_len EQU 1
CAN_TSR_ALST2 EQU 0x00040000 ; ALST2
CAN_TSR_ALST2_ofs EQU 18
CAN_TSR_ALST2_len EQU 1
CAN_TSR_TXOK2 EQU 0x00020000 ; TXOK2
CAN_TSR_TXOK2_ofs EQU 17
CAN_TSR_TXOK2_len EQU 1
CAN_TSR_RQCP2 EQU 0x00010000 ; RQCP2
CAN_TSR_RQCP2_ofs EQU 16
CAN_TSR_RQCP2_len EQU 1
CAN_TSR_ABRQ1 EQU 0x00008000 ; ABRQ1
CAN_TSR_ABRQ1_ofs EQU 15
CAN_TSR_ABRQ1_len EQU 1
CAN_TSR_TERR1 EQU 0x00000800 ; TERR1
CAN_TSR_TERR1_ofs EQU 11
CAN_TSR_TERR1_len EQU 1
CAN_TSR_ALST1 EQU 0x00000400 ; ALST1
CAN_TSR_ALST1_ofs EQU 10
CAN_TSR_ALST1_len EQU 1
CAN_TSR_TXOK1 EQU 0x00000200 ; TXOK1
CAN_TSR_TXOK1_ofs EQU 9
CAN_TSR_TXOK1_len EQU 1
CAN_TSR_RQCP1 EQU 0x00000100 ; RQCP1
CAN_TSR_RQCP1_ofs EQU 8
CAN_TSR_RQCP1_len EQU 1
CAN_TSR_ABRQ0 EQU 0x00000080 ; ABRQ0
CAN_TSR_ABRQ0_ofs EQU 7
CAN_TSR_ABRQ0_len EQU 1
CAN_TSR_TERR0 EQU 0x00000008 ; TERR0
CAN_TSR_TERR0_ofs EQU 3
CAN_TSR_TERR0_len EQU 1
CAN_TSR_ALST0 EQU 0x00000004 ; ALST0
CAN_TSR_ALST0_ofs EQU 2
CAN_TSR_ALST0_len EQU 1
CAN_TSR_TXOK0 EQU 0x00000002 ; TXOK0
CAN_TSR_TXOK0_ofs EQU 1
CAN_TSR_TXOK0_len EQU 1
CAN_TSR_RQCP0 EQU 0x00000001 ; RQCP0
CAN_TSR_RQCP0_ofs EQU 0
CAN_TSR_RQCP0_len EQU 1
; CAN_RF0R fields:
CAN_RF0R_RFOM0 EQU 0x00000020 ; RFOM0
CAN_RF0R_RFOM0_ofs EQU 5
CAN_RF0R_RFOM0_len EQU 1
CAN_RF0R_FOVR0 EQU 0x00000010 ; FOVR0
CAN_RF0R_FOVR0_ofs EQU 4
CAN_RF0R_FOVR0_len EQU 1
CAN_RF0R_FULL0 EQU 0x00000008 ; FULL0
CAN_RF0R_FULL0_ofs EQU 3
CAN_RF0R_FULL0_len EQU 1
CAN_RF0R_FMP0 EQU 0x00000003 ; FMP0
CAN_RF0R_FMP0_ofs EQU 0
CAN_RF0R_FMP0_len EQU 2
; CAN_RF1R fields:
CAN_RF1R_RFOM1 EQU 0x00000020 ; RFOM1
CAN_RF1R_RFOM1_ofs EQU 5
CAN_RF1R_RFOM1_len EQU 1
CAN_RF1R_FOVR1 EQU 0x00000010 ; FOVR1
CAN_RF1R_FOVR1_ofs EQU 4
CAN_RF1R_FOVR1_len EQU 1
CAN_RF1R_FULL1 EQU 0x00000008 ; FULL1
CAN_RF1R_FULL1_ofs EQU 3
CAN_RF1R_FULL1_len EQU 1
CAN_RF1R_FMP1 EQU 0x00000003 ; FMP1
CAN_RF1R_FMP1_ofs EQU 0
CAN_RF1R_FMP1_len EQU 2
; CAN_IER fields:
CAN_IER_SLKIE EQU 0x00020000 ; SLKIE
CAN_IER_SLKIE_ofs EQU 17
CAN_IER_SLKIE_len EQU 1
CAN_IER_WKUIE EQU 0x00010000 ; WKUIE
CAN_IER_WKUIE_ofs EQU 16
CAN_IER_WKUIE_len EQU 1
CAN_IER_ERRIE EQU 0x00008000 ; ERRIE
CAN_IER_ERRIE_ofs EQU 15
CAN_IER_ERRIE_len EQU 1
CAN_IER_LECIE EQU 0x00000800 ; LECIE
CAN_IER_LECIE_ofs EQU 11
CAN_IER_LECIE_len EQU 1
CAN_IER_BOFIE EQU 0x00000400 ; BOFIE
CAN_IER_BOFIE_ofs EQU 10
CAN_IER_BOFIE_len EQU 1
CAN_IER_EPVIE EQU 0x00000200 ; EPVIE
CAN_IER_EPVIE_ofs EQU 9
CAN_IER_EPVIE_len EQU 1
CAN_IER_EWGIE EQU 0x00000100 ; EWGIE
CAN_IER_EWGIE_ofs EQU 8
CAN_IER_EWGIE_len EQU 1
CAN_IER_FOVIE1 EQU 0x00000040 ; FOVIE1
CAN_IER_FOVIE1_ofs EQU 6
CAN_IER_FOVIE1_len EQU 1
CAN_IER_FFIE1 EQU 0x00000020 ; FFIE1
CAN_IER_FFIE1_ofs EQU 5
CAN_IER_FFIE1_len EQU 1
CAN_IER_FMPIE1 EQU 0x00000010 ; FMPIE1
CAN_IER_FMPIE1_ofs EQU 4
CAN_IER_FMPIE1_len EQU 1
CAN_IER_FOVIE0 EQU 0x00000008 ; FOVIE0
CAN_IER_FOVIE0_ofs EQU 3
CAN_IER_FOVIE0_len EQU 1
CAN_IER_FFIE0 EQU 0x00000004 ; FFIE0
CAN_IER_FFIE0_ofs EQU 2
CAN_IER_FFIE0_len EQU 1
CAN_IER_FMPIE0 EQU 0x00000002 ; FMPIE0
CAN_IER_FMPIE0_ofs EQU 1
CAN_IER_FMPIE0_len EQU 1
CAN_IER_TMEIE EQU 0x00000001 ; TMEIE
CAN_IER_TMEIE_ofs EQU 0
CAN_IER_TMEIE_len EQU 1
; CAN_ESR fields:
CAN_ESR_REC EQU 0xff000000 ; REC
CAN_ESR_REC_ofs EQU 24
CAN_ESR_REC_len EQU 8
CAN_ESR_TEC EQU 0x00ff0000 ; TEC
CAN_ESR_TEC_ofs EQU 16
CAN_ESR_TEC_len EQU 8
CAN_ESR_LEC EQU 0x00000070 ; LEC
CAN_ESR_LEC_ofs EQU 4
CAN_ESR_LEC_len EQU 3
CAN_ESR_BOFF EQU 0x00000004 ; BOFF
CAN_ESR_BOFF_ofs EQU 2
CAN_ESR_BOFF_len EQU 1
CAN_ESR_EPVF EQU 0x00000002 ; EPVF
CAN_ESR_EPVF_ofs EQU 1
CAN_ESR_EPVF_len EQU 1
CAN_ESR_EWGF EQU 0x00000001 ; EWGF
CAN_ESR_EWGF_ofs EQU 0
CAN_ESR_EWGF_len EQU 1
; CAN_BTR fields:
CAN_BTR_SILM EQU 0x80000000 ; SILM
CAN_BTR_SILM_ofs EQU 31
CAN_BTR_SILM_len EQU 1
CAN_BTR_LBKM EQU 0x40000000 ; LBKM
CAN_BTR_LBKM_ofs EQU 30
CAN_BTR_LBKM_len EQU 1
CAN_BTR_SJW EQU 0x03000000 ; SJW
CAN_BTR_SJW_ofs EQU 24
CAN_BTR_SJW_len EQU 2
CAN_BTR_TS2 EQU 0x00700000 ; TS2
CAN_BTR_TS2_ofs EQU 20
CAN_BTR_TS2_len EQU 3
CAN_BTR_TS1 EQU 0x000f0000 ; TS1
CAN_BTR_TS1_ofs EQU 16
CAN_BTR_TS1_len EQU 4
CAN_BTR_BRP EQU 0x000003ff ; BRP
CAN_BTR_BRP_ofs EQU 0
CAN_BTR_BRP_len EQU 10
; CAN_TI0R fields:
CAN_TI0R_STID EQU 0xffe00000 ; STID
CAN_TI0R_STID_ofs EQU 21
CAN_TI0R_STID_len EQU 11
CAN_TI0R_EXID EQU 0x001ffff8 ; EXID
CAN_TI0R_EXID_ofs EQU 3
CAN_TI0R_EXID_len EQU 18
CAN_TI0R_IDE EQU 0x00000004 ; IDE
CAN_TI0R_IDE_ofs EQU 2
CAN_TI0R_IDE_len EQU 1
CAN_TI0R_RTR EQU 0x00000002 ; RTR
CAN_TI0R_RTR_ofs EQU 1
CAN_TI0R_RTR_len EQU 1
CAN_TI0R_TXRQ EQU 0x00000001 ; TXRQ
CAN_TI0R_TXRQ_ofs EQU 0
CAN_TI0R_TXRQ_len EQU 1
; CAN_TDT0R fields:
CAN_TDT0R_TIME EQU 0xffff0000 ; TIME
CAN_TDT0R_TIME_ofs EQU 16
CAN_TDT0R_TIME_len EQU 16
CAN_TDT0R_TGT EQU 0x00000100 ; TGT
CAN_TDT0R_TGT_ofs EQU 8
CAN_TDT0R_TGT_len EQU 1
CAN_TDT0R_DLC EQU 0x0000000f ; DLC
CAN_TDT0R_DLC_ofs EQU 0
CAN_TDT0R_DLC_len EQU 4
; CAN_TDL0R fields:
CAN_TDL0R_DATA3 EQU 0xff000000 ; DATA3
CAN_TDL0R_DATA3_ofs EQU 24
CAN_TDL0R_DATA3_len EQU 8
CAN_TDL0R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_TDL0R_DATA2_ofs EQU 16
CAN_TDL0R_DATA2_len EQU 8
CAN_TDL0R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_TDL0R_DATA1_ofs EQU 8
CAN_TDL0R_DATA1_len EQU 8
CAN_TDL0R_DATA0 EQU 0x000000ff ; DATA0
CAN_TDL0R_DATA0_ofs EQU 0
CAN_TDL0R_DATA0_len EQU 8
; CAN_TDH0R fields:
CAN_TDH0R_DATA7 EQU 0xff000000 ; DATA7
CAN_TDH0R_DATA7_ofs EQU 24
CAN_TDH0R_DATA7_len EQU 8
CAN_TDH0R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_TDH0R_DATA6_ofs EQU 16
CAN_TDH0R_DATA6_len EQU 8
CAN_TDH0R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_TDH0R_DATA5_ofs EQU 8
CAN_TDH0R_DATA5_len EQU 8
CAN_TDH0R_DATA4 EQU 0x000000ff ; DATA4
CAN_TDH0R_DATA4_ofs EQU 0
CAN_TDH0R_DATA4_len EQU 8
; CAN_TI1R fields:
CAN_TI1R_STID EQU 0xffe00000 ; STID
CAN_TI1R_STID_ofs EQU 21
CAN_TI1R_STID_len EQU 11
CAN_TI1R_EXID EQU 0x001ffff8 ; EXID
CAN_TI1R_EXID_ofs EQU 3
CAN_TI1R_EXID_len EQU 18
CAN_TI1R_IDE EQU 0x00000004 ; IDE
CAN_TI1R_IDE_ofs EQU 2
CAN_TI1R_IDE_len EQU 1
CAN_TI1R_RTR EQU 0x00000002 ; RTR
CAN_TI1R_RTR_ofs EQU 1
CAN_TI1R_RTR_len EQU 1
CAN_TI1R_TXRQ EQU 0x00000001 ; TXRQ
CAN_TI1R_TXRQ_ofs EQU 0
CAN_TI1R_TXRQ_len EQU 1
; CAN_TDT1R fields:
CAN_TDT1R_TIME EQU 0xffff0000 ; TIME
CAN_TDT1R_TIME_ofs EQU 16
CAN_TDT1R_TIME_len EQU 16
CAN_TDT1R_TGT EQU 0x00000100 ; TGT
CAN_TDT1R_TGT_ofs EQU 8
CAN_TDT1R_TGT_len EQU 1
CAN_TDT1R_DLC EQU 0x0000000f ; DLC
CAN_TDT1R_DLC_ofs EQU 0
CAN_TDT1R_DLC_len EQU 4
; CAN_TDL1R fields:
CAN_TDL1R_DATA3 EQU 0xff000000 ; DATA3
CAN_TDL1R_DATA3_ofs EQU 24
CAN_TDL1R_DATA3_len EQU 8
CAN_TDL1R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_TDL1R_DATA2_ofs EQU 16
CAN_TDL1R_DATA2_len EQU 8
CAN_TDL1R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_TDL1R_DATA1_ofs EQU 8
CAN_TDL1R_DATA1_len EQU 8
CAN_TDL1R_DATA0 EQU 0x000000ff ; DATA0
CAN_TDL1R_DATA0_ofs EQU 0
CAN_TDL1R_DATA0_len EQU 8
; CAN_TDH1R fields:
CAN_TDH1R_DATA7 EQU 0xff000000 ; DATA7
CAN_TDH1R_DATA7_ofs EQU 24
CAN_TDH1R_DATA7_len EQU 8
CAN_TDH1R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_TDH1R_DATA6_ofs EQU 16
CAN_TDH1R_DATA6_len EQU 8
CAN_TDH1R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_TDH1R_DATA5_ofs EQU 8
CAN_TDH1R_DATA5_len EQU 8
CAN_TDH1R_DATA4 EQU 0x000000ff ; DATA4
CAN_TDH1R_DATA4_ofs EQU 0
CAN_TDH1R_DATA4_len EQU 8
; CAN_TI2R fields:
CAN_TI2R_STID EQU 0xffe00000 ; STID
CAN_TI2R_STID_ofs EQU 21
CAN_TI2R_STID_len EQU 11
CAN_TI2R_EXID EQU 0x001ffff8 ; EXID
CAN_TI2R_EXID_ofs EQU 3
CAN_TI2R_EXID_len EQU 18
CAN_TI2R_IDE EQU 0x00000004 ; IDE
CAN_TI2R_IDE_ofs EQU 2
CAN_TI2R_IDE_len EQU 1
CAN_TI2R_RTR EQU 0x00000002 ; RTR
CAN_TI2R_RTR_ofs EQU 1
CAN_TI2R_RTR_len EQU 1
CAN_TI2R_TXRQ EQU 0x00000001 ; TXRQ
CAN_TI2R_TXRQ_ofs EQU 0
CAN_TI2R_TXRQ_len EQU 1
; CAN_TDT2R fields:
CAN_TDT2R_TIME EQU 0xffff0000 ; TIME
CAN_TDT2R_TIME_ofs EQU 16
CAN_TDT2R_TIME_len EQU 16
CAN_TDT2R_TGT EQU 0x00000100 ; TGT
CAN_TDT2R_TGT_ofs EQU 8
CAN_TDT2R_TGT_len EQU 1
CAN_TDT2R_DLC EQU 0x0000000f ; DLC
CAN_TDT2R_DLC_ofs EQU 0
CAN_TDT2R_DLC_len EQU 4
; CAN_TDL2R fields:
CAN_TDL2R_DATA3 EQU 0xff000000 ; DATA3
CAN_TDL2R_DATA3_ofs EQU 24
CAN_TDL2R_DATA3_len EQU 8
CAN_TDL2R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_TDL2R_DATA2_ofs EQU 16
CAN_TDL2R_DATA2_len EQU 8
CAN_TDL2R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_TDL2R_DATA1_ofs EQU 8
CAN_TDL2R_DATA1_len EQU 8
CAN_TDL2R_DATA0 EQU 0x000000ff ; DATA0
CAN_TDL2R_DATA0_ofs EQU 0
CAN_TDL2R_DATA0_len EQU 8
; CAN_TDH2R fields:
CAN_TDH2R_DATA7 EQU 0xff000000 ; DATA7
CAN_TDH2R_DATA7_ofs EQU 24
CAN_TDH2R_DATA7_len EQU 8
CAN_TDH2R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_TDH2R_DATA6_ofs EQU 16
CAN_TDH2R_DATA6_len EQU 8
CAN_TDH2R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_TDH2R_DATA5_ofs EQU 8
CAN_TDH2R_DATA5_len EQU 8
CAN_TDH2R_DATA4 EQU 0x000000ff ; DATA4
CAN_TDH2R_DATA4_ofs EQU 0
CAN_TDH2R_DATA4_len EQU 8
; CAN_RI0R fields:
CAN_RI0R_STID EQU 0xffe00000 ; STID
CAN_RI0R_STID_ofs EQU 21
CAN_RI0R_STID_len EQU 11
CAN_RI0R_EXID EQU 0x001ffff8 ; EXID
CAN_RI0R_EXID_ofs EQU 3
CAN_RI0R_EXID_len EQU 18
CAN_RI0R_IDE EQU 0x00000004 ; IDE
CAN_RI0R_IDE_ofs EQU 2
CAN_RI0R_IDE_len EQU 1
CAN_RI0R_RTR EQU 0x00000002 ; RTR
CAN_RI0R_RTR_ofs EQU 1
CAN_RI0R_RTR_len EQU 1
; CAN_RDT0R fields:
CAN_RDT0R_TIME EQU 0xffff0000 ; TIME
CAN_RDT0R_TIME_ofs EQU 16
CAN_RDT0R_TIME_len EQU 16
CAN_RDT0R_FMI EQU 0x0000ff00 ; FMI
CAN_RDT0R_FMI_ofs EQU 8
CAN_RDT0R_FMI_len EQU 8
CAN_RDT0R_DLC EQU 0x0000000f ; DLC
CAN_RDT0R_DLC_ofs EQU 0
CAN_RDT0R_DLC_len EQU 4
; CAN_RDL0R fields:
CAN_RDL0R_DATA3 EQU 0xff000000 ; DATA3
CAN_RDL0R_DATA3_ofs EQU 24
CAN_RDL0R_DATA3_len EQU 8
CAN_RDL0R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_RDL0R_DATA2_ofs EQU 16
CAN_RDL0R_DATA2_len EQU 8
CAN_RDL0R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_RDL0R_DATA1_ofs EQU 8
CAN_RDL0R_DATA1_len EQU 8
CAN_RDL0R_DATA0 EQU 0x000000ff ; DATA0
CAN_RDL0R_DATA0_ofs EQU 0
CAN_RDL0R_DATA0_len EQU 8
; CAN_RDH0R fields:
CAN_RDH0R_DATA7 EQU 0xff000000 ; DATA7
CAN_RDH0R_DATA7_ofs EQU 24
CAN_RDH0R_DATA7_len EQU 8
CAN_RDH0R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_RDH0R_DATA6_ofs EQU 16
CAN_RDH0R_DATA6_len EQU 8
CAN_RDH0R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_RDH0R_DATA5_ofs EQU 8
CAN_RDH0R_DATA5_len EQU 8
CAN_RDH0R_DATA4 EQU 0x000000ff ; DATA4
CAN_RDH0R_DATA4_ofs EQU 0
CAN_RDH0R_DATA4_len EQU 8
; CAN_RI1R fields:
CAN_RI1R_STID EQU 0xffe00000 ; STID
CAN_RI1R_STID_ofs EQU 21
CAN_RI1R_STID_len EQU 11
CAN_RI1R_EXID EQU 0x001ffff8 ; EXID
CAN_RI1R_EXID_ofs EQU 3
CAN_RI1R_EXID_len EQU 18
CAN_RI1R_IDE EQU 0x00000004 ; IDE
CAN_RI1R_IDE_ofs EQU 2
CAN_RI1R_IDE_len EQU 1
CAN_RI1R_RTR EQU 0x00000002 ; RTR
CAN_RI1R_RTR_ofs EQU 1
CAN_RI1R_RTR_len EQU 1
; CAN_RDT1R fields:
CAN_RDT1R_TIME EQU 0xffff0000 ; TIME
CAN_RDT1R_TIME_ofs EQU 16
CAN_RDT1R_TIME_len EQU 16
CAN_RDT1R_FMI EQU 0x0000ff00 ; FMI
CAN_RDT1R_FMI_ofs EQU 8
CAN_RDT1R_FMI_len EQU 8
CAN_RDT1R_DLC EQU 0x0000000f ; DLC
CAN_RDT1R_DLC_ofs EQU 0
CAN_RDT1R_DLC_len EQU 4
; CAN_RDL1R fields:
CAN_RDL1R_DATA3 EQU 0xff000000 ; DATA3
CAN_RDL1R_DATA3_ofs EQU 24
CAN_RDL1R_DATA3_len EQU 8
CAN_RDL1R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_RDL1R_DATA2_ofs EQU 16
CAN_RDL1R_DATA2_len EQU 8
CAN_RDL1R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_RDL1R_DATA1_ofs EQU 8
CAN_RDL1R_DATA1_len EQU 8
CAN_RDL1R_DATA0 EQU 0x000000ff ; DATA0
CAN_RDL1R_DATA0_ofs EQU 0
CAN_RDL1R_DATA0_len EQU 8
; CAN_RDH1R fields:
CAN_RDH1R_DATA7 EQU 0xff000000 ; DATA7
CAN_RDH1R_DATA7_ofs EQU 24
CAN_RDH1R_DATA7_len EQU 8
CAN_RDH1R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_RDH1R_DATA6_ofs EQU 16
CAN_RDH1R_DATA6_len EQU 8
CAN_RDH1R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_RDH1R_DATA5_ofs EQU 8
CAN_RDH1R_DATA5_len EQU 8
CAN_RDH1R_DATA4 EQU 0x000000ff ; DATA4
CAN_RDH1R_DATA4_ofs EQU 0
CAN_RDH1R_DATA4_len EQU 8
; CAN_FMR fields:
CAN_FMR_CAN2SB EQU 0x00003f00 ; CAN2 start bank
CAN_FMR_CAN2SB_ofs EQU 8
CAN_FMR_CAN2SB_len EQU 6
CAN_FMR_FINIT EQU 0x00000001 ; Filter init mode
CAN_FMR_FINIT_ofs EQU 0
CAN_FMR_FINIT_len EQU 1
; CAN_FM1R fields:
CAN_FM1R_FBM0 EQU 0x00000001 ; Filter mode
CAN_FM1R_FBM0_ofs EQU 0
CAN_FM1R_FBM0_len EQU 1
CAN_FM1R_FBM1 EQU 0x00000002 ; Filter mode
CAN_FM1R_FBM1_ofs EQU 1
CAN_FM1R_FBM1_len EQU 1
CAN_FM1R_FBM2 EQU 0x00000004 ; Filter mode
CAN_FM1R_FBM2_ofs EQU 2
CAN_FM1R_FBM2_len EQU 1
CAN_FM1R_FBM3 EQU 0x00000008 ; Filter mode
CAN_FM1R_FBM3_ofs EQU 3
CAN_FM1R_FBM3_len EQU 1
CAN_FM1R_FBM4 EQU 0x00000010 ; Filter mode
CAN_FM1R_FBM4_ofs EQU 4
CAN_FM1R_FBM4_len EQU 1
CAN_FM1R_FBM5 EQU 0x00000020 ; Filter mode
CAN_FM1R_FBM5_ofs EQU 5
CAN_FM1R_FBM5_len EQU 1
CAN_FM1R_FBM6 EQU 0x00000040 ; Filter mode
CAN_FM1R_FBM6_ofs EQU 6
CAN_FM1R_FBM6_len EQU 1
CAN_FM1R_FBM7 EQU 0x00000080 ; Filter mode
CAN_FM1R_FBM7_ofs EQU 7
CAN_FM1R_FBM7_len EQU 1
CAN_FM1R_FBM8 EQU 0x00000100 ; Filter mode
CAN_FM1R_FBM8_ofs EQU 8
CAN_FM1R_FBM8_len EQU 1
CAN_FM1R_FBM9 EQU 0x00000200 ; Filter mode
CAN_FM1R_FBM9_ofs EQU 9
CAN_FM1R_FBM9_len EQU 1
CAN_FM1R_FBM10 EQU 0x00000400 ; Filter mode
CAN_FM1R_FBM10_ofs EQU 10
CAN_FM1R_FBM10_len EQU 1
CAN_FM1R_FBM11 EQU 0x00000800 ; Filter mode
CAN_FM1R_FBM11_ofs EQU 11
CAN_FM1R_FBM11_len EQU 1
CAN_FM1R_FBM12 EQU 0x00001000 ; Filter mode
CAN_FM1R_FBM12_ofs EQU 12
CAN_FM1R_FBM12_len EQU 1
CAN_FM1R_FBM13 EQU 0x00002000 ; Filter mode
CAN_FM1R_FBM13_ofs EQU 13
CAN_FM1R_FBM13_len EQU 1
CAN_FM1R_FBM14 EQU 0x00004000 ; Filter mode
CAN_FM1R_FBM14_ofs EQU 14
CAN_FM1R_FBM14_len EQU 1
CAN_FM1R_FBM15 EQU 0x00008000 ; Filter mode
CAN_FM1R_FBM15_ofs EQU 15
CAN_FM1R_FBM15_len EQU 1
CAN_FM1R_FBM16 EQU 0x00010000 ; Filter mode
CAN_FM1R_FBM16_ofs EQU 16
CAN_FM1R_FBM16_len EQU 1
CAN_FM1R_FBM17 EQU 0x00020000 ; Filter mode
CAN_FM1R_FBM17_ofs EQU 17
CAN_FM1R_FBM17_len EQU 1
CAN_FM1R_FBM18 EQU 0x00040000 ; Filter mode
CAN_FM1R_FBM18_ofs EQU 18
CAN_FM1R_FBM18_len EQU 1
CAN_FM1R_FBM19 EQU 0x00080000 ; Filter mode
CAN_FM1R_FBM19_ofs EQU 19
CAN_FM1R_FBM19_len EQU 1
CAN_FM1R_FBM20 EQU 0x00100000 ; Filter mode
CAN_FM1R_FBM20_ofs EQU 20
CAN_FM1R_FBM20_len EQU 1
CAN_FM1R_FBM21 EQU 0x00200000 ; Filter mode
CAN_FM1R_FBM21_ofs EQU 21
CAN_FM1R_FBM21_len EQU 1
CAN_FM1R_FBM22 EQU 0x00400000 ; Filter mode
CAN_FM1R_FBM22_ofs EQU 22
CAN_FM1R_FBM22_len EQU 1
CAN_FM1R_FBM23 EQU 0x00800000 ; Filter mode
CAN_FM1R_FBM23_ofs EQU 23
CAN_FM1R_FBM23_len EQU 1
CAN_FM1R_FBM24 EQU 0x01000000 ; Filter mode
CAN_FM1R_FBM24_ofs EQU 24
CAN_FM1R_FBM24_len EQU 1
CAN_FM1R_FBM25 EQU 0x02000000 ; Filter mode
CAN_FM1R_FBM25_ofs EQU 25
CAN_FM1R_FBM25_len EQU 1
CAN_FM1R_FBM26 EQU 0x04000000 ; Filter mode
CAN_FM1R_FBM26_ofs EQU 26
CAN_FM1R_FBM26_len EQU 1
CAN_FM1R_FBM27 EQU 0x08000000 ; Filter mode
CAN_FM1R_FBM27_ofs EQU 27
CAN_FM1R_FBM27_len EQU 1
; CAN_FS1R fields:
CAN_FS1R_FSC0 EQU 0x00000001 ; Filter scale configuration
CAN_FS1R_FSC0_ofs EQU 0
CAN_FS1R_FSC0_len EQU 1
CAN_FS1R_FSC1 EQU 0x00000002 ; Filter scale configuration
CAN_FS1R_FSC1_ofs EQU 1
CAN_FS1R_FSC1_len EQU 1
CAN_FS1R_FSC2 EQU 0x00000004 ; Filter scale configuration
CAN_FS1R_FSC2_ofs EQU 2
CAN_FS1R_FSC2_len EQU 1
CAN_FS1R_FSC3 EQU 0x00000008 ; Filter scale configuration
CAN_FS1R_FSC3_ofs EQU 3
CAN_FS1R_FSC3_len EQU 1
CAN_FS1R_FSC4 EQU 0x00000010 ; Filter scale configuration
CAN_FS1R_FSC4_ofs EQU 4
CAN_FS1R_FSC4_len EQU 1
CAN_FS1R_FSC5 EQU 0x00000020 ; Filter scale configuration
CAN_FS1R_FSC5_ofs EQU 5
CAN_FS1R_FSC5_len EQU 1
CAN_FS1R_FSC6 EQU 0x00000040 ; Filter scale configuration
CAN_FS1R_FSC6_ofs EQU 6
CAN_FS1R_FSC6_len EQU 1
CAN_FS1R_FSC7 EQU 0x00000080 ; Filter scale configuration
CAN_FS1R_FSC7_ofs EQU 7
CAN_FS1R_FSC7_len EQU 1
CAN_FS1R_FSC8 EQU 0x00000100 ; Filter scale configuration
CAN_FS1R_FSC8_ofs EQU 8
CAN_FS1R_FSC8_len EQU 1
CAN_FS1R_FSC9 EQU 0x00000200 ; Filter scale configuration
CAN_FS1R_FSC9_ofs EQU 9
CAN_FS1R_FSC9_len EQU 1
CAN_FS1R_FSC10 EQU 0x00000400 ; Filter scale configuration
CAN_FS1R_FSC10_ofs EQU 10
CAN_FS1R_FSC10_len EQU 1
CAN_FS1R_FSC11 EQU 0x00000800 ; Filter scale configuration
CAN_FS1R_FSC11_ofs EQU 11
CAN_FS1R_FSC11_len EQU 1
CAN_FS1R_FSC12 EQU 0x00001000 ; Filter scale configuration
CAN_FS1R_FSC12_ofs EQU 12
CAN_FS1R_FSC12_len EQU 1
CAN_FS1R_FSC13 EQU 0x00002000 ; Filter scale configuration
CAN_FS1R_FSC13_ofs EQU 13
CAN_FS1R_FSC13_len EQU 1
CAN_FS1R_FSC14 EQU 0x00004000 ; Filter scale configuration
CAN_FS1R_FSC14_ofs EQU 14
CAN_FS1R_FSC14_len EQU 1
CAN_FS1R_FSC15 EQU 0x00008000 ; Filter scale configuration
CAN_FS1R_FSC15_ofs EQU 15
CAN_FS1R_FSC15_len EQU 1
CAN_FS1R_FSC16 EQU 0x00010000 ; Filter scale configuration
CAN_FS1R_FSC16_ofs EQU 16
CAN_FS1R_FSC16_len EQU 1
CAN_FS1R_FSC17 EQU 0x00020000 ; Filter scale configuration
CAN_FS1R_FSC17_ofs EQU 17
CAN_FS1R_FSC17_len EQU 1
CAN_FS1R_FSC18 EQU 0x00040000 ; Filter scale configuration
CAN_FS1R_FSC18_ofs EQU 18
CAN_FS1R_FSC18_len EQU 1
CAN_FS1R_FSC19 EQU 0x00080000 ; Filter scale configuration
CAN_FS1R_FSC19_ofs EQU 19
CAN_FS1R_FSC19_len EQU 1
CAN_FS1R_FSC20 EQU 0x00100000 ; Filter scale configuration
CAN_FS1R_FSC20_ofs EQU 20
CAN_FS1R_FSC20_len EQU 1
CAN_FS1R_FSC21 EQU 0x00200000 ; Filter scale configuration
CAN_FS1R_FSC21_ofs EQU 21
CAN_FS1R_FSC21_len EQU 1
CAN_FS1R_FSC22 EQU 0x00400000 ; Filter scale configuration
CAN_FS1R_FSC22_ofs EQU 22
CAN_FS1R_FSC22_len EQU 1
CAN_FS1R_FSC23 EQU 0x00800000 ; Filter scale configuration
CAN_FS1R_FSC23_ofs EQU 23
CAN_FS1R_FSC23_len EQU 1
CAN_FS1R_FSC24 EQU 0x01000000 ; Filter scale configuration
CAN_FS1R_FSC24_ofs EQU 24
CAN_FS1R_FSC24_len EQU 1
CAN_FS1R_FSC25 EQU 0x02000000 ; Filter scale configuration
CAN_FS1R_FSC25_ofs EQU 25
CAN_FS1R_FSC25_len EQU 1
CAN_FS1R_FSC26 EQU 0x04000000 ; Filter scale configuration
CAN_FS1R_FSC26_ofs EQU 26
CAN_FS1R_FSC26_len EQU 1
CAN_FS1R_FSC27 EQU 0x08000000 ; Filter scale configuration
CAN_FS1R_FSC27_ofs EQU 27
CAN_FS1R_FSC27_len EQU 1
; CAN_FFA1R fields:
CAN_FFA1R_FFA0 EQU 0x00000001 ; Filter FIFO assignment for filter 0
CAN_FFA1R_FFA0_ofs EQU 0
CAN_FFA1R_FFA0_len EQU 1
CAN_FFA1R_FFA1 EQU 0x00000002 ; Filter FIFO assignment for filter 1
CAN_FFA1R_FFA1_ofs EQU 1
CAN_FFA1R_FFA1_len EQU 1
CAN_FFA1R_FFA2 EQU 0x00000004 ; Filter FIFO assignment for filter 2
CAN_FFA1R_FFA2_ofs EQU 2
CAN_FFA1R_FFA2_len EQU 1
CAN_FFA1R_FFA3 EQU 0x00000008 ; Filter FIFO assignment for filter 3
CAN_FFA1R_FFA3_ofs EQU 3
CAN_FFA1R_FFA3_len EQU 1
CAN_FFA1R_FFA4 EQU 0x00000010 ; Filter FIFO assignment for filter 4
CAN_FFA1R_FFA4_ofs EQU 4
CAN_FFA1R_FFA4_len EQU 1
CAN_FFA1R_FFA5 EQU 0x00000020 ; Filter FIFO assignment for filter 5
CAN_FFA1R_FFA5_ofs EQU 5
CAN_FFA1R_FFA5_len EQU 1
CAN_FFA1R_FFA6 EQU 0x00000040 ; Filter FIFO assignment for filter 6
CAN_FFA1R_FFA6_ofs EQU 6
CAN_FFA1R_FFA6_len EQU 1
CAN_FFA1R_FFA7 EQU 0x00000080 ; Filter FIFO assignment for filter 7
CAN_FFA1R_FFA7_ofs EQU 7
CAN_FFA1R_FFA7_len EQU 1
CAN_FFA1R_FFA8 EQU 0x00000100 ; Filter FIFO assignment for filter 8
CAN_FFA1R_FFA8_ofs EQU 8
CAN_FFA1R_FFA8_len EQU 1
CAN_FFA1R_FFA9 EQU 0x00000200 ; Filter FIFO assignment for filter 9
CAN_FFA1R_FFA9_ofs EQU 9
CAN_FFA1R_FFA9_len EQU 1
CAN_FFA1R_FFA10 EQU 0x00000400 ; Filter FIFO assignment for filter 10
CAN_FFA1R_FFA10_ofs EQU 10
CAN_FFA1R_FFA10_len EQU 1
CAN_FFA1R_FFA11 EQU 0x00000800 ; Filter FIFO assignment for filter 11
CAN_FFA1R_FFA11_ofs EQU 11
CAN_FFA1R_FFA11_len EQU 1
CAN_FFA1R_FFA12 EQU 0x00001000 ; Filter FIFO assignment for filter 12
CAN_FFA1R_FFA12_ofs EQU 12
CAN_FFA1R_FFA12_len EQU 1
CAN_FFA1R_FFA13 EQU 0x00002000 ; Filter FIFO assignment for filter 13
CAN_FFA1R_FFA13_ofs EQU 13
CAN_FFA1R_FFA13_len EQU 1
CAN_FFA1R_FFA14 EQU 0x00004000 ; Filter FIFO assignment for filter 14
CAN_FFA1R_FFA14_ofs EQU 14
CAN_FFA1R_FFA14_len EQU 1
CAN_FFA1R_FFA15 EQU 0x00008000 ; Filter FIFO assignment for filter 15
CAN_FFA1R_FFA15_ofs EQU 15
CAN_FFA1R_FFA15_len EQU 1
CAN_FFA1R_FFA16 EQU 0x00010000 ; Filter FIFO assignment for filter 16
CAN_FFA1R_FFA16_ofs EQU 16
CAN_FFA1R_FFA16_len EQU 1
CAN_FFA1R_FFA17 EQU 0x00020000 ; Filter FIFO assignment for filter 17
CAN_FFA1R_FFA17_ofs EQU 17
CAN_FFA1R_FFA17_len EQU 1
CAN_FFA1R_FFA18 EQU 0x00040000 ; Filter FIFO assignment for filter 18
CAN_FFA1R_FFA18_ofs EQU 18
CAN_FFA1R_FFA18_len EQU 1
CAN_FFA1R_FFA19 EQU 0x00080000 ; Filter FIFO assignment for filter 19
CAN_FFA1R_FFA19_ofs EQU 19
CAN_FFA1R_FFA19_len EQU 1
CAN_FFA1R_FFA20 EQU 0x00100000 ; Filter FIFO assignment for filter 20
CAN_FFA1R_FFA20_ofs EQU 20
CAN_FFA1R_FFA20_len EQU 1
CAN_FFA1R_FFA21 EQU 0x00200000 ; Filter FIFO assignment for filter 21
CAN_FFA1R_FFA21_ofs EQU 21
CAN_FFA1R_FFA21_len EQU 1
CAN_FFA1R_FFA22 EQU 0x00400000 ; Filter FIFO assignment for filter 22
CAN_FFA1R_FFA22_ofs EQU 22
CAN_FFA1R_FFA22_len EQU 1
CAN_FFA1R_FFA23 EQU 0x00800000 ; Filter FIFO assignment for filter 23
CAN_FFA1R_FFA23_ofs EQU 23
CAN_FFA1R_FFA23_len EQU 1
CAN_FFA1R_FFA24 EQU 0x01000000 ; Filter FIFO assignment for filter 24
CAN_FFA1R_FFA24_ofs EQU 24
CAN_FFA1R_FFA24_len EQU 1
CAN_FFA1R_FFA25 EQU 0x02000000 ; Filter FIFO assignment for filter 25
CAN_FFA1R_FFA25_ofs EQU 25
CAN_FFA1R_FFA25_len EQU 1
CAN_FFA1R_FFA26 EQU 0x04000000 ; Filter FIFO assignment for filter 26
CAN_FFA1R_FFA26_ofs EQU 26
CAN_FFA1R_FFA26_len EQU 1
CAN_FFA1R_FFA27 EQU 0x08000000 ; Filter FIFO assignment for filter 27
CAN_FFA1R_FFA27_ofs EQU 27
CAN_FFA1R_FFA27_len EQU 1
; CAN_FA1R fields:
CAN_FA1R_FACT0 EQU 0x00000001 ; Filter active
CAN_FA1R_FACT0_ofs EQU 0
CAN_FA1R_FACT0_len EQU 1
CAN_FA1R_FACT1 EQU 0x00000002 ; Filter active
CAN_FA1R_FACT1_ofs EQU 1
CAN_FA1R_FACT1_len EQU 1
CAN_FA1R_FACT2 EQU 0x00000004 ; Filter active
CAN_FA1R_FACT2_ofs EQU 2
CAN_FA1R_FACT2_len EQU 1
CAN_FA1R_FACT3 EQU 0x00000008 ; Filter active
CAN_FA1R_FACT3_ofs EQU 3
CAN_FA1R_FACT3_len EQU 1
CAN_FA1R_FACT4 EQU 0x00000010 ; Filter active
CAN_FA1R_FACT4_ofs EQU 4
CAN_FA1R_FACT4_len EQU 1
CAN_FA1R_FACT5 EQU 0x00000020 ; Filter active
CAN_FA1R_FACT5_ofs EQU 5
CAN_FA1R_FACT5_len EQU 1
CAN_FA1R_FACT6 EQU 0x00000040 ; Filter active
CAN_FA1R_FACT6_ofs EQU 6
CAN_FA1R_FACT6_len EQU 1
CAN_FA1R_FACT7 EQU 0x00000080 ; Filter active
CAN_FA1R_FACT7_ofs EQU 7
CAN_FA1R_FACT7_len EQU 1
CAN_FA1R_FACT8 EQU 0x00000100 ; Filter active
CAN_FA1R_FACT8_ofs EQU 8
CAN_FA1R_FACT8_len EQU 1
CAN_FA1R_FACT9 EQU 0x00000200 ; Filter active
CAN_FA1R_FACT9_ofs EQU 9
CAN_FA1R_FACT9_len EQU 1
CAN_FA1R_FACT10 EQU 0x00000400 ; Filter active
CAN_FA1R_FACT10_ofs EQU 10
CAN_FA1R_FACT10_len EQU 1
CAN_FA1R_FACT11 EQU 0x00000800 ; Filter active
CAN_FA1R_FACT11_ofs EQU 11
CAN_FA1R_FACT11_len EQU 1
CAN_FA1R_FACT12 EQU 0x00001000 ; Filter active
CAN_FA1R_FACT12_ofs EQU 12
CAN_FA1R_FACT12_len EQU 1
CAN_FA1R_FACT13 EQU 0x00002000 ; Filter active
CAN_FA1R_FACT13_ofs EQU 13
CAN_FA1R_FACT13_len EQU 1
CAN_FA1R_FACT14 EQU 0x00004000 ; Filter active
CAN_FA1R_FACT14_ofs EQU 14
CAN_FA1R_FACT14_len EQU 1
CAN_FA1R_FACT15 EQU 0x00008000 ; Filter active
CAN_FA1R_FACT15_ofs EQU 15
CAN_FA1R_FACT15_len EQU 1
CAN_FA1R_FACT16 EQU 0x00010000 ; Filter active
CAN_FA1R_FACT16_ofs EQU 16
CAN_FA1R_FACT16_len EQU 1
CAN_FA1R_FACT17 EQU 0x00020000 ; Filter active
CAN_FA1R_FACT17_ofs EQU 17
CAN_FA1R_FACT17_len EQU 1
CAN_FA1R_FACT18 EQU 0x00040000 ; Filter active
CAN_FA1R_FACT18_ofs EQU 18
CAN_FA1R_FACT18_len EQU 1
CAN_FA1R_FACT19 EQU 0x00080000 ; Filter active
CAN_FA1R_FACT19_ofs EQU 19
CAN_FA1R_FACT19_len EQU 1
CAN_FA1R_FACT20 EQU 0x00100000 ; Filter active
CAN_FA1R_FACT20_ofs EQU 20
CAN_FA1R_FACT20_len EQU 1
CAN_FA1R_FACT21 EQU 0x00200000 ; Filter active
CAN_FA1R_FACT21_ofs EQU 21
CAN_FA1R_FACT21_len EQU 1
CAN_FA1R_FACT22 EQU 0x00400000 ; Filter active
CAN_FA1R_FACT22_ofs EQU 22
CAN_FA1R_FACT22_len EQU 1
CAN_FA1R_FACT23 EQU 0x00800000 ; Filter active
CAN_FA1R_FACT23_ofs EQU 23
CAN_FA1R_FACT23_len EQU 1
CAN_FA1R_FACT24 EQU 0x01000000 ; Filter active
CAN_FA1R_FACT24_ofs EQU 24
CAN_FA1R_FACT24_len EQU 1
CAN_FA1R_FACT25 EQU 0x02000000 ; Filter active
CAN_FA1R_FACT25_ofs EQU 25
CAN_FA1R_FACT25_len EQU 1
CAN_FA1R_FACT26 EQU 0x04000000 ; Filter active
CAN_FA1R_FACT26_ofs EQU 26
CAN_FA1R_FACT26_len EQU 1
CAN_FA1R_FACT27 EQU 0x08000000 ; Filter active
CAN_FA1R_FACT27_ofs EQU 27
CAN_FA1R_FACT27_len EQU 1
; CAN_F0R1 fields:
CAN_F0R1_FB0 EQU 0x00000001 ; Filter bits
CAN_F0R1_FB0_ofs EQU 0
CAN_F0R1_FB0_len EQU 1
CAN_F0R1_FB1 EQU 0x00000002 ; Filter bits
CAN_F0R1_FB1_ofs EQU 1
CAN_F0R1_FB1_len EQU 1
CAN_F0R1_FB2 EQU 0x00000004 ; Filter bits
CAN_F0R1_FB2_ofs EQU 2
CAN_F0R1_FB2_len EQU 1
CAN_F0R1_FB3 EQU 0x00000008 ; Filter bits
CAN_F0R1_FB3_ofs EQU 3
CAN_F0R1_FB3_len EQU 1
CAN_F0R1_FB4 EQU 0x00000010 ; Filter bits
CAN_F0R1_FB4_ofs EQU 4
CAN_F0R1_FB4_len EQU 1
CAN_F0R1_FB5 EQU 0x00000020 ; Filter bits
CAN_F0R1_FB5_ofs EQU 5
CAN_F0R1_FB5_len EQU 1
CAN_F0R1_FB6 EQU 0x00000040 ; Filter bits
CAN_F0R1_FB6_ofs EQU 6
CAN_F0R1_FB6_len EQU 1
CAN_F0R1_FB7 EQU 0x00000080 ; Filter bits
CAN_F0R1_FB7_ofs EQU 7
CAN_F0R1_FB7_len EQU 1
CAN_F0R1_FB8 EQU 0x00000100 ; Filter bits
CAN_F0R1_FB8_ofs EQU 8
CAN_F0R1_FB8_len EQU 1
CAN_F0R1_FB9 EQU 0x00000200 ; Filter bits
CAN_F0R1_FB9_ofs EQU 9
CAN_F0R1_FB9_len EQU 1
CAN_F0R1_FB10 EQU 0x00000400 ; Filter bits
CAN_F0R1_FB10_ofs EQU 10
CAN_F0R1_FB10_len EQU 1
CAN_F0R1_FB11 EQU 0x00000800 ; Filter bits
CAN_F0R1_FB11_ofs EQU 11
CAN_F0R1_FB11_len EQU 1
CAN_F0R1_FB12 EQU 0x00001000 ; Filter bits
CAN_F0R1_FB12_ofs EQU 12
CAN_F0R1_FB12_len EQU 1
CAN_F0R1_FB13 EQU 0x00002000 ; Filter bits
CAN_F0R1_FB13_ofs EQU 13
CAN_F0R1_FB13_len EQU 1
CAN_F0R1_FB14 EQU 0x00004000 ; Filter bits
CAN_F0R1_FB14_ofs EQU 14
CAN_F0R1_FB14_len EQU 1
CAN_F0R1_FB15 EQU 0x00008000 ; Filter bits
CAN_F0R1_FB15_ofs EQU 15
CAN_F0R1_FB15_len EQU 1
CAN_F0R1_FB16 EQU 0x00010000 ; Filter bits
CAN_F0R1_FB16_ofs EQU 16
CAN_F0R1_FB16_len EQU 1
CAN_F0R1_FB17 EQU 0x00020000 ; Filter bits
CAN_F0R1_FB17_ofs EQU 17
CAN_F0R1_FB17_len EQU 1
CAN_F0R1_FB18 EQU 0x00040000 ; Filter bits
CAN_F0R1_FB18_ofs EQU 18
CAN_F0R1_FB18_len EQU 1
CAN_F0R1_FB19 EQU 0x00080000 ; Filter bits
CAN_F0R1_FB19_ofs EQU 19
CAN_F0R1_FB19_len EQU 1
CAN_F0R1_FB20 EQU 0x00100000 ; Filter bits
CAN_F0R1_FB20_ofs EQU 20
CAN_F0R1_FB20_len EQU 1
CAN_F0R1_FB21 EQU 0x00200000 ; Filter bits
CAN_F0R1_FB21_ofs EQU 21
CAN_F0R1_FB21_len EQU 1
CAN_F0R1_FB22 EQU 0x00400000 ; Filter bits
CAN_F0R1_FB22_ofs EQU 22
CAN_F0R1_FB22_len EQU 1
CAN_F0R1_FB23 EQU 0x00800000 ; Filter bits
CAN_F0R1_FB23_ofs EQU 23
CAN_F0R1_FB23_len EQU 1
CAN_F0R1_FB24 EQU 0x01000000 ; Filter bits
CAN_F0R1_FB24_ofs EQU 24
CAN_F0R1_FB24_len EQU 1
CAN_F0R1_FB25 EQU 0x02000000 ; Filter bits
CAN_F0R1_FB25_ofs EQU 25
CAN_F0R1_FB25_len EQU 1
CAN_F0R1_FB26 EQU 0x04000000 ; Filter bits
CAN_F0R1_FB26_ofs EQU 26
CAN_F0R1_FB26_len EQU 1
CAN_F0R1_FB27 EQU 0x08000000 ; Filter bits
CAN_F0R1_FB27_ofs EQU 27
CAN_F0R1_FB27_len EQU 1
CAN_F0R1_FB28 EQU 0x10000000 ; Filter bits
CAN_F0R1_FB28_ofs EQU 28
CAN_F0R1_FB28_len EQU 1
CAN_F0R1_FB29 EQU 0x20000000 ; Filter bits
CAN_F0R1_FB29_ofs EQU 29
CAN_F0R1_FB29_len EQU 1
CAN_F0R1_FB30 EQU 0x40000000 ; Filter bits
CAN_F0R1_FB30_ofs EQU 30
CAN_F0R1_FB30_len EQU 1
CAN_F0R1_FB31 EQU 0x80000000 ; Filter bits
CAN_F0R1_FB31_ofs EQU 31
CAN_F0R1_FB31_len EQU 1
; CAN_F0R2 fields:
CAN_F0R2_FB0 EQU 0x00000001 ; Filter bits
CAN_F0R2_FB0_ofs EQU 0
CAN_F0R2_FB0_len EQU 1
CAN_F0R2_FB1 EQU 0x00000002 ; Filter bits
CAN_F0R2_FB1_ofs EQU 1
CAN_F0R2_FB1_len EQU 1
CAN_F0R2_FB2 EQU 0x00000004 ; Filter bits
CAN_F0R2_FB2_ofs EQU 2
CAN_F0R2_FB2_len EQU 1
CAN_F0R2_FB3 EQU 0x00000008 ; Filter bits
CAN_F0R2_FB3_ofs EQU 3
CAN_F0R2_FB3_len EQU 1
CAN_F0R2_FB4 EQU 0x00000010 ; Filter bits
CAN_F0R2_FB4_ofs EQU 4
CAN_F0R2_FB4_len EQU 1
CAN_F0R2_FB5 EQU 0x00000020 ; Filter bits
CAN_F0R2_FB5_ofs EQU 5
CAN_F0R2_FB5_len EQU 1
CAN_F0R2_FB6 EQU 0x00000040 ; Filter bits
CAN_F0R2_FB6_ofs EQU 6
CAN_F0R2_FB6_len EQU 1
CAN_F0R2_FB7 EQU 0x00000080 ; Filter bits
CAN_F0R2_FB7_ofs EQU 7
CAN_F0R2_FB7_len EQU 1
CAN_F0R2_FB8 EQU 0x00000100 ; Filter bits
CAN_F0R2_FB8_ofs EQU 8
CAN_F0R2_FB8_len EQU 1
CAN_F0R2_FB9 EQU 0x00000200 ; Filter bits
CAN_F0R2_FB9_ofs EQU 9
CAN_F0R2_FB9_len EQU 1
CAN_F0R2_FB10 EQU 0x00000400 ; Filter bits
CAN_F0R2_FB10_ofs EQU 10
CAN_F0R2_FB10_len EQU 1
CAN_F0R2_FB11 EQU 0x00000800 ; Filter bits
CAN_F0R2_FB11_ofs EQU 11
CAN_F0R2_FB11_len EQU 1
CAN_F0R2_FB12 EQU 0x00001000 ; Filter bits
CAN_F0R2_FB12_ofs EQU 12
CAN_F0R2_FB12_len EQU 1
CAN_F0R2_FB13 EQU 0x00002000 ; Filter bits
CAN_F0R2_FB13_ofs EQU 13
CAN_F0R2_FB13_len EQU 1
CAN_F0R2_FB14 EQU 0x00004000 ; Filter bits
CAN_F0R2_FB14_ofs EQU 14
CAN_F0R2_FB14_len EQU 1
CAN_F0R2_FB15 EQU 0x00008000 ; Filter bits
CAN_F0R2_FB15_ofs EQU 15
CAN_F0R2_FB15_len EQU 1
CAN_F0R2_FB16 EQU 0x00010000 ; Filter bits
CAN_F0R2_FB16_ofs EQU 16
CAN_F0R2_FB16_len EQU 1
CAN_F0R2_FB17 EQU 0x00020000 ; Filter bits
CAN_F0R2_FB17_ofs EQU 17
CAN_F0R2_FB17_len EQU 1
CAN_F0R2_FB18 EQU 0x00040000 ; Filter bits
CAN_F0R2_FB18_ofs EQU 18
CAN_F0R2_FB18_len EQU 1
CAN_F0R2_FB19 EQU 0x00080000 ; Filter bits
CAN_F0R2_FB19_ofs EQU 19
CAN_F0R2_FB19_len EQU 1
CAN_F0R2_FB20 EQU 0x00100000 ; Filter bits
CAN_F0R2_FB20_ofs EQU 20
CAN_F0R2_FB20_len EQU 1
CAN_F0R2_FB21 EQU 0x00200000 ; Filter bits
CAN_F0R2_FB21_ofs EQU 21
CAN_F0R2_FB21_len EQU 1
CAN_F0R2_FB22 EQU 0x00400000 ; Filter bits
CAN_F0R2_FB22_ofs EQU 22
CAN_F0R2_FB22_len EQU 1
CAN_F0R2_FB23 EQU 0x00800000 ; Filter bits
CAN_F0R2_FB23_ofs EQU 23
CAN_F0R2_FB23_len EQU 1
CAN_F0R2_FB24 EQU 0x01000000 ; Filter bits
CAN_F0R2_FB24_ofs EQU 24
CAN_F0R2_FB24_len EQU 1
CAN_F0R2_FB25 EQU 0x02000000 ; Filter bits
CAN_F0R2_FB25_ofs EQU 25
CAN_F0R2_FB25_len EQU 1
CAN_F0R2_FB26 EQU 0x04000000 ; Filter bits
CAN_F0R2_FB26_ofs EQU 26
CAN_F0R2_FB26_len EQU 1
CAN_F0R2_FB27 EQU 0x08000000 ; Filter bits
CAN_F0R2_FB27_ofs EQU 27
CAN_F0R2_FB27_len EQU 1
CAN_F0R2_FB28 EQU 0x10000000 ; Filter bits
CAN_F0R2_FB28_ofs EQU 28
CAN_F0R2_FB28_len EQU 1
CAN_F0R2_FB29 EQU 0x20000000 ; Filter bits
CAN_F0R2_FB29_ofs EQU 29
CAN_F0R2_FB29_len EQU 1
CAN_F0R2_FB30 EQU 0x40000000 ; Filter bits
CAN_F0R2_FB30_ofs EQU 30
CAN_F0R2_FB30_len EQU 1
CAN_F0R2_FB31 EQU 0x80000000 ; Filter bits
CAN_F0R2_FB31_ofs EQU 31
CAN_F0R2_FB31_len EQU 1
; CAN_F1R1 fields:
CAN_FiRx_FB0 EQU 0x00000001 ; Filter bits
CAN_FiRx_FB0_ofs EQU 0
CAN_FiRx_FB0_len EQU 1
CAN_FiRx_FB1 EQU 0x00000002 ; Filter bits
CAN_FiRx_FB1_ofs EQU 1
CAN_FiRx_FB1_len EQU 1
CAN_FiRx_FB2 EQU 0x00000004 ; Filter bits
CAN_FiRx_FB2_ofs EQU 2
CAN_FiRx_FB2_len EQU 1
CAN_FiRx_FB3 EQU 0x00000008 ; Filter bits
CAN_FiRx_FB3_ofs EQU 3
CAN_FiRx_FB3_len EQU 1
CAN_FiRx_FB4 EQU 0x00000010 ; Filter bits
CAN_FiRx_FB4_ofs EQU 4
CAN_FiRx_FB4_len EQU 1
CAN_FiRx_FB5 EQU 0x00000020 ; Filter bits
CAN_FiRx_FB5_ofs EQU 5
CAN_FiRx_FB5_len EQU 1
CAN_FiRx_FB6 EQU 0x00000040 ; Filter bits
CAN_FiRx_FB6_ofs EQU 6
CAN_FiRx_FB6_len EQU 1
CAN_FiRx_FB7 EQU 0x00000080 ; Filter bits
CAN_FiRx_FB7_ofs EQU 7
CAN_FiRx_FB7_len EQU 1
CAN_FiRx_FB8 EQU 0x00000100 ; Filter bits
CAN_FiRx_FB8_ofs EQU 8
CAN_FiRx_FB8_len EQU 1
CAN_FiRx_FB9 EQU 0x00000200 ; Filter bits
CAN_FiRx_FB9_ofs EQU 9
CAN_FiRx_FB9_len EQU 1
CAN_FiRx_FB10 EQU 0x00000400 ; Filter bits
CAN_FiRx_FB10_ofs EQU 10
CAN_FiRx_FB10_len EQU 1
CAN_FiRx_FB11 EQU 0x00000800 ; Filter bits
CAN_FiRx_FB11_ofs EQU 11
CAN_FiRx_FB11_len EQU 1
CAN_FiRx_FB12 EQU 0x00001000 ; Filter bits
CAN_FiRx_FB12_ofs EQU 12
CAN_FiRx_FB12_len EQU 1
CAN_FiRx_FB13 EQU 0x00002000 ; Filter bits
CAN_FiRx_FB13_ofs EQU 13
CAN_FiRx_FB13_len EQU 1
CAN_FiRx_FB14 EQU 0x00004000 ; Filter bits
CAN_FiRx_FB14_ofs EQU 14
CAN_FiRx_FB14_len EQU 1
CAN_FiRx_FB15 EQU 0x00008000 ; Filter bits
CAN_FiRx_FB15_ofs EQU 15
CAN_FiRx_FB15_len EQU 1
CAN_FiRx_FB16 EQU 0x00010000 ; Filter bits
CAN_FiRx_FB16_ofs EQU 16
CAN_FiRx_FB16_len EQU 1
CAN_FiRx_FB17 EQU 0x00020000 ; Filter bits
CAN_FiRx_FB17_ofs EQU 17
CAN_FiRx_FB17_len EQU 1
CAN_FiRx_FB18 EQU 0x00040000 ; Filter bits
CAN_FiRx_FB18_ofs EQU 18
CAN_FiRx_FB18_len EQU 1
CAN_FiRx_FB19 EQU 0x00080000 ; Filter bits
CAN_FiRx_FB19_ofs EQU 19
CAN_FiRx_FB19_len EQU 1
CAN_FiRx_FB20 EQU 0x00100000 ; Filter bits
CAN_FiRx_FB20_ofs EQU 20
CAN_FiRx_FB20_len EQU 1
CAN_FiRx_FB21 EQU 0x00200000 ; Filter bits
CAN_FiRx_FB21_ofs EQU 21
CAN_FiRx_FB21_len EQU 1
CAN_FiRx_FB22 EQU 0x00400000 ; Filter bits
CAN_FiRx_FB22_ofs EQU 22
CAN_FiRx_FB22_len EQU 1
CAN_FiRx_FB23 EQU 0x00800000 ; Filter bits
CAN_FiRx_FB23_ofs EQU 23
CAN_FiRx_FB23_len EQU 1
CAN_FiRx_FB24 EQU 0x01000000 ; Filter bits
CAN_FiRx_FB24_ofs EQU 24
CAN_FiRx_FB24_len EQU 1
CAN_FiRx_FB25 EQU 0x02000000 ; Filter bits
CAN_FiRx_FB25_ofs EQU 25
CAN_FiRx_FB25_len EQU 1
CAN_FiRx_FB26 EQU 0x04000000 ; Filter bits
CAN_FiRx_FB26_ofs EQU 26
CAN_FiRx_FB26_len EQU 1
CAN_FiRx_FB27 EQU 0x08000000 ; Filter bits
CAN_FiRx_FB27_ofs EQU 27
CAN_FiRx_FB27_len EQU 1
CAN_FiRx_FB28 EQU 0x10000000 ; Filter bits
CAN_FiRx_FB28_ofs EQU 28
CAN_FiRx_FB28_len EQU 1
CAN_FiRx_FB29 EQU 0x20000000 ; Filter bits
CAN_FiRx_FB29_ofs EQU 29
CAN_FiRx_FB29_len EQU 1
CAN_FiRx_FB30 EQU 0x40000000 ; Filter bits
CAN_FiRx_FB30_ofs EQU 30
CAN_FiRx_FB30_len EQU 1
CAN_FiRx_FB31 EQU 0x80000000 ; Filter bits
CAN_FiRx_FB31_ofs EQU 31
CAN_FiRx_FB31_len EQU 1
; ---- USB_FS ------------------------------------------------
; Desc: Universal serial bus full-speed device interface
; USB_FS base address:
USB_FS_BASE EQU 0x40005c00
; USB_FS registers:
USB_FS_USB_EP0R EQU (USB_FS_BASE + 0x0) ; endpoint 0 register
USB_FS_USB_EP1R EQU (USB_FS_BASE + 0x4) ; endpoint 1 register
USB_FS_USB_EP2R EQU (USB_FS_BASE + 0x8) ; endpoint 2 register
USB_FS_USB_EP3R EQU (USB_FS_BASE + 0xc) ; endpoint 3 register
USB_FS_USB_EP4R EQU (USB_FS_BASE + 0x10) ; endpoint 4 register
USB_FS_USB_EP5R EQU (USB_FS_BASE + 0x14) ; endpoint 5 register
USB_FS_USB_EP6R EQU (USB_FS_BASE + 0x18) ; endpoint 6 register
USB_FS_USB_EP7R EQU (USB_FS_BASE + 0x1c) ; endpoint 7 register
USB_FS_USB_CNTR EQU (USB_FS_BASE + 0x40) ; control register
USB_FS_ISTR EQU (USB_FS_BASE + 0x44) ; interrupt status register
USB_FS_FNR EQU (USB_FS_BASE + 0x48) ; frame number register
USB_FS_DADDR EQU (USB_FS_BASE + 0x4c) ; device address
USB_FS_BTABLE EQU (USB_FS_BASE + 0x50) ; Buffer table address
; USB_FS_USB_EP0R fields:
USB_FS_USB_EP0R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP0R_EA_ofs EQU 0
USB_FS_USB_EP0R_EA_len EQU 4
USB_FS_USB_EP0R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP0R_STAT_TX_ofs EQU 4
USB_FS_USB_EP0R_STAT_TX_len EQU 2
USB_FS_USB_EP0R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP0R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP0R_DTOG_TX_len EQU 1
USB_FS_USB_EP0R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP0R_CTR_TX_ofs EQU 7
USB_FS_USB_EP0R_CTR_TX_len EQU 1
USB_FS_USB_EP0R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP0R_EP_KIND_ofs EQU 8
USB_FS_USB_EP0R_EP_KIND_len EQU 1
USB_FS_USB_EP0R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP0R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP0R_EP_TYPE_len EQU 2
USB_FS_USB_EP0R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP0R_SETUP_ofs EQU 11
USB_FS_USB_EP0R_SETUP_len EQU 1
USB_FS_USB_EP0R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP0R_STAT_RX_ofs EQU 12
USB_FS_USB_EP0R_STAT_RX_len EQU 2
USB_FS_USB_EP0R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP0R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP0R_DTOG_RX_len EQU 1
USB_FS_USB_EP0R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP0R_CTR_RX_ofs EQU 15
USB_FS_USB_EP0R_CTR_RX_len EQU 1
; USB_FS_USB_EP1R fields:
USB_FS_USB_EP1R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP1R_EA_ofs EQU 0
USB_FS_USB_EP1R_EA_len EQU 4
USB_FS_USB_EP1R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP1R_STAT_TX_ofs EQU 4
USB_FS_USB_EP1R_STAT_TX_len EQU 2
USB_FS_USB_EP1R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP1R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP1R_DTOG_TX_len EQU 1
USB_FS_USB_EP1R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP1R_CTR_TX_ofs EQU 7
USB_FS_USB_EP1R_CTR_TX_len EQU 1
USB_FS_USB_EP1R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP1R_EP_KIND_ofs EQU 8
USB_FS_USB_EP1R_EP_KIND_len EQU 1
USB_FS_USB_EP1R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP1R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP1R_EP_TYPE_len EQU 2
USB_FS_USB_EP1R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP1R_SETUP_ofs EQU 11
USB_FS_USB_EP1R_SETUP_len EQU 1
USB_FS_USB_EP1R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP1R_STAT_RX_ofs EQU 12
USB_FS_USB_EP1R_STAT_RX_len EQU 2
USB_FS_USB_EP1R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP1R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP1R_DTOG_RX_len EQU 1
USB_FS_USB_EP1R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP1R_CTR_RX_ofs EQU 15
USB_FS_USB_EP1R_CTR_RX_len EQU 1
; USB_FS_USB_EP2R fields:
USB_FS_USB_EP2R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP2R_EA_ofs EQU 0
USB_FS_USB_EP2R_EA_len EQU 4
USB_FS_USB_EP2R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP2R_STAT_TX_ofs EQU 4
USB_FS_USB_EP2R_STAT_TX_len EQU 2
USB_FS_USB_EP2R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP2R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP2R_DTOG_TX_len EQU 1
USB_FS_USB_EP2R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP2R_CTR_TX_ofs EQU 7
USB_FS_USB_EP2R_CTR_TX_len EQU 1
USB_FS_USB_EP2R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP2R_EP_KIND_ofs EQU 8
USB_FS_USB_EP2R_EP_KIND_len EQU 1
USB_FS_USB_EP2R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP2R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP2R_EP_TYPE_len EQU 2
USB_FS_USB_EP2R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP2R_SETUP_ofs EQU 11
USB_FS_USB_EP2R_SETUP_len EQU 1
USB_FS_USB_EP2R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP2R_STAT_RX_ofs EQU 12
USB_FS_USB_EP2R_STAT_RX_len EQU 2
USB_FS_USB_EP2R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP2R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP2R_DTOG_RX_len EQU 1
USB_FS_USB_EP2R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP2R_CTR_RX_ofs EQU 15
USB_FS_USB_EP2R_CTR_RX_len EQU 1
; USB_FS_USB_EP3R fields:
USB_FS_USB_EP3R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP3R_EA_ofs EQU 0
USB_FS_USB_EP3R_EA_len EQU 4
USB_FS_USB_EP3R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP3R_STAT_TX_ofs EQU 4
USB_FS_USB_EP3R_STAT_TX_len EQU 2
USB_FS_USB_EP3R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP3R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP3R_DTOG_TX_len EQU 1
USB_FS_USB_EP3R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP3R_CTR_TX_ofs EQU 7
USB_FS_USB_EP3R_CTR_TX_len EQU 1
USB_FS_USB_EP3R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP3R_EP_KIND_ofs EQU 8
USB_FS_USB_EP3R_EP_KIND_len EQU 1
USB_FS_USB_EP3R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP3R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP3R_EP_TYPE_len EQU 2
USB_FS_USB_EP3R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP3R_SETUP_ofs EQU 11
USB_FS_USB_EP3R_SETUP_len EQU 1
USB_FS_USB_EP3R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP3R_STAT_RX_ofs EQU 12
USB_FS_USB_EP3R_STAT_RX_len EQU 2
USB_FS_USB_EP3R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP3R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP3R_DTOG_RX_len EQU 1
USB_FS_USB_EP3R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP3R_CTR_RX_ofs EQU 15
USB_FS_USB_EP3R_CTR_RX_len EQU 1
; USB_FS_USB_EP4R fields:
USB_FS_USB_EP4R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP4R_EA_ofs EQU 0
USB_FS_USB_EP4R_EA_len EQU 4
USB_FS_USB_EP4R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP4R_STAT_TX_ofs EQU 4
USB_FS_USB_EP4R_STAT_TX_len EQU 2
USB_FS_USB_EP4R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP4R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP4R_DTOG_TX_len EQU 1
USB_FS_USB_EP4R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP4R_CTR_TX_ofs EQU 7
USB_FS_USB_EP4R_CTR_TX_len EQU 1
USB_FS_USB_EP4R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP4R_EP_KIND_ofs EQU 8
USB_FS_USB_EP4R_EP_KIND_len EQU 1
USB_FS_USB_EP4R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP4R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP4R_EP_TYPE_len EQU 2
USB_FS_USB_EP4R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP4R_SETUP_ofs EQU 11
USB_FS_USB_EP4R_SETUP_len EQU 1
USB_FS_USB_EP4R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP4R_STAT_RX_ofs EQU 12
USB_FS_USB_EP4R_STAT_RX_len EQU 2
USB_FS_USB_EP4R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP4R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP4R_DTOG_RX_len EQU 1
USB_FS_USB_EP4R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP4R_CTR_RX_ofs EQU 15
USB_FS_USB_EP4R_CTR_RX_len EQU 1
; USB_FS_USB_EP5R fields:
USB_FS_USB_EP5R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP5R_EA_ofs EQU 0
USB_FS_USB_EP5R_EA_len EQU 4
USB_FS_USB_EP5R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP5R_STAT_TX_ofs EQU 4
USB_FS_USB_EP5R_STAT_TX_len EQU 2
USB_FS_USB_EP5R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP5R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP5R_DTOG_TX_len EQU 1
USB_FS_USB_EP5R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP5R_CTR_TX_ofs EQU 7
USB_FS_USB_EP5R_CTR_TX_len EQU 1
USB_FS_USB_EP5R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP5R_EP_KIND_ofs EQU 8
USB_FS_USB_EP5R_EP_KIND_len EQU 1
USB_FS_USB_EP5R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP5R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP5R_EP_TYPE_len EQU 2
USB_FS_USB_EP5R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP5R_SETUP_ofs EQU 11
USB_FS_USB_EP5R_SETUP_len EQU 1
USB_FS_USB_EP5R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP5R_STAT_RX_ofs EQU 12
USB_FS_USB_EP5R_STAT_RX_len EQU 2
USB_FS_USB_EP5R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP5R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP5R_DTOG_RX_len EQU 1
USB_FS_USB_EP5R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP5R_CTR_RX_ofs EQU 15
USB_FS_USB_EP5R_CTR_RX_len EQU 1
; USB_FS_USB_EP6R fields:
USB_FS_USB_EP6R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP6R_EA_ofs EQU 0
USB_FS_USB_EP6R_EA_len EQU 4
USB_FS_USB_EP6R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP6R_STAT_TX_ofs EQU 4
USB_FS_USB_EP6R_STAT_TX_len EQU 2
USB_FS_USB_EP6R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP6R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP6R_DTOG_TX_len EQU 1
USB_FS_USB_EP6R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP6R_CTR_TX_ofs EQU 7
USB_FS_USB_EP6R_CTR_TX_len EQU 1
USB_FS_USB_EP6R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP6R_EP_KIND_ofs EQU 8
USB_FS_USB_EP6R_EP_KIND_len EQU 1
USB_FS_USB_EP6R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP6R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP6R_EP_TYPE_len EQU 2
USB_FS_USB_EP6R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP6R_SETUP_ofs EQU 11
USB_FS_USB_EP6R_SETUP_len EQU 1
USB_FS_USB_EP6R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP6R_STAT_RX_ofs EQU 12
USB_FS_USB_EP6R_STAT_RX_len EQU 2
USB_FS_USB_EP6R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP6R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP6R_DTOG_RX_len EQU 1
USB_FS_USB_EP6R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP6R_CTR_RX_ofs EQU 15
USB_FS_USB_EP6R_CTR_RX_len EQU 1
; USB_FS_USB_EP7R fields:
USB_FS_USB_EP7R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP7R_EA_ofs EQU 0
USB_FS_USB_EP7R_EA_len EQU 4
USB_FS_USB_EP7R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP7R_STAT_TX_ofs EQU 4
USB_FS_USB_EP7R_STAT_TX_len EQU 2
USB_FS_USB_EP7R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP7R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP7R_DTOG_TX_len EQU 1
USB_FS_USB_EP7R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP7R_CTR_TX_ofs EQU 7
USB_FS_USB_EP7R_CTR_TX_len EQU 1
USB_FS_USB_EP7R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP7R_EP_KIND_ofs EQU 8
USB_FS_USB_EP7R_EP_KIND_len EQU 1
USB_FS_USB_EP7R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP7R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP7R_EP_TYPE_len EQU 2
USB_FS_USB_EP7R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP7R_SETUP_ofs EQU 11
USB_FS_USB_EP7R_SETUP_len EQU 1
USB_FS_USB_EP7R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP7R_STAT_RX_ofs EQU 12
USB_FS_USB_EP7R_STAT_RX_len EQU 2
USB_FS_USB_EP7R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP7R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP7R_DTOG_RX_len EQU 1
USB_FS_USB_EP7R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP7R_CTR_RX_ofs EQU 15
USB_FS_USB_EP7R_CTR_RX_len EQU 1
; USB_FS_USB_CNTR fields:
USB_FS_USB_CNTR_FRES EQU 0x00000001 ; Force USB Reset
USB_FS_USB_CNTR_FRES_ofs EQU 0
USB_FS_USB_CNTR_FRES_len EQU 1
USB_FS_USB_CNTR_PDWN EQU 0x00000002 ; Power down
USB_FS_USB_CNTR_PDWN_ofs EQU 1
USB_FS_USB_CNTR_PDWN_len EQU 1
USB_FS_USB_CNTR_LPMODE EQU 0x00000004 ; Low-power mode
USB_FS_USB_CNTR_LPMODE_ofs EQU 2
USB_FS_USB_CNTR_LPMODE_len EQU 1
USB_FS_USB_CNTR_FSUSP EQU 0x00000008 ; Force suspend
USB_FS_USB_CNTR_FSUSP_ofs EQU 3
USB_FS_USB_CNTR_FSUSP_len EQU 1
USB_FS_USB_CNTR_RESUME EQU 0x00000010 ; Resume request
USB_FS_USB_CNTR_RESUME_ofs EQU 4
USB_FS_USB_CNTR_RESUME_len EQU 1
USB_FS_USB_CNTR_ESOFM EQU 0x00000100 ; Expected start of frame interrupt mask
USB_FS_USB_CNTR_ESOFM_ofs EQU 8
USB_FS_USB_CNTR_ESOFM_len EQU 1
USB_FS_USB_CNTR_SOFM EQU 0x00000200 ; Start of frame interrupt mask
USB_FS_USB_CNTR_SOFM_ofs EQU 9
USB_FS_USB_CNTR_SOFM_len EQU 1
USB_FS_USB_CNTR_RESETM EQU 0x00000400 ; USB reset interrupt mask
USB_FS_USB_CNTR_RESETM_ofs EQU 10
USB_FS_USB_CNTR_RESETM_len EQU 1
USB_FS_USB_CNTR_SUSPM EQU 0x00000800 ; Suspend mode interrupt mask
USB_FS_USB_CNTR_SUSPM_ofs EQU 11
USB_FS_USB_CNTR_SUSPM_len EQU 1
USB_FS_USB_CNTR_WKUPM EQU 0x00001000 ; Wakeup interrupt mask
USB_FS_USB_CNTR_WKUPM_ofs EQU 12
USB_FS_USB_CNTR_WKUPM_len EQU 1
USB_FS_USB_CNTR_ERRM EQU 0x00002000 ; Error interrupt mask
USB_FS_USB_CNTR_ERRM_ofs EQU 13
USB_FS_USB_CNTR_ERRM_len EQU 1
USB_FS_USB_CNTR_PMAOVRM EQU 0x00004000 ; Packet memory area over / underrun interrupt mask
USB_FS_USB_CNTR_PMAOVRM_ofs EQU 14
USB_FS_USB_CNTR_PMAOVRM_len EQU 1
USB_FS_USB_CNTR_CTRM EQU 0x00008000 ; Correct transfer interrupt mask
USB_FS_USB_CNTR_CTRM_ofs EQU 15
USB_FS_USB_CNTR_CTRM_len EQU 1
; USB_FS_ISTR fields:
USB_FS_ISTR_EP_ID EQU 0x0000000f ; Endpoint Identifier
USB_FS_ISTR_EP_ID_ofs EQU 0
USB_FS_ISTR_EP_ID_len EQU 4
USB_FS_ISTR_DIR EQU 0x00000010 ; Direction of transaction
USB_FS_ISTR_DIR_ofs EQU 4
USB_FS_ISTR_DIR_len EQU 1
USB_FS_ISTR_ESOF EQU 0x00000100 ; Expected start frame
USB_FS_ISTR_ESOF_ofs EQU 8
USB_FS_ISTR_ESOF_len EQU 1
USB_FS_ISTR_SOF EQU 0x00000200 ; start of frame
USB_FS_ISTR_SOF_ofs EQU 9
USB_FS_ISTR_SOF_len EQU 1
USB_FS_ISTR_RESET EQU 0x00000400 ; reset request
USB_FS_ISTR_RESET_ofs EQU 10
USB_FS_ISTR_RESET_len EQU 1
USB_FS_ISTR_SUSP EQU 0x00000800 ; Suspend mode request
USB_FS_ISTR_SUSP_ofs EQU 11
USB_FS_ISTR_SUSP_len EQU 1
USB_FS_ISTR_WKUP EQU 0x00001000 ; Wakeup
USB_FS_ISTR_WKUP_ofs EQU 12
USB_FS_ISTR_WKUP_len EQU 1
USB_FS_ISTR_ERR EQU 0x00002000 ; Error
USB_FS_ISTR_ERR_ofs EQU 13
USB_FS_ISTR_ERR_len EQU 1
USB_FS_ISTR_PMAOVR EQU 0x00004000 ; Packet memory area over / underrun
USB_FS_ISTR_PMAOVR_ofs EQU 14
USB_FS_ISTR_PMAOVR_len EQU 1
USB_FS_ISTR_CTR EQU 0x00008000 ; Correct transfer
USB_FS_ISTR_CTR_ofs EQU 15
USB_FS_ISTR_CTR_len EQU 1
; USB_FS_FNR fields:
USB_FS_FNR_FN EQU 0x000007ff ; Frame number
USB_FS_FNR_FN_ofs EQU 0
USB_FS_FNR_FN_len EQU 11
USB_FS_FNR_LSOF EQU 0x00001800 ; Lost SOF
USB_FS_FNR_LSOF_ofs EQU 11
USB_FS_FNR_LSOF_len EQU 2
USB_FS_FNR_LCK EQU 0x00002000 ; Locked
USB_FS_FNR_LCK_ofs EQU 13
USB_FS_FNR_LCK_len EQU 1
USB_FS_FNR_RXDM EQU 0x00004000 ; Receive data - line status
USB_FS_FNR_RXDM_ofs EQU 14
USB_FS_FNR_RXDM_len EQU 1
USB_FS_FNR_RXDP EQU 0x00008000 ; Receive data + line status
USB_FS_FNR_RXDP_ofs EQU 15
USB_FS_FNR_RXDP_len EQU 1
; USB_FS_DADDR fields:
USB_FS_DADDR_ADD EQU 0x00000001 ; Device address
USB_FS_DADDR_ADD_ofs EQU 0
USB_FS_DADDR_ADD_len EQU 1
USB_FS_DADDR_ADD1 EQU 0x00000002 ; Device address
USB_FS_DADDR_ADD1_ofs EQU 1
USB_FS_DADDR_ADD1_len EQU 1
USB_FS_DADDR_ADD2 EQU 0x00000004 ; Device address
USB_FS_DADDR_ADD2_ofs EQU 2
USB_FS_DADDR_ADD2_len EQU 1
USB_FS_DADDR_ADD3 EQU 0x00000008 ; Device address
USB_FS_DADDR_ADD3_ofs EQU 3
USB_FS_DADDR_ADD3_len EQU 1
USB_FS_DADDR_ADD4 EQU 0x00000010 ; Device address
USB_FS_DADDR_ADD4_ofs EQU 4
USB_FS_DADDR_ADD4_len EQU 1
USB_FS_DADDR_ADD5 EQU 0x00000020 ; Device address
USB_FS_DADDR_ADD5_ofs EQU 5
USB_FS_DADDR_ADD5_len EQU 1
USB_FS_DADDR_ADD6 EQU 0x00000040 ; Device address
USB_FS_DADDR_ADD6_ofs EQU 6
USB_FS_DADDR_ADD6_len EQU 1
USB_FS_DADDR_EF EQU 0x00000080 ; Enable function
USB_FS_DADDR_EF_ofs EQU 7
USB_FS_DADDR_EF_len EQU 1
; USB_FS_BTABLE fields:
USB_FS_BTABLE_BTABLE EQU 0x0000fff8 ; Buffer table
USB_FS_BTABLE_BTABLE_ofs EQU 3
USB_FS_BTABLE_BTABLE_len EQU 13
; ---- I2C1 --------------------------------------------------
; Desc: Inter-integrated circuit
; I2C1 base address:
I2C1_BASE EQU 0x40005400
; I2C1 registers:
I2C1_CR1 EQU (I2C1_BASE + 0x0) ; Control register 1
I2C1_CR2 EQU (I2C1_BASE + 0x4) ; Control register 2
I2C1_OAR1 EQU (I2C1_BASE + 0x8) ; Own address register 1
I2C1_OAR2 EQU (I2C1_BASE + 0xc) ; Own address register 2
I2C1_TIMINGR EQU (I2C1_BASE + 0x10) ; Timing register
I2C1_TIMEOUTR EQU (I2C1_BASE + 0x14) ; Status register 1
I2C1_ISR EQU (I2C1_BASE + 0x18) ; Interrupt and Status register
I2C1_ICR EQU (I2C1_BASE + 0x1c) ; Interrupt clear register
I2C1_PECR EQU (I2C1_BASE + 0x20) ; PEC register
I2C1_RXDR EQU (I2C1_BASE + 0x24) ; Receive data register
I2C1_TXDR EQU (I2C1_BASE + 0x28) ; Transmit data register
; I2C1_CR1 fields:
I2C_CR1_PE EQU 0x00000001 ; Peripheral enable
I2C_CR1_PE_ofs EQU 0
I2C_CR1_PE_len EQU 1
I2C_CR1_TXIE EQU 0x00000002 ; TX Interrupt enable
I2C_CR1_TXIE_ofs EQU 1
I2C_CR1_TXIE_len EQU 1
I2C_CR1_RXIE EQU 0x00000004 ; RX Interrupt enable
I2C_CR1_RXIE_ofs EQU 2
I2C_CR1_RXIE_len EQU 1
I2C_CR1_ADDRIE EQU 0x00000008 ; Address match interrupt enable (slave only)
I2C_CR1_ADDRIE_ofs EQU 3
I2C_CR1_ADDRIE_len EQU 1
I2C_CR1_NACKIE EQU 0x00000010 ; Not acknowledge received interrupt enable
I2C_CR1_NACKIE_ofs EQU 4
I2C_CR1_NACKIE_len EQU 1
I2C_CR1_STOPIE EQU 0x00000020 ; STOP detection Interrupt enable
I2C_CR1_STOPIE_ofs EQU 5
I2C_CR1_STOPIE_len EQU 1
I2C_CR1_TCIE EQU 0x00000040 ; Transfer Complete interrupt enable
I2C_CR1_TCIE_ofs EQU 6
I2C_CR1_TCIE_len EQU 1
I2C_CR1_ERRIE EQU 0x00000080 ; Error interrupts enable
I2C_CR1_ERRIE_ofs EQU 7
I2C_CR1_ERRIE_len EQU 1
I2C_CR1_DNF EQU 0x00000f00 ; Digital noise filter
I2C_CR1_DNF_ofs EQU 8
I2C_CR1_DNF_len EQU 4
I2C_CR1_ANFOFF EQU 0x00001000 ; Analog noise filter OFF
I2C_CR1_ANFOFF_ofs EQU 12
I2C_CR1_ANFOFF_len EQU 1
I2C_CR1_SWRST EQU 0x00002000 ; Software reset
I2C_CR1_SWRST_ofs EQU 13
I2C_CR1_SWRST_len EQU 1
I2C_CR1_TXDMAEN EQU 0x00004000 ; DMA transmission requests enable
I2C_CR1_TXDMAEN_ofs EQU 14
I2C_CR1_TXDMAEN_len EQU 1
I2C_CR1_RXDMAEN EQU 0x00008000 ; DMA reception requests enable
I2C_CR1_RXDMAEN_ofs EQU 15
I2C_CR1_RXDMAEN_len EQU 1
I2C_CR1_SBC EQU 0x00010000 ; Slave byte control
I2C_CR1_SBC_ofs EQU 16
I2C_CR1_SBC_len EQU 1
I2C_CR1_NOSTRETCH EQU 0x00020000 ; Clock stretching disable
I2C_CR1_NOSTRETCH_ofs EQU 17
I2C_CR1_NOSTRETCH_len EQU 1
I2C_CR1_WUPEN EQU 0x00040000 ; Wakeup from STOP enable
I2C_CR1_WUPEN_ofs EQU 18
I2C_CR1_WUPEN_len EQU 1
I2C_CR1_GCEN EQU 0x00080000 ; General call enable
I2C_CR1_GCEN_ofs EQU 19
I2C_CR1_GCEN_len EQU 1
I2C_CR1_SMBHEN EQU 0x00100000 ; SMBus Host address enable
I2C_CR1_SMBHEN_ofs EQU 20
I2C_CR1_SMBHEN_len EQU 1
I2C_CR1_SMBDEN EQU 0x00200000 ; SMBus Device Default address enable
I2C_CR1_SMBDEN_ofs EQU 21
I2C_CR1_SMBDEN_len EQU 1
I2C_CR1_ALERTEN EQU 0x00400000 ; SMBUS alert enable
I2C_CR1_ALERTEN_ofs EQU 22
I2C_CR1_ALERTEN_len EQU 1
I2C_CR1_PECEN EQU 0x00800000 ; PEC enable
I2C_CR1_PECEN_ofs EQU 23
I2C_CR1_PECEN_len EQU 1
; I2C1_CR2 fields:
I2C_CR2_PECBYTE EQU 0x04000000 ; Packet error checking byte
I2C_CR2_PECBYTE_ofs EQU 26
I2C_CR2_PECBYTE_len EQU 1
I2C_CR2_AUTOEND EQU 0x02000000 ; Automatic end mode (master mode)
I2C_CR2_AUTOEND_ofs EQU 25
I2C_CR2_AUTOEND_len EQU 1
I2C_CR2_RELOAD EQU 0x01000000 ; NBYTES reload mode
I2C_CR2_RELOAD_ofs EQU 24
I2C_CR2_RELOAD_len EQU 1
I2C_CR2_NBYTES EQU 0x00ff0000 ; Number of bytes
I2C_CR2_NBYTES_ofs EQU 16
I2C_CR2_NBYTES_len EQU 8
I2C_CR2_NACK EQU 0x00008000 ; NACK generation (slave mode)
I2C_CR2_NACK_ofs EQU 15
I2C_CR2_NACK_len EQU 1
I2C_CR2_STOP EQU 0x00004000 ; Stop generation (master mode)
I2C_CR2_STOP_ofs EQU 14
I2C_CR2_STOP_len EQU 1
I2C_CR2_START EQU 0x00002000 ; Start generation
I2C_CR2_START_ofs EQU 13
I2C_CR2_START_len EQU 1
I2C_CR2_HEAD10R EQU 0x00001000 ; 10-bit address header only read direction (master receiver mode)
I2C_CR2_HEAD10R_ofs EQU 12
I2C_CR2_HEAD10R_len EQU 1
I2C_CR2_ADD10 EQU 0x00000800 ; 10-bit addressing mode (master mode)
I2C_CR2_ADD10_ofs EQU 11
I2C_CR2_ADD10_len EQU 1
I2C_CR2_RD_WRN EQU 0x00000400 ; Transfer direction (master mode)
I2C_CR2_RD_WRN_ofs EQU 10
I2C_CR2_RD_WRN_len EQU 1
I2C_CR2_SADD8 EQU 0x00000300 ; Slave address bit 9:8 (master mode)
I2C_CR2_SADD8_ofs EQU 8
I2C_CR2_SADD8_len EQU 2
I2C_CR2_SADD1 EQU 0x000000fe ; Slave address bit 7:1 (master mode)
I2C_CR2_SADD1_ofs EQU 1
I2C_CR2_SADD1_len EQU 7
I2C_CR2_SADD0 EQU 0x00000001 ; Slave address bit 0 (master mode)
I2C_CR2_SADD0_ofs EQU 0
I2C_CR2_SADD0_len EQU 1
; I2C1_OAR1 fields:
I2C_OAR1_OA1_0 EQU 0x00000001 ; Interface address
I2C_OAR1_OA1_0_ofs EQU 0
I2C_OAR1_OA1_0_len EQU 1
I2C_OAR1_OA1_1 EQU 0x000000fe ; Interface address
I2C_OAR1_OA1_1_ofs EQU 1
I2C_OAR1_OA1_1_len EQU 7
I2C_OAR1_OA1_8 EQU 0x00000300 ; Interface address
I2C_OAR1_OA1_8_ofs EQU 8
I2C_OAR1_OA1_8_len EQU 2
I2C_OAR1_OA1MODE EQU 0x00000400 ; Own Address 1 10-bit mode
I2C_OAR1_OA1MODE_ofs EQU 10
I2C_OAR1_OA1MODE_len EQU 1
I2C_OAR1_OA1EN EQU 0x00008000 ; Own Address 1 enable
I2C_OAR1_OA1EN_ofs EQU 15
I2C_OAR1_OA1EN_len EQU 1
; I2C1_OAR2 fields:
I2C_OAR2_OA2 EQU 0x000000fe ; Interface address
I2C_OAR2_OA2_ofs EQU 1
I2C_OAR2_OA2_len EQU 7
I2C_OAR2_OA2MSK EQU 0x00000700 ; Own Address 2 masks
I2C_OAR2_OA2MSK_ofs EQU 8
I2C_OAR2_OA2MSK_len EQU 3
I2C_OAR2_OA2EN EQU 0x00008000 ; Own Address 2 enable
I2C_OAR2_OA2EN_ofs EQU 15
I2C_OAR2_OA2EN_len EQU 1
; I2C1_TIMINGR fields:
I2C_TIMINGR_SCLL EQU 0x000000ff ; SCL low period (master mode)
I2C_TIMINGR_SCLL_ofs EQU 0
I2C_TIMINGR_SCLL_len EQU 8
I2C_TIMINGR_SCLH EQU 0x0000ff00 ; SCL high period (master mode)
I2C_TIMINGR_SCLH_ofs EQU 8
I2C_TIMINGR_SCLH_len EQU 8
I2C_TIMINGR_SDADEL EQU 0x000f0000 ; Data hold time
I2C_TIMINGR_SDADEL_ofs EQU 16
I2C_TIMINGR_SDADEL_len EQU 4
I2C_TIMINGR_SCLDEL EQU 0x00f00000 ; Data setup time
I2C_TIMINGR_SCLDEL_ofs EQU 20
I2C_TIMINGR_SCLDEL_len EQU 4
I2C_TIMINGR_PRESC EQU 0xf0000000 ; Timing prescaler
I2C_TIMINGR_PRESC_ofs EQU 28
I2C_TIMINGR_PRESC_len EQU 4
; I2C1_TIMEOUTR fields:
I2C_TIMEOUTR_TIMEOUTA EQU 0x00000fff ; Bus timeout A
I2C_TIMEOUTR_TIMEOUTA_ofs EQU 0
I2C_TIMEOUTR_TIMEOUTA_len EQU 12
I2C_TIMEOUTR_TIDLE EQU 0x00001000 ; Idle clock timeout detection
I2C_TIMEOUTR_TIDLE_ofs EQU 12
I2C_TIMEOUTR_TIDLE_len EQU 1
I2C_TIMEOUTR_TIMOUTEN EQU 0x00008000 ; Clock timeout enable
I2C_TIMEOUTR_TIMOUTEN_ofs EQU 15
I2C_TIMEOUTR_TIMOUTEN_len EQU 1
I2C_TIMEOUTR_TIMEOUTB EQU 0x0fff0000 ; Bus timeout B
I2C_TIMEOUTR_TIMEOUTB_ofs EQU 16
I2C_TIMEOUTR_TIMEOUTB_len EQU 12
I2C_TIMEOUTR_TEXTEN EQU 0x80000000 ; Extended clock timeout enable
I2C_TIMEOUTR_TEXTEN_ofs EQU 31
I2C_TIMEOUTR_TEXTEN_len EQU 1
; I2C1_ISR fields:
I2C_ISR_ADDCODE EQU 0x00fe0000 ; Address match code (Slave mode)
I2C_ISR_ADDCODE_ofs EQU 17
I2C_ISR_ADDCODE_len EQU 7
I2C_ISR_DIR EQU 0x00010000 ; Transfer direction (Slave mode)
I2C_ISR_DIR_ofs EQU 16
I2C_ISR_DIR_len EQU 1
I2C_ISR_BUSY EQU 0x00008000 ; Bus busy
I2C_ISR_BUSY_ofs EQU 15
I2C_ISR_BUSY_len EQU 1
I2C_ISR_ALERT EQU 0x00002000 ; SMBus alert
I2C_ISR_ALERT_ofs EQU 13
I2C_ISR_ALERT_len EQU 1
I2C_ISR_TIMEOUT EQU 0x00001000 ; Timeout or t_low detection flag
I2C_ISR_TIMEOUT_ofs EQU 12
I2C_ISR_TIMEOUT_len EQU 1
I2C_ISR_PECERR EQU 0x00000800 ; PEC Error in reception
I2C_ISR_PECERR_ofs EQU 11
I2C_ISR_PECERR_len EQU 1
I2C_ISR_OVR EQU 0x00000400 ; Overrun/Underrun (slave mode)
I2C_ISR_OVR_ofs EQU 10
I2C_ISR_OVR_len EQU 1
I2C_ISR_ARLO EQU 0x00000200 ; Arbitration lost
I2C_ISR_ARLO_ofs EQU 9
I2C_ISR_ARLO_len EQU 1
I2C_ISR_BERR EQU 0x00000100 ; Bus error
I2C_ISR_BERR_ofs EQU 8
I2C_ISR_BERR_len EQU 1
I2C_ISR_TCR EQU 0x00000080 ; Transfer Complete Reload
I2C_ISR_TCR_ofs EQU 7
I2C_ISR_TCR_len EQU 1
I2C_ISR_TC EQU 0x00000040 ; Transfer Complete (master mode)
I2C_ISR_TC_ofs EQU 6
I2C_ISR_TC_len EQU 1
I2C_ISR_STOPF EQU 0x00000020 ; Stop detection flag
I2C_ISR_STOPF_ofs EQU 5
I2C_ISR_STOPF_len EQU 1
I2C_ISR_NACKF EQU 0x00000010 ; Not acknowledge received flag
I2C_ISR_NACKF_ofs EQU 4
I2C_ISR_NACKF_len EQU 1
I2C_ISR_ADDR EQU 0x00000008 ; Address matched (slave mode)
I2C_ISR_ADDR_ofs EQU 3
I2C_ISR_ADDR_len EQU 1
I2C_ISR_RXNE EQU 0x00000004 ; Receive data register not empty (receivers)
I2C_ISR_RXNE_ofs EQU 2
I2C_ISR_RXNE_len EQU 1
I2C_ISR_TXIS EQU 0x00000002 ; Transmit interrupt status (transmitters)
I2C_ISR_TXIS_ofs EQU 1
I2C_ISR_TXIS_len EQU 1
I2C_ISR_TXE EQU 0x00000001 ; Transmit data register empty (transmitters)
I2C_ISR_TXE_ofs EQU 0
I2C_ISR_TXE_len EQU 1
; I2C1_ICR fields:
I2C_ICR_ALERTCF EQU 0x00002000 ; Alert flag clear
I2C_ICR_ALERTCF_ofs EQU 13
I2C_ICR_ALERTCF_len EQU 1
I2C_ICR_TIMOUTCF EQU 0x00001000 ; Timeout detection flag clear
I2C_ICR_TIMOUTCF_ofs EQU 12
I2C_ICR_TIMOUTCF_len EQU 1
I2C_ICR_PECCF EQU 0x00000800 ; PEC Error flag clear
I2C_ICR_PECCF_ofs EQU 11
I2C_ICR_PECCF_len EQU 1
I2C_ICR_OVRCF EQU 0x00000400 ; Overrun/Underrun flag clear
I2C_ICR_OVRCF_ofs EQU 10
I2C_ICR_OVRCF_len EQU 1
I2C_ICR_ARLOCF EQU 0x00000200 ; Arbitration lost flag clear
I2C_ICR_ARLOCF_ofs EQU 9
I2C_ICR_ARLOCF_len EQU 1
I2C_ICR_BERRCF EQU 0x00000100 ; Bus error flag clear
I2C_ICR_BERRCF_ofs EQU 8
I2C_ICR_BERRCF_len EQU 1
I2C_ICR_STOPCF EQU 0x00000020 ; Stop detection flag clear
I2C_ICR_STOPCF_ofs EQU 5
I2C_ICR_STOPCF_len EQU 1
I2C_ICR_NACKCF EQU 0x00000010 ; Not Acknowledge flag clear
I2C_ICR_NACKCF_ofs EQU 4
I2C_ICR_NACKCF_len EQU 1
I2C_ICR_ADDRCF EQU 0x00000008 ; Address Matched flag clear
I2C_ICR_ADDRCF_ofs EQU 3
I2C_ICR_ADDRCF_len EQU 1
; I2C1_PECR fields:
I2C_PECR_PEC EQU 0x000000ff ; Packet error checking register
I2C_PECR_PEC_ofs EQU 0
I2C_PECR_PEC_len EQU 8
; I2C1_RXDR fields:
I2C_RXDR_RXDATA EQU 0x000000ff ; 8-bit receive data
I2C_RXDR_RXDATA_ofs EQU 0
I2C_RXDR_RXDATA_len EQU 8
; I2C1_TXDR fields:
I2C_TXDR_TXDATA EQU 0x000000ff ; 8-bit transmit data
I2C_TXDR_TXDATA_ofs EQU 0
I2C_TXDR_TXDATA_len EQU 8
; ---- I2C2 --------------------------------------------------
; Desc: None
; I2C2 base address:
I2C2_BASE EQU 0x40005800
; I2C2 registers:
I2C2_CR1 EQU (I2C2_BASE + 0x0) ; Control register 1
I2C2_CR2 EQU (I2C2_BASE + 0x4) ; Control register 2
I2C2_OAR1 EQU (I2C2_BASE + 0x8) ; Own address register 1
I2C2_OAR2 EQU (I2C2_BASE + 0xc) ; Own address register 2
I2C2_TIMINGR EQU (I2C2_BASE + 0x10) ; Timing register
I2C2_TIMEOUTR EQU (I2C2_BASE + 0x14) ; Status register 1
I2C2_ISR EQU (I2C2_BASE + 0x18) ; Interrupt and Status register
I2C2_ICR EQU (I2C2_BASE + 0x1c) ; Interrupt clear register
I2C2_PECR EQU (I2C2_BASE + 0x20) ; PEC register
I2C2_RXDR EQU (I2C2_BASE + 0x24) ; Receive data register
I2C2_TXDR EQU (I2C2_BASE + 0x28) ; Transmit data register
; Fields the same as in the first instance.
; ---- IWDG --------------------------------------------------
; Desc: Independent watchdog
; IWDG base address:
IWDG_BASE EQU 0x40003000
; IWDG registers:
IWDG_KR EQU (IWDG_BASE + 0x0) ; Key register
IWDG_PR EQU (IWDG_BASE + 0x4) ; Prescaler register
IWDG_RLR EQU (IWDG_BASE + 0x8) ; Reload register
IWDG_SR EQU (IWDG_BASE + 0xc) ; Status register
IWDG_WINR EQU (IWDG_BASE + 0x10) ; Window register
; IWDG_KR fields:
IWDG_KR_KEY EQU 0x0000ffff ; Key value
IWDG_KR_KEY_ofs EQU 0
IWDG_KR_KEY_len EQU 16
; IWDG_PR fields:
IWDG_PR_PR EQU 0x00000007 ; Prescaler divider
IWDG_PR_PR_ofs EQU 0
IWDG_PR_PR_len EQU 3
; IWDG_RLR fields:
IWDG_RLR_RL EQU 0x00000fff ; Watchdog counter reload value
IWDG_RLR_RL_ofs EQU 0
IWDG_RLR_RL_len EQU 12
; IWDG_SR fields:
IWDG_SR_PVU EQU 0x00000001 ; Watchdog prescaler value update
IWDG_SR_PVU_ofs EQU 0
IWDG_SR_PVU_len EQU 1
IWDG_SR_RVU EQU 0x00000002 ; Watchdog counter reload value update
IWDG_SR_RVU_ofs EQU 1
IWDG_SR_RVU_len EQU 1
IWDG_SR_WVU EQU 0x00000004 ; Watchdog counter window value update
IWDG_SR_WVU_ofs EQU 2
IWDG_SR_WVU_len EQU 1
; IWDG_WINR fields:
IWDG_WINR_WIN EQU 0x00000fff ; Watchdog counter window value
IWDG_WINR_WIN_ofs EQU 0
IWDG_WINR_WIN_len EQU 12
; ---- WWDG --------------------------------------------------
; Desc: Window watchdog
; WWDG base address:
WWDG_BASE EQU 0x40002c00
; WWDG registers:
WWDG_CR EQU (WWDG_BASE + 0x0) ; Control register
WWDG_CFR EQU (WWDG_BASE + 0x4) ; Configuration register
WWDG_SR EQU (WWDG_BASE + 0x8) ; Status register
; WWDG_CR fields:
WWDG_CR_T EQU 0x0000007f ; 7-bit counter
WWDG_CR_T_ofs EQU 0
WWDG_CR_T_len EQU 7
WWDG_CR_WDGA EQU 0x00000080 ; Activation bit
WWDG_CR_WDGA_ofs EQU 7
WWDG_CR_WDGA_len EQU 1
; WWDG_CFR fields:
WWDG_CFR_EWI EQU 0x00000200 ; Early wakeup interrupt
WWDG_CFR_EWI_ofs EQU 9
WWDG_CFR_EWI_len EQU 1
WWDG_CFR_WDGTB EQU 0x00000180 ; Timer base
WWDG_CFR_WDGTB_ofs EQU 7
WWDG_CFR_WDGTB_len EQU 2
WWDG_CFR_W EQU 0x0000007f ; 7-bit window value
WWDG_CFR_W_ofs EQU 0
WWDG_CFR_W_len EQU 7
; WWDG_SR fields:
WWDG_SR_EWIF EQU 0x00000001 ; Early wakeup interrupt flag
WWDG_SR_EWIF_ofs EQU 0
WWDG_SR_EWIF_len EQU 1
; ---- RTC ---------------------------------------------------
; Desc: Real-time clock
; RTC base address:
RTC_BASE EQU 0x40002800
; RTC registers:
RTC_TR EQU (RTC_BASE + 0x0) ; time register
RTC_DR EQU (RTC_BASE + 0x4) ; date register
RTC_CR EQU (RTC_BASE + 0x8) ; control register
RTC_ISR EQU (RTC_BASE + 0xc) ; initialization and status register
RTC_PRER EQU (RTC_BASE + 0x10) ; prescaler register
RTC_WUTR EQU (RTC_BASE + 0x14) ; wakeup timer register
RTC_ALRMAR EQU (RTC_BASE + 0x1c) ; alarm A register
RTC_ALRMBR EQU (RTC_BASE + 0x20) ; alarm B register
RTC_WPR EQU (RTC_BASE + 0x24) ; write protection register
RTC_SSR EQU (RTC_BASE + 0x28) ; sub second register
RTC_SHIFTR EQU (RTC_BASE + 0x2c) ; shift control register
RTC_TSTR EQU (RTC_BASE + 0x30) ; time stamp time register
RTC_TSDR EQU (RTC_BASE + 0x34) ; time stamp date register
RTC_TSSSR EQU (RTC_BASE + 0x38) ; timestamp sub second register
RTC_CALR EQU (RTC_BASE + 0x3c) ; calibration register
RTC_TAFCR EQU (RTC_BASE + 0x40) ; tamper and alternate function configuration register
RTC_ALRMASSR EQU (RTC_BASE + 0x44) ; alarm A sub second register
RTC_ALRMBSSR EQU (RTC_BASE + 0x48) ; alarm B sub second register
RTC_BKP0R EQU (RTC_BASE + 0x50) ; backup register
RTC_BKP1R EQU (RTC_BASE + 0x54) ; backup register
RTC_BKP2R EQU (RTC_BASE + 0x58) ; backup register
RTC_BKP3R EQU (RTC_BASE + 0x5c) ; backup register
RTC_BKP4R EQU (RTC_BASE + 0x60) ; backup register
RTC_BKP5R EQU (RTC_BASE + 0x64) ; backup register
RTC_BKP6R EQU (RTC_BASE + 0x68) ; backup register
RTC_BKP7R EQU (RTC_BASE + 0x6c) ; backup register
RTC_BKP8R EQU (RTC_BASE + 0x70) ; backup register
RTC_BKP9R EQU (RTC_BASE + 0x74) ; backup register
RTC_BKP10R EQU (RTC_BASE + 0x78) ; backup register
RTC_BKP11R EQU (RTC_BASE + 0x7c) ; backup register
RTC_BKP12R EQU (RTC_BASE + 0x80) ; backup register
RTC_BKP13R EQU (RTC_BASE + 0x84) ; backup register
RTC_BKP14R EQU (RTC_BASE + 0x88) ; backup register
RTC_BKP15R EQU (RTC_BASE + 0x8c) ; backup register
RTC_BKP16R EQU (RTC_BASE + 0x90) ; backup register
RTC_BKP17R EQU (RTC_BASE + 0x94) ; backup register
RTC_BKP18R EQU (RTC_BASE + 0x98) ; backup register
RTC_BKP19R EQU (RTC_BASE + 0x9c) ; backup register
RTC_BKP20R EQU (RTC_BASE + 0xa0) ; backup register
RTC_BKP21R EQU (RTC_BASE + 0xa4) ; backup register
RTC_BKP22R EQU (RTC_BASE + 0xa8) ; backup register
RTC_BKP23R EQU (RTC_BASE + 0xac) ; backup register
RTC_BKP24R EQU (RTC_BASE + 0xb0) ; backup register
RTC_BKP25R EQU (RTC_BASE + 0xb4) ; backup register
RTC_BKP26R EQU (RTC_BASE + 0xb8) ; backup register
RTC_BKP27R EQU (RTC_BASE + 0xbc) ; backup register
RTC_BKP28R EQU (RTC_BASE + 0xc0) ; backup register
RTC_BKP29R EQU (RTC_BASE + 0xc4) ; backup register
RTC_BKP30R EQU (RTC_BASE + 0xc8) ; backup register
RTC_BKP31R EQU (RTC_BASE + 0xcc) ; backup register
; RTC_TR fields:
RTC_TR_PM EQU 0x00400000 ; AM/PM notation
RTC_TR_PM_ofs EQU 22
RTC_TR_PM_len EQU 1
RTC_TR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_TR_HT_ofs EQU 20
RTC_TR_HT_len EQU 2
RTC_TR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_TR_HU_ofs EQU 16
RTC_TR_HU_len EQU 4
RTC_TR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_TR_MNT_ofs EQU 12
RTC_TR_MNT_len EQU 3
RTC_TR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_TR_MNU_ofs EQU 8
RTC_TR_MNU_len EQU 4
RTC_TR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_TR_ST_ofs EQU 4
RTC_TR_ST_len EQU 3
RTC_TR_SU EQU 0x0000000f ; Second units in BCD format
RTC_TR_SU_ofs EQU 0
RTC_TR_SU_len EQU 4
; RTC_DR fields:
RTC_DR_YT EQU 0x00f00000 ; Year tens in BCD format
RTC_DR_YT_ofs EQU 20
RTC_DR_YT_len EQU 4
RTC_DR_YU EQU 0x000f0000 ; Year units in BCD format
RTC_DR_YU_ofs EQU 16
RTC_DR_YU_len EQU 4
RTC_DR_WDU EQU 0x0000e000 ; Week day units
RTC_DR_WDU_ofs EQU 13
RTC_DR_WDU_len EQU 3
RTC_DR_MT EQU 0x00001000 ; Month tens in BCD format
RTC_DR_MT_ofs EQU 12
RTC_DR_MT_len EQU 1
RTC_DR_MU EQU 0x00000f00 ; Month units in BCD format
RTC_DR_MU_ofs EQU 8
RTC_DR_MU_len EQU 4
RTC_DR_DT EQU 0x00000030 ; Date tens in BCD format
RTC_DR_DT_ofs EQU 4
RTC_DR_DT_len EQU 2
RTC_DR_DU EQU 0x0000000f ; Date units in BCD format
RTC_DR_DU_ofs EQU 0
RTC_DR_DU_len EQU 4
; RTC_CR fields:
RTC_CR_WCKSEL EQU 0x00000007 ; Wakeup clock selection
RTC_CR_WCKSEL_ofs EQU 0
RTC_CR_WCKSEL_len EQU 3
RTC_CR_TSEDGE EQU 0x00000008 ; Time-stamp event active edge
RTC_CR_TSEDGE_ofs EQU 3
RTC_CR_TSEDGE_len EQU 1
RTC_CR_REFCKON EQU 0x00000010 ; Reference clock detection enable (50 or 60 Hz)
RTC_CR_REFCKON_ofs EQU 4
RTC_CR_REFCKON_len EQU 1
RTC_CR_BYPSHAD EQU 0x00000020 ; Bypass the shadow registers
RTC_CR_BYPSHAD_ofs EQU 5
RTC_CR_BYPSHAD_len EQU 1
RTC_CR_FMT EQU 0x00000040 ; Hour format
RTC_CR_FMT_ofs EQU 6
RTC_CR_FMT_len EQU 1
RTC_CR_ALRAE EQU 0x00000100 ; Alarm A enable
RTC_CR_ALRAE_ofs EQU 8
RTC_CR_ALRAE_len EQU 1
RTC_CR_ALRBE EQU 0x00000200 ; Alarm B enable
RTC_CR_ALRBE_ofs EQU 9
RTC_CR_ALRBE_len EQU 1
RTC_CR_WUTE EQU 0x00000400 ; Wakeup timer enable
RTC_CR_WUTE_ofs EQU 10
RTC_CR_WUTE_len EQU 1
RTC_CR_TSE EQU 0x00000800 ; Time stamp enable
RTC_CR_TSE_ofs EQU 11
RTC_CR_TSE_len EQU 1
RTC_CR_ALRAIE EQU 0x00001000 ; Alarm A interrupt enable
RTC_CR_ALRAIE_ofs EQU 12
RTC_CR_ALRAIE_len EQU 1
RTC_CR_ALRBIE EQU 0x00002000 ; Alarm B interrupt enable
RTC_CR_ALRBIE_ofs EQU 13
RTC_CR_ALRBIE_len EQU 1
RTC_CR_WUTIE EQU 0x00004000 ; Wakeup timer interrupt enable
RTC_CR_WUTIE_ofs EQU 14
RTC_CR_WUTIE_len EQU 1
RTC_CR_TSIE EQU 0x00008000 ; Time-stamp interrupt enable
RTC_CR_TSIE_ofs EQU 15
RTC_CR_TSIE_len EQU 1
RTC_CR_ADD1H EQU 0x00010000 ; Add 1 hour (summer time change)
RTC_CR_ADD1H_ofs EQU 16
RTC_CR_ADD1H_len EQU 1
RTC_CR_SUB1H EQU 0x00020000 ; Subtract 1 hour (winter time change)
RTC_CR_SUB1H_ofs EQU 17
RTC_CR_SUB1H_len EQU 1
RTC_CR_BKP EQU 0x00040000 ; Backup
RTC_CR_BKP_ofs EQU 18
RTC_CR_BKP_len EQU 1
RTC_CR_COSEL EQU 0x00080000 ; Calibration output selection
RTC_CR_COSEL_ofs EQU 19
RTC_CR_COSEL_len EQU 1
RTC_CR_POL EQU 0x00100000 ; Output polarity
RTC_CR_POL_ofs EQU 20
RTC_CR_POL_len EQU 1
RTC_CR_OSEL EQU 0x00600000 ; Output selection
RTC_CR_OSEL_ofs EQU 21
RTC_CR_OSEL_len EQU 2
RTC_CR_COE EQU 0x00800000 ; Calibration output enable
RTC_CR_COE_ofs EQU 23
RTC_CR_COE_len EQU 1
; RTC_ISR fields:
RTC_ISR_ALRAWF EQU 0x00000001 ; Alarm A write flag
RTC_ISR_ALRAWF_ofs EQU 0
RTC_ISR_ALRAWF_len EQU 1
RTC_ISR_ALRBWF EQU 0x00000002 ; Alarm B write flag
RTC_ISR_ALRBWF_ofs EQU 1
RTC_ISR_ALRBWF_len EQU 1
RTC_ISR_WUTWF EQU 0x00000004 ; Wakeup timer write flag
RTC_ISR_WUTWF_ofs EQU 2
RTC_ISR_WUTWF_len EQU 1
RTC_ISR_SHPF EQU 0x00000008 ; Shift operation pending
RTC_ISR_SHPF_ofs EQU 3
RTC_ISR_SHPF_len EQU 1
RTC_ISR_INITS EQU 0x00000010 ; Initialization status flag
RTC_ISR_INITS_ofs EQU 4
RTC_ISR_INITS_len EQU 1
RTC_ISR_RSF EQU 0x00000020 ; Registers synchronization flag
RTC_ISR_RSF_ofs EQU 5
RTC_ISR_RSF_len EQU 1
RTC_ISR_INITF EQU 0x00000040 ; Initialization flag
RTC_ISR_INITF_ofs EQU 6
RTC_ISR_INITF_len EQU 1
RTC_ISR_INIT EQU 0x00000080 ; Initialization mode
RTC_ISR_INIT_ofs EQU 7
RTC_ISR_INIT_len EQU 1
RTC_ISR_ALRAF EQU 0x00000100 ; Alarm A flag
RTC_ISR_ALRAF_ofs EQU 8
RTC_ISR_ALRAF_len EQU 1
RTC_ISR_ALRBF EQU 0x00000200 ; Alarm B flag
RTC_ISR_ALRBF_ofs EQU 9
RTC_ISR_ALRBF_len EQU 1
RTC_ISR_WUTF EQU 0x00000400 ; Wakeup timer flag
RTC_ISR_WUTF_ofs EQU 10
RTC_ISR_WUTF_len EQU 1
RTC_ISR_TSF EQU 0x00000800 ; Time-stamp flag
RTC_ISR_TSF_ofs EQU 11
RTC_ISR_TSF_len EQU 1
RTC_ISR_TSOVF EQU 0x00001000 ; Time-stamp overflow flag
RTC_ISR_TSOVF_ofs EQU 12
RTC_ISR_TSOVF_len EQU 1
RTC_ISR_TAMP1F EQU 0x00002000 ; Tamper detection flag
RTC_ISR_TAMP1F_ofs EQU 13
RTC_ISR_TAMP1F_len EQU 1
RTC_ISR_TAMP2F EQU 0x00004000 ; RTC_TAMP2 detection flag
RTC_ISR_TAMP2F_ofs EQU 14
RTC_ISR_TAMP2F_len EQU 1
RTC_ISR_TAMP3F EQU 0x00008000 ; RTC_TAMP3 detection flag
RTC_ISR_TAMP3F_ofs EQU 15
RTC_ISR_TAMP3F_len EQU 1
RTC_ISR_RECALPF EQU 0x00010000 ; Recalibration pending Flag
RTC_ISR_RECALPF_ofs EQU 16
RTC_ISR_RECALPF_len EQU 1
; RTC_PRER fields:
RTC_PRER_PREDIV_A EQU 0x007f0000 ; Asynchronous prescaler factor
RTC_PRER_PREDIV_A_ofs EQU 16
RTC_PRER_PREDIV_A_len EQU 7
RTC_PRER_PREDIV_S EQU 0x00007fff ; Synchronous prescaler factor
RTC_PRER_PREDIV_S_ofs EQU 0
RTC_PRER_PREDIV_S_len EQU 15
; RTC_WUTR fields:
RTC_WUTR_WUT EQU 0x0000ffff ; Wakeup auto-reload value bits
RTC_WUTR_WUT_ofs EQU 0
RTC_WUTR_WUT_len EQU 16
; RTC_ALRMAR fields:
RTC_ALRMAR_MSK4 EQU 0x80000000 ; Alarm A date mask
RTC_ALRMAR_MSK4_ofs EQU 31
RTC_ALRMAR_MSK4_len EQU 1
RTC_ALRMAR_WDSEL EQU 0x40000000 ; Week day selection
RTC_ALRMAR_WDSEL_ofs EQU 30
RTC_ALRMAR_WDSEL_len EQU 1
RTC_ALRMAR_DT EQU 0x30000000 ; Date tens in BCD format
RTC_ALRMAR_DT_ofs EQU 28
RTC_ALRMAR_DT_len EQU 2
RTC_ALRMAR_DU EQU 0x0f000000 ; Date units or day in BCD format
RTC_ALRMAR_DU_ofs EQU 24
RTC_ALRMAR_DU_len EQU 4
RTC_ALRMAR_MSK3 EQU 0x00800000 ; Alarm A hours mask
RTC_ALRMAR_MSK3_ofs EQU 23
RTC_ALRMAR_MSK3_len EQU 1
RTC_ALRMAR_PM EQU 0x00400000 ; AM/PM notation
RTC_ALRMAR_PM_ofs EQU 22
RTC_ALRMAR_PM_len EQU 1
RTC_ALRMAR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_ALRMAR_HT_ofs EQU 20
RTC_ALRMAR_HT_len EQU 2
RTC_ALRMAR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_ALRMAR_HU_ofs EQU 16
RTC_ALRMAR_HU_len EQU 4
RTC_ALRMAR_MSK2 EQU 0x00008000 ; Alarm A minutes mask
RTC_ALRMAR_MSK2_ofs EQU 15
RTC_ALRMAR_MSK2_len EQU 1
RTC_ALRMAR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_ALRMAR_MNT_ofs EQU 12
RTC_ALRMAR_MNT_len EQU 3
RTC_ALRMAR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_ALRMAR_MNU_ofs EQU 8
RTC_ALRMAR_MNU_len EQU 4
RTC_ALRMAR_MSK1 EQU 0x00000080 ; Alarm A seconds mask
RTC_ALRMAR_MSK1_ofs EQU 7
RTC_ALRMAR_MSK1_len EQU 1
RTC_ALRMAR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_ALRMAR_ST_ofs EQU 4
RTC_ALRMAR_ST_len EQU 3
RTC_ALRMAR_SU EQU 0x0000000f ; Second units in BCD format
RTC_ALRMAR_SU_ofs EQU 0
RTC_ALRMAR_SU_len EQU 4
; RTC_ALRMBR fields:
RTC_ALRMBR_MSK4 EQU 0x80000000 ; Alarm B date mask
RTC_ALRMBR_MSK4_ofs EQU 31
RTC_ALRMBR_MSK4_len EQU 1
RTC_ALRMBR_WDSEL EQU 0x40000000 ; Week day selection
RTC_ALRMBR_WDSEL_ofs EQU 30
RTC_ALRMBR_WDSEL_len EQU 1
RTC_ALRMBR_DT EQU 0x30000000 ; Date tens in BCD format
RTC_ALRMBR_DT_ofs EQU 28
RTC_ALRMBR_DT_len EQU 2
RTC_ALRMBR_DU EQU 0x0f000000 ; Date units or day in BCD format
RTC_ALRMBR_DU_ofs EQU 24
RTC_ALRMBR_DU_len EQU 4
RTC_ALRMBR_MSK3 EQU 0x00800000 ; Alarm B hours mask
RTC_ALRMBR_MSK3_ofs EQU 23
RTC_ALRMBR_MSK3_len EQU 1
RTC_ALRMBR_PM EQU 0x00400000 ; AM/PM notation
RTC_ALRMBR_PM_ofs EQU 22
RTC_ALRMBR_PM_len EQU 1
RTC_ALRMBR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_ALRMBR_HT_ofs EQU 20
RTC_ALRMBR_HT_len EQU 2
RTC_ALRMBR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_ALRMBR_HU_ofs EQU 16
RTC_ALRMBR_HU_len EQU 4
RTC_ALRMBR_MSK2 EQU 0x00008000 ; Alarm B minutes mask
RTC_ALRMBR_MSK2_ofs EQU 15
RTC_ALRMBR_MSK2_len EQU 1
RTC_ALRMBR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_ALRMBR_MNT_ofs EQU 12
RTC_ALRMBR_MNT_len EQU 3
RTC_ALRMBR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_ALRMBR_MNU_ofs EQU 8
RTC_ALRMBR_MNU_len EQU 4
RTC_ALRMBR_MSK1 EQU 0x00000080 ; Alarm B seconds mask
RTC_ALRMBR_MSK1_ofs EQU 7
RTC_ALRMBR_MSK1_len EQU 1
RTC_ALRMBR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_ALRMBR_ST_ofs EQU 4
RTC_ALRMBR_ST_len EQU 3
RTC_ALRMBR_SU EQU 0x0000000f ; Second units in BCD format
RTC_ALRMBR_SU_ofs EQU 0
RTC_ALRMBR_SU_len EQU 4
; RTC_WPR fields:
RTC_WPR_KEY EQU 0x000000ff ; Write protection key
RTC_WPR_KEY_ofs EQU 0
RTC_WPR_KEY_len EQU 8
; RTC_SSR fields:
RTC_SSR_SS EQU 0x0000ffff ; Sub second value
RTC_SSR_SS_ofs EQU 0
RTC_SSR_SS_len EQU 16
; RTC_SHIFTR fields:
RTC_SHIFTR_ADD1S EQU 0x80000000 ; Add one second
RTC_SHIFTR_ADD1S_ofs EQU 31
RTC_SHIFTR_ADD1S_len EQU 1
RTC_SHIFTR_SUBFS EQU 0x00007fff ; Subtract a fraction of a second
RTC_SHIFTR_SUBFS_ofs EQU 0
RTC_SHIFTR_SUBFS_len EQU 15
; RTC_TSTR fields:
RTC_TSTR_SU EQU 0x0000000f ; Second units in BCD format
RTC_TSTR_SU_ofs EQU 0
RTC_TSTR_SU_len EQU 4
RTC_TSTR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_TSTR_ST_ofs EQU 4
RTC_TSTR_ST_len EQU 3
RTC_TSTR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_TSTR_MNU_ofs EQU 8
RTC_TSTR_MNU_len EQU 4
RTC_TSTR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_TSTR_MNT_ofs EQU 12
RTC_TSTR_MNT_len EQU 3
RTC_TSTR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_TSTR_HU_ofs EQU 16
RTC_TSTR_HU_len EQU 4
RTC_TSTR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_TSTR_HT_ofs EQU 20
RTC_TSTR_HT_len EQU 2
RTC_TSTR_PM EQU 0x00400000 ; AM/PM notation
RTC_TSTR_PM_ofs EQU 22
RTC_TSTR_PM_len EQU 1
; RTC_TSDR fields:
RTC_TSDR_WDU EQU 0x0000e000 ; Week day units
RTC_TSDR_WDU_ofs EQU 13
RTC_TSDR_WDU_len EQU 3
RTC_TSDR_MT EQU 0x00001000 ; Month tens in BCD format
RTC_TSDR_MT_ofs EQU 12
RTC_TSDR_MT_len EQU 1
RTC_TSDR_MU EQU 0x00000f00 ; Month units in BCD format
RTC_TSDR_MU_ofs EQU 8
RTC_TSDR_MU_len EQU 4
RTC_TSDR_DT EQU 0x00000030 ; Date tens in BCD format
RTC_TSDR_DT_ofs EQU 4
RTC_TSDR_DT_len EQU 2
RTC_TSDR_DU EQU 0x0000000f ; Date units in BCD format
RTC_TSDR_DU_ofs EQU 0
RTC_TSDR_DU_len EQU 4
; RTC_TSSSR fields:
RTC_TSSSR_SS EQU 0x0000ffff ; Sub second value
RTC_TSSSR_SS_ofs EQU 0
RTC_TSSSR_SS_len EQU 16
; RTC_CALR fields:
RTC_CALR_CALP EQU 0x00008000 ; Increase frequency of RTC by 488.5 ppm
RTC_CALR_CALP_ofs EQU 15
RTC_CALR_CALP_len EQU 1
RTC_CALR_CALW8 EQU 0x00004000 ; Use an 8-second calibration cycle period
RTC_CALR_CALW8_ofs EQU 14
RTC_CALR_CALW8_len EQU 1
RTC_CALR_CALW16 EQU 0x00002000 ; Use a 16-second calibration cycle period
RTC_CALR_CALW16_ofs EQU 13
RTC_CALR_CALW16_len EQU 1
RTC_CALR_CALM EQU 0x000001ff ; Calibration minus
RTC_CALR_CALM_ofs EQU 0
RTC_CALR_CALM_len EQU 9
; RTC_TAFCR fields:
RTC_TAFCR_TAMP1E EQU 0x00000001 ; Tamper 1 detection enable
RTC_TAFCR_TAMP1E_ofs EQU 0
RTC_TAFCR_TAMP1E_len EQU 1
RTC_TAFCR_TAMP1TRG EQU 0x00000002 ; Active level for tamper 1
RTC_TAFCR_TAMP1TRG_ofs EQU 1
RTC_TAFCR_TAMP1TRG_len EQU 1
RTC_TAFCR_TAMPIE EQU 0x00000004 ; Tamper interrupt enable
RTC_TAFCR_TAMPIE_ofs EQU 2
RTC_TAFCR_TAMPIE_len EQU 1
RTC_TAFCR_TAMP2E EQU 0x00000008 ; Tamper 2 detection enable
RTC_TAFCR_TAMP2E_ofs EQU 3
RTC_TAFCR_TAMP2E_len EQU 1
RTC_TAFCR_TAMP2TRG EQU 0x00000010 ; Active level for tamper 2
RTC_TAFCR_TAMP2TRG_ofs EQU 4
RTC_TAFCR_TAMP2TRG_len EQU 1
RTC_TAFCR_TAMP3E EQU 0x00000020 ; Tamper 3 detection enable
RTC_TAFCR_TAMP3E_ofs EQU 5
RTC_TAFCR_TAMP3E_len EQU 1
RTC_TAFCR_TAMP3TRG EQU 0x00000040 ; Active level for tamper 3
RTC_TAFCR_TAMP3TRG_ofs EQU 6
RTC_TAFCR_TAMP3TRG_len EQU 1
RTC_TAFCR_TAMPTS EQU 0x00000080 ; Activate timestamp on tamper detection event
RTC_TAFCR_TAMPTS_ofs EQU 7
RTC_TAFCR_TAMPTS_len EQU 1
RTC_TAFCR_TAMPFREQ EQU 0x00000700 ; Tamper sampling frequency
RTC_TAFCR_TAMPFREQ_ofs EQU 8
RTC_TAFCR_TAMPFREQ_len EQU 3
RTC_TAFCR_TAMPFLT EQU 0x00001800 ; Tamper filter count
RTC_TAFCR_TAMPFLT_ofs EQU 11
RTC_TAFCR_TAMPFLT_len EQU 2
RTC_TAFCR_TAMPPRCH EQU 0x00006000 ; Tamper precharge duration
RTC_TAFCR_TAMPPRCH_ofs EQU 13
RTC_TAFCR_TAMPPRCH_len EQU 2
RTC_TAFCR_TAMPPUDIS EQU 0x00008000 ; TAMPER pull-up disable
RTC_TAFCR_TAMPPUDIS_ofs EQU 15
RTC_TAFCR_TAMPPUDIS_len EQU 1
RTC_TAFCR_PC13VALUE EQU 0x00040000 ; PC13 value
RTC_TAFCR_PC13VALUE_ofs EQU 18
RTC_TAFCR_PC13VALUE_len EQU 1
RTC_TAFCR_PC13MODE EQU 0x00080000 ; PC13 mode
RTC_TAFCR_PC13MODE_ofs EQU 19
RTC_TAFCR_PC13MODE_len EQU 1
RTC_TAFCR_PC14VALUE EQU 0x00100000 ; PC14 value
RTC_TAFCR_PC14VALUE_ofs EQU 20
RTC_TAFCR_PC14VALUE_len EQU 1
RTC_TAFCR_PC14MODE EQU 0x00200000 ; PC 14 mode
RTC_TAFCR_PC14MODE_ofs EQU 21
RTC_TAFCR_PC14MODE_len EQU 1
RTC_TAFCR_PC15VALUE EQU 0x00400000 ; PC15 value
RTC_TAFCR_PC15VALUE_ofs EQU 22
RTC_TAFCR_PC15VALUE_len EQU 1
RTC_TAFCR_PC15MODE EQU 0x00800000 ; PC15 mode
RTC_TAFCR_PC15MODE_ofs EQU 23
RTC_TAFCR_PC15MODE_len EQU 1
; RTC_ALRMASSR fields:
RTC_ALRMASSR_MASKSS EQU 0x0f000000 ; Mask the most-significant bits starting at this bit
RTC_ALRMASSR_MASKSS_ofs EQU 24
RTC_ALRMASSR_MASKSS_len EQU 4
RTC_ALRMASSR_SS EQU 0x00007fff ; Sub seconds value
RTC_ALRMASSR_SS_ofs EQU 0
RTC_ALRMASSR_SS_len EQU 15
; RTC_ALRMBSSR fields:
RTC_ALRMBSSR_MASKSS EQU 0x0f000000 ; Mask the most-significant bits starting at this bit
RTC_ALRMBSSR_MASKSS_ofs EQU 24
RTC_ALRMBSSR_MASKSS_len EQU 4
RTC_ALRMBSSR_SS EQU 0x00007fff ; Sub seconds value
RTC_ALRMBSSR_SS_ofs EQU 0
RTC_ALRMBSSR_SS_len EQU 15
; RTC_BKP0R fields:
RTC_BKP0R_BKP EQU 0xffffffff ; BKP
RTC_BKP0R_BKP_ofs EQU 0
RTC_BKP0R_BKP_len EQU 32
; RTC_BKP1R fields:
RTC_BKP1R_BKP EQU 0xffffffff ; BKP
RTC_BKP1R_BKP_ofs EQU 0
RTC_BKP1R_BKP_len EQU 32
; RTC_BKP2R fields:
RTC_BKP2R_BKP EQU 0xffffffff ; BKP
RTC_BKP2R_BKP_ofs EQU 0
RTC_BKP2R_BKP_len EQU 32
; RTC_BKP3R fields:
RTC_BKP3R_BKP EQU 0xffffffff ; BKP
RTC_BKP3R_BKP_ofs EQU 0
RTC_BKP3R_BKP_len EQU 32
; RTC_BKP4R fields:
RTC_BKP4R_BKP EQU 0xffffffff ; BKP
RTC_BKP4R_BKP_ofs EQU 0
RTC_BKP4R_BKP_len EQU 32
; RTC_BKP5R fields:
RTC_BKP5R_BKP EQU 0xffffffff ; BKP
RTC_BKP5R_BKP_ofs EQU 0
RTC_BKP5R_BKP_len EQU 32
; RTC_BKP6R fields:
RTC_BKP6R_BKP EQU 0xffffffff ; BKP
RTC_BKP6R_BKP_ofs EQU 0
RTC_BKP6R_BKP_len EQU 32
; RTC_BKP7R fields:
RTC_BKP7R_BKP EQU 0xffffffff ; BKP
RTC_BKP7R_BKP_ofs EQU 0
RTC_BKP7R_BKP_len EQU 32
; RTC_BKP8R fields:
RTC_BKP8R_BKP EQU 0xffffffff ; BKP
RTC_BKP8R_BKP_ofs EQU 0
RTC_BKP8R_BKP_len EQU 32
; RTC_BKP9R fields:
RTC_BKP9R_BKP EQU 0xffffffff ; BKP
RTC_BKP9R_BKP_ofs EQU 0
RTC_BKP9R_BKP_len EQU 32
; RTC_BKP10R fields:
RTC_BKP10R_BKP EQU 0xffffffff ; BKP
RTC_BKP10R_BKP_ofs EQU 0
RTC_BKP10R_BKP_len EQU 32
; RTC_BKP11R fields:
RTC_BKP11R_BKP EQU 0xffffffff ; BKP
RTC_BKP11R_BKP_ofs EQU 0
RTC_BKP11R_BKP_len EQU 32
; RTC_BKP12R fields:
RTC_BKP12R_BKP EQU 0xffffffff ; BKP
RTC_BKP12R_BKP_ofs EQU 0
RTC_BKP12R_BKP_len EQU 32
; RTC_BKP13R fields:
RTC_BKP13R_BKP EQU 0xffffffff ; BKP
RTC_BKP13R_BKP_ofs EQU 0
RTC_BKP13R_BKP_len EQU 32
; RTC_BKP14R fields:
RTC_BKP14R_BKP EQU 0xffffffff ; BKP
RTC_BKP14R_BKP_ofs EQU 0
RTC_BKP14R_BKP_len EQU 32
; RTC_BKP15R fields:
RTC_BKP15R_BKP EQU 0xffffffff ; BKP
RTC_BKP15R_BKP_ofs EQU 0
RTC_BKP15R_BKP_len EQU 32
; RTC_BKP16R fields:
RTC_BKP16R_BKP EQU 0xffffffff ; BKP
RTC_BKP16R_BKP_ofs EQU 0
RTC_BKP16R_BKP_len EQU 32
; RTC_BKP17R fields:
RTC_BKP17R_BKP EQU 0xffffffff ; BKP
RTC_BKP17R_BKP_ofs EQU 0
RTC_BKP17R_BKP_len EQU 32
; RTC_BKP18R fields:
RTC_BKP18R_BKP EQU 0xffffffff ; BKP
RTC_BKP18R_BKP_ofs EQU 0
RTC_BKP18R_BKP_len EQU 32
; RTC_BKP19R fields:
RTC_BKP19R_BKP EQU 0xffffffff ; BKP
RTC_BKP19R_BKP_ofs EQU 0
RTC_BKP19R_BKP_len EQU 32
; RTC_BKP20R fields:
RTC_BKP20R_BKP EQU 0xffffffff ; BKP
RTC_BKP20R_BKP_ofs EQU 0
RTC_BKP20R_BKP_len EQU 32
; RTC_BKP21R fields:
RTC_BKP21R_BKP EQU 0xffffffff ; BKP
RTC_BKP21R_BKP_ofs EQU 0
RTC_BKP21R_BKP_len EQU 32
; RTC_BKP22R fields:
RTC_BKP22R_BKP EQU 0xffffffff ; BKP
RTC_BKP22R_BKP_ofs EQU 0
RTC_BKP22R_BKP_len EQU 32
; RTC_BKP23R fields:
RTC_BKP23R_BKP EQU 0xffffffff ; BKP
RTC_BKP23R_BKP_ofs EQU 0
RTC_BKP23R_BKP_len EQU 32
; RTC_BKP24R fields:
RTC_BKP24R_BKP EQU 0xffffffff ; BKP
RTC_BKP24R_BKP_ofs EQU 0
RTC_BKP24R_BKP_len EQU 32
; RTC_BKP25R fields:
RTC_BKP25R_BKP EQU 0xffffffff ; BKP
RTC_BKP25R_BKP_ofs EQU 0
RTC_BKP25R_BKP_len EQU 32
; RTC_BKP26R fields:
RTC_BKP26R_BKP EQU 0xffffffff ; BKP
RTC_BKP26R_BKP_ofs EQU 0
RTC_BKP26R_BKP_len EQU 32
; RTC_BKP27R fields:
RTC_BKP27R_BKP EQU 0xffffffff ; BKP
RTC_BKP27R_BKP_ofs EQU 0
RTC_BKP27R_BKP_len EQU 32
; RTC_BKP28R fields:
RTC_BKP28R_BKP EQU 0xffffffff ; BKP
RTC_BKP28R_BKP_ofs EQU 0
RTC_BKP28R_BKP_len EQU 32
; RTC_BKP29R fields:
RTC_BKP29R_BKP EQU 0xffffffff ; BKP
RTC_BKP29R_BKP_ofs EQU 0
RTC_BKP29R_BKP_len EQU 32
; RTC_BKP30R fields:
RTC_BKP30R_BKP EQU 0xffffffff ; BKP
RTC_BKP30R_BKP_ofs EQU 0
RTC_BKP30R_BKP_len EQU 32
; RTC_BKP31R fields:
RTC_BKP31R_BKP EQU 0xffffffff ; BKP
RTC_BKP31R_BKP_ofs EQU 0
RTC_BKP31R_BKP_len EQU 32
; ---- TIM6 --------------------------------------------------
; Desc: Basic timers
; TIM6 base address:
TIM6_BASE EQU 0x40001000
; TIM6 registers:
TIM6_CR1 EQU (TIM6_BASE + 0x0) ; control register 1
TIM6_CR2 EQU (TIM6_BASE + 0x4) ; control register 2
TIM6_DIER EQU (TIM6_BASE + 0xc) ; DMA/Interrupt enable register
TIM6_SR EQU (TIM6_BASE + 0x10) ; status register
TIM6_EGR EQU (TIM6_BASE + 0x14) ; event generation register
TIM6_CNT EQU (TIM6_BASE + 0x24) ; counter
TIM6_PSC EQU (TIM6_BASE + 0x28) ; prescaler
TIM6_ARR EQU (TIM6_BASE + 0x2c) ; auto-reload register
; TIM6_CR1 fields:
TIM6_CR1_CEN EQU 0x00000001 ; Counter enable
TIM6_CR1_CEN_ofs EQU 0
TIM6_CR1_CEN_len EQU 1
TIM6_CR1_UDIS EQU 0x00000002 ; Update disable
TIM6_CR1_UDIS_ofs EQU 1
TIM6_CR1_UDIS_len EQU 1
TIM6_CR1_URS EQU 0x00000004 ; Update request source
TIM6_CR1_URS_ofs EQU 2
TIM6_CR1_URS_len EQU 1
TIM6_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM6_CR1_OPM_ofs EQU 3
TIM6_CR1_OPM_len EQU 1
TIM6_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM6_CR1_ARPE_ofs EQU 7
TIM6_CR1_ARPE_len EQU 1
TIM6_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM6_CR1_UIFREMAP_ofs EQU 11
TIM6_CR1_UIFREMAP_len EQU 1
; TIM6_CR2 fields:
TIM6_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM6_CR2_MMS_ofs EQU 4
TIM6_CR2_MMS_len EQU 3
; TIM6_DIER fields:
TIM6_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM6_DIER_UDE_ofs EQU 8
TIM6_DIER_UDE_len EQU 1
TIM6_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM6_DIER_UIE_ofs EQU 0
TIM6_DIER_UIE_len EQU 1
; TIM6_SR fields:
TIM6_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM6_SR_UIF_ofs EQU 0
TIM6_SR_UIF_len EQU 1
; TIM6_EGR fields:
TIM6_EGR_UG EQU 0x00000001 ; Update generation
TIM6_EGR_UG_ofs EQU 0
TIM6_EGR_UG_len EQU 1
; TIM6_CNT fields:
TIM6_CNT_CNT EQU 0x0000ffff ; Low counter value
TIM6_CNT_CNT_ofs EQU 0
TIM6_CNT_CNT_len EQU 16
TIM6_CNT_UIFCPY EQU 0x80000000 ; UIF Copy
TIM6_CNT_UIFCPY_ofs EQU 31
TIM6_CNT_UIFCPY_len EQU 1
; TIM6_PSC fields:
TIM6_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM6_PSC_PSC_ofs EQU 0
TIM6_PSC_PSC_len EQU 16
; TIM6_ARR fields:
TIM6_ARR_ARR EQU 0x0000ffff ; Low Auto-reload value
TIM6_ARR_ARR_ofs EQU 0
TIM6_ARR_ARR_len EQU 16
; ---- TIM7 --------------------------------------------------
; Desc: None
; TIM7 base address:
TIM7_BASE EQU 0x40001400
; TIM7 registers:
; ---- DAC ---------------------------------------------------
; Desc: Digital-to-analog converter
; DAC base address:
DAC_BASE EQU 0x40007400
; DAC registers:
DAC_CR EQU (DAC_BASE + 0x0) ; control register
DAC_SWTRIGR EQU (DAC_BASE + 0x4) ; software trigger register
DAC_DHR12R1 EQU (DAC_BASE + 0x8) ; channel1 12-bit right-aligned data holding register
DAC_DHR12L1 EQU (DAC_BASE + 0xc) ; channel1 12-bit left aligned data holding register
DAC_DHR8R1 EQU (DAC_BASE + 0x10) ; channel1 8-bit right aligned data holding register
DAC_DHR12R2 EQU (DAC_BASE + 0x14) ; channel2 12-bit right aligned data holding register
DAC_DHR12L2 EQU (DAC_BASE + 0x18) ; channel2 12-bit left aligned data holding register
DAC_DHR8R2 EQU (DAC_BASE + 0x1c) ; channel2 8-bit right-aligned data holding register
DAC_DHR12RD EQU (DAC_BASE + 0x20) ; Dual DAC 12-bit right-aligned data holding register
DAC_DHR12LD EQU (DAC_BASE + 0x24) ; DUAL DAC 12-bit left aligned data holding register
DAC_DHR8RD EQU (DAC_BASE + 0x28) ; DUAL DAC 8-bit right aligned data holding register
DAC_DOR1 EQU (DAC_BASE + 0x2c) ; channel1 data output register
DAC_DOR2 EQU (DAC_BASE + 0x30) ; channel2 data output register
DAC_SR EQU (DAC_BASE + 0x34) ; status register
; DAC_CR fields:
DAC_CR_DMAUDRIE2 EQU 0x20000000 ; DAC channel2 DMA underrun interrupt enable
DAC_CR_DMAUDRIE2_ofs EQU 29
DAC_CR_DMAUDRIE2_len EQU 1
DAC_CR_DMAEN2 EQU 0x10000000 ; DAC channel2 DMA enable
DAC_CR_DMAEN2_ofs EQU 28
DAC_CR_DMAEN2_len EQU 1
DAC_CR_MAMP2 EQU 0x0f000000 ; DAC channel2 mask/amplitude selector
DAC_CR_MAMP2_ofs EQU 24
DAC_CR_MAMP2_len EQU 4
DAC_CR_WAVE2 EQU 0x00c00000 ; DAC channel2 noise/triangle wave generation enable
DAC_CR_WAVE2_ofs EQU 22
DAC_CR_WAVE2_len EQU 2
DAC_CR_TSEL2 EQU 0x00380000 ; DAC channel2 trigger selection
DAC_CR_TSEL2_ofs EQU 19
DAC_CR_TSEL2_len EQU 3
DAC_CR_TEN2 EQU 0x00040000 ; DAC channel2 trigger enable
DAC_CR_TEN2_ofs EQU 18
DAC_CR_TEN2_len EQU 1
DAC_CR_BOFF2 EQU 0x00020000 ; DAC channel2 output buffer disable
DAC_CR_BOFF2_ofs EQU 17
DAC_CR_BOFF2_len EQU 1
DAC_CR_EN2 EQU 0x00010000 ; DAC channel2 enable
DAC_CR_EN2_ofs EQU 16
DAC_CR_EN2_len EQU 1
DAC_CR_DMAUDRIE1 EQU 0x00002000 ; DAC channel1 DMA Underrun Interrupt enable
DAC_CR_DMAUDRIE1_ofs EQU 13
DAC_CR_DMAUDRIE1_len EQU 1
DAC_CR_DMAEN1 EQU 0x00001000 ; DAC channel1 DMA enable
DAC_CR_DMAEN1_ofs EQU 12
DAC_CR_DMAEN1_len EQU 1
DAC_CR_MAMP1 EQU 0x00000f00 ; DAC channel1 mask/amplitude selector
DAC_CR_MAMP1_ofs EQU 8
DAC_CR_MAMP1_len EQU 4
DAC_CR_WAVE1 EQU 0x000000c0 ; DAC channel1 noise/triangle wave generation enable
DAC_CR_WAVE1_ofs EQU 6
DAC_CR_WAVE1_len EQU 2
DAC_CR_TSEL1 EQU 0x00000038 ; DAC channel1 trigger selection
DAC_CR_TSEL1_ofs EQU 3
DAC_CR_TSEL1_len EQU 3
DAC_CR_TEN1 EQU 0x00000004 ; DAC channel1 trigger enable
DAC_CR_TEN1_ofs EQU 2
DAC_CR_TEN1_len EQU 1
DAC_CR_BOFF1 EQU 0x00000002 ; DAC channel1 output buffer disable
DAC_CR_BOFF1_ofs EQU 1
DAC_CR_BOFF1_len EQU 1
DAC_CR_EN1 EQU 0x00000001 ; DAC channel1 enable
DAC_CR_EN1_ofs EQU 0
DAC_CR_EN1_len EQU 1
; DAC_SWTRIGR fields:
DAC_SWTRIGR_SWTRIG2 EQU 0x00000002 ; DAC channel2 software trigger
DAC_SWTRIGR_SWTRIG2_ofs EQU 1
DAC_SWTRIGR_SWTRIG2_len EQU 1
DAC_SWTRIGR_SWTRIG1 EQU 0x00000001 ; DAC channel1 software trigger
DAC_SWTRIGR_SWTRIG1_ofs EQU 0
DAC_SWTRIGR_SWTRIG1_len EQU 1
; DAC_DHR12R1 fields:
DAC_DHR12R1_DACC1DHR EQU 0x00000fff ; DAC channel1 12-bit right-aligned data
DAC_DHR12R1_DACC1DHR_ofs EQU 0
DAC_DHR12R1_DACC1DHR_len EQU 12
; DAC_DHR12L1 fields:
DAC_DHR12L1_DACC1DHR EQU 0x0000fff0 ; DAC channel1 12-bit left-aligned data
DAC_DHR12L1_DACC1DHR_ofs EQU 4
DAC_DHR12L1_DACC1DHR_len EQU 12
; DAC_DHR8R1 fields:
DAC_DHR8R1_DACC1DHR EQU 0x000000ff ; DAC channel1 8-bit right-aligned data
DAC_DHR8R1_DACC1DHR_ofs EQU 0
DAC_DHR8R1_DACC1DHR_len EQU 8
; DAC_DHR12R2 fields:
DAC_DHR12R2_DACC2DHR EQU 0x00000fff ; DAC channel2 12-bit right-aligned data
DAC_DHR12R2_DACC2DHR_ofs EQU 0
DAC_DHR12R2_DACC2DHR_len EQU 12
; DAC_DHR12L2 fields:
DAC_DHR12L2_DACC2DHR EQU 0x0000fff0 ; DAC channel2 12-bit left-aligned data
DAC_DHR12L2_DACC2DHR_ofs EQU 4
DAC_DHR12L2_DACC2DHR_len EQU 12
; DAC_DHR8R2 fields:
DAC_DHR8R2_DACC2DHR EQU 0x000000ff ; DAC channel2 8-bit right-aligned data
DAC_DHR8R2_DACC2DHR_ofs EQU 0
DAC_DHR8R2_DACC2DHR_len EQU 8
; DAC_DHR12RD fields:
DAC_DHR12RD_DACC2DHR EQU 0x0fff0000 ; DAC channel2 12-bit right-aligned data
DAC_DHR12RD_DACC2DHR_ofs EQU 16
DAC_DHR12RD_DACC2DHR_len EQU 12
DAC_DHR12RD_DACC1DHR EQU 0x00000fff ; DAC channel1 12-bit right-aligned data
DAC_DHR12RD_DACC1DHR_ofs EQU 0
DAC_DHR12RD_DACC1DHR_len EQU 12
; DAC_DHR12LD fields:
DAC_DHR12LD_DACC2DHR EQU 0xfff00000 ; DAC channel2 12-bit left-aligned data
DAC_DHR12LD_DACC2DHR_ofs EQU 20
DAC_DHR12LD_DACC2DHR_len EQU 12
DAC_DHR12LD_DACC1DHR EQU 0x0000fff0 ; DAC channel1 12-bit left-aligned data
DAC_DHR12LD_DACC1DHR_ofs EQU 4
DAC_DHR12LD_DACC1DHR_len EQU 12
; DAC_DHR8RD fields:
DAC_DHR8RD_DACC2DHR EQU 0x0000ff00 ; DAC channel2 8-bit right-aligned data
DAC_DHR8RD_DACC2DHR_ofs EQU 8
DAC_DHR8RD_DACC2DHR_len EQU 8
DAC_DHR8RD_DACC1DHR EQU 0x000000ff ; DAC channel1 8-bit right-aligned data
DAC_DHR8RD_DACC1DHR_ofs EQU 0
DAC_DHR8RD_DACC1DHR_len EQU 8
; DAC_DOR1 fields:
DAC_DOR1_DACC1DOR EQU 0x00000fff ; DAC channel1 data output
DAC_DOR1_DACC1DOR_ofs EQU 0
DAC_DOR1_DACC1DOR_len EQU 12
; DAC_DOR2 fields:
DAC_DOR2_DACC2DOR EQU 0x00000fff ; DAC channel2 data output
DAC_DOR2_DACC2DOR_ofs EQU 0
DAC_DOR2_DACC2DOR_len EQU 12
; DAC_SR fields:
DAC_SR_DMAUDR2 EQU 0x20000000 ; DAC channel2 DMA underrun flag
DAC_SR_DMAUDR2_ofs EQU 29
DAC_SR_DMAUDR2_len EQU 1
DAC_SR_DMAUDR1 EQU 0x00002000 ; DAC channel1 DMA underrun flag
DAC_SR_DMAUDR1_ofs EQU 13
DAC_SR_DMAUDR1_len EQU 1
; ---- NVIC --------------------------------------------------
; Desc: Nested Vectored Interrupt Controller
; NVIC base address:
NVIC_BASE EQU 0xe000e000
; NVIC registers:
NVIC_ICTR EQU (NVIC_BASE + 0x4) ; Interrupt Controller Type Register
NVIC_STIR EQU (NVIC_BASE + 0xf00) ; Software Triggered Interrupt Register
NVIC_ISER0 EQU (NVIC_BASE + 0x100) ; Interrupt Set-Enable Register
NVIC_ISER1 EQU (NVIC_BASE + 0x104) ; Interrupt Set-Enable Register
NVIC_ISER2 EQU (NVIC_BASE + 0x108) ; Interrupt Set-Enable Register
NVIC_ICER0 EQU (NVIC_BASE + 0x180) ; Interrupt Clear-Enable Register
NVIC_ICER1 EQU (NVIC_BASE + 0x184) ; Interrupt Clear-Enable Register
NVIC_ICER2 EQU (NVIC_BASE + 0x188) ; Interrupt Clear-Enable Register
NVIC_ISPR0 EQU (NVIC_BASE + 0x200) ; Interrupt Set-Pending Register
NVIC_ISPR1 EQU (NVIC_BASE + 0x204) ; Interrupt Set-Pending Register
NVIC_ISPR2 EQU (NVIC_BASE + 0x208) ; Interrupt Set-Pending Register
NVIC_ICPR0 EQU (NVIC_BASE + 0x280) ; Interrupt Clear-Pending Register
NVIC_ICPR1 EQU (NVIC_BASE + 0x284) ; Interrupt Clear-Pending Register
NVIC_ICPR2 EQU (NVIC_BASE + 0x288) ; Interrupt Clear-Pending Register
NVIC_IABR0 EQU (NVIC_BASE + 0x300) ; Interrupt Active Bit Register
NVIC_IABR1 EQU (NVIC_BASE + 0x304) ; Interrupt Active Bit Register
NVIC_IABR2 EQU (NVIC_BASE + 0x308) ; Interrupt Active Bit Register
NVIC_IPR0 EQU (NVIC_BASE + 0x400) ; Interrupt Priority Register
NVIC_IPR1 EQU (NVIC_BASE + 0x404) ; Interrupt Priority Register
NVIC_IPR2 EQU (NVIC_BASE + 0x408) ; Interrupt Priority Register
NVIC_IPR3 EQU (NVIC_BASE + 0x40c) ; Interrupt Priority Register
NVIC_IPR4 EQU (NVIC_BASE + 0x410) ; Interrupt Priority Register
NVIC_IPR5 EQU (NVIC_BASE + 0x414) ; Interrupt Priority Register
NVIC_IPR6 EQU (NVIC_BASE + 0x418) ; Interrupt Priority Register
NVIC_IPR7 EQU (NVIC_BASE + 0x41c) ; Interrupt Priority Register
NVIC_IPR8 EQU (NVIC_BASE + 0x420) ; Interrupt Priority Register
NVIC_IPR9 EQU (NVIC_BASE + 0x424) ; Interrupt Priority Register
NVIC_IPR10 EQU (NVIC_BASE + 0x428) ; Interrupt Priority Register
NVIC_IPR11 EQU (NVIC_BASE + 0x42c) ; Interrupt Priority Register
NVIC_IPR12 EQU (NVIC_BASE + 0x430) ; Interrupt Priority Register
NVIC_IPR13 EQU (NVIC_BASE + 0x434) ; Interrupt Priority Register
NVIC_IPR14 EQU (NVIC_BASE + 0x438) ; Interrupt Priority Register
NVIC_IPR15 EQU (NVIC_BASE + 0x43c) ; Interrupt Priority Register
NVIC_IPR16 EQU (NVIC_BASE + 0x440) ; Interrupt Priority Register
NVIC_IPR17 EQU (NVIC_BASE + 0x444) ; Interrupt Priority Register
NVIC_IPR18 EQU (NVIC_BASE + 0x448) ; Interrupt Priority Register
NVIC_IPR19 EQU (NVIC_BASE + 0x44c) ; Interrupt Priority Register
NVIC_IPR20 EQU (NVIC_BASE + 0x450) ; Interrupt Priority Register
; NVIC_ICTR fields:
NVIC_ICTR_INTLINESNUM EQU 0x0000000f ; Total number of interrupt lines in groups
NVIC_ICTR_INTLINESNUM_ofs EQU 0
NVIC_ICTR_INTLINESNUM_len EQU 4
; NVIC_STIR fields:
NVIC_STIR_INTID EQU 0x000001ff ; interrupt to be triggered
NVIC_STIR_INTID_ofs EQU 0
NVIC_STIR_INTID_len EQU 9
; NVIC_ISERx fields:
NVIC_ISERx_SETENA EQU 0xffffffff ; SETENA
NVIC_ISERx_SETENA_ofs EQU 0
NVIC_ISERx_SETENA_len EQU 32
; NVIC_ICERx fields:
NVIC_ICERx_CLRENA EQU 0xffffffff ; CLRENA
NVIC_ICERx_CLRENA_ofs EQU 0
NVIC_ICERx_CLRENA_len EQU 32
; NVIC_ISPR0 fields:
NVIC_ISPRx_SETPEND EQU 0xffffffff ; SETPEND
NVIC_ISPRx_SETPEND_ofs EQU 0
NVIC_ISPRx_SETPEND_len EQU 32
; NVIC_ICPRx fields:
NVIC_ICPRx_CLRPEND EQU 0xffffffff ; CLRPEND
NVIC_ICPRx_CLRPEND_ofs EQU 0
NVIC_ICPRx_CLRPEND_len EQU 32
; NVIC_IABRx fields:
NVIC_IABRx_ACTIVE EQU 0xffffffff ; ACTIVE
NVIC_IABRx_ACTIVE_ofs EQU 0
NVIC_IABRx_ACTIVE_len EQU 32
; NVIC_IPRx fields:
NVIC_IPRx_IPR_N0 EQU 0x000000ff ; IPR_N0
NVIC_IPRx_IPR_N0_ofs EQU 0
NVIC_IPRx_IPR_N0_len EQU 8
NVIC_IPRx_IPR_N1 EQU 0x0000ff00 ; IPR_N1
NVIC_IPRx_IPR_N1_ofs EQU 8
NVIC_IPRx_IPR_N1_len EQU 8
NVIC_IPRx_IPR_N2 EQU 0x00ff0000 ; IPR_N2
NVIC_IPRx_IPR_N2_ofs EQU 16
NVIC_IPRx_IPR_N2_len EQU 8
NVIC_IPRx_IPR_N3 EQU 0xff000000 ; IPR_N3
NVIC_IPRx_IPR_N3_ofs EQU 24
NVIC_IPRx_IPR_N3_len EQU 8
; ---- FPU ---------------------------------------------------
; Desc: Floting point unit
; FPU base address:
FPU_BASE EQU 0xe000ed88
; FPU registers:
FPU_CPACR EQU (FPU_BASE + 0x0) ; Coprocessor Access Control Register
FPU_FPCCR EQU (FPU_BASE + 0x1ac) ; FP Context Control Register
FPU_FPCAR EQU (FPU_BASE + 0x1b0) ; FP Context Address Register
FPU_FPDSCR EQU (FPU_BASE + 0x1b4) ; FP Default Status Control Register
FPU_MVFR0 EQU (FPU_BASE + 0x1b8) ; Media and VFP Feature Register 0
FPU_MVFR1 EQU (FPU_BASE + 0x1bc) ; Media and VFP Feature Register 1
; FPU_CPACR fields:
FPU_CPACR_CP0 EQU 0x00000001 ; Access privileges for coprocessor 0
FPU_CPACR_CP0_ofs EQU 0
FPU_CPACR_CP0_len EQU 1
FPU_CPACR_CP1 EQU 0x00000004 ; Access privileges for coprocessor 1
FPU_CPACR_CP1_ofs EQU 2
FPU_CPACR_CP1_len EQU 1
FPU_CPACR_CP2 EQU 0x00000010 ; Access privileges for coprocessor 2
FPU_CPACR_CP2_ofs EQU 4
FPU_CPACR_CP2_len EQU 1
FPU_CPACR_CP3 EQU 0x00000040 ; Access privileges for coprocessor 3
FPU_CPACR_CP3_ofs EQU 6
FPU_CPACR_CP3_len EQU 1
FPU_CPACR_CP4 EQU 0x00000100 ; Access privileges for coprocessor 4
FPU_CPACR_CP4_ofs EQU 8
FPU_CPACR_CP4_len EQU 1
FPU_CPACR_CP5 EQU 0x00000400 ; Access privileges for coprocessor 5
FPU_CPACR_CP5_ofs EQU 10
FPU_CPACR_CP5_len EQU 1
FPU_CPACR_CP6 EQU 0x00003000 ; Access privileges for coprocessor 6
FPU_CPACR_CP6_ofs EQU 12
FPU_CPACR_CP6_len EQU 2
FPU_CPACR_CP7 EQU 0x00004000 ; Access privileges for coprocessor 7
FPU_CPACR_CP7_ofs EQU 14
FPU_CPACR_CP7_len EQU 1
FPU_CPACR_CP10 EQU 0x00100000 ; Access privileges for coprocessor 10
FPU_CPACR_CP10_ofs EQU 20
FPU_CPACR_CP10_len EQU 1
FPU_CPACR_CP11 EQU 0x00400000 ; Access privileges for coprocessor 11
FPU_CPACR_CP11_ofs EQU 22
FPU_CPACR_CP11_len EQU 1
; FPU_FPCCR fields:
FPU_FPCCR_LSPACT EQU 0x00000001 ; LSPACT
FPU_FPCCR_LSPACT_ofs EQU 0
FPU_FPCCR_LSPACT_len EQU 1
FPU_FPCCR_USER EQU 0x00000002 ; USER
FPU_FPCCR_USER_ofs EQU 1
FPU_FPCCR_USER_len EQU 1
FPU_FPCCR_THREAD EQU 0x00000008 ; THREAD
FPU_FPCCR_THREAD_ofs EQU 3
FPU_FPCCR_THREAD_len EQU 1
FPU_FPCCR_HFRDY EQU 0x00000010 ; HFRDY
FPU_FPCCR_HFRDY_ofs EQU 4
FPU_FPCCR_HFRDY_len EQU 1
FPU_FPCCR_MMRDY EQU 0x00000020 ; MMRDY
FPU_FPCCR_MMRDY_ofs EQU 5
FPU_FPCCR_MMRDY_len EQU 1
FPU_FPCCR_BFRDY EQU 0x00000040 ; BFRDY
FPU_FPCCR_BFRDY_ofs EQU 6
FPU_FPCCR_BFRDY_len EQU 1
FPU_FPCCR_MONRDY EQU 0x00000100 ; MONRDY
FPU_FPCCR_MONRDY_ofs EQU 8
FPU_FPCCR_MONRDY_len EQU 1
FPU_FPCCR_LSPEN EQU 0x40000000 ; LSPEN
FPU_FPCCR_LSPEN_ofs EQU 30
FPU_FPCCR_LSPEN_len EQU 1
FPU_FPCCR_ASPEN EQU 0x80000000 ; ASPEN
FPU_FPCCR_ASPEN_ofs EQU 31
FPU_FPCCR_ASPEN_len EQU 1
; FPU_FPCAR fields:
FPU_FPCAR_ADDRESS EQU 0xfffffff8 ; ADDRESS
FPU_FPCAR_ADDRESS_ofs EQU 3
FPU_FPCAR_ADDRESS_len EQU 29
; FPU_FPDSCR fields:
FPU_FPDSCR_RMode EQU 0x00c00000 ; RMode
FPU_FPDSCR_RMode_ofs EQU 22
FPU_FPDSCR_RMode_len EQU 2
FPU_FPDSCR_FZ EQU 0x01000000 ; FZ
FPU_FPDSCR_FZ_ofs EQU 24
FPU_FPDSCR_FZ_len EQU 1
FPU_FPDSCR_DN EQU 0x02000000 ; DN
FPU_FPDSCR_DN_ofs EQU 25
FPU_FPDSCR_DN_len EQU 1
FPU_FPDSCR_AHP EQU 0x04000000 ; AHP
FPU_FPDSCR_AHP_ofs EQU 26
FPU_FPDSCR_AHP_len EQU 1
; FPU_MVFR0 fields:
FPU_MVFR0_A_SIMD EQU 0x0000000f ; A_SIMD registers
FPU_MVFR0_A_SIMD_ofs EQU 0
FPU_MVFR0_A_SIMD_len EQU 4
FPU_MVFR0_Single_precision EQU 0x000000f0 ; Single_precision
FPU_MVFR0_Single_precision_ofs EQU 4
FPU_MVFR0_Single_precision_len EQU 4
FPU_MVFR0_Double_precision EQU 0x00000f00 ; Double_precision
FPU_MVFR0_Double_precision_ofs EQU 8
FPU_MVFR0_Double_precision_len EQU 4
FPU_MVFR0_FP_exception_trapping EQU 0x0000f000 ; FP exception trapping
FPU_MVFR0_FP_exception_trapping_ofs EQU 12
FPU_MVFR0_FP_exception_trapping_len EQU 4
FPU_MVFR0_Divide EQU 0x000f0000 ; Divide
FPU_MVFR0_Divide_ofs EQU 16
FPU_MVFR0_Divide_len EQU 4
FPU_MVFR0_Square_root EQU 0x00f00000 ; Square root
FPU_MVFR0_Square_root_ofs EQU 20
FPU_MVFR0_Square_root_len EQU 4
FPU_MVFR0_Short_vectors EQU 0x0f000000 ; Short vectors
FPU_MVFR0_Short_vectors_ofs EQU 24
FPU_MVFR0_Short_vectors_len EQU 4
FPU_MVFR0_FP_rounding_modes EQU 0xf0000000 ; FP rounding modes
FPU_MVFR0_FP_rounding_modes_ofs EQU 28
FPU_MVFR0_FP_rounding_modes_len EQU 4
; FPU_MVFR1 fields:
FPU_MVFR1_FtZ_mode EQU 0x0000000f ; FtZ mode
FPU_MVFR1_FtZ_mode_ofs EQU 0
FPU_MVFR1_FtZ_mode_len EQU 4
FPU_MVFR1_D_NaN_mode EQU 0x000000f0 ; D_NaN mode
FPU_MVFR1_D_NaN_mode_ofs EQU 4
FPU_MVFR1_D_NaN_mode_len EQU 4
FPU_MVFR1_FP_HPFP EQU 0x0f000000 ; FP HPFP
FPU_MVFR1_FP_HPFP_ofs EQU 24
FPU_MVFR1_FP_HPFP_len EQU 4
FPU_MVFR1_FP_fused_MAC EQU 0xf0000000 ; FP fused MAC
FPU_MVFR1_FP_fused_MAC_ofs EQU 28
FPU_MVFR1_FP_fused_MAC_len EQU 4
; ---- DBGMCU ------------------------------------------------
; Desc: Debug support
; DBGMCU base address:
DBGMCU_BASE EQU 0xe0042000
; DBGMCU registers:
DBGMCU_IDCODE EQU (DBGMCU_BASE + 0x0) ; MCU Device ID Code Register
DBGMCU_CR EQU (DBGMCU_BASE + 0x4) ; Debug MCU Configuration Register
DBGMCU_APB1FZ EQU (DBGMCU_BASE + 0x8) ; APB Low Freeze Register
DBGMCU_APB2FZ EQU (DBGMCU_BASE + 0xc) ; APB High Freeze Register
; DBGMCU_IDCODE fields:
DBGMCU_IDCODE_DEV_ID EQU 0x00000fff ; Device Identifier
DBGMCU_IDCODE_DEV_ID_ofs EQU 0
DBGMCU_IDCODE_DEV_ID_len EQU 12
DBGMCU_IDCODE_REV_ID EQU 0xffff0000 ; Revision Identifier
DBGMCU_IDCODE_REV_ID_ofs EQU 16
DBGMCU_IDCODE_REV_ID_len EQU 16
; DBGMCU_CR fields:
DBGMCU_CR_DBG_SLEEP EQU 0x00000001 ; Debug Sleep mode
DBGMCU_CR_DBG_SLEEP_ofs EQU 0
DBGMCU_CR_DBG_SLEEP_len EQU 1
DBGMCU_CR_DBG_STOP EQU 0x00000002 ; Debug Stop Mode
DBGMCU_CR_DBG_STOP_ofs EQU 1
DBGMCU_CR_DBG_STOP_len EQU 1
DBGMCU_CR_DBG_STANDBY EQU 0x00000004 ; Debug Standby Mode
DBGMCU_CR_DBG_STANDBY_ofs EQU 2
DBGMCU_CR_DBG_STANDBY_len EQU 1
DBGMCU_CR_TRACE_IOEN EQU 0x00000020 ; Trace pin assignment control
DBGMCU_CR_TRACE_IOEN_ofs EQU 5
DBGMCU_CR_TRACE_IOEN_len EQU 1
DBGMCU_CR_TRACE_MODE EQU 0x000000c0 ; Trace pin assignment control
DBGMCU_CR_TRACE_MODE_ofs EQU 6
DBGMCU_CR_TRACE_MODE_len EQU 2
; DBGMCU_APB1FZ fields:
DBGMCU_APB1FZ_DBG_TIM2_STOP EQU 0x00000001 ; Debug Timer 2 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM2_STOP_ofs EQU 0
DBGMCU_APB1FZ_DBG_TIM2_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM3_STOP EQU 0x00000002 ; Debug Timer 3 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM3_STOP_ofs EQU 1
DBGMCU_APB1FZ_DBG_TIM3_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM4_STOP EQU 0x00000004 ; Debug Timer 4 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM4_STOP_ofs EQU 2
DBGMCU_APB1FZ_DBG_TIM4_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM5_STOP EQU 0x00000008 ; Debug Timer 5 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM5_STOP_ofs EQU 3
DBGMCU_APB1FZ_DBG_TIM5_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM6_STOP EQU 0x00000010 ; Debug Timer 6 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM6_STOP_ofs EQU 4
DBGMCU_APB1FZ_DBG_TIM6_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM7_STOP EQU 0x00000020 ; Debug Timer 7 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM7_STOP_ofs EQU 5
DBGMCU_APB1FZ_DBG_TIM7_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM12_STOP EQU 0x00000040 ; Debug Timer 12 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM12_STOP_ofs EQU 6
DBGMCU_APB1FZ_DBG_TIM12_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM13_STOP EQU 0x00000080 ; Debug Timer 13 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM13_STOP_ofs EQU 7
DBGMCU_APB1FZ_DBG_TIM13_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIMER14_STOP EQU 0x00000100 ; Debug Timer 14 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIMER14_STOP_ofs EQU 8
DBGMCU_APB1FZ_DBG_TIMER14_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM18_STOP EQU 0x00000200 ; Debug Timer 18 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM18_STOP_ofs EQU 9
DBGMCU_APB1FZ_DBG_TIM18_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_RTC_STOP EQU 0x00000400 ; Debug RTC stopped when Core is halted
DBGMCU_APB1FZ_DBG_RTC_STOP_ofs EQU 10
DBGMCU_APB1FZ_DBG_RTC_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_WWDG_STOP EQU 0x00000800 ; Debug Window Wachdog stopped when Core is halted
DBGMCU_APB1FZ_DBG_WWDG_STOP_ofs EQU 11
DBGMCU_APB1FZ_DBG_WWDG_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_IWDG_STOP EQU 0x00001000 ; Debug Independent Wachdog stopped when Core is halted
DBGMCU_APB1FZ_DBG_IWDG_STOP_ofs EQU 12
DBGMCU_APB1FZ_DBG_IWDG_STOP_len EQU 1
DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT EQU 0x00200000 ; SMBUS timeout mode stopped when Core is halted
DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT_ofs EQU 21
DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT_len EQU 1
DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT EQU 0x00400000 ; SMBUS timeout mode stopped when Core is halted
DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT_ofs EQU 22
DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT_len EQU 1
DBGMCU_APB1FZ_DBG_CAN_STOP EQU 0x02000000 ; Debug CAN stopped when core is halted
DBGMCU_APB1FZ_DBG_CAN_STOP_ofs EQU 25
DBGMCU_APB1FZ_DBG_CAN_STOP_len EQU 1
; DBGMCU_APB2FZ fields:
DBGMCU_APB2FZ_DBG_TIM15_STOP EQU 0x00000004 ; Debug Timer 15 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM15_STOP_ofs EQU 2
DBGMCU_APB2FZ_DBG_TIM15_STOP_len EQU 1
DBGMCU_APB2FZ_DBG_TIM16_STOP EQU 0x00000008 ; Debug Timer 16 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM16_STOP_ofs EQU 3
DBGMCU_APB2FZ_DBG_TIM16_STOP_len EQU 1
DBGMCU_APB2FZ_DBG_TIM17_STO EQU 0x00000010 ; Debug Timer 17 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM17_STO_ofs EQU 4
DBGMCU_APB2FZ_DBG_TIM17_STO_len EQU 1
DBGMCU_APB2FZ_DBG_TIM19_STOP EQU 0x00000020 ; Debug Timer 19 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM19_STOP_ofs EQU 5
DBGMCU_APB2FZ_DBG_TIM19_STOP_len EQU 1
; ---- TIM1 --------------------------------------------------
; Desc: Advanced timer
; TIM1 base address:
TIM1_BASE EQU 0x40012c00
; TIM1 registers:
TIM1_CR1 EQU (TIM1_BASE + 0x0) ; control register 1
TIM1_CR2 EQU (TIM1_BASE + 0x4) ; control register 2
TIM1_SMCR EQU (TIM1_BASE + 0x8) ; slave mode control register
TIM1_DIER EQU (TIM1_BASE + 0xc) ; DMA/Interrupt enable register
TIM1_SR EQU (TIM1_BASE + 0x10) ; status register
TIM1_EGR EQU (TIM1_BASE + 0x14) ; event generation register
TIM1_CCMR1_Output EQU (TIM1_BASE + 0x18) ; capture/compare mode register (output mode)
TIM1_CCMR1_Input EQU (TIM1_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM1_CCMR2_Output EQU (TIM1_BASE + 0x1c) ; capture/compare mode register (output mode)
TIM1_CCMR2_Input EQU (TIM1_BASE + 0x1c) ; capture/compare mode register 2 (input mode)
TIM1_CCER EQU (TIM1_BASE + 0x20) ; capture/compare enable register
TIM1_CNT EQU (TIM1_BASE + 0x24) ; counter
TIM1_PSC EQU (TIM1_BASE + 0x28) ; prescaler
TIM1_ARR EQU (TIM1_BASE + 0x2c) ; auto-reload register
TIM1_RCR EQU (TIM1_BASE + 0x30) ; repetition counter register
TIM1_CCR1 EQU (TIM1_BASE + 0x34) ; capture/compare register 1
TIM1_CCR2 EQU (TIM1_BASE + 0x38) ; capture/compare register 2
TIM1_CCR3 EQU (TIM1_BASE + 0x3c) ; capture/compare register 3
TIM1_CCR4 EQU (TIM1_BASE + 0x40) ; capture/compare register 4
TIM1_BDTR EQU (TIM1_BASE + 0x44) ; break and dead-time register
TIM1_DCR EQU (TIM1_BASE + 0x48) ; DMA control register
TIM1_DMAR EQU (TIM1_BASE + 0x4c) ; DMA address for full transfer
TIM1_CCMR3_Output EQU (TIM1_BASE + 0x54) ; capture/compare mode register 3 (output mode)
TIM1_CCR5 EQU (TIM1_BASE + 0x58) ; capture/compare register 5
TIM1_CCR6 EQU (TIM1_BASE + 0x5c) ; capture/compare register 6
TIM1_OR EQU (TIM1_BASE + 0x60) ; option registers
; TIM1_CR1 fields:
TIM1_CR1_CEN EQU 0x00000001 ; Counter enable
TIM1_CR1_CEN_ofs EQU 0
TIM1_CR1_CEN_len EQU 1
TIM1_CR1_UDIS EQU 0x00000002 ; Update disable
TIM1_CR1_UDIS_ofs EQU 1
TIM1_CR1_UDIS_len EQU 1
TIM1_CR1_URS EQU 0x00000004 ; Update request source
TIM1_CR1_URS_ofs EQU 2
TIM1_CR1_URS_len EQU 1
TIM1_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM1_CR1_OPM_ofs EQU 3
TIM1_CR1_OPM_len EQU 1
TIM1_CR1_DIR EQU 0x00000010 ; Direction
TIM1_CR1_DIR_ofs EQU 4
TIM1_CR1_DIR_len EQU 1
TIM1_CR1_CMS EQU 0x00000060 ; Center-aligned mode selection
TIM1_CR1_CMS_ofs EQU 5
TIM1_CR1_CMS_len EQU 2
TIM1_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM1_CR1_ARPE_ofs EQU 7
TIM1_CR1_ARPE_len EQU 1
TIM1_CR1_CKD EQU 0x00000300 ; Clock division
TIM1_CR1_CKD_ofs EQU 8
TIM1_CR1_CKD_len EQU 2
TIM1_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM1_CR1_UIFREMAP_ofs EQU 11
TIM1_CR1_UIFREMAP_len EQU 1
; TIM1_CR2 fields:
TIM1_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM1_CR2_CCPC_ofs EQU 0
TIM1_CR2_CCPC_len EQU 1
TIM1_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM1_CR2_CCUS_ofs EQU 2
TIM1_CR2_CCUS_len EQU 1
TIM1_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM1_CR2_CCDS_ofs EQU 3
TIM1_CR2_CCDS_len EQU 1
TIM1_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM1_CR2_MMS_ofs EQU 4
TIM1_CR2_MMS_len EQU 3
TIM1_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM1_CR2_TI1S_ofs EQU 7
TIM1_CR2_TI1S_len EQU 1
TIM1_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM1_CR2_OIS1_ofs EQU 8
TIM1_CR2_OIS1_len EQU 1
TIM1_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM1_CR2_OIS1N_ofs EQU 9
TIM1_CR2_OIS1N_len EQU 1
TIM1_CR2_OIS2 EQU 0x00000400 ; Output Idle state 2
TIM1_CR2_OIS2_ofs EQU 10
TIM1_CR2_OIS2_len EQU 1
TIM1_CR2_OIS2N EQU 0x00000800 ; Output Idle state 2
TIM1_CR2_OIS2N_ofs EQU 11
TIM1_CR2_OIS2N_len EQU 1
TIM1_CR2_OIS3 EQU 0x00001000 ; Output Idle state 3
TIM1_CR2_OIS3_ofs EQU 12
TIM1_CR2_OIS3_len EQU 1
TIM1_CR2_OIS3N EQU 0x00002000 ; Output Idle state 3
TIM1_CR2_OIS3N_ofs EQU 13
TIM1_CR2_OIS3N_len EQU 1
TIM1_CR2_OIS4 EQU 0x00004000 ; Output Idle state 4
TIM1_CR2_OIS4_ofs EQU 14
TIM1_CR2_OIS4_len EQU 1
TIM1_CR2_OIS5 EQU 0x00010000 ; Output Idle state 5
TIM1_CR2_OIS5_ofs EQU 16
TIM1_CR2_OIS5_len EQU 1
TIM1_CR2_OIS6 EQU 0x00040000 ; Output Idle state 6
TIM1_CR2_OIS6_ofs EQU 18
TIM1_CR2_OIS6_len EQU 1
TIM1_CR2_MMS2 EQU 0x00f00000 ; Master mode selection 2
TIM1_CR2_MMS2_ofs EQU 20
TIM1_CR2_MMS2_len EQU 4
; TIM1_SMCR fields:
TIM1_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM1_SMCR_SMS_ofs EQU 0
TIM1_SMCR_SMS_len EQU 3
TIM1_SMCR_OCCS EQU 0x00000008 ; OCREF clear selection
TIM1_SMCR_OCCS_ofs EQU 3
TIM1_SMCR_OCCS_len EQU 1
TIM1_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM1_SMCR_TS_ofs EQU 4
TIM1_SMCR_TS_len EQU 3
TIM1_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM1_SMCR_MSM_ofs EQU 7
TIM1_SMCR_MSM_len EQU 1
TIM1_SMCR_ETF EQU 0x00000f00 ; External trigger filter
TIM1_SMCR_ETF_ofs EQU 8
TIM1_SMCR_ETF_len EQU 4
TIM1_SMCR_ETPS EQU 0x00003000 ; External trigger prescaler
TIM1_SMCR_ETPS_ofs EQU 12
TIM1_SMCR_ETPS_len EQU 2
TIM1_SMCR_ECE EQU 0x00004000 ; External clock enable
TIM1_SMCR_ECE_ofs EQU 14
TIM1_SMCR_ECE_len EQU 1
TIM1_SMCR_ETP EQU 0x00008000 ; External trigger polarity
TIM1_SMCR_ETP_ofs EQU 15
TIM1_SMCR_ETP_len EQU 1
TIM1_SMCR_SMS3 EQU 0x00010000 ; Slave mode selection bit 3
TIM1_SMCR_SMS3_ofs EQU 16
TIM1_SMCR_SMS3_len EQU 1
; TIM1_DIER fields:
TIM1_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM1_DIER_TDE_ofs EQU 14
TIM1_DIER_TDE_len EQU 1
TIM1_DIER_COMDE EQU 0x00002000 ; Reserved
TIM1_DIER_COMDE_ofs EQU 13
TIM1_DIER_COMDE_len EQU 1
TIM1_DIER_CC4DE EQU 0x00001000 ; Capture/Compare 4 DMA request enable
TIM1_DIER_CC4DE_ofs EQU 12
TIM1_DIER_CC4DE_len EQU 1
TIM1_DIER_CC3DE EQU 0x00000800 ; Capture/Compare 3 DMA request enable
TIM1_DIER_CC3DE_ofs EQU 11
TIM1_DIER_CC3DE_len EQU 1
TIM1_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM1_DIER_CC2DE_ofs EQU 10
TIM1_DIER_CC2DE_len EQU 1
TIM1_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM1_DIER_CC1DE_ofs EQU 9
TIM1_DIER_CC1DE_len EQU 1
TIM1_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM1_DIER_UDE_ofs EQU 8
TIM1_DIER_UDE_len EQU 1
TIM1_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM1_DIER_BIE_ofs EQU 7
TIM1_DIER_BIE_len EQU 1
TIM1_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM1_DIER_TIE_ofs EQU 6
TIM1_DIER_TIE_len EQU 1
TIM1_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM1_DIER_COMIE_ofs EQU 5
TIM1_DIER_COMIE_len EQU 1
TIM1_DIER_CC4IE EQU 0x00000010 ; Capture/Compare 4 interrupt enable
TIM1_DIER_CC4IE_ofs EQU 4
TIM1_DIER_CC4IE_len EQU 1
TIM1_DIER_CC3IE EQU 0x00000008 ; Capture/Compare 3 interrupt enable
TIM1_DIER_CC3IE_ofs EQU 3
TIM1_DIER_CC3IE_len EQU 1
TIM1_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM1_DIER_CC2IE_ofs EQU 2
TIM1_DIER_CC2IE_len EQU 1
TIM1_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM1_DIER_CC1IE_ofs EQU 1
TIM1_DIER_CC1IE_len EQU 1
TIM1_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM1_DIER_UIE_ofs EQU 0
TIM1_DIER_UIE_len EQU 1
; TIM1_SR fields:
TIM1_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM1_SR_UIF_ofs EQU 0
TIM1_SR_UIF_len EQU 1
TIM1_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM1_SR_CC1IF_ofs EQU 1
TIM1_SR_CC1IF_len EQU 1
TIM1_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM1_SR_CC2IF_ofs EQU 2
TIM1_SR_CC2IF_len EQU 1
TIM1_SR_CC3IF EQU 0x00000008 ; Capture/Compare 3 interrupt flag
TIM1_SR_CC3IF_ofs EQU 3
TIM1_SR_CC3IF_len EQU 1
TIM1_SR_CC4IF EQU 0x00000010 ; Capture/Compare 4 interrupt flag
TIM1_SR_CC4IF_ofs EQU 4
TIM1_SR_CC4IF_len EQU 1
TIM1_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM1_SR_COMIF_ofs EQU 5
TIM1_SR_COMIF_len EQU 1
TIM1_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM1_SR_TIF_ofs EQU 6
TIM1_SR_TIF_len EQU 1
TIM1_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM1_SR_BIF_ofs EQU 7
TIM1_SR_BIF_len EQU 1
TIM1_SR_B2IF EQU 0x00000100 ; Break 2 interrupt flag
TIM1_SR_B2IF_ofs EQU 8
TIM1_SR_B2IF_len EQU 1
TIM1_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM1_SR_CC1OF_ofs EQU 9
TIM1_SR_CC1OF_len EQU 1
TIM1_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM1_SR_CC2OF_ofs EQU 10
TIM1_SR_CC2OF_len EQU 1
TIM1_SR_CC3OF EQU 0x00000800 ; Capture/Compare 3 overcapture flag
TIM1_SR_CC3OF_ofs EQU 11
TIM1_SR_CC3OF_len EQU 1
TIM1_SR_CC4OF EQU 0x00001000 ; Capture/Compare 4 overcapture flag
TIM1_SR_CC4OF_ofs EQU 12
TIM1_SR_CC4OF_len EQU 1
TIM1_SR_C5IF EQU 0x00010000 ; Capture/Compare 5 interrupt flag
TIM1_SR_C5IF_ofs EQU 16
TIM1_SR_C5IF_len EQU 1
TIM1_SR_C6IF EQU 0x00020000 ; Capture/Compare 6 interrupt flag
TIM1_SR_C6IF_ofs EQU 17
TIM1_SR_C6IF_len EQU 1
; TIM1_EGR fields:
TIM1_EGR_UG EQU 0x00000001 ; Update generation
TIM1_EGR_UG_ofs EQU 0
TIM1_EGR_UG_len EQU 1
TIM1_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM1_EGR_CC1G_ofs EQU 1
TIM1_EGR_CC1G_len EQU 1
TIM1_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM1_EGR_CC2G_ofs EQU 2
TIM1_EGR_CC2G_len EQU 1
TIM1_EGR_CC3G EQU 0x00000008 ; Capture/compare 3 generation
TIM1_EGR_CC3G_ofs EQU 3
TIM1_EGR_CC3G_len EQU 1
TIM1_EGR_CC4G EQU 0x00000010 ; Capture/compare 4 generation
TIM1_EGR_CC4G_ofs EQU 4
TIM1_EGR_CC4G_len EQU 1
TIM1_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM1_EGR_COMG_ofs EQU 5
TIM1_EGR_COMG_len EQU 1
TIM1_EGR_TG EQU 0x00000040 ; Trigger generation
TIM1_EGR_TG_ofs EQU 6
TIM1_EGR_TG_len EQU 1
TIM1_EGR_BG EQU 0x00000080 ; Break generation
TIM1_EGR_BG_ofs EQU 7
TIM1_EGR_BG_len EQU 1
TIM1_EGR_B2G EQU 0x00000100 ; Break 2 generation
TIM1_EGR_B2G_ofs EQU 8
TIM1_EGR_B2G_len EQU 1
; TIM1_CCMR1_Output fields:
TIM1_CCMR1_Output_OC2CE EQU 0x00008000 ; Output Compare 2 clear enable
TIM1_CCMR1_Output_OC2CE_ofs EQU 15
TIM1_CCMR1_Output_OC2CE_len EQU 1
TIM1_CCMR1_Output_OC2M EQU 0x00007000 ; Output Compare 2 mode
TIM1_CCMR1_Output_OC2M_ofs EQU 12
TIM1_CCMR1_Output_OC2M_len EQU 3
TIM1_CCMR1_Output_OC2PE EQU 0x00000800 ; Output Compare 2 preload enable
TIM1_CCMR1_Output_OC2PE_ofs EQU 11
TIM1_CCMR1_Output_OC2PE_len EQU 1
TIM1_CCMR1_Output_OC2FE EQU 0x00000400 ; Output Compare 2 fast enable
TIM1_CCMR1_Output_OC2FE_ofs EQU 10
TIM1_CCMR1_Output_OC2FE_len EQU 1
TIM1_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM1_CCMR1_Output_CC2S_ofs EQU 8
TIM1_CCMR1_Output_CC2S_len EQU 2
TIM1_CCMR1_Output_OC1CE EQU 0x00000080 ; Output Compare 1 clear enable
TIM1_CCMR1_Output_OC1CE_ofs EQU 7
TIM1_CCMR1_Output_OC1CE_len EQU 1
TIM1_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM1_CCMR1_Output_OC1M_ofs EQU 4
TIM1_CCMR1_Output_OC1M_len EQU 3
TIM1_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM1_CCMR1_Output_OC1PE_ofs EQU 3
TIM1_CCMR1_Output_OC1PE_len EQU 1
TIM1_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM1_CCMR1_Output_OC1FE_ofs EQU 2
TIM1_CCMR1_Output_OC1FE_len EQU 1
TIM1_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM1_CCMR1_Output_CC1S_ofs EQU 0
TIM1_CCMR1_Output_CC1S_len EQU 2
TIM1_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode bit 3
TIM1_CCMR1_Output_OC1M_3_ofs EQU 16
TIM1_CCMR1_Output_OC1M_3_len EQU 1
TIM1_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output Compare 2 mode bit 3
TIM1_CCMR1_Output_OC2M_3_ofs EQU 24
TIM1_CCMR1_Output_OC2M_3_len EQU 1
; TIM1_CCMR1_Input fields:
TIM1_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM1_CCMR1_Input_IC2F_ofs EQU 12
TIM1_CCMR1_Input_IC2F_len EQU 4
TIM1_CCMR1_Input_IC2PCS EQU 0x00000c00 ; Input capture 2 prescaler
TIM1_CCMR1_Input_IC2PCS_ofs EQU 10
TIM1_CCMR1_Input_IC2PCS_len EQU 2
TIM1_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM1_CCMR1_Input_CC2S_ofs EQU 8
TIM1_CCMR1_Input_CC2S_len EQU 2
TIM1_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM1_CCMR1_Input_IC1F_ofs EQU 4
TIM1_CCMR1_Input_IC1F_len EQU 4
TIM1_CCMR1_Input_IC1PCS EQU 0x0000000c ; Input capture 1 prescaler
TIM1_CCMR1_Input_IC1PCS_ofs EQU 2
TIM1_CCMR1_Input_IC1PCS_len EQU 2
TIM1_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM1_CCMR1_Input_CC1S_ofs EQU 0
TIM1_CCMR1_Input_CC1S_len EQU 2
; TIM1_CCMR2_Output fields:
TIM1_CCMR2_Output_OC4CE EQU 0x00008000 ; Output compare 4 clear enable
TIM1_CCMR2_Output_OC4CE_ofs EQU 15
TIM1_CCMR2_Output_OC4CE_len EQU 1
TIM1_CCMR2_Output_OC4M EQU 0x00007000 ; Output compare 4 mode
TIM1_CCMR2_Output_OC4M_ofs EQU 12
TIM1_CCMR2_Output_OC4M_len EQU 3
TIM1_CCMR2_Output_OC4PE EQU 0x00000800 ; Output compare 4 preload enable
TIM1_CCMR2_Output_OC4PE_ofs EQU 11
TIM1_CCMR2_Output_OC4PE_len EQU 1
TIM1_CCMR2_Output_OC4FE EQU 0x00000400 ; Output compare 4 fast enable
TIM1_CCMR2_Output_OC4FE_ofs EQU 10
TIM1_CCMR2_Output_OC4FE_len EQU 1
TIM1_CCMR2_Output_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM1_CCMR2_Output_CC4S_ofs EQU 8
TIM1_CCMR2_Output_CC4S_len EQU 2
TIM1_CCMR2_Output_OC3CE EQU 0x00000080 ; Output compare 3 clear enable
TIM1_CCMR2_Output_OC3CE_ofs EQU 7
TIM1_CCMR2_Output_OC3CE_len EQU 1
TIM1_CCMR2_Output_OC3M EQU 0x00000070 ; Output compare 3 mode
TIM1_CCMR2_Output_OC3M_ofs EQU 4
TIM1_CCMR2_Output_OC3M_len EQU 3
TIM1_CCMR2_Output_OC3PE EQU 0x00000008 ; Output compare 3 preload enable
TIM1_CCMR2_Output_OC3PE_ofs EQU 3
TIM1_CCMR2_Output_OC3PE_len EQU 1
TIM1_CCMR2_Output_OC3FE EQU 0x00000004 ; Output compare 3 fast enable
TIM1_CCMR2_Output_OC3FE_ofs EQU 2
TIM1_CCMR2_Output_OC3FE_len EQU 1
TIM1_CCMR2_Output_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM1_CCMR2_Output_CC3S_ofs EQU 0
TIM1_CCMR2_Output_CC3S_len EQU 2
TIM1_CCMR2_Output_OC3M_3 EQU 0x00010000 ; Output Compare 3 mode bit 3
TIM1_CCMR2_Output_OC3M_3_ofs EQU 16
TIM1_CCMR2_Output_OC3M_3_len EQU 1
TIM1_CCMR2_Output_OC4M_3 EQU 0x01000000 ; Output Compare 4 mode bit 3
TIM1_CCMR2_Output_OC4M_3_ofs EQU 24
TIM1_CCMR2_Output_OC4M_3_len EQU 1
; TIM1_CCMR2_Input fields:
TIM1_CCMR2_Input_IC4F EQU 0x0000f000 ; Input capture 4 filter
TIM1_CCMR2_Input_IC4F_ofs EQU 12
TIM1_CCMR2_Input_IC4F_len EQU 4
TIM1_CCMR2_Input_IC4PSC EQU 0x00000c00 ; Input capture 4 prescaler
TIM1_CCMR2_Input_IC4PSC_ofs EQU 10
TIM1_CCMR2_Input_IC4PSC_len EQU 2
TIM1_CCMR2_Input_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM1_CCMR2_Input_CC4S_ofs EQU 8
TIM1_CCMR2_Input_CC4S_len EQU 2
TIM1_CCMR2_Input_IC3F EQU 0x000000f0 ; Input capture 3 filter
TIM1_CCMR2_Input_IC3F_ofs EQU 4
TIM1_CCMR2_Input_IC3F_len EQU 4
TIM1_CCMR2_Input_IC3PSC EQU 0x0000000c ; Input capture 3 prescaler
TIM1_CCMR2_Input_IC3PSC_ofs EQU 2
TIM1_CCMR2_Input_IC3PSC_len EQU 2
TIM1_CCMR2_Input_CC3S EQU 0x00000003 ; Capture/compare 3 selection
TIM1_CCMR2_Input_CC3S_ofs EQU 0
TIM1_CCMR2_Input_CC3S_len EQU 2
; TIM1_CCER fields:
TIM1_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM1_CCER_CC1E_ofs EQU 0
TIM1_CCER_CC1E_len EQU 1
TIM1_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM1_CCER_CC1P_ofs EQU 1
TIM1_CCER_CC1P_len EQU 1
TIM1_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM1_CCER_CC1NE_ofs EQU 2
TIM1_CCER_CC1NE_len EQU 1
TIM1_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM1_CCER_CC1NP_ofs EQU 3
TIM1_CCER_CC1NP_len EQU 1
TIM1_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM1_CCER_CC2E_ofs EQU 4
TIM1_CCER_CC2E_len EQU 1
TIM1_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM1_CCER_CC2P_ofs EQU 5
TIM1_CCER_CC2P_len EQU 1
TIM1_CCER_CC2NE EQU 0x00000040 ; Capture/Compare 2 complementary output enable
TIM1_CCER_CC2NE_ofs EQU 6
TIM1_CCER_CC2NE_len EQU 1
TIM1_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM1_CCER_CC2NP_ofs EQU 7
TIM1_CCER_CC2NP_len EQU 1
TIM1_CCER_CC3E EQU 0x00000100 ; Capture/Compare 3 output enable
TIM1_CCER_CC3E_ofs EQU 8
TIM1_CCER_CC3E_len EQU 1
TIM1_CCER_CC3P EQU 0x00000200 ; Capture/Compare 3 output Polarity
TIM1_CCER_CC3P_ofs EQU 9
TIM1_CCER_CC3P_len EQU 1
TIM1_CCER_CC3NE EQU 0x00000400 ; Capture/Compare 3 complementary output enable
TIM1_CCER_CC3NE_ofs EQU 10
TIM1_CCER_CC3NE_len EQU 1
TIM1_CCER_CC3NP EQU 0x00000800 ; Capture/Compare 3 output Polarity
TIM1_CCER_CC3NP_ofs EQU 11
TIM1_CCER_CC3NP_len EQU 1
TIM1_CCER_CC4E EQU 0x00001000 ; Capture/Compare 4 output enable
TIM1_CCER_CC4E_ofs EQU 12
TIM1_CCER_CC4E_len EQU 1
TIM1_CCER_CC4P EQU 0x00002000 ; Capture/Compare 3 output Polarity
TIM1_CCER_CC4P_ofs EQU 13
TIM1_CCER_CC4P_len EQU 1
TIM1_CCER_CC4NP EQU 0x00008000 ; Capture/Compare 4 output Polarity
TIM1_CCER_CC4NP_ofs EQU 15
TIM1_CCER_CC4NP_len EQU 1
TIM1_CCER_CC5E EQU 0x00010000 ; Capture/Compare 5 output enable
TIM1_CCER_CC5E_ofs EQU 16
TIM1_CCER_CC5E_len EQU 1
TIM1_CCER_CC5P EQU 0x00020000 ; Capture/Compare 5 output Polarity
TIM1_CCER_CC5P_ofs EQU 17
TIM1_CCER_CC5P_len EQU 1
TIM1_CCER_CC6E EQU 0x00100000 ; Capture/Compare 6 output enable
TIM1_CCER_CC6E_ofs EQU 20
TIM1_CCER_CC6E_len EQU 1
TIM1_CCER_CC6P EQU 0x00200000 ; Capture/Compare 6 output Polarity
TIM1_CCER_CC6P_ofs EQU 21
TIM1_CCER_CC6P_len EQU 1
; TIM1_CNT fields:
TIM1_CNT_CNT EQU 0x0000ffff ; counter value
TIM1_CNT_CNT_ofs EQU 0
TIM1_CNT_CNT_len EQU 16
TIM1_CNT_UIFCPY EQU 0x80000000 ; UIF copy
TIM1_CNT_UIFCPY_ofs EQU 31
TIM1_CNT_UIFCPY_len EQU 1
; TIM1_PSC fields:
TIM1_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM1_PSC_PSC_ofs EQU 0
TIM1_PSC_PSC_len EQU 16
; TIM1_ARR fields:
TIM1_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM1_ARR_ARR_ofs EQU 0
TIM1_ARR_ARR_len EQU 16
; TIM1_RCR fields:
TIM1_RCR_REP EQU 0x0000ffff ; Repetition counter value
TIM1_RCR_REP_ofs EQU 0
TIM1_RCR_REP_len EQU 16
; TIM1_CCR1 fields:
TIM1_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM1_CCR1_CCR1_ofs EQU 0
TIM1_CCR1_CCR1_len EQU 16
; TIM1_CCR2 fields:
TIM1_CCR2_CCR2 EQU 0x0000ffff ; Capture/Compare 2 value
TIM1_CCR2_CCR2_ofs EQU 0
TIM1_CCR2_CCR2_len EQU 16
; TIM1_CCR3 fields:
TIM1_CCR3_CCR3 EQU 0x0000ffff ; Capture/Compare 3 value
TIM1_CCR3_CCR3_ofs EQU 0
TIM1_CCR3_CCR3_len EQU 16
; TIM1_CCR4 fields:
TIM1_CCR4_CCR4 EQU 0x0000ffff ; Capture/Compare 3 value
TIM1_CCR4_CCR4_ofs EQU 0
TIM1_CCR4_CCR4_len EQU 16
; TIM1_BDTR fields:
TIM1_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM1_BDTR_DTG_ofs EQU 0
TIM1_BDTR_DTG_len EQU 8
TIM1_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM1_BDTR_LOCK_ofs EQU 8
TIM1_BDTR_LOCK_len EQU 2
TIM1_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM1_BDTR_OSSI_ofs EQU 10
TIM1_BDTR_OSSI_len EQU 1
TIM1_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM1_BDTR_OSSR_ofs EQU 11
TIM1_BDTR_OSSR_len EQU 1
TIM1_BDTR_BKE EQU 0x00001000 ; Break enable
TIM1_BDTR_BKE_ofs EQU 12
TIM1_BDTR_BKE_len EQU 1
TIM1_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM1_BDTR_BKP_ofs EQU 13
TIM1_BDTR_BKP_len EQU 1
TIM1_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM1_BDTR_AOE_ofs EQU 14
TIM1_BDTR_AOE_len EQU 1
TIM1_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM1_BDTR_MOE_ofs EQU 15
TIM1_BDTR_MOE_len EQU 1
TIM1_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM1_BDTR_BKF_ofs EQU 16
TIM1_BDTR_BKF_len EQU 4
TIM1_BDTR_BK2F EQU 0x00f00000 ; Break 2 filter
TIM1_BDTR_BK2F_ofs EQU 20
TIM1_BDTR_BK2F_len EQU 4
TIM1_BDTR_BK2E EQU 0x01000000 ; Break 2 enable
TIM1_BDTR_BK2E_ofs EQU 24
TIM1_BDTR_BK2E_len EQU 1
TIM1_BDTR_BK2P EQU 0x02000000 ; Break 2 polarity
TIM1_BDTR_BK2P_ofs EQU 25
TIM1_BDTR_BK2P_len EQU 1
; TIM1_DCR fields:
TIM1_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM1_DCR_DBL_ofs EQU 8
TIM1_DCR_DBL_len EQU 5
TIM1_DCR_DBA EQU 0x0000001f ; DMA base address
TIM1_DCR_DBA_ofs EQU 0
TIM1_DCR_DBA_len EQU 5
; TIM1_DMAR fields:
TIM1_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM1_DMAR_DMAB_ofs EQU 0
TIM1_DMAR_DMAB_len EQU 16
; TIM1_CCMR3_Output fields:
TIM1_CCMR3_Output_OC5FE EQU 0x00000004 ; Output compare 5 fast enable
TIM1_CCMR3_Output_OC5FE_ofs EQU 2
TIM1_CCMR3_Output_OC5FE_len EQU 1
TIM1_CCMR3_Output_OC5PE EQU 0x00000008 ; Output compare 5 preload enable
TIM1_CCMR3_Output_OC5PE_ofs EQU 3
TIM1_CCMR3_Output_OC5PE_len EQU 1
TIM1_CCMR3_Output_OC5M EQU 0x00000070 ; Output compare 5 mode
TIM1_CCMR3_Output_OC5M_ofs EQU 4
TIM1_CCMR3_Output_OC5M_len EQU 3
TIM1_CCMR3_Output_OC5CE EQU 0x00000080 ; Output compare 5 clear enable
TIM1_CCMR3_Output_OC5CE_ofs EQU 7
TIM1_CCMR3_Output_OC5CE_len EQU 1
TIM1_CCMR3_Output_OC6FE EQU 0x00000400 ; Output compare 6 fast enable
TIM1_CCMR3_Output_OC6FE_ofs EQU 10
TIM1_CCMR3_Output_OC6FE_len EQU 1
TIM1_CCMR3_Output_OC6PE EQU 0x00000800 ; Output compare 6 preload enable
TIM1_CCMR3_Output_OC6PE_ofs EQU 11
TIM1_CCMR3_Output_OC6PE_len EQU 1
TIM1_CCMR3_Output_OC6M EQU 0x00007000 ; Output compare 6 mode
TIM1_CCMR3_Output_OC6M_ofs EQU 12
TIM1_CCMR3_Output_OC6M_len EQU 3
TIM1_CCMR3_Output_OC6CE EQU 0x00008000 ; Output compare 6 clear enable
TIM1_CCMR3_Output_OC6CE_ofs EQU 15
TIM1_CCMR3_Output_OC6CE_len EQU 1
TIM1_CCMR3_Output_OC5M_3 EQU 0x00010000 ; Outout Compare 5 mode bit 3
TIM1_CCMR3_Output_OC5M_3_ofs EQU 16
TIM1_CCMR3_Output_OC5M_3_len EQU 1
TIM1_CCMR3_Output_OC6M_3 EQU 0x01000000 ; Outout Compare 6 mode bit 3
TIM1_CCMR3_Output_OC6M_3_ofs EQU 24
TIM1_CCMR3_Output_OC6M_3_len EQU 1
; TIM1_CCR5 fields:
TIM1_CCR5_CCR5 EQU 0x0000ffff ; Capture/Compare 5 value
TIM1_CCR5_CCR5_ofs EQU 0
TIM1_CCR5_CCR5_len EQU 16
TIM1_CCR5_GC5C1 EQU 0x20000000 ; Group Channel 5 and Channel 1
TIM1_CCR5_GC5C1_ofs EQU 29
TIM1_CCR5_GC5C1_len EQU 1
TIM1_CCR5_GC5C2 EQU 0x40000000 ; Group Channel 5 and Channel 2
TIM1_CCR5_GC5C2_ofs EQU 30
TIM1_CCR5_GC5C2_len EQU 1
TIM1_CCR5_GC5C3 EQU 0x80000000 ; Group Channel 5 and Channel 3
TIM1_CCR5_GC5C3_ofs EQU 31
TIM1_CCR5_GC5C3_len EQU 1
; TIM1_CCR6 fields:
TIM1_CCR6_CCR6 EQU 0x0000ffff ; Capture/Compare 6 value
TIM1_CCR6_CCR6_ofs EQU 0
TIM1_CCR6_CCR6_len EQU 16
; TIM1_OR fields:
TIM1_OR_TIM1_ETR_ADC1_RMP EQU 0x00000003 ; TIM1_ETR_ADC1 remapping capability
TIM1_OR_TIM1_ETR_ADC1_RMP_ofs EQU 0
TIM1_OR_TIM1_ETR_ADC1_RMP_len EQU 2
TIM1_OR_TIM1_ETR_ADC4_RMP EQU 0x0000000c ; TIM1_ETR_ADC4 remapping capability
TIM1_OR_TIM1_ETR_ADC4_RMP_ofs EQU 2
TIM1_OR_TIM1_ETR_ADC4_RMP_len EQU 2
; ---- TIM8 --------------------------------------------------
; Desc: Advanced-timers
; TIM8 base address:
TIM8_BASE EQU 0x40013400
; TIM8 registers:
TIM8_CR1 EQU (TIM8_BASE + 0x0) ; control register 1
TIM8_CR2 EQU (TIM8_BASE + 0x4) ; control register 2
TIM8_SMCR EQU (TIM8_BASE + 0x8) ; slave mode control register
TIM8_DIER EQU (TIM8_BASE + 0xc) ; DMA/Interrupt enable register
TIM8_SR EQU (TIM8_BASE + 0x10) ; status register
TIM8_EGR EQU (TIM8_BASE + 0x14) ; event generation register
TIM8_CCMR1_Output EQU (TIM8_BASE + 0x18) ; capture/compare mode register (output mode)
TIM8_CCMR1_Input EQU (TIM8_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM8_CCMR2_Output EQU (TIM8_BASE + 0x1c) ; capture/compare mode register (output mode)
TIM8_CCMR2_Input EQU (TIM8_BASE + 0x1c) ; capture/compare mode register 2 (input mode)
TIM8_CCER EQU (TIM8_BASE + 0x20) ; capture/compare enable register
TIM8_CNT EQU (TIM8_BASE + 0x24) ; counter
TIM8_PSC EQU (TIM8_BASE + 0x28) ; prescaler
TIM8_ARR EQU (TIM8_BASE + 0x2c) ; auto-reload register
TIM8_RCR EQU (TIM8_BASE + 0x30) ; repetition counter register
TIM8_CCR1 EQU (TIM8_BASE + 0x34) ; capture/compare register 1
TIM8_CCR2 EQU (TIM8_BASE + 0x38) ; capture/compare register 2
TIM8_CCR3 EQU (TIM8_BASE + 0x3c) ; capture/compare register 3
TIM8_CCR4 EQU (TIM8_BASE + 0x40) ; capture/compare register 4
TIM8_BDTR EQU (TIM8_BASE + 0x44) ; break and dead-time register
TIM8_DCR EQU (TIM8_BASE + 0x48) ; DMA control register
TIM8_DMAR EQU (TIM8_BASE + 0x4c) ; DMA address for full transfer
TIM8_CCMR3_Output EQU (TIM8_BASE + 0x54) ; capture/compare mode register 3 (output mode)
TIM8_CCR5 EQU (TIM8_BASE + 0x58) ; capture/compare register 5
TIM8_CCR6 EQU (TIM8_BASE + 0x5c) ; capture/compare register 6
TIM8_OR EQU (TIM8_BASE + 0x60) ; option registers
; TIM8_CR1 fields:
TIM8_CR1_CEN EQU 0x00000001 ; Counter enable
TIM8_CR1_CEN_ofs EQU 0
TIM8_CR1_CEN_len EQU 1
TIM8_CR1_UDIS EQU 0x00000002 ; Update disable
TIM8_CR1_UDIS_ofs EQU 1
TIM8_CR1_UDIS_len EQU 1
TIM8_CR1_URS EQU 0x00000004 ; Update request source
TIM8_CR1_URS_ofs EQU 2
TIM8_CR1_URS_len EQU 1
TIM8_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM8_CR1_OPM_ofs EQU 3
TIM8_CR1_OPM_len EQU 1
TIM8_CR1_DIR EQU 0x00000010 ; Direction
TIM8_CR1_DIR_ofs EQU 4
TIM8_CR1_DIR_len EQU 1
TIM8_CR1_CMS EQU 0x00000060 ; Center-aligned mode selection
TIM8_CR1_CMS_ofs EQU 5
TIM8_CR1_CMS_len EQU 2
TIM8_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM8_CR1_ARPE_ofs EQU 7
TIM8_CR1_ARPE_len EQU 1
TIM8_CR1_CKD EQU 0x00000300 ; Clock division
TIM8_CR1_CKD_ofs EQU 8
TIM8_CR1_CKD_len EQU 2
TIM8_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM8_CR1_UIFREMAP_ofs EQU 11
TIM8_CR1_UIFREMAP_len EQU 1
; TIM8_CR2 fields:
TIM8_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM8_CR2_CCPC_ofs EQU 0
TIM8_CR2_CCPC_len EQU 1
TIM8_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM8_CR2_CCUS_ofs EQU 2
TIM8_CR2_CCUS_len EQU 1
TIM8_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM8_CR2_CCDS_ofs EQU 3
TIM8_CR2_CCDS_len EQU 1
TIM8_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM8_CR2_MMS_ofs EQU 4
TIM8_CR2_MMS_len EQU 3
TIM8_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM8_CR2_TI1S_ofs EQU 7
TIM8_CR2_TI1S_len EQU 1
TIM8_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM8_CR2_OIS1_ofs EQU 8
TIM8_CR2_OIS1_len EQU 1
TIM8_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM8_CR2_OIS1N_ofs EQU 9
TIM8_CR2_OIS1N_len EQU 1
TIM8_CR2_OIS2 EQU 0x00000400 ; Output Idle state 2
TIM8_CR2_OIS2_ofs EQU 10
TIM8_CR2_OIS2_len EQU 1
TIM8_CR2_OIS2N EQU 0x00000800 ; Output Idle state 2
TIM8_CR2_OIS2N_ofs EQU 11
TIM8_CR2_OIS2N_len EQU 1
TIM8_CR2_OIS3 EQU 0x00001000 ; Output Idle state 3
TIM8_CR2_OIS3_ofs EQU 12
TIM8_CR2_OIS3_len EQU 1
TIM8_CR2_OIS3N EQU 0x00002000 ; Output Idle state 3
TIM8_CR2_OIS3N_ofs EQU 13
TIM8_CR2_OIS3N_len EQU 1
TIM8_CR2_OIS4 EQU 0x00004000 ; Output Idle state 4
TIM8_CR2_OIS4_ofs EQU 14
TIM8_CR2_OIS4_len EQU 1
TIM8_CR2_OIS5 EQU 0x00010000 ; Output Idle state 5
TIM8_CR2_OIS5_ofs EQU 16
TIM8_CR2_OIS5_len EQU 1
TIM8_CR2_OIS6 EQU 0x00040000 ; Output Idle state 6
TIM8_CR2_OIS6_ofs EQU 18
TIM8_CR2_OIS6_len EQU 1
TIM8_CR2_MMS2 EQU 0x00f00000 ; Master mode selection 2
TIM8_CR2_MMS2_ofs EQU 20
TIM8_CR2_MMS2_len EQU 4
; TIM8_SMCR fields:
TIM8_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM8_SMCR_SMS_ofs EQU 0
TIM8_SMCR_SMS_len EQU 3
TIM8_SMCR_OCCS EQU 0x00000008 ; OCREF clear selection
TIM8_SMCR_OCCS_ofs EQU 3
TIM8_SMCR_OCCS_len EQU 1
TIM8_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM8_SMCR_TS_ofs EQU 4
TIM8_SMCR_TS_len EQU 3
TIM8_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM8_SMCR_MSM_ofs EQU 7
TIM8_SMCR_MSM_len EQU 1
TIM8_SMCR_ETF EQU 0x00000f00 ; External trigger filter
TIM8_SMCR_ETF_ofs EQU 8
TIM8_SMCR_ETF_len EQU 4
TIM8_SMCR_ETPS EQU 0x00003000 ; External trigger prescaler
TIM8_SMCR_ETPS_ofs EQU 12
TIM8_SMCR_ETPS_len EQU 2
TIM8_SMCR_ECE EQU 0x00004000 ; External clock enable
TIM8_SMCR_ECE_ofs EQU 14
TIM8_SMCR_ECE_len EQU 1
TIM8_SMCR_ETP EQU 0x00008000 ; External trigger polarity
TIM8_SMCR_ETP_ofs EQU 15
TIM8_SMCR_ETP_len EQU 1
TIM8_SMCR_SMS3 EQU 0x00010000 ; Slave mode selection bit 3
TIM8_SMCR_SMS3_ofs EQU 16
TIM8_SMCR_SMS3_len EQU 1
; TIM8_DIER fields:
TIM8_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM8_DIER_TDE_ofs EQU 14
TIM8_DIER_TDE_len EQU 1
TIM8_DIER_COMDE EQU 0x00002000 ; Reserved
TIM8_DIER_COMDE_ofs EQU 13
TIM8_DIER_COMDE_len EQU 1
TIM8_DIER_CC4DE EQU 0x00001000 ; Capture/Compare 4 DMA request enable
TIM8_DIER_CC4DE_ofs EQU 12
TIM8_DIER_CC4DE_len EQU 1
TIM8_DIER_CC3DE EQU 0x00000800 ; Capture/Compare 3 DMA request enable
TIM8_DIER_CC3DE_ofs EQU 11
TIM8_DIER_CC3DE_len EQU 1
TIM8_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM8_DIER_CC2DE_ofs EQU 10
TIM8_DIER_CC2DE_len EQU 1
TIM8_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM8_DIER_CC1DE_ofs EQU 9
TIM8_DIER_CC1DE_len EQU 1
TIM8_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM8_DIER_UDE_ofs EQU 8
TIM8_DIER_UDE_len EQU 1
TIM8_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM8_DIER_BIE_ofs EQU 7
TIM8_DIER_BIE_len EQU 1
TIM8_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM8_DIER_TIE_ofs EQU 6
TIM8_DIER_TIE_len EQU 1
TIM8_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM8_DIER_COMIE_ofs EQU 5
TIM8_DIER_COMIE_len EQU 1
TIM8_DIER_CC4IE EQU 0x00000010 ; Capture/Compare 4 interrupt enable
TIM8_DIER_CC4IE_ofs EQU 4
TIM8_DIER_CC4IE_len EQU 1
TIM8_DIER_CC3IE EQU 0x00000008 ; Capture/Compare 3 interrupt enable
TIM8_DIER_CC3IE_ofs EQU 3
TIM8_DIER_CC3IE_len EQU 1
TIM8_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM8_DIER_CC2IE_ofs EQU 2
TIM8_DIER_CC2IE_len EQU 1
TIM8_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM8_DIER_CC1IE_ofs EQU 1
TIM8_DIER_CC1IE_len EQU 1
TIM8_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM8_DIER_UIE_ofs EQU 0
TIM8_DIER_UIE_len EQU 1
; TIM8_SR fields:
TIM8_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM8_SR_UIF_ofs EQU 0
TIM8_SR_UIF_len EQU 1
TIM8_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM8_SR_CC1IF_ofs EQU 1
TIM8_SR_CC1IF_len EQU 1
TIM8_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM8_SR_CC2IF_ofs EQU 2
TIM8_SR_CC2IF_len EQU 1
TIM8_SR_CC3IF EQU 0x00000008 ; Capture/Compare 3 interrupt flag
TIM8_SR_CC3IF_ofs EQU 3
TIM8_SR_CC3IF_len EQU 1
TIM8_SR_CC4IF EQU 0x00000010 ; Capture/Compare 4 interrupt flag
TIM8_SR_CC4IF_ofs EQU 4
TIM8_SR_CC4IF_len EQU 1
TIM8_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM8_SR_COMIF_ofs EQU 5
TIM8_SR_COMIF_len EQU 1
TIM8_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM8_SR_TIF_ofs EQU 6
TIM8_SR_TIF_len EQU 1
TIM8_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM8_SR_BIF_ofs EQU 7
TIM8_SR_BIF_len EQU 1
TIM8_SR_B2IF EQU 0x00000100 ; Break 2 interrupt flag
TIM8_SR_B2IF_ofs EQU 8
TIM8_SR_B2IF_len EQU 1
TIM8_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM8_SR_CC1OF_ofs EQU 9
TIM8_SR_CC1OF_len EQU 1
TIM8_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM8_SR_CC2OF_ofs EQU 10
TIM8_SR_CC2OF_len EQU 1
TIM8_SR_CC3OF EQU 0x00000800 ; Capture/Compare 3 overcapture flag
TIM8_SR_CC3OF_ofs EQU 11
TIM8_SR_CC3OF_len EQU 1
TIM8_SR_CC4OF EQU 0x00001000 ; Capture/Compare 4 overcapture flag
TIM8_SR_CC4OF_ofs EQU 12
TIM8_SR_CC4OF_len EQU 1
TIM8_SR_C5IF EQU 0x00010000 ; Capture/Compare 5 interrupt flag
TIM8_SR_C5IF_ofs EQU 16
TIM8_SR_C5IF_len EQU 1
TIM8_SR_C6IF EQU 0x00020000 ; Capture/Compare 6 interrupt flag
TIM8_SR_C6IF_ofs EQU 17
TIM8_SR_C6IF_len EQU 1
; TIM8_EGR fields:
TIM8_EGR_UG EQU 0x00000001 ; Update generation
TIM8_EGR_UG_ofs EQU 0
TIM8_EGR_UG_len EQU 1
TIM8_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM8_EGR_CC1G_ofs EQU 1
TIM8_EGR_CC1G_len EQU 1
TIM8_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM8_EGR_CC2G_ofs EQU 2
TIM8_EGR_CC2G_len EQU 1
TIM8_EGR_CC3G EQU 0x00000008 ; Capture/compare 3 generation
TIM8_EGR_CC3G_ofs EQU 3
TIM8_EGR_CC3G_len EQU 1
TIM8_EGR_CC4G EQU 0x00000010 ; Capture/compare 4 generation
TIM8_EGR_CC4G_ofs EQU 4
TIM8_EGR_CC4G_len EQU 1
TIM8_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM8_EGR_COMG_ofs EQU 5
TIM8_EGR_COMG_len EQU 1
TIM8_EGR_TG EQU 0x00000040 ; Trigger generation
TIM8_EGR_TG_ofs EQU 6
TIM8_EGR_TG_len EQU 1
TIM8_EGR_BG EQU 0x00000080 ; Break generation
TIM8_EGR_BG_ofs EQU 7
TIM8_EGR_BG_len EQU 1
TIM8_EGR_B2G EQU 0x00000100 ; Break 2 generation
TIM8_EGR_B2G_ofs EQU 8
TIM8_EGR_B2G_len EQU 1
; TIM8_CCMR1_Output fields:
TIM8_CCMR1_Output_OC2CE EQU 0x00008000 ; Output Compare 2 clear enable
TIM8_CCMR1_Output_OC2CE_ofs EQU 15
TIM8_CCMR1_Output_OC2CE_len EQU 1
TIM8_CCMR1_Output_OC2M EQU 0x00007000 ; Output Compare 2 mode
TIM8_CCMR1_Output_OC2M_ofs EQU 12
TIM8_CCMR1_Output_OC2M_len EQU 3
TIM8_CCMR1_Output_OC2PE EQU 0x00000800 ; Output Compare 2 preload enable
TIM8_CCMR1_Output_OC2PE_ofs EQU 11
TIM8_CCMR1_Output_OC2PE_len EQU 1
TIM8_CCMR1_Output_OC2FE EQU 0x00000400 ; Output Compare 2 fast enable
TIM8_CCMR1_Output_OC2FE_ofs EQU 10
TIM8_CCMR1_Output_OC2FE_len EQU 1
TIM8_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM8_CCMR1_Output_CC2S_ofs EQU 8
TIM8_CCMR1_Output_CC2S_len EQU 2
TIM8_CCMR1_Output_OC1CE EQU 0x00000080 ; Output Compare 1 clear enable
TIM8_CCMR1_Output_OC1CE_ofs EQU 7
TIM8_CCMR1_Output_OC1CE_len EQU 1
TIM8_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM8_CCMR1_Output_OC1M_ofs EQU 4
TIM8_CCMR1_Output_OC1M_len EQU 3
TIM8_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM8_CCMR1_Output_OC1PE_ofs EQU 3
TIM8_CCMR1_Output_OC1PE_len EQU 1
TIM8_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM8_CCMR1_Output_OC1FE_ofs EQU 2
TIM8_CCMR1_Output_OC1FE_len EQU 1
TIM8_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM8_CCMR1_Output_CC1S_ofs EQU 0
TIM8_CCMR1_Output_CC1S_len EQU 2
TIM8_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode bit 3
TIM8_CCMR1_Output_OC1M_3_ofs EQU 16
TIM8_CCMR1_Output_OC1M_3_len EQU 1
TIM8_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output Compare 2 mode bit 3
TIM8_CCMR1_Output_OC2M_3_ofs EQU 24
TIM8_CCMR1_Output_OC2M_3_len EQU 1
; TIM8_CCMR1_Input fields:
TIM8_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM8_CCMR1_Input_IC2F_ofs EQU 12
TIM8_CCMR1_Input_IC2F_len EQU 4
TIM8_CCMR1_Input_IC2PCS EQU 0x00000c00 ; Input capture 2 prescaler
TIM8_CCMR1_Input_IC2PCS_ofs EQU 10
TIM8_CCMR1_Input_IC2PCS_len EQU 2
TIM8_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM8_CCMR1_Input_CC2S_ofs EQU 8
TIM8_CCMR1_Input_CC2S_len EQU 2
TIM8_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM8_CCMR1_Input_IC1F_ofs EQU 4
TIM8_CCMR1_Input_IC1F_len EQU 4
TIM8_CCMR1_Input_IC1PCS EQU 0x0000000c ; Input capture 1 prescaler
TIM8_CCMR1_Input_IC1PCS_ofs EQU 2
TIM8_CCMR1_Input_IC1PCS_len EQU 2
TIM8_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM8_CCMR1_Input_CC1S_ofs EQU 0
TIM8_CCMR1_Input_CC1S_len EQU 2
; TIM8_CCMR2_Output fields:
TIM8_CCMR2_Output_OC4CE EQU 0x00008000 ; Output compare 4 clear enable
TIM8_CCMR2_Output_OC4CE_ofs EQU 15
TIM8_CCMR2_Output_OC4CE_len EQU 1
TIM8_CCMR2_Output_OC4M EQU 0x00007000 ; Output compare 4 mode
TIM8_CCMR2_Output_OC4M_ofs EQU 12
TIM8_CCMR2_Output_OC4M_len EQU 3
TIM8_CCMR2_Output_OC4PE EQU 0x00000800 ; Output compare 4 preload enable
TIM8_CCMR2_Output_OC4PE_ofs EQU 11
TIM8_CCMR2_Output_OC4PE_len EQU 1
TIM8_CCMR2_Output_OC4FE EQU 0x00000400 ; Output compare 4 fast enable
TIM8_CCMR2_Output_OC4FE_ofs EQU 10
TIM8_CCMR2_Output_OC4FE_len EQU 1
TIM8_CCMR2_Output_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM8_CCMR2_Output_CC4S_ofs EQU 8
TIM8_CCMR2_Output_CC4S_len EQU 2
TIM8_CCMR2_Output_OC3CE EQU 0x00000080 ; Output compare 3 clear enable
TIM8_CCMR2_Output_OC3CE_ofs EQU 7
TIM8_CCMR2_Output_OC3CE_len EQU 1
TIM8_CCMR2_Output_OC3M EQU 0x00000070 ; Output compare 3 mode
TIM8_CCMR2_Output_OC3M_ofs EQU 4
TIM8_CCMR2_Output_OC3M_len EQU 3
TIM8_CCMR2_Output_OC3PE EQU 0x00000008 ; Output compare 3 preload enable
TIM8_CCMR2_Output_OC3PE_ofs EQU 3
TIM8_CCMR2_Output_OC3PE_len EQU 1
TIM8_CCMR2_Output_OC3FE EQU 0x00000004 ; Output compare 3 fast enable
TIM8_CCMR2_Output_OC3FE_ofs EQU 2
TIM8_CCMR2_Output_OC3FE_len EQU 1
TIM8_CCMR2_Output_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM8_CCMR2_Output_CC3S_ofs EQU 0
TIM8_CCMR2_Output_CC3S_len EQU 2
TIM8_CCMR2_Output_OC3M_3 EQU 0x00010000 ; Output Compare 3 mode bit 3
TIM8_CCMR2_Output_OC3M_3_ofs EQU 16
TIM8_CCMR2_Output_OC3M_3_len EQU 1
TIM8_CCMR2_Output_OC4M_3 EQU 0x01000000 ; Output Compare 4 mode bit 3
TIM8_CCMR2_Output_OC4M_3_ofs EQU 24
TIM8_CCMR2_Output_OC4M_3_len EQU 1
; TIM8_CCMR2_Input fields:
TIM8_CCMR2_Input_IC4F EQU 0x0000f000 ; Input capture 4 filter
TIM8_CCMR2_Input_IC4F_ofs EQU 12
TIM8_CCMR2_Input_IC4F_len EQU 4
TIM8_CCMR2_Input_IC4PSC EQU 0x00000c00 ; Input capture 4 prescaler
TIM8_CCMR2_Input_IC4PSC_ofs EQU 10
TIM8_CCMR2_Input_IC4PSC_len EQU 2
TIM8_CCMR2_Input_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM8_CCMR2_Input_CC4S_ofs EQU 8
TIM8_CCMR2_Input_CC4S_len EQU 2
TIM8_CCMR2_Input_IC3F EQU 0x000000f0 ; Input capture 3 filter
TIM8_CCMR2_Input_IC3F_ofs EQU 4
TIM8_CCMR2_Input_IC3F_len EQU 4
TIM8_CCMR2_Input_IC3PSC EQU 0x0000000c ; Input capture 3 prescaler
TIM8_CCMR2_Input_IC3PSC_ofs EQU 2
TIM8_CCMR2_Input_IC3PSC_len EQU 2
TIM8_CCMR2_Input_CC3S EQU 0x00000003 ; Capture/compare 3 selection
TIM8_CCMR2_Input_CC3S_ofs EQU 0
TIM8_CCMR2_Input_CC3S_len EQU 2
; TIM8_CCER fields:
TIM8_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM8_CCER_CC1E_ofs EQU 0
TIM8_CCER_CC1E_len EQU 1
TIM8_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM8_CCER_CC1P_ofs EQU 1
TIM8_CCER_CC1P_len EQU 1
TIM8_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM8_CCER_CC1NE_ofs EQU 2
TIM8_CCER_CC1NE_len EQU 1
TIM8_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM8_CCER_CC1NP_ofs EQU 3
TIM8_CCER_CC1NP_len EQU 1
TIM8_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM8_CCER_CC2E_ofs EQU 4
TIM8_CCER_CC2E_len EQU 1
TIM8_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM8_CCER_CC2P_ofs EQU 5
TIM8_CCER_CC2P_len EQU 1
TIM8_CCER_CC2NE EQU 0x00000040 ; Capture/Compare 2 complementary output enable
TIM8_CCER_CC2NE_ofs EQU 6
TIM8_CCER_CC2NE_len EQU 1
TIM8_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM8_CCER_CC2NP_ofs EQU 7
TIM8_CCER_CC2NP_len EQU 1
TIM8_CCER_CC3E EQU 0x00000100 ; Capture/Compare 3 output enable
TIM8_CCER_CC3E_ofs EQU 8
TIM8_CCER_CC3E_len EQU 1
TIM8_CCER_CC3P EQU 0x00000200 ; Capture/Compare 3 output Polarity
TIM8_CCER_CC3P_ofs EQU 9
TIM8_CCER_CC3P_len EQU 1
TIM8_CCER_CC3NE EQU 0x00000400 ; Capture/Compare 3 complementary output enable
TIM8_CCER_CC3NE_ofs EQU 10
TIM8_CCER_CC3NE_len EQU 1
TIM8_CCER_CC3NP EQU 0x00000800 ; Capture/Compare 3 output Polarity
TIM8_CCER_CC3NP_ofs EQU 11
TIM8_CCER_CC3NP_len EQU 1
TIM8_CCER_CC4E EQU 0x00001000 ; Capture/Compare 4 output enable
TIM8_CCER_CC4E_ofs EQU 12
TIM8_CCER_CC4E_len EQU 1
TIM8_CCER_CC4P EQU 0x00002000 ; Capture/Compare 3 output Polarity
TIM8_CCER_CC4P_ofs EQU 13
TIM8_CCER_CC4P_len EQU 1
TIM8_CCER_CC4NP EQU 0x00008000 ; Capture/Compare 4 output Polarity
TIM8_CCER_CC4NP_ofs EQU 15
TIM8_CCER_CC4NP_len EQU 1
TIM8_CCER_CC5E EQU 0x00010000 ; Capture/Compare 5 output enable
TIM8_CCER_CC5E_ofs EQU 16
TIM8_CCER_CC5E_len EQU 1
TIM8_CCER_CC5P EQU 0x00020000 ; Capture/Compare 5 output Polarity
TIM8_CCER_CC5P_ofs EQU 17
TIM8_CCER_CC5P_len EQU 1
TIM8_CCER_CC6E EQU 0x00100000 ; Capture/Compare 6 output enable
TIM8_CCER_CC6E_ofs EQU 20
TIM8_CCER_CC6E_len EQU 1
TIM8_CCER_CC6P EQU 0x00200000 ; Capture/Compare 6 output Polarity
TIM8_CCER_CC6P_ofs EQU 21
TIM8_CCER_CC6P_len EQU 1
; TIM8_CNT fields:
TIM8_CNT_CNT EQU 0x0000ffff ; counter value
TIM8_CNT_CNT_ofs EQU 0
TIM8_CNT_CNT_len EQU 16
TIM8_CNT_UIFCPY EQU 0x80000000 ; UIF copy
TIM8_CNT_UIFCPY_ofs EQU 31
TIM8_CNT_UIFCPY_len EQU 1
; TIM8_PSC fields:
TIM8_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM8_PSC_PSC_ofs EQU 0
TIM8_PSC_PSC_len EQU 16
; TIM8_ARR fields:
TIM8_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM8_ARR_ARR_ofs EQU 0
TIM8_ARR_ARR_len EQU 16
; TIM8_RCR fields:
TIM8_RCR_REP EQU 0x0000ffff ; Repetition counter value
TIM8_RCR_REP_ofs EQU 0
TIM8_RCR_REP_len EQU 16
; TIM8_CCR1 fields:
TIM8_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM8_CCR1_CCR1_ofs EQU 0
TIM8_CCR1_CCR1_len EQU 16
; TIM8_CCR2 fields:
TIM8_CCR2_CCR2 EQU 0x0000ffff ; Capture/Compare 2 value
TIM8_CCR2_CCR2_ofs EQU 0
TIM8_CCR2_CCR2_len EQU 16
; TIM8_CCR3 fields:
TIM8_CCR3_CCR3 EQU 0x0000ffff ; Capture/Compare 3 value
TIM8_CCR3_CCR3_ofs EQU 0
TIM8_CCR3_CCR3_len EQU 16
; TIM8_CCR4 fields:
TIM8_CCR4_CCR4 EQU 0x0000ffff ; Capture/Compare 3 value
TIM8_CCR4_CCR4_ofs EQU 0
TIM8_CCR4_CCR4_len EQU 16
; TIM8_BDTR fields:
TIM8_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM8_BDTR_DTG_ofs EQU 0
TIM8_BDTR_DTG_len EQU 8
TIM8_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM8_BDTR_LOCK_ofs EQU 8
TIM8_BDTR_LOCK_len EQU 2
TIM8_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM8_BDTR_OSSI_ofs EQU 10
TIM8_BDTR_OSSI_len EQU 1
TIM8_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM8_BDTR_OSSR_ofs EQU 11
TIM8_BDTR_OSSR_len EQU 1
TIM8_BDTR_BKE EQU 0x00001000 ; Break enable
TIM8_BDTR_BKE_ofs EQU 12
TIM8_BDTR_BKE_len EQU 1
TIM8_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM8_BDTR_BKP_ofs EQU 13
TIM8_BDTR_BKP_len EQU 1
TIM8_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM8_BDTR_AOE_ofs EQU 14
TIM8_BDTR_AOE_len EQU 1
TIM8_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM8_BDTR_MOE_ofs EQU 15
TIM8_BDTR_MOE_len EQU 1
TIM8_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM8_BDTR_BKF_ofs EQU 16
TIM8_BDTR_BKF_len EQU 4
TIM8_BDTR_BK2F EQU 0x00f00000 ; Break 2 filter
TIM8_BDTR_BK2F_ofs EQU 20
TIM8_BDTR_BK2F_len EQU 4
TIM8_BDTR_BK2E EQU 0x01000000 ; Break 2 enable
TIM8_BDTR_BK2E_ofs EQU 24
TIM8_BDTR_BK2E_len EQU 1
TIM8_BDTR_BK2P EQU 0x02000000 ; Break 2 polarity
TIM8_BDTR_BK2P_ofs EQU 25
TIM8_BDTR_BK2P_len EQU 1
; TIM8_DCR fields:
TIM8_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM8_DCR_DBL_ofs EQU 8
TIM8_DCR_DBL_len EQU 5
TIM8_DCR_DBA EQU 0x0000001f ; DMA base address
TIM8_DCR_DBA_ofs EQU 0
TIM8_DCR_DBA_len EQU 5
; TIM8_DMAR fields:
TIM8_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM8_DMAR_DMAB_ofs EQU 0
TIM8_DMAR_DMAB_len EQU 16
; TIM8_CCMR3_Output fields:
TIM8_CCMR3_Output_OC5FE EQU 0x00000004 ; Output compare 5 fast enable
TIM8_CCMR3_Output_OC5FE_ofs EQU 2
TIM8_CCMR3_Output_OC5FE_len EQU 1
TIM8_CCMR3_Output_OC5PE EQU 0x00000008 ; Output compare 5 preload enable
TIM8_CCMR3_Output_OC5PE_ofs EQU 3
TIM8_CCMR3_Output_OC5PE_len EQU 1
TIM8_CCMR3_Output_OC5M EQU 0x00000070 ; Output compare 5 mode
TIM8_CCMR3_Output_OC5M_ofs EQU 4
TIM8_CCMR3_Output_OC5M_len EQU 3
TIM8_CCMR3_Output_OC5CE EQU 0x00000080 ; Output compare 5 clear enable
TIM8_CCMR3_Output_OC5CE_ofs EQU 7
TIM8_CCMR3_Output_OC5CE_len EQU 1
TIM8_CCMR3_Output_OC6FE EQU 0x00000400 ; Output compare 6 fast enable
TIM8_CCMR3_Output_OC6FE_ofs EQU 10
TIM8_CCMR3_Output_OC6FE_len EQU 1
TIM8_CCMR3_Output_OC6PE EQU 0x00000800 ; Output compare 6 preload enable
TIM8_CCMR3_Output_OC6PE_ofs EQU 11
TIM8_CCMR3_Output_OC6PE_len EQU 1
TIM8_CCMR3_Output_OC6M EQU 0x00007000 ; Output compare 6 mode
TIM8_CCMR3_Output_OC6M_ofs EQU 12
TIM8_CCMR3_Output_OC6M_len EQU 3
TIM8_CCMR3_Output_OC6CE EQU 0x00008000 ; Output compare 6 clear enable
TIM8_CCMR3_Output_OC6CE_ofs EQU 15
TIM8_CCMR3_Output_OC6CE_len EQU 1
TIM8_CCMR3_Output_OC5M_3 EQU 0x00010000 ; Outout Compare 5 mode bit 3
TIM8_CCMR3_Output_OC5M_3_ofs EQU 16
TIM8_CCMR3_Output_OC5M_3_len EQU 1
TIM8_CCMR3_Output_OC6M_3 EQU 0x01000000 ; Outout Compare 6 mode bit 3
TIM8_CCMR3_Output_OC6M_3_ofs EQU 24
TIM8_CCMR3_Output_OC6M_3_len EQU 1
; TIM8_CCR5 fields:
TIM8_CCR5_CCR5 EQU 0x0000ffff ; Capture/Compare 5 value
TIM8_CCR5_CCR5_ofs EQU 0
TIM8_CCR5_CCR5_len EQU 16
TIM8_CCR5_GC5C1 EQU 0x20000000 ; Group Channel 5 and Channel 1
TIM8_CCR5_GC5C1_ofs EQU 29
TIM8_CCR5_GC5C1_len EQU 1
TIM8_CCR5_GC5C2 EQU 0x40000000 ; Group Channel 5 and Channel 2
TIM8_CCR5_GC5C2_ofs EQU 30
TIM8_CCR5_GC5C2_len EQU 1
TIM8_CCR5_GC5C3 EQU 0x80000000 ; Group Channel 5 and Channel 3
TIM8_CCR5_GC5C3_ofs EQU 31
TIM8_CCR5_GC5C3_len EQU 1
; TIM8_CCR6 fields:
TIM8_CCR6_CCR6 EQU 0x0000ffff ; Capture/Compare 6 value
TIM8_CCR6_CCR6_ofs EQU 0
TIM8_CCR6_CCR6_len EQU 16
; TIM8_OR fields:
TIM8_OR_TIM8_ETR_ADC2_RMP EQU 0x00000003 ; TIM8_ETR_ADC2 remapping capability
TIM8_OR_TIM8_ETR_ADC2_RMP_ofs EQU 0
TIM8_OR_TIM8_ETR_ADC2_RMP_len EQU 2
TIM8_OR_TIM8_ETR_ADC3_RMP EQU 0x0000000c ; TIM8_ETR_ADC3 remapping capability
TIM8_OR_TIM8_ETR_ADC3_RMP_ofs EQU 2
TIM8_OR_TIM8_ETR_ADC3_RMP_len EQU 2
; ---- ADC1 --------------------------------------------------
; Desc: Analog-to-Digital Converter
; ADC1 base address:
ADC1_BASE EQU 0x50000000
; ADC1 registers:
ADC1_ISR EQU (ADC1_BASE + 0x0) ; interrupt and status register
ADC1_IER EQU (ADC1_BASE + 0x4) ; interrupt enable register
ADC1_CR EQU (ADC1_BASE + 0x8) ; control register
ADC1_CFGR EQU (ADC1_BASE + 0xc) ; configuration register
ADC1_SMPR1 EQU (ADC1_BASE + 0x14) ; sample time register 1
ADC1_SMPR2 EQU (ADC1_BASE + 0x18) ; sample time register 2
ADC1_TR1 EQU (ADC1_BASE + 0x20) ; watchdog threshold register 1
ADC1_TR2 EQU (ADC1_BASE + 0x24) ; watchdog threshold register
ADC1_TR3 EQU (ADC1_BASE + 0x28) ; watchdog threshold register 3
ADC1_SQR1 EQU (ADC1_BASE + 0x30) ; regular sequence register 1
ADC1_SQR2 EQU (ADC1_BASE + 0x34) ; regular sequence register 2
ADC1_SQR3 EQU (ADC1_BASE + 0x38) ; regular sequence register 3
ADC1_SQR4 EQU (ADC1_BASE + 0x3c) ; regular sequence register 4
ADC1_DR EQU (ADC1_BASE + 0x40) ; regular Data Register
ADC1_JSQR EQU (ADC1_BASE + 0x4c) ; injected sequence register
ADC1_OFR1 EQU (ADC1_BASE + 0x60) ; offset register 1
ADC1_OFR2 EQU (ADC1_BASE + 0x64) ; offset register 2
ADC1_OFR3 EQU (ADC1_BASE + 0x68) ; offset register 3
ADC1_OFR4 EQU (ADC1_BASE + 0x6c) ; offset register 4
ADC1_JDR1 EQU (ADC1_BASE + 0x80) ; injected data register 1
ADC1_JDR2 EQU (ADC1_BASE + 0x84) ; injected data register 2
ADC1_JDR3 EQU (ADC1_BASE + 0x88) ; injected data register 3
ADC1_JDR4 EQU (ADC1_BASE + 0x8c) ; injected data register 4
ADC1_AWD2CR EQU (ADC1_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC1_AWD3CR EQU (ADC1_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC1_DIFSEL EQU (ADC1_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC1_CALFACT EQU (ADC1_BASE + 0xb4) ; Calibration Factors
; ADC1_ISR fields:
ADC1_ISR_JQOVF EQU 0x00000400 ; JQOVF
ADC1_ISR_JQOVF_ofs EQU 10
ADC1_ISR_JQOVF_len EQU 1
ADC1_ISR_AWD3 EQU 0x00000200 ; AWD3
ADC1_ISR_AWD3_ofs EQU 9
ADC1_ISR_AWD3_len EQU 1
ADC1_ISR_AWD2 EQU 0x00000100 ; AWD2
ADC1_ISR_AWD2_ofs EQU 8
ADC1_ISR_AWD2_len EQU 1
ADC1_ISR_AWD1 EQU 0x00000080 ; AWD1
ADC1_ISR_AWD1_ofs EQU 7
ADC1_ISR_AWD1_len EQU 1
ADC1_ISR_JEOS EQU 0x00000040 ; JEOS
ADC1_ISR_JEOS_ofs EQU 6
ADC1_ISR_JEOS_len EQU 1
ADC1_ISR_JEOC EQU 0x00000020 ; JEOC
ADC1_ISR_JEOC_ofs EQU 5
ADC1_ISR_JEOC_len EQU 1
ADC1_ISR_OVR EQU 0x00000010 ; OVR
ADC1_ISR_OVR_ofs EQU 4
ADC1_ISR_OVR_len EQU 1
ADC1_ISR_EOS EQU 0x00000008 ; EOS
ADC1_ISR_EOS_ofs EQU 3
ADC1_ISR_EOS_len EQU 1
ADC1_ISR_EOC EQU 0x00000004 ; EOC
ADC1_ISR_EOC_ofs EQU 2
ADC1_ISR_EOC_len EQU 1
ADC1_ISR_EOSMP EQU 0x00000002 ; EOSMP
ADC1_ISR_EOSMP_ofs EQU 1
ADC1_ISR_EOSMP_len EQU 1
ADC1_ISR_ADRDY EQU 0x00000001 ; ADRDY
ADC1_ISR_ADRDY_ofs EQU 0
ADC1_ISR_ADRDY_len EQU 1
; ADC1_IER fields:
ADC1_IER_JQOVFIE EQU 0x00000400 ; JQOVFIE
ADC1_IER_JQOVFIE_ofs EQU 10
ADC1_IER_JQOVFIE_len EQU 1
ADC1_IER_AWD3IE EQU 0x00000200 ; AWD3IE
ADC1_IER_AWD3IE_ofs EQU 9
ADC1_IER_AWD3IE_len EQU 1
ADC1_IER_AWD2IE EQU 0x00000100 ; AWD2IE
ADC1_IER_AWD2IE_ofs EQU 8
ADC1_IER_AWD2IE_len EQU 1
ADC1_IER_AWD1IE EQU 0x00000080 ; AWD1IE
ADC1_IER_AWD1IE_ofs EQU 7
ADC1_IER_AWD1IE_len EQU 1
ADC1_IER_JEOSIE EQU 0x00000040 ; JEOSIE
ADC1_IER_JEOSIE_ofs EQU 6
ADC1_IER_JEOSIE_len EQU 1
ADC1_IER_JEOCIE EQU 0x00000020 ; JEOCIE
ADC1_IER_JEOCIE_ofs EQU 5
ADC1_IER_JEOCIE_len EQU 1
ADC1_IER_OVRIE EQU 0x00000010 ; OVRIE
ADC1_IER_OVRIE_ofs EQU 4
ADC1_IER_OVRIE_len EQU 1
ADC1_IER_EOSIE EQU 0x00000008 ; EOSIE
ADC1_IER_EOSIE_ofs EQU 3
ADC1_IER_EOSIE_len EQU 1
ADC1_IER_EOCIE EQU 0x00000004 ; EOCIE
ADC1_IER_EOCIE_ofs EQU 2
ADC1_IER_EOCIE_len EQU 1
ADC1_IER_EOSMPIE EQU 0x00000002 ; EOSMPIE
ADC1_IER_EOSMPIE_ofs EQU 1
ADC1_IER_EOSMPIE_len EQU 1
ADC1_IER_ADRDYIE EQU 0x00000001 ; ADRDYIE
ADC1_IER_ADRDYIE_ofs EQU 0
ADC1_IER_ADRDYIE_len EQU 1
; ADC1_CR fields:
ADC1_CR_ADCAL EQU 0x80000000 ; ADCAL
ADC1_CR_ADCAL_ofs EQU 31
ADC1_CR_ADCAL_len EQU 1
ADC1_CR_ADCALDIF EQU 0x40000000 ; ADCALDIF
ADC1_CR_ADCALDIF_ofs EQU 30
ADC1_CR_ADCALDIF_len EQU 1
ADC1_CR_DEEPPWD EQU 0x20000000 ; DEEPPWD
ADC1_CR_DEEPPWD_ofs EQU 29
ADC1_CR_DEEPPWD_len EQU 1
ADC1_CR_ADVREGEN EQU 0x10000000 ; ADVREGEN
ADC1_CR_ADVREGEN_ofs EQU 28
ADC1_CR_ADVREGEN_len EQU 1
ADC1_CR_JADSTP EQU 0x00000020 ; JADSTP
ADC1_CR_JADSTP_ofs EQU 5
ADC1_CR_JADSTP_len EQU 1
ADC1_CR_ADSTP EQU 0x00000010 ; ADSTP
ADC1_CR_ADSTP_ofs EQU 4
ADC1_CR_ADSTP_len EQU 1
ADC1_CR_JADSTART EQU 0x00000008 ; JADSTART
ADC1_CR_JADSTART_ofs EQU 3
ADC1_CR_JADSTART_len EQU 1
ADC1_CR_ADSTART EQU 0x00000004 ; ADSTART
ADC1_CR_ADSTART_ofs EQU 2
ADC1_CR_ADSTART_len EQU 1
ADC1_CR_ADDIS EQU 0x00000002 ; ADDIS
ADC1_CR_ADDIS_ofs EQU 1
ADC1_CR_ADDIS_len EQU 1
ADC1_CR_ADEN EQU 0x00000001 ; ADEN
ADC1_CR_ADEN_ofs EQU 0
ADC1_CR_ADEN_len EQU 1
; ADC1_CFGR fields:
ADC1_CFGR_AWDCH1CH EQU 0x7c000000 ; AWDCH1CH
ADC1_CFGR_AWDCH1CH_ofs EQU 26
ADC1_CFGR_AWDCH1CH_len EQU 5
ADC1_CFGR_JAUTO EQU 0x02000000 ; JAUTO
ADC1_CFGR_JAUTO_ofs EQU 25
ADC1_CFGR_JAUTO_len EQU 1
ADC1_CFGR_JAWD1EN EQU 0x01000000 ; JAWD1EN
ADC1_CFGR_JAWD1EN_ofs EQU 24
ADC1_CFGR_JAWD1EN_len EQU 1
ADC1_CFGR_AWD1EN EQU 0x00800000 ; AWD1EN
ADC1_CFGR_AWD1EN_ofs EQU 23
ADC1_CFGR_AWD1EN_len EQU 1
ADC1_CFGR_AWD1SGL EQU 0x00400000 ; AWD1SGL
ADC1_CFGR_AWD1SGL_ofs EQU 22
ADC1_CFGR_AWD1SGL_len EQU 1
ADC1_CFGR_JQM EQU 0x00200000 ; JQM
ADC1_CFGR_JQM_ofs EQU 21
ADC1_CFGR_JQM_len EQU 1
ADC1_CFGR_JDISCEN EQU 0x00100000 ; JDISCEN
ADC1_CFGR_JDISCEN_ofs EQU 20
ADC1_CFGR_JDISCEN_len EQU 1
ADC1_CFGR_DISCNUM EQU 0x000e0000 ; DISCNUM
ADC1_CFGR_DISCNUM_ofs EQU 17
ADC1_CFGR_DISCNUM_len EQU 3
ADC1_CFGR_DISCEN EQU 0x00010000 ; DISCEN
ADC1_CFGR_DISCEN_ofs EQU 16
ADC1_CFGR_DISCEN_len EQU 1
ADC1_CFGR_AUTOFF EQU 0x00008000 ; AUTOFF
ADC1_CFGR_AUTOFF_ofs EQU 15
ADC1_CFGR_AUTOFF_len EQU 1
ADC1_CFGR_AUTDLY EQU 0x00004000 ; AUTDLY
ADC1_CFGR_AUTDLY_ofs EQU 14
ADC1_CFGR_AUTDLY_len EQU 1
ADC1_CFGR_CONT EQU 0x00002000 ; CONT
ADC1_CFGR_CONT_ofs EQU 13
ADC1_CFGR_CONT_len EQU 1
ADC1_CFGR_OVRMOD EQU 0x00001000 ; OVRMOD
ADC1_CFGR_OVRMOD_ofs EQU 12
ADC1_CFGR_OVRMOD_len EQU 1
ADC1_CFGR_EXTEN EQU 0x00000c00 ; EXTEN
ADC1_CFGR_EXTEN_ofs EQU 10
ADC1_CFGR_EXTEN_len EQU 2
ADC1_CFGR_EXTSEL EQU 0x000003c0 ; EXTSEL
ADC1_CFGR_EXTSEL_ofs EQU 6
ADC1_CFGR_EXTSEL_len EQU 4
ADC1_CFGR_ALIGN EQU 0x00000020 ; ALIGN
ADC1_CFGR_ALIGN_ofs EQU 5
ADC1_CFGR_ALIGN_len EQU 1
ADC1_CFGR_RES EQU 0x00000018 ; RES
ADC1_CFGR_RES_ofs EQU 3
ADC1_CFGR_RES_len EQU 2
ADC1_CFGR_DMACFG EQU 0x00000002 ; DMACFG
ADC1_CFGR_DMACFG_ofs EQU 1
ADC1_CFGR_DMACFG_len EQU 1
ADC1_CFGR_DMAEN EQU 0x00000001 ; DMAEN
ADC1_CFGR_DMAEN_ofs EQU 0
ADC1_CFGR_DMAEN_len EQU 1
; ADC1_SMPR1 fields:
ADC1_SMPR1_SMP9 EQU 0x38000000 ; SMP9
ADC1_SMPR1_SMP9_ofs EQU 27
ADC1_SMPR1_SMP9_len EQU 3
ADC1_SMPR1_SMP8 EQU 0x07000000 ; SMP8
ADC1_SMPR1_SMP8_ofs EQU 24
ADC1_SMPR1_SMP8_len EQU 3
ADC1_SMPR1_SMP7 EQU 0x00e00000 ; SMP7
ADC1_SMPR1_SMP7_ofs EQU 21
ADC1_SMPR1_SMP7_len EQU 3
ADC1_SMPR1_SMP6 EQU 0x001c0000 ; SMP6
ADC1_SMPR1_SMP6_ofs EQU 18
ADC1_SMPR1_SMP6_len EQU 3
ADC1_SMPR1_SMP5 EQU 0x00038000 ; SMP5
ADC1_SMPR1_SMP5_ofs EQU 15
ADC1_SMPR1_SMP5_len EQU 3
ADC1_SMPR1_SMP4 EQU 0x00007000 ; SMP4
ADC1_SMPR1_SMP4_ofs EQU 12
ADC1_SMPR1_SMP4_len EQU 3
ADC1_SMPR1_SMP3 EQU 0x00000e00 ; SMP3
ADC1_SMPR1_SMP3_ofs EQU 9
ADC1_SMPR1_SMP3_len EQU 3
ADC1_SMPR1_SMP2 EQU 0x000001c0 ; SMP2
ADC1_SMPR1_SMP2_ofs EQU 6
ADC1_SMPR1_SMP2_len EQU 3
ADC1_SMPR1_SMP1 EQU 0x00000038 ; SMP1
ADC1_SMPR1_SMP1_ofs EQU 3
ADC1_SMPR1_SMP1_len EQU 3
; ADC1_SMPR2 fields:
ADC1_SMPR2_SMP18 EQU 0x07000000 ; SMP18
ADC1_SMPR2_SMP18_ofs EQU 24
ADC1_SMPR2_SMP18_len EQU 3
ADC1_SMPR2_SMP17 EQU 0x00e00000 ; SMP17
ADC1_SMPR2_SMP17_ofs EQU 21
ADC1_SMPR2_SMP17_len EQU 3
ADC1_SMPR2_SMP16 EQU 0x001c0000 ; SMP16
ADC1_SMPR2_SMP16_ofs EQU 18
ADC1_SMPR2_SMP16_len EQU 3
ADC1_SMPR2_SMP15 EQU 0x00038000 ; SMP15
ADC1_SMPR2_SMP15_ofs EQU 15
ADC1_SMPR2_SMP15_len EQU 3
ADC1_SMPR2_SMP14 EQU 0x00007000 ; SMP14
ADC1_SMPR2_SMP14_ofs EQU 12
ADC1_SMPR2_SMP14_len EQU 3
ADC1_SMPR2_SMP13 EQU 0x00000e00 ; SMP13
ADC1_SMPR2_SMP13_ofs EQU 9
ADC1_SMPR2_SMP13_len EQU 3
ADC1_SMPR2_SMP12 EQU 0x000001c0 ; SMP12
ADC1_SMPR2_SMP12_ofs EQU 6
ADC1_SMPR2_SMP12_len EQU 3
ADC1_SMPR2_SMP11 EQU 0x00000038 ; SMP11
ADC1_SMPR2_SMP11_ofs EQU 3
ADC1_SMPR2_SMP11_len EQU 3
ADC1_SMPR2_SMP10 EQU 0x00000007 ; SMP10
ADC1_SMPR2_SMP10_ofs EQU 0
ADC1_SMPR2_SMP10_len EQU 3
; ADC1_TR1 fields:
ADC1_TR1_HT1 EQU 0x0fff0000 ; HT1
ADC1_TR1_HT1_ofs EQU 16
ADC1_TR1_HT1_len EQU 12
ADC1_TR1_LT1 EQU 0x00000fff ; LT1
ADC1_TR1_LT1_ofs EQU 0
ADC1_TR1_LT1_len EQU 12
; ADC1_TR2 fields:
ADC1_TR2_HT2 EQU 0x00ff0000 ; HT2
ADC1_TR2_HT2_ofs EQU 16
ADC1_TR2_HT2_len EQU 8
ADC1_TR2_LT2 EQU 0x000000ff ; LT2
ADC1_TR2_LT2_ofs EQU 0
ADC1_TR2_LT2_len EQU 8
; ADC1_TR3 fields:
ADC1_TR3_HT3 EQU 0x00ff0000 ; HT3
ADC1_TR3_HT3_ofs EQU 16
ADC1_TR3_HT3_len EQU 8
ADC1_TR3_LT3 EQU 0x000000ff ; LT3
ADC1_TR3_LT3_ofs EQU 0
ADC1_TR3_LT3_len EQU 8
; ADC1_SQR1 fields:
ADC1_SQR1_SQ4 EQU 0x1f000000 ; SQ4
ADC1_SQR1_SQ4_ofs EQU 24
ADC1_SQR1_SQ4_len EQU 5
ADC1_SQR1_SQ3 EQU 0x007c0000 ; SQ3
ADC1_SQR1_SQ3_ofs EQU 18
ADC1_SQR1_SQ3_len EQU 5
ADC1_SQR1_SQ2 EQU 0x0001f000 ; SQ2
ADC1_SQR1_SQ2_ofs EQU 12
ADC1_SQR1_SQ2_len EQU 5
ADC1_SQR1_SQ1 EQU 0x000007c0 ; SQ1
ADC1_SQR1_SQ1_ofs EQU 6
ADC1_SQR1_SQ1_len EQU 5
ADC1_SQR1_L3 EQU 0x0000000f ; L3
ADC1_SQR1_L3_ofs EQU 0
ADC1_SQR1_L3_len EQU 4
; ADC1_SQR2 fields:
ADC1_SQR2_SQ9 EQU 0x1f000000 ; SQ9
ADC1_SQR2_SQ9_ofs EQU 24
ADC1_SQR2_SQ9_len EQU 5
ADC1_SQR2_SQ8 EQU 0x007c0000 ; SQ8
ADC1_SQR2_SQ8_ofs EQU 18
ADC1_SQR2_SQ8_len EQU 5
ADC1_SQR2_SQ7 EQU 0x0001f000 ; SQ7
ADC1_SQR2_SQ7_ofs EQU 12
ADC1_SQR2_SQ7_len EQU 5
ADC1_SQR2_SQ6 EQU 0x000007c0 ; SQ6
ADC1_SQR2_SQ6_ofs EQU 6
ADC1_SQR2_SQ6_len EQU 5
ADC1_SQR2_SQ5 EQU 0x0000001f ; SQ5
ADC1_SQR2_SQ5_ofs EQU 0
ADC1_SQR2_SQ5_len EQU 5
; ADC1_SQR3 fields:
ADC1_SQR3_SQ14 EQU 0x1f000000 ; SQ14
ADC1_SQR3_SQ14_ofs EQU 24
ADC1_SQR3_SQ14_len EQU 5
ADC1_SQR3_SQ13 EQU 0x007c0000 ; SQ13
ADC1_SQR3_SQ13_ofs EQU 18
ADC1_SQR3_SQ13_len EQU 5
ADC1_SQR3_SQ12 EQU 0x0001f000 ; SQ12
ADC1_SQR3_SQ12_ofs EQU 12
ADC1_SQR3_SQ12_len EQU 5
ADC1_SQR3_SQ11 EQU 0x000007c0 ; SQ11
ADC1_SQR3_SQ11_ofs EQU 6
ADC1_SQR3_SQ11_len EQU 5
ADC1_SQR3_SQ10 EQU 0x0000001f ; SQ10
ADC1_SQR3_SQ10_ofs EQU 0
ADC1_SQR3_SQ10_len EQU 5
; ADC1_SQR4 fields:
ADC1_SQR4_SQ16 EQU 0x000007c0 ; SQ16
ADC1_SQR4_SQ16_ofs EQU 6
ADC1_SQR4_SQ16_len EQU 5
ADC1_SQR4_SQ15 EQU 0x0000001f ; SQ15
ADC1_SQR4_SQ15_ofs EQU 0
ADC1_SQR4_SQ15_len EQU 5
; ADC1_DR fields:
ADC1_DR_regularDATA EQU 0x0000ffff ; regularDATA
ADC1_DR_regularDATA_ofs EQU 0
ADC1_DR_regularDATA_len EQU 16
; ADC1_JSQR fields:
ADC1_JSQR_JSQ4 EQU 0x7c000000 ; JSQ4
ADC1_JSQR_JSQ4_ofs EQU 26
ADC1_JSQR_JSQ4_len EQU 5
ADC1_JSQR_JSQ3 EQU 0x01f00000 ; JSQ3
ADC1_JSQR_JSQ3_ofs EQU 20
ADC1_JSQR_JSQ3_len EQU 5
ADC1_JSQR_JSQ2 EQU 0x0007c000 ; JSQ2
ADC1_JSQR_JSQ2_ofs EQU 14
ADC1_JSQR_JSQ2_len EQU 5
ADC1_JSQR_JSQ1 EQU 0x00001f00 ; JSQ1
ADC1_JSQR_JSQ1_ofs EQU 8
ADC1_JSQR_JSQ1_len EQU 5
ADC1_JSQR_JEXTEN EQU 0x000000c0 ; JEXTEN
ADC1_JSQR_JEXTEN_ofs EQU 6
ADC1_JSQR_JEXTEN_len EQU 2
ADC1_JSQR_JEXTSEL EQU 0x0000003c ; JEXTSEL
ADC1_JSQR_JEXTSEL_ofs EQU 2
ADC1_JSQR_JEXTSEL_len EQU 4
ADC1_JSQR_JL EQU 0x00000003 ; JL
ADC1_JSQR_JL_ofs EQU 0
ADC1_JSQR_JL_len EQU 2
; ADC1_OFR1 fields:
ADC1_OFR1_OFFSET1_EN EQU 0x80000000 ; OFFSET1_EN
ADC1_OFR1_OFFSET1_EN_ofs EQU 31
ADC1_OFR1_OFFSET1_EN_len EQU 1
ADC1_OFR1_OFFSET1_CH EQU 0x7c000000 ; OFFSET1_CH
ADC1_OFR1_OFFSET1_CH_ofs EQU 26
ADC1_OFR1_OFFSET1_CH_len EQU 5
ADC1_OFR1_OFFSET1 EQU 0x00000fff ; OFFSET1
ADC1_OFR1_OFFSET1_ofs EQU 0
ADC1_OFR1_OFFSET1_len EQU 12
; ADC1_OFR2 fields:
ADC1_OFR2_OFFSET2_EN EQU 0x80000000 ; OFFSET2_EN
ADC1_OFR2_OFFSET2_EN_ofs EQU 31
ADC1_OFR2_OFFSET2_EN_len EQU 1
ADC1_OFR2_OFFSET2_CH EQU 0x7c000000 ; OFFSET2_CH
ADC1_OFR2_OFFSET2_CH_ofs EQU 26
ADC1_OFR2_OFFSET2_CH_len EQU 5
ADC1_OFR2_OFFSET2 EQU 0x00000fff ; OFFSET2
ADC1_OFR2_OFFSET2_ofs EQU 0
ADC1_OFR2_OFFSET2_len EQU 12
; ADC1_OFR3 fields:
ADC1_OFR3_OFFSET3_EN EQU 0x80000000 ; OFFSET3_EN
ADC1_OFR3_OFFSET3_EN_ofs EQU 31
ADC1_OFR3_OFFSET3_EN_len EQU 1
ADC1_OFR3_OFFSET3_CH EQU 0x7c000000 ; OFFSET3_CH
ADC1_OFR3_OFFSET3_CH_ofs EQU 26
ADC1_OFR3_OFFSET3_CH_len EQU 5
ADC1_OFR3_OFFSET3 EQU 0x00000fff ; OFFSET3
ADC1_OFR3_OFFSET3_ofs EQU 0
ADC1_OFR3_OFFSET3_len EQU 12
; ADC1_OFR4 fields:
ADC1_OFR4_OFFSET4_EN EQU 0x80000000 ; OFFSET4_EN
ADC1_OFR4_OFFSET4_EN_ofs EQU 31
ADC1_OFR4_OFFSET4_EN_len EQU 1
ADC1_OFR4_OFFSET4_CH EQU 0x7c000000 ; OFFSET4_CH
ADC1_OFR4_OFFSET4_CH_ofs EQU 26
ADC1_OFR4_OFFSET4_CH_len EQU 5
ADC1_OFR4_OFFSET4 EQU 0x00000fff ; OFFSET4
ADC1_OFR4_OFFSET4_ofs EQU 0
ADC1_OFR4_OFFSET4_len EQU 12
; ADC1_JDR1 fields:
ADC1_JDR1_JDATA1 EQU 0x0000ffff ; JDATA1
ADC1_JDR1_JDATA1_ofs EQU 0
ADC1_JDR1_JDATA1_len EQU 16
; ADC1_JDR2 fields:
ADC1_JDR2_JDATA2 EQU 0x0000ffff ; JDATA2
ADC1_JDR2_JDATA2_ofs EQU 0
ADC1_JDR2_JDATA2_len EQU 16
; ADC1_JDR3 fields:
ADC1_JDR3_JDATA3 EQU 0x0000ffff ; JDATA3
ADC1_JDR3_JDATA3_ofs EQU 0
ADC1_JDR3_JDATA3_len EQU 16
; ADC1_JDR4 fields:
ADC1_JDR4_JDATA4 EQU 0x0000ffff ; JDATA4
ADC1_JDR4_JDATA4_ofs EQU 0
ADC1_JDR4_JDATA4_len EQU 16
; ADC1_AWD2CR fields:
ADC1_AWD2CR_AWD2CH EQU 0x0007fffe ; AWD2CH
ADC1_AWD2CR_AWD2CH_ofs EQU 1
ADC1_AWD2CR_AWD2CH_len EQU 18
; ADC1_AWD3CR fields:
ADC1_AWD3CR_AWD3CH EQU 0x0007fffe ; AWD3CH
ADC1_AWD3CR_AWD3CH_ofs EQU 1
ADC1_AWD3CR_AWD3CH_len EQU 18
; ADC1_DIFSEL fields:
ADC1_DIFSEL_DIFSEL_1_15 EQU 0x0000fffe ; Differential mode for channels 15 to 1
ADC1_DIFSEL_DIFSEL_1_15_ofs EQU 1
ADC1_DIFSEL_DIFSEL_1_15_len EQU 15
ADC1_DIFSEL_DIFSEL_16_18 EQU 0x00070000 ; Differential mode for channels 18 to 16
ADC1_DIFSEL_DIFSEL_16_18_ofs EQU 16
ADC1_DIFSEL_DIFSEL_16_18_len EQU 3
; ADC1_CALFACT fields:
ADC1_CALFACT_CALFACT_D EQU 0x007f0000 ; CALFACT_D
ADC1_CALFACT_CALFACT_D_ofs EQU 16
ADC1_CALFACT_CALFACT_D_len EQU 7
ADC1_CALFACT_CALFACT_S EQU 0x0000007f ; CALFACT_S
ADC1_CALFACT_CALFACT_S_ofs EQU 0
ADC1_CALFACT_CALFACT_S_len EQU 7
; ---- ADC2 --------------------------------------------------
; Desc: None
; ADC2 base address:
ADC2_BASE EQU 0x50000100
; ADC2 registers:
ADC2_ISR EQU (ADC2_BASE + 0x0) ; interrupt and status register
ADC2_IER EQU (ADC2_BASE + 0x4) ; interrupt enable register
ADC2_CR EQU (ADC2_BASE + 0x8) ; control register
ADC2_CFGR EQU (ADC2_BASE + 0xc) ; configuration register
ADC2_SMPR1 EQU (ADC2_BASE + 0x14) ; sample time register 1
ADC2_SMPR2 EQU (ADC2_BASE + 0x18) ; sample time register 2
ADC2_TR1 EQU (ADC2_BASE + 0x20) ; watchdog threshold register 1
ADC2_TR2 EQU (ADC2_BASE + 0x24) ; watchdog threshold register
ADC2_TR3 EQU (ADC2_BASE + 0x28) ; watchdog threshold register 3
ADC2_SQR1 EQU (ADC2_BASE + 0x30) ; regular sequence register 1
ADC2_SQR2 EQU (ADC2_BASE + 0x34) ; regular sequence register 2
ADC2_SQR3 EQU (ADC2_BASE + 0x38) ; regular sequence register 3
ADC2_SQR4 EQU (ADC2_BASE + 0x3c) ; regular sequence register 4
ADC2_DR EQU (ADC2_BASE + 0x40) ; regular Data Register
ADC2_JSQR EQU (ADC2_BASE + 0x4c) ; injected sequence register
ADC2_OFR1 EQU (ADC2_BASE + 0x60) ; offset register 1
ADC2_OFR2 EQU (ADC2_BASE + 0x64) ; offset register 2
ADC2_OFR3 EQU (ADC2_BASE + 0x68) ; offset register 3
ADC2_OFR4 EQU (ADC2_BASE + 0x6c) ; offset register 4
ADC2_JDR1 EQU (ADC2_BASE + 0x80) ; injected data register 1
ADC2_JDR2 EQU (ADC2_BASE + 0x84) ; injected data register 2
ADC2_JDR3 EQU (ADC2_BASE + 0x88) ; injected data register 3
ADC2_JDR4 EQU (ADC2_BASE + 0x8c) ; injected data register 4
ADC2_AWD2CR EQU (ADC2_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC2_AWD3CR EQU (ADC2_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC2_DIFSEL EQU (ADC2_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC2_CALFACT EQU (ADC2_BASE + 0xb4) ; Calibration Factors
; Fields the same as in the first instance.
; ---- ADC3 --------------------------------------------------
; Desc: None
; ADC3 base address:
ADC3_BASE EQU 0x50000400
; ADC3 registers:
ADC3_ISR EQU (ADC3_BASE + 0x0) ; interrupt and status register
ADC3_IER EQU (ADC3_BASE + 0x4) ; interrupt enable register
ADC3_CR EQU (ADC3_BASE + 0x8) ; control register
ADC3_CFGR EQU (ADC3_BASE + 0xc) ; configuration register
ADC3_SMPR1 EQU (ADC3_BASE + 0x14) ; sample time register 1
ADC3_SMPR2 EQU (ADC3_BASE + 0x18) ; sample time register 2
ADC3_TR1 EQU (ADC3_BASE + 0x20) ; watchdog threshold register 1
ADC3_TR2 EQU (ADC3_BASE + 0x24) ; watchdog threshold register
ADC3_TR3 EQU (ADC3_BASE + 0x28) ; watchdog threshold register 3
ADC3_SQR1 EQU (ADC3_BASE + 0x30) ; regular sequence register 1
ADC3_SQR2 EQU (ADC3_BASE + 0x34) ; regular sequence register 2
ADC3_SQR3 EQU (ADC3_BASE + 0x38) ; regular sequence register 3
ADC3_SQR4 EQU (ADC3_BASE + 0x3c) ; regular sequence register 4
ADC3_DR EQU (ADC3_BASE + 0x40) ; regular Data Register
ADC3_JSQR EQU (ADC3_BASE + 0x4c) ; injected sequence register
ADC3_OFR1 EQU (ADC3_BASE + 0x60) ; offset register 1
ADC3_OFR2 EQU (ADC3_BASE + 0x64) ; offset register 2
ADC3_OFR3 EQU (ADC3_BASE + 0x68) ; offset register 3
ADC3_OFR4 EQU (ADC3_BASE + 0x6c) ; offset register 4
ADC3_JDR1 EQU (ADC3_BASE + 0x80) ; injected data register 1
ADC3_JDR2 EQU (ADC3_BASE + 0x84) ; injected data register 2
ADC3_JDR3 EQU (ADC3_BASE + 0x88) ; injected data register 3
ADC3_JDR4 EQU (ADC3_BASE + 0x8c) ; injected data register 4
ADC3_AWD2CR EQU (ADC3_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC3_AWD3CR EQU (ADC3_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC3_DIFSEL EQU (ADC3_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC3_CALFACT EQU (ADC3_BASE + 0xb4) ; Calibration Factors
; Fields the same as in the first instance.
; ---- ADC4 --------------------------------------------------
; Desc: None
; ADC4 base address:
ADC4_BASE EQU 0x50000500
; ADC4 registers:
ADC4_ISR EQU (ADC4_BASE + 0x0) ; interrupt and status register
ADC4_IER EQU (ADC4_BASE + 0x4) ; interrupt enable register
ADC4_CR EQU (ADC4_BASE + 0x8) ; control register
ADC4_CFGR EQU (ADC4_BASE + 0xc) ; configuration register
ADC4_SMPR1 EQU (ADC4_BASE + 0x14) ; sample time register 1
ADC4_SMPR2 EQU (ADC4_BASE + 0x18) ; sample time register 2
ADC4_TR1 EQU (ADC4_BASE + 0x20) ; watchdog threshold register 1
ADC4_TR2 EQU (ADC4_BASE + 0x24) ; watchdog threshold register
ADC4_TR3 EQU (ADC4_BASE + 0x28) ; watchdog threshold register 3
ADC4_SQR1 EQU (ADC4_BASE + 0x30) ; regular sequence register 1
ADC4_SQR2 EQU (ADC4_BASE + 0x34) ; regular sequence register 2
ADC4_SQR3 EQU (ADC4_BASE + 0x38) ; regular sequence register 3
ADC4_SQR4 EQU (ADC4_BASE + 0x3c) ; regular sequence register 4
ADC4_DR EQU (ADC4_BASE + 0x40) ; regular Data Register
ADC4_JSQR EQU (ADC4_BASE + 0x4c) ; injected sequence register
ADC4_OFR1 EQU (ADC4_BASE + 0x60) ; offset register 1
ADC4_OFR2 EQU (ADC4_BASE + 0x64) ; offset register 2
ADC4_OFR3 EQU (ADC4_BASE + 0x68) ; offset register 3
ADC4_OFR4 EQU (ADC4_BASE + 0x6c) ; offset register 4
ADC4_JDR1 EQU (ADC4_BASE + 0x80) ; injected data register 1
ADC4_JDR2 EQU (ADC4_BASE + 0x84) ; injected data register 2
ADC4_JDR3 EQU (ADC4_BASE + 0x88) ; injected data register 3
ADC4_JDR4 EQU (ADC4_BASE + 0x8c) ; injected data register 4
ADC4_AWD2CR EQU (ADC4_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC4_AWD3CR EQU (ADC4_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC4_DIFSEL EQU (ADC4_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC4_CALFACT EQU (ADC4_BASE + 0xb4) ; Calibration Factors
; Fields the same as in the first instance.
; ---- ADC12 -------------------------------------------------
; Desc: Analog-to-Digital Converter
; ADC12 base address:
ADC12_BASE EQU 0x50000300
; ADC12 registers:
ADC12_CSR EQU (ADC12_BASE + 0x0) ; ADC Common status register
ADC12_CCR EQU (ADC12_BASE + 0x8) ; ADC common control register
ADC12_CDR EQU (ADC12_BASE + 0xc) ; ADC common regular data register for dual and triple modes
; ADC12_CSR fields:
ADCC_CSR_ADDRDY_MST EQU 0x00000001 ; ADDRDY_MST
ADCC_CSR_ADDRDY_MST_ofs EQU 0
ADCC_CSR_ADDRDY_MST_len EQU 1
ADCC_CSR_EOSMP_MST EQU 0x00000002 ; EOSMP_MST
ADCC_CSR_EOSMP_MST_ofs EQU 1
ADCC_CSR_EOSMP_MST_len EQU 1
ADCC_CSR_EOC_MST EQU 0x00000004 ; EOC_MST
ADCC_CSR_EOC_MST_ofs EQU 2
ADCC_CSR_EOC_MST_len EQU 1
ADCC_CSR_EOS_MST EQU 0x00000008 ; EOS_MST
ADCC_CSR_EOS_MST_ofs EQU 3
ADCC_CSR_EOS_MST_len EQU 1
ADCC_CSR_OVR_MST EQU 0x00000010 ; OVR_MST
ADCC_CSR_OVR_MST_ofs EQU 4
ADCC_CSR_OVR_MST_len EQU 1
ADCC_CSR_JEOC_MST EQU 0x00000020 ; JEOC_MST
ADCC_CSR_JEOC_MST_ofs EQU 5
ADCC_CSR_JEOC_MST_len EQU 1
ADCC_CSR_JEOS_MST EQU 0x00000040 ; JEOS_MST
ADCC_CSR_JEOS_MST_ofs EQU 6
ADCC_CSR_JEOS_MST_len EQU 1
ADCC_CSR_AWD1_MST EQU 0x00000080 ; AWD1_MST
ADCC_CSR_AWD1_MST_ofs EQU 7
ADCC_CSR_AWD1_MST_len EQU 1
ADCC_CSR_AWD2_MST EQU 0x00000100 ; AWD2_MST
ADCC_CSR_AWD2_MST_ofs EQU 8
ADCC_CSR_AWD2_MST_len EQU 1
ADCC_CSR_AWD3_MST EQU 0x00000200 ; AWD3_MST
ADCC_CSR_AWD3_MST_ofs EQU 9
ADCC_CSR_AWD3_MST_len EQU 1
ADCC_CSR_JQOVF_MST EQU 0x00000400 ; JQOVF_MST
ADCC_CSR_JQOVF_MST_ofs EQU 10
ADCC_CSR_JQOVF_MST_len EQU 1
ADCC_CSR_ADRDY_SLV EQU 0x00010000 ; ADRDY_SLV
ADCC_CSR_ADRDY_SLV_ofs EQU 16
ADCC_CSR_ADRDY_SLV_len EQU 1
ADCC_CSR_EOSMP_SLV EQU 0x00020000 ; EOSMP_SLV
ADCC_CSR_EOSMP_SLV_ofs EQU 17
ADCC_CSR_EOSMP_SLV_len EQU 1
ADCC_CSR_EOC_SLV EQU 0x00040000 ; End of regular conversion of the slave ADC
ADCC_CSR_EOC_SLV_ofs EQU 18
ADCC_CSR_EOC_SLV_len EQU 1
ADCC_CSR_EOS_SLV EQU 0x00080000 ; End of regular sequence flag of the slave ADC
ADCC_CSR_EOS_SLV_ofs EQU 19
ADCC_CSR_EOS_SLV_len EQU 1
ADCC_CSR_OVR_SLV EQU 0x00100000 ; Overrun flag of the slave ADC
ADCC_CSR_OVR_SLV_ofs EQU 20
ADCC_CSR_OVR_SLV_len EQU 1
ADCC_CSR_JEOC_SLV EQU 0x00200000 ; End of injected conversion flag of the slave ADC
ADCC_CSR_JEOC_SLV_ofs EQU 21
ADCC_CSR_JEOC_SLV_len EQU 1
ADCC_CSR_JEOS_SLV EQU 0x00400000 ; End of injected sequence flag of the slave ADC
ADCC_CSR_JEOS_SLV_ofs EQU 22
ADCC_CSR_JEOS_SLV_len EQU 1
ADCC_CSR_AWD1_SLV EQU 0x00800000 ; Analog watchdog 1 flag of the slave ADC
ADCC_CSR_AWD1_SLV_ofs EQU 23
ADCC_CSR_AWD1_SLV_len EQU 1
ADCC_CSR_AWD2_SLV EQU 0x01000000 ; Analog watchdog 2 flag of the slave ADC
ADCC_CSR_AWD2_SLV_ofs EQU 24
ADCC_CSR_AWD2_SLV_len EQU 1
ADCC_CSR_AWD3_SLV EQU 0x02000000 ; Analog watchdog 3 flag of the slave ADC
ADCC_CSR_AWD3_SLV_ofs EQU 25
ADCC_CSR_AWD3_SLV_len EQU 1
ADCC_CSR_JQOVF_SLV EQU 0x04000000 ; Injected Context Queue Overflow flag of the slave ADC
ADCC_CSR_JQOVF_SLV_ofs EQU 26
ADCC_CSR_JQOVF_SLV_len EQU 1
; ADC12_CCR fields:
ADCC_CCR_MULT EQU 0x0000001f ; Multi ADC mode selection
ADCC_CCR_MULT_ofs EQU 0
ADCC_CCR_MULT_len EQU 5
ADCC_CCR_DELAY EQU 0x00000f00 ; Delay between 2 sampling phases
ADCC_CCR_DELAY_ofs EQU 8
ADCC_CCR_DELAY_len EQU 4
ADCC_CCR_DMACFG EQU 0x00002000 ; DMA configuration (for multi-ADC mode)
ADCC_CCR_DMACFG_ofs EQU 13
ADCC_CCR_DMACFG_len EQU 1
ADCC_CCR_MDMA EQU 0x0000c000 ; Direct memory access mode for multi ADC mode
ADCC_CCR_MDMA_ofs EQU 14
ADCC_CCR_MDMA_len EQU 2
ADCC_CCR_CKMODE EQU 0x00030000 ; ADC clock mode
ADCC_CCR_CKMODE_ofs EQU 16
ADCC_CCR_CKMODE_len EQU 2
ADCC_CCR_VREFEN EQU 0x00400000 ; VREFINT enable
ADCC_CCR_VREFEN_ofs EQU 22
ADCC_CCR_VREFEN_len EQU 1
ADCC_CCR_TSEN EQU 0x00800000 ; Temperature sensor enable
ADCC_CCR_TSEN_ofs EQU 23
ADCC_CCR_TSEN_len EQU 1
ADCC_CCR_VBATEN EQU 0x01000000 ; VBAT enable
ADCC_CCR_VBATEN_ofs EQU 24
ADCC_CCR_VBATEN_len EQU 1
; ADC12_CDR fields:
ADCC_CDR_RDATA_SLV EQU 0xffff0000 ; Regular data of the slave ADC
ADCC_CDR_RDATA_SLV_ofs EQU 16
ADCC_CDR_RDATA_SLV_len EQU 16
ADCC_CDR_RDATA_MST EQU 0x0000ffff ; Regular data of the master ADC
ADCC_CDR_RDATA_MST_ofs EQU 0
ADCC_CDR_RDATA_MST_len EQU 16
; ---- ADC34 -------------------------------------------------
; Desc: None
; ADC34 base address:
ADC34_BASE EQU 0x50000700
; ADC34 registers:
ADC34_CSR EQU (ADC34_BASE + 0x0) ; ADC Common status register
ADC34_CCR EQU (ADC34_BASE + 0x8) ; ADC common control register
ADC34_CDR EQU (ADC34_BASE + 0xc) ; ADC common regular data register for dual and triple modes
; Fields the same as in the first instance.
; ---- SYSCFG ------------------------------------------------
; Desc: System configuration controller
; SYSCFG base address:
SYSCFG_BASE EQU 0x40010000
; SYSCFG registers:
SYSCFG_CFGR1 EQU (SYSCFG_BASE + 0x0) ; configuration register 1
SYSCFG_EXTICR1 EQU (SYSCFG_BASE + 0x8) ; external interrupt configuration register 1
SYSCFG_EXTICR2 EQU (SYSCFG_BASE + 0xc) ; external interrupt configuration register 2
SYSCFG_EXTICR3 EQU (SYSCFG_BASE + 0x10) ; external interrupt configuration register 3
SYSCFG_EXTICR4 EQU (SYSCFG_BASE + 0x14) ; external interrupt configuration register 4
SYSCFG_CFGR2 EQU (SYSCFG_BASE + 0x18) ; configuration register 2
SYSCFG_RCR EQU (SYSCFG_BASE + 0x4) ; CCM SRAM protection register
; SYSCFG_CFGR1 fields:
SYSCFG_CFGR1_MEM_MODE EQU 0x00000003 ; Memory mapping selection bits
SYSCFG_CFGR1_MEM_MODE_ofs EQU 0
SYSCFG_CFGR1_MEM_MODE_len EQU 2
SYSCFG_CFGR1_USB_IT_RMP EQU 0x00000020 ; USB interrupt remap
SYSCFG_CFGR1_USB_IT_RMP_ofs EQU 5
SYSCFG_CFGR1_USB_IT_RMP_len EQU 1
SYSCFG_CFGR1_TIM1_ITR_RMP EQU 0x00000040 ; Timer 1 ITR3 selection
SYSCFG_CFGR1_TIM1_ITR_RMP_ofs EQU 6
SYSCFG_CFGR1_TIM1_ITR_RMP_len EQU 1
SYSCFG_CFGR1_DAC_TRIG_RMP EQU 0x00000080 ; DAC trigger remap (when TSEL = 001)
SYSCFG_CFGR1_DAC_TRIG_RMP_ofs EQU 7
SYSCFG_CFGR1_DAC_TRIG_RMP_len EQU 1
SYSCFG_CFGR1_ADC24_DMA_RMP EQU 0x00000100 ; ADC24 DMA remapping bit
SYSCFG_CFGR1_ADC24_DMA_RMP_ofs EQU 8
SYSCFG_CFGR1_ADC24_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM16_DMA_RMP EQU 0x00000800 ; TIM16 DMA request remapping bit
SYSCFG_CFGR1_TIM16_DMA_RMP_ofs EQU 11
SYSCFG_CFGR1_TIM16_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM17_DMA_RMP EQU 0x00001000 ; TIM17 DMA request remapping bit
SYSCFG_CFGR1_TIM17_DMA_RMP_ofs EQU 12
SYSCFG_CFGR1_TIM17_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM6_DAC1_DMA_RMP EQU 0x00002000 ; TIM6 and DAC1 DMA request remapping bit
SYSCFG_CFGR1_TIM6_DAC1_DMA_RMP_ofs EQU 13
SYSCFG_CFGR1_TIM6_DAC1_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM7_DAC2_DMA_RMP EQU 0x00004000 ; TIM7 and DAC2 DMA request remapping bit
SYSCFG_CFGR1_TIM7_DAC2_DMA_RMP_ofs EQU 14
SYSCFG_CFGR1_TIM7_DAC2_DMA_RMP_len EQU 1
SYSCFG_CFGR1_I2C_PB6_FM EQU 0x00010000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB6_FM_ofs EQU 16
SYSCFG_CFGR1_I2C_PB6_FM_len EQU 1
SYSCFG_CFGR1_I2C_PB7_FM EQU 0x00020000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB7_FM_ofs EQU 17
SYSCFG_CFGR1_I2C_PB7_FM_len EQU 1
SYSCFG_CFGR1_I2C_PB8_FM EQU 0x00040000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB8_FM_ofs EQU 18
SYSCFG_CFGR1_I2C_PB8_FM_len EQU 1
SYSCFG_CFGR1_I2C_PB9_FM EQU 0x00080000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB9_FM_ofs EQU 19
SYSCFG_CFGR1_I2C_PB9_FM_len EQU 1
SYSCFG_CFGR1_I2C1_FM EQU 0x00100000 ; I2C1 Fast Mode Plus
SYSCFG_CFGR1_I2C1_FM_ofs EQU 20
SYSCFG_CFGR1_I2C1_FM_len EQU 1
SYSCFG_CFGR1_I2C2_FM EQU 0x00200000 ; I2C2 Fast Mode Plus
SYSCFG_CFGR1_I2C2_FM_ofs EQU 21
SYSCFG_CFGR1_I2C2_FM_len EQU 1
SYSCFG_CFGR1_ENCODER_MODE EQU 0x00c00000 ; Encoder mode
SYSCFG_CFGR1_ENCODER_MODE_ofs EQU 22
SYSCFG_CFGR1_ENCODER_MODE_len EQU 2
SYSCFG_CFGR1_FPU_IT EQU 0xfc000000 ; Interrupt enable bits from FPU
SYSCFG_CFGR1_FPU_IT_ofs EQU 26
SYSCFG_CFGR1_FPU_IT_len EQU 6
; SYSCFG_EXTICR1 fields:
SYSCFG_EXTICR1_EXTI3 EQU 0x0000f000 ; EXTI 3 configuration bits
SYSCFG_EXTICR1_EXTI3_ofs EQU 12
SYSCFG_EXTICR1_EXTI3_len EQU 4
SYSCFG_EXTICR1_EXTI2 EQU 0x00000f00 ; EXTI 2 configuration bits
SYSCFG_EXTICR1_EXTI2_ofs EQU 8
SYSCFG_EXTICR1_EXTI2_len EQU 4
SYSCFG_EXTICR1_EXTI1 EQU 0x000000f0 ; EXTI 1 configuration bits
SYSCFG_EXTICR1_EXTI1_ofs EQU 4
SYSCFG_EXTICR1_EXTI1_len EQU 4
SYSCFG_EXTICR1_EXTI0 EQU 0x0000000f ; EXTI 0 configuration bits
SYSCFG_EXTICR1_EXTI0_ofs EQU 0
SYSCFG_EXTICR1_EXTI0_len EQU 4
; SYSCFG_EXTICR2 fields:
SYSCFG_EXTICR2_EXTI7 EQU 0x0000f000 ; EXTI 7 configuration bits
SYSCFG_EXTICR2_EXTI7_ofs EQU 12
SYSCFG_EXTICR2_EXTI7_len EQU 4
SYSCFG_EXTICR2_EXTI6 EQU 0x00000f00 ; EXTI 6 configuration bits
SYSCFG_EXTICR2_EXTI6_ofs EQU 8
SYSCFG_EXTICR2_EXTI6_len EQU 4
SYSCFG_EXTICR2_EXTI5 EQU 0x000000f0 ; EXTI 5 configuration bits
SYSCFG_EXTICR2_EXTI5_ofs EQU 4
SYSCFG_EXTICR2_EXTI5_len EQU 4
SYSCFG_EXTICR2_EXTI4 EQU 0x0000000f ; EXTI 4 configuration bits
SYSCFG_EXTICR2_EXTI4_ofs EQU 0
SYSCFG_EXTICR2_EXTI4_len EQU 4
; SYSCFG_EXTICR3 fields:
SYSCFG_EXTICR3_EXTI11 EQU 0x0000f000 ; EXTI 11 configuration bits
SYSCFG_EXTICR3_EXTI11_ofs EQU 12
SYSCFG_EXTICR3_EXTI11_len EQU 4
SYSCFG_EXTICR3_EXTI10 EQU 0x00000f00 ; EXTI 10 configuration bits
SYSCFG_EXTICR3_EXTI10_ofs EQU 8
SYSCFG_EXTICR3_EXTI10_len EQU 4
SYSCFG_EXTICR3_EXTI9 EQU 0x000000f0 ; EXTI 9 configuration bits
SYSCFG_EXTICR3_EXTI9_ofs EQU 4
SYSCFG_EXTICR3_EXTI9_len EQU 4
SYSCFG_EXTICR3_EXTI8 EQU 0x0000000f ; EXTI 8 configuration bits
SYSCFG_EXTICR3_EXTI8_ofs EQU 0
SYSCFG_EXTICR3_EXTI8_len EQU 4
; SYSCFG_EXTICR4 fields:
SYSCFG_EXTICR4_EXTI15 EQU 0x0000f000 ; EXTI 15 configuration bits
SYSCFG_EXTICR4_EXTI15_ofs EQU 12
SYSCFG_EXTICR4_EXTI15_len EQU 4
SYSCFG_EXTICR4_EXTI14 EQU 0x00000f00 ; EXTI 14 configuration bits
SYSCFG_EXTICR4_EXTI14_ofs EQU 8
SYSCFG_EXTICR4_EXTI14_len EQU 4
SYSCFG_EXTICR4_EXTI13 EQU 0x000000f0 ; EXTI 13 configuration bits
SYSCFG_EXTICR4_EXTI13_ofs EQU 4
SYSCFG_EXTICR4_EXTI13_len EQU 4
SYSCFG_EXTICR4_EXTI12 EQU 0x0000000f ; EXTI 12 configuration bits
SYSCFG_EXTICR4_EXTI12_ofs EQU 0
SYSCFG_EXTICR4_EXTI12_len EQU 4
; SYSCFG_CFGR2 fields:
SYSCFG_CFGR2_LOCUP_LOCK EQU 0x00000001 ; Cortex-M0 LOCKUP bit enable bit
SYSCFG_CFGR2_LOCUP_LOCK_ofs EQU 0
SYSCFG_CFGR2_LOCUP_LOCK_len EQU 1
SYSCFG_CFGR2_SRAM_PARITY_LOCK EQU 0x00000002 ; SRAM parity lock bit
SYSCFG_CFGR2_SRAM_PARITY_LOCK_ofs EQU 1
SYSCFG_CFGR2_SRAM_PARITY_LOCK_len EQU 1
SYSCFG_CFGR2_PVD_LOCK EQU 0x00000004 ; PVD lock enable bit
SYSCFG_CFGR2_PVD_LOCK_ofs EQU 2
SYSCFG_CFGR2_PVD_LOCK_len EQU 1
SYSCFG_CFGR2_BYP_ADD_PAR EQU 0x00000010 ; Bypass address bit 29 in parity calculation
SYSCFG_CFGR2_BYP_ADD_PAR_ofs EQU 4
SYSCFG_CFGR2_BYP_ADD_PAR_len EQU 1
SYSCFG_CFGR2_SRAM_PEF EQU 0x00000100 ; SRAM parity flag
SYSCFG_CFGR2_SRAM_PEF_ofs EQU 8
SYSCFG_CFGR2_SRAM_PEF_len EQU 1
; SYSCFG_RCR fields:
SYSCFG_RCR_PAGE0_WP EQU 0x00000001 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE0_WP_ofs EQU 0
SYSCFG_RCR_PAGE0_WP_len EQU 1
SYSCFG_RCR_PAGE1_WP EQU 0x00000002 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE1_WP_ofs EQU 1
SYSCFG_RCR_PAGE1_WP_len EQU 1
SYSCFG_RCR_PAGE2_WP EQU 0x00000004 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE2_WP_ofs EQU 2
SYSCFG_RCR_PAGE2_WP_len EQU 1
SYSCFG_RCR_PAGE3_WP EQU 0x00000008 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE3_WP_ofs EQU 3
SYSCFG_RCR_PAGE3_WP_len EQU 1
SYSCFG_RCR_PAGE4_WP EQU 0x00000010 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE4_WP_ofs EQU 4
SYSCFG_RCR_PAGE4_WP_len EQU 1
SYSCFG_RCR_PAGE5_WP EQU 0x00000020 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE5_WP_ofs EQU 5
SYSCFG_RCR_PAGE5_WP_len EQU 1
SYSCFG_RCR_PAGE6_WP EQU 0x00000040 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE6_WP_ofs EQU 6
SYSCFG_RCR_PAGE6_WP_len EQU 1
SYSCFG_RCR_PAGE7_WP EQU 0x00000080 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE7_WP_ofs EQU 7
SYSCFG_RCR_PAGE7_WP_len EQU 1
; ---- OPAMP -------------------------------------------------
; Desc: Operational amplifier
; OPAMP base address:
OPAMP_BASE EQU 0x40010038
; OPAMP registers:
OPAMP1_CR EQU (OPAMP_BASE + 0x0) ; OPAMP1 control register
OPAMP2_CR EQU (OPAMP_BASE + 0x4) ; OPAMP2 control register
OPAMP3_CR EQU (OPAMP_BASE + 0x8) ; OPAMP3 control register
OPAMP4_CR EQU (OPAMP_BASE + 0xc) ; OPAMP4 control register
; OPAMP_OPAMP1_CR fields:
OPAMPx_CR_EN EQU 0x00000001 ; OPAMPx enable
OPAMPx_CR_EN_ofs EQU 0
OPAMPx_CR_EN_len EQU 1
OPAMPx_CR_FORCE_VP EQU 0x00000002 ; FORCE_VP
OPAMPx_CR_FORCE_VP_ofs EQU 1
OPAMPx_CR_FORCE_VP_len EQU 1
OPAMPx_CR_VP_SEL EQU 0x0000000c ; OPAMPx Non inverting input selection
OPAMPx_CR_VP_SEL_ofs EQU 2
OPAMPx_CR_VP_SEL_len EQU 2
OPAMPx_CR_VM_SEL EQU 0x00000060 ; OPAMPx inverting input selection
OPAMPx_CR_VM_SEL_ofs EQU 5
OPAMPx_CR_VM_SEL_len EQU 2
OPAMPx_CR_TCM_EN EQU 0x00000080 ; Timer controlled Mux mode enable
OPAMPx_CR_TCM_EN_ofs EQU 7
OPAMPx_CR_TCM_EN_len EQU 1
OPAMPx_CR_VMS_SEL EQU 0x00000100 ; OPAMPx inverting input secondary selection
OPAMPx_CR_VMS_SEL_ofs EQU 8
OPAMPx_CR_VMS_SEL_len EQU 1
OPAMPx_CR_VPS_SEL EQU 0x00000600 ; OPAMPx Non inverting input secondary selection
OPAMPx_CR_VPS_SEL_ofs EQU 9
OPAMPx_CR_VPS_SEL_len EQU 2
OPAMPx_CR_CALON EQU 0x00000800 ; Calibration mode enable
OPAMPx_CR_CALON_ofs EQU 11
OPAMPx_CR_CALON_len EQU 1
OPAMPx_CR_CALSEL EQU 0x00003000 ; Calibration selection
OPAMPx_CR_CALSEL_ofs EQU 12
OPAMPx_CR_CALSEL_len EQU 2
OPAMPx_CR_PGA_GAIN EQU 0x0003c000 ; Gain in PGA mode
OPAMPx_CR_PGA_GAIN_ofs EQU 14
OPAMPx_CR_PGA_GAIN_len EQU 4
OPAMPx_CR_USER_TRIM EQU 0x00040000 ; User trimming enable
OPAMPx_CR_USER_TRIM_ofs EQU 18
OPAMPx_CR_USER_TRIM_len EQU 1
OPAMPx_CR_TRIMOFFSETP EQU 0x00f80000 ; Offset trimming value (PMOS)
OPAMPx_CR_TRIMOFFSETP_ofs EQU 19
OPAMPx_CR_TRIMOFFSETP_len EQU 5
OPAMPx_CR_TRIMOFFSETN EQU 0x1f000000 ; Offset trimming value (NMOS)
OPAMPx_CR_TRIMOFFSETN_ofs EQU 24
OPAMPx_CR_TRIMOFFSETN_len EQU 5
OPAMPx_CR_TSTREF EQU 0x20000000 ; TSTREF
OPAMPx_CR_TSTREF_ofs EQU 29
OPAMPx_CR_TSTREF_len EQU 1
OPAMPx_CR_OUTCAL EQU 0x40000000 ; OPAMPx ouput status flag
OPAMPx_CR_OUTCAL_ofs EQU 30
OPAMPx_CR_OUTCAL_len EQU 1
OPAMPx_CR_LOCK EQU 0x80000000 ; OPAMPx lock
OPAMPx_CR_LOCK_ofs EQU 31
OPAMPx_CR_LOCK_len EQU 1
END
| 42.982213 | 127 | 0.644135 |
63217f3535b73afc034546eb7d8e72cf1f66413f | 2,101 | asm | Assembly | programs/oeis/192/A192023.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/192/A192023.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | programs/oeis/192/A192023.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | ; A192023: The Wiener index of the comb-shaped graph |_|_|...|_| with 2n (n>=1) nodes. The Wiener index of a connected graph is the sum of the distances between all unordered pairs of vertices in the graph.
; 1,10,31,68,125,206,315,456,633,850,1111,1420,1781,2198,2675,3216,3825,4506,5263,6100,7021,8030,9131,10328,11625,13026,14535,16156,17893,19750,21731,23840,26081,28458,30975,33636,36445,39406,42523,45800,49241,52850,56631,60588,64725,69046,73555,78256,83153,88250,93551,99060,104781,110718,116875,123256,129865,136706,143783,151100,158661,166470,174531,182848,191425,200266,209375,218756,228413,238350,248571,259080,269881,280978,292375,304076,316085,328406,341043,354000,367281,380890,394831,409108,423725,438686,453995,469656,485673,502050,518791,535900,553381,571238,589475,608096,627105,646506,666303,686500,707101,728110,749531,771368,793625,816306,839415,862956,886933,911350,936211,961520,987281,1013498,1040175,1067316,1094925,1123006,1151563,1180600,1210121,1240130,1270631,1301628,1333125,1365126,1397635,1430656,1464193,1498250,1532831,1567940,1603581,1639758,1676475,1713736,1751545,1789906,1828823,1868300,1908341,1948950,1990131,2031888,2074225,2117146,2160655,2204756,2249453,2294750,2340651,2387160,2434281,2482018,2530375,2579356,2628965,2679206,2730083,2781600,2833761,2886570,2940031,2994148,3048925,3104366,3160475,3217256,3274713,3332850,3391671,3451180,3511381,3572278,3633875,3696176,3759185,3822906,3887343,3952500,4018381,4084990,4152331,4220408,4289225,4358786,4429095,4500156,4571973,4644550,4717891,4792000,4866881,4942538,5018975,5096196,5174205,5253006,5332603,5413000,5494201,5576210,5659031,5742668,5827125,5912406,5998515,6085456,6173233,6261850,6351311,6441620,6532781,6624798,6717675,6811416,6906025,7001506,7097863,7195100,7293221,7392230,7492131,7592928,7694625,7797226,7900735,8005156,8110493,8216750,8323931,8432040,8541081,8651058,8761975,8873836,8986645,9100406,9215123,9330800,9447441,9565050,9683631,9803188,9923725,10045246,10167755,10291256,10415753,10541250
mov $1,1
lpb $0
add $2,4
add $2,$0
sub $0,1
add $1,$2
sub $2,1
add $1,$2
lpe
| 161.615385 | 1,803 | 0.831985 |
447e3141a23eac5d4a8d5e5b2675350570ccfdcb | 81,148 | asm | Assembly | src/presets/routeb_data.asm | rioscrodrigo/sm_practice_hack | a52823862ba1880b603029df4adc5afc3df5a171 | [
"Unlicense"
] | null | null | null | src/presets/routeb_data.asm | rioscrodrigo/sm_practice_hack | a52823862ba1880b603029df4adc5afc3df5a171 | [
"Unlicense"
] | null | null | null | src/presets/routeb_data.asm | rioscrodrigo/sm_practice_hack | a52823862ba1880b603029df4adc5afc3df5a171 | [
"Unlicense"
] | null | null | null |
preset_routeb_crateria_ship:
dw #$0000
dl $7E078B : db $02 : dw $0000 ; Elevator Index
dl $7E078D : db $02 : dw $88FE ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $91F8 ; MDB
dl $7E079F : db $02 : dw $0000 ; Region
dl $7E07C3 : db $02 : dw $C629 ; GFX Pointers
dl $7E07C5 : db $02 : dw $7CBA ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2AD ; GFX Pointers
dl $7E07F3 : db $02 : dw $0006 ; Music Bank
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $C000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $03FA ; Screen X position in pixels
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $03D3 ; Screen Y position in pixels
dl $7E093F : db $02 : dw $0000 ; Ceres escape flag
dl $7E09A2 : db $02 : dw $0000 ; Equipped Items
dl $7E09A4 : db $02 : dw $0000 ; Collected Items
dl $7E09A6 : db $02 : dw $0000 ; Beams
dl $7E09A8 : db $02 : dw $0000 ; Beams
dl $7E09C0 : db $02 : dw $0000 ; Manual/Auto reserve tank
dl $7E09C2 : db $02 : dw $0063 ; Health
dl $7E09C4 : db $02 : dw $0063 ; Max helath
dl $7E09C6 : db $02 : dw $0000 ; Missiles
dl $7E09C8 : db $02 : dw $0000 ; Max missiles
dl $7E09CA : db $02 : dw $0000 ; Supers
dl $7E09CC : db $02 : dw $0000 ; Max supers
dl $7E09CE : db $02 : dw $0000 ; Pbs
dl $7E09D0 : db $02 : dw $0000 ; Max pbs
dl $7E09D4 : db $02 : dw $0000 ; Max reserves
dl $7E09D6 : db $02 : dw $0000 ; Reserves
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0A68 : db $02 : dw $0000 ; Flash suit
dl $7E0A76 : db $02 : dw $0000 ; Hyper beam
dl $7E0AF6 : db $02 : dw $047E ; Samus X
dl $7E0AFA : db $02 : dw $0443 ; Samus Y
dl $7E0B3F : db $02 : dw $0000 ; Blue suit
dl $7ED7C0 : db $02 : dw $0000 ; SRAM copy
dl $7ED7C2 : db $02 : dw $0000 ; SRAM copy
dl $7ED7C4 : db $02 : dw $0000 ; SRAM copy
dl $7ED7C6 : db $02 : dw $0000 ; SRAM copy
dl $7ED7C8 : db $02 : dw $0800 ; SRAM copy
dl $7ED7CA : db $02 : dw $0400 ; SRAM copy
dl $7ED7CC : db $02 : dw $0200 ; SRAM copy
dl $7ED7CE : db $02 : dw $0100 ; SRAM copy
dl $7ED7D0 : db $02 : dw $0040 ; SRAM copy
dl $7ED7D2 : db $02 : dw $0080 ; SRAM copy
dl $7ED7D4 : db $02 : dw $8000 ; SRAM copy
dl $7ED7D6 : db $02 : dw $2000 ; SRAM copy
dl $7ED7D8 : db $02 : dw $4000 ; SRAM copy
dl $7ED7DA : db $02 : dw $0020 ; SRAM copy
dl $7ED7DC : db $02 : dw $0010 ; SRAM copy
dl $7ED7DE : db $02 : dw $0000 ; SRAM copy
dl $7ED7E0 : db $02 : dw $0063 ; SRAM copy
dl $7ED7E2 : db $02 : dw $0063 ; SRAM copy
dl $7ED7E4 : db $02 : dw $0000 ; SRAM copy
dl $7ED7E6 : db $02 : dw $0000 ; SRAM copy
dl $7ED7E8 : db $02 : dw $0000 ; SRAM copy
dl $7ED7EA : db $02 : dw $0000 ; SRAM copy
dl $7ED7EC : db $02 : dw $0000 ; SRAM copy
dl $7ED7EE : db $02 : dw $0000 ; SRAM copy
dl $7ED7F0 : db $02 : dw $0000 ; SRAM copy
dl $7ED7F2 : db $02 : dw $0000 ; SRAM copy
dl $7ED7F4 : db $02 : dw $0000 ; SRAM copy
dl $7ED7F6 : db $02 : dw $0000 ; SRAM copy
dl $7ED7F8 : db $02 : dw $0039 ; SRAM copy
dl $7ED7FA : db $02 : dw $0012 ; SRAM copy
dl $7ED7FC : db $02 : dw $0001 ; SRAM copy
dl $7ED7FE : db $02 : dw $0000 ; SRAM copy
dl $7ED800 : db $02 : dw $0000 ; SRAM copy
dl $7ED802 : db $02 : dw $0001 ; SRAM copy
dl $7ED804 : db $02 : dw $0001 ; SRAM copy
dl $7ED806 : db $02 : dw $0001 ; SRAM copy
dl $7ED808 : db $02 : dw $0000 ; SRAM copy
dl $7ED80A : db $02 : dw $0000 ; SRAM copy
dl $7ED80C : db $02 : dw $0000 ; SRAM copy
dl $7ED80E : db $02 : dw $0000 ; SRAM copy
dl $7ED810 : db $02 : dw $0000 ; SRAM copy
dl $7ED812 : db $02 : dw $0000 ; SRAM copy
dl $7ED814 : db $02 : dw $0000 ; SRAM copy
dl $7ED816 : db $02 : dw $0000 ; SRAM copy
dl $7ED818 : db $02 : dw $0000 ; SRAM copy
dl $7ED81A : db $02 : dw $0000 ; SRAM copy
dl $7ED81C : db $02 : dw $0000 ; SRAM copy
dl $7ED81E : db $02 : dw $0000 ; SRAM copy
dl $7ED820 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED822 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED824 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED826 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED828 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED82A : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED82C : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED82E : db $02 : dw $0001 ; Events, Items, Doors
dl $7ED830 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED832 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED834 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED836 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED838 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED83A : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED83C : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED83E : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED840 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED842 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED844 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED846 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED848 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED84A : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED84C : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED84E : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED850 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED852 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED854 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED856 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED858 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED85A : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED85C : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED85E : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED860 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED862 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED864 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED866 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED868 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED86A : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED86C : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED86E : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED870 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED872 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED874 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED876 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED878 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED87A : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED87C : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED87E : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED880 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED882 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED884 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED886 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED888 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED88A : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED88C : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED88E : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED890 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED892 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED894 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED896 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED898 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED89A : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED89C : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED89E : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8A0 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8A2 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8A4 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8A6 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8A8 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8AA : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8AC : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8AE : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8B0 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8B2 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8B4 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8B6 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8B8 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8BA : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8BC : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8BE : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8C0 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8C2 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8C4 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8C6 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8C8 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8CA : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8CC : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8CE : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8D0 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8D2 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8D4 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8D6 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8D8 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8DA : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8DC : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8DE : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8E0 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8E2 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8E4 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8E6 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8E8 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8EA : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8EC : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8EE : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8F0 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8F2 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8F4 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8F6 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8F8 : db $02 : dw $0001 ; Events, Items, Doors
dl $7ED8FA : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8FC : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED8FE : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED900 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED902 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED904 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED906 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED908 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED90A : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED90C : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED90E : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED910 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED912 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED914 : db $02 : dw $0005 ; Events, Items, Doors
dl $7ED916 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED918 : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED91C : db $02 : dw $0000 ; Events, Items, Doors
dl $7ED91E : db $02 : dw $0000 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_crateria_morph:
dw #preset_routeb_crateria_ship ; Crateria: Ship
dl $7E078D : db $02 : dw $8976 ; DDB
dl $7E078F : db $02 : dw $0002 ; DoorOut Index
dl $7E079B : db $02 : dw $92B3 ; MDB
dl $7E090F : db $02 : dw $9800 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0100 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $0400 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0200 ; Screen Y position in pixels
dl $7E0AF6 : db $02 : dw $0134 ; Samus X
dl $7E0AFA : db $02 : dw $028B ; Samus Y
dl $7ED91A : db $02 : dw $0002 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_crateria_elevator:
dw #preset_routeb_crateria_morph ; Crateria: Morph
dl $7E078D : db $02 : dw $8B9E ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $9E9F ; MDB
dl $7E079F : db $02 : dw $0001 ; Region
dl $7E07C3 : db $02 : dw $E6B0 ; GFX Pointers
dl $7E07C5 : db $02 : dw $64BB ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B2 ; GFX Pointers
dl $7E07F5 : db $02 : dw $0007 ; Music Track
dl $7E090F : db $02 : dw $E000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0248 ; Screen Y position in pixels
dl $7E09A2 : db $02 : dw $0004 ; Equipped Items
dl $7E09A4 : db $02 : dw $0004 ; Collected Items
dl $7E0A1C : db $02 : dw $0000 ; Samus position/state
dl $7E0A1E : db $02 : dw $0000 ; More position/state
dl $7E0AF6 : db $02 : dw $0180 ; Samus X
dl $7E0AFA : db $02 : dw $02B8 ; Samus Y
dl $7ED870 : db $02 : dw $0002 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0003 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_crateria_elevator_2:
dw #preset_routeb_crateria_elevator ; Crateria: Elevator
dl $7E078D : db $02 : dw $8EB6 ; DDB
dl $7E078F : db $02 : dw $0002 ; DoorOut Index
dl $7E079B : db $02 : dw $97B5 ; MDB
dl $7E079F : db $02 : dw $0000 ; Region
dl $7E07C3 : db $02 : dw $F911 ; GFX Pointers
dl $7E07C5 : db $02 : dw $43BA ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2AF ; GFX Pointers
dl $7E07F5 : db $02 : dw $0003 ; Music Track
dl $7E090F : db $02 : dw $9000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C6 : db $02 : dw $0005 ; Missiles
dl $7E09C8 : db $02 : dw $0005 ; Max missiles
dl $7E0AF6 : db $02 : dw $0080 ; Samus X
dl $7E0AFA : db $02 : dw $0088 ; Samus Y
dl $7ED870 : db $02 : dw $0082 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0008 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_crateria_climb:
dw #preset_routeb_crateria_elevator_2 ; Crateria: Elevator 2
dl $7E078D : db $02 : dw $8B4A ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $96BA ; MDB
dl $7E07C3 : db $02 : dw $C629 ; GFX Pointers
dl $7E07C5 : db $02 : dw $7CBA ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2AD ; GFX Pointers
dl $7E07F3 : db $02 : dw $0009 ; Music Bank
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $E000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0700 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $3000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0200 ; Screen Y position in pixels
dl $7E09C6 : db $02 : dw $0004 ; Missiles
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $07C4 ; Samus X
dl $7E0AFA : db $02 : dw $028B ; Samus Y
dl $7ED820 : db $02 : dw $0001 ; Events, Items, Doors
dl $7ED8B0 : db $02 : dw $0100 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_crateria_bomb_torizo:
dw #preset_routeb_crateria_climb ; Crateria: Climb
dl $7E078D : db $02 : dw $8C82 ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $86EE ; MDB
dl $7E07F3 : db $02 : dw $0006 ; Music Bank
dl $7E07F5 : db $02 : dw $0006 ; Music Track
dl $7E090F : db $02 : dw $6000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0300 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0054 ; Health
dl $7E09C6 : db $02 : dw $0000 ; Missiles
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $004E ; Samus X
dl $7E0AFA : db $02 : dw $039B ; Samus Y
dl $7ED8B0 : db $02 : dw $0102 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $000D ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_brinstar_green_brinstar_elevator:
dw #preset_routeb_crateria_bomb_torizo ; Crateria: Bomb Torizo
dl $7E078D : db $02 : dw $8C0A ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $9AD9 ; MDB
dl $7E079F : db $02 : dw $0001 ; Region
dl $7E07C3 : db $02 : dw $E6B0 ; GFX Pointers
dl $7E07C5 : db $02 : dw $64BB ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B2 ; GFX Pointers
dl $7E07F3 : db $02 : dw $000F ; Music Bank
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $8000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0300 ; Screen X position in pixels
dl $7E0915 : db $02 : dw $0200 ; Screen Y position in pixels
dl $7E09A2 : db $02 : dw $1004 ; Equipped Items
dl $7E09A4 : db $02 : dw $1004 ; Collected Items
dl $7E09C2 : db $02 : dw $0063 ; Health
dl $7E0A1C : db $02 : dw $0000 ; Samus position/state
dl $7E0A1E : db $02 : dw $0000 ; More position/state
dl $7E0AF6 : db $02 : dw $0380 ; Samus X
dl $7E0AFA : db $02 : dw $0299 ; Samus Y
dl $7ED828 : db $02 : dw $0004 ; Events, Items, Doors
dl $7ED870 : db $02 : dw $4082 ; Events, Items, Doors
dl $7ED8B0 : db $02 : dw $0112 ; Events, Items, Doors
dl $7ED8B2 : db $02 : dw $0001 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0014 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_brinstar_sporespawn:
dw #preset_routeb_brinstar_green_brinstar_elevator ; Brinstar: Green Brinstar Elevator
dl $7E078D : db $02 : dw $8F3A ; DDB
dl $7E079B : db $02 : dw $9D19 ; MDB
dl $7E090F : db $02 : dw $B400 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $0FFF ; Screen subpixel Y position
dl $7E09C2 : db $02 : dw $0040 ; Health
dl $7E09C6 : db $02 : dw $000A ; Missiles
dl $7E09C8 : db $02 : dw $000A ; Max missiles
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $0031 ; Samus X
dl $7E0AFA : db $02 : dw $029B ; Samus Y
dl $7ED872 : db $02 : dw $0004 ; Events, Items, Doors
dl $7ED8B2 : db $02 : dw $0011 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0018 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_brinstar_green_hill:
dw #preset_routeb_brinstar_sporespawn ; Brinstar: SporeSpawn
dl $7E078D : db $02 : dw $8DC6 ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $9CB3 ; MDB
dl $7E090F : db $02 : dw $3000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0600 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $F800 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $001F ; Screen Y position in pixels
dl $7E09A6 : db $02 : dw $1000 ; Beams
dl $7E09A8 : db $02 : dw $1000 ; Beams
dl $7E09C2 : db $02 : dw $0045 ; Health
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $06D0 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED828 : db $02 : dw $0204 ; Events, Items, Doors
dl $7ED872 : db $02 : dw $0006 ; Events, Items, Doors
dl $7ED8B2 : db $02 : dw $1011 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $001E ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_brinstar_springball:
dw #preset_routeb_brinstar_green_hill ; Brinstar: Green Hill
dl $7E078D : db $02 : dw $8FD6 ; DDB
dl $7E079B : db $02 : dw $9AD9 ; MDB
dl $7E090F : db $02 : dw $0FFF ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0021 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $004F ; Health
dl $7E0AF6 : db $02 : dw $06C5 ; Samus X
dl $7ED91A : db $02 : dw $001F ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_brinstar_spikeway:
dw #preset_routeb_brinstar_springball ; Brinstar: SpringBall
dl $7E078D : db $02 : dw $8EFE ; DDB
dl $7E079B : db $02 : dw $A0A4 ; MDB
dl $7E090F : db $02 : dw $6000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $3000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0100 ; Screen Y position in pixels
dl $7E09A2 : db $02 : dw $1006 ; Equipped Items
dl $7E09A4 : db $02 : dw $1006 ; Collected Items
dl $7E09C2 : db $02 : dw $0046 ; Health
dl $7E09C6 : db $02 : dw $0005 ; Missiles
dl $7E0AF6 : db $02 : dw $00C9 ; Samus X
dl $7E0AFA : db $02 : dw $018B ; Samus Y
dl $7ED874 : db $02 : dw $0001 ; Events, Items, Doors
dl $7ED8B4 : db $02 : dw $0140 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0022 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_brinstar_red_brinstar:
dw #preset_routeb_brinstar_spikeway ; Brinstar: SpikeWay
dl $7E078D : db $02 : dw $9096 ; DDB
dl $7E079B : db $02 : dw $9C5E ; MDB
dl $7E090F : db $02 : dw $1000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0200 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $4C00 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0063 ; Health
dl $7E09C6 : db $02 : dw $0007 ; Missiles
dl $7E0AF6 : db $02 : dw $02C9 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED91A : db $02 : dw $0024 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_brinstar_etank_hallway:
dw #preset_routeb_brinstar_red_brinstar ; Brinstar: Red Brinstar
dl $7E078D : db $02 : dw $9132 ; DDB
dl $7E079B : db $02 : dw $A322 ; MDB
dl $7E07C3 : db $02 : dw $A5AA ; GFX Pointers
dl $7E07C5 : db $02 : dw $5FBC ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B3 ; GFX Pointers
dl $7E07F3 : db $02 : dw $0012 ; Music Bank
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $7C00 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $054C ; Screen Y position in pixels
dl $7E09A2 : db $02 : dw $1007 ; Equipped Items
dl $7E09A4 : db $02 : dw $1007 ; Collected Items
dl $7E09C2 : db $02 : dw $0036 ; Health
dl $7E09C6 : db $02 : dw $0008 ; Missiles
dl $7E09C8 : db $02 : dw $000F ; Max missiles
dl $7E0AF6 : db $02 : dw $00C6 ; Samus X
dl $7E0AFA : db $02 : dw $05BB ; Samus Y
dl $7ED874 : db $02 : dw $0015 ; Events, Items, Doors
dl $7ED8B4 : db $02 : dw $0340 ; Events, Items, Doors
dl $7ED8C2 : db $02 : dw $0001 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0029 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_brinstar_kraids_lair:
dw #preset_routeb_brinstar_etank_hallway ; Brinstar: E-Tank Hallway
dl $7E078D : db $02 : dw $AEDA ; DDB
dl $7E078F : db $02 : dw $0005 ; DoorOut Index
dl $7E079B : db $02 : dw $A471 ; MDB
dl $7E090F : db $02 : dw $A000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0200 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $011F ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $00B8 ; Health
dl $7E09C4 : db $02 : dw $00C7 ; Max helath
dl $7E09C6 : db $02 : dw $000B ; Missiles
dl $7E0AF6 : db $02 : dw $02CC ; Samus X
dl $7E0AFA : db $02 : dw $018B ; Samus Y
dl $7ED874 : db $02 : dw $0017 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $002C ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_brinstar_kraid:
dw #preset_routeb_brinstar_kraids_lair ; Brinstar: Kraids Lair
dl $7E078D : db $02 : dw $919E ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $A56B ; MDB
dl $7E07F3 : db $02 : dw $0027 ; Music Bank
dl $7E07F5 : db $02 : dw $0006 ; Music Track
dl $7E090F : db $02 : dw $0000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0100 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $3800 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0100 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $00BF ; Health
dl $7E0AF6 : db $02 : dw $01CD ; Samus X
dl $7ED8B4 : db $02 : dw $8340 ; Events, Items, Doors
dl $7ED8B6 : db $02 : dw $0004 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_brinstar_water_tank:
dw #preset_routeb_brinstar_kraid ; Brinstar: Kraid
dl $7E078D : db $02 : dw $913E ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $A253 ; MDB
dl $7E07F3 : db $02 : dw $0012 ; Music Bank
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $AFFF ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $CBFF ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0508 ; Screen Y position in pixels
dl $7E09A2 : db $02 : dw $1107 ; Equipped Items
dl $7E09A4 : db $02 : dw $1107 ; Collected Items
dl $7E09C2 : db $02 : dw $00BD ; Health
dl $7E09C6 : db $02 : dw $0008 ; Missiles
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $0039 ; Samus X
dl $7E0AFA : db $02 : dw $058B ; Samus Y
dl $7ED828 : db $02 : dw $0304 ; Events, Items, Doors
dl $7ED874 : db $02 : dw $0037 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $002E ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_upper_norfair_elevator:
dw #preset_routeb_brinstar_water_tank ; Brinstar: Water Tank
dl $7E078D : db $02 : dw $9246 ; DDB
dl $7E078F : db $02 : dw $0002 ; DoorOut Index
dl $7E079B : db $02 : dw $A7DE ; MDB
dl $7E079F : db $02 : dw $0002 ; Region
dl $7E07C3 : db $02 : dw $C3F9 ; GFX Pointers
dl $7E07C5 : db $02 : dw $BBBD ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B6 ; GFX Pointers
dl $7E07F3 : db $02 : dw $0015 ; Music Bank
dl $7E090F : db $02 : dw $0000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0219 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0090 ; Health
dl $7E09C6 : db $02 : dw $000E ; Missiles
dl $7E0A1C : db $02 : dw $009B ; Samus position/state
dl $7E0A1E : db $02 : dw $0000 ; More position/state
dl $7E0AF6 : db $02 : dw $0080 ; Samus X
dl $7E0AFA : db $02 : dw $0289 ; Samus Y
dl $7ED91A : db $02 : dw $0030 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_hot_spring:
dw #preset_routeb_upper_norfair_upper_norfair_elevator ; Upper Norfair: Upper Norfair Elevator
dl $7E078D : db $02 : dw $9282 ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $A8F8 ; MDB
dl $7E090F : db $02 : dw $B000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $3000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0600 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $006D ; Health
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $003E ; Samus X
dl $7E0AFA : db $02 : dw $068B ; Samus Y
dl $7ED91A : db $02 : dw $0031 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_super_missiles:
dw #preset_routeb_upper_norfair_hot_spring ; Upper Norfair: Hot Spring
dl $7E078D : db $02 : dw $944A ; DDB
dl $7E078F : db $02 : dw $0002 ; DoorOut Index
dl $7E079B : db $02 : dw $A9E5 ; MDB
dl $7E07C5 : db $02 : dw $E4BD ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B5 ; GFX Pointers
dl $7E07F5 : db $02 : dw $0003 ; Music Track
dl $7E090F : db $02 : dw $3000 ; Screen subpixel X position.
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0063 ; Health
dl $7E09C6 : db $02 : dw $0006 ; Missiles
dl $7E09CA : db $02 : dw $0005 ; Supers
dl $7E09CC : db $02 : dw $0005 ; Max supers
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $007C ; Samus X
dl $7E0AFA : db $02 : dw $00AB ; Samus Y
dl $7ED876 : db $02 : dw $0010 ; Events, Items, Doors
dl $7ED8B8 : db $02 : dw $0008 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0032 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_unknown:
dw #preset_routeb_upper_norfair_super_missiles ; Upper Norfair: Super Missiles
dl $7E078D : db $02 : dw $AFC2 ; DDB
dl $7E079B : db $02 : dw $A923 ; MDB
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $5000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $9BFF ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0300 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $012B ; Health
dl $7E09C4 : db $02 : dw $012B ; Max helath
dl $7E09C6 : db $02 : dw $000F ; Missiles
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $0036 ; Samus X
dl $7E0AFA : db $02 : dw $038B ; Samus Y
dl $7ED876 : db $02 : dw $0050 ; Events, Items, Doors
dl $7ED8B8 : db $02 : dw $0018 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0034 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_road_to_ice_beam:
dw #preset_routeb_upper_norfair_unknown ; Upper Norfair: Unknown
dl $7E078D : db $02 : dw $973E ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $A7DE ; MDB
dl $7E07C5 : db $02 : dw $BBBD ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B6 ; GFX Pointers
dl $7E090F : db $02 : dw $FB80 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $3C00 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0211 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $00E7 ; Health
dl $7E09CA : db $02 : dw $0004 ; Supers
dl $7E0AF6 : db $02 : dw $004F ; Samus X
dl $7E0AFA : db $02 : dw $028B ; Samus Y
dl $7ED8B8 : db $02 : dw $0058 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0035 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_the_four_horsemen:
dw #preset_routeb_upper_norfair_road_to_ice_beam ; Upper Norfair: Road to Ice Beam
dl $7E090F : db $02 : dw $7000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $4000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0513 ; Screen Y position in pixels
dl $7E09A6 : db $02 : dw $1002 ; Beams
dl $7E09A8 : db $02 : dw $1002 ; Beams
dl $7E09C2 : db $02 : dw $0107 ; Health
dl $7E09CA : db $02 : dw $0005 ; Supers
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $00B2 ; Samus X
dl $7E0AFA : db $02 : dw $059B ; Samus Y
dl $7ED876 : db $02 : dw $0052 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0037 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_bubble_mountain_supers:
dw #preset_routeb_upper_norfair_the_four_horsemen ; Upper Norfair: The Four Horsemen
dl $7E078D : db $02 : dw $9582 ; DDB
dl $7E078F : db $02 : dw $0004 ; DoorOut Index
dl $7E079B : db $02 : dw $AB07 ; MDB
dl $7E07C5 : db $02 : dw $E4BD ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B5 ; GFX Pointers
dl $7E090F : db $02 : dw $D000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0129 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $012B ; Health
dl $7E09CA : db $02 : dw $0009 ; Supers
dl $7E09CC : db $02 : dw $000A ; Max supers
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $003A ; Samus X
dl $7E0AFA : db $02 : dw $01BB ; Samus Y
dl $7ED876 : db $02 : dw $1052 ; Events, Items, Doors
dl $7ED8B8 : db $02 : dw $2458 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0038 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_blue_gate_glich:
dw #preset_routeb_upper_norfair_bubble_mountain_supers ; Upper Norfair: Bubble Mountain Supers
dl $7E078D : db $02 : dw $955E ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E090F : db $02 : dw $F000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $BC00 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0402 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0112 ; Health
dl $7E09CA : db $02 : dw $000A ; Supers
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $00CE ; Samus X
dl $7E0AFA : db $02 : dw $048B ; Samus Y
dl $7ED91A : db $02 : dw $0039 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_speed_way:
dw #preset_routeb_upper_norfair_blue_gate_glich ; Upper Norfair: Blue Gate Glich
dl $7E078D : db $02 : dw $95B2 ; DDB
dl $7E079B : db $02 : dw $AD1B ; MDB
dl $7E07F5 : db $02 : dw $0003 ; Music Track
dl $7E090F : db $02 : dw $D000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $1C00 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09A2 : db $02 : dw $3107 ; Equipped Items
dl $7E09A4 : db $02 : dw $3107 ; Collected Items
dl $7E09C2 : db $02 : dw $012B ; Health
dl $7E09CA : db $02 : dw $0009 ; Supers
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $002E ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED876 : db $02 : dw $9052 ; Events, Items, Doors
dl $7ED8BA : db $02 : dw $0002 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $003A ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_speed_ball:
dw #preset_routeb_upper_norfair_speed_way ; Upper Norfair: Speed Way
dl $7E078D : db $02 : dw $955E ; DDB
dl $7E079B : db $02 : dw $AB07 ; MDB
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $0000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $BC00 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0200 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $00EF ; Health
dl $7E09C6 : db $02 : dw $0005 ; Missiles
dl $7E09CA : db $02 : dw $000A ; Supers
dl $7E0AF6 : db $02 : dw $0033 ; Samus X
dl $7E0AFA : db $02 : dw $025B ; Samus Y
dl $7ED822 : db $02 : dw $0020 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $003C ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_zero_mission:
dw #preset_routeb_upper_norfair_speed_ball ; Upper Norfair: Speed Ball
dl $7E078D : db $02 : dw $928E ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $B026 ; MDB
dl $7E07C3 : db $02 : dw $860B ; GFX Pointers
dl $7E07C5 : db $02 : dw $58C0 ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2BE ; GFX Pointers
dl $7E090F : db $02 : dw $E000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $7400 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $00CA ; Health
dl $7E0AF6 : db $02 : dw $0036 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED91A : db $02 : dw $003F ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_energy_spark:
dw #preset_routeb_upper_norfair_zero_mission ; Upper Norfair: Zero Mission
dl $7E078D : db $02 : dw $973E ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $A7DE ; MDB
dl $7E07C3 : db $02 : dw $C3F9 ; GFX Pointers
dl $7E07C5 : db $02 : dw $BBBD ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B6 ; GFX Pointers
dl $7E090F : db $02 : dw $9000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $3800 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0320 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $00FD ; Health
dl $7E09C6 : db $02 : dw $000F ; Missiles
dl $7E09CA : db $02 : dw $0009 ; Supers
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $00B6 ; Samus X
dl $7E0AFA : db $02 : dw $039B ; Samus Y
dl $7ED8B6 : db $02 : dw $2004 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_spark_again:
dw #preset_routeb_upper_norfair_energy_spark ; Upper Norfair: Energy Spark
dl $7E078D : db $02 : dw $94CE ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $A815 ; MDB
dl $7E090F : db $02 : dw $6000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0500 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $0400 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $002A ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $00F4 ; Health
dl $7E09C4 : db $02 : dw $01F3 ; Max helath
dl $7E09C6 : db $02 : dw $0004 ; Missiles
dl $7E0AF6 : db $02 : dw $05C5 ; Samus X
dl $7E0AFA : db $02 : dw $00BB ; Samus Y
dl $7ED872 : db $02 : dw $0007 ; Events, Items, Doors
dl $7ED876 : db $02 : dw $9056 ; Events, Items, Doors
dl $7ED8B8 : db $02 : dw $245A ; Events, Items, Doors
dl $7ED8BA : db $02 : dw $0006 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0041 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_grapplebeam:
dw #preset_routeb_upper_norfair_spark_again ; Upper Norfair: Spark Again
dl $7E078D : db $02 : dw $B0B0 ; DDB
dl $7E078F : db $02 : dw $0003 ; DoorOut Index
dl $7E079B : db $02 : dw $B192 ; MDB
dl $7E07C5 : db $02 : dw $E4BD ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B5 ; GFX Pointers
dl $7E090F : db $02 : dw $E000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0600 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $8400 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $039C ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01A8 ; Health
dl $7E09C6 : db $02 : dw $000C ; Missiles
dl $7E09CA : db $02 : dw $000A ; Supers
dl $7E0AF6 : db $02 : dw $069B ; Samus X
dl $7E0AFA : db $02 : dw $042B ; Samus Y
dl $7ED8BA : db $02 : dw $000E ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0043 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_grapple_way:
dw #preset_routeb_upper_norfair_grapplebeam ; Upper Norfair: GrappleBeam
dl $7E078D : db $02 : dw $97F2 ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E090F : db $02 : dw $3000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $04C8 ; Screen Y position in pixels
dl $7E09A2 : db $02 : dw $7107 ; Equipped Items
dl $7E09A4 : db $02 : dw $7107 ; Collected Items
dl $7E09C2 : db $02 : dw $016C ; Health
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $062E ; Samus X
dl $7E0AFA : db $02 : dw $055B ; Samus Y
dl $7ED878 : db $02 : dw $0004 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0044 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_upper_norfair_the_real_bubble_mountain:
dw #preset_routeb_upper_norfair_grapple_way ; Upper Norfair: Grapple Way
dl $7E078D : db $02 : dw $9762 ; DDB
dl $7E078F : db $02 : dw $0002 ; DoorOut Index
dl $7E079B : db $02 : dw $B0DD ; MDB
dl $7E090F : db $02 : dw $4000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $8000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0024 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01F3 ; Health
dl $7E09C6 : db $02 : dw $000F ; Missiles
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $06CE ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED91A : db $02 : dw $0046 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_maridia_elevator:
dw #preset_routeb_upper_norfair_the_real_bubble_mountain ; Upper Norfair: The Real Bubble Mountain
dl $7E078D : db $02 : dw $9756 ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $D765 ; MDB
dl $7E079F : db $02 : dw $0004 ; Region
dl $7E07C3 : db $02 : dw $B130 ; GFX Pointers
dl $7E07C5 : db $02 : dw $3CBE ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B8 ; GFX Pointers
dl $7E07F5 : db $02 : dw $0003 ; Music Track
dl $7E090F : db $02 : dw $8000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01BC ; Health
dl $7E09CA : db $02 : dw $0009 ; Supers
dl $7E0A1C : db $02 : dw $009B ; Samus position/state
dl $7E0A1E : db $02 : dw $0000 ; More position/state
dl $7E0AF6 : db $02 : dw $0080 ; Samus X
dl $7E0AFA : db $02 : dw $0088 ; Samus Y
dl $7ED8BA : db $02 : dw $002E ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_water_jump:
dw #preset_routeb_maridia_maridia_elevator ; Maridia: Maridia Elevator
dl $7E078D : db $02 : dw $A60C ; DDB
dl $7E079B : db $02 : dw $D340 ; MDB
dl $7E07F3 : db $02 : dw $001B ; Music Bank
dl $7E07F5 : db $02 : dw $0006 ; Music Track
dl $7E090F : db $02 : dw $36C0 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $7000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0300 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0162 ; Health
dl $7E09C6 : db $02 : dw $000B ; Missiles
dl $7E09CA : db $02 : dw $0008 ; Supers
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $002F ; Samus X
dl $7E0AFA : db $02 : dw $038B ; Samus Y
dl $7ED8BC : db $02 : dw $0800 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_bootwon:
dw #preset_routeb_maridia_water_jump ; Maridia: Water Jump
dl $7E078D : db $02 : dw $A504 ; DDB
dl $7E079B : db $02 : dw $D08A ; MDB
dl $7E090F : db $02 : dw $0C00 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0400 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $5000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0174 ; Health
dl $7E09C6 : db $02 : dw $000A ; Missiles
dl $7E09CA : db $02 : dw $0009 ; Supers
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $04C8 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED8B2 : db $02 : dw $3011 ; Events, Items, Doors
dl $7ED8BC : db $02 : dw $0A00 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0047 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_sand_pit:
dw #preset_routeb_maridia_bootwon ; Maridia: Bootwon
dl $7E078D : db $02 : dw $A750 ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $D6D0 ; MDB
dl $7E090F : db $02 : dw $2B4E ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0200 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $00CD ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0130 ; Health
dl $7E09C6 : db $02 : dw $0002 ; Missiles
dl $7E09CA : db $02 : dw $0000 ; Supers
dl $7E09CE : db $02 : dw $0003 ; Pbs
dl $7E09D0 : db $02 : dw $0005 ; Max pbs
dl $7E0AF6 : db $02 : dw $02C7 ; Samus X
dl $7E0AFA : db $02 : dw $015B ; Samus Y
dl $7ED82C : db $02 : dw $0002 ; Events, Items, Doors
dl $7ED87A : db $02 : dw $0004 ; Events, Items, Doors
dl $7ED8B6 : db $02 : dw $2005 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0048 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_grappleway_underwater:
dw #preset_routeb_maridia_sand_pit ; Maridia: Sand Pit
dl $7E078D : db $02 : dw $A600 ; DDB
dl $7E079B : db $02 : dw $D48E ; MDB
dl $7E090F : db $02 : dw $4001 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $7000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0104 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0133 ; Health
dl $7E09C6 : db $02 : dw $0001 ; Missiles
dl $7E09CA : db $02 : dw $0001 ; Supers
dl $7E09CE : db $02 : dw $0001 ; Pbs
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $0035 ; Samus X
dl $7E0AFA : db $02 : dw $018B ; Samus Y
dl $7ED8B4 : db $02 : dw $8348 ; Events, Items, Doors
dl $7ED8BC : db $02 : dw $0E00 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0049 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_wrecked_ship_wrecked_ship_elevator:
dw #preset_routeb_maridia_grappleway_underwater ; Maridia: GrappleWay UnderWater
dl $7E078D : db $02 : dw $B260 ; DDB
dl $7E078F : db $02 : dw $0002 ; DoorOut Index
dl $7E079B : db $02 : dw $94CC ; MDB
dl $7E079F : db $02 : dw $0000 ; Region
dl $7E07C3 : db $02 : dw $F911 ; GFX Pointers
dl $7E07C5 : db $02 : dw $43BA ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2AF ; GFX Pointers
dl $7E07F5 : db $02 : dw $0003 ; Music Track
dl $7E090F : db $02 : dw $9000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09A2 : db $02 : dw $7127 ; Equipped Items
dl $7E09A4 : db $02 : dw $7127 ; Collected Items
dl $7E09C2 : db $02 : dw $010B ; Health
dl $7E09C6 : db $02 : dw $0003 ; Missiles
dl $7E09CE : db $02 : dw $0005 ; Pbs
dl $7E0A1C : db $02 : dw $009B ; Samus position/state
dl $7E0A1E : db $02 : dw $0000 ; More position/state
dl $7E0AF6 : db $02 : dw $0080 ; Samus X
dl $7E0AFA : db $02 : dw $0089 ; Samus Y
dl $7ED820 : db $02 : dw $0801 ; Events, Items, Doors
dl $7ED830 : db $02 : dw $0001 ; Events, Items, Doors
dl $7ED870 : db $02 : dw $4086 ; Events, Items, Doors
dl $7ED8BC : db $02 : dw $1E00 ; Events, Items, Doors
dl $7ED8C2 : db $02 : dw $0003 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $004C ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_wrecked_ship_wrecked_ship_2:
dw #preset_routeb_wrecked_ship_wrecked_ship_elevator ; Wrecked Ship: Wrecked Ship Elevator
dl $7E078D : db $02 : dw $B1E8 ; DDB
dl $7E078F : db $02 : dw $0005 ; DoorOut Index
dl $7E079B : db $02 : dw $CA08 ; MDB
dl $7E07C3 : db $02 : dw $C629 ; GFX Pointers
dl $7E07C5 : db $02 : dw $7CBA ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2AD ; GFX Pointers
dl $7E07F3 : db $02 : dw $0006 ; Music Bank
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $1D3F ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0800 ; Screen X position in pixels
dl $7E0915 : db $02 : dw $01FB ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0135 ; Health
dl $7E09C6 : db $02 : dw $000F ; Missiles
dl $7E09CA : db $02 : dw $0008 ; Supers
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $08CA ; Samus X
dl $7E0AFA : db $02 : dw $028B ; Samus Y
dl $7ED8BA : db $02 : dw $402E ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0050 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_wrecked_ship_phantoon:
dw #preset_routeb_wrecked_ship_wrecked_ship_2 ; Wrecked Ship: Wrecked Ship
dl $7E078D : db $02 : dw $A1D4 ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $CC6F ; MDB
dl $7E079F : db $02 : dw $0003 ; Region
dl $7E07C3 : db $02 : dw $AE9E ; GFX Pointers
dl $7E07C5 : db $02 : dw $A6BB ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B1 ; GFX Pointers
dl $7E07F3 : db $02 : dw $0030 ; Music Bank
dl $7E090F : db $02 : dw $6400 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0100 ; Screen X position in pixels
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $00E0 ; Health
dl $7E09C6 : db $02 : dw $000C ; Missiles
dl $7E09CA : db $02 : dw $0007 ; Supers
dl $7E09CE : db $02 : dw $0004 ; Pbs
dl $7E0AF6 : db $02 : dw $01D1 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED8BA : db $02 : dw $502E ; Events, Items, Doors
dl $7ED8BC : db $02 : dw $1E0A ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0053 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_wrecked_ship_wave_beam:
dw #preset_routeb_wrecked_ship_phantoon ; Wrecked Ship: Phantoon
dl $7E078D : db $02 : dw $A2F4 ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $CBD5 ; MDB
dl $7E07C5 : db $02 : dw $E7BB ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B0 ; GFX Pointers
dl $7E07F5 : db $02 : dw $0006 ; Music Track
dl $7E090F : db $02 : dw $1000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0915 : db $02 : dw $0400 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0074 ; Health
dl $7E09C8 : db $02 : dw $0014 ; Max missiles
dl $7E09CA : db $02 : dw $000A ; Supers
dl $7E09CE : db $02 : dw $0003 ; Pbs
dl $7E0AF6 : db $02 : dw $0034 ; Samus X
dl $7E0AFA : db $02 : dw $048B ; Samus Y
dl $7ED82A : db $02 : dw $0100 ; Events, Items, Doors
dl $7ED878 : db $02 : dw $0104 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0056 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_lower_norfair_maridia_elevator_2:
dw #preset_routeb_wrecked_ship_wave_beam ; Wrecked Ship: Wave Beam
dl $7E078D : db $02 : dw $8A5A ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $D3DF ; MDB
dl $7E079F : db $02 : dw $0004 ; Region
dl $7E07C3 : db $02 : dw $B130 ; GFX Pointers
dl $7E07C5 : db $02 : dw $3CBE ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B8 ; GFX Pointers
dl $7E07F3 : db $02 : dw $001B ; Music Bank
dl $7E090F : db $02 : dw $8000 ; Screen subpixel X position.
dl $7E0915 : db $02 : dw $0208 ; Screen Y position in pixels
dl $7E09A6 : db $02 : dw $1003 ; Beams
dl $7E09A8 : db $02 : dw $1003 ; Beams
dl $7E09C2 : db $02 : dw $0023 ; Health
dl $7E09CE : db $02 : dw $0004 ; Pbs
dl $7E0A1C : db $02 : dw $009B ; Samus position/state
dl $7E0A1E : db $02 : dw $0000 ; More position/state
dl $7E0AF6 : db $02 : dw $0080 ; Samus X
dl $7E0AFA : db $02 : dw $0298 ; Samus Y
dl $7ED878 : db $02 : dw $0504 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $005E ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_lower_norfair_upper_norfair_elevator_2:
dw #preset_routeb_lower_norfair_maridia_elevator_2 ; Lower Norfair: Maridia Elevator 2
dl $7E078D : db $02 : dw $B284 ; DDB
dl $7E079B : db $02 : dw $AFCE ; MDB
dl $7E079F : db $02 : dw $0002 ; Region
dl $7E07C3 : db $02 : dw $C3F9 ; GFX Pointers
dl $7E07C5 : db $02 : dw $BBBD ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B6 ; GFX Pointers
dl $7E07F3 : db $02 : dw $0015 ; Music Bank
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $C000 ; Screen subpixel X position.
dl $7E0915 : db $02 : dw $0200 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0046 ; Health
dl $7E09CE : db $02 : dw $0005 ; Pbs
dw #$FFFF
.after
preset_routeb_lower_norfair_road_to_lower_norfair:
dw #preset_routeb_lower_norfair_upper_norfair_elevator_2 ; Lower Norfair: Upper Norfair Elevator 2
dl $7E078D : db $02 : dw $9762 ; DDB
dl $7E078F : db $02 : dw $0002 ; DoorOut Index
dl $7E079B : db $02 : dw $B0DD ; MDB
dl $7E07C5 : db $02 : dw $E4BD ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B5 ; GFX Pointers
dl $7E090F : db $02 : dw $4000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $13FF ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0112 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01E4 ; Health
dl $7E09C6 : db $02 : dw $0011 ; Missiles
dl $7E09CE : db $02 : dw $000A ; Pbs
dl $7E09D0 : db $02 : dw $000A ; Max pbs
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $0035 ; Samus X
dl $7E0AFA : db $02 : dw $018B ; Samus Y
dl $7ED878 : db $02 : dw $0505 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0061 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_lower_norfair_lavadive:
dw #preset_routeb_lower_norfair_road_to_lower_norfair ; Lower Norfair: Road to Lower Norfair
dl $7E078D : db $02 : dw $9672 ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $AEDF ; MDB
dl $7E090F : db $02 : dw $5000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0400 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01F1 ; Health
dl $7E09C6 : db $02 : dw $0014 ; Missiles
dl $7E09CE : db $02 : dw $0008 ; Pbs
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $0080 ; Samus X
dl $7E0AFA : db $02 : dw $049B ; Samus Y
dl $7ED8B8 : db $02 : dw $2C5A ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0063 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_lower_norfair_lower_norfair_elevator:
dw #preset_routeb_lower_norfair_lavadive ; Lower Norfair: LavaDive
dl $7E078D : db $02 : dw $96F6 ; DDB
dl $7E079B : db $02 : dw $B236 ; MDB
dl $7E07F3 : db $02 : dw $0018 ; Music Bank
dl $7E090F : db $02 : dw $6000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0700 ; Screen X position in pixels
dl $7E0915 : db $02 : dw $0200 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0193 ; Health
dl $7E09CE : db $02 : dw $0007 ; Pbs
dl $7E0A1C : db $02 : dw $009B ; Samus position/state
dl $7E0A1E : db $02 : dw $0000 ; More position/state
dl $7E0AF6 : db $02 : dw $0780 ; Samus X
dl $7E0AFA : db $02 : dw $0289 ; Samus Y
dl $7ED8BA : db $02 : dw $502F ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_lower_norfair_screw_attack:
dw #preset_routeb_lower_norfair_lower_norfair_elevator ; Lower Norfair: Lower Norfair Elevator
dl $7E078D : db $02 : dw $998A ; DDB
dl $7E078F : db $02 : dw $0002 ; DoorOut Index
dl $7E079B : db $02 : dw $B6C1 ; MDB
dl $7E07F5 : db $02 : dw $0003 ; Music Track
dl $7E090F : db $02 : dw $8380 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0100 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $4800 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $001F ; Screen Y position in pixels
dl $7E09A2 : db $02 : dw $712F ; Equipped Items
dl $7E09A4 : db $02 : dw $712F ; Collected Items
dl $7E09C2 : db $02 : dw $0165 ; Health
dl $7E09CA : db $02 : dw $0000 ; Supers
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $01AF ; Samus X
dl $7E0AFA : db $02 : dw $00B4 ; Samus Y
dl $7ED87A : db $02 : dw $4004 ; Events, Items, Doors
dl $7ED8BE : db $02 : dw $2000 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0064 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_lower_norfair_the_red_room:
dw #preset_routeb_lower_norfair_screw_attack ; Lower Norfair: Screw Attack
dl $7E078D : db $02 : dw $9972 ; DDB
dl $7E078F : db $02 : dw $0003 ; DoorOut Index
dl $7E079B : db $02 : dw $B236 ; MDB
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $C000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $001C ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $00EC ; Health
dl $7E09CA : db $02 : dw $0005 ; Supers
dl $7E09CE : db $02 : dw $0006 ; Pbs
dl $7E0AF6 : db $02 : dw $002F ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dw #$FFFF
.after
preset_routeb_lower_norfair_health_refill:
dw #preset_routeb_lower_norfair_the_red_room ; Lower Norfair: The Red Room
dl $7E078D : db $02 : dw $98EE ; DDB
dl $7E078F : db $02 : dw $0004 ; DoorOut Index
dl $7E079B : db $02 : dw $B305 ; MDB
dl $7E07C3 : db $02 : dw $860B ; GFX Pointers
dl $7E07C5 : db $02 : dw $58C0 ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2BE ; GFX Pointers
dl $7E090F : db $02 : dw $8000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0400 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01F3 ; Health
dl $7E09CE : db $02 : dw $0007 ; Pbs
dl $7E0AF6 : db $02 : dw $0037 ; Samus X
dl $7ED8C0 : db $02 : dw $0002 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_lower_norfair_metal_pirates:
dw #preset_routeb_lower_norfair_health_refill ; Lower Norfair: Health Refill
dl $7E078D : db $02 : dw $995A ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $9104 ; MDB
dl $7E07C3 : db $02 : dw $C3F9 ; GFX Pointers
dl $7E07C5 : db $02 : dw $E4BD ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B5 ; GFX Pointers
dl $7E090F : db $02 : dw $B000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $D000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0300 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01C1 ; Health
dl $7E09CA : db $02 : dw $0009 ; Supers
dl $7E09CE : db $02 : dw $0008 ; Pbs
dl $7E0AF6 : db $02 : dw $0030 ; Samus X
dl $7E0AFA : db $02 : dw $038B ; Samus Y
dl $7ED8C0 : db $02 : dw $000E ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_lower_norfair_ridley:
dw #preset_routeb_lower_norfair_metal_pirates ; Lower Norfair: Metal Pirates
dl $7E078D : db $02 : dw $9A32 ; DDB
dl $7E079B : db $02 : dw $B37A ; MDB
dl $7E090F : db $02 : dw $7000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $C400 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01EA ; Health
dl $7E09CE : db $02 : dw $000A ; Pbs
dl $7E0AF6 : db $02 : dw $0035 ; Samus X
dl $7E0AFA : db $02 : dw $009B ; Samus Y
dl $7ED8C0 : db $02 : dw $003E ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_lower_norfair_chilean_climb:
dw #preset_routeb_lower_norfair_ridley ; Lower Norfair: Ridley
dl $7E078D : db $02 : dw $B430 ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $B6EE ; MDB
dl $7E07C5 : db $02 : dw $BBBD ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B6 ; GFX Pointers
dl $7E090F : db $02 : dw $F680 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0500 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $1800 ; Screen subpixel Y position
dl $7E09C2 : db $02 : dw $00F6 ; Health
dl $7E09C6 : db $02 : dw $000C ; Missiles
dl $7E09C8 : db $02 : dw $0019 ; Max missiles
dl $7E09CA : db $02 : dw $0004 ; Supers
dl $7E09CE : db $02 : dw $0009 ; Pbs
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $05CE ; Samus X
dl $7E0AFA : db $02 : dw $005C ; Samus Y
dl $7ED82A : db $02 : dw $0101 ; Events, Items, Doors
dl $7ED87C : db $02 : dw $0002 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0065 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_lower_norfair_zero_mission_dejavu:
dw #preset_routeb_lower_norfair_chilean_climb ; Lower Norfair: Chilean Climb
dl $7E078D : db $02 : dw $928E ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $B026 ; MDB
dl $7E07C3 : db $02 : dw $860B ; GFX Pointers
dl $7E07C5 : db $02 : dw $58C0 ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2BE ; GFX Pointers
dl $7E07F3 : db $02 : dw $0015 ; Music Bank
dl $7E090F : db $02 : dw $D000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $2800 ; Screen subpixel Y position
dl $7E09C2 : db $02 : dw $010A ; Health
dl $7E09CA : db $02 : dw $0005 ; Supers
dl $7E09CE : db $02 : dw $000A ; Pbs
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $0032 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED91A : db $02 : dw $0068 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_lower_norfair_elevator_climb:
dw #preset_routeb_lower_norfair_zero_mission_dejavu ; Lower Norfair: Zero Mission DeJaVu
dl $7E078D : db $02 : dw $938A ; DDB
dl $7E079B : db $02 : dw $AFA3 ; MDB
dl $7E07C3 : db $02 : dw $C3F9 ; GFX Pointers
dl $7E07C5 : db $02 : dw $E4BD ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B5 ; GFX Pointers
dl $7E090F : db $02 : dw $7000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0500 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $5C00 ; Screen subpixel Y position
dl $7E09C2 : db $02 : dw $01F3 ; Health
dl $7E09C6 : db $02 : dw $0019 ; Missiles
dl $7E09CA : db $02 : dw $000A ; Supers
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $05D7 ; Samus X
dw #$FFFF
.after
preset_routeb_red_tower_red_tower_elevator:
dw #preset_routeb_lower_norfair_elevator_climb ; Lower Norfair: Elevator Climb
dl $7E078D : db $02 : dw $92EE ; DDB
dl $7E078F : db $02 : dw $0004 ; DoorOut Index
dl $7E079B : db $02 : dw $A6A1 ; MDB
dl $7E079F : db $02 : dw $0001 ; Region
dl $7E07C3 : db $02 : dw $A5AA ; GFX Pointers
dl $7E07C5 : db $02 : dw $5FBC ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B3 ; GFX Pointers
dl $7E07F3 : db $02 : dw $0012 ; Music Bank
dl $7E07F5 : db $02 : dw $0003 ; Music Track
dl $7E090F : db $02 : dw $4000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0A1C : db $02 : dw $009B ; Samus position/state
dl $7E0A1E : db $02 : dw $0000 ; More position/state
dl $7E0AF6 : db $02 : dw $0080 ; Samus X
dl $7E0AFA : db $02 : dw $0086 ; Samus Y
dl $7ED91A : db $02 : dw $0069 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_red_tower_red_tower_climb:
dw #preset_routeb_red_tower_red_tower_elevator ; Red Tower: Red Tower Elevator
dl $7E078D : db $02 : dw $90DE ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $A408 ; MDB
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $C000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0400 ; Screen X position in pixels
dl $7E0915 : db $02 : dw $0003 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $0195 ; Health
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $04C7 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED91A : db $02 : dw $006A ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_red_tower_water_spike_corridor:
dw #preset_routeb_red_tower_red_tower_climb ; Red Tower: Red Tower Climb
dl $7E078D : db $02 : dw $907E ; DDB
dl $7E079B : db $02 : dw $A293 ; MDB
dl $7E090F : db $02 : dw $1000 ; Screen subpixel X position.
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01A3 ; Health
dl $7E0AF6 : db $02 : dw $04D0 ; Samus X
dl $7ED91A : db $02 : dw $006B ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_return_maridia_entrace:
dw #preset_routeb_red_tower_water_spike_corridor ; Red Tower: Water Spike Corridor
dl $7E078D : db $02 : dw $A360 ; DDB
dl $7E079B : db $02 : dw $CEFB ; MDB
dl $7E079F : db $02 : dw $0004 ; Region
dl $7E07C3 : db $02 : dw $B130 ; GFX Pointers
dl $7E07C5 : db $02 : dw $3CBE ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B8 ; GFX Pointers
dl $7E090F : db $02 : dw $A000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $3C00 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $006F ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01B5 ; Health
dl $7E0AF6 : db $02 : dw $007F ; Samus X
dl $7E0AFA : db $02 : dw $0103 ; Samus Y
dw #$FFFF
.after
preset_routeb_maridia_return_red_tubes:
dw #preset_routeb_maridia_return_maridia_entrace ; Maridia Return: Maridia Entrace
dl $7E078D : db $02 : dw $A438 ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $CFC9 ; MDB
dl $7E07F3 : db $02 : dw $001B ; Music Bank
dl $7E07F5 : db $02 : dw $0006 ; Music Track
dl $7E090F : db $02 : dw $E000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $001B ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01B1 ; Health
dl $7E09CA : db $02 : dw $0009 ; Supers
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $002D ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED8BE : db $02 : dw $2001 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $006C ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_return_halfie_spark:
dw #preset_routeb_maridia_return_red_tubes ; Maridia Return: Red Tubes
dl $7E078D : db $02 : dw $A4B0 ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $D617 ; MDB
dl $7E07C3 : db $02 : dw $E78D ; GFX Pointers
dl $7E07C5 : db $02 : dw $2EBE ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B9 ; GFX Pointers
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $8000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0276 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $8000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $01EB ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01F3 ; Health
dl $7E09CA : db $02 : dw $0007 ; Supers
dl $7E0AF6 : db $02 : dw $02DE ; Samus X
dl $7E0AFA : db $02 : dw $027B ; Samus Y
dl $7ED8BE : db $02 : dw $2081 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $006D ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_return_draygon:
dw #preset_routeb_maridia_return_halfie_spark ; Maridia Return: Halfie Spark
dl $7E078D : db $02 : dw $A7F8 ; DDB
dl $7E078F : db $02 : dw $0002 ; DoorOut Index
dl $7E079B : db $02 : dw $D78F ; MDB
dl $7E090F : db $02 : dw $A001 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0100 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $5400 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $01F3 ; Screen Y position in pixels
dl $7E09CA : db $02 : dw $0006 ; Supers
dl $7E0AF6 : db $02 : dw $0137 ; Samus X
dl $7E0AFA : db $02 : dw $028B ; Samus Y
dl $7ED8BE : db $02 : dw $2A81 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $006E ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_return_reverse_halfie:
dw #preset_routeb_maridia_return_draygon ; Maridia Return: Draygon
dl $7E078D : db $02 : dw $A96C ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E090F : db $02 : dw $8000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $2400 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09A2 : db $02 : dw $732F ; Equipped Items
dl $7E09A4 : db $02 : dw $732F ; Collected Items
dl $7E09C2 : db $02 : dw $00E1 ; Health
dl $7E09CA : db $02 : dw $0009 ; Supers
dl $7E0AF6 : db $02 : dw $007F ; Samus X
dl $7E0AFA : db $02 : dw $009B ; Samus Y
dl $7ED82C : db $02 : dw $0003 ; Events, Items, Doors
dl $7ED87A : db $02 : dw $4804 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0070 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_return_plasma_beam:
dw #preset_routeb_maridia_return_reverse_halfie ; Maridia Return: Reverse Halfie
dl $7E078D : db $02 : dw $A54C ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $D6FD ; MDB
dl $7E07F5 : db $02 : dw $0006 ; Music Track
dl $7E090F : db $02 : dw $E000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E09C2 : db $02 : dw $0158 ; Health
dl $7E09CA : db $02 : dw $000A ; Supers
dl $7E0AF6 : db $02 : dw $0030 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED8BE : db $02 : dw $2A87 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0077 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_return_tube_room:
dw #preset_routeb_maridia_return_plasma_beam ; Maridia Return: Plasma Beam
dl $7E078D : db $02 : dw $A51C ; DDB
dl $7E078F : db $02 : dw $0003 ; DoorOut Index
dl $7E079B : db $02 : dw $D3DF ; MDB
dl $7E07C3 : db $02 : dw $B130 ; GFX Pointers
dl $7E07C5 : db $02 : dw $3CBE ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B8 ; GFX Pointers
dl $7E090F : db $02 : dw $3000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $3400 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0500 ; Screen Y position in pixels
dl $7E09A6 : db $02 : dw $100B ; Beams
dl $7E09A8 : db $02 : dw $100B ; Beams
dl $7E09C2 : db $02 : dw $017B ; Health
dl $7E09C6 : db $02 : dw $0018 ; Missiles
dl $7E09CE : db $02 : dw $0009 ; Pbs
dl $7E0AF6 : db $02 : dw $0035 ; Samus X
dl $7E0AFA : db $02 : dw $05BB ; Samus Y
dl $7ED87A : db $02 : dw $480C ; Events, Items, Doors
dl $7ED8BE : db $02 : dw $3A87 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $0079 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_maridia_return_red_tubes_return:
dw #preset_routeb_maridia_return_tube_room ; Maridia Return: Tube Room
dl $7E078D : db $02 : dw $B3E4 ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $D1A3 ; MDB
dl $7E090F : db $02 : dw $1002 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $4C00 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $010D ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $018F ; Health
dl $7E0AF6 : db $02 : dw $0032 ; Samus X
dl $7E0AFA : db $02 : dw $018B ; Samus Y
dl $7ED91A : db $02 : dw $007C ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_backtracking_green_brinstar_entrace:
dw #preset_routeb_maridia_return_red_tubes_return ; Maridia Return: Red Tubes Return
dl $7E078D : db $02 : dw $8CFA ; DDB
dl $7E078F : db $02 : dw $0003 ; DoorOut Index
dl $7E079B : db $02 : dw $D913 ; MDB
dl $7E07C3 : db $02 : dw $E78D ; GFX Pointers
dl $7E07C5 : db $02 : dw $2EBE ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B9 ; GFX Pointers
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $8000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $F800 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $019E ; Health
dl $7E09C6 : db $02 : dw $0019 ; Missiles
dl $7E09CE : db $02 : dw $000A ; Pbs
dl $7E0AF6 : db $02 : dw $0069 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED820 : db $02 : dw $2801 ; Events, Items, Doors
dl $7ED8BC : db $02 : dw $3E0A ; Events, Items, Doors
dl $7ED91A : db $02 : dw $007D ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_backtracking_crateria_elevator:
dw #preset_routeb_backtracking_green_brinstar_entrace ; Backtracking: Green Brinstar Entrace
dl $7E078D : db $02 : dw $8EB6 ; DDB
dl $7E078F : db $02 : dw $0002 ; DoorOut Index
dl $7E079B : db $02 : dw $97B5 ; MDB
dl $7E079F : db $02 : dw $0000 ; Region
dl $7E07C3 : db $02 : dw $F911 ; GFX Pointers
dl $7E07C5 : db $02 : dw $43BA ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2AF ; GFX Pointers
dl $7E07F3 : db $02 : dw $0009 ; Music Bank
dl $7E07F5 : db $02 : dw $0003 ; Music Track
dl $7E090F : db $02 : dw $5000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E09C2 : db $02 : dw $01A1 ; Health
dl $7E09CE : db $02 : dw $0007 ; Pbs
dl $7E0A1C : db $02 : dw $009B ; Samus position/state
dl $7E0A1E : db $02 : dw $0000 ; More position/state
dl $7E0AF6 : db $02 : dw $0080 ; Samus X
dl $7E0AFA : db $02 : dw $0088 ; Samus Y
dl $7ED8B2 : db $02 : dw $3019 ; Events, Items, Doors
dl $7ED91A : db $02 : dw $007F ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_backtracking_g4:
dw #preset_routeb_backtracking_crateria_elevator ; Backtracking: Crateria Elevator
dl $7E078D : db $02 : dw $ADC6 ; DDB
dl $7E078F : db $02 : dw $0005 ; DoorOut Index
dl $7E079B : db $02 : dw $A5ED ; MDB
dl $7E07C3 : db $02 : dw $A5AA ; GFX Pointers
dl $7E07C5 : db $02 : dw $47BC ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2B4 ; GFX Pointers
dl $7E07F5 : db $02 : dw $0004 ; Music Track
dl $7E090F : db $02 : dw $DC00 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $DC00 ; Screen subpixel Y position
dl $7E09C2 : db $02 : dw $019D ; Health
dl $7E09CA : db $02 : dw $0008 ; Supers
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $0035 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED8B0 : db $02 : dw $4152 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_tourian_tourian_elevator:
dw #preset_routeb_backtracking_g4 ; Backtracking: G4
dl $7E078D : db $02 : dw $9222 ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $DAAE ; MDB
dl $7E079F : db $02 : dw $0005 ; Region
dl $7E07C3 : db $02 : dw $D414 ; GFX Pointers
dl $7E07C5 : db $02 : dw $EDBF ; GFX Pointers
dl $7E07C7 : db $02 : dw $C2BA ; GFX Pointers
dl $7E07F3 : db $02 : dw $001E ; Music Bank
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $B001 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0238 ; Screen Y position in pixels
dl $7E0A1C : db $02 : dw $009B ; Samus position/state
dl $7E0A1E : db $02 : dw $0000 ; More position/state
dl $7E0AF6 : db $02 : dw $0080 ; Samus X
dl $7E0AFA : db $02 : dw $02A8 ; Samus Y
dl $7ED820 : db $02 : dw $2FC1 ; Events, Items, Doors
dl $7ED90C : db $02 : dw $0100 ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_tourian_metroids_room_2:
dw #preset_routeb_tourian_tourian_elevator ; Tourian: Tourian Elevator
dl $7E078D : db $02 : dw $A984 ; DDB
dl $7E078F : db $02 : dw $0000 ; DoorOut Index
dl $7E079B : db $02 : dw $DAE1 ; MDB
dl $7E090F : db $02 : dw $9000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $7800 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01F3 ; Health
dl $7E09CA : db $02 : dw $000A ; Supers
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $0031 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED822 : db $02 : dw $0021 ; Events, Items, Doors
dl $7ED8C0 : db $02 : dw $00BE ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_tourian_metroids_room_3:
dw #preset_routeb_tourian_metroids_room_2 ; Tourian: Metroids Room 2
dl $7E078D : db $02 : dw $A9B4 ; DDB
dl $7E078F : db $02 : dw $0001 ; DoorOut Index
dl $7E079B : db $02 : dw $DB31 ; MDB
dl $7E0913 : db $02 : dw $D800 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0023 ; Screen Y position in pixels
dl $7E09CE : db $02 : dw $0008 ; Pbs
dl $7E0A1C : db $02 : dw $0001 ; Samus position/state
dl $7E0A1E : db $02 : dw $0008 ; More position/state
dl $7E0AF6 : db $02 : dw $00C9 ; Samus X
dl $7ED822 : db $02 : dw $0023 ; Events, Items, Doors
dl $7ED8C0 : db $02 : dw $01BE ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_tourian_metroids_room_4:
dw #preset_routeb_tourian_metroids_room_3 ; Tourian: Metroids Room 3
dl $7E078D : db $02 : dw $A9CC ; DDB
dl $7E079B : db $02 : dw $DB7D ; MDB
dl $7E0911 : db $02 : dw $0400 ; Screen X position in pixels
dl $7E0913 : db $02 : dw $0000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0000 ; Screen Y position in pixels
dl $7E09CE : db $02 : dw $000A ; Pbs
dl $7E0AF6 : db $02 : dw $0486 ; Samus X
dl $7E0AFA : db $02 : dw $006B ; Samus Y
dl $7ED822 : db $02 : dw $0027 ; Events, Items, Doors
dl $7ED8C0 : db $02 : dw $03BE ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_tourian_pirates_room:
dw #preset_routeb_tourian_metroids_room_4 ; Tourian: Metroids Room 4
dl $7E078D : db $02 : dw $A9E4 ; DDB
dl $7E079B : db $02 : dw $DBCD ; MDB
dl $7E090F : db $02 : dw $5000 ; Screen subpixel X position.
dl $7E0911 : db $02 : dw $0000 ; Screen X position in pixels
dl $7E0915 : db $02 : dw $001C ; Screen Y position in pixels
dl $7E0A1C : db $02 : dw $0002 ; Samus position/state
dl $7E0A1E : db $02 : dw $0004 ; More position/state
dl $7E0AF6 : db $02 : dw $0034 ; Samus X
dl $7E0AFA : db $02 : dw $008B ; Samus Y
dl $7ED822 : db $02 : dw $002F ; Events, Items, Doors
dl $7ED8C0 : db $02 : dw $07BE ; Events, Items, Doors
dw #$FFFF
.after
preset_routeb_tourian_baby_skip:
dw #preset_routeb_tourian_pirates_room ; Tourian: Pirates Room
dl $7E078D : db $02 : dw $A9FC ; DDB
dl $7E079B : db $02 : dw $DC19 ; MDB
dl $7E07F3 : db $02 : dw $0024 ; Music Bank
dl $7E07F5 : db $02 : dw $0006 ; Music Track
dl $7E090F : db $02 : dw $2000 ; Screen subpixel X position.
dl $7E0915 : db $02 : dw $0023 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01D5 ; Health
dl $7E0AF6 : db $02 : dw $002A ; Samus X
dw #$FFFF
.after
preset_routeb_tourian_zebetite_skip:
dw #preset_routeb_tourian_baby_skip ; Tourian: Baby Skip
dl $7E078D : db $02 : dw $AAA4 ; DDB
dl $7E079B : db $02 : dw $DDF3 ; MDB
dl $7E07F3 : db $02 : dw $001E ; Music Bank
dl $7E07F5 : db $02 : dw $0005 ; Music Track
dl $7E090F : db $02 : dw $6000 ; Screen subpixel X position.
dl $7E0913 : db $02 : dw $1000 ; Screen subpixel Y position
dl $7E0915 : db $02 : dw $0026 ; Screen Y position in pixels
dl $7E09C2 : db $02 : dw $01F3 ; Health
dl $7E09CA : db $02 : dw $0008 ; Supers
dl $7E0AF6 : db $02 : dw $0044 ; Samus X
dl $7ED830 : db $02 : dw $0011 ; Events, Items, Doors
dl $7ED8C0 : db $02 : dw $3FBE ; Events, Items, Doors
dw #$FFFF
.after
| 46.960648 | 102 | 0.61007 |
240ead5082b03e12ca9d1a1b72d8cd5a83e6e17e | 1,836 | asm | Assembly | engine/gameModes.asm | laoo/TimePilot | 88b2548ab23d213677047ca530b68f9523ea7140 | [
"MIT"
] | 24 | 2018-05-17T05:55:38.000Z | 2021-12-30T10:22:45.000Z | engine/gameModes.asm | laoo/TimePilot | 88b2548ab23d213677047ca530b68f9523ea7140 | [
"MIT"
] | 1 | 2018-06-27T11:08:01.000Z | 2018-06-27T11:08:01.000Z | engine/gameModes.asm | laoo/TimePilot | 88b2548ab23d213677047ca530b68f9523ea7140 | [
"MIT"
] | 3 | 2018-05-19T03:47:19.000Z | 2021-06-01T12:33:32.000Z | .proc gameModes
; normal mode
.proc normal
lda #8
sta SPAWN.enemy.maxEnemies
lda #6
sta SPAWN.enemy.maxEnemiesSquadron
lda #$27-4
sta OLP.enemies.maxEnemiesOLP
lda #{nop}
sta SPAWN.enemyShots
sta SPAWN.enemyBombs
lda rapidusDetected
beq swarm.finish ; shared finishing code
jsr rapidusLevelValues ; rewrite default level values for rapidus (because swarm mode changes it)
@
bmi swarm.finish ; N is set by rapidusLevelValues->memCopyShort
.endp
; swarm mode | press select on titlescreen (rapidus only)
.proc swarm
lda #8+configSwarmModeAddEnemies
sta SPAWN.enemy.maxEnemies
lda #8-2+configSwarmModeAddEnemies
sta SPAWN.enemy.maxEnemiesSquadron
lda #$27-configSwarmModeAddEnemies
sta OLP.enemies.maxEnemiesOLP
lda #{rts}
sta SPAWN.enemyShots
sta SPAWN.enemyBombs
lda #0
sta levelInformation.levelEnemyPeriodicity
sta levelInformation.levelEnemyPeriodicity+1
sta levelInformation.levelEnemyPeriodicity+2
sta levelInformation.levelEnemyPeriodicity+3
sta levelInformation.levelEnemyPeriodicity+4
lda #63
sta levelInformation.levelAgilityMinimum
sta levelInformation.levelAgilityMinimum+1
sta levelInformation.levelAgilityMinimum+2
sta levelInformation.levelAgilityMinimum+3
sta levelInformation.levelAgilityMinimum+4
lda #127
sta levelInformation.levelSquadronPeriodicity
sta levelInformation.levelSquadronPeriodicity+1
sta levelInformation.levelSquadronPeriodicity+2
sta levelInformation.levelSquadronPeriodicity+3
sta levelInformation.levelSquadronPeriodicity+4
lda #1
sta levelCurrent.swarmMode
sta levelCurrent.difficulty
lda #10
sta playerLives
finish
lda SPAWN.globalSpawnDelay ; first time spawn delay when game starts
sta levelInformation.levelAllowSpawnsDelay
rts
.endp
.endp
| 27.818182 | 104 | 0.783769 |
9f674bf0330c8905928f3c649ebd8b4056c5822d | 1,954 | asm | Assembly | WRK-V1.2/TOOLS/crt/src/intel/strset.asm | intj-t/openvmsft | 0d17fbce8607ab2b880be976c2e86d8cfc3e83bb | [
"Intel"
] | 2 | 2021-01-27T10:19:30.000Z | 2021-02-09T06:24:30.000Z | WRK-V1.2/TOOLS/crt/src/intel/strset.asm | intj-t/openvmsft | 0d17fbce8607ab2b880be976c2e86d8cfc3e83bb | [
"Intel"
] | null | null | null | WRK-V1.2/TOOLS/crt/src/intel/strset.asm | intj-t/openvmsft | 0d17fbce8607ab2b880be976c2e86d8cfc3e83bb | [
"Intel"
] | 1 | 2021-01-27T10:19:36.000Z | 2021-01-27T10:19:36.000Z | page ,132
title strset - set all characters of string to character
;***
;strset.asm - sets all charcaters of string to given character
;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;Purpose:
; defines _strset() - sets all of the characters in a string (except
; the '\0') equal to a given character.
;
;*******************************************************************************
.xlist
include cruntime.inc
.list
page
;***
;char *_strset(string, val) - sets all of string to val
;
;Purpose:
; Sets all of characters in string (except the terminating '/0'
; character) equal to val.
;
; Algorithm:
; char *
; _strset (string, val)
; char *string;
; char val;
; {
; char *start = string;
;
; while (*string)
; *string++ = val;
; return(start);
; }
;
;Entry:
; char *string - string to modify
; char val - value to fill string with
;
;Exit:
; returns string -- now filled with val's
;
;Uses:
;
;Exceptions:
;
;*******************************************************************************
CODESEG
public _strset
_strset proc \
uses edi, \
string:ptr byte, \
val:byte
mov edi,[string] ; di = string
mov edx,edi ; dx=string addr; save return value
xor eax,eax ; ax = 0
or ecx,-1 ; cx = -1
repne scasb ; scan string & count bytes
add ecx,2 ; cx=-strlen
neg ecx ; cx=strlen
mov al,[val] ; al = byte value to store
mov edi,edx ; di=string addr
rep stosb
mov eax,edx ; return value: string addr
ret ; _cdecl return
_strset endp
end
| 24.734177 | 80 | 0.452405 |
f6f372f76cefff40cfc64def5257edddb2c2bc0e | 465 | asm | Assembly | sound/song_names.asm | ISSOtm/Aevilia-GB | 9b4e233bac6fbf175ca9ae7e4c0a8f16c8222275 | [
"Apache-2.0"
] | 53 | 2017-08-25T01:27:33.000Z | 2021-08-30T19:55:57.000Z | sound/song_names.asm | ISSOtm/Aevilia-GB | 9b4e233bac6fbf175ca9ae7e4c0a8f16c8222275 | [
"Apache-2.0"
] | 6 | 2017-08-24T19:40:33.000Z | 2018-05-14T19:37:34.000Z | sound/song_names.asm | ISSOtm/Aevilia-GB | 9b4e233bac6fbf175ca9ae7e4c0a8f16c8222275 | [
"Apache-2.0"
] | 10 | 2017-08-24T18:37:35.000Z | 2019-10-02T04:35:39.000Z |
SECTION "Song names", ROMX
InvalidSongName::
dstr "MISSINGNO."
SongNames::
dw .song0
dw .song1
dw .song2
dw .song3
dw .song4
dw .song5
dw .song6
dw .song7
dw .song8
.song0
dstr "Safe Place"
.song1
dstr "Battle Time!"
.song2
dstr "Menu Chill"
.song3
dstr "Overworld Theme"
.song4
dstr "Boss Fight!"
.song5
dstr "Scare Chord"
.song6
dstr "Neo Safe Place"
.song7
dstr "Avocado Invaders"
.song8
dstr "Forest"
| 12.916667 | 27 | 0.634409 |
622284b91992ea2dc60340b6b78052090cc1ec14 | 720 | asm | Assembly | oeis/052/A052845.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/052/A052845.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/052/A052845.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A052845: Expansion of e.g.f.: exp(x^2/(1-x)).
; Submitted by Christian Krause
; 1,0,2,6,36,240,1920,17640,183120,2116800,26943840,374220000,5628934080,91122071040,1579034096640,29155689763200,571308920582400,11838533804697600,258608278645516800,5938673374272038400,143003892952893772800,3602735624977961472000,94765181895686279577600,2597656713625171483084800,74077240928503351111372800,2194178200494655599544320000,67407833485880833976110080000,2144938570766472140007828480000,70606093625791466913023293440000,2401523921392465738637885276160000
mov $4,1
lpb $0
sub $0,1
add $1,$4
mul $1,$0
mul $2,2
mov $3,$2
add $4,$2
mul $4,$0
add $4,$1
div $4,2
sub $4,$2
add $2,$4
mov $4,$3
lpe
mov $0,$4
| 34.285714 | 467 | 0.7875 |
2f1e24443840e1e739dc277afa108a240ab90b47 | 2,914 | asm | Assembly | source/init/ttyname.asm | re0ah/shell-asm-linux | aa3351f785b2906369e8bb1e8165b924d3018252 | [
"Unlicense"
] | null | null | null | source/init/ttyname.asm | re0ah/shell-asm-linux | aa3351f785b2906369e8bb1e8165b924d3018252 | [
"Unlicense"
] | null | null | null | source/init/ttyname.asm | re0ah/shell-asm-linux | aa3351f785b2906369e8bb1e8165b924d3018252 | [
"Unlicense"
] | null | null | null | %define BUFSIZ 8192
%define AT_FDCWD -100
section .rodata
devpts_path db "/dev/pts/", 0
section .bss
ttyname resb 32
;struc __dirstream
; fd resd 1 ;0..3, file descriptor
; allocation resq 1 ;4..11, space allocated for the block
; size resq 1 ;12..19, total valid data in the block
; offset resq 1 ;20..27, current offset into the block
; filepos resq 1 ;28..35, position of next entry to read
; errcode resd 1 ;36..39, delayed error code
; _data resb 8 ;40..47, not using, for align
;endstruc ;48 bytes
;struc timespec
; tv_sec resq 1 ;0..7
; tv_nsec resq 1 ;8..15
;endstruc ;16 bytes
;struc stat
; st_dev resq 1 ;0..7, device
; st_ino resq 1 ;8..15, file serial number
; st_nlink resq 1 ;16..23, link count
; st_mode resd 1 ;24..27, file mode
; st_uid resd 1 ;28..31, user id of the file's owner
; st_gid resd 1 ;32..35, group id of the file's group
; __pad0 resd 1 ;36..39
; st_rdev resq 1 ;40..47, device number, if device
; st_size resq 1 ;48..55, size of file, in bytes
; st_blksize resq 1 ;56..63, optimal block size for I/O
; st_blocks resq 1 ;64..71, Nr. 512-byte blocks allocated
; st_atim resq 2 ;72..87, timespec, time of last access
; st_mtim resq 2 ;88..103, timespec, time of last modification
; st_ctim resq 2 ;104..119, timespec, time of last status change
; __glibc_reserved resq 3 ;120..143, __syscall_slong_t
;endstruc ;144
;struc dirent
; d_ino resq 1 ;0..7
; d_off resq 1 ;8..15
; d_reclen resw 1 ;16..17
; d_type resb 1 ;18..18
; d_name resb 261 ;19..279
;endstruc ;280 bytes
section .text
ttyname_init:
%define BUFSIZ4 32768
%define ALLOC_TTYNAME_INIT 33240 ;sizeof(__dirstream) +
;bufsiz * 4 +
;sizeof(stat) +
;sizeof(dirent)
sub rsp, ALLOC_TTYNAME_INIT
mov rdi, rsp;struct __distream
xor rax, rax
mov rcx, 6 ;8 * 6 = 48 bytes, sizeof(__dirstream)
rep stosq
mov rdi, AT_FDCWD
mov rsi, devpts_path
mov edx, 0x98800 ;O_RDONLY |
;O_NDELAY |
;O_DIRECTORY |
;O_LARGEFILE |
;O_CLOEXEC
mov rax, 0x101 ;openat
syscall
mov dword[rsp], eax ;dirstream->fd
mov edi, eax ;fd
lea rsi, [rsp + 40] ;data ptr
mov rdx, 32768 ;allocation
mov rax, 0xd9 ;getdents64
syscall
xor rdi, rdi ;fd
lea rsi, [rsp + 32808];struct stat
mov rax, 0x05 ;fstat
syscall
mov rax, [rsp + 32816]
lea rdx, [rsp + 40] ;dirstream data ptr
jmp .readdir_start
.readdir:
add rdx, rcx
.readdir_start:
movzx rcx, word[rdx + 16];stat, d_reclen
cmp qword[rdx], rax ;dirent, d_ino
jne .readdir
mov eax, 0x2F737470 ;pts/
mov rdi, ttyname
stosd
mov eax, dword[rdx + 19]
mov dword[rdi], eax
mov edi, dword[rsp] ;dirstream->fd
mov rax, 0x03 ;close
syscall
add rsp, ALLOC_TTYNAME_INIT
ret
| 26.252252 | 68 | 0.631778 |
0f42c2c5fb07268d3134d2b6b0dad6d1e8002441 | 19,250 | asm | Assembly | dds.asm | NullMember/MSP430G2-DDS-Example | a5cebea543479cc62c8297c8afa759699bf54695 | [
"MIT"
] | null | null | null | dds.asm | NullMember/MSP430G2-DDS-Example | a5cebea543479cc62c8297c8afa759699bf54695 | [
"MIT"
] | null | null | null | dds.asm | NullMember/MSP430G2-DDS-Example | a5cebea543479cc62c8297c8afa759699bf54695 | [
"MIT"
] | null | null | null | ; Copyright (c) 2019 Malik Enes Şafak
;
; Permission is hereby granted, free of charge, to any person obtaining
; a copy of this software and associated documentation files (the
; "Software"), to deal in the Software without restriction, including
; without limitation the rights to use, copy, modify, merge, publish,
; distribute, sublicense, and/or sell copies of the Software, and to
; permit persons to whom the Software is furnished to do so, subject to
; the following conditions:
;
; The above copyright notice and this permission notice shall be
; included in all copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
; EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
; NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
; LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
; OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
; WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
.msp430
.include "msp430g2452.inc"
RAM equ 0x0200
ROM equ 0xE000
REGPHASELOW equ R15
REGPHASEHIGH equ R14
REGTUNINGLOW equ R13
REGTUNINGHIGH equ R12
REGPITCH equ R11
OSCSTATUS equ R10
REGCOUNTER equ R9
OSC1MUTE equ BIT0
OSC2MUTE equ BIT1
OSC1 equ BIT2
OSC2 equ BIT3
PRECALCTDIVS equ 0x0863
;------------------------------------------------------------------------------
; Main Code
; This program uses Q16.16 fixed point calculations for DDS
;------------------------------------------------------------------------------
.entry_point RESET ;SET ENTRY POINT
.org ROM ;ENTRY POINT ADDRESS IS BEGINNING ADDRESS OF FLASH
RESET:
MOV.W #0x0300, SP ;SET SP TO HIGHEST RAM ADDRESS
STOPWDT:
MOV.W #WDTPW+WDTHOLD, &WDTCTL ;STOP WDT
CONFCPU:
MOV.B &CALBC1_16MHZ_, &BCSCTL1 ;SET BCSCTL1 TO FACTORY CALIBRATED 16MHZ VALUE
MOV.B &CALDCO_16MHZ_, &DCOCTL ;SET DCOCTL TO FACTORY CALIBRATED 16MHZ VALUE
CONFTIMER:
MOV.W #TASSEL_2+ID_1+MC_1, &TACTL ;TIMER A CLOCK SOURCE SMCLK, INPUT DIVIDER 2, UP MODE
MOV.W #255, &TACCR0 ;SMCLK UPDATES AT 8MHZ OUR SAMPLING FREQUENCY IS 31.25KHZ
BIS.W #CCIE, &TACCTL0 ;TIMER A C/C 0 IRQ IS ENABLED
CONFPWM:
MOV.B #0xFF, &P1DIR ;SET P1 OUTPUT AND LOW FOR LOWER ENERGY CONSUMPTION AND NOISE
MOV.B #0, &P1OUT
BIS.B #BIT6, &P1DIR ;SET P1.6 TO OUTPUT
BIS.B #BIT6, &P1SEL ;SET P1.6 SPECIAL FUNC1 (FOR PWM)
BIC.B #BIT6, &P1SEL2 ;CLEAR P1.6 SPECIAL FUNC2
MOV.W #OUTMOD_7, &TACCTL1 ;SET C/C 1 OUTMOD TO RESET/SET
MOV.W #128, &TACCR1
BIS.W #CCIE, &TACCTL1 ;ENABLE C/C 1 CCIE IRQ
CONFADC:
BIC.W #ENC, &ADC10CTL0
MOV.W #0, &TACCR2
MOV.W #ADC10SR+ADC10ON+MSC, &ADC10CTL0
MOV.W #SHS_1+ADC10DIV_7+ADC10SSEL_3+CONSEQ_2, &ADC10CTL1
BIS.B #BIT0, &ADC10AE0
BIS.W #ADC10IE, &ADC10CTL0
BIS.W #ENC, &ADC10CTL0
CONFBUTTON:
BIC.B #BIT3, &P1DIR ;SET P1.3 TO INPUT
BIS.B #BIT3, &P1REN ;ENABLE PULLUP/PULLDOWN RESISTOR
BIS.B #BIT3, &P1OUT ;SELECT PULLUP RESISTOR
BIS.B #BIT3, &P1IES ;SET FALLING EDGE INTERRUPT
BIS.B #BIT3, &P1IE ;ENABLE INTERRUPT IN P1.3
BIC.B #BIT3, &P1IFG ;CLEAR INTERRUPT FLAG (CAUSED BY CHANGING SETTINGS)
MAIN:
MOV.B #0xFF, &P2DIR ;DISABLE P2 FOR LOWER ENERGY CONSUMPTION AND NOISE
MOV.B #0, &P2OUT
MOV.W #PRECALCTDIVS, &TDIVSLOWEST ;COPY PRECALCULATED TABLESIZE/SAMPLERATE (1024/62500) CONSTANT TO RAM
MOV.W #1, &FREQUENCYLOW ;SET FREQUENCY (IN THIS CASE 1)
JMP CLCTNW
SETSR:
BIS.W #GIE, R2 ;ENABLE GLOBAL INTERRUPTS
BIS.W #CPUOFF, R2 ;ENABLE LPM0
LOOP:
JMP LOOP
; calculate frequency * (table size / sample rate) and store result in tuning word registers
CLCTNW:
MOV.W #32, REGCOUNTER ;WE MULTIPLY 32x32-BIT VALUES
CLCTNWLOOP:
RRC.W &FREQUENCYHIGHEST
RRC.W &FREQUENCYHIGH ;SHIFT FREQUENCY TO RIGHT
RRC.W &FREQUENCYLOW
RRC.W &FREQUENCYLOWEST
JNC CLCTNWTEST ;IF CARRY 0 GOTO CLCTNWTEST
ADD &TDIVSLOWEST, &MULREGLOWEST ;IF CARRY 1 ADD TDIVS TO PRODUCT
ADDC &TDIVSLOW, &MULREGLOW
ADDC &TDIVSHIGH, &MULREGHIGH
ADDC &TDIVSHIGHEST, &MULREGHIGHEST
CLCTNWTEST:
RLA.W &TDIVSLOWEST ;SHIFT TDIVS TO LEFT
RLC.W &TDIVSLOW
RLC.W &TDIVSHIGH
RLC.W &TDIVSHIGHEST
DEC.W REGCOUNTER ;DECREASE COUNTER
JNZ CLCTNWLOOP ;IF COUNTER NOT 0 GOTO CLCTNWLOOP
CLCTNWSTORE:
MOV.W &MULREGLOW, REGTUNINGLOW ;IF COUNTER IS 0 COPY PRODUCT TO TUNING WORD
MOV.W &MULREGHIGH, REGTUNINGHIGH
JMP SETSR ;GOTO SET STATUS REGISTER
DDSINTERRUPT:
BIC.W #CCIFG, &TACCTL0 ;CLEAR C/C 0 CCIFG IRQ FLAG
BIT.W #OSC1MUTE, OSCSTATUS
JZ DDSRETURN
ADD.W REGTUNINGLOW, REGPHASELOW ;ADD TUNING WORD TO PHASEACCUMULATOR
ADDC.W REGTUNINGHIGH, REGPHASEHIGH
CMP.W #0x0400, REGPHASEHIGH
JL DDSRETURN
MOV.W #0, REGPHASEHIGH ;BECAUSE OUR TABLE SIZE IS 1024 IN SIZE
DDSRETURN:
RETI ;RETURN FROM INTERRUPT
PWMINTERRUPT:
BIC.W #CCIFG, &TACCTL1
BIT.W #OSC1MUTE, OSCSTATUS
JZ PWMRETURN
MOV.B SINTABLE(REGPHASEHIGH), &TACCR1
PWMRETURN:
RETI
BUTTONINTERRUPT:
BIC.B #BIT3, &P1IFG
XOR.W #OSC1MUTE, OSCSTATUS
MOV.W #0, &TACCR1
RETI
ADCINTERRUPT:
BIC.W #ADC10IFG, &ADC10CTL0
MOV.W &ADC10MEM, REGPITCH
RRA.W REGPITCH
BIC.W #BIT0, REGPITCH
BIC.W #BIT1, REGPITCH
MOV.W PITCHTABLE(REGPITCH), REGTUNINGHIGH
MOV.W PITCHTABLE+2(REGPITCH), REGTUNINGLOW
RRA.W REGPITCH
RRA.W REGPITCH
RETI
; Frequency Table
PITCHTABLE:
DW 0, 17557 ;C-1
DW 0, 18601 ;C#-1
DW 0, 19707 ;D-1
DW 0, 20879 ;D#-1
DW 0, 22120 ;E-1
DW 0, 23436 ;F-1
DW 0, 24829 ;F#-1
DW 0, 26306 ;G-1
DW 0, 27870 ;G#-1
DW 0, 29527 ;A-1
DW 0, 31283 ;A#-1
DW 0, 33143 ;B-1
DW 0, 35114 ;C0
DW 0, 37202 ;C#0
DW 0, 39415 ;D0
DW 0, 41758 ;D#0
DW 0, 44241 ;E0
DW 0, 46872 ;F0
DW 0, 49659 ;F#0
DW 0, 52612 ;G0
DW 0, 55741 ;G#0
DW 0, 59055 ;A0
DW 0, 62567 ;A#0
DW 1, 751 ;B0
DW 1, 4693 ;C1
DW 1, 8869 ;C#1
DW 1, 13294 ;D1
DW 1, 17981 ;D#1
DW 1, 22947 ;E1
DW 1, 28209 ;F1
DW 1, 33783 ;F#1
DW 1, 39689 ;G1
DW 1, 45946 ;G#1
DW 1, 52575 ;A1
DW 1, 59598 ;A#1
DW 2, 1503 ;B1
DW 2, 9387 ;C2
DW 2, 17739 ;C#2
DW 2, 26588 ;D2
DW 2, 35963 ;D#2
DW 2, 45895 ;E2
DW 2, 56418 ;F2
DW 3, 2031 ;F#2
DW 3, 13842 ;G2
DW 3, 26357 ;G#2
DW 3, 39615 ;A2
DW 3, 53661 ;A#2
DW 4, 3007 ;B2
DW 4, 18774 ;C3
DW 4, 35478 ;C#3
DW 4, 53176 ;D3
DW 5, 6390 ;D#3
DW 5, 26254 ;E3
DW 5, 47300 ;F3
DW 6, 4062 ;F#3
DW 6, 27685 ;G3
DW 6, 52714 ;G#3
DW 7, 13694 ;A3
DW 7, 41787 ;A#3
DW 8, 6015 ;B3
DW 8, 37548 ;C4
DW 9, 5421 ;C#4
DW 9, 40816 ;D4
DW 10, 12780 ;D#4
DW 10, 52509 ;E4
DW 11, 29065 ;F4
DW 12, 8124 ;F#4
DW 12, 55371 ;G4
DW 13, 39892 ;G#4
DW 14, 27388 ;A4
DW 15, 18039 ;A#4
DW 16, 12030 ;B4
DW 17, 9561 ;C5
DW 18, 10842 ;C#5
DW 19, 16096 ;D5
DW 20, 25560 ;D#5
DW 21, 39483 ;E5
DW 22, 58131 ;F5
DW 24, 16249 ;F#5
DW 25, 45207 ;G5
DW 27, 14248 ;G#5
DW 28, 54777 ;A5
DW 30, 36078 ;A#5
DW 32, 24060 ;B5
DW 34, 19122 ;C6
DW 36, 21684 ;C#6
DW 38, 32193 ;D6
DW 40, 51120 ;D#6
DW 43, 13431 ;E6
DW 45, 50727 ;F6
DW 48, 32499 ;F#6
DW 51, 24879 ;G6
DW 54, 28496 ;G#6
DW 57, 44019 ;A6
DW 61, 6620 ;A#6
DW 64, 48121 ;B6
DW 68, 38244 ;C7
DW 72, 43369 ;C#7
DW 76, 64386 ;D7
DW 81, 36704 ;D#7
DW 86, 26862 ;E7
DW 91, 35919 ;F7
DW 96, 64999 ;F#7
DW 102, 49758 ;G7
DW 108, 56992 ;G#7
DW 115, 22502 ;A7
DW 122, 13240 ;A#7
DW 129, 30706 ;B7
DW 137, 10953 ;C8
DW 145, 21202 ;C#8
DW 153, 63236 ;D8
DW 163, 7873 ;D#8
DW 172, 53724 ;E8
DW 183, 6302 ;F8
DW 193, 64463 ;F#8
DW 205, 33980 ;G8
DW 217, 48448 ;G#8
DW 230, 45004 ;A8
DW 244, 26480 ;A#8
DW 258, 61413 ;B8
DW 274, 21907 ;C9
DW 290, 42405 ;C#9
DW 307, 60937 ;D9
DW 326, 15747 ;D#9
DW 345, 41913 ;E9
DW 366, 12605 ;F9
DW 387, 63391 ;F#9
DW 411, 2425 ;G9
; Sine Wave Table
SINTABLE:
DB 128,128,129,130,131,131,132,133,134,135,135,136,137,138,138,139
DB 140,141,142,142,143,144,145,145,146,147,148,149,149,150,151,152
DB 152,153,154,155,155,156,157,158,158,159,160,161,162,162,163,164
DB 165,165,166,167,167,168,169,170,170,171,172,173,173,174,175,176
DB 176,177,178,178,179,180,181,181,182,183,183,184,185,186,186,187
DB 188,188,189,190,190,191,192,192,193,194,194,195,196,196,197,198
DB 198,199,200,200,201,202,202,203,203,204,205,205,206,207,207,208
DB 208,209,210,210,211,211,212,213,213,214,214,215,215,216,217,217
DB 218,218,219,219,220,220,221,221,222,222,223,224,224,225,225,226
DB 226,227,227,228,228,228,229,229,230,230,231,231,232,232,233,233
DB 234,234,234,235,235,236,236,236,237,237,238,238,238,239,239,240
DB 240,240,241,241,241,242,242,242,243,243,243,244,244,244,245,245
DB 245,246,246,246,246,247,247,247,248,248,248,248,249,249,249,249
DB 250,250,250,250,250,251,251,251,251,251,252,252,252,252,252,252
DB 253,253,253,253,253,253,253,254,254,254,254,254,254,254,254,254
DB 254,254,255,255,255,255,255,255,255,255,255,255,255,255,255,255
DB 255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,254
DB 254,254,254,254,254,254,254,254,254,254,253,253,253,253,253,253
DB 253,252,252,252,252,252,252,251,251,251,251,251,250,250,250,250
DB 250,249,249,249,249,248,248,248,248,247,247,247,246,246,246,246
DB 245,245,245,244,244,244,243,243,243,242,242,242,241,241,241,240
DB 240,240,239,239,238,238,238,237,237,236,236,236,235,235,234,234
DB 234,233,233,232,232,231,231,230,230,229,229,228,228,228,227,227
DB 226,226,225,225,224,224,223,222,222,221,221,220,220,219,219,218
DB 218,217,217,216,215,215,214,214,213,213,212,211,211,210,210,209
DB 208,208,207,207,206,205,205,204,203,203,202,202,201,200,200,199
DB 198,198,197,196,196,195,194,194,193,192,192,191,190,190,189,188
DB 188,187,186,186,185,184,183,183,182,181,181,180,179,178,178,177
DB 176,176,175,174,173,173,172,171,170,170,169,168,167,167,166,165
DB 165,164,163,162,162,161,160,159,158,158,157,156,155,155,154,153
DB 152,152,151,150,149,149,148,147,146,145,145,144,143,142,142,141
DB 140,139,138,138,137,136,135,135,134,133,132,131,131,130,129,128
DB 128,127,126,125,124,124,123,122,121,120,120,119,118,117,117,116
DB 115,114,113,113,112,111,110,110,109,108,107,106,106,105,104,103
DB 103,102,101,100,100,99,98,97,97,96,95,94,93,93,92,91
DB 90,90,89,88,88,87,86,85,85,84,83,82,82,81,80,79
DB 79,78,77,77,76,75,74,74,73,72,72,71,70,69,69,68
DB 67,67,66,65,65,64,63,63,62,61,61,60,59,59,58,57
DB 57,56,55,55,54,53,53,52,52,51,50,50,49,48,48,47
DB 47,46,45,45,44,44,43,42,42,41,41,40,40,39,38,38
DB 37,37,36,36,35,35,34,34,33,33,32,31,31,30,30,29
DB 29,28,28,27,27,27,26,26,25,25,24,24,23,23,22,22
DB 21,21,21,20,20,19,19,19,18,18,17,17,17,16,16,15
DB 15,15,14,14,14,13,13,13,12,12,12,11,11,11,10,10
DB 10,9,9,9,9,8,8,8,7,7,7,7,6,6,6,6
DB 5,5,5,5,5,4,4,4,4,4,3,3,3,3,3,3
DB 2,2,2,2,2,2,2,1,1,1,1,1,1,1,1,1
DB 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0
DB 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
DB 1,1,1,1,1,1,1,1,1,1,2,2,2,2,2,2
DB 2,3,3,3,3,3,3,4,4,4,4,4,5,5,5,5
DB 5,6,6,6,6,7,7,7,7,8,8,8,9,9,9,9
DB 10,10,10,11,11,11,12,12,12,13,13,13,14,14,14,15
DB 15,15,16,16,17,17,17,18,18,19,19,19,20,20,21,21
DB 21,22,22,23,23,24,24,25,25,26,26,27,27,27,28,28
DB 29,29,30,30,31,31,32,33,33,34,34,35,35,36,36,37
DB 37,38,38,39,40,40,41,41,42,42,43,44,44,45,45,46
DB 47,47,48,48,49,50,50,51,52,52,53,53,54,55,55,56
DB 57,57,58,59,59,60,61,61,62,63,63,64,65,65,66,67
DB 67,68,69,69,70,71,72,72,73,74,74,75,76,77,77,78
DB 79,79,80,81,82,82,83,84,85,85,86,87,88,88,89,90
DB 90,91,92,93,93,94,95,96,97,97,98,99,100,100,101,102
DB 103,103,104,105,106,106,107,108,109,110,110,111,112,113,113,114
DB 115,116,117,117,118,119,120,120,121,122,123,124,124,125,126,127
; Triangle Wave Table
TRIANGLETABLE:
DB 0x0,0x1,0x1,0x2,0x2,0x3,0x3,0x4,0x4,0x5,0x5,0x6,0x6,0x7,0x7,0x8
DB 0x8,0x9,0x9,0xa,0xa,0xb,0xb,0xc,0xc,0xd,0xd,0xe,0xe,0xf,0xf,0x10
DB 0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15,0x16,0x16,0x17,0x17,0x18
DB 0x18,0x19,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1e,0x1e,0x1f,0x1f,0x20
DB 0x20,0x21,0x21,0x22,0x22,0x23,0x23,0x24,0x24,0x25,0x25,0x26,0x26,0x27,0x27,0x28
DB 0x28,0x29,0x29,0x2a,0x2a,0x2b,0x2b,0x2c,0x2c,0x2d,0x2d,0x2e,0x2e,0x2f,0x2f,0x30
DB 0x30,0x31,0x31,0x32,0x32,0x33,0x33,0x34,0x34,0x35,0x35,0x36,0x36,0x37,0x37,0x38
DB 0x38,0x39,0x39,0x3a,0x3a,0x3b,0x3b,0x3c,0x3c,0x3d,0x3d,0x3e,0x3e,0x3f,0x3f,0x40
DB 0x40,0x41,0x41,0x42,0x42,0x43,0x43,0x44,0x44,0x45,0x45,0x46,0x46,0x47,0x47,0x48
DB 0x48,0x49,0x49,0x4a,0x4a,0x4b,0x4b,0x4c,0x4c,0x4d,0x4d,0x4e,0x4e,0x4f,0x4f,0x50
DB 0x50,0x51,0x51,0x52,0x52,0x53,0x53,0x54,0x54,0x55,0x55,0x56,0x56,0x57,0x57,0x58
DB 0x58,0x59,0x59,0x5a,0x5a,0x5b,0x5b,0x5c,0x5c,0x5d,0x5d,0x5e,0x5e,0x5f,0x5f,0x60
DB 0x60,0x61,0x61,0x62,0x62,0x63,0x63,0x64,0x64,0x65,0x65,0x66,0x66,0x67,0x67,0x68
DB 0x68,0x69,0x69,0x6a,0x6a,0x6b,0x6b,0x6c,0x6c,0x6d,0x6d,0x6e,0x6e,0x6f,0x6f,0x70
DB 0x70,0x71,0x71,0x72,0x72,0x73,0x73,0x74,0x74,0x75,0x75,0x76,0x76,0x77,0x77,0x78
DB 0x78,0x79,0x79,0x7a,0x7a,0x7b,0x7b,0x7c,0x7c,0x7d,0x7d,0x7e,0x7e,0x7f,0x7f,0x80
DB 0x80,0x80,0x81,0x81,0x82,0x82,0x83,0x83,0x84,0x84,0x85,0x85,0x86,0x86,0x87,0x87
DB 0x88,0x88,0x89,0x89,0x8a,0x8a,0x8b,0x8b,0x8c,0x8c,0x8d,0x8d,0x8e,0x8e,0x8f,0x8f
DB 0x90,0x90,0x91,0x91,0x92,0x92,0x93,0x93,0x94,0x94,0x95,0x95,0x96,0x96,0x97,0x97
DB 0x98,0x98,0x99,0x99,0x9a,0x9a,0x9b,0x9b,0x9c,0x9c,0x9d,0x9d,0x9e,0x9e,0x9f,0x9f
DB 0xa0,0xa0,0xa1,0xa1,0xa2,0xa2,0xa3,0xa3,0xa4,0xa4,0xa5,0xa5,0xa6,0xa6,0xa7,0xa7
DB 0xa8,0xa8,0xa9,0xa9,0xaa,0xaa,0xab,0xab,0xac,0xac,0xad,0xad,0xae,0xae,0xaf,0xaf
DB 0xb0,0xb0,0xb1,0xb1,0xb2,0xb2,0xb3,0xb3,0xb4,0xb4,0xb5,0xb5,0xb6,0xb6,0xb7,0xb7
DB 0xb8,0xb8,0xb9,0xb9,0xba,0xba,0xbb,0xbb,0xbc,0xbc,0xbd,0xbd,0xbe,0xbe,0xbf,0xbf
DB 0xc0,0xc0,0xc1,0xc1,0xc2,0xc2,0xc3,0xc3,0xc4,0xc4,0xc5,0xc5,0xc6,0xc6,0xc7,0xc7
DB 0xc8,0xc8,0xc9,0xc9,0xca,0xca,0xcb,0xcb,0xcc,0xcc,0xcd,0xcd,0xce,0xce,0xcf,0xcf
DB 0xd0,0xd0,0xd1,0xd1,0xd2,0xd2,0xd3,0xd3,0xd4,0xd4,0xd5,0xd5,0xd6,0xd6,0xd7,0xd7
DB 0xd8,0xd8,0xd9,0xd9,0xda,0xda,0xdb,0xdb,0xdc,0xdc,0xdd,0xdd,0xde,0xde,0xdf,0xdf
DB 0xe0,0xe0,0xe1,0xe1,0xe2,0xe2,0xe3,0xe3,0xe4,0xe4,0xe5,0xe5,0xe6,0xe6,0xe7,0xe7
DB 0xe8,0xe8,0xe9,0xe9,0xea,0xea,0xeb,0xeb,0xec,0xec,0xed,0xed,0xee,0xee,0xef,0xef
DB 0xf0,0xf0,0xf1,0xf1,0xf2,0xf2,0xf3,0xf3,0xf4,0xf4,0xf5,0xf5,0xf6,0xf6,0xf7,0xf7
DB 0xf8,0xf8,0xf9,0xf9,0xfa,0xfa,0xfb,0xfb,0xfc,0xfc,0xfd,0xfd,0xfe,0xfe,0xff,0xff
DB 0xff,0xfe,0xfe,0xfd,0xfd,0xfc,0xfc,0xfb,0xfb,0xfa,0xfa,0xf9,0xf9,0xf8,0xf8,0xf7
DB 0xf7,0xf6,0xf6,0xf5,0xf5,0xf4,0xf4,0xf3,0xf3,0xf2,0xf2,0xf1,0xf1,0xf0,0xf0,0xef
DB 0xef,0xee,0xee,0xed,0xed,0xec,0xec,0xeb,0xeb,0xea,0xea,0xe9,0xe9,0xe8,0xe8,0xe7
DB 0xe7,0xe6,0xe6,0xe5,0xe5,0xe4,0xe4,0xe3,0xe3,0xe2,0xe2,0xe1,0xe1,0xe0,0xe0,0xdf
DB 0xdf,0xde,0xde,0xdd,0xdd,0xdc,0xdc,0xdb,0xdb,0xda,0xda,0xd9,0xd9,0xd8,0xd8,0xd7
DB 0xd7,0xd6,0xd6,0xd5,0xd5,0xd4,0xd4,0xd3,0xd3,0xd2,0xd2,0xd1,0xd1,0xd0,0xd0,0xcf
DB 0xcf,0xce,0xce,0xcd,0xcd,0xcc,0xcc,0xcb,0xcb,0xca,0xca,0xc9,0xc9,0xc8,0xc8,0xc7
DB 0xc7,0xc6,0xc6,0xc5,0xc5,0xc4,0xc4,0xc3,0xc3,0xc2,0xc2,0xc1,0xc1,0xc0,0xc0,0xbf
DB 0xbf,0xbe,0xbe,0xbd,0xbd,0xbc,0xbc,0xbb,0xbb,0xba,0xba,0xb9,0xb9,0xb8,0xb8,0xb7
DB 0xb7,0xb6,0xb6,0xb5,0xb5,0xb4,0xb4,0xb3,0xb3,0xb2,0xb2,0xb1,0xb1,0xb0,0xb0,0xaf
DB 0xaf,0xae,0xae,0xad,0xad,0xac,0xac,0xab,0xab,0xaa,0xaa,0xa9,0xa9,0xa8,0xa8,0xa7
DB 0xa7,0xa6,0xa6,0xa5,0xa5,0xa4,0xa4,0xa3,0xa3,0xa2,0xa2,0xa1,0xa1,0xa0,0xa0,0x9f
DB 0x9f,0x9e,0x9e,0x9d,0x9d,0x9c,0x9c,0x9b,0x9b,0x9a,0x9a,0x99,0x99,0x98,0x98,0x97
DB 0x97,0x96,0x96,0x95,0x95,0x94,0x94,0x93,0x93,0x92,0x92,0x91,0x91,0x90,0x90,0x8f
DB 0x8f,0x8e,0x8e,0x8d,0x8d,0x8c,0x8c,0x8b,0x8b,0x8a,0x8a,0x89,0x89,0x88,0x88,0x87
DB 0x87,0x86,0x86,0x85,0x85,0x84,0x84,0x83,0x83,0x82,0x82,0x81,0x81,0x80,0x80,0x80
DB 0x7f,0x7f,0x7e,0x7e,0x7d,0x7d,0x7c,0x7c,0x7b,0x7b,0x7a,0x7a,0x79,0x79,0x78,0x78
DB 0x77,0x77,0x76,0x76,0x75,0x75,0x74,0x74,0x73,0x73,0x72,0x72,0x71,0x71,0x70,0x70
DB 0x6f,0x6f,0x6e,0x6e,0x6d,0x6d,0x6c,0x6c,0x6b,0x6b,0x6a,0x6a,0x69,0x69,0x68,0x68
DB 0x67,0x67,0x66,0x66,0x65,0x65,0x64,0x64,0x63,0x63,0x62,0x62,0x61,0x61,0x60,0x60
DB 0x5f,0x5f,0x5e,0x5e,0x5d,0x5d,0x5c,0x5c,0x5b,0x5b,0x5a,0x5a,0x59,0x59,0x58,0x58
DB 0x57,0x57,0x56,0x56,0x55,0x55,0x54,0x54,0x53,0x53,0x52,0x52,0x51,0x51,0x50,0x50
DB 0x4f,0x4f,0x4e,0x4e,0x4d,0x4d,0x4c,0x4c,0x4b,0x4b,0x4a,0x4a,0x49,0x49,0x48,0x48
DB 0x47,0x47,0x46,0x46,0x45,0x45,0x44,0x44,0x43,0x43,0x42,0x42,0x41,0x41,0x40,0x40
DB 0x3f,0x3f,0x3e,0x3e,0x3d,0x3d,0x3c,0x3c,0x3b,0x3b,0x3a,0x3a,0x39,0x39,0x38,0x38
DB 0x37,0x37,0x36,0x36,0x35,0x35,0x34,0x34,0x33,0x33,0x32,0x32,0x31,0x31,0x30,0x30
DB 0x2f,0x2f,0x2e,0x2e,0x2d,0x2d,0x2c,0x2c,0x2b,0x2b,0x2a,0x2a,0x29,0x29,0x28,0x28
DB 0x27,0x27,0x26,0x26,0x25,0x25,0x24,0x24,0x23,0x23,0x22,0x22,0x21,0x21,0x20,0x20
DB 0x1f,0x1f,0x1e,0x1e,0x1d,0x1d,0x1c,0x1c,0x1b,0x1b,0x1a,0x1a,0x19,0x19,0x18,0x18
DB 0x17,0x17,0x16,0x16,0x15,0x15,0x14,0x14,0x13,0x13,0x12,0x12,0x11,0x11,0x10,0x10
DB 0xf,0xf,0xe,0xe,0xd,0xd,0xc,0xc,0xb,0xb,0xa,0xa,0x9,0x9,0x8,0x8
DB 0x7,0x7,0x6,0x6,0x5,0x5,0x4,0x4,0x3,0x3,0x2,0x2,0x1,0x1,0x0,0x0
.org RAM
FREQUENCYLOWEST:
.org RAM+2
FREQUENCYLOW:
.org RAM+4
FREQUENCYHIGH:
.org RAM+6
FREQUENCYHIGHEST:
.org RAM+8
TDIVSLOWEST:
.org RAM+10
TDIVSLOW:
.org RAM+12
TDIVSHIGH:
.org RAM+14
TDIVSHIGHEST:
.org RAM+16
MULREGLOWEST:
.org RAM+18
MULREGLOW:
.org RAM+20
MULREGHIGH:
.org RAM+22
MULREGHIGHEST:
; Interrupt Vectors
.org 0xFFE4 ;P1 INTERRUPT
DW BUTTONINTERRUPT
.org 0xFFEA ;ADC10 INTERRUPT
DW ADCINTERRUPT
.org 0xFFF0 ;TACCIE1 INTERRUPT
DW PWMINTERRUPT
.org 0xFFF2 ;TACCIE0 INTERRUPT
DW DDSINTERRUPT
.org 0xFFFE ;RESET INTERRUPT
DW RESET
.end | 41.75705 | 117 | 0.648883 |
b091d59180d946a034998b16f623f04b35180a97 | 2,378 | asm | Assembly | cc4x86/tests/regressive/asm_listings/redundant_copy__optimize_noregalloc.asm | artyompal/C-compiler | 0c13e96b926d4c3282be8e9629cbc7ba439ea2d4 | [
"MIT"
] | 4 | 2017-03-19T20:10:55.000Z | 2022-01-20T08:34:25.000Z | cc4x86/tests/regressive/asm_listings/redundant_copy__optimize_noregalloc.asm | artyompal/C-compiler | 0c13e96b926d4c3282be8e9629cbc7ba439ea2d4 | [
"MIT"
] | null | null | null | cc4x86/tests/regressive/asm_listings/redundant_copy__optimize_noregalloc.asm | artyompal/C-compiler | 0c13e96b926d4c3282be8e9629cbc7ba439ea2d4 | [
"MIT"
] | null | null | null |
.686
.model flat
.xmm
.code
_test proc
create_stack_frame
; start of inline function test1
mov dword30,256
imul dword30,512
sub dword30,131072
; end of inline function test1
cmp dword30,0
je label0000
mov dword5,1
set_retval dword5
destroy_stack_frame
ret
label0000:
; start of inline function test2
mov dword41,555
add dword41,666
sub dword41,1221
; end of inline function test2
cmp dword41,0
je label0001
mov dword10,2
set_retval dword10
destroy_stack_frame
ret
label0001:
; start of inline function test3
mov dword105,444
mov dword103,222
mov dword106,dword103
cmp dword105,0
jle label0007
mov dword103,111
jmp label0008
label0007:
mov dword106,dword105
label0008:
mov dword59,dword106
add dword59,dword103
add dword59,111
sub dword59,dword105
; end of inline function test3
cmp dword59,0
je label0002
mov dword15,3
set_retval dword15
destroy_stack_frame
ret
label0002:
; start of inline function test4
mov dword111,5
inc dword111
mov dword72,dword111
add dword72,4
sub dword72,10
; end of inline function test4
cmp dword72,0
je label0003
mov dword20,4
set_retval dword20
destroy_stack_frame
ret
label0003:
; start of inline function test5
mov dword116,888
cmp dword116,0
jle label000b
mov dword117,444
jmp label000c
label000b:
mov dword117,222
label000c:
mov dword90,dword117
add dword90,444
sub dword90,dword116
; end of inline function test5
cmp dword90,0
je label0004
mov dword25,3
set_retval dword25
destroy_stack_frame
ret
label0004:
mov dword26,0
set_retval dword26
destroy_stack_frame
ret
_test endp
end
| 24.265306 | 34 | 0.527334 |
728cd9711fd634c937d3b44b1071d48f7bbe7f17 | 2,817 | asm | Assembly | Satellite Decryption/03-Number-Subroutine/decrypt-packet.asm | JaredsOSToolbox/AssemblerPrograms | a9158c5b135689ec39c71944c121d65a61d8a6b4 | [
"MIT"
] | null | null | null | Satellite Decryption/03-Number-Subroutine/decrypt-packet.asm | JaredsOSToolbox/AssemblerPrograms | a9158c5b135689ec39c71944c121d65a61d8a6b4 | [
"MIT"
] | null | null | null | Satellite Decryption/03-Number-Subroutine/decrypt-packet.asm | JaredsOSToolbox/AssemblerPrograms | a9158c5b135689ec39c71944c121d65a61d8a6b4 | [
"MIT"
] | null | null | null | ; taken from here cause I was banging my head against a wall for hours -> https://gist.github.com/BertrandBordage/10921263
; checking if file exists -> https://gist.github.com/Archenoth/5380671
; This program will decrypt a packet from an incoming satallite
; It decrypts the packet in memory so there is no need to write subroutines to reverse the order of the bytes
; Written by Jared Dyreson
; CPSC-240 TR @ 11:30 to 13:20
; Our Macros
%define SYS_EXIT 60
%define SYS_READ 0
%define SYS_WRITE 1
%define SYS_OPEN 2
%define SYS_CLOSE 3
%define STDOUT 1
%define SYS_CREATE 85
%define BUFFER_SIZE 180
; headers to clean this code up
%include "print.asm"
%include "decryption_algorithm.asm"
%include "packet_struct.inc"
section .text
global _start
_start:
; So we can read in our argument from argv[]
add rsp, byte 0x10
pop rdi
_check_file_continutity:
; basic if/else control flow -> https://stackoverflow.com/questions/14292903/complex-if-statement-in-assembly
mov rdx,0
cmp rdx,rax
jle _cont
jnle _exit_failiure
_cont:
; open the file
mov rax, SYS_OPEN
mov rsi, 0
syscall
mov [fd], rax
jmp _read_write
_read_write:
; Read the file into the buffer
mov rax, SYS_READ
mov rdi, [fd]
mov rsi, file_buffer
mov rdx, BUFFER_SIZE
syscall
cmp rax, 0
je close_file
jp _read_write
_exit_failiure:
; exit with code 1
mov rax, 60
mov rdi, 1
syscall
close_file:
; Close the file stream
mov rax, SYS_CLOSE
mov rdi, fd
syscall
xor r8, r8
xor rax, rax
call decrypt
exit:
; implementing code
; mov eax, dword [file_buffer+msg_length]
; call cvtEndian
; mov dword [file_buffer+msg_length], eax
mov rsi, status_message
mov rdx, status_message_length
call print
mov rsi, file_buffer+status_msg
mov rdx, 128
call print
mov rsi, endl
mov rdx, 2
call print
mov rsi, status_message_size
mov rdx, status_message_size_length
call print
; mov eax, dword[file_buffer+msg_length]
; call cvtEndian
; mov dword[file_buffer+msg_length], eax
mov eax, dword[file_buffer+NodeNumber]
call cvtEndian
mov dword[file_buffer+NodeNumber], eax
call printDWord
; mov rsi, file_buffer+msg_length
; mov rdx, 1
; call print
; mov rsi, file_buffer+msg_length
; mov rdx, 1
; call print
; mov rsi, rax
; mov rdx, rbx
; call print
; mov rsi, file_buffer
; mov rdx, BUFFER_SIZE
; call print
mov rsi, endl
mov rdx, 2
call print
mov rax, 60
mov rdi, BUFFER_SIZE
syscall
section .data
key: dq 0x36,0x13,0x92,0xa5,0x5a,0x27,0xf3,0x00,0x32
endl: db 0xA, 0xD
status_message db "Status Message: "
status_message_length equ $-status_message
status_message_size db "Status Message Length: "
status_message_size_length equ $-status_message_size
fd dw 0
section .bss
file_buffer resb BUFFER_SIZE
| 21.180451 | 122 | 0.729499 |
410d0b155dc3259ac551ecd41814e2408f3f36cc | 2,451 | asm | Assembly | 31.asm | Dhananjay8/MIT_lab | 6b3487a04440372133773298ed64627a1463f151 | [
"Apache-2.0"
] | null | null | null | 31.asm | Dhananjay8/MIT_lab | 6b3487a04440372133773298ed64627a1463f151 | [
"Apache-2.0"
] | null | null | null | 31.asm | Dhananjay8/MIT_lab | 6b3487a04440372133773298ed64627a1463f151 | [
"Apache-2.0"
] | null | null | null | section .data
msg1: db "enter choice",10
db "1.hex to bcd",10
db "2.bcd to hex",10
db "3.exit",10
len1:equ $-msg1
msg2: db "enter 4 digit hex no:"
len2: equ $-msg2
msg3: db "enter 5 digit BCD no:"
len3: equ $-msg3
msg4: db "BCD no :"
len4: equ $-msg4
msg5: db "hex no :"
len5: equ $-msg5
n: db "",10
section .bss
num: resb 6
res: resb 8
chc: resb 2
cnt: resb 1
cnt1: resb 1
%macro write 2
mov rax,1
mov rdi,1
mov rsi,%1
mov rdx,%2
syscall
%endmacro
%macro read 2
mov rax,0
mov rdi,0
mov rsi,%1
mov rdx,%2
syscall
%endmacro
global _start
section .text
_start:
menu:
write msg1,len1
read chc,2
cmp byte[chc],31h
je hextobcd
cmp byte[chc],32h
je bcdtohex
jmp exit
hextobcd:
write msg2,len2
read num,5
mov byte[cnt],5
mov byte[cnt1],04;for conversin to ascii
call asc_hex ;store result in rax
mov rbx,0Ah ;divide by 10
up2: mov rdx,00
div rbx ;rax/rbx quo in rax ,rem in rdx
push rdx
dec byte[cnt]
jnz up2
mov ecx,0
mov esi,res
mov byte[cnt],5
above: pop rcx ;h_a
cmp cl,09h
jbe add30
add cl,07h
add30: add cl,30h
mov byte[esi],cl
inc esi
dec byte[cnt]
jnz above
mov byte[esi],10 ;set end to new line
write res,5
write n,1
jmp menu
bcdtohex:
write msg3,len3
read num,6
mov qword[res],0
mov byte[cnt1],05 ;for conversion 5 digit
call asc_hex
mov rcx,0
mov rcx,rax
mov rax,0
mov rbx,0
mov al,cl
and al,0Fh
mov bx,01h
mul bx
adc qword[res],rax
mov rax,0
mov rbx,0
ror rcx,04 ;ror
mov al,cl ;dont forget to and
and al,0Fh
mov bx,0Ah
mul bx
adc qword[res],rax
mov rax,0
mov rbx,0
ror rcx,04
mov al,cl
and al,0Fh
mov bx,64h
mul bx
adc qword[res],rax
mov rax,0
mov rbx,0
ror rcx,04
mov al,cl
and al,0Fh
mov bx,3E8h
mul bx
adc qword[res],rax
mov rax,0
mov rbx,0
ror rcx,04
mov al,cl
and al,0Fh
mov bx,2710h
mul bx
adc qword[res],rax
mov rcx,0
mov rcx,qword[res]
mov byte[cnt1],05h
mov rsi,res
rol ecx,16 ; from ecx=00065535 to ecx=65535000
up3:
rol ecx,4 ;con to hex to ascii
mov bl,cl
and bl,0Fh
cmp bl,09h
jbe add3
add bl,07h
add3: add bl,30h
mov [rsi],bl
inc rsi
dec byte[cnt1]
jnz up3
mov byte[rsi],10 ;;dont forget
write msg5,len5
write res,4
write n,1
jmp menu
asc_hex:
mov rsi,num
mov rax,0
up1:
rol rax,04
mov bl,[rsi]
cmp bl,39h
jbe sub30
sub bl,07h
sub30: sub bl,30h
add al,bl
inc rsi
dec byte[cnt1]
jnz up1 ;in eax
ret
exit:
mov rax,60
mov rdi,00
syscall
| 12.073892 | 48 | 0.661363 |
db9b2a75805e95ee9869feefdc9c8bf7df7cc4d9 | 880 | asm | Assembly | CO2008/W4/ex3.asm | Smithienious/hcmut-201 | be16b77831aae83ff42e656a181881686c74e674 | [
"MIT"
] | null | null | null | CO2008/W4/ex3.asm | Smithienious/hcmut-201 | be16b77831aae83ff42e656a181881686c74e674 | [
"MIT"
] | 2 | 2020-10-12T09:57:12.000Z | 2020-11-09T11:05:01.000Z | CO2008/W4/ex3.asm | Smithienious/hcmut-201 | be16b77831aae83ff42e656a181881686c74e674 | [
"MIT"
] | 4 | 2020-10-12T10:30:56.000Z | 2020-12-15T14:46:04.000Z | .data:
a: .word 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
msg: .asciiz "Enter an integer: "
msg1: .asciiz "Position of the integer: "
msg2: .asciiz "The integer does not exist in the array"
# Start program code
.text:
.globl main
main:
li $s7, 40 # array size
li $s1, 0 # int i = 0
li $s2, 0 # int pos = 0
la $s3, a
li $a0, 0
# Print string msg
li $v0, 4
la $a0, msg
syscall
# Get input and save
li $v0, 5
syscall
move $s0, $v0
WHILE:
slt $t0, $s1, $s7 # while (i < n)
bne $t0, 1, WEXIT
add $t1, $s1, $s3 # index [i]
lw $t1, 0($t1) # get a[i]
beq $t1, $s0, TRUE
addi $s1, $s1, 4
addi $s2, $s2, 1
j WHILE
WEXIT:
# Print string msg2
li $v0, 4
la $a0, msg2
syscall
j EXIT
TRUE:
# Print string msg1
li $v0, 4
la $a0, msg1
syscall
# Print pos
li $v0, 1
move $a0, $s2
syscall
EXIT:
# Exit
li $v0, 10
syscall
| 14.915254 | 56 | 0.556818 |
01aa31e443daf3e79ff6dd8e4602dd49c811d160 | 933 | asm | Assembly | programs/oeis/070/A070824.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/070/A070824.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/070/A070824.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A070824: Number of divisors of n which are > 1 and < n (nontrivial divisors).
; 0,0,0,1,0,2,0,2,1,2,0,4,0,2,2,3,0,4,0,4,2,2,0,6,1,2,2,4,0,6,0,4,2,2,2,7,0,2,2,6,0,6,0,4,4,2,0,8,1,4,2,4,0,6,2,6,2,2,0,10,0,2,4,5,2,6,0,4,2,6,0,10,0,2,4,4,2,6,0,8,3,2,0,10,2,2,2,6,0,10,2,4,2,2,2,10,0,4,4,7,0,6,0,6,6,2,0,10,0,6,2,8,0,6,2,4,4,2,2,14,1,2,2,4,2,10,0,6,2,6,0,10,2,2,6,6,0,6,0,10,2,2,2,13,2,2,4,4,0,10,0,6,4,6,2,10,0,2,2,10,2,8,0,4,6,2,0,14,1,6,4,4,0,6,4,8,2,2,0,16,0,6,2,6,2,6,2,4,6,6,0,12,0,2,6,7,0,10,0,10,2,2,2,10,2,2,4,8,2,14,0,4,2,2,2,14,2,2,2,10,2,6,0,10,7,2,0,10,0,6,6,6,0,10,2,4,2,6,0,18,0,4,4,4,4,6,2,6,2,6
mov $4,$0
mov $7,2
lpb $7,1
sub $7,1
add $0,$7
add $0,1
mov $2,$0
mov $6,0
lpb $2,1
mov $5,$0
lpb $5,1
trn $5,$2
add $6,1
lpe
sub $2,1
mov $5,2
lpe
sub $0,$5
mov $3,$7
mov $8,$6
lpb $3,1
mov $1,$8
sub $3,1
lpe
lpe
lpb $4,1
sub $1,$8
mov $4,0
lpe
sub $1,3
| 27.441176 | 528 | 0.508039 |
fe618dfe4f4338b6bc93bab3489cf4fe65afd8a5 | 1,948 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i7-8650U_0xd2.log_77_1470.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i7-8650U_0xd2.log_77_1470.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i7-8650U_0xd2.log_77_1470.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r13
push %r15
push %r9
push %rcx
push %rdi
push %rsi
lea addresses_A_ht+0xdd89, %rsi
lea addresses_normal_ht+0x3229, %rdi
nop
nop
nop
nop
dec %r15
mov $74, %rcx
rep movsb
add %rsi, %rsi
lea addresses_normal_ht+0x1d749, %rsi
lea addresses_WT_ht+0x11b49, %rdi
nop
nop
nop
nop
nop
cmp $31217, %r13
mov $52, %rcx
rep movsb
nop
xor $46410, %rdi
lea addresses_UC_ht+0xb8d, %rsi
lea addresses_A_ht+0x1b8f1, %rdi
nop
add $25474, %r9
mov $119, %rcx
rep movsw
nop
nop
cmp %r9, %r9
pop %rsi
pop %rdi
pop %rcx
pop %r9
pop %r15
pop %r13
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %rbp
push %rcx
push %rdi
push %rsi
// Faulty Load
lea addresses_RW+0xb349, %rdi
clflush (%rdi)
nop
dec %rbp
vmovups (%rdi), %ymm7
vextracti128 $0, %ymm7, %xmm7
vpextrq $1, %xmm7, %rcx
lea oracles, %rsi
and $0xff, %rcx
shlq $12, %rcx
mov (%rsi,%rcx,1), %rcx
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_RW', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_RW', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'type': 'addresses_A_ht', 'congruent': 6, 'same': False}, 'dst': {'type': 'addresses_normal_ht', 'congruent': 4, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_normal_ht', 'congruent': 9, 'same': True}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 9, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 2, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 0, 'same': False}}
{'32': 77}
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
*/
| 22.136364 | 230 | 0.662731 |
9d9a61ae2a4cec31986b8d8f2fb3997ac261d198 | 861 | asm | Assembly | programs/oeis/128/A128801.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/128/A128801.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/128/A128801.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A128801: a(n) = n*(n-1)*7^n.
; 0,98,2058,28812,336140,3529470,34588806,322828856,2905459704,25422772410,217505941730,1827049910532,15114685623492,123436599258518,996987917088030,7975903336704240,63275499804520304,498294560960597394,3898422153397614906,30321061193092560380,234589262914979282940,1806337324445340478638,13848586154080943669558,105752839722072660749352,804641171798378940484200,6101862219471040298671850,46130078379201064657959186,347749821627823410498461556,2614563473720301938192136884,19609226052902264536441026630,146731105292406600151989750990,1095592252849969281134856807392,8163929368011061417488771693792,60719224674582269292572739472578,450794243796141090202433974872170,3341180865783163374441569460817260,24724738406795408970867614010047724,182688344894654966284744036852019294
add $0,1
mov $2,7
pow $2,$0
bin $0,2
mul $0,$2
mul $0,2
| 86.1 | 772 | 0.902439 |
5e4c8b9f369f927149639c84fa26c67639344ea0 | 1,522 | asm | Assembly | GloableVarirables.asm | sleepingburrito/BackIsle | 546b4ac35136144c9103e0266bfa8d02a2834e17 | [
"MIT"
] | 1 | 2019-07-23T15:43:01.000Z | 2019-07-23T15:43:01.000Z | GloableVarirables.asm | sleepingburrito/BackIsle | 546b4ac35136144c9103e0266bfa8d02a2834e17 | [
"MIT"
] | null | null | null | GloableVarirables.asm | sleepingburrito/BackIsle | 546b4ac35136144c9103e0266bfa8d02a2834e17 | [
"MIT"
] | null | null | null | SECTION "RAM", WRAM0
spriteOAMBuffer: DS SPRITE_OAM_SIZE_MAX_BYTES
stack: ds STACK_SIZE_MAX
StackPointer: dw ;used for saving
romBank: ds 1 ;(read only) of what bank you are in
frameCounter: dl ;number of frames the game has ran
gameState: ds 1
joyPad: ds 1
joyPadLast: ds 1
tmpVars: ds 16 ;must managed yourself
rngIndex: ds 1
;dialog
;======
dialogTextBank: ds 1 ;set
dialogTextStart: dw ;set
dialogStringBuffer: ds DILOG_CHANGE_MAX_TEXT_ON_SCREEN
dialogStringNull: ds 1 ;null to stop text drawing, never used
dialogExpressIndex: ds 1 ;id of expression to draw
;drawing
;=======
drawTextX: ds 1
drawTextY: ds 1
drawTextPointer: dw
;map
;===
mapBank: ds 1 ;set for floor
mapX: ds 1 ;set for x/y
mapY: ds 1
mapTilePatternBank: ds 1
mapTilePattern: dw ;read only, set with SetMapTilePatternPointer
mapTileMapStart: dw ;read only, set with TileMapStartOffset
;sprites
;=======
spriteIndex: ds 1
spriteBank: ds 1
;npc sprites
;===========
NpcSpriteTileStart: ds 1
NpcSpriteFacingReg: ds 1
NpcSpriteXY: dw
NpcSpriteSpeed: ds 1
;npc Map
;======
mapNpc: ds NPC_MAP_SIZE
;player
;======
playerNpcMapX: ds 1 ;where the player is
playerNpcMapY: ds 1
playerSpriteX: ds 1 ;where to draw the player
playerSpriteY: ds 1
playerFlags: ds 1
playerFacing: ds 1
SECTION "CART RAM", SRAM
;========================
;for save data
gameName: ds GAME_NAME_LENGTH ;used to init cart ram for new game
saveChecksum: ds SRAM_CHECKSOME_SIZE ;check save corruption
| 21.138889 | 66 | 0.706307 |
8588e68b1edc525f86bd41256b582d4cfc7012f5 | 1,877 | asm | Assembly | programs/oeis/216/A216414.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/216/A216414.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/216/A216414.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A216414: a(n) = (-1)^(n-3)*binomial(n,3) - 1.
; 0,-5,9,-21,34,-57,83,-121,164,-221,285,-365,454,-561,679,-817,968,-1141,1329,-1541,1770,-2025,2299,-2601,2924,-3277,3653,-4061,4494,-4961,5455,-5985,6544,-7141,7769,-8437,9138,-9881,10659,-11481,12340,-13245,14189,-15181,16214,-17297,18423,-19601,20824,-22101,23425,-24805,26234,-27721,29259,-30857,32508,-34221,35989,-37821,39710,-41665,43679,-45761,47904,-50117,52393,-54741,57154,-59641,62195,-64825,67524,-70301,73149,-76077,79078,-82161,85319,-88561,91880,-95285,98769,-102341,105994,-109737,113563,-117481,121484,-125581,129765,-134045,138414,-142881,147439,-152097,156848,-161701,166649,-171701,176850,-182105,187459,-192921,198484,-204157,209933,-215821,221814,-227921,234135,-240465,246904,-253461,260129,-266917,273818,-280841,287979,-295241,302620,-310125,317749,-325501,333374,-341377,349503,-357761,366144,-374661,383305,-392085,400994,-410041,419219,-428537,437988,-447581,457309,-467181,477190,-487345,497639,-508081,518664,-529397,540273,-551301,562474,-573801,585275,-596905,608684,-620621,632709,-644957,657358,-669921,682639,-695521,708560,-721765,735129,-748661,762354,-776217,790243,-804441,818804,-833341,848045,-862925,877974,-893201,908599,-924177,939928,-955861,971969,-988261,1004730,-1021385,1038219,-1055241,1072444,-1089837,1107413,-1125181,1143134,-1161281,1179615,-1198145,1216864,-1235781,1254889,-1274197,1293698,-1313401,1333299,-1353401,1373700,-1394205,1414909,-1435821,1456934,-1478257,1499783,-1521521,1543464,-1565621,1587985,-1610565,1633354,-1656361,1679579,-1703017,1726668,-1750541,1774629,-1798941,1823470,-1848225,1873199,-1898401,1923824,-1949477,1975353,-2001461,2027794,-2054361,2081155,-2108185,2135444,-2162941,2190669,-2218637,2246838,-2275281,2303959,-2332881,2362040,-2391445,2421089,-2450981,2481114,-2511497,2542123,-2573001,2604124,-2635501
mov $1,-4
bin $1,$0
sub $1,1
| 268.142857 | 1,798 | 0.777837 |
64f04b26d985535710c21321c5dcdc72b18fcc02 | 7,544 | asm | Assembly | findpdis.asm | rene0/asmstuff | b03f6ab0f621eeabd82a65ca216393c041f93091 | [
"BSD-2-Clause"
] | null | null | null | findpdis.asm | rene0/asmstuff | b03f6ab0f621eeabd82a65ca216393c041f93091 | [
"BSD-2-Clause"
] | null | null | null | findpdis.asm | rene0/asmstuff | b03f6ab0f621eeabd82a65ca216393c041f93091 | [
"BSD-2-Clause"
] | null | null | null | ; Copyright (c) 1997-2000 René Ladan. All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; 1. Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
; OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
; OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
; SUCH DAMAGE.
[SEGMENT .text]
EXTERN OpenFile,CloseFile,GetVidSegment,WipeScreen,Sound,NoSound
EXTERN DecToStr,StrToDec,InitDelay,Delay
; ------------------------------------------------------------------------------
; CheckNumber - 1999-07-12
; DOEL : Kijkt of EDX een PDI is (ZF=1) en schrijft EDX naar het scherm (CX=len)
; ------------------------------------------------------------------------------
%MACRO CheckNumber 0
push EDX ; Bewaar het origineel
mov EAX,EDX ; EAX wordt gedeeld
mov EBX,10 ; Deelfactor
mov CX,0 ; Teller 0
mov DI,18 ; Positie 10 (0-based)
NonZero:
mov EDX,0 ; Hoogste dubbelwoord van N = 0, wis de rest
div EBX ; Deel EAX (=N) door 10
push EDX
add DX,0730h ; Attribuut, naar cijfer
mov [ES:DI],DX
dec DI
dec DI
inc CX ; Weer een cijfer gedaan
test EAX,EAX ; N al 0 ?
JNZ NonZero ; Nee, terug
mov EBX,0 ; controlesom = 0
mov DX,CX ; Kopieer count
PutDigit:
pop EAX
test AL,AL ; Nul?
JZ NextDigit ; Er valt niets op te tellen
cmp AL,1
JNE DoCalc ; PDI berekenen als EAX > 1
inc EBX ; 1 optellen bij controlesom
JMP SHORT NextDigit
DoCalc:
mov ESI,1 ; Mult=1
push CX ; bewaar buitenste count
mov CX,DX ; Tijdelijk buitenste count
AddLoop:
imul ESI,EAX ; CX maal, dus ESI=EAX^CX
dec CX
JNZ AddLoop
pop CX ; hersteld
add EBX,ESI
NextDigit:
dec CX ; sneller dan LOOP
JNZ PutDigit ; ivm pairing
mov CX,DX ; Count weer in CX
pop EDX ; origineel hersteld
cmp EBX,EDX ; ZF=1 -> PDI
%ENDMACRO
; ------------------------------------------------------------------------------
; MoveFilePointer - 1999-07-10
; DOEL : Verplaatst de filepointer naar de code in AL met offset 0.
; LEEST : AL,BX
; GEBRUIKT : DX
; SCHRIJFT : AX,CX,CF
; ------------------------------------------------------------------------------
MoveFilePointer:
push DX ; Bewaar lo(PDICount)
mov AH,0x42 ; Move file pointer (BX=FHandle)
mov CX,0 ; Geen offset
mov DX,0 ; " "
INT 0x21 ; roep DOS aan
pop DX ; Herstel lo(PDICount)
RET
; ------------------------------------------------------------------------------
; WriteNum - 1999-07-09
; DOEL : Schrijft EDX+CRLF naar FindPDIs.LST (formaat in SI, lengte in CX)
; LEEST : CX,EDX,SI,BufNumb
; SCHRIJFT : AX,CX,DI,CF,BufNumb
; GEBRUIKT : DX
; ------------------------------------------------------------------------------
WriteNum:
push DX ; Bewaar lo(PDICount)
lea DI,[BufNumb] ; EDX -> DS:DI
CALL DecToStr
mov AH,0x40 ; Write to file/device
lea DX,[BufNumb] ; van DS:DX
INT 0x21 ; roep DOS aan
mov CX,2 ; lengte CRLF
lea DX,[CRLF]
mov AH,0x40 ; in AX staat het aantal geschreven bytes
INT 0x21 ; roep DOS aan
pop DX ; Herstel lo(PDICount)
RET
; ------------------------------------------------------------------------------
; ReadCounter - 1999-07-12
; DOEL : Haalt de teller op uit de 1e regel van FindPDIs.LST in EDX
; LEEST : AX,(adres) BufNumb
; SCHRIJFT : BX,AH,CX,EDX,SI,CF
; ROEPT AAN : StrToDec
; ------------------------------------------------------------------------------
%MACRO ReadCounter 0
mov BX,AX ; Copy FHandle
mov AH,0x3F ; Read file/device
mov CX,10 ; aantal bytes
lea DX,[BufNumb] ; buffer op DS:DX
INT 0x21 ; roep DOS aan
JC Close ; Bij fout proberen te sluiten
lea SI,[BufNumb]
CALL StrToDec ; DS:SI -> EDX
%ENDMACRO
; ------------------------------------------------------------------------------
; WriteCounter - 1999-07-12
; DOEL : Schrijft EDX naar de 1e regel van FindPDIs.LST
; LEEST : EDX,(adres) BufNumb,FHandle
; SCHRIJFT : AX,CX,DX,SI,DI,CF
; ROEPT AAN : DecToStr,MoveFilePointer
; ------------------------------------------------------------------------------
%MACRO WriteCounter 0
mov BX,FHandle ; Vernietigd door CheckNumber
mov AL,0 ; Move file pointer to top
CALL MoveFilePointer
JC Close ; Bij fout proberen te sluiten
mov CX,9 ; aantal bytes
mov SI,10 ; 10 lang, voorlopende 0
CALL WriteNum ; hierna bestand gesloten
%ENDMACRO
; ------------------------------------------------------------------------------
; WritePDI - 1999-07-09
; DOEL : Voegt EDX toe aan FindPDIs.LST
; ------------------------------------------------------------------------------
%MACRO WritePDI 0
mov BX,FHandle ; Vernietigd door CheckNumber
mov SI,0 ; eigen lengte
CALL WriteNum
JC Close ; bij fout proberen te sluiten
%ENDMACRO
; ------------------------------------------------------------------------------
; Main - 1999-07-10
; DOEL : Dit is het hoofdprogramma
; LEEST : DGroup,AX
; SCHRIJFT : AX,EDX,DS,CF,ZF,Freq
; ROEPT AAN : GetVidSegment,WipeScreen,OpenFile,CloseFile,MoveFilePointer
; MACRO'S : ReadCounter,WriteCounter,CheckNumber,WritePDI
; ------------------------------------------------------------------------------
..start:
mov AX,DGroup ; Zet eigen datasegment in DS op
mov DS,AX ; via een GP-register
CALL GetVidSegment
CALL WipeScreen
CALL InitDelay
CALL OpenFile
JC Einde ; Kon het bestand niet openen
ReadCounter
mov AL,2 ; File pointer naar einde
CALL MoveFilePointer
CheckNumb:
mov AH,0x11 ; 1 cyclus, net als xor
INT 0x16 ; Check keyboard
JNZ Abort ; Geen toets -> ZF=1
CheckNumber
JNZ NextNumb ; Getal is geen PDI
WritePDI
mov WORD [Freq],1000 ; Hz
CALL Sound
mov CX,500 ; ms wachten
CALL Delay
CALL NoSound
NextNumb:
inc EDX
JNZ CheckNumb ; 0xFFFFFFFF + 1 = 0
Abort:
WriteCounter
Close:
CALL CloseFile
Einde:
mov AH,0x4C ; Terminate process DOS Service
INT 0x21 ; Roep DOS aan
[SEGMENT .data]
GLOBAL FileName
FileName DB 'findpdis.lst',0
CRLF DB 13,10
[SEGMENT .bss]
EXTERN FHandle,Freq
BufNumb RESB 10
[SEGMENT .stack stack]
RESB 1024
GROUP DGroup data bss stack
| 34.290909 | 81 | 0.559517 |
fa46f2bae5b6ca269e31ecc537257d73fa10b73a | 2,165 | asm | Assembly | Tests/MIPS/Registers/Registers.asm | Thar0/armips | 4616b009959a8675eb2c9af66470b30c4083dffb | [
"MIT"
] | 283 | 2015-01-02T01:02:28.000Z | 2022-03-28T11:16:10.000Z | Tests/MIPS/Registers/Registers.asm | Thar0/armips | 4616b009959a8675eb2c9af66470b30c4083dffb | [
"MIT"
] | 117 | 2015-01-04T10:24:50.000Z | 2022-03-12T19:51:13.000Z | Tests/MIPS/Registers/Registers.asm | Thar0/armips | 4616b009959a8675eb2c9af66470b30c4083dffb | [
"MIT"
] | 82 | 2015-02-07T15:03:47.000Z | 2022-01-09T12:18:38.000Z | .ps2
.create "output.bin",0
move r0,r0
move r0,zero
move r0,$0
move r0,$zero
move r0,at
move r0,r1
move r0,$1
move r0,$at
move r0,v0
move r0,r2
move r0,$v0
move r0,v1
move r0,r3
move r0,$v1
move r0,a0
move r0,r4
move r0,$a0
move r0,a1
move r0,r5
move r0,$a1
move r0,a2
move r0,r6
move r0,$a2
move r0,a3
move r0,r7
move r0,$a3
move r0,t0
move r0,r8
move r0,$t0
move r0,t1
move r0,r9
move r0,$t1
move r0,t2
move r0,r10
move r0,$t2
move r0,t3
move r0,r11
move r0,$t3
move r0,t4
move r0,r12
move r0,$t4
move r0,t5
move r0,r13
move r0,$t5
move r0,t6
move r0,r14
move r0,$t6
move r0,t7
move r0,r15
move r0,$t7
move r0,s0
move r0,r16
move r0,$s0
move r0,s1
move r0,r17
move r0,$s1
move r0,s2
move r0,r18
move r0,$s2
move r0,s3
move r0,r19
move r0,$s3
move r0,s4
move r0,r20
move r0,$s4
move r0,s5
move r0,r21
move r0,$s5
move r0,s6
move r0,r22
move r0,$s6
move r0,s7
move r0,r23
move r0,$s7
move r0,t8
move r0,r24
move r0,$t8
move r0,t9
move r0,r25
move r0,$t9
move r0,k0
move r0,r26
move r0,$k0
move r0,k1
move r0,r27
move r0,$k1
move r0,gp
move r0,r28
move r0,$gp
move r0,sp
move r0,r29
move r0,$sp
move r0,fp
move r0,r30
move r0,$fp
move r0,ra
move r0,r31
move r0,$ra
mfc1 r0,f0
mfc1 r0,$f0
mfc1 r0,f1
mfc1 r0,$f1
mfc1 r0,f2
mfc1 r0,$f2
mfc1 r0,f3
mfc1 r0,$f3
mfc1 r0,f4
mfc1 r0,$f4
mfc1 r0,f5
mfc1 r0,$f5
mfc1 r0,f6
mfc1 r0,$f6
mfc1 r0,f7
mfc1 r0,$f7
mfc1 r0,f8
mfc1 r0,$f8
mfc1 r0,f9
mfc1 r0,$f9
mfc1 r0,f10
mfc1 r0,$f10
mfc1 r0,f11
mfc1 r0,$f11
mfc1 r0,f12
mfc1 r0,$f12
mfc1 r0,f13
mfc1 r0,$f13
mfc1 r0,f14
mfc1 r0,$f14
mfc1 r0,f15
mfc1 r0,$f15
mfc1 r0,f16
mfc1 r0,$f16
mfc1 r0,f17
mfc1 r0,$f17
mfc1 r0,f18
mfc1 r0,$f18
mfc1 r0,f19
mfc1 r0,$f19
mfc1 r0,f20
mfc1 r0,$f20
mfc1 r0,f21
mfc1 r0,$f21
mfc1 r0,f22
mfc1 r0,$f22
mfc1 r0,f23
mfc1 r0,$f23
mfc1 r0,f24
mfc1 r0,$f24
mfc1 r0,f25
mfc1 r0,$f25
mfc1 r0,f26
mfc1 r0,$f26
mfc1 r0,f27
mfc1 r0,$f27
mfc1 r0,f28
mfc1 r0,$f28
mfc1 r0,f29
mfc1 r0,$f29
mfc1 r0,f30
mfc1 r0,$f30
mfc1 r0,f31
mfc1 r0,$f31
addu r31,r2,r2
addu r2,r31,r2
addu r2,r2,r31
.close
| 12.514451 | 22 | 0.656351 |
acabfe6769aa32dccb330821583384aa00b102f6 | 7,322 | asm | Assembly | 30_2.asm | elder-george/black_book_vga | 3c5bc027ef34ae9e89c288d8e6c249d9bd27a42d | [
"BSD-3-Clause"
] | 2 | 2018-09-24T17:37:14.000Z | 2019-01-20T21:55:17.000Z | 30_2.asm | elder-george/black_book_vga | 3c5bc027ef34ae9e89c288d8e6c249d9bd27a42d | [
"BSD-3-Clause"
] | null | null | null | 30_2.asm | elder-george/black_book_vga | 3c5bc027ef34ae9e89c288d8e6c249d9bd27a42d | [
"BSD-3-Clause"
] | null | null | null | ; Demonstrates the interaction of the split screen and
; horizontal pel panning. On a VGA, first pans right in the top
; half while the split screen jerks around, because split screen
; pel panning suppression is disabled, then enables split screen
; pel panning suppression and pans right in the top half while the
; split screen remains stable. On an EGA, the split screen jerks
; around in both cases, because the EGA doesn't support split
; screen pel panning suppression.
;
; The jerking in the split screen occurs because the split screen
; is being pel panned (panned by single pixels--intrabyte panning),
; but is not and cannot be byte panned (panned by single bytes--
; "extrabyte" panning) because the start address of the split screen
; is forever fixed at 0.
;*********************************************************************
global start
%include 'common.inc'
IS_VGA equ 1 ;set to 0 to assemble for EGA
LOGICAL_SCREEN_WIDTH equ 1024 ;# of pixels across virtual
; screen that we'll pan across
SCREEN_HEIGHT equ 350
SPLIT_SCREEN_START equ 200 ;start scan line for split screen
SPLIT_SCREEN_HEIGHT equ SCREEN_HEIGHT-SPLIT_SCREEN_START-1
section code
start:
mov ax, data
mov ds, ax
SET_VIDEO_MODE MODE_V640x350x16
; Set the Offset register to make the offset from the start of one
; scan line to the start of the next the desired number of pixels.
; This gives us a virtual screen wider than the actual screen to
; pan across.
; Note that the Offset register is programmed with the logical
; screen width in words, not bytes, hence the final division by 2.
SET_PORT CRTC, CRTC_HOFFSET, (LOGICAL_SCREEN_WIDTH/8/2)
; Set the start address to display the memory just past the split
; screen memory.
mov word [StartAddress],SPLIT_SCREEN_HEIGHT*(LOGICAL_SCREEN_WIDTH/8)
call SetStartAddress
; Set the split screen start scan line.
mov word [SplitScreenLine],SPLIT_SCREEN_START
call SetSplitScreenScanLine
; Fill the split screen portion of display memory (starting at
; offset 0) with a choppy diagonal pattern sloping left.
mov ax, VGA_VIDEO_SEGMENT
mov es, ax
xor di, di
mov dx, SPLIT_SCREEN_HEIGHT ; fill all lines in the split screen
mov ax, 0000111111110000b ; starting pattern
cld
.RowLoop:
mov cx, LOGICAL_SCREEN_WIDTH/8/4;fill 1 scan line
.ColumnLoop:
stosw ; draw part of a diagonal line
mov word[es:di], 0 ; make vertical blank spaces so panning effects can be seen easily
times 2 inc di
loop .ColumnLoop
rol ax, 1
dec dx
jnz .RowLoop
; Fill the portion of display memory that will be displayed in the
; normal screen (the non-split screen part of the display) with a
; choppy diagonal pattern sloping right.
mov di,SPLIT_SCREEN_HEIGHT*(LOGICAL_SCREEN_WIDTH/8)
mov dx, SCREEN_HEIGHT
mov ax, 1010010100010000b ; starting pattern
cld
.RowLoop2:
mov cx, LOGICAL_SCREEN_WIDTH/8/4;fill 1 scan line
.ColumnLoop2:
stosw
mov word[es:di], 0
times 2 inc di
loop .ColumnLoop2
ror ax, 1
dec dx
jnz .RowLoop2
; Pel pan the non-split screen portion of the display; because
; split screen pel panning suppression is not turned on, the split
; screen jerks back and forth as the pel panning setting cycles.
mov cx, 200
call PanRight
WAIT_FOR_KEYPRESS
; Return to the original screen location, with pel panning turned off.
mov word [StartAddress],SPLIT_SCREEN_HEIGHT*(LOGICAL_SCREEN_WIDTH/8)
call SetStartAddress
mov byte[PelPan],0
call SetPelPan
; Turn on split screen pel panning suppression, so the split screen
; won't be affected by pel panning. Not done on EGA because both
; readable registers and the split screen pel panning suppression bit
; aren't supported by EGAs.
%if IS_VGA
mov dx, INPUT_STATUS_0
in al, dx ;reset the AC Index/Data toggle to Index state
GET_PORT AC, 20h|AC_MODE_CONTROL ; bit 5 set to 1 to keep video on
or al, 20h ; enable split screen pel panning suppression
dec dx
out dx, al ;write the new AC Mode Control setting with
; split screen pel panning suppression turned on
%else
; not done for EGA
%endif
; Pel pan the non-split screen portion of the display; because
; split screen pel panning suppression is turned on, the split
; screen will not move as the pel panning setting cycles.
mov cx, 200
call PanRight
.exit:
WAIT_FOR_KEYPRESS
SET_VIDEO_MODE MODE_T80x50
EXIT 0
; Sets the start address to the value specifed by StartAddress.
SetStartAddress:
call WaitForVerticalSyncEnd
cli
WITH_PORT CRTC, CRTC_START_ADDRESS_HIGH
mov al, byte [StartAddress+1]
out dx, al
WITH_PORT CRTC, CRTC_START_ADDRESS_LOW
mov al, byte[StartAddress]
out dx, al
sti
ret
; Sets the horizontal pel panning setting to the value specified
; by PelPan. Waits until the start of vertical sync to do so, so
; the new pel pan setting can be loaded during non-display time
; and can be ready by the start of the next frame.
SetPelPan:
call WaitForVerticalSyncStart ; also resets the AC Index/Data toggle to Index state
SET_PORT AC, (AC_PEL_PANNING|20h), byte [PelPan]
ret
SetSplitScreenScanLine:
multipush ax, cx, dx
; Wait for the trailing edge of vertical sync before setting so that
; one half of the address isn't loaded before the start of the frame
; and the other half after, resulting in flicker as one frame is
; displayed with mismatched halves. The new start address won't be
; loaded until the start of the next frame; that is, one full frame
; will be displayed before the new start address takes effect.
call WaitForVerticalSyncEnd
cli
WITH_PORT CRTC, CRTC_LINE_COMPARE
mov al, byte[SplitScreenLine]
out dx, al
mov ah, byte[SplitScreenLine+1]
and ah, 1
mov cl, 4
shl ah, cl
%if IS_VGA
WITH_PORT CRTC, CRTC_OVERFLOW
in al, dx ;get the current Overflow reg setting
and al, ~10h ;turn off split screen bit 8
or al, ah ; new split screen bit 8
out dx, al
dec dx
mov ah, byte[SplitScreenLine+1]
and ah, 2
mov cl, 3
ror ah, cl ; move bit 9 of the split split screen scan line
; into position for the Maximum Scan Line register
WITH_PORT CRTC, CRTC_MAX_SCAN_LINE
in al, dx
and al, ~40h
or al, ah
out dx, al
%else
WITH_PORT CRTC, CRTC_OVERFLOW
or ah, 0fh
out dx, ah
%endif
sti
multipop ax, cx, dx
ret
; Pan horizontally to the right the number of pixels specified by CX.
; Input: CX = # of pixels by which to pan horizontally
PanRight:
.Loop:
inc byte[PelPan]
and byte[PelPan], 07h
jnz .SetStartAddress
inc word[StartAddress]
.SetStartAddress:
call SetStartAddress
call SetPelPan
loop .Loop
ret
section data
SplitScreenLine resw 1 ; line the split screen currently starts after
StartAddress resw 1 ; display memory offset at which scanning for video data starts
PelPan resb 1 ; current intrabyte horizontal pel panning setting
section stack stack
resb 512 | 34.537736 | 102 | 0.699126 |
03c25b57aeb6901ce79bea71b8103ae65c503972 | 438 | asm | Assembly | programs/oeis/282/A282166.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/282/A282166.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/282/A282166.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A282166: a(n) is the minimal sum of a positive integer sequence of length n with no duplicate substrings of length greater than 1, and every number different from its neighbors.
; 1,3,4,7,8,12,13,17,18,22,24,28,30,35,37,42,44,49,51,56,59
add $0,2
lpb $0
mov $2,$0
trn $0,2
seq $2,193832 ; Irregular triangle read by rows in which row n lists 2n-1 copies of 2n-1 and n copies of 2n, for n >= 1.
add $1,$2
lpe
sub $1,2
mov $0,$1
| 33.692308 | 179 | 0.691781 |
f3f00c6daa2446e528e605d324b91d02f3928c49 | 344 | asm | Assembly | programs/oeis/113/A113704.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/113/A113704.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/113/A113704.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A113704: Triangular indicator function for divisibility, read by rows.
; 1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,0,0,1,0,1,1,1,0,0,1,0,1,0,0,0,0,0,1,0,1,1,0,1,0,0,0,1,0,1,0,1,0,0,0,0,0,1,0,1,1,0,0,1,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,1,0,1,1,1,1,0,1,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0
lpb $0
add $1,1
mov $2,$0
sub $0,$1
gcd $2,$0
lpe
cmp $0,$2
| 31.272727 | 201 | 0.555233 |
bc50a2979b98aa01091712e9e4611ee8378d7adb | 679,709 | asm | Assembly | kernel.asm | chrisyees/cs153_lab2 | af62bd9886e08bdf25debf4c32b1ff28e4c9e92d | [
"MIT-0"
] | null | null | null | kernel.asm | chrisyees/cs153_lab2 | af62bd9886e08bdf25debf4c32b1ff28e4c9e92d | [
"MIT-0"
] | null | null | null | kernel.asm | chrisyees/cs153_lab2 | af62bd9886e08bdf25debf4c32b1ff28e4c9e92d | [
"MIT-0"
] | null | null | null |
kernel: file format elf32-i386
Disassembly of section .text:
80100000 <multiboot_header>:
80100000: 02 b0 ad 1b 00 00 add 0x1bad(%eax),%dh
80100006: 00 00 add %al,(%eax)
80100008: fe 4f 52 decb 0x52(%edi)
8010000b: e4 0f in $0xf,%al
8010000c <entry>:
# Entering xv6 on boot processor, with paging off.
.globl entry
entry:
# Turn on page size extension for 4Mbyte pages
movl %cr4, %eax
8010000c: 0f 20 e0 mov %cr4,%eax
orl $(CR4_PSE), %eax
8010000f: 83 c8 10 or $0x10,%eax
movl %eax, %cr4
80100012: 0f 22 e0 mov %eax,%cr4
# Set page directory
movl $(V2P_WO(entrypgdir)), %eax
80100015: b8 00 90 10 00 mov $0x109000,%eax
movl %eax, %cr3
8010001a: 0f 22 d8 mov %eax,%cr3
# Turn on paging.
movl %cr0, %eax
8010001d: 0f 20 c0 mov %cr0,%eax
orl $(CR0_PG|CR0_WP), %eax
80100020: 0d 00 00 01 80 or $0x80010000,%eax
movl %eax, %cr0
80100025: 0f 22 c0 mov %eax,%cr0
# Set up the stack pointer.
movl $(stack + KSTACKSIZE), %esp
80100028: bc c0 b5 10 80 mov $0x8010b5c0,%esp
# Jump to main(), and switch to executing at
# high addresses. The indirect call is needed because
# the assembler produces a PC-relative instruction
# for a direct jump.
mov $main, %eax
8010002d: b8 e0 2d 10 80 mov $0x80102de0,%eax
jmp *%eax
80100032: ff e0 jmp *%eax
80100034: 66 90 xchg %ax,%ax
80100036: 66 90 xchg %ax,%ax
80100038: 66 90 xchg %ax,%ax
8010003a: 66 90 xchg %ax,%ax
8010003c: 66 90 xchg %ax,%ax
8010003e: 66 90 xchg %ax,%ax
80100040 <binit>:
struct buf head;
} bcache;
void
binit(void)
{
80100040: 55 push %ebp
80100041: 89 e5 mov %esp,%ebp
80100043: 53 push %ebx
//PAGEBREAK!
// Create linked list of buffers
bcache.head.prev = &bcache.head;
bcache.head.next = &bcache.head;
for(b = bcache.buf; b < bcache.buf+NBUF; b++){
80100044: bb f4 b5 10 80 mov $0x8010b5f4,%ebx
struct buf head;
} bcache;
void
binit(void)
{
80100049: 83 ec 14 sub $0x14,%esp
struct buf *b;
initlock(&bcache.lock, "bcache");
8010004c: c7 44 24 04 a0 6d 10 movl $0x80106da0,0x4(%esp)
80100053: 80
80100054: c7 04 24 c0 b5 10 80 movl $0x8010b5c0,(%esp)
8010005b: e8 e0 3f 00 00 call 80104040 <initlock>
//PAGEBREAK!
// Create linked list of buffers
bcache.head.prev = &bcache.head;
bcache.head.next = &bcache.head;
80100060: ba bc fc 10 80 mov $0x8010fcbc,%edx
initlock(&bcache.lock, "bcache");
//PAGEBREAK!
// Create linked list of buffers
bcache.head.prev = &bcache.head;
80100065: c7 05 0c fd 10 80 bc movl $0x8010fcbc,0x8010fd0c
8010006c: fc 10 80
bcache.head.next = &bcache.head;
8010006f: c7 05 10 fd 10 80 bc movl $0x8010fcbc,0x8010fd10
80100076: fc 10 80
80100079: eb 09 jmp 80100084 <binit+0x44>
8010007b: 90 nop
8010007c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80100080: 89 da mov %ebx,%edx
for(b = bcache.buf; b < bcache.buf+NBUF; b++){
80100082: 89 c3 mov %eax,%ebx
80100084: 8d 43 0c lea 0xc(%ebx),%eax
b->next = bcache.head.next;
80100087: 89 53 54 mov %edx,0x54(%ebx)
b->prev = &bcache.head;
8010008a: c7 43 50 bc fc 10 80 movl $0x8010fcbc,0x50(%ebx)
initsleeplock(&b->lock, "buffer");
80100091: 89 04 24 mov %eax,(%esp)
80100094: c7 44 24 04 a7 6d 10 movl $0x80106da7,0x4(%esp)
8010009b: 80
8010009c: e8 8f 3e 00 00 call 80103f30 <initsleeplock>
bcache.head.next->prev = b;
801000a1: a1 10 fd 10 80 mov 0x8010fd10,%eax
801000a6: 89 58 50 mov %ebx,0x50(%eax)
//PAGEBREAK!
// Create linked list of buffers
bcache.head.prev = &bcache.head;
bcache.head.next = &bcache.head;
for(b = bcache.buf; b < bcache.buf+NBUF; b++){
801000a9: 8d 83 5c 02 00 00 lea 0x25c(%ebx),%eax
801000af: 3d bc fc 10 80 cmp $0x8010fcbc,%eax
b->next = bcache.head.next;
b->prev = &bcache.head;
initsleeplock(&b->lock, "buffer");
bcache.head.next->prev = b;
bcache.head.next = b;
801000b4: 89 1d 10 fd 10 80 mov %ebx,0x8010fd10
//PAGEBREAK!
// Create linked list of buffers
bcache.head.prev = &bcache.head;
bcache.head.next = &bcache.head;
for(b = bcache.buf; b < bcache.buf+NBUF; b++){
801000ba: 75 c4 jne 80100080 <binit+0x40>
b->prev = &bcache.head;
initsleeplock(&b->lock, "buffer");
bcache.head.next->prev = b;
bcache.head.next = b;
}
}
801000bc: 83 c4 14 add $0x14,%esp
801000bf: 5b pop %ebx
801000c0: 5d pop %ebp
801000c1: c3 ret
801000c2: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
801000c9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801000d0 <bread>:
}
// Return a locked buf with the contents of the indicated block.
struct buf*
bread(uint dev, uint blockno)
{
801000d0: 55 push %ebp
801000d1: 89 e5 mov %esp,%ebp
801000d3: 57 push %edi
801000d4: 56 push %esi
801000d5: 53 push %ebx
801000d6: 83 ec 1c sub $0x1c,%esp
801000d9: 8b 75 08 mov 0x8(%ebp),%esi
static struct buf*
bget(uint dev, uint blockno)
{
struct buf *b;
acquire(&bcache.lock);
801000dc: c7 04 24 c0 b5 10 80 movl $0x8010b5c0,(%esp)
}
// Return a locked buf with the contents of the indicated block.
struct buf*
bread(uint dev, uint blockno)
{
801000e3: 8b 7d 0c mov 0xc(%ebp),%edi
static struct buf*
bget(uint dev, uint blockno)
{
struct buf *b;
acquire(&bcache.lock);
801000e6: e8 45 40 00 00 call 80104130 <acquire>
// Is the block already cached?
for(b = bcache.head.next; b != &bcache.head; b = b->next){
801000eb: 8b 1d 10 fd 10 80 mov 0x8010fd10,%ebx
801000f1: 81 fb bc fc 10 80 cmp $0x8010fcbc,%ebx
801000f7: 75 12 jne 8010010b <bread+0x3b>
801000f9: eb 25 jmp 80100120 <bread+0x50>
801000fb: 90 nop
801000fc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80100100: 8b 5b 54 mov 0x54(%ebx),%ebx
80100103: 81 fb bc fc 10 80 cmp $0x8010fcbc,%ebx
80100109: 74 15 je 80100120 <bread+0x50>
if(b->dev == dev && b->blockno == blockno){
8010010b: 3b 73 04 cmp 0x4(%ebx),%esi
8010010e: 75 f0 jne 80100100 <bread+0x30>
80100110: 3b 7b 08 cmp 0x8(%ebx),%edi
80100113: 75 eb jne 80100100 <bread+0x30>
b->refcnt++;
80100115: 83 43 4c 01 addl $0x1,0x4c(%ebx)
80100119: eb 3f jmp 8010015a <bread+0x8a>
8010011b: 90 nop
8010011c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
}
// Not cached; recycle an unused buffer.
// Even if refcnt==0, B_DIRTY indicates a buffer is in use
// because log.c has modified it but not yet committed it.
for(b = bcache.head.prev; b != &bcache.head; b = b->prev){
80100120: 8b 1d 0c fd 10 80 mov 0x8010fd0c,%ebx
80100126: 81 fb bc fc 10 80 cmp $0x8010fcbc,%ebx
8010012c: 75 0d jne 8010013b <bread+0x6b>
8010012e: eb 58 jmp 80100188 <bread+0xb8>
80100130: 8b 5b 50 mov 0x50(%ebx),%ebx
80100133: 81 fb bc fc 10 80 cmp $0x8010fcbc,%ebx
80100139: 74 4d je 80100188 <bread+0xb8>
if(b->refcnt == 0 && (b->flags & B_DIRTY) == 0) {
8010013b: 8b 43 4c mov 0x4c(%ebx),%eax
8010013e: 85 c0 test %eax,%eax
80100140: 75 ee jne 80100130 <bread+0x60>
80100142: f6 03 04 testb $0x4,(%ebx)
80100145: 75 e9 jne 80100130 <bread+0x60>
b->dev = dev;
80100147: 89 73 04 mov %esi,0x4(%ebx)
b->blockno = blockno;
8010014a: 89 7b 08 mov %edi,0x8(%ebx)
b->flags = 0;
8010014d: c7 03 00 00 00 00 movl $0x0,(%ebx)
b->refcnt = 1;
80100153: c7 43 4c 01 00 00 00 movl $0x1,0x4c(%ebx)
release(&bcache.lock);
8010015a: c7 04 24 c0 b5 10 80 movl $0x8010b5c0,(%esp)
80100161: e8 ba 40 00 00 call 80104220 <release>
acquiresleep(&b->lock);
80100166: 8d 43 0c lea 0xc(%ebx),%eax
80100169: 89 04 24 mov %eax,(%esp)
8010016c: e8 ff 3d 00 00 call 80103f70 <acquiresleep>
bread(uint dev, uint blockno)
{
struct buf *b;
b = bget(dev, blockno);
if((b->flags & B_VALID) == 0) {
80100171: f6 03 02 testb $0x2,(%ebx)
80100174: 75 08 jne 8010017e <bread+0xae>
iderw(b);
80100176: 89 1c 24 mov %ebx,(%esp)
80100179: e8 92 1f 00 00 call 80102110 <iderw>
}
return b;
}
8010017e: 83 c4 1c add $0x1c,%esp
80100181: 89 d8 mov %ebx,%eax
80100183: 5b pop %ebx
80100184: 5e pop %esi
80100185: 5f pop %edi
80100186: 5d pop %ebp
80100187: c3 ret
release(&bcache.lock);
acquiresleep(&b->lock);
return b;
}
}
panic("bget: no buffers");
80100188: c7 04 24 ae 6d 10 80 movl $0x80106dae,(%esp)
8010018f: e8 cc 01 00 00 call 80100360 <panic>
80100194: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
8010019a: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
801001a0 <bwrite>:
}
// Write b's contents to disk. Must be locked.
void
bwrite(struct buf *b)
{
801001a0: 55 push %ebp
801001a1: 89 e5 mov %esp,%ebp
801001a3: 53 push %ebx
801001a4: 83 ec 14 sub $0x14,%esp
801001a7: 8b 5d 08 mov 0x8(%ebp),%ebx
if(!holdingsleep(&b->lock))
801001aa: 8d 43 0c lea 0xc(%ebx),%eax
801001ad: 89 04 24 mov %eax,(%esp)
801001b0: e8 5b 3e 00 00 call 80104010 <holdingsleep>
801001b5: 85 c0 test %eax,%eax
801001b7: 74 10 je 801001c9 <bwrite+0x29>
panic("bwrite");
b->flags |= B_DIRTY;
801001b9: 83 0b 04 orl $0x4,(%ebx)
iderw(b);
801001bc: 89 5d 08 mov %ebx,0x8(%ebp)
}
801001bf: 83 c4 14 add $0x14,%esp
801001c2: 5b pop %ebx
801001c3: 5d pop %ebp
bwrite(struct buf *b)
{
if(!holdingsleep(&b->lock))
panic("bwrite");
b->flags |= B_DIRTY;
iderw(b);
801001c4: e9 47 1f 00 00 jmp 80102110 <iderw>
// Write b's contents to disk. Must be locked.
void
bwrite(struct buf *b)
{
if(!holdingsleep(&b->lock))
panic("bwrite");
801001c9: c7 04 24 bf 6d 10 80 movl $0x80106dbf,(%esp)
801001d0: e8 8b 01 00 00 call 80100360 <panic>
801001d5: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
801001d9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801001e0 <brelse>:
// Release a locked buffer.
// Move to the head of the MRU list.
void
brelse(struct buf *b)
{
801001e0: 55 push %ebp
801001e1: 89 e5 mov %esp,%ebp
801001e3: 56 push %esi
801001e4: 53 push %ebx
801001e5: 83 ec 10 sub $0x10,%esp
801001e8: 8b 5d 08 mov 0x8(%ebp),%ebx
if(!holdingsleep(&b->lock))
801001eb: 8d 73 0c lea 0xc(%ebx),%esi
801001ee: 89 34 24 mov %esi,(%esp)
801001f1: e8 1a 3e 00 00 call 80104010 <holdingsleep>
801001f6: 85 c0 test %eax,%eax
801001f8: 74 5b je 80100255 <brelse+0x75>
panic("brelse");
releasesleep(&b->lock);
801001fa: 89 34 24 mov %esi,(%esp)
801001fd: e8 ce 3d 00 00 call 80103fd0 <releasesleep>
acquire(&bcache.lock);
80100202: c7 04 24 c0 b5 10 80 movl $0x8010b5c0,(%esp)
80100209: e8 22 3f 00 00 call 80104130 <acquire>
b->refcnt--;
if (b->refcnt == 0) {
8010020e: 83 6b 4c 01 subl $0x1,0x4c(%ebx)
80100212: 75 2f jne 80100243 <brelse+0x63>
// no one is waiting for it.
b->next->prev = b->prev;
80100214: 8b 43 54 mov 0x54(%ebx),%eax
80100217: 8b 53 50 mov 0x50(%ebx),%edx
8010021a: 89 50 50 mov %edx,0x50(%eax)
b->prev->next = b->next;
8010021d: 8b 43 50 mov 0x50(%ebx),%eax
80100220: 8b 53 54 mov 0x54(%ebx),%edx
80100223: 89 50 54 mov %edx,0x54(%eax)
b->next = bcache.head.next;
80100226: a1 10 fd 10 80 mov 0x8010fd10,%eax
b->prev = &bcache.head;
8010022b: c7 43 50 bc fc 10 80 movl $0x8010fcbc,0x50(%ebx)
b->refcnt--;
if (b->refcnt == 0) {
// no one is waiting for it.
b->next->prev = b->prev;
b->prev->next = b->next;
b->next = bcache.head.next;
80100232: 89 43 54 mov %eax,0x54(%ebx)
b->prev = &bcache.head;
bcache.head.next->prev = b;
80100235: a1 10 fd 10 80 mov 0x8010fd10,%eax
8010023a: 89 58 50 mov %ebx,0x50(%eax)
bcache.head.next = b;
8010023d: 89 1d 10 fd 10 80 mov %ebx,0x8010fd10
}
release(&bcache.lock);
80100243: c7 45 08 c0 b5 10 80 movl $0x8010b5c0,0x8(%ebp)
}
8010024a: 83 c4 10 add $0x10,%esp
8010024d: 5b pop %ebx
8010024e: 5e pop %esi
8010024f: 5d pop %ebp
b->prev = &bcache.head;
bcache.head.next->prev = b;
bcache.head.next = b;
}
release(&bcache.lock);
80100250: e9 cb 3f 00 00 jmp 80104220 <release>
// Move to the head of the MRU list.
void
brelse(struct buf *b)
{
if(!holdingsleep(&b->lock))
panic("brelse");
80100255: c7 04 24 c6 6d 10 80 movl $0x80106dc6,(%esp)
8010025c: e8 ff 00 00 00 call 80100360 <panic>
80100261: 66 90 xchg %ax,%ax
80100263: 66 90 xchg %ax,%ax
80100265: 66 90 xchg %ax,%ax
80100267: 66 90 xchg %ax,%ax
80100269: 66 90 xchg %ax,%ax
8010026b: 66 90 xchg %ax,%ax
8010026d: 66 90 xchg %ax,%ax
8010026f: 90 nop
80100270 <consoleread>:
}
}
int
consoleread(struct inode *ip, char *dst, int n)
{
80100270: 55 push %ebp
80100271: 89 e5 mov %esp,%ebp
80100273: 57 push %edi
80100274: 56 push %esi
80100275: 53 push %ebx
80100276: 83 ec 1c sub $0x1c,%esp
80100279: 8b 7d 08 mov 0x8(%ebp),%edi
8010027c: 8b 75 0c mov 0xc(%ebp),%esi
uint target;
int c;
iunlock(ip);
8010027f: 89 3c 24 mov %edi,(%esp)
80100282: e8 f9 14 00 00 call 80101780 <iunlock>
target = n;
acquire(&cons.lock);
80100287: c7 04 24 20 a5 10 80 movl $0x8010a520,(%esp)
8010028e: e8 9d 3e 00 00 call 80104130 <acquire>
while(n > 0){
80100293: 8b 55 10 mov 0x10(%ebp),%edx
80100296: 85 d2 test %edx,%edx
80100298: 0f 8e bc 00 00 00 jle 8010035a <consoleread+0xea>
8010029e: 8b 5d 10 mov 0x10(%ebp),%ebx
801002a1: eb 25 jmp 801002c8 <consoleread+0x58>
801002a3: 90 nop
801002a4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
while(input.r == input.w){
if(myproc()->killed){
801002a8: e8 e3 33 00 00 call 80103690 <myproc>
801002ad: 8b 40 28 mov 0x28(%eax),%eax
801002b0: 85 c0 test %eax,%eax
801002b2: 75 74 jne 80100328 <consoleread+0xb8>
release(&cons.lock);
ilock(ip);
return -1;
}
sleep(&input.r, &cons.lock);
801002b4: c7 44 24 04 20 a5 10 movl $0x8010a520,0x4(%esp)
801002bb: 80
801002bc: c7 04 24 a0 ff 10 80 movl $0x8010ffa0,(%esp)
801002c3: e8 28 39 00 00 call 80103bf0 <sleep>
iunlock(ip);
target = n;
acquire(&cons.lock);
while(n > 0){
while(input.r == input.w){
801002c8: a1 a0 ff 10 80 mov 0x8010ffa0,%eax
801002cd: 3b 05 a4 ff 10 80 cmp 0x8010ffa4,%eax
801002d3: 74 d3 je 801002a8 <consoleread+0x38>
ilock(ip);
return -1;
}
sleep(&input.r, &cons.lock);
}
c = input.buf[input.r++ % INPUT_BUF];
801002d5: 8d 50 01 lea 0x1(%eax),%edx
801002d8: 89 15 a0 ff 10 80 mov %edx,0x8010ffa0
801002de: 89 c2 mov %eax,%edx
801002e0: 83 e2 7f and $0x7f,%edx
801002e3: 0f b6 8a 20 ff 10 80 movzbl -0x7fef00e0(%edx),%ecx
801002ea: 0f be d1 movsbl %cl,%edx
if(c == C('D')){ // EOF
801002ed: 83 fa 04 cmp $0x4,%edx
801002f0: 74 57 je 80100349 <consoleread+0xd9>
// caller gets a 0-byte result.
input.r--;
}
break;
}
*dst++ = c;
801002f2: 83 c6 01 add $0x1,%esi
--n;
801002f5: 83 eb 01 sub $0x1,%ebx
if(c == '\n')
801002f8: 83 fa 0a cmp $0xa,%edx
// caller gets a 0-byte result.
input.r--;
}
break;
}
*dst++ = c;
801002fb: 88 4e ff mov %cl,-0x1(%esi)
--n;
if(c == '\n')
801002fe: 74 53 je 80100353 <consoleread+0xe3>
int c;
iunlock(ip);
target = n;
acquire(&cons.lock);
while(n > 0){
80100300: 85 db test %ebx,%ebx
80100302: 75 c4 jne 801002c8 <consoleread+0x58>
80100304: 8b 45 10 mov 0x10(%ebp),%eax
*dst++ = c;
--n;
if(c == '\n')
break;
}
release(&cons.lock);
80100307: c7 04 24 20 a5 10 80 movl $0x8010a520,(%esp)
8010030e: 89 45 e4 mov %eax,-0x1c(%ebp)
80100311: e8 0a 3f 00 00 call 80104220 <release>
ilock(ip);
80100316: 89 3c 24 mov %edi,(%esp)
80100319: e8 82 13 00 00 call 801016a0 <ilock>
8010031e: 8b 45 e4 mov -0x1c(%ebp),%eax
return target - n;
80100321: eb 1e jmp 80100341 <consoleread+0xd1>
80100323: 90 nop
80100324: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
target = n;
acquire(&cons.lock);
while(n > 0){
while(input.r == input.w){
if(myproc()->killed){
release(&cons.lock);
80100328: c7 04 24 20 a5 10 80 movl $0x8010a520,(%esp)
8010032f: e8 ec 3e 00 00 call 80104220 <release>
ilock(ip);
80100334: 89 3c 24 mov %edi,(%esp)
80100337: e8 64 13 00 00 call 801016a0 <ilock>
return -1;
8010033c: b8 ff ff ff ff mov $0xffffffff,%eax
}
release(&cons.lock);
ilock(ip);
return target - n;
}
80100341: 83 c4 1c add $0x1c,%esp
80100344: 5b pop %ebx
80100345: 5e pop %esi
80100346: 5f pop %edi
80100347: 5d pop %ebp
80100348: c3 ret
}
sleep(&input.r, &cons.lock);
}
c = input.buf[input.r++ % INPUT_BUF];
if(c == C('D')){ // EOF
if(n < target){
80100349: 39 5d 10 cmp %ebx,0x10(%ebp)
8010034c: 76 05 jbe 80100353 <consoleread+0xe3>
// Save ^D for next time, to make sure
// caller gets a 0-byte result.
input.r--;
8010034e: a3 a0 ff 10 80 mov %eax,0x8010ffa0
80100353: 8b 45 10 mov 0x10(%ebp),%eax
80100356: 29 d8 sub %ebx,%eax
80100358: eb ad jmp 80100307 <consoleread+0x97>
int c;
iunlock(ip);
target = n;
acquire(&cons.lock);
while(n > 0){
8010035a: 31 c0 xor %eax,%eax
8010035c: eb a9 jmp 80100307 <consoleread+0x97>
8010035e: 66 90 xchg %ax,%ax
80100360 <panic>:
release(&cons.lock);
}
void
panic(char *s)
{
80100360: 55 push %ebp
80100361: 89 e5 mov %esp,%ebp
80100363: 56 push %esi
80100364: 53 push %ebx
80100365: 83 ec 40 sub $0x40,%esp
}
static inline void
cli(void)
{
asm volatile("cli");
80100368: fa cli
int i;
uint pcs[10];
cli();
cons.locking = 0;
80100369: c7 05 54 a5 10 80 00 movl $0x0,0x8010a554
80100370: 00 00 00
// use lapiccpunum so that we can call panic from mycpu()
cprintf("lapicid %d: panic: ", lapicid());
cprintf(s);
cprintf("\n");
getcallerpcs(&s, pcs);
80100373: 8d 5d d0 lea -0x30(%ebp),%ebx
uint pcs[10];
cli();
cons.locking = 0;
// use lapiccpunum so that we can call panic from mycpu()
cprintf("lapicid %d: panic: ", lapicid());
80100376: e8 d5 23 00 00 call 80102750 <lapicid>
8010037b: 8d 75 f8 lea -0x8(%ebp),%esi
8010037e: c7 04 24 cd 6d 10 80 movl $0x80106dcd,(%esp)
80100385: 89 44 24 04 mov %eax,0x4(%esp)
80100389: e8 c2 02 00 00 call 80100650 <cprintf>
cprintf(s);
8010038e: 8b 45 08 mov 0x8(%ebp),%eax
80100391: 89 04 24 mov %eax,(%esp)
80100394: e8 b7 02 00 00 call 80100650 <cprintf>
cprintf("\n");
80100399: c7 04 24 87 77 10 80 movl $0x80107787,(%esp)
801003a0: e8 ab 02 00 00 call 80100650 <cprintf>
getcallerpcs(&s, pcs);
801003a5: 8d 45 08 lea 0x8(%ebp),%eax
801003a8: 89 5c 24 04 mov %ebx,0x4(%esp)
801003ac: 89 04 24 mov %eax,(%esp)
801003af: e8 ac 3c 00 00 call 80104060 <getcallerpcs>
801003b4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
for(i=0; i<10; i++)
cprintf(" %p", pcs[i]);
801003b8: 8b 03 mov (%ebx),%eax
801003ba: 83 c3 04 add $0x4,%ebx
801003bd: c7 04 24 e1 6d 10 80 movl $0x80106de1,(%esp)
801003c4: 89 44 24 04 mov %eax,0x4(%esp)
801003c8: e8 83 02 00 00 call 80100650 <cprintf>
// use lapiccpunum so that we can call panic from mycpu()
cprintf("lapicid %d: panic: ", lapicid());
cprintf(s);
cprintf("\n");
getcallerpcs(&s, pcs);
for(i=0; i<10; i++)
801003cd: 39 f3 cmp %esi,%ebx
801003cf: 75 e7 jne 801003b8 <panic+0x58>
cprintf(" %p", pcs[i]);
panicked = 1; // freeze other CPU
801003d1: c7 05 58 a5 10 80 01 movl $0x1,0x8010a558
801003d8: 00 00 00
801003db: eb fe jmp 801003db <panic+0x7b>
801003dd: 8d 76 00 lea 0x0(%esi),%esi
801003e0 <consputc>:
}
void
consputc(int c)
{
if(panicked){
801003e0: 8b 15 58 a5 10 80 mov 0x8010a558,%edx
801003e6: 85 d2 test %edx,%edx
801003e8: 74 06 je 801003f0 <consputc+0x10>
801003ea: fa cli
801003eb: eb fe jmp 801003eb <consputc+0xb>
801003ed: 8d 76 00 lea 0x0(%esi),%esi
crt[pos] = ' ' | 0x0700;
}
void
consputc(int c)
{
801003f0: 55 push %ebp
801003f1: 89 e5 mov %esp,%ebp
801003f3: 57 push %edi
801003f4: 56 push %esi
801003f5: 53 push %ebx
801003f6: 89 c3 mov %eax,%ebx
801003f8: 83 ec 1c sub $0x1c,%esp
cli();
for(;;)
;
}
if(c == BACKSPACE){
801003fb: 3d 00 01 00 00 cmp $0x100,%eax
80100400: 0f 84 ac 00 00 00 je 801004b2 <consputc+0xd2>
uartputc('\b'); uartputc(' '); uartputc('\b');
} else
uartputc(c);
80100406: 89 04 24 mov %eax,(%esp)
80100409: e8 a2 53 00 00 call 801057b0 <uartputc>
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
8010040e: bf d4 03 00 00 mov $0x3d4,%edi
80100413: b8 0e 00 00 00 mov $0xe,%eax
80100418: 89 fa mov %edi,%edx
8010041a: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
8010041b: be d5 03 00 00 mov $0x3d5,%esi
80100420: 89 f2 mov %esi,%edx
80100422: ec in (%dx),%al
{
int pos;
// Cursor position: col + 80*row.
outb(CRTPORT, 14);
pos = inb(CRTPORT+1) << 8;
80100423: 0f b6 c8 movzbl %al,%ecx
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
80100426: 89 fa mov %edi,%edx
80100428: c1 e1 08 shl $0x8,%ecx
8010042b: b8 0f 00 00 00 mov $0xf,%eax
80100430: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
80100431: 89 f2 mov %esi,%edx
80100433: ec in (%dx),%al
outb(CRTPORT, 15);
pos |= inb(CRTPORT+1);
80100434: 0f b6 c0 movzbl %al,%eax
80100437: 09 c1 or %eax,%ecx
if(c == '\n')
80100439: 83 fb 0a cmp $0xa,%ebx
8010043c: 0f 84 0d 01 00 00 je 8010054f <consputc+0x16f>
pos += 80 - pos%80;
else if(c == BACKSPACE){
80100442: 81 fb 00 01 00 00 cmp $0x100,%ebx
80100448: 0f 84 e8 00 00 00 je 80100536 <consputc+0x156>
if(pos > 0) --pos;
} else
crt[pos++] = (c&0xff) | 0x0700; // black on white
8010044e: 0f b6 db movzbl %bl,%ebx
80100451: 80 cf 07 or $0x7,%bh
80100454: 8d 79 01 lea 0x1(%ecx),%edi
80100457: 66 89 9c 09 00 80 0b mov %bx,-0x7ff48000(%ecx,%ecx,1)
8010045e: 80
if(pos < 0 || pos > 25*80)
8010045f: 81 ff d0 07 00 00 cmp $0x7d0,%edi
80100465: 0f 87 bf 00 00 00 ja 8010052a <consputc+0x14a>
panic("pos under/overflow");
if((pos/80) >= 24){ // Scroll up.
8010046b: 81 ff 7f 07 00 00 cmp $0x77f,%edi
80100471: 7f 68 jg 801004db <consputc+0xfb>
80100473: 89 f8 mov %edi,%eax
80100475: 89 fb mov %edi,%ebx
80100477: c1 e8 08 shr $0x8,%eax
8010047a: 89 c6 mov %eax,%esi
8010047c: 8d 8c 3f 00 80 0b 80 lea -0x7ff48000(%edi,%edi,1),%ecx
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
80100483: bf d4 03 00 00 mov $0x3d4,%edi
80100488: b8 0e 00 00 00 mov $0xe,%eax
8010048d: 89 fa mov %edi,%edx
8010048f: ee out %al,(%dx)
80100490: 89 f0 mov %esi,%eax
80100492: b2 d5 mov $0xd5,%dl
80100494: ee out %al,(%dx)
80100495: b8 0f 00 00 00 mov $0xf,%eax
8010049a: 89 fa mov %edi,%edx
8010049c: ee out %al,(%dx)
8010049d: 89 d8 mov %ebx,%eax
8010049f: b2 d5 mov $0xd5,%dl
801004a1: ee out %al,(%dx)
outb(CRTPORT, 14);
outb(CRTPORT+1, pos>>8);
outb(CRTPORT, 15);
outb(CRTPORT+1, pos);
crt[pos] = ' ' | 0x0700;
801004a2: b8 20 07 00 00 mov $0x720,%eax
801004a7: 66 89 01 mov %ax,(%ecx)
if(c == BACKSPACE){
uartputc('\b'); uartputc(' '); uartputc('\b');
} else
uartputc(c);
cgaputc(c);
}
801004aa: 83 c4 1c add $0x1c,%esp
801004ad: 5b pop %ebx
801004ae: 5e pop %esi
801004af: 5f pop %edi
801004b0: 5d pop %ebp
801004b1: c3 ret
for(;;)
;
}
if(c == BACKSPACE){
uartputc('\b'); uartputc(' '); uartputc('\b');
801004b2: c7 04 24 08 00 00 00 movl $0x8,(%esp)
801004b9: e8 f2 52 00 00 call 801057b0 <uartputc>
801004be: c7 04 24 20 00 00 00 movl $0x20,(%esp)
801004c5: e8 e6 52 00 00 call 801057b0 <uartputc>
801004ca: c7 04 24 08 00 00 00 movl $0x8,(%esp)
801004d1: e8 da 52 00 00 call 801057b0 <uartputc>
801004d6: e9 33 ff ff ff jmp 8010040e <consputc+0x2e>
if(pos < 0 || pos > 25*80)
panic("pos under/overflow");
if((pos/80) >= 24){ // Scroll up.
memmove(crt, crt+80, sizeof(crt[0])*23*80);
801004db: c7 44 24 08 60 0e 00 movl $0xe60,0x8(%esp)
801004e2: 00
pos -= 80;
801004e3: 8d 5f b0 lea -0x50(%edi),%ebx
if(pos < 0 || pos > 25*80)
panic("pos under/overflow");
if((pos/80) >= 24){ // Scroll up.
memmove(crt, crt+80, sizeof(crt[0])*23*80);
801004e6: c7 44 24 04 a0 80 0b movl $0x800b80a0,0x4(%esp)
801004ed: 80
pos -= 80;
memset(crt+pos, 0, sizeof(crt[0])*(24*80 - pos));
801004ee: 8d b4 1b 00 80 0b 80 lea -0x7ff48000(%ebx,%ebx,1),%esi
if(pos < 0 || pos > 25*80)
panic("pos under/overflow");
if((pos/80) >= 24){ // Scroll up.
memmove(crt, crt+80, sizeof(crt[0])*23*80);
801004f5: c7 04 24 00 80 0b 80 movl $0x800b8000,(%esp)
801004fc: e8 0f 3e 00 00 call 80104310 <memmove>
pos -= 80;
memset(crt+pos, 0, sizeof(crt[0])*(24*80 - pos));
80100501: b8 d0 07 00 00 mov $0x7d0,%eax
80100506: 29 f8 sub %edi,%eax
80100508: 01 c0 add %eax,%eax
8010050a: 89 34 24 mov %esi,(%esp)
8010050d: 89 44 24 08 mov %eax,0x8(%esp)
80100511: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
80100518: 00
80100519: e8 52 3d 00 00 call 80104270 <memset>
8010051e: 89 f1 mov %esi,%ecx
80100520: be 07 00 00 00 mov $0x7,%esi
80100525: e9 59 ff ff ff jmp 80100483 <consputc+0xa3>
if(pos > 0) --pos;
} else
crt[pos++] = (c&0xff) | 0x0700; // black on white
if(pos < 0 || pos > 25*80)
panic("pos under/overflow");
8010052a: c7 04 24 e5 6d 10 80 movl $0x80106de5,(%esp)
80100531: e8 2a fe ff ff call 80100360 <panic>
pos |= inb(CRTPORT+1);
if(c == '\n')
pos += 80 - pos%80;
else if(c == BACKSPACE){
if(pos > 0) --pos;
80100536: 85 c9 test %ecx,%ecx
80100538: 8d 79 ff lea -0x1(%ecx),%edi
8010053b: 0f 85 1e ff ff ff jne 8010045f <consputc+0x7f>
80100541: b9 00 80 0b 80 mov $0x800b8000,%ecx
80100546: 31 db xor %ebx,%ebx
80100548: 31 f6 xor %esi,%esi
8010054a: e9 34 ff ff ff jmp 80100483 <consputc+0xa3>
pos = inb(CRTPORT+1) << 8;
outb(CRTPORT, 15);
pos |= inb(CRTPORT+1);
if(c == '\n')
pos += 80 - pos%80;
8010054f: 89 c8 mov %ecx,%eax
80100551: ba 67 66 66 66 mov $0x66666667,%edx
80100556: f7 ea imul %edx
80100558: c1 ea 05 shr $0x5,%edx
8010055b: 8d 04 92 lea (%edx,%edx,4),%eax
8010055e: c1 e0 04 shl $0x4,%eax
80100561: 8d 78 50 lea 0x50(%eax),%edi
80100564: e9 f6 fe ff ff jmp 8010045f <consputc+0x7f>
80100569: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80100570 <printint>:
int locking;
} cons;
static void
printint(int xx, int base, int sign)
{
80100570: 55 push %ebp
80100571: 89 e5 mov %esp,%ebp
80100573: 57 push %edi
80100574: 56 push %esi
80100575: 89 d6 mov %edx,%esi
80100577: 53 push %ebx
80100578: 83 ec 1c sub $0x1c,%esp
static char digits[] = "0123456789abcdef";
char buf[16];
int i;
uint x;
if(sign && (sign = xx < 0))
8010057b: 85 c9 test %ecx,%ecx
8010057d: 74 61 je 801005e0 <printint+0x70>
8010057f: 85 c0 test %eax,%eax
80100581: 79 5d jns 801005e0 <printint+0x70>
x = -xx;
80100583: f7 d8 neg %eax
80100585: bf 01 00 00 00 mov $0x1,%edi
else
x = xx;
i = 0;
8010058a: 31 c9 xor %ecx,%ecx
8010058c: eb 04 jmp 80100592 <printint+0x22>
8010058e: 66 90 xchg %ax,%ax
do{
buf[i++] = digits[x % base];
80100590: 89 d9 mov %ebx,%ecx
80100592: 31 d2 xor %edx,%edx
80100594: f7 f6 div %esi
80100596: 8d 59 01 lea 0x1(%ecx),%ebx
80100599: 0f b6 92 10 6e 10 80 movzbl -0x7fef91f0(%edx),%edx
}while((x /= base) != 0);
801005a0: 85 c0 test %eax,%eax
else
x = xx;
i = 0;
do{
buf[i++] = digits[x % base];
801005a2: 88 54 1d d7 mov %dl,-0x29(%ebp,%ebx,1)
}while((x /= base) != 0);
801005a6: 75 e8 jne 80100590 <printint+0x20>
if(sign)
801005a8: 85 ff test %edi,%edi
else
x = xx;
i = 0;
do{
buf[i++] = digits[x % base];
801005aa: 89 d8 mov %ebx,%eax
}while((x /= base) != 0);
if(sign)
801005ac: 74 08 je 801005b6 <printint+0x46>
buf[i++] = '-';
801005ae: 8d 59 02 lea 0x2(%ecx),%ebx
801005b1: c6 44 05 d8 2d movb $0x2d,-0x28(%ebp,%eax,1)
while(--i >= 0)
801005b6: 83 eb 01 sub $0x1,%ebx
801005b9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
consputc(buf[i]);
801005c0: 0f be 44 1d d8 movsbl -0x28(%ebp,%ebx,1),%eax
}while((x /= base) != 0);
if(sign)
buf[i++] = '-';
while(--i >= 0)
801005c5: 83 eb 01 sub $0x1,%ebx
consputc(buf[i]);
801005c8: e8 13 fe ff ff call 801003e0 <consputc>
}while((x /= base) != 0);
if(sign)
buf[i++] = '-';
while(--i >= 0)
801005cd: 83 fb ff cmp $0xffffffff,%ebx
801005d0: 75 ee jne 801005c0 <printint+0x50>
consputc(buf[i]);
}
801005d2: 83 c4 1c add $0x1c,%esp
801005d5: 5b pop %ebx
801005d6: 5e pop %esi
801005d7: 5f pop %edi
801005d8: 5d pop %ebp
801005d9: c3 ret
801005da: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
uint x;
if(sign && (sign = xx < 0))
x = -xx;
else
x = xx;
801005e0: 31 ff xor %edi,%edi
801005e2: eb a6 jmp 8010058a <printint+0x1a>
801005e4: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
801005ea: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
801005f0 <consolewrite>:
return target - n;
}
int
consolewrite(struct inode *ip, char *buf, int n)
{
801005f0: 55 push %ebp
801005f1: 89 e5 mov %esp,%ebp
801005f3: 57 push %edi
801005f4: 56 push %esi
801005f5: 53 push %ebx
801005f6: 83 ec 1c sub $0x1c,%esp
int i;
iunlock(ip);
801005f9: 8b 45 08 mov 0x8(%ebp),%eax
return target - n;
}
int
consolewrite(struct inode *ip, char *buf, int n)
{
801005fc: 8b 75 10 mov 0x10(%ebp),%esi
int i;
iunlock(ip);
801005ff: 89 04 24 mov %eax,(%esp)
80100602: e8 79 11 00 00 call 80101780 <iunlock>
acquire(&cons.lock);
80100607: c7 04 24 20 a5 10 80 movl $0x8010a520,(%esp)
8010060e: e8 1d 3b 00 00 call 80104130 <acquire>
80100613: 8b 7d 0c mov 0xc(%ebp),%edi
for(i = 0; i < n; i++)
80100616: 85 f6 test %esi,%esi
80100618: 8d 1c 37 lea (%edi,%esi,1),%ebx
8010061b: 7e 12 jle 8010062f <consolewrite+0x3f>
8010061d: 8d 76 00 lea 0x0(%esi),%esi
consputc(buf[i] & 0xff);
80100620: 0f b6 07 movzbl (%edi),%eax
80100623: 83 c7 01 add $0x1,%edi
80100626: e8 b5 fd ff ff call 801003e0 <consputc>
{
int i;
iunlock(ip);
acquire(&cons.lock);
for(i = 0; i < n; i++)
8010062b: 39 df cmp %ebx,%edi
8010062d: 75 f1 jne 80100620 <consolewrite+0x30>
consputc(buf[i] & 0xff);
release(&cons.lock);
8010062f: c7 04 24 20 a5 10 80 movl $0x8010a520,(%esp)
80100636: e8 e5 3b 00 00 call 80104220 <release>
ilock(ip);
8010063b: 8b 45 08 mov 0x8(%ebp),%eax
8010063e: 89 04 24 mov %eax,(%esp)
80100641: e8 5a 10 00 00 call 801016a0 <ilock>
return n;
}
80100646: 83 c4 1c add $0x1c,%esp
80100649: 89 f0 mov %esi,%eax
8010064b: 5b pop %ebx
8010064c: 5e pop %esi
8010064d: 5f pop %edi
8010064e: 5d pop %ebp
8010064f: c3 ret
80100650 <cprintf>:
//PAGEBREAK: 50
// Print to the console. only understands %d, %x, %p, %s.
void
cprintf(char *fmt, ...)
{
80100650: 55 push %ebp
80100651: 89 e5 mov %esp,%ebp
80100653: 57 push %edi
80100654: 56 push %esi
80100655: 53 push %ebx
80100656: 83 ec 1c sub $0x1c,%esp
int i, c, locking;
uint *argp;
char *s;
locking = cons.locking;
80100659: a1 54 a5 10 80 mov 0x8010a554,%eax
if(locking)
8010065e: 85 c0 test %eax,%eax
{
int i, c, locking;
uint *argp;
char *s;
locking = cons.locking;
80100660: 89 45 e0 mov %eax,-0x20(%ebp)
if(locking)
80100663: 0f 85 27 01 00 00 jne 80100790 <cprintf+0x140>
acquire(&cons.lock);
if (fmt == 0)
80100669: 8b 45 08 mov 0x8(%ebp),%eax
8010066c: 85 c0 test %eax,%eax
8010066e: 89 c1 mov %eax,%ecx
80100670: 0f 84 2b 01 00 00 je 801007a1 <cprintf+0x151>
panic("null fmt");
argp = (uint*)(void*)(&fmt + 1);
for(i = 0; (c = fmt[i] & 0xff) != 0; i++){
80100676: 0f b6 00 movzbl (%eax),%eax
80100679: 31 db xor %ebx,%ebx
8010067b: 89 cf mov %ecx,%edi
8010067d: 8d 75 0c lea 0xc(%ebp),%esi
80100680: 85 c0 test %eax,%eax
80100682: 75 4c jne 801006d0 <cprintf+0x80>
80100684: eb 5f jmp 801006e5 <cprintf+0x95>
80100686: 66 90 xchg %ax,%ax
if(c != '%'){
consputc(c);
continue;
}
c = fmt[++i] & 0xff;
80100688: 83 c3 01 add $0x1,%ebx
8010068b: 0f b6 14 1f movzbl (%edi,%ebx,1),%edx
if(c == 0)
8010068f: 85 d2 test %edx,%edx
80100691: 74 52 je 801006e5 <cprintf+0x95>
break;
switch(c){
80100693: 83 fa 70 cmp $0x70,%edx
80100696: 74 72 je 8010070a <cprintf+0xba>
80100698: 7f 66 jg 80100700 <cprintf+0xb0>
8010069a: 83 fa 25 cmp $0x25,%edx
8010069d: 8d 76 00 lea 0x0(%esi),%esi
801006a0: 0f 84 a2 00 00 00 je 80100748 <cprintf+0xf8>
801006a6: 83 fa 64 cmp $0x64,%edx
801006a9: 75 7d jne 80100728 <cprintf+0xd8>
case 'd':
printint(*argp++, 10, 1);
801006ab: 8d 46 04 lea 0x4(%esi),%eax
801006ae: b9 01 00 00 00 mov $0x1,%ecx
801006b3: 89 45 e4 mov %eax,-0x1c(%ebp)
801006b6: 8b 06 mov (%esi),%eax
801006b8: ba 0a 00 00 00 mov $0xa,%edx
801006bd: e8 ae fe ff ff call 80100570 <printint>
801006c2: 8b 75 e4 mov -0x1c(%ebp),%esi
if (fmt == 0)
panic("null fmt");
argp = (uint*)(void*)(&fmt + 1);
for(i = 0; (c = fmt[i] & 0xff) != 0; i++){
801006c5: 83 c3 01 add $0x1,%ebx
801006c8: 0f b6 04 1f movzbl (%edi,%ebx,1),%eax
801006cc: 85 c0 test %eax,%eax
801006ce: 74 15 je 801006e5 <cprintf+0x95>
if(c != '%'){
801006d0: 83 f8 25 cmp $0x25,%eax
801006d3: 74 b3 je 80100688 <cprintf+0x38>
consputc('%');
break;
default:
// Print unknown % sequence to draw attention.
consputc('%');
consputc(c);
801006d5: e8 06 fd ff ff call 801003e0 <consputc>
if (fmt == 0)
panic("null fmt");
argp = (uint*)(void*)(&fmt + 1);
for(i = 0; (c = fmt[i] & 0xff) != 0; i++){
801006da: 83 c3 01 add $0x1,%ebx
801006dd: 0f b6 04 1f movzbl (%edi,%ebx,1),%eax
801006e1: 85 c0 test %eax,%eax
801006e3: 75 eb jne 801006d0 <cprintf+0x80>
consputc(c);
break;
}
}
if(locking)
801006e5: 8b 45 e0 mov -0x20(%ebp),%eax
801006e8: 85 c0 test %eax,%eax
801006ea: 74 0c je 801006f8 <cprintf+0xa8>
release(&cons.lock);
801006ec: c7 04 24 20 a5 10 80 movl $0x8010a520,(%esp)
801006f3: e8 28 3b 00 00 call 80104220 <release>
}
801006f8: 83 c4 1c add $0x1c,%esp
801006fb: 5b pop %ebx
801006fc: 5e pop %esi
801006fd: 5f pop %edi
801006fe: 5d pop %ebp
801006ff: c3 ret
continue;
}
c = fmt[++i] & 0xff;
if(c == 0)
break;
switch(c){
80100700: 83 fa 73 cmp $0x73,%edx
80100703: 74 53 je 80100758 <cprintf+0x108>
80100705: 83 fa 78 cmp $0x78,%edx
80100708: 75 1e jne 80100728 <cprintf+0xd8>
case 'd':
printint(*argp++, 10, 1);
break;
case 'x':
case 'p':
printint(*argp++, 16, 0);
8010070a: 8d 46 04 lea 0x4(%esi),%eax
8010070d: 31 c9 xor %ecx,%ecx
8010070f: 89 45 e4 mov %eax,-0x1c(%ebp)
80100712: 8b 06 mov (%esi),%eax
80100714: ba 10 00 00 00 mov $0x10,%edx
80100719: e8 52 fe ff ff call 80100570 <printint>
8010071e: 8b 75 e4 mov -0x1c(%ebp),%esi
break;
80100721: eb a2 jmp 801006c5 <cprintf+0x75>
80100723: 90 nop
80100724: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
case '%':
consputc('%');
break;
default:
// Print unknown % sequence to draw attention.
consputc('%');
80100728: b8 25 00 00 00 mov $0x25,%eax
8010072d: 89 55 e4 mov %edx,-0x1c(%ebp)
80100730: e8 ab fc ff ff call 801003e0 <consputc>
consputc(c);
80100735: 8b 55 e4 mov -0x1c(%ebp),%edx
80100738: 89 d0 mov %edx,%eax
8010073a: e8 a1 fc ff ff call 801003e0 <consputc>
8010073f: eb 99 jmp 801006da <cprintf+0x8a>
80100741: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
s = "(null)";
for(; *s; s++)
consputc(*s);
break;
case '%':
consputc('%');
80100748: b8 25 00 00 00 mov $0x25,%eax
8010074d: e8 8e fc ff ff call 801003e0 <consputc>
break;
80100752: e9 6e ff ff ff jmp 801006c5 <cprintf+0x75>
80100757: 90 nop
case 'x':
case 'p':
printint(*argp++, 16, 0);
break;
case 's':
if((s = (char*)*argp++) == 0)
80100758: 8d 46 04 lea 0x4(%esi),%eax
8010075b: 8b 36 mov (%esi),%esi
8010075d: 89 45 e4 mov %eax,-0x1c(%ebp)
s = "(null)";
80100760: b8 f8 6d 10 80 mov $0x80106df8,%eax
80100765: 85 f6 test %esi,%esi
80100767: 0f 44 f0 cmove %eax,%esi
for(; *s; s++)
8010076a: 0f be 06 movsbl (%esi),%eax
8010076d: 84 c0 test %al,%al
8010076f: 74 16 je 80100787 <cprintf+0x137>
80100771: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80100778: 83 c6 01 add $0x1,%esi
consputc(*s);
8010077b: e8 60 fc ff ff call 801003e0 <consputc>
printint(*argp++, 16, 0);
break;
case 's':
if((s = (char*)*argp++) == 0)
s = "(null)";
for(; *s; s++)
80100780: 0f be 06 movsbl (%esi),%eax
80100783: 84 c0 test %al,%al
80100785: 75 f1 jne 80100778 <cprintf+0x128>
case 'x':
case 'p':
printint(*argp++, 16, 0);
break;
case 's':
if((s = (char*)*argp++) == 0)
80100787: 8b 75 e4 mov -0x1c(%ebp),%esi
8010078a: e9 36 ff ff ff jmp 801006c5 <cprintf+0x75>
8010078f: 90 nop
uint *argp;
char *s;
locking = cons.locking;
if(locking)
acquire(&cons.lock);
80100790: c7 04 24 20 a5 10 80 movl $0x8010a520,(%esp)
80100797: e8 94 39 00 00 call 80104130 <acquire>
8010079c: e9 c8 fe ff ff jmp 80100669 <cprintf+0x19>
if (fmt == 0)
panic("null fmt");
801007a1: c7 04 24 ff 6d 10 80 movl $0x80106dff,(%esp)
801007a8: e8 b3 fb ff ff call 80100360 <panic>
801007ad: 8d 76 00 lea 0x0(%esi),%esi
801007b0 <consoleintr>:
#define C(x) ((x)-'@') // Control-x
void
consoleintr(int (*getc)(void))
{
801007b0: 55 push %ebp
801007b1: 89 e5 mov %esp,%ebp
801007b3: 57 push %edi
801007b4: 56 push %esi
int c, doprocdump = 0;
801007b5: 31 f6 xor %esi,%esi
#define C(x) ((x)-'@') // Control-x
void
consoleintr(int (*getc)(void))
{
801007b7: 53 push %ebx
801007b8: 83 ec 1c sub $0x1c,%esp
801007bb: 8b 5d 08 mov 0x8(%ebp),%ebx
int c, doprocdump = 0;
acquire(&cons.lock);
801007be: c7 04 24 20 a5 10 80 movl $0x8010a520,(%esp)
801007c5: e8 66 39 00 00 call 80104130 <acquire>
801007ca: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
while((c = getc()) >= 0){
801007d0: ff d3 call *%ebx
801007d2: 85 c0 test %eax,%eax
801007d4: 89 c7 mov %eax,%edi
801007d6: 78 48 js 80100820 <consoleintr+0x70>
switch(c){
801007d8: 83 ff 10 cmp $0x10,%edi
801007db: 0f 84 2f 01 00 00 je 80100910 <consoleintr+0x160>
801007e1: 7e 5d jle 80100840 <consoleintr+0x90>
801007e3: 83 ff 15 cmp $0x15,%edi
801007e6: 0f 84 d4 00 00 00 je 801008c0 <consoleintr+0x110>
801007ec: 83 ff 7f cmp $0x7f,%edi
801007ef: 90 nop
801007f0: 75 53 jne 80100845 <consoleintr+0x95>
input.e--;
consputc(BACKSPACE);
}
break;
case C('H'): case '\x7f': // Backspace
if(input.e != input.w){
801007f2: a1 a8 ff 10 80 mov 0x8010ffa8,%eax
801007f7: 3b 05 a4 ff 10 80 cmp 0x8010ffa4,%eax
801007fd: 74 d1 je 801007d0 <consoleintr+0x20>
input.e--;
801007ff: 83 e8 01 sub $0x1,%eax
80100802: a3 a8 ff 10 80 mov %eax,0x8010ffa8
consputc(BACKSPACE);
80100807: b8 00 01 00 00 mov $0x100,%eax
8010080c: e8 cf fb ff ff call 801003e0 <consputc>
consoleintr(int (*getc)(void))
{
int c, doprocdump = 0;
acquire(&cons.lock);
while((c = getc()) >= 0){
80100811: ff d3 call *%ebx
80100813: 85 c0 test %eax,%eax
80100815: 89 c7 mov %eax,%edi
80100817: 79 bf jns 801007d8 <consoleintr+0x28>
80100819: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
}
}
break;
}
}
release(&cons.lock);
80100820: c7 04 24 20 a5 10 80 movl $0x8010a520,(%esp)
80100827: e8 f4 39 00 00 call 80104220 <release>
if(doprocdump) {
8010082c: 85 f6 test %esi,%esi
8010082e: 0f 85 ec 00 00 00 jne 80100920 <consoleintr+0x170>
procdump(); // now call procdump() wo. cons.lock held
}
}
80100834: 83 c4 1c add $0x1c,%esp
80100837: 5b pop %ebx
80100838: 5e pop %esi
80100839: 5f pop %edi
8010083a: 5d pop %ebp
8010083b: c3 ret
8010083c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
{
int c, doprocdump = 0;
acquire(&cons.lock);
while((c = getc()) >= 0){
switch(c){
80100840: 83 ff 08 cmp $0x8,%edi
80100843: 74 ad je 801007f2 <consoleintr+0x42>
input.e--;
consputc(BACKSPACE);
}
break;
default:
if(c != 0 && input.e-input.r < INPUT_BUF){
80100845: 85 ff test %edi,%edi
80100847: 74 87 je 801007d0 <consoleintr+0x20>
80100849: a1 a8 ff 10 80 mov 0x8010ffa8,%eax
8010084e: 89 c2 mov %eax,%edx
80100850: 2b 15 a0 ff 10 80 sub 0x8010ffa0,%edx
80100856: 83 fa 7f cmp $0x7f,%edx
80100859: 0f 87 71 ff ff ff ja 801007d0 <consoleintr+0x20>
c = (c == '\r') ? '\n' : c;
input.buf[input.e++ % INPUT_BUF] = c;
8010085f: 8d 50 01 lea 0x1(%eax),%edx
80100862: 83 e0 7f and $0x7f,%eax
consputc(BACKSPACE);
}
break;
default:
if(c != 0 && input.e-input.r < INPUT_BUF){
c = (c == '\r') ? '\n' : c;
80100865: 83 ff 0d cmp $0xd,%edi
input.buf[input.e++ % INPUT_BUF] = c;
80100868: 89 15 a8 ff 10 80 mov %edx,0x8010ffa8
consputc(BACKSPACE);
}
break;
default:
if(c != 0 && input.e-input.r < INPUT_BUF){
c = (c == '\r') ? '\n' : c;
8010086e: 0f 84 b8 00 00 00 je 8010092c <consoleintr+0x17c>
input.buf[input.e++ % INPUT_BUF] = c;
80100874: 89 f9 mov %edi,%ecx
80100876: 88 88 20 ff 10 80 mov %cl,-0x7fef00e0(%eax)
consputc(c);
8010087c: 89 f8 mov %edi,%eax
8010087e: e8 5d fb ff ff call 801003e0 <consputc>
if(c == '\n' || c == C('D') || input.e == input.r+INPUT_BUF){
80100883: 83 ff 04 cmp $0x4,%edi
80100886: a1 a8 ff 10 80 mov 0x8010ffa8,%eax
8010088b: 74 19 je 801008a6 <consoleintr+0xf6>
8010088d: 83 ff 0a cmp $0xa,%edi
80100890: 74 14 je 801008a6 <consoleintr+0xf6>
80100892: 8b 0d a0 ff 10 80 mov 0x8010ffa0,%ecx
80100898: 8d 91 80 00 00 00 lea 0x80(%ecx),%edx
8010089e: 39 d0 cmp %edx,%eax
801008a0: 0f 85 2a ff ff ff jne 801007d0 <consoleintr+0x20>
input.w = input.e;
wakeup(&input.r);
801008a6: c7 04 24 a0 ff 10 80 movl $0x8010ffa0,(%esp)
if(c != 0 && input.e-input.r < INPUT_BUF){
c = (c == '\r') ? '\n' : c;
input.buf[input.e++ % INPUT_BUF] = c;
consputc(c);
if(c == '\n' || c == C('D') || input.e == input.r+INPUT_BUF){
input.w = input.e;
801008ad: a3 a4 ff 10 80 mov %eax,0x8010ffa4
wakeup(&input.r);
801008b2: e8 c9 34 00 00 call 80103d80 <wakeup>
801008b7: e9 14 ff ff ff jmp 801007d0 <consoleintr+0x20>
801008bc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
case C('P'): // Process listing.
// procdump() locks cons.lock indirectly; invoke later
doprocdump = 1;
break;
case C('U'): // Kill line.
while(input.e != input.w &&
801008c0: a1 a8 ff 10 80 mov 0x8010ffa8,%eax
801008c5: 3b 05 a4 ff 10 80 cmp 0x8010ffa4,%eax
801008cb: 75 2b jne 801008f8 <consoleintr+0x148>
801008cd: e9 fe fe ff ff jmp 801007d0 <consoleintr+0x20>
801008d2: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
input.buf[(input.e-1) % INPUT_BUF] != '\n'){
input.e--;
801008d8: a3 a8 ff 10 80 mov %eax,0x8010ffa8
consputc(BACKSPACE);
801008dd: b8 00 01 00 00 mov $0x100,%eax
801008e2: e8 f9 fa ff ff call 801003e0 <consputc>
case C('P'): // Process listing.
// procdump() locks cons.lock indirectly; invoke later
doprocdump = 1;
break;
case C('U'): // Kill line.
while(input.e != input.w &&
801008e7: a1 a8 ff 10 80 mov 0x8010ffa8,%eax
801008ec: 3b 05 a4 ff 10 80 cmp 0x8010ffa4,%eax
801008f2: 0f 84 d8 fe ff ff je 801007d0 <consoleintr+0x20>
input.buf[(input.e-1) % INPUT_BUF] != '\n'){
801008f8: 83 e8 01 sub $0x1,%eax
801008fb: 89 c2 mov %eax,%edx
801008fd: 83 e2 7f and $0x7f,%edx
case C('P'): // Process listing.
// procdump() locks cons.lock indirectly; invoke later
doprocdump = 1;
break;
case C('U'): // Kill line.
while(input.e != input.w &&
80100900: 80 ba 20 ff 10 80 0a cmpb $0xa,-0x7fef00e0(%edx)
80100907: 75 cf jne 801008d8 <consoleintr+0x128>
80100909: e9 c2 fe ff ff jmp 801007d0 <consoleintr+0x20>
8010090e: 66 90 xchg %ax,%ax
acquire(&cons.lock);
while((c = getc()) >= 0){
switch(c){
case C('P'): // Process listing.
// procdump() locks cons.lock indirectly; invoke later
doprocdump = 1;
80100910: be 01 00 00 00 mov $0x1,%esi
80100915: e9 b6 fe ff ff jmp 801007d0 <consoleintr+0x20>
8010091a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
}
release(&cons.lock);
if(doprocdump) {
procdump(); // now call procdump() wo. cons.lock held
}
}
80100920: 83 c4 1c add $0x1c,%esp
80100923: 5b pop %ebx
80100924: 5e pop %esi
80100925: 5f pop %edi
80100926: 5d pop %ebp
break;
}
}
release(&cons.lock);
if(doprocdump) {
procdump(); // now call procdump() wo. cons.lock held
80100927: e9 34 35 00 00 jmp 80103e60 <procdump>
}
break;
default:
if(c != 0 && input.e-input.r < INPUT_BUF){
c = (c == '\r') ? '\n' : c;
input.buf[input.e++ % INPUT_BUF] = c;
8010092c: c6 80 20 ff 10 80 0a movb $0xa,-0x7fef00e0(%eax)
consputc(c);
80100933: b8 0a 00 00 00 mov $0xa,%eax
80100938: e8 a3 fa ff ff call 801003e0 <consputc>
8010093d: a1 a8 ff 10 80 mov 0x8010ffa8,%eax
80100942: e9 5f ff ff ff jmp 801008a6 <consoleintr+0xf6>
80100947: 89 f6 mov %esi,%esi
80100949: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80100950 <consoleinit>:
return n;
}
void
consoleinit(void)
{
80100950: 55 push %ebp
80100951: 89 e5 mov %esp,%ebp
80100953: 83 ec 18 sub $0x18,%esp
initlock(&cons.lock, "console");
80100956: c7 44 24 04 08 6e 10 movl $0x80106e08,0x4(%esp)
8010095d: 80
8010095e: c7 04 24 20 a5 10 80 movl $0x8010a520,(%esp)
80100965: e8 d6 36 00 00 call 80104040 <initlock>
devsw[CONSOLE].write = consolewrite;
devsw[CONSOLE].read = consoleread;
cons.locking = 1;
ioapicenable(IRQ_KBD, 0);
8010096a: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
80100971: 00
80100972: c7 04 24 01 00 00 00 movl $0x1,(%esp)
void
consoleinit(void)
{
initlock(&cons.lock, "console");
devsw[CONSOLE].write = consolewrite;
80100979: c7 05 6c 09 11 80 f0 movl $0x801005f0,0x8011096c
80100980: 05 10 80
devsw[CONSOLE].read = consoleread;
80100983: c7 05 68 09 11 80 70 movl $0x80100270,0x80110968
8010098a: 02 10 80
cons.locking = 1;
8010098d: c7 05 54 a5 10 80 01 movl $0x1,0x8010a554
80100994: 00 00 00
ioapicenable(IRQ_KBD, 0);
80100997: e8 04 19 00 00 call 801022a0 <ioapicenable>
}
8010099c: c9 leave
8010099d: c3 ret
8010099e: 66 90 xchg %ax,%ax
801009a0 <exec>:
//
//returns address of page fault, -1 otherwise
//(N+1) < rcr2()<ke - N + pgsize
int
exec(char *path, char **argv)
{
801009a0: 55 push %ebp
801009a1: 89 e5 mov %esp,%ebp
801009a3: 57 push %edi
801009a4: 56 push %esi
801009a5: 53 push %ebx
801009a6: 81 ec 2c 01 00 00 sub $0x12c,%esp
uint argc, sz, sb, sp, ustack[3+MAXARG+1];
struct elfhdr elf;
struct inode *ip;
struct proghdr ph;
pde_t *pgdir, *oldpgdir;
struct proc *curproc = myproc();
801009ac: e8 df 2c 00 00 call 80103690 <myproc>
801009b1: 89 85 f4 fe ff ff mov %eax,-0x10c(%ebp)
begin_op();
801009b7: e8 44 21 00 00 call 80102b00 <begin_op>
if((ip = namei(path)) == 0){
801009bc: 8b 45 08 mov 0x8(%ebp),%eax
801009bf: 89 04 24 mov %eax,(%esp)
801009c2: e8 29 15 00 00 call 80101ef0 <namei>
801009c7: 85 c0 test %eax,%eax
801009c9: 89 c3 mov %eax,%ebx
801009cb: 0f 84 3f 02 00 00 je 80100c10 <exec+0x270>
end_op();
cprintf("exec: fail\n");
return -1;
}
ilock(ip);
801009d1: 89 04 24 mov %eax,(%esp)
801009d4: e8 c7 0c 00 00 call 801016a0 <ilock>
pgdir = 0;
// Check ELF header
if(readi(ip, (char*)&elf, 0, sizeof(elf)) != sizeof(elf))
801009d9: 8d 85 24 ff ff ff lea -0xdc(%ebp),%eax
801009df: c7 44 24 0c 34 00 00 movl $0x34,0xc(%esp)
801009e6: 00
801009e7: c7 44 24 08 00 00 00 movl $0x0,0x8(%esp)
801009ee: 00
801009ef: 89 44 24 04 mov %eax,0x4(%esp)
801009f3: 89 1c 24 mov %ebx,(%esp)
801009f6: e8 55 0f 00 00 call 80101950 <readi>
801009fb: 83 f8 34 cmp $0x34,%eax
801009fe: 74 20 je 80100a20 <exec+0x80>
bad:
if(pgdir)
freevm(pgdir);
if(ip){
iunlockput(ip);
80100a00: 89 1c 24 mov %ebx,(%esp)
80100a03: e8 f8 0e 00 00 call 80101900 <iunlockput>
end_op();
80100a08: e8 63 21 00 00 call 80102b70 <end_op>
}
return -1;
80100a0d: b8 ff ff ff ff mov $0xffffffff,%eax
}
80100a12: 81 c4 2c 01 00 00 add $0x12c,%esp
80100a18: 5b pop %ebx
80100a19: 5e pop %esi
80100a1a: 5f pop %edi
80100a1b: 5d pop %ebp
80100a1c: c3 ret
80100a1d: 8d 76 00 lea 0x0(%esi),%esi
pgdir = 0;
// Check ELF header
if(readi(ip, (char*)&elf, 0, sizeof(elf)) != sizeof(elf))
goto bad;
if(elf.magic != ELF_MAGIC)
80100a20: 81 bd 24 ff ff ff 7f cmpl $0x464c457f,-0xdc(%ebp)
80100a27: 45 4c 46
80100a2a: 75 d4 jne 80100a00 <exec+0x60>
goto bad;
if((pgdir = setupkvm()) == 0)
80100a2c: e8 8f 5f 00 00 call 801069c0 <setupkvm>
80100a31: 85 c0 test %eax,%eax
80100a33: 89 85 f0 fe ff ff mov %eax,-0x110(%ebp)
80100a39: 74 c5 je 80100a00 <exec+0x60>
goto bad;
// Load program into memory.
sz = 0;
for(i=0, off=elf.phoff; i<elf.phnum; i++, off+=sizeof(ph)){
80100a3b: 66 83 bd 50 ff ff ff cmpw $0x0,-0xb0(%ebp)
80100a42: 00
80100a43: 8b b5 40 ff ff ff mov -0xc0(%ebp),%esi
if((pgdir = setupkvm()) == 0)
goto bad;
// Load program into memory.
sz = 0;
80100a49: c7 85 ec fe ff ff 00 movl $0x0,-0x114(%ebp)
80100a50: 00 00 00
for(i=0, off=elf.phoff; i<elf.phnum; i++, off+=sizeof(ph)){
80100a53: 0f 84 da 00 00 00 je 80100b33 <exec+0x193>
80100a59: 31 ff xor %edi,%edi
80100a5b: eb 18 jmp 80100a75 <exec+0xd5>
80100a5d: 8d 76 00 lea 0x0(%esi),%esi
80100a60: 0f b7 85 50 ff ff ff movzwl -0xb0(%ebp),%eax
80100a67: 83 c7 01 add $0x1,%edi
80100a6a: 83 c6 20 add $0x20,%esi
80100a6d: 39 f8 cmp %edi,%eax
80100a6f: 0f 8e be 00 00 00 jle 80100b33 <exec+0x193>
if(readi(ip, (char*)&ph, off, sizeof(ph)) != sizeof(ph))
80100a75: 8d 85 04 ff ff ff lea -0xfc(%ebp),%eax
80100a7b: c7 44 24 0c 20 00 00 movl $0x20,0xc(%esp)
80100a82: 00
80100a83: 89 74 24 08 mov %esi,0x8(%esp)
80100a87: 89 44 24 04 mov %eax,0x4(%esp)
80100a8b: 89 1c 24 mov %ebx,(%esp)
80100a8e: e8 bd 0e 00 00 call 80101950 <readi>
80100a93: 83 f8 20 cmp $0x20,%eax
80100a96: 0f 85 84 00 00 00 jne 80100b20 <exec+0x180>
goto bad;
if(ph.type != ELF_PROG_LOAD)
80100a9c: 83 bd 04 ff ff ff 01 cmpl $0x1,-0xfc(%ebp)
80100aa3: 75 bb jne 80100a60 <exec+0xc0>
continue;
if(ph.memsz < ph.filesz)
80100aa5: 8b 85 18 ff ff ff mov -0xe8(%ebp),%eax
80100aab: 3b 85 14 ff ff ff cmp -0xec(%ebp),%eax
80100ab1: 72 6d jb 80100b20 <exec+0x180>
goto bad;
if(ph.vaddr + ph.memsz < ph.vaddr)
80100ab3: 03 85 0c ff ff ff add -0xf4(%ebp),%eax
80100ab9: 72 65 jb 80100b20 <exec+0x180>
goto bad;
if((sz = allocuvm(pgdir, sz, ph.vaddr + ph.memsz)) == 0)
80100abb: 89 44 24 08 mov %eax,0x8(%esp)
80100abf: 8b 85 ec fe ff ff mov -0x114(%ebp),%eax
80100ac5: 89 44 24 04 mov %eax,0x4(%esp)
80100ac9: 8b 85 f0 fe ff ff mov -0x110(%ebp),%eax
80100acf: 89 04 24 mov %eax,(%esp)
80100ad2: e8 49 5d 00 00 call 80106820 <allocuvm>
80100ad7: 85 c0 test %eax,%eax
80100ad9: 89 85 ec fe ff ff mov %eax,-0x114(%ebp)
80100adf: 74 3f je 80100b20 <exec+0x180>
goto bad;
if(ph.vaddr % PGSIZE != 0)
80100ae1: 8b 85 0c ff ff ff mov -0xf4(%ebp),%eax
80100ae7: a9 ff 0f 00 00 test $0xfff,%eax
80100aec: 75 32 jne 80100b20 <exec+0x180>
goto bad;
if(loaduvm(pgdir, (char*)ph.vaddr, ip, ph.off, ph.filesz) < 0)
80100aee: 8b 95 14 ff ff ff mov -0xec(%ebp),%edx
80100af4: 89 44 24 04 mov %eax,0x4(%esp)
80100af8: 8b 85 f0 fe ff ff mov -0x110(%ebp),%eax
80100afe: 89 5c 24 08 mov %ebx,0x8(%esp)
80100b02: 89 54 24 10 mov %edx,0x10(%esp)
80100b06: 8b 95 08 ff ff ff mov -0xf8(%ebp),%edx
80100b0c: 89 04 24 mov %eax,(%esp)
80100b0f: 89 54 24 0c mov %edx,0xc(%esp)
80100b13: e8 48 5c 00 00 call 80106760 <loaduvm>
80100b18: 85 c0 test %eax,%eax
80100b1a: 0f 89 40 ff ff ff jns 80100a60 <exec+0xc0>
freevm(oldpgdir);
return 0;
bad:
if(pgdir)
freevm(pgdir);
80100b20: 8b 85 f0 fe ff ff mov -0x110(%ebp),%eax
80100b26: 89 04 24 mov %eax,(%esp)
80100b29: e8 12 5e 00 00 call 80106940 <freevm>
80100b2e: e9 cd fe ff ff jmp 80100a00 <exec+0x60>
if(ph.vaddr % PGSIZE != 0)
goto bad;
if(loaduvm(pgdir, (char*)ph.vaddr, ip, ph.off, ph.filesz) < 0)
goto bad;
}
iunlockput(ip);
80100b33: 89 1c 24 mov %ebx,(%esp)
80100b36: e8 c5 0d 00 00 call 80101900 <iunlockput>
80100b3b: 90 nop
80100b3c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
end_op();
80100b40: e8 2b 20 00 00 call 80102b70 <end_op>
ip = 0;
// Allocate two pages at the next page boundary.
// Make the first inaccessible. Use the second as the user stack.
sz = PGROUNDUP(sz);
if((sp = allocuvm(pgdir, KERNBASE - PGSIZE, KERNBASE - 4)) == 0)
80100b45: 8b 85 f0 fe ff ff mov -0x110(%ebp),%eax
80100b4b: c7 44 24 08 fc ff ff movl $0x7ffffffc,0x8(%esp)
80100b52: 7f
80100b53: c7 44 24 04 00 f0 ff movl $0x7ffff000,0x4(%esp)
80100b5a: 7f
80100b5b: 89 04 24 mov %eax,(%esp)
80100b5e: e8 bd 5c 00 00 call 80106820 <allocuvm>
80100b63: 85 c0 test %eax,%eax
80100b65: 0f 84 8d 00 00 00 je 80100bf8 <exec+0x258>
//clearpteu(pgdir, (char*)(sz - 2*PGSIZE));
sp = KERNBASE - 4;
sb = KERNBASE - PGSIZE;
// Push argument strings, prepare rest of stack in ustack.
for(argc = 0; argv[argc]; argc++) {
80100b6b: 8b 45 0c mov 0xc(%ebp),%eax
80100b6e: 8b 00 mov (%eax),%eax
80100b70: 85 c0 test %eax,%eax
80100b72: 0f 84 9b 01 00 00 je 80100d13 <exec+0x373>
80100b78: 8b 4d 0c mov 0xc(%ebp),%ecx
80100b7b: 31 d2 xor %edx,%edx
80100b7d: bb fc ff ff 7f mov $0x7ffffffc,%ebx
80100b82: 8d 71 04 lea 0x4(%ecx),%esi
80100b85: 89 cf mov %ecx,%edi
80100b87: 89 f1 mov %esi,%ecx
80100b89: 89 d6 mov %edx,%esi
80100b8b: 89 ca mov %ecx,%edx
80100b8d: eb 27 jmp 80100bb6 <exec+0x216>
80100b8f: 90 nop
80100b90: 8b 95 e8 fe ff ff mov -0x118(%ebp),%edx
if(argc >= MAXARG)
goto bad;
sp = (sp - (strlen(argv[argc]) + 1)) & ~3;
if(copyout(pgdir, sp, argv[argc], strlen(argv[argc]) + 1) < 0)
goto bad;
ustack[3+argc] = sp;
80100b96: 8d 8d 58 ff ff ff lea -0xa8(%ebp),%ecx
80100b9c: 89 9c b5 64 ff ff ff mov %ebx,-0x9c(%ebp,%esi,4)
//clearpteu(pgdir, (char*)(sz - 2*PGSIZE));
sp = KERNBASE - 4;
sb = KERNBASE - PGSIZE;
// Push argument strings, prepare rest of stack in ustack.
for(argc = 0; argv[argc]; argc++) {
80100ba3: 83 c6 01 add $0x1,%esi
80100ba6: 8b 02 mov (%edx),%eax
80100ba8: 89 d7 mov %edx,%edi
80100baa: 85 c0 test %eax,%eax
80100bac: 74 7d je 80100c2b <exec+0x28b>
80100bae: 83 c2 04 add $0x4,%edx
if(argc >= MAXARG)
80100bb1: 83 fe 20 cmp $0x20,%esi
80100bb4: 74 42 je 80100bf8 <exec+0x258>
goto bad;
sp = (sp - (strlen(argv[argc]) + 1)) & ~3;
80100bb6: 89 04 24 mov %eax,(%esp)
80100bb9: 89 95 e8 fe ff ff mov %edx,-0x118(%ebp)
80100bbf: e8 cc 38 00 00 call 80104490 <strlen>
80100bc4: f7 d0 not %eax
80100bc6: 01 c3 add %eax,%ebx
if(copyout(pgdir, sp, argv[argc], strlen(argv[argc]) + 1) < 0)
80100bc8: 8b 07 mov (%edi),%eax
// Push argument strings, prepare rest of stack in ustack.
for(argc = 0; argv[argc]; argc++) {
if(argc >= MAXARG)
goto bad;
sp = (sp - (strlen(argv[argc]) + 1)) & ~3;
80100bca: 83 e3 fc and $0xfffffffc,%ebx
if(copyout(pgdir, sp, argv[argc], strlen(argv[argc]) + 1) < 0)
80100bcd: 89 04 24 mov %eax,(%esp)
80100bd0: e8 bb 38 00 00 call 80104490 <strlen>
80100bd5: 83 c0 01 add $0x1,%eax
80100bd8: 89 44 24 0c mov %eax,0xc(%esp)
80100bdc: 8b 07 mov (%edi),%eax
80100bde: 89 5c 24 04 mov %ebx,0x4(%esp)
80100be2: 89 44 24 08 mov %eax,0x8(%esp)
80100be6: 8b 85 f0 fe ff ff mov -0x110(%ebp),%eax
80100bec: 89 04 24 mov %eax,(%esp)
80100bef: e8 9c 60 00 00 call 80106c90 <copyout>
80100bf4: 85 c0 test %eax,%eax
80100bf6: 79 98 jns 80100b90 <exec+0x1f0>
freevm(oldpgdir);
return 0;
bad:
if(pgdir)
freevm(pgdir);
80100bf8: 8b 85 f0 fe ff ff mov -0x110(%ebp),%eax
80100bfe: 89 04 24 mov %eax,(%esp)
80100c01: e8 3a 5d 00 00 call 80106940 <freevm>
if(ip){
iunlockput(ip);
end_op();
}
return -1;
80100c06: b8 ff ff ff ff mov $0xffffffff,%eax
80100c0b: e9 02 fe ff ff jmp 80100a12 <exec+0x72>
struct proc *curproc = myproc();
begin_op();
if((ip = namei(path)) == 0){
end_op();
80100c10: e8 5b 1f 00 00 call 80102b70 <end_op>
cprintf("exec: fail\n");
80100c15: c7 04 24 21 6e 10 80 movl $0x80106e21,(%esp)
80100c1c: e8 2f fa ff ff call 80100650 <cprintf>
return -1;
80100c21: b8 ff ff ff ff mov $0xffffffff,%eax
80100c26: e9 e7 fd ff ff jmp 80100a12 <exec+0x72>
80100c2b: 89 f2 mov %esi,%edx
sp = (sp - (strlen(argv[argc]) + 1)) & ~3;
if(copyout(pgdir, sp, argv[argc], strlen(argv[argc]) + 1) < 0)
goto bad;
ustack[3+argc] = sp;
}
ustack[3+argc] = 0;
80100c2d: c7 84 95 64 ff ff ff movl $0x0,-0x9c(%ebp,%edx,4)
80100c34: 00 00 00 00
ustack[0] = 0xffffffff; // fake return PC
ustack[1] = argc;
ustack[2] = sp - (argc+1)*4; // argv pointer
80100c38: 8d 04 95 04 00 00 00 lea 0x4(,%edx,4),%eax
ustack[3+argc] = sp;
}
ustack[3+argc] = 0;
ustack[0] = 0xffffffff; // fake return PC
ustack[1] = argc;
80100c3f: 89 95 5c ff ff ff mov %edx,-0xa4(%ebp)
ustack[2] = sp - (argc+1)*4; // argv pointer
80100c45: 89 da mov %ebx,%edx
80100c47: 29 c2 sub %eax,%edx
sp -= (3+argc+1) * 4;
80100c49: 83 c0 0c add $0xc,%eax
80100c4c: 29 c3 sub %eax,%ebx
if(copyout(pgdir, sp, ustack, (3+argc+1)*4) < 0)
80100c4e: 89 44 24 0c mov %eax,0xc(%esp)
80100c52: 8b 85 f0 fe ff ff mov -0x110(%ebp),%eax
80100c58: 89 4c 24 08 mov %ecx,0x8(%esp)
80100c5c: 89 5c 24 04 mov %ebx,0x4(%esp)
goto bad;
ustack[3+argc] = sp;
}
ustack[3+argc] = 0;
ustack[0] = 0xffffffff; // fake return PC
80100c60: c7 85 58 ff ff ff ff movl $0xffffffff,-0xa8(%ebp)
80100c67: ff ff ff
ustack[1] = argc;
ustack[2] = sp - (argc+1)*4; // argv pointer
sp -= (3+argc+1) * 4;
if(copyout(pgdir, sp, ustack, (3+argc+1)*4) < 0)
80100c6a: 89 04 24 mov %eax,(%esp)
}
ustack[3+argc] = 0;
ustack[0] = 0xffffffff; // fake return PC
ustack[1] = argc;
ustack[2] = sp - (argc+1)*4; // argv pointer
80100c6d: 89 95 60 ff ff ff mov %edx,-0xa0(%ebp)
sp -= (3+argc+1) * 4;
if(copyout(pgdir, sp, ustack, (3+argc+1)*4) < 0)
80100c73: e8 18 60 00 00 call 80106c90 <copyout>
80100c78: 85 c0 test %eax,%eax
80100c7a: 0f 88 78 ff ff ff js 80100bf8 <exec+0x258>
goto bad;
// Save program name for debugging.
for(last=s=path; *s; s++)
80100c80: 8b 45 08 mov 0x8(%ebp),%eax
80100c83: 0f b6 10 movzbl (%eax),%edx
80100c86: 84 d2 test %dl,%dl
80100c88: 74 19 je 80100ca3 <exec+0x303>
80100c8a: 8b 4d 08 mov 0x8(%ebp),%ecx
80100c8d: 83 c0 01 add $0x1,%eax
if(*s == '/')
last = s+1;
80100c90: 80 fa 2f cmp $0x2f,%dl
sp -= (3+argc+1) * 4;
if(copyout(pgdir, sp, ustack, (3+argc+1)*4) < 0)
goto bad;
// Save program name for debugging.
for(last=s=path; *s; s++)
80100c93: 0f b6 10 movzbl (%eax),%edx
if(*s == '/')
last = s+1;
80100c96: 0f 44 c8 cmove %eax,%ecx
80100c99: 83 c0 01 add $0x1,%eax
sp -= (3+argc+1) * 4;
if(copyout(pgdir, sp, ustack, (3+argc+1)*4) < 0)
goto bad;
// Save program name for debugging.
for(last=s=path; *s; s++)
80100c9c: 84 d2 test %dl,%dl
80100c9e: 75 f0 jne 80100c90 <exec+0x2f0>
80100ca0: 89 4d 08 mov %ecx,0x8(%ebp)
if(*s == '/')
last = s+1;
safestrcpy(curproc->name, last, sizeof(curproc->name));
80100ca3: 8b bd f4 fe ff ff mov -0x10c(%ebp),%edi
80100ca9: 8b 45 08 mov 0x8(%ebp),%eax
80100cac: c7 44 24 08 10 00 00 movl $0x10,0x8(%esp)
80100cb3: 00
80100cb4: 89 44 24 04 mov %eax,0x4(%esp)
80100cb8: 89 f8 mov %edi,%eax
80100cba: 83 c0 70 add $0x70,%eax
80100cbd: 89 04 24 mov %eax,(%esp)
80100cc0: e8 8b 37 00 00 call 80104450 <safestrcpy>
end_op();
ip = 0;
// Allocate two pages at the next page boundary.
// Make the first inaccessible. Use the second as the user stack.
sz = PGROUNDUP(sz);
80100cc5: 8b 85 ec fe ff ff mov -0x114(%ebp),%eax
last = s+1;
safestrcpy(curproc->name, last, sizeof(curproc->name));
// Commit to the user image.
oldpgdir = curproc->pgdir;
curproc->pgdir = pgdir;
80100ccb: 8b 95 f0 fe ff ff mov -0x110(%ebp),%edx
if(*s == '/')
last = s+1;
safestrcpy(curproc->name, last, sizeof(curproc->name));
// Commit to the user image.
oldpgdir = curproc->pgdir;
80100cd1: 8b 77 08 mov 0x8(%edi),%esi
curproc->pgdir = pgdir;
curproc->sz = sz;
curproc->sb = sb;
80100cd4: c7 47 04 00 f0 ff 7f movl $0x7ffff000,0x4(%edi)
end_op();
ip = 0;
// Allocate two pages at the next page boundary.
// Make the first inaccessible. Use the second as the user stack.
sz = PGROUNDUP(sz);
80100cdb: 05 ff 0f 00 00 add $0xfff,%eax
80100ce0: 25 00 f0 ff ff and $0xfffff000,%eax
80100ce5: 89 07 mov %eax,(%edi)
// Commit to the user image.
oldpgdir = curproc->pgdir;
curproc->pgdir = pgdir;
curproc->sz = sz;
curproc->sb = sb;
curproc->tf->eip = elf.entry; // main
80100ce7: 8b 47 1c mov 0x1c(%edi),%eax
last = s+1;
safestrcpy(curproc->name, last, sizeof(curproc->name));
// Commit to the user image.
oldpgdir = curproc->pgdir;
curproc->pgdir = pgdir;
80100cea: 89 57 08 mov %edx,0x8(%edi)
curproc->sz = sz;
curproc->sb = sb;
curproc->tf->eip = elf.entry; // main
80100ced: 8b 95 3c ff ff ff mov -0xc4(%ebp),%edx
80100cf3: 89 50 38 mov %edx,0x38(%eax)
curproc->tf->esp = sp;
80100cf6: 8b 47 1c mov 0x1c(%edi),%eax
80100cf9: 89 58 44 mov %ebx,0x44(%eax)
switchuvm(curproc);
80100cfc: 89 3c 24 mov %edi,(%esp)
80100cff: e8 bc 58 00 00 call 801065c0 <switchuvm>
freevm(oldpgdir);
80100d04: 89 34 24 mov %esi,(%esp)
80100d07: e8 34 5c 00 00 call 80106940 <freevm>
return 0;
80100d0c: 31 c0 xor %eax,%eax
80100d0e: e9 ff fc ff ff jmp 80100a12 <exec+0x72>
//clearpteu(pgdir, (char*)(sz - 2*PGSIZE));
sp = KERNBASE - 4;
sb = KERNBASE - PGSIZE;
// Push argument strings, prepare rest of stack in ustack.
for(argc = 0; argv[argc]; argc++) {
80100d13: bb fc ff ff 7f mov $0x7ffffffc,%ebx
80100d18: 31 d2 xor %edx,%edx
80100d1a: 8d 8d 58 ff ff ff lea -0xa8(%ebp),%ecx
80100d20: e9 08 ff ff ff jmp 80100c2d <exec+0x28d>
80100d25: 66 90 xchg %ax,%ax
80100d27: 66 90 xchg %ax,%ax
80100d29: 66 90 xchg %ax,%ax
80100d2b: 66 90 xchg %ax,%ax
80100d2d: 66 90 xchg %ax,%ax
80100d2f: 90 nop
80100d30 <fileinit>:
struct file file[NFILE];
} ftable;
void
fileinit(void)
{
80100d30: 55 push %ebp
80100d31: 89 e5 mov %esp,%ebp
80100d33: 83 ec 18 sub $0x18,%esp
initlock(&ftable.lock, "ftable");
80100d36: c7 44 24 04 2d 6e 10 movl $0x80106e2d,0x4(%esp)
80100d3d: 80
80100d3e: c7 04 24 c0 ff 10 80 movl $0x8010ffc0,(%esp)
80100d45: e8 f6 32 00 00 call 80104040 <initlock>
}
80100d4a: c9 leave
80100d4b: c3 ret
80100d4c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80100d50 <filealloc>:
// Allocate a file structure.
struct file*
filealloc(void)
{
80100d50: 55 push %ebp
80100d51: 89 e5 mov %esp,%ebp
80100d53: 53 push %ebx
struct file *f;
acquire(&ftable.lock);
for(f = ftable.file; f < ftable.file + NFILE; f++){
80100d54: bb f4 ff 10 80 mov $0x8010fff4,%ebx
}
// Allocate a file structure.
struct file*
filealloc(void)
{
80100d59: 83 ec 14 sub $0x14,%esp
struct file *f;
acquire(&ftable.lock);
80100d5c: c7 04 24 c0 ff 10 80 movl $0x8010ffc0,(%esp)
80100d63: e8 c8 33 00 00 call 80104130 <acquire>
80100d68: eb 11 jmp 80100d7b <filealloc+0x2b>
80100d6a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
for(f = ftable.file; f < ftable.file + NFILE; f++){
80100d70: 83 c3 18 add $0x18,%ebx
80100d73: 81 fb 54 09 11 80 cmp $0x80110954,%ebx
80100d79: 74 25 je 80100da0 <filealloc+0x50>
if(f->ref == 0){
80100d7b: 8b 43 04 mov 0x4(%ebx),%eax
80100d7e: 85 c0 test %eax,%eax
80100d80: 75 ee jne 80100d70 <filealloc+0x20>
f->ref = 1;
release(&ftable.lock);
80100d82: c7 04 24 c0 ff 10 80 movl $0x8010ffc0,(%esp)
struct file *f;
acquire(&ftable.lock);
for(f = ftable.file; f < ftable.file + NFILE; f++){
if(f->ref == 0){
f->ref = 1;
80100d89: c7 43 04 01 00 00 00 movl $0x1,0x4(%ebx)
release(&ftable.lock);
80100d90: e8 8b 34 00 00 call 80104220 <release>
return f;
}
}
release(&ftable.lock);
return 0;
}
80100d95: 83 c4 14 add $0x14,%esp
acquire(&ftable.lock);
for(f = ftable.file; f < ftable.file + NFILE; f++){
if(f->ref == 0){
f->ref = 1;
release(&ftable.lock);
return f;
80100d98: 89 d8 mov %ebx,%eax
}
}
release(&ftable.lock);
return 0;
}
80100d9a: 5b pop %ebx
80100d9b: 5d pop %ebp
80100d9c: c3 ret
80100d9d: 8d 76 00 lea 0x0(%esi),%esi
f->ref = 1;
release(&ftable.lock);
return f;
}
}
release(&ftable.lock);
80100da0: c7 04 24 c0 ff 10 80 movl $0x8010ffc0,(%esp)
80100da7: e8 74 34 00 00 call 80104220 <release>
return 0;
}
80100dac: 83 c4 14 add $0x14,%esp
release(&ftable.lock);
return f;
}
}
release(&ftable.lock);
return 0;
80100daf: 31 c0 xor %eax,%eax
}
80100db1: 5b pop %ebx
80100db2: 5d pop %ebp
80100db3: c3 ret
80100db4: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80100dba: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
80100dc0 <filedup>:
// Increment ref count for file f.
struct file*
filedup(struct file *f)
{
80100dc0: 55 push %ebp
80100dc1: 89 e5 mov %esp,%ebp
80100dc3: 53 push %ebx
80100dc4: 83 ec 14 sub $0x14,%esp
80100dc7: 8b 5d 08 mov 0x8(%ebp),%ebx
acquire(&ftable.lock);
80100dca: c7 04 24 c0 ff 10 80 movl $0x8010ffc0,(%esp)
80100dd1: e8 5a 33 00 00 call 80104130 <acquire>
if(f->ref < 1)
80100dd6: 8b 43 04 mov 0x4(%ebx),%eax
80100dd9: 85 c0 test %eax,%eax
80100ddb: 7e 1a jle 80100df7 <filedup+0x37>
panic("filedup");
f->ref++;
80100ddd: 83 c0 01 add $0x1,%eax
80100de0: 89 43 04 mov %eax,0x4(%ebx)
release(&ftable.lock);
80100de3: c7 04 24 c0 ff 10 80 movl $0x8010ffc0,(%esp)
80100dea: e8 31 34 00 00 call 80104220 <release>
return f;
}
80100def: 83 c4 14 add $0x14,%esp
80100df2: 89 d8 mov %ebx,%eax
80100df4: 5b pop %ebx
80100df5: 5d pop %ebp
80100df6: c3 ret
struct file*
filedup(struct file *f)
{
acquire(&ftable.lock);
if(f->ref < 1)
panic("filedup");
80100df7: c7 04 24 34 6e 10 80 movl $0x80106e34,(%esp)
80100dfe: e8 5d f5 ff ff call 80100360 <panic>
80100e03: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80100e09: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80100e10 <fileclose>:
}
// Close file f. (Decrement ref count, close when reaches 0.)
void
fileclose(struct file *f)
{
80100e10: 55 push %ebp
80100e11: 89 e5 mov %esp,%ebp
80100e13: 57 push %edi
80100e14: 56 push %esi
80100e15: 53 push %ebx
80100e16: 83 ec 1c sub $0x1c,%esp
80100e19: 8b 7d 08 mov 0x8(%ebp),%edi
struct file ff;
acquire(&ftable.lock);
80100e1c: c7 04 24 c0 ff 10 80 movl $0x8010ffc0,(%esp)
80100e23: e8 08 33 00 00 call 80104130 <acquire>
if(f->ref < 1)
80100e28: 8b 57 04 mov 0x4(%edi),%edx
80100e2b: 85 d2 test %edx,%edx
80100e2d: 0f 8e 89 00 00 00 jle 80100ebc <fileclose+0xac>
panic("fileclose");
if(--f->ref > 0){
80100e33: 83 ea 01 sub $0x1,%edx
80100e36: 85 d2 test %edx,%edx
80100e38: 89 57 04 mov %edx,0x4(%edi)
80100e3b: 74 13 je 80100e50 <fileclose+0x40>
release(&ftable.lock);
80100e3d: c7 45 08 c0 ff 10 80 movl $0x8010ffc0,0x8(%ebp)
else if(ff.type == FD_INODE){
begin_op();
iput(ff.ip);
end_op();
}
}
80100e44: 83 c4 1c add $0x1c,%esp
80100e47: 5b pop %ebx
80100e48: 5e pop %esi
80100e49: 5f pop %edi
80100e4a: 5d pop %ebp
acquire(&ftable.lock);
if(f->ref < 1)
panic("fileclose");
if(--f->ref > 0){
release(&ftable.lock);
80100e4b: e9 d0 33 00 00 jmp 80104220 <release>
return;
}
ff = *f;
80100e50: 0f b6 47 09 movzbl 0x9(%edi),%eax
80100e54: 8b 37 mov (%edi),%esi
80100e56: 8b 5f 0c mov 0xc(%edi),%ebx
f->ref = 0;
f->type = FD_NONE;
80100e59: c7 07 00 00 00 00 movl $0x0,(%edi)
panic("fileclose");
if(--f->ref > 0){
release(&ftable.lock);
return;
}
ff = *f;
80100e5f: 88 45 e7 mov %al,-0x19(%ebp)
80100e62: 8b 47 10 mov 0x10(%edi),%eax
f->ref = 0;
f->type = FD_NONE;
release(&ftable.lock);
80100e65: c7 04 24 c0 ff 10 80 movl $0x8010ffc0,(%esp)
panic("fileclose");
if(--f->ref > 0){
release(&ftable.lock);
return;
}
ff = *f;
80100e6c: 89 45 e0 mov %eax,-0x20(%ebp)
f->ref = 0;
f->type = FD_NONE;
release(&ftable.lock);
80100e6f: e8 ac 33 00 00 call 80104220 <release>
if(ff.type == FD_PIPE)
80100e74: 83 fe 01 cmp $0x1,%esi
80100e77: 74 0f je 80100e88 <fileclose+0x78>
pipeclose(ff.pipe, ff.writable);
else if(ff.type == FD_INODE){
80100e79: 83 fe 02 cmp $0x2,%esi
80100e7c: 74 22 je 80100ea0 <fileclose+0x90>
begin_op();
iput(ff.ip);
end_op();
}
}
80100e7e: 83 c4 1c add $0x1c,%esp
80100e81: 5b pop %ebx
80100e82: 5e pop %esi
80100e83: 5f pop %edi
80100e84: 5d pop %ebp
80100e85: c3 ret
80100e86: 66 90 xchg %ax,%ax
f->ref = 0;
f->type = FD_NONE;
release(&ftable.lock);
if(ff.type == FD_PIPE)
pipeclose(ff.pipe, ff.writable);
80100e88: 0f be 75 e7 movsbl -0x19(%ebp),%esi
80100e8c: 89 1c 24 mov %ebx,(%esp)
80100e8f: 89 74 24 04 mov %esi,0x4(%esp)
80100e93: e8 b8 23 00 00 call 80103250 <pipeclose>
80100e98: eb e4 jmp 80100e7e <fileclose+0x6e>
80100e9a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
else if(ff.type == FD_INODE){
begin_op();
80100ea0: e8 5b 1c 00 00 call 80102b00 <begin_op>
iput(ff.ip);
80100ea5: 8b 45 e0 mov -0x20(%ebp),%eax
80100ea8: 89 04 24 mov %eax,(%esp)
80100eab: e8 10 09 00 00 call 801017c0 <iput>
end_op();
}
}
80100eb0: 83 c4 1c add $0x1c,%esp
80100eb3: 5b pop %ebx
80100eb4: 5e pop %esi
80100eb5: 5f pop %edi
80100eb6: 5d pop %ebp
if(ff.type == FD_PIPE)
pipeclose(ff.pipe, ff.writable);
else if(ff.type == FD_INODE){
begin_op();
iput(ff.ip);
end_op();
80100eb7: e9 b4 1c 00 00 jmp 80102b70 <end_op>
{
struct file ff;
acquire(&ftable.lock);
if(f->ref < 1)
panic("fileclose");
80100ebc: c7 04 24 3c 6e 10 80 movl $0x80106e3c,(%esp)
80100ec3: e8 98 f4 ff ff call 80100360 <panic>
80100ec8: 90 nop
80100ec9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80100ed0 <filestat>:
}
// Get metadata about file f.
int
filestat(struct file *f, struct stat *st)
{
80100ed0: 55 push %ebp
80100ed1: 89 e5 mov %esp,%ebp
80100ed3: 53 push %ebx
80100ed4: 83 ec 14 sub $0x14,%esp
80100ed7: 8b 5d 08 mov 0x8(%ebp),%ebx
if(f->type == FD_INODE){
80100eda: 83 3b 02 cmpl $0x2,(%ebx)
80100edd: 75 31 jne 80100f10 <filestat+0x40>
ilock(f->ip);
80100edf: 8b 43 10 mov 0x10(%ebx),%eax
80100ee2: 89 04 24 mov %eax,(%esp)
80100ee5: e8 b6 07 00 00 call 801016a0 <ilock>
stati(f->ip, st);
80100eea: 8b 45 0c mov 0xc(%ebp),%eax
80100eed: 89 44 24 04 mov %eax,0x4(%esp)
80100ef1: 8b 43 10 mov 0x10(%ebx),%eax
80100ef4: 89 04 24 mov %eax,(%esp)
80100ef7: e8 24 0a 00 00 call 80101920 <stati>
iunlock(f->ip);
80100efc: 8b 43 10 mov 0x10(%ebx),%eax
80100eff: 89 04 24 mov %eax,(%esp)
80100f02: e8 79 08 00 00 call 80101780 <iunlock>
return 0;
}
return -1;
}
80100f07: 83 c4 14 add $0x14,%esp
{
if(f->type == FD_INODE){
ilock(f->ip);
stati(f->ip, st);
iunlock(f->ip);
return 0;
80100f0a: 31 c0 xor %eax,%eax
}
return -1;
}
80100f0c: 5b pop %ebx
80100f0d: 5d pop %ebp
80100f0e: c3 ret
80100f0f: 90 nop
80100f10: 83 c4 14 add $0x14,%esp
ilock(f->ip);
stati(f->ip, st);
iunlock(f->ip);
return 0;
}
return -1;
80100f13: b8 ff ff ff ff mov $0xffffffff,%eax
}
80100f18: 5b pop %ebx
80100f19: 5d pop %ebp
80100f1a: c3 ret
80100f1b: 90 nop
80100f1c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80100f20 <fileread>:
// Read from file f.
int
fileread(struct file *f, char *addr, int n)
{
80100f20: 55 push %ebp
80100f21: 89 e5 mov %esp,%ebp
80100f23: 57 push %edi
80100f24: 56 push %esi
80100f25: 53 push %ebx
80100f26: 83 ec 1c sub $0x1c,%esp
80100f29: 8b 5d 08 mov 0x8(%ebp),%ebx
80100f2c: 8b 75 0c mov 0xc(%ebp),%esi
80100f2f: 8b 7d 10 mov 0x10(%ebp),%edi
int r;
if(f->readable == 0)
80100f32: 80 7b 08 00 cmpb $0x0,0x8(%ebx)
80100f36: 74 68 je 80100fa0 <fileread+0x80>
return -1;
if(f->type == FD_PIPE)
80100f38: 8b 03 mov (%ebx),%eax
80100f3a: 83 f8 01 cmp $0x1,%eax
80100f3d: 74 49 je 80100f88 <fileread+0x68>
return piperead(f->pipe, addr, n);
if(f->type == FD_INODE){
80100f3f: 83 f8 02 cmp $0x2,%eax
80100f42: 75 63 jne 80100fa7 <fileread+0x87>
ilock(f->ip);
80100f44: 8b 43 10 mov 0x10(%ebx),%eax
80100f47: 89 04 24 mov %eax,(%esp)
80100f4a: e8 51 07 00 00 call 801016a0 <ilock>
if((r = readi(f->ip, addr, f->off, n)) > 0)
80100f4f: 89 7c 24 0c mov %edi,0xc(%esp)
80100f53: 8b 43 14 mov 0x14(%ebx),%eax
80100f56: 89 74 24 04 mov %esi,0x4(%esp)
80100f5a: 89 44 24 08 mov %eax,0x8(%esp)
80100f5e: 8b 43 10 mov 0x10(%ebx),%eax
80100f61: 89 04 24 mov %eax,(%esp)
80100f64: e8 e7 09 00 00 call 80101950 <readi>
80100f69: 85 c0 test %eax,%eax
80100f6b: 89 c6 mov %eax,%esi
80100f6d: 7e 03 jle 80100f72 <fileread+0x52>
f->off += r;
80100f6f: 01 43 14 add %eax,0x14(%ebx)
iunlock(f->ip);
80100f72: 8b 43 10 mov 0x10(%ebx),%eax
80100f75: 89 04 24 mov %eax,(%esp)
80100f78: e8 03 08 00 00 call 80101780 <iunlock>
return -1;
if(f->type == FD_PIPE)
return piperead(f->pipe, addr, n);
if(f->type == FD_INODE){
ilock(f->ip);
if((r = readi(f->ip, addr, f->off, n)) > 0)
80100f7d: 89 f0 mov %esi,%eax
f->off += r;
iunlock(f->ip);
return r;
}
panic("fileread");
}
80100f7f: 83 c4 1c add $0x1c,%esp
80100f82: 5b pop %ebx
80100f83: 5e pop %esi
80100f84: 5f pop %edi
80100f85: 5d pop %ebp
80100f86: c3 ret
80100f87: 90 nop
int r;
if(f->readable == 0)
return -1;
if(f->type == FD_PIPE)
return piperead(f->pipe, addr, n);
80100f88: 8b 43 0c mov 0xc(%ebx),%eax
80100f8b: 89 45 08 mov %eax,0x8(%ebp)
f->off += r;
iunlock(f->ip);
return r;
}
panic("fileread");
}
80100f8e: 83 c4 1c add $0x1c,%esp
80100f91: 5b pop %ebx
80100f92: 5e pop %esi
80100f93: 5f pop %edi
80100f94: 5d pop %ebp
int r;
if(f->readable == 0)
return -1;
if(f->type == FD_PIPE)
return piperead(f->pipe, addr, n);
80100f95: e9 36 24 00 00 jmp 801033d0 <piperead>
80100f9a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
fileread(struct file *f, char *addr, int n)
{
int r;
if(f->readable == 0)
return -1;
80100fa0: b8 ff ff ff ff mov $0xffffffff,%eax
80100fa5: eb d8 jmp 80100f7f <fileread+0x5f>
if((r = readi(f->ip, addr, f->off, n)) > 0)
f->off += r;
iunlock(f->ip);
return r;
}
panic("fileread");
80100fa7: c7 04 24 46 6e 10 80 movl $0x80106e46,(%esp)
80100fae: e8 ad f3 ff ff call 80100360 <panic>
80100fb3: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80100fb9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80100fc0 <filewrite>:
//PAGEBREAK!
// Write to file f.
int
filewrite(struct file *f, char *addr, int n)
{
80100fc0: 55 push %ebp
80100fc1: 89 e5 mov %esp,%ebp
80100fc3: 57 push %edi
80100fc4: 56 push %esi
80100fc5: 53 push %ebx
80100fc6: 83 ec 2c sub $0x2c,%esp
80100fc9: 8b 45 0c mov 0xc(%ebp),%eax
80100fcc: 8b 7d 08 mov 0x8(%ebp),%edi
80100fcf: 89 45 dc mov %eax,-0x24(%ebp)
80100fd2: 8b 45 10 mov 0x10(%ebp),%eax
int r;
if(f->writable == 0)
80100fd5: 80 7f 09 00 cmpb $0x0,0x9(%edi)
//PAGEBREAK!
// Write to file f.
int
filewrite(struct file *f, char *addr, int n)
{
80100fd9: 89 45 e4 mov %eax,-0x1c(%ebp)
int r;
if(f->writable == 0)
80100fdc: 0f 84 ae 00 00 00 je 80101090 <filewrite+0xd0>
return -1;
if(f->type == FD_PIPE)
80100fe2: 8b 07 mov (%edi),%eax
80100fe4: 83 f8 01 cmp $0x1,%eax
80100fe7: 0f 84 c2 00 00 00 je 801010af <filewrite+0xef>
return pipewrite(f->pipe, addr, n);
if(f->type == FD_INODE){
80100fed: 83 f8 02 cmp $0x2,%eax
80100ff0: 0f 85 d7 00 00 00 jne 801010cd <filewrite+0x10d>
// and 2 blocks of slop for non-aligned writes.
// this really belongs lower down, since writei()
// might be writing a device like the console.
int max = ((LOGSIZE-1-1-2) / 2) * 512;
int i = 0;
while(i < n){
80100ff6: 8b 45 e4 mov -0x1c(%ebp),%eax
80100ff9: 31 db xor %ebx,%ebx
80100ffb: 85 c0 test %eax,%eax
80100ffd: 7f 31 jg 80101030 <filewrite+0x70>
80100fff: e9 9c 00 00 00 jmp 801010a0 <filewrite+0xe0>
80101004: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
begin_op();
ilock(f->ip);
if ((r = writei(f->ip, addr + i, f->off, n1)) > 0)
f->off += r;
iunlock(f->ip);
80101008: 8b 4f 10 mov 0x10(%edi),%ecx
n1 = max;
begin_op();
ilock(f->ip);
if ((r = writei(f->ip, addr + i, f->off, n1)) > 0)
f->off += r;
8010100b: 01 47 14 add %eax,0x14(%edi)
8010100e: 89 45 e0 mov %eax,-0x20(%ebp)
iunlock(f->ip);
80101011: 89 0c 24 mov %ecx,(%esp)
80101014: e8 67 07 00 00 call 80101780 <iunlock>
end_op();
80101019: e8 52 1b 00 00 call 80102b70 <end_op>
8010101e: 8b 45 e0 mov -0x20(%ebp),%eax
if(r < 0)
break;
if(r != n1)
80101021: 39 f0 cmp %esi,%eax
80101023: 0f 85 98 00 00 00 jne 801010c1 <filewrite+0x101>
panic("short filewrite");
i += r;
80101029: 01 c3 add %eax,%ebx
// and 2 blocks of slop for non-aligned writes.
// this really belongs lower down, since writei()
// might be writing a device like the console.
int max = ((LOGSIZE-1-1-2) / 2) * 512;
int i = 0;
while(i < n){
8010102b: 39 5d e4 cmp %ebx,-0x1c(%ebp)
8010102e: 7e 70 jle 801010a0 <filewrite+0xe0>
int n1 = n - i;
80101030: 8b 75 e4 mov -0x1c(%ebp),%esi
80101033: b8 00 1a 00 00 mov $0x1a00,%eax
80101038: 29 de sub %ebx,%esi
8010103a: 81 fe 00 1a 00 00 cmp $0x1a00,%esi
80101040: 0f 4f f0 cmovg %eax,%esi
if(n1 > max)
n1 = max;
begin_op();
80101043: e8 b8 1a 00 00 call 80102b00 <begin_op>
ilock(f->ip);
80101048: 8b 47 10 mov 0x10(%edi),%eax
8010104b: 89 04 24 mov %eax,(%esp)
8010104e: e8 4d 06 00 00 call 801016a0 <ilock>
if ((r = writei(f->ip, addr + i, f->off, n1)) > 0)
80101053: 89 74 24 0c mov %esi,0xc(%esp)
80101057: 8b 47 14 mov 0x14(%edi),%eax
8010105a: 89 44 24 08 mov %eax,0x8(%esp)
8010105e: 8b 45 dc mov -0x24(%ebp),%eax
80101061: 01 d8 add %ebx,%eax
80101063: 89 44 24 04 mov %eax,0x4(%esp)
80101067: 8b 47 10 mov 0x10(%edi),%eax
8010106a: 89 04 24 mov %eax,(%esp)
8010106d: e8 de 09 00 00 call 80101a50 <writei>
80101072: 85 c0 test %eax,%eax
80101074: 7f 92 jg 80101008 <filewrite+0x48>
f->off += r;
iunlock(f->ip);
80101076: 8b 4f 10 mov 0x10(%edi),%ecx
80101079: 89 45 e0 mov %eax,-0x20(%ebp)
8010107c: 89 0c 24 mov %ecx,(%esp)
8010107f: e8 fc 06 00 00 call 80101780 <iunlock>
end_op();
80101084: e8 e7 1a 00 00 call 80102b70 <end_op>
if(r < 0)
80101089: 8b 45 e0 mov -0x20(%ebp),%eax
8010108c: 85 c0 test %eax,%eax
8010108e: 74 91 je 80101021 <filewrite+0x61>
i += r;
}
return i == n ? n : -1;
}
panic("filewrite");
}
80101090: 83 c4 2c add $0x2c,%esp
filewrite(struct file *f, char *addr, int n)
{
int r;
if(f->writable == 0)
return -1;
80101093: b8 ff ff ff ff mov $0xffffffff,%eax
i += r;
}
return i == n ? n : -1;
}
panic("filewrite");
}
80101098: 5b pop %ebx
80101099: 5e pop %esi
8010109a: 5f pop %edi
8010109b: 5d pop %ebp
8010109c: c3 ret
8010109d: 8d 76 00 lea 0x0(%esi),%esi
break;
if(r != n1)
panic("short filewrite");
i += r;
}
return i == n ? n : -1;
801010a0: 3b 5d e4 cmp -0x1c(%ebp),%ebx
801010a3: 89 d8 mov %ebx,%eax
801010a5: 75 e9 jne 80101090 <filewrite+0xd0>
}
panic("filewrite");
}
801010a7: 83 c4 2c add $0x2c,%esp
801010aa: 5b pop %ebx
801010ab: 5e pop %esi
801010ac: 5f pop %edi
801010ad: 5d pop %ebp
801010ae: c3 ret
int r;
if(f->writable == 0)
return -1;
if(f->type == FD_PIPE)
return pipewrite(f->pipe, addr, n);
801010af: 8b 47 0c mov 0xc(%edi),%eax
801010b2: 89 45 08 mov %eax,0x8(%ebp)
i += r;
}
return i == n ? n : -1;
}
panic("filewrite");
}
801010b5: 83 c4 2c add $0x2c,%esp
801010b8: 5b pop %ebx
801010b9: 5e pop %esi
801010ba: 5f pop %edi
801010bb: 5d pop %ebp
int r;
if(f->writable == 0)
return -1;
if(f->type == FD_PIPE)
return pipewrite(f->pipe, addr, n);
801010bc: e9 1f 22 00 00 jmp 801032e0 <pipewrite>
end_op();
if(r < 0)
break;
if(r != n1)
panic("short filewrite");
801010c1: c7 04 24 4f 6e 10 80 movl $0x80106e4f,(%esp)
801010c8: e8 93 f2 ff ff call 80100360 <panic>
i += r;
}
return i == n ? n : -1;
}
panic("filewrite");
801010cd: c7 04 24 55 6e 10 80 movl $0x80106e55,(%esp)
801010d4: e8 87 f2 ff ff call 80100360 <panic>
801010d9: 66 90 xchg %ax,%ax
801010db: 66 90 xchg %ax,%ax
801010dd: 66 90 xchg %ax,%ax
801010df: 90 nop
801010e0 <balloc>:
// Blocks.
// Allocate a zeroed disk block.
static uint
balloc(uint dev)
{
801010e0: 55 push %ebp
801010e1: 89 e5 mov %esp,%ebp
801010e3: 57 push %edi
801010e4: 56 push %esi
801010e5: 53 push %ebx
801010e6: 83 ec 2c sub $0x2c,%esp
801010e9: 89 45 d8 mov %eax,-0x28(%ebp)
int b, bi, m;
struct buf *bp;
bp = 0;
for(b = 0; b < sb.size; b += BPB){
801010ec: a1 c0 09 11 80 mov 0x801109c0,%eax
801010f1: 85 c0 test %eax,%eax
801010f3: 0f 84 8c 00 00 00 je 80101185 <balloc+0xa5>
801010f9: c7 45 dc 00 00 00 00 movl $0x0,-0x24(%ebp)
bp = bread(dev, BBLOCK(b, sb));
80101100: 8b 75 dc mov -0x24(%ebp),%esi
80101103: 89 f0 mov %esi,%eax
80101105: c1 f8 0c sar $0xc,%eax
80101108: 03 05 d8 09 11 80 add 0x801109d8,%eax
8010110e: 89 44 24 04 mov %eax,0x4(%esp)
80101112: 8b 45 d8 mov -0x28(%ebp),%eax
80101115: 89 04 24 mov %eax,(%esp)
80101118: e8 b3 ef ff ff call 801000d0 <bread>
8010111d: 89 45 e4 mov %eax,-0x1c(%ebp)
80101120: a1 c0 09 11 80 mov 0x801109c0,%eax
80101125: 89 45 e0 mov %eax,-0x20(%ebp)
for(bi = 0; bi < BPB && b + bi < sb.size; bi++){
80101128: 31 c0 xor %eax,%eax
8010112a: eb 33 jmp 8010115f <balloc+0x7f>
8010112c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
m = 1 << (bi % 8);
if((bp->data[bi/8] & m) == 0){ // Is block free?
80101130: 8b 5d e4 mov -0x1c(%ebp),%ebx
80101133: 89 c2 mov %eax,%edx
bp = 0;
for(b = 0; b < sb.size; b += BPB){
bp = bread(dev, BBLOCK(b, sb));
for(bi = 0; bi < BPB && b + bi < sb.size; bi++){
m = 1 << (bi % 8);
80101135: 89 c1 mov %eax,%ecx
if((bp->data[bi/8] & m) == 0){ // Is block free?
80101137: c1 fa 03 sar $0x3,%edx
bp = 0;
for(b = 0; b < sb.size; b += BPB){
bp = bread(dev, BBLOCK(b, sb));
for(bi = 0; bi < BPB && b + bi < sb.size; bi++){
m = 1 << (bi % 8);
8010113a: 83 e1 07 and $0x7,%ecx
8010113d: bf 01 00 00 00 mov $0x1,%edi
80101142: d3 e7 shl %cl,%edi
if((bp->data[bi/8] & m) == 0){ // Is block free?
80101144: 0f b6 5c 13 5c movzbl 0x5c(%ebx,%edx,1),%ebx
bp = 0;
for(b = 0; b < sb.size; b += BPB){
bp = bread(dev, BBLOCK(b, sb));
for(bi = 0; bi < BPB && b + bi < sb.size; bi++){
m = 1 << (bi % 8);
80101149: 89 f9 mov %edi,%ecx
if((bp->data[bi/8] & m) == 0){ // Is block free?
8010114b: 0f b6 fb movzbl %bl,%edi
8010114e: 85 cf test %ecx,%edi
80101150: 74 46 je 80101198 <balloc+0xb8>
struct buf *bp;
bp = 0;
for(b = 0; b < sb.size; b += BPB){
bp = bread(dev, BBLOCK(b, sb));
for(bi = 0; bi < BPB && b + bi < sb.size; bi++){
80101152: 83 c0 01 add $0x1,%eax
80101155: 83 c6 01 add $0x1,%esi
80101158: 3d 00 10 00 00 cmp $0x1000,%eax
8010115d: 74 05 je 80101164 <balloc+0x84>
8010115f: 3b 75 e0 cmp -0x20(%ebp),%esi
80101162: 72 cc jb 80101130 <balloc+0x50>
brelse(bp);
bzero(dev, b + bi);
return b + bi;
}
}
brelse(bp);
80101164: 8b 45 e4 mov -0x1c(%ebp),%eax
80101167: 89 04 24 mov %eax,(%esp)
8010116a: e8 71 f0 ff ff call 801001e0 <brelse>
{
int b, bi, m;
struct buf *bp;
bp = 0;
for(b = 0; b < sb.size; b += BPB){
8010116f: 81 45 dc 00 10 00 00 addl $0x1000,-0x24(%ebp)
80101176: 8b 45 dc mov -0x24(%ebp),%eax
80101179: 3b 05 c0 09 11 80 cmp 0x801109c0,%eax
8010117f: 0f 82 7b ff ff ff jb 80101100 <balloc+0x20>
return b + bi;
}
}
brelse(bp);
}
panic("balloc: out of blocks");
80101185: c7 04 24 5f 6e 10 80 movl $0x80106e5f,(%esp)
8010118c: e8 cf f1 ff ff call 80100360 <panic>
80101191: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
for(b = 0; b < sb.size; b += BPB){
bp = bread(dev, BBLOCK(b, sb));
for(bi = 0; bi < BPB && b + bi < sb.size; bi++){
m = 1 << (bi % 8);
if((bp->data[bi/8] & m) == 0){ // Is block free?
bp->data[bi/8] |= m; // Mark block in use.
80101198: 09 d9 or %ebx,%ecx
8010119a: 8b 5d e4 mov -0x1c(%ebp),%ebx
8010119d: 88 4c 13 5c mov %cl,0x5c(%ebx,%edx,1)
log_write(bp);
801011a1: 89 1c 24 mov %ebx,(%esp)
801011a4: e8 f7 1a 00 00 call 80102ca0 <log_write>
brelse(bp);
801011a9: 89 1c 24 mov %ebx,(%esp)
801011ac: e8 2f f0 ff ff call 801001e0 <brelse>
static void
bzero(int dev, int bno)
{
struct buf *bp;
bp = bread(dev, bno);
801011b1: 8b 45 d8 mov -0x28(%ebp),%eax
801011b4: 89 74 24 04 mov %esi,0x4(%esp)
801011b8: 89 04 24 mov %eax,(%esp)
801011bb: e8 10 ef ff ff call 801000d0 <bread>
memset(bp->data, 0, BSIZE);
801011c0: c7 44 24 08 00 02 00 movl $0x200,0x8(%esp)
801011c7: 00
801011c8: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
801011cf: 00
static void
bzero(int dev, int bno)
{
struct buf *bp;
bp = bread(dev, bno);
801011d0: 89 c3 mov %eax,%ebx
memset(bp->data, 0, BSIZE);
801011d2: 8d 40 5c lea 0x5c(%eax),%eax
801011d5: 89 04 24 mov %eax,(%esp)
801011d8: e8 93 30 00 00 call 80104270 <memset>
log_write(bp);
801011dd: 89 1c 24 mov %ebx,(%esp)
801011e0: e8 bb 1a 00 00 call 80102ca0 <log_write>
brelse(bp);
801011e5: 89 1c 24 mov %ebx,(%esp)
801011e8: e8 f3 ef ff ff call 801001e0 <brelse>
}
}
brelse(bp);
}
panic("balloc: out of blocks");
}
801011ed: 83 c4 2c add $0x2c,%esp
801011f0: 89 f0 mov %esi,%eax
801011f2: 5b pop %ebx
801011f3: 5e pop %esi
801011f4: 5f pop %edi
801011f5: 5d pop %ebp
801011f6: c3 ret
801011f7: 89 f6 mov %esi,%esi
801011f9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80101200 <iget>:
// Find the inode with number inum on device dev
// and return the in-memory copy. Does not lock
// the inode and does not read it from disk.
static struct inode*
iget(uint dev, uint inum)
{
80101200: 55 push %ebp
80101201: 89 e5 mov %esp,%ebp
80101203: 57 push %edi
80101204: 89 c7 mov %eax,%edi
80101206: 56 push %esi
struct inode *ip, *empty;
acquire(&icache.lock);
// Is the inode already cached?
empty = 0;
80101207: 31 f6 xor %esi,%esi
// Find the inode with number inum on device dev
// and return the in-memory copy. Does not lock
// the inode and does not read it from disk.
static struct inode*
iget(uint dev, uint inum)
{
80101209: 53 push %ebx
acquire(&icache.lock);
// Is the inode already cached?
empty = 0;
for(ip = &icache.inode[0]; ip < &icache.inode[NINODE]; ip++){
8010120a: bb 14 0a 11 80 mov $0x80110a14,%ebx
// Find the inode with number inum on device dev
// and return the in-memory copy. Does not lock
// the inode and does not read it from disk.
static struct inode*
iget(uint dev, uint inum)
{
8010120f: 83 ec 1c sub $0x1c,%esp
struct inode *ip, *empty;
acquire(&icache.lock);
80101212: c7 04 24 e0 09 11 80 movl $0x801109e0,(%esp)
// Find the inode with number inum on device dev
// and return the in-memory copy. Does not lock
// the inode and does not read it from disk.
static struct inode*
iget(uint dev, uint inum)
{
80101219: 89 55 e4 mov %edx,-0x1c(%ebp)
struct inode *ip, *empty;
acquire(&icache.lock);
8010121c: e8 0f 2f 00 00 call 80104130 <acquire>
// Is the inode already cached?
empty = 0;
for(ip = &icache.inode[0]; ip < &icache.inode[NINODE]; ip++){
80101221: 8b 55 e4 mov -0x1c(%ebp),%edx
80101224: eb 14 jmp 8010123a <iget+0x3a>
80101226: 66 90 xchg %ax,%ax
if(ip->ref > 0 && ip->dev == dev && ip->inum == inum){
ip->ref++;
release(&icache.lock);
return ip;
}
if(empty == 0 && ip->ref == 0) // Remember empty slot.
80101228: 85 f6 test %esi,%esi
8010122a: 74 3c je 80101268 <iget+0x68>
acquire(&icache.lock);
// Is the inode already cached?
empty = 0;
for(ip = &icache.inode[0]; ip < &icache.inode[NINODE]; ip++){
8010122c: 81 c3 90 00 00 00 add $0x90,%ebx
80101232: 81 fb 34 26 11 80 cmp $0x80112634,%ebx
80101238: 74 46 je 80101280 <iget+0x80>
if(ip->ref > 0 && ip->dev == dev && ip->inum == inum){
8010123a: 8b 4b 08 mov 0x8(%ebx),%ecx
8010123d: 85 c9 test %ecx,%ecx
8010123f: 7e e7 jle 80101228 <iget+0x28>
80101241: 39 3b cmp %edi,(%ebx)
80101243: 75 e3 jne 80101228 <iget+0x28>
80101245: 39 53 04 cmp %edx,0x4(%ebx)
80101248: 75 de jne 80101228 <iget+0x28>
ip->ref++;
8010124a: 83 c1 01 add $0x1,%ecx
release(&icache.lock);
return ip;
8010124d: 89 de mov %ebx,%esi
// Is the inode already cached?
empty = 0;
for(ip = &icache.inode[0]; ip < &icache.inode[NINODE]; ip++){
if(ip->ref > 0 && ip->dev == dev && ip->inum == inum){
ip->ref++;
release(&icache.lock);
8010124f: c7 04 24 e0 09 11 80 movl $0x801109e0,(%esp)
// Is the inode already cached?
empty = 0;
for(ip = &icache.inode[0]; ip < &icache.inode[NINODE]; ip++){
if(ip->ref > 0 && ip->dev == dev && ip->inum == inum){
ip->ref++;
80101256: 89 4b 08 mov %ecx,0x8(%ebx)
release(&icache.lock);
80101259: e8 c2 2f 00 00 call 80104220 <release>
ip->ref = 1;
ip->valid = 0;
release(&icache.lock);
return ip;
}
8010125e: 83 c4 1c add $0x1c,%esp
80101261: 89 f0 mov %esi,%eax
80101263: 5b pop %ebx
80101264: 5e pop %esi
80101265: 5f pop %edi
80101266: 5d pop %ebp
80101267: c3 ret
80101268: 85 c9 test %ecx,%ecx
8010126a: 0f 44 f3 cmove %ebx,%esi
acquire(&icache.lock);
// Is the inode already cached?
empty = 0;
for(ip = &icache.inode[0]; ip < &icache.inode[NINODE]; ip++){
8010126d: 81 c3 90 00 00 00 add $0x90,%ebx
80101273: 81 fb 34 26 11 80 cmp $0x80112634,%ebx
80101279: 75 bf jne 8010123a <iget+0x3a>
8010127b: 90 nop
8010127c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
if(empty == 0 && ip->ref == 0) // Remember empty slot.
empty = ip;
}
// Recycle an inode cache entry.
if(empty == 0)
80101280: 85 f6 test %esi,%esi
80101282: 74 29 je 801012ad <iget+0xad>
panic("iget: no inodes");
ip = empty;
ip->dev = dev;
80101284: 89 3e mov %edi,(%esi)
ip->inum = inum;
80101286: 89 56 04 mov %edx,0x4(%esi)
ip->ref = 1;
80101289: c7 46 08 01 00 00 00 movl $0x1,0x8(%esi)
ip->valid = 0;
80101290: c7 46 4c 00 00 00 00 movl $0x0,0x4c(%esi)
release(&icache.lock);
80101297: c7 04 24 e0 09 11 80 movl $0x801109e0,(%esp)
8010129e: e8 7d 2f 00 00 call 80104220 <release>
return ip;
}
801012a3: 83 c4 1c add $0x1c,%esp
801012a6: 89 f0 mov %esi,%eax
801012a8: 5b pop %ebx
801012a9: 5e pop %esi
801012aa: 5f pop %edi
801012ab: 5d pop %ebp
801012ac: c3 ret
empty = ip;
}
// Recycle an inode cache entry.
if(empty == 0)
panic("iget: no inodes");
801012ad: c7 04 24 75 6e 10 80 movl $0x80106e75,(%esp)
801012b4: e8 a7 f0 ff ff call 80100360 <panic>
801012b9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
801012c0 <bmap>:
// Return the disk block address of the nth block in inode ip.
// If there is no such block, bmap allocates one.
static uint
bmap(struct inode *ip, uint bn)
{
801012c0: 55 push %ebp
801012c1: 89 e5 mov %esp,%ebp
801012c3: 57 push %edi
801012c4: 56 push %esi
801012c5: 53 push %ebx
801012c6: 89 c3 mov %eax,%ebx
801012c8: 83 ec 1c sub $0x1c,%esp
uint addr, *a;
struct buf *bp;
if(bn < NDIRECT){
801012cb: 83 fa 0b cmp $0xb,%edx
801012ce: 77 18 ja 801012e8 <bmap+0x28>
801012d0: 8d 34 90 lea (%eax,%edx,4),%esi
if((addr = ip->addrs[bn]) == 0)
801012d3: 8b 46 5c mov 0x5c(%esi),%eax
801012d6: 85 c0 test %eax,%eax
801012d8: 74 66 je 80101340 <bmap+0x80>
brelse(bp);
return addr;
}
panic("bmap: out of range");
}
801012da: 83 c4 1c add $0x1c,%esp
801012dd: 5b pop %ebx
801012de: 5e pop %esi
801012df: 5f pop %edi
801012e0: 5d pop %ebp
801012e1: c3 ret
801012e2: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
if(bn < NDIRECT){
if((addr = ip->addrs[bn]) == 0)
ip->addrs[bn] = addr = balloc(ip->dev);
return addr;
}
bn -= NDIRECT;
801012e8: 8d 72 f4 lea -0xc(%edx),%esi
if(bn < NINDIRECT){
801012eb: 83 fe 7f cmp $0x7f,%esi
801012ee: 77 77 ja 80101367 <bmap+0xa7>
// Load indirect block, allocating if necessary.
if((addr = ip->addrs[NDIRECT]) == 0)
801012f0: 8b 80 8c 00 00 00 mov 0x8c(%eax),%eax
801012f6: 85 c0 test %eax,%eax
801012f8: 74 5e je 80101358 <bmap+0x98>
ip->addrs[NDIRECT] = addr = balloc(ip->dev);
bp = bread(ip->dev, addr);
801012fa: 89 44 24 04 mov %eax,0x4(%esp)
801012fe: 8b 03 mov (%ebx),%eax
80101300: 89 04 24 mov %eax,(%esp)
80101303: e8 c8 ed ff ff call 801000d0 <bread>
a = (uint*)bp->data;
if((addr = a[bn]) == 0){
80101308: 8d 54 b0 5c lea 0x5c(%eax,%esi,4),%edx
if(bn < NINDIRECT){
// Load indirect block, allocating if necessary.
if((addr = ip->addrs[NDIRECT]) == 0)
ip->addrs[NDIRECT] = addr = balloc(ip->dev);
bp = bread(ip->dev, addr);
8010130c: 89 c7 mov %eax,%edi
a = (uint*)bp->data;
if((addr = a[bn]) == 0){
8010130e: 8b 32 mov (%edx),%esi
80101310: 85 f6 test %esi,%esi
80101312: 75 19 jne 8010132d <bmap+0x6d>
a[bn] = addr = balloc(ip->dev);
80101314: 8b 03 mov (%ebx),%eax
80101316: 89 55 e4 mov %edx,-0x1c(%ebp)
80101319: e8 c2 fd ff ff call 801010e0 <balloc>
8010131e: 8b 55 e4 mov -0x1c(%ebp),%edx
80101321: 89 02 mov %eax,(%edx)
80101323: 89 c6 mov %eax,%esi
log_write(bp);
80101325: 89 3c 24 mov %edi,(%esp)
80101328: e8 73 19 00 00 call 80102ca0 <log_write>
}
brelse(bp);
8010132d: 89 3c 24 mov %edi,(%esp)
80101330: e8 ab ee ff ff call 801001e0 <brelse>
return addr;
}
panic("bmap: out of range");
}
80101335: 83 c4 1c add $0x1c,%esp
a = (uint*)bp->data;
if((addr = a[bn]) == 0){
a[bn] = addr = balloc(ip->dev);
log_write(bp);
}
brelse(bp);
80101338: 89 f0 mov %esi,%eax
return addr;
}
panic("bmap: out of range");
}
8010133a: 5b pop %ebx
8010133b: 5e pop %esi
8010133c: 5f pop %edi
8010133d: 5d pop %ebp
8010133e: c3 ret
8010133f: 90 nop
uint addr, *a;
struct buf *bp;
if(bn < NDIRECT){
if((addr = ip->addrs[bn]) == 0)
ip->addrs[bn] = addr = balloc(ip->dev);
80101340: 8b 03 mov (%ebx),%eax
80101342: e8 99 fd ff ff call 801010e0 <balloc>
80101347: 89 46 5c mov %eax,0x5c(%esi)
brelse(bp);
return addr;
}
panic("bmap: out of range");
}
8010134a: 83 c4 1c add $0x1c,%esp
8010134d: 5b pop %ebx
8010134e: 5e pop %esi
8010134f: 5f pop %edi
80101350: 5d pop %ebp
80101351: c3 ret
80101352: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
bn -= NDIRECT;
if(bn < NINDIRECT){
// Load indirect block, allocating if necessary.
if((addr = ip->addrs[NDIRECT]) == 0)
ip->addrs[NDIRECT] = addr = balloc(ip->dev);
80101358: 8b 03 mov (%ebx),%eax
8010135a: e8 81 fd ff ff call 801010e0 <balloc>
8010135f: 89 83 8c 00 00 00 mov %eax,0x8c(%ebx)
80101365: eb 93 jmp 801012fa <bmap+0x3a>
}
brelse(bp);
return addr;
}
panic("bmap: out of range");
80101367: c7 04 24 85 6e 10 80 movl $0x80106e85,(%esp)
8010136e: e8 ed ef ff ff call 80100360 <panic>
80101373: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80101379: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80101380 <readsb>:
struct superblock sb;
// Read the super block.
void
readsb(int dev, struct superblock *sb)
{
80101380: 55 push %ebp
80101381: 89 e5 mov %esp,%ebp
80101383: 56 push %esi
80101384: 53 push %ebx
80101385: 83 ec 10 sub $0x10,%esp
struct buf *bp;
bp = bread(dev, 1);
80101388: 8b 45 08 mov 0x8(%ebp),%eax
8010138b: c7 44 24 04 01 00 00 movl $0x1,0x4(%esp)
80101392: 00
struct superblock sb;
// Read the super block.
void
readsb(int dev, struct superblock *sb)
{
80101393: 8b 75 0c mov 0xc(%ebp),%esi
struct buf *bp;
bp = bread(dev, 1);
80101396: 89 04 24 mov %eax,(%esp)
80101399: e8 32 ed ff ff call 801000d0 <bread>
memmove(sb, bp->data, sizeof(*sb));
8010139e: 89 34 24 mov %esi,(%esp)
801013a1: c7 44 24 08 1c 00 00 movl $0x1c,0x8(%esp)
801013a8: 00
void
readsb(int dev, struct superblock *sb)
{
struct buf *bp;
bp = bread(dev, 1);
801013a9: 89 c3 mov %eax,%ebx
memmove(sb, bp->data, sizeof(*sb));
801013ab: 8d 40 5c lea 0x5c(%eax),%eax
801013ae: 89 44 24 04 mov %eax,0x4(%esp)
801013b2: e8 59 2f 00 00 call 80104310 <memmove>
brelse(bp);
801013b7: 89 5d 08 mov %ebx,0x8(%ebp)
}
801013ba: 83 c4 10 add $0x10,%esp
801013bd: 5b pop %ebx
801013be: 5e pop %esi
801013bf: 5d pop %ebp
{
struct buf *bp;
bp = bread(dev, 1);
memmove(sb, bp->data, sizeof(*sb));
brelse(bp);
801013c0: e9 1b ee ff ff jmp 801001e0 <brelse>
801013c5: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
801013c9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801013d0 <bfree>:
}
// Free a disk block.
static void
bfree(int dev, uint b)
{
801013d0: 55 push %ebp
801013d1: 89 e5 mov %esp,%ebp
801013d3: 57 push %edi
801013d4: 89 d7 mov %edx,%edi
801013d6: 56 push %esi
801013d7: 53 push %ebx
801013d8: 89 c3 mov %eax,%ebx
801013da: 83 ec 1c sub $0x1c,%esp
struct buf *bp;
int bi, m;
readsb(dev, &sb);
801013dd: 89 04 24 mov %eax,(%esp)
801013e0: c7 44 24 04 c0 09 11 movl $0x801109c0,0x4(%esp)
801013e7: 80
801013e8: e8 93 ff ff ff call 80101380 <readsb>
bp = bread(dev, BBLOCK(b, sb));
801013ed: 89 fa mov %edi,%edx
801013ef: c1 ea 0c shr $0xc,%edx
801013f2: 03 15 d8 09 11 80 add 0x801109d8,%edx
801013f8: 89 1c 24 mov %ebx,(%esp)
bi = b % BPB;
m = 1 << (bi % 8);
801013fb: bb 01 00 00 00 mov $0x1,%ebx
{
struct buf *bp;
int bi, m;
readsb(dev, &sb);
bp = bread(dev, BBLOCK(b, sb));
80101400: 89 54 24 04 mov %edx,0x4(%esp)
80101404: e8 c7 ec ff ff call 801000d0 <bread>
bi = b % BPB;
m = 1 << (bi % 8);
80101409: 89 f9 mov %edi,%ecx
struct buf *bp;
int bi, m;
readsb(dev, &sb);
bp = bread(dev, BBLOCK(b, sb));
bi = b % BPB;
8010140b: 81 e7 ff 0f 00 00 and $0xfff,%edi
80101411: 89 fa mov %edi,%edx
m = 1 << (bi % 8);
80101413: 83 e1 07 and $0x7,%ecx
if((bp->data[bi/8] & m) == 0)
80101416: c1 fa 03 sar $0x3,%edx
int bi, m;
readsb(dev, &sb);
bp = bread(dev, BBLOCK(b, sb));
bi = b % BPB;
m = 1 << (bi % 8);
80101419: d3 e3 shl %cl,%ebx
{
struct buf *bp;
int bi, m;
readsb(dev, &sb);
bp = bread(dev, BBLOCK(b, sb));
8010141b: 89 c6 mov %eax,%esi
bi = b % BPB;
m = 1 << (bi % 8);
if((bp->data[bi/8] & m) == 0)
8010141d: 0f b6 44 10 5c movzbl 0x5c(%eax,%edx,1),%eax
80101422: 0f b6 c8 movzbl %al,%ecx
80101425: 85 d9 test %ebx,%ecx
80101427: 74 20 je 80101449 <bfree+0x79>
panic("freeing free block");
bp->data[bi/8] &= ~m;
80101429: f7 d3 not %ebx
8010142b: 21 c3 and %eax,%ebx
8010142d: 88 5c 16 5c mov %bl,0x5c(%esi,%edx,1)
log_write(bp);
80101431: 89 34 24 mov %esi,(%esp)
80101434: e8 67 18 00 00 call 80102ca0 <log_write>
brelse(bp);
80101439: 89 34 24 mov %esi,(%esp)
8010143c: e8 9f ed ff ff call 801001e0 <brelse>
}
80101441: 83 c4 1c add $0x1c,%esp
80101444: 5b pop %ebx
80101445: 5e pop %esi
80101446: 5f pop %edi
80101447: 5d pop %ebp
80101448: c3 ret
readsb(dev, &sb);
bp = bread(dev, BBLOCK(b, sb));
bi = b % BPB;
m = 1 << (bi % 8);
if((bp->data[bi/8] & m) == 0)
panic("freeing free block");
80101449: c7 04 24 98 6e 10 80 movl $0x80106e98,(%esp)
80101450: e8 0b ef ff ff call 80100360 <panic>
80101455: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80101459: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80101460 <iinit>:
struct inode inode[NINODE];
} icache;
void
iinit(int dev)
{
80101460: 55 push %ebp
80101461: 89 e5 mov %esp,%ebp
80101463: 53 push %ebx
80101464: bb 20 0a 11 80 mov $0x80110a20,%ebx
80101469: 83 ec 24 sub $0x24,%esp
int i = 0;
initlock(&icache.lock, "icache");
8010146c: c7 44 24 04 ab 6e 10 movl $0x80106eab,0x4(%esp)
80101473: 80
80101474: c7 04 24 e0 09 11 80 movl $0x801109e0,(%esp)
8010147b: e8 c0 2b 00 00 call 80104040 <initlock>
for(i = 0; i < NINODE; i++) {
initsleeplock(&icache.inode[i].lock, "inode");
80101480: 89 1c 24 mov %ebx,(%esp)
80101483: 81 c3 90 00 00 00 add $0x90,%ebx
80101489: c7 44 24 04 b2 6e 10 movl $0x80106eb2,0x4(%esp)
80101490: 80
80101491: e8 9a 2a 00 00 call 80103f30 <initsleeplock>
iinit(int dev)
{
int i = 0;
initlock(&icache.lock, "icache");
for(i = 0; i < NINODE; i++) {
80101496: 81 fb 40 26 11 80 cmp $0x80112640,%ebx
8010149c: 75 e2 jne 80101480 <iinit+0x20>
initsleeplock(&icache.inode[i].lock, "inode");
}
readsb(dev, &sb);
8010149e: 8b 45 08 mov 0x8(%ebp),%eax
801014a1: c7 44 24 04 c0 09 11 movl $0x801109c0,0x4(%esp)
801014a8: 80
801014a9: 89 04 24 mov %eax,(%esp)
801014ac: e8 cf fe ff ff call 80101380 <readsb>
cprintf("sb: size %d nblocks %d ninodes %d nlog %d logstart %d\
801014b1: a1 d8 09 11 80 mov 0x801109d8,%eax
801014b6: c7 04 24 18 6f 10 80 movl $0x80106f18,(%esp)
801014bd: 89 44 24 1c mov %eax,0x1c(%esp)
801014c1: a1 d4 09 11 80 mov 0x801109d4,%eax
801014c6: 89 44 24 18 mov %eax,0x18(%esp)
801014ca: a1 d0 09 11 80 mov 0x801109d0,%eax
801014cf: 89 44 24 14 mov %eax,0x14(%esp)
801014d3: a1 cc 09 11 80 mov 0x801109cc,%eax
801014d8: 89 44 24 10 mov %eax,0x10(%esp)
801014dc: a1 c8 09 11 80 mov 0x801109c8,%eax
801014e1: 89 44 24 0c mov %eax,0xc(%esp)
801014e5: a1 c4 09 11 80 mov 0x801109c4,%eax
801014ea: 89 44 24 08 mov %eax,0x8(%esp)
801014ee: a1 c0 09 11 80 mov 0x801109c0,%eax
801014f3: 89 44 24 04 mov %eax,0x4(%esp)
801014f7: e8 54 f1 ff ff call 80100650 <cprintf>
inodestart %d bmap start %d\n", sb.size, sb.nblocks,
sb.ninodes, sb.nlog, sb.logstart, sb.inodestart,
sb.bmapstart);
}
801014fc: 83 c4 24 add $0x24,%esp
801014ff: 5b pop %ebx
80101500: 5d pop %ebp
80101501: c3 ret
80101502: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80101509: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80101510 <ialloc>:
// Allocate an inode on device dev.
// Mark it as allocated by giving it type type.
// Returns an unlocked but allocated and referenced inode.
struct inode*
ialloc(uint dev, short type)
{
80101510: 55 push %ebp
80101511: 89 e5 mov %esp,%ebp
80101513: 57 push %edi
80101514: 56 push %esi
80101515: 53 push %ebx
80101516: 83 ec 2c sub $0x2c,%esp
80101519: 8b 45 0c mov 0xc(%ebp),%eax
int inum;
struct buf *bp;
struct dinode *dip;
for(inum = 1; inum < sb.ninodes; inum++){
8010151c: 83 3d c8 09 11 80 01 cmpl $0x1,0x801109c8
// Allocate an inode on device dev.
// Mark it as allocated by giving it type type.
// Returns an unlocked but allocated and referenced inode.
struct inode*
ialloc(uint dev, short type)
{
80101523: 8b 7d 08 mov 0x8(%ebp),%edi
80101526: 89 45 e4 mov %eax,-0x1c(%ebp)
int inum;
struct buf *bp;
struct dinode *dip;
for(inum = 1; inum < sb.ninodes; inum++){
80101529: 0f 86 a2 00 00 00 jbe 801015d1 <ialloc+0xc1>
8010152f: be 01 00 00 00 mov $0x1,%esi
80101534: bb 01 00 00 00 mov $0x1,%ebx
80101539: eb 1a jmp 80101555 <ialloc+0x45>
8010153b: 90 nop
8010153c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
dip->type = type;
log_write(bp); // mark it allocated on the disk
brelse(bp);
return iget(dev, inum);
}
brelse(bp);
80101540: 89 14 24 mov %edx,(%esp)
{
int inum;
struct buf *bp;
struct dinode *dip;
for(inum = 1; inum < sb.ninodes; inum++){
80101543: 83 c3 01 add $0x1,%ebx
dip->type = type;
log_write(bp); // mark it allocated on the disk
brelse(bp);
return iget(dev, inum);
}
brelse(bp);
80101546: e8 95 ec ff ff call 801001e0 <brelse>
{
int inum;
struct buf *bp;
struct dinode *dip;
for(inum = 1; inum < sb.ninodes; inum++){
8010154b: 89 de mov %ebx,%esi
8010154d: 3b 1d c8 09 11 80 cmp 0x801109c8,%ebx
80101553: 73 7c jae 801015d1 <ialloc+0xc1>
bp = bread(dev, IBLOCK(inum, sb));
80101555: 89 f0 mov %esi,%eax
80101557: c1 e8 03 shr $0x3,%eax
8010155a: 03 05 d4 09 11 80 add 0x801109d4,%eax
80101560: 89 3c 24 mov %edi,(%esp)
80101563: 89 44 24 04 mov %eax,0x4(%esp)
80101567: e8 64 eb ff ff call 801000d0 <bread>
8010156c: 89 c2 mov %eax,%edx
dip = (struct dinode*)bp->data + inum%IPB;
8010156e: 89 f0 mov %esi,%eax
80101570: 83 e0 07 and $0x7,%eax
80101573: c1 e0 06 shl $0x6,%eax
80101576: 8d 4c 02 5c lea 0x5c(%edx,%eax,1),%ecx
if(dip->type == 0){ // a free inode
8010157a: 66 83 39 00 cmpw $0x0,(%ecx)
8010157e: 75 c0 jne 80101540 <ialloc+0x30>
memset(dip, 0, sizeof(*dip));
80101580: 89 0c 24 mov %ecx,(%esp)
80101583: c7 44 24 08 40 00 00 movl $0x40,0x8(%esp)
8010158a: 00
8010158b: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
80101592: 00
80101593: 89 55 dc mov %edx,-0x24(%ebp)
80101596: 89 4d e0 mov %ecx,-0x20(%ebp)
80101599: e8 d2 2c 00 00 call 80104270 <memset>
dip->type = type;
8010159e: 0f b7 45 e4 movzwl -0x1c(%ebp),%eax
log_write(bp); // mark it allocated on the disk
801015a2: 8b 55 dc mov -0x24(%ebp),%edx
for(inum = 1; inum < sb.ninodes; inum++){
bp = bread(dev, IBLOCK(inum, sb));
dip = (struct dinode*)bp->data + inum%IPB;
if(dip->type == 0){ // a free inode
memset(dip, 0, sizeof(*dip));
dip->type = type;
801015a5: 8b 4d e0 mov -0x20(%ebp),%ecx
log_write(bp); // mark it allocated on the disk
801015a8: 89 55 e4 mov %edx,-0x1c(%ebp)
for(inum = 1; inum < sb.ninodes; inum++){
bp = bread(dev, IBLOCK(inum, sb));
dip = (struct dinode*)bp->data + inum%IPB;
if(dip->type == 0){ // a free inode
memset(dip, 0, sizeof(*dip));
dip->type = type;
801015ab: 66 89 01 mov %ax,(%ecx)
log_write(bp); // mark it allocated on the disk
801015ae: 89 14 24 mov %edx,(%esp)
801015b1: e8 ea 16 00 00 call 80102ca0 <log_write>
brelse(bp);
801015b6: 8b 55 e4 mov -0x1c(%ebp),%edx
801015b9: 89 14 24 mov %edx,(%esp)
801015bc: e8 1f ec ff ff call 801001e0 <brelse>
return iget(dev, inum);
}
brelse(bp);
}
panic("ialloc: no inodes");
}
801015c1: 83 c4 2c add $0x2c,%esp
if(dip->type == 0){ // a free inode
memset(dip, 0, sizeof(*dip));
dip->type = type;
log_write(bp); // mark it allocated on the disk
brelse(bp);
return iget(dev, inum);
801015c4: 89 f2 mov %esi,%edx
}
brelse(bp);
}
panic("ialloc: no inodes");
}
801015c6: 5b pop %ebx
if(dip->type == 0){ // a free inode
memset(dip, 0, sizeof(*dip));
dip->type = type;
log_write(bp); // mark it allocated on the disk
brelse(bp);
return iget(dev, inum);
801015c7: 89 f8 mov %edi,%eax
}
brelse(bp);
}
panic("ialloc: no inodes");
}
801015c9: 5e pop %esi
801015ca: 5f pop %edi
801015cb: 5d pop %ebp
if(dip->type == 0){ // a free inode
memset(dip, 0, sizeof(*dip));
dip->type = type;
log_write(bp); // mark it allocated on the disk
brelse(bp);
return iget(dev, inum);
801015cc: e9 2f fc ff ff jmp 80101200 <iget>
}
brelse(bp);
}
panic("ialloc: no inodes");
801015d1: c7 04 24 b8 6e 10 80 movl $0x80106eb8,(%esp)
801015d8: e8 83 ed ff ff call 80100360 <panic>
801015dd: 8d 76 00 lea 0x0(%esi),%esi
801015e0 <iupdate>:
// Must be called after every change to an ip->xxx field
// that lives on disk, since i-node cache is write-through.
// Caller must hold ip->lock.
void
iupdate(struct inode *ip)
{
801015e0: 55 push %ebp
801015e1: 89 e5 mov %esp,%ebp
801015e3: 56 push %esi
801015e4: 53 push %ebx
801015e5: 83 ec 10 sub $0x10,%esp
801015e8: 8b 5d 08 mov 0x8(%ebp),%ebx
struct buf *bp;
struct dinode *dip;
bp = bread(ip->dev, IBLOCK(ip->inum, sb));
801015eb: 8b 43 04 mov 0x4(%ebx),%eax
dip->type = ip->type;
dip->major = ip->major;
dip->minor = ip->minor;
dip->nlink = ip->nlink;
dip->size = ip->size;
memmove(dip->addrs, ip->addrs, sizeof(ip->addrs));
801015ee: 83 c3 5c add $0x5c,%ebx
iupdate(struct inode *ip)
{
struct buf *bp;
struct dinode *dip;
bp = bread(ip->dev, IBLOCK(ip->inum, sb));
801015f1: c1 e8 03 shr $0x3,%eax
801015f4: 03 05 d4 09 11 80 add 0x801109d4,%eax
801015fa: 89 44 24 04 mov %eax,0x4(%esp)
801015fe: 8b 43 a4 mov -0x5c(%ebx),%eax
80101601: 89 04 24 mov %eax,(%esp)
80101604: e8 c7 ea ff ff call 801000d0 <bread>
dip = (struct dinode*)bp->data + ip->inum%IPB;
80101609: 8b 53 a8 mov -0x58(%ebx),%edx
8010160c: 83 e2 07 and $0x7,%edx
8010160f: c1 e2 06 shl $0x6,%edx
80101612: 8d 54 10 5c lea 0x5c(%eax,%edx,1),%edx
iupdate(struct inode *ip)
{
struct buf *bp;
struct dinode *dip;
bp = bread(ip->dev, IBLOCK(ip->inum, sb));
80101616: 89 c6 mov %eax,%esi
dip = (struct dinode*)bp->data + ip->inum%IPB;
dip->type = ip->type;
80101618: 0f b7 43 f4 movzwl -0xc(%ebx),%eax
dip->major = ip->major;
dip->minor = ip->minor;
dip->nlink = ip->nlink;
dip->size = ip->size;
memmove(dip->addrs, ip->addrs, sizeof(ip->addrs));
8010161c: 83 c2 0c add $0xc,%edx
struct buf *bp;
struct dinode *dip;
bp = bread(ip->dev, IBLOCK(ip->inum, sb));
dip = (struct dinode*)bp->data + ip->inum%IPB;
dip->type = ip->type;
8010161f: 66 89 42 f4 mov %ax,-0xc(%edx)
dip->major = ip->major;
80101623: 0f b7 43 f6 movzwl -0xa(%ebx),%eax
80101627: 66 89 42 f6 mov %ax,-0xa(%edx)
dip->minor = ip->minor;
8010162b: 0f b7 43 f8 movzwl -0x8(%ebx),%eax
8010162f: 66 89 42 f8 mov %ax,-0x8(%edx)
dip->nlink = ip->nlink;
80101633: 0f b7 43 fa movzwl -0x6(%ebx),%eax
80101637: 66 89 42 fa mov %ax,-0x6(%edx)
dip->size = ip->size;
8010163b: 8b 43 fc mov -0x4(%ebx),%eax
8010163e: 89 42 fc mov %eax,-0x4(%edx)
memmove(dip->addrs, ip->addrs, sizeof(ip->addrs));
80101641: 89 5c 24 04 mov %ebx,0x4(%esp)
80101645: 89 14 24 mov %edx,(%esp)
80101648: c7 44 24 08 34 00 00 movl $0x34,0x8(%esp)
8010164f: 00
80101650: e8 bb 2c 00 00 call 80104310 <memmove>
log_write(bp);
80101655: 89 34 24 mov %esi,(%esp)
80101658: e8 43 16 00 00 call 80102ca0 <log_write>
brelse(bp);
8010165d: 89 75 08 mov %esi,0x8(%ebp)
}
80101660: 83 c4 10 add $0x10,%esp
80101663: 5b pop %ebx
80101664: 5e pop %esi
80101665: 5d pop %ebp
dip->minor = ip->minor;
dip->nlink = ip->nlink;
dip->size = ip->size;
memmove(dip->addrs, ip->addrs, sizeof(ip->addrs));
log_write(bp);
brelse(bp);
80101666: e9 75 eb ff ff jmp 801001e0 <brelse>
8010166b: 90 nop
8010166c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80101670 <idup>:
// Increment reference count for ip.
// Returns ip to enable ip = idup(ip1) idiom.
struct inode*
idup(struct inode *ip)
{
80101670: 55 push %ebp
80101671: 89 e5 mov %esp,%ebp
80101673: 53 push %ebx
80101674: 83 ec 14 sub $0x14,%esp
80101677: 8b 5d 08 mov 0x8(%ebp),%ebx
acquire(&icache.lock);
8010167a: c7 04 24 e0 09 11 80 movl $0x801109e0,(%esp)
80101681: e8 aa 2a 00 00 call 80104130 <acquire>
ip->ref++;
80101686: 83 43 08 01 addl $0x1,0x8(%ebx)
release(&icache.lock);
8010168a: c7 04 24 e0 09 11 80 movl $0x801109e0,(%esp)
80101691: e8 8a 2b 00 00 call 80104220 <release>
return ip;
}
80101696: 83 c4 14 add $0x14,%esp
80101699: 89 d8 mov %ebx,%eax
8010169b: 5b pop %ebx
8010169c: 5d pop %ebp
8010169d: c3 ret
8010169e: 66 90 xchg %ax,%ax
801016a0 <ilock>:
// Lock the given inode.
// Reads the inode from disk if necessary.
void
ilock(struct inode *ip)
{
801016a0: 55 push %ebp
801016a1: 89 e5 mov %esp,%ebp
801016a3: 56 push %esi
801016a4: 53 push %ebx
801016a5: 83 ec 10 sub $0x10,%esp
801016a8: 8b 5d 08 mov 0x8(%ebp),%ebx
struct buf *bp;
struct dinode *dip;
if(ip == 0 || ip->ref < 1)
801016ab: 85 db test %ebx,%ebx
801016ad: 0f 84 b3 00 00 00 je 80101766 <ilock+0xc6>
801016b3: 8b 53 08 mov 0x8(%ebx),%edx
801016b6: 85 d2 test %edx,%edx
801016b8: 0f 8e a8 00 00 00 jle 80101766 <ilock+0xc6>
panic("ilock");
acquiresleep(&ip->lock);
801016be: 8d 43 0c lea 0xc(%ebx),%eax
801016c1: 89 04 24 mov %eax,(%esp)
801016c4: e8 a7 28 00 00 call 80103f70 <acquiresleep>
if(ip->valid == 0){
801016c9: 8b 43 4c mov 0x4c(%ebx),%eax
801016cc: 85 c0 test %eax,%eax
801016ce: 74 08 je 801016d8 <ilock+0x38>
brelse(bp);
ip->valid = 1;
if(ip->type == 0)
panic("ilock: no type");
}
}
801016d0: 83 c4 10 add $0x10,%esp
801016d3: 5b pop %ebx
801016d4: 5e pop %esi
801016d5: 5d pop %ebp
801016d6: c3 ret
801016d7: 90 nop
panic("ilock");
acquiresleep(&ip->lock);
if(ip->valid == 0){
bp = bread(ip->dev, IBLOCK(ip->inum, sb));
801016d8: 8b 43 04 mov 0x4(%ebx),%eax
801016db: c1 e8 03 shr $0x3,%eax
801016de: 03 05 d4 09 11 80 add 0x801109d4,%eax
801016e4: 89 44 24 04 mov %eax,0x4(%esp)
801016e8: 8b 03 mov (%ebx),%eax
801016ea: 89 04 24 mov %eax,(%esp)
801016ed: e8 de e9 ff ff call 801000d0 <bread>
dip = (struct dinode*)bp->data + ip->inum%IPB;
801016f2: 8b 53 04 mov 0x4(%ebx),%edx
801016f5: 83 e2 07 and $0x7,%edx
801016f8: c1 e2 06 shl $0x6,%edx
801016fb: 8d 54 10 5c lea 0x5c(%eax,%edx,1),%edx
panic("ilock");
acquiresleep(&ip->lock);
if(ip->valid == 0){
bp = bread(ip->dev, IBLOCK(ip->inum, sb));
801016ff: 89 c6 mov %eax,%esi
dip = (struct dinode*)bp->data + ip->inum%IPB;
ip->type = dip->type;
80101701: 0f b7 02 movzwl (%edx),%eax
ip->major = dip->major;
ip->minor = dip->minor;
ip->nlink = dip->nlink;
ip->size = dip->size;
memmove(ip->addrs, dip->addrs, sizeof(ip->addrs));
80101704: 83 c2 0c add $0xc,%edx
acquiresleep(&ip->lock);
if(ip->valid == 0){
bp = bread(ip->dev, IBLOCK(ip->inum, sb));
dip = (struct dinode*)bp->data + ip->inum%IPB;
ip->type = dip->type;
80101707: 66 89 43 50 mov %ax,0x50(%ebx)
ip->major = dip->major;
8010170b: 0f b7 42 f6 movzwl -0xa(%edx),%eax
8010170f: 66 89 43 52 mov %ax,0x52(%ebx)
ip->minor = dip->minor;
80101713: 0f b7 42 f8 movzwl -0x8(%edx),%eax
80101717: 66 89 43 54 mov %ax,0x54(%ebx)
ip->nlink = dip->nlink;
8010171b: 0f b7 42 fa movzwl -0x6(%edx),%eax
8010171f: 66 89 43 56 mov %ax,0x56(%ebx)
ip->size = dip->size;
80101723: 8b 42 fc mov -0x4(%edx),%eax
80101726: 89 43 58 mov %eax,0x58(%ebx)
memmove(ip->addrs, dip->addrs, sizeof(ip->addrs));
80101729: 8d 43 5c lea 0x5c(%ebx),%eax
8010172c: 89 54 24 04 mov %edx,0x4(%esp)
80101730: c7 44 24 08 34 00 00 movl $0x34,0x8(%esp)
80101737: 00
80101738: 89 04 24 mov %eax,(%esp)
8010173b: e8 d0 2b 00 00 call 80104310 <memmove>
brelse(bp);
80101740: 89 34 24 mov %esi,(%esp)
80101743: e8 98 ea ff ff call 801001e0 <brelse>
ip->valid = 1;
if(ip->type == 0)
80101748: 66 83 7b 50 00 cmpw $0x0,0x50(%ebx)
ip->minor = dip->minor;
ip->nlink = dip->nlink;
ip->size = dip->size;
memmove(ip->addrs, dip->addrs, sizeof(ip->addrs));
brelse(bp);
ip->valid = 1;
8010174d: c7 43 4c 01 00 00 00 movl $0x1,0x4c(%ebx)
if(ip->type == 0)
80101754: 0f 85 76 ff ff ff jne 801016d0 <ilock+0x30>
panic("ilock: no type");
8010175a: c7 04 24 d0 6e 10 80 movl $0x80106ed0,(%esp)
80101761: e8 fa eb ff ff call 80100360 <panic>
{
struct buf *bp;
struct dinode *dip;
if(ip == 0 || ip->ref < 1)
panic("ilock");
80101766: c7 04 24 ca 6e 10 80 movl $0x80106eca,(%esp)
8010176d: e8 ee eb ff ff call 80100360 <panic>
80101772: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80101779: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80101780 <iunlock>:
}
// Unlock the given inode.
void
iunlock(struct inode *ip)
{
80101780: 55 push %ebp
80101781: 89 e5 mov %esp,%ebp
80101783: 56 push %esi
80101784: 53 push %ebx
80101785: 83 ec 10 sub $0x10,%esp
80101788: 8b 5d 08 mov 0x8(%ebp),%ebx
if(ip == 0 || !holdingsleep(&ip->lock) || ip->ref < 1)
8010178b: 85 db test %ebx,%ebx
8010178d: 74 24 je 801017b3 <iunlock+0x33>
8010178f: 8d 73 0c lea 0xc(%ebx),%esi
80101792: 89 34 24 mov %esi,(%esp)
80101795: e8 76 28 00 00 call 80104010 <holdingsleep>
8010179a: 85 c0 test %eax,%eax
8010179c: 74 15 je 801017b3 <iunlock+0x33>
8010179e: 8b 43 08 mov 0x8(%ebx),%eax
801017a1: 85 c0 test %eax,%eax
801017a3: 7e 0e jle 801017b3 <iunlock+0x33>
panic("iunlock");
releasesleep(&ip->lock);
801017a5: 89 75 08 mov %esi,0x8(%ebp)
}
801017a8: 83 c4 10 add $0x10,%esp
801017ab: 5b pop %ebx
801017ac: 5e pop %esi
801017ad: 5d pop %ebp
iunlock(struct inode *ip)
{
if(ip == 0 || !holdingsleep(&ip->lock) || ip->ref < 1)
panic("iunlock");
releasesleep(&ip->lock);
801017ae: e9 1d 28 00 00 jmp 80103fd0 <releasesleep>
// Unlock the given inode.
void
iunlock(struct inode *ip)
{
if(ip == 0 || !holdingsleep(&ip->lock) || ip->ref < 1)
panic("iunlock");
801017b3: c7 04 24 df 6e 10 80 movl $0x80106edf,(%esp)
801017ba: e8 a1 eb ff ff call 80100360 <panic>
801017bf: 90 nop
801017c0 <iput>:
// to it, free the inode (and its content) on disk.
// All calls to iput() must be inside a transaction in
// case it has to free the inode.
void
iput(struct inode *ip)
{
801017c0: 55 push %ebp
801017c1: 89 e5 mov %esp,%ebp
801017c3: 57 push %edi
801017c4: 56 push %esi
801017c5: 53 push %ebx
801017c6: 83 ec 1c sub $0x1c,%esp
801017c9: 8b 75 08 mov 0x8(%ebp),%esi
acquiresleep(&ip->lock);
801017cc: 8d 7e 0c lea 0xc(%esi),%edi
801017cf: 89 3c 24 mov %edi,(%esp)
801017d2: e8 99 27 00 00 call 80103f70 <acquiresleep>
if(ip->valid && ip->nlink == 0){
801017d7: 8b 56 4c mov 0x4c(%esi),%edx
801017da: 85 d2 test %edx,%edx
801017dc: 74 07 je 801017e5 <iput+0x25>
801017de: 66 83 7e 56 00 cmpw $0x0,0x56(%esi)
801017e3: 74 2b je 80101810 <iput+0x50>
ip->type = 0;
iupdate(ip);
ip->valid = 0;
}
}
releasesleep(&ip->lock);
801017e5: 89 3c 24 mov %edi,(%esp)
801017e8: e8 e3 27 00 00 call 80103fd0 <releasesleep>
acquire(&icache.lock);
801017ed: c7 04 24 e0 09 11 80 movl $0x801109e0,(%esp)
801017f4: e8 37 29 00 00 call 80104130 <acquire>
ip->ref--;
801017f9: 83 6e 08 01 subl $0x1,0x8(%esi)
release(&icache.lock);
801017fd: c7 45 08 e0 09 11 80 movl $0x801109e0,0x8(%ebp)
}
80101804: 83 c4 1c add $0x1c,%esp
80101807: 5b pop %ebx
80101808: 5e pop %esi
80101809: 5f pop %edi
8010180a: 5d pop %ebp
}
releasesleep(&ip->lock);
acquire(&icache.lock);
ip->ref--;
release(&icache.lock);
8010180b: e9 10 2a 00 00 jmp 80104220 <release>
void
iput(struct inode *ip)
{
acquiresleep(&ip->lock);
if(ip->valid && ip->nlink == 0){
acquire(&icache.lock);
80101810: c7 04 24 e0 09 11 80 movl $0x801109e0,(%esp)
80101817: e8 14 29 00 00 call 80104130 <acquire>
int r = ip->ref;
8010181c: 8b 5e 08 mov 0x8(%esi),%ebx
release(&icache.lock);
8010181f: c7 04 24 e0 09 11 80 movl $0x801109e0,(%esp)
80101826: e8 f5 29 00 00 call 80104220 <release>
if(r == 1){
8010182b: 83 fb 01 cmp $0x1,%ebx
8010182e: 75 b5 jne 801017e5 <iput+0x25>
80101830: 8d 4e 30 lea 0x30(%esi),%ecx
80101833: 89 f3 mov %esi,%ebx
80101835: 89 7d e4 mov %edi,-0x1c(%ebp)
80101838: 89 cf mov %ecx,%edi
8010183a: eb 0b jmp 80101847 <iput+0x87>
8010183c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80101840: 83 c3 04 add $0x4,%ebx
{
int i, j;
struct buf *bp;
uint *a;
for(i = 0; i < NDIRECT; i++){
80101843: 39 fb cmp %edi,%ebx
80101845: 74 19 je 80101860 <iput+0xa0>
if(ip->addrs[i]){
80101847: 8b 53 5c mov 0x5c(%ebx),%edx
8010184a: 85 d2 test %edx,%edx
8010184c: 74 f2 je 80101840 <iput+0x80>
bfree(ip->dev, ip->addrs[i]);
8010184e: 8b 06 mov (%esi),%eax
80101850: e8 7b fb ff ff call 801013d0 <bfree>
ip->addrs[i] = 0;
80101855: c7 43 5c 00 00 00 00 movl $0x0,0x5c(%ebx)
8010185c: eb e2 jmp 80101840 <iput+0x80>
8010185e: 66 90 xchg %ax,%ax
}
}
if(ip->addrs[NDIRECT]){
80101860: 8b 86 8c 00 00 00 mov 0x8c(%esi),%eax
80101866: 8b 7d e4 mov -0x1c(%ebp),%edi
80101869: 85 c0 test %eax,%eax
8010186b: 75 2b jne 80101898 <iput+0xd8>
brelse(bp);
bfree(ip->dev, ip->addrs[NDIRECT]);
ip->addrs[NDIRECT] = 0;
}
ip->size = 0;
8010186d: c7 46 58 00 00 00 00 movl $0x0,0x58(%esi)
iupdate(ip);
80101874: 89 34 24 mov %esi,(%esp)
80101877: e8 64 fd ff ff call 801015e0 <iupdate>
int r = ip->ref;
release(&icache.lock);
if(r == 1){
// inode has no links and no other references: truncate and free.
itrunc(ip);
ip->type = 0;
8010187c: 31 c0 xor %eax,%eax
8010187e: 66 89 46 50 mov %ax,0x50(%esi)
iupdate(ip);
80101882: 89 34 24 mov %esi,(%esp)
80101885: e8 56 fd ff ff call 801015e0 <iupdate>
ip->valid = 0;
8010188a: c7 46 4c 00 00 00 00 movl $0x0,0x4c(%esi)
80101891: e9 4f ff ff ff jmp 801017e5 <iput+0x25>
80101896: 66 90 xchg %ax,%ax
ip->addrs[i] = 0;
}
}
if(ip->addrs[NDIRECT]){
bp = bread(ip->dev, ip->addrs[NDIRECT]);
80101898: 89 44 24 04 mov %eax,0x4(%esp)
8010189c: 8b 06 mov (%esi),%eax
a = (uint*)bp->data;
for(j = 0; j < NINDIRECT; j++){
8010189e: 31 db xor %ebx,%ebx
ip->addrs[i] = 0;
}
}
if(ip->addrs[NDIRECT]){
bp = bread(ip->dev, ip->addrs[NDIRECT]);
801018a0: 89 04 24 mov %eax,(%esp)
801018a3: e8 28 e8 ff ff call 801000d0 <bread>
a = (uint*)bp->data;
for(j = 0; j < NINDIRECT; j++){
801018a8: 89 7d e0 mov %edi,-0x20(%ebp)
}
}
if(ip->addrs[NDIRECT]){
bp = bread(ip->dev, ip->addrs[NDIRECT]);
a = (uint*)bp->data;
801018ab: 8d 48 5c lea 0x5c(%eax),%ecx
ip->addrs[i] = 0;
}
}
if(ip->addrs[NDIRECT]){
bp = bread(ip->dev, ip->addrs[NDIRECT]);
801018ae: 89 45 e4 mov %eax,-0x1c(%ebp)
a = (uint*)bp->data;
for(j = 0; j < NINDIRECT; j++){
801018b1: 89 cf mov %ecx,%edi
801018b3: 31 c0 xor %eax,%eax
801018b5: eb 0e jmp 801018c5 <iput+0x105>
801018b7: 90 nop
801018b8: 83 c3 01 add $0x1,%ebx
801018bb: 81 fb 80 00 00 00 cmp $0x80,%ebx
801018c1: 89 d8 mov %ebx,%eax
801018c3: 74 10 je 801018d5 <iput+0x115>
if(a[j])
801018c5: 8b 14 87 mov (%edi,%eax,4),%edx
801018c8: 85 d2 test %edx,%edx
801018ca: 74 ec je 801018b8 <iput+0xf8>
bfree(ip->dev, a[j]);
801018cc: 8b 06 mov (%esi),%eax
801018ce: e8 fd fa ff ff call 801013d0 <bfree>
801018d3: eb e3 jmp 801018b8 <iput+0xf8>
}
brelse(bp);
801018d5: 8b 45 e4 mov -0x1c(%ebp),%eax
801018d8: 8b 7d e0 mov -0x20(%ebp),%edi
801018db: 89 04 24 mov %eax,(%esp)
801018de: e8 fd e8 ff ff call 801001e0 <brelse>
bfree(ip->dev, ip->addrs[NDIRECT]);
801018e3: 8b 96 8c 00 00 00 mov 0x8c(%esi),%edx
801018e9: 8b 06 mov (%esi),%eax
801018eb: e8 e0 fa ff ff call 801013d0 <bfree>
ip->addrs[NDIRECT] = 0;
801018f0: c7 86 8c 00 00 00 00 movl $0x0,0x8c(%esi)
801018f7: 00 00 00
801018fa: e9 6e ff ff ff jmp 8010186d <iput+0xad>
801018ff: 90 nop
80101900 <iunlockput>:
}
// Common idiom: unlock, then put.
void
iunlockput(struct inode *ip)
{
80101900: 55 push %ebp
80101901: 89 e5 mov %esp,%ebp
80101903: 53 push %ebx
80101904: 83 ec 14 sub $0x14,%esp
80101907: 8b 5d 08 mov 0x8(%ebp),%ebx
iunlock(ip);
8010190a: 89 1c 24 mov %ebx,(%esp)
8010190d: e8 6e fe ff ff call 80101780 <iunlock>
iput(ip);
80101912: 89 5d 08 mov %ebx,0x8(%ebp)
}
80101915: 83 c4 14 add $0x14,%esp
80101918: 5b pop %ebx
80101919: 5d pop %ebp
// Common idiom: unlock, then put.
void
iunlockput(struct inode *ip)
{
iunlock(ip);
iput(ip);
8010191a: e9 a1 fe ff ff jmp 801017c0 <iput>
8010191f: 90 nop
80101920 <stati>:
// Copy stat information from inode.
// Caller must hold ip->lock.
void
stati(struct inode *ip, struct stat *st)
{
80101920: 55 push %ebp
80101921: 89 e5 mov %esp,%ebp
80101923: 8b 55 08 mov 0x8(%ebp),%edx
80101926: 8b 45 0c mov 0xc(%ebp),%eax
st->dev = ip->dev;
80101929: 8b 0a mov (%edx),%ecx
8010192b: 89 48 04 mov %ecx,0x4(%eax)
st->ino = ip->inum;
8010192e: 8b 4a 04 mov 0x4(%edx),%ecx
80101931: 89 48 08 mov %ecx,0x8(%eax)
st->type = ip->type;
80101934: 0f b7 4a 50 movzwl 0x50(%edx),%ecx
80101938: 66 89 08 mov %cx,(%eax)
st->nlink = ip->nlink;
8010193b: 0f b7 4a 56 movzwl 0x56(%edx),%ecx
8010193f: 66 89 48 0c mov %cx,0xc(%eax)
st->size = ip->size;
80101943: 8b 52 58 mov 0x58(%edx),%edx
80101946: 89 50 10 mov %edx,0x10(%eax)
}
80101949: 5d pop %ebp
8010194a: c3 ret
8010194b: 90 nop
8010194c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80101950 <readi>:
//PAGEBREAK!
// Read data from inode.
// Caller must hold ip->lock.
int
readi(struct inode *ip, char *dst, uint off, uint n)
{
80101950: 55 push %ebp
80101951: 89 e5 mov %esp,%ebp
80101953: 57 push %edi
80101954: 56 push %esi
80101955: 53 push %ebx
80101956: 83 ec 2c sub $0x2c,%esp
80101959: 8b 45 0c mov 0xc(%ebp),%eax
8010195c: 8b 7d 08 mov 0x8(%ebp),%edi
8010195f: 8b 75 10 mov 0x10(%ebp),%esi
80101962: 89 45 e0 mov %eax,-0x20(%ebp)
80101965: 8b 45 14 mov 0x14(%ebp),%eax
uint tot, m;
struct buf *bp;
if(ip->type == T_DEV){
80101968: 66 83 7f 50 03 cmpw $0x3,0x50(%edi)
//PAGEBREAK!
// Read data from inode.
// Caller must hold ip->lock.
int
readi(struct inode *ip, char *dst, uint off, uint n)
{
8010196d: 89 45 e4 mov %eax,-0x1c(%ebp)
uint tot, m;
struct buf *bp;
if(ip->type == T_DEV){
80101970: 0f 84 aa 00 00 00 je 80101a20 <readi+0xd0>
if(ip->major < 0 || ip->major >= NDEV || !devsw[ip->major].read)
return -1;
return devsw[ip->major].read(ip, dst, n);
}
if(off > ip->size || off + n < off)
80101976: 8b 47 58 mov 0x58(%edi),%eax
80101979: 39 f0 cmp %esi,%eax
8010197b: 0f 82 c7 00 00 00 jb 80101a48 <readi+0xf8>
80101981: 8b 5d e4 mov -0x1c(%ebp),%ebx
80101984: 89 da mov %ebx,%edx
80101986: 01 f2 add %esi,%edx
80101988: 0f 82 ba 00 00 00 jb 80101a48 <readi+0xf8>
return -1;
if(off + n > ip->size)
n = ip->size - off;
8010198e: 89 c1 mov %eax,%ecx
80101990: 29 f1 sub %esi,%ecx
80101992: 39 d0 cmp %edx,%eax
80101994: 0f 43 cb cmovae %ebx,%ecx
for(tot=0; tot<n; tot+=m, off+=m, dst+=m){
80101997: 31 c0 xor %eax,%eax
80101999: 85 c9 test %ecx,%ecx
}
if(off > ip->size || off + n < off)
return -1;
if(off + n > ip->size)
n = ip->size - off;
8010199b: 89 4d e4 mov %ecx,-0x1c(%ebp)
for(tot=0; tot<n; tot+=m, off+=m, dst+=m){
8010199e: 74 70 je 80101a10 <readi+0xc0>
801019a0: 89 7d d8 mov %edi,-0x28(%ebp)
801019a3: 89 c7 mov %eax,%edi
801019a5: 8d 76 00 lea 0x0(%esi),%esi
bp = bread(ip->dev, bmap(ip, off/BSIZE));
801019a8: 8b 5d d8 mov -0x28(%ebp),%ebx
801019ab: 89 f2 mov %esi,%edx
801019ad: c1 ea 09 shr $0x9,%edx
801019b0: 89 d8 mov %ebx,%eax
801019b2: e8 09 f9 ff ff call 801012c0 <bmap>
801019b7: 89 44 24 04 mov %eax,0x4(%esp)
801019bb: 8b 03 mov (%ebx),%eax
m = min(n - tot, BSIZE - off%BSIZE);
801019bd: bb 00 02 00 00 mov $0x200,%ebx
return -1;
if(off + n > ip->size)
n = ip->size - off;
for(tot=0; tot<n; tot+=m, off+=m, dst+=m){
bp = bread(ip->dev, bmap(ip, off/BSIZE));
801019c2: 89 04 24 mov %eax,(%esp)
801019c5: e8 06 e7 ff ff call 801000d0 <bread>
m = min(n - tot, BSIZE - off%BSIZE);
801019ca: 8b 4d e4 mov -0x1c(%ebp),%ecx
801019cd: 29 f9 sub %edi,%ecx
return -1;
if(off + n > ip->size)
n = ip->size - off;
for(tot=0; tot<n; tot+=m, off+=m, dst+=m){
bp = bread(ip->dev, bmap(ip, off/BSIZE));
801019cf: 89 c2 mov %eax,%edx
m = min(n - tot, BSIZE - off%BSIZE);
801019d1: 89 f0 mov %esi,%eax
801019d3: 25 ff 01 00 00 and $0x1ff,%eax
801019d8: 29 c3 sub %eax,%ebx
memmove(dst, bp->data + off%BSIZE, m);
801019da: 8d 44 02 5c lea 0x5c(%edx,%eax,1),%eax
if(off + n > ip->size)
n = ip->size - off;
for(tot=0; tot<n; tot+=m, off+=m, dst+=m){
bp = bread(ip->dev, bmap(ip, off/BSIZE));
m = min(n - tot, BSIZE - off%BSIZE);
801019de: 39 cb cmp %ecx,%ebx
memmove(dst, bp->data + off%BSIZE, m);
801019e0: 89 44 24 04 mov %eax,0x4(%esp)
801019e4: 8b 45 e0 mov -0x20(%ebp),%eax
if(off + n > ip->size)
n = ip->size - off;
for(tot=0; tot<n; tot+=m, off+=m, dst+=m){
bp = bread(ip->dev, bmap(ip, off/BSIZE));
m = min(n - tot, BSIZE - off%BSIZE);
801019e7: 0f 47 d9 cmova %ecx,%ebx
memmove(dst, bp->data + off%BSIZE, m);
801019ea: 89 5c 24 08 mov %ebx,0x8(%esp)
if(off > ip->size || off + n < off)
return -1;
if(off + n > ip->size)
n = ip->size - off;
for(tot=0; tot<n; tot+=m, off+=m, dst+=m){
801019ee: 01 df add %ebx,%edi
801019f0: 01 de add %ebx,%esi
bp = bread(ip->dev, bmap(ip, off/BSIZE));
m = min(n - tot, BSIZE - off%BSIZE);
memmove(dst, bp->data + off%BSIZE, m);
801019f2: 89 55 dc mov %edx,-0x24(%ebp)
801019f5: 89 04 24 mov %eax,(%esp)
801019f8: e8 13 29 00 00 call 80104310 <memmove>
brelse(bp);
801019fd: 8b 55 dc mov -0x24(%ebp),%edx
80101a00: 89 14 24 mov %edx,(%esp)
80101a03: e8 d8 e7 ff ff call 801001e0 <brelse>
if(off > ip->size || off + n < off)
return -1;
if(off + n > ip->size)
n = ip->size - off;
for(tot=0; tot<n; tot+=m, off+=m, dst+=m){
80101a08: 01 5d e0 add %ebx,-0x20(%ebp)
80101a0b: 39 7d e4 cmp %edi,-0x1c(%ebp)
80101a0e: 77 98 ja 801019a8 <readi+0x58>
bp = bread(ip->dev, bmap(ip, off/BSIZE));
m = min(n - tot, BSIZE - off%BSIZE);
memmove(dst, bp->data + off%BSIZE, m);
brelse(bp);
}
return n;
80101a10: 8b 45 e4 mov -0x1c(%ebp),%eax
}
80101a13: 83 c4 2c add $0x2c,%esp
80101a16: 5b pop %ebx
80101a17: 5e pop %esi
80101a18: 5f pop %edi
80101a19: 5d pop %ebp
80101a1a: c3 ret
80101a1b: 90 nop
80101a1c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
{
uint tot, m;
struct buf *bp;
if(ip->type == T_DEV){
if(ip->major < 0 || ip->major >= NDEV || !devsw[ip->major].read)
80101a20: 0f bf 47 52 movswl 0x52(%edi),%eax
80101a24: 66 83 f8 09 cmp $0x9,%ax
80101a28: 77 1e ja 80101a48 <readi+0xf8>
80101a2a: 8b 04 c5 60 09 11 80 mov -0x7feef6a0(,%eax,8),%eax
80101a31: 85 c0 test %eax,%eax
80101a33: 74 13 je 80101a48 <readi+0xf8>
return -1;
return devsw[ip->major].read(ip, dst, n);
80101a35: 8b 75 e4 mov -0x1c(%ebp),%esi
80101a38: 89 75 10 mov %esi,0x10(%ebp)
m = min(n - tot, BSIZE - off%BSIZE);
memmove(dst, bp->data + off%BSIZE, m);
brelse(bp);
}
return n;
}
80101a3b: 83 c4 2c add $0x2c,%esp
80101a3e: 5b pop %ebx
80101a3f: 5e pop %esi
80101a40: 5f pop %edi
80101a41: 5d pop %ebp
struct buf *bp;
if(ip->type == T_DEV){
if(ip->major < 0 || ip->major >= NDEV || !devsw[ip->major].read)
return -1;
return devsw[ip->major].read(ip, dst, n);
80101a42: ff e0 jmp *%eax
80101a44: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
uint tot, m;
struct buf *bp;
if(ip->type == T_DEV){
if(ip->major < 0 || ip->major >= NDEV || !devsw[ip->major].read)
return -1;
80101a48: b8 ff ff ff ff mov $0xffffffff,%eax
80101a4d: eb c4 jmp 80101a13 <readi+0xc3>
80101a4f: 90 nop
80101a50 <writei>:
// PAGEBREAK!
// Write data to inode.
// Caller must hold ip->lock.
int
writei(struct inode *ip, char *src, uint off, uint n)
{
80101a50: 55 push %ebp
80101a51: 89 e5 mov %esp,%ebp
80101a53: 57 push %edi
80101a54: 56 push %esi
80101a55: 53 push %ebx
80101a56: 83 ec 2c sub $0x2c,%esp
80101a59: 8b 45 08 mov 0x8(%ebp),%eax
80101a5c: 8b 75 0c mov 0xc(%ebp),%esi
80101a5f: 8b 4d 14 mov 0x14(%ebp),%ecx
uint tot, m;
struct buf *bp;
if(ip->type == T_DEV){
80101a62: 66 83 78 50 03 cmpw $0x3,0x50(%eax)
// PAGEBREAK!
// Write data to inode.
// Caller must hold ip->lock.
int
writei(struct inode *ip, char *src, uint off, uint n)
{
80101a67: 89 75 dc mov %esi,-0x24(%ebp)
80101a6a: 8b 75 10 mov 0x10(%ebp),%esi
80101a6d: 89 45 d8 mov %eax,-0x28(%ebp)
80101a70: 89 4d e0 mov %ecx,-0x20(%ebp)
uint tot, m;
struct buf *bp;
if(ip->type == T_DEV){
80101a73: 0f 84 b7 00 00 00 je 80101b30 <writei+0xe0>
if(ip->major < 0 || ip->major >= NDEV || !devsw[ip->major].write)
return -1;
return devsw[ip->major].write(ip, src, n);
}
if(off > ip->size || off + n < off)
80101a79: 8b 45 d8 mov -0x28(%ebp),%eax
80101a7c: 39 70 58 cmp %esi,0x58(%eax)
80101a7f: 0f 82 e3 00 00 00 jb 80101b68 <writei+0x118>
80101a85: 8b 4d e0 mov -0x20(%ebp),%ecx
80101a88: 89 c8 mov %ecx,%eax
80101a8a: 01 f0 add %esi,%eax
80101a8c: 0f 82 d6 00 00 00 jb 80101b68 <writei+0x118>
return -1;
if(off + n > MAXFILE*BSIZE)
80101a92: 3d 00 18 01 00 cmp $0x11800,%eax
80101a97: 0f 87 cb 00 00 00 ja 80101b68 <writei+0x118>
return -1;
for(tot=0; tot<n; tot+=m, off+=m, src+=m){
80101a9d: 85 c9 test %ecx,%ecx
80101a9f: c7 45 e4 00 00 00 00 movl $0x0,-0x1c(%ebp)
80101aa6: 74 77 je 80101b1f <writei+0xcf>
bp = bread(ip->dev, bmap(ip, off/BSIZE));
80101aa8: 8b 7d d8 mov -0x28(%ebp),%edi
80101aab: 89 f2 mov %esi,%edx
m = min(n - tot, BSIZE - off%BSIZE);
80101aad: bb 00 02 00 00 mov $0x200,%ebx
return -1;
if(off + n > MAXFILE*BSIZE)
return -1;
for(tot=0; tot<n; tot+=m, off+=m, src+=m){
bp = bread(ip->dev, bmap(ip, off/BSIZE));
80101ab2: c1 ea 09 shr $0x9,%edx
80101ab5: 89 f8 mov %edi,%eax
80101ab7: e8 04 f8 ff ff call 801012c0 <bmap>
80101abc: 89 44 24 04 mov %eax,0x4(%esp)
80101ac0: 8b 07 mov (%edi),%eax
80101ac2: 89 04 24 mov %eax,(%esp)
80101ac5: e8 06 e6 ff ff call 801000d0 <bread>
m = min(n - tot, BSIZE - off%BSIZE);
80101aca: 8b 4d e0 mov -0x20(%ebp),%ecx
80101acd: 2b 4d e4 sub -0x1c(%ebp),%ecx
memmove(bp->data + off%BSIZE, src, m);
80101ad0: 8b 55 dc mov -0x24(%ebp),%edx
return -1;
if(off + n > MAXFILE*BSIZE)
return -1;
for(tot=0; tot<n; tot+=m, off+=m, src+=m){
bp = bread(ip->dev, bmap(ip, off/BSIZE));
80101ad3: 89 c7 mov %eax,%edi
m = min(n - tot, BSIZE - off%BSIZE);
80101ad5: 89 f0 mov %esi,%eax
80101ad7: 25 ff 01 00 00 and $0x1ff,%eax
80101adc: 29 c3 sub %eax,%ebx
80101ade: 39 cb cmp %ecx,%ebx
80101ae0: 0f 47 d9 cmova %ecx,%ebx
memmove(bp->data + off%BSIZE, src, m);
80101ae3: 8d 44 07 5c lea 0x5c(%edi,%eax,1),%eax
if(off > ip->size || off + n < off)
return -1;
if(off + n > MAXFILE*BSIZE)
return -1;
for(tot=0; tot<n; tot+=m, off+=m, src+=m){
80101ae7: 01 de add %ebx,%esi
bp = bread(ip->dev, bmap(ip, off/BSIZE));
m = min(n - tot, BSIZE - off%BSIZE);
memmove(bp->data + off%BSIZE, src, m);
80101ae9: 89 54 24 04 mov %edx,0x4(%esp)
80101aed: 89 5c 24 08 mov %ebx,0x8(%esp)
80101af1: 89 04 24 mov %eax,(%esp)
80101af4: e8 17 28 00 00 call 80104310 <memmove>
log_write(bp);
80101af9: 89 3c 24 mov %edi,(%esp)
80101afc: e8 9f 11 00 00 call 80102ca0 <log_write>
brelse(bp);
80101b01: 89 3c 24 mov %edi,(%esp)
80101b04: e8 d7 e6 ff ff call 801001e0 <brelse>
if(off > ip->size || off + n < off)
return -1;
if(off + n > MAXFILE*BSIZE)
return -1;
for(tot=0; tot<n; tot+=m, off+=m, src+=m){
80101b09: 01 5d e4 add %ebx,-0x1c(%ebp)
80101b0c: 8b 45 e4 mov -0x1c(%ebp),%eax
80101b0f: 01 5d dc add %ebx,-0x24(%ebp)
80101b12: 39 45 e0 cmp %eax,-0x20(%ebp)
80101b15: 77 91 ja 80101aa8 <writei+0x58>
memmove(bp->data + off%BSIZE, src, m);
log_write(bp);
brelse(bp);
}
if(n > 0 && off > ip->size){
80101b17: 8b 45 d8 mov -0x28(%ebp),%eax
80101b1a: 39 70 58 cmp %esi,0x58(%eax)
80101b1d: 72 39 jb 80101b58 <writei+0x108>
ip->size = off;
iupdate(ip);
}
return n;
80101b1f: 8b 45 e0 mov -0x20(%ebp),%eax
}
80101b22: 83 c4 2c add $0x2c,%esp
80101b25: 5b pop %ebx
80101b26: 5e pop %esi
80101b27: 5f pop %edi
80101b28: 5d pop %ebp
80101b29: c3 ret
80101b2a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
{
uint tot, m;
struct buf *bp;
if(ip->type == T_DEV){
if(ip->major < 0 || ip->major >= NDEV || !devsw[ip->major].write)
80101b30: 0f bf 40 52 movswl 0x52(%eax),%eax
80101b34: 66 83 f8 09 cmp $0x9,%ax
80101b38: 77 2e ja 80101b68 <writei+0x118>
80101b3a: 8b 04 c5 64 09 11 80 mov -0x7feef69c(,%eax,8),%eax
80101b41: 85 c0 test %eax,%eax
80101b43: 74 23 je 80101b68 <writei+0x118>
return -1;
return devsw[ip->major].write(ip, src, n);
80101b45: 89 4d 10 mov %ecx,0x10(%ebp)
if(n > 0 && off > ip->size){
ip->size = off;
iupdate(ip);
}
return n;
}
80101b48: 83 c4 2c add $0x2c,%esp
80101b4b: 5b pop %ebx
80101b4c: 5e pop %esi
80101b4d: 5f pop %edi
80101b4e: 5d pop %ebp
struct buf *bp;
if(ip->type == T_DEV){
if(ip->major < 0 || ip->major >= NDEV || !devsw[ip->major].write)
return -1;
return devsw[ip->major].write(ip, src, n);
80101b4f: ff e0 jmp *%eax
80101b51: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
log_write(bp);
brelse(bp);
}
if(n > 0 && off > ip->size){
ip->size = off;
80101b58: 8b 45 d8 mov -0x28(%ebp),%eax
80101b5b: 89 70 58 mov %esi,0x58(%eax)
iupdate(ip);
80101b5e: 89 04 24 mov %eax,(%esp)
80101b61: e8 7a fa ff ff call 801015e0 <iupdate>
80101b66: eb b7 jmp 80101b1f <writei+0xcf>
}
return n;
}
80101b68: 83 c4 2c add $0x2c,%esp
uint tot, m;
struct buf *bp;
if(ip->type == T_DEV){
if(ip->major < 0 || ip->major >= NDEV || !devsw[ip->major].write)
return -1;
80101b6b: b8 ff ff ff ff mov $0xffffffff,%eax
if(n > 0 && off > ip->size){
ip->size = off;
iupdate(ip);
}
return n;
}
80101b70: 5b pop %ebx
80101b71: 5e pop %esi
80101b72: 5f pop %edi
80101b73: 5d pop %ebp
80101b74: c3 ret
80101b75: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80101b79: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80101b80 <namecmp>:
//PAGEBREAK!
// Directories
int
namecmp(const char *s, const char *t)
{
80101b80: 55 push %ebp
80101b81: 89 e5 mov %esp,%ebp
80101b83: 83 ec 18 sub $0x18,%esp
return strncmp(s, t, DIRSIZ);
80101b86: 8b 45 0c mov 0xc(%ebp),%eax
80101b89: c7 44 24 08 0e 00 00 movl $0xe,0x8(%esp)
80101b90: 00
80101b91: 89 44 24 04 mov %eax,0x4(%esp)
80101b95: 8b 45 08 mov 0x8(%ebp),%eax
80101b98: 89 04 24 mov %eax,(%esp)
80101b9b: e8 f0 27 00 00 call 80104390 <strncmp>
}
80101ba0: c9 leave
80101ba1: c3 ret
80101ba2: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80101ba9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80101bb0 <dirlookup>:
// Look for a directory entry in a directory.
// If found, set *poff to byte offset of entry.
struct inode*
dirlookup(struct inode *dp, char *name, uint *poff)
{
80101bb0: 55 push %ebp
80101bb1: 89 e5 mov %esp,%ebp
80101bb3: 57 push %edi
80101bb4: 56 push %esi
80101bb5: 53 push %ebx
80101bb6: 83 ec 2c sub $0x2c,%esp
80101bb9: 8b 5d 08 mov 0x8(%ebp),%ebx
uint off, inum;
struct dirent de;
if(dp->type != T_DIR)
80101bbc: 66 83 7b 50 01 cmpw $0x1,0x50(%ebx)
80101bc1: 0f 85 97 00 00 00 jne 80101c5e <dirlookup+0xae>
panic("dirlookup not DIR");
for(off = 0; off < dp->size; off += sizeof(de)){
80101bc7: 8b 53 58 mov 0x58(%ebx),%edx
80101bca: 31 ff xor %edi,%edi
80101bcc: 8d 75 d8 lea -0x28(%ebp),%esi
80101bcf: 85 d2 test %edx,%edx
80101bd1: 75 0d jne 80101be0 <dirlookup+0x30>
80101bd3: eb 73 jmp 80101c48 <dirlookup+0x98>
80101bd5: 8d 76 00 lea 0x0(%esi),%esi
80101bd8: 83 c7 10 add $0x10,%edi
80101bdb: 39 7b 58 cmp %edi,0x58(%ebx)
80101bde: 76 68 jbe 80101c48 <dirlookup+0x98>
if(readi(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
80101be0: c7 44 24 0c 10 00 00 movl $0x10,0xc(%esp)
80101be7: 00
80101be8: 89 7c 24 08 mov %edi,0x8(%esp)
80101bec: 89 74 24 04 mov %esi,0x4(%esp)
80101bf0: 89 1c 24 mov %ebx,(%esp)
80101bf3: e8 58 fd ff ff call 80101950 <readi>
80101bf8: 83 f8 10 cmp $0x10,%eax
80101bfb: 75 55 jne 80101c52 <dirlookup+0xa2>
panic("dirlookup read");
if(de.inum == 0)
80101bfd: 66 83 7d d8 00 cmpw $0x0,-0x28(%ebp)
80101c02: 74 d4 je 80101bd8 <dirlookup+0x28>
// Directories
int
namecmp(const char *s, const char *t)
{
return strncmp(s, t, DIRSIZ);
80101c04: 8d 45 da lea -0x26(%ebp),%eax
80101c07: 89 44 24 04 mov %eax,0x4(%esp)
80101c0b: 8b 45 0c mov 0xc(%ebp),%eax
80101c0e: c7 44 24 08 0e 00 00 movl $0xe,0x8(%esp)
80101c15: 00
80101c16: 89 04 24 mov %eax,(%esp)
80101c19: e8 72 27 00 00 call 80104390 <strncmp>
for(off = 0; off < dp->size; off += sizeof(de)){
if(readi(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
panic("dirlookup read");
if(de.inum == 0)
continue;
if(namecmp(name, de.name) == 0){
80101c1e: 85 c0 test %eax,%eax
80101c20: 75 b6 jne 80101bd8 <dirlookup+0x28>
// entry matches path element
if(poff)
80101c22: 8b 45 10 mov 0x10(%ebp),%eax
80101c25: 85 c0 test %eax,%eax
80101c27: 74 05 je 80101c2e <dirlookup+0x7e>
*poff = off;
80101c29: 8b 45 10 mov 0x10(%ebp),%eax
80101c2c: 89 38 mov %edi,(%eax)
inum = de.inum;
80101c2e: 0f b7 55 d8 movzwl -0x28(%ebp),%edx
return iget(dp->dev, inum);
80101c32: 8b 03 mov (%ebx),%eax
80101c34: e8 c7 f5 ff ff call 80101200 <iget>
}
}
return 0;
}
80101c39: 83 c4 2c add $0x2c,%esp
80101c3c: 5b pop %ebx
80101c3d: 5e pop %esi
80101c3e: 5f pop %edi
80101c3f: 5d pop %ebp
80101c40: c3 ret
80101c41: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80101c48: 83 c4 2c add $0x2c,%esp
inum = de.inum;
return iget(dp->dev, inum);
}
}
return 0;
80101c4b: 31 c0 xor %eax,%eax
}
80101c4d: 5b pop %ebx
80101c4e: 5e pop %esi
80101c4f: 5f pop %edi
80101c50: 5d pop %ebp
80101c51: c3 ret
if(dp->type != T_DIR)
panic("dirlookup not DIR");
for(off = 0; off < dp->size; off += sizeof(de)){
if(readi(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
panic("dirlookup read");
80101c52: c7 04 24 f9 6e 10 80 movl $0x80106ef9,(%esp)
80101c59: e8 02 e7 ff ff call 80100360 <panic>
{
uint off, inum;
struct dirent de;
if(dp->type != T_DIR)
panic("dirlookup not DIR");
80101c5e: c7 04 24 e7 6e 10 80 movl $0x80106ee7,(%esp)
80101c65: e8 f6 e6 ff ff call 80100360 <panic>
80101c6a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80101c70 <namex>:
// If parent != 0, return the inode for the parent and copy the final
// path element into name, which must have room for DIRSIZ bytes.
// Must be called inside a transaction since it calls iput().
static struct inode*
namex(char *path, int nameiparent, char *name)
{
80101c70: 55 push %ebp
80101c71: 89 e5 mov %esp,%ebp
80101c73: 57 push %edi
80101c74: 89 cf mov %ecx,%edi
80101c76: 56 push %esi
80101c77: 53 push %ebx
80101c78: 89 c3 mov %eax,%ebx
80101c7a: 83 ec 2c sub $0x2c,%esp
struct inode *ip, *next;
if(*path == '/')
80101c7d: 80 38 2f cmpb $0x2f,(%eax)
// If parent != 0, return the inode for the parent and copy the final
// path element into name, which must have room for DIRSIZ bytes.
// Must be called inside a transaction since it calls iput().
static struct inode*
namex(char *path, int nameiparent, char *name)
{
80101c80: 89 55 e0 mov %edx,-0x20(%ebp)
struct inode *ip, *next;
if(*path == '/')
80101c83: 0f 84 51 01 00 00 je 80101dda <namex+0x16a>
ip = iget(ROOTDEV, ROOTINO);
else
ip = idup(myproc()->cwd);
80101c89: e8 02 1a 00 00 call 80103690 <myproc>
80101c8e: 8b 70 6c mov 0x6c(%eax),%esi
// Increment reference count for ip.
// Returns ip to enable ip = idup(ip1) idiom.
struct inode*
idup(struct inode *ip)
{
acquire(&icache.lock);
80101c91: c7 04 24 e0 09 11 80 movl $0x801109e0,(%esp)
80101c98: e8 93 24 00 00 call 80104130 <acquire>
ip->ref++;
80101c9d: 83 46 08 01 addl $0x1,0x8(%esi)
release(&icache.lock);
80101ca1: c7 04 24 e0 09 11 80 movl $0x801109e0,(%esp)
80101ca8: e8 73 25 00 00 call 80104220 <release>
80101cad: eb 04 jmp 80101cb3 <namex+0x43>
80101caf: 90 nop
{
char *s;
int len;
while(*path == '/')
path++;
80101cb0: 83 c3 01 add $0x1,%ebx
skipelem(char *path, char *name)
{
char *s;
int len;
while(*path == '/')
80101cb3: 0f b6 03 movzbl (%ebx),%eax
80101cb6: 3c 2f cmp $0x2f,%al
80101cb8: 74 f6 je 80101cb0 <namex+0x40>
path++;
if(*path == 0)
80101cba: 84 c0 test %al,%al
80101cbc: 0f 84 ed 00 00 00 je 80101daf <namex+0x13f>
return 0;
s = path;
while(*path != '/' && *path != 0)
80101cc2: 0f b6 03 movzbl (%ebx),%eax
80101cc5: 89 da mov %ebx,%edx
80101cc7: 84 c0 test %al,%al
80101cc9: 0f 84 b1 00 00 00 je 80101d80 <namex+0x110>
80101ccf: 3c 2f cmp $0x2f,%al
80101cd1: 75 0f jne 80101ce2 <namex+0x72>
80101cd3: e9 a8 00 00 00 jmp 80101d80 <namex+0x110>
80101cd8: 3c 2f cmp $0x2f,%al
80101cda: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80101ce0: 74 0a je 80101cec <namex+0x7c>
path++;
80101ce2: 83 c2 01 add $0x1,%edx
while(*path == '/')
path++;
if(*path == 0)
return 0;
s = path;
while(*path != '/' && *path != 0)
80101ce5: 0f b6 02 movzbl (%edx),%eax
80101ce8: 84 c0 test %al,%al
80101cea: 75 ec jne 80101cd8 <namex+0x68>
80101cec: 89 d1 mov %edx,%ecx
80101cee: 29 d9 sub %ebx,%ecx
path++;
len = path - s;
if(len >= DIRSIZ)
80101cf0: 83 f9 0d cmp $0xd,%ecx
80101cf3: 0f 8e 8f 00 00 00 jle 80101d88 <namex+0x118>
memmove(name, s, DIRSIZ);
80101cf9: 89 5c 24 04 mov %ebx,0x4(%esp)
80101cfd: c7 44 24 08 0e 00 00 movl $0xe,0x8(%esp)
80101d04: 00
80101d05: 89 3c 24 mov %edi,(%esp)
80101d08: 89 55 e4 mov %edx,-0x1c(%ebp)
80101d0b: e8 00 26 00 00 call 80104310 <memmove>
path++;
if(*path == 0)
return 0;
s = path;
while(*path != '/' && *path != 0)
path++;
80101d10: 8b 55 e4 mov -0x1c(%ebp),%edx
80101d13: 89 d3 mov %edx,%ebx
memmove(name, s, DIRSIZ);
else {
memmove(name, s, len);
name[len] = 0;
}
while(*path == '/')
80101d15: 80 3a 2f cmpb $0x2f,(%edx)
80101d18: 75 0e jne 80101d28 <namex+0xb8>
80101d1a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
path++;
80101d20: 83 c3 01 add $0x1,%ebx
memmove(name, s, DIRSIZ);
else {
memmove(name, s, len);
name[len] = 0;
}
while(*path == '/')
80101d23: 80 3b 2f cmpb $0x2f,(%ebx)
80101d26: 74 f8 je 80101d20 <namex+0xb0>
ip = iget(ROOTDEV, ROOTINO);
else
ip = idup(myproc()->cwd);
while((path = skipelem(path, name)) != 0){
ilock(ip);
80101d28: 89 34 24 mov %esi,(%esp)
80101d2b: e8 70 f9 ff ff call 801016a0 <ilock>
if(ip->type != T_DIR){
80101d30: 66 83 7e 50 01 cmpw $0x1,0x50(%esi)
80101d35: 0f 85 85 00 00 00 jne 80101dc0 <namex+0x150>
iunlockput(ip);
return 0;
}
if(nameiparent && *path == '\0'){
80101d3b: 8b 55 e0 mov -0x20(%ebp),%edx
80101d3e: 85 d2 test %edx,%edx
80101d40: 74 09 je 80101d4b <namex+0xdb>
80101d42: 80 3b 00 cmpb $0x0,(%ebx)
80101d45: 0f 84 a5 00 00 00 je 80101df0 <namex+0x180>
// Stop one level early.
iunlock(ip);
return ip;
}
if((next = dirlookup(ip, name, 0)) == 0){
80101d4b: c7 44 24 08 00 00 00 movl $0x0,0x8(%esp)
80101d52: 00
80101d53: 89 7c 24 04 mov %edi,0x4(%esp)
80101d57: 89 34 24 mov %esi,(%esp)
80101d5a: e8 51 fe ff ff call 80101bb0 <dirlookup>
80101d5f: 85 c0 test %eax,%eax
80101d61: 74 5d je 80101dc0 <namex+0x150>
// Common idiom: unlock, then put.
void
iunlockput(struct inode *ip)
{
iunlock(ip);
80101d63: 89 34 24 mov %esi,(%esp)
80101d66: 89 45 e4 mov %eax,-0x1c(%ebp)
80101d69: e8 12 fa ff ff call 80101780 <iunlock>
iput(ip);
80101d6e: 89 34 24 mov %esi,(%esp)
80101d71: e8 4a fa ff ff call 801017c0 <iput>
if((next = dirlookup(ip, name, 0)) == 0){
iunlockput(ip);
return 0;
}
iunlockput(ip);
ip = next;
80101d76: 8b 45 e4 mov -0x1c(%ebp),%eax
80101d79: 89 c6 mov %eax,%esi
80101d7b: e9 33 ff ff ff jmp 80101cb3 <namex+0x43>
while(*path == '/')
path++;
if(*path == 0)
return 0;
s = path;
while(*path != '/' && *path != 0)
80101d80: 31 c9 xor %ecx,%ecx
80101d82: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
path++;
len = path - s;
if(len >= DIRSIZ)
memmove(name, s, DIRSIZ);
else {
memmove(name, s, len);
80101d88: 89 4c 24 08 mov %ecx,0x8(%esp)
80101d8c: 89 5c 24 04 mov %ebx,0x4(%esp)
80101d90: 89 3c 24 mov %edi,(%esp)
80101d93: 89 55 dc mov %edx,-0x24(%ebp)
80101d96: 89 4d e4 mov %ecx,-0x1c(%ebp)
80101d99: e8 72 25 00 00 call 80104310 <memmove>
name[len] = 0;
80101d9e: 8b 4d e4 mov -0x1c(%ebp),%ecx
80101da1: 8b 55 dc mov -0x24(%ebp),%edx
80101da4: c6 04 0f 00 movb $0x0,(%edi,%ecx,1)
80101da8: 89 d3 mov %edx,%ebx
80101daa: e9 66 ff ff ff jmp 80101d15 <namex+0xa5>
return 0;
}
iunlockput(ip);
ip = next;
}
if(nameiparent){
80101daf: 8b 45 e0 mov -0x20(%ebp),%eax
80101db2: 85 c0 test %eax,%eax
80101db4: 75 4c jne 80101e02 <namex+0x192>
80101db6: 89 f0 mov %esi,%eax
iput(ip);
return 0;
}
return ip;
}
80101db8: 83 c4 2c add $0x2c,%esp
80101dbb: 5b pop %ebx
80101dbc: 5e pop %esi
80101dbd: 5f pop %edi
80101dbe: 5d pop %ebp
80101dbf: c3 ret
// Common idiom: unlock, then put.
void
iunlockput(struct inode *ip)
{
iunlock(ip);
80101dc0: 89 34 24 mov %esi,(%esp)
80101dc3: e8 b8 f9 ff ff call 80101780 <iunlock>
iput(ip);
80101dc8: 89 34 24 mov %esi,(%esp)
80101dcb: e8 f0 f9 ff ff call 801017c0 <iput>
if(nameiparent){
iput(ip);
return 0;
}
return ip;
}
80101dd0: 83 c4 2c add $0x2c,%esp
iunlock(ip);
return ip;
}
if((next = dirlookup(ip, name, 0)) == 0){
iunlockput(ip);
return 0;
80101dd3: 31 c0 xor %eax,%eax
if(nameiparent){
iput(ip);
return 0;
}
return ip;
}
80101dd5: 5b pop %ebx
80101dd6: 5e pop %esi
80101dd7: 5f pop %edi
80101dd8: 5d pop %ebp
80101dd9: c3 ret
namex(char *path, int nameiparent, char *name)
{
struct inode *ip, *next;
if(*path == '/')
ip = iget(ROOTDEV, ROOTINO);
80101dda: ba 01 00 00 00 mov $0x1,%edx
80101ddf: b8 01 00 00 00 mov $0x1,%eax
80101de4: e8 17 f4 ff ff call 80101200 <iget>
80101de9: 89 c6 mov %eax,%esi
80101deb: e9 c3 fe ff ff jmp 80101cb3 <namex+0x43>
iunlockput(ip);
return 0;
}
if(nameiparent && *path == '\0'){
// Stop one level early.
iunlock(ip);
80101df0: 89 34 24 mov %esi,(%esp)
80101df3: e8 88 f9 ff ff call 80101780 <iunlock>
if(nameiparent){
iput(ip);
return 0;
}
return ip;
}
80101df8: 83 c4 2c add $0x2c,%esp
return 0;
}
if(nameiparent && *path == '\0'){
// Stop one level early.
iunlock(ip);
return ip;
80101dfb: 89 f0 mov %esi,%eax
if(nameiparent){
iput(ip);
return 0;
}
return ip;
}
80101dfd: 5b pop %ebx
80101dfe: 5e pop %esi
80101dff: 5f pop %edi
80101e00: 5d pop %ebp
80101e01: c3 ret
}
iunlockput(ip);
ip = next;
}
if(nameiparent){
iput(ip);
80101e02: 89 34 24 mov %esi,(%esp)
80101e05: e8 b6 f9 ff ff call 801017c0 <iput>
return 0;
80101e0a: 31 c0 xor %eax,%eax
80101e0c: eb aa jmp 80101db8 <namex+0x148>
80101e0e: 66 90 xchg %ax,%ax
80101e10 <dirlink>:
}
// Write a new directory entry (name, inum) into the directory dp.
int
dirlink(struct inode *dp, char *name, uint inum)
{
80101e10: 55 push %ebp
80101e11: 89 e5 mov %esp,%ebp
80101e13: 57 push %edi
80101e14: 56 push %esi
80101e15: 53 push %ebx
80101e16: 83 ec 2c sub $0x2c,%esp
80101e19: 8b 5d 08 mov 0x8(%ebp),%ebx
int off;
struct dirent de;
struct inode *ip;
// Check that name is not present.
if((ip = dirlookup(dp, name, 0)) != 0){
80101e1c: 8b 45 0c mov 0xc(%ebp),%eax
80101e1f: c7 44 24 08 00 00 00 movl $0x0,0x8(%esp)
80101e26: 00
80101e27: 89 1c 24 mov %ebx,(%esp)
80101e2a: 89 44 24 04 mov %eax,0x4(%esp)
80101e2e: e8 7d fd ff ff call 80101bb0 <dirlookup>
80101e33: 85 c0 test %eax,%eax
80101e35: 0f 85 8b 00 00 00 jne 80101ec6 <dirlink+0xb6>
iput(ip);
return -1;
}
// Look for an empty dirent.
for(off = 0; off < dp->size; off += sizeof(de)){
80101e3b: 8b 43 58 mov 0x58(%ebx),%eax
80101e3e: 31 ff xor %edi,%edi
80101e40: 8d 75 d8 lea -0x28(%ebp),%esi
80101e43: 85 c0 test %eax,%eax
80101e45: 75 13 jne 80101e5a <dirlink+0x4a>
80101e47: eb 35 jmp 80101e7e <dirlink+0x6e>
80101e49: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80101e50: 8d 57 10 lea 0x10(%edi),%edx
80101e53: 39 53 58 cmp %edx,0x58(%ebx)
80101e56: 89 d7 mov %edx,%edi
80101e58: 76 24 jbe 80101e7e <dirlink+0x6e>
if(readi(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
80101e5a: c7 44 24 0c 10 00 00 movl $0x10,0xc(%esp)
80101e61: 00
80101e62: 89 7c 24 08 mov %edi,0x8(%esp)
80101e66: 89 74 24 04 mov %esi,0x4(%esp)
80101e6a: 89 1c 24 mov %ebx,(%esp)
80101e6d: e8 de fa ff ff call 80101950 <readi>
80101e72: 83 f8 10 cmp $0x10,%eax
80101e75: 75 5e jne 80101ed5 <dirlink+0xc5>
panic("dirlink read");
if(de.inum == 0)
80101e77: 66 83 7d d8 00 cmpw $0x0,-0x28(%ebp)
80101e7c: 75 d2 jne 80101e50 <dirlink+0x40>
break;
}
strncpy(de.name, name, DIRSIZ);
80101e7e: 8b 45 0c mov 0xc(%ebp),%eax
80101e81: c7 44 24 08 0e 00 00 movl $0xe,0x8(%esp)
80101e88: 00
80101e89: 89 44 24 04 mov %eax,0x4(%esp)
80101e8d: 8d 45 da lea -0x26(%ebp),%eax
80101e90: 89 04 24 mov %eax,(%esp)
80101e93: e8 68 25 00 00 call 80104400 <strncpy>
de.inum = inum;
80101e98: 8b 45 10 mov 0x10(%ebp),%eax
if(writei(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
80101e9b: c7 44 24 0c 10 00 00 movl $0x10,0xc(%esp)
80101ea2: 00
80101ea3: 89 7c 24 08 mov %edi,0x8(%esp)
80101ea7: 89 74 24 04 mov %esi,0x4(%esp)
80101eab: 89 1c 24 mov %ebx,(%esp)
if(de.inum == 0)
break;
}
strncpy(de.name, name, DIRSIZ);
de.inum = inum;
80101eae: 66 89 45 d8 mov %ax,-0x28(%ebp)
if(writei(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
80101eb2: e8 99 fb ff ff call 80101a50 <writei>
80101eb7: 83 f8 10 cmp $0x10,%eax
80101eba: 75 25 jne 80101ee1 <dirlink+0xd1>
panic("dirlink");
return 0;
80101ebc: 31 c0 xor %eax,%eax
}
80101ebe: 83 c4 2c add $0x2c,%esp
80101ec1: 5b pop %ebx
80101ec2: 5e pop %esi
80101ec3: 5f pop %edi
80101ec4: 5d pop %ebp
80101ec5: c3 ret
struct dirent de;
struct inode *ip;
// Check that name is not present.
if((ip = dirlookup(dp, name, 0)) != 0){
iput(ip);
80101ec6: 89 04 24 mov %eax,(%esp)
80101ec9: e8 f2 f8 ff ff call 801017c0 <iput>
return -1;
80101ece: b8 ff ff ff ff mov $0xffffffff,%eax
80101ed3: eb e9 jmp 80101ebe <dirlink+0xae>
}
// Look for an empty dirent.
for(off = 0; off < dp->size; off += sizeof(de)){
if(readi(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
panic("dirlink read");
80101ed5: c7 04 24 08 6f 10 80 movl $0x80106f08,(%esp)
80101edc: e8 7f e4 ff ff call 80100360 <panic>
}
strncpy(de.name, name, DIRSIZ);
de.inum = inum;
if(writei(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
panic("dirlink");
80101ee1: c7 04 24 06 75 10 80 movl $0x80107506,(%esp)
80101ee8: e8 73 e4 ff ff call 80100360 <panic>
80101eed: 8d 76 00 lea 0x0(%esi),%esi
80101ef0 <namei>:
return ip;
}
struct inode*
namei(char *path)
{
80101ef0: 55 push %ebp
char name[DIRSIZ];
return namex(path, 0, name);
80101ef1: 31 d2 xor %edx,%edx
return ip;
}
struct inode*
namei(char *path)
{
80101ef3: 89 e5 mov %esp,%ebp
80101ef5: 83 ec 18 sub $0x18,%esp
char name[DIRSIZ];
return namex(path, 0, name);
80101ef8: 8b 45 08 mov 0x8(%ebp),%eax
80101efb: 8d 4d ea lea -0x16(%ebp),%ecx
80101efe: e8 6d fd ff ff call 80101c70 <namex>
}
80101f03: c9 leave
80101f04: c3 ret
80101f05: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80101f09: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80101f10 <nameiparent>:
struct inode*
nameiparent(char *path, char *name)
{
80101f10: 55 push %ebp
return namex(path, 1, name);
80101f11: ba 01 00 00 00 mov $0x1,%edx
return namex(path, 0, name);
}
struct inode*
nameiparent(char *path, char *name)
{
80101f16: 89 e5 mov %esp,%ebp
return namex(path, 1, name);
80101f18: 8b 4d 0c mov 0xc(%ebp),%ecx
80101f1b: 8b 45 08 mov 0x8(%ebp),%eax
}
80101f1e: 5d pop %ebp
}
struct inode*
nameiparent(char *path, char *name)
{
return namex(path, 1, name);
80101f1f: e9 4c fd ff ff jmp 80101c70 <namex>
80101f24: 66 90 xchg %ax,%ax
80101f26: 66 90 xchg %ax,%ax
80101f28: 66 90 xchg %ax,%ax
80101f2a: 66 90 xchg %ax,%ax
80101f2c: 66 90 xchg %ax,%ax
80101f2e: 66 90 xchg %ax,%ax
80101f30 <idestart>:
}
// Start the request for b. Caller must hold idelock.
static void
idestart(struct buf *b)
{
80101f30: 55 push %ebp
80101f31: 89 e5 mov %esp,%ebp
80101f33: 56 push %esi
80101f34: 89 c6 mov %eax,%esi
80101f36: 53 push %ebx
80101f37: 83 ec 10 sub $0x10,%esp
if(b == 0)
80101f3a: 85 c0 test %eax,%eax
80101f3c: 0f 84 99 00 00 00 je 80101fdb <idestart+0xab>
panic("idestart");
if(b->blockno >= FSSIZE)
80101f42: 8b 48 08 mov 0x8(%eax),%ecx
80101f45: 81 f9 e7 03 00 00 cmp $0x3e7,%ecx
80101f4b: 0f 87 7e 00 00 00 ja 80101fcf <idestart+0x9f>
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
80101f51: ba f7 01 00 00 mov $0x1f7,%edx
80101f56: 66 90 xchg %ax,%ax
80101f58: ec in (%dx),%al
static int
idewait(int checkerr)
{
int r;
while(((r = inb(0x1f7)) & (IDE_BSY|IDE_DRDY)) != IDE_DRDY)
80101f59: 83 e0 c0 and $0xffffffc0,%eax
80101f5c: 3c 40 cmp $0x40,%al
80101f5e: 75 f8 jne 80101f58 <idestart+0x28>
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
80101f60: 31 db xor %ebx,%ebx
80101f62: ba f6 03 00 00 mov $0x3f6,%edx
80101f67: 89 d8 mov %ebx,%eax
80101f69: ee out %al,(%dx)
80101f6a: ba f2 01 00 00 mov $0x1f2,%edx
80101f6f: b8 01 00 00 00 mov $0x1,%eax
80101f74: ee out %al,(%dx)
80101f75: 0f b6 c1 movzbl %cl,%eax
80101f78: b2 f3 mov $0xf3,%dl
80101f7a: ee out %al,(%dx)
idewait(0);
outb(0x3f6, 0); // generate interrupt
outb(0x1f2, sector_per_block); // number of sectors
outb(0x1f3, sector & 0xff);
outb(0x1f4, (sector >> 8) & 0xff);
80101f7b: 89 c8 mov %ecx,%eax
80101f7d: b2 f4 mov $0xf4,%dl
80101f7f: c1 f8 08 sar $0x8,%eax
80101f82: ee out %al,(%dx)
80101f83: b2 f5 mov $0xf5,%dl
80101f85: 89 d8 mov %ebx,%eax
80101f87: ee out %al,(%dx)
outb(0x1f5, (sector >> 16) & 0xff);
outb(0x1f6, 0xe0 | ((b->dev&1)<<4) | ((sector>>24)&0x0f));
80101f88: 0f b6 46 04 movzbl 0x4(%esi),%eax
80101f8c: b2 f6 mov $0xf6,%dl
80101f8e: 83 e0 01 and $0x1,%eax
80101f91: c1 e0 04 shl $0x4,%eax
80101f94: 83 c8 e0 or $0xffffffe0,%eax
80101f97: ee out %al,(%dx)
if(b->flags & B_DIRTY){
80101f98: f6 06 04 testb $0x4,(%esi)
80101f9b: 75 13 jne 80101fb0 <idestart+0x80>
80101f9d: ba f7 01 00 00 mov $0x1f7,%edx
80101fa2: b8 20 00 00 00 mov $0x20,%eax
80101fa7: ee out %al,(%dx)
outb(0x1f7, write_cmd);
outsl(0x1f0, b->data, BSIZE/4);
} else {
outb(0x1f7, read_cmd);
}
}
80101fa8: 83 c4 10 add $0x10,%esp
80101fab: 5b pop %ebx
80101fac: 5e pop %esi
80101fad: 5d pop %ebp
80101fae: c3 ret
80101faf: 90 nop
80101fb0: b2 f7 mov $0xf7,%dl
80101fb2: b8 30 00 00 00 mov $0x30,%eax
80101fb7: ee out %al,(%dx)
}
static inline void
outsl(int port, const void *addr, int cnt)
{
asm volatile("cld; rep outsl" :
80101fb8: b9 80 00 00 00 mov $0x80,%ecx
outb(0x1f4, (sector >> 8) & 0xff);
outb(0x1f5, (sector >> 16) & 0xff);
outb(0x1f6, 0xe0 | ((b->dev&1)<<4) | ((sector>>24)&0x0f));
if(b->flags & B_DIRTY){
outb(0x1f7, write_cmd);
outsl(0x1f0, b->data, BSIZE/4);
80101fbd: 83 c6 5c add $0x5c,%esi
80101fc0: ba f0 01 00 00 mov $0x1f0,%edx
80101fc5: fc cld
80101fc6: f3 6f rep outsl %ds:(%esi),(%dx)
} else {
outb(0x1f7, read_cmd);
}
}
80101fc8: 83 c4 10 add $0x10,%esp
80101fcb: 5b pop %ebx
80101fcc: 5e pop %esi
80101fcd: 5d pop %ebp
80101fce: c3 ret
idestart(struct buf *b)
{
if(b == 0)
panic("idestart");
if(b->blockno >= FSSIZE)
panic("incorrect blockno");
80101fcf: c7 04 24 74 6f 10 80 movl $0x80106f74,(%esp)
80101fd6: e8 85 e3 ff ff call 80100360 <panic>
// Start the request for b. Caller must hold idelock.
static void
idestart(struct buf *b)
{
if(b == 0)
panic("idestart");
80101fdb: c7 04 24 6b 6f 10 80 movl $0x80106f6b,(%esp)
80101fe2: e8 79 e3 ff ff call 80100360 <panic>
80101fe7: 89 f6 mov %esi,%esi
80101fe9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80101ff0 <ideinit>:
return 0;
}
void
ideinit(void)
{
80101ff0: 55 push %ebp
80101ff1: 89 e5 mov %esp,%ebp
80101ff3: 83 ec 18 sub $0x18,%esp
int i;
initlock(&idelock, "ide");
80101ff6: c7 44 24 04 86 6f 10 movl $0x80106f86,0x4(%esp)
80101ffd: 80
80101ffe: c7 04 24 80 a5 10 80 movl $0x8010a580,(%esp)
80102005: e8 36 20 00 00 call 80104040 <initlock>
ioapicenable(IRQ_IDE, ncpu - 1);
8010200a: a1 00 2d 11 80 mov 0x80112d00,%eax
8010200f: c7 04 24 0e 00 00 00 movl $0xe,(%esp)
80102016: 83 e8 01 sub $0x1,%eax
80102019: 89 44 24 04 mov %eax,0x4(%esp)
8010201d: e8 7e 02 00 00 call 801022a0 <ioapicenable>
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
80102022: ba f7 01 00 00 mov $0x1f7,%edx
80102027: 90 nop
80102028: ec in (%dx),%al
static int
idewait(int checkerr)
{
int r;
while(((r = inb(0x1f7)) & (IDE_BSY|IDE_DRDY)) != IDE_DRDY)
80102029: 83 e0 c0 and $0xffffffc0,%eax
8010202c: 3c 40 cmp $0x40,%al
8010202e: 75 f8 jne 80102028 <ideinit+0x38>
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
80102030: ba f6 01 00 00 mov $0x1f6,%edx
80102035: b8 f0 ff ff ff mov $0xfffffff0,%eax
8010203a: ee out %al,(%dx)
8010203b: b9 e8 03 00 00 mov $0x3e8,%ecx
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
80102040: b2 f7 mov $0xf7,%dl
80102042: eb 09 jmp 8010204d <ideinit+0x5d>
80102044: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
ioapicenable(IRQ_IDE, ncpu - 1);
idewait(0);
// Check if disk 1 is present
outb(0x1f6, 0xe0 | (1<<4));
for(i=0; i<1000; i++){
80102048: 83 e9 01 sub $0x1,%ecx
8010204b: 74 0f je 8010205c <ideinit+0x6c>
8010204d: ec in (%dx),%al
if(inb(0x1f7) != 0){
8010204e: 84 c0 test %al,%al
80102050: 74 f6 je 80102048 <ideinit+0x58>
havedisk1 = 1;
80102052: c7 05 60 a5 10 80 01 movl $0x1,0x8010a560
80102059: 00 00 00
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
8010205c: ba f6 01 00 00 mov $0x1f6,%edx
80102061: b8 e0 ff ff ff mov $0xffffffe0,%eax
80102066: ee out %al,(%dx)
}
}
// Switch back to disk 0.
outb(0x1f6, 0xe0 | (0<<4));
}
80102067: c9 leave
80102068: c3 ret
80102069: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80102070 <ideintr>:
}
// Interrupt handler.
void
ideintr(void)
{
80102070: 55 push %ebp
80102071: 89 e5 mov %esp,%ebp
80102073: 57 push %edi
80102074: 56 push %esi
80102075: 53 push %ebx
80102076: 83 ec 1c sub $0x1c,%esp
struct buf *b;
// First queued buffer is the active request.
acquire(&idelock);
80102079: c7 04 24 80 a5 10 80 movl $0x8010a580,(%esp)
80102080: e8 ab 20 00 00 call 80104130 <acquire>
if((b = idequeue) == 0){
80102085: 8b 1d 64 a5 10 80 mov 0x8010a564,%ebx
8010208b: 85 db test %ebx,%ebx
8010208d: 74 30 je 801020bf <ideintr+0x4f>
release(&idelock);
return;
}
idequeue = b->qnext;
8010208f: 8b 43 58 mov 0x58(%ebx),%eax
80102092: a3 64 a5 10 80 mov %eax,0x8010a564
// Read data if needed.
if(!(b->flags & B_DIRTY) && idewait(1) >= 0)
80102097: 8b 33 mov (%ebx),%esi
80102099: f7 c6 04 00 00 00 test $0x4,%esi
8010209f: 74 37 je 801020d8 <ideintr+0x68>
insl(0x1f0, b->data, BSIZE/4);
// Wake process waiting for this buf.
b->flags |= B_VALID;
b->flags &= ~B_DIRTY;
801020a1: 83 e6 fb and $0xfffffffb,%esi
801020a4: 83 ce 02 or $0x2,%esi
801020a7: 89 33 mov %esi,(%ebx)
wakeup(b);
801020a9: 89 1c 24 mov %ebx,(%esp)
801020ac: e8 cf 1c 00 00 call 80103d80 <wakeup>
// Start disk on next buf in queue.
if(idequeue != 0)
801020b1: a1 64 a5 10 80 mov 0x8010a564,%eax
801020b6: 85 c0 test %eax,%eax
801020b8: 74 05 je 801020bf <ideintr+0x4f>
idestart(idequeue);
801020ba: e8 71 fe ff ff call 80101f30 <idestart>
// First queued buffer is the active request.
acquire(&idelock);
if((b = idequeue) == 0){
release(&idelock);
801020bf: c7 04 24 80 a5 10 80 movl $0x8010a580,(%esp)
801020c6: e8 55 21 00 00 call 80104220 <release>
// Start disk on next buf in queue.
if(idequeue != 0)
idestart(idequeue);
release(&idelock);
}
801020cb: 83 c4 1c add $0x1c,%esp
801020ce: 5b pop %ebx
801020cf: 5e pop %esi
801020d0: 5f pop %edi
801020d1: 5d pop %ebp
801020d2: c3 ret
801020d3: 90 nop
801020d4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
801020d8: ba f7 01 00 00 mov $0x1f7,%edx
801020dd: 8d 76 00 lea 0x0(%esi),%esi
801020e0: ec in (%dx),%al
static int
idewait(int checkerr)
{
int r;
while(((r = inb(0x1f7)) & (IDE_BSY|IDE_DRDY)) != IDE_DRDY)
801020e1: 89 c1 mov %eax,%ecx
801020e3: 83 e1 c0 and $0xffffffc0,%ecx
801020e6: 80 f9 40 cmp $0x40,%cl
801020e9: 75 f5 jne 801020e0 <ideintr+0x70>
;
if(checkerr && (r & (IDE_DF|IDE_ERR)) != 0)
801020eb: a8 21 test $0x21,%al
801020ed: 75 b2 jne 801020a1 <ideintr+0x31>
}
idequeue = b->qnext;
// Read data if needed.
if(!(b->flags & B_DIRTY) && idewait(1) >= 0)
insl(0x1f0, b->data, BSIZE/4);
801020ef: 8d 7b 5c lea 0x5c(%ebx),%edi
}
static inline void
insl(int port, void *addr, int cnt)
{
asm volatile("cld; rep insl" :
801020f2: b9 80 00 00 00 mov $0x80,%ecx
801020f7: ba f0 01 00 00 mov $0x1f0,%edx
801020fc: fc cld
801020fd: f3 6d rep insl (%dx),%es:(%edi)
801020ff: 8b 33 mov (%ebx),%esi
80102101: eb 9e jmp 801020a1 <ideintr+0x31>
80102103: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80102109: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80102110 <iderw>:
// Sync buf with disk.
// If B_DIRTY is set, write buf to disk, clear B_DIRTY, set B_VALID.
// Else if B_VALID is not set, read buf from disk, set B_VALID.
void
iderw(struct buf *b)
{
80102110: 55 push %ebp
80102111: 89 e5 mov %esp,%ebp
80102113: 53 push %ebx
80102114: 83 ec 14 sub $0x14,%esp
80102117: 8b 5d 08 mov 0x8(%ebp),%ebx
struct buf **pp;
if(!holdingsleep(&b->lock))
8010211a: 8d 43 0c lea 0xc(%ebx),%eax
8010211d: 89 04 24 mov %eax,(%esp)
80102120: e8 eb 1e 00 00 call 80104010 <holdingsleep>
80102125: 85 c0 test %eax,%eax
80102127: 0f 84 9e 00 00 00 je 801021cb <iderw+0xbb>
panic("iderw: buf not locked");
if((b->flags & (B_VALID|B_DIRTY)) == B_VALID)
8010212d: 8b 03 mov (%ebx),%eax
8010212f: 83 e0 06 and $0x6,%eax
80102132: 83 f8 02 cmp $0x2,%eax
80102135: 0f 84 a8 00 00 00 je 801021e3 <iderw+0xd3>
panic("iderw: nothing to do");
if(b->dev != 0 && !havedisk1)
8010213b: 8b 53 04 mov 0x4(%ebx),%edx
8010213e: 85 d2 test %edx,%edx
80102140: 74 0d je 8010214f <iderw+0x3f>
80102142: a1 60 a5 10 80 mov 0x8010a560,%eax
80102147: 85 c0 test %eax,%eax
80102149: 0f 84 88 00 00 00 je 801021d7 <iderw+0xc7>
panic("iderw: ide disk 1 not present");
acquire(&idelock); //DOC:acquire-lock
8010214f: c7 04 24 80 a5 10 80 movl $0x8010a580,(%esp)
80102156: e8 d5 1f 00 00 call 80104130 <acquire>
// Append b to idequeue.
b->qnext = 0;
for(pp=&idequeue; *pp; pp=&(*pp)->qnext) //DOC:insert-queue
8010215b: a1 64 a5 10 80 mov 0x8010a564,%eax
panic("iderw: ide disk 1 not present");
acquire(&idelock); //DOC:acquire-lock
// Append b to idequeue.
b->qnext = 0;
80102160: c7 43 58 00 00 00 00 movl $0x0,0x58(%ebx)
for(pp=&idequeue; *pp; pp=&(*pp)->qnext) //DOC:insert-queue
80102167: 85 c0 test %eax,%eax
80102169: 75 07 jne 80102172 <iderw+0x62>
8010216b: eb 4e jmp 801021bb <iderw+0xab>
8010216d: 8d 76 00 lea 0x0(%esi),%esi
80102170: 89 d0 mov %edx,%eax
80102172: 8b 50 58 mov 0x58(%eax),%edx
80102175: 85 d2 test %edx,%edx
80102177: 75 f7 jne 80102170 <iderw+0x60>
80102179: 83 c0 58 add $0x58,%eax
;
*pp = b;
8010217c: 89 18 mov %ebx,(%eax)
// Start disk if necessary.
if(idequeue == b)
8010217e: 39 1d 64 a5 10 80 cmp %ebx,0x8010a564
80102184: 74 3c je 801021c2 <iderw+0xb2>
idestart(b);
// Wait for request to finish.
while((b->flags & (B_VALID|B_DIRTY)) != B_VALID){
80102186: 8b 03 mov (%ebx),%eax
80102188: 83 e0 06 and $0x6,%eax
8010218b: 83 f8 02 cmp $0x2,%eax
8010218e: 74 1a je 801021aa <iderw+0x9a>
sleep(b, &idelock);
80102190: c7 44 24 04 80 a5 10 movl $0x8010a580,0x4(%esp)
80102197: 80
80102198: 89 1c 24 mov %ebx,(%esp)
8010219b: e8 50 1a 00 00 call 80103bf0 <sleep>
// Start disk if necessary.
if(idequeue == b)
idestart(b);
// Wait for request to finish.
while((b->flags & (B_VALID|B_DIRTY)) != B_VALID){
801021a0: 8b 13 mov (%ebx),%edx
801021a2: 83 e2 06 and $0x6,%edx
801021a5: 83 fa 02 cmp $0x2,%edx
801021a8: 75 e6 jne 80102190 <iderw+0x80>
sleep(b, &idelock);
}
release(&idelock);
801021aa: c7 45 08 80 a5 10 80 movl $0x8010a580,0x8(%ebp)
}
801021b1: 83 c4 14 add $0x14,%esp
801021b4: 5b pop %ebx
801021b5: 5d pop %ebp
while((b->flags & (B_VALID|B_DIRTY)) != B_VALID){
sleep(b, &idelock);
}
release(&idelock);
801021b6: e9 65 20 00 00 jmp 80104220 <release>
acquire(&idelock); //DOC:acquire-lock
// Append b to idequeue.
b->qnext = 0;
for(pp=&idequeue; *pp; pp=&(*pp)->qnext) //DOC:insert-queue
801021bb: b8 64 a5 10 80 mov $0x8010a564,%eax
801021c0: eb ba jmp 8010217c <iderw+0x6c>
;
*pp = b;
// Start disk if necessary.
if(idequeue == b)
idestart(b);
801021c2: 89 d8 mov %ebx,%eax
801021c4: e8 67 fd ff ff call 80101f30 <idestart>
801021c9: eb bb jmp 80102186 <iderw+0x76>
iderw(struct buf *b)
{
struct buf **pp;
if(!holdingsleep(&b->lock))
panic("iderw: buf not locked");
801021cb: c7 04 24 8a 6f 10 80 movl $0x80106f8a,(%esp)
801021d2: e8 89 e1 ff ff call 80100360 <panic>
if((b->flags & (B_VALID|B_DIRTY)) == B_VALID)
panic("iderw: nothing to do");
if(b->dev != 0 && !havedisk1)
panic("iderw: ide disk 1 not present");
801021d7: c7 04 24 b5 6f 10 80 movl $0x80106fb5,(%esp)
801021de: e8 7d e1 ff ff call 80100360 <panic>
struct buf **pp;
if(!holdingsleep(&b->lock))
panic("iderw: buf not locked");
if((b->flags & (B_VALID|B_DIRTY)) == B_VALID)
panic("iderw: nothing to do");
801021e3: c7 04 24 a0 6f 10 80 movl $0x80106fa0,(%esp)
801021ea: e8 71 e1 ff ff call 80100360 <panic>
801021ef: 90 nop
801021f0 <ioapicinit>:
ioapic->data = data;
}
void
ioapicinit(void)
{
801021f0: 55 push %ebp
801021f1: 89 e5 mov %esp,%ebp
801021f3: 56 push %esi
801021f4: 53 push %ebx
801021f5: 83 ec 10 sub $0x10,%esp
int i, id, maxintr;
ioapic = (volatile struct ioapic*)IOAPIC;
801021f8: c7 05 34 26 11 80 00 movl $0xfec00000,0x80112634
801021ff: 00 c0 fe
};
static uint
ioapicread(int reg)
{
ioapic->reg = reg;
80102202: c7 05 00 00 c0 fe 01 movl $0x1,0xfec00000
80102209: 00 00 00
return ioapic->data;
8010220c: 8b 15 34 26 11 80 mov 0x80112634,%edx
80102212: 8b 42 10 mov 0x10(%edx),%eax
};
static uint
ioapicread(int reg)
{
ioapic->reg = reg;
80102215: c7 02 00 00 00 00 movl $0x0,(%edx)
return ioapic->data;
8010221b: 8b 1d 34 26 11 80 mov 0x80112634,%ebx
int i, id, maxintr;
ioapic = (volatile struct ioapic*)IOAPIC;
maxintr = (ioapicread(REG_VER) >> 16) & 0xFF;
id = ioapicread(REG_ID) >> 24;
if(id != ioapicid)
80102221: 0f b6 15 60 27 11 80 movzbl 0x80112760,%edx
ioapicinit(void)
{
int i, id, maxintr;
ioapic = (volatile struct ioapic*)IOAPIC;
maxintr = (ioapicread(REG_VER) >> 16) & 0xFF;
80102228: c1 e8 10 shr $0x10,%eax
8010222b: 0f b6 f0 movzbl %al,%esi
static uint
ioapicread(int reg)
{
ioapic->reg = reg;
return ioapic->data;
8010222e: 8b 43 10 mov 0x10(%ebx),%eax
{
int i, id, maxintr;
ioapic = (volatile struct ioapic*)IOAPIC;
maxintr = (ioapicread(REG_VER) >> 16) & 0xFF;
id = ioapicread(REG_ID) >> 24;
80102231: c1 e8 18 shr $0x18,%eax
if(id != ioapicid)
80102234: 39 c2 cmp %eax,%edx
80102236: 74 12 je 8010224a <ioapicinit+0x5a>
cprintf("ioapicinit: id isn't equal to ioapicid; not a MP\n");
80102238: c7 04 24 d4 6f 10 80 movl $0x80106fd4,(%esp)
8010223f: e8 0c e4 ff ff call 80100650 <cprintf>
80102244: 8b 1d 34 26 11 80 mov 0x80112634,%ebx
8010224a: ba 10 00 00 00 mov $0x10,%edx
8010224f: 31 c0 xor %eax,%eax
80102251: eb 07 jmp 8010225a <ioapicinit+0x6a>
80102253: 90 nop
80102254: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80102258: 89 cb mov %ecx,%ebx
}
static void
ioapicwrite(int reg, uint data)
{
ioapic->reg = reg;
8010225a: 89 13 mov %edx,(%ebx)
ioapic->data = data;
8010225c: 8b 1d 34 26 11 80 mov 0x80112634,%ebx
80102262: 8d 48 20 lea 0x20(%eax),%ecx
cprintf("ioapicinit: id isn't equal to ioapicid; not a MP\n");
// Mark all interrupts edge-triggered, active high, disabled,
// and not routed to any CPUs.
for(i = 0; i <= maxintr; i++){
ioapicwrite(REG_TABLE+2*i, INT_DISABLED | (T_IRQ0 + i));
80102265: 81 c9 00 00 01 00 or $0x10000,%ecx
if(id != ioapicid)
cprintf("ioapicinit: id isn't equal to ioapicid; not a MP\n");
// Mark all interrupts edge-triggered, active high, disabled,
// and not routed to any CPUs.
for(i = 0; i <= maxintr; i++){
8010226b: 83 c0 01 add $0x1,%eax
static void
ioapicwrite(int reg, uint data)
{
ioapic->reg = reg;
ioapic->data = data;
8010226e: 89 4b 10 mov %ecx,0x10(%ebx)
80102271: 8d 4a 01 lea 0x1(%edx),%ecx
80102274: 83 c2 02 add $0x2,%edx
}
static void
ioapicwrite(int reg, uint data)
{
ioapic->reg = reg;
80102277: 89 0b mov %ecx,(%ebx)
ioapic->data = data;
80102279: 8b 0d 34 26 11 80 mov 0x80112634,%ecx
if(id != ioapicid)
cprintf("ioapicinit: id isn't equal to ioapicid; not a MP\n");
// Mark all interrupts edge-triggered, active high, disabled,
// and not routed to any CPUs.
for(i = 0; i <= maxintr; i++){
8010227f: 39 c6 cmp %eax,%esi
static void
ioapicwrite(int reg, uint data)
{
ioapic->reg = reg;
ioapic->data = data;
80102281: c7 41 10 00 00 00 00 movl $0x0,0x10(%ecx)
if(id != ioapicid)
cprintf("ioapicinit: id isn't equal to ioapicid; not a MP\n");
// Mark all interrupts edge-triggered, active high, disabled,
// and not routed to any CPUs.
for(i = 0; i <= maxintr; i++){
80102288: 7d ce jge 80102258 <ioapicinit+0x68>
ioapicwrite(REG_TABLE+2*i, INT_DISABLED | (T_IRQ0 + i));
ioapicwrite(REG_TABLE+2*i+1, 0);
}
}
8010228a: 83 c4 10 add $0x10,%esp
8010228d: 5b pop %ebx
8010228e: 5e pop %esi
8010228f: 5d pop %ebp
80102290: c3 ret
80102291: eb 0d jmp 801022a0 <ioapicenable>
80102293: 90 nop
80102294: 90 nop
80102295: 90 nop
80102296: 90 nop
80102297: 90 nop
80102298: 90 nop
80102299: 90 nop
8010229a: 90 nop
8010229b: 90 nop
8010229c: 90 nop
8010229d: 90 nop
8010229e: 90 nop
8010229f: 90 nop
801022a0 <ioapicenable>:
void
ioapicenable(int irq, int cpunum)
{
801022a0: 55 push %ebp
801022a1: 89 e5 mov %esp,%ebp
801022a3: 8b 55 08 mov 0x8(%ebp),%edx
801022a6: 53 push %ebx
801022a7: 8b 45 0c mov 0xc(%ebp),%eax
// Mark interrupt edge-triggered, active high,
// enabled, and routed to the given cpunum,
// which happens to be that cpu's APIC ID.
ioapicwrite(REG_TABLE+2*irq, T_IRQ0 + irq);
801022aa: 8d 5a 20 lea 0x20(%edx),%ebx
801022ad: 8d 4c 12 10 lea 0x10(%edx,%edx,1),%ecx
}
static void
ioapicwrite(int reg, uint data)
{
ioapic->reg = reg;
801022b1: 8b 15 34 26 11 80 mov 0x80112634,%edx
{
// Mark interrupt edge-triggered, active high,
// enabled, and routed to the given cpunum,
// which happens to be that cpu's APIC ID.
ioapicwrite(REG_TABLE+2*irq, T_IRQ0 + irq);
ioapicwrite(REG_TABLE+2*irq+1, cpunum << 24);
801022b7: c1 e0 18 shl $0x18,%eax
}
static void
ioapicwrite(int reg, uint data)
{
ioapic->reg = reg;
801022ba: 89 0a mov %ecx,(%edx)
ioapic->data = data;
801022bc: 8b 15 34 26 11 80 mov 0x80112634,%edx
{
// Mark interrupt edge-triggered, active high,
// enabled, and routed to the given cpunum,
// which happens to be that cpu's APIC ID.
ioapicwrite(REG_TABLE+2*irq, T_IRQ0 + irq);
ioapicwrite(REG_TABLE+2*irq+1, cpunum << 24);
801022c2: 83 c1 01 add $0x1,%ecx
static void
ioapicwrite(int reg, uint data)
{
ioapic->reg = reg;
ioapic->data = data;
801022c5: 89 5a 10 mov %ebx,0x10(%edx)
}
static void
ioapicwrite(int reg, uint data)
{
ioapic->reg = reg;
801022c8: 89 0a mov %ecx,(%edx)
ioapic->data = data;
801022ca: 8b 15 34 26 11 80 mov 0x80112634,%edx
801022d0: 89 42 10 mov %eax,0x10(%edx)
// Mark interrupt edge-triggered, active high,
// enabled, and routed to the given cpunum,
// which happens to be that cpu's APIC ID.
ioapicwrite(REG_TABLE+2*irq, T_IRQ0 + irq);
ioapicwrite(REG_TABLE+2*irq+1, cpunum << 24);
}
801022d3: 5b pop %ebx
801022d4: 5d pop %ebp
801022d5: c3 ret
801022d6: 66 90 xchg %ax,%ax
801022d8: 66 90 xchg %ax,%ax
801022da: 66 90 xchg %ax,%ax
801022dc: 66 90 xchg %ax,%ax
801022de: 66 90 xchg %ax,%ax
801022e0 <kfree>:
// which normally should have been returned by a
// call to kalloc(). (The exception is when
// initializing the allocator; see kinit above.)
void
kfree(char *v)
{
801022e0: 55 push %ebp
801022e1: 89 e5 mov %esp,%ebp
801022e3: 53 push %ebx
801022e4: 83 ec 14 sub $0x14,%esp
801022e7: 8b 5d 08 mov 0x8(%ebp),%ebx
struct run *r;
if((uint)v % PGSIZE || v < end || V2P(v) >= PHYSTOP)
801022ea: f7 c3 ff 0f 00 00 test $0xfff,%ebx
801022f0: 75 7c jne 8010236e <kfree+0x8e>
801022f2: 81 fb f4 58 11 80 cmp $0x801158f4,%ebx
801022f8: 72 74 jb 8010236e <kfree+0x8e>
801022fa: 8d 83 00 00 00 80 lea -0x80000000(%ebx),%eax
80102300: 3d ff ff ff 0d cmp $0xdffffff,%eax
80102305: 77 67 ja 8010236e <kfree+0x8e>
panic("kfree");
// Fill with junk to catch dangling refs.
memset(v, 1, PGSIZE);
80102307: c7 44 24 08 00 10 00 movl $0x1000,0x8(%esp)
8010230e: 00
8010230f: c7 44 24 04 01 00 00 movl $0x1,0x4(%esp)
80102316: 00
80102317: 89 1c 24 mov %ebx,(%esp)
8010231a: e8 51 1f 00 00 call 80104270 <memset>
if(kmem.use_lock)
8010231f: 8b 15 74 26 11 80 mov 0x80112674,%edx
80102325: 85 d2 test %edx,%edx
80102327: 75 37 jne 80102360 <kfree+0x80>
acquire(&kmem.lock);
r = (struct run*)v;
r->next = kmem.freelist;
80102329: a1 78 26 11 80 mov 0x80112678,%eax
8010232e: 89 03 mov %eax,(%ebx)
kmem.freelist = r;
if(kmem.use_lock)
80102330: a1 74 26 11 80 mov 0x80112674,%eax
if(kmem.use_lock)
acquire(&kmem.lock);
r = (struct run*)v;
r->next = kmem.freelist;
kmem.freelist = r;
80102335: 89 1d 78 26 11 80 mov %ebx,0x80112678
if(kmem.use_lock)
8010233b: 85 c0 test %eax,%eax
8010233d: 75 09 jne 80102348 <kfree+0x68>
release(&kmem.lock);
}
8010233f: 83 c4 14 add $0x14,%esp
80102342: 5b pop %ebx
80102343: 5d pop %ebp
80102344: c3 ret
80102345: 8d 76 00 lea 0x0(%esi),%esi
acquire(&kmem.lock);
r = (struct run*)v;
r->next = kmem.freelist;
kmem.freelist = r;
if(kmem.use_lock)
release(&kmem.lock);
80102348: c7 45 08 40 26 11 80 movl $0x80112640,0x8(%ebp)
}
8010234f: 83 c4 14 add $0x14,%esp
80102352: 5b pop %ebx
80102353: 5d pop %ebp
acquire(&kmem.lock);
r = (struct run*)v;
r->next = kmem.freelist;
kmem.freelist = r;
if(kmem.use_lock)
release(&kmem.lock);
80102354: e9 c7 1e 00 00 jmp 80104220 <release>
80102359: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
// Fill with junk to catch dangling refs.
memset(v, 1, PGSIZE);
if(kmem.use_lock)
acquire(&kmem.lock);
80102360: c7 04 24 40 26 11 80 movl $0x80112640,(%esp)
80102367: e8 c4 1d 00 00 call 80104130 <acquire>
8010236c: eb bb jmp 80102329 <kfree+0x49>
kfree(char *v)
{
struct run *r;
if((uint)v % PGSIZE || v < end || V2P(v) >= PHYSTOP)
panic("kfree");
8010236e: c7 04 24 06 70 10 80 movl $0x80107006,(%esp)
80102375: e8 e6 df ff ff call 80100360 <panic>
8010237a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80102380 <freerange>:
kmem.use_lock = 1;
}
void
freerange(void *vstart, void *vend)
{
80102380: 55 push %ebp
80102381: 89 e5 mov %esp,%ebp
80102383: 56 push %esi
80102384: 53 push %ebx
80102385: 83 ec 10 sub $0x10,%esp
char *p;
p = (char*)PGROUNDUP((uint)vstart);
80102388: 8b 45 08 mov 0x8(%ebp),%eax
kmem.use_lock = 1;
}
void
freerange(void *vstart, void *vend)
{
8010238b: 8b 75 0c mov 0xc(%ebp),%esi
char *p;
p = (char*)PGROUNDUP((uint)vstart);
8010238e: 8d 90 ff 0f 00 00 lea 0xfff(%eax),%edx
80102394: 81 e2 00 f0 ff ff and $0xfffff000,%edx
for(; p + PGSIZE <= (char*)vend; p += PGSIZE)
8010239a: 8d 9a 00 10 00 00 lea 0x1000(%edx),%ebx
801023a0: 39 de cmp %ebx,%esi
801023a2: 73 08 jae 801023ac <freerange+0x2c>
801023a4: eb 18 jmp 801023be <freerange+0x3e>
801023a6: 66 90 xchg %ax,%ax
801023a8: 89 da mov %ebx,%edx
801023aa: 89 c3 mov %eax,%ebx
kfree(p);
801023ac: 89 14 24 mov %edx,(%esp)
801023af: e8 2c ff ff ff call 801022e0 <kfree>
void
freerange(void *vstart, void *vend)
{
char *p;
p = (char*)PGROUNDUP((uint)vstart);
for(; p + PGSIZE <= (char*)vend; p += PGSIZE)
801023b4: 8d 83 00 10 00 00 lea 0x1000(%ebx),%eax
801023ba: 39 f0 cmp %esi,%eax
801023bc: 76 ea jbe 801023a8 <freerange+0x28>
kfree(p);
}
801023be: 83 c4 10 add $0x10,%esp
801023c1: 5b pop %ebx
801023c2: 5e pop %esi
801023c3: 5d pop %ebp
801023c4: c3 ret
801023c5: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
801023c9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801023d0 <kinit1>:
// the pages mapped by entrypgdir on free list.
// 2. main() calls kinit2() with the rest of the physical pages
// after installing a full page table that maps them on all cores.
void
kinit1(void *vstart, void *vend)
{
801023d0: 55 push %ebp
801023d1: 89 e5 mov %esp,%ebp
801023d3: 56 push %esi
801023d4: 53 push %ebx
801023d5: 83 ec 10 sub $0x10,%esp
801023d8: 8b 75 0c mov 0xc(%ebp),%esi
initlock(&kmem.lock, "kmem");
801023db: c7 44 24 04 0c 70 10 movl $0x8010700c,0x4(%esp)
801023e2: 80
801023e3: c7 04 24 40 26 11 80 movl $0x80112640,(%esp)
801023ea: e8 51 1c 00 00 call 80104040 <initlock>
void
freerange(void *vstart, void *vend)
{
char *p;
p = (char*)PGROUNDUP((uint)vstart);
801023ef: 8b 45 08 mov 0x8(%ebp),%eax
// after installing a full page table that maps them on all cores.
void
kinit1(void *vstart, void *vend)
{
initlock(&kmem.lock, "kmem");
kmem.use_lock = 0;
801023f2: c7 05 74 26 11 80 00 movl $0x0,0x80112674
801023f9: 00 00 00
void
freerange(void *vstart, void *vend)
{
char *p;
p = (char*)PGROUNDUP((uint)vstart);
801023fc: 8d 90 ff 0f 00 00 lea 0xfff(%eax),%edx
80102402: 81 e2 00 f0 ff ff and $0xfffff000,%edx
for(; p + PGSIZE <= (char*)vend; p += PGSIZE)
80102408: 8d 9a 00 10 00 00 lea 0x1000(%edx),%ebx
8010240e: 39 de cmp %ebx,%esi
80102410: 73 0a jae 8010241c <kinit1+0x4c>
80102412: eb 1a jmp 8010242e <kinit1+0x5e>
80102414: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80102418: 89 da mov %ebx,%edx
8010241a: 89 c3 mov %eax,%ebx
kfree(p);
8010241c: 89 14 24 mov %edx,(%esp)
8010241f: e8 bc fe ff ff call 801022e0 <kfree>
void
freerange(void *vstart, void *vend)
{
char *p;
p = (char*)PGROUNDUP((uint)vstart);
for(; p + PGSIZE <= (char*)vend; p += PGSIZE)
80102424: 8d 83 00 10 00 00 lea 0x1000(%ebx),%eax
8010242a: 39 c6 cmp %eax,%esi
8010242c: 73 ea jae 80102418 <kinit1+0x48>
kinit1(void *vstart, void *vend)
{
initlock(&kmem.lock, "kmem");
kmem.use_lock = 0;
freerange(vstart, vend);
}
8010242e: 83 c4 10 add $0x10,%esp
80102431: 5b pop %ebx
80102432: 5e pop %esi
80102433: 5d pop %ebp
80102434: c3 ret
80102435: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80102439: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80102440 <kinit2>:
void
kinit2(void *vstart, void *vend)
{
80102440: 55 push %ebp
80102441: 89 e5 mov %esp,%ebp
80102443: 56 push %esi
80102444: 53 push %ebx
80102445: 83 ec 10 sub $0x10,%esp
void
freerange(void *vstart, void *vend)
{
char *p;
p = (char*)PGROUNDUP((uint)vstart);
80102448: 8b 45 08 mov 0x8(%ebp),%eax
freerange(vstart, vend);
}
void
kinit2(void *vstart, void *vend)
{
8010244b: 8b 75 0c mov 0xc(%ebp),%esi
void
freerange(void *vstart, void *vend)
{
char *p;
p = (char*)PGROUNDUP((uint)vstart);
8010244e: 8d 90 ff 0f 00 00 lea 0xfff(%eax),%edx
80102454: 81 e2 00 f0 ff ff and $0xfffff000,%edx
for(; p + PGSIZE <= (char*)vend; p += PGSIZE)
8010245a: 8d 9a 00 10 00 00 lea 0x1000(%edx),%ebx
80102460: 39 de cmp %ebx,%esi
80102462: 73 08 jae 8010246c <kinit2+0x2c>
80102464: eb 18 jmp 8010247e <kinit2+0x3e>
80102466: 66 90 xchg %ax,%ax
80102468: 89 da mov %ebx,%edx
8010246a: 89 c3 mov %eax,%ebx
kfree(p);
8010246c: 89 14 24 mov %edx,(%esp)
8010246f: e8 6c fe ff ff call 801022e0 <kfree>
void
freerange(void *vstart, void *vend)
{
char *p;
p = (char*)PGROUNDUP((uint)vstart);
for(; p + PGSIZE <= (char*)vend; p += PGSIZE)
80102474: 8d 83 00 10 00 00 lea 0x1000(%ebx),%eax
8010247a: 39 c6 cmp %eax,%esi
8010247c: 73 ea jae 80102468 <kinit2+0x28>
void
kinit2(void *vstart, void *vend)
{
freerange(vstart, vend);
kmem.use_lock = 1;
8010247e: c7 05 74 26 11 80 01 movl $0x1,0x80112674
80102485: 00 00 00
}
80102488: 83 c4 10 add $0x10,%esp
8010248b: 5b pop %ebx
8010248c: 5e pop %esi
8010248d: 5d pop %ebp
8010248e: c3 ret
8010248f: 90 nop
80102490 <kalloc>:
// Allocate one 4096-byte page of physical memory.
// Returns a pointer that the kernel can use.
// Returns 0 if the memory cannot be allocated.
char*
kalloc(void)
{
80102490: 55 push %ebp
80102491: 89 e5 mov %esp,%ebp
80102493: 53 push %ebx
80102494: 83 ec 14 sub $0x14,%esp
struct run *r;
if(kmem.use_lock)
80102497: a1 74 26 11 80 mov 0x80112674,%eax
8010249c: 85 c0 test %eax,%eax
8010249e: 75 30 jne 801024d0 <kalloc+0x40>
acquire(&kmem.lock);
r = kmem.freelist;
801024a0: 8b 1d 78 26 11 80 mov 0x80112678,%ebx
if(r)
801024a6: 85 db test %ebx,%ebx
801024a8: 74 08 je 801024b2 <kalloc+0x22>
kmem.freelist = r->next;
801024aa: 8b 13 mov (%ebx),%edx
801024ac: 89 15 78 26 11 80 mov %edx,0x80112678
if(kmem.use_lock)
801024b2: 85 c0 test %eax,%eax
801024b4: 74 0c je 801024c2 <kalloc+0x32>
release(&kmem.lock);
801024b6: c7 04 24 40 26 11 80 movl $0x80112640,(%esp)
801024bd: e8 5e 1d 00 00 call 80104220 <release>
return (char*)r;
}
801024c2: 83 c4 14 add $0x14,%esp
801024c5: 89 d8 mov %ebx,%eax
801024c7: 5b pop %ebx
801024c8: 5d pop %ebp
801024c9: c3 ret
801024ca: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
kalloc(void)
{
struct run *r;
if(kmem.use_lock)
acquire(&kmem.lock);
801024d0: c7 04 24 40 26 11 80 movl $0x80112640,(%esp)
801024d7: e8 54 1c 00 00 call 80104130 <acquire>
801024dc: a1 74 26 11 80 mov 0x80112674,%eax
801024e1: eb bd jmp 801024a0 <kalloc+0x10>
801024e3: 66 90 xchg %ax,%ax
801024e5: 66 90 xchg %ax,%ax
801024e7: 66 90 xchg %ax,%ax
801024e9: 66 90 xchg %ax,%ax
801024eb: 66 90 xchg %ax,%ax
801024ed: 66 90 xchg %ax,%ax
801024ef: 90 nop
801024f0 <kbdgetc>:
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
801024f0: ba 64 00 00 00 mov $0x64,%edx
801024f5: ec in (%dx),%al
normalmap, shiftmap, ctlmap, ctlmap
};
uint st, data, c;
st = inb(KBSTATP);
if((st & KBS_DIB) == 0)
801024f6: a8 01 test $0x1,%al
801024f8: 0f 84 ba 00 00 00 je 801025b8 <kbdgetc+0xc8>
801024fe: b2 60 mov $0x60,%dl
80102500: ec in (%dx),%al
return -1;
data = inb(KBDATAP);
80102501: 0f b6 c8 movzbl %al,%ecx
if(data == 0xE0){
80102504: 81 f9 e0 00 00 00 cmp $0xe0,%ecx
8010250a: 0f 84 88 00 00 00 je 80102598 <kbdgetc+0xa8>
shift |= E0ESC;
return 0;
} else if(data & 0x80){
80102510: 84 c0 test %al,%al
80102512: 79 2c jns 80102540 <kbdgetc+0x50>
// Key released
data = (shift & E0ESC ? data : data & 0x7F);
80102514: 8b 15 b4 a5 10 80 mov 0x8010a5b4,%edx
8010251a: f6 c2 40 test $0x40,%dl
8010251d: 75 05 jne 80102524 <kbdgetc+0x34>
8010251f: 89 c1 mov %eax,%ecx
80102521: 83 e1 7f and $0x7f,%ecx
shift &= ~(shiftcode[data] | E0ESC);
80102524: 0f b6 81 40 71 10 80 movzbl -0x7fef8ec0(%ecx),%eax
8010252b: 83 c8 40 or $0x40,%eax
8010252e: 0f b6 c0 movzbl %al,%eax
80102531: f7 d0 not %eax
80102533: 21 d0 and %edx,%eax
80102535: a3 b4 a5 10 80 mov %eax,0x8010a5b4
return 0;
8010253a: 31 c0 xor %eax,%eax
8010253c: c3 ret
8010253d: 8d 76 00 lea 0x0(%esi),%esi
#include "defs.h"
#include "kbd.h"
int
kbdgetc(void)
{
80102540: 55 push %ebp
80102541: 89 e5 mov %esp,%ebp
80102543: 53 push %ebx
80102544: 8b 1d b4 a5 10 80 mov 0x8010a5b4,%ebx
} else if(data & 0x80){
// Key released
data = (shift & E0ESC ? data : data & 0x7F);
shift &= ~(shiftcode[data] | E0ESC);
return 0;
} else if(shift & E0ESC){
8010254a: f6 c3 40 test $0x40,%bl
8010254d: 74 09 je 80102558 <kbdgetc+0x68>
// Last character was an E0 escape; or with 0x80
data |= 0x80;
8010254f: 83 c8 80 or $0xffffff80,%eax
shift &= ~E0ESC;
80102552: 83 e3 bf and $0xffffffbf,%ebx
data = (shift & E0ESC ? data : data & 0x7F);
shift &= ~(shiftcode[data] | E0ESC);
return 0;
} else if(shift & E0ESC){
// Last character was an E0 escape; or with 0x80
data |= 0x80;
80102555: 0f b6 c8 movzbl %al,%ecx
shift &= ~E0ESC;
}
shift |= shiftcode[data];
80102558: 0f b6 91 40 71 10 80 movzbl -0x7fef8ec0(%ecx),%edx
shift ^= togglecode[data];
8010255f: 0f b6 81 40 70 10 80 movzbl -0x7fef8fc0(%ecx),%eax
// Last character was an E0 escape; or with 0x80
data |= 0x80;
shift &= ~E0ESC;
}
shift |= shiftcode[data];
80102566: 09 da or %ebx,%edx
shift ^= togglecode[data];
80102568: 31 c2 xor %eax,%edx
c = charcode[shift & (CTL | SHIFT)][data];
8010256a: 89 d0 mov %edx,%eax
8010256c: 83 e0 03 and $0x3,%eax
8010256f: 8b 04 85 20 70 10 80 mov -0x7fef8fe0(,%eax,4),%eax
data |= 0x80;
shift &= ~E0ESC;
}
shift |= shiftcode[data];
shift ^= togglecode[data];
80102576: 89 15 b4 a5 10 80 mov %edx,0x8010a5b4
c = charcode[shift & (CTL | SHIFT)][data];
if(shift & CAPSLOCK){
8010257c: 83 e2 08 and $0x8,%edx
shift &= ~E0ESC;
}
shift |= shiftcode[data];
shift ^= togglecode[data];
c = charcode[shift & (CTL | SHIFT)][data];
8010257f: 0f b6 04 08 movzbl (%eax,%ecx,1),%eax
if(shift & CAPSLOCK){
80102583: 74 0b je 80102590 <kbdgetc+0xa0>
if('a' <= c && c <= 'z')
80102585: 8d 50 9f lea -0x61(%eax),%edx
80102588: 83 fa 19 cmp $0x19,%edx
8010258b: 77 1b ja 801025a8 <kbdgetc+0xb8>
c += 'A' - 'a';
8010258d: 83 e8 20 sub $0x20,%eax
else if('A' <= c && c <= 'Z')
c += 'a' - 'A';
}
return c;
}
80102590: 5b pop %ebx
80102591: 5d pop %ebp
80102592: c3 ret
80102593: 90 nop
80102594: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
if((st & KBS_DIB) == 0)
return -1;
data = inb(KBDATAP);
if(data == 0xE0){
shift |= E0ESC;
80102598: 83 0d b4 a5 10 80 40 orl $0x40,0x8010a5b4
return 0;
8010259f: 31 c0 xor %eax,%eax
801025a1: c3 ret
801025a2: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
shift ^= togglecode[data];
c = charcode[shift & (CTL | SHIFT)][data];
if(shift & CAPSLOCK){
if('a' <= c && c <= 'z')
c += 'A' - 'a';
else if('A' <= c && c <= 'Z')
801025a8: 8d 48 bf lea -0x41(%eax),%ecx
c += 'a' - 'A';
801025ab: 8d 50 20 lea 0x20(%eax),%edx
801025ae: 83 f9 19 cmp $0x19,%ecx
801025b1: 0f 46 c2 cmovbe %edx,%eax
}
return c;
801025b4: eb da jmp 80102590 <kbdgetc+0xa0>
801025b6: 66 90 xchg %ax,%ax
};
uint st, data, c;
st = inb(KBSTATP);
if((st & KBS_DIB) == 0)
return -1;
801025b8: b8 ff ff ff ff mov $0xffffffff,%eax
801025bd: c3 ret
801025be: 66 90 xchg %ax,%ax
801025c0 <kbdintr>:
return c;
}
void
kbdintr(void)
{
801025c0: 55 push %ebp
801025c1: 89 e5 mov %esp,%ebp
801025c3: 83 ec 18 sub $0x18,%esp
consoleintr(kbdgetc);
801025c6: c7 04 24 f0 24 10 80 movl $0x801024f0,(%esp)
801025cd: e8 de e1 ff ff call 801007b0 <consoleintr>
}
801025d2: c9 leave
801025d3: c3 ret
801025d4: 66 90 xchg %ax,%ax
801025d6: 66 90 xchg %ax,%ax
801025d8: 66 90 xchg %ax,%ax
801025da: 66 90 xchg %ax,%ax
801025dc: 66 90 xchg %ax,%ax
801025de: 66 90 xchg %ax,%ax
801025e0 <fill_rtcdate>:
return inb(CMOS_RETURN);
}
static void fill_rtcdate(struct rtcdate *r)
{
801025e0: 55 push %ebp
801025e1: 89 c1 mov %eax,%ecx
801025e3: 89 e5 mov %esp,%ebp
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
801025e5: ba 70 00 00 00 mov $0x70,%edx
801025ea: 53 push %ebx
801025eb: 31 c0 xor %eax,%eax
801025ed: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
801025ee: bb 71 00 00 00 mov $0x71,%ebx
801025f3: 89 da mov %ebx,%edx
801025f5: ec in (%dx),%al
static uint cmos_read(uint reg)
{
outb(CMOS_PORT, reg);
microdelay(200);
return inb(CMOS_RETURN);
801025f6: 0f b6 c0 movzbl %al,%eax
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
801025f9: b2 70 mov $0x70,%dl
801025fb: 89 01 mov %eax,(%ecx)
801025fd: b8 02 00 00 00 mov $0x2,%eax
80102602: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
80102603: 89 da mov %ebx,%edx
80102605: ec in (%dx),%al
80102606: 0f b6 c0 movzbl %al,%eax
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
80102609: b2 70 mov $0x70,%dl
8010260b: 89 41 04 mov %eax,0x4(%ecx)
8010260e: b8 04 00 00 00 mov $0x4,%eax
80102613: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
80102614: 89 da mov %ebx,%edx
80102616: ec in (%dx),%al
80102617: 0f b6 c0 movzbl %al,%eax
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
8010261a: b2 70 mov $0x70,%dl
8010261c: 89 41 08 mov %eax,0x8(%ecx)
8010261f: b8 07 00 00 00 mov $0x7,%eax
80102624: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
80102625: 89 da mov %ebx,%edx
80102627: ec in (%dx),%al
80102628: 0f b6 c0 movzbl %al,%eax
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
8010262b: b2 70 mov $0x70,%dl
8010262d: 89 41 0c mov %eax,0xc(%ecx)
80102630: b8 08 00 00 00 mov $0x8,%eax
80102635: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
80102636: 89 da mov %ebx,%edx
80102638: ec in (%dx),%al
80102639: 0f b6 c0 movzbl %al,%eax
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
8010263c: b2 70 mov $0x70,%dl
8010263e: 89 41 10 mov %eax,0x10(%ecx)
80102641: b8 09 00 00 00 mov $0x9,%eax
80102646: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
80102647: 89 da mov %ebx,%edx
80102649: ec in (%dx),%al
8010264a: 0f b6 d8 movzbl %al,%ebx
8010264d: 89 59 14 mov %ebx,0x14(%ecx)
r->minute = cmos_read(MINS);
r->hour = cmos_read(HOURS);
r->day = cmos_read(DAY);
r->month = cmos_read(MONTH);
r->year = cmos_read(YEAR);
}
80102650: 5b pop %ebx
80102651: 5d pop %ebp
80102652: c3 ret
80102653: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80102659: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80102660 <lapicinit>:
}
void
lapicinit(void)
{
if(!lapic)
80102660: a1 7c 26 11 80 mov 0x8011267c,%eax
lapic[ID]; // wait for write to finish, by reading
}
void
lapicinit(void)
{
80102665: 55 push %ebp
80102666: 89 e5 mov %esp,%ebp
if(!lapic)
80102668: 85 c0 test %eax,%eax
8010266a: 0f 84 c0 00 00 00 je 80102730 <lapicinit+0xd0>
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
80102670: c7 80 f0 00 00 00 3f movl $0x13f,0xf0(%eax)
80102677: 01 00 00
lapic[ID]; // wait for write to finish, by reading
8010267a: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
8010267d: c7 80 e0 03 00 00 0b movl $0xb,0x3e0(%eax)
80102684: 00 00 00
lapic[ID]; // wait for write to finish, by reading
80102687: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
8010268a: c7 80 20 03 00 00 20 movl $0x20020,0x320(%eax)
80102691: 00 02 00
lapic[ID]; // wait for write to finish, by reading
80102694: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
80102697: c7 80 80 03 00 00 80 movl $0x989680,0x380(%eax)
8010269e: 96 98 00
lapic[ID]; // wait for write to finish, by reading
801026a1: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801026a4: c7 80 50 03 00 00 00 movl $0x10000,0x350(%eax)
801026ab: 00 01 00
lapic[ID]; // wait for write to finish, by reading
801026ae: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801026b1: c7 80 60 03 00 00 00 movl $0x10000,0x360(%eax)
801026b8: 00 01 00
lapic[ID]; // wait for write to finish, by reading
801026bb: 8b 50 20 mov 0x20(%eax),%edx
lapicw(LINT0, MASKED);
lapicw(LINT1, MASKED);
// Disable performance counter overflow interrupts
// on machines that provide that interrupt entry.
if(((lapic[VER]>>16) & 0xFF) >= 4)
801026be: 8b 50 30 mov 0x30(%eax),%edx
801026c1: c1 ea 10 shr $0x10,%edx
801026c4: 80 fa 03 cmp $0x3,%dl
801026c7: 77 6f ja 80102738 <lapicinit+0xd8>
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801026c9: c7 80 70 03 00 00 33 movl $0x33,0x370(%eax)
801026d0: 00 00 00
lapic[ID]; // wait for write to finish, by reading
801026d3: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801026d6: c7 80 80 02 00 00 00 movl $0x0,0x280(%eax)
801026dd: 00 00 00
lapic[ID]; // wait for write to finish, by reading
801026e0: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801026e3: c7 80 80 02 00 00 00 movl $0x0,0x280(%eax)
801026ea: 00 00 00
lapic[ID]; // wait for write to finish, by reading
801026ed: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801026f0: c7 80 b0 00 00 00 00 movl $0x0,0xb0(%eax)
801026f7: 00 00 00
lapic[ID]; // wait for write to finish, by reading
801026fa: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801026fd: c7 80 10 03 00 00 00 movl $0x0,0x310(%eax)
80102704: 00 00 00
lapic[ID]; // wait for write to finish, by reading
80102707: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
8010270a: c7 80 00 03 00 00 00 movl $0x88500,0x300(%eax)
80102711: 85 08 00
lapic[ID]; // wait for write to finish, by reading
80102714: 8b 50 20 mov 0x20(%eax),%edx
80102717: 90 nop
lapicw(EOI, 0);
// Send an Init Level De-Assert to synchronise arbitration ID's.
lapicw(ICRHI, 0);
lapicw(ICRLO, BCAST | INIT | LEVEL);
while(lapic[ICRLO] & DELIVS)
80102718: 8b 90 00 03 00 00 mov 0x300(%eax),%edx
8010271e: 80 e6 10 and $0x10,%dh
80102721: 75 f5 jne 80102718 <lapicinit+0xb8>
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
80102723: c7 80 80 00 00 00 00 movl $0x0,0x80(%eax)
8010272a: 00 00 00
lapic[ID]; // wait for write to finish, by reading
8010272d: 8b 40 20 mov 0x20(%eax),%eax
while(lapic[ICRLO] & DELIVS)
;
// Enable interrupts on the APIC (but not on the processor).
lapicw(TPR, 0);
}
80102730: 5d pop %ebp
80102731: c3 ret
80102732: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
80102738: c7 80 40 03 00 00 00 movl $0x10000,0x340(%eax)
8010273f: 00 01 00
lapic[ID]; // wait for write to finish, by reading
80102742: 8b 50 20 mov 0x20(%eax),%edx
80102745: eb 82 jmp 801026c9 <lapicinit+0x69>
80102747: 89 f6 mov %esi,%esi
80102749: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80102750 <lapicid>:
}
int
lapicid(void)
{
if (!lapic)
80102750: a1 7c 26 11 80 mov 0x8011267c,%eax
lapicw(TPR, 0);
}
int
lapicid(void)
{
80102755: 55 push %ebp
80102756: 89 e5 mov %esp,%ebp
if (!lapic)
80102758: 85 c0 test %eax,%eax
8010275a: 74 0c je 80102768 <lapicid+0x18>
return 0;
return lapic[ID] >> 24;
8010275c: 8b 40 20 mov 0x20(%eax),%eax
}
8010275f: 5d pop %ebp
int
lapicid(void)
{
if (!lapic)
return 0;
return lapic[ID] >> 24;
80102760: c1 e8 18 shr $0x18,%eax
}
80102763: c3 ret
80102764: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
int
lapicid(void)
{
if (!lapic)
return 0;
80102768: 31 c0 xor %eax,%eax
return lapic[ID] >> 24;
}
8010276a: 5d pop %ebp
8010276b: c3 ret
8010276c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80102770 <lapiceoi>:
// Acknowledge interrupt.
void
lapiceoi(void)
{
if(lapic)
80102770: a1 7c 26 11 80 mov 0x8011267c,%eax
}
// Acknowledge interrupt.
void
lapiceoi(void)
{
80102775: 55 push %ebp
80102776: 89 e5 mov %esp,%ebp
if(lapic)
80102778: 85 c0 test %eax,%eax
8010277a: 74 0d je 80102789 <lapiceoi+0x19>
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
8010277c: c7 80 b0 00 00 00 00 movl $0x0,0xb0(%eax)
80102783: 00 00 00
lapic[ID]; // wait for write to finish, by reading
80102786: 8b 40 20 mov 0x20(%eax),%eax
void
lapiceoi(void)
{
if(lapic)
lapicw(EOI, 0);
}
80102789: 5d pop %ebp
8010278a: c3 ret
8010278b: 90 nop
8010278c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80102790 <microdelay>:
// Spin for a given number of microseconds.
// On real hardware would want to tune this dynamically.
void
microdelay(int us)
{
80102790: 55 push %ebp
80102791: 89 e5 mov %esp,%ebp
}
80102793: 5d pop %ebp
80102794: c3 ret
80102795: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80102799: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801027a0 <lapicstartap>:
// Start additional processor running entry code at addr.
// See Appendix B of MultiProcessor Specification.
void
lapicstartap(uchar apicid, uint addr)
{
801027a0: 55 push %ebp
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
801027a1: ba 70 00 00 00 mov $0x70,%edx
801027a6: 89 e5 mov %esp,%ebp
801027a8: b8 0f 00 00 00 mov $0xf,%eax
801027ad: 53 push %ebx
801027ae: 8b 4d 08 mov 0x8(%ebp),%ecx
801027b1: 8b 5d 0c mov 0xc(%ebp),%ebx
801027b4: ee out %al,(%dx)
801027b5: b8 0a 00 00 00 mov $0xa,%eax
801027ba: b2 71 mov $0x71,%dl
801027bc: ee out %al,(%dx)
// and the warm reset vector (DWORD based at 40:67) to point at
// the AP startup code prior to the [universal startup algorithm]."
outb(CMOS_PORT, 0xF); // offset 0xF is shutdown code
outb(CMOS_PORT+1, 0x0A);
wrv = (ushort*)P2V((0x40<<4 | 0x67)); // Warm reset vector
wrv[0] = 0;
801027bd: 31 c0 xor %eax,%eax
801027bf: 66 a3 67 04 00 80 mov %ax,0x80000467
wrv[1] = addr >> 4;
801027c5: 89 d8 mov %ebx,%eax
801027c7: c1 e8 04 shr $0x4,%eax
801027ca: 66 a3 69 04 00 80 mov %ax,0x80000469
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801027d0: a1 7c 26 11 80 mov 0x8011267c,%eax
wrv[0] = 0;
wrv[1] = addr >> 4;
// "Universal startup algorithm."
// Send INIT (level-triggered) interrupt to reset other CPU.
lapicw(ICRHI, apicid<<24);
801027d5: c1 e1 18 shl $0x18,%ecx
// when it is in the halted state due to an INIT. So the second
// should be ignored, but it is part of the official Intel algorithm.
// Bochs complains about the second one. Too bad for Bochs.
for(i = 0; i < 2; i++){
lapicw(ICRHI, apicid<<24);
lapicw(ICRLO, STARTUP | (addr>>12));
801027d8: c1 eb 0c shr $0xc,%ebx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801027db: 89 88 10 03 00 00 mov %ecx,0x310(%eax)
lapic[ID]; // wait for write to finish, by reading
801027e1: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801027e4: c7 80 00 03 00 00 00 movl $0xc500,0x300(%eax)
801027eb: c5 00 00
lapic[ID]; // wait for write to finish, by reading
801027ee: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801027f1: c7 80 00 03 00 00 00 movl $0x8500,0x300(%eax)
801027f8: 85 00 00
lapic[ID]; // wait for write to finish, by reading
801027fb: 8b 50 20 mov 0x20(%eax),%edx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
801027fe: 89 88 10 03 00 00 mov %ecx,0x310(%eax)
lapic[ID]; // wait for write to finish, by reading
80102804: 8b 50 20 mov 0x20(%eax),%edx
// when it is in the halted state due to an INIT. So the second
// should be ignored, but it is part of the official Intel algorithm.
// Bochs complains about the second one. Too bad for Bochs.
for(i = 0; i < 2; i++){
lapicw(ICRHI, apicid<<24);
lapicw(ICRLO, STARTUP | (addr>>12));
80102807: 89 da mov %ebx,%edx
80102809: 80 ce 06 or $0x6,%dh
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
8010280c: 89 90 00 03 00 00 mov %edx,0x300(%eax)
lapic[ID]; // wait for write to finish, by reading
80102812: 8b 58 20 mov 0x20(%eax),%ebx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
80102815: 89 88 10 03 00 00 mov %ecx,0x310(%eax)
lapic[ID]; // wait for write to finish, by reading
8010281b: 8b 48 20 mov 0x20(%eax),%ecx
//PAGEBREAK!
static void
lapicw(int index, int value)
{
lapic[index] = value;
8010281e: 89 90 00 03 00 00 mov %edx,0x300(%eax)
lapic[ID]; // wait for write to finish, by reading
80102824: 8b 40 20 mov 0x20(%eax),%eax
for(i = 0; i < 2; i++){
lapicw(ICRHI, apicid<<24);
lapicw(ICRLO, STARTUP | (addr>>12));
microdelay(200);
}
}
80102827: 5b pop %ebx
80102828: 5d pop %ebp
80102829: c3 ret
8010282a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80102830 <cmostime>:
r->year = cmos_read(YEAR);
}
// qemu seems to use 24-hour GWT and the values are BCD encoded
void cmostime(struct rtcdate *r)
{
80102830: 55 push %ebp
80102831: ba 70 00 00 00 mov $0x70,%edx
80102836: 89 e5 mov %esp,%ebp
80102838: b8 0b 00 00 00 mov $0xb,%eax
8010283d: 57 push %edi
8010283e: 56 push %esi
8010283f: 53 push %ebx
80102840: 83 ec 4c sub $0x4c,%esp
80102843: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
80102844: b2 71 mov $0x71,%dl
80102846: ec in (%dx),%al
80102847: 88 45 b7 mov %al,-0x49(%ebp)
8010284a: 8d 5d b8 lea -0x48(%ebp),%ebx
struct rtcdate t1, t2;
int sb, bcd;
sb = cmos_read(CMOS_STATB);
bcd = (sb & (1 << 2)) == 0;
8010284d: 80 65 b7 04 andb $0x4,-0x49(%ebp)
80102851: 8d 7d d0 lea -0x30(%ebp),%edi
80102854: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
80102858: be 70 00 00 00 mov $0x70,%esi
// make sure CMOS doesn't modify time while we read it
for(;;) {
fill_rtcdate(&t1);
8010285d: 89 d8 mov %ebx,%eax
8010285f: e8 7c fd ff ff call 801025e0 <fill_rtcdate>
80102864: b8 0a 00 00 00 mov $0xa,%eax
80102869: 89 f2 mov %esi,%edx
8010286b: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
8010286c: ba 71 00 00 00 mov $0x71,%edx
80102871: ec in (%dx),%al
if(cmos_read(CMOS_STATA) & CMOS_UIP)
80102872: 84 c0 test %al,%al
80102874: 78 e7 js 8010285d <cmostime+0x2d>
continue;
fill_rtcdate(&t2);
80102876: 89 f8 mov %edi,%eax
80102878: e8 63 fd ff ff call 801025e0 <fill_rtcdate>
if(memcmp(&t1, &t2, sizeof(t1)) == 0)
8010287d: c7 44 24 08 18 00 00 movl $0x18,0x8(%esp)
80102884: 00
80102885: 89 7c 24 04 mov %edi,0x4(%esp)
80102889: 89 1c 24 mov %ebx,(%esp)
8010288c: e8 2f 1a 00 00 call 801042c0 <memcmp>
80102891: 85 c0 test %eax,%eax
80102893: 75 c3 jne 80102858 <cmostime+0x28>
break;
}
// convert
if(bcd) {
80102895: 80 7d b7 00 cmpb $0x0,-0x49(%ebp)
80102899: 75 78 jne 80102913 <cmostime+0xe3>
#define CONV(x) (t1.x = ((t1.x >> 4) * 10) + (t1.x & 0xf))
CONV(second);
8010289b: 8b 45 b8 mov -0x48(%ebp),%eax
8010289e: 89 c2 mov %eax,%edx
801028a0: 83 e0 0f and $0xf,%eax
801028a3: c1 ea 04 shr $0x4,%edx
801028a6: 8d 14 92 lea (%edx,%edx,4),%edx
801028a9: 8d 04 50 lea (%eax,%edx,2),%eax
801028ac: 89 45 b8 mov %eax,-0x48(%ebp)
CONV(minute);
801028af: 8b 45 bc mov -0x44(%ebp),%eax
801028b2: 89 c2 mov %eax,%edx
801028b4: 83 e0 0f and $0xf,%eax
801028b7: c1 ea 04 shr $0x4,%edx
801028ba: 8d 14 92 lea (%edx,%edx,4),%edx
801028bd: 8d 04 50 lea (%eax,%edx,2),%eax
801028c0: 89 45 bc mov %eax,-0x44(%ebp)
CONV(hour );
801028c3: 8b 45 c0 mov -0x40(%ebp),%eax
801028c6: 89 c2 mov %eax,%edx
801028c8: 83 e0 0f and $0xf,%eax
801028cb: c1 ea 04 shr $0x4,%edx
801028ce: 8d 14 92 lea (%edx,%edx,4),%edx
801028d1: 8d 04 50 lea (%eax,%edx,2),%eax
801028d4: 89 45 c0 mov %eax,-0x40(%ebp)
CONV(day );
801028d7: 8b 45 c4 mov -0x3c(%ebp),%eax
801028da: 89 c2 mov %eax,%edx
801028dc: 83 e0 0f and $0xf,%eax
801028df: c1 ea 04 shr $0x4,%edx
801028e2: 8d 14 92 lea (%edx,%edx,4),%edx
801028e5: 8d 04 50 lea (%eax,%edx,2),%eax
801028e8: 89 45 c4 mov %eax,-0x3c(%ebp)
CONV(month );
801028eb: 8b 45 c8 mov -0x38(%ebp),%eax
801028ee: 89 c2 mov %eax,%edx
801028f0: 83 e0 0f and $0xf,%eax
801028f3: c1 ea 04 shr $0x4,%edx
801028f6: 8d 14 92 lea (%edx,%edx,4),%edx
801028f9: 8d 04 50 lea (%eax,%edx,2),%eax
801028fc: 89 45 c8 mov %eax,-0x38(%ebp)
CONV(year );
801028ff: 8b 45 cc mov -0x34(%ebp),%eax
80102902: 89 c2 mov %eax,%edx
80102904: 83 e0 0f and $0xf,%eax
80102907: c1 ea 04 shr $0x4,%edx
8010290a: 8d 14 92 lea (%edx,%edx,4),%edx
8010290d: 8d 04 50 lea (%eax,%edx,2),%eax
80102910: 89 45 cc mov %eax,-0x34(%ebp)
#undef CONV
}
*r = t1;
80102913: 8b 4d 08 mov 0x8(%ebp),%ecx
80102916: 8b 45 b8 mov -0x48(%ebp),%eax
80102919: 89 01 mov %eax,(%ecx)
8010291b: 8b 45 bc mov -0x44(%ebp),%eax
8010291e: 89 41 04 mov %eax,0x4(%ecx)
80102921: 8b 45 c0 mov -0x40(%ebp),%eax
80102924: 89 41 08 mov %eax,0x8(%ecx)
80102927: 8b 45 c4 mov -0x3c(%ebp),%eax
8010292a: 89 41 0c mov %eax,0xc(%ecx)
8010292d: 8b 45 c8 mov -0x38(%ebp),%eax
80102930: 89 41 10 mov %eax,0x10(%ecx)
80102933: 8b 45 cc mov -0x34(%ebp),%eax
80102936: 89 41 14 mov %eax,0x14(%ecx)
r->year += 2000;
80102939: 81 41 14 d0 07 00 00 addl $0x7d0,0x14(%ecx)
}
80102940: 83 c4 4c add $0x4c,%esp
80102943: 5b pop %ebx
80102944: 5e pop %esi
80102945: 5f pop %edi
80102946: 5d pop %ebp
80102947: c3 ret
80102948: 66 90 xchg %ax,%ax
8010294a: 66 90 xchg %ax,%ax
8010294c: 66 90 xchg %ax,%ax
8010294e: 66 90 xchg %ax,%ax
80102950 <install_trans>:
}
// Copy committed blocks from log to their home location
static void
install_trans(void)
{
80102950: 55 push %ebp
80102951: 89 e5 mov %esp,%ebp
80102953: 57 push %edi
80102954: 56 push %esi
80102955: 53 push %ebx
int tail;
for (tail = 0; tail < log.lh.n; tail++) {
80102956: 31 db xor %ebx,%ebx
}
// Copy committed blocks from log to their home location
static void
install_trans(void)
{
80102958: 83 ec 1c sub $0x1c,%esp
int tail;
for (tail = 0; tail < log.lh.n; tail++) {
8010295b: a1 c8 26 11 80 mov 0x801126c8,%eax
80102960: 85 c0 test %eax,%eax
80102962: 7e 78 jle 801029dc <install_trans+0x8c>
80102964: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
struct buf *lbuf = bread(log.dev, log.start+tail+1); // read log block
80102968: a1 b4 26 11 80 mov 0x801126b4,%eax
8010296d: 01 d8 add %ebx,%eax
8010296f: 83 c0 01 add $0x1,%eax
80102972: 89 44 24 04 mov %eax,0x4(%esp)
80102976: a1 c4 26 11 80 mov 0x801126c4,%eax
8010297b: 89 04 24 mov %eax,(%esp)
8010297e: e8 4d d7 ff ff call 801000d0 <bread>
80102983: 89 c7 mov %eax,%edi
struct buf *dbuf = bread(log.dev, log.lh.block[tail]); // read dst
80102985: 8b 04 9d cc 26 11 80 mov -0x7feed934(,%ebx,4),%eax
static void
install_trans(void)
{
int tail;
for (tail = 0; tail < log.lh.n; tail++) {
8010298c: 83 c3 01 add $0x1,%ebx
struct buf *lbuf = bread(log.dev, log.start+tail+1); // read log block
struct buf *dbuf = bread(log.dev, log.lh.block[tail]); // read dst
8010298f: 89 44 24 04 mov %eax,0x4(%esp)
80102993: a1 c4 26 11 80 mov 0x801126c4,%eax
80102998: 89 04 24 mov %eax,(%esp)
8010299b: e8 30 d7 ff ff call 801000d0 <bread>
memmove(dbuf->data, lbuf->data, BSIZE); // copy block to dst
801029a0: c7 44 24 08 00 02 00 movl $0x200,0x8(%esp)
801029a7: 00
{
int tail;
for (tail = 0; tail < log.lh.n; tail++) {
struct buf *lbuf = bread(log.dev, log.start+tail+1); // read log block
struct buf *dbuf = bread(log.dev, log.lh.block[tail]); // read dst
801029a8: 89 c6 mov %eax,%esi
memmove(dbuf->data, lbuf->data, BSIZE); // copy block to dst
801029aa: 8d 47 5c lea 0x5c(%edi),%eax
801029ad: 89 44 24 04 mov %eax,0x4(%esp)
801029b1: 8d 46 5c lea 0x5c(%esi),%eax
801029b4: 89 04 24 mov %eax,(%esp)
801029b7: e8 54 19 00 00 call 80104310 <memmove>
bwrite(dbuf); // write dst to disk
801029bc: 89 34 24 mov %esi,(%esp)
801029bf: e8 dc d7 ff ff call 801001a0 <bwrite>
brelse(lbuf);
801029c4: 89 3c 24 mov %edi,(%esp)
801029c7: e8 14 d8 ff ff call 801001e0 <brelse>
brelse(dbuf);
801029cc: 89 34 24 mov %esi,(%esp)
801029cf: e8 0c d8 ff ff call 801001e0 <brelse>
static void
install_trans(void)
{
int tail;
for (tail = 0; tail < log.lh.n; tail++) {
801029d4: 39 1d c8 26 11 80 cmp %ebx,0x801126c8
801029da: 7f 8c jg 80102968 <install_trans+0x18>
memmove(dbuf->data, lbuf->data, BSIZE); // copy block to dst
bwrite(dbuf); // write dst to disk
brelse(lbuf);
brelse(dbuf);
}
}
801029dc: 83 c4 1c add $0x1c,%esp
801029df: 5b pop %ebx
801029e0: 5e pop %esi
801029e1: 5f pop %edi
801029e2: 5d pop %ebp
801029e3: c3 ret
801029e4: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
801029ea: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
801029f0 <write_head>:
// Write in-memory log header to disk.
// This is the true point at which the
// current transaction commits.
static void
write_head(void)
{
801029f0: 55 push %ebp
801029f1: 89 e5 mov %esp,%ebp
801029f3: 57 push %edi
801029f4: 56 push %esi
801029f5: 53 push %ebx
801029f6: 83 ec 1c sub $0x1c,%esp
struct buf *buf = bread(log.dev, log.start);
801029f9: a1 b4 26 11 80 mov 0x801126b4,%eax
801029fe: 89 44 24 04 mov %eax,0x4(%esp)
80102a02: a1 c4 26 11 80 mov 0x801126c4,%eax
80102a07: 89 04 24 mov %eax,(%esp)
80102a0a: e8 c1 d6 ff ff call 801000d0 <bread>
struct logheader *hb = (struct logheader *) (buf->data);
int i;
hb->n = log.lh.n;
80102a0f: 8b 1d c8 26 11 80 mov 0x801126c8,%ebx
for (i = 0; i < log.lh.n; i++) {
80102a15: 31 d2 xor %edx,%edx
80102a17: 85 db test %ebx,%ebx
// This is the true point at which the
// current transaction commits.
static void
write_head(void)
{
struct buf *buf = bread(log.dev, log.start);
80102a19: 89 c7 mov %eax,%edi
struct logheader *hb = (struct logheader *) (buf->data);
int i;
hb->n = log.lh.n;
80102a1b: 89 58 5c mov %ebx,0x5c(%eax)
80102a1e: 8d 70 5c lea 0x5c(%eax),%esi
for (i = 0; i < log.lh.n; i++) {
80102a21: 7e 17 jle 80102a3a <write_head+0x4a>
80102a23: 90 nop
80102a24: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
hb->block[i] = log.lh.block[i];
80102a28: 8b 0c 95 cc 26 11 80 mov -0x7feed934(,%edx,4),%ecx
80102a2f: 89 4c 96 04 mov %ecx,0x4(%esi,%edx,4)
{
struct buf *buf = bread(log.dev, log.start);
struct logheader *hb = (struct logheader *) (buf->data);
int i;
hb->n = log.lh.n;
for (i = 0; i < log.lh.n; i++) {
80102a33: 83 c2 01 add $0x1,%edx
80102a36: 39 da cmp %ebx,%edx
80102a38: 75 ee jne 80102a28 <write_head+0x38>
hb->block[i] = log.lh.block[i];
}
bwrite(buf);
80102a3a: 89 3c 24 mov %edi,(%esp)
80102a3d: e8 5e d7 ff ff call 801001a0 <bwrite>
brelse(buf);
80102a42: 89 3c 24 mov %edi,(%esp)
80102a45: e8 96 d7 ff ff call 801001e0 <brelse>
}
80102a4a: 83 c4 1c add $0x1c,%esp
80102a4d: 5b pop %ebx
80102a4e: 5e pop %esi
80102a4f: 5f pop %edi
80102a50: 5d pop %ebp
80102a51: c3 ret
80102a52: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80102a59: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80102a60 <initlog>:
static void recover_from_log(void);
static void commit();
void
initlog(int dev)
{
80102a60: 55 push %ebp
80102a61: 89 e5 mov %esp,%ebp
80102a63: 56 push %esi
80102a64: 53 push %ebx
80102a65: 83 ec 30 sub $0x30,%esp
80102a68: 8b 5d 08 mov 0x8(%ebp),%ebx
if (sizeof(struct logheader) >= BSIZE)
panic("initlog: too big logheader");
struct superblock sb;
initlock(&log.lock, "log");
80102a6b: c7 44 24 04 40 72 10 movl $0x80107240,0x4(%esp)
80102a72: 80
80102a73: c7 04 24 80 26 11 80 movl $0x80112680,(%esp)
80102a7a: e8 c1 15 00 00 call 80104040 <initlock>
readsb(dev, &sb);
80102a7f: 8d 45 dc lea -0x24(%ebp),%eax
80102a82: 89 44 24 04 mov %eax,0x4(%esp)
80102a86: 89 1c 24 mov %ebx,(%esp)
80102a89: e8 f2 e8 ff ff call 80101380 <readsb>
log.start = sb.logstart;
80102a8e: 8b 45 ec mov -0x14(%ebp),%eax
log.size = sb.nlog;
80102a91: 8b 55 e8 mov -0x18(%ebp),%edx
// Read the log header from disk into the in-memory log header
static void
read_head(void)
{
struct buf *buf = bread(log.dev, log.start);
80102a94: 89 1c 24 mov %ebx,(%esp)
struct superblock sb;
initlock(&log.lock, "log");
readsb(dev, &sb);
log.start = sb.logstart;
log.size = sb.nlog;
log.dev = dev;
80102a97: 89 1d c4 26 11 80 mov %ebx,0x801126c4
// Read the log header from disk into the in-memory log header
static void
read_head(void)
{
struct buf *buf = bread(log.dev, log.start);
80102a9d: 89 44 24 04 mov %eax,0x4(%esp)
struct superblock sb;
initlock(&log.lock, "log");
readsb(dev, &sb);
log.start = sb.logstart;
log.size = sb.nlog;
80102aa1: 89 15 b8 26 11 80 mov %edx,0x801126b8
panic("initlog: too big logheader");
struct superblock sb;
initlock(&log.lock, "log");
readsb(dev, &sb);
log.start = sb.logstart;
80102aa7: a3 b4 26 11 80 mov %eax,0x801126b4
// Read the log header from disk into the in-memory log header
static void
read_head(void)
{
struct buf *buf = bread(log.dev, log.start);
80102aac: e8 1f d6 ff ff call 801000d0 <bread>
struct logheader *lh = (struct logheader *) (buf->data);
int i;
log.lh.n = lh->n;
for (i = 0; i < log.lh.n; i++) {
80102ab1: 31 d2 xor %edx,%edx
read_head(void)
{
struct buf *buf = bread(log.dev, log.start);
struct logheader *lh = (struct logheader *) (buf->data);
int i;
log.lh.n = lh->n;
80102ab3: 8b 58 5c mov 0x5c(%eax),%ebx
80102ab6: 8d 70 5c lea 0x5c(%eax),%esi
for (i = 0; i < log.lh.n; i++) {
80102ab9: 85 db test %ebx,%ebx
read_head(void)
{
struct buf *buf = bread(log.dev, log.start);
struct logheader *lh = (struct logheader *) (buf->data);
int i;
log.lh.n = lh->n;
80102abb: 89 1d c8 26 11 80 mov %ebx,0x801126c8
for (i = 0; i < log.lh.n; i++) {
80102ac1: 7e 17 jle 80102ada <initlog+0x7a>
80102ac3: 90 nop
80102ac4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
log.lh.block[i] = lh->block[i];
80102ac8: 8b 4c 96 04 mov 0x4(%esi,%edx,4),%ecx
80102acc: 89 0c 95 cc 26 11 80 mov %ecx,-0x7feed934(,%edx,4)
{
struct buf *buf = bread(log.dev, log.start);
struct logheader *lh = (struct logheader *) (buf->data);
int i;
log.lh.n = lh->n;
for (i = 0; i < log.lh.n; i++) {
80102ad3: 83 c2 01 add $0x1,%edx
80102ad6: 39 da cmp %ebx,%edx
80102ad8: 75 ee jne 80102ac8 <initlog+0x68>
log.lh.block[i] = lh->block[i];
}
brelse(buf);
80102ada: 89 04 24 mov %eax,(%esp)
80102add: e8 fe d6 ff ff call 801001e0 <brelse>
static void
recover_from_log(void)
{
read_head();
install_trans(); // if committed, copy from log to disk
80102ae2: e8 69 fe ff ff call 80102950 <install_trans>
log.lh.n = 0;
80102ae7: c7 05 c8 26 11 80 00 movl $0x0,0x801126c8
80102aee: 00 00 00
write_head(); // clear the log
80102af1: e8 fa fe ff ff call 801029f0 <write_head>
readsb(dev, &sb);
log.start = sb.logstart;
log.size = sb.nlog;
log.dev = dev;
recover_from_log();
}
80102af6: 83 c4 30 add $0x30,%esp
80102af9: 5b pop %ebx
80102afa: 5e pop %esi
80102afb: 5d pop %ebp
80102afc: c3 ret
80102afd: 8d 76 00 lea 0x0(%esi),%esi
80102b00 <begin_op>:
}
// called at the start of each FS system call.
void
begin_op(void)
{
80102b00: 55 push %ebp
80102b01: 89 e5 mov %esp,%ebp
80102b03: 83 ec 18 sub $0x18,%esp
acquire(&log.lock);
80102b06: c7 04 24 80 26 11 80 movl $0x80112680,(%esp)
80102b0d: e8 1e 16 00 00 call 80104130 <acquire>
80102b12: eb 18 jmp 80102b2c <begin_op+0x2c>
80102b14: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
while(1){
if(log.committing){
sleep(&log, &log.lock);
80102b18: c7 44 24 04 80 26 11 movl $0x80112680,0x4(%esp)
80102b1f: 80
80102b20: c7 04 24 80 26 11 80 movl $0x80112680,(%esp)
80102b27: e8 c4 10 00 00 call 80103bf0 <sleep>
void
begin_op(void)
{
acquire(&log.lock);
while(1){
if(log.committing){
80102b2c: a1 c0 26 11 80 mov 0x801126c0,%eax
80102b31: 85 c0 test %eax,%eax
80102b33: 75 e3 jne 80102b18 <begin_op+0x18>
sleep(&log, &log.lock);
} else if(log.lh.n + (log.outstanding+1)*MAXOPBLOCKS > LOGSIZE){
80102b35: a1 bc 26 11 80 mov 0x801126bc,%eax
80102b3a: 8b 15 c8 26 11 80 mov 0x801126c8,%edx
80102b40: 83 c0 01 add $0x1,%eax
80102b43: 8d 0c 80 lea (%eax,%eax,4),%ecx
80102b46: 8d 14 4a lea (%edx,%ecx,2),%edx
80102b49: 83 fa 1e cmp $0x1e,%edx
80102b4c: 7f ca jg 80102b18 <begin_op+0x18>
// this op might exhaust log space; wait for commit.
sleep(&log, &log.lock);
} else {
log.outstanding += 1;
release(&log.lock);
80102b4e: c7 04 24 80 26 11 80 movl $0x80112680,(%esp)
sleep(&log, &log.lock);
} else if(log.lh.n + (log.outstanding+1)*MAXOPBLOCKS > LOGSIZE){
// this op might exhaust log space; wait for commit.
sleep(&log, &log.lock);
} else {
log.outstanding += 1;
80102b55: a3 bc 26 11 80 mov %eax,0x801126bc
release(&log.lock);
80102b5a: e8 c1 16 00 00 call 80104220 <release>
break;
}
}
}
80102b5f: c9 leave
80102b60: c3 ret
80102b61: eb 0d jmp 80102b70 <end_op>
80102b63: 90 nop
80102b64: 90 nop
80102b65: 90 nop
80102b66: 90 nop
80102b67: 90 nop
80102b68: 90 nop
80102b69: 90 nop
80102b6a: 90 nop
80102b6b: 90 nop
80102b6c: 90 nop
80102b6d: 90 nop
80102b6e: 90 nop
80102b6f: 90 nop
80102b70 <end_op>:
// called at the end of each FS system call.
// commits if this was the last outstanding operation.
void
end_op(void)
{
80102b70: 55 push %ebp
80102b71: 89 e5 mov %esp,%ebp
80102b73: 57 push %edi
80102b74: 56 push %esi
80102b75: 53 push %ebx
80102b76: 83 ec 1c sub $0x1c,%esp
int do_commit = 0;
acquire(&log.lock);
80102b79: c7 04 24 80 26 11 80 movl $0x80112680,(%esp)
80102b80: e8 ab 15 00 00 call 80104130 <acquire>
log.outstanding -= 1;
80102b85: a1 bc 26 11 80 mov 0x801126bc,%eax
if(log.committing)
80102b8a: 8b 15 c0 26 11 80 mov 0x801126c0,%edx
end_op(void)
{
int do_commit = 0;
acquire(&log.lock);
log.outstanding -= 1;
80102b90: 83 e8 01 sub $0x1,%eax
if(log.committing)
80102b93: 85 d2 test %edx,%edx
end_op(void)
{
int do_commit = 0;
acquire(&log.lock);
log.outstanding -= 1;
80102b95: a3 bc 26 11 80 mov %eax,0x801126bc
if(log.committing)
80102b9a: 0f 85 f3 00 00 00 jne 80102c93 <end_op+0x123>
panic("log.committing");
if(log.outstanding == 0){
80102ba0: 85 c0 test %eax,%eax
80102ba2: 0f 85 cb 00 00 00 jne 80102c73 <end_op+0x103>
// begin_op() may be waiting for log space,
// and decrementing log.outstanding has decreased
// the amount of reserved space.
wakeup(&log);
}
release(&log.lock);
80102ba8: c7 04 24 80 26 11 80 movl $0x80112680,(%esp)
}
static void
commit()
{
if (log.lh.n > 0) {
80102baf: 31 db xor %ebx,%ebx
log.outstanding -= 1;
if(log.committing)
panic("log.committing");
if(log.outstanding == 0){
do_commit = 1;
log.committing = 1;
80102bb1: c7 05 c0 26 11 80 01 movl $0x1,0x801126c0
80102bb8: 00 00 00
// begin_op() may be waiting for log space,
// and decrementing log.outstanding has decreased
// the amount of reserved space.
wakeup(&log);
}
release(&log.lock);
80102bbb: e8 60 16 00 00 call 80104220 <release>
}
static void
commit()
{
if (log.lh.n > 0) {
80102bc0: a1 c8 26 11 80 mov 0x801126c8,%eax
80102bc5: 85 c0 test %eax,%eax
80102bc7: 0f 8e 90 00 00 00 jle 80102c5d <end_op+0xed>
80102bcd: 8d 76 00 lea 0x0(%esi),%esi
write_log(void)
{
int tail;
for (tail = 0; tail < log.lh.n; tail++) {
struct buf *to = bread(log.dev, log.start+tail+1); // log block
80102bd0: a1 b4 26 11 80 mov 0x801126b4,%eax
80102bd5: 01 d8 add %ebx,%eax
80102bd7: 83 c0 01 add $0x1,%eax
80102bda: 89 44 24 04 mov %eax,0x4(%esp)
80102bde: a1 c4 26 11 80 mov 0x801126c4,%eax
80102be3: 89 04 24 mov %eax,(%esp)
80102be6: e8 e5 d4 ff ff call 801000d0 <bread>
80102beb: 89 c6 mov %eax,%esi
struct buf *from = bread(log.dev, log.lh.block[tail]); // cache block
80102bed: 8b 04 9d cc 26 11 80 mov -0x7feed934(,%ebx,4),%eax
static void
write_log(void)
{
int tail;
for (tail = 0; tail < log.lh.n; tail++) {
80102bf4: 83 c3 01 add $0x1,%ebx
struct buf *to = bread(log.dev, log.start+tail+1); // log block
struct buf *from = bread(log.dev, log.lh.block[tail]); // cache block
80102bf7: 89 44 24 04 mov %eax,0x4(%esp)
80102bfb: a1 c4 26 11 80 mov 0x801126c4,%eax
80102c00: 89 04 24 mov %eax,(%esp)
80102c03: e8 c8 d4 ff ff call 801000d0 <bread>
memmove(to->data, from->data, BSIZE);
80102c08: c7 44 24 08 00 02 00 movl $0x200,0x8(%esp)
80102c0f: 00
{
int tail;
for (tail = 0; tail < log.lh.n; tail++) {
struct buf *to = bread(log.dev, log.start+tail+1); // log block
struct buf *from = bread(log.dev, log.lh.block[tail]); // cache block
80102c10: 89 c7 mov %eax,%edi
memmove(to->data, from->data, BSIZE);
80102c12: 8d 40 5c lea 0x5c(%eax),%eax
80102c15: 89 44 24 04 mov %eax,0x4(%esp)
80102c19: 8d 46 5c lea 0x5c(%esi),%eax
80102c1c: 89 04 24 mov %eax,(%esp)
80102c1f: e8 ec 16 00 00 call 80104310 <memmove>
bwrite(to); // write the log
80102c24: 89 34 24 mov %esi,(%esp)
80102c27: e8 74 d5 ff ff call 801001a0 <bwrite>
brelse(from);
80102c2c: 89 3c 24 mov %edi,(%esp)
80102c2f: e8 ac d5 ff ff call 801001e0 <brelse>
brelse(to);
80102c34: 89 34 24 mov %esi,(%esp)
80102c37: e8 a4 d5 ff ff call 801001e0 <brelse>
static void
write_log(void)
{
int tail;
for (tail = 0; tail < log.lh.n; tail++) {
80102c3c: 3b 1d c8 26 11 80 cmp 0x801126c8,%ebx
80102c42: 7c 8c jl 80102bd0 <end_op+0x60>
static void
commit()
{
if (log.lh.n > 0) {
write_log(); // Write modified blocks from cache to log
write_head(); // Write header to disk -- the real commit
80102c44: e8 a7 fd ff ff call 801029f0 <write_head>
install_trans(); // Now install writes to home locations
80102c49: e8 02 fd ff ff call 80102950 <install_trans>
log.lh.n = 0;
80102c4e: c7 05 c8 26 11 80 00 movl $0x0,0x801126c8
80102c55: 00 00 00
write_head(); // Erase the transaction from the log
80102c58: e8 93 fd ff ff call 801029f0 <write_head>
if(do_commit){
// call commit w/o holding locks, since not allowed
// to sleep with locks.
commit();
acquire(&log.lock);
80102c5d: c7 04 24 80 26 11 80 movl $0x80112680,(%esp)
80102c64: e8 c7 14 00 00 call 80104130 <acquire>
log.committing = 0;
80102c69: c7 05 c0 26 11 80 00 movl $0x0,0x801126c0
80102c70: 00 00 00
wakeup(&log);
80102c73: c7 04 24 80 26 11 80 movl $0x80112680,(%esp)
80102c7a: e8 01 11 00 00 call 80103d80 <wakeup>
release(&log.lock);
80102c7f: c7 04 24 80 26 11 80 movl $0x80112680,(%esp)
80102c86: e8 95 15 00 00 call 80104220 <release>
}
}
80102c8b: 83 c4 1c add $0x1c,%esp
80102c8e: 5b pop %ebx
80102c8f: 5e pop %esi
80102c90: 5f pop %edi
80102c91: 5d pop %ebp
80102c92: c3 ret
int do_commit = 0;
acquire(&log.lock);
log.outstanding -= 1;
if(log.committing)
panic("log.committing");
80102c93: c7 04 24 44 72 10 80 movl $0x80107244,(%esp)
80102c9a: e8 c1 d6 ff ff call 80100360 <panic>
80102c9f: 90 nop
80102ca0 <log_write>:
// modify bp->data[]
// log_write(bp)
// brelse(bp)
void
log_write(struct buf *b)
{
80102ca0: 55 push %ebp
80102ca1: 89 e5 mov %esp,%ebp
80102ca3: 53 push %ebx
80102ca4: 83 ec 14 sub $0x14,%esp
int i;
if (log.lh.n >= LOGSIZE || log.lh.n >= log.size - 1)
80102ca7: a1 c8 26 11 80 mov 0x801126c8,%eax
// modify bp->data[]
// log_write(bp)
// brelse(bp)
void
log_write(struct buf *b)
{
80102cac: 8b 5d 08 mov 0x8(%ebp),%ebx
int i;
if (log.lh.n >= LOGSIZE || log.lh.n >= log.size - 1)
80102caf: 83 f8 1d cmp $0x1d,%eax
80102cb2: 0f 8f 98 00 00 00 jg 80102d50 <log_write+0xb0>
80102cb8: 8b 0d b8 26 11 80 mov 0x801126b8,%ecx
80102cbe: 8d 51 ff lea -0x1(%ecx),%edx
80102cc1: 39 d0 cmp %edx,%eax
80102cc3: 0f 8d 87 00 00 00 jge 80102d50 <log_write+0xb0>
panic("too big a transaction");
if (log.outstanding < 1)
80102cc9: a1 bc 26 11 80 mov 0x801126bc,%eax
80102cce: 85 c0 test %eax,%eax
80102cd0: 0f 8e 86 00 00 00 jle 80102d5c <log_write+0xbc>
panic("log_write outside of trans");
acquire(&log.lock);
80102cd6: c7 04 24 80 26 11 80 movl $0x80112680,(%esp)
80102cdd: e8 4e 14 00 00 call 80104130 <acquire>
for (i = 0; i < log.lh.n; i++) {
80102ce2: 8b 15 c8 26 11 80 mov 0x801126c8,%edx
80102ce8: 83 fa 00 cmp $0x0,%edx
80102ceb: 7e 54 jle 80102d41 <log_write+0xa1>
if (log.lh.block[i] == b->blockno) // log absorbtion
80102ced: 8b 4b 08 mov 0x8(%ebx),%ecx
panic("too big a transaction");
if (log.outstanding < 1)
panic("log_write outside of trans");
acquire(&log.lock);
for (i = 0; i < log.lh.n; i++) {
80102cf0: 31 c0 xor %eax,%eax
if (log.lh.block[i] == b->blockno) // log absorbtion
80102cf2: 39 0d cc 26 11 80 cmp %ecx,0x801126cc
80102cf8: 75 0f jne 80102d09 <log_write+0x69>
80102cfa: eb 3c jmp 80102d38 <log_write+0x98>
80102cfc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80102d00: 39 0c 85 cc 26 11 80 cmp %ecx,-0x7feed934(,%eax,4)
80102d07: 74 2f je 80102d38 <log_write+0x98>
panic("too big a transaction");
if (log.outstanding < 1)
panic("log_write outside of trans");
acquire(&log.lock);
for (i = 0; i < log.lh.n; i++) {
80102d09: 83 c0 01 add $0x1,%eax
80102d0c: 39 d0 cmp %edx,%eax
80102d0e: 75 f0 jne 80102d00 <log_write+0x60>
if (log.lh.block[i] == b->blockno) // log absorbtion
break;
}
log.lh.block[i] = b->blockno;
80102d10: 89 0c 95 cc 26 11 80 mov %ecx,-0x7feed934(,%edx,4)
if (i == log.lh.n)
log.lh.n++;
80102d17: 83 c2 01 add $0x1,%edx
80102d1a: 89 15 c8 26 11 80 mov %edx,0x801126c8
b->flags |= B_DIRTY; // prevent eviction
80102d20: 83 0b 04 orl $0x4,(%ebx)
release(&log.lock);
80102d23: c7 45 08 80 26 11 80 movl $0x80112680,0x8(%ebp)
}
80102d2a: 83 c4 14 add $0x14,%esp
80102d2d: 5b pop %ebx
80102d2e: 5d pop %ebp
}
log.lh.block[i] = b->blockno;
if (i == log.lh.n)
log.lh.n++;
b->flags |= B_DIRTY; // prevent eviction
release(&log.lock);
80102d2f: e9 ec 14 00 00 jmp 80104220 <release>
80102d34: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
acquire(&log.lock);
for (i = 0; i < log.lh.n; i++) {
if (log.lh.block[i] == b->blockno) // log absorbtion
break;
}
log.lh.block[i] = b->blockno;
80102d38: 89 0c 85 cc 26 11 80 mov %ecx,-0x7feed934(,%eax,4)
80102d3f: eb df jmp 80102d20 <log_write+0x80>
80102d41: 8b 43 08 mov 0x8(%ebx),%eax
80102d44: a3 cc 26 11 80 mov %eax,0x801126cc
if (i == log.lh.n)
80102d49: 75 d5 jne 80102d20 <log_write+0x80>
80102d4b: eb ca jmp 80102d17 <log_write+0x77>
80102d4d: 8d 76 00 lea 0x0(%esi),%esi
log_write(struct buf *b)
{
int i;
if (log.lh.n >= LOGSIZE || log.lh.n >= log.size - 1)
panic("too big a transaction");
80102d50: c7 04 24 53 72 10 80 movl $0x80107253,(%esp)
80102d57: e8 04 d6 ff ff call 80100360 <panic>
if (log.outstanding < 1)
panic("log_write outside of trans");
80102d5c: c7 04 24 69 72 10 80 movl $0x80107269,(%esp)
80102d63: e8 f8 d5 ff ff call 80100360 <panic>
80102d68: 66 90 xchg %ax,%ax
80102d6a: 66 90 xchg %ax,%ax
80102d6c: 66 90 xchg %ax,%ax
80102d6e: 66 90 xchg %ax,%ax
80102d70 <mpmain>:
}
// Common CPU setup code.
static void
mpmain(void)
{
80102d70: 55 push %ebp
80102d71: 89 e5 mov %esp,%ebp
80102d73: 53 push %ebx
80102d74: 83 ec 14 sub $0x14,%esp
cprintf("cpu%d: starting %d\n", cpuid(), cpuid());
80102d77: e8 f4 08 00 00 call 80103670 <cpuid>
80102d7c: 89 c3 mov %eax,%ebx
80102d7e: e8 ed 08 00 00 call 80103670 <cpuid>
80102d83: 89 5c 24 08 mov %ebx,0x8(%esp)
80102d87: c7 04 24 84 72 10 80 movl $0x80107284,(%esp)
80102d8e: 89 44 24 04 mov %eax,0x4(%esp)
80102d92: e8 b9 d8 ff ff call 80100650 <cprintf>
idtinit(); // load idt register
80102d97: e8 14 27 00 00 call 801054b0 <idtinit>
xchg(&(mycpu()->started), 1); // tell startothers() we're up
80102d9c: e8 4f 08 00 00 call 801035f0 <mycpu>
80102da1: 89 c2 mov %eax,%edx
xchg(volatile uint *addr, uint newval)
{
uint result;
// The + in "+m" denotes a read-modify-write operand.
asm volatile("lock; xchgl %0, %1" :
80102da3: b8 01 00 00 00 mov $0x1,%eax
80102da8: f0 87 82 a0 00 00 00 lock xchg %eax,0xa0(%edx)
scheduler(); // start running processes
80102daf: e8 9c 0b 00 00 call 80103950 <scheduler>
80102db4: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80102dba: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
80102dc0 <mpenter>:
}
// Other CPUs jump here from entryother.S.
static void
mpenter(void)
{
80102dc0: 55 push %ebp
80102dc1: 89 e5 mov %esp,%ebp
80102dc3: 83 ec 08 sub $0x8,%esp
switchkvm();
80102dc6: e8 d5 37 00 00 call 801065a0 <switchkvm>
seginit();
80102dcb: e8 90 36 00 00 call 80106460 <seginit>
lapicinit();
80102dd0: e8 8b f8 ff ff call 80102660 <lapicinit>
mpmain();
80102dd5: e8 96 ff ff ff call 80102d70 <mpmain>
80102dda: 66 90 xchg %ax,%ax
80102ddc: 66 90 xchg %ax,%ax
80102dde: 66 90 xchg %ax,%ax
80102de0 <main>:
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
80102de0: 55 push %ebp
80102de1: 89 e5 mov %esp,%ebp
80102de3: 53 push %ebx
// The linker has placed the image of entryother.S in
// _binary_entryother_start.
code = P2V(0x7000);
memmove(code, _binary_entryother_start, (uint)_binary_entryother_size);
for(c = cpus; c < cpus+ncpu; c++){
80102de4: bb 80 27 11 80 mov $0x80112780,%ebx
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
80102de9: 83 e4 f0 and $0xfffffff0,%esp
80102dec: 83 ec 10 sub $0x10,%esp
kinit1(end, P2V(4*1024*1024)); // phys page allocator
80102def: c7 44 24 04 00 00 40 movl $0x80400000,0x4(%esp)
80102df6: 80
80102df7: c7 04 24 f4 58 11 80 movl $0x801158f4,(%esp)
80102dfe: e8 cd f5 ff ff call 801023d0 <kinit1>
kvmalloc(); // kernel page table
80102e03: e8 48 3c 00 00 call 80106a50 <kvmalloc>
mpinit(); // detect other processors
80102e08: e8 73 01 00 00 call 80102f80 <mpinit>
80102e0d: 8d 76 00 lea 0x0(%esi),%esi
lapicinit(); // interrupt controller
80102e10: e8 4b f8 ff ff call 80102660 <lapicinit>
seginit(); // segment descriptors
80102e15: e8 46 36 00 00 call 80106460 <seginit>
picinit(); // disable pic
80102e1a: e8 21 03 00 00 call 80103140 <picinit>
80102e1f: 90 nop
ioapicinit(); // another interrupt controller
80102e20: e8 cb f3 ff ff call 801021f0 <ioapicinit>
consoleinit(); // console hardware
80102e25: e8 26 db ff ff call 80100950 <consoleinit>
uartinit(); // serial port
80102e2a: e8 d1 29 00 00 call 80105800 <uartinit>
80102e2f: 90 nop
pinit(); // process table
80102e30: e8 9b 07 00 00 call 801035d0 <pinit>
shminit(); // shared memory
80102e35: e8 e6 3e 00 00 call 80106d20 <shminit>
tvinit(); // trap vectors
80102e3a: e8 d1 25 00 00 call 80105410 <tvinit>
80102e3f: 90 nop
binit(); // buffer cache
80102e40: e8 fb d1 ff ff call 80100040 <binit>
fileinit(); // file table
80102e45: e8 e6 de ff ff call 80100d30 <fileinit>
ideinit(); // disk
80102e4a: e8 a1 f1 ff ff call 80101ff0 <ideinit>
// Write entry code to unused memory at 0x7000.
// The linker has placed the image of entryother.S in
// _binary_entryother_start.
code = P2V(0x7000);
memmove(code, _binary_entryother_start, (uint)_binary_entryother_size);
80102e4f: c7 44 24 08 8a 00 00 movl $0x8a,0x8(%esp)
80102e56: 00
80102e57: c7 44 24 04 8c a4 10 movl $0x8010a48c,0x4(%esp)
80102e5e: 80
80102e5f: c7 04 24 00 70 00 80 movl $0x80007000,(%esp)
80102e66: e8 a5 14 00 00 call 80104310 <memmove>
for(c = cpus; c < cpus+ncpu; c++){
80102e6b: 69 05 00 2d 11 80 b0 imul $0xb0,0x80112d00,%eax
80102e72: 00 00 00
80102e75: 05 80 27 11 80 add $0x80112780,%eax
80102e7a: 39 d8 cmp %ebx,%eax
80102e7c: 76 65 jbe 80102ee3 <main+0x103>
80102e7e: 66 90 xchg %ax,%ax
if(c == mycpu()) // We've started already.
80102e80: e8 6b 07 00 00 call 801035f0 <mycpu>
80102e85: 39 d8 cmp %ebx,%eax
80102e87: 74 41 je 80102eca <main+0xea>
continue;
// Tell entryother.S what stack to use, where to enter, and what
// pgdir to use. We cannot use kpgdir yet, because the AP processor
// is running in low memory, so we use entrypgdir for the APs too.
stack = kalloc();
80102e89: e8 02 f6 ff ff call 80102490 <kalloc>
*(void**)(code-4) = stack + KSTACKSIZE;
*(void**)(code-8) = mpenter;
80102e8e: c7 05 f8 6f 00 80 c0 movl $0x80102dc0,0x80006ff8
80102e95: 2d 10 80
*(int**)(code-12) = (void *) V2P(entrypgdir);
80102e98: c7 05 f4 6f 00 80 00 movl $0x109000,0x80006ff4
80102e9f: 90 10 00
// Tell entryother.S what stack to use, where to enter, and what
// pgdir to use. We cannot use kpgdir yet, because the AP processor
// is running in low memory, so we use entrypgdir for the APs too.
stack = kalloc();
*(void**)(code-4) = stack + KSTACKSIZE;
80102ea2: 05 00 10 00 00 add $0x1000,%eax
80102ea7: a3 fc 6f 00 80 mov %eax,0x80006ffc
*(void**)(code-8) = mpenter;
*(int**)(code-12) = (void *) V2P(entrypgdir);
lapicstartap(c->apicid, V2P(code));
80102eac: 0f b6 03 movzbl (%ebx),%eax
80102eaf: c7 44 24 04 00 70 00 movl $0x7000,0x4(%esp)
80102eb6: 00
80102eb7: 89 04 24 mov %eax,(%esp)
80102eba: e8 e1 f8 ff ff call 801027a0 <lapicstartap>
80102ebf: 90 nop
// wait for cpu to finish mpmain()
while(c->started == 0)
80102ec0: 8b 83 a0 00 00 00 mov 0xa0(%ebx),%eax
80102ec6: 85 c0 test %eax,%eax
80102ec8: 74 f6 je 80102ec0 <main+0xe0>
// The linker has placed the image of entryother.S in
// _binary_entryother_start.
code = P2V(0x7000);
memmove(code, _binary_entryother_start, (uint)_binary_entryother_size);
for(c = cpus; c < cpus+ncpu; c++){
80102eca: 69 05 00 2d 11 80 b0 imul $0xb0,0x80112d00,%eax
80102ed1: 00 00 00
80102ed4: 81 c3 b0 00 00 00 add $0xb0,%ebx
80102eda: 05 80 27 11 80 add $0x80112780,%eax
80102edf: 39 c3 cmp %eax,%ebx
80102ee1: 72 9d jb 80102e80 <main+0xa0>
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
ideinit(); // disk
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
80102ee3: c7 44 24 04 00 00 00 movl $0x8e000000,0x4(%esp)
80102eea: 8e
80102eeb: c7 04 24 00 00 40 80 movl $0x80400000,(%esp)
80102ef2: e8 49 f5 ff ff call 80102440 <kinit2>
userinit(); // first user process
80102ef7: e8 c4 07 00 00 call 801036c0 <userinit>
mpmain(); // finish this processor's setup
80102efc: e8 6f fe ff ff call 80102d70 <mpmain>
80102f01: 66 90 xchg %ax,%ax
80102f03: 66 90 xchg %ax,%ax
80102f05: 66 90 xchg %ax,%ax
80102f07: 66 90 xchg %ax,%ax
80102f09: 66 90 xchg %ax,%ax
80102f0b: 66 90 xchg %ax,%ax
80102f0d: 66 90 xchg %ax,%ax
80102f0f: 90 nop
80102f10 <mpsearch1>:
}
// Look for an MP structure in the len bytes at addr.
static struct mp*
mpsearch1(uint a, int len)
{
80102f10: 55 push %ebp
80102f11: 89 e5 mov %esp,%ebp
80102f13: 56 push %esi
uchar *e, *p, *addr;
addr = P2V(a);
80102f14: 8d b0 00 00 00 80 lea -0x80000000(%eax),%esi
}
// Look for an MP structure in the len bytes at addr.
static struct mp*
mpsearch1(uint a, int len)
{
80102f1a: 53 push %ebx
uchar *e, *p, *addr;
addr = P2V(a);
e = addr+len;
80102f1b: 8d 1c 16 lea (%esi,%edx,1),%ebx
}
// Look for an MP structure in the len bytes at addr.
static struct mp*
mpsearch1(uint a, int len)
{
80102f1e: 83 ec 10 sub $0x10,%esp
uchar *e, *p, *addr;
addr = P2V(a);
e = addr+len;
for(p = addr; p < e; p += sizeof(struct mp))
80102f21: 39 de cmp %ebx,%esi
80102f23: 73 3c jae 80102f61 <mpsearch1+0x51>
80102f25: 8d 76 00 lea 0x0(%esi),%esi
if(memcmp(p, "_MP_", 4) == 0 && sum(p, sizeof(struct mp)) == 0)
80102f28: c7 44 24 08 04 00 00 movl $0x4,0x8(%esp)
80102f2f: 00
80102f30: c7 44 24 04 98 72 10 movl $0x80107298,0x4(%esp)
80102f37: 80
80102f38: 89 34 24 mov %esi,(%esp)
80102f3b: e8 80 13 00 00 call 801042c0 <memcmp>
80102f40: 85 c0 test %eax,%eax
80102f42: 75 16 jne 80102f5a <mpsearch1+0x4a>
80102f44: 31 c9 xor %ecx,%ecx
80102f46: 31 d2 xor %edx,%edx
{
int i, sum;
sum = 0;
for(i=0; i<len; i++)
sum += addr[i];
80102f48: 0f b6 04 16 movzbl (%esi,%edx,1),%eax
sum(uchar *addr, int len)
{
int i, sum;
sum = 0;
for(i=0; i<len; i++)
80102f4c: 83 c2 01 add $0x1,%edx
sum += addr[i];
80102f4f: 01 c1 add %eax,%ecx
sum(uchar *addr, int len)
{
int i, sum;
sum = 0;
for(i=0; i<len; i++)
80102f51: 83 fa 10 cmp $0x10,%edx
80102f54: 75 f2 jne 80102f48 <mpsearch1+0x38>
uchar *e, *p, *addr;
addr = P2V(a);
e = addr+len;
for(p = addr; p < e; p += sizeof(struct mp))
if(memcmp(p, "_MP_", 4) == 0 && sum(p, sizeof(struct mp)) == 0)
80102f56: 84 c9 test %cl,%cl
80102f58: 74 10 je 80102f6a <mpsearch1+0x5a>
{
uchar *e, *p, *addr;
addr = P2V(a);
e = addr+len;
for(p = addr; p < e; p += sizeof(struct mp))
80102f5a: 83 c6 10 add $0x10,%esi
80102f5d: 39 f3 cmp %esi,%ebx
80102f5f: 77 c7 ja 80102f28 <mpsearch1+0x18>
if(memcmp(p, "_MP_", 4) == 0 && sum(p, sizeof(struct mp)) == 0)
return (struct mp*)p;
return 0;
}
80102f61: 83 c4 10 add $0x10,%esp
addr = P2V(a);
e = addr+len;
for(p = addr; p < e; p += sizeof(struct mp))
if(memcmp(p, "_MP_", 4) == 0 && sum(p, sizeof(struct mp)) == 0)
return (struct mp*)p;
return 0;
80102f64: 31 c0 xor %eax,%eax
}
80102f66: 5b pop %ebx
80102f67: 5e pop %esi
80102f68: 5d pop %ebp
80102f69: c3 ret
80102f6a: 83 c4 10 add $0x10,%esp
80102f6d: 89 f0 mov %esi,%eax
80102f6f: 5b pop %ebx
80102f70: 5e pop %esi
80102f71: 5d pop %ebp
80102f72: c3 ret
80102f73: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80102f79: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80102f80 <mpinit>:
return conf;
}
void
mpinit(void)
{
80102f80: 55 push %ebp
80102f81: 89 e5 mov %esp,%ebp
80102f83: 57 push %edi
80102f84: 56 push %esi
80102f85: 53 push %ebx
80102f86: 83 ec 1c sub $0x1c,%esp
uchar *bda;
uint p;
struct mp *mp;
bda = (uchar *) P2V(0x400);
if((p = ((bda[0x0F]<<8)| bda[0x0E]) << 4)){
80102f89: 0f b6 05 0f 04 00 80 movzbl 0x8000040f,%eax
80102f90: 0f b6 15 0e 04 00 80 movzbl 0x8000040e,%edx
80102f97: c1 e0 08 shl $0x8,%eax
80102f9a: 09 d0 or %edx,%eax
80102f9c: c1 e0 04 shl $0x4,%eax
80102f9f: 85 c0 test %eax,%eax
80102fa1: 75 1b jne 80102fbe <mpinit+0x3e>
if((mp = mpsearch1(p, 1024)))
return mp;
} else {
p = ((bda[0x14]<<8)|bda[0x13])*1024;
80102fa3: 0f b6 05 14 04 00 80 movzbl 0x80000414,%eax
80102faa: 0f b6 15 13 04 00 80 movzbl 0x80000413,%edx
80102fb1: c1 e0 08 shl $0x8,%eax
80102fb4: 09 d0 or %edx,%eax
80102fb6: c1 e0 0a shl $0xa,%eax
if((mp = mpsearch1(p-1024, 1024)))
80102fb9: 2d 00 04 00 00 sub $0x400,%eax
uint p;
struct mp *mp;
bda = (uchar *) P2V(0x400);
if((p = ((bda[0x0F]<<8)| bda[0x0E]) << 4)){
if((mp = mpsearch1(p, 1024)))
80102fbe: ba 00 04 00 00 mov $0x400,%edx
80102fc3: e8 48 ff ff ff call 80102f10 <mpsearch1>
80102fc8: 85 c0 test %eax,%eax
80102fca: 89 c7 mov %eax,%edi
80102fcc: 0f 84 22 01 00 00 je 801030f4 <mpinit+0x174>
mpconfig(struct mp **pmp)
{
struct mpconf *conf;
struct mp *mp;
if((mp = mpsearch()) == 0 || mp->physaddr == 0)
80102fd2: 8b 77 04 mov 0x4(%edi),%esi
80102fd5: 85 f6 test %esi,%esi
80102fd7: 0f 84 30 01 00 00 je 8010310d <mpinit+0x18d>
return 0;
conf = (struct mpconf*) P2V((uint) mp->physaddr);
80102fdd: 8d 86 00 00 00 80 lea -0x80000000(%esi),%eax
if(memcmp(conf, "PCMP", 4) != 0)
80102fe3: c7 44 24 08 04 00 00 movl $0x4,0x8(%esp)
80102fea: 00
80102feb: c7 44 24 04 9d 72 10 movl $0x8010729d,0x4(%esp)
80102ff2: 80
80102ff3: 89 04 24 mov %eax,(%esp)
struct mpconf *conf;
struct mp *mp;
if((mp = mpsearch()) == 0 || mp->physaddr == 0)
return 0;
conf = (struct mpconf*) P2V((uint) mp->physaddr);
80102ff6: 89 45 e4 mov %eax,-0x1c(%ebp)
if(memcmp(conf, "PCMP", 4) != 0)
80102ff9: e8 c2 12 00 00 call 801042c0 <memcmp>
80102ffe: 85 c0 test %eax,%eax
80103000: 0f 85 07 01 00 00 jne 8010310d <mpinit+0x18d>
return 0;
if(conf->version != 1 && conf->version != 4)
80103006: 0f b6 86 06 00 00 80 movzbl -0x7ffffffa(%esi),%eax
8010300d: 3c 04 cmp $0x4,%al
8010300f: 0f 85 0b 01 00 00 jne 80103120 <mpinit+0x1a0>
return 0;
if(sum((uchar*)conf, conf->length) != 0)
80103015: 0f b7 86 04 00 00 80 movzwl -0x7ffffffc(%esi),%eax
sum(uchar *addr, int len)
{
int i, sum;
sum = 0;
for(i=0; i<len; i++)
8010301c: 85 c0 test %eax,%eax
8010301e: 74 21 je 80103041 <mpinit+0xc1>
static uchar
sum(uchar *addr, int len)
{
int i, sum;
sum = 0;
80103020: 31 c9 xor %ecx,%ecx
for(i=0; i<len; i++)
80103022: 31 d2 xor %edx,%edx
80103024: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
sum += addr[i];
80103028: 0f b6 9c 16 00 00 00 movzbl -0x80000000(%esi,%edx,1),%ebx
8010302f: 80
sum(uchar *addr, int len)
{
int i, sum;
sum = 0;
for(i=0; i<len; i++)
80103030: 83 c2 01 add $0x1,%edx
sum += addr[i];
80103033: 01 d9 add %ebx,%ecx
sum(uchar *addr, int len)
{
int i, sum;
sum = 0;
for(i=0; i<len; i++)
80103035: 39 d0 cmp %edx,%eax
80103037: 7f ef jg 80103028 <mpinit+0xa8>
conf = (struct mpconf*) P2V((uint) mp->physaddr);
if(memcmp(conf, "PCMP", 4) != 0)
return 0;
if(conf->version != 1 && conf->version != 4)
return 0;
if(sum((uchar*)conf, conf->length) != 0)
80103039: 84 c9 test %cl,%cl
8010303b: 0f 85 cc 00 00 00 jne 8010310d <mpinit+0x18d>
struct mp *mp;
struct mpconf *conf;
struct mpproc *proc;
struct mpioapic *ioapic;
if((conf = mpconfig(&mp)) == 0)
80103041: 8b 45 e4 mov -0x1c(%ebp),%eax
80103044: 85 c0 test %eax,%eax
80103046: 0f 84 c1 00 00 00 je 8010310d <mpinit+0x18d>
panic("Expect to run on an SMP");
ismp = 1;
lapic = (uint*)conf->lapicaddr;
8010304c: 8b 86 24 00 00 80 mov -0x7fffffdc(%esi),%eax
struct mpproc *proc;
struct mpioapic *ioapic;
if((conf = mpconfig(&mp)) == 0)
panic("Expect to run on an SMP");
ismp = 1;
80103052: bb 01 00 00 00 mov $0x1,%ebx
lapic = (uint*)conf->lapicaddr;
80103057: a3 7c 26 11 80 mov %eax,0x8011267c
for(p=(uchar*)(conf+1), e=(uchar*)conf+conf->length; p<e; ){
8010305c: 0f b7 96 04 00 00 80 movzwl -0x7ffffffc(%esi),%edx
80103063: 8d 86 2c 00 00 80 lea -0x7fffffd4(%esi),%eax
80103069: 03 55 e4 add -0x1c(%ebp),%edx
8010306c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80103070: 39 c2 cmp %eax,%edx
80103072: 76 1b jbe 8010308f <mpinit+0x10f>
80103074: 0f b6 08 movzbl (%eax),%ecx
switch(*p){
80103077: 80 f9 04 cmp $0x4,%cl
8010307a: 77 74 ja 801030f0 <mpinit+0x170>
8010307c: ff 24 8d dc 72 10 80 jmp *-0x7fef8d24(,%ecx,4)
80103083: 90 nop
80103084: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
p += sizeof(struct mpioapic);
continue;
case MPBUS:
case MPIOINTR:
case MPLINTR:
p += 8;
80103088: 83 c0 08 add $0x8,%eax
if((conf = mpconfig(&mp)) == 0)
panic("Expect to run on an SMP");
ismp = 1;
lapic = (uint*)conf->lapicaddr;
for(p=(uchar*)(conf+1), e=(uchar*)conf+conf->length; p<e; ){
8010308b: 39 c2 cmp %eax,%edx
8010308d: 77 e5 ja 80103074 <mpinit+0xf4>
default:
ismp = 0;
break;
}
}
if(!ismp)
8010308f: 85 db test %ebx,%ebx
80103091: 0f 84 93 00 00 00 je 8010312a <mpinit+0x1aa>
panic("Didn't find a suitable machine");
if(mp->imcrp){
80103097: 80 7f 0c 00 cmpb $0x0,0xc(%edi)
8010309b: 74 12 je 801030af <mpinit+0x12f>
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
8010309d: ba 22 00 00 00 mov $0x22,%edx
801030a2: b8 70 00 00 00 mov $0x70,%eax
801030a7: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
801030a8: b2 23 mov $0x23,%dl
801030aa: ec in (%dx),%al
// Bochs doesn't support IMCR, so this doesn't run on Bochs.
// But it would on real hardware.
outb(0x22, 0x70); // Select IMCR
outb(0x23, inb(0x23) | 1); // Mask external interrupts.
801030ab: 83 c8 01 or $0x1,%eax
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
801030ae: ee out %al,(%dx)
}
}
801030af: 83 c4 1c add $0x1c,%esp
801030b2: 5b pop %ebx
801030b3: 5e pop %esi
801030b4: 5f pop %edi
801030b5: 5d pop %ebp
801030b6: c3 ret
801030b7: 90 nop
lapic = (uint*)conf->lapicaddr;
for(p=(uchar*)(conf+1), e=(uchar*)conf+conf->length; p<e; ){
switch(*p){
case MPPROC:
proc = (struct mpproc*)p;
if(ncpu < NCPU) {
801030b8: 8b 35 00 2d 11 80 mov 0x80112d00,%esi
801030be: 83 fe 07 cmp $0x7,%esi
801030c1: 7f 17 jg 801030da <mpinit+0x15a>
cpus[ncpu].apicid = proc->apicid; // apicid may differ from ncpu
801030c3: 0f b6 48 01 movzbl 0x1(%eax),%ecx
801030c7: 69 f6 b0 00 00 00 imul $0xb0,%esi,%esi
ncpu++;
801030cd: 83 05 00 2d 11 80 01 addl $0x1,0x80112d00
for(p=(uchar*)(conf+1), e=(uchar*)conf+conf->length; p<e; ){
switch(*p){
case MPPROC:
proc = (struct mpproc*)p;
if(ncpu < NCPU) {
cpus[ncpu].apicid = proc->apicid; // apicid may differ from ncpu
801030d4: 88 8e 80 27 11 80 mov %cl,-0x7feed880(%esi)
ncpu++;
}
p += sizeof(struct mpproc);
801030da: 83 c0 14 add $0x14,%eax
continue;
801030dd: eb 91 jmp 80103070 <mpinit+0xf0>
801030df: 90 nop
case MPIOAPIC:
ioapic = (struct mpioapic*)p;
ioapicid = ioapic->apicno;
801030e0: 0f b6 48 01 movzbl 0x1(%eax),%ecx
p += sizeof(struct mpioapic);
801030e4: 83 c0 08 add $0x8,%eax
}
p += sizeof(struct mpproc);
continue;
case MPIOAPIC:
ioapic = (struct mpioapic*)p;
ioapicid = ioapic->apicno;
801030e7: 88 0d 60 27 11 80 mov %cl,0x80112760
p += sizeof(struct mpioapic);
continue;
801030ed: eb 81 jmp 80103070 <mpinit+0xf0>
801030ef: 90 nop
case MPIOINTR:
case MPLINTR:
p += 8;
continue;
default:
ismp = 0;
801030f0: 31 db xor %ebx,%ebx
801030f2: eb 83 jmp 80103077 <mpinit+0xf7>
} else {
p = ((bda[0x14]<<8)|bda[0x13])*1024;
if((mp = mpsearch1(p-1024, 1024)))
return mp;
}
return mpsearch1(0xF0000, 0x10000);
801030f4: ba 00 00 01 00 mov $0x10000,%edx
801030f9: b8 00 00 0f 00 mov $0xf0000,%eax
801030fe: e8 0d fe ff ff call 80102f10 <mpsearch1>
mpconfig(struct mp **pmp)
{
struct mpconf *conf;
struct mp *mp;
if((mp = mpsearch()) == 0 || mp->physaddr == 0)
80103103: 85 c0 test %eax,%eax
} else {
p = ((bda[0x14]<<8)|bda[0x13])*1024;
if((mp = mpsearch1(p-1024, 1024)))
return mp;
}
return mpsearch1(0xF0000, 0x10000);
80103105: 89 c7 mov %eax,%edi
mpconfig(struct mp **pmp)
{
struct mpconf *conf;
struct mp *mp;
if((mp = mpsearch()) == 0 || mp->physaddr == 0)
80103107: 0f 85 c5 fe ff ff jne 80102fd2 <mpinit+0x52>
struct mpconf *conf;
struct mpproc *proc;
struct mpioapic *ioapic;
if((conf = mpconfig(&mp)) == 0)
panic("Expect to run on an SMP");
8010310d: c7 04 24 a2 72 10 80 movl $0x801072a2,(%esp)
80103114: e8 47 d2 ff ff call 80100360 <panic>
80103119: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
if((mp = mpsearch()) == 0 || mp->physaddr == 0)
return 0;
conf = (struct mpconf*) P2V((uint) mp->physaddr);
if(memcmp(conf, "PCMP", 4) != 0)
return 0;
if(conf->version != 1 && conf->version != 4)
80103120: 3c 01 cmp $0x1,%al
80103122: 0f 84 ed fe ff ff je 80103015 <mpinit+0x95>
80103128: eb e3 jmp 8010310d <mpinit+0x18d>
ismp = 0;
break;
}
}
if(!ismp)
panic("Didn't find a suitable machine");
8010312a: c7 04 24 bc 72 10 80 movl $0x801072bc,(%esp)
80103131: e8 2a d2 ff ff call 80100360 <panic>
80103136: 66 90 xchg %ax,%ax
80103138: 66 90 xchg %ax,%ax
8010313a: 66 90 xchg %ax,%ax
8010313c: 66 90 xchg %ax,%ax
8010313e: 66 90 xchg %ax,%ax
80103140 <picinit>:
#define IO_PIC2 0xA0 // Slave (IRQs 8-15)
// Don't use the 8259A interrupt controllers. Xv6 assumes SMP hardware.
void
picinit(void)
{
80103140: 55 push %ebp
80103141: ba 21 00 00 00 mov $0x21,%edx
80103146: 89 e5 mov %esp,%ebp
80103148: b8 ff ff ff ff mov $0xffffffff,%eax
8010314d: ee out %al,(%dx)
8010314e: b2 a1 mov $0xa1,%dl
80103150: ee out %al,(%dx)
// mask all interrupts
outb(IO_PIC1+1, 0xFF);
outb(IO_PIC2+1, 0xFF);
}
80103151: 5d pop %ebp
80103152: c3 ret
80103153: 66 90 xchg %ax,%ax
80103155: 66 90 xchg %ax,%ax
80103157: 66 90 xchg %ax,%ax
80103159: 66 90 xchg %ax,%ax
8010315b: 66 90 xchg %ax,%ax
8010315d: 66 90 xchg %ax,%ax
8010315f: 90 nop
80103160 <pipealloc>:
int writeopen; // write fd is still open
};
int
pipealloc(struct file **f0, struct file **f1)
{
80103160: 55 push %ebp
80103161: 89 e5 mov %esp,%ebp
80103163: 57 push %edi
80103164: 56 push %esi
80103165: 53 push %ebx
80103166: 83 ec 1c sub $0x1c,%esp
80103169: 8b 75 08 mov 0x8(%ebp),%esi
8010316c: 8b 5d 0c mov 0xc(%ebp),%ebx
struct pipe *p;
p = 0;
*f0 = *f1 = 0;
8010316f: c7 03 00 00 00 00 movl $0x0,(%ebx)
80103175: c7 06 00 00 00 00 movl $0x0,(%esi)
if((*f0 = filealloc()) == 0 || (*f1 = filealloc()) == 0)
8010317b: e8 d0 db ff ff call 80100d50 <filealloc>
80103180: 85 c0 test %eax,%eax
80103182: 89 06 mov %eax,(%esi)
80103184: 0f 84 a4 00 00 00 je 8010322e <pipealloc+0xce>
8010318a: e8 c1 db ff ff call 80100d50 <filealloc>
8010318f: 85 c0 test %eax,%eax
80103191: 89 03 mov %eax,(%ebx)
80103193: 0f 84 87 00 00 00 je 80103220 <pipealloc+0xc0>
goto bad;
if((p = (struct pipe*)kalloc()) == 0)
80103199: e8 f2 f2 ff ff call 80102490 <kalloc>
8010319e: 85 c0 test %eax,%eax
801031a0: 89 c7 mov %eax,%edi
801031a2: 74 7c je 80103220 <pipealloc+0xc0>
goto bad;
p->readopen = 1;
801031a4: c7 80 3c 02 00 00 01 movl $0x1,0x23c(%eax)
801031ab: 00 00 00
p->writeopen = 1;
801031ae: c7 80 40 02 00 00 01 movl $0x1,0x240(%eax)
801031b5: 00 00 00
p->nwrite = 0;
801031b8: c7 80 38 02 00 00 00 movl $0x0,0x238(%eax)
801031bf: 00 00 00
p->nread = 0;
801031c2: c7 80 34 02 00 00 00 movl $0x0,0x234(%eax)
801031c9: 00 00 00
initlock(&p->lock, "pipe");
801031cc: 89 04 24 mov %eax,(%esp)
801031cf: c7 44 24 04 f0 72 10 movl $0x801072f0,0x4(%esp)
801031d6: 80
801031d7: e8 64 0e 00 00 call 80104040 <initlock>
(*f0)->type = FD_PIPE;
801031dc: 8b 06 mov (%esi),%eax
801031de: c7 00 01 00 00 00 movl $0x1,(%eax)
(*f0)->readable = 1;
801031e4: 8b 06 mov (%esi),%eax
801031e6: c6 40 08 01 movb $0x1,0x8(%eax)
(*f0)->writable = 0;
801031ea: 8b 06 mov (%esi),%eax
801031ec: c6 40 09 00 movb $0x0,0x9(%eax)
(*f0)->pipe = p;
801031f0: 8b 06 mov (%esi),%eax
801031f2: 89 78 0c mov %edi,0xc(%eax)
(*f1)->type = FD_PIPE;
801031f5: 8b 03 mov (%ebx),%eax
801031f7: c7 00 01 00 00 00 movl $0x1,(%eax)
(*f1)->readable = 0;
801031fd: 8b 03 mov (%ebx),%eax
801031ff: c6 40 08 00 movb $0x0,0x8(%eax)
(*f1)->writable = 1;
80103203: 8b 03 mov (%ebx),%eax
80103205: c6 40 09 01 movb $0x1,0x9(%eax)
(*f1)->pipe = p;
80103209: 8b 03 mov (%ebx),%eax
return 0;
8010320b: 31 db xor %ebx,%ebx
(*f0)->writable = 0;
(*f0)->pipe = p;
(*f1)->type = FD_PIPE;
(*f1)->readable = 0;
(*f1)->writable = 1;
(*f1)->pipe = p;
8010320d: 89 78 0c mov %edi,0xc(%eax)
if(*f0)
fileclose(*f0);
if(*f1)
fileclose(*f1);
return -1;
}
80103210: 83 c4 1c add $0x1c,%esp
80103213: 89 d8 mov %ebx,%eax
80103215: 5b pop %ebx
80103216: 5e pop %esi
80103217: 5f pop %edi
80103218: 5d pop %ebp
80103219: c3 ret
8010321a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
//PAGEBREAK: 20
bad:
if(p)
kfree((char*)p);
if(*f0)
80103220: 8b 06 mov (%esi),%eax
80103222: 85 c0 test %eax,%eax
80103224: 74 08 je 8010322e <pipealloc+0xce>
fileclose(*f0);
80103226: 89 04 24 mov %eax,(%esp)
80103229: e8 e2 db ff ff call 80100e10 <fileclose>
if(*f1)
8010322e: 8b 03 mov (%ebx),%eax
fileclose(*f1);
return -1;
80103230: bb ff ff ff ff mov $0xffffffff,%ebx
bad:
if(p)
kfree((char*)p);
if(*f0)
fileclose(*f0);
if(*f1)
80103235: 85 c0 test %eax,%eax
80103237: 74 d7 je 80103210 <pipealloc+0xb0>
fileclose(*f1);
80103239: 89 04 24 mov %eax,(%esp)
8010323c: e8 cf db ff ff call 80100e10 <fileclose>
return -1;
}
80103241: 83 c4 1c add $0x1c,%esp
80103244: 89 d8 mov %ebx,%eax
80103246: 5b pop %ebx
80103247: 5e pop %esi
80103248: 5f pop %edi
80103249: 5d pop %ebp
8010324a: c3 ret
8010324b: 90 nop
8010324c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80103250 <pipeclose>:
void
pipeclose(struct pipe *p, int writable)
{
80103250: 55 push %ebp
80103251: 89 e5 mov %esp,%ebp
80103253: 56 push %esi
80103254: 53 push %ebx
80103255: 83 ec 10 sub $0x10,%esp
80103258: 8b 5d 08 mov 0x8(%ebp),%ebx
8010325b: 8b 75 0c mov 0xc(%ebp),%esi
acquire(&p->lock);
8010325e: 89 1c 24 mov %ebx,(%esp)
80103261: e8 ca 0e 00 00 call 80104130 <acquire>
if(writable){
80103266: 85 f6 test %esi,%esi
80103268: 74 3e je 801032a8 <pipeclose+0x58>
p->writeopen = 0;
wakeup(&p->nread);
8010326a: 8d 83 34 02 00 00 lea 0x234(%ebx),%eax
void
pipeclose(struct pipe *p, int writable)
{
acquire(&p->lock);
if(writable){
p->writeopen = 0;
80103270: c7 83 40 02 00 00 00 movl $0x0,0x240(%ebx)
80103277: 00 00 00
wakeup(&p->nread);
8010327a: 89 04 24 mov %eax,(%esp)
8010327d: e8 fe 0a 00 00 call 80103d80 <wakeup>
} else {
p->readopen = 0;
wakeup(&p->nwrite);
}
if(p->readopen == 0 && p->writeopen == 0){
80103282: 8b 93 3c 02 00 00 mov 0x23c(%ebx),%edx
80103288: 85 d2 test %edx,%edx
8010328a: 75 0a jne 80103296 <pipeclose+0x46>
8010328c: 8b 83 40 02 00 00 mov 0x240(%ebx),%eax
80103292: 85 c0 test %eax,%eax
80103294: 74 32 je 801032c8 <pipeclose+0x78>
release(&p->lock);
kfree((char*)p);
} else
release(&p->lock);
80103296: 89 5d 08 mov %ebx,0x8(%ebp)
}
80103299: 83 c4 10 add $0x10,%esp
8010329c: 5b pop %ebx
8010329d: 5e pop %esi
8010329e: 5d pop %ebp
}
if(p->readopen == 0 && p->writeopen == 0){
release(&p->lock);
kfree((char*)p);
} else
release(&p->lock);
8010329f: e9 7c 0f 00 00 jmp 80104220 <release>
801032a4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
if(writable){
p->writeopen = 0;
wakeup(&p->nread);
} else {
p->readopen = 0;
wakeup(&p->nwrite);
801032a8: 8d 83 38 02 00 00 lea 0x238(%ebx),%eax
acquire(&p->lock);
if(writable){
p->writeopen = 0;
wakeup(&p->nread);
} else {
p->readopen = 0;
801032ae: c7 83 3c 02 00 00 00 movl $0x0,0x23c(%ebx)
801032b5: 00 00 00
wakeup(&p->nwrite);
801032b8: 89 04 24 mov %eax,(%esp)
801032bb: e8 c0 0a 00 00 call 80103d80 <wakeup>
801032c0: eb c0 jmp 80103282 <pipeclose+0x32>
801032c2: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
}
if(p->readopen == 0 && p->writeopen == 0){
release(&p->lock);
801032c8: 89 1c 24 mov %ebx,(%esp)
801032cb: e8 50 0f 00 00 call 80104220 <release>
kfree((char*)p);
801032d0: 89 5d 08 mov %ebx,0x8(%ebp)
} else
release(&p->lock);
}
801032d3: 83 c4 10 add $0x10,%esp
801032d6: 5b pop %ebx
801032d7: 5e pop %esi
801032d8: 5d pop %ebp
p->readopen = 0;
wakeup(&p->nwrite);
}
if(p->readopen == 0 && p->writeopen == 0){
release(&p->lock);
kfree((char*)p);
801032d9: e9 02 f0 ff ff jmp 801022e0 <kfree>
801032de: 66 90 xchg %ax,%ax
801032e0 <pipewrite>:
}
//PAGEBREAK: 40
int
pipewrite(struct pipe *p, char *addr, int n)
{
801032e0: 55 push %ebp
801032e1: 89 e5 mov %esp,%ebp
801032e3: 57 push %edi
801032e4: 56 push %esi
801032e5: 53 push %ebx
801032e6: 83 ec 1c sub $0x1c,%esp
801032e9: 8b 5d 08 mov 0x8(%ebp),%ebx
int i;
acquire(&p->lock);
801032ec: 89 1c 24 mov %ebx,(%esp)
801032ef: e8 3c 0e 00 00 call 80104130 <acquire>
for(i = 0; i < n; i++){
801032f4: 8b 4d 10 mov 0x10(%ebp),%ecx
801032f7: 85 c9 test %ecx,%ecx
801032f9: 0f 8e b2 00 00 00 jle 801033b1 <pipewrite+0xd1>
801032ff: 8b 4d 0c mov 0xc(%ebp),%ecx
while(p->nwrite == p->nread + PIPESIZE){ //DOC: pipewrite-full
if(p->readopen == 0 || myproc()->killed){
release(&p->lock);
return -1;
}
wakeup(&p->nread);
80103302: 8d bb 34 02 00 00 lea 0x234(%ebx),%edi
80103308: 8b 83 38 02 00 00 mov 0x238(%ebx),%eax
sleep(&p->nwrite, &p->lock); //DOC: pipewrite-sleep
8010330e: 8d b3 38 02 00 00 lea 0x238(%ebx),%esi
80103314: 89 4d e4 mov %ecx,-0x1c(%ebp)
80103317: 03 4d 10 add 0x10(%ebp),%ecx
8010331a: 89 4d e0 mov %ecx,-0x20(%ebp)
{
int i;
acquire(&p->lock);
for(i = 0; i < n; i++){
while(p->nwrite == p->nread + PIPESIZE){ //DOC: pipewrite-full
8010331d: 8b 8b 34 02 00 00 mov 0x234(%ebx),%ecx
80103323: 81 c1 00 02 00 00 add $0x200,%ecx
80103329: 39 c8 cmp %ecx,%eax
8010332b: 74 38 je 80103365 <pipewrite+0x85>
8010332d: eb 55 jmp 80103384 <pipewrite+0xa4>
8010332f: 90 nop
if(p->readopen == 0 || myproc()->killed){
80103330: e8 5b 03 00 00 call 80103690 <myproc>
80103335: 8b 40 28 mov 0x28(%eax),%eax
80103338: 85 c0 test %eax,%eax
8010333a: 75 33 jne 8010336f <pipewrite+0x8f>
release(&p->lock);
return -1;
}
wakeup(&p->nread);
8010333c: 89 3c 24 mov %edi,(%esp)
8010333f: e8 3c 0a 00 00 call 80103d80 <wakeup>
sleep(&p->nwrite, &p->lock); //DOC: pipewrite-sleep
80103344: 89 5c 24 04 mov %ebx,0x4(%esp)
80103348: 89 34 24 mov %esi,(%esp)
8010334b: e8 a0 08 00 00 call 80103bf0 <sleep>
{
int i;
acquire(&p->lock);
for(i = 0; i < n; i++){
while(p->nwrite == p->nread + PIPESIZE){ //DOC: pipewrite-full
80103350: 8b 83 34 02 00 00 mov 0x234(%ebx),%eax
80103356: 8b 93 38 02 00 00 mov 0x238(%ebx),%edx
8010335c: 05 00 02 00 00 add $0x200,%eax
80103361: 39 c2 cmp %eax,%edx
80103363: 75 23 jne 80103388 <pipewrite+0xa8>
if(p->readopen == 0 || myproc()->killed){
80103365: 8b 93 3c 02 00 00 mov 0x23c(%ebx),%edx
8010336b: 85 d2 test %edx,%edx
8010336d: 75 c1 jne 80103330 <pipewrite+0x50>
release(&p->lock);
8010336f: 89 1c 24 mov %ebx,(%esp)
80103372: e8 a9 0e 00 00 call 80104220 <release>
return -1;
80103377: b8 ff ff ff ff mov $0xffffffff,%eax
p->data[p->nwrite++ % PIPESIZE] = addr[i];
}
wakeup(&p->nread); //DOC: pipewrite-wakeup1
release(&p->lock);
return n;
}
8010337c: 83 c4 1c add $0x1c,%esp
8010337f: 5b pop %ebx
80103380: 5e pop %esi
80103381: 5f pop %edi
80103382: 5d pop %ebp
80103383: c3 ret
{
int i;
acquire(&p->lock);
for(i = 0; i < n; i++){
while(p->nwrite == p->nread + PIPESIZE){ //DOC: pipewrite-full
80103384: 89 c2 mov %eax,%edx
80103386: 66 90 xchg %ax,%ax
return -1;
}
wakeup(&p->nread);
sleep(&p->nwrite, &p->lock); //DOC: pipewrite-sleep
}
p->data[p->nwrite++ % PIPESIZE] = addr[i];
80103388: 8b 4d e4 mov -0x1c(%ebp),%ecx
8010338b: 8d 42 01 lea 0x1(%edx),%eax
8010338e: 81 e2 ff 01 00 00 and $0x1ff,%edx
80103394: 89 83 38 02 00 00 mov %eax,0x238(%ebx)
8010339a: 83 45 e4 01 addl $0x1,-0x1c(%ebp)
8010339e: 0f b6 09 movzbl (%ecx),%ecx
801033a1: 88 4c 13 34 mov %cl,0x34(%ebx,%edx,1)
pipewrite(struct pipe *p, char *addr, int n)
{
int i;
acquire(&p->lock);
for(i = 0; i < n; i++){
801033a5: 8b 4d e4 mov -0x1c(%ebp),%ecx
801033a8: 3b 4d e0 cmp -0x20(%ebp),%ecx
801033ab: 0f 85 6c ff ff ff jne 8010331d <pipewrite+0x3d>
wakeup(&p->nread);
sleep(&p->nwrite, &p->lock); //DOC: pipewrite-sleep
}
p->data[p->nwrite++ % PIPESIZE] = addr[i];
}
wakeup(&p->nread); //DOC: pipewrite-wakeup1
801033b1: 8d 83 34 02 00 00 lea 0x234(%ebx),%eax
801033b7: 89 04 24 mov %eax,(%esp)
801033ba: e8 c1 09 00 00 call 80103d80 <wakeup>
release(&p->lock);
801033bf: 89 1c 24 mov %ebx,(%esp)
801033c2: e8 59 0e 00 00 call 80104220 <release>
return n;
801033c7: 8b 45 10 mov 0x10(%ebp),%eax
801033ca: eb b0 jmp 8010337c <pipewrite+0x9c>
801033cc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
801033d0 <piperead>:
}
int
piperead(struct pipe *p, char *addr, int n)
{
801033d0: 55 push %ebp
801033d1: 89 e5 mov %esp,%ebp
801033d3: 57 push %edi
801033d4: 56 push %esi
801033d5: 53 push %ebx
801033d6: 83 ec 1c sub $0x1c,%esp
801033d9: 8b 75 08 mov 0x8(%ebp),%esi
801033dc: 8b 7d 0c mov 0xc(%ebp),%edi
int i;
acquire(&p->lock);
801033df: 89 34 24 mov %esi,(%esp)
801033e2: e8 49 0d 00 00 call 80104130 <acquire>
while(p->nread == p->nwrite && p->writeopen){ //DOC: pipe-empty
801033e7: 8b 86 34 02 00 00 mov 0x234(%esi),%eax
801033ed: 3b 86 38 02 00 00 cmp 0x238(%esi),%eax
801033f3: 75 5b jne 80103450 <piperead+0x80>
801033f5: 8b 9e 40 02 00 00 mov 0x240(%esi),%ebx
801033fb: 85 db test %ebx,%ebx
801033fd: 74 51 je 80103450 <piperead+0x80>
if(myproc()->killed){
release(&p->lock);
return -1;
}
sleep(&p->nread, &p->lock); //DOC: piperead-sleep
801033ff: 8d 9e 34 02 00 00 lea 0x234(%esi),%ebx
80103405: eb 25 jmp 8010342c <piperead+0x5c>
80103407: 90 nop
80103408: 89 74 24 04 mov %esi,0x4(%esp)
8010340c: 89 1c 24 mov %ebx,(%esp)
8010340f: e8 dc 07 00 00 call 80103bf0 <sleep>
piperead(struct pipe *p, char *addr, int n)
{
int i;
acquire(&p->lock);
while(p->nread == p->nwrite && p->writeopen){ //DOC: pipe-empty
80103414: 8b 86 34 02 00 00 mov 0x234(%esi),%eax
8010341a: 3b 86 38 02 00 00 cmp 0x238(%esi),%eax
80103420: 75 2e jne 80103450 <piperead+0x80>
80103422: 8b 96 40 02 00 00 mov 0x240(%esi),%edx
80103428: 85 d2 test %edx,%edx
8010342a: 74 24 je 80103450 <piperead+0x80>
if(myproc()->killed){
8010342c: e8 5f 02 00 00 call 80103690 <myproc>
80103431: 8b 48 28 mov 0x28(%eax),%ecx
80103434: 85 c9 test %ecx,%ecx
80103436: 74 d0 je 80103408 <piperead+0x38>
release(&p->lock);
80103438: 89 34 24 mov %esi,(%esp)
8010343b: e8 e0 0d 00 00 call 80104220 <release>
addr[i] = p->data[p->nread++ % PIPESIZE];
}
wakeup(&p->nwrite); //DOC: piperead-wakeup
release(&p->lock);
return i;
}
80103440: 83 c4 1c add $0x1c,%esp
acquire(&p->lock);
while(p->nread == p->nwrite && p->writeopen){ //DOC: pipe-empty
if(myproc()->killed){
release(&p->lock);
return -1;
80103443: b8 ff ff ff ff mov $0xffffffff,%eax
addr[i] = p->data[p->nread++ % PIPESIZE];
}
wakeup(&p->nwrite); //DOC: piperead-wakeup
release(&p->lock);
return i;
}
80103448: 5b pop %ebx
80103449: 5e pop %esi
8010344a: 5f pop %edi
8010344b: 5d pop %ebp
8010344c: c3 ret
8010344d: 8d 76 00 lea 0x0(%esi),%esi
release(&p->lock);
return -1;
}
sleep(&p->nread, &p->lock); //DOC: piperead-sleep
}
for(i = 0; i < n; i++){ //DOC: piperead-copy
80103450: 8b 55 10 mov 0x10(%ebp),%edx
if(p->nread == p->nwrite)
80103453: 31 db xor %ebx,%ebx
release(&p->lock);
return -1;
}
sleep(&p->nread, &p->lock); //DOC: piperead-sleep
}
for(i = 0; i < n; i++){ //DOC: piperead-copy
80103455: 85 d2 test %edx,%edx
80103457: 7f 2b jg 80103484 <piperead+0xb4>
80103459: eb 31 jmp 8010348c <piperead+0xbc>
8010345b: 90 nop
8010345c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
if(p->nread == p->nwrite)
break;
addr[i] = p->data[p->nread++ % PIPESIZE];
80103460: 8d 48 01 lea 0x1(%eax),%ecx
80103463: 25 ff 01 00 00 and $0x1ff,%eax
80103468: 89 8e 34 02 00 00 mov %ecx,0x234(%esi)
8010346e: 0f b6 44 06 34 movzbl 0x34(%esi,%eax,1),%eax
80103473: 88 04 1f mov %al,(%edi,%ebx,1)
release(&p->lock);
return -1;
}
sleep(&p->nread, &p->lock); //DOC: piperead-sleep
}
for(i = 0; i < n; i++){ //DOC: piperead-copy
80103476: 83 c3 01 add $0x1,%ebx
80103479: 3b 5d 10 cmp 0x10(%ebp),%ebx
8010347c: 74 0e je 8010348c <piperead+0xbc>
if(p->nread == p->nwrite)
8010347e: 8b 86 34 02 00 00 mov 0x234(%esi),%eax
80103484: 3b 86 38 02 00 00 cmp 0x238(%esi),%eax
8010348a: 75 d4 jne 80103460 <piperead+0x90>
break;
addr[i] = p->data[p->nread++ % PIPESIZE];
}
wakeup(&p->nwrite); //DOC: piperead-wakeup
8010348c: 8d 86 38 02 00 00 lea 0x238(%esi),%eax
80103492: 89 04 24 mov %eax,(%esp)
80103495: e8 e6 08 00 00 call 80103d80 <wakeup>
release(&p->lock);
8010349a: 89 34 24 mov %esi,(%esp)
8010349d: e8 7e 0d 00 00 call 80104220 <release>
return i;
}
801034a2: 83 c4 1c add $0x1c,%esp
break;
addr[i] = p->data[p->nread++ % PIPESIZE];
}
wakeup(&p->nwrite); //DOC: piperead-wakeup
release(&p->lock);
return i;
801034a5: 89 d8 mov %ebx,%eax
}
801034a7: 5b pop %ebx
801034a8: 5e pop %esi
801034a9: 5f pop %edi
801034aa: 5d pop %ebp
801034ab: c3 ret
801034ac: 66 90 xchg %ax,%ax
801034ae: 66 90 xchg %ax,%ax
801034b0 <allocproc>:
// If found, change state to EMBRYO and initialize
// state required to run in the kernel.
// Otherwise return 0.
static struct proc*
allocproc(void)
{
801034b0: 55 push %ebp
801034b1: 89 e5 mov %esp,%ebp
801034b3: 53 push %ebx
struct proc *p;
char *sp;
acquire(&ptable.lock);
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++)
801034b4: bb 54 2d 11 80 mov $0x80112d54,%ebx
// If found, change state to EMBRYO and initialize
// state required to run in the kernel.
// Otherwise return 0.
static struct proc*
allocproc(void)
{
801034b9: 83 ec 14 sub $0x14,%esp
struct proc *p;
char *sp;
acquire(&ptable.lock);
801034bc: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
801034c3: e8 68 0c 00 00 call 80104130 <acquire>
801034c8: eb 11 jmp 801034db <allocproc+0x2b>
801034ca: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++)
801034d0: 83 eb 80 sub $0xffffff80,%ebx
801034d3: 81 fb 54 4d 11 80 cmp $0x80114d54,%ebx
801034d9: 74 7d je 80103558 <allocproc+0xa8>
if(p->state == UNUSED)
801034db: 8b 43 10 mov 0x10(%ebx),%eax
801034de: 85 c0 test %eax,%eax
801034e0: 75 ee jne 801034d0 <allocproc+0x20>
release(&ptable.lock);
return 0;
found:
p->state = EMBRYO;
p->pid = nextpid++;
801034e2: a1 04 a0 10 80 mov 0x8010a004,%eax
release(&ptable.lock);
801034e7: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
release(&ptable.lock);
return 0;
found:
p->state = EMBRYO;
801034ee: c7 43 10 01 00 00 00 movl $0x1,0x10(%ebx)
p->pid = nextpid++;
801034f5: 8d 50 01 lea 0x1(%eax),%edx
801034f8: 89 15 04 a0 10 80 mov %edx,0x8010a004
801034fe: 89 43 14 mov %eax,0x14(%ebx)
release(&ptable.lock);
80103501: e8 1a 0d 00 00 call 80104220 <release>
// Allocate kernel stack.
if((p->kstack = kalloc()) == 0){
80103506: e8 85 ef ff ff call 80102490 <kalloc>
8010350b: 85 c0 test %eax,%eax
8010350d: 89 43 0c mov %eax,0xc(%ebx)
80103510: 74 5a je 8010356c <allocproc+0xbc>
return 0;
}
sp = p->kstack + KSTACKSIZE;
// Leave room for trap frame.
sp -= sizeof *p->tf;
80103512: 8d 90 b4 0f 00 00 lea 0xfb4(%eax),%edx
// Set up new context to start executing at forkret,
// which returns to trapret.
sp -= 4;
*(uint*)sp = (uint)trapret;
sp -= sizeof *p->context;
80103518: 05 9c 0f 00 00 add $0xf9c,%eax
return 0;
}
sp = p->kstack + KSTACKSIZE;
// Leave room for trap frame.
sp -= sizeof *p->tf;
8010351d: 89 53 1c mov %edx,0x1c(%ebx)
p->tf = (struct trapframe*)sp;
// Set up new context to start executing at forkret,
// which returns to trapret.
sp -= 4;
*(uint*)sp = (uint)trapret;
80103520: c7 40 14 05 54 10 80 movl $0x80105405,0x14(%eax)
sp -= sizeof *p->context;
p->context = (struct context*)sp;
memset(p->context, 0, sizeof *p->context);
80103527: c7 44 24 08 14 00 00 movl $0x14,0x8(%esp)
8010352e: 00
8010352f: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
80103536: 00
80103537: 89 04 24 mov %eax,(%esp)
// which returns to trapret.
sp -= 4;
*(uint*)sp = (uint)trapret;
sp -= sizeof *p->context;
p->context = (struct context*)sp;
8010353a: 89 43 20 mov %eax,0x20(%ebx)
memset(p->context, 0, sizeof *p->context);
8010353d: e8 2e 0d 00 00 call 80104270 <memset>
p->context->eip = (uint)forkret;
80103542: 8b 43 20 mov 0x20(%ebx),%eax
80103545: c7 40 10 80 35 10 80 movl $0x80103580,0x10(%eax)
return p;
8010354c: 89 d8 mov %ebx,%eax
}
8010354e: 83 c4 14 add $0x14,%esp
80103551: 5b pop %ebx
80103552: 5d pop %ebp
80103553: c3 ret
80103554: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++)
if(p->state == UNUSED)
goto found;
release(&ptable.lock);
80103558: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
8010355f: e8 bc 0c 00 00 call 80104220 <release>
p->context = (struct context*)sp;
memset(p->context, 0, sizeof *p->context);
p->context->eip = (uint)forkret;
return p;
}
80103564: 83 c4 14 add $0x14,%esp
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++)
if(p->state == UNUSED)
goto found;
release(&ptable.lock);
return 0;
80103567: 31 c0 xor %eax,%eax
p->context = (struct context*)sp;
memset(p->context, 0, sizeof *p->context);
p->context->eip = (uint)forkret;
return p;
}
80103569: 5b pop %ebx
8010356a: 5d pop %ebp
8010356b: c3 ret
release(&ptable.lock);
// Allocate kernel stack.
if((p->kstack = kalloc()) == 0){
p->state = UNUSED;
8010356c: c7 43 10 00 00 00 00 movl $0x0,0x10(%ebx)
return 0;
80103573: eb d9 jmp 8010354e <allocproc+0x9e>
80103575: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80103579: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80103580 <forkret>:
// A fork child's very first scheduling by scheduler()
// will swtch here. "Return" to user space.
void
forkret(void)
{
80103580: 55 push %ebp
80103581: 89 e5 mov %esp,%ebp
80103583: 83 ec 18 sub $0x18,%esp
static int first = 1;
// Still holding ptable.lock from scheduler.
release(&ptable.lock);
80103586: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
8010358d: e8 8e 0c 00 00 call 80104220 <release>
if (first) {
80103592: a1 00 a0 10 80 mov 0x8010a000,%eax
80103597: 85 c0 test %eax,%eax
80103599: 75 05 jne 801035a0 <forkret+0x20>
iinit(ROOTDEV);
initlog(ROOTDEV);
}
// Return to "caller", actually trapret (see allocproc).
}
8010359b: c9 leave
8010359c: c3 ret
8010359d: 8d 76 00 lea 0x0(%esi),%esi
if (first) {
// Some initialization functions must be run in the context
// of a regular process (e.g., they call sleep), and thus cannot
// be run from main().
first = 0;
iinit(ROOTDEV);
801035a0: c7 04 24 01 00 00 00 movl $0x1,(%esp)
if (first) {
// Some initialization functions must be run in the context
// of a regular process (e.g., they call sleep), and thus cannot
// be run from main().
first = 0;
801035a7: c7 05 00 a0 10 80 00 movl $0x0,0x8010a000
801035ae: 00 00 00
iinit(ROOTDEV);
801035b1: e8 aa de ff ff call 80101460 <iinit>
initlog(ROOTDEV);
801035b6: c7 04 24 01 00 00 00 movl $0x1,(%esp)
801035bd: e8 9e f4 ff ff call 80102a60 <initlog>
}
// Return to "caller", actually trapret (see allocproc).
}
801035c2: c9 leave
801035c3: c3 ret
801035c4: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
801035ca: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
801035d0 <pinit>:
static void wakeup1(void *chan);
void
pinit(void)
{
801035d0: 55 push %ebp
801035d1: 89 e5 mov %esp,%ebp
801035d3: 83 ec 18 sub $0x18,%esp
initlock(&ptable.lock, "ptable");
801035d6: c7 44 24 04 f5 72 10 movl $0x801072f5,0x4(%esp)
801035dd: 80
801035de: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
801035e5: e8 56 0a 00 00 call 80104040 <initlock>
}
801035ea: c9 leave
801035eb: c3 ret
801035ec: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
801035f0 <mycpu>:
// Must be called with interrupts disabled to avoid the caller being
// rescheduled between reading lapicid and running through the loop.
struct cpu*
mycpu(void)
{
801035f0: 55 push %ebp
801035f1: 89 e5 mov %esp,%ebp
801035f3: 56 push %esi
801035f4: 53 push %ebx
801035f5: 83 ec 10 sub $0x10,%esp
static inline uint
readeflags(void)
{
uint eflags;
asm volatile("pushfl; popl %0" : "=r" (eflags));
801035f8: 9c pushf
801035f9: 58 pop %eax
int apicid, i;
if(readeflags()&FL_IF)
801035fa: f6 c4 02 test $0x2,%ah
801035fd: 75 57 jne 80103656 <mycpu+0x66>
panic("mycpu called with interrupts enabled\n");
apicid = lapicid();
801035ff: e8 4c f1 ff ff call 80102750 <lapicid>
// APIC IDs are not guaranteed to be contiguous. Maybe we should have
// a reverse map, or reserve a register to store &cpus[i].
for (i = 0; i < ncpu; ++i) {
80103604: 8b 35 00 2d 11 80 mov 0x80112d00,%esi
8010360a: 85 f6 test %esi,%esi
8010360c: 7e 3c jle 8010364a <mycpu+0x5a>
if (cpus[i].apicid == apicid)
8010360e: 0f b6 15 80 27 11 80 movzbl 0x80112780,%edx
80103615: 39 c2 cmp %eax,%edx
80103617: 74 2d je 80103646 <mycpu+0x56>
80103619: b9 30 28 11 80 mov $0x80112830,%ecx
panic("mycpu called with interrupts enabled\n");
apicid = lapicid();
// APIC IDs are not guaranteed to be contiguous. Maybe we should have
// a reverse map, or reserve a register to store &cpus[i].
for (i = 0; i < ncpu; ++i) {
8010361e: 31 d2 xor %edx,%edx
80103620: 83 c2 01 add $0x1,%edx
80103623: 39 f2 cmp %esi,%edx
80103625: 74 23 je 8010364a <mycpu+0x5a>
if (cpus[i].apicid == apicid)
80103627: 0f b6 19 movzbl (%ecx),%ebx
8010362a: 81 c1 b0 00 00 00 add $0xb0,%ecx
80103630: 39 c3 cmp %eax,%ebx
80103632: 75 ec jne 80103620 <mycpu+0x30>
return &cpus[i];
80103634: 69 c2 b0 00 00 00 imul $0xb0,%edx,%eax
}
panic("unknown apicid\n");
}
8010363a: 83 c4 10 add $0x10,%esp
8010363d: 5b pop %ebx
8010363e: 5e pop %esi
8010363f: 5d pop %ebp
apicid = lapicid();
// APIC IDs are not guaranteed to be contiguous. Maybe we should have
// a reverse map, or reserve a register to store &cpus[i].
for (i = 0; i < ncpu; ++i) {
if (cpus[i].apicid == apicid)
return &cpus[i];
80103640: 05 80 27 11 80 add $0x80112780,%eax
}
panic("unknown apicid\n");
}
80103645: c3 ret
panic("mycpu called with interrupts enabled\n");
apicid = lapicid();
// APIC IDs are not guaranteed to be contiguous. Maybe we should have
// a reverse map, or reserve a register to store &cpus[i].
for (i = 0; i < ncpu; ++i) {
80103646: 31 d2 xor %edx,%edx
80103648: eb ea jmp 80103634 <mycpu+0x44>
if (cpus[i].apicid == apicid)
return &cpus[i];
}
panic("unknown apicid\n");
8010364a: c7 04 24 fc 72 10 80 movl $0x801072fc,(%esp)
80103651: e8 0a cd ff ff call 80100360 <panic>
mycpu(void)
{
int apicid, i;
if(readeflags()&FL_IF)
panic("mycpu called with interrupts enabled\n");
80103656: c7 04 24 d8 73 10 80 movl $0x801073d8,(%esp)
8010365d: e8 fe cc ff ff call 80100360 <panic>
80103662: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80103669: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80103670 <cpuid>:
initlock(&ptable.lock, "ptable");
}
// Must be called with interrupts disabled
int
cpuid() {
80103670: 55 push %ebp
80103671: 89 e5 mov %esp,%ebp
80103673: 83 ec 08 sub $0x8,%esp
return mycpu()-cpus;
80103676: e8 75 ff ff ff call 801035f0 <mycpu>
}
8010367b: c9 leave
}
// Must be called with interrupts disabled
int
cpuid() {
return mycpu()-cpus;
8010367c: 2d 80 27 11 80 sub $0x80112780,%eax
80103681: c1 f8 04 sar $0x4,%eax
80103684: 69 c0 a3 8b 2e ba imul $0xba2e8ba3,%eax,%eax
}
8010368a: c3 ret
8010368b: 90 nop
8010368c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80103690 <myproc>:
}
// Disable interrupts so that we are not rescheduled
// while reading proc from the cpu structure
struct proc*
myproc(void) {
80103690: 55 push %ebp
80103691: 89 e5 mov %esp,%ebp
80103693: 53 push %ebx
80103694: 83 ec 04 sub $0x4,%esp
struct cpu *c;
struct proc *p;
pushcli();
80103697: e8 54 0a 00 00 call 801040f0 <pushcli>
c = mycpu();
8010369c: e8 4f ff ff ff call 801035f0 <mycpu>
p = c->proc;
801036a1: 8b 98 ac 00 00 00 mov 0xac(%eax),%ebx
popcli();
801036a7: e8 04 0b 00 00 call 801041b0 <popcli>
return p;
}
801036ac: 83 c4 04 add $0x4,%esp
801036af: 89 d8 mov %ebx,%eax
801036b1: 5b pop %ebx
801036b2: 5d pop %ebp
801036b3: c3 ret
801036b4: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
801036ba: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
801036c0 <userinit>:
//PAGEBREAK: 32
// Set up first user process.
void
userinit(void)
{
801036c0: 55 push %ebp
801036c1: 89 e5 mov %esp,%ebp
801036c3: 53 push %ebx
801036c4: 83 ec 14 sub $0x14,%esp
struct proc *p;
extern char _binary_initcode_start[], _binary_initcode_size[];
p = allocproc();
801036c7: e8 e4 fd ff ff call 801034b0 <allocproc>
801036cc: 89 c3 mov %eax,%ebx
initproc = p;
801036ce: a3 b8 a5 10 80 mov %eax,0x8010a5b8
if((p->pgdir = setupkvm()) == 0)
801036d3: e8 e8 32 00 00 call 801069c0 <setupkvm>
801036d8: 85 c0 test %eax,%eax
801036da: 89 43 08 mov %eax,0x8(%ebx)
801036dd: 0f 84 d4 00 00 00 je 801037b7 <userinit+0xf7>
panic("userinit: out of memory?");
inituvm(p->pgdir, _binary_initcode_start, (int)_binary_initcode_size);
801036e3: 89 04 24 mov %eax,(%esp)
801036e6: c7 44 24 08 2c 00 00 movl $0x2c,0x8(%esp)
801036ed: 00
801036ee: c7 44 24 04 60 a4 10 movl $0x8010a460,0x4(%esp)
801036f5: 80
801036f6: e8 d5 2f 00 00 call 801066d0 <inituvm>
p->sz = PGSIZE;
801036fb: c7 03 00 10 00 00 movl $0x1000,(%ebx)
memset(p->tf, 0, sizeof(*p->tf));
80103701: c7 44 24 08 4c 00 00 movl $0x4c,0x8(%esp)
80103708: 00
80103709: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
80103710: 00
80103711: 8b 43 1c mov 0x1c(%ebx),%eax
80103714: 89 04 24 mov %eax,(%esp)
80103717: e8 54 0b 00 00 call 80104270 <memset>
p->tf->cs = (SEG_UCODE << 3) | DPL_USER;
8010371c: 8b 43 1c mov 0x1c(%ebx),%eax
8010371f: ba 1b 00 00 00 mov $0x1b,%edx
p->tf->ds = (SEG_UDATA << 3) | DPL_USER;
80103724: b9 23 00 00 00 mov $0x23,%ecx
if((p->pgdir = setupkvm()) == 0)
panic("userinit: out of memory?");
inituvm(p->pgdir, _binary_initcode_start, (int)_binary_initcode_size);
p->sz = PGSIZE;
memset(p->tf, 0, sizeof(*p->tf));
p->tf->cs = (SEG_UCODE << 3) | DPL_USER;
80103729: 66 89 50 3c mov %dx,0x3c(%eax)
p->tf->ds = (SEG_UDATA << 3) | DPL_USER;
8010372d: 8b 43 1c mov 0x1c(%ebx),%eax
80103730: 66 89 48 2c mov %cx,0x2c(%eax)
p->tf->es = p->tf->ds;
80103734: 8b 43 1c mov 0x1c(%ebx),%eax
80103737: 0f b7 50 2c movzwl 0x2c(%eax),%edx
8010373b: 66 89 50 28 mov %dx,0x28(%eax)
p->tf->ss = p->tf->ds;
8010373f: 8b 43 1c mov 0x1c(%ebx),%eax
80103742: 0f b7 50 2c movzwl 0x2c(%eax),%edx
80103746: 66 89 50 48 mov %dx,0x48(%eax)
p->tf->eflags = FL_IF;
8010374a: 8b 43 1c mov 0x1c(%ebx),%eax
8010374d: c7 40 40 00 02 00 00 movl $0x200,0x40(%eax)
p->tf->esp = PGSIZE;
80103754: 8b 43 1c mov 0x1c(%ebx),%eax
80103757: c7 40 44 00 10 00 00 movl $0x1000,0x44(%eax)
p->tf->eip = 0; // beginning of initcode.S
8010375e: 8b 43 1c mov 0x1c(%ebx),%eax
80103761: c7 40 38 00 00 00 00 movl $0x0,0x38(%eax)
safestrcpy(p->name, "initcode", sizeof(p->name));
80103768: 8d 43 70 lea 0x70(%ebx),%eax
8010376b: c7 44 24 08 10 00 00 movl $0x10,0x8(%esp)
80103772: 00
80103773: c7 44 24 04 25 73 10 movl $0x80107325,0x4(%esp)
8010377a: 80
8010377b: 89 04 24 mov %eax,(%esp)
8010377e: e8 cd 0c 00 00 call 80104450 <safestrcpy>
p->cwd = namei("/");
80103783: c7 04 24 2e 73 10 80 movl $0x8010732e,(%esp)
8010378a: e8 61 e7 ff ff call 80101ef0 <namei>
8010378f: 89 43 6c mov %eax,0x6c(%ebx)
// this assignment to p->state lets other cores
// run this process. the acquire forces the above
// writes to be visible, and the lock is also needed
// because the assignment might not be atomic.
acquire(&ptable.lock);
80103792: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103799: e8 92 09 00 00 call 80104130 <acquire>
p->state = RUNNABLE;
8010379e: c7 43 10 03 00 00 00 movl $0x3,0x10(%ebx)
release(&ptable.lock);
801037a5: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
801037ac: e8 6f 0a 00 00 call 80104220 <release>
}
801037b1: 83 c4 14 add $0x14,%esp
801037b4: 5b pop %ebx
801037b5: 5d pop %ebp
801037b6: c3 ret
p = allocproc();
initproc = p;
if((p->pgdir = setupkvm()) == 0)
panic("userinit: out of memory?");
801037b7: c7 04 24 0c 73 10 80 movl $0x8010730c,(%esp)
801037be: e8 9d cb ff ff call 80100360 <panic>
801037c3: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
801037c9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801037d0 <growproc>:
// Grow current process's memory by n bytes.
// Return 0 on success, -1 on failure.
int
growproc(int n)
{
801037d0: 55 push %ebp
801037d1: 89 e5 mov %esp,%ebp
801037d3: 56 push %esi
801037d4: 53 push %ebx
801037d5: 83 ec 10 sub $0x10,%esp
801037d8: 8b 75 08 mov 0x8(%ebp),%esi
uint sz;
struct proc *curproc = myproc();
801037db: e8 b0 fe ff ff call 80103690 <myproc>
sz = curproc->sz;
if(n > 0){
801037e0: 83 fe 00 cmp $0x0,%esi
// Return 0 on success, -1 on failure.
int
growproc(int n)
{
uint sz;
struct proc *curproc = myproc();
801037e3: 89 c3 mov %eax,%ebx
sz = curproc->sz;
801037e5: 8b 00 mov (%eax),%eax
if(n > 0){
801037e7: 7e 2f jle 80103818 <growproc+0x48>
if((sz = allocuvm(curproc->pgdir, sz, sz + n)) == 0)
801037e9: 01 c6 add %eax,%esi
801037eb: 89 74 24 08 mov %esi,0x8(%esp)
801037ef: 89 44 24 04 mov %eax,0x4(%esp)
801037f3: 8b 43 08 mov 0x8(%ebx),%eax
801037f6: 89 04 24 mov %eax,(%esp)
801037f9: e8 22 30 00 00 call 80106820 <allocuvm>
801037fe: 85 c0 test %eax,%eax
80103800: 74 36 je 80103838 <growproc+0x68>
return -1;
} else if(n < 0){
if((sz = deallocuvm(curproc->pgdir, sz, sz + n)) == 0)
return -1;
}
curproc->sz = sz;
80103802: 89 03 mov %eax,(%ebx)
switchuvm(curproc);
80103804: 89 1c 24 mov %ebx,(%esp)
80103807: e8 b4 2d 00 00 call 801065c0 <switchuvm>
return 0;
8010380c: 31 c0 xor %eax,%eax
}
8010380e: 83 c4 10 add $0x10,%esp
80103811: 5b pop %ebx
80103812: 5e pop %esi
80103813: 5d pop %ebp
80103814: c3 ret
80103815: 8d 76 00 lea 0x0(%esi),%esi
sz = curproc->sz;
if(n > 0){
if((sz = allocuvm(curproc->pgdir, sz, sz + n)) == 0)
return -1;
} else if(n < 0){
80103818: 74 e8 je 80103802 <growproc+0x32>
if((sz = deallocuvm(curproc->pgdir, sz, sz + n)) == 0)
8010381a: 01 c6 add %eax,%esi
8010381c: 89 74 24 08 mov %esi,0x8(%esp)
80103820: 89 44 24 04 mov %eax,0x4(%esp)
80103824: 8b 43 08 mov 0x8(%ebx),%eax
80103827: 89 04 24 mov %eax,(%esp)
8010382a: e8 f1 30 00 00 call 80106920 <deallocuvm>
8010382f: 85 c0 test %eax,%eax
80103831: 75 cf jne 80103802 <growproc+0x32>
80103833: 90 nop
80103834: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
struct proc *curproc = myproc();
sz = curproc->sz;
if(n > 0){
if((sz = allocuvm(curproc->pgdir, sz, sz + n)) == 0)
return -1;
80103838: b8 ff ff ff ff mov $0xffffffff,%eax
8010383d: eb cf jmp 8010380e <growproc+0x3e>
8010383f: 90 nop
80103840 <fork>:
// Create a new process copying p as the parent.
// Sets up stack to return as if from system call.
// Caller must set state of returned proc to RUNNABLE.
int
fork(void)
{
80103840: 55 push %ebp
80103841: 89 e5 mov %esp,%ebp
80103843: 57 push %edi
80103844: 56 push %esi
80103845: 53 push %ebx
80103846: 83 ec 1c sub $0x1c,%esp
int i, pid;
struct proc *np;
struct proc *curproc = myproc();
80103849: e8 42 fe ff ff call 80103690 <myproc>
8010384e: 89 c3 mov %eax,%ebx
// Allocate process.
if((np = allocproc()) == 0){
80103850: e8 5b fc ff ff call 801034b0 <allocproc>
80103855: 85 c0 test %eax,%eax
80103857: 89 c7 mov %eax,%edi
80103859: 89 45 e4 mov %eax,-0x1c(%ebp)
8010385c: 0f 84 c4 00 00 00 je 80103926 <fork+0xe6>
return -1;
}
// Copy process state from proc.
if((np->pgdir = copyuvm(curproc->pgdir, curproc->sz, curproc->sb)) == 0){
80103862: 8b 43 04 mov 0x4(%ebx),%eax
80103865: 89 44 24 08 mov %eax,0x8(%esp)
80103869: 8b 03 mov (%ebx),%eax
8010386b: 89 44 24 04 mov %eax,0x4(%esp)
8010386f: 8b 43 08 mov 0x8(%ebx),%eax
80103872: 89 04 24 mov %eax,(%esp)
80103875: e8 26 32 00 00 call 80106aa0 <copyuvm>
8010387a: 85 c0 test %eax,%eax
8010387c: 89 47 08 mov %eax,0x8(%edi)
8010387f: 0f 84 a8 00 00 00 je 8010392d <fork+0xed>
kfree(np->kstack);
np->kstack = 0;
np->state = UNUSED;
return -1;
}
np->sz = curproc->sz;
80103885: 8b 03 mov (%ebx),%eax
80103887: 8b 4d e4 mov -0x1c(%ebp),%ecx
8010388a: 89 01 mov %eax,(%ecx)
np->parent = curproc;
*np->tf = *curproc->tf;
8010388c: 8b 79 1c mov 0x1c(%ecx),%edi
8010388f: 89 c8 mov %ecx,%eax
np->kstack = 0;
np->state = UNUSED;
return -1;
}
np->sz = curproc->sz;
np->parent = curproc;
80103891: 89 59 18 mov %ebx,0x18(%ecx)
*np->tf = *curproc->tf;
80103894: 8b 73 1c mov 0x1c(%ebx),%esi
80103897: b9 13 00 00 00 mov $0x13,%ecx
8010389c: f3 a5 rep movsl %ds:(%esi),%es:(%edi)
// Clear %eax so that fork returns 0 in the child.
np->tf->eax = 0;
for(i = 0; i < NOFILE; i++)
8010389e: 31 f6 xor %esi,%esi
np->sz = curproc->sz;
np->parent = curproc;
*np->tf = *curproc->tf;
// Clear %eax so that fork returns 0 in the child.
np->tf->eax = 0;
801038a0: 8b 40 1c mov 0x1c(%eax),%eax
801038a3: c7 40 1c 00 00 00 00 movl $0x0,0x1c(%eax)
801038aa: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
for(i = 0; i < NOFILE; i++)
if(curproc->ofile[i])
801038b0: 8b 44 b3 2c mov 0x2c(%ebx,%esi,4),%eax
801038b4: 85 c0 test %eax,%eax
801038b6: 74 0f je 801038c7 <fork+0x87>
np->ofile[i] = filedup(curproc->ofile[i]);
801038b8: 89 04 24 mov %eax,(%esp)
801038bb: e8 00 d5 ff ff call 80100dc0 <filedup>
801038c0: 8b 55 e4 mov -0x1c(%ebp),%edx
801038c3: 89 44 b2 2c mov %eax,0x2c(%edx,%esi,4)
*np->tf = *curproc->tf;
// Clear %eax so that fork returns 0 in the child.
np->tf->eax = 0;
for(i = 0; i < NOFILE; i++)
801038c7: 83 c6 01 add $0x1,%esi
801038ca: 83 fe 10 cmp $0x10,%esi
801038cd: 75 e1 jne 801038b0 <fork+0x70>
if(curproc->ofile[i])
np->ofile[i] = filedup(curproc->ofile[i]);
np->cwd = idup(curproc->cwd);
801038cf: 8b 43 6c mov 0x6c(%ebx),%eax
safestrcpy(np->name, curproc->name, sizeof(curproc->name));
801038d2: 83 c3 70 add $0x70,%ebx
np->tf->eax = 0;
for(i = 0; i < NOFILE; i++)
if(curproc->ofile[i])
np->ofile[i] = filedup(curproc->ofile[i]);
np->cwd = idup(curproc->cwd);
801038d5: 89 04 24 mov %eax,(%esp)
801038d8: e8 93 dd ff ff call 80101670 <idup>
801038dd: 8b 7d e4 mov -0x1c(%ebp),%edi
801038e0: 89 47 6c mov %eax,0x6c(%edi)
safestrcpy(np->name, curproc->name, sizeof(curproc->name));
801038e3: 8d 47 70 lea 0x70(%edi),%eax
801038e6: 89 5c 24 04 mov %ebx,0x4(%esp)
801038ea: c7 44 24 08 10 00 00 movl $0x10,0x8(%esp)
801038f1: 00
801038f2: 89 04 24 mov %eax,(%esp)
801038f5: e8 56 0b 00 00 call 80104450 <safestrcpy>
pid = np->pid;
801038fa: 8b 5f 14 mov 0x14(%edi),%ebx
acquire(&ptable.lock);
801038fd: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103904: e8 27 08 00 00 call 80104130 <acquire>
np->state = RUNNABLE;
80103909: c7 47 10 03 00 00 00 movl $0x3,0x10(%edi)
release(&ptable.lock);
80103910: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103917: e8 04 09 00 00 call 80104220 <release>
return pid;
8010391c: 89 d8 mov %ebx,%eax
}
8010391e: 83 c4 1c add $0x1c,%esp
80103921: 5b pop %ebx
80103922: 5e pop %esi
80103923: 5f pop %edi
80103924: 5d pop %ebp
80103925: c3 ret
struct proc *np;
struct proc *curproc = myproc();
// Allocate process.
if((np = allocproc()) == 0){
return -1;
80103926: b8 ff ff ff ff mov $0xffffffff,%eax
8010392b: eb f1 jmp 8010391e <fork+0xde>
}
// Copy process state from proc.
if((np->pgdir = copyuvm(curproc->pgdir, curproc->sz, curproc->sb)) == 0){
kfree(np->kstack);
8010392d: 8b 7d e4 mov -0x1c(%ebp),%edi
80103930: 8b 47 0c mov 0xc(%edi),%eax
80103933: 89 04 24 mov %eax,(%esp)
80103936: e8 a5 e9 ff ff call 801022e0 <kfree>
np->kstack = 0;
np->state = UNUSED;
return -1;
8010393b: b8 ff ff ff ff mov $0xffffffff,%eax
}
// Copy process state from proc.
if((np->pgdir = copyuvm(curproc->pgdir, curproc->sz, curproc->sb)) == 0){
kfree(np->kstack);
np->kstack = 0;
80103940: c7 47 0c 00 00 00 00 movl $0x0,0xc(%edi)
np->state = UNUSED;
80103947: c7 47 10 00 00 00 00 movl $0x0,0x10(%edi)
return -1;
8010394e: eb ce jmp 8010391e <fork+0xde>
80103950 <scheduler>:
// - swtch to start running that process
// - eventually that process transfers control
// via swtch back to the scheduler.
void
scheduler(void)
{
80103950: 55 push %ebp
80103951: 89 e5 mov %esp,%ebp
80103953: 57 push %edi
80103954: 56 push %esi
80103955: 53 push %ebx
80103956: 83 ec 1c sub $0x1c,%esp
struct proc *p;
struct cpu *c = mycpu();
80103959: e8 92 fc ff ff call 801035f0 <mycpu>
8010395e: 89 c6 mov %eax,%esi
c->proc = 0;
80103960: c7 80 ac 00 00 00 00 movl $0x0,0xac(%eax)
80103967: 00 00 00
8010396a: 8d 78 04 lea 0x4(%eax),%edi
8010396d: 8d 76 00 lea 0x0(%esi),%esi
}
static inline void
sti(void)
{
asm volatile("sti");
80103970: fb sti
for(;;){
// Enable interrupts on this processor.
sti();
// Loop over process table looking for process to run.
acquire(&ptable.lock);
80103971: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
80103978: bb 54 2d 11 80 mov $0x80112d54,%ebx
for(;;){
// Enable interrupts on this processor.
sti();
// Loop over process table looking for process to run.
acquire(&ptable.lock);
8010397d: e8 ae 07 00 00 call 80104130 <acquire>
80103982: eb 0f jmp 80103993 <scheduler+0x43>
80103984: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
80103988: 83 eb 80 sub $0xffffff80,%ebx
8010398b: 81 fb 54 4d 11 80 cmp $0x80114d54,%ebx
80103991: 74 45 je 801039d8 <scheduler+0x88>
if(p->state != RUNNABLE)
80103993: 83 7b 10 03 cmpl $0x3,0x10(%ebx)
80103997: 75 ef jne 80103988 <scheduler+0x38>
continue;
// Switch to chosen process. It is the process's job
// to release ptable.lock and then reacquire it
// before jumping back to us.
c->proc = p;
80103999: 89 9e ac 00 00 00 mov %ebx,0xac(%esi)
switchuvm(p);
8010399f: 89 1c 24 mov %ebx,(%esp)
// Enable interrupts on this processor.
sti();
// Loop over process table looking for process to run.
acquire(&ptable.lock);
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
801039a2: 83 eb 80 sub $0xffffff80,%ebx
// Switch to chosen process. It is the process's job
// to release ptable.lock and then reacquire it
// before jumping back to us.
c->proc = p;
switchuvm(p);
801039a5: e8 16 2c 00 00 call 801065c0 <switchuvm>
p->state = RUNNING;
swtch(&(c->scheduler), p->context);
801039aa: 8b 43 a0 mov -0x60(%ebx),%eax
// Switch to chosen process. It is the process's job
// to release ptable.lock and then reacquire it
// before jumping back to us.
c->proc = p;
switchuvm(p);
p->state = RUNNING;
801039ad: c7 43 90 04 00 00 00 movl $0x4,-0x70(%ebx)
swtch(&(c->scheduler), p->context);
801039b4: 89 3c 24 mov %edi,(%esp)
801039b7: 89 44 24 04 mov %eax,0x4(%esp)
801039bb: e8 eb 0a 00 00 call 801044ab <swtch>
switchkvm();
801039c0: e8 db 2b 00 00 call 801065a0 <switchkvm>
// Enable interrupts on this processor.
sti();
// Loop over process table looking for process to run.
acquire(&ptable.lock);
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
801039c5: 81 fb 54 4d 11 80 cmp $0x80114d54,%ebx
swtch(&(c->scheduler), p->context);
switchkvm();
// Process is done running for now.
// It should have changed its p->state before coming back.
c->proc = 0;
801039cb: c7 86 ac 00 00 00 00 movl $0x0,0xac(%esi)
801039d2: 00 00 00
// Enable interrupts on this processor.
sti();
// Loop over process table looking for process to run.
acquire(&ptable.lock);
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
801039d5: 75 bc jne 80103993 <scheduler+0x43>
801039d7: 90 nop
// Process is done running for now.
// It should have changed its p->state before coming back.
c->proc = 0;
}
release(&ptable.lock);
801039d8: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
801039df: e8 3c 08 00 00 call 80104220 <release>
}
801039e4: eb 8a jmp 80103970 <scheduler+0x20>
801039e6: 8d 76 00 lea 0x0(%esi),%esi
801039e9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801039f0 <sched>:
// be proc->intena and proc->ncli, but that would
// break in the few places where a lock is held but
// there's no process.
void
sched(void)
{
801039f0: 55 push %ebp
801039f1: 89 e5 mov %esp,%ebp
801039f3: 56 push %esi
801039f4: 53 push %ebx
801039f5: 83 ec 10 sub $0x10,%esp
int intena;
struct proc *p = myproc();
801039f8: e8 93 fc ff ff call 80103690 <myproc>
if(!holding(&ptable.lock))
801039fd: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
// there's no process.
void
sched(void)
{
int intena;
struct proc *p = myproc();
80103a04: 89 c3 mov %eax,%ebx
if(!holding(&ptable.lock))
80103a06: e8 b5 06 00 00 call 801040c0 <holding>
80103a0b: 85 c0 test %eax,%eax
80103a0d: 74 4f je 80103a5e <sched+0x6e>
panic("sched ptable.lock");
if(mycpu()->ncli != 1)
80103a0f: e8 dc fb ff ff call 801035f0 <mycpu>
80103a14: 83 b8 a4 00 00 00 01 cmpl $0x1,0xa4(%eax)
80103a1b: 75 65 jne 80103a82 <sched+0x92>
panic("sched locks");
if(p->state == RUNNING)
80103a1d: 83 7b 10 04 cmpl $0x4,0x10(%ebx)
80103a21: 74 53 je 80103a76 <sched+0x86>
static inline uint
readeflags(void)
{
uint eflags;
asm volatile("pushfl; popl %0" : "=r" (eflags));
80103a23: 9c pushf
80103a24: 58 pop %eax
panic("sched running");
if(readeflags()&FL_IF)
80103a25: f6 c4 02 test $0x2,%ah
80103a28: 75 40 jne 80103a6a <sched+0x7a>
panic("sched interruptible");
intena = mycpu()->intena;
80103a2a: e8 c1 fb ff ff call 801035f0 <mycpu>
swtch(&p->context, mycpu()->scheduler);
80103a2f: 83 c3 20 add $0x20,%ebx
panic("sched locks");
if(p->state == RUNNING)
panic("sched running");
if(readeflags()&FL_IF)
panic("sched interruptible");
intena = mycpu()->intena;
80103a32: 8b b0 a8 00 00 00 mov 0xa8(%eax),%esi
swtch(&p->context, mycpu()->scheduler);
80103a38: e8 b3 fb ff ff call 801035f0 <mycpu>
80103a3d: 8b 40 04 mov 0x4(%eax),%eax
80103a40: 89 1c 24 mov %ebx,(%esp)
80103a43: 89 44 24 04 mov %eax,0x4(%esp)
80103a47: e8 5f 0a 00 00 call 801044ab <swtch>
mycpu()->intena = intena;
80103a4c: e8 9f fb ff ff call 801035f0 <mycpu>
80103a51: 89 b0 a8 00 00 00 mov %esi,0xa8(%eax)
}
80103a57: 83 c4 10 add $0x10,%esp
80103a5a: 5b pop %ebx
80103a5b: 5e pop %esi
80103a5c: 5d pop %ebp
80103a5d: c3 ret
{
int intena;
struct proc *p = myproc();
if(!holding(&ptable.lock))
panic("sched ptable.lock");
80103a5e: c7 04 24 30 73 10 80 movl $0x80107330,(%esp)
80103a65: e8 f6 c8 ff ff call 80100360 <panic>
if(mycpu()->ncli != 1)
panic("sched locks");
if(p->state == RUNNING)
panic("sched running");
if(readeflags()&FL_IF)
panic("sched interruptible");
80103a6a: c7 04 24 5c 73 10 80 movl $0x8010735c,(%esp)
80103a71: e8 ea c8 ff ff call 80100360 <panic>
if(!holding(&ptable.lock))
panic("sched ptable.lock");
if(mycpu()->ncli != 1)
panic("sched locks");
if(p->state == RUNNING)
panic("sched running");
80103a76: c7 04 24 4e 73 10 80 movl $0x8010734e,(%esp)
80103a7d: e8 de c8 ff ff call 80100360 <panic>
struct proc *p = myproc();
if(!holding(&ptable.lock))
panic("sched ptable.lock");
if(mycpu()->ncli != 1)
panic("sched locks");
80103a82: c7 04 24 42 73 10 80 movl $0x80107342,(%esp)
80103a89: e8 d2 c8 ff ff call 80100360 <panic>
80103a8e: 66 90 xchg %ax,%ax
80103a90 <exit>:
// Exit the current process. Does not return.
// An exited process remains in the zombie state
// until its parent calls wait() to find out it exited.
void
exit(void)
{
80103a90: 55 push %ebp
80103a91: 89 e5 mov %esp,%ebp
80103a93: 56 push %esi
struct proc *curproc = myproc();
struct proc *p;
int fd;
if(curproc == initproc)
80103a94: 31 f6 xor %esi,%esi
// Exit the current process. Does not return.
// An exited process remains in the zombie state
// until its parent calls wait() to find out it exited.
void
exit(void)
{
80103a96: 53 push %ebx
80103a97: 83 ec 10 sub $0x10,%esp
struct proc *curproc = myproc();
80103a9a: e8 f1 fb ff ff call 80103690 <myproc>
struct proc *p;
int fd;
if(curproc == initproc)
80103a9f: 3b 05 b8 a5 10 80 cmp 0x8010a5b8,%eax
// An exited process remains in the zombie state
// until its parent calls wait() to find out it exited.
void
exit(void)
{
struct proc *curproc = myproc();
80103aa5: 89 c3 mov %eax,%ebx
struct proc *p;
int fd;
if(curproc == initproc)
80103aa7: 0f 84 ea 00 00 00 je 80103b97 <exit+0x107>
80103aad: 8d 76 00 lea 0x0(%esi),%esi
panic("init exiting");
// Close all open files.
for(fd = 0; fd < NOFILE; fd++){
if(curproc->ofile[fd]){
80103ab0: 8b 44 b3 2c mov 0x2c(%ebx,%esi,4),%eax
80103ab4: 85 c0 test %eax,%eax
80103ab6: 74 10 je 80103ac8 <exit+0x38>
fileclose(curproc->ofile[fd]);
80103ab8: 89 04 24 mov %eax,(%esp)
80103abb: e8 50 d3 ff ff call 80100e10 <fileclose>
curproc->ofile[fd] = 0;
80103ac0: c7 44 b3 2c 00 00 00 movl $0x0,0x2c(%ebx,%esi,4)
80103ac7: 00
if(curproc == initproc)
panic("init exiting");
// Close all open files.
for(fd = 0; fd < NOFILE; fd++){
80103ac8: 83 c6 01 add $0x1,%esi
80103acb: 83 fe 10 cmp $0x10,%esi
80103ace: 75 e0 jne 80103ab0 <exit+0x20>
fileclose(curproc->ofile[fd]);
curproc->ofile[fd] = 0;
}
}
begin_op();
80103ad0: e8 2b f0 ff ff call 80102b00 <begin_op>
iput(curproc->cwd);
80103ad5: 8b 43 6c mov 0x6c(%ebx),%eax
80103ad8: 89 04 24 mov %eax,(%esp)
80103adb: e8 e0 dc ff ff call 801017c0 <iput>
end_op();
80103ae0: e8 8b f0 ff ff call 80102b70 <end_op>
curproc->cwd = 0;
80103ae5: c7 43 6c 00 00 00 00 movl $0x0,0x6c(%ebx)
acquire(&ptable.lock);
80103aec: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103af3: e8 38 06 00 00 call 80104130 <acquire>
// Parent might be sleeping in wait().
wakeup1(curproc->parent);
80103af8: 8b 43 18 mov 0x18(%ebx),%eax
static void
wakeup1(void *chan)
{
struct proc *p;
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++)
80103afb: ba 54 2d 11 80 mov $0x80112d54,%edx
80103b00: eb 11 jmp 80103b13 <exit+0x83>
80103b02: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80103b08: 83 ea 80 sub $0xffffff80,%edx
80103b0b: 81 fa 54 4d 11 80 cmp $0x80114d54,%edx
80103b11: 74 1d je 80103b30 <exit+0xa0>
if(p->state == SLEEPING && p->chan == chan)
80103b13: 83 7a 10 02 cmpl $0x2,0x10(%edx)
80103b17: 75 ef jne 80103b08 <exit+0x78>
80103b19: 3b 42 24 cmp 0x24(%edx),%eax
80103b1c: 75 ea jne 80103b08 <exit+0x78>
p->state = RUNNABLE;
80103b1e: c7 42 10 03 00 00 00 movl $0x3,0x10(%edx)
static void
wakeup1(void *chan)
{
struct proc *p;
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++)
80103b25: 83 ea 80 sub $0xffffff80,%edx
80103b28: 81 fa 54 4d 11 80 cmp $0x80114d54,%edx
80103b2e: 75 e3 jne 80103b13 <exit+0x83>
wakeup1(curproc->parent);
// Pass abandoned children to init.
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
if(p->parent == curproc){
p->parent = initproc;
80103b30: a1 b8 a5 10 80 mov 0x8010a5b8,%eax
80103b35: b9 54 2d 11 80 mov $0x80112d54,%ecx
80103b3a: eb 0f jmp 80103b4b <exit+0xbb>
80103b3c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
// Parent might be sleeping in wait().
wakeup1(curproc->parent);
// Pass abandoned children to init.
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
80103b40: 83 e9 80 sub $0xffffff80,%ecx
80103b43: 81 f9 54 4d 11 80 cmp $0x80114d54,%ecx
80103b49: 74 34 je 80103b7f <exit+0xef>
if(p->parent == curproc){
80103b4b: 39 59 18 cmp %ebx,0x18(%ecx)
80103b4e: 75 f0 jne 80103b40 <exit+0xb0>
p->parent = initproc;
if(p->state == ZOMBIE)
80103b50: 83 79 10 05 cmpl $0x5,0x10(%ecx)
wakeup1(curproc->parent);
// Pass abandoned children to init.
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
if(p->parent == curproc){
p->parent = initproc;
80103b54: 89 41 18 mov %eax,0x18(%ecx)
if(p->state == ZOMBIE)
80103b57: 75 e7 jne 80103b40 <exit+0xb0>
80103b59: ba 54 2d 11 80 mov $0x80112d54,%edx
80103b5e: eb 0b jmp 80103b6b <exit+0xdb>
static void
wakeup1(void *chan)
{
struct proc *p;
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++)
80103b60: 83 ea 80 sub $0xffffff80,%edx
80103b63: 81 fa 54 4d 11 80 cmp $0x80114d54,%edx
80103b69: 74 d5 je 80103b40 <exit+0xb0>
if(p->state == SLEEPING && p->chan == chan)
80103b6b: 83 7a 10 02 cmpl $0x2,0x10(%edx)
80103b6f: 75 ef jne 80103b60 <exit+0xd0>
80103b71: 3b 42 24 cmp 0x24(%edx),%eax
80103b74: 75 ea jne 80103b60 <exit+0xd0>
p->state = RUNNABLE;
80103b76: c7 42 10 03 00 00 00 movl $0x3,0x10(%edx)
80103b7d: eb e1 jmp 80103b60 <exit+0xd0>
wakeup1(initproc);
}
}
// Jump into the scheduler, never to return.
curproc->state = ZOMBIE;
80103b7f: c7 43 10 05 00 00 00 movl $0x5,0x10(%ebx)
sched();
80103b86: e8 65 fe ff ff call 801039f0 <sched>
panic("zombie exit");
80103b8b: c7 04 24 7d 73 10 80 movl $0x8010737d,(%esp)
80103b92: e8 c9 c7 ff ff call 80100360 <panic>
struct proc *curproc = myproc();
struct proc *p;
int fd;
if(curproc == initproc)
panic("init exiting");
80103b97: c7 04 24 70 73 10 80 movl $0x80107370,(%esp)
80103b9e: e8 bd c7 ff ff call 80100360 <panic>
80103ba3: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80103ba9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80103bb0 <yield>:
}
// Give up the CPU for one scheduling round.
void
yield(void)
{
80103bb0: 55 push %ebp
80103bb1: 89 e5 mov %esp,%ebp
80103bb3: 83 ec 18 sub $0x18,%esp
acquire(&ptable.lock); //DOC: yieldlock
80103bb6: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103bbd: e8 6e 05 00 00 call 80104130 <acquire>
myproc()->state = RUNNABLE;
80103bc2: e8 c9 fa ff ff call 80103690 <myproc>
80103bc7: c7 40 10 03 00 00 00 movl $0x3,0x10(%eax)
sched();
80103bce: e8 1d fe ff ff call 801039f0 <sched>
release(&ptable.lock);
80103bd3: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103bda: e8 41 06 00 00 call 80104220 <release>
}
80103bdf: c9 leave
80103be0: c3 ret
80103be1: eb 0d jmp 80103bf0 <sleep>
80103be3: 90 nop
80103be4: 90 nop
80103be5: 90 nop
80103be6: 90 nop
80103be7: 90 nop
80103be8: 90 nop
80103be9: 90 nop
80103bea: 90 nop
80103beb: 90 nop
80103bec: 90 nop
80103bed: 90 nop
80103bee: 90 nop
80103bef: 90 nop
80103bf0 <sleep>:
// Atomically release lock and sleep on chan.
// Reacquires lock when awakened.
void
sleep(void *chan, struct spinlock *lk)
{
80103bf0: 55 push %ebp
80103bf1: 89 e5 mov %esp,%ebp
80103bf3: 57 push %edi
80103bf4: 56 push %esi
80103bf5: 53 push %ebx
80103bf6: 83 ec 1c sub $0x1c,%esp
80103bf9: 8b 7d 08 mov 0x8(%ebp),%edi
80103bfc: 8b 75 0c mov 0xc(%ebp),%esi
struct proc *p = myproc();
80103bff: e8 8c fa ff ff call 80103690 <myproc>
if(p == 0)
80103c04: 85 c0 test %eax,%eax
// Atomically release lock and sleep on chan.
// Reacquires lock when awakened.
void
sleep(void *chan, struct spinlock *lk)
{
struct proc *p = myproc();
80103c06: 89 c3 mov %eax,%ebx
if(p == 0)
80103c08: 0f 84 7c 00 00 00 je 80103c8a <sleep+0x9a>
panic("sleep");
if(lk == 0)
80103c0e: 85 f6 test %esi,%esi
80103c10: 74 6c je 80103c7e <sleep+0x8e>
// change p->state and then call sched.
// Once we hold ptable.lock, we can be
// guaranteed that we won't miss any wakeup
// (wakeup runs with ptable.lock locked),
// so it's okay to release lk.
if(lk != &ptable.lock){ //DOC: sleeplock0
80103c12: 81 fe 20 2d 11 80 cmp $0x80112d20,%esi
80103c18: 74 46 je 80103c60 <sleep+0x70>
acquire(&ptable.lock); //DOC: sleeplock1
80103c1a: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103c21: e8 0a 05 00 00 call 80104130 <acquire>
release(lk);
80103c26: 89 34 24 mov %esi,(%esp)
80103c29: e8 f2 05 00 00 call 80104220 <release>
}
// Go to sleep.
p->chan = chan;
80103c2e: 89 7b 24 mov %edi,0x24(%ebx)
p->state = SLEEPING;
80103c31: c7 43 10 02 00 00 00 movl $0x2,0x10(%ebx)
sched();
80103c38: e8 b3 fd ff ff call 801039f0 <sched>
// Tidy up.
p->chan = 0;
80103c3d: c7 43 24 00 00 00 00 movl $0x0,0x24(%ebx)
// Reacquire original lock.
if(lk != &ptable.lock){ //DOC: sleeplock2
release(&ptable.lock);
80103c44: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103c4b: e8 d0 05 00 00 call 80104220 <release>
acquire(lk);
80103c50: 89 75 08 mov %esi,0x8(%ebp)
}
}
80103c53: 83 c4 1c add $0x1c,%esp
80103c56: 5b pop %ebx
80103c57: 5e pop %esi
80103c58: 5f pop %edi
80103c59: 5d pop %ebp
p->chan = 0;
// Reacquire original lock.
if(lk != &ptable.lock){ //DOC: sleeplock2
release(&ptable.lock);
acquire(lk);
80103c5a: e9 d1 04 00 00 jmp 80104130 <acquire>
80103c5f: 90 nop
if(lk != &ptable.lock){ //DOC: sleeplock0
acquire(&ptable.lock); //DOC: sleeplock1
release(lk);
}
// Go to sleep.
p->chan = chan;
80103c60: 89 78 24 mov %edi,0x24(%eax)
p->state = SLEEPING;
80103c63: c7 40 10 02 00 00 00 movl $0x2,0x10(%eax)
sched();
80103c6a: e8 81 fd ff ff call 801039f0 <sched>
// Tidy up.
p->chan = 0;
80103c6f: c7 43 24 00 00 00 00 movl $0x0,0x24(%ebx)
// Reacquire original lock.
if(lk != &ptable.lock){ //DOC: sleeplock2
release(&ptable.lock);
acquire(lk);
}
}
80103c76: 83 c4 1c add $0x1c,%esp
80103c79: 5b pop %ebx
80103c7a: 5e pop %esi
80103c7b: 5f pop %edi
80103c7c: 5d pop %ebp
80103c7d: c3 ret
if(p == 0)
panic("sleep");
if(lk == 0)
panic("sleep without lk");
80103c7e: c7 04 24 8f 73 10 80 movl $0x8010738f,(%esp)
80103c85: e8 d6 c6 ff ff call 80100360 <panic>
sleep(void *chan, struct spinlock *lk)
{
struct proc *p = myproc();
if(p == 0)
panic("sleep");
80103c8a: c7 04 24 89 73 10 80 movl $0x80107389,(%esp)
80103c91: e8 ca c6 ff ff call 80100360 <panic>
80103c96: 8d 76 00 lea 0x0(%esi),%esi
80103c99: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80103ca0 <wait>:
// Wait for a child process to exit and return its pid.
// Return -1 if this process has no children.
int
wait(void)
{
80103ca0: 55 push %ebp
80103ca1: 89 e5 mov %esp,%ebp
80103ca3: 56 push %esi
80103ca4: 53 push %ebx
80103ca5: 83 ec 10 sub $0x10,%esp
struct proc *p;
int havekids, pid;
struct proc *curproc = myproc();
80103ca8: e8 e3 f9 ff ff call 80103690 <myproc>
acquire(&ptable.lock);
80103cad: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
int
wait(void)
{
struct proc *p;
int havekids, pid;
struct proc *curproc = myproc();
80103cb4: 89 c6 mov %eax,%esi
acquire(&ptable.lock);
80103cb6: e8 75 04 00 00 call 80104130 <acquire>
for(;;){
// Scan through table looking for exited children.
havekids = 0;
80103cbb: 31 c0 xor %eax,%eax
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
80103cbd: bb 54 2d 11 80 mov $0x80112d54,%ebx
80103cc2: eb 0f jmp 80103cd3 <wait+0x33>
80103cc4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80103cc8: 83 eb 80 sub $0xffffff80,%ebx
80103ccb: 81 fb 54 4d 11 80 cmp $0x80114d54,%ebx
80103cd1: 74 1d je 80103cf0 <wait+0x50>
if(p->parent != curproc)
80103cd3: 39 73 18 cmp %esi,0x18(%ebx)
80103cd6: 75 f0 jne 80103cc8 <wait+0x28>
continue;
havekids = 1;
if(p->state == ZOMBIE){
80103cd8: 83 7b 10 05 cmpl $0x5,0x10(%ebx)
80103cdc: 74 2f je 80103d0d <wait+0x6d>
acquire(&ptable.lock);
for(;;){
// Scan through table looking for exited children.
havekids = 0;
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
80103cde: 83 eb 80 sub $0xffffff80,%ebx
if(p->parent != curproc)
continue;
havekids = 1;
80103ce1: b8 01 00 00 00 mov $0x1,%eax
acquire(&ptable.lock);
for(;;){
// Scan through table looking for exited children.
havekids = 0;
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
80103ce6: 81 fb 54 4d 11 80 cmp $0x80114d54,%ebx
80103cec: 75 e5 jne 80103cd3 <wait+0x33>
80103cee: 66 90 xchg %ax,%ax
return pid;
}
}
// No point waiting if we don't have any children.
if(!havekids || curproc->killed){
80103cf0: 85 c0 test %eax,%eax
80103cf2: 74 6e je 80103d62 <wait+0xc2>
80103cf4: 8b 46 28 mov 0x28(%esi),%eax
80103cf7: 85 c0 test %eax,%eax
80103cf9: 75 67 jne 80103d62 <wait+0xc2>
release(&ptable.lock);
return -1;
}
// Wait for children to exit. (See wakeup1 call in proc_exit.)
sleep(curproc, &ptable.lock); //DOC: wait-sleep
80103cfb: c7 44 24 04 20 2d 11 movl $0x80112d20,0x4(%esp)
80103d02: 80
80103d03: 89 34 24 mov %esi,(%esp)
80103d06: e8 e5 fe ff ff call 80103bf0 <sleep>
}
80103d0b: eb ae jmp 80103cbb <wait+0x1b>
continue;
havekids = 1;
if(p->state == ZOMBIE){
// Found one.
pid = p->pid;
kfree(p->kstack);
80103d0d: 8b 43 0c mov 0xc(%ebx),%eax
if(p->parent != curproc)
continue;
havekids = 1;
if(p->state == ZOMBIE){
// Found one.
pid = p->pid;
80103d10: 8b 73 14 mov 0x14(%ebx),%esi
kfree(p->kstack);
80103d13: 89 04 24 mov %eax,(%esp)
80103d16: e8 c5 e5 ff ff call 801022e0 <kfree>
p->kstack = 0;
freevm(p->pgdir);
80103d1b: 8b 43 08 mov 0x8(%ebx),%eax
havekids = 1;
if(p->state == ZOMBIE){
// Found one.
pid = p->pid;
kfree(p->kstack);
p->kstack = 0;
80103d1e: c7 43 0c 00 00 00 00 movl $0x0,0xc(%ebx)
freevm(p->pgdir);
80103d25: 89 04 24 mov %eax,(%esp)
80103d28: e8 13 2c 00 00 call 80106940 <freevm>
p->pid = 0;
p->parent = 0;
p->name[0] = 0;
p->killed = 0;
p->state = UNUSED;
release(&ptable.lock);
80103d2d: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
// Found one.
pid = p->pid;
kfree(p->kstack);
p->kstack = 0;
freevm(p->pgdir);
p->pid = 0;
80103d34: c7 43 14 00 00 00 00 movl $0x0,0x14(%ebx)
p->parent = 0;
80103d3b: c7 43 18 00 00 00 00 movl $0x0,0x18(%ebx)
p->name[0] = 0;
80103d42: c6 43 70 00 movb $0x0,0x70(%ebx)
p->killed = 0;
80103d46: c7 43 28 00 00 00 00 movl $0x0,0x28(%ebx)
p->state = UNUSED;
80103d4d: c7 43 10 00 00 00 00 movl $0x0,0x10(%ebx)
release(&ptable.lock);
80103d54: e8 c7 04 00 00 call 80104220 <release>
}
// Wait for children to exit. (See wakeup1 call in proc_exit.)
sleep(curproc, &ptable.lock); //DOC: wait-sleep
}
}
80103d59: 83 c4 10 add $0x10,%esp
p->parent = 0;
p->name[0] = 0;
p->killed = 0;
p->state = UNUSED;
release(&ptable.lock);
return pid;
80103d5c: 89 f0 mov %esi,%eax
}
// Wait for children to exit. (See wakeup1 call in proc_exit.)
sleep(curproc, &ptable.lock); //DOC: wait-sleep
}
}
80103d5e: 5b pop %ebx
80103d5f: 5e pop %esi
80103d60: 5d pop %ebp
80103d61: c3 ret
}
}
// No point waiting if we don't have any children.
if(!havekids || curproc->killed){
release(&ptable.lock);
80103d62: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103d69: e8 b2 04 00 00 call 80104220 <release>
}
// Wait for children to exit. (See wakeup1 call in proc_exit.)
sleep(curproc, &ptable.lock); //DOC: wait-sleep
}
}
80103d6e: 83 c4 10 add $0x10,%esp
}
// No point waiting if we don't have any children.
if(!havekids || curproc->killed){
release(&ptable.lock);
return -1;
80103d71: b8 ff ff ff ff mov $0xffffffff,%eax
}
// Wait for children to exit. (See wakeup1 call in proc_exit.)
sleep(curproc, &ptable.lock); //DOC: wait-sleep
}
}
80103d76: 5b pop %ebx
80103d77: 5e pop %esi
80103d78: 5d pop %ebp
80103d79: c3 ret
80103d7a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80103d80 <wakeup>:
}
// Wake up all processes sleeping on chan.
void
wakeup(void *chan)
{
80103d80: 55 push %ebp
80103d81: 89 e5 mov %esp,%ebp
80103d83: 53 push %ebx
80103d84: 83 ec 14 sub $0x14,%esp
80103d87: 8b 5d 08 mov 0x8(%ebp),%ebx
acquire(&ptable.lock);
80103d8a: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103d91: e8 9a 03 00 00 call 80104130 <acquire>
static void
wakeup1(void *chan)
{
struct proc *p;
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++)
80103d96: b8 54 2d 11 80 mov $0x80112d54,%eax
80103d9b: eb 0d jmp 80103daa <wakeup+0x2a>
80103d9d: 8d 76 00 lea 0x0(%esi),%esi
80103da0: 83 e8 80 sub $0xffffff80,%eax
80103da3: 3d 54 4d 11 80 cmp $0x80114d54,%eax
80103da8: 74 1e je 80103dc8 <wakeup+0x48>
if(p->state == SLEEPING && p->chan == chan)
80103daa: 83 78 10 02 cmpl $0x2,0x10(%eax)
80103dae: 75 f0 jne 80103da0 <wakeup+0x20>
80103db0: 3b 58 24 cmp 0x24(%eax),%ebx
80103db3: 75 eb jne 80103da0 <wakeup+0x20>
p->state = RUNNABLE;
80103db5: c7 40 10 03 00 00 00 movl $0x3,0x10(%eax)
static void
wakeup1(void *chan)
{
struct proc *p;
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++)
80103dbc: 83 e8 80 sub $0xffffff80,%eax
80103dbf: 3d 54 4d 11 80 cmp $0x80114d54,%eax
80103dc4: 75 e4 jne 80103daa <wakeup+0x2a>
80103dc6: 66 90 xchg %ax,%ax
void
wakeup(void *chan)
{
acquire(&ptable.lock);
wakeup1(chan);
release(&ptable.lock);
80103dc8: c7 45 08 20 2d 11 80 movl $0x80112d20,0x8(%ebp)
}
80103dcf: 83 c4 14 add $0x14,%esp
80103dd2: 5b pop %ebx
80103dd3: 5d pop %ebp
void
wakeup(void *chan)
{
acquire(&ptable.lock);
wakeup1(chan);
release(&ptable.lock);
80103dd4: e9 47 04 00 00 jmp 80104220 <release>
80103dd9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80103de0 <kill>:
// Kill the process with the given pid.
// Process won't exit until it returns
// to user space (see trap in trap.c).
int
kill(int pid)
{
80103de0: 55 push %ebp
80103de1: 89 e5 mov %esp,%ebp
80103de3: 53 push %ebx
80103de4: 83 ec 14 sub $0x14,%esp
80103de7: 8b 5d 08 mov 0x8(%ebp),%ebx
struct proc *p;
acquire(&ptable.lock);
80103dea: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103df1: e8 3a 03 00 00 call 80104130 <acquire>
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
80103df6: b8 54 2d 11 80 mov $0x80112d54,%eax
80103dfb: eb 0d jmp 80103e0a <kill+0x2a>
80103dfd: 8d 76 00 lea 0x0(%esi),%esi
80103e00: 83 e8 80 sub $0xffffff80,%eax
80103e03: 3d 54 4d 11 80 cmp $0x80114d54,%eax
80103e08: 74 36 je 80103e40 <kill+0x60>
if(p->pid == pid){
80103e0a: 39 58 14 cmp %ebx,0x14(%eax)
80103e0d: 75 f1 jne 80103e00 <kill+0x20>
p->killed = 1;
// Wake process from sleep if necessary.
if(p->state == SLEEPING)
80103e0f: 83 78 10 02 cmpl $0x2,0x10(%eax)
struct proc *p;
acquire(&ptable.lock);
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
if(p->pid == pid){
p->killed = 1;
80103e13: c7 40 28 01 00 00 00 movl $0x1,0x28(%eax)
// Wake process from sleep if necessary.
if(p->state == SLEEPING)
80103e1a: 74 14 je 80103e30 <kill+0x50>
p->state = RUNNABLE;
release(&ptable.lock);
80103e1c: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103e23: e8 f8 03 00 00 call 80104220 <release>
return 0;
}
}
release(&ptable.lock);
return -1;
}
80103e28: 83 c4 14 add $0x14,%esp
p->killed = 1;
// Wake process from sleep if necessary.
if(p->state == SLEEPING)
p->state = RUNNABLE;
release(&ptable.lock);
return 0;
80103e2b: 31 c0 xor %eax,%eax
}
}
release(&ptable.lock);
return -1;
}
80103e2d: 5b pop %ebx
80103e2e: 5d pop %ebp
80103e2f: c3 ret
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
if(p->pid == pid){
p->killed = 1;
// Wake process from sleep if necessary.
if(p->state == SLEEPING)
p->state = RUNNABLE;
80103e30: c7 40 10 03 00 00 00 movl $0x3,0x10(%eax)
80103e37: eb e3 jmp 80103e1c <kill+0x3c>
80103e39: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
release(&ptable.lock);
return 0;
}
}
release(&ptable.lock);
80103e40: c7 04 24 20 2d 11 80 movl $0x80112d20,(%esp)
80103e47: e8 d4 03 00 00 call 80104220 <release>
return -1;
}
80103e4c: 83 c4 14 add $0x14,%esp
release(&ptable.lock);
return 0;
}
}
release(&ptable.lock);
return -1;
80103e4f: b8 ff ff ff ff mov $0xffffffff,%eax
}
80103e54: 5b pop %ebx
80103e55: 5d pop %ebp
80103e56: c3 ret
80103e57: 89 f6 mov %esi,%esi
80103e59: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80103e60 <procdump>:
// Print a process listing to console. For debugging.
// Runs when user types ^P on console.
// No lock to avoid wedging a stuck machine further.
void
procdump(void)
{
80103e60: 55 push %ebp
80103e61: 89 e5 mov %esp,%ebp
80103e63: 57 push %edi
80103e64: 56 push %esi
80103e65: 53 push %ebx
80103e66: bb c4 2d 11 80 mov $0x80112dc4,%ebx
80103e6b: 83 ec 4c sub $0x4c,%esp
80103e6e: 8d 75 e8 lea -0x18(%ebp),%esi
80103e71: eb 20 jmp 80103e93 <procdump+0x33>
80103e73: 90 nop
80103e74: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
if(p->state == SLEEPING){
getcallerpcs((uint*)p->context->ebp+2, pc);
for(i=0; i<10 && pc[i] != 0; i++)
cprintf(" %p", pc[i]);
}
cprintf("\n");
80103e78: c7 04 24 87 77 10 80 movl $0x80107787,(%esp)
80103e7f: e8 cc c7 ff ff call 80100650 <cprintf>
80103e84: 83 eb 80 sub $0xffffff80,%ebx
int i;
struct proc *p;
char *state;
uint pc[10];
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
80103e87: 81 fb c4 4d 11 80 cmp $0x80114dc4,%ebx
80103e8d: 0f 84 8d 00 00 00 je 80103f20 <procdump+0xc0>
if(p->state == UNUSED)
80103e93: 8b 43 a0 mov -0x60(%ebx),%eax
80103e96: 85 c0 test %eax,%eax
80103e98: 74 ea je 80103e84 <procdump+0x24>
continue;
if(p->state >= 0 && p->state < NELEM(states) && states[p->state])
80103e9a: 83 f8 05 cmp $0x5,%eax
state = states[p->state];
else
state = "???";
80103e9d: ba a0 73 10 80 mov $0x801073a0,%edx
uint pc[10];
for(p = ptable.proc; p < &ptable.proc[NPROC]; p++){
if(p->state == UNUSED)
continue;
if(p->state >= 0 && p->state < NELEM(states) && states[p->state])
80103ea2: 77 11 ja 80103eb5 <procdump+0x55>
80103ea4: 8b 14 85 00 74 10 80 mov -0x7fef8c00(,%eax,4),%edx
state = states[p->state];
else
state = "???";
80103eab: b8 a0 73 10 80 mov $0x801073a0,%eax
80103eb0: 85 d2 test %edx,%edx
80103eb2: 0f 44 d0 cmove %eax,%edx
cprintf("%d %s %s", p->pid, state, p->name);
80103eb5: 8b 43 a4 mov -0x5c(%ebx),%eax
80103eb8: 89 5c 24 0c mov %ebx,0xc(%esp)
80103ebc: 89 54 24 08 mov %edx,0x8(%esp)
80103ec0: c7 04 24 a4 73 10 80 movl $0x801073a4,(%esp)
80103ec7: 89 44 24 04 mov %eax,0x4(%esp)
80103ecb: e8 80 c7 ff ff call 80100650 <cprintf>
if(p->state == SLEEPING){
80103ed0: 83 7b a0 02 cmpl $0x2,-0x60(%ebx)
80103ed4: 75 a2 jne 80103e78 <procdump+0x18>
getcallerpcs((uint*)p->context->ebp+2, pc);
80103ed6: 8d 45 c0 lea -0x40(%ebp),%eax
80103ed9: 89 44 24 04 mov %eax,0x4(%esp)
80103edd: 8b 43 b0 mov -0x50(%ebx),%eax
80103ee0: 8d 7d c0 lea -0x40(%ebp),%edi
80103ee3: 8b 40 0c mov 0xc(%eax),%eax
80103ee6: 83 c0 08 add $0x8,%eax
80103ee9: 89 04 24 mov %eax,(%esp)
80103eec: e8 6f 01 00 00 call 80104060 <getcallerpcs>
80103ef1: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
for(i=0; i<10 && pc[i] != 0; i++)
80103ef8: 8b 17 mov (%edi),%edx
80103efa: 85 d2 test %edx,%edx
80103efc: 0f 84 76 ff ff ff je 80103e78 <procdump+0x18>
cprintf(" %p", pc[i]);
80103f02: 89 54 24 04 mov %edx,0x4(%esp)
80103f06: 83 c7 04 add $0x4,%edi
80103f09: c7 04 24 e1 6d 10 80 movl $0x80106de1,(%esp)
80103f10: e8 3b c7 ff ff call 80100650 <cprintf>
else
state = "???";
cprintf("%d %s %s", p->pid, state, p->name);
if(p->state == SLEEPING){
getcallerpcs((uint*)p->context->ebp+2, pc);
for(i=0; i<10 && pc[i] != 0; i++)
80103f15: 39 f7 cmp %esi,%edi
80103f17: 75 df jne 80103ef8 <procdump+0x98>
80103f19: e9 5a ff ff ff jmp 80103e78 <procdump+0x18>
80103f1e: 66 90 xchg %ax,%ax
cprintf(" %p", pc[i]);
}
cprintf("\n");
}
}
80103f20: 83 c4 4c add $0x4c,%esp
80103f23: 5b pop %ebx
80103f24: 5e pop %esi
80103f25: 5f pop %edi
80103f26: 5d pop %ebp
80103f27: c3 ret
80103f28: 66 90 xchg %ax,%ax
80103f2a: 66 90 xchg %ax,%ax
80103f2c: 66 90 xchg %ax,%ax
80103f2e: 66 90 xchg %ax,%ax
80103f30 <initsleeplock>:
#include "spinlock.h"
#include "sleeplock.h"
void
initsleeplock(struct sleeplock *lk, char *name)
{
80103f30: 55 push %ebp
80103f31: 89 e5 mov %esp,%ebp
80103f33: 53 push %ebx
80103f34: 83 ec 14 sub $0x14,%esp
80103f37: 8b 5d 08 mov 0x8(%ebp),%ebx
initlock(&lk->lk, "sleep lock");
80103f3a: c7 44 24 04 18 74 10 movl $0x80107418,0x4(%esp)
80103f41: 80
80103f42: 8d 43 04 lea 0x4(%ebx),%eax
80103f45: 89 04 24 mov %eax,(%esp)
80103f48: e8 f3 00 00 00 call 80104040 <initlock>
lk->name = name;
80103f4d: 8b 45 0c mov 0xc(%ebp),%eax
lk->locked = 0;
80103f50: c7 03 00 00 00 00 movl $0x0,(%ebx)
lk->pid = 0;
80103f56: c7 43 3c 00 00 00 00 movl $0x0,0x3c(%ebx)
void
initsleeplock(struct sleeplock *lk, char *name)
{
initlock(&lk->lk, "sleep lock");
lk->name = name;
80103f5d: 89 43 38 mov %eax,0x38(%ebx)
lk->locked = 0;
lk->pid = 0;
}
80103f60: 83 c4 14 add $0x14,%esp
80103f63: 5b pop %ebx
80103f64: 5d pop %ebp
80103f65: c3 ret
80103f66: 8d 76 00 lea 0x0(%esi),%esi
80103f69: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80103f70 <acquiresleep>:
void
acquiresleep(struct sleeplock *lk)
{
80103f70: 55 push %ebp
80103f71: 89 e5 mov %esp,%ebp
80103f73: 56 push %esi
80103f74: 53 push %ebx
80103f75: 83 ec 10 sub $0x10,%esp
80103f78: 8b 5d 08 mov 0x8(%ebp),%ebx
acquire(&lk->lk);
80103f7b: 8d 73 04 lea 0x4(%ebx),%esi
80103f7e: 89 34 24 mov %esi,(%esp)
80103f81: e8 aa 01 00 00 call 80104130 <acquire>
while (lk->locked) {
80103f86: 8b 13 mov (%ebx),%edx
80103f88: 85 d2 test %edx,%edx
80103f8a: 74 16 je 80103fa2 <acquiresleep+0x32>
80103f8c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
sleep(lk, &lk->lk);
80103f90: 89 74 24 04 mov %esi,0x4(%esp)
80103f94: 89 1c 24 mov %ebx,(%esp)
80103f97: e8 54 fc ff ff call 80103bf0 <sleep>
void
acquiresleep(struct sleeplock *lk)
{
acquire(&lk->lk);
while (lk->locked) {
80103f9c: 8b 03 mov (%ebx),%eax
80103f9e: 85 c0 test %eax,%eax
80103fa0: 75 ee jne 80103f90 <acquiresleep+0x20>
sleep(lk, &lk->lk);
}
lk->locked = 1;
80103fa2: c7 03 01 00 00 00 movl $0x1,(%ebx)
lk->pid = myproc()->pid;
80103fa8: e8 e3 f6 ff ff call 80103690 <myproc>
80103fad: 8b 40 14 mov 0x14(%eax),%eax
80103fb0: 89 43 3c mov %eax,0x3c(%ebx)
release(&lk->lk);
80103fb3: 89 75 08 mov %esi,0x8(%ebp)
}
80103fb6: 83 c4 10 add $0x10,%esp
80103fb9: 5b pop %ebx
80103fba: 5e pop %esi
80103fbb: 5d pop %ebp
while (lk->locked) {
sleep(lk, &lk->lk);
}
lk->locked = 1;
lk->pid = myproc()->pid;
release(&lk->lk);
80103fbc: e9 5f 02 00 00 jmp 80104220 <release>
80103fc1: eb 0d jmp 80103fd0 <releasesleep>
80103fc3: 90 nop
80103fc4: 90 nop
80103fc5: 90 nop
80103fc6: 90 nop
80103fc7: 90 nop
80103fc8: 90 nop
80103fc9: 90 nop
80103fca: 90 nop
80103fcb: 90 nop
80103fcc: 90 nop
80103fcd: 90 nop
80103fce: 90 nop
80103fcf: 90 nop
80103fd0 <releasesleep>:
}
void
releasesleep(struct sleeplock *lk)
{
80103fd0: 55 push %ebp
80103fd1: 89 e5 mov %esp,%ebp
80103fd3: 56 push %esi
80103fd4: 53 push %ebx
80103fd5: 83 ec 10 sub $0x10,%esp
80103fd8: 8b 5d 08 mov 0x8(%ebp),%ebx
acquire(&lk->lk);
80103fdb: 8d 73 04 lea 0x4(%ebx),%esi
80103fde: 89 34 24 mov %esi,(%esp)
80103fe1: e8 4a 01 00 00 call 80104130 <acquire>
lk->locked = 0;
80103fe6: c7 03 00 00 00 00 movl $0x0,(%ebx)
lk->pid = 0;
80103fec: c7 43 3c 00 00 00 00 movl $0x0,0x3c(%ebx)
wakeup(lk);
80103ff3: 89 1c 24 mov %ebx,(%esp)
80103ff6: e8 85 fd ff ff call 80103d80 <wakeup>
release(&lk->lk);
80103ffb: 89 75 08 mov %esi,0x8(%ebp)
}
80103ffe: 83 c4 10 add $0x10,%esp
80104001: 5b pop %ebx
80104002: 5e pop %esi
80104003: 5d pop %ebp
{
acquire(&lk->lk);
lk->locked = 0;
lk->pid = 0;
wakeup(lk);
release(&lk->lk);
80104004: e9 17 02 00 00 jmp 80104220 <release>
80104009: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80104010 <holdingsleep>:
}
int
holdingsleep(struct sleeplock *lk)
{
80104010: 55 push %ebp
80104011: 89 e5 mov %esp,%ebp
80104013: 56 push %esi
80104014: 53 push %ebx
80104015: 83 ec 10 sub $0x10,%esp
80104018: 8b 5d 08 mov 0x8(%ebp),%ebx
int r;
acquire(&lk->lk);
8010401b: 8d 73 04 lea 0x4(%ebx),%esi
8010401e: 89 34 24 mov %esi,(%esp)
80104021: e8 0a 01 00 00 call 80104130 <acquire>
r = lk->locked;
80104026: 8b 1b mov (%ebx),%ebx
release(&lk->lk);
80104028: 89 34 24 mov %esi,(%esp)
8010402b: e8 f0 01 00 00 call 80104220 <release>
return r;
}
80104030: 83 c4 10 add $0x10,%esp
80104033: 89 d8 mov %ebx,%eax
80104035: 5b pop %ebx
80104036: 5e pop %esi
80104037: 5d pop %ebp
80104038: c3 ret
80104039: 66 90 xchg %ax,%ax
8010403b: 66 90 xchg %ax,%ax
8010403d: 66 90 xchg %ax,%ax
8010403f: 90 nop
80104040 <initlock>:
#include "proc.h"
#include "spinlock.h"
void
initlock(struct spinlock *lk, char *name)
{
80104040: 55 push %ebp
80104041: 89 e5 mov %esp,%ebp
80104043: 8b 45 08 mov 0x8(%ebp),%eax
lk->name = name;
80104046: 8b 55 0c mov 0xc(%ebp),%edx
lk->locked = 0;
80104049: c7 00 00 00 00 00 movl $0x0,(%eax)
#include "spinlock.h"
void
initlock(struct spinlock *lk, char *name)
{
lk->name = name;
8010404f: 89 50 04 mov %edx,0x4(%eax)
lk->locked = 0;
lk->cpu = 0;
80104052: c7 40 08 00 00 00 00 movl $0x0,0x8(%eax)
}
80104059: 5d pop %ebp
8010405a: c3 ret
8010405b: 90 nop
8010405c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80104060 <getcallerpcs>:
}
// Record the current call stack in pcs[] by following the %ebp chain.
void
getcallerpcs(void *v, uint pcs[])
{
80104060: 55 push %ebp
80104061: 89 e5 mov %esp,%ebp
uint *ebp;
int i;
ebp = (uint*)v - 2;
80104063: 8b 45 08 mov 0x8(%ebp),%eax
}
// Record the current call stack in pcs[] by following the %ebp chain.
void
getcallerpcs(void *v, uint pcs[])
{
80104066: 8b 4d 0c mov 0xc(%ebp),%ecx
80104069: 53 push %ebx
uint *ebp;
int i;
ebp = (uint*)v - 2;
8010406a: 8d 50 f8 lea -0x8(%eax),%edx
for(i = 0; i < 10; i++){
8010406d: 31 c0 xor %eax,%eax
8010406f: 90 nop
if(ebp == 0 || ebp < (uint*)KERNBASE || ebp == (uint*)0xffffffff)
80104070: 8d 9a 00 00 00 80 lea -0x80000000(%edx),%ebx
80104076: 81 fb fe ff ff 7f cmp $0x7ffffffe,%ebx
8010407c: 77 1a ja 80104098 <getcallerpcs+0x38>
break;
pcs[i] = ebp[1]; // saved %eip
8010407e: 8b 5a 04 mov 0x4(%edx),%ebx
80104081: 89 1c 81 mov %ebx,(%ecx,%eax,4)
{
uint *ebp;
int i;
ebp = (uint*)v - 2;
for(i = 0; i < 10; i++){
80104084: 83 c0 01 add $0x1,%eax
if(ebp == 0 || ebp < (uint*)KERNBASE || ebp == (uint*)0xffffffff)
break;
pcs[i] = ebp[1]; // saved %eip
ebp = (uint*)ebp[0]; // saved %ebp
80104087: 8b 12 mov (%edx),%edx
{
uint *ebp;
int i;
ebp = (uint*)v - 2;
for(i = 0; i < 10; i++){
80104089: 83 f8 0a cmp $0xa,%eax
8010408c: 75 e2 jne 80104070 <getcallerpcs+0x10>
pcs[i] = ebp[1]; // saved %eip
ebp = (uint*)ebp[0]; // saved %ebp
}
for(; i < 10; i++)
pcs[i] = 0;
}
8010408e: 5b pop %ebx
8010408f: 5d pop %ebp
80104090: c3 ret
80104091: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
break;
pcs[i] = ebp[1]; // saved %eip
ebp = (uint*)ebp[0]; // saved %ebp
}
for(; i < 10; i++)
pcs[i] = 0;
80104098: c7 04 81 00 00 00 00 movl $0x0,(%ecx,%eax,4)
if(ebp == 0 || ebp < (uint*)KERNBASE || ebp == (uint*)0xffffffff)
break;
pcs[i] = ebp[1]; // saved %eip
ebp = (uint*)ebp[0]; // saved %ebp
}
for(; i < 10; i++)
8010409f: 83 c0 01 add $0x1,%eax
801040a2: 83 f8 0a cmp $0xa,%eax
801040a5: 74 e7 je 8010408e <getcallerpcs+0x2e>
pcs[i] = 0;
801040a7: c7 04 81 00 00 00 00 movl $0x0,(%ecx,%eax,4)
if(ebp == 0 || ebp < (uint*)KERNBASE || ebp == (uint*)0xffffffff)
break;
pcs[i] = ebp[1]; // saved %eip
ebp = (uint*)ebp[0]; // saved %ebp
}
for(; i < 10; i++)
801040ae: 83 c0 01 add $0x1,%eax
801040b1: 83 f8 0a cmp $0xa,%eax
801040b4: 75 e2 jne 80104098 <getcallerpcs+0x38>
801040b6: eb d6 jmp 8010408e <getcallerpcs+0x2e>
801040b8: 90 nop
801040b9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
801040c0 <holding>:
}
// Check whether this cpu is holding the lock.
int
holding(struct spinlock *lock)
{
801040c0: 55 push %ebp
return lock->locked && lock->cpu == mycpu();
801040c1: 31 c0 xor %eax,%eax
}
// Check whether this cpu is holding the lock.
int
holding(struct spinlock *lock)
{
801040c3: 89 e5 mov %esp,%ebp
801040c5: 53 push %ebx
801040c6: 83 ec 04 sub $0x4,%esp
801040c9: 8b 55 08 mov 0x8(%ebp),%edx
return lock->locked && lock->cpu == mycpu();
801040cc: 8b 0a mov (%edx),%ecx
801040ce: 85 c9 test %ecx,%ecx
801040d0: 74 10 je 801040e2 <holding+0x22>
801040d2: 8b 5a 08 mov 0x8(%edx),%ebx
801040d5: e8 16 f5 ff ff call 801035f0 <mycpu>
801040da: 39 c3 cmp %eax,%ebx
801040dc: 0f 94 c0 sete %al
801040df: 0f b6 c0 movzbl %al,%eax
}
801040e2: 83 c4 04 add $0x4,%esp
801040e5: 5b pop %ebx
801040e6: 5d pop %ebp
801040e7: c3 ret
801040e8: 90 nop
801040e9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
801040f0 <pushcli>:
// it takes two popcli to undo two pushcli. Also, if interrupts
// are off, then pushcli, popcli leaves them off.
void
pushcli(void)
{
801040f0: 55 push %ebp
801040f1: 89 e5 mov %esp,%ebp
801040f3: 53 push %ebx
801040f4: 83 ec 04 sub $0x4,%esp
801040f7: 9c pushf
801040f8: 5b pop %ebx
}
static inline void
cli(void)
{
asm volatile("cli");
801040f9: fa cli
int eflags;
eflags = readeflags();
cli();
if(mycpu()->ncli == 0)
801040fa: e8 f1 f4 ff ff call 801035f0 <mycpu>
801040ff: 8b 80 a4 00 00 00 mov 0xa4(%eax),%eax
80104105: 85 c0 test %eax,%eax
80104107: 75 11 jne 8010411a <pushcli+0x2a>
mycpu()->intena = eflags & FL_IF;
80104109: e8 e2 f4 ff ff call 801035f0 <mycpu>
8010410e: 81 e3 00 02 00 00 and $0x200,%ebx
80104114: 89 98 a8 00 00 00 mov %ebx,0xa8(%eax)
mycpu()->ncli += 1;
8010411a: e8 d1 f4 ff ff call 801035f0 <mycpu>
8010411f: 83 80 a4 00 00 00 01 addl $0x1,0xa4(%eax)
}
80104126: 83 c4 04 add $0x4,%esp
80104129: 5b pop %ebx
8010412a: 5d pop %ebp
8010412b: c3 ret
8010412c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80104130 <acquire>:
// Loops (spins) until the lock is acquired.
// Holding a lock for a long time may cause
// other CPUs to waste time spinning to acquire it.
void
acquire(struct spinlock *lk)
{
80104130: 55 push %ebp
80104131: 89 e5 mov %esp,%ebp
80104133: 53 push %ebx
80104134: 83 ec 14 sub $0x14,%esp
pushcli(); // disable interrupts to avoid deadlock.
80104137: e8 b4 ff ff ff call 801040f0 <pushcli>
if(holding(lk))
8010413c: 8b 55 08 mov 0x8(%ebp),%edx
// Check whether this cpu is holding the lock.
int
holding(struct spinlock *lock)
{
return lock->locked && lock->cpu == mycpu();
8010413f: 8b 02 mov (%edx),%eax
80104141: 85 c0 test %eax,%eax
80104143: 75 43 jne 80104188 <acquire+0x58>
xchg(volatile uint *addr, uint newval)
{
uint result;
// The + in "+m" denotes a read-modify-write operand.
asm volatile("lock; xchgl %0, %1" :
80104145: b9 01 00 00 00 mov $0x1,%ecx
8010414a: eb 07 jmp 80104153 <acquire+0x23>
8010414c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80104150: 8b 55 08 mov 0x8(%ebp),%edx
80104153: 89 c8 mov %ecx,%eax
80104155: f0 87 02 lock xchg %eax,(%edx)
pushcli(); // disable interrupts to avoid deadlock.
if(holding(lk))
panic("acquire");
// The xchg is atomic.
while(xchg(&lk->locked, 1) != 0)
80104158: 85 c0 test %eax,%eax
8010415a: 75 f4 jne 80104150 <acquire+0x20>
;
// Tell the C compiler and the processor to not move loads or stores
// past this point, to ensure that the critical section's memory
// references happen after the lock is acquired.
__sync_synchronize();
8010415c: 0f ae f0 mfence
// Record info about lock acquisition for debugging.
lk->cpu = mycpu();
8010415f: 8b 5d 08 mov 0x8(%ebp),%ebx
80104162: e8 89 f4 ff ff call 801035f0 <mycpu>
80104167: 89 43 08 mov %eax,0x8(%ebx)
getcallerpcs(&lk, lk->pcs);
8010416a: 8b 45 08 mov 0x8(%ebp),%eax
8010416d: 83 c0 0c add $0xc,%eax
80104170: 89 44 24 04 mov %eax,0x4(%esp)
80104174: 8d 45 08 lea 0x8(%ebp),%eax
80104177: 89 04 24 mov %eax,(%esp)
8010417a: e8 e1 fe ff ff call 80104060 <getcallerpcs>
}
8010417f: 83 c4 14 add $0x14,%esp
80104182: 5b pop %ebx
80104183: 5d pop %ebp
80104184: c3 ret
80104185: 8d 76 00 lea 0x0(%esi),%esi
// Check whether this cpu is holding the lock.
int
holding(struct spinlock *lock)
{
return lock->locked && lock->cpu == mycpu();
80104188: 8b 5a 08 mov 0x8(%edx),%ebx
8010418b: e8 60 f4 ff ff call 801035f0 <mycpu>
// other CPUs to waste time spinning to acquire it.
void
acquire(struct spinlock *lk)
{
pushcli(); // disable interrupts to avoid deadlock.
if(holding(lk))
80104190: 39 c3 cmp %eax,%ebx
80104192: 74 05 je 80104199 <acquire+0x69>
80104194: 8b 55 08 mov 0x8(%ebp),%edx
80104197: eb ac jmp 80104145 <acquire+0x15>
panic("acquire");
80104199: c7 04 24 23 74 10 80 movl $0x80107423,(%esp)
801041a0: e8 bb c1 ff ff call 80100360 <panic>
801041a5: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
801041a9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801041b0 <popcli>:
mycpu()->ncli += 1;
}
void
popcli(void)
{
801041b0: 55 push %ebp
801041b1: 89 e5 mov %esp,%ebp
801041b3: 83 ec 18 sub $0x18,%esp
static inline uint
readeflags(void)
{
uint eflags;
asm volatile("pushfl; popl %0" : "=r" (eflags));
801041b6: 9c pushf
801041b7: 58 pop %eax
if(readeflags()&FL_IF)
801041b8: f6 c4 02 test $0x2,%ah
801041bb: 75 49 jne 80104206 <popcli+0x56>
panic("popcli - interruptible");
if(--mycpu()->ncli < 0)
801041bd: e8 2e f4 ff ff call 801035f0 <mycpu>
801041c2: 8b 88 a4 00 00 00 mov 0xa4(%eax),%ecx
801041c8: 8d 51 ff lea -0x1(%ecx),%edx
801041cb: 85 d2 test %edx,%edx
801041cd: 89 90 a4 00 00 00 mov %edx,0xa4(%eax)
801041d3: 78 25 js 801041fa <popcli+0x4a>
panic("popcli");
if(mycpu()->ncli == 0 && mycpu()->intena)
801041d5: e8 16 f4 ff ff call 801035f0 <mycpu>
801041da: 8b 90 a4 00 00 00 mov 0xa4(%eax),%edx
801041e0: 85 d2 test %edx,%edx
801041e2: 74 04 je 801041e8 <popcli+0x38>
sti();
}
801041e4: c9 leave
801041e5: c3 ret
801041e6: 66 90 xchg %ax,%ax
{
if(readeflags()&FL_IF)
panic("popcli - interruptible");
if(--mycpu()->ncli < 0)
panic("popcli");
if(mycpu()->ncli == 0 && mycpu()->intena)
801041e8: e8 03 f4 ff ff call 801035f0 <mycpu>
801041ed: 8b 80 a8 00 00 00 mov 0xa8(%eax),%eax
801041f3: 85 c0 test %eax,%eax
801041f5: 74 ed je 801041e4 <popcli+0x34>
}
static inline void
sti(void)
{
asm volatile("sti");
801041f7: fb sti
sti();
}
801041f8: c9 leave
801041f9: c3 ret
popcli(void)
{
if(readeflags()&FL_IF)
panic("popcli - interruptible");
if(--mycpu()->ncli < 0)
panic("popcli");
801041fa: c7 04 24 42 74 10 80 movl $0x80107442,(%esp)
80104201: e8 5a c1 ff ff call 80100360 <panic>
void
popcli(void)
{
if(readeflags()&FL_IF)
panic("popcli - interruptible");
80104206: c7 04 24 2b 74 10 80 movl $0x8010742b,(%esp)
8010420d: e8 4e c1 ff ff call 80100360 <panic>
80104212: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80104219: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80104220 <release>:
}
// Release the lock.
void
release(struct spinlock *lk)
{
80104220: 55 push %ebp
80104221: 89 e5 mov %esp,%ebp
80104223: 56 push %esi
80104224: 53 push %ebx
80104225: 83 ec 10 sub $0x10,%esp
80104228: 8b 5d 08 mov 0x8(%ebp),%ebx
// Check whether this cpu is holding the lock.
int
holding(struct spinlock *lock)
{
return lock->locked && lock->cpu == mycpu();
8010422b: 8b 03 mov (%ebx),%eax
8010422d: 85 c0 test %eax,%eax
8010422f: 75 0f jne 80104240 <release+0x20>
// Release the lock.
void
release(struct spinlock *lk)
{
if(!holding(lk))
panic("release");
80104231: c7 04 24 49 74 10 80 movl $0x80107449,(%esp)
80104238: e8 23 c1 ff ff call 80100360 <panic>
8010423d: 8d 76 00 lea 0x0(%esi),%esi
// Check whether this cpu is holding the lock.
int
holding(struct spinlock *lock)
{
return lock->locked && lock->cpu == mycpu();
80104240: 8b 73 08 mov 0x8(%ebx),%esi
80104243: e8 a8 f3 ff ff call 801035f0 <mycpu>
// Release the lock.
void
release(struct spinlock *lk)
{
if(!holding(lk))
80104248: 39 c6 cmp %eax,%esi
8010424a: 75 e5 jne 80104231 <release+0x11>
panic("release");
lk->pcs[0] = 0;
8010424c: c7 43 0c 00 00 00 00 movl $0x0,0xc(%ebx)
lk->cpu = 0;
80104253: c7 43 08 00 00 00 00 movl $0x0,0x8(%ebx)
// Tell the C compiler and the processor to not move loads or stores
// past this point, to ensure that all the stores in the critical
// section are visible to other cores before the lock is released.
// Both the C compiler and the hardware may re-order loads and
// stores; __sync_synchronize() tells them both not to.
__sync_synchronize();
8010425a: 0f ae f0 mfence
// Release the lock, equivalent to lk->locked = 0.
// This code can't use a C assignment, since it might
// not be atomic. A real OS would use C atomics here.
asm volatile("movl $0, %0" : "+m" (lk->locked) : );
8010425d: c7 03 00 00 00 00 movl $0x0,(%ebx)
popcli();
}
80104263: 83 c4 10 add $0x10,%esp
80104266: 5b pop %ebx
80104267: 5e pop %esi
80104268: 5d pop %ebp
// Release the lock, equivalent to lk->locked = 0.
// This code can't use a C assignment, since it might
// not be atomic. A real OS would use C atomics here.
asm volatile("movl $0, %0" : "+m" (lk->locked) : );
popcli();
80104269: e9 42 ff ff ff jmp 801041b0 <popcli>
8010426e: 66 90 xchg %ax,%ax
80104270 <memset>:
#include "types.h"
#include "x86.h"
void*
memset(void *dst, int c, uint n)
{
80104270: 55 push %ebp
80104271: 89 e5 mov %esp,%ebp
80104273: 8b 55 08 mov 0x8(%ebp),%edx
80104276: 57 push %edi
80104277: 8b 4d 10 mov 0x10(%ebp),%ecx
8010427a: 53 push %ebx
if ((int)dst%4 == 0 && n%4 == 0){
8010427b: f6 c2 03 test $0x3,%dl
8010427e: 75 05 jne 80104285 <memset+0x15>
80104280: f6 c1 03 test $0x3,%cl
80104283: 74 13 je 80104298 <memset+0x28>
}
static inline void
stosb(void *addr, int data, int cnt)
{
asm volatile("cld; rep stosb" :
80104285: 89 d7 mov %edx,%edi
80104287: 8b 45 0c mov 0xc(%ebp),%eax
8010428a: fc cld
8010428b: f3 aa rep stos %al,%es:(%edi)
c &= 0xFF;
stosl(dst, (c<<24)|(c<<16)|(c<<8)|c, n/4);
} else
stosb(dst, c, n);
return dst;
}
8010428d: 5b pop %ebx
8010428e: 89 d0 mov %edx,%eax
80104290: 5f pop %edi
80104291: 5d pop %ebp
80104292: c3 ret
80104293: 90 nop
80104294: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
void*
memset(void *dst, int c, uint n)
{
if ((int)dst%4 == 0 && n%4 == 0){
c &= 0xFF;
80104298: 0f b6 7d 0c movzbl 0xc(%ebp),%edi
stosl(dst, (c<<24)|(c<<16)|(c<<8)|c, n/4);
8010429c: c1 e9 02 shr $0x2,%ecx
8010429f: 89 f8 mov %edi,%eax
801042a1: 89 fb mov %edi,%ebx
801042a3: c1 e0 18 shl $0x18,%eax
801042a6: c1 e3 10 shl $0x10,%ebx
801042a9: 09 d8 or %ebx,%eax
801042ab: 09 f8 or %edi,%eax
801042ad: c1 e7 08 shl $0x8,%edi
801042b0: 09 f8 or %edi,%eax
}
static inline void
stosl(void *addr, int data, int cnt)
{
asm volatile("cld; rep stosl" :
801042b2: 89 d7 mov %edx,%edi
801042b4: fc cld
801042b5: f3 ab rep stos %eax,%es:(%edi)
} else
stosb(dst, c, n);
return dst;
}
801042b7: 5b pop %ebx
801042b8: 89 d0 mov %edx,%eax
801042ba: 5f pop %edi
801042bb: 5d pop %ebp
801042bc: c3 ret
801042bd: 8d 76 00 lea 0x0(%esi),%esi
801042c0 <memcmp>:
int
memcmp(const void *v1, const void *v2, uint n)
{
801042c0: 55 push %ebp
801042c1: 89 e5 mov %esp,%ebp
801042c3: 8b 45 10 mov 0x10(%ebp),%eax
801042c6: 57 push %edi
801042c7: 56 push %esi
801042c8: 8b 75 0c mov 0xc(%ebp),%esi
801042cb: 53 push %ebx
801042cc: 8b 5d 08 mov 0x8(%ebp),%ebx
const uchar *s1, *s2;
s1 = v1;
s2 = v2;
while(n-- > 0){
801042cf: 85 c0 test %eax,%eax
801042d1: 8d 78 ff lea -0x1(%eax),%edi
801042d4: 74 26 je 801042fc <memcmp+0x3c>
if(*s1 != *s2)
801042d6: 0f b6 03 movzbl (%ebx),%eax
801042d9: 31 d2 xor %edx,%edx
801042db: 0f b6 0e movzbl (%esi),%ecx
801042de: 38 c8 cmp %cl,%al
801042e0: 74 16 je 801042f8 <memcmp+0x38>
801042e2: eb 24 jmp 80104308 <memcmp+0x48>
801042e4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
801042e8: 0f b6 44 13 01 movzbl 0x1(%ebx,%edx,1),%eax
801042ed: 83 c2 01 add $0x1,%edx
801042f0: 0f b6 0c 16 movzbl (%esi,%edx,1),%ecx
801042f4: 38 c8 cmp %cl,%al
801042f6: 75 10 jne 80104308 <memcmp+0x48>
{
const uchar *s1, *s2;
s1 = v1;
s2 = v2;
while(n-- > 0){
801042f8: 39 fa cmp %edi,%edx
801042fa: 75 ec jne 801042e8 <memcmp+0x28>
return *s1 - *s2;
s1++, s2++;
}
return 0;
}
801042fc: 5b pop %ebx
if(*s1 != *s2)
return *s1 - *s2;
s1++, s2++;
}
return 0;
801042fd: 31 c0 xor %eax,%eax
}
801042ff: 5e pop %esi
80104300: 5f pop %edi
80104301: 5d pop %ebp
80104302: c3 ret
80104303: 90 nop
80104304: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80104308: 5b pop %ebx
s1 = v1;
s2 = v2;
while(n-- > 0){
if(*s1 != *s2)
return *s1 - *s2;
80104309: 29 c8 sub %ecx,%eax
s1++, s2++;
}
return 0;
}
8010430b: 5e pop %esi
8010430c: 5f pop %edi
8010430d: 5d pop %ebp
8010430e: c3 ret
8010430f: 90 nop
80104310 <memmove>:
void*
memmove(void *dst, const void *src, uint n)
{
80104310: 55 push %ebp
80104311: 89 e5 mov %esp,%ebp
80104313: 57 push %edi
80104314: 8b 45 08 mov 0x8(%ebp),%eax
80104317: 56 push %esi
80104318: 8b 75 0c mov 0xc(%ebp),%esi
8010431b: 53 push %ebx
8010431c: 8b 5d 10 mov 0x10(%ebp),%ebx
const char *s;
char *d;
s = src;
d = dst;
if(s < d && s + n > d){
8010431f: 39 c6 cmp %eax,%esi
80104321: 73 35 jae 80104358 <memmove+0x48>
80104323: 8d 0c 1e lea (%esi,%ebx,1),%ecx
80104326: 39 c8 cmp %ecx,%eax
80104328: 73 2e jae 80104358 <memmove+0x48>
s += n;
d += n;
while(n-- > 0)
8010432a: 85 db test %ebx,%ebx
s = src;
d = dst;
if(s < d && s + n > d){
s += n;
d += n;
8010432c: 8d 3c 18 lea (%eax,%ebx,1),%edi
while(n-- > 0)
8010432f: 8d 53 ff lea -0x1(%ebx),%edx
80104332: 74 1b je 8010434f <memmove+0x3f>
80104334: f7 db neg %ebx
80104336: 8d 34 19 lea (%ecx,%ebx,1),%esi
80104339: 01 fb add %edi,%ebx
8010433b: 90 nop
8010433c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
*--d = *--s;
80104340: 0f b6 0c 16 movzbl (%esi,%edx,1),%ecx
80104344: 88 0c 13 mov %cl,(%ebx,%edx,1)
s = src;
d = dst;
if(s < d && s + n > d){
s += n;
d += n;
while(n-- > 0)
80104347: 83 ea 01 sub $0x1,%edx
8010434a: 83 fa ff cmp $0xffffffff,%edx
8010434d: 75 f1 jne 80104340 <memmove+0x30>
} else
while(n-- > 0)
*d++ = *s++;
return dst;
}
8010434f: 5b pop %ebx
80104350: 5e pop %esi
80104351: 5f pop %edi
80104352: 5d pop %ebp
80104353: c3 ret
80104354: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
s += n;
d += n;
while(n-- > 0)
*--d = *--s;
} else
while(n-- > 0)
80104358: 31 d2 xor %edx,%edx
8010435a: 85 db test %ebx,%ebx
8010435c: 74 f1 je 8010434f <memmove+0x3f>
8010435e: 66 90 xchg %ax,%ax
*d++ = *s++;
80104360: 0f b6 0c 16 movzbl (%esi,%edx,1),%ecx
80104364: 88 0c 10 mov %cl,(%eax,%edx,1)
80104367: 83 c2 01 add $0x1,%edx
s += n;
d += n;
while(n-- > 0)
*--d = *--s;
} else
while(n-- > 0)
8010436a: 39 da cmp %ebx,%edx
8010436c: 75 f2 jne 80104360 <memmove+0x50>
*d++ = *s++;
return dst;
}
8010436e: 5b pop %ebx
8010436f: 5e pop %esi
80104370: 5f pop %edi
80104371: 5d pop %ebp
80104372: c3 ret
80104373: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80104379: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80104380 <memcpy>:
// memcpy exists to placate GCC. Use memmove.
void*
memcpy(void *dst, const void *src, uint n)
{
80104380: 55 push %ebp
80104381: 89 e5 mov %esp,%ebp
return memmove(dst, src, n);
}
80104383: 5d pop %ebp
// memcpy exists to placate GCC. Use memmove.
void*
memcpy(void *dst, const void *src, uint n)
{
return memmove(dst, src, n);
80104384: e9 87 ff ff ff jmp 80104310 <memmove>
80104389: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80104390 <strncmp>:
}
int
strncmp(const char *p, const char *q, uint n)
{
80104390: 55 push %ebp
80104391: 89 e5 mov %esp,%ebp
80104393: 56 push %esi
80104394: 8b 75 10 mov 0x10(%ebp),%esi
80104397: 53 push %ebx
80104398: 8b 4d 08 mov 0x8(%ebp),%ecx
8010439b: 8b 5d 0c mov 0xc(%ebp),%ebx
while(n > 0 && *p && *p == *q)
8010439e: 85 f6 test %esi,%esi
801043a0: 74 30 je 801043d2 <strncmp+0x42>
801043a2: 0f b6 01 movzbl (%ecx),%eax
801043a5: 84 c0 test %al,%al
801043a7: 74 2f je 801043d8 <strncmp+0x48>
801043a9: 0f b6 13 movzbl (%ebx),%edx
801043ac: 38 d0 cmp %dl,%al
801043ae: 75 46 jne 801043f6 <strncmp+0x66>
801043b0: 8d 51 01 lea 0x1(%ecx),%edx
801043b3: 01 ce add %ecx,%esi
801043b5: eb 14 jmp 801043cb <strncmp+0x3b>
801043b7: 90 nop
801043b8: 0f b6 02 movzbl (%edx),%eax
801043bb: 84 c0 test %al,%al
801043bd: 74 31 je 801043f0 <strncmp+0x60>
801043bf: 0f b6 19 movzbl (%ecx),%ebx
801043c2: 83 c2 01 add $0x1,%edx
801043c5: 38 d8 cmp %bl,%al
801043c7: 75 17 jne 801043e0 <strncmp+0x50>
n--, p++, q++;
801043c9: 89 cb mov %ecx,%ebx
}
int
strncmp(const char *p, const char *q, uint n)
{
while(n > 0 && *p && *p == *q)
801043cb: 39 f2 cmp %esi,%edx
n--, p++, q++;
801043cd: 8d 4b 01 lea 0x1(%ebx),%ecx
}
int
strncmp(const char *p, const char *q, uint n)
{
while(n > 0 && *p && *p == *q)
801043d0: 75 e6 jne 801043b8 <strncmp+0x28>
n--, p++, q++;
if(n == 0)
return 0;
return (uchar)*p - (uchar)*q;
}
801043d2: 5b pop %ebx
strncmp(const char *p, const char *q, uint n)
{
while(n > 0 && *p && *p == *q)
n--, p++, q++;
if(n == 0)
return 0;
801043d3: 31 c0 xor %eax,%eax
return (uchar)*p - (uchar)*q;
}
801043d5: 5e pop %esi
801043d6: 5d pop %ebp
801043d7: c3 ret
801043d8: 0f b6 1b movzbl (%ebx),%ebx
}
int
strncmp(const char *p, const char *q, uint n)
{
while(n > 0 && *p && *p == *q)
801043db: 31 c0 xor %eax,%eax
801043dd: 8d 76 00 lea 0x0(%esi),%esi
n--, p++, q++;
if(n == 0)
return 0;
return (uchar)*p - (uchar)*q;
801043e0: 0f b6 d3 movzbl %bl,%edx
801043e3: 29 d0 sub %edx,%eax
}
801043e5: 5b pop %ebx
801043e6: 5e pop %esi
801043e7: 5d pop %ebp
801043e8: c3 ret
801043e9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
801043f0: 0f b6 5b 01 movzbl 0x1(%ebx),%ebx
801043f4: eb ea jmp 801043e0 <strncmp+0x50>
}
int
strncmp(const char *p, const char *q, uint n)
{
while(n > 0 && *p && *p == *q)
801043f6: 89 d3 mov %edx,%ebx
801043f8: eb e6 jmp 801043e0 <strncmp+0x50>
801043fa: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80104400 <strncpy>:
return (uchar)*p - (uchar)*q;
}
char*
strncpy(char *s, const char *t, int n)
{
80104400: 55 push %ebp
80104401: 89 e5 mov %esp,%ebp
80104403: 8b 45 08 mov 0x8(%ebp),%eax
80104406: 56 push %esi
80104407: 8b 4d 10 mov 0x10(%ebp),%ecx
8010440a: 53 push %ebx
8010440b: 8b 5d 0c mov 0xc(%ebp),%ebx
char *os;
os = s;
while(n-- > 0 && (*s++ = *t++) != 0)
8010440e: 89 c2 mov %eax,%edx
80104410: eb 19 jmp 8010442b <strncpy+0x2b>
80104412: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80104418: 83 c3 01 add $0x1,%ebx
8010441b: 0f b6 4b ff movzbl -0x1(%ebx),%ecx
8010441f: 83 c2 01 add $0x1,%edx
80104422: 84 c9 test %cl,%cl
80104424: 88 4a ff mov %cl,-0x1(%edx)
80104427: 74 09 je 80104432 <strncpy+0x32>
80104429: 89 f1 mov %esi,%ecx
8010442b: 85 c9 test %ecx,%ecx
8010442d: 8d 71 ff lea -0x1(%ecx),%esi
80104430: 7f e6 jg 80104418 <strncpy+0x18>
;
while(n-- > 0)
80104432: 31 c9 xor %ecx,%ecx
80104434: 85 f6 test %esi,%esi
80104436: 7e 0f jle 80104447 <strncpy+0x47>
*s++ = 0;
80104438: c6 04 0a 00 movb $0x0,(%edx,%ecx,1)
8010443c: 89 f3 mov %esi,%ebx
8010443e: 83 c1 01 add $0x1,%ecx
80104441: 29 cb sub %ecx,%ebx
char *os;
os = s;
while(n-- > 0 && (*s++ = *t++) != 0)
;
while(n-- > 0)
80104443: 85 db test %ebx,%ebx
80104445: 7f f1 jg 80104438 <strncpy+0x38>
*s++ = 0;
return os;
}
80104447: 5b pop %ebx
80104448: 5e pop %esi
80104449: 5d pop %ebp
8010444a: c3 ret
8010444b: 90 nop
8010444c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80104450 <safestrcpy>:
// Like strncpy but guaranteed to NUL-terminate.
char*
safestrcpy(char *s, const char *t, int n)
{
80104450: 55 push %ebp
80104451: 89 e5 mov %esp,%ebp
80104453: 8b 4d 10 mov 0x10(%ebp),%ecx
80104456: 56 push %esi
80104457: 8b 45 08 mov 0x8(%ebp),%eax
8010445a: 53 push %ebx
8010445b: 8b 55 0c mov 0xc(%ebp),%edx
char *os;
os = s;
if(n <= 0)
8010445e: 85 c9 test %ecx,%ecx
80104460: 7e 26 jle 80104488 <safestrcpy+0x38>
80104462: 8d 74 0a ff lea -0x1(%edx,%ecx,1),%esi
80104466: 89 c1 mov %eax,%ecx
80104468: eb 17 jmp 80104481 <safestrcpy+0x31>
8010446a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
return os;
while(--n > 0 && (*s++ = *t++) != 0)
80104470: 83 c2 01 add $0x1,%edx
80104473: 0f b6 5a ff movzbl -0x1(%edx),%ebx
80104477: 83 c1 01 add $0x1,%ecx
8010447a: 84 db test %bl,%bl
8010447c: 88 59 ff mov %bl,-0x1(%ecx)
8010447f: 74 04 je 80104485 <safestrcpy+0x35>
80104481: 39 f2 cmp %esi,%edx
80104483: 75 eb jne 80104470 <safestrcpy+0x20>
;
*s = 0;
80104485: c6 01 00 movb $0x0,(%ecx)
return os;
}
80104488: 5b pop %ebx
80104489: 5e pop %esi
8010448a: 5d pop %ebp
8010448b: c3 ret
8010448c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80104490 <strlen>:
int
strlen(const char *s)
{
80104490: 55 push %ebp
int n;
for(n = 0; s[n]; n++)
80104491: 31 c0 xor %eax,%eax
return os;
}
int
strlen(const char *s)
{
80104493: 89 e5 mov %esp,%ebp
80104495: 8b 55 08 mov 0x8(%ebp),%edx
int n;
for(n = 0; s[n]; n++)
80104498: 80 3a 00 cmpb $0x0,(%edx)
8010449b: 74 0c je 801044a9 <strlen+0x19>
8010449d: 8d 76 00 lea 0x0(%esi),%esi
801044a0: 83 c0 01 add $0x1,%eax
801044a3: 80 3c 02 00 cmpb $0x0,(%edx,%eax,1)
801044a7: 75 f7 jne 801044a0 <strlen+0x10>
;
return n;
}
801044a9: 5d pop %ebp
801044aa: c3 ret
801044ab <swtch>:
# Save current register context in old
# and then load register context from new.
.globl swtch
swtch:
movl 4(%esp), %eax
801044ab: 8b 44 24 04 mov 0x4(%esp),%eax
movl 8(%esp), %edx
801044af: 8b 54 24 08 mov 0x8(%esp),%edx
# Save old callee-save registers
pushl %ebp
801044b3: 55 push %ebp
pushl %ebx
801044b4: 53 push %ebx
pushl %esi
801044b5: 56 push %esi
pushl %edi
801044b6: 57 push %edi
# Switch stacks
movl %esp, (%eax)
801044b7: 89 20 mov %esp,(%eax)
movl %edx, %esp
801044b9: 89 d4 mov %edx,%esp
# Load new callee-save registers
popl %edi
801044bb: 5f pop %edi
popl %esi
801044bc: 5e pop %esi
popl %ebx
801044bd: 5b pop %ebx
popl %ebp
801044be: 5d pop %ebp
ret
801044bf: c3 ret
801044c0 <fetchint>:
// to a saved program counter, and then the first argument.
// Fetch the int at addr from the current process.
int
fetchint(uint addr, int *ip)
{
801044c0: 55 push %ebp
801044c1: 89 e5 mov %esp,%ebp
// struct proc *curproc = myproc();
//if(addr >= (KERNBASE + 4)) || addr+4 > (curproc->sz + PGSIZE - 1))
// return -1;
*ip = *(int*)(addr);
801044c3: 8b 45 08 mov 0x8(%ebp),%eax
801044c6: 8b 10 mov (%eax),%edx
801044c8: 8b 45 0c mov 0xc(%ebp),%eax
801044cb: 89 10 mov %edx,(%eax)
return 0;
}
801044cd: 31 c0 xor %eax,%eax
801044cf: 5d pop %ebp
801044d0: c3 ret
801044d1: eb 0d jmp 801044e0 <fetchstr>
801044d3: 90 nop
801044d4: 90 nop
801044d5: 90 nop
801044d6: 90 nop
801044d7: 90 nop
801044d8: 90 nop
801044d9: 90 nop
801044da: 90 nop
801044db: 90 nop
801044dc: 90 nop
801044dd: 90 nop
801044de: 90 nop
801044df: 90 nop
801044e0 <fetchstr>:
// Fetch the nul-terminated string at addr from the current process.
// Doesn't actually copy the string - just sets *pp to point at it.
// Returns length of string, not including nul.
int
fetchstr(uint addr, char **pp)
{
801044e0: 55 push %ebp
801044e1: 89 e5 mov %esp,%ebp
801044e3: 8b 55 08 mov 0x8(%ebp),%edx
char *s, *ep;
// struct proc *curproc = myproc();
//panic("hei");
if(addr >= (KERNBASE + 4))
801044e6: 81 fa 03 00 00 80 cmp $0x80000003,%edx
801044ec: 77 2e ja 8010451c <fetchstr+0x3c>
return -1;
*pp = (char*)addr;
801044ee: 8b 4d 0c mov 0xc(%ebp),%ecx
ep = (char*)KERNBASE;//curproc->sz;
for(s = *pp; s < ep; s++){
801044f1: 81 fa ff ff ff 7f cmp $0x7fffffff,%edx
char *s, *ep;
// struct proc *curproc = myproc();
//panic("hei");
if(addr >= (KERNBASE + 4))
return -1;
*pp = (char*)addr;
801044f7: 89 d0 mov %edx,%eax
801044f9: 89 11 mov %edx,(%ecx)
ep = (char*)KERNBASE;//curproc->sz;
for(s = *pp; s < ep; s++){
801044fb: 77 1f ja 8010451c <fetchstr+0x3c>
if(*s == 0)
801044fd: 80 3a 00 cmpb $0x0,(%edx)
80104500: 75 10 jne 80104512 <fetchstr+0x32>
80104502: eb 24 jmp 80104528 <fetchstr+0x48>
80104504: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80104508: 80 38 00 cmpb $0x0,(%eax)
8010450b: 90 nop
8010450c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80104510: 74 16 je 80104528 <fetchstr+0x48>
//panic("hei");
if(addr >= (KERNBASE + 4))
return -1;
*pp = (char*)addr;
ep = (char*)KERNBASE;//curproc->sz;
for(s = *pp; s < ep; s++){
80104512: 83 c0 01 add $0x1,%eax
80104515: 3d 00 00 00 80 cmp $0x80000000,%eax
8010451a: 75 ec jne 80104508 <fetchstr+0x28>
{
char *s, *ep;
// struct proc *curproc = myproc();
//panic("hei");
if(addr >= (KERNBASE + 4))
return -1;
8010451c: b8 ff ff ff ff mov $0xffffffff,%eax
for(s = *pp; s < ep; s++){
if(*s == 0)
return s - *pp;
}
return -1;
}
80104521: 5d pop %ebp
80104522: c3 ret
80104523: 90 nop
80104524: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
return -1;
*pp = (char*)addr;
ep = (char*)KERNBASE;//curproc->sz;
for(s = *pp; s < ep; s++){
if(*s == 0)
return s - *pp;
80104528: 29 d0 sub %edx,%eax
}
return -1;
}
8010452a: 5d pop %ebp
8010452b: c3 ret
8010452c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80104530 <argint>:
// Fetch the nth 32-bit system call argument.
int
argint(int n, int *ip)
{
80104530: 55 push %ebp
80104531: 89 e5 mov %esp,%ebp
80104533: 83 ec 08 sub $0x8,%esp
return fetchint((myproc()->tf->esp) + 4 + 4*n, ip);
80104536: e8 55 f1 ff ff call 80103690 <myproc>
{
// struct proc *curproc = myproc();
//if(addr >= (KERNBASE + 4)) || addr+4 > (curproc->sz + PGSIZE - 1))
// return -1;
*ip = *(int*)(addr);
8010453b: 8b 55 08 mov 0x8(%ebp),%edx
// Fetch the nth 32-bit system call argument.
int
argint(int n, int *ip)
{
return fetchint((myproc()->tf->esp) + 4 + 4*n, ip);
8010453e: 8b 40 1c mov 0x1c(%eax),%eax
{
// struct proc *curproc = myproc();
//if(addr >= (KERNBASE + 4)) || addr+4 > (curproc->sz + PGSIZE - 1))
// return -1;
*ip = *(int*)(addr);
80104541: 8b 40 44 mov 0x44(%eax),%eax
80104544: 8b 54 90 04 mov 0x4(%eax,%edx,4),%edx
80104548: 8b 45 0c mov 0xc(%ebp),%eax
8010454b: 89 10 mov %edx,(%eax)
// Fetch the nth 32-bit system call argument.
int
argint(int n, int *ip)
{
return fetchint((myproc()->tf->esp) + 4 + 4*n, ip);
}
8010454d: 31 c0 xor %eax,%eax
8010454f: c9 leave
80104550: c3 ret
80104551: eb 0d jmp 80104560 <argptr>
80104553: 90 nop
80104554: 90 nop
80104555: 90 nop
80104556: 90 nop
80104557: 90 nop
80104558: 90 nop
80104559: 90 nop
8010455a: 90 nop
8010455b: 90 nop
8010455c: 90 nop
8010455d: 90 nop
8010455e: 90 nop
8010455f: 90 nop
80104560 <argptr>:
// Fetch the nth word-sized system call argument as a pointer
// to a block of memory of size bytes. Check that the pointer
// lies within the process address space.
int
argptr(int n, char **pp, int size)
{
80104560: 55 push %ebp
80104561: 89 e5 mov %esp,%ebp
80104563: 83 ec 08 sub $0x8,%esp
// Fetch the nth 32-bit system call argument.
int
argint(int n, int *ip)
{
return fetchint((myproc()->tf->esp) + 4 + 4*n, ip);
80104566: e8 25 f1 ff ff call 80103690 <myproc>
if(argint(n, &i) < 0)
return -1;
// if(size < 0 || (uint)i >= (KERNBASE + 4)) || (uint)i+size > (curproc->sz + PGSIZE - 1))
// return -1;
*pp = (char*)i;
8010456b: 8b 55 08 mov 0x8(%ebp),%edx
// Fetch the nth 32-bit system call argument.
int
argint(int n, int *ip)
{
return fetchint((myproc()->tf->esp) + 4 + 4*n, ip);
8010456e: 8b 40 1c mov 0x1c(%eax),%eax
{
// struct proc *curproc = myproc();
//if(addr >= (KERNBASE + 4)) || addr+4 > (curproc->sz + PGSIZE - 1))
// return -1;
*ip = *(int*)(addr);
80104571: 8b 40 44 mov 0x44(%eax),%eax
if(argint(n, &i) < 0)
return -1;
// if(size < 0 || (uint)i >= (KERNBASE + 4)) || (uint)i+size > (curproc->sz + PGSIZE - 1))
// return -1;
*pp = (char*)i;
80104574: 8b 54 90 04 mov 0x4(%eax,%edx,4),%edx
80104578: 8b 45 0c mov 0xc(%ebp),%eax
8010457b: 89 10 mov %edx,(%eax)
return 0;
}
8010457d: 31 c0 xor %eax,%eax
8010457f: c9 leave
80104580: c3 ret
80104581: eb 0d jmp 80104590 <argstr>
80104583: 90 nop
80104584: 90 nop
80104585: 90 nop
80104586: 90 nop
80104587: 90 nop
80104588: 90 nop
80104589: 90 nop
8010458a: 90 nop
8010458b: 90 nop
8010458c: 90 nop
8010458d: 90 nop
8010458e: 90 nop
8010458f: 90 nop
80104590 <argstr>:
// Check that the pointer is valid and the string is nul-terminated.
// (There is no shared writable memory, so the string can't change
// between this check and being used by the kernel.)
int
argstr(int n, char **pp)
{
80104590: 55 push %ebp
80104591: 89 e5 mov %esp,%ebp
80104593: 83 ec 08 sub $0x8,%esp
// Fetch the nth 32-bit system call argument.
int
argint(int n, int *ip)
{
return fetchint((myproc()->tf->esp) + 4 + 4*n, ip);
80104596: e8 f5 f0 ff ff call 80103690 <myproc>
{
// struct proc *curproc = myproc();
//if(addr >= (KERNBASE + 4)) || addr+4 > (curproc->sz + PGSIZE - 1))
// return -1;
*ip = *(int*)(addr);
8010459b: 8b 55 08 mov 0x8(%ebp),%edx
// Fetch the nth 32-bit system call argument.
int
argint(int n, int *ip)
{
return fetchint((myproc()->tf->esp) + 4 + 4*n, ip);
8010459e: 8b 40 1c mov 0x1c(%eax),%eax
{
// struct proc *curproc = myproc();
//if(addr >= (KERNBASE + 4)) || addr+4 > (curproc->sz + PGSIZE - 1))
// return -1;
*ip = *(int*)(addr);
801045a1: 8b 40 44 mov 0x44(%eax),%eax
801045a4: 8b 54 90 04 mov 0x4(%eax,%edx,4),%edx
fetchstr(uint addr, char **pp)
{
char *s, *ep;
// struct proc *curproc = myproc();
//panic("hei");
if(addr >= (KERNBASE + 4))
801045a8: 81 fa 03 00 00 80 cmp $0x80000003,%edx
801045ae: 77 27 ja 801045d7 <argstr+0x47>
return -1;
*pp = (char*)addr;
801045b0: 8b 4d 0c mov 0xc(%ebp),%ecx
ep = (char*)KERNBASE;//curproc->sz;
for(s = *pp; s < ep; s++){
801045b3: 81 fa ff ff ff 7f cmp $0x7fffffff,%edx
char *s, *ep;
// struct proc *curproc = myproc();
//panic("hei");
if(addr >= (KERNBASE + 4))
return -1;
*pp = (char*)addr;
801045b9: 89 d0 mov %edx,%eax
801045bb: 89 11 mov %edx,(%ecx)
ep = (char*)KERNBASE;//curproc->sz;
for(s = *pp; s < ep; s++){
801045bd: 77 18 ja 801045d7 <argstr+0x47>
if(*s == 0)
801045bf: 80 3a 00 cmpb $0x0,(%edx)
801045c2: 75 0e jne 801045d2 <argstr+0x42>
801045c4: eb 1a jmp 801045e0 <argstr+0x50>
801045c6: 66 90 xchg %ax,%ax
801045c8: 80 38 00 cmpb $0x0,(%eax)
801045cb: 90 nop
801045cc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
801045d0: 74 0e je 801045e0 <argstr+0x50>
//panic("hei");
if(addr >= (KERNBASE + 4))
return -1;
*pp = (char*)addr;
ep = (char*)KERNBASE;//curproc->sz;
for(s = *pp; s < ep; s++){
801045d2: 83 c0 01 add $0x1,%eax
801045d5: 79 f1 jns 801045c8 <argstr+0x38>
{
char *s, *ep;
// struct proc *curproc = myproc();
//panic("hei");
if(addr >= (KERNBASE + 4))
return -1;
801045d7: b8 ff ff ff ff mov $0xffffffff,%eax
{
int addr;
if(argint(n, &addr) < 0)
return -1;
return fetchstr(addr, pp);
}
801045dc: c9 leave
801045dd: c3 ret
801045de: 66 90 xchg %ax,%ax
return -1;
*pp = (char*)addr;
ep = (char*)KERNBASE;//curproc->sz;
for(s = *pp; s < ep; s++){
if(*s == 0)
return s - *pp;
801045e0: 29 d0 sub %edx,%eax
{
int addr;
if(argint(n, &addr) < 0)
return -1;
return fetchstr(addr, pp);
}
801045e2: c9 leave
801045e3: c3 ret
801045e4: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
801045ea: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
801045f0 <syscall>:
[SYS_shm_close] sys_shm_close
};
void
syscall(void)
{
801045f0: 55 push %ebp
801045f1: 89 e5 mov %esp,%ebp
801045f3: 56 push %esi
801045f4: 53 push %ebx
801045f5: 83 ec 10 sub $0x10,%esp
int num;
struct proc *curproc = myproc();
801045f8: e8 93 f0 ff ff call 80103690 <myproc>
num = curproc->tf->eax;
801045fd: 8b 70 1c mov 0x1c(%eax),%esi
void
syscall(void)
{
int num;
struct proc *curproc = myproc();
80104600: 89 c3 mov %eax,%ebx
num = curproc->tf->eax;
80104602: 8b 46 1c mov 0x1c(%esi),%eax
if(num > 0 && num < NELEM(syscalls) && syscalls[num]) {
80104605: 8d 50 ff lea -0x1(%eax),%edx
80104608: 83 fa 16 cmp $0x16,%edx
8010460b: 77 1b ja 80104628 <syscall+0x38>
8010460d: 8b 14 85 80 74 10 80 mov -0x7fef8b80(,%eax,4),%edx
80104614: 85 d2 test %edx,%edx
80104616: 74 10 je 80104628 <syscall+0x38>
curproc->tf->eax = syscalls[num]();
80104618: ff d2 call *%edx
8010461a: 89 46 1c mov %eax,0x1c(%esi)
} else {
cprintf("%d %s: unknown sys call %d\n",
curproc->pid, curproc->name, num);
curproc->tf->eax = -1;
}
}
8010461d: 83 c4 10 add $0x10,%esp
80104620: 5b pop %ebx
80104621: 5e pop %esi
80104622: 5d pop %ebp
80104623: c3 ret
80104624: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
num = curproc->tf->eax;
if(num > 0 && num < NELEM(syscalls) && syscalls[num]) {
curproc->tf->eax = syscalls[num]();
} else {
cprintf("%d %s: unknown sys call %d\n",
80104628: 89 44 24 0c mov %eax,0xc(%esp)
curproc->pid, curproc->name, num);
8010462c: 8d 43 70 lea 0x70(%ebx),%eax
8010462f: 89 44 24 08 mov %eax,0x8(%esp)
num = curproc->tf->eax;
if(num > 0 && num < NELEM(syscalls) && syscalls[num]) {
curproc->tf->eax = syscalls[num]();
} else {
cprintf("%d %s: unknown sys call %d\n",
80104633: 8b 43 14 mov 0x14(%ebx),%eax
80104636: c7 04 24 51 74 10 80 movl $0x80107451,(%esp)
8010463d: 89 44 24 04 mov %eax,0x4(%esp)
80104641: e8 0a c0 ff ff call 80100650 <cprintf>
curproc->pid, curproc->name, num);
curproc->tf->eax = -1;
80104646: 8b 43 1c mov 0x1c(%ebx),%eax
80104649: c7 40 1c ff ff ff ff movl $0xffffffff,0x1c(%eax)
}
}
80104650: 83 c4 10 add $0x10,%esp
80104653: 5b pop %ebx
80104654: 5e pop %esi
80104655: 5d pop %ebp
80104656: c3 ret
80104657: 66 90 xchg %ax,%ax
80104659: 66 90 xchg %ax,%ax
8010465b: 66 90 xchg %ax,%ax
8010465d: 66 90 xchg %ax,%ax
8010465f: 90 nop
80104660 <fdalloc>:
// Allocate a file descriptor for the given file.
// Takes over file reference from caller on success.
static int
fdalloc(struct file *f)
{
80104660: 55 push %ebp
80104661: 89 e5 mov %esp,%ebp
80104663: 53 push %ebx
80104664: 89 c3 mov %eax,%ebx
80104666: 83 ec 04 sub $0x4,%esp
int fd;
struct proc *curproc = myproc();
80104669: e8 22 f0 ff ff call 80103690 <myproc>
for(fd = 0; fd < NOFILE; fd++){
8010466e: 31 d2 xor %edx,%edx
if(curproc->ofile[fd] == 0){
80104670: 8b 4c 90 2c mov 0x2c(%eax,%edx,4),%ecx
80104674: 85 c9 test %ecx,%ecx
80104676: 74 18 je 80104690 <fdalloc+0x30>
fdalloc(struct file *f)
{
int fd;
struct proc *curproc = myproc();
for(fd = 0; fd < NOFILE; fd++){
80104678: 83 c2 01 add $0x1,%edx
8010467b: 83 fa 10 cmp $0x10,%edx
8010467e: 75 f0 jne 80104670 <fdalloc+0x10>
curproc->ofile[fd] = f;
return fd;
}
}
return -1;
}
80104680: 83 c4 04 add $0x4,%esp
if(curproc->ofile[fd] == 0){
curproc->ofile[fd] = f;
return fd;
}
}
return -1;
80104683: b8 ff ff ff ff mov $0xffffffff,%eax
}
80104688: 5b pop %ebx
80104689: 5d pop %ebp
8010468a: c3 ret
8010468b: 90 nop
8010468c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
int fd;
struct proc *curproc = myproc();
for(fd = 0; fd < NOFILE; fd++){
if(curproc->ofile[fd] == 0){
curproc->ofile[fd] = f;
80104690: 89 5c 90 2c mov %ebx,0x2c(%eax,%edx,4)
return fd;
}
}
return -1;
}
80104694: 83 c4 04 add $0x4,%esp
struct proc *curproc = myproc();
for(fd = 0; fd < NOFILE; fd++){
if(curproc->ofile[fd] == 0){
curproc->ofile[fd] = f;
return fd;
80104697: 89 d0 mov %edx,%eax
}
}
return -1;
}
80104699: 5b pop %ebx
8010469a: 5d pop %ebp
8010469b: c3 ret
8010469c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
801046a0 <create>:
return -1;
}
static struct inode*
create(char *path, short type, short major, short minor)
{
801046a0: 55 push %ebp
801046a1: 89 e5 mov %esp,%ebp
801046a3: 57 push %edi
801046a4: 56 push %esi
801046a5: 53 push %ebx
801046a6: 83 ec 4c sub $0x4c,%esp
801046a9: 89 4d c0 mov %ecx,-0x40(%ebp)
801046ac: 8b 4d 08 mov 0x8(%ebp),%ecx
uint off;
struct inode *ip, *dp;
char name[DIRSIZ];
if((dp = nameiparent(path, name)) == 0)
801046af: 8d 5d da lea -0x26(%ebp),%ebx
801046b2: 89 5c 24 04 mov %ebx,0x4(%esp)
801046b6: 89 04 24 mov %eax,(%esp)
return -1;
}
static struct inode*
create(char *path, short type, short major, short minor)
{
801046b9: 89 55 c4 mov %edx,-0x3c(%ebp)
801046bc: 89 4d bc mov %ecx,-0x44(%ebp)
uint off;
struct inode *ip, *dp;
char name[DIRSIZ];
if((dp = nameiparent(path, name)) == 0)
801046bf: e8 4c d8 ff ff call 80101f10 <nameiparent>
801046c4: 85 c0 test %eax,%eax
801046c6: 89 c7 mov %eax,%edi
801046c8: 0f 84 da 00 00 00 je 801047a8 <create+0x108>
return 0;
ilock(dp);
801046ce: 89 04 24 mov %eax,(%esp)
801046d1: e8 ca cf ff ff call 801016a0 <ilock>
if((ip = dirlookup(dp, name, &off)) != 0){
801046d6: 8d 45 d4 lea -0x2c(%ebp),%eax
801046d9: 89 44 24 08 mov %eax,0x8(%esp)
801046dd: 89 5c 24 04 mov %ebx,0x4(%esp)
801046e1: 89 3c 24 mov %edi,(%esp)
801046e4: e8 c7 d4 ff ff call 80101bb0 <dirlookup>
801046e9: 85 c0 test %eax,%eax
801046eb: 89 c6 mov %eax,%esi
801046ed: 74 41 je 80104730 <create+0x90>
iunlockput(dp);
801046ef: 89 3c 24 mov %edi,(%esp)
801046f2: e8 09 d2 ff ff call 80101900 <iunlockput>
ilock(ip);
801046f7: 89 34 24 mov %esi,(%esp)
801046fa: e8 a1 cf ff ff call 801016a0 <ilock>
if(type == T_FILE && ip->type == T_FILE)
801046ff: 66 83 7d c4 02 cmpw $0x2,-0x3c(%ebp)
80104704: 75 12 jne 80104718 <create+0x78>
80104706: 66 83 7e 50 02 cmpw $0x2,0x50(%esi)
8010470b: 89 f0 mov %esi,%eax
8010470d: 75 09 jne 80104718 <create+0x78>
panic("create: dirlink");
iunlockput(dp);
return ip;
}
8010470f: 83 c4 4c add $0x4c,%esp
80104712: 5b pop %ebx
80104713: 5e pop %esi
80104714: 5f pop %edi
80104715: 5d pop %ebp
80104716: c3 ret
80104717: 90 nop
if((ip = dirlookup(dp, name, &off)) != 0){
iunlockput(dp);
ilock(ip);
if(type == T_FILE && ip->type == T_FILE)
return ip;
iunlockput(ip);
80104718: 89 34 24 mov %esi,(%esp)
8010471b: e8 e0 d1 ff ff call 80101900 <iunlockput>
panic("create: dirlink");
iunlockput(dp);
return ip;
}
80104720: 83 c4 4c add $0x4c,%esp
iunlockput(dp);
ilock(ip);
if(type == T_FILE && ip->type == T_FILE)
return ip;
iunlockput(ip);
return 0;
80104723: 31 c0 xor %eax,%eax
panic("create: dirlink");
iunlockput(dp);
return ip;
}
80104725: 5b pop %ebx
80104726: 5e pop %esi
80104727: 5f pop %edi
80104728: 5d pop %ebp
80104729: c3 ret
8010472a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
return ip;
iunlockput(ip);
return 0;
}
if((ip = ialloc(dp->dev, type)) == 0)
80104730: 0f bf 45 c4 movswl -0x3c(%ebp),%eax
80104734: 89 44 24 04 mov %eax,0x4(%esp)
80104738: 8b 07 mov (%edi),%eax
8010473a: 89 04 24 mov %eax,(%esp)
8010473d: e8 ce cd ff ff call 80101510 <ialloc>
80104742: 85 c0 test %eax,%eax
80104744: 89 c6 mov %eax,%esi
80104746: 0f 84 bf 00 00 00 je 8010480b <create+0x16b>
panic("create: ialloc");
ilock(ip);
8010474c: 89 04 24 mov %eax,(%esp)
8010474f: e8 4c cf ff ff call 801016a0 <ilock>
ip->major = major;
80104754: 0f b7 45 c0 movzwl -0x40(%ebp),%eax
80104758: 66 89 46 52 mov %ax,0x52(%esi)
ip->minor = minor;
8010475c: 0f b7 45 bc movzwl -0x44(%ebp),%eax
80104760: 66 89 46 54 mov %ax,0x54(%esi)
ip->nlink = 1;
80104764: b8 01 00 00 00 mov $0x1,%eax
80104769: 66 89 46 56 mov %ax,0x56(%esi)
iupdate(ip);
8010476d: 89 34 24 mov %esi,(%esp)
80104770: e8 6b ce ff ff call 801015e0 <iupdate>
if(type == T_DIR){ // Create . and .. entries.
80104775: 66 83 7d c4 01 cmpw $0x1,-0x3c(%ebp)
8010477a: 74 34 je 801047b0 <create+0x110>
// No ip->nlink++ for ".": avoid cyclic ref count.
if(dirlink(ip, ".", ip->inum) < 0 || dirlink(ip, "..", dp->inum) < 0)
panic("create dots");
}
if(dirlink(dp, name, ip->inum) < 0)
8010477c: 8b 46 04 mov 0x4(%esi),%eax
8010477f: 89 5c 24 04 mov %ebx,0x4(%esp)
80104783: 89 3c 24 mov %edi,(%esp)
80104786: 89 44 24 08 mov %eax,0x8(%esp)
8010478a: e8 81 d6 ff ff call 80101e10 <dirlink>
8010478f: 85 c0 test %eax,%eax
80104791: 78 6c js 801047ff <create+0x15f>
panic("create: dirlink");
iunlockput(dp);
80104793: 89 3c 24 mov %edi,(%esp)
80104796: e8 65 d1 ff ff call 80101900 <iunlockput>
return ip;
}
8010479b: 83 c4 4c add $0x4c,%esp
if(dirlink(dp, name, ip->inum) < 0)
panic("create: dirlink");
iunlockput(dp);
return ip;
8010479e: 89 f0 mov %esi,%eax
}
801047a0: 5b pop %ebx
801047a1: 5e pop %esi
801047a2: 5f pop %edi
801047a3: 5d pop %ebp
801047a4: c3 ret
801047a5: 8d 76 00 lea 0x0(%esi),%esi
uint off;
struct inode *ip, *dp;
char name[DIRSIZ];
if((dp = nameiparent(path, name)) == 0)
return 0;
801047a8: 31 c0 xor %eax,%eax
801047aa: e9 60 ff ff ff jmp 8010470f <create+0x6f>
801047af: 90 nop
ip->minor = minor;
ip->nlink = 1;
iupdate(ip);
if(type == T_DIR){ // Create . and .. entries.
dp->nlink++; // for ".."
801047b0: 66 83 47 56 01 addw $0x1,0x56(%edi)
iupdate(dp);
801047b5: 89 3c 24 mov %edi,(%esp)
801047b8: e8 23 ce ff ff call 801015e0 <iupdate>
// No ip->nlink++ for ".": avoid cyclic ref count.
if(dirlink(ip, ".", ip->inum) < 0 || dirlink(ip, "..", dp->inum) < 0)
801047bd: 8b 46 04 mov 0x4(%esi),%eax
801047c0: c7 44 24 04 fc 74 10 movl $0x801074fc,0x4(%esp)
801047c7: 80
801047c8: 89 34 24 mov %esi,(%esp)
801047cb: 89 44 24 08 mov %eax,0x8(%esp)
801047cf: e8 3c d6 ff ff call 80101e10 <dirlink>
801047d4: 85 c0 test %eax,%eax
801047d6: 78 1b js 801047f3 <create+0x153>
801047d8: 8b 47 04 mov 0x4(%edi),%eax
801047db: c7 44 24 04 fb 74 10 movl $0x801074fb,0x4(%esp)
801047e2: 80
801047e3: 89 34 24 mov %esi,(%esp)
801047e6: 89 44 24 08 mov %eax,0x8(%esp)
801047ea: e8 21 d6 ff ff call 80101e10 <dirlink>
801047ef: 85 c0 test %eax,%eax
801047f1: 79 89 jns 8010477c <create+0xdc>
panic("create dots");
801047f3: c7 04 24 ef 74 10 80 movl $0x801074ef,(%esp)
801047fa: e8 61 bb ff ff call 80100360 <panic>
}
if(dirlink(dp, name, ip->inum) < 0)
panic("create: dirlink");
801047ff: c7 04 24 fe 74 10 80 movl $0x801074fe,(%esp)
80104806: e8 55 bb ff ff call 80100360 <panic>
iunlockput(ip);
return 0;
}
if((ip = ialloc(dp->dev, type)) == 0)
panic("create: ialloc");
8010480b: c7 04 24 e0 74 10 80 movl $0x801074e0,(%esp)
80104812: e8 49 bb ff ff call 80100360 <panic>
80104817: 89 f6 mov %esi,%esi
80104819: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80104820 <argfd.constprop.0>:
#include "fcntl.h"
// Fetch the nth word-sized system call argument as a file descriptor
// and return both the descriptor and the corresponding struct file.
static int
argfd(int n, int *pfd, struct file **pf)
80104820: 55 push %ebp
80104821: 89 e5 mov %esp,%ebp
80104823: 56 push %esi
80104824: 89 c6 mov %eax,%esi
80104826: 53 push %ebx
80104827: 89 d3 mov %edx,%ebx
80104829: 83 ec 20 sub $0x20,%esp
{
int fd;
struct file *f;
if(argint(n, &fd) < 0)
8010482c: 8d 45 f4 lea -0xc(%ebp),%eax
8010482f: 89 44 24 04 mov %eax,0x4(%esp)
80104833: c7 04 24 00 00 00 00 movl $0x0,(%esp)
8010483a: e8 f1 fc ff ff call 80104530 <argint>
8010483f: 85 c0 test %eax,%eax
80104841: 78 2d js 80104870 <argfd.constprop.0+0x50>
return -1;
if(fd < 0 || fd >= NOFILE || (f=myproc()->ofile[fd]) == 0)
80104843: 83 7d f4 0f cmpl $0xf,-0xc(%ebp)
80104847: 77 27 ja 80104870 <argfd.constprop.0+0x50>
80104849: e8 42 ee ff ff call 80103690 <myproc>
8010484e: 8b 55 f4 mov -0xc(%ebp),%edx
80104851: 8b 44 90 2c mov 0x2c(%eax,%edx,4),%eax
80104855: 85 c0 test %eax,%eax
80104857: 74 17 je 80104870 <argfd.constprop.0+0x50>
return -1;
if(pfd)
80104859: 85 f6 test %esi,%esi
8010485b: 74 02 je 8010485f <argfd.constprop.0+0x3f>
*pfd = fd;
8010485d: 89 16 mov %edx,(%esi)
if(pf)
8010485f: 85 db test %ebx,%ebx
80104861: 74 1d je 80104880 <argfd.constprop.0+0x60>
*pf = f;
80104863: 89 03 mov %eax,(%ebx)
return 0;
80104865: 31 c0 xor %eax,%eax
}
80104867: 83 c4 20 add $0x20,%esp
8010486a: 5b pop %ebx
8010486b: 5e pop %esi
8010486c: 5d pop %ebp
8010486d: c3 ret
8010486e: 66 90 xchg %ax,%ax
80104870: 83 c4 20 add $0x20,%esp
{
int fd;
struct file *f;
if(argint(n, &fd) < 0)
return -1;
80104873: b8 ff ff ff ff mov $0xffffffff,%eax
if(pfd)
*pfd = fd;
if(pf)
*pf = f;
return 0;
}
80104878: 5b pop %ebx
80104879: 5e pop %esi
8010487a: 5d pop %ebp
8010487b: c3 ret
8010487c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
return -1;
if(pfd)
*pfd = fd;
if(pf)
*pf = f;
return 0;
80104880: 31 c0 xor %eax,%eax
80104882: eb e3 jmp 80104867 <argfd.constprop.0+0x47>
80104884: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
8010488a: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
80104890 <sys_dup>:
return -1;
}
int
sys_dup(void)
{
80104890: 55 push %ebp
struct file *f;
int fd;
if(argfd(0, 0, &f) < 0)
80104891: 31 c0 xor %eax,%eax
return -1;
}
int
sys_dup(void)
{
80104893: 89 e5 mov %esp,%ebp
80104895: 53 push %ebx
80104896: 83 ec 24 sub $0x24,%esp
struct file *f;
int fd;
if(argfd(0, 0, &f) < 0)
80104899: 8d 55 f4 lea -0xc(%ebp),%edx
8010489c: e8 7f ff ff ff call 80104820 <argfd.constprop.0>
801048a1: 85 c0 test %eax,%eax
801048a3: 78 23 js 801048c8 <sys_dup+0x38>
return -1;
if((fd=fdalloc(f)) < 0)
801048a5: 8b 45 f4 mov -0xc(%ebp),%eax
801048a8: e8 b3 fd ff ff call 80104660 <fdalloc>
801048ad: 85 c0 test %eax,%eax
801048af: 89 c3 mov %eax,%ebx
801048b1: 78 15 js 801048c8 <sys_dup+0x38>
return -1;
filedup(f);
801048b3: 8b 45 f4 mov -0xc(%ebp),%eax
801048b6: 89 04 24 mov %eax,(%esp)
801048b9: e8 02 c5 ff ff call 80100dc0 <filedup>
return fd;
801048be: 89 d8 mov %ebx,%eax
}
801048c0: 83 c4 24 add $0x24,%esp
801048c3: 5b pop %ebx
801048c4: 5d pop %ebp
801048c5: c3 ret
801048c6: 66 90 xchg %ax,%ax
{
struct file *f;
int fd;
if(argfd(0, 0, &f) < 0)
return -1;
801048c8: b8 ff ff ff ff mov $0xffffffff,%eax
801048cd: eb f1 jmp 801048c0 <sys_dup+0x30>
801048cf: 90 nop
801048d0 <sys_read>:
return fd;
}
int
sys_read(void)
{
801048d0: 55 push %ebp
struct file *f;
int n;
char *p;
if(argfd(0, 0, &f) < 0 || argint(2, &n) < 0 || argptr(1, &p, n) < 0)
801048d1: 31 c0 xor %eax,%eax
return fd;
}
int
sys_read(void)
{
801048d3: 89 e5 mov %esp,%ebp
801048d5: 83 ec 28 sub $0x28,%esp
struct file *f;
int n;
char *p;
if(argfd(0, 0, &f) < 0 || argint(2, &n) < 0 || argptr(1, &p, n) < 0)
801048d8: 8d 55 ec lea -0x14(%ebp),%edx
801048db: e8 40 ff ff ff call 80104820 <argfd.constprop.0>
801048e0: 85 c0 test %eax,%eax
801048e2: 78 54 js 80104938 <sys_read+0x68>
801048e4: 8d 45 f0 lea -0x10(%ebp),%eax
801048e7: 89 44 24 04 mov %eax,0x4(%esp)
801048eb: c7 04 24 02 00 00 00 movl $0x2,(%esp)
801048f2: e8 39 fc ff ff call 80104530 <argint>
801048f7: 85 c0 test %eax,%eax
801048f9: 78 3d js 80104938 <sys_read+0x68>
801048fb: 8b 45 f0 mov -0x10(%ebp),%eax
801048fe: c7 04 24 01 00 00 00 movl $0x1,(%esp)
80104905: 89 44 24 08 mov %eax,0x8(%esp)
80104909: 8d 45 f4 lea -0xc(%ebp),%eax
8010490c: 89 44 24 04 mov %eax,0x4(%esp)
80104910: e8 4b fc ff ff call 80104560 <argptr>
80104915: 85 c0 test %eax,%eax
80104917: 78 1f js 80104938 <sys_read+0x68>
return -1;
return fileread(f, p, n);
80104919: 8b 45 f0 mov -0x10(%ebp),%eax
8010491c: 89 44 24 08 mov %eax,0x8(%esp)
80104920: 8b 45 f4 mov -0xc(%ebp),%eax
80104923: 89 44 24 04 mov %eax,0x4(%esp)
80104927: 8b 45 ec mov -0x14(%ebp),%eax
8010492a: 89 04 24 mov %eax,(%esp)
8010492d: e8 ee c5 ff ff call 80100f20 <fileread>
}
80104932: c9 leave
80104933: c3 ret
80104934: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
struct file *f;
int n;
char *p;
if(argfd(0, 0, &f) < 0 || argint(2, &n) < 0 || argptr(1, &p, n) < 0)
return -1;
80104938: b8 ff ff ff ff mov $0xffffffff,%eax
return fileread(f, p, n);
}
8010493d: c9 leave
8010493e: c3 ret
8010493f: 90 nop
80104940 <sys_write>:
int
sys_write(void)
{
80104940: 55 push %ebp
struct file *f;
int n;
char *p;
if(argfd(0, 0, &f) < 0 || argint(2, &n) < 0 || argptr(1, &p, n) < 0)
80104941: 31 c0 xor %eax,%eax
return fileread(f, p, n);
}
int
sys_write(void)
{
80104943: 89 e5 mov %esp,%ebp
80104945: 83 ec 28 sub $0x28,%esp
struct file *f;
int n;
char *p;
if(argfd(0, 0, &f) < 0 || argint(2, &n) < 0 || argptr(1, &p, n) < 0)
80104948: 8d 55 ec lea -0x14(%ebp),%edx
8010494b: e8 d0 fe ff ff call 80104820 <argfd.constprop.0>
80104950: 85 c0 test %eax,%eax
80104952: 78 54 js 801049a8 <sys_write+0x68>
80104954: 8d 45 f0 lea -0x10(%ebp),%eax
80104957: 89 44 24 04 mov %eax,0x4(%esp)
8010495b: c7 04 24 02 00 00 00 movl $0x2,(%esp)
80104962: e8 c9 fb ff ff call 80104530 <argint>
80104967: 85 c0 test %eax,%eax
80104969: 78 3d js 801049a8 <sys_write+0x68>
8010496b: 8b 45 f0 mov -0x10(%ebp),%eax
8010496e: c7 04 24 01 00 00 00 movl $0x1,(%esp)
80104975: 89 44 24 08 mov %eax,0x8(%esp)
80104979: 8d 45 f4 lea -0xc(%ebp),%eax
8010497c: 89 44 24 04 mov %eax,0x4(%esp)
80104980: e8 db fb ff ff call 80104560 <argptr>
80104985: 85 c0 test %eax,%eax
80104987: 78 1f js 801049a8 <sys_write+0x68>
return -1;
return filewrite(f, p, n);
80104989: 8b 45 f0 mov -0x10(%ebp),%eax
8010498c: 89 44 24 08 mov %eax,0x8(%esp)
80104990: 8b 45 f4 mov -0xc(%ebp),%eax
80104993: 89 44 24 04 mov %eax,0x4(%esp)
80104997: 8b 45 ec mov -0x14(%ebp),%eax
8010499a: 89 04 24 mov %eax,(%esp)
8010499d: e8 1e c6 ff ff call 80100fc0 <filewrite>
}
801049a2: c9 leave
801049a3: c3 ret
801049a4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
struct file *f;
int n;
char *p;
if(argfd(0, 0, &f) < 0 || argint(2, &n) < 0 || argptr(1, &p, n) < 0)
return -1;
801049a8: b8 ff ff ff ff mov $0xffffffff,%eax
return filewrite(f, p, n);
}
801049ad: c9 leave
801049ae: c3 ret
801049af: 90 nop
801049b0 <sys_close>:
int
sys_close(void)
{
801049b0: 55 push %ebp
801049b1: 89 e5 mov %esp,%ebp
801049b3: 83 ec 28 sub $0x28,%esp
int fd;
struct file *f;
if(argfd(0, &fd, &f) < 0)
801049b6: 8d 55 f4 lea -0xc(%ebp),%edx
801049b9: 8d 45 f0 lea -0x10(%ebp),%eax
801049bc: e8 5f fe ff ff call 80104820 <argfd.constprop.0>
801049c1: 85 c0 test %eax,%eax
801049c3: 78 23 js 801049e8 <sys_close+0x38>
return -1;
myproc()->ofile[fd] = 0;
801049c5: e8 c6 ec ff ff call 80103690 <myproc>
801049ca: 8b 55 f0 mov -0x10(%ebp),%edx
801049cd: c7 44 90 2c 00 00 00 movl $0x0,0x2c(%eax,%edx,4)
801049d4: 00
fileclose(f);
801049d5: 8b 45 f4 mov -0xc(%ebp),%eax
801049d8: 89 04 24 mov %eax,(%esp)
801049db: e8 30 c4 ff ff call 80100e10 <fileclose>
return 0;
801049e0: 31 c0 xor %eax,%eax
}
801049e2: c9 leave
801049e3: c3 ret
801049e4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
{
int fd;
struct file *f;
if(argfd(0, &fd, &f) < 0)
return -1;
801049e8: b8 ff ff ff ff mov $0xffffffff,%eax
myproc()->ofile[fd] = 0;
fileclose(f);
return 0;
}
801049ed: c9 leave
801049ee: c3 ret
801049ef: 90 nop
801049f0 <sys_fstat>:
int
sys_fstat(void)
{
801049f0: 55 push %ebp
struct file *f;
struct stat *st;
if(argfd(0, 0, &f) < 0 || argptr(1, (void*)&st, sizeof(*st)) < 0)
801049f1: 31 c0 xor %eax,%eax
return 0;
}
int
sys_fstat(void)
{
801049f3: 89 e5 mov %esp,%ebp
801049f5: 83 ec 28 sub $0x28,%esp
struct file *f;
struct stat *st;
if(argfd(0, 0, &f) < 0 || argptr(1, (void*)&st, sizeof(*st)) < 0)
801049f8: 8d 55 f0 lea -0x10(%ebp),%edx
801049fb: e8 20 fe ff ff call 80104820 <argfd.constprop.0>
80104a00: 85 c0 test %eax,%eax
80104a02: 78 34 js 80104a38 <sys_fstat+0x48>
80104a04: 8d 45 f4 lea -0xc(%ebp),%eax
80104a07: c7 44 24 08 14 00 00 movl $0x14,0x8(%esp)
80104a0e: 00
80104a0f: 89 44 24 04 mov %eax,0x4(%esp)
80104a13: c7 04 24 01 00 00 00 movl $0x1,(%esp)
80104a1a: e8 41 fb ff ff call 80104560 <argptr>
80104a1f: 85 c0 test %eax,%eax
80104a21: 78 15 js 80104a38 <sys_fstat+0x48>
return -1;
return filestat(f, st);
80104a23: 8b 45 f4 mov -0xc(%ebp),%eax
80104a26: 89 44 24 04 mov %eax,0x4(%esp)
80104a2a: 8b 45 f0 mov -0x10(%ebp),%eax
80104a2d: 89 04 24 mov %eax,(%esp)
80104a30: e8 9b c4 ff ff call 80100ed0 <filestat>
}
80104a35: c9 leave
80104a36: c3 ret
80104a37: 90 nop
{
struct file *f;
struct stat *st;
if(argfd(0, 0, &f) < 0 || argptr(1, (void*)&st, sizeof(*st)) < 0)
return -1;
80104a38: b8 ff ff ff ff mov $0xffffffff,%eax
return filestat(f, st);
}
80104a3d: c9 leave
80104a3e: c3 ret
80104a3f: 90 nop
80104a40 <sys_link>:
// Create the path new as a link to the same inode as old.
int
sys_link(void)
{
80104a40: 55 push %ebp
80104a41: 89 e5 mov %esp,%ebp
80104a43: 57 push %edi
80104a44: 56 push %esi
80104a45: 53 push %ebx
80104a46: 83 ec 3c sub $0x3c,%esp
char name[DIRSIZ], *new, *old;
struct inode *dp, *ip;
if(argstr(0, &old) < 0 || argstr(1, &new) < 0)
80104a49: 8d 45 d4 lea -0x2c(%ebp),%eax
80104a4c: 89 44 24 04 mov %eax,0x4(%esp)
80104a50: c7 04 24 00 00 00 00 movl $0x0,(%esp)
80104a57: e8 34 fb ff ff call 80104590 <argstr>
80104a5c: 85 c0 test %eax,%eax
80104a5e: 0f 88 e6 00 00 00 js 80104b4a <sys_link+0x10a>
80104a64: 8d 45 d0 lea -0x30(%ebp),%eax
80104a67: 89 44 24 04 mov %eax,0x4(%esp)
80104a6b: c7 04 24 01 00 00 00 movl $0x1,(%esp)
80104a72: e8 19 fb ff ff call 80104590 <argstr>
80104a77: 85 c0 test %eax,%eax
80104a79: 0f 88 cb 00 00 00 js 80104b4a <sys_link+0x10a>
return -1;
begin_op();
80104a7f: e8 7c e0 ff ff call 80102b00 <begin_op>
if((ip = namei(old)) == 0){
80104a84: 8b 45 d4 mov -0x2c(%ebp),%eax
80104a87: 89 04 24 mov %eax,(%esp)
80104a8a: e8 61 d4 ff ff call 80101ef0 <namei>
80104a8f: 85 c0 test %eax,%eax
80104a91: 89 c3 mov %eax,%ebx
80104a93: 0f 84 ac 00 00 00 je 80104b45 <sys_link+0x105>
end_op();
return -1;
}
ilock(ip);
80104a99: 89 04 24 mov %eax,(%esp)
80104a9c: e8 ff cb ff ff call 801016a0 <ilock>
if(ip->type == T_DIR){
80104aa1: 66 83 7b 50 01 cmpw $0x1,0x50(%ebx)
80104aa6: 0f 84 91 00 00 00 je 80104b3d <sys_link+0xfd>
iunlockput(ip);
end_op();
return -1;
}
ip->nlink++;
80104aac: 66 83 43 56 01 addw $0x1,0x56(%ebx)
iupdate(ip);
iunlock(ip);
if((dp = nameiparent(new, name)) == 0)
80104ab1: 8d 7d da lea -0x26(%ebp),%edi
end_op();
return -1;
}
ip->nlink++;
iupdate(ip);
80104ab4: 89 1c 24 mov %ebx,(%esp)
80104ab7: e8 24 cb ff ff call 801015e0 <iupdate>
iunlock(ip);
80104abc: 89 1c 24 mov %ebx,(%esp)
80104abf: e8 bc cc ff ff call 80101780 <iunlock>
if((dp = nameiparent(new, name)) == 0)
80104ac4: 8b 45 d0 mov -0x30(%ebp),%eax
80104ac7: 89 7c 24 04 mov %edi,0x4(%esp)
80104acb: 89 04 24 mov %eax,(%esp)
80104ace: e8 3d d4 ff ff call 80101f10 <nameiparent>
80104ad3: 85 c0 test %eax,%eax
80104ad5: 89 c6 mov %eax,%esi
80104ad7: 74 4f je 80104b28 <sys_link+0xe8>
goto bad;
ilock(dp);
80104ad9: 89 04 24 mov %eax,(%esp)
80104adc: e8 bf cb ff ff call 801016a0 <ilock>
if(dp->dev != ip->dev || dirlink(dp, name, ip->inum) < 0){
80104ae1: 8b 03 mov (%ebx),%eax
80104ae3: 39 06 cmp %eax,(%esi)
80104ae5: 75 39 jne 80104b20 <sys_link+0xe0>
80104ae7: 8b 43 04 mov 0x4(%ebx),%eax
80104aea: 89 7c 24 04 mov %edi,0x4(%esp)
80104aee: 89 34 24 mov %esi,(%esp)
80104af1: 89 44 24 08 mov %eax,0x8(%esp)
80104af5: e8 16 d3 ff ff call 80101e10 <dirlink>
80104afa: 85 c0 test %eax,%eax
80104afc: 78 22 js 80104b20 <sys_link+0xe0>
iunlockput(dp);
goto bad;
}
iunlockput(dp);
80104afe: 89 34 24 mov %esi,(%esp)
80104b01: e8 fa cd ff ff call 80101900 <iunlockput>
iput(ip);
80104b06: 89 1c 24 mov %ebx,(%esp)
80104b09: e8 b2 cc ff ff call 801017c0 <iput>
end_op();
80104b0e: e8 5d e0 ff ff call 80102b70 <end_op>
ip->nlink--;
iupdate(ip);
iunlockput(ip);
end_op();
return -1;
}
80104b13: 83 c4 3c add $0x3c,%esp
iunlockput(dp);
iput(ip);
end_op();
return 0;
80104b16: 31 c0 xor %eax,%eax
ip->nlink--;
iupdate(ip);
iunlockput(ip);
end_op();
return -1;
}
80104b18: 5b pop %ebx
80104b19: 5e pop %esi
80104b1a: 5f pop %edi
80104b1b: 5d pop %ebp
80104b1c: c3 ret
80104b1d: 8d 76 00 lea 0x0(%esi),%esi
if((dp = nameiparent(new, name)) == 0)
goto bad;
ilock(dp);
if(dp->dev != ip->dev || dirlink(dp, name, ip->inum) < 0){
iunlockput(dp);
80104b20: 89 34 24 mov %esi,(%esp)
80104b23: e8 d8 cd ff ff call 80101900 <iunlockput>
end_op();
return 0;
bad:
ilock(ip);
80104b28: 89 1c 24 mov %ebx,(%esp)
80104b2b: e8 70 cb ff ff call 801016a0 <ilock>
ip->nlink--;
80104b30: 66 83 6b 56 01 subw $0x1,0x56(%ebx)
iupdate(ip);
80104b35: 89 1c 24 mov %ebx,(%esp)
80104b38: e8 a3 ca ff ff call 801015e0 <iupdate>
iunlockput(ip);
80104b3d: 89 1c 24 mov %ebx,(%esp)
80104b40: e8 bb cd ff ff call 80101900 <iunlockput>
end_op();
80104b45: e8 26 e0 ff ff call 80102b70 <end_op>
return -1;
}
80104b4a: 83 c4 3c add $0x3c,%esp
ilock(ip);
ip->nlink--;
iupdate(ip);
iunlockput(ip);
end_op();
return -1;
80104b4d: b8 ff ff ff ff mov $0xffffffff,%eax
}
80104b52: 5b pop %ebx
80104b53: 5e pop %esi
80104b54: 5f pop %edi
80104b55: 5d pop %ebp
80104b56: c3 ret
80104b57: 89 f6 mov %esi,%esi
80104b59: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80104b60 <sys_unlink>:
}
//PAGEBREAK!
int
sys_unlink(void)
{
80104b60: 55 push %ebp
80104b61: 89 e5 mov %esp,%ebp
80104b63: 57 push %edi
80104b64: 56 push %esi
80104b65: 53 push %ebx
80104b66: 83 ec 5c sub $0x5c,%esp
struct inode *ip, *dp;
struct dirent de;
char name[DIRSIZ], *path;
uint off;
if(argstr(0, &path) < 0)
80104b69: 8d 45 c0 lea -0x40(%ebp),%eax
80104b6c: 89 44 24 04 mov %eax,0x4(%esp)
80104b70: c7 04 24 00 00 00 00 movl $0x0,(%esp)
80104b77: e8 14 fa ff ff call 80104590 <argstr>
80104b7c: 85 c0 test %eax,%eax
80104b7e: 0f 88 76 01 00 00 js 80104cfa <sys_unlink+0x19a>
return -1;
begin_op();
80104b84: e8 77 df ff ff call 80102b00 <begin_op>
if((dp = nameiparent(path, name)) == 0){
80104b89: 8b 45 c0 mov -0x40(%ebp),%eax
80104b8c: 8d 5d ca lea -0x36(%ebp),%ebx
80104b8f: 89 5c 24 04 mov %ebx,0x4(%esp)
80104b93: 89 04 24 mov %eax,(%esp)
80104b96: e8 75 d3 ff ff call 80101f10 <nameiparent>
80104b9b: 85 c0 test %eax,%eax
80104b9d: 89 45 b4 mov %eax,-0x4c(%ebp)
80104ba0: 0f 84 4f 01 00 00 je 80104cf5 <sys_unlink+0x195>
end_op();
return -1;
}
ilock(dp);
80104ba6: 8b 75 b4 mov -0x4c(%ebp),%esi
80104ba9: 89 34 24 mov %esi,(%esp)
80104bac: e8 ef ca ff ff call 801016a0 <ilock>
// Cannot unlink "." or "..".
if(namecmp(name, ".") == 0 || namecmp(name, "..") == 0)
80104bb1: c7 44 24 04 fc 74 10 movl $0x801074fc,0x4(%esp)
80104bb8: 80
80104bb9: 89 1c 24 mov %ebx,(%esp)
80104bbc: e8 bf cf ff ff call 80101b80 <namecmp>
80104bc1: 85 c0 test %eax,%eax
80104bc3: 0f 84 21 01 00 00 je 80104cea <sys_unlink+0x18a>
80104bc9: c7 44 24 04 fb 74 10 movl $0x801074fb,0x4(%esp)
80104bd0: 80
80104bd1: 89 1c 24 mov %ebx,(%esp)
80104bd4: e8 a7 cf ff ff call 80101b80 <namecmp>
80104bd9: 85 c0 test %eax,%eax
80104bdb: 0f 84 09 01 00 00 je 80104cea <sys_unlink+0x18a>
goto bad;
if((ip = dirlookup(dp, name, &off)) == 0)
80104be1: 8d 45 c4 lea -0x3c(%ebp),%eax
80104be4: 89 5c 24 04 mov %ebx,0x4(%esp)
80104be8: 89 44 24 08 mov %eax,0x8(%esp)
80104bec: 89 34 24 mov %esi,(%esp)
80104bef: e8 bc cf ff ff call 80101bb0 <dirlookup>
80104bf4: 85 c0 test %eax,%eax
80104bf6: 89 c3 mov %eax,%ebx
80104bf8: 0f 84 ec 00 00 00 je 80104cea <sys_unlink+0x18a>
goto bad;
ilock(ip);
80104bfe: 89 04 24 mov %eax,(%esp)
80104c01: e8 9a ca ff ff call 801016a0 <ilock>
if(ip->nlink < 1)
80104c06: 66 83 7b 56 00 cmpw $0x0,0x56(%ebx)
80104c0b: 0f 8e 24 01 00 00 jle 80104d35 <sys_unlink+0x1d5>
panic("unlink: nlink < 1");
if(ip->type == T_DIR && !isdirempty(ip)){
80104c11: 66 83 7b 50 01 cmpw $0x1,0x50(%ebx)
80104c16: 8d 75 d8 lea -0x28(%ebp),%esi
80104c19: 74 7d je 80104c98 <sys_unlink+0x138>
iunlockput(ip);
goto bad;
}
memset(&de, 0, sizeof(de));
80104c1b: c7 44 24 08 10 00 00 movl $0x10,0x8(%esp)
80104c22: 00
80104c23: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
80104c2a: 00
80104c2b: 89 34 24 mov %esi,(%esp)
80104c2e: e8 3d f6 ff ff call 80104270 <memset>
if(writei(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
80104c33: 8b 45 c4 mov -0x3c(%ebp),%eax
80104c36: c7 44 24 0c 10 00 00 movl $0x10,0xc(%esp)
80104c3d: 00
80104c3e: 89 74 24 04 mov %esi,0x4(%esp)
80104c42: 89 44 24 08 mov %eax,0x8(%esp)
80104c46: 8b 45 b4 mov -0x4c(%ebp),%eax
80104c49: 89 04 24 mov %eax,(%esp)
80104c4c: e8 ff cd ff ff call 80101a50 <writei>
80104c51: 83 f8 10 cmp $0x10,%eax
80104c54: 0f 85 cf 00 00 00 jne 80104d29 <sys_unlink+0x1c9>
panic("unlink: writei");
if(ip->type == T_DIR){
80104c5a: 66 83 7b 50 01 cmpw $0x1,0x50(%ebx)
80104c5f: 0f 84 a3 00 00 00 je 80104d08 <sys_unlink+0x1a8>
dp->nlink--;
iupdate(dp);
}
iunlockput(dp);
80104c65: 8b 45 b4 mov -0x4c(%ebp),%eax
80104c68: 89 04 24 mov %eax,(%esp)
80104c6b: e8 90 cc ff ff call 80101900 <iunlockput>
ip->nlink--;
80104c70: 66 83 6b 56 01 subw $0x1,0x56(%ebx)
iupdate(ip);
80104c75: 89 1c 24 mov %ebx,(%esp)
80104c78: e8 63 c9 ff ff call 801015e0 <iupdate>
iunlockput(ip);
80104c7d: 89 1c 24 mov %ebx,(%esp)
80104c80: e8 7b cc ff ff call 80101900 <iunlockput>
end_op();
80104c85: e8 e6 de ff ff call 80102b70 <end_op>
bad:
iunlockput(dp);
end_op();
return -1;
}
80104c8a: 83 c4 5c add $0x5c,%esp
iupdate(ip);
iunlockput(ip);
end_op();
return 0;
80104c8d: 31 c0 xor %eax,%eax
bad:
iunlockput(dp);
end_op();
return -1;
}
80104c8f: 5b pop %ebx
80104c90: 5e pop %esi
80104c91: 5f pop %edi
80104c92: 5d pop %ebp
80104c93: c3 ret
80104c94: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
isdirempty(struct inode *dp)
{
int off;
struct dirent de;
for(off=2*sizeof(de); off<dp->size; off+=sizeof(de)){
80104c98: 83 7b 58 20 cmpl $0x20,0x58(%ebx)
80104c9c: 0f 86 79 ff ff ff jbe 80104c1b <sys_unlink+0xbb>
80104ca2: bf 20 00 00 00 mov $0x20,%edi
80104ca7: eb 15 jmp 80104cbe <sys_unlink+0x15e>
80104ca9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80104cb0: 8d 57 10 lea 0x10(%edi),%edx
80104cb3: 3b 53 58 cmp 0x58(%ebx),%edx
80104cb6: 0f 83 5f ff ff ff jae 80104c1b <sys_unlink+0xbb>
80104cbc: 89 d7 mov %edx,%edi
if(readi(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
80104cbe: c7 44 24 0c 10 00 00 movl $0x10,0xc(%esp)
80104cc5: 00
80104cc6: 89 7c 24 08 mov %edi,0x8(%esp)
80104cca: 89 74 24 04 mov %esi,0x4(%esp)
80104cce: 89 1c 24 mov %ebx,(%esp)
80104cd1: e8 7a cc ff ff call 80101950 <readi>
80104cd6: 83 f8 10 cmp $0x10,%eax
80104cd9: 75 42 jne 80104d1d <sys_unlink+0x1bd>
panic("isdirempty: readi");
if(de.inum != 0)
80104cdb: 66 83 7d d8 00 cmpw $0x0,-0x28(%ebp)
80104ce0: 74 ce je 80104cb0 <sys_unlink+0x150>
ilock(ip);
if(ip->nlink < 1)
panic("unlink: nlink < 1");
if(ip->type == T_DIR && !isdirempty(ip)){
iunlockput(ip);
80104ce2: 89 1c 24 mov %ebx,(%esp)
80104ce5: e8 16 cc ff ff call 80101900 <iunlockput>
end_op();
return 0;
bad:
iunlockput(dp);
80104cea: 8b 45 b4 mov -0x4c(%ebp),%eax
80104ced: 89 04 24 mov %eax,(%esp)
80104cf0: e8 0b cc ff ff call 80101900 <iunlockput>
end_op();
80104cf5: e8 76 de ff ff call 80102b70 <end_op>
return -1;
}
80104cfa: 83 c4 5c add $0x5c,%esp
return 0;
bad:
iunlockput(dp);
end_op();
return -1;
80104cfd: b8 ff ff ff ff mov $0xffffffff,%eax
}
80104d02: 5b pop %ebx
80104d03: 5e pop %esi
80104d04: 5f pop %edi
80104d05: 5d pop %ebp
80104d06: c3 ret
80104d07: 90 nop
memset(&de, 0, sizeof(de));
if(writei(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
panic("unlink: writei");
if(ip->type == T_DIR){
dp->nlink--;
80104d08: 8b 45 b4 mov -0x4c(%ebp),%eax
80104d0b: 66 83 68 56 01 subw $0x1,0x56(%eax)
iupdate(dp);
80104d10: 89 04 24 mov %eax,(%esp)
80104d13: e8 c8 c8 ff ff call 801015e0 <iupdate>
80104d18: e9 48 ff ff ff jmp 80104c65 <sys_unlink+0x105>
int off;
struct dirent de;
for(off=2*sizeof(de); off<dp->size; off+=sizeof(de)){
if(readi(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
panic("isdirempty: readi");
80104d1d: c7 04 24 20 75 10 80 movl $0x80107520,(%esp)
80104d24: e8 37 b6 ff ff call 80100360 <panic>
goto bad;
}
memset(&de, 0, sizeof(de));
if(writei(dp, (char*)&de, off, sizeof(de)) != sizeof(de))
panic("unlink: writei");
80104d29: c7 04 24 32 75 10 80 movl $0x80107532,(%esp)
80104d30: e8 2b b6 ff ff call 80100360 <panic>
if((ip = dirlookup(dp, name, &off)) == 0)
goto bad;
ilock(ip);
if(ip->nlink < 1)
panic("unlink: nlink < 1");
80104d35: c7 04 24 0e 75 10 80 movl $0x8010750e,(%esp)
80104d3c: e8 1f b6 ff ff call 80100360 <panic>
80104d41: eb 0d jmp 80104d50 <sys_open>
80104d43: 90 nop
80104d44: 90 nop
80104d45: 90 nop
80104d46: 90 nop
80104d47: 90 nop
80104d48: 90 nop
80104d49: 90 nop
80104d4a: 90 nop
80104d4b: 90 nop
80104d4c: 90 nop
80104d4d: 90 nop
80104d4e: 90 nop
80104d4f: 90 nop
80104d50 <sys_open>:
return ip;
}
int
sys_open(void)
{
80104d50: 55 push %ebp
80104d51: 89 e5 mov %esp,%ebp
80104d53: 57 push %edi
80104d54: 56 push %esi
80104d55: 53 push %ebx
80104d56: 83 ec 2c sub $0x2c,%esp
char *path;
int fd, omode;
struct file *f;
struct inode *ip;
if(argstr(0, &path) < 0 || argint(1, &omode) < 0)
80104d59: 8d 45 e0 lea -0x20(%ebp),%eax
80104d5c: 89 44 24 04 mov %eax,0x4(%esp)
80104d60: c7 04 24 00 00 00 00 movl $0x0,(%esp)
80104d67: e8 24 f8 ff ff call 80104590 <argstr>
80104d6c: 85 c0 test %eax,%eax
80104d6e: 0f 88 d1 00 00 00 js 80104e45 <sys_open+0xf5>
80104d74: 8d 45 e4 lea -0x1c(%ebp),%eax
80104d77: 89 44 24 04 mov %eax,0x4(%esp)
80104d7b: c7 04 24 01 00 00 00 movl $0x1,(%esp)
80104d82: e8 a9 f7 ff ff call 80104530 <argint>
80104d87: 85 c0 test %eax,%eax
80104d89: 0f 88 b6 00 00 00 js 80104e45 <sys_open+0xf5>
return -1;
begin_op();
80104d8f: e8 6c dd ff ff call 80102b00 <begin_op>
if(omode & O_CREATE){
80104d94: f6 45 e5 02 testb $0x2,-0x1b(%ebp)
80104d98: 0f 85 82 00 00 00 jne 80104e20 <sys_open+0xd0>
if(ip == 0){
end_op();
return -1;
}
} else {
if((ip = namei(path)) == 0){
80104d9e: 8b 45 e0 mov -0x20(%ebp),%eax
80104da1: 89 04 24 mov %eax,(%esp)
80104da4: e8 47 d1 ff ff call 80101ef0 <namei>
80104da9: 85 c0 test %eax,%eax
80104dab: 89 c6 mov %eax,%esi
80104dad: 0f 84 8d 00 00 00 je 80104e40 <sys_open+0xf0>
end_op();
return -1;
}
ilock(ip);
80104db3: 89 04 24 mov %eax,(%esp)
80104db6: e8 e5 c8 ff ff call 801016a0 <ilock>
if(ip->type == T_DIR && omode != O_RDONLY){
80104dbb: 66 83 7e 50 01 cmpw $0x1,0x50(%esi)
80104dc0: 0f 84 92 00 00 00 je 80104e58 <sys_open+0x108>
end_op();
return -1;
}
}
if((f = filealloc()) == 0 || (fd = fdalloc(f)) < 0){
80104dc6: e8 85 bf ff ff call 80100d50 <filealloc>
80104dcb: 85 c0 test %eax,%eax
80104dcd: 89 c3 mov %eax,%ebx
80104dcf: 0f 84 93 00 00 00 je 80104e68 <sys_open+0x118>
80104dd5: e8 86 f8 ff ff call 80104660 <fdalloc>
80104dda: 85 c0 test %eax,%eax
80104ddc: 89 c7 mov %eax,%edi
80104dde: 0f 88 94 00 00 00 js 80104e78 <sys_open+0x128>
fileclose(f);
iunlockput(ip);
end_op();
return -1;
}
iunlock(ip);
80104de4: 89 34 24 mov %esi,(%esp)
80104de7: e8 94 c9 ff ff call 80101780 <iunlock>
end_op();
80104dec: e8 7f dd ff ff call 80102b70 <end_op>
f->type = FD_INODE;
80104df1: c7 03 02 00 00 00 movl $0x2,(%ebx)
f->ip = ip;
f->off = 0;
f->readable = !(omode & O_WRONLY);
80104df7: 8b 45 e4 mov -0x1c(%ebp),%eax
}
iunlock(ip);
end_op();
f->type = FD_INODE;
f->ip = ip;
80104dfa: 89 73 10 mov %esi,0x10(%ebx)
f->off = 0;
80104dfd: c7 43 14 00 00 00 00 movl $0x0,0x14(%ebx)
f->readable = !(omode & O_WRONLY);
80104e04: 89 c2 mov %eax,%edx
80104e06: 83 e2 01 and $0x1,%edx
80104e09: 83 f2 01 xor $0x1,%edx
f->writable = (omode & O_WRONLY) || (omode & O_RDWR);
80104e0c: a8 03 test $0x3,%al
end_op();
f->type = FD_INODE;
f->ip = ip;
f->off = 0;
f->readable = !(omode & O_WRONLY);
80104e0e: 88 53 08 mov %dl,0x8(%ebx)
f->writable = (omode & O_WRONLY) || (omode & O_RDWR);
return fd;
80104e11: 89 f8 mov %edi,%eax
f->type = FD_INODE;
f->ip = ip;
f->off = 0;
f->readable = !(omode & O_WRONLY);
f->writable = (omode & O_WRONLY) || (omode & O_RDWR);
80104e13: 0f 95 43 09 setne 0x9(%ebx)
return fd;
}
80104e17: 83 c4 2c add $0x2c,%esp
80104e1a: 5b pop %ebx
80104e1b: 5e pop %esi
80104e1c: 5f pop %edi
80104e1d: 5d pop %ebp
80104e1e: c3 ret
80104e1f: 90 nop
return -1;
begin_op();
if(omode & O_CREATE){
ip = create(path, T_FILE, 0, 0);
80104e20: 8b 45 e0 mov -0x20(%ebp),%eax
80104e23: 31 c9 xor %ecx,%ecx
80104e25: ba 02 00 00 00 mov $0x2,%edx
80104e2a: c7 04 24 00 00 00 00 movl $0x0,(%esp)
80104e31: e8 6a f8 ff ff call 801046a0 <create>
if(ip == 0){
80104e36: 85 c0 test %eax,%eax
return -1;
begin_op();
if(omode & O_CREATE){
ip = create(path, T_FILE, 0, 0);
80104e38: 89 c6 mov %eax,%esi
if(ip == 0){
80104e3a: 75 8a jne 80104dc6 <sys_open+0x76>
80104e3c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
if((f = filealloc()) == 0 || (fd = fdalloc(f)) < 0){
if(f)
fileclose(f);
iunlockput(ip);
end_op();
80104e40: e8 2b dd ff ff call 80102b70 <end_op>
f->ip = ip;
f->off = 0;
f->readable = !(omode & O_WRONLY);
f->writable = (omode & O_WRONLY) || (omode & O_RDWR);
return fd;
}
80104e45: 83 c4 2c add $0x2c,%esp
if((f = filealloc()) == 0 || (fd = fdalloc(f)) < 0){
if(f)
fileclose(f);
iunlockput(ip);
end_op();
return -1;
80104e48: b8 ff ff ff ff mov $0xffffffff,%eax
f->ip = ip;
f->off = 0;
f->readable = !(omode & O_WRONLY);
f->writable = (omode & O_WRONLY) || (omode & O_RDWR);
return fd;
}
80104e4d: 5b pop %ebx
80104e4e: 5e pop %esi
80104e4f: 5f pop %edi
80104e50: 5d pop %ebp
80104e51: c3 ret
80104e52: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
if((ip = namei(path)) == 0){
end_op();
return -1;
}
ilock(ip);
if(ip->type == T_DIR && omode != O_RDONLY){
80104e58: 8b 45 e4 mov -0x1c(%ebp),%eax
80104e5b: 85 c0 test %eax,%eax
80104e5d: 0f 84 63 ff ff ff je 80104dc6 <sys_open+0x76>
80104e63: 90 nop
80104e64: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
}
if((f = filealloc()) == 0 || (fd = fdalloc(f)) < 0){
if(f)
fileclose(f);
iunlockput(ip);
80104e68: 89 34 24 mov %esi,(%esp)
80104e6b: e8 90 ca ff ff call 80101900 <iunlockput>
80104e70: eb ce jmp 80104e40 <sys_open+0xf0>
80104e72: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
}
}
if((f = filealloc()) == 0 || (fd = fdalloc(f)) < 0){
if(f)
fileclose(f);
80104e78: 89 1c 24 mov %ebx,(%esp)
80104e7b: e8 90 bf ff ff call 80100e10 <fileclose>
80104e80: eb e6 jmp 80104e68 <sys_open+0x118>
80104e82: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80104e89: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80104e90 <sys_mkdir>:
return fd;
}
int
sys_mkdir(void)
{
80104e90: 55 push %ebp
80104e91: 89 e5 mov %esp,%ebp
80104e93: 83 ec 28 sub $0x28,%esp
char *path;
struct inode *ip;
begin_op();
80104e96: e8 65 dc ff ff call 80102b00 <begin_op>
if(argstr(0, &path) < 0 || (ip = create(path, T_DIR, 0, 0)) == 0){
80104e9b: 8d 45 f4 lea -0xc(%ebp),%eax
80104e9e: 89 44 24 04 mov %eax,0x4(%esp)
80104ea2: c7 04 24 00 00 00 00 movl $0x0,(%esp)
80104ea9: e8 e2 f6 ff ff call 80104590 <argstr>
80104eae: 85 c0 test %eax,%eax
80104eb0: 78 2e js 80104ee0 <sys_mkdir+0x50>
80104eb2: 8b 45 f4 mov -0xc(%ebp),%eax
80104eb5: 31 c9 xor %ecx,%ecx
80104eb7: ba 01 00 00 00 mov $0x1,%edx
80104ebc: c7 04 24 00 00 00 00 movl $0x0,(%esp)
80104ec3: e8 d8 f7 ff ff call 801046a0 <create>
80104ec8: 85 c0 test %eax,%eax
80104eca: 74 14 je 80104ee0 <sys_mkdir+0x50>
end_op();
return -1;
}
iunlockput(ip);
80104ecc: 89 04 24 mov %eax,(%esp)
80104ecf: e8 2c ca ff ff call 80101900 <iunlockput>
end_op();
80104ed4: e8 97 dc ff ff call 80102b70 <end_op>
return 0;
80104ed9: 31 c0 xor %eax,%eax
}
80104edb: c9 leave
80104edc: c3 ret
80104edd: 8d 76 00 lea 0x0(%esi),%esi
char *path;
struct inode *ip;
begin_op();
if(argstr(0, &path) < 0 || (ip = create(path, T_DIR, 0, 0)) == 0){
end_op();
80104ee0: e8 8b dc ff ff call 80102b70 <end_op>
return -1;
80104ee5: b8 ff ff ff ff mov $0xffffffff,%eax
}
iunlockput(ip);
end_op();
return 0;
}
80104eea: c9 leave
80104eeb: c3 ret
80104eec: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80104ef0 <sys_mknod>:
int
sys_mknod(void)
{
80104ef0: 55 push %ebp
80104ef1: 89 e5 mov %esp,%ebp
80104ef3: 83 ec 28 sub $0x28,%esp
struct inode *ip;
char *path;
int major, minor;
begin_op();
80104ef6: e8 05 dc ff ff call 80102b00 <begin_op>
if((argstr(0, &path)) < 0 ||
80104efb: 8d 45 ec lea -0x14(%ebp),%eax
80104efe: 89 44 24 04 mov %eax,0x4(%esp)
80104f02: c7 04 24 00 00 00 00 movl $0x0,(%esp)
80104f09: e8 82 f6 ff ff call 80104590 <argstr>
80104f0e: 85 c0 test %eax,%eax
80104f10: 78 5e js 80104f70 <sys_mknod+0x80>
argint(1, &major) < 0 ||
80104f12: 8d 45 f0 lea -0x10(%ebp),%eax
80104f15: 89 44 24 04 mov %eax,0x4(%esp)
80104f19: c7 04 24 01 00 00 00 movl $0x1,(%esp)
80104f20: e8 0b f6 ff ff call 80104530 <argint>
struct inode *ip;
char *path;
int major, minor;
begin_op();
if((argstr(0, &path)) < 0 ||
80104f25: 85 c0 test %eax,%eax
80104f27: 78 47 js 80104f70 <sys_mknod+0x80>
argint(1, &major) < 0 ||
argint(2, &minor) < 0 ||
80104f29: 8d 45 f4 lea -0xc(%ebp),%eax
80104f2c: 89 44 24 04 mov %eax,0x4(%esp)
80104f30: c7 04 24 02 00 00 00 movl $0x2,(%esp)
80104f37: e8 f4 f5 ff ff call 80104530 <argint>
char *path;
int major, minor;
begin_op();
if((argstr(0, &path)) < 0 ||
argint(1, &major) < 0 ||
80104f3c: 85 c0 test %eax,%eax
80104f3e: 78 30 js 80104f70 <sys_mknod+0x80>
argint(2, &minor) < 0 ||
(ip = create(path, T_DEV, major, minor)) == 0){
80104f40: 0f bf 45 f4 movswl -0xc(%ebp),%eax
int major, minor;
begin_op();
if((argstr(0, &path)) < 0 ||
argint(1, &major) < 0 ||
argint(2, &minor) < 0 ||
80104f44: ba 03 00 00 00 mov $0x3,%edx
(ip = create(path, T_DEV, major, minor)) == 0){
80104f49: 0f bf 4d f0 movswl -0x10(%ebp),%ecx
80104f4d: 89 04 24 mov %eax,(%esp)
int major, minor;
begin_op();
if((argstr(0, &path)) < 0 ||
argint(1, &major) < 0 ||
argint(2, &minor) < 0 ||
80104f50: 8b 45 ec mov -0x14(%ebp),%eax
80104f53: e8 48 f7 ff ff call 801046a0 <create>
80104f58: 85 c0 test %eax,%eax
80104f5a: 74 14 je 80104f70 <sys_mknod+0x80>
(ip = create(path, T_DEV, major, minor)) == 0){
end_op();
return -1;
}
iunlockput(ip);
80104f5c: 89 04 24 mov %eax,(%esp)
80104f5f: e8 9c c9 ff ff call 80101900 <iunlockput>
end_op();
80104f64: e8 07 dc ff ff call 80102b70 <end_op>
return 0;
80104f69: 31 c0 xor %eax,%eax
}
80104f6b: c9 leave
80104f6c: c3 ret
80104f6d: 8d 76 00 lea 0x0(%esi),%esi
begin_op();
if((argstr(0, &path)) < 0 ||
argint(1, &major) < 0 ||
argint(2, &minor) < 0 ||
(ip = create(path, T_DEV, major, minor)) == 0){
end_op();
80104f70: e8 fb db ff ff call 80102b70 <end_op>
return -1;
80104f75: b8 ff ff ff ff mov $0xffffffff,%eax
}
iunlockput(ip);
end_op();
return 0;
}
80104f7a: c9 leave
80104f7b: c3 ret
80104f7c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80104f80 <sys_chdir>:
int
sys_chdir(void)
{
80104f80: 55 push %ebp
80104f81: 89 e5 mov %esp,%ebp
80104f83: 56 push %esi
80104f84: 53 push %ebx
80104f85: 83 ec 20 sub $0x20,%esp
char *path;
struct inode *ip;
struct proc *curproc = myproc();
80104f88: e8 03 e7 ff ff call 80103690 <myproc>
80104f8d: 89 c6 mov %eax,%esi
begin_op();
80104f8f: e8 6c db ff ff call 80102b00 <begin_op>
if(argstr(0, &path) < 0 || (ip = namei(path)) == 0){
80104f94: 8d 45 f4 lea -0xc(%ebp),%eax
80104f97: 89 44 24 04 mov %eax,0x4(%esp)
80104f9b: c7 04 24 00 00 00 00 movl $0x0,(%esp)
80104fa2: e8 e9 f5 ff ff call 80104590 <argstr>
80104fa7: 85 c0 test %eax,%eax
80104fa9: 78 4a js 80104ff5 <sys_chdir+0x75>
80104fab: 8b 45 f4 mov -0xc(%ebp),%eax
80104fae: 89 04 24 mov %eax,(%esp)
80104fb1: e8 3a cf ff ff call 80101ef0 <namei>
80104fb6: 85 c0 test %eax,%eax
80104fb8: 89 c3 mov %eax,%ebx
80104fba: 74 39 je 80104ff5 <sys_chdir+0x75>
end_op();
return -1;
}
ilock(ip);
80104fbc: 89 04 24 mov %eax,(%esp)
80104fbf: e8 dc c6 ff ff call 801016a0 <ilock>
if(ip->type != T_DIR){
80104fc4: 66 83 7b 50 01 cmpw $0x1,0x50(%ebx)
iunlockput(ip);
80104fc9: 89 1c 24 mov %ebx,(%esp)
if(argstr(0, &path) < 0 || (ip = namei(path)) == 0){
end_op();
return -1;
}
ilock(ip);
if(ip->type != T_DIR){
80104fcc: 75 22 jne 80104ff0 <sys_chdir+0x70>
iunlockput(ip);
end_op();
return -1;
}
iunlock(ip);
80104fce: e8 ad c7 ff ff call 80101780 <iunlock>
iput(curproc->cwd);
80104fd3: 8b 46 6c mov 0x6c(%esi),%eax
80104fd6: 89 04 24 mov %eax,(%esp)
80104fd9: e8 e2 c7 ff ff call 801017c0 <iput>
end_op();
80104fde: e8 8d db ff ff call 80102b70 <end_op>
curproc->cwd = ip;
return 0;
80104fe3: 31 c0 xor %eax,%eax
return -1;
}
iunlock(ip);
iput(curproc->cwd);
end_op();
curproc->cwd = ip;
80104fe5: 89 5e 6c mov %ebx,0x6c(%esi)
return 0;
}
80104fe8: 83 c4 20 add $0x20,%esp
80104feb: 5b pop %ebx
80104fec: 5e pop %esi
80104fed: 5d pop %ebp
80104fee: c3 ret
80104fef: 90 nop
end_op();
return -1;
}
ilock(ip);
if(ip->type != T_DIR){
iunlockput(ip);
80104ff0: e8 0b c9 ff ff call 80101900 <iunlockput>
end_op();
80104ff5: e8 76 db ff ff call 80102b70 <end_op>
iunlock(ip);
iput(curproc->cwd);
end_op();
curproc->cwd = ip;
return 0;
}
80104ffa: 83 c4 20 add $0x20,%esp
}
ilock(ip);
if(ip->type != T_DIR){
iunlockput(ip);
end_op();
return -1;
80104ffd: b8 ff ff ff ff mov $0xffffffff,%eax
iunlock(ip);
iput(curproc->cwd);
end_op();
curproc->cwd = ip;
return 0;
}
80105002: 5b pop %ebx
80105003: 5e pop %esi
80105004: 5d pop %ebp
80105005: c3 ret
80105006: 8d 76 00 lea 0x0(%esi),%esi
80105009: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80105010 <sys_exec>:
int
sys_exec(void)
{
80105010: 55 push %ebp
80105011: 89 e5 mov %esp,%ebp
80105013: 57 push %edi
80105014: 56 push %esi
80105015: 53 push %ebx
80105016: 81 ec ac 00 00 00 sub $0xac,%esp
char *path, *argv[MAXARG];
int i;
uint uargv, uarg;
if(argstr(0, &path) < 0 || argint(1, (int*)&uargv) < 0){
8010501c: 8d 85 5c ff ff ff lea -0xa4(%ebp),%eax
80105022: 89 44 24 04 mov %eax,0x4(%esp)
80105026: c7 04 24 00 00 00 00 movl $0x0,(%esp)
8010502d: e8 5e f5 ff ff call 80104590 <argstr>
80105032: 85 c0 test %eax,%eax
80105034: 0f 88 84 00 00 00 js 801050be <sys_exec+0xae>
8010503a: 8d 85 60 ff ff ff lea -0xa0(%ebp),%eax
80105040: 89 44 24 04 mov %eax,0x4(%esp)
80105044: c7 04 24 01 00 00 00 movl $0x1,(%esp)
8010504b: e8 e0 f4 ff ff call 80104530 <argint>
80105050: 85 c0 test %eax,%eax
80105052: 78 6a js 801050be <sys_exec+0xae>
return -1;
}
memset(argv, 0, sizeof(argv));
80105054: 8d 85 68 ff ff ff lea -0x98(%ebp),%eax
for(i=0;; i++){
8010505a: 31 db xor %ebx,%ebx
uint uargv, uarg;
if(argstr(0, &path) < 0 || argint(1, (int*)&uargv) < 0){
return -1;
}
memset(argv, 0, sizeof(argv));
8010505c: c7 44 24 08 80 00 00 movl $0x80,0x8(%esp)
80105063: 00
80105064: 8d b5 68 ff ff ff lea -0x98(%ebp),%esi
8010506a: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
80105071: 00
80105072: 8d bd 64 ff ff ff lea -0x9c(%ebp),%edi
80105078: 89 04 24 mov %eax,(%esp)
8010507b: e8 f0 f1 ff ff call 80104270 <memset>
for(i=0;; i++){
if(i >= NELEM(argv))
return -1;
if(fetchint(uargv+4*i, (int*)&uarg) < 0)
80105080: 8b 85 60 ff ff ff mov -0xa0(%ebp),%eax
80105086: 89 7c 24 04 mov %edi,0x4(%esp)
8010508a: 8d 04 98 lea (%eax,%ebx,4),%eax
8010508d: 89 04 24 mov %eax,(%esp)
80105090: e8 2b f4 ff ff call 801044c0 <fetchint>
80105095: 85 c0 test %eax,%eax
80105097: 78 25 js 801050be <sys_exec+0xae>
return -1;
if(uarg == 0){
80105099: 8b 85 64 ff ff ff mov -0x9c(%ebp),%eax
8010509f: 85 c0 test %eax,%eax
801050a1: 74 2d je 801050d0 <sys_exec+0xc0>
argv[i] = 0;
break;
}
if(fetchstr(uarg, &argv[i]) < 0)
801050a3: 89 74 24 04 mov %esi,0x4(%esp)
801050a7: 89 04 24 mov %eax,(%esp)
801050aa: e8 31 f4 ff ff call 801044e0 <fetchstr>
801050af: 85 c0 test %eax,%eax
801050b1: 78 0b js 801050be <sys_exec+0xae>
if(argstr(0, &path) < 0 || argint(1, (int*)&uargv) < 0){
return -1;
}
memset(argv, 0, sizeof(argv));
for(i=0;; i++){
801050b3: 83 c3 01 add $0x1,%ebx
801050b6: 83 c6 04 add $0x4,%esi
if(i >= NELEM(argv))
801050b9: 83 fb 20 cmp $0x20,%ebx
801050bc: 75 c2 jne 80105080 <sys_exec+0x70>
}
if(fetchstr(uarg, &argv[i]) < 0)
return -1;
}
return exec(path, argv);
}
801050be: 81 c4 ac 00 00 00 add $0xac,%esp
char *path, *argv[MAXARG];
int i;
uint uargv, uarg;
if(argstr(0, &path) < 0 || argint(1, (int*)&uargv) < 0){
return -1;
801050c4: b8 ff ff ff ff mov $0xffffffff,%eax
}
if(fetchstr(uarg, &argv[i]) < 0)
return -1;
}
return exec(path, argv);
}
801050c9: 5b pop %ebx
801050ca: 5e pop %esi
801050cb: 5f pop %edi
801050cc: 5d pop %ebp
801050cd: c3 ret
801050ce: 66 90 xchg %ax,%ax
break;
}
if(fetchstr(uarg, &argv[i]) < 0)
return -1;
}
return exec(path, argv);
801050d0: 8d 85 68 ff ff ff lea -0x98(%ebp),%eax
801050d6: 89 44 24 04 mov %eax,0x4(%esp)
801050da: 8b 85 5c ff ff ff mov -0xa4(%ebp),%eax
if(i >= NELEM(argv))
return -1;
if(fetchint(uargv+4*i, (int*)&uarg) < 0)
return -1;
if(uarg == 0){
argv[i] = 0;
801050e0: c7 84 9d 68 ff ff ff movl $0x0,-0x98(%ebp,%ebx,4)
801050e7: 00 00 00 00
break;
}
if(fetchstr(uarg, &argv[i]) < 0)
return -1;
}
return exec(path, argv);
801050eb: 89 04 24 mov %eax,(%esp)
801050ee: e8 ad b8 ff ff call 801009a0 <exec>
}
801050f3: 81 c4 ac 00 00 00 add $0xac,%esp
801050f9: 5b pop %ebx
801050fa: 5e pop %esi
801050fb: 5f pop %edi
801050fc: 5d pop %ebp
801050fd: c3 ret
801050fe: 66 90 xchg %ax,%ax
80105100 <sys_pipe>:
int
sys_pipe(void)
{
80105100: 55 push %ebp
80105101: 89 e5 mov %esp,%ebp
80105103: 53 push %ebx
80105104: 83 ec 24 sub $0x24,%esp
int *fd;
struct file *rf, *wf;
int fd0, fd1;
if(argptr(0, (void*)&fd, 2*sizeof(fd[0])) < 0)
80105107: 8d 45 ec lea -0x14(%ebp),%eax
8010510a: c7 44 24 08 08 00 00 movl $0x8,0x8(%esp)
80105111: 00
80105112: 89 44 24 04 mov %eax,0x4(%esp)
80105116: c7 04 24 00 00 00 00 movl $0x0,(%esp)
8010511d: e8 3e f4 ff ff call 80104560 <argptr>
80105122: 85 c0 test %eax,%eax
80105124: 78 6d js 80105193 <sys_pipe+0x93>
return -1;
if(pipealloc(&rf, &wf) < 0)
80105126: 8d 45 f4 lea -0xc(%ebp),%eax
80105129: 89 44 24 04 mov %eax,0x4(%esp)
8010512d: 8d 45 f0 lea -0x10(%ebp),%eax
80105130: 89 04 24 mov %eax,(%esp)
80105133: e8 28 e0 ff ff call 80103160 <pipealloc>
80105138: 85 c0 test %eax,%eax
8010513a: 78 57 js 80105193 <sys_pipe+0x93>
return -1;
fd0 = -1;
if((fd0 = fdalloc(rf)) < 0 || (fd1 = fdalloc(wf)) < 0){
8010513c: 8b 45 f0 mov -0x10(%ebp),%eax
8010513f: e8 1c f5 ff ff call 80104660 <fdalloc>
80105144: 85 c0 test %eax,%eax
80105146: 89 c3 mov %eax,%ebx
80105148: 78 33 js 8010517d <sys_pipe+0x7d>
8010514a: 8b 45 f4 mov -0xc(%ebp),%eax
8010514d: e8 0e f5 ff ff call 80104660 <fdalloc>
80105152: 85 c0 test %eax,%eax
80105154: 78 1a js 80105170 <sys_pipe+0x70>
myproc()->ofile[fd0] = 0;
fileclose(rf);
fileclose(wf);
return -1;
}
fd[0] = fd0;
80105156: 8b 55 ec mov -0x14(%ebp),%edx
80105159: 89 1a mov %ebx,(%edx)
fd[1] = fd1;
8010515b: 8b 55 ec mov -0x14(%ebp),%edx
8010515e: 89 42 04 mov %eax,0x4(%edx)
return 0;
}
80105161: 83 c4 24 add $0x24,%esp
fileclose(wf);
return -1;
}
fd[0] = fd0;
fd[1] = fd1;
return 0;
80105164: 31 c0 xor %eax,%eax
}
80105166: 5b pop %ebx
80105167: 5d pop %ebp
80105168: c3 ret
80105169: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
if(pipealloc(&rf, &wf) < 0)
return -1;
fd0 = -1;
if((fd0 = fdalloc(rf)) < 0 || (fd1 = fdalloc(wf)) < 0){
if(fd0 >= 0)
myproc()->ofile[fd0] = 0;
80105170: e8 1b e5 ff ff call 80103690 <myproc>
80105175: c7 44 98 2c 00 00 00 movl $0x0,0x2c(%eax,%ebx,4)
8010517c: 00
fileclose(rf);
8010517d: 8b 45 f0 mov -0x10(%ebp),%eax
80105180: 89 04 24 mov %eax,(%esp)
80105183: e8 88 bc ff ff call 80100e10 <fileclose>
fileclose(wf);
80105188: 8b 45 f4 mov -0xc(%ebp),%eax
8010518b: 89 04 24 mov %eax,(%esp)
8010518e: e8 7d bc ff ff call 80100e10 <fileclose>
return -1;
}
fd[0] = fd0;
fd[1] = fd1;
return 0;
}
80105193: 83 c4 24 add $0x24,%esp
if((fd0 = fdalloc(rf)) < 0 || (fd1 = fdalloc(wf)) < 0){
if(fd0 >= 0)
myproc()->ofile[fd0] = 0;
fileclose(rf);
fileclose(wf);
return -1;
80105196: b8 ff ff ff ff mov $0xffffffff,%eax
}
fd[0] = fd0;
fd[1] = fd1;
return 0;
}
8010519b: 5b pop %ebx
8010519c: 5d pop %ebp
8010519d: c3 ret
8010519e: 66 90 xchg %ax,%ax
801051a0 <sys_shm_open>:
#include "param.h"
#include "memlayout.h"
#include "mmu.h"
#include "proc.h"
int sys_shm_open(void) {
801051a0: 55 push %ebp
801051a1: 89 e5 mov %esp,%ebp
801051a3: 83 ec 28 sub $0x28,%esp
int id;
char **pointer;
if(argint(0, &id) < 0)
801051a6: 8d 45 f0 lea -0x10(%ebp),%eax
801051a9: 89 44 24 04 mov %eax,0x4(%esp)
801051ad: c7 04 24 00 00 00 00 movl $0x0,(%esp)
801051b4: e8 77 f3 ff ff call 80104530 <argint>
801051b9: 85 c0 test %eax,%eax
801051bb: 78 33 js 801051f0 <sys_shm_open+0x50>
return -1;
if(argptr(1, (char **) (&pointer),4)<0)
801051bd: 8d 45 f4 lea -0xc(%ebp),%eax
801051c0: c7 44 24 08 04 00 00 movl $0x4,0x8(%esp)
801051c7: 00
801051c8: 89 44 24 04 mov %eax,0x4(%esp)
801051cc: c7 04 24 01 00 00 00 movl $0x1,(%esp)
801051d3: e8 88 f3 ff ff call 80104560 <argptr>
801051d8: 85 c0 test %eax,%eax
801051da: 78 14 js 801051f0 <sys_shm_open+0x50>
return -1;
return shm_open(id, pointer);
801051dc: 8b 45 f4 mov -0xc(%ebp),%eax
801051df: 89 44 24 04 mov %eax,0x4(%esp)
801051e3: 8b 45 f0 mov -0x10(%ebp),%eax
801051e6: 89 04 24 mov %eax,(%esp)
801051e9: e8 92 1b 00 00 call 80106d80 <shm_open>
}
801051ee: c9 leave
801051ef: c3 ret
int sys_shm_open(void) {
int id;
char **pointer;
if(argint(0, &id) < 0)
return -1;
801051f0: b8 ff ff ff ff mov $0xffffffff,%eax
if(argptr(1, (char **) (&pointer),4)<0)
return -1;
return shm_open(id, pointer);
}
801051f5: c9 leave
801051f6: c3 ret
801051f7: 89 f6 mov %esi,%esi
801051f9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80105200 <sys_shm_close>:
int sys_shm_close(void) {
80105200: 55 push %ebp
80105201: 89 e5 mov %esp,%ebp
80105203: 83 ec 28 sub $0x28,%esp
int id;
if(argint(0, &id) < 0)
80105206: 8d 45 f4 lea -0xc(%ebp),%eax
80105209: 89 44 24 04 mov %eax,0x4(%esp)
8010520d: c7 04 24 00 00 00 00 movl $0x0,(%esp)
80105214: e8 17 f3 ff ff call 80104530 <argint>
80105219: 85 c0 test %eax,%eax
8010521b: 78 13 js 80105230 <sys_shm_close+0x30>
return -1;
return shm_close(id);
8010521d: 8b 45 f4 mov -0xc(%ebp),%eax
80105220: 89 04 24 mov %eax,(%esp)
80105223: e8 68 1b 00 00 call 80106d90 <shm_close>
}
80105228: c9 leave
80105229: c3 ret
8010522a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
int sys_shm_close(void) {
int id;
if(argint(0, &id) < 0)
return -1;
80105230: b8 ff ff ff ff mov $0xffffffff,%eax
return shm_close(id);
}
80105235: c9 leave
80105236: c3 ret
80105237: 89 f6 mov %esi,%esi
80105239: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80105240 <sys_fork>:
int
sys_fork(void)
{
80105240: 55 push %ebp
80105241: 89 e5 mov %esp,%ebp
return fork();
}
80105243: 5d pop %ebp
}
int
sys_fork(void)
{
return fork();
80105244: e9 f7 e5 ff ff jmp 80103840 <fork>
80105249: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80105250 <sys_exit>:
}
int
sys_exit(void)
{
80105250: 55 push %ebp
80105251: 89 e5 mov %esp,%ebp
80105253: 83 ec 08 sub $0x8,%esp
exit();
80105256: e8 35 e8 ff ff call 80103a90 <exit>
return 0; // not reached
}
8010525b: 31 c0 xor %eax,%eax
8010525d: c9 leave
8010525e: c3 ret
8010525f: 90 nop
80105260 <sys_wait>:
int
sys_wait(void)
{
80105260: 55 push %ebp
80105261: 89 e5 mov %esp,%ebp
return wait();
}
80105263: 5d pop %ebp
}
int
sys_wait(void)
{
return wait();
80105264: e9 37 ea ff ff jmp 80103ca0 <wait>
80105269: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80105270 <sys_kill>:
}
int
sys_kill(void)
{
80105270: 55 push %ebp
80105271: 89 e5 mov %esp,%ebp
80105273: 83 ec 28 sub $0x28,%esp
int pid;
if(argint(0, &pid) < 0)
80105276: 8d 45 f4 lea -0xc(%ebp),%eax
80105279: 89 44 24 04 mov %eax,0x4(%esp)
8010527d: c7 04 24 00 00 00 00 movl $0x0,(%esp)
80105284: e8 a7 f2 ff ff call 80104530 <argint>
80105289: 85 c0 test %eax,%eax
8010528b: 78 13 js 801052a0 <sys_kill+0x30>
return -1;
return kill(pid);
8010528d: 8b 45 f4 mov -0xc(%ebp),%eax
80105290: 89 04 24 mov %eax,(%esp)
80105293: e8 48 eb ff ff call 80103de0 <kill>
}
80105298: c9 leave
80105299: c3 ret
8010529a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
sys_kill(void)
{
int pid;
if(argint(0, &pid) < 0)
return -1;
801052a0: b8 ff ff ff ff mov $0xffffffff,%eax
return kill(pid);
}
801052a5: c9 leave
801052a6: c3 ret
801052a7: 89 f6 mov %esi,%esi
801052a9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801052b0 <sys_getpid>:
int
sys_getpid(void)
{
801052b0: 55 push %ebp
801052b1: 89 e5 mov %esp,%ebp
801052b3: 83 ec 08 sub $0x8,%esp
return myproc()->pid;
801052b6: e8 d5 e3 ff ff call 80103690 <myproc>
801052bb: 8b 40 14 mov 0x14(%eax),%eax
}
801052be: c9 leave
801052bf: c3 ret
801052c0 <sys_sbrk>:
int
sys_sbrk(void)
{
801052c0: 55 push %ebp
801052c1: 89 e5 mov %esp,%ebp
801052c3: 53 push %ebx
801052c4: 83 ec 24 sub $0x24,%esp
int addr;
int n;
if(argint(0, &n) < 0)
801052c7: 8d 45 f4 lea -0xc(%ebp),%eax
801052ca: 89 44 24 04 mov %eax,0x4(%esp)
801052ce: c7 04 24 00 00 00 00 movl $0x0,(%esp)
801052d5: e8 56 f2 ff ff call 80104530 <argint>
801052da: 85 c0 test %eax,%eax
801052dc: 78 22 js 80105300 <sys_sbrk+0x40>
return -1;
addr = myproc()->sz;
801052de: e8 ad e3 ff ff call 80103690 <myproc>
if(growproc(n) < 0)
801052e3: 8b 55 f4 mov -0xc(%ebp),%edx
int addr;
int n;
if(argint(0, &n) < 0)
return -1;
addr = myproc()->sz;
801052e6: 8b 18 mov (%eax),%ebx
if(growproc(n) < 0)
801052e8: 89 14 24 mov %edx,(%esp)
801052eb: e8 e0 e4 ff ff call 801037d0 <growproc>
801052f0: 85 c0 test %eax,%eax
801052f2: 78 0c js 80105300 <sys_sbrk+0x40>
return -1;
return addr;
801052f4: 89 d8 mov %ebx,%eax
}
801052f6: 83 c4 24 add $0x24,%esp
801052f9: 5b pop %ebx
801052fa: 5d pop %ebp
801052fb: c3 ret
801052fc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
{
int addr;
int n;
if(argint(0, &n) < 0)
return -1;
80105300: b8 ff ff ff ff mov $0xffffffff,%eax
80105305: eb ef jmp 801052f6 <sys_sbrk+0x36>
80105307: 89 f6 mov %esi,%esi
80105309: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80105310 <sys_sleep>:
return addr;
}
int
sys_sleep(void)
{
80105310: 55 push %ebp
80105311: 89 e5 mov %esp,%ebp
80105313: 53 push %ebx
80105314: 83 ec 24 sub $0x24,%esp
int n;
uint ticks0;
if(argint(0, &n) < 0)
80105317: 8d 45 f4 lea -0xc(%ebp),%eax
8010531a: 89 44 24 04 mov %eax,0x4(%esp)
8010531e: c7 04 24 00 00 00 00 movl $0x0,(%esp)
80105325: e8 06 f2 ff ff call 80104530 <argint>
8010532a: 85 c0 test %eax,%eax
8010532c: 78 7e js 801053ac <sys_sleep+0x9c>
return -1;
acquire(&tickslock);
8010532e: c7 04 24 60 4d 11 80 movl $0x80114d60,(%esp)
80105335: e8 f6 ed ff ff call 80104130 <acquire>
ticks0 = ticks;
while(ticks - ticks0 < n){
8010533a: 8b 55 f4 mov -0xc(%ebp),%edx
uint ticks0;
if(argint(0, &n) < 0)
return -1;
acquire(&tickslock);
ticks0 = ticks;
8010533d: 8b 1d a0 55 11 80 mov 0x801155a0,%ebx
while(ticks - ticks0 < n){
80105343: 85 d2 test %edx,%edx
80105345: 75 29 jne 80105370 <sys_sleep+0x60>
80105347: eb 4f jmp 80105398 <sys_sleep+0x88>
80105349: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
if(myproc()->killed){
release(&tickslock);
return -1;
}
sleep(&ticks, &tickslock);
80105350: c7 44 24 04 60 4d 11 movl $0x80114d60,0x4(%esp)
80105357: 80
80105358: c7 04 24 a0 55 11 80 movl $0x801155a0,(%esp)
8010535f: e8 8c e8 ff ff call 80103bf0 <sleep>
if(argint(0, &n) < 0)
return -1;
acquire(&tickslock);
ticks0 = ticks;
while(ticks - ticks0 < n){
80105364: a1 a0 55 11 80 mov 0x801155a0,%eax
80105369: 29 d8 sub %ebx,%eax
8010536b: 3b 45 f4 cmp -0xc(%ebp),%eax
8010536e: 73 28 jae 80105398 <sys_sleep+0x88>
if(myproc()->killed){
80105370: e8 1b e3 ff ff call 80103690 <myproc>
80105375: 8b 40 28 mov 0x28(%eax),%eax
80105378: 85 c0 test %eax,%eax
8010537a: 74 d4 je 80105350 <sys_sleep+0x40>
release(&tickslock);
8010537c: c7 04 24 60 4d 11 80 movl $0x80114d60,(%esp)
80105383: e8 98 ee ff ff call 80104220 <release>
return -1;
80105388: b8 ff ff ff ff mov $0xffffffff,%eax
}
sleep(&ticks, &tickslock);
}
release(&tickslock);
return 0;
}
8010538d: 83 c4 24 add $0x24,%esp
80105390: 5b pop %ebx
80105391: 5d pop %ebp
80105392: c3 ret
80105393: 90 nop
80105394: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
release(&tickslock);
return -1;
}
sleep(&ticks, &tickslock);
}
release(&tickslock);
80105398: c7 04 24 60 4d 11 80 movl $0x80114d60,(%esp)
8010539f: e8 7c ee ff ff call 80104220 <release>
return 0;
}
801053a4: 83 c4 24 add $0x24,%esp
return -1;
}
sleep(&ticks, &tickslock);
}
release(&tickslock);
return 0;
801053a7: 31 c0 xor %eax,%eax
}
801053a9: 5b pop %ebx
801053aa: 5d pop %ebp
801053ab: c3 ret
{
int n;
uint ticks0;
if(argint(0, &n) < 0)
return -1;
801053ac: b8 ff ff ff ff mov $0xffffffff,%eax
801053b1: eb da jmp 8010538d <sys_sleep+0x7d>
801053b3: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
801053b9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801053c0 <sys_uptime>:
// return how many clock tick interrupts have occurred
// since start.
int
sys_uptime(void)
{
801053c0: 55 push %ebp
801053c1: 89 e5 mov %esp,%ebp
801053c3: 53 push %ebx
801053c4: 83 ec 14 sub $0x14,%esp
uint xticks;
acquire(&tickslock);
801053c7: c7 04 24 60 4d 11 80 movl $0x80114d60,(%esp)
801053ce: e8 5d ed ff ff call 80104130 <acquire>
xticks = ticks;
801053d3: 8b 1d a0 55 11 80 mov 0x801155a0,%ebx
release(&tickslock);
801053d9: c7 04 24 60 4d 11 80 movl $0x80114d60,(%esp)
801053e0: e8 3b ee ff ff call 80104220 <release>
return xticks;
}
801053e5: 83 c4 14 add $0x14,%esp
801053e8: 89 d8 mov %ebx,%eax
801053ea: 5b pop %ebx
801053eb: 5d pop %ebp
801053ec: c3 ret
801053ed <alltraps>:
# vectors.S sends all traps here.
.globl alltraps
alltraps:
# Build trap frame.
pushl %ds
801053ed: 1e push %ds
pushl %es
801053ee: 06 push %es
pushl %fs
801053ef: 0f a0 push %fs
pushl %gs
801053f1: 0f a8 push %gs
pushal
801053f3: 60 pusha
# Set up data segments.
movw $(SEG_KDATA<<3), %ax
801053f4: 66 b8 10 00 mov $0x10,%ax
movw %ax, %ds
801053f8: 8e d8 mov %eax,%ds
movw %ax, %es
801053fa: 8e c0 mov %eax,%es
# Call trap(tf), where tf=%esp
pushl %esp
801053fc: 54 push %esp
call trap
801053fd: e8 de 00 00 00 call 801054e0 <trap>
addl $4, %esp
80105402: 83 c4 04 add $0x4,%esp
80105405 <trapret>:
# Return falls through to trapret...
.globl trapret
trapret:
popal
80105405: 61 popa
popl %gs
80105406: 0f a9 pop %gs
popl %fs
80105408: 0f a1 pop %fs
popl %es
8010540a: 07 pop %es
popl %ds
8010540b: 1f pop %ds
addl $0x8, %esp # trapno and errcode
8010540c: 83 c4 08 add $0x8,%esp
iret
8010540f: cf iret
80105410 <tvinit>:
void
tvinit(void)
{
int i;
for(i = 0; i < 256; i++)
80105410: 31 c0 xor %eax,%eax
80105412: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
SETGATE(idt[i], 0, SEG_KCODE<<3, vectors[i], 0);
80105418: 8b 14 85 08 a0 10 80 mov -0x7fef5ff8(,%eax,4),%edx
8010541f: b9 08 00 00 00 mov $0x8,%ecx
80105424: 66 89 0c c5 a2 4d 11 mov %cx,-0x7feeb25e(,%eax,8)
8010542b: 80
8010542c: c6 04 c5 a4 4d 11 80 movb $0x0,-0x7feeb25c(,%eax,8)
80105433: 00
80105434: c6 04 c5 a5 4d 11 80 movb $0x8e,-0x7feeb25b(,%eax,8)
8010543b: 8e
8010543c: 66 89 14 c5 a0 4d 11 mov %dx,-0x7feeb260(,%eax,8)
80105443: 80
80105444: c1 ea 10 shr $0x10,%edx
80105447: 66 89 14 c5 a6 4d 11 mov %dx,-0x7feeb25a(,%eax,8)
8010544e: 80
void
tvinit(void)
{
int i;
for(i = 0; i < 256; i++)
8010544f: 83 c0 01 add $0x1,%eax
80105452: 3d 00 01 00 00 cmp $0x100,%eax
80105457: 75 bf jne 80105418 <tvinit+0x8>
struct spinlock tickslock;
uint ticks;
void
tvinit(void)
{
80105459: 55 push %ebp
int i;
for(i = 0; i < 256; i++)
SETGATE(idt[i], 0, SEG_KCODE<<3, vectors[i], 0);
SETGATE(idt[T_SYSCALL], 1, SEG_KCODE<<3, vectors[T_SYSCALL], DPL_USER);
8010545a: ba 08 00 00 00 mov $0x8,%edx
struct spinlock tickslock;
uint ticks;
void
tvinit(void)
{
8010545f: 89 e5 mov %esp,%ebp
80105461: 83 ec 18 sub $0x18,%esp
int i;
for(i = 0; i < 256; i++)
SETGATE(idt[i], 0, SEG_KCODE<<3, vectors[i], 0);
SETGATE(idt[T_SYSCALL], 1, SEG_KCODE<<3, vectors[T_SYSCALL], DPL_USER);
80105464: a1 08 a1 10 80 mov 0x8010a108,%eax
initlock(&tickslock, "time");
80105469: c7 44 24 04 41 75 10 movl $0x80107541,0x4(%esp)
80105470: 80
80105471: c7 04 24 60 4d 11 80 movl $0x80114d60,(%esp)
{
int i;
for(i = 0; i < 256; i++)
SETGATE(idt[i], 0, SEG_KCODE<<3, vectors[i], 0);
SETGATE(idt[T_SYSCALL], 1, SEG_KCODE<<3, vectors[T_SYSCALL], DPL_USER);
80105478: 66 89 15 a2 4f 11 80 mov %dx,0x80114fa2
8010547f: 66 a3 a0 4f 11 80 mov %ax,0x80114fa0
80105485: c1 e8 10 shr $0x10,%eax
80105488: c6 05 a4 4f 11 80 00 movb $0x0,0x80114fa4
8010548f: c6 05 a5 4f 11 80 ef movb $0xef,0x80114fa5
80105496: 66 a3 a6 4f 11 80 mov %ax,0x80114fa6
initlock(&tickslock, "time");
8010549c: e8 9f eb ff ff call 80104040 <initlock>
}
801054a1: c9 leave
801054a2: c3 ret
801054a3: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
801054a9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801054b0 <idtinit>:
void
idtinit(void)
{
801054b0: 55 push %ebp
static inline void
lidt(struct gatedesc *p, int size)
{
volatile ushort pd[3];
pd[0] = size-1;
801054b1: b8 ff 07 00 00 mov $0x7ff,%eax
801054b6: 89 e5 mov %esp,%ebp
801054b8: 83 ec 10 sub $0x10,%esp
801054bb: 66 89 45 fa mov %ax,-0x6(%ebp)
pd[1] = (uint)p;
801054bf: b8 a0 4d 11 80 mov $0x80114da0,%eax
801054c4: 66 89 45 fc mov %ax,-0x4(%ebp)
pd[2] = (uint)p >> 16;
801054c8: c1 e8 10 shr $0x10,%eax
801054cb: 66 89 45 fe mov %ax,-0x2(%ebp)
asm volatile("lidt (%0)" : : "r" (pd));
801054cf: 8d 45 fa lea -0x6(%ebp),%eax
801054d2: 0f 01 18 lidtl (%eax)
lidt(idt, sizeof(idt));
}
801054d5: c9 leave
801054d6: c3 ret
801054d7: 89 f6 mov %esi,%esi
801054d9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801054e0 <trap>:
//PAGEBREAK: 41
void
trap(struct trapframe *tf)
{
801054e0: 55 push %ebp
801054e1: 89 e5 mov %esp,%ebp
801054e3: 57 push %edi
801054e4: 56 push %esi
801054e5: 53 push %ebx
801054e6: 83 ec 3c sub $0x3c,%esp
801054e9: 8b 5d 08 mov 0x8(%ebp),%ebx
if(tf->trapno == T_SYSCALL){
801054ec: 8b 43 30 mov 0x30(%ebx),%eax
801054ef: 83 f8 40 cmp $0x40,%eax
801054f2: 0f 84 c0 01 00 00 je 801056b8 <trap+0x1d8>
if(myproc()->killed)
exit();
return;
}
switch(tf->trapno){
801054f8: 83 e8 0e sub $0xe,%eax
801054fb: 83 f8 31 cmp $0x31,%eax
801054fe: 77 26 ja 80105526 <trap+0x46>
80105500: ff 24 85 08 76 10 80 jmp *-0x7fef89f8(,%eax,4)
80105507: 90 nop
static inline uint
rcr2(void)
{
uint val;
asm volatile("movl %%cr2,%0" : "=r" (val));
80105508: 0f 20 d6 mov %cr2,%esi
cpuid(), tf->cs, tf->eip);
lapiceoi();
break;
case T_PGFLT:
//panic("PAGE FAULT");
if(PGROUNDDOWN(rcr2()) == myproc()->sb - PGSIZE)
8010550b: e8 80 e1 ff ff call 80103690 <myproc>
80105510: 81 e6 00 f0 ff ff and $0xfffff000,%esi
80105516: 8b 40 04 mov 0x4(%eax),%eax
80105519: 2d 00 10 00 00 sub $0x1000,%eax
8010551e: 39 c6 cmp %eax,%esi
80105520: 0f 84 40 02 00 00 je 80105766 <trap+0x286>
break;
}
//PAGEBREAK: 13
default:
if(myproc() == 0 || (tf->cs&3) == 0){
80105526: e8 65 e1 ff ff call 80103690 <myproc>
8010552b: 85 c0 test %eax,%eax
8010552d: 0f 84 fd 01 00 00 je 80105730 <trap+0x250>
80105533: f6 43 3c 03 testb $0x3,0x3c(%ebx)
80105537: 0f 84 f3 01 00 00 je 80105730 <trap+0x250>
8010553d: 0f 20 d1 mov %cr2,%ecx
cprintf("unexpected trap %d from cpu %d eip %x (cr2=0x%x)\n",
tf->trapno, cpuid(), tf->eip, rcr2());
panic("trap");
}
// In user space, assume process misbehaved.
cprintf("pid %d %s: trap %d err %d on cpu %d "
80105540: 8b 53 38 mov 0x38(%ebx),%edx
80105543: 89 4d d8 mov %ecx,-0x28(%ebp)
80105546: 89 55 dc mov %edx,-0x24(%ebp)
80105549: e8 22 e1 ff ff call 80103670 <cpuid>
8010554e: 8b 73 30 mov 0x30(%ebx),%esi
80105551: 89 c7 mov %eax,%edi
80105553: 8b 43 34 mov 0x34(%ebx),%eax
80105556: 89 45 e4 mov %eax,-0x1c(%ebp)
"eip 0x%x addr 0x%x--kill proc\n",
myproc()->pid, myproc()->name, tf->trapno,
80105559: e8 32 e1 ff ff call 80103690 <myproc>
8010555e: 89 45 e0 mov %eax,-0x20(%ebp)
80105561: e8 2a e1 ff ff call 80103690 <myproc>
cprintf("unexpected trap %d from cpu %d eip %x (cr2=0x%x)\n",
tf->trapno, cpuid(), tf->eip, rcr2());
panic("trap");
}
// In user space, assume process misbehaved.
cprintf("pid %d %s: trap %d err %d on cpu %d "
80105566: 8b 4d d8 mov -0x28(%ebp),%ecx
80105569: 89 74 24 0c mov %esi,0xc(%esp)
"eip 0x%x addr 0x%x--kill proc\n",
myproc()->pid, myproc()->name, tf->trapno,
8010556d: 8b 75 e0 mov -0x20(%ebp),%esi
cprintf("unexpected trap %d from cpu %d eip %x (cr2=0x%x)\n",
tf->trapno, cpuid(), tf->eip, rcr2());
panic("trap");
}
// In user space, assume process misbehaved.
cprintf("pid %d %s: trap %d err %d on cpu %d "
80105570: 8b 55 dc mov -0x24(%ebp),%edx
80105573: 89 7c 24 14 mov %edi,0x14(%esp)
80105577: 8b 7d e4 mov -0x1c(%ebp),%edi
8010557a: 89 4c 24 1c mov %ecx,0x1c(%esp)
"eip 0x%x addr 0x%x--kill proc\n",
myproc()->pid, myproc()->name, tf->trapno,
8010557e: 83 c6 70 add $0x70,%esi
cprintf("unexpected trap %d from cpu %d eip %x (cr2=0x%x)\n",
tf->trapno, cpuid(), tf->eip, rcr2());
panic("trap");
}
// In user space, assume process misbehaved.
cprintf("pid %d %s: trap %d err %d on cpu %d "
80105581: 89 54 24 18 mov %edx,0x18(%esp)
80105585: 89 7c 24 10 mov %edi,0x10(%esp)
"eip 0x%x addr 0x%x--kill proc\n",
myproc()->pid, myproc()->name, tf->trapno,
80105589: 89 74 24 08 mov %esi,0x8(%esp)
cprintf("unexpected trap %d from cpu %d eip %x (cr2=0x%x)\n",
tf->trapno, cpuid(), tf->eip, rcr2());
panic("trap");
}
// In user space, assume process misbehaved.
cprintf("pid %d %s: trap %d err %d on cpu %d "
8010558d: 8b 40 14 mov 0x14(%eax),%eax
80105590: c7 04 24 c4 75 10 80 movl $0x801075c4,(%esp)
80105597: 89 44 24 04 mov %eax,0x4(%esp)
8010559b: e8 b0 b0 ff ff call 80100650 <cprintf>
"eip 0x%x addr 0x%x--kill proc\n",
myproc()->pid, myproc()->name, tf->trapno,
tf->err, cpuid(), tf->eip, rcr2());
myproc()->killed = 1;
801055a0: e8 eb e0 ff ff call 80103690 <myproc>
801055a5: c7 40 28 01 00 00 00 movl $0x1,0x28(%eax)
}
// Force process exit if it has been killed and is in user space.
// (If it is still executing in the kernel, let it keep running
// until it gets to the regular system call return.)
if(myproc() && myproc()->killed && (tf->cs&3) == DPL_USER)
801055ac: e8 df e0 ff ff call 80103690 <myproc>
801055b1: 85 c0 test %eax,%eax
801055b3: 74 0c je 801055c1 <trap+0xe1>
801055b5: e8 d6 e0 ff ff call 80103690 <myproc>
801055ba: 8b 50 28 mov 0x28(%eax),%edx
801055bd: 85 d2 test %edx,%edx
801055bf: 75 4f jne 80105610 <trap+0x130>
exit();
// Force process to give up CPU on clock tick.
// If interrupts were on while locks held, would need to check nlock.
if(myproc() && myproc()->state == RUNNING &&
801055c1: e8 ca e0 ff ff call 80103690 <myproc>
801055c6: 85 c0 test %eax,%eax
801055c8: 74 11 je 801055db <trap+0xfb>
801055ca: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
801055d0: e8 bb e0 ff ff call 80103690 <myproc>
801055d5: 83 78 10 04 cmpl $0x4,0x10(%eax)
801055d9: 74 4d je 80105628 <trap+0x148>
tf->trapno == T_IRQ0+IRQ_TIMER)
yield();
// Check if the process has been killed since we yielded
if(myproc() && myproc()->killed && (tf->cs&3) == DPL_USER)
801055db: e8 b0 e0 ff ff call 80103690 <myproc>
801055e0: 85 c0 test %eax,%eax
801055e2: 74 1d je 80105601 <trap+0x121>
801055e4: e8 a7 e0 ff ff call 80103690 <myproc>
801055e9: 8b 40 28 mov 0x28(%eax),%eax
801055ec: 85 c0 test %eax,%eax
801055ee: 74 11 je 80105601 <trap+0x121>
801055f0: 0f b7 43 3c movzwl 0x3c(%ebx),%eax
801055f4: 83 e0 03 and $0x3,%eax
801055f7: 66 83 f8 03 cmp $0x3,%ax
801055fb: 0f 84 e8 00 00 00 je 801056e9 <trap+0x209>
exit();
}
80105601: 83 c4 3c add $0x3c,%esp
80105604: 5b pop %ebx
80105605: 5e pop %esi
80105606: 5f pop %edi
80105607: 5d pop %ebp
80105608: c3 ret
80105609: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
}
// Force process exit if it has been killed and is in user space.
// (If it is still executing in the kernel, let it keep running
// until it gets to the regular system call return.)
if(myproc() && myproc()->killed && (tf->cs&3) == DPL_USER)
80105610: 0f b7 43 3c movzwl 0x3c(%ebx),%eax
80105614: 83 e0 03 and $0x3,%eax
80105617: 66 83 f8 03 cmp $0x3,%ax
8010561b: 75 a4 jne 801055c1 <trap+0xe1>
exit();
8010561d: e8 6e e4 ff ff call 80103a90 <exit>
80105622: eb 9d jmp 801055c1 <trap+0xe1>
80105624: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
// Force process to give up CPU on clock tick.
// If interrupts were on while locks held, would need to check nlock.
if(myproc() && myproc()->state == RUNNING &&
80105628: 83 7b 30 20 cmpl $0x20,0x30(%ebx)
8010562c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80105630: 75 a9 jne 801055db <trap+0xfb>
tf->trapno == T_IRQ0+IRQ_TIMER)
yield();
80105632: e8 79 e5 ff ff call 80103bb0 <yield>
80105637: eb a2 jmp 801055db <trap+0xfb>
80105639: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
return;
}
switch(tf->trapno){
case T_IRQ0 + IRQ_TIMER:
if(cpuid() == 0){
80105640: e8 2b e0 ff ff call 80103670 <cpuid>
80105645: 85 c0 test %eax,%eax
80105647: 0f 84 b3 00 00 00 je 80105700 <trap+0x220>
8010564d: 8d 76 00 lea 0x0(%esi),%esi
}
lapiceoi();
break;
case T_IRQ0 + IRQ_IDE:
ideintr();
lapiceoi();
80105650: e8 1b d1 ff ff call 80102770 <lapiceoi>
break;
80105655: e9 52 ff ff ff jmp 801055ac <trap+0xcc>
8010565a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
case T_IRQ0 + IRQ_IDE+1:
// Bochs generates spurious IDE1 interrupts.
break;
case T_IRQ0 + IRQ_KBD:
kbdintr();
80105660: e8 5b cf ff ff call 801025c0 <kbdintr>
lapiceoi();
80105665: e8 06 d1 ff ff call 80102770 <lapiceoi>
break;
8010566a: e9 3d ff ff ff jmp 801055ac <trap+0xcc>
8010566f: 90 nop
case T_IRQ0 + IRQ_COM1:
uartintr();
80105670: e8 2b 02 00 00 call 801058a0 <uartintr>
lapiceoi();
80105675: e8 f6 d0 ff ff call 80102770 <lapiceoi>
break;
8010567a: e9 2d ff ff ff jmp 801055ac <trap+0xcc>
8010567f: 90 nop
case T_IRQ0 + 7:
case T_IRQ0 + IRQ_SPURIOUS:
cprintf("cpu%d: spurious interrupt at %x:%x\n",
80105680: 8b 7b 38 mov 0x38(%ebx),%edi
80105683: 0f b7 73 3c movzwl 0x3c(%ebx),%esi
80105687: e8 e4 df ff ff call 80103670 <cpuid>
8010568c: c7 04 24 6c 75 10 80 movl $0x8010756c,(%esp)
80105693: 89 7c 24 0c mov %edi,0xc(%esp)
80105697: 89 74 24 08 mov %esi,0x8(%esp)
8010569b: 89 44 24 04 mov %eax,0x4(%esp)
8010569f: e8 ac af ff ff call 80100650 <cprintf>
cpuid(), tf->cs, tf->eip);
lapiceoi();
801056a4: e8 c7 d0 ff ff call 80102770 <lapiceoi>
break;
801056a9: e9 fe fe ff ff jmp 801055ac <trap+0xcc>
801056ae: 66 90 xchg %ax,%ax
release(&tickslock);
}
lapiceoi();
break;
case T_IRQ0 + IRQ_IDE:
ideintr();
801056b0: e8 bb c9 ff ff call 80102070 <ideintr>
801056b5: eb 96 jmp 8010564d <trap+0x16d>
801056b7: 90 nop
801056b8: 90 nop
801056b9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
//PAGEBREAK: 41
void
trap(struct trapframe *tf)
{
if(tf->trapno == T_SYSCALL){
if(myproc()->killed)
801056c0: e8 cb df ff ff call 80103690 <myproc>
801056c5: 8b 70 28 mov 0x28(%eax),%esi
801056c8: 85 f6 test %esi,%esi
801056ca: 75 2c jne 801056f8 <trap+0x218>
exit();
myproc()->tf = tf;
801056cc: e8 bf df ff ff call 80103690 <myproc>
801056d1: 89 58 1c mov %ebx,0x1c(%eax)
syscall();
801056d4: e8 17 ef ff ff call 801045f0 <syscall>
if(myproc()->killed)
801056d9: e8 b2 df ff ff call 80103690 <myproc>
801056de: 8b 48 28 mov 0x28(%eax),%ecx
801056e1: 85 c9 test %ecx,%ecx
801056e3: 0f 84 18 ff ff ff je 80105601 <trap+0x121>
yield();
// Check if the process has been killed since we yielded
if(myproc() && myproc()->killed && (tf->cs&3) == DPL_USER)
exit();
}
801056e9: 83 c4 3c add $0x3c,%esp
801056ec: 5b pop %ebx
801056ed: 5e pop %esi
801056ee: 5f pop %edi
801056ef: 5d pop %ebp
if(myproc()->killed)
exit();
myproc()->tf = tf;
syscall();
if(myproc()->killed)
exit();
801056f0: e9 9b e3 ff ff jmp 80103a90 <exit>
801056f5: 8d 76 00 lea 0x0(%esi),%esi
void
trap(struct trapframe *tf)
{
if(tf->trapno == T_SYSCALL){
if(myproc()->killed)
exit();
801056f8: e8 93 e3 ff ff call 80103a90 <exit>
801056fd: eb cd jmp 801056cc <trap+0x1ec>
801056ff: 90 nop
}
switch(tf->trapno){
case T_IRQ0 + IRQ_TIMER:
if(cpuid() == 0){
acquire(&tickslock);
80105700: c7 04 24 60 4d 11 80 movl $0x80114d60,(%esp)
80105707: e8 24 ea ff ff call 80104130 <acquire>
ticks++;
wakeup(&ticks);
8010570c: c7 04 24 a0 55 11 80 movl $0x801155a0,(%esp)
switch(tf->trapno){
case T_IRQ0 + IRQ_TIMER:
if(cpuid() == 0){
acquire(&tickslock);
ticks++;
80105713: 83 05 a0 55 11 80 01 addl $0x1,0x801155a0
wakeup(&ticks);
8010571a: e8 61 e6 ff ff call 80103d80 <wakeup>
release(&tickslock);
8010571f: c7 04 24 60 4d 11 80 movl $0x80114d60,(%esp)
80105726: e8 f5 ea ff ff call 80104220 <release>
8010572b: e9 1d ff ff ff jmp 8010564d <trap+0x16d>
80105730: 0f 20 d7 mov %cr2,%edi
//PAGEBREAK: 13
default:
if(myproc() == 0 || (tf->cs&3) == 0){
// In kernel, it must be our mistake.
cprintf("unexpected trap %d from cpu %d eip %x (cr2=0x%x)\n",
80105733: 8b 73 38 mov 0x38(%ebx),%esi
80105736: e8 35 df ff ff call 80103670 <cpuid>
8010573b: 89 7c 24 10 mov %edi,0x10(%esp)
8010573f: 89 74 24 0c mov %esi,0xc(%esp)
80105743: 89 44 24 08 mov %eax,0x8(%esp)
80105747: 8b 43 30 mov 0x30(%ebx),%eax
8010574a: c7 04 24 90 75 10 80 movl $0x80107590,(%esp)
80105751: 89 44 24 04 mov %eax,0x4(%esp)
80105755: e8 f6 ae ff ff call 80100650 <cprintf>
tf->trapno, cpuid(), tf->eip, rcr2());
panic("trap");
8010575a: c7 04 24 64 75 10 80 movl $0x80107564,(%esp)
80105761: e8 fa ab ff ff call 80100360 <panic>
break;
case T_PGFLT:
//panic("PAGE FAULT");
if(PGROUNDDOWN(rcr2()) == myproc()->sb - PGSIZE)
{
panic("WE FOUND AN ACTUAL PAGE FAULT");
80105766: c7 04 24 46 75 10 80 movl $0x80107546,(%esp)
8010576d: e8 ee ab ff ff call 80100360 <panic>
80105772: 66 90 xchg %ax,%ax
80105774: 66 90 xchg %ax,%ax
80105776: 66 90 xchg %ax,%ax
80105778: 66 90 xchg %ax,%ax
8010577a: 66 90 xchg %ax,%ax
8010577c: 66 90 xchg %ax,%ax
8010577e: 66 90 xchg %ax,%ax
80105780 <uartgetc>:
}
static int
uartgetc(void)
{
if(!uart)
80105780: a1 bc a5 10 80 mov 0x8010a5bc,%eax
outb(COM1+0, c);
}
static int
uartgetc(void)
{
80105785: 55 push %ebp
80105786: 89 e5 mov %esp,%ebp
if(!uart)
80105788: 85 c0 test %eax,%eax
8010578a: 74 14 je 801057a0 <uartgetc+0x20>
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
8010578c: ba fd 03 00 00 mov $0x3fd,%edx
80105791: ec in (%dx),%al
return -1;
if(!(inb(COM1+5) & 0x01))
80105792: a8 01 test $0x1,%al
80105794: 74 0a je 801057a0 <uartgetc+0x20>
80105796: b2 f8 mov $0xf8,%dl
80105798: ec in (%dx),%al
return -1;
return inb(COM1+0);
80105799: 0f b6 c0 movzbl %al,%eax
}
8010579c: 5d pop %ebp
8010579d: c3 ret
8010579e: 66 90 xchg %ax,%ax
static int
uartgetc(void)
{
if(!uart)
return -1;
801057a0: b8 ff ff ff ff mov $0xffffffff,%eax
if(!(inb(COM1+5) & 0x01))
return -1;
return inb(COM1+0);
}
801057a5: 5d pop %ebp
801057a6: c3 ret
801057a7: 89 f6 mov %esi,%esi
801057a9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801057b0 <uartputc>:
void
uartputc(int c)
{
int i;
if(!uart)
801057b0: a1 bc a5 10 80 mov 0x8010a5bc,%eax
801057b5: 85 c0 test %eax,%eax
801057b7: 74 3f je 801057f8 <uartputc+0x48>
uartputc(*p);
}
void
uartputc(int c)
{
801057b9: 55 push %ebp
801057ba: 89 e5 mov %esp,%ebp
801057bc: 56 push %esi
801057bd: be fd 03 00 00 mov $0x3fd,%esi
801057c2: 53 push %ebx
int i;
if(!uart)
801057c3: bb 80 00 00 00 mov $0x80,%ebx
uartputc(*p);
}
void
uartputc(int c)
{
801057c8: 83 ec 10 sub $0x10,%esp
801057cb: eb 14 jmp 801057e1 <uartputc+0x31>
801057cd: 8d 76 00 lea 0x0(%esi),%esi
int i;
if(!uart)
return;
for(i = 0; i < 128 && !(inb(COM1+5) & 0x20); i++)
microdelay(10);
801057d0: c7 04 24 0a 00 00 00 movl $0xa,(%esp)
801057d7: e8 b4 cf ff ff call 80102790 <microdelay>
{
int i;
if(!uart)
return;
for(i = 0; i < 128 && !(inb(COM1+5) & 0x20); i++)
801057dc: 83 eb 01 sub $0x1,%ebx
801057df: 74 07 je 801057e8 <uartputc+0x38>
801057e1: 89 f2 mov %esi,%edx
801057e3: ec in (%dx),%al
801057e4: a8 20 test $0x20,%al
801057e6: 74 e8 je 801057d0 <uartputc+0x20>
microdelay(10);
outb(COM1+0, c);
801057e8: 0f b6 45 08 movzbl 0x8(%ebp),%eax
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
801057ec: ba f8 03 00 00 mov $0x3f8,%edx
801057f1: ee out %al,(%dx)
}
801057f2: 83 c4 10 add $0x10,%esp
801057f5: 5b pop %ebx
801057f6: 5e pop %esi
801057f7: 5d pop %ebp
801057f8: f3 c3 repz ret
801057fa: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80105800 <uartinit>:
static int uart; // is there a uart?
void
uartinit(void)
{
80105800: 55 push %ebp
80105801: 31 c9 xor %ecx,%ecx
80105803: 89 e5 mov %esp,%ebp
80105805: 89 c8 mov %ecx,%eax
80105807: 57 push %edi
80105808: bf fa 03 00 00 mov $0x3fa,%edi
8010580d: 56 push %esi
8010580e: 89 fa mov %edi,%edx
80105810: 53 push %ebx
80105811: 83 ec 1c sub $0x1c,%esp
80105814: ee out %al,(%dx)
80105815: be fb 03 00 00 mov $0x3fb,%esi
8010581a: b8 80 ff ff ff mov $0xffffff80,%eax
8010581f: 89 f2 mov %esi,%edx
80105821: ee out %al,(%dx)
80105822: b8 0c 00 00 00 mov $0xc,%eax
80105827: b2 f8 mov $0xf8,%dl
80105829: ee out %al,(%dx)
8010582a: bb f9 03 00 00 mov $0x3f9,%ebx
8010582f: 89 c8 mov %ecx,%eax
80105831: 89 da mov %ebx,%edx
80105833: ee out %al,(%dx)
80105834: b8 03 00 00 00 mov $0x3,%eax
80105839: 89 f2 mov %esi,%edx
8010583b: ee out %al,(%dx)
8010583c: b2 fc mov $0xfc,%dl
8010583e: 89 c8 mov %ecx,%eax
80105840: ee out %al,(%dx)
80105841: b8 01 00 00 00 mov $0x1,%eax
80105846: 89 da mov %ebx,%edx
80105848: ee out %al,(%dx)
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
80105849: b2 fd mov $0xfd,%dl
8010584b: ec in (%dx),%al
outb(COM1+3, 0x03); // Lock divisor, 8 data bits.
outb(COM1+4, 0);
outb(COM1+1, 0x01); // Enable receive interrupts.
// If status is 0xFF, no serial port.
if(inb(COM1+5) == 0xFF)
8010584c: 3c ff cmp $0xff,%al
8010584e: 74 42 je 80105892 <uartinit+0x92>
return;
uart = 1;
80105850: c7 05 bc a5 10 80 01 movl $0x1,0x8010a5bc
80105857: 00 00 00
8010585a: 89 fa mov %edi,%edx
8010585c: ec in (%dx),%al
8010585d: b2 f8 mov $0xf8,%dl
8010585f: ec in (%dx),%al
// Acknowledge pre-existing interrupt conditions;
// enable interrupts.
inb(COM1+2);
inb(COM1+0);
ioapicenable(IRQ_COM1, 0);
80105860: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
80105867: 00
// Announce that we're here.
for(p="xv6...\n"; *p; p++)
80105868: bb d0 76 10 80 mov $0x801076d0,%ebx
// Acknowledge pre-existing interrupt conditions;
// enable interrupts.
inb(COM1+2);
inb(COM1+0);
ioapicenable(IRQ_COM1, 0);
8010586d: c7 04 24 04 00 00 00 movl $0x4,(%esp)
80105874: e8 27 ca ff ff call 801022a0 <ioapicenable>
// Announce that we're here.
for(p="xv6...\n"; *p; p++)
80105879: b8 78 00 00 00 mov $0x78,%eax
8010587e: 66 90 xchg %ax,%ax
uartputc(*p);
80105880: 89 04 24 mov %eax,(%esp)
inb(COM1+2);
inb(COM1+0);
ioapicenable(IRQ_COM1, 0);
// Announce that we're here.
for(p="xv6...\n"; *p; p++)
80105883: 83 c3 01 add $0x1,%ebx
uartputc(*p);
80105886: e8 25 ff ff ff call 801057b0 <uartputc>
inb(COM1+2);
inb(COM1+0);
ioapicenable(IRQ_COM1, 0);
// Announce that we're here.
for(p="xv6...\n"; *p; p++)
8010588b: 0f be 03 movsbl (%ebx),%eax
8010588e: 84 c0 test %al,%al
80105890: 75 ee jne 80105880 <uartinit+0x80>
uartputc(*p);
}
80105892: 83 c4 1c add $0x1c,%esp
80105895: 5b pop %ebx
80105896: 5e pop %esi
80105897: 5f pop %edi
80105898: 5d pop %ebp
80105899: c3 ret
8010589a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
801058a0 <uartintr>:
return inb(COM1+0);
}
void
uartintr(void)
{
801058a0: 55 push %ebp
801058a1: 89 e5 mov %esp,%ebp
801058a3: 83 ec 18 sub $0x18,%esp
consoleintr(uartgetc);
801058a6: c7 04 24 80 57 10 80 movl $0x80105780,(%esp)
801058ad: e8 fe ae ff ff call 801007b0 <consoleintr>
}
801058b2: c9 leave
801058b3: c3 ret
801058b4 <vector0>:
# generated by vectors.pl - do not edit
# handlers
.globl alltraps
.globl vector0
vector0:
pushl $0
801058b4: 6a 00 push $0x0
pushl $0
801058b6: 6a 00 push $0x0
jmp alltraps
801058b8: e9 30 fb ff ff jmp 801053ed <alltraps>
801058bd <vector1>:
.globl vector1
vector1:
pushl $0
801058bd: 6a 00 push $0x0
pushl $1
801058bf: 6a 01 push $0x1
jmp alltraps
801058c1: e9 27 fb ff ff jmp 801053ed <alltraps>
801058c6 <vector2>:
.globl vector2
vector2:
pushl $0
801058c6: 6a 00 push $0x0
pushl $2
801058c8: 6a 02 push $0x2
jmp alltraps
801058ca: e9 1e fb ff ff jmp 801053ed <alltraps>
801058cf <vector3>:
.globl vector3
vector3:
pushl $0
801058cf: 6a 00 push $0x0
pushl $3
801058d1: 6a 03 push $0x3
jmp alltraps
801058d3: e9 15 fb ff ff jmp 801053ed <alltraps>
801058d8 <vector4>:
.globl vector4
vector4:
pushl $0
801058d8: 6a 00 push $0x0
pushl $4
801058da: 6a 04 push $0x4
jmp alltraps
801058dc: e9 0c fb ff ff jmp 801053ed <alltraps>
801058e1 <vector5>:
.globl vector5
vector5:
pushl $0
801058e1: 6a 00 push $0x0
pushl $5
801058e3: 6a 05 push $0x5
jmp alltraps
801058e5: e9 03 fb ff ff jmp 801053ed <alltraps>
801058ea <vector6>:
.globl vector6
vector6:
pushl $0
801058ea: 6a 00 push $0x0
pushl $6
801058ec: 6a 06 push $0x6
jmp alltraps
801058ee: e9 fa fa ff ff jmp 801053ed <alltraps>
801058f3 <vector7>:
.globl vector7
vector7:
pushl $0
801058f3: 6a 00 push $0x0
pushl $7
801058f5: 6a 07 push $0x7
jmp alltraps
801058f7: e9 f1 fa ff ff jmp 801053ed <alltraps>
801058fc <vector8>:
.globl vector8
vector8:
pushl $8
801058fc: 6a 08 push $0x8
jmp alltraps
801058fe: e9 ea fa ff ff jmp 801053ed <alltraps>
80105903 <vector9>:
.globl vector9
vector9:
pushl $0
80105903: 6a 00 push $0x0
pushl $9
80105905: 6a 09 push $0x9
jmp alltraps
80105907: e9 e1 fa ff ff jmp 801053ed <alltraps>
8010590c <vector10>:
.globl vector10
vector10:
pushl $10
8010590c: 6a 0a push $0xa
jmp alltraps
8010590e: e9 da fa ff ff jmp 801053ed <alltraps>
80105913 <vector11>:
.globl vector11
vector11:
pushl $11
80105913: 6a 0b push $0xb
jmp alltraps
80105915: e9 d3 fa ff ff jmp 801053ed <alltraps>
8010591a <vector12>:
.globl vector12
vector12:
pushl $12
8010591a: 6a 0c push $0xc
jmp alltraps
8010591c: e9 cc fa ff ff jmp 801053ed <alltraps>
80105921 <vector13>:
.globl vector13
vector13:
pushl $13
80105921: 6a 0d push $0xd
jmp alltraps
80105923: e9 c5 fa ff ff jmp 801053ed <alltraps>
80105928 <vector14>:
.globl vector14
vector14:
pushl $14
80105928: 6a 0e push $0xe
jmp alltraps
8010592a: e9 be fa ff ff jmp 801053ed <alltraps>
8010592f <vector15>:
.globl vector15
vector15:
pushl $0
8010592f: 6a 00 push $0x0
pushl $15
80105931: 6a 0f push $0xf
jmp alltraps
80105933: e9 b5 fa ff ff jmp 801053ed <alltraps>
80105938 <vector16>:
.globl vector16
vector16:
pushl $0
80105938: 6a 00 push $0x0
pushl $16
8010593a: 6a 10 push $0x10
jmp alltraps
8010593c: e9 ac fa ff ff jmp 801053ed <alltraps>
80105941 <vector17>:
.globl vector17
vector17:
pushl $17
80105941: 6a 11 push $0x11
jmp alltraps
80105943: e9 a5 fa ff ff jmp 801053ed <alltraps>
80105948 <vector18>:
.globl vector18
vector18:
pushl $0
80105948: 6a 00 push $0x0
pushl $18
8010594a: 6a 12 push $0x12
jmp alltraps
8010594c: e9 9c fa ff ff jmp 801053ed <alltraps>
80105951 <vector19>:
.globl vector19
vector19:
pushl $0
80105951: 6a 00 push $0x0
pushl $19
80105953: 6a 13 push $0x13
jmp alltraps
80105955: e9 93 fa ff ff jmp 801053ed <alltraps>
8010595a <vector20>:
.globl vector20
vector20:
pushl $0
8010595a: 6a 00 push $0x0
pushl $20
8010595c: 6a 14 push $0x14
jmp alltraps
8010595e: e9 8a fa ff ff jmp 801053ed <alltraps>
80105963 <vector21>:
.globl vector21
vector21:
pushl $0
80105963: 6a 00 push $0x0
pushl $21
80105965: 6a 15 push $0x15
jmp alltraps
80105967: e9 81 fa ff ff jmp 801053ed <alltraps>
8010596c <vector22>:
.globl vector22
vector22:
pushl $0
8010596c: 6a 00 push $0x0
pushl $22
8010596e: 6a 16 push $0x16
jmp alltraps
80105970: e9 78 fa ff ff jmp 801053ed <alltraps>
80105975 <vector23>:
.globl vector23
vector23:
pushl $0
80105975: 6a 00 push $0x0
pushl $23
80105977: 6a 17 push $0x17
jmp alltraps
80105979: e9 6f fa ff ff jmp 801053ed <alltraps>
8010597e <vector24>:
.globl vector24
vector24:
pushl $0
8010597e: 6a 00 push $0x0
pushl $24
80105980: 6a 18 push $0x18
jmp alltraps
80105982: e9 66 fa ff ff jmp 801053ed <alltraps>
80105987 <vector25>:
.globl vector25
vector25:
pushl $0
80105987: 6a 00 push $0x0
pushl $25
80105989: 6a 19 push $0x19
jmp alltraps
8010598b: e9 5d fa ff ff jmp 801053ed <alltraps>
80105990 <vector26>:
.globl vector26
vector26:
pushl $0
80105990: 6a 00 push $0x0
pushl $26
80105992: 6a 1a push $0x1a
jmp alltraps
80105994: e9 54 fa ff ff jmp 801053ed <alltraps>
80105999 <vector27>:
.globl vector27
vector27:
pushl $0
80105999: 6a 00 push $0x0
pushl $27
8010599b: 6a 1b push $0x1b
jmp alltraps
8010599d: e9 4b fa ff ff jmp 801053ed <alltraps>
801059a2 <vector28>:
.globl vector28
vector28:
pushl $0
801059a2: 6a 00 push $0x0
pushl $28
801059a4: 6a 1c push $0x1c
jmp alltraps
801059a6: e9 42 fa ff ff jmp 801053ed <alltraps>
801059ab <vector29>:
.globl vector29
vector29:
pushl $0
801059ab: 6a 00 push $0x0
pushl $29
801059ad: 6a 1d push $0x1d
jmp alltraps
801059af: e9 39 fa ff ff jmp 801053ed <alltraps>
801059b4 <vector30>:
.globl vector30
vector30:
pushl $0
801059b4: 6a 00 push $0x0
pushl $30
801059b6: 6a 1e push $0x1e
jmp alltraps
801059b8: e9 30 fa ff ff jmp 801053ed <alltraps>
801059bd <vector31>:
.globl vector31
vector31:
pushl $0
801059bd: 6a 00 push $0x0
pushl $31
801059bf: 6a 1f push $0x1f
jmp alltraps
801059c1: e9 27 fa ff ff jmp 801053ed <alltraps>
801059c6 <vector32>:
.globl vector32
vector32:
pushl $0
801059c6: 6a 00 push $0x0
pushl $32
801059c8: 6a 20 push $0x20
jmp alltraps
801059ca: e9 1e fa ff ff jmp 801053ed <alltraps>
801059cf <vector33>:
.globl vector33
vector33:
pushl $0
801059cf: 6a 00 push $0x0
pushl $33
801059d1: 6a 21 push $0x21
jmp alltraps
801059d3: e9 15 fa ff ff jmp 801053ed <alltraps>
801059d8 <vector34>:
.globl vector34
vector34:
pushl $0
801059d8: 6a 00 push $0x0
pushl $34
801059da: 6a 22 push $0x22
jmp alltraps
801059dc: e9 0c fa ff ff jmp 801053ed <alltraps>
801059e1 <vector35>:
.globl vector35
vector35:
pushl $0
801059e1: 6a 00 push $0x0
pushl $35
801059e3: 6a 23 push $0x23
jmp alltraps
801059e5: e9 03 fa ff ff jmp 801053ed <alltraps>
801059ea <vector36>:
.globl vector36
vector36:
pushl $0
801059ea: 6a 00 push $0x0
pushl $36
801059ec: 6a 24 push $0x24
jmp alltraps
801059ee: e9 fa f9 ff ff jmp 801053ed <alltraps>
801059f3 <vector37>:
.globl vector37
vector37:
pushl $0
801059f3: 6a 00 push $0x0
pushl $37
801059f5: 6a 25 push $0x25
jmp alltraps
801059f7: e9 f1 f9 ff ff jmp 801053ed <alltraps>
801059fc <vector38>:
.globl vector38
vector38:
pushl $0
801059fc: 6a 00 push $0x0
pushl $38
801059fe: 6a 26 push $0x26
jmp alltraps
80105a00: e9 e8 f9 ff ff jmp 801053ed <alltraps>
80105a05 <vector39>:
.globl vector39
vector39:
pushl $0
80105a05: 6a 00 push $0x0
pushl $39
80105a07: 6a 27 push $0x27
jmp alltraps
80105a09: e9 df f9 ff ff jmp 801053ed <alltraps>
80105a0e <vector40>:
.globl vector40
vector40:
pushl $0
80105a0e: 6a 00 push $0x0
pushl $40
80105a10: 6a 28 push $0x28
jmp alltraps
80105a12: e9 d6 f9 ff ff jmp 801053ed <alltraps>
80105a17 <vector41>:
.globl vector41
vector41:
pushl $0
80105a17: 6a 00 push $0x0
pushl $41
80105a19: 6a 29 push $0x29
jmp alltraps
80105a1b: e9 cd f9 ff ff jmp 801053ed <alltraps>
80105a20 <vector42>:
.globl vector42
vector42:
pushl $0
80105a20: 6a 00 push $0x0
pushl $42
80105a22: 6a 2a push $0x2a
jmp alltraps
80105a24: e9 c4 f9 ff ff jmp 801053ed <alltraps>
80105a29 <vector43>:
.globl vector43
vector43:
pushl $0
80105a29: 6a 00 push $0x0
pushl $43
80105a2b: 6a 2b push $0x2b
jmp alltraps
80105a2d: e9 bb f9 ff ff jmp 801053ed <alltraps>
80105a32 <vector44>:
.globl vector44
vector44:
pushl $0
80105a32: 6a 00 push $0x0
pushl $44
80105a34: 6a 2c push $0x2c
jmp alltraps
80105a36: e9 b2 f9 ff ff jmp 801053ed <alltraps>
80105a3b <vector45>:
.globl vector45
vector45:
pushl $0
80105a3b: 6a 00 push $0x0
pushl $45
80105a3d: 6a 2d push $0x2d
jmp alltraps
80105a3f: e9 a9 f9 ff ff jmp 801053ed <alltraps>
80105a44 <vector46>:
.globl vector46
vector46:
pushl $0
80105a44: 6a 00 push $0x0
pushl $46
80105a46: 6a 2e push $0x2e
jmp alltraps
80105a48: e9 a0 f9 ff ff jmp 801053ed <alltraps>
80105a4d <vector47>:
.globl vector47
vector47:
pushl $0
80105a4d: 6a 00 push $0x0
pushl $47
80105a4f: 6a 2f push $0x2f
jmp alltraps
80105a51: e9 97 f9 ff ff jmp 801053ed <alltraps>
80105a56 <vector48>:
.globl vector48
vector48:
pushl $0
80105a56: 6a 00 push $0x0
pushl $48
80105a58: 6a 30 push $0x30
jmp alltraps
80105a5a: e9 8e f9 ff ff jmp 801053ed <alltraps>
80105a5f <vector49>:
.globl vector49
vector49:
pushl $0
80105a5f: 6a 00 push $0x0
pushl $49
80105a61: 6a 31 push $0x31
jmp alltraps
80105a63: e9 85 f9 ff ff jmp 801053ed <alltraps>
80105a68 <vector50>:
.globl vector50
vector50:
pushl $0
80105a68: 6a 00 push $0x0
pushl $50
80105a6a: 6a 32 push $0x32
jmp alltraps
80105a6c: e9 7c f9 ff ff jmp 801053ed <alltraps>
80105a71 <vector51>:
.globl vector51
vector51:
pushl $0
80105a71: 6a 00 push $0x0
pushl $51
80105a73: 6a 33 push $0x33
jmp alltraps
80105a75: e9 73 f9 ff ff jmp 801053ed <alltraps>
80105a7a <vector52>:
.globl vector52
vector52:
pushl $0
80105a7a: 6a 00 push $0x0
pushl $52
80105a7c: 6a 34 push $0x34
jmp alltraps
80105a7e: e9 6a f9 ff ff jmp 801053ed <alltraps>
80105a83 <vector53>:
.globl vector53
vector53:
pushl $0
80105a83: 6a 00 push $0x0
pushl $53
80105a85: 6a 35 push $0x35
jmp alltraps
80105a87: e9 61 f9 ff ff jmp 801053ed <alltraps>
80105a8c <vector54>:
.globl vector54
vector54:
pushl $0
80105a8c: 6a 00 push $0x0
pushl $54
80105a8e: 6a 36 push $0x36
jmp alltraps
80105a90: e9 58 f9 ff ff jmp 801053ed <alltraps>
80105a95 <vector55>:
.globl vector55
vector55:
pushl $0
80105a95: 6a 00 push $0x0
pushl $55
80105a97: 6a 37 push $0x37
jmp alltraps
80105a99: e9 4f f9 ff ff jmp 801053ed <alltraps>
80105a9e <vector56>:
.globl vector56
vector56:
pushl $0
80105a9e: 6a 00 push $0x0
pushl $56
80105aa0: 6a 38 push $0x38
jmp alltraps
80105aa2: e9 46 f9 ff ff jmp 801053ed <alltraps>
80105aa7 <vector57>:
.globl vector57
vector57:
pushl $0
80105aa7: 6a 00 push $0x0
pushl $57
80105aa9: 6a 39 push $0x39
jmp alltraps
80105aab: e9 3d f9 ff ff jmp 801053ed <alltraps>
80105ab0 <vector58>:
.globl vector58
vector58:
pushl $0
80105ab0: 6a 00 push $0x0
pushl $58
80105ab2: 6a 3a push $0x3a
jmp alltraps
80105ab4: e9 34 f9 ff ff jmp 801053ed <alltraps>
80105ab9 <vector59>:
.globl vector59
vector59:
pushl $0
80105ab9: 6a 00 push $0x0
pushl $59
80105abb: 6a 3b push $0x3b
jmp alltraps
80105abd: e9 2b f9 ff ff jmp 801053ed <alltraps>
80105ac2 <vector60>:
.globl vector60
vector60:
pushl $0
80105ac2: 6a 00 push $0x0
pushl $60
80105ac4: 6a 3c push $0x3c
jmp alltraps
80105ac6: e9 22 f9 ff ff jmp 801053ed <alltraps>
80105acb <vector61>:
.globl vector61
vector61:
pushl $0
80105acb: 6a 00 push $0x0
pushl $61
80105acd: 6a 3d push $0x3d
jmp alltraps
80105acf: e9 19 f9 ff ff jmp 801053ed <alltraps>
80105ad4 <vector62>:
.globl vector62
vector62:
pushl $0
80105ad4: 6a 00 push $0x0
pushl $62
80105ad6: 6a 3e push $0x3e
jmp alltraps
80105ad8: e9 10 f9 ff ff jmp 801053ed <alltraps>
80105add <vector63>:
.globl vector63
vector63:
pushl $0
80105add: 6a 00 push $0x0
pushl $63
80105adf: 6a 3f push $0x3f
jmp alltraps
80105ae1: e9 07 f9 ff ff jmp 801053ed <alltraps>
80105ae6 <vector64>:
.globl vector64
vector64:
pushl $0
80105ae6: 6a 00 push $0x0
pushl $64
80105ae8: 6a 40 push $0x40
jmp alltraps
80105aea: e9 fe f8 ff ff jmp 801053ed <alltraps>
80105aef <vector65>:
.globl vector65
vector65:
pushl $0
80105aef: 6a 00 push $0x0
pushl $65
80105af1: 6a 41 push $0x41
jmp alltraps
80105af3: e9 f5 f8 ff ff jmp 801053ed <alltraps>
80105af8 <vector66>:
.globl vector66
vector66:
pushl $0
80105af8: 6a 00 push $0x0
pushl $66
80105afa: 6a 42 push $0x42
jmp alltraps
80105afc: e9 ec f8 ff ff jmp 801053ed <alltraps>
80105b01 <vector67>:
.globl vector67
vector67:
pushl $0
80105b01: 6a 00 push $0x0
pushl $67
80105b03: 6a 43 push $0x43
jmp alltraps
80105b05: e9 e3 f8 ff ff jmp 801053ed <alltraps>
80105b0a <vector68>:
.globl vector68
vector68:
pushl $0
80105b0a: 6a 00 push $0x0
pushl $68
80105b0c: 6a 44 push $0x44
jmp alltraps
80105b0e: e9 da f8 ff ff jmp 801053ed <alltraps>
80105b13 <vector69>:
.globl vector69
vector69:
pushl $0
80105b13: 6a 00 push $0x0
pushl $69
80105b15: 6a 45 push $0x45
jmp alltraps
80105b17: e9 d1 f8 ff ff jmp 801053ed <alltraps>
80105b1c <vector70>:
.globl vector70
vector70:
pushl $0
80105b1c: 6a 00 push $0x0
pushl $70
80105b1e: 6a 46 push $0x46
jmp alltraps
80105b20: e9 c8 f8 ff ff jmp 801053ed <alltraps>
80105b25 <vector71>:
.globl vector71
vector71:
pushl $0
80105b25: 6a 00 push $0x0
pushl $71
80105b27: 6a 47 push $0x47
jmp alltraps
80105b29: e9 bf f8 ff ff jmp 801053ed <alltraps>
80105b2e <vector72>:
.globl vector72
vector72:
pushl $0
80105b2e: 6a 00 push $0x0
pushl $72
80105b30: 6a 48 push $0x48
jmp alltraps
80105b32: e9 b6 f8 ff ff jmp 801053ed <alltraps>
80105b37 <vector73>:
.globl vector73
vector73:
pushl $0
80105b37: 6a 00 push $0x0
pushl $73
80105b39: 6a 49 push $0x49
jmp alltraps
80105b3b: e9 ad f8 ff ff jmp 801053ed <alltraps>
80105b40 <vector74>:
.globl vector74
vector74:
pushl $0
80105b40: 6a 00 push $0x0
pushl $74
80105b42: 6a 4a push $0x4a
jmp alltraps
80105b44: e9 a4 f8 ff ff jmp 801053ed <alltraps>
80105b49 <vector75>:
.globl vector75
vector75:
pushl $0
80105b49: 6a 00 push $0x0
pushl $75
80105b4b: 6a 4b push $0x4b
jmp alltraps
80105b4d: e9 9b f8 ff ff jmp 801053ed <alltraps>
80105b52 <vector76>:
.globl vector76
vector76:
pushl $0
80105b52: 6a 00 push $0x0
pushl $76
80105b54: 6a 4c push $0x4c
jmp alltraps
80105b56: e9 92 f8 ff ff jmp 801053ed <alltraps>
80105b5b <vector77>:
.globl vector77
vector77:
pushl $0
80105b5b: 6a 00 push $0x0
pushl $77
80105b5d: 6a 4d push $0x4d
jmp alltraps
80105b5f: e9 89 f8 ff ff jmp 801053ed <alltraps>
80105b64 <vector78>:
.globl vector78
vector78:
pushl $0
80105b64: 6a 00 push $0x0
pushl $78
80105b66: 6a 4e push $0x4e
jmp alltraps
80105b68: e9 80 f8 ff ff jmp 801053ed <alltraps>
80105b6d <vector79>:
.globl vector79
vector79:
pushl $0
80105b6d: 6a 00 push $0x0
pushl $79
80105b6f: 6a 4f push $0x4f
jmp alltraps
80105b71: e9 77 f8 ff ff jmp 801053ed <alltraps>
80105b76 <vector80>:
.globl vector80
vector80:
pushl $0
80105b76: 6a 00 push $0x0
pushl $80
80105b78: 6a 50 push $0x50
jmp alltraps
80105b7a: e9 6e f8 ff ff jmp 801053ed <alltraps>
80105b7f <vector81>:
.globl vector81
vector81:
pushl $0
80105b7f: 6a 00 push $0x0
pushl $81
80105b81: 6a 51 push $0x51
jmp alltraps
80105b83: e9 65 f8 ff ff jmp 801053ed <alltraps>
80105b88 <vector82>:
.globl vector82
vector82:
pushl $0
80105b88: 6a 00 push $0x0
pushl $82
80105b8a: 6a 52 push $0x52
jmp alltraps
80105b8c: e9 5c f8 ff ff jmp 801053ed <alltraps>
80105b91 <vector83>:
.globl vector83
vector83:
pushl $0
80105b91: 6a 00 push $0x0
pushl $83
80105b93: 6a 53 push $0x53
jmp alltraps
80105b95: e9 53 f8 ff ff jmp 801053ed <alltraps>
80105b9a <vector84>:
.globl vector84
vector84:
pushl $0
80105b9a: 6a 00 push $0x0
pushl $84
80105b9c: 6a 54 push $0x54
jmp alltraps
80105b9e: e9 4a f8 ff ff jmp 801053ed <alltraps>
80105ba3 <vector85>:
.globl vector85
vector85:
pushl $0
80105ba3: 6a 00 push $0x0
pushl $85
80105ba5: 6a 55 push $0x55
jmp alltraps
80105ba7: e9 41 f8 ff ff jmp 801053ed <alltraps>
80105bac <vector86>:
.globl vector86
vector86:
pushl $0
80105bac: 6a 00 push $0x0
pushl $86
80105bae: 6a 56 push $0x56
jmp alltraps
80105bb0: e9 38 f8 ff ff jmp 801053ed <alltraps>
80105bb5 <vector87>:
.globl vector87
vector87:
pushl $0
80105bb5: 6a 00 push $0x0
pushl $87
80105bb7: 6a 57 push $0x57
jmp alltraps
80105bb9: e9 2f f8 ff ff jmp 801053ed <alltraps>
80105bbe <vector88>:
.globl vector88
vector88:
pushl $0
80105bbe: 6a 00 push $0x0
pushl $88
80105bc0: 6a 58 push $0x58
jmp alltraps
80105bc2: e9 26 f8 ff ff jmp 801053ed <alltraps>
80105bc7 <vector89>:
.globl vector89
vector89:
pushl $0
80105bc7: 6a 00 push $0x0
pushl $89
80105bc9: 6a 59 push $0x59
jmp alltraps
80105bcb: e9 1d f8 ff ff jmp 801053ed <alltraps>
80105bd0 <vector90>:
.globl vector90
vector90:
pushl $0
80105bd0: 6a 00 push $0x0
pushl $90
80105bd2: 6a 5a push $0x5a
jmp alltraps
80105bd4: e9 14 f8 ff ff jmp 801053ed <alltraps>
80105bd9 <vector91>:
.globl vector91
vector91:
pushl $0
80105bd9: 6a 00 push $0x0
pushl $91
80105bdb: 6a 5b push $0x5b
jmp alltraps
80105bdd: e9 0b f8 ff ff jmp 801053ed <alltraps>
80105be2 <vector92>:
.globl vector92
vector92:
pushl $0
80105be2: 6a 00 push $0x0
pushl $92
80105be4: 6a 5c push $0x5c
jmp alltraps
80105be6: e9 02 f8 ff ff jmp 801053ed <alltraps>
80105beb <vector93>:
.globl vector93
vector93:
pushl $0
80105beb: 6a 00 push $0x0
pushl $93
80105bed: 6a 5d push $0x5d
jmp alltraps
80105bef: e9 f9 f7 ff ff jmp 801053ed <alltraps>
80105bf4 <vector94>:
.globl vector94
vector94:
pushl $0
80105bf4: 6a 00 push $0x0
pushl $94
80105bf6: 6a 5e push $0x5e
jmp alltraps
80105bf8: e9 f0 f7 ff ff jmp 801053ed <alltraps>
80105bfd <vector95>:
.globl vector95
vector95:
pushl $0
80105bfd: 6a 00 push $0x0
pushl $95
80105bff: 6a 5f push $0x5f
jmp alltraps
80105c01: e9 e7 f7 ff ff jmp 801053ed <alltraps>
80105c06 <vector96>:
.globl vector96
vector96:
pushl $0
80105c06: 6a 00 push $0x0
pushl $96
80105c08: 6a 60 push $0x60
jmp alltraps
80105c0a: e9 de f7 ff ff jmp 801053ed <alltraps>
80105c0f <vector97>:
.globl vector97
vector97:
pushl $0
80105c0f: 6a 00 push $0x0
pushl $97
80105c11: 6a 61 push $0x61
jmp alltraps
80105c13: e9 d5 f7 ff ff jmp 801053ed <alltraps>
80105c18 <vector98>:
.globl vector98
vector98:
pushl $0
80105c18: 6a 00 push $0x0
pushl $98
80105c1a: 6a 62 push $0x62
jmp alltraps
80105c1c: e9 cc f7 ff ff jmp 801053ed <alltraps>
80105c21 <vector99>:
.globl vector99
vector99:
pushl $0
80105c21: 6a 00 push $0x0
pushl $99
80105c23: 6a 63 push $0x63
jmp alltraps
80105c25: e9 c3 f7 ff ff jmp 801053ed <alltraps>
80105c2a <vector100>:
.globl vector100
vector100:
pushl $0
80105c2a: 6a 00 push $0x0
pushl $100
80105c2c: 6a 64 push $0x64
jmp alltraps
80105c2e: e9 ba f7 ff ff jmp 801053ed <alltraps>
80105c33 <vector101>:
.globl vector101
vector101:
pushl $0
80105c33: 6a 00 push $0x0
pushl $101
80105c35: 6a 65 push $0x65
jmp alltraps
80105c37: e9 b1 f7 ff ff jmp 801053ed <alltraps>
80105c3c <vector102>:
.globl vector102
vector102:
pushl $0
80105c3c: 6a 00 push $0x0
pushl $102
80105c3e: 6a 66 push $0x66
jmp alltraps
80105c40: e9 a8 f7 ff ff jmp 801053ed <alltraps>
80105c45 <vector103>:
.globl vector103
vector103:
pushl $0
80105c45: 6a 00 push $0x0
pushl $103
80105c47: 6a 67 push $0x67
jmp alltraps
80105c49: e9 9f f7 ff ff jmp 801053ed <alltraps>
80105c4e <vector104>:
.globl vector104
vector104:
pushl $0
80105c4e: 6a 00 push $0x0
pushl $104
80105c50: 6a 68 push $0x68
jmp alltraps
80105c52: e9 96 f7 ff ff jmp 801053ed <alltraps>
80105c57 <vector105>:
.globl vector105
vector105:
pushl $0
80105c57: 6a 00 push $0x0
pushl $105
80105c59: 6a 69 push $0x69
jmp alltraps
80105c5b: e9 8d f7 ff ff jmp 801053ed <alltraps>
80105c60 <vector106>:
.globl vector106
vector106:
pushl $0
80105c60: 6a 00 push $0x0
pushl $106
80105c62: 6a 6a push $0x6a
jmp alltraps
80105c64: e9 84 f7 ff ff jmp 801053ed <alltraps>
80105c69 <vector107>:
.globl vector107
vector107:
pushl $0
80105c69: 6a 00 push $0x0
pushl $107
80105c6b: 6a 6b push $0x6b
jmp alltraps
80105c6d: e9 7b f7 ff ff jmp 801053ed <alltraps>
80105c72 <vector108>:
.globl vector108
vector108:
pushl $0
80105c72: 6a 00 push $0x0
pushl $108
80105c74: 6a 6c push $0x6c
jmp alltraps
80105c76: e9 72 f7 ff ff jmp 801053ed <alltraps>
80105c7b <vector109>:
.globl vector109
vector109:
pushl $0
80105c7b: 6a 00 push $0x0
pushl $109
80105c7d: 6a 6d push $0x6d
jmp alltraps
80105c7f: e9 69 f7 ff ff jmp 801053ed <alltraps>
80105c84 <vector110>:
.globl vector110
vector110:
pushl $0
80105c84: 6a 00 push $0x0
pushl $110
80105c86: 6a 6e push $0x6e
jmp alltraps
80105c88: e9 60 f7 ff ff jmp 801053ed <alltraps>
80105c8d <vector111>:
.globl vector111
vector111:
pushl $0
80105c8d: 6a 00 push $0x0
pushl $111
80105c8f: 6a 6f push $0x6f
jmp alltraps
80105c91: e9 57 f7 ff ff jmp 801053ed <alltraps>
80105c96 <vector112>:
.globl vector112
vector112:
pushl $0
80105c96: 6a 00 push $0x0
pushl $112
80105c98: 6a 70 push $0x70
jmp alltraps
80105c9a: e9 4e f7 ff ff jmp 801053ed <alltraps>
80105c9f <vector113>:
.globl vector113
vector113:
pushl $0
80105c9f: 6a 00 push $0x0
pushl $113
80105ca1: 6a 71 push $0x71
jmp alltraps
80105ca3: e9 45 f7 ff ff jmp 801053ed <alltraps>
80105ca8 <vector114>:
.globl vector114
vector114:
pushl $0
80105ca8: 6a 00 push $0x0
pushl $114
80105caa: 6a 72 push $0x72
jmp alltraps
80105cac: e9 3c f7 ff ff jmp 801053ed <alltraps>
80105cb1 <vector115>:
.globl vector115
vector115:
pushl $0
80105cb1: 6a 00 push $0x0
pushl $115
80105cb3: 6a 73 push $0x73
jmp alltraps
80105cb5: e9 33 f7 ff ff jmp 801053ed <alltraps>
80105cba <vector116>:
.globl vector116
vector116:
pushl $0
80105cba: 6a 00 push $0x0
pushl $116
80105cbc: 6a 74 push $0x74
jmp alltraps
80105cbe: e9 2a f7 ff ff jmp 801053ed <alltraps>
80105cc3 <vector117>:
.globl vector117
vector117:
pushl $0
80105cc3: 6a 00 push $0x0
pushl $117
80105cc5: 6a 75 push $0x75
jmp alltraps
80105cc7: e9 21 f7 ff ff jmp 801053ed <alltraps>
80105ccc <vector118>:
.globl vector118
vector118:
pushl $0
80105ccc: 6a 00 push $0x0
pushl $118
80105cce: 6a 76 push $0x76
jmp alltraps
80105cd0: e9 18 f7 ff ff jmp 801053ed <alltraps>
80105cd5 <vector119>:
.globl vector119
vector119:
pushl $0
80105cd5: 6a 00 push $0x0
pushl $119
80105cd7: 6a 77 push $0x77
jmp alltraps
80105cd9: e9 0f f7 ff ff jmp 801053ed <alltraps>
80105cde <vector120>:
.globl vector120
vector120:
pushl $0
80105cde: 6a 00 push $0x0
pushl $120
80105ce0: 6a 78 push $0x78
jmp alltraps
80105ce2: e9 06 f7 ff ff jmp 801053ed <alltraps>
80105ce7 <vector121>:
.globl vector121
vector121:
pushl $0
80105ce7: 6a 00 push $0x0
pushl $121
80105ce9: 6a 79 push $0x79
jmp alltraps
80105ceb: e9 fd f6 ff ff jmp 801053ed <alltraps>
80105cf0 <vector122>:
.globl vector122
vector122:
pushl $0
80105cf0: 6a 00 push $0x0
pushl $122
80105cf2: 6a 7a push $0x7a
jmp alltraps
80105cf4: e9 f4 f6 ff ff jmp 801053ed <alltraps>
80105cf9 <vector123>:
.globl vector123
vector123:
pushl $0
80105cf9: 6a 00 push $0x0
pushl $123
80105cfb: 6a 7b push $0x7b
jmp alltraps
80105cfd: e9 eb f6 ff ff jmp 801053ed <alltraps>
80105d02 <vector124>:
.globl vector124
vector124:
pushl $0
80105d02: 6a 00 push $0x0
pushl $124
80105d04: 6a 7c push $0x7c
jmp alltraps
80105d06: e9 e2 f6 ff ff jmp 801053ed <alltraps>
80105d0b <vector125>:
.globl vector125
vector125:
pushl $0
80105d0b: 6a 00 push $0x0
pushl $125
80105d0d: 6a 7d push $0x7d
jmp alltraps
80105d0f: e9 d9 f6 ff ff jmp 801053ed <alltraps>
80105d14 <vector126>:
.globl vector126
vector126:
pushl $0
80105d14: 6a 00 push $0x0
pushl $126
80105d16: 6a 7e push $0x7e
jmp alltraps
80105d18: e9 d0 f6 ff ff jmp 801053ed <alltraps>
80105d1d <vector127>:
.globl vector127
vector127:
pushl $0
80105d1d: 6a 00 push $0x0
pushl $127
80105d1f: 6a 7f push $0x7f
jmp alltraps
80105d21: e9 c7 f6 ff ff jmp 801053ed <alltraps>
80105d26 <vector128>:
.globl vector128
vector128:
pushl $0
80105d26: 6a 00 push $0x0
pushl $128
80105d28: 68 80 00 00 00 push $0x80
jmp alltraps
80105d2d: e9 bb f6 ff ff jmp 801053ed <alltraps>
80105d32 <vector129>:
.globl vector129
vector129:
pushl $0
80105d32: 6a 00 push $0x0
pushl $129
80105d34: 68 81 00 00 00 push $0x81
jmp alltraps
80105d39: e9 af f6 ff ff jmp 801053ed <alltraps>
80105d3e <vector130>:
.globl vector130
vector130:
pushl $0
80105d3e: 6a 00 push $0x0
pushl $130
80105d40: 68 82 00 00 00 push $0x82
jmp alltraps
80105d45: e9 a3 f6 ff ff jmp 801053ed <alltraps>
80105d4a <vector131>:
.globl vector131
vector131:
pushl $0
80105d4a: 6a 00 push $0x0
pushl $131
80105d4c: 68 83 00 00 00 push $0x83
jmp alltraps
80105d51: e9 97 f6 ff ff jmp 801053ed <alltraps>
80105d56 <vector132>:
.globl vector132
vector132:
pushl $0
80105d56: 6a 00 push $0x0
pushl $132
80105d58: 68 84 00 00 00 push $0x84
jmp alltraps
80105d5d: e9 8b f6 ff ff jmp 801053ed <alltraps>
80105d62 <vector133>:
.globl vector133
vector133:
pushl $0
80105d62: 6a 00 push $0x0
pushl $133
80105d64: 68 85 00 00 00 push $0x85
jmp alltraps
80105d69: e9 7f f6 ff ff jmp 801053ed <alltraps>
80105d6e <vector134>:
.globl vector134
vector134:
pushl $0
80105d6e: 6a 00 push $0x0
pushl $134
80105d70: 68 86 00 00 00 push $0x86
jmp alltraps
80105d75: e9 73 f6 ff ff jmp 801053ed <alltraps>
80105d7a <vector135>:
.globl vector135
vector135:
pushl $0
80105d7a: 6a 00 push $0x0
pushl $135
80105d7c: 68 87 00 00 00 push $0x87
jmp alltraps
80105d81: e9 67 f6 ff ff jmp 801053ed <alltraps>
80105d86 <vector136>:
.globl vector136
vector136:
pushl $0
80105d86: 6a 00 push $0x0
pushl $136
80105d88: 68 88 00 00 00 push $0x88
jmp alltraps
80105d8d: e9 5b f6 ff ff jmp 801053ed <alltraps>
80105d92 <vector137>:
.globl vector137
vector137:
pushl $0
80105d92: 6a 00 push $0x0
pushl $137
80105d94: 68 89 00 00 00 push $0x89
jmp alltraps
80105d99: e9 4f f6 ff ff jmp 801053ed <alltraps>
80105d9e <vector138>:
.globl vector138
vector138:
pushl $0
80105d9e: 6a 00 push $0x0
pushl $138
80105da0: 68 8a 00 00 00 push $0x8a
jmp alltraps
80105da5: e9 43 f6 ff ff jmp 801053ed <alltraps>
80105daa <vector139>:
.globl vector139
vector139:
pushl $0
80105daa: 6a 00 push $0x0
pushl $139
80105dac: 68 8b 00 00 00 push $0x8b
jmp alltraps
80105db1: e9 37 f6 ff ff jmp 801053ed <alltraps>
80105db6 <vector140>:
.globl vector140
vector140:
pushl $0
80105db6: 6a 00 push $0x0
pushl $140
80105db8: 68 8c 00 00 00 push $0x8c
jmp alltraps
80105dbd: e9 2b f6 ff ff jmp 801053ed <alltraps>
80105dc2 <vector141>:
.globl vector141
vector141:
pushl $0
80105dc2: 6a 00 push $0x0
pushl $141
80105dc4: 68 8d 00 00 00 push $0x8d
jmp alltraps
80105dc9: e9 1f f6 ff ff jmp 801053ed <alltraps>
80105dce <vector142>:
.globl vector142
vector142:
pushl $0
80105dce: 6a 00 push $0x0
pushl $142
80105dd0: 68 8e 00 00 00 push $0x8e
jmp alltraps
80105dd5: e9 13 f6 ff ff jmp 801053ed <alltraps>
80105dda <vector143>:
.globl vector143
vector143:
pushl $0
80105dda: 6a 00 push $0x0
pushl $143
80105ddc: 68 8f 00 00 00 push $0x8f
jmp alltraps
80105de1: e9 07 f6 ff ff jmp 801053ed <alltraps>
80105de6 <vector144>:
.globl vector144
vector144:
pushl $0
80105de6: 6a 00 push $0x0
pushl $144
80105de8: 68 90 00 00 00 push $0x90
jmp alltraps
80105ded: e9 fb f5 ff ff jmp 801053ed <alltraps>
80105df2 <vector145>:
.globl vector145
vector145:
pushl $0
80105df2: 6a 00 push $0x0
pushl $145
80105df4: 68 91 00 00 00 push $0x91
jmp alltraps
80105df9: e9 ef f5 ff ff jmp 801053ed <alltraps>
80105dfe <vector146>:
.globl vector146
vector146:
pushl $0
80105dfe: 6a 00 push $0x0
pushl $146
80105e00: 68 92 00 00 00 push $0x92
jmp alltraps
80105e05: e9 e3 f5 ff ff jmp 801053ed <alltraps>
80105e0a <vector147>:
.globl vector147
vector147:
pushl $0
80105e0a: 6a 00 push $0x0
pushl $147
80105e0c: 68 93 00 00 00 push $0x93
jmp alltraps
80105e11: e9 d7 f5 ff ff jmp 801053ed <alltraps>
80105e16 <vector148>:
.globl vector148
vector148:
pushl $0
80105e16: 6a 00 push $0x0
pushl $148
80105e18: 68 94 00 00 00 push $0x94
jmp alltraps
80105e1d: e9 cb f5 ff ff jmp 801053ed <alltraps>
80105e22 <vector149>:
.globl vector149
vector149:
pushl $0
80105e22: 6a 00 push $0x0
pushl $149
80105e24: 68 95 00 00 00 push $0x95
jmp alltraps
80105e29: e9 bf f5 ff ff jmp 801053ed <alltraps>
80105e2e <vector150>:
.globl vector150
vector150:
pushl $0
80105e2e: 6a 00 push $0x0
pushl $150
80105e30: 68 96 00 00 00 push $0x96
jmp alltraps
80105e35: e9 b3 f5 ff ff jmp 801053ed <alltraps>
80105e3a <vector151>:
.globl vector151
vector151:
pushl $0
80105e3a: 6a 00 push $0x0
pushl $151
80105e3c: 68 97 00 00 00 push $0x97
jmp alltraps
80105e41: e9 a7 f5 ff ff jmp 801053ed <alltraps>
80105e46 <vector152>:
.globl vector152
vector152:
pushl $0
80105e46: 6a 00 push $0x0
pushl $152
80105e48: 68 98 00 00 00 push $0x98
jmp alltraps
80105e4d: e9 9b f5 ff ff jmp 801053ed <alltraps>
80105e52 <vector153>:
.globl vector153
vector153:
pushl $0
80105e52: 6a 00 push $0x0
pushl $153
80105e54: 68 99 00 00 00 push $0x99
jmp alltraps
80105e59: e9 8f f5 ff ff jmp 801053ed <alltraps>
80105e5e <vector154>:
.globl vector154
vector154:
pushl $0
80105e5e: 6a 00 push $0x0
pushl $154
80105e60: 68 9a 00 00 00 push $0x9a
jmp alltraps
80105e65: e9 83 f5 ff ff jmp 801053ed <alltraps>
80105e6a <vector155>:
.globl vector155
vector155:
pushl $0
80105e6a: 6a 00 push $0x0
pushl $155
80105e6c: 68 9b 00 00 00 push $0x9b
jmp alltraps
80105e71: e9 77 f5 ff ff jmp 801053ed <alltraps>
80105e76 <vector156>:
.globl vector156
vector156:
pushl $0
80105e76: 6a 00 push $0x0
pushl $156
80105e78: 68 9c 00 00 00 push $0x9c
jmp alltraps
80105e7d: e9 6b f5 ff ff jmp 801053ed <alltraps>
80105e82 <vector157>:
.globl vector157
vector157:
pushl $0
80105e82: 6a 00 push $0x0
pushl $157
80105e84: 68 9d 00 00 00 push $0x9d
jmp alltraps
80105e89: e9 5f f5 ff ff jmp 801053ed <alltraps>
80105e8e <vector158>:
.globl vector158
vector158:
pushl $0
80105e8e: 6a 00 push $0x0
pushl $158
80105e90: 68 9e 00 00 00 push $0x9e
jmp alltraps
80105e95: e9 53 f5 ff ff jmp 801053ed <alltraps>
80105e9a <vector159>:
.globl vector159
vector159:
pushl $0
80105e9a: 6a 00 push $0x0
pushl $159
80105e9c: 68 9f 00 00 00 push $0x9f
jmp alltraps
80105ea1: e9 47 f5 ff ff jmp 801053ed <alltraps>
80105ea6 <vector160>:
.globl vector160
vector160:
pushl $0
80105ea6: 6a 00 push $0x0
pushl $160
80105ea8: 68 a0 00 00 00 push $0xa0
jmp alltraps
80105ead: e9 3b f5 ff ff jmp 801053ed <alltraps>
80105eb2 <vector161>:
.globl vector161
vector161:
pushl $0
80105eb2: 6a 00 push $0x0
pushl $161
80105eb4: 68 a1 00 00 00 push $0xa1
jmp alltraps
80105eb9: e9 2f f5 ff ff jmp 801053ed <alltraps>
80105ebe <vector162>:
.globl vector162
vector162:
pushl $0
80105ebe: 6a 00 push $0x0
pushl $162
80105ec0: 68 a2 00 00 00 push $0xa2
jmp alltraps
80105ec5: e9 23 f5 ff ff jmp 801053ed <alltraps>
80105eca <vector163>:
.globl vector163
vector163:
pushl $0
80105eca: 6a 00 push $0x0
pushl $163
80105ecc: 68 a3 00 00 00 push $0xa3
jmp alltraps
80105ed1: e9 17 f5 ff ff jmp 801053ed <alltraps>
80105ed6 <vector164>:
.globl vector164
vector164:
pushl $0
80105ed6: 6a 00 push $0x0
pushl $164
80105ed8: 68 a4 00 00 00 push $0xa4
jmp alltraps
80105edd: e9 0b f5 ff ff jmp 801053ed <alltraps>
80105ee2 <vector165>:
.globl vector165
vector165:
pushl $0
80105ee2: 6a 00 push $0x0
pushl $165
80105ee4: 68 a5 00 00 00 push $0xa5
jmp alltraps
80105ee9: e9 ff f4 ff ff jmp 801053ed <alltraps>
80105eee <vector166>:
.globl vector166
vector166:
pushl $0
80105eee: 6a 00 push $0x0
pushl $166
80105ef0: 68 a6 00 00 00 push $0xa6
jmp alltraps
80105ef5: e9 f3 f4 ff ff jmp 801053ed <alltraps>
80105efa <vector167>:
.globl vector167
vector167:
pushl $0
80105efa: 6a 00 push $0x0
pushl $167
80105efc: 68 a7 00 00 00 push $0xa7
jmp alltraps
80105f01: e9 e7 f4 ff ff jmp 801053ed <alltraps>
80105f06 <vector168>:
.globl vector168
vector168:
pushl $0
80105f06: 6a 00 push $0x0
pushl $168
80105f08: 68 a8 00 00 00 push $0xa8
jmp alltraps
80105f0d: e9 db f4 ff ff jmp 801053ed <alltraps>
80105f12 <vector169>:
.globl vector169
vector169:
pushl $0
80105f12: 6a 00 push $0x0
pushl $169
80105f14: 68 a9 00 00 00 push $0xa9
jmp alltraps
80105f19: e9 cf f4 ff ff jmp 801053ed <alltraps>
80105f1e <vector170>:
.globl vector170
vector170:
pushl $0
80105f1e: 6a 00 push $0x0
pushl $170
80105f20: 68 aa 00 00 00 push $0xaa
jmp alltraps
80105f25: e9 c3 f4 ff ff jmp 801053ed <alltraps>
80105f2a <vector171>:
.globl vector171
vector171:
pushl $0
80105f2a: 6a 00 push $0x0
pushl $171
80105f2c: 68 ab 00 00 00 push $0xab
jmp alltraps
80105f31: e9 b7 f4 ff ff jmp 801053ed <alltraps>
80105f36 <vector172>:
.globl vector172
vector172:
pushl $0
80105f36: 6a 00 push $0x0
pushl $172
80105f38: 68 ac 00 00 00 push $0xac
jmp alltraps
80105f3d: e9 ab f4 ff ff jmp 801053ed <alltraps>
80105f42 <vector173>:
.globl vector173
vector173:
pushl $0
80105f42: 6a 00 push $0x0
pushl $173
80105f44: 68 ad 00 00 00 push $0xad
jmp alltraps
80105f49: e9 9f f4 ff ff jmp 801053ed <alltraps>
80105f4e <vector174>:
.globl vector174
vector174:
pushl $0
80105f4e: 6a 00 push $0x0
pushl $174
80105f50: 68 ae 00 00 00 push $0xae
jmp alltraps
80105f55: e9 93 f4 ff ff jmp 801053ed <alltraps>
80105f5a <vector175>:
.globl vector175
vector175:
pushl $0
80105f5a: 6a 00 push $0x0
pushl $175
80105f5c: 68 af 00 00 00 push $0xaf
jmp alltraps
80105f61: e9 87 f4 ff ff jmp 801053ed <alltraps>
80105f66 <vector176>:
.globl vector176
vector176:
pushl $0
80105f66: 6a 00 push $0x0
pushl $176
80105f68: 68 b0 00 00 00 push $0xb0
jmp alltraps
80105f6d: e9 7b f4 ff ff jmp 801053ed <alltraps>
80105f72 <vector177>:
.globl vector177
vector177:
pushl $0
80105f72: 6a 00 push $0x0
pushl $177
80105f74: 68 b1 00 00 00 push $0xb1
jmp alltraps
80105f79: e9 6f f4 ff ff jmp 801053ed <alltraps>
80105f7e <vector178>:
.globl vector178
vector178:
pushl $0
80105f7e: 6a 00 push $0x0
pushl $178
80105f80: 68 b2 00 00 00 push $0xb2
jmp alltraps
80105f85: e9 63 f4 ff ff jmp 801053ed <alltraps>
80105f8a <vector179>:
.globl vector179
vector179:
pushl $0
80105f8a: 6a 00 push $0x0
pushl $179
80105f8c: 68 b3 00 00 00 push $0xb3
jmp alltraps
80105f91: e9 57 f4 ff ff jmp 801053ed <alltraps>
80105f96 <vector180>:
.globl vector180
vector180:
pushl $0
80105f96: 6a 00 push $0x0
pushl $180
80105f98: 68 b4 00 00 00 push $0xb4
jmp alltraps
80105f9d: e9 4b f4 ff ff jmp 801053ed <alltraps>
80105fa2 <vector181>:
.globl vector181
vector181:
pushl $0
80105fa2: 6a 00 push $0x0
pushl $181
80105fa4: 68 b5 00 00 00 push $0xb5
jmp alltraps
80105fa9: e9 3f f4 ff ff jmp 801053ed <alltraps>
80105fae <vector182>:
.globl vector182
vector182:
pushl $0
80105fae: 6a 00 push $0x0
pushl $182
80105fb0: 68 b6 00 00 00 push $0xb6
jmp alltraps
80105fb5: e9 33 f4 ff ff jmp 801053ed <alltraps>
80105fba <vector183>:
.globl vector183
vector183:
pushl $0
80105fba: 6a 00 push $0x0
pushl $183
80105fbc: 68 b7 00 00 00 push $0xb7
jmp alltraps
80105fc1: e9 27 f4 ff ff jmp 801053ed <alltraps>
80105fc6 <vector184>:
.globl vector184
vector184:
pushl $0
80105fc6: 6a 00 push $0x0
pushl $184
80105fc8: 68 b8 00 00 00 push $0xb8
jmp alltraps
80105fcd: e9 1b f4 ff ff jmp 801053ed <alltraps>
80105fd2 <vector185>:
.globl vector185
vector185:
pushl $0
80105fd2: 6a 00 push $0x0
pushl $185
80105fd4: 68 b9 00 00 00 push $0xb9
jmp alltraps
80105fd9: e9 0f f4 ff ff jmp 801053ed <alltraps>
80105fde <vector186>:
.globl vector186
vector186:
pushl $0
80105fde: 6a 00 push $0x0
pushl $186
80105fe0: 68 ba 00 00 00 push $0xba
jmp alltraps
80105fe5: e9 03 f4 ff ff jmp 801053ed <alltraps>
80105fea <vector187>:
.globl vector187
vector187:
pushl $0
80105fea: 6a 00 push $0x0
pushl $187
80105fec: 68 bb 00 00 00 push $0xbb
jmp alltraps
80105ff1: e9 f7 f3 ff ff jmp 801053ed <alltraps>
80105ff6 <vector188>:
.globl vector188
vector188:
pushl $0
80105ff6: 6a 00 push $0x0
pushl $188
80105ff8: 68 bc 00 00 00 push $0xbc
jmp alltraps
80105ffd: e9 eb f3 ff ff jmp 801053ed <alltraps>
80106002 <vector189>:
.globl vector189
vector189:
pushl $0
80106002: 6a 00 push $0x0
pushl $189
80106004: 68 bd 00 00 00 push $0xbd
jmp alltraps
80106009: e9 df f3 ff ff jmp 801053ed <alltraps>
8010600e <vector190>:
.globl vector190
vector190:
pushl $0
8010600e: 6a 00 push $0x0
pushl $190
80106010: 68 be 00 00 00 push $0xbe
jmp alltraps
80106015: e9 d3 f3 ff ff jmp 801053ed <alltraps>
8010601a <vector191>:
.globl vector191
vector191:
pushl $0
8010601a: 6a 00 push $0x0
pushl $191
8010601c: 68 bf 00 00 00 push $0xbf
jmp alltraps
80106021: e9 c7 f3 ff ff jmp 801053ed <alltraps>
80106026 <vector192>:
.globl vector192
vector192:
pushl $0
80106026: 6a 00 push $0x0
pushl $192
80106028: 68 c0 00 00 00 push $0xc0
jmp alltraps
8010602d: e9 bb f3 ff ff jmp 801053ed <alltraps>
80106032 <vector193>:
.globl vector193
vector193:
pushl $0
80106032: 6a 00 push $0x0
pushl $193
80106034: 68 c1 00 00 00 push $0xc1
jmp alltraps
80106039: e9 af f3 ff ff jmp 801053ed <alltraps>
8010603e <vector194>:
.globl vector194
vector194:
pushl $0
8010603e: 6a 00 push $0x0
pushl $194
80106040: 68 c2 00 00 00 push $0xc2
jmp alltraps
80106045: e9 a3 f3 ff ff jmp 801053ed <alltraps>
8010604a <vector195>:
.globl vector195
vector195:
pushl $0
8010604a: 6a 00 push $0x0
pushl $195
8010604c: 68 c3 00 00 00 push $0xc3
jmp alltraps
80106051: e9 97 f3 ff ff jmp 801053ed <alltraps>
80106056 <vector196>:
.globl vector196
vector196:
pushl $0
80106056: 6a 00 push $0x0
pushl $196
80106058: 68 c4 00 00 00 push $0xc4
jmp alltraps
8010605d: e9 8b f3 ff ff jmp 801053ed <alltraps>
80106062 <vector197>:
.globl vector197
vector197:
pushl $0
80106062: 6a 00 push $0x0
pushl $197
80106064: 68 c5 00 00 00 push $0xc5
jmp alltraps
80106069: e9 7f f3 ff ff jmp 801053ed <alltraps>
8010606e <vector198>:
.globl vector198
vector198:
pushl $0
8010606e: 6a 00 push $0x0
pushl $198
80106070: 68 c6 00 00 00 push $0xc6
jmp alltraps
80106075: e9 73 f3 ff ff jmp 801053ed <alltraps>
8010607a <vector199>:
.globl vector199
vector199:
pushl $0
8010607a: 6a 00 push $0x0
pushl $199
8010607c: 68 c7 00 00 00 push $0xc7
jmp alltraps
80106081: e9 67 f3 ff ff jmp 801053ed <alltraps>
80106086 <vector200>:
.globl vector200
vector200:
pushl $0
80106086: 6a 00 push $0x0
pushl $200
80106088: 68 c8 00 00 00 push $0xc8
jmp alltraps
8010608d: e9 5b f3 ff ff jmp 801053ed <alltraps>
80106092 <vector201>:
.globl vector201
vector201:
pushl $0
80106092: 6a 00 push $0x0
pushl $201
80106094: 68 c9 00 00 00 push $0xc9
jmp alltraps
80106099: e9 4f f3 ff ff jmp 801053ed <alltraps>
8010609e <vector202>:
.globl vector202
vector202:
pushl $0
8010609e: 6a 00 push $0x0
pushl $202
801060a0: 68 ca 00 00 00 push $0xca
jmp alltraps
801060a5: e9 43 f3 ff ff jmp 801053ed <alltraps>
801060aa <vector203>:
.globl vector203
vector203:
pushl $0
801060aa: 6a 00 push $0x0
pushl $203
801060ac: 68 cb 00 00 00 push $0xcb
jmp alltraps
801060b1: e9 37 f3 ff ff jmp 801053ed <alltraps>
801060b6 <vector204>:
.globl vector204
vector204:
pushl $0
801060b6: 6a 00 push $0x0
pushl $204
801060b8: 68 cc 00 00 00 push $0xcc
jmp alltraps
801060bd: e9 2b f3 ff ff jmp 801053ed <alltraps>
801060c2 <vector205>:
.globl vector205
vector205:
pushl $0
801060c2: 6a 00 push $0x0
pushl $205
801060c4: 68 cd 00 00 00 push $0xcd
jmp alltraps
801060c9: e9 1f f3 ff ff jmp 801053ed <alltraps>
801060ce <vector206>:
.globl vector206
vector206:
pushl $0
801060ce: 6a 00 push $0x0
pushl $206
801060d0: 68 ce 00 00 00 push $0xce
jmp alltraps
801060d5: e9 13 f3 ff ff jmp 801053ed <alltraps>
801060da <vector207>:
.globl vector207
vector207:
pushl $0
801060da: 6a 00 push $0x0
pushl $207
801060dc: 68 cf 00 00 00 push $0xcf
jmp alltraps
801060e1: e9 07 f3 ff ff jmp 801053ed <alltraps>
801060e6 <vector208>:
.globl vector208
vector208:
pushl $0
801060e6: 6a 00 push $0x0
pushl $208
801060e8: 68 d0 00 00 00 push $0xd0
jmp alltraps
801060ed: e9 fb f2 ff ff jmp 801053ed <alltraps>
801060f2 <vector209>:
.globl vector209
vector209:
pushl $0
801060f2: 6a 00 push $0x0
pushl $209
801060f4: 68 d1 00 00 00 push $0xd1
jmp alltraps
801060f9: e9 ef f2 ff ff jmp 801053ed <alltraps>
801060fe <vector210>:
.globl vector210
vector210:
pushl $0
801060fe: 6a 00 push $0x0
pushl $210
80106100: 68 d2 00 00 00 push $0xd2
jmp alltraps
80106105: e9 e3 f2 ff ff jmp 801053ed <alltraps>
8010610a <vector211>:
.globl vector211
vector211:
pushl $0
8010610a: 6a 00 push $0x0
pushl $211
8010610c: 68 d3 00 00 00 push $0xd3
jmp alltraps
80106111: e9 d7 f2 ff ff jmp 801053ed <alltraps>
80106116 <vector212>:
.globl vector212
vector212:
pushl $0
80106116: 6a 00 push $0x0
pushl $212
80106118: 68 d4 00 00 00 push $0xd4
jmp alltraps
8010611d: e9 cb f2 ff ff jmp 801053ed <alltraps>
80106122 <vector213>:
.globl vector213
vector213:
pushl $0
80106122: 6a 00 push $0x0
pushl $213
80106124: 68 d5 00 00 00 push $0xd5
jmp alltraps
80106129: e9 bf f2 ff ff jmp 801053ed <alltraps>
8010612e <vector214>:
.globl vector214
vector214:
pushl $0
8010612e: 6a 00 push $0x0
pushl $214
80106130: 68 d6 00 00 00 push $0xd6
jmp alltraps
80106135: e9 b3 f2 ff ff jmp 801053ed <alltraps>
8010613a <vector215>:
.globl vector215
vector215:
pushl $0
8010613a: 6a 00 push $0x0
pushl $215
8010613c: 68 d7 00 00 00 push $0xd7
jmp alltraps
80106141: e9 a7 f2 ff ff jmp 801053ed <alltraps>
80106146 <vector216>:
.globl vector216
vector216:
pushl $0
80106146: 6a 00 push $0x0
pushl $216
80106148: 68 d8 00 00 00 push $0xd8
jmp alltraps
8010614d: e9 9b f2 ff ff jmp 801053ed <alltraps>
80106152 <vector217>:
.globl vector217
vector217:
pushl $0
80106152: 6a 00 push $0x0
pushl $217
80106154: 68 d9 00 00 00 push $0xd9
jmp alltraps
80106159: e9 8f f2 ff ff jmp 801053ed <alltraps>
8010615e <vector218>:
.globl vector218
vector218:
pushl $0
8010615e: 6a 00 push $0x0
pushl $218
80106160: 68 da 00 00 00 push $0xda
jmp alltraps
80106165: e9 83 f2 ff ff jmp 801053ed <alltraps>
8010616a <vector219>:
.globl vector219
vector219:
pushl $0
8010616a: 6a 00 push $0x0
pushl $219
8010616c: 68 db 00 00 00 push $0xdb
jmp alltraps
80106171: e9 77 f2 ff ff jmp 801053ed <alltraps>
80106176 <vector220>:
.globl vector220
vector220:
pushl $0
80106176: 6a 00 push $0x0
pushl $220
80106178: 68 dc 00 00 00 push $0xdc
jmp alltraps
8010617d: e9 6b f2 ff ff jmp 801053ed <alltraps>
80106182 <vector221>:
.globl vector221
vector221:
pushl $0
80106182: 6a 00 push $0x0
pushl $221
80106184: 68 dd 00 00 00 push $0xdd
jmp alltraps
80106189: e9 5f f2 ff ff jmp 801053ed <alltraps>
8010618e <vector222>:
.globl vector222
vector222:
pushl $0
8010618e: 6a 00 push $0x0
pushl $222
80106190: 68 de 00 00 00 push $0xde
jmp alltraps
80106195: e9 53 f2 ff ff jmp 801053ed <alltraps>
8010619a <vector223>:
.globl vector223
vector223:
pushl $0
8010619a: 6a 00 push $0x0
pushl $223
8010619c: 68 df 00 00 00 push $0xdf
jmp alltraps
801061a1: e9 47 f2 ff ff jmp 801053ed <alltraps>
801061a6 <vector224>:
.globl vector224
vector224:
pushl $0
801061a6: 6a 00 push $0x0
pushl $224
801061a8: 68 e0 00 00 00 push $0xe0
jmp alltraps
801061ad: e9 3b f2 ff ff jmp 801053ed <alltraps>
801061b2 <vector225>:
.globl vector225
vector225:
pushl $0
801061b2: 6a 00 push $0x0
pushl $225
801061b4: 68 e1 00 00 00 push $0xe1
jmp alltraps
801061b9: e9 2f f2 ff ff jmp 801053ed <alltraps>
801061be <vector226>:
.globl vector226
vector226:
pushl $0
801061be: 6a 00 push $0x0
pushl $226
801061c0: 68 e2 00 00 00 push $0xe2
jmp alltraps
801061c5: e9 23 f2 ff ff jmp 801053ed <alltraps>
801061ca <vector227>:
.globl vector227
vector227:
pushl $0
801061ca: 6a 00 push $0x0
pushl $227
801061cc: 68 e3 00 00 00 push $0xe3
jmp alltraps
801061d1: e9 17 f2 ff ff jmp 801053ed <alltraps>
801061d6 <vector228>:
.globl vector228
vector228:
pushl $0
801061d6: 6a 00 push $0x0
pushl $228
801061d8: 68 e4 00 00 00 push $0xe4
jmp alltraps
801061dd: e9 0b f2 ff ff jmp 801053ed <alltraps>
801061e2 <vector229>:
.globl vector229
vector229:
pushl $0
801061e2: 6a 00 push $0x0
pushl $229
801061e4: 68 e5 00 00 00 push $0xe5
jmp alltraps
801061e9: e9 ff f1 ff ff jmp 801053ed <alltraps>
801061ee <vector230>:
.globl vector230
vector230:
pushl $0
801061ee: 6a 00 push $0x0
pushl $230
801061f0: 68 e6 00 00 00 push $0xe6
jmp alltraps
801061f5: e9 f3 f1 ff ff jmp 801053ed <alltraps>
801061fa <vector231>:
.globl vector231
vector231:
pushl $0
801061fa: 6a 00 push $0x0
pushl $231
801061fc: 68 e7 00 00 00 push $0xe7
jmp alltraps
80106201: e9 e7 f1 ff ff jmp 801053ed <alltraps>
80106206 <vector232>:
.globl vector232
vector232:
pushl $0
80106206: 6a 00 push $0x0
pushl $232
80106208: 68 e8 00 00 00 push $0xe8
jmp alltraps
8010620d: e9 db f1 ff ff jmp 801053ed <alltraps>
80106212 <vector233>:
.globl vector233
vector233:
pushl $0
80106212: 6a 00 push $0x0
pushl $233
80106214: 68 e9 00 00 00 push $0xe9
jmp alltraps
80106219: e9 cf f1 ff ff jmp 801053ed <alltraps>
8010621e <vector234>:
.globl vector234
vector234:
pushl $0
8010621e: 6a 00 push $0x0
pushl $234
80106220: 68 ea 00 00 00 push $0xea
jmp alltraps
80106225: e9 c3 f1 ff ff jmp 801053ed <alltraps>
8010622a <vector235>:
.globl vector235
vector235:
pushl $0
8010622a: 6a 00 push $0x0
pushl $235
8010622c: 68 eb 00 00 00 push $0xeb
jmp alltraps
80106231: e9 b7 f1 ff ff jmp 801053ed <alltraps>
80106236 <vector236>:
.globl vector236
vector236:
pushl $0
80106236: 6a 00 push $0x0
pushl $236
80106238: 68 ec 00 00 00 push $0xec
jmp alltraps
8010623d: e9 ab f1 ff ff jmp 801053ed <alltraps>
80106242 <vector237>:
.globl vector237
vector237:
pushl $0
80106242: 6a 00 push $0x0
pushl $237
80106244: 68 ed 00 00 00 push $0xed
jmp alltraps
80106249: e9 9f f1 ff ff jmp 801053ed <alltraps>
8010624e <vector238>:
.globl vector238
vector238:
pushl $0
8010624e: 6a 00 push $0x0
pushl $238
80106250: 68 ee 00 00 00 push $0xee
jmp alltraps
80106255: e9 93 f1 ff ff jmp 801053ed <alltraps>
8010625a <vector239>:
.globl vector239
vector239:
pushl $0
8010625a: 6a 00 push $0x0
pushl $239
8010625c: 68 ef 00 00 00 push $0xef
jmp alltraps
80106261: e9 87 f1 ff ff jmp 801053ed <alltraps>
80106266 <vector240>:
.globl vector240
vector240:
pushl $0
80106266: 6a 00 push $0x0
pushl $240
80106268: 68 f0 00 00 00 push $0xf0
jmp alltraps
8010626d: e9 7b f1 ff ff jmp 801053ed <alltraps>
80106272 <vector241>:
.globl vector241
vector241:
pushl $0
80106272: 6a 00 push $0x0
pushl $241
80106274: 68 f1 00 00 00 push $0xf1
jmp alltraps
80106279: e9 6f f1 ff ff jmp 801053ed <alltraps>
8010627e <vector242>:
.globl vector242
vector242:
pushl $0
8010627e: 6a 00 push $0x0
pushl $242
80106280: 68 f2 00 00 00 push $0xf2
jmp alltraps
80106285: e9 63 f1 ff ff jmp 801053ed <alltraps>
8010628a <vector243>:
.globl vector243
vector243:
pushl $0
8010628a: 6a 00 push $0x0
pushl $243
8010628c: 68 f3 00 00 00 push $0xf3
jmp alltraps
80106291: e9 57 f1 ff ff jmp 801053ed <alltraps>
80106296 <vector244>:
.globl vector244
vector244:
pushl $0
80106296: 6a 00 push $0x0
pushl $244
80106298: 68 f4 00 00 00 push $0xf4
jmp alltraps
8010629d: e9 4b f1 ff ff jmp 801053ed <alltraps>
801062a2 <vector245>:
.globl vector245
vector245:
pushl $0
801062a2: 6a 00 push $0x0
pushl $245
801062a4: 68 f5 00 00 00 push $0xf5
jmp alltraps
801062a9: e9 3f f1 ff ff jmp 801053ed <alltraps>
801062ae <vector246>:
.globl vector246
vector246:
pushl $0
801062ae: 6a 00 push $0x0
pushl $246
801062b0: 68 f6 00 00 00 push $0xf6
jmp alltraps
801062b5: e9 33 f1 ff ff jmp 801053ed <alltraps>
801062ba <vector247>:
.globl vector247
vector247:
pushl $0
801062ba: 6a 00 push $0x0
pushl $247
801062bc: 68 f7 00 00 00 push $0xf7
jmp alltraps
801062c1: e9 27 f1 ff ff jmp 801053ed <alltraps>
801062c6 <vector248>:
.globl vector248
vector248:
pushl $0
801062c6: 6a 00 push $0x0
pushl $248
801062c8: 68 f8 00 00 00 push $0xf8
jmp alltraps
801062cd: e9 1b f1 ff ff jmp 801053ed <alltraps>
801062d2 <vector249>:
.globl vector249
vector249:
pushl $0
801062d2: 6a 00 push $0x0
pushl $249
801062d4: 68 f9 00 00 00 push $0xf9
jmp alltraps
801062d9: e9 0f f1 ff ff jmp 801053ed <alltraps>
801062de <vector250>:
.globl vector250
vector250:
pushl $0
801062de: 6a 00 push $0x0
pushl $250
801062e0: 68 fa 00 00 00 push $0xfa
jmp alltraps
801062e5: e9 03 f1 ff ff jmp 801053ed <alltraps>
801062ea <vector251>:
.globl vector251
vector251:
pushl $0
801062ea: 6a 00 push $0x0
pushl $251
801062ec: 68 fb 00 00 00 push $0xfb
jmp alltraps
801062f1: e9 f7 f0 ff ff jmp 801053ed <alltraps>
801062f6 <vector252>:
.globl vector252
vector252:
pushl $0
801062f6: 6a 00 push $0x0
pushl $252
801062f8: 68 fc 00 00 00 push $0xfc
jmp alltraps
801062fd: e9 eb f0 ff ff jmp 801053ed <alltraps>
80106302 <vector253>:
.globl vector253
vector253:
pushl $0
80106302: 6a 00 push $0x0
pushl $253
80106304: 68 fd 00 00 00 push $0xfd
jmp alltraps
80106309: e9 df f0 ff ff jmp 801053ed <alltraps>
8010630e <vector254>:
.globl vector254
vector254:
pushl $0
8010630e: 6a 00 push $0x0
pushl $254
80106310: 68 fe 00 00 00 push $0xfe
jmp alltraps
80106315: e9 d3 f0 ff ff jmp 801053ed <alltraps>
8010631a <vector255>:
.globl vector255
vector255:
pushl $0
8010631a: 6a 00 push $0x0
pushl $255
8010631c: 68 ff 00 00 00 push $0xff
jmp alltraps
80106321: e9 c7 f0 ff ff jmp 801053ed <alltraps>
80106326: 66 90 xchg %ax,%ax
80106328: 66 90 xchg %ax,%ax
8010632a: 66 90 xchg %ax,%ax
8010632c: 66 90 xchg %ax,%ax
8010632e: 66 90 xchg %ax,%ax
80106330 <walkpgdir>:
// Return the address of the PTE in page table pgdir
// that corresponds to virtual address va. If alloc!=0,
// create any required page table pages.
static pte_t *
walkpgdir(pde_t *pgdir, const void *va, int alloc)
{
80106330: 55 push %ebp
80106331: 89 e5 mov %esp,%ebp
80106333: 57 push %edi
80106334: 56 push %esi
80106335: 89 d6 mov %edx,%esi
pde_t *pde;
pte_t *pgtab;
pde = &pgdir[PDX(va)];
80106337: c1 ea 16 shr $0x16,%edx
// Return the address of the PTE in page table pgdir
// that corresponds to virtual address va. If alloc!=0,
// create any required page table pages.
static pte_t *
walkpgdir(pde_t *pgdir, const void *va, int alloc)
{
8010633a: 53 push %ebx
pde_t *pde;
pte_t *pgtab;
pde = &pgdir[PDX(va)];
8010633b: 8d 3c 90 lea (%eax,%edx,4),%edi
// Return the address of the PTE in page table pgdir
// that corresponds to virtual address va. If alloc!=0,
// create any required page table pages.
static pte_t *
walkpgdir(pde_t *pgdir, const void *va, int alloc)
{
8010633e: 83 ec 1c sub $0x1c,%esp
pde_t *pde;
pte_t *pgtab;
pde = &pgdir[PDX(va)];
if(*pde & PTE_P){
80106341: 8b 1f mov (%edi),%ebx
80106343: f6 c3 01 test $0x1,%bl
80106346: 74 28 je 80106370 <walkpgdir+0x40>
pgtab = (pte_t*)P2V(PTE_ADDR(*pde));
80106348: 81 e3 00 f0 ff ff and $0xfffff000,%ebx
8010634e: 81 c3 00 00 00 80 add $0x80000000,%ebx
// The permissions here are overly generous, but they can
// be further restricted by the permissions in the page table
// entries, if necessary.
*pde = V2P(pgtab) | PTE_P | PTE_W | PTE_U;
}
return &pgtab[PTX(va)];
80106354: c1 ee 0a shr $0xa,%esi
}
80106357: 83 c4 1c add $0x1c,%esp
// The permissions here are overly generous, but they can
// be further restricted by the permissions in the page table
// entries, if necessary.
*pde = V2P(pgtab) | PTE_P | PTE_W | PTE_U;
}
return &pgtab[PTX(va)];
8010635a: 89 f2 mov %esi,%edx
8010635c: 81 e2 fc 0f 00 00 and $0xffc,%edx
80106362: 8d 04 13 lea (%ebx,%edx,1),%eax
}
80106365: 5b pop %ebx
80106366: 5e pop %esi
80106367: 5f pop %edi
80106368: 5d pop %ebp
80106369: c3 ret
8010636a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
pde = &pgdir[PDX(va)];
if(*pde & PTE_P){
pgtab = (pte_t*)P2V(PTE_ADDR(*pde));
} else {
if(!alloc || (pgtab = (pte_t*)kalloc()) == 0)
80106370: 85 c9 test %ecx,%ecx
80106372: 74 34 je 801063a8 <walkpgdir+0x78>
80106374: e8 17 c1 ff ff call 80102490 <kalloc>
80106379: 85 c0 test %eax,%eax
8010637b: 89 c3 mov %eax,%ebx
8010637d: 74 29 je 801063a8 <walkpgdir+0x78>
return 0;
// Make sure all those PTE_P bits are zero.
memset(pgtab, 0, PGSIZE);
8010637f: c7 44 24 08 00 10 00 movl $0x1000,0x8(%esp)
80106386: 00
80106387: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
8010638e: 00
8010638f: 89 04 24 mov %eax,(%esp)
80106392: e8 d9 de ff ff call 80104270 <memset>
// The permissions here are overly generous, but they can
// be further restricted by the permissions in the page table
// entries, if necessary.
*pde = V2P(pgtab) | PTE_P | PTE_W | PTE_U;
80106397: 8d 83 00 00 00 80 lea -0x80000000(%ebx),%eax
8010639d: 83 c8 07 or $0x7,%eax
801063a0: 89 07 mov %eax,(%edi)
801063a2: eb b0 jmp 80106354 <walkpgdir+0x24>
801063a4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
}
return &pgtab[PTX(va)];
}
801063a8: 83 c4 1c add $0x1c,%esp
pde = &pgdir[PDX(va)];
if(*pde & PTE_P){
pgtab = (pte_t*)P2V(PTE_ADDR(*pde));
} else {
if(!alloc || (pgtab = (pte_t*)kalloc()) == 0)
return 0;
801063ab: 31 c0 xor %eax,%eax
// be further restricted by the permissions in the page table
// entries, if necessary.
*pde = V2P(pgtab) | PTE_P | PTE_W | PTE_U;
}
return &pgtab[PTX(va)];
}
801063ad: 5b pop %ebx
801063ae: 5e pop %esi
801063af: 5f pop %edi
801063b0: 5d pop %ebp
801063b1: c3 ret
801063b2: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
801063b9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801063c0 <deallocuvm.part.0>:
// Deallocate user pages to bring the process size from oldsz to
// newsz. oldsz and newsz need not be page-aligned, nor does newsz
// need to be less than oldsz. oldsz can be larger than the actual
// process size. Returns the new process size.
int
deallocuvm(pde_t *pgdir, uint oldsz, uint newsz)
801063c0: 55 push %ebp
801063c1: 89 e5 mov %esp,%ebp
801063c3: 57 push %edi
801063c4: 89 c7 mov %eax,%edi
801063c6: 56 push %esi
801063c7: 89 d6 mov %edx,%esi
801063c9: 53 push %ebx
uint a, pa;
if(newsz >= oldsz)
return oldsz;
a = PGROUNDUP(newsz);
801063ca: 8d 99 ff 0f 00 00 lea 0xfff(%ecx),%ebx
// Deallocate user pages to bring the process size from oldsz to
// newsz. oldsz and newsz need not be page-aligned, nor does newsz
// need to be less than oldsz. oldsz can be larger than the actual
// process size. Returns the new process size.
int
deallocuvm(pde_t *pgdir, uint oldsz, uint newsz)
801063d0: 83 ec 1c sub $0x1c,%esp
uint a, pa;
if(newsz >= oldsz)
return oldsz;
a = PGROUNDUP(newsz);
801063d3: 81 e3 00 f0 ff ff and $0xfffff000,%ebx
for(; a < oldsz; a += PGSIZE){
801063d9: 39 d3 cmp %edx,%ebx
// Deallocate user pages to bring the process size from oldsz to
// newsz. oldsz and newsz need not be page-aligned, nor does newsz
// need to be less than oldsz. oldsz can be larger than the actual
// process size. Returns the new process size.
int
deallocuvm(pde_t *pgdir, uint oldsz, uint newsz)
801063db: 89 4d e0 mov %ecx,-0x20(%ebp)
if(newsz >= oldsz)
return oldsz;
a = PGROUNDUP(newsz);
for(; a < oldsz; a += PGSIZE){
801063de: 72 3b jb 8010641b <deallocuvm.part.0+0x5b>
801063e0: eb 5e jmp 80106440 <deallocuvm.part.0+0x80>
801063e2: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
pte = walkpgdir(pgdir, (char*)a, 0);
if(!pte)
a = PGADDR(PDX(a) + 1, 0, 0) - PGSIZE;
else if((*pte & PTE_P) != 0){
801063e8: 8b 10 mov (%eax),%edx
801063ea: f6 c2 01 test $0x1,%dl
801063ed: 74 22 je 80106411 <deallocuvm.part.0+0x51>
pa = PTE_ADDR(*pte);
if(pa == 0)
801063ef: 81 e2 00 f0 ff ff and $0xfffff000,%edx
801063f5: 74 54 je 8010644b <deallocuvm.part.0+0x8b>
panic("kfree");
char *v = P2V(pa);
801063f7: 81 c2 00 00 00 80 add $0x80000000,%edx
kfree(v);
801063fd: 89 14 24 mov %edx,(%esp)
80106400: 89 45 e4 mov %eax,-0x1c(%ebp)
80106403: e8 d8 be ff ff call 801022e0 <kfree>
*pte = 0;
80106408: 8b 45 e4 mov -0x1c(%ebp),%eax
8010640b: c7 00 00 00 00 00 movl $0x0,(%eax)
if(newsz >= oldsz)
return oldsz;
a = PGROUNDUP(newsz);
for(; a < oldsz; a += PGSIZE){
80106411: 81 c3 00 10 00 00 add $0x1000,%ebx
80106417: 39 f3 cmp %esi,%ebx
80106419: 73 25 jae 80106440 <deallocuvm.part.0+0x80>
pte = walkpgdir(pgdir, (char*)a, 0);
8010641b: 31 c9 xor %ecx,%ecx
8010641d: 89 da mov %ebx,%edx
8010641f: 89 f8 mov %edi,%eax
80106421: e8 0a ff ff ff call 80106330 <walkpgdir>
if(!pte)
80106426: 85 c0 test %eax,%eax
80106428: 75 be jne 801063e8 <deallocuvm.part.0+0x28>
a = PGADDR(PDX(a) + 1, 0, 0) - PGSIZE;
8010642a: 81 e3 00 00 c0 ff and $0xffc00000,%ebx
80106430: 81 c3 00 f0 3f 00 add $0x3ff000,%ebx
if(newsz >= oldsz)
return oldsz;
a = PGROUNDUP(newsz);
for(; a < oldsz; a += PGSIZE){
80106436: 81 c3 00 10 00 00 add $0x1000,%ebx
8010643c: 39 f3 cmp %esi,%ebx
8010643e: 72 db jb 8010641b <deallocuvm.part.0+0x5b>
kfree(v);
*pte = 0;
}
}
return newsz;
}
80106440: 8b 45 e0 mov -0x20(%ebp),%eax
80106443: 83 c4 1c add $0x1c,%esp
80106446: 5b pop %ebx
80106447: 5e pop %esi
80106448: 5f pop %edi
80106449: 5d pop %ebp
8010644a: c3 ret
if(!pte)
a = PGADDR(PDX(a) + 1, 0, 0) - PGSIZE;
else if((*pte & PTE_P) != 0){
pa = PTE_ADDR(*pte);
if(pa == 0)
panic("kfree");
8010644b: c7 04 24 06 70 10 80 movl $0x80107006,(%esp)
80106452: e8 09 9f ff ff call 80100360 <panic>
80106457: 89 f6 mov %esi,%esi
80106459: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80106460 <seginit>:
// Set up CPU's kernel segment descriptors.
// Run once on entry on each CPU.
void
seginit(void)
{
80106460: 55 push %ebp
80106461: 89 e5 mov %esp,%ebp
80106463: 83 ec 18 sub $0x18,%esp
// Map "logical" addresses to virtual addresses using identity map.
// Cannot share a CODE descriptor for both kernel and user
// because it would have to have DPL_USR, but the CPU forbids
// an interrupt from CPL=0 to DPL=3.
c = &cpus[cpuid()];
80106466: e8 05 d2 ff ff call 80103670 <cpuid>
c->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);
8010646b: 31 c9 xor %ecx,%ecx
8010646d: ba ff ff ff ff mov $0xffffffff,%edx
// Map "logical" addresses to virtual addresses using identity map.
// Cannot share a CODE descriptor for both kernel and user
// because it would have to have DPL_USR, but the CPU forbids
// an interrupt from CPL=0 to DPL=3.
c = &cpus[cpuid()];
80106472: 69 c0 b0 00 00 00 imul $0xb0,%eax,%eax
80106478: 05 80 27 11 80 add $0x80112780,%eax
c->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);
8010647d: 66 89 50 78 mov %dx,0x78(%eax)
c->gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);
80106481: ba ff ff ff ff mov $0xffffffff,%edx
c->gdt[SEG_UCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, DPL_USER);
c->gdt[SEG_UDATA] = SEG(STA_W, 0, 0xffffffff, DPL_USER);
lgdt(c->gdt, sizeof(c->gdt));
80106486: 83 c0 70 add $0x70,%eax
// Map "logical" addresses to virtual addresses using identity map.
// Cannot share a CODE descriptor for both kernel and user
// because it would have to have DPL_USR, but the CPU forbids
// an interrupt from CPL=0 to DPL=3.
c = &cpus[cpuid()];
c->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);
80106489: 66 89 48 0a mov %cx,0xa(%eax)
c->gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);
8010648d: 31 c9 xor %ecx,%ecx
8010648f: 66 89 50 10 mov %dx,0x10(%eax)
c->gdt[SEG_UCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, DPL_USER);
80106493: ba ff ff ff ff mov $0xffffffff,%edx
// Cannot share a CODE descriptor for both kernel and user
// because it would have to have DPL_USR, but the CPU forbids
// an interrupt from CPL=0 to DPL=3.
c = &cpus[cpuid()];
c->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);
c->gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);
80106498: 66 89 48 12 mov %cx,0x12(%eax)
c->gdt[SEG_UCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, DPL_USER);
8010649c: 31 c9 xor %ecx,%ecx
8010649e: 66 89 50 18 mov %dx,0x18(%eax)
c->gdt[SEG_UDATA] = SEG(STA_W, 0, 0xffffffff, DPL_USER);
801064a2: ba ff ff ff ff mov $0xffffffff,%edx
// because it would have to have DPL_USR, but the CPU forbids
// an interrupt from CPL=0 to DPL=3.
c = &cpus[cpuid()];
c->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);
c->gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);
c->gdt[SEG_UCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, DPL_USER);
801064a7: 66 89 48 1a mov %cx,0x1a(%eax)
c->gdt[SEG_UDATA] = SEG(STA_W, 0, 0xffffffff, DPL_USER);
801064ab: 31 c9 xor %ecx,%ecx
// Map "logical" addresses to virtual addresses using identity map.
// Cannot share a CODE descriptor for both kernel and user
// because it would have to have DPL_USR, but the CPU forbids
// an interrupt from CPL=0 to DPL=3.
c = &cpus[cpuid()];
c->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);
801064ad: c6 40 0d 9a movb $0x9a,0xd(%eax)
801064b1: c6 40 0e cf movb $0xcf,0xe(%eax)
c->gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);
801064b5: c6 40 15 92 movb $0x92,0x15(%eax)
801064b9: c6 40 16 cf movb $0xcf,0x16(%eax)
c->gdt[SEG_UCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, DPL_USER);
801064bd: c6 40 1d fa movb $0xfa,0x1d(%eax)
801064c1: c6 40 1e cf movb $0xcf,0x1e(%eax)
c->gdt[SEG_UDATA] = SEG(STA_W, 0, 0xffffffff, DPL_USER);
801064c5: c6 40 25 f2 movb $0xf2,0x25(%eax)
801064c9: c6 40 26 cf movb $0xcf,0x26(%eax)
801064cd: 66 89 50 20 mov %dx,0x20(%eax)
static inline void
lgdt(struct segdesc *p, int size)
{
volatile ushort pd[3];
pd[0] = size-1;
801064d1: ba 2f 00 00 00 mov $0x2f,%edx
// Map "logical" addresses to virtual addresses using identity map.
// Cannot share a CODE descriptor for both kernel and user
// because it would have to have DPL_USR, but the CPU forbids
// an interrupt from CPL=0 to DPL=3.
c = &cpus[cpuid()];
c->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);
801064d6: c6 40 0c 00 movb $0x0,0xc(%eax)
801064da: c6 40 0f 00 movb $0x0,0xf(%eax)
c->gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);
801064de: c6 40 14 00 movb $0x0,0x14(%eax)
801064e2: c6 40 17 00 movb $0x0,0x17(%eax)
c->gdt[SEG_UCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, DPL_USER);
801064e6: c6 40 1c 00 movb $0x0,0x1c(%eax)
801064ea: c6 40 1f 00 movb $0x0,0x1f(%eax)
c->gdt[SEG_UDATA] = SEG(STA_W, 0, 0xffffffff, DPL_USER);
801064ee: 66 89 48 22 mov %cx,0x22(%eax)
801064f2: c6 40 24 00 movb $0x0,0x24(%eax)
801064f6: c6 40 27 00 movb $0x0,0x27(%eax)
801064fa: 66 89 55 f2 mov %dx,-0xe(%ebp)
pd[1] = (uint)p;
801064fe: 66 89 45 f4 mov %ax,-0xc(%ebp)
pd[2] = (uint)p >> 16;
80106502: c1 e8 10 shr $0x10,%eax
80106505: 66 89 45 f6 mov %ax,-0xa(%ebp)
asm volatile("lgdt (%0)" : : "r" (pd));
80106509: 8d 45 f2 lea -0xe(%ebp),%eax
8010650c: 0f 01 10 lgdtl (%eax)
lgdt(c->gdt, sizeof(c->gdt));
}
8010650f: c9 leave
80106510: c3 ret
80106511: eb 0d jmp 80106520 <mappages>
80106513: 90 nop
80106514: 90 nop
80106515: 90 nop
80106516: 90 nop
80106517: 90 nop
80106518: 90 nop
80106519: 90 nop
8010651a: 90 nop
8010651b: 90 nop
8010651c: 90 nop
8010651d: 90 nop
8010651e: 90 nop
8010651f: 90 nop
80106520 <mappages>:
// Create PTEs for virtual addresses starting at va that refer to
// physical addresses starting at pa. va and size might not
// be page-aligned.
int
mappages(pde_t *pgdir, void *va, uint size, uint pa, int perm)
{
80106520: 55 push %ebp
80106521: 89 e5 mov %esp,%ebp
80106523: 57 push %edi
80106524: 56 push %esi
80106525: 53 push %ebx
80106526: 83 ec 1c sub $0x1c,%esp
80106529: 8b 45 0c mov 0xc(%ebp),%eax
char *a, *last;
pte_t *pte;
a = (char*)PGROUNDDOWN((uint)va);
last = (char*)PGROUNDDOWN(((uint)va) + size - 1);
8010652c: 8b 55 10 mov 0x10(%ebp),%edx
// Create PTEs for virtual addresses starting at va that refer to
// physical addresses starting at pa. va and size might not
// be page-aligned.
int
mappages(pde_t *pgdir, void *va, uint size, uint pa, int perm)
{
8010652f: 8b 7d 14 mov 0x14(%ebp),%edi
for(;;){
if((pte = walkpgdir(pgdir, a, 1)) == 0)
return -1;
if(*pte & PTE_P)
panic("remap");
*pte = pa | perm | PTE_P;
80106532: 83 4d 18 01 orl $0x1,0x18(%ebp)
mappages(pde_t *pgdir, void *va, uint size, uint pa, int perm)
{
char *a, *last;
pte_t *pte;
a = (char*)PGROUNDDOWN((uint)va);
80106536: 89 c3 mov %eax,%ebx
80106538: 81 e3 00 f0 ff ff and $0xfffff000,%ebx
last = (char*)PGROUNDDOWN(((uint)va) + size - 1);
8010653e: 8d 44 10 ff lea -0x1(%eax,%edx,1),%eax
80106542: 29 df sub %ebx,%edi
80106544: 89 45 e4 mov %eax,-0x1c(%ebp)
80106547: 81 65 e4 00 f0 ff ff andl $0xfffff000,-0x1c(%ebp)
8010654e: eb 15 jmp 80106565 <mappages+0x45>
for(;;){
if((pte = walkpgdir(pgdir, a, 1)) == 0)
return -1;
if(*pte & PTE_P)
80106550: f6 00 01 testb $0x1,(%eax)
80106553: 75 3d jne 80106592 <mappages+0x72>
panic("remap");
*pte = pa | perm | PTE_P;
80106555: 0b 75 18 or 0x18(%ebp),%esi
if(a == last)
80106558: 3b 5d e4 cmp -0x1c(%ebp),%ebx
for(;;){
if((pte = walkpgdir(pgdir, a, 1)) == 0)
return -1;
if(*pte & PTE_P)
panic("remap");
*pte = pa | perm | PTE_P;
8010655b: 89 30 mov %esi,(%eax)
if(a == last)
8010655d: 74 29 je 80106588 <mappages+0x68>
break;
a += PGSIZE;
8010655f: 81 c3 00 10 00 00 add $0x1000,%ebx
pte_t *pte;
a = (char*)PGROUNDDOWN((uint)va);
last = (char*)PGROUNDDOWN(((uint)va) + size - 1);
for(;;){
if((pte = walkpgdir(pgdir, a, 1)) == 0)
80106565: 8b 45 08 mov 0x8(%ebp),%eax
80106568: b9 01 00 00 00 mov $0x1,%ecx
8010656d: 89 da mov %ebx,%edx
8010656f: 8d 34 3b lea (%ebx,%edi,1),%esi
80106572: e8 b9 fd ff ff call 80106330 <walkpgdir>
80106577: 85 c0 test %eax,%eax
80106579: 75 d5 jne 80106550 <mappages+0x30>
break;
a += PGSIZE;
pa += PGSIZE;
}
return 0;
}
8010657b: 83 c4 1c add $0x1c,%esp
a = (char*)PGROUNDDOWN((uint)va);
last = (char*)PGROUNDDOWN(((uint)va) + size - 1);
for(;;){
if((pte = walkpgdir(pgdir, a, 1)) == 0)
return -1;
8010657e: b8 ff ff ff ff mov $0xffffffff,%eax
break;
a += PGSIZE;
pa += PGSIZE;
}
return 0;
}
80106583: 5b pop %ebx
80106584: 5e pop %esi
80106585: 5f pop %edi
80106586: 5d pop %ebp
80106587: c3 ret
80106588: 83 c4 1c add $0x1c,%esp
if(a == last)
break;
a += PGSIZE;
pa += PGSIZE;
}
return 0;
8010658b: 31 c0 xor %eax,%eax
}
8010658d: 5b pop %ebx
8010658e: 5e pop %esi
8010658f: 5f pop %edi
80106590: 5d pop %ebp
80106591: c3 ret
last = (char*)PGROUNDDOWN(((uint)va) + size - 1);
for(;;){
if((pte = walkpgdir(pgdir, a, 1)) == 0)
return -1;
if(*pte & PTE_P)
panic("remap");
80106592: c7 04 24 d8 76 10 80 movl $0x801076d8,(%esp)
80106599: e8 c2 9d ff ff call 80100360 <panic>
8010659e: 66 90 xchg %ax,%ax
801065a0 <switchkvm>:
// Switch h/w page table register to the kernel-only page table,
// for when no process is running.
void
switchkvm(void)
{
lcr3(V2P(kpgdir)); // switch to the kernel page table
801065a0: a1 a4 55 11 80 mov 0x801155a4,%eax
// Switch h/w page table register to the kernel-only page table,
// for when no process is running.
void
switchkvm(void)
{
801065a5: 55 push %ebp
801065a6: 89 e5 mov %esp,%ebp
lcr3(V2P(kpgdir)); // switch to the kernel page table
801065a8: 05 00 00 00 80 add $0x80000000,%eax
}
static inline void
lcr3(uint val)
{
asm volatile("movl %0,%%cr3" : : "r" (val));
801065ad: 0f 22 d8 mov %eax,%cr3
}
801065b0: 5d pop %ebp
801065b1: c3 ret
801065b2: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
801065b9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801065c0 <switchuvm>:
// Switch TSS and h/w page table to correspond to process p.
void
switchuvm(struct proc *p)
{
801065c0: 55 push %ebp
801065c1: 89 e5 mov %esp,%ebp
801065c3: 57 push %edi
801065c4: 56 push %esi
801065c5: 53 push %ebx
801065c6: 83 ec 1c sub $0x1c,%esp
801065c9: 8b 75 08 mov 0x8(%ebp),%esi
if(p == 0)
801065cc: 85 f6 test %esi,%esi
801065ce: 0f 84 cd 00 00 00 je 801066a1 <switchuvm+0xe1>
panic("switchuvm: no process");
if(p->kstack == 0)
801065d4: 8b 46 0c mov 0xc(%esi),%eax
801065d7: 85 c0 test %eax,%eax
801065d9: 0f 84 da 00 00 00 je 801066b9 <switchuvm+0xf9>
panic("switchuvm: no kstack");
if(p->pgdir == 0)
801065df: 8b 7e 08 mov 0x8(%esi),%edi
801065e2: 85 ff test %edi,%edi
801065e4: 0f 84 c3 00 00 00 je 801066ad <switchuvm+0xed>
panic("switchuvm: no pgdir");
pushcli();
801065ea: e8 01 db ff ff call 801040f0 <pushcli>
mycpu()->gdt[SEG_TSS] = SEG16(STS_T32A, &mycpu()->ts,
801065ef: e8 fc cf ff ff call 801035f0 <mycpu>
801065f4: 89 c3 mov %eax,%ebx
801065f6: e8 f5 cf ff ff call 801035f0 <mycpu>
801065fb: 89 c7 mov %eax,%edi
801065fd: e8 ee cf ff ff call 801035f0 <mycpu>
80106602: 83 c7 08 add $0x8,%edi
80106605: 89 45 e4 mov %eax,-0x1c(%ebp)
80106608: e8 e3 cf ff ff call 801035f0 <mycpu>
8010660d: 8b 4d e4 mov -0x1c(%ebp),%ecx
80106610: ba 67 00 00 00 mov $0x67,%edx
80106615: 66 89 93 98 00 00 00 mov %dx,0x98(%ebx)
8010661c: 66 89 bb 9a 00 00 00 mov %di,0x9a(%ebx)
80106623: c6 83 9d 00 00 00 99 movb $0x99,0x9d(%ebx)
8010662a: 83 c1 08 add $0x8,%ecx
8010662d: c1 e9 10 shr $0x10,%ecx
80106630: 83 c0 08 add $0x8,%eax
80106633: c1 e8 18 shr $0x18,%eax
80106636: 88 8b 9c 00 00 00 mov %cl,0x9c(%ebx)
8010663c: c6 83 9e 00 00 00 40 movb $0x40,0x9e(%ebx)
80106643: 88 83 9f 00 00 00 mov %al,0x9f(%ebx)
mycpu()->gdt[SEG_TSS].s = 0;
mycpu()->ts.ss0 = SEG_KDATA << 3;
mycpu()->ts.esp0 = (uint)p->kstack + KSTACKSIZE;
// setting IOPL=0 in eflags *and* iomb beyond the tss segment limit
// forbids I/O instructions (e.g., inb and outb) from user space
mycpu()->ts.iomb = (ushort) 0xFFFF;
80106649: bb ff ff ff ff mov $0xffffffff,%ebx
panic("switchuvm: no pgdir");
pushcli();
mycpu()->gdt[SEG_TSS] = SEG16(STS_T32A, &mycpu()->ts,
sizeof(mycpu()->ts)-1, 0);
mycpu()->gdt[SEG_TSS].s = 0;
8010664e: e8 9d cf ff ff call 801035f0 <mycpu>
80106653: 80 a0 9d 00 00 00 ef andb $0xef,0x9d(%eax)
mycpu()->ts.ss0 = SEG_KDATA << 3;
8010665a: e8 91 cf ff ff call 801035f0 <mycpu>
8010665f: b9 10 00 00 00 mov $0x10,%ecx
80106664: 66 89 48 10 mov %cx,0x10(%eax)
mycpu()->ts.esp0 = (uint)p->kstack + KSTACKSIZE;
80106668: e8 83 cf ff ff call 801035f0 <mycpu>
8010666d: 8b 56 0c mov 0xc(%esi),%edx
80106670: 8d 8a 00 10 00 00 lea 0x1000(%edx),%ecx
80106676: 89 48 0c mov %ecx,0xc(%eax)
// setting IOPL=0 in eflags *and* iomb beyond the tss segment limit
// forbids I/O instructions (e.g., inb and outb) from user space
mycpu()->ts.iomb = (ushort) 0xFFFF;
80106679: e8 72 cf ff ff call 801035f0 <mycpu>
8010667e: 66 89 58 6e mov %bx,0x6e(%eax)
}
static inline void
ltr(ushort sel)
{
asm volatile("ltr %0" : : "r" (sel));
80106682: b8 28 00 00 00 mov $0x28,%eax
80106687: 0f 00 d8 ltr %ax
ltr(SEG_TSS << 3);
lcr3(V2P(p->pgdir)); // switch to process's address space
8010668a: 8b 46 08 mov 0x8(%esi),%eax
8010668d: 05 00 00 00 80 add $0x80000000,%eax
}
static inline void
lcr3(uint val)
{
asm volatile("movl %0,%%cr3" : : "r" (val));
80106692: 0f 22 d8 mov %eax,%cr3
popcli();
}
80106695: 83 c4 1c add $0x1c,%esp
80106698: 5b pop %ebx
80106699: 5e pop %esi
8010669a: 5f pop %edi
8010669b: 5d pop %ebp
// setting IOPL=0 in eflags *and* iomb beyond the tss segment limit
// forbids I/O instructions (e.g., inb and outb) from user space
mycpu()->ts.iomb = (ushort) 0xFFFF;
ltr(SEG_TSS << 3);
lcr3(V2P(p->pgdir)); // switch to process's address space
popcli();
8010669c: e9 0f db ff ff jmp 801041b0 <popcli>
// Switch TSS and h/w page table to correspond to process p.
void
switchuvm(struct proc *p)
{
if(p == 0)
panic("switchuvm: no process");
801066a1: c7 04 24 de 76 10 80 movl $0x801076de,(%esp)
801066a8: e8 b3 9c ff ff call 80100360 <panic>
if(p->kstack == 0)
panic("switchuvm: no kstack");
if(p->pgdir == 0)
panic("switchuvm: no pgdir");
801066ad: c7 04 24 09 77 10 80 movl $0x80107709,(%esp)
801066b4: e8 a7 9c ff ff call 80100360 <panic>
switchuvm(struct proc *p)
{
if(p == 0)
panic("switchuvm: no process");
if(p->kstack == 0)
panic("switchuvm: no kstack");
801066b9: c7 04 24 f4 76 10 80 movl $0x801076f4,(%esp)
801066c0: e8 9b 9c ff ff call 80100360 <panic>
801066c5: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
801066c9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
801066d0 <inituvm>:
// Load the initcode into address 0 of pgdir.
// sz must be less than a page.
void
inituvm(pde_t *pgdir, char *init, uint sz)
{
801066d0: 55 push %ebp
801066d1: 89 e5 mov %esp,%ebp
801066d3: 57 push %edi
801066d4: 56 push %esi
801066d5: 53 push %ebx
801066d6: 83 ec 2c sub $0x2c,%esp
801066d9: 8b 75 10 mov 0x10(%ebp),%esi
801066dc: 8b 55 08 mov 0x8(%ebp),%edx
801066df: 8b 7d 0c mov 0xc(%ebp),%edi
char *mem;
if(sz >= PGSIZE)
801066e2: 81 fe ff 0f 00 00 cmp $0xfff,%esi
801066e8: 77 64 ja 8010674e <inituvm+0x7e>
801066ea: 89 55 e4 mov %edx,-0x1c(%ebp)
panic("inituvm: more than a page");
mem = kalloc();
801066ed: e8 9e bd ff ff call 80102490 <kalloc>
memset(mem, 0, PGSIZE);
801066f2: c7 44 24 08 00 10 00 movl $0x1000,0x8(%esp)
801066f9: 00
801066fa: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
80106701: 00
80106702: 89 04 24 mov %eax,(%esp)
{
char *mem;
if(sz >= PGSIZE)
panic("inituvm: more than a page");
mem = kalloc();
80106705: 89 c3 mov %eax,%ebx
memset(mem, 0, PGSIZE);
80106707: e8 64 db ff ff call 80104270 <memset>
mappages(pgdir, 0, PGSIZE, V2P(mem), PTE_W|PTE_U);
8010670c: 8b 55 e4 mov -0x1c(%ebp),%edx
8010670f: 8d 83 00 00 00 80 lea -0x80000000(%ebx),%eax
80106715: c7 44 24 10 06 00 00 movl $0x6,0x10(%esp)
8010671c: 00
8010671d: 89 44 24 0c mov %eax,0xc(%esp)
80106721: c7 44 24 08 00 10 00 movl $0x1000,0x8(%esp)
80106728: 00
80106729: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
80106730: 00
80106731: 89 14 24 mov %edx,(%esp)
80106734: e8 e7 fd ff ff call 80106520 <mappages>
memmove(mem, init, sz);
80106739: 89 75 10 mov %esi,0x10(%ebp)
8010673c: 89 7d 0c mov %edi,0xc(%ebp)
8010673f: 89 5d 08 mov %ebx,0x8(%ebp)
}
80106742: 83 c4 2c add $0x2c,%esp
80106745: 5b pop %ebx
80106746: 5e pop %esi
80106747: 5f pop %edi
80106748: 5d pop %ebp
if(sz >= PGSIZE)
panic("inituvm: more than a page");
mem = kalloc();
memset(mem, 0, PGSIZE);
mappages(pgdir, 0, PGSIZE, V2P(mem), PTE_W|PTE_U);
memmove(mem, init, sz);
80106749: e9 c2 db ff ff jmp 80104310 <memmove>
inituvm(pde_t *pgdir, char *init, uint sz)
{
char *mem;
if(sz >= PGSIZE)
panic("inituvm: more than a page");
8010674e: c7 04 24 1d 77 10 80 movl $0x8010771d,(%esp)
80106755: e8 06 9c ff ff call 80100360 <panic>
8010675a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80106760 <loaduvm>:
// Load a program segment into pgdir. addr must be page-aligned
// and the pages from addr to addr+sz must already be mapped.
int
loaduvm(pde_t *pgdir, char *addr, struct inode *ip, uint offset, uint sz)
{
80106760: 55 push %ebp
80106761: 89 e5 mov %esp,%ebp
80106763: 57 push %edi
80106764: 56 push %esi
80106765: 53 push %ebx
80106766: 83 ec 1c sub $0x1c,%esp
uint i, pa, n;
pte_t *pte;
if((uint) addr % PGSIZE != 0)
80106769: f7 45 0c ff 0f 00 00 testl $0xfff,0xc(%ebp)
80106770: 0f 85 98 00 00 00 jne 8010680e <loaduvm+0xae>
panic("loaduvm: addr must be page aligned");
for(i = 0; i < sz; i += PGSIZE){
80106776: 8b 75 18 mov 0x18(%ebp),%esi
80106779: 31 db xor %ebx,%ebx
8010677b: 85 f6 test %esi,%esi
8010677d: 75 1a jne 80106799 <loaduvm+0x39>
8010677f: eb 77 jmp 801067f8 <loaduvm+0x98>
80106781: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80106788: 81 c3 00 10 00 00 add $0x1000,%ebx
8010678e: 81 ee 00 10 00 00 sub $0x1000,%esi
80106794: 39 5d 18 cmp %ebx,0x18(%ebp)
80106797: 76 5f jbe 801067f8 <loaduvm+0x98>
80106799: 8b 55 0c mov 0xc(%ebp),%edx
if((pte = walkpgdir(pgdir, addr+i, 0)) == 0)
8010679c: 31 c9 xor %ecx,%ecx
8010679e: 8b 45 08 mov 0x8(%ebp),%eax
801067a1: 01 da add %ebx,%edx
801067a3: e8 88 fb ff ff call 80106330 <walkpgdir>
801067a8: 85 c0 test %eax,%eax
801067aa: 74 56 je 80106802 <loaduvm+0xa2>
panic("loaduvm: address should exist");
pa = PTE_ADDR(*pte);
801067ac: 8b 00 mov (%eax),%eax
if(sz - i < PGSIZE)
n = sz - i;
else
n = PGSIZE;
801067ae: bf 00 10 00 00 mov $0x1000,%edi
801067b3: 8b 4d 14 mov 0x14(%ebp),%ecx
if((uint) addr % PGSIZE != 0)
panic("loaduvm: addr must be page aligned");
for(i = 0; i < sz; i += PGSIZE){
if((pte = walkpgdir(pgdir, addr+i, 0)) == 0)
panic("loaduvm: address should exist");
pa = PTE_ADDR(*pte);
801067b6: 25 00 f0 ff ff and $0xfffff000,%eax
if(sz - i < PGSIZE)
n = sz - i;
else
n = PGSIZE;
801067bb: 81 fe 00 10 00 00 cmp $0x1000,%esi
801067c1: 0f 42 fe cmovb %esi,%edi
if(readi(ip, P2V(pa), offset+i, n) != n)
801067c4: 05 00 00 00 80 add $0x80000000,%eax
801067c9: 89 44 24 04 mov %eax,0x4(%esp)
801067cd: 8b 45 10 mov 0x10(%ebp),%eax
801067d0: 01 d9 add %ebx,%ecx
801067d2: 89 7c 24 0c mov %edi,0xc(%esp)
801067d6: 89 4c 24 08 mov %ecx,0x8(%esp)
801067da: 89 04 24 mov %eax,(%esp)
801067dd: e8 6e b1 ff ff call 80101950 <readi>
801067e2: 39 f8 cmp %edi,%eax
801067e4: 74 a2 je 80106788 <loaduvm+0x28>
return -1;
}
return 0;
}
801067e6: 83 c4 1c add $0x1c,%esp
if(sz - i < PGSIZE)
n = sz - i;
else
n = PGSIZE;
if(readi(ip, P2V(pa), offset+i, n) != n)
return -1;
801067e9: b8 ff ff ff ff mov $0xffffffff,%eax
}
return 0;
}
801067ee: 5b pop %ebx
801067ef: 5e pop %esi
801067f0: 5f pop %edi
801067f1: 5d pop %ebp
801067f2: c3 ret
801067f3: 90 nop
801067f4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
801067f8: 83 c4 1c add $0x1c,%esp
else
n = PGSIZE;
if(readi(ip, P2V(pa), offset+i, n) != n)
return -1;
}
return 0;
801067fb: 31 c0 xor %eax,%eax
}
801067fd: 5b pop %ebx
801067fe: 5e pop %esi
801067ff: 5f pop %edi
80106800: 5d pop %ebp
80106801: c3 ret
if((uint) addr % PGSIZE != 0)
panic("loaduvm: addr must be page aligned");
for(i = 0; i < sz; i += PGSIZE){
if((pte = walkpgdir(pgdir, addr+i, 0)) == 0)
panic("loaduvm: address should exist");
80106802: c7 04 24 37 77 10 80 movl $0x80107737,(%esp)
80106809: e8 52 9b ff ff call 80100360 <panic>
{
uint i, pa, n;
pte_t *pte;
if((uint) addr % PGSIZE != 0)
panic("loaduvm: addr must be page aligned");
8010680e: c7 04 24 d8 77 10 80 movl $0x801077d8,(%esp)
80106815: e8 46 9b ff ff call 80100360 <panic>
8010681a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80106820 <allocuvm>:
// Allocate page tables and physical memory to grow process from oldsz to
// newsz, which need not be page aligned. Returns new size or 0 on error.
int
allocuvm(pde_t *pgdir, uint oldsz, uint newsz)
{
80106820: 55 push %ebp
80106821: 89 e5 mov %esp,%ebp
80106823: 57 push %edi
80106824: 56 push %esi
80106825: 53 push %ebx
80106826: 83 ec 2c sub $0x2c,%esp
80106829: 8b 7d 10 mov 0x10(%ebp),%edi
char *mem;
uint a;
if(newsz >= KERNBASE)
8010682c: 85 ff test %edi,%edi
8010682e: 0f 88 8f 00 00 00 js 801068c3 <allocuvm+0xa3>
return 0;
if(newsz < oldsz)
80106834: 3b 7d 0c cmp 0xc(%ebp),%edi
return oldsz;
80106837: 8b 45 0c mov 0xc(%ebp),%eax
char *mem;
uint a;
if(newsz >= KERNBASE)
return 0;
if(newsz < oldsz)
8010683a: 0f 82 85 00 00 00 jb 801068c5 <allocuvm+0xa5>
return oldsz;
a = PGROUNDUP(oldsz);
80106840: 8d 98 ff 0f 00 00 lea 0xfff(%eax),%ebx
80106846: 81 e3 00 f0 ff ff and $0xfffff000,%ebx
for(; a < newsz; a += PGSIZE){
8010684c: 39 df cmp %ebx,%edi
8010684e: 77 57 ja 801068a7 <allocuvm+0x87>
80106850: eb 7e jmp 801068d0 <allocuvm+0xb0>
80106852: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
if(mem == 0){
cprintf("allocuvm out of memory\n");
deallocuvm(pgdir, newsz, oldsz);
return 0;
}
memset(mem, 0, PGSIZE);
80106858: c7 44 24 08 00 10 00 movl $0x1000,0x8(%esp)
8010685f: 00
80106860: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
80106867: 00
80106868: 89 04 24 mov %eax,(%esp)
8010686b: e8 00 da ff ff call 80104270 <memset>
if(mappages(pgdir, (char*)a, PGSIZE, V2P(mem), PTE_W|PTE_U) < 0){
80106870: 8d 86 00 00 00 80 lea -0x80000000(%esi),%eax
80106876: 89 44 24 0c mov %eax,0xc(%esp)
8010687a: 8b 45 08 mov 0x8(%ebp),%eax
8010687d: c7 44 24 10 06 00 00 movl $0x6,0x10(%esp)
80106884: 00
80106885: c7 44 24 08 00 10 00 movl $0x1000,0x8(%esp)
8010688c: 00
8010688d: 89 5c 24 04 mov %ebx,0x4(%esp)
80106891: 89 04 24 mov %eax,(%esp)
80106894: e8 87 fc ff ff call 80106520 <mappages>
80106899: 85 c0 test %eax,%eax
8010689b: 78 43 js 801068e0 <allocuvm+0xc0>
return 0;
if(newsz < oldsz)
return oldsz;
a = PGROUNDUP(oldsz);
for(; a < newsz; a += PGSIZE){
8010689d: 81 c3 00 10 00 00 add $0x1000,%ebx
801068a3: 39 df cmp %ebx,%edi
801068a5: 76 29 jbe 801068d0 <allocuvm+0xb0>
mem = kalloc();
801068a7: e8 e4 bb ff ff call 80102490 <kalloc>
if(mem == 0){
801068ac: 85 c0 test %eax,%eax
if(newsz < oldsz)
return oldsz;
a = PGROUNDUP(oldsz);
for(; a < newsz; a += PGSIZE){
mem = kalloc();
801068ae: 89 c6 mov %eax,%esi
if(mem == 0){
801068b0: 75 a6 jne 80106858 <allocuvm+0x38>
cprintf("allocuvm out of memory\n");
801068b2: c7 04 24 55 77 10 80 movl $0x80107755,(%esp)
801068b9: e8 92 9d ff ff call 80100650 <cprintf>
deallocuvm(pde_t *pgdir, uint oldsz, uint newsz)
{
pte_t *pte;
uint a, pa;
if(newsz >= oldsz)
801068be: 3b 7d 0c cmp 0xc(%ebp),%edi
801068c1: 77 47 ja 8010690a <allocuvm+0xea>
memset(mem, 0, PGSIZE);
if(mappages(pgdir, (char*)a, PGSIZE, V2P(mem), PTE_W|PTE_U) < 0){
cprintf("allocuvm out of memory (2)\n");
deallocuvm(pgdir, newsz, oldsz);
kfree(mem);
return 0;
801068c3: 31 c0 xor %eax,%eax
}
}
return newsz;
}
801068c5: 83 c4 2c add $0x2c,%esp
801068c8: 5b pop %ebx
801068c9: 5e pop %esi
801068ca: 5f pop %edi
801068cb: 5d pop %ebp
801068cc: c3 ret
801068cd: 8d 76 00 lea 0x0(%esi),%esi
801068d0: 83 c4 2c add $0x2c,%esp
801068d3: 89 f8 mov %edi,%eax
801068d5: 5b pop %ebx
801068d6: 5e pop %esi
801068d7: 5f pop %edi
801068d8: 5d pop %ebp
801068d9: c3 ret
801068da: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
deallocuvm(pgdir, newsz, oldsz);
return 0;
}
memset(mem, 0, PGSIZE);
if(mappages(pgdir, (char*)a, PGSIZE, V2P(mem), PTE_W|PTE_U) < 0){
cprintf("allocuvm out of memory (2)\n");
801068e0: c7 04 24 6d 77 10 80 movl $0x8010776d,(%esp)
801068e7: e8 64 9d ff ff call 80100650 <cprintf>
deallocuvm(pde_t *pgdir, uint oldsz, uint newsz)
{
pte_t *pte;
uint a, pa;
if(newsz >= oldsz)
801068ec: 3b 7d 0c cmp 0xc(%ebp),%edi
801068ef: 76 0d jbe 801068fe <allocuvm+0xde>
801068f1: 8b 4d 0c mov 0xc(%ebp),%ecx
801068f4: 89 fa mov %edi,%edx
801068f6: 8b 45 08 mov 0x8(%ebp),%eax
801068f9: e8 c2 fa ff ff call 801063c0 <deallocuvm.part.0>
}
memset(mem, 0, PGSIZE);
if(mappages(pgdir, (char*)a, PGSIZE, V2P(mem), PTE_W|PTE_U) < 0){
cprintf("allocuvm out of memory (2)\n");
deallocuvm(pgdir, newsz, oldsz);
kfree(mem);
801068fe: 89 34 24 mov %esi,(%esp)
80106901: e8 da b9 ff ff call 801022e0 <kfree>
return 0;
80106906: 31 c0 xor %eax,%eax
80106908: eb bb jmp 801068c5 <allocuvm+0xa5>
8010690a: 8b 4d 0c mov 0xc(%ebp),%ecx
8010690d: 89 fa mov %edi,%edx
8010690f: 8b 45 08 mov 0x8(%ebp),%eax
80106912: e8 a9 fa ff ff call 801063c0 <deallocuvm.part.0>
for(; a < newsz; a += PGSIZE){
mem = kalloc();
if(mem == 0){
cprintf("allocuvm out of memory\n");
deallocuvm(pgdir, newsz, oldsz);
return 0;
80106917: 31 c0 xor %eax,%eax
80106919: eb aa jmp 801068c5 <allocuvm+0xa5>
8010691b: 90 nop
8010691c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80106920 <deallocuvm>:
// newsz. oldsz and newsz need not be page-aligned, nor does newsz
// need to be less than oldsz. oldsz can be larger than the actual
// process size. Returns the new process size.
int
deallocuvm(pde_t *pgdir, uint oldsz, uint newsz)
{
80106920: 55 push %ebp
80106921: 89 e5 mov %esp,%ebp
80106923: 8b 55 0c mov 0xc(%ebp),%edx
80106926: 8b 4d 10 mov 0x10(%ebp),%ecx
80106929: 8b 45 08 mov 0x8(%ebp),%eax
pte_t *pte;
uint a, pa;
if(newsz >= oldsz)
8010692c: 39 d1 cmp %edx,%ecx
8010692e: 73 08 jae 80106938 <deallocuvm+0x18>
kfree(v);
*pte = 0;
}
}
return newsz;
}
80106930: 5d pop %ebp
80106931: e9 8a fa ff ff jmp 801063c0 <deallocuvm.part.0>
80106936: 66 90 xchg %ax,%ax
80106938: 89 d0 mov %edx,%eax
8010693a: 5d pop %ebp
8010693b: c3 ret
8010693c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80106940 <freevm>:
// Free a page table and all the physical memory pages
// in the user part.
void
freevm(pde_t *pgdir)
{
80106940: 55 push %ebp
80106941: 89 e5 mov %esp,%ebp
80106943: 56 push %esi
80106944: 53 push %ebx
80106945: 83 ec 10 sub $0x10,%esp
80106948: 8b 75 08 mov 0x8(%ebp),%esi
uint i;
if(pgdir == 0)
8010694b: 85 f6 test %esi,%esi
8010694d: 74 59 je 801069a8 <freevm+0x68>
8010694f: 31 c9 xor %ecx,%ecx
80106951: ba 00 00 00 80 mov $0x80000000,%edx
80106956: 89 f0 mov %esi,%eax
panic("freevm: no pgdir");
deallocuvm(pgdir, KERNBASE, 0);
for(i = 0; i < NPDENTRIES; i++){
80106958: 31 db xor %ebx,%ebx
8010695a: e8 61 fa ff ff call 801063c0 <deallocuvm.part.0>
8010695f: eb 12 jmp 80106973 <freevm+0x33>
80106961: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80106968: 83 c3 01 add $0x1,%ebx
8010696b: 81 fb 00 04 00 00 cmp $0x400,%ebx
80106971: 74 27 je 8010699a <freevm+0x5a>
if(pgdir[i] & PTE_P){
80106973: 8b 14 9e mov (%esi,%ebx,4),%edx
80106976: f6 c2 01 test $0x1,%dl
80106979: 74 ed je 80106968 <freevm+0x28>
char * v = P2V(PTE_ADDR(pgdir[i]));
8010697b: 81 e2 00 f0 ff ff and $0xfffff000,%edx
uint i;
if(pgdir == 0)
panic("freevm: no pgdir");
deallocuvm(pgdir, KERNBASE, 0);
for(i = 0; i < NPDENTRIES; i++){
80106981: 83 c3 01 add $0x1,%ebx
if(pgdir[i] & PTE_P){
char * v = P2V(PTE_ADDR(pgdir[i]));
80106984: 81 c2 00 00 00 80 add $0x80000000,%edx
kfree(v);
8010698a: 89 14 24 mov %edx,(%esp)
8010698d: e8 4e b9 ff ff call 801022e0 <kfree>
uint i;
if(pgdir == 0)
panic("freevm: no pgdir");
deallocuvm(pgdir, KERNBASE, 0);
for(i = 0; i < NPDENTRIES; i++){
80106992: 81 fb 00 04 00 00 cmp $0x400,%ebx
80106998: 75 d9 jne 80106973 <freevm+0x33>
if(pgdir[i] & PTE_P){
char * v = P2V(PTE_ADDR(pgdir[i]));
kfree(v);
}
}
kfree((char*)pgdir);
8010699a: 89 75 08 mov %esi,0x8(%ebp)
}
8010699d: 83 c4 10 add $0x10,%esp
801069a0: 5b pop %ebx
801069a1: 5e pop %esi
801069a2: 5d pop %ebp
if(pgdir[i] & PTE_P){
char * v = P2V(PTE_ADDR(pgdir[i]));
kfree(v);
}
}
kfree((char*)pgdir);
801069a3: e9 38 b9 ff ff jmp 801022e0 <kfree>
freevm(pde_t *pgdir)
{
uint i;
if(pgdir == 0)
panic("freevm: no pgdir");
801069a8: c7 04 24 89 77 10 80 movl $0x80107789,(%esp)
801069af: e8 ac 99 ff ff call 80100360 <panic>
801069b4: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
801069ba: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
801069c0 <setupkvm>:
};
// Set up kernel part of a page table.
pde_t*
setupkvm(void)
{
801069c0: 55 push %ebp
801069c1: 89 e5 mov %esp,%ebp
801069c3: 56 push %esi
801069c4: 53 push %ebx
801069c5: 83 ec 20 sub $0x20,%esp
pde_t *pgdir;
struct kmap *k;
if((pgdir = (pde_t*)kalloc()) == 0)
801069c8: e8 c3 ba ff ff call 80102490 <kalloc>
801069cd: 85 c0 test %eax,%eax
801069cf: 89 c6 mov %eax,%esi
801069d1: 74 75 je 80106a48 <setupkvm+0x88>
return 0;
memset(pgdir, 0, PGSIZE);
801069d3: c7 44 24 08 00 10 00 movl $0x1000,0x8(%esp)
801069da: 00
if (P2V(PHYSTOP) > (void*)DEVSPACE)
panic("PHYSTOP too high");
for(k = kmap; k < &kmap[NELEM(kmap)]; k++)
801069db: bb 20 a4 10 80 mov $0x8010a420,%ebx
pde_t *pgdir;
struct kmap *k;
if((pgdir = (pde_t*)kalloc()) == 0)
return 0;
memset(pgdir, 0, PGSIZE);
801069e0: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
801069e7: 00
801069e8: 89 04 24 mov %eax,(%esp)
801069eb: e8 80 d8 ff ff call 80104270 <memset>
if (P2V(PHYSTOP) > (void*)DEVSPACE)
panic("PHYSTOP too high");
for(k = kmap; k < &kmap[NELEM(kmap)]; k++)
if(mappages(pgdir, k->virt, k->phys_end - k->phys_start,
801069f0: 8b 53 0c mov 0xc(%ebx),%edx
801069f3: 8b 43 04 mov 0x4(%ebx),%eax
801069f6: 89 34 24 mov %esi,(%esp)
801069f9: 89 54 24 10 mov %edx,0x10(%esp)
801069fd: 8b 53 08 mov 0x8(%ebx),%edx
80106a00: 89 44 24 0c mov %eax,0xc(%esp)
80106a04: 29 c2 sub %eax,%edx
80106a06: 8b 03 mov (%ebx),%eax
80106a08: 89 54 24 08 mov %edx,0x8(%esp)
80106a0c: 89 44 24 04 mov %eax,0x4(%esp)
80106a10: e8 0b fb ff ff call 80106520 <mappages>
80106a15: 85 c0 test %eax,%eax
80106a17: 78 17 js 80106a30 <setupkvm+0x70>
if((pgdir = (pde_t*)kalloc()) == 0)
return 0;
memset(pgdir, 0, PGSIZE);
if (P2V(PHYSTOP) > (void*)DEVSPACE)
panic("PHYSTOP too high");
for(k = kmap; k < &kmap[NELEM(kmap)]; k++)
80106a19: 83 c3 10 add $0x10,%ebx
80106a1c: 81 fb 60 a4 10 80 cmp $0x8010a460,%ebx
80106a22: 72 cc jb 801069f0 <setupkvm+0x30>
80106a24: 89 f0 mov %esi,%eax
(uint)k->phys_start, k->perm) < 0) {
freevm(pgdir);
return 0;
}
return pgdir;
}
80106a26: 83 c4 20 add $0x20,%esp
80106a29: 5b pop %ebx
80106a2a: 5e pop %esi
80106a2b: 5d pop %ebp
80106a2c: c3 ret
80106a2d: 8d 76 00 lea 0x0(%esi),%esi
if (P2V(PHYSTOP) > (void*)DEVSPACE)
panic("PHYSTOP too high");
for(k = kmap; k < &kmap[NELEM(kmap)]; k++)
if(mappages(pgdir, k->virt, k->phys_end - k->phys_start,
(uint)k->phys_start, k->perm) < 0) {
freevm(pgdir);
80106a30: 89 34 24 mov %esi,(%esp)
80106a33: e8 08 ff ff ff call 80106940 <freevm>
return 0;
}
return pgdir;
}
80106a38: 83 c4 20 add $0x20,%esp
panic("PHYSTOP too high");
for(k = kmap; k < &kmap[NELEM(kmap)]; k++)
if(mappages(pgdir, k->virt, k->phys_end - k->phys_start,
(uint)k->phys_start, k->perm) < 0) {
freevm(pgdir);
return 0;
80106a3b: 31 c0 xor %eax,%eax
}
return pgdir;
}
80106a3d: 5b pop %ebx
80106a3e: 5e pop %esi
80106a3f: 5d pop %ebp
80106a40: c3 ret
80106a41: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
{
pde_t *pgdir;
struct kmap *k;
if((pgdir = (pde_t*)kalloc()) == 0)
return 0;
80106a48: 31 c0 xor %eax,%eax
80106a4a: eb da jmp 80106a26 <setupkvm+0x66>
80106a4c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80106a50 <kvmalloc>:
// Allocate one page table for the machine for the kernel address
// space for scheduler processes.
void
kvmalloc(void)
{
80106a50: 55 push %ebp
80106a51: 89 e5 mov %esp,%ebp
80106a53: 83 ec 08 sub $0x8,%esp
kpgdir = setupkvm();
80106a56: e8 65 ff ff ff call 801069c0 <setupkvm>
80106a5b: a3 a4 55 11 80 mov %eax,0x801155a4
// Switch h/w page table register to the kernel-only page table,
// for when no process is running.
void
switchkvm(void)
{
lcr3(V2P(kpgdir)); // switch to the kernel page table
80106a60: 05 00 00 00 80 add $0x80000000,%eax
80106a65: 0f 22 d8 mov %eax,%cr3
void
kvmalloc(void)
{
kpgdir = setupkvm();
switchkvm();
}
80106a68: c9 leave
80106a69: c3 ret
80106a6a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80106a70 <clearpteu>:
// Clear PTE_U on a page. Used to create an inaccessible
// page beneath the user stack.
void
clearpteu(pde_t *pgdir, char *uva)
{
80106a70: 55 push %ebp
pte_t *pte;
pte = walkpgdir(pgdir, uva, 0);
80106a71: 31 c9 xor %ecx,%ecx
// Clear PTE_U on a page. Used to create an inaccessible
// page beneath the user stack.
void
clearpteu(pde_t *pgdir, char *uva)
{
80106a73: 89 e5 mov %esp,%ebp
80106a75: 83 ec 18 sub $0x18,%esp
pte_t *pte;
pte = walkpgdir(pgdir, uva, 0);
80106a78: 8b 55 0c mov 0xc(%ebp),%edx
80106a7b: 8b 45 08 mov 0x8(%ebp),%eax
80106a7e: e8 ad f8 ff ff call 80106330 <walkpgdir>
if(pte == 0)
80106a83: 85 c0 test %eax,%eax
80106a85: 74 05 je 80106a8c <clearpteu+0x1c>
panic("clearpteu");
*pte &= ~PTE_U;
80106a87: 83 20 fb andl $0xfffffffb,(%eax)
}
80106a8a: c9 leave
80106a8b: c3 ret
{
pte_t *pte;
pte = walkpgdir(pgdir, uva, 0);
if(pte == 0)
panic("clearpteu");
80106a8c: c7 04 24 9a 77 10 80 movl $0x8010779a,(%esp)
80106a93: e8 c8 98 ff ff call 80100360 <panic>
80106a98: 90 nop
80106a99: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
80106aa0 <copyuvm>:
// Given a parent process's page table, create a copy
// of it for a child.
pde_t*
copyuvm(pde_t *pgdir, uint sz, uint sb)
{
80106aa0: 55 push %ebp
80106aa1: 89 e5 mov %esp,%ebp
80106aa3: 57 push %edi
80106aa4: 56 push %esi
80106aa5: 53 push %ebx
80106aa6: 83 ec 2c sub $0x2c,%esp
pde_t *d;
pte_t *pte;
uint pa, i, flags;
char *mem;
if((d = setupkvm()) == 0)
80106aa9: e8 12 ff ff ff call 801069c0 <setupkvm>
80106aae: 85 c0 test %eax,%eax
80106ab0: 89 45 e0 mov %eax,-0x20(%ebp)
80106ab3: 0f 84 6d 01 00 00 je 80106c26 <copyuvm+0x186>
return 0;
for(i = 0; i < sz; i += PGSIZE){
80106ab9: 8b 45 0c mov 0xc(%ebp),%eax
80106abc: 85 c0 test %eax,%eax
80106abe: 0f 84 ac 00 00 00 je 80106b70 <copyuvm+0xd0>
80106ac4: 31 db xor %ebx,%ebx
80106ac6: eb 51 jmp 80106b19 <copyuvm+0x79>
panic("copyuvm: page not present");
pa = PTE_ADDR(*pte);
flags = PTE_FLAGS(*pte);
if((mem = kalloc()) == 0)
goto bad;
memmove(mem, (char*)P2V(pa), PGSIZE);
80106ac8: 81 c7 00 00 00 80 add $0x80000000,%edi
80106ace: c7 44 24 08 00 10 00 movl $0x1000,0x8(%esp)
80106ad5: 00
80106ad6: 89 7c 24 04 mov %edi,0x4(%esp)
80106ada: 89 04 24 mov %eax,(%esp)
80106add: e8 2e d8 ff ff call 80104310 <memmove>
if(mappages(d, (void*)i, PGSIZE, V2P(mem), flags) < 0)
80106ae2: 8b 45 e4 mov -0x1c(%ebp),%eax
80106ae5: 8d 96 00 00 00 80 lea -0x80000000(%esi),%edx
80106aeb: 89 54 24 0c mov %edx,0xc(%esp)
80106aef: c7 44 24 08 00 10 00 movl $0x1000,0x8(%esp)
80106af6: 00
80106af7: 89 5c 24 04 mov %ebx,0x4(%esp)
80106afb: 89 44 24 10 mov %eax,0x10(%esp)
80106aff: 8b 45 e0 mov -0x20(%ebp),%eax
80106b02: 89 04 24 mov %eax,(%esp)
80106b05: e8 16 fa ff ff call 80106520 <mappages>
80106b0a: 85 c0 test %eax,%eax
80106b0c: 78 4d js 80106b5b <copyuvm+0xbb>
uint pa, i, flags;
char *mem;
if((d = setupkvm()) == 0)
return 0;
for(i = 0; i < sz; i += PGSIZE){
80106b0e: 81 c3 00 10 00 00 add $0x1000,%ebx
80106b14: 39 5d 0c cmp %ebx,0xc(%ebp)
80106b17: 76 57 jbe 80106b70 <copyuvm+0xd0>
if((pte = walkpgdir(pgdir, (void *) i, 0)) == 0)
80106b19: 8b 45 08 mov 0x8(%ebp),%eax
80106b1c: 31 c9 xor %ecx,%ecx
80106b1e: 89 da mov %ebx,%edx
80106b20: e8 0b f8 ff ff call 80106330 <walkpgdir>
80106b25: 85 c0 test %eax,%eax
80106b27: 0f 84 0c 01 00 00 je 80106c39 <copyuvm+0x199>
panic("copyuvm: pte should exist");
if(!(*pte & PTE_P))
80106b2d: 8b 30 mov (%eax),%esi
80106b2f: f7 c6 01 00 00 00 test $0x1,%esi
80106b35: 0f 84 f2 00 00 00 je 80106c2d <copyuvm+0x18d>
panic("copyuvm: page not present");
pa = PTE_ADDR(*pte);
80106b3b: 89 f7 mov %esi,%edi
flags = PTE_FLAGS(*pte);
80106b3d: 81 e6 ff 0f 00 00 and $0xfff,%esi
80106b43: 89 75 e4 mov %esi,-0x1c(%ebp)
for(i = 0; i < sz; i += PGSIZE){
if((pte = walkpgdir(pgdir, (void *) i, 0)) == 0)
panic("copyuvm: pte should exist");
if(!(*pte & PTE_P))
panic("copyuvm: page not present");
pa = PTE_ADDR(*pte);
80106b46: 81 e7 00 f0 ff ff and $0xfffff000,%edi
flags = PTE_FLAGS(*pte);
if((mem = kalloc()) == 0)
80106b4c: e8 3f b9 ff ff call 80102490 <kalloc>
80106b51: 85 c0 test %eax,%eax
80106b53: 89 c6 mov %eax,%esi
80106b55: 0f 85 6d ff ff ff jne 80106ac8 <copyuvm+0x28>
goto bad;
}
return d;
bad:
freevm(d);
80106b5b: 8b 45 e0 mov -0x20(%ebp),%eax
80106b5e: 89 04 24 mov %eax,(%esp)
80106b61: e8 da fd ff ff call 80106940 <freevm>
return 0;
80106b66: 31 c0 xor %eax,%eax
}
80106b68: 83 c4 2c add $0x2c,%esp
80106b6b: 5b pop %ebx
80106b6c: 5e pop %esi
80106b6d: 5f pop %edi
80106b6e: 5d pop %ebp
80106b6f: c3 ret
goto bad;
memmove(mem, (char*)P2V(pa), PGSIZE);
if(mappages(d, (void*)i, PGSIZE, V2P(mem), flags) < 0)
goto bad;
}
for(i = sb; i < (KERNBASE - 4); i += PGSIZE){
80106b70: 81 7d 10 fb ff ff 7f cmpl $0x7ffffffb,0x10(%ebp)
80106b77: 0f 87 9e 00 00 00 ja 80106c1b <copyuvm+0x17b>
80106b7d: 8b 5d 10 mov 0x10(%ebp),%ebx
80106b80: eb 5a jmp 80106bdc <copyuvm+0x13c>
80106b82: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
panic("copyuvm: page not present");
pa = PTE_ADDR(*pte);
flags = PTE_FLAGS(*pte);
if((mem = kalloc()) == 0)
goto bad;
memmove(mem, (char*)P2V(pa), PGSIZE);
80106b88: 81 c7 00 00 00 80 add $0x80000000,%edi
80106b8e: c7 44 24 08 00 10 00 movl $0x1000,0x8(%esp)
80106b95: 00
80106b96: 89 7c 24 04 mov %edi,0x4(%esp)
80106b9a: 89 04 24 mov %eax,(%esp)
80106b9d: e8 6e d7 ff ff call 80104310 <memmove>
if(mappages(d, (void*)i, PGSIZE, V2P(mem), flags) < 0)
80106ba2: 8b 45 e4 mov -0x1c(%ebp),%eax
80106ba5: 8d 96 00 00 00 80 lea -0x80000000(%esi),%edx
80106bab: 89 54 24 0c mov %edx,0xc(%esp)
80106baf: c7 44 24 08 00 10 00 movl $0x1000,0x8(%esp)
80106bb6: 00
80106bb7: 89 5c 24 04 mov %ebx,0x4(%esp)
80106bbb: 89 44 24 10 mov %eax,0x10(%esp)
80106bbf: 8b 45 e0 mov -0x20(%ebp),%eax
80106bc2: 89 04 24 mov %eax,(%esp)
80106bc5: e8 56 f9 ff ff call 80106520 <mappages>
80106bca: 85 c0 test %eax,%eax
80106bcc: 78 8d js 80106b5b <copyuvm+0xbb>
goto bad;
memmove(mem, (char*)P2V(pa), PGSIZE);
if(mappages(d, (void*)i, PGSIZE, V2P(mem), flags) < 0)
goto bad;
}
for(i = sb; i < (KERNBASE - 4); i += PGSIZE){
80106bce: 81 c3 00 10 00 00 add $0x1000,%ebx
80106bd4: 81 fb fb ff ff 7f cmp $0x7ffffffb,%ebx
80106bda: 77 3f ja 80106c1b <copyuvm+0x17b>
if((pte = walkpgdir(pgdir, (void *) i, 0)) == 0)
80106bdc: 8b 45 08 mov 0x8(%ebp),%eax
80106bdf: 31 c9 xor %ecx,%ecx
80106be1: 89 da mov %ebx,%edx
80106be3: e8 48 f7 ff ff call 80106330 <walkpgdir>
80106be8: 85 c0 test %eax,%eax
80106bea: 74 4d je 80106c39 <copyuvm+0x199>
panic("copyuvm: pte should exist");
if(!(*pte & PTE_P))
80106bec: 8b 30 mov (%eax),%esi
80106bee: f7 c6 01 00 00 00 test $0x1,%esi
80106bf4: 74 37 je 80106c2d <copyuvm+0x18d>
panic("copyuvm: page not present");
pa = PTE_ADDR(*pte);
80106bf6: 89 f7 mov %esi,%edi
flags = PTE_FLAGS(*pte);
80106bf8: 81 e6 ff 0f 00 00 and $0xfff,%esi
80106bfe: 89 75 e4 mov %esi,-0x1c(%ebp)
for(i = sb; i < (KERNBASE - 4); i += PGSIZE){
if((pte = walkpgdir(pgdir, (void *) i, 0)) == 0)
panic("copyuvm: pte should exist");
if(!(*pte & PTE_P))
panic("copyuvm: page not present");
pa = PTE_ADDR(*pte);
80106c01: 81 e7 00 f0 ff ff and $0xfffff000,%edi
flags = PTE_FLAGS(*pte);
if((mem = kalloc()) == 0)
80106c07: e8 84 b8 ff ff call 80102490 <kalloc>
80106c0c: 85 c0 test %eax,%eax
80106c0e: 89 c6 mov %eax,%esi
80106c10: 0f 85 72 ff ff ff jne 80106b88 <copyuvm+0xe8>
80106c16: e9 40 ff ff ff jmp 80106b5b <copyuvm+0xbb>
80106c1b: 8b 45 e0 mov -0x20(%ebp),%eax
return d;
bad:
freevm(d);
return 0;
}
80106c1e: 83 c4 2c add $0x2c,%esp
80106c21: 5b pop %ebx
80106c22: 5e pop %esi
80106c23: 5f pop %edi
80106c24: 5d pop %ebp
80106c25: c3 ret
pte_t *pte;
uint pa, i, flags;
char *mem;
if((d = setupkvm()) == 0)
return 0;
80106c26: 31 c0 xor %eax,%eax
80106c28: e9 3b ff ff ff jmp 80106b68 <copyuvm+0xc8>
for(i = 0; i < sz; i += PGSIZE){
if((pte = walkpgdir(pgdir, (void *) i, 0)) == 0)
panic("copyuvm: pte should exist");
if(!(*pte & PTE_P))
panic("copyuvm: page not present");
80106c2d: c7 04 24 be 77 10 80 movl $0x801077be,(%esp)
80106c34: e8 27 97 ff ff call 80100360 <panic>
if((d = setupkvm()) == 0)
return 0;
for(i = 0; i < sz; i += PGSIZE){
if((pte = walkpgdir(pgdir, (void *) i, 0)) == 0)
panic("copyuvm: pte should exist");
80106c39: c7 04 24 a4 77 10 80 movl $0x801077a4,(%esp)
80106c40: e8 1b 97 ff ff call 80100360 <panic>
80106c45: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80106c49: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80106c50 <uva2ka>:
//PAGEBREAK!
// Map user virtual address to kernel address.
char*
uva2ka(pde_t *pgdir, char *uva)
{
80106c50: 55 push %ebp
pte_t *pte;
pte = walkpgdir(pgdir, uva, 0);
80106c51: 31 c9 xor %ecx,%ecx
//PAGEBREAK!
// Map user virtual address to kernel address.
char*
uva2ka(pde_t *pgdir, char *uva)
{
80106c53: 89 e5 mov %esp,%ebp
80106c55: 83 ec 08 sub $0x8,%esp
pte_t *pte;
pte = walkpgdir(pgdir, uva, 0);
80106c58: 8b 55 0c mov 0xc(%ebp),%edx
80106c5b: 8b 45 08 mov 0x8(%ebp),%eax
80106c5e: e8 cd f6 ff ff call 80106330 <walkpgdir>
if((*pte & PTE_P) == 0)
80106c63: 8b 00 mov (%eax),%eax
80106c65: 89 c2 mov %eax,%edx
80106c67: 83 e2 05 and $0x5,%edx
return 0;
if((*pte & PTE_U) == 0)
80106c6a: 83 fa 05 cmp $0x5,%edx
80106c6d: 75 11 jne 80106c80 <uva2ka+0x30>
return 0;
return (char*)P2V(PTE_ADDR(*pte));
80106c6f: 25 00 f0 ff ff and $0xfffff000,%eax
80106c74: 05 00 00 00 80 add $0x80000000,%eax
}
80106c79: c9 leave
80106c7a: c3 ret
80106c7b: 90 nop
80106c7c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
pte = walkpgdir(pgdir, uva, 0);
if((*pte & PTE_P) == 0)
return 0;
if((*pte & PTE_U) == 0)
return 0;
80106c80: 31 c0 xor %eax,%eax
return (char*)P2V(PTE_ADDR(*pte));
}
80106c82: c9 leave
80106c83: c3 ret
80106c84: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
80106c8a: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
80106c90 <copyout>:
// Copy len bytes from p to user address va in page table pgdir.
// Most useful when pgdir is not the current page table.
// uva2ka ensures this only works for PTE_U pages.
int
copyout(pde_t *pgdir, uint va, void *p, uint len)
{
80106c90: 55 push %ebp
80106c91: 89 e5 mov %esp,%ebp
80106c93: 57 push %edi
80106c94: 56 push %esi
80106c95: 53 push %ebx
80106c96: 83 ec 1c sub $0x1c,%esp
80106c99: 8b 5d 14 mov 0x14(%ebp),%ebx
80106c9c: 8b 4d 0c mov 0xc(%ebp),%ecx
80106c9f: 8b 7d 10 mov 0x10(%ebp),%edi
char *buf, *pa0;
uint n, va0;
buf = (char*)p;
while(len > 0){
80106ca2: 85 db test %ebx,%ebx
80106ca4: 75 3a jne 80106ce0 <copyout+0x50>
80106ca6: eb 68 jmp 80106d10 <copyout+0x80>
va0 = (uint)PGROUNDDOWN(va);
pa0 = uva2ka(pgdir, (char*)va0);
if(pa0 == 0)
return -1;
n = PGSIZE - (va - va0);
80106ca8: 8b 4d e4 mov -0x1c(%ebp),%ecx
80106cab: 89 f2 mov %esi,%edx
if(n > len)
n = len;
memmove(pa0 + (va - va0), buf, n);
80106cad: 89 7c 24 04 mov %edi,0x4(%esp)
while(len > 0){
va0 = (uint)PGROUNDDOWN(va);
pa0 = uva2ka(pgdir, (char*)va0);
if(pa0 == 0)
return -1;
n = PGSIZE - (va - va0);
80106cb1: 29 ca sub %ecx,%edx
80106cb3: 81 c2 00 10 00 00 add $0x1000,%edx
80106cb9: 39 da cmp %ebx,%edx
80106cbb: 0f 47 d3 cmova %ebx,%edx
if(n > len)
n = len;
memmove(pa0 + (va - va0), buf, n);
80106cbe: 29 f1 sub %esi,%ecx
80106cc0: 01 c8 add %ecx,%eax
80106cc2: 89 54 24 08 mov %edx,0x8(%esp)
80106cc6: 89 04 24 mov %eax,(%esp)
80106cc9: 89 55 e4 mov %edx,-0x1c(%ebp)
80106ccc: e8 3f d6 ff ff call 80104310 <memmove>
len -= n;
buf += n;
80106cd1: 8b 55 e4 mov -0x1c(%ebp),%edx
va = va0 + PGSIZE;
80106cd4: 8d 8e 00 10 00 00 lea 0x1000(%esi),%ecx
n = PGSIZE - (va - va0);
if(n > len)
n = len;
memmove(pa0 + (va - va0), buf, n);
len -= n;
buf += n;
80106cda: 01 d7 add %edx,%edi
{
char *buf, *pa0;
uint n, va0;
buf = (char*)p;
while(len > 0){
80106cdc: 29 d3 sub %edx,%ebx
80106cde: 74 30 je 80106d10 <copyout+0x80>
va0 = (uint)PGROUNDDOWN(va);
pa0 = uva2ka(pgdir, (char*)va0);
80106ce0: 8b 45 08 mov 0x8(%ebp),%eax
char *buf, *pa0;
uint n, va0;
buf = (char*)p;
while(len > 0){
va0 = (uint)PGROUNDDOWN(va);
80106ce3: 89 ce mov %ecx,%esi
80106ce5: 81 e6 00 f0 ff ff and $0xfffff000,%esi
pa0 = uva2ka(pgdir, (char*)va0);
80106ceb: 89 74 24 04 mov %esi,0x4(%esp)
char *buf, *pa0;
uint n, va0;
buf = (char*)p;
while(len > 0){
va0 = (uint)PGROUNDDOWN(va);
80106cef: 89 4d e4 mov %ecx,-0x1c(%ebp)
pa0 = uva2ka(pgdir, (char*)va0);
80106cf2: 89 04 24 mov %eax,(%esp)
80106cf5: e8 56 ff ff ff call 80106c50 <uva2ka>
if(pa0 == 0)
80106cfa: 85 c0 test %eax,%eax
80106cfc: 75 aa jne 80106ca8 <copyout+0x18>
len -= n;
buf += n;
va = va0 + PGSIZE;
}
return 0;
}
80106cfe: 83 c4 1c add $0x1c,%esp
buf = (char*)p;
while(len > 0){
va0 = (uint)PGROUNDDOWN(va);
pa0 = uva2ka(pgdir, (char*)va0);
if(pa0 == 0)
return -1;
80106d01: b8 ff ff ff ff mov $0xffffffff,%eax
len -= n;
buf += n;
va = va0 + PGSIZE;
}
return 0;
}
80106d06: 5b pop %ebx
80106d07: 5e pop %esi
80106d08: 5f pop %edi
80106d09: 5d pop %ebp
80106d0a: c3 ret
80106d0b: 90 nop
80106d0c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80106d10: 83 c4 1c add $0x1c,%esp
memmove(pa0 + (va - va0), buf, n);
len -= n;
buf += n;
va = va0 + PGSIZE;
}
return 0;
80106d13: 31 c0 xor %eax,%eax
}
80106d15: 5b pop %ebx
80106d16: 5e pop %esi
80106d17: 5f pop %edi
80106d18: 5d pop %ebp
80106d19: c3 ret
80106d1a: 66 90 xchg %ax,%ax
80106d1c: 66 90 xchg %ax,%ax
80106d1e: 66 90 xchg %ax,%ax
80106d20 <shminit>:
char *frame;
int refcnt;
} shm_pages[64];
} shm_table;
void shminit() {
80106d20: 55 push %ebp
80106d21: 89 e5 mov %esp,%ebp
80106d23: 83 ec 18 sub $0x18,%esp
int i;
initlock(&(shm_table.lock), "SHM lock");
80106d26: c7 44 24 04 fc 77 10 movl $0x801077fc,0x4(%esp)
80106d2d: 80
80106d2e: c7 04 24 c0 55 11 80 movl $0x801155c0,(%esp)
80106d35: e8 06 d3 ff ff call 80104040 <initlock>
acquire(&(shm_table.lock));
80106d3a: c7 04 24 c0 55 11 80 movl $0x801155c0,(%esp)
80106d41: e8 ea d3 ff ff call 80104130 <acquire>
80106d46: b8 f4 55 11 80 mov $0x801155f4,%eax
80106d4b: 90 nop
80106d4c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
for (i = 0; i< 64; i++) {
shm_table.shm_pages[i].id =0;
80106d50: c7 00 00 00 00 00 movl $0x0,(%eax)
80106d56: 83 c0 0c add $0xc,%eax
shm_table.shm_pages[i].frame =0;
80106d59: c7 40 f8 00 00 00 00 movl $0x0,-0x8(%eax)
shm_table.shm_pages[i].refcnt =0;
80106d60: c7 40 fc 00 00 00 00 movl $0x0,-0x4(%eax)
void shminit() {
int i;
initlock(&(shm_table.lock), "SHM lock");
acquire(&(shm_table.lock));
for (i = 0; i< 64; i++) {
80106d67: 3d f4 58 11 80 cmp $0x801158f4,%eax
80106d6c: 75 e2 jne 80106d50 <shminit+0x30>
shm_table.shm_pages[i].id =0;
shm_table.shm_pages[i].frame =0;
shm_table.shm_pages[i].refcnt =0;
}
release(&(shm_table.lock));
80106d6e: c7 04 24 c0 55 11 80 movl $0x801155c0,(%esp)
80106d75: e8 a6 d4 ff ff call 80104220 <release>
}
80106d7a: c9 leave
80106d7b: c3 ret
80106d7c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80106d80 <shm_open>:
int shm_open(int id, char **pointer) {
80106d80: 55 push %ebp
return 0; //added to remove compiler warning -- you should decide what to return
}
80106d81: 31 c0 xor %eax,%eax
shm_table.shm_pages[i].refcnt =0;
}
release(&(shm_table.lock));
}
int shm_open(int id, char **pointer) {
80106d83: 89 e5 mov %esp,%ebp
return 0; //added to remove compiler warning -- you should decide what to return
}
80106d85: 5d pop %ebp
80106d86: c3 ret
80106d87: 89 f6 mov %esi,%esi
80106d89: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
80106d90 <shm_close>:
int shm_close(int id) {
80106d90: 55 push %ebp
return 0; //added to remove compiler warning -- you should decide what to return
}
80106d91: 31 c0 xor %eax,%eax
return 0; //added to remove compiler warning -- you should decide what to return
}
int shm_close(int id) {
80106d93: 89 e5 mov %esp,%ebp
return 0; //added to remove compiler warning -- you should decide what to return
}
80106d95: 5d pop %ebp
80106d96: c3 ret
| 33.022834 | 91 | 0.53742 |
9cdaa72219bc5ce7ef1d759ac583b2da1f102c8f | 684 | asm | Assembly | experimental-computer-system/Font3x5/fonttable.asm | paulscottrobson/assorted-archives | 87ce21ef1556bed441fffbb5c4c3c11c06324385 | [
"MIT"
] | null | null | null | experimental-computer-system/Font3x5/fonttable.asm | paulscottrobson/assorted-archives | 87ce21ef1556bed441fffbb5c4c3c11c06324385 | [
"MIT"
] | null | null | null | experimental-computer-system/Font3x5/fonttable.asm | paulscottrobson/assorted-archives | 87ce21ef1556bed441fffbb5c4c3c11c06324385 | [
"MIT"
] | 1 | 2020-01-02T13:54:19.000Z | 2020-01-02T13:54:19.000Z | dw 22223
dw 63451
dw 63327
dw 62031
dw 55005
dw 62415
dw 62409
dw 62175
dw 47067
dw 59695
dw 58591
dw 46939
dw 37455
dw 49115
dw 63195
dw 63199
dw 63433
dw 63379
dw 63467
dw 62367
dw 59685
dw 46815
dw 46805
dw 47099
dw 46427
dw 46373
dw 58703
dw 62031
dw 37139
dw 58527
dw 23845
dw 15
dw 1
dw 18693
dw 46081
dw 48891
dw 24181
dw 42315
dw 22359
dw 18433
dw 10531
dw 35113
dw 43947
dw 19365
dw 41
dw 897
dw 33
dw 9545
dw 63199
dw 22831
dw 59343
dw 59295
dw 46995
dw 62367
dw 62431
dw 58515
dw 63455
dw 63391
dw 2081
dw 2089
dw 10787
dw 7281
dw 34985
dw 58757 | 10.6875 | 10 | 0.627193 |
af5734858ca6b7c3b89d886d0b8947beca269931 | 1,600 | asm | Assembly | boot/pikos_bootsect.asm | pikobyte/pikos | ab60ddcde8133690e22dad374ab2055210daf6e2 | [
"MIT"
] | 1 | 2020-04-19T20:09:24.000Z | 2020-04-19T20:09:24.000Z | boot/pikos_bootsect.asm | pikobyte/pikos | ab60ddcde8133690e22dad374ab2055210daf6e2 | [
"MIT"
] | 1 | 2018-09-25T18:43:42.000Z | 2018-09-25T18:43:42.000Z | boot/pikos_bootsect.asm | pikobyte/pikos | ab60ddcde8133690e22dad374ab2055210daf6e2 | [
"MIT"
] | 2 | 2018-09-26T07:58:16.000Z | 2018-09-27T14:36:03.000Z | ;
; pikos_bootsect.asm
;
; pikOS boot sector which switches to 32-bit protected mode and launches the
; kernel.
; Bootloader offset.
[org 0x7c00]
KERNEL_OFFSET equ 0x1000 ; Set a location to link the kernel
mov [BOOT_DRIVE], dl ; Set boot drive.
mov bp, 0x9000
mov sp, bp ; Set the stack
mov bx, MSG_REAL_MODE
call print_str ; Print boot mode.
call print_ln
call load_kernel ; Read the kernel.
call switch_to_pm ; 32-bit mode.
jmp $
; Include necessary files for used functions.
%include "boot/pikos_print_str.asm"
%include "boot/pikos_print_hex.asm"
%include "boot/pikos_print32.asm"
%include "boot/pikos_disk.asm"
%include "boot/pikos_gdt.asm"
%include "boot/pikos_switch.asm"
; Load the kernel from the drive.
[bits 16]
load_kernel:
mov bx, MSG_LOAD_KERNEL
call print_str
call print_ln
mov bx, KERNEL_OFFSET ; Read the kernel from the
mov dh, 16 ; disc and store at the
mov dl, [BOOT_DRIVE] ; 16 sectors at 0x1000
call disk_load
ret
; Hand over control to the kernel.
[bits 32]
BEGIN_PM:
mov ebx, MSG_PROT_MODE
call print_string_pm ; Print 32-bit switch message
call KERNEL_OFFSET ; Gives control to the kernel
jmp $
; Message declarations.
MSG_REAL_MODE db "Started in 16-bit real mode", 0
MSG_PROT_MODE db "Loaded 32-bit protected mode", 0
MSG_LOAD_KERNEL db "Loading kernel into memory", 0
; Declare memory for the boot drive.
BOOT_DRIVE db 0
; Create the boot-sector.
times 510-($-$$) db 0
dw 0xaa55 | 22.857143 | 76 | 0.675 |
ee4998d93578f29a2545386cc189a88e6187b26a | 324 | asm | Assembly | programs/oeis/139/A139154.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/139/A139154.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/139/A139154.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A139154: Natural numbers of the form (n!+7)/7.
; 721,5761,51841,518401,5702401,68428801,889574401,12454041601,186810624001,2988969984001,50812489728001,914624815104001,17377871486976001,347557429739520001,7298706024529920001
add $0,7
mov $1,2
lpb $0
mul $1,$0
sub $0,1
lpe
sub $1,10080
div $1,14
add $1,721
mov $0,$1
| 23.142857 | 177 | 0.765432 |
766e6af8f110dbf98ac03d6dfc03b6489d0cbd4a | 945 | asm | Assembly | verify/alfy/7_bonus/access_with_struct_element.alfy.asm | alexandruradovici/alf-alfy-asm-public | 43a73cc13c38f39125620fb9bd566c261cff1c73 | [
"BSD-2-Clause"
] | 3 | 2019-02-11T11:12:54.000Z | 2019-03-25T12:05:59.000Z | verify/alfy/7_bonus/access_with_struct_element.alfy.asm | alexandruradovici/alf-alfy-asm-public | 43a73cc13c38f39125620fb9bd566c261cff1c73 | [
"BSD-2-Clause"
] | 105 | 2019-02-25T15:35:52.000Z | 2020-05-31T14:32:07.000Z | verify/alfy/7_bonus/access_with_struct_element.alfy.asm | alexandruradovici/alf-alfy-asm-language-public | 43a73cc13c38f39125620fb9bd566c261cff1c73 | [
"BSD-2-Clause"
] | 21 | 2016-03-29T18:27:21.000Z | 2016-05-11T19:46:03.000Z |
; script
start:
; asm
readnumber r2
; element of struct structure: r3 element position
; s: r4
set r4 36
set r5 0
add r3 r4 r5
store r3 r2
; asm
readnumber r2
; element of array int: r3
; v: r4
set r4 0
; element of struct structure: r5 element position
; s: r6
set r6 36
set r7 0
add r5 r6 r7
load r5 r5
set r6 4
mul r5 r5 r6
add r3 r4 r5
store r3 r2
; asm
; element of array int: r2
; v: r3
set r3 0
; element of struct structure: r4 element position
; s: r5
set r5 36
set r6 0
add r4 r5 r6
load r4 r4
set r5 4
mul r4 r4 r5
add r2 r3 r4
load r2 r2
writenumber r2
stop | 22.5 | 62 | 0.428571 |
28615cca45c8b083129a351ce14bd8e406a9c1cf | 1,726 | asm | Assembly | programs/oeis/136/A136119.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/136/A136119.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/136/A136119.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A136119: Limiting sequence when we start with the positive integers (A000027) and delete in step n >= 1 the term at position n + a(n).
; 1,3,4,5,7,8,10,11,13,14,15,17,18,20,21,22,24,25,27,28,29,31,32,34,35,37,38,39,41,42,44,45,46,48,49,51,52,54,55,56,58,59,61,62,63,65,66,68,69,71,72,73,75,76,78,79,80,82,83,85,86,87,89,90,92,93,95,96,97,99,100,102,103,104,106,107,109,110,112,113,114,116,117,119,120,121,123,124,126,127,128,130,131,133,134,136,137,138,140,141,143,144,145,147,148,150,151,153,154,155,157,158,160,161,162,164,165,167,168,169,171,172,174,175,177,178,179,181,182,184,185,186,188,189,191,192,194,195,196,198,199,201,202,203,205,206,208,209,211,212,213,215,216,218,219,220,222,223,225,226,227,229,230,232,233,235,236,237,239,240,242,243,244,246,247,249,250,252,253,254,256,257,259,260,261,263,264,266,267,268,270,271,273,274,276,277,278,280,281,283,284,285,287,288,290,291,293,294,295,297,298,300,301,302,304,305,307,308,310,311,312,314,315,317,318,319,321,322,324,325,326,328,329,331,332,334,335,336,338,339,341,342,343,345,346,348,349,351,352,353
mov $3,$0
add $3,1
mov $5,$0
lpb $3,1
mov $0,$5
sub $3,1
sub $0,$3
mov $10,2
mov $12,$0
lpb $10,1
mov $0,$12
sub $10,1
add $0,$10
sub $0,1
mov $2,3
mov $6,$0
mul $6,$0
mov $7,$0
add $7,$0
add $7,1
mov $9,$0
lpb $2,1
add $0,$2
lpb $6,1
add $0,2
add $7,2
trn $6,$7
lpe
mov $2,1
lpe
add $0,5
mov $4,$0
sub $4,10
mov $11,$9
mul $11,5
add $4,$11
div $4,2
mov $8,$10
lpb $8,1
sub $8,1
mov $13,$4
lpe
lpe
lpb $12,1
mov $12,0
sub $13,$4
lpe
mov $4,$13
trn $4,3
add $4,1
add $1,$4
lpe
| 30.821429 | 925 | 0.60197 |
7169011b447a6c2b5fa1a503ee450131d74812b5 | 2,986 | asm | Assembly | 08/asm/FibonacciElement.asm | Bozar/Nand2Tetris | 5f91805823b7572263bc31b0b4537aed14d6b4e7 | [
"MIT"
] | 3 | 2019-12-04T12:17:32.000Z | 2021-08-04T07:08:24.000Z | 08/asm/FibonacciElement.asm | Bozar/Nand2Tetris | 5f91805823b7572263bc31b0b4537aed14d6b4e7 | [
"MIT"
] | null | null | null | 08/asm/FibonacciElement.asm | Bozar/Nand2Tetris | 5f91805823b7572263bc31b0b4537aed14d6b4e7 | [
"MIT"
] | 1 | 2021-07-31T16:01:22.000Z | 2021-07-31T16:01:22.000Z | @256
D=A
@SP
M=D
@RETURN_ADDRESS$Sys.init$bootstrap
D=A
@SP
A=M
M=D
@SP
M=M+1
@LCL
D=M
@SP
A=M
M=D
@SP
M=M+1
@ARG
D=M
@SP
A=M
M=D
@SP
M=M+1
@THIS
D=M
@SP
A=M
M=D
@SP
M=M+1
@THAT
D=M
@SP
A=M
M=D
@SP
M=M+1
@SP
D=M
@0
D=D-A
@5
D=D-A
@ARG
M=D
@SP
D=M
@LCL
M=D
@Sys.init
0;JMP
(RETURN_ADDRESS$Sys.init$bootstrap)
(Main.fibonacci)
@R13
M=D
@ARG
D=M
@0
D=D+A
@R14
M=D
@R13
D=M
@R14
A=M
D=M
@SP
A=M
M=D
@SP
M=M+1
@2
D=A
@SP
A=M
M=D
@SP
M=M+1
@SP
M=M-1
@SP
A=M
D=M
@SP
M=M-1
@SP
A=M
D=M-D
@ARITHMETIC_TRUE_0
D;JLT
@0
D=A
@ARITHMETIC_END_0
0;JMP
(ARITHMETIC_TRUE_0)
@0
D=!A
(ARITHMETIC_END_0)
@SP
A=M
M=D
@SP
M=M+1
@SP
M=M-1
@SP
A=M
D=M
@Main.fibonacci$IF_TRUE
D;JNE
@Main.fibonacci$IF_FALSE
0;JMP
(Main.fibonacci$IF_TRUE)
@R13
M=D
@ARG
D=M
@0
D=D+A
@R14
M=D
@R13
D=M
@R14
A=M
D=M
@SP
A=M
M=D
@SP
M=M+1
@LCL
D=M
@TEMP_SAVE_FRAME
M=D
@5
D=A
@TEMP_SAVE_FRAME
D=M-D
A=D
D=M
@TEMP_SAVE_RET_ADDRESS
M=D
@SP
M=M-1
@SP
A=M
D=M
@R13
M=D
@ARG
D=M
@0
D=D+A
@R14
M=D
@R13
D=M
@R14
A=M
M=D
@ARG
D=M+1
@SP
M=D
@TEMP_SAVE_FRAME
A=M-1
D=M
@THAT
M=D
@2
D=A
@TEMP_SAVE_FRAME
A=M-D
D=M
@THIS
M=D
@3
D=A
@TEMP_SAVE_FRAME
A=M-D
D=M
@ARG
M=D
@4
D=A
@TEMP_SAVE_FRAME
A=M-D
D=M
@LCL
M=D
@TEMP_SAVE_RET_ADDRESS
A=M
0;JMP
(Main.fibonacci$IF_FALSE)
@R13
M=D
@ARG
D=M
@0
D=D+A
@R14
M=D
@R13
D=M
@R14
A=M
D=M
@SP
A=M
M=D
@SP
M=M+1
@2
D=A
@SP
A=M
M=D
@SP
M=M+1
@SP
M=M-1
@SP
A=M
D=M
@SP
M=M-1
@SP
A=M
D=M-D
@SP
A=M
M=D
@SP
M=M+1
@RETURN_ADDRESS$Main.fibonacci$1
D=A
@SP
A=M
M=D
@SP
M=M+1
@LCL
D=M
@SP
A=M
M=D
@SP
M=M+1
@ARG
D=M
@SP
A=M
M=D
@SP
M=M+1
@THIS
D=M
@SP
A=M
M=D
@SP
M=M+1
@THAT
D=M
@SP
A=M
M=D
@SP
M=M+1
@SP
D=M
@1
D=D-A
@5
D=D-A
@ARG
M=D
@SP
D=M
@LCL
M=D
@Main.fibonacci
0;JMP
(RETURN_ADDRESS$Main.fibonacci$1)
@R13
M=D
@ARG
D=M
@0
D=D+A
@R14
M=D
@R13
D=M
@R14
A=M
D=M
@SP
A=M
M=D
@SP
M=M+1
@1
D=A
@SP
A=M
M=D
@SP
M=M+1
@SP
M=M-1
@SP
A=M
D=M
@SP
M=M-1
@SP
A=M
D=M-D
@SP
A=M
M=D
@SP
M=M+1
@RETURN_ADDRESS$Main.fibonacci$2
D=A
@SP
A=M
M=D
@SP
M=M+1
@LCL
D=M
@SP
A=M
M=D
@SP
M=M+1
@ARG
D=M
@SP
A=M
M=D
@SP
M=M+1
@THIS
D=M
@SP
A=M
M=D
@SP
M=M+1
@THAT
D=M
@SP
A=M
M=D
@SP
M=M+1
@SP
D=M
@1
D=D-A
@5
D=D-A
@ARG
M=D
@SP
D=M
@LCL
M=D
@Main.fibonacci
0;JMP
(RETURN_ADDRESS$Main.fibonacci$2)
@SP
M=M-1
@SP
A=M
D=M
@SP
M=M-1
@SP
A=M
D=D+M
@SP
A=M
M=D
@SP
M=M+1
@LCL
D=M
@TEMP_SAVE_FRAME
M=D
@5
D=A
@TEMP_SAVE_FRAME
D=M-D
A=D
D=M
@TEMP_SAVE_RET_ADDRESS
M=D
@SP
M=M-1
@SP
A=M
D=M
@R13
M=D
@ARG
D=M
@0
D=D+A
@R14
M=D
@R13
D=M
@R14
A=M
M=D
@ARG
D=M+1
@SP
M=D
@TEMP_SAVE_FRAME
A=M-1
D=M
@THAT
M=D
@2
D=A
@TEMP_SAVE_FRAME
A=M-D
D=M
@THIS
M=D
@3
D=A
@TEMP_SAVE_FRAME
A=M-D
D=M
@ARG
M=D
@4
D=A
@TEMP_SAVE_FRAME
A=M-D
D=M
@LCL
M=D
@TEMP_SAVE_RET_ADDRESS
A=M
0;JMP
(Sys.init)
@4
D=A
@SP
A=M
M=D
@SP
M=M+1
@RETURN_ADDRESS$Main.fibonacci$0
D=A
@SP
A=M
M=D
@SP
M=M+1
@LCL
D=M
@SP
A=M
M=D
@SP
M=M+1
@ARG
D=M
@SP
A=M
M=D
@SP
M=M+1
@THIS
D=M
@SP
A=M
M=D
@SP
M=M+1
@THAT
D=M
@SP
A=M
M=D
@SP
M=M+1
@SP
D=M
@1
D=D-A
@5
D=D-A
@ARG
M=D
@SP
D=M
@LCL
M=D
@Main.fibonacci
0;JMP
(RETURN_ADDRESS$Main.fibonacci$0)
(Sys.init$WHILE)
@Sys.init$WHILE
0;JMP | 5.786822 | 35 | 0.61219 |
c2b69de29d3c88c51a5c805e5eefc40c7b4ec580 | 414 | asm | Assembly | programs/oeis/174/A174738.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/174/A174738.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/174/A174738.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A174738: Partial sums of floor(n/7).
; 0,0,0,0,0,0,0,1,2,3,4,5,6,7,9,11,13,15,17,19,21,24,27,30,33,36,39,42,46,50,54,58,62,66,70,75,80,85,90,95,100,105,111,117,123,129,135,141,147,154,161,168,175,182,189,196,204,212,220,228,236,244,252,261,270,279,288,297,306,315,325,335,345,355,365,375,385,396,407,418,429,440,451,462,474,486,498,510,522,534,546,559,572,585,598,611,624,637,651,665
sub $0,2
bin $0,2
div $0,7
| 59.142857 | 346 | 0.693237 |
7588581383bc07e832bdec7cc15577bc22c5c032 | 695 | asm | Assembly | oeis/236/A236332.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/236/A236332.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/236/A236332.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A236332: The number of orbits of 4-tuples of the dihedral group of order 2n acting on {1,2,...,n}.
; 1,8,14,36,63,112,172,260,365,504,666,868,1099,1376,1688,2052,2457,2920,3430,4004,4631,5328,6084,6916,7813,8792,9842,10980,12195,13504,14896,16388,17969,19656,21438,23332,25327,27440,29660,32004,34461,37048,39754,42596,45563,48672,51912,55300,58825,62504,66326,70308,74439,78736,83188,87812,92597,97560,102690,108004,113491,119168,125024,131076,137313,143752,150382,157220,164255,171504,178956,186628,194509,202616,210938,219492,228267,237280,246520,256004,265721,275688,285894,296356,307063,318032
add $0,1
mov $1,$0
pow $0,3
mov $2,$1
pow $2,7
gcd $2,8
add $0,$2
sub $0,2
div $0,2
add $0,1
| 49.642857 | 499 | 0.766906 |
a8c50afb9f0725c1de2c41ded6dae789b35b91e2 | 602 | asm | Assembly | libsrc/enterprise/exos_redirect_channel.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 38 | 2021-06-18T12:56:15.000Z | 2022-03-12T20:38:40.000Z | libsrc/enterprise/exos_redirect_channel.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 2 | 2021-06-20T16:28:12.000Z | 2021-11-17T21:33:56.000Z | libsrc/enterprise/exos_redirect_channel.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 6 | 2021-06-18T18:18:36.000Z | 2021-12-22T08:01:32.000Z | ;
; Enterprise 64/128 specific routines
; by Stefano Bodrato, 2011
;
; exos_redirect_channel(unsigned char main_channel, unsigned char secondary_channel);
;
;
; $Id: exos_redirect_channel.asm,v 1.3 2016-06-19 20:17:32 dom Exp $
;
SECTION code_clib
PUBLIC exos_redirect_channel
PUBLIC _exos_redirect_channel
EXTERN exos_redirect_channel_callee
EXTERN ASMDISP_EXOS_REDIRECT_CHANNEL_CALLEE
exos_redirect_channel:
_exos_redirect_channel:
pop bc
pop de
pop hl
push hl
push de
push bc
jp exos_redirect_channel_callee + ASMDISP_EXOS_REDIRECT_CHANNEL_CALLEE
| 19.419355 | 85 | 0.769103 |
12fbe19e98d5b875811d2124d6016975f6ebaf97 | 5,038 | asm | Assembly | src/shaders/post_processing/gen5_6/Core_Kernels/PA_AVS_IEF_Unpack_8x4.asm | me176c-dev/android_hardware_intel-vaapi-driver | 0f2dca8d604220405e4678c0b6c4faa578d994ec | [
"MIT"
] | 192 | 2018-01-26T11:51:55.000Z | 2022-03-25T20:04:19.000Z | src/shaders/post_processing/gen5_6/Core_Kernels/PA_AVS_IEF_Unpack_8x4.asm | me176c-dev/android_hardware_intel-vaapi-driver | 0f2dca8d604220405e4678c0b6c4faa578d994ec | [
"MIT"
] | 256 | 2017-01-23T02:10:27.000Z | 2018-01-23T10:00:05.000Z | src/shaders/post_processing/gen5_6/Core_Kernels/PA_AVS_IEF_Unpack_8x4.asm | me176c-dev/android_hardware_intel-vaapi-driver | 0f2dca8d604220405e4678c0b6c4faa578d994ec | [
"MIT"
] | 64 | 2018-01-30T19:51:53.000Z | 2021-11-24T01:26:14.000Z | /*
* All Video Processing kernels
* Copyright © <2010>, Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* This file was originally licensed under the following license
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
//---------- PA_AVS_IEF_Unpack_8x8.asm ----------
// Yoni: In order to optimize unpacking, 3 methods are being checked:
// 1. AVS_ORIGINAL
// 2. AVS_ROUND_TO_8_BITS
// 3. AVS_INDIRECT_ACCESS
//
// Only 1 method should stay in the code
//#define AVS_ROUND_TO_8_BITS
//#define AVS_INDIRECT_ACCESS
// Move first 8x8 words of Y to dest GRF
mov (8) uwDEST_Y(0)<1> ubAVS_RESPONSE(2,1)<16;4,2>
mov (8) uwDEST_Y(1)<1> ubAVS_RESPONSE(2,8+1)<16;4,2>
mov (8) uwDEST_Y(2)<1> ubAVS_RESPONSE(3,1)<16;4,2>
mov (8) uwDEST_Y(3)<1> ubAVS_RESPONSE(3,8+1)<16;4,2>
mov (8) uwDEST_Y(4)<1> ubAVS_RESPONSE(8,1)<16;4,2>
mov (8) uwDEST_Y(5)<1> ubAVS_RESPONSE(8,8+1)<16;4,2>
mov (8) uwDEST_Y(6)<1> ubAVS_RESPONSE(9,1)<16;4,2>
mov (8) uwDEST_Y(7)<1> ubAVS_RESPONSE(9,8+1)<16;4,2>
// Move first 4x8 words of V to dest GRF
mov (4) uwDEST_V(0)<1> ubAVS_RESPONSE(0,1)<16;2,4>
mov (4) uwDEST_V(0,8)<1> ubAVS_RESPONSE(1,1)<16;2,4>
mov (4) uwDEST_V(1)<1> ubAVS_RESPONSE(6,1)<16;2,4>
mov (4) uwDEST_V(1,8)<1> ubAVS_RESPONSE(7,1)<16;2,4>
// Move first 4x8 words of U to dest GRF
mov (4) uwDEST_U(0)<1> ubAVS_RESPONSE(4,1)<16;2,4>
mov (4) uwDEST_U(0,8)<1> ubAVS_RESPONSE(5,1)<16;2,4>
mov (4) uwDEST_U(1)<1> ubAVS_RESPONSE(10,1)<16;2,4>
mov (4) uwDEST_U(1,8)<1> ubAVS_RESPONSE(11,1)<16;2,4>
// Move second 8x8 words of Y to dest GRF
mov (8) uwDEST_Y(0,8)<1> ubAVS_RESPONSE_2(2,1)<16;4,2>
mov (8) uwDEST_Y(1,8)<1> ubAVS_RESPONSE_2(2,8+1)<16;4,2>
mov (8) uwDEST_Y(2,8)<1> ubAVS_RESPONSE_2(3,1)<16;4,2>
mov (8) uwDEST_Y(3,8)<1> ubAVS_RESPONSE_2(3,8+1)<16;4,2>
mov (8) uwDEST_Y(4,8)<1> ubAVS_RESPONSE_2(8,1)<16;4,2>
mov (8) uwDEST_Y(5,8)<1> ubAVS_RESPONSE_2(8,8+1)<16;4,2>
mov (8) uwDEST_Y(6,8)<1> ubAVS_RESPONSE_2(9,1)<16;4,2>
mov (8) uwDEST_Y(7,8)<1> ubAVS_RESPONSE_2(9,8+1)<16;4,2>
// Move second 4x8 words of V to dest GRF
mov (4) uwDEST_V(0,4)<1> ubAVS_RESPONSE_2(0,1)<16;2,4>
mov (4) uwDEST_V(0,12)<1> ubAVS_RESPONSE_2(1,1)<16;2,4>
mov (4) uwDEST_V(1,4)<1> ubAVS_RESPONSE_2(6,1)<16;2,4>
mov (4) uwDEST_V(1,12)<1> ubAVS_RESPONSE_2(7,1)<16;2,4>
// Move second 4x8 words of U to dest GRF
mov (4) uwDEST_U(0,4)<1> ubAVS_RESPONSE_2(4,1)<16;2,4>
mov (4) uwDEST_U(0,12)<1> ubAVS_RESPONSE_2(5,1)<16;2,4>
mov (4) uwDEST_U(1,4)<1> ubAVS_RESPONSE_2(10,1)<16;2,4>
mov (4) uwDEST_U(1,12)<1> ubAVS_RESPONSE_2(11,1)<16;2,4>
//------------------------------------------------------------------------------
// Re-define new number of lines
#undef nUV_NUM_OF_ROWS
#undef nY_NUM_OF_ROWS
#define nY_NUM_OF_ROWS 8
#define nUV_NUM_OF_ROWS 8
| 46.648148 | 80 | 0.601032 |
ceb3db4b7370a592a27d6049cd02a61ed5789318 | 1,536 | asm | Assembly | programs/oeis/198/A198644.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/198/A198644.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/198/A198644.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A198644: 8*3^n-1.
; 7,23,71,215,647,1943,5831,17495,52487,157463,472391,1417175,4251527,12754583,38263751,114791255,344373767,1033121303,3099363911,9298091735,27894275207,83682825623,251048476871,753145430615,2259436291847,6778308875543,20334926626631,61004779879895,183014339639687,549043018919063,1647129056757191,4941387170271575,14824161510814727,44472484532444183,133417453597332551,400252360791997655,1200757082375992967,3602271247127978903,10806813741383936711,32420441224151810135,97261323672455430407,291783971017366291223,875351913052098873671,2626055739156296621015,7878167217468889863047,23634501652406669589143,70903504957220008767431,212710514871660026302295,638131544614980078906887,1914394633844940236720663,5743183901534820710161991,17229551704604462130485975,51688655113813386391457927,155065965341440159174373783,465197896024320477523121351,1395593688072961432569364055,4186781064218884297708092167,12560343192656652893124276503,37681029577969958679372829511,113043088733909876038118488535,339129266201729628114355465607,1017387798605188884343066396823,3052163395815566653029199190471,9156490187446699959087597571415,27469470562340099877262792714247,82408411687020299631788378142743,247225235061060898895365134428231,741675705183182696686095403284695,2225027115549548090058286209854087,6675081346648644270174858629562263,20025244039945932810524575888686791,60075732119837798431573727666060375,180227196359513395294721182998181127,540681589078540185884163548994543383
mov $1,3
pow $1,$0
mul $1,8
sub $1,1
mov $0,$1
| 170.666667 | 1,467 | 0.929688 |
4727d4241717380e3163cf1767564e113519d1d6 | 171 | asm | Assembly | data/pokemon/dex_entries/lickitung.asm | AtmaBuster/pokeplat-gen2 | fa83b2e75575949b8f72cb2c48f7a1042e97f70f | [
"blessing"
] | 6 | 2021-06-19T06:41:19.000Z | 2022-02-15T17:12:33.000Z | data/pokemon/dex_entries/lickitung.asm | AtmaBuster/pokeplat-gen2-old | 01e42c55db5408d72d89133dc84a46c699d849ad | [
"blessing"
] | null | null | null | data/pokemon/dex_entries/lickitung.asm | AtmaBuster/pokeplat-gen2-old | 01e42c55db5408d72d89133dc84a46c699d849ad | [
"blessing"
] | 3 | 2021-01-15T18:45:40.000Z | 2021-10-16T03:35:27.000Z | db "LICKING@" ; species name
db "It has a tongue"
next "that is over 6'6''"
next "long. It uses this"
page "long tongue to"
next "lick its body"
next "clean.@"
| 17.1 | 29 | 0.631579 |
539ddd4ce01d6952ad2aaf6e2d4ad5d54b99e537 | 2,055 | asm | Assembly | T2_3.asm | caleberocha/T2OrgArq | d14f56163bddb19b520f1e8d9eff858b0a668623 | [
"Unlicense"
] | 1 | 2018-04-26T00:33:07.000Z | 2018-04-26T00:33:07.000Z | T2_3.asm | caleberocha/T2OrgArq | d14f56163bddb19b520f1e8d9eff858b0a668623 | [
"Unlicense"
] | null | null | null | T2_3.asm | caleberocha/T2OrgArq | d14f56163bddb19b520f1e8d9eff858b0a668623 | [
"Unlicense"
] | null | null | null | main
ldi r1,p_amount
sub sp,2
stw r1,sp
ldi sr,read_amount
bnz sp,print
read_amount
ldw r1,0xf006
stw r1,amount
ldi r1,10
stw r1,0xf000
read_number
ldi r1,p_number
sub sp,2
stw r1,sp
ldi sr,read_number_order
bnz sp,print
read_number_order
ldw r1,order
add r1,1
stw r1,order
stw r1,0xf002
read_number_end
ldi r1,p_number_end
sub sp,2
stw r1,sp
ldi sr,read_number_prompt
bnz sp,print
read_number_prompt
ldw r1,0xf006
sub sp,2
stw r1,sp
ldi r1,10
stw r1,0xf000
ldw r1,order
ldw r2,amount
sub r3,r1,r2
bez r3,count_numbers
slt r3,r2,r1
bnz r3,count_numbers
bnz sp,read_number
count_numbers
ldw r5,order
bez r5,print_numbers
sub r5,1
stw r5,order
ldw r1,sp
add sp,2
xor r6,r6,r6
ldi r3,numbers_grouped
count_numbers_loop
ldw r2,numbers_grouped_count
sub r4,r6,r2
bez r4,add_number
ldw r2,r3
sub r2,r1,r2
bnz r2,count_numbers_next
bnz sp,count_numbers_increment
add_number
stw r1,r3
ldw r2,numbers_grouped_count
add r2,1
stw r2,numbers_grouped_count
count_numbers_increment
add r3,2
ldw r2,r3
add r2,1
stw r2,r3
bnz sp,count_numbers
count_numbers_next
add r3,4
add r6,1
ldw r2,numbers_grouped_count
sub r2,r6,r2
bez r2,add_number
bnz sp,count_numbers_loop
print_numbers
ldi r1,header
sub sp,2
stw r1,sp
ldi sr,print_numbers_begin
bnz sp,print
print_numbers_begin
ldi r1,10
stw r1,0xf000
ldi r1,numbers_grouped
ldw r2,numbers_grouped_count
xor r6,r6,r6
print_numbers_loop
ldw r3,r1
stw r3,0xf002
ldi r3,9
stw r3,0xf000
add r1,2
ldw r3,r1
stw r3,0xf002
ldi r3,10
stw r3,0xf000
add r1,2
add r6,1
sub r4,r6,r2
bez r4,end
bnz sp,print_numbers_loop
end
hcf
print
ldw r1,sp
add sp,2
print_loop
ldb r2,r1
stw r2,0xf000
add r1,1
bnz r2,print_loop
bnz sp,sr
p_amount "Quantos numeros? "
p_number "Digite o numero "
p_number_end ": "
amount 0
order 0
numbers_grouped 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
numbers_grouped_count 0
header "Numero Quantidade"
| 15.222222 | 138 | 0.737226 |
d83e8fe86cdfd627d3ac559d0d084acff4d3ee5b | 3,024 | asm | Assembly | symbolinen_konekieli/Linux/kolmas_c_fun_64.asm | tkukka/VariousContent | f7e7ae98ff8521c6c709dabe30855104afe3fe04 | [
"MIT"
] | null | null | null | symbolinen_konekieli/Linux/kolmas_c_fun_64.asm | tkukka/VariousContent | f7e7ae98ff8521c6c709dabe30855104afe3fe04 | [
"MIT"
] | null | null | null | symbolinen_konekieli/Linux/kolmas_c_fun_64.asm | tkukka/VariousContent | f7e7ae98ff8521c6c709dabe30855104afe3fe04 | [
"MIT"
] | null | null | null | BITS 64
DEFAULT REL
SECTION .rodata
vakioteksti db "12345", 0
SECTION .text
EXTERN strtoul
EXTERN reset_errno
EXTERN get_errno
GLOBAL muunna:function
;Vastaa: const char *muunna(unsigned long *)
;Kokeilufunktio, joka kutsuu C-funktioita. Varsinaisesti muuntaa merkkijonon numeeriseen muotoon.
;Palauttaa numeerisen tuloksen ja osoitteen lähdemerkkijonoon. Merkkijonon osoite on NULL, jos muunnos epäonnistui.
muunna: push rbp
mov rbp, rsp
sub rsp, 2*8 ;varataan muistia pinosta 16 tavua
mov [rsp + 8], rdi ;kopioidaan lukuarvon osoite talteen
call reset_errno
mov rax, -1 ;jokin testiarvo != 0
call get_errno
cmp eax, 0 ;errno nollattavissa?
je .nolla
xor eax, eax ;virhetilanne. paluuarvoksi NULL
jmp .loppu
.nolla: mov rdi, vakioteksti
mov rsi, rsp ;RSI = char *end
mov edx, 10
xor eax, eax
call strtoul wrt ..plt ;standardi C funktio
mov rdx, rax ;RDX = muunnoksen tulos. ulong 8 tavua x64:ssa
call get_errno
cmp eax, 0
je .toinen_tarkistus
xor eax, eax ;virhetilanne. paluuarvoksi NULL
jmp .loppu
.toinen_tarkistus: mov rax, vakioteksti
mov rcx, [rsp]
cmp rax, rcx ;tekstin pointterien vertailu
jne .kolmas_tarkistus
xor eax, eax ;muunnos pysähtyi ekaan merkkin
jmp .loppu
.kolmas_tarkistus: cmp byte [rcx], 0 ;muunnettu kokonaan?
je .muunnos_ok
xor eax, eax ;muunnos pysähtyi välille
jmp .loppu
.muunnos_ok: mov r11, [rsp + 8]
mov [r11], rdx ;muunnoksen tulos muistiin
mov rax, vakioteksti
.loppu: leave ;vapautetaan pinosta varattu muisti
ret
| 53.052632 | 115 | 0.375331 |
605f37d6b381f8d0750b701c2779de3c783c7866 | 1,880 | asm | Assembly | programs/oeis/016/A016987.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/016/A016987.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/016/A016987.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A016987: a(n) = (7*n)^7.
; 0,823543,105413504,1801088541,13492928512,64339296875,230539333248,678223072849,1727094849536,3938980639167,8235430000000,16048523266853,29509034655744,51676101935731,86812553324672,140710042265625,221068140740608,337931541778439,504189521813376,736141813551277,1054135040000000,1483273860320763,2054210978157184,2804020163098721,3777156435935232,5026507568359375,6614541047773568,8614550657858229,11112006825558016,14206014885142787,18010885410000000,22657820762815273,28296722014797824,35098120384607511,43255237347640192,52986177566328125,64536258792112128,78180482889742219,94226152134563456,113015634933443697,134929285120000000,160388518974780383,189859054121057664,223854314446892101,262939005204119552,307732862434921875,358914580876636288,417225924495460409,483476023799709696,558545864083284007,643392968750000000,739056281869446093,846661254115016704,967425136234782491,1102662484205853312,1253790880222890625,1422336873671426048,1609942146236642799,1818369905298276736,2049511509762293717,2305393332480000000,2588183863405242403,2900201057640354944,3243919932521508681,3621980417894121472,4037195463728984375,4492559409229761408,4991256617582519389,5536670380497944576,6132392096696902827,6782230728490000000,7490222540601799313,8260641125390352384,9098007718612700671,10007101809887004032,10992972052001953125,12060947473224122368,13216648996753920179,14466001271480793216,15815244818188341337,17270948495360000000,18840022288735946823,20529730428771889024,22347704840150388461,24301958927495380992,26400901701440546875,28653352249202188928,31068554553807275169,33656192666127302656,36426406233868639247,39389806391670000000,42557492016457714933,45941066352209444864,49552654008277002051,53404918335418932352,57511079183693515625,61884931046362841088,66540861593958614359,71493870602660352896,76759589281136626557
pow $0,7
mul $0,823543
| 313.333333 | 1,828 | 0.932979 |
0f86f2a6ad8ca43929df495ed72c5533c240ceeb | 361 | asm | Assembly | oeis/104/A104640.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/104/A104640.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/104/A104640.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A104640: Number of odd digits in n^3.
; Submitted by Jamie Morken(w1)
; 1,0,1,0,2,1,2,2,2,1,4,2,3,1,4,1,3,2,2,0,2,1,3,2,3,4,3,3,2,1,4,2,5,3,2,1,3,2,5,0,2,1,4,2,4,4,3,4,4,2,4,1,3,3,4,4,5,5,4,1,2,2,2,1,2,2,3,3,3,2,6,3,4,1,3,3,4,3,4,2,4,4,5,3,3,2,3,2,3,2,6,2,3,2,5,2,4,4,4,1
add $0,1
pow $0,3
lpb $0
mov $2,$0
div $0,10
mod $2,2
add $3,$2
lpe
mov $0,$3
| 25.785714 | 201 | 0.540166 |
da5696e19634d11346a5044c038a17331a084850 | 266 | asm | Assembly | Src/BE6502/blink.asm | rprouse/65C02_SBC | eb127413d363c53a6f851232403f8a96c802e860 | [
"MIT"
] | null | null | null | Src/BE6502/blink.asm | rprouse/65C02_SBC | eb127413d363c53a6f851232403f8a96c802e860 | [
"MIT"
] | null | null | null | Src/BE6502/blink.asm | rprouse/65C02_SBC | eb127413d363c53a6f851232403f8a96c802e860 | [
"MIT"
] | null | null | null | .setcpu "65C02"
.segment "OS"
.org $8000
reset:
lda #$ff
sta $6002
lda #$50
sta $6000
loop:
ror
sta $6000
jmp loop
nmi:
jmp nmi
irq_brk:
jmp irq_brk
.segment "VECTORS"
.org $FFFA
.word nmi
.word reset
.word irq_brk | 9.5 | 19 | 0.567669 |
19a7d205e113b2c6e19581a2326508035160ea01 | 449 | asm | Assembly | programs/oeis/017/A017425.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/017/A017425.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/017/A017425.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A017425: a(n) = 11*n + 3.
; 3,14,25,36,47,58,69,80,91,102,113,124,135,146,157,168,179,190,201,212,223,234,245,256,267,278,289,300,311,322,333,344,355,366,377,388,399,410,421,432,443,454,465,476,487,498,509,520,531,542,553,564,575,586,597,608,619,630,641,652,663,674,685,696,707,718,729,740,751,762,773,784,795,806,817,828,839,850,861,872,883,894,905,916,927,938,949,960,971,982,993,1004,1015,1026,1037,1048,1059,1070,1081,1092
mul $0,11
add $0,3
| 74.833333 | 400 | 0.719376 |
0237375af0b6ca44faca7a55340d80d291ca7c4a | 382 | asm | Assembly | programs/oeis/277/A277792.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/277/A277792.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/277/A277792.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A277792: Squares that are also pentagonal pyramidal numbers.
; 0,1,196,2601,15376,60025,181476,461041,1032256,2099601,3960100,7027801,11861136,19193161,29964676,45360225,66846976,96216481,135629316,187662601,255360400,342287001,452583076,591024721,763085376,975000625,1233835876,1547556921,1925103376,2376465001,2912760900
pow $0,2
mul $0,2
mov $1,$0
sub $0,1
bin $1,2
mul $0,$1
| 38.2 | 261 | 0.811518 |
9d36fb758050d58872a8a7a35fc76bb4c727e59e | 3,997 | asm | Assembly | _incObj/5B Staircase.asm | kodishmediacenter/msu-md-sonic | 3aa7c5e8add9660df2cd0eceaa214e7d59f2415c | [
"CC0-1.0"
] | 9 | 2021-01-15T13:47:53.000Z | 2022-01-17T15:33:55.000Z | _incObj/5B Staircase.asm | kodishmediacenter/msu-md-sonic | 3aa7c5e8add9660df2cd0eceaa214e7d59f2415c | [
"CC0-1.0"
] | 7 | 2021-01-14T02:18:48.000Z | 2021-03-24T15:44:30.000Z | _incObj/5B Staircase.asm | kodishmediacenter/msu-md-sonic | 3aa7c5e8add9660df2cd0eceaa214e7d59f2415c | [
"CC0-1.0"
] | 2 | 2021-01-14T13:14:26.000Z | 2021-01-29T17:46:04.000Z | ; ---------------------------------------------------------------------------
; Object 5B - blocks that form a staircase (SLZ)
; ---------------------------------------------------------------------------
Staircase:
moveq #0,d0
move.b obRoutine(a0),d0
move.w Stair_Index(pc,d0.w),d1
jsr Stair_Index(pc,d1.w)
out_of_range DeleteObject,stair_origX(a0)
bra.w DisplaySprite
; ===========================================================================
Stair_Index: dc.w Stair_Main-Stair_Index
dc.w Stair_Move-Stair_Index
dc.w Stair_Solid-Stair_Index
stair_origX: equ $30 ; original x-axis position
stair_origY: equ $32 ; original y-axis position
stair_parent: equ $3C ; address of parent object (4 bytes)
; ===========================================================================
Stair_Main: ; Routine 0
addq.b #2,obRoutine(a0)
moveq #$38,d3
moveq #1,d4
btst #0,obStatus(a0) ; is object flipped?
beq.s @notflipped ; if not, branch
moveq #$3B,d3
moveq #-1,d4
@notflipped:
move.w obX(a0),d2
movea.l a0,a1
moveq #3,d1
bra.s @makeblocks
; ===========================================================================
@loop:
bsr.w FindNextFreeObj
bne.w @fail
move.b #4,obRoutine(a1)
@makeblocks:
move.b #id_Staircase,0(a1) ; load another block object
move.l #Map_Stair,obMap(a1)
move.w #$4000,obGfx(a1)
move.b #4,obRender(a1)
move.b #3,obPriority(a1)
move.b #$10,obActWid(a1)
move.b obSubtype(a0),obSubtype(a1)
move.w d2,obX(a1)
move.w obY(a0),obY(a1)
move.w obX(a0),stair_origX(a1)
move.w obY(a1),stair_origY(a1)
addi.w #$20,d2
move.b d3,$37(a1)
move.l a0,stair_parent(a1)
add.b d4,d3
dbf d1,@loop ; repeat sequence 3 times
@fail:
Stair_Move: ; Routine 2
moveq #0,d0
move.b obSubtype(a0),d0
andi.w #7,d0
add.w d0,d0
move.w Stair_TypeIndex(pc,d0.w),d1
jsr Stair_TypeIndex(pc,d1.w)
Stair_Solid: ; Routine 4
movea.l stair_parent(a0),a2
moveq #0,d0
move.b $37(a0),d0
move.b (a2,d0.w),d0
add.w stair_origY(a0),d0
move.w d0,obY(a0)
moveq #0,d1
move.b obActWid(a0),d1
addi.w #$B,d1
move.w #$10,d2
move.w #$11,d3
move.w obX(a0),d4
bsr.w SolidObject
tst.b d4
bpl.s loc_10F92
move.b d4,$36(a2)
loc_10F92:
btst #3,obStatus(a0)
beq.s locret_10FA0
move.b #1,$36(a2)
locret_10FA0:
rts
; ===========================================================================
Stair_TypeIndex:dc.w Stair_Type00-Stair_TypeIndex
dc.w Stair_Type01-Stair_TypeIndex
dc.w Stair_Type02-Stair_TypeIndex
dc.w Stair_Type01-Stair_TypeIndex
; ===========================================================================
Stair_Type00:
tst.w $34(a0)
bne.s loc_10FC0
cmpi.b #1,$36(a0)
bne.s locret_10FBE
move.w #$1E,$34(a0)
locret_10FBE:
rts
; ===========================================================================
loc_10FC0:
subq.w #1,$34(a0)
bne.s locret_10FBE
addq.b #1,obSubtype(a0) ; add 1 to type
rts
; ===========================================================================
Stair_Type02:
tst.w $34(a0)
bne.s loc_10FE0
tst.b $36(a0)
bpl.s locret_10FDE
move.w #$3C,$34(a0)
locret_10FDE:
rts
; ===========================================================================
loc_10FE0:
subq.w #1,$34(a0)
bne.s loc_10FEC
addq.b #1,obSubtype(a0) ; add 1 to type
rts
; ===========================================================================
loc_10FEC:
lea $38(a0),a1
move.w $34(a0),d0
lsr.b #2,d0
andi.b #1,d0
move.b d0,(a1)+
eori.b #1,d0
move.b d0,(a1)+
eori.b #1,d0
move.b d0,(a1)+
eori.b #1,d0
move.b d0,(a1)+
rts
; ===========================================================================
Stair_Type01:
lea $38(a0),a1
cmpi.b #$80,(a1)
beq.s locret_11038
addq.b #1,(a1)
moveq #0,d1
move.b (a1)+,d1
swap d1
lsr.l #1,d1
move.l d1,d2
lsr.l #1,d1
move.l d1,d3
add.l d2,d3
swap d1
swap d2
swap d3
move.b d3,(a1)+
move.b d2,(a1)+
move.b d1,(a1)+
locret_11038:
rts
rts
| 22.455056 | 77 | 0.505129 |
faf4d2e1f772903482fe50879f9acf293f35dfff | 2,306 | asm | Assembly | Ejemplos y Utilidades/ejemplos mikroC/ejemplo timer0/timer0.asm | DAFRELECTRONICS/ThunderBolt | f90425804e11b0c067ee20675033f12cd3fe45c2 | [
"CC0-1.0"
] | 1 | 2019-03-20T21:01:17.000Z | 2019-03-20T21:01:17.000Z | Ejemplos y Utilidades/ejemplos mikroC/ejemplo timer0/timer0.asm | DAFRELECTRONICS/ThunderBolt | f90425804e11b0c067ee20675033f12cd3fe45c2 | [
"CC0-1.0"
] | null | null | null | Ejemplos y Utilidades/ejemplos mikroC/ejemplo timer0/timer0.asm | DAFRELECTRONICS/ThunderBolt | f90425804e11b0c067ee20675033f12cd3fe45c2 | [
"CC0-1.0"
] | null | null | null |
_interrupt:
;timer0.c,7 :: void interrupt()
;timer0.c,9 :: if (INTCON.f2 == 1)
BTFSS INTCON+0, 2
GOTO L_interrupt0
;timer0.c,11 :: T0CON.f7 = 0;
BCF T0CON+0, 7
;timer0.c,12 :: INTCON.f2 = 0;
BCF INTCON+0, 2
;timer0.c,13 :: TMR0H = 0;
CLRF TMR0H+0
;timer0.c,14 :: TMR0L = 0;
CLRF TMR0L+0
;timer0.c,15 :: PORTC.f1 = !PORTC.f1;
BTG PORTC+0, 1
;timer0.c,16 :: T0CON.f7 = 1;
BSF T0CON+0, 7
;timer0.c,17 :: }
L_interrupt0:
;timer0.c,18 :: }
L_end_interrupt:
L__interrupt5:
RETFIE 1
; end of _interrupt
_main:
;timer0.c,23 :: void main()
;timer0.c,25 :: TRISA= 0b00000000;
CLRF TRISA+0
;timer0.c,26 :: TRISB= 0b00000000;
CLRF TRISB+0
;timer0.c,27 :: TRISC= 0b00000001;
MOVLW 1
MOVWF TRISC+0
;timer0.c,29 :: PORTA = 0;
CLRF PORTA+0
;timer0.c,30 :: PORTB = 0;
CLRF PORTB+0
;timer0.c,31 :: PORTC = 0;
CLRF PORTC+0
;timer0.c,33 :: T0CON = 0b00000001;
MOVLW 1
MOVWF T0CON+0
;timer0.c,34 :: TMR0H = 0x15;
MOVLW 21
MOVWF TMR0H+0
;timer0.c,35 :: TMR0L = 0xA0;
MOVLW 160
MOVWF TMR0L+0
;timer0.c,36 :: INTCON = 0b11100000;
MOVLW 224
MOVWF INTCON+0
;timer0.c,37 :: RCON.f7 = 0;
BCF RCON+0, 7
;timer0.c,38 :: T0CON.f7 = 1;
BSF T0CON+0, 7
;timer0.c,40 :: while(1)
L_main1:
;timer0.c,42 :: PORTC.f2 = !PORTC.f2;
BTG PORTC+0, 2
;timer0.c,43 :: delay_ms(500);
MOVLW 31
MOVWF R11, 0
MOVLW 113
MOVWF R12, 0
MOVLW 30
MOVWF R13, 0
L_main3:
DECFSZ R13, 1, 1
BRA L_main3
DECFSZ R12, 1, 1
BRA L_main3
DECFSZ R11, 1, 1
BRA L_main3
NOP
;timer0.c,44 :: }
GOTO L_main1
;timer0.c,45 :: }
L_end_main:
GOTO $+0
; end of _main
_bootInterrupt:
;timer0.c,47 :: void bootInterrupt() //tabla de saltos para poder activar interrupciones usando un bootloader, manda llamar interrupciones y al main segun correponda
;timer0.c,50 :: goto _main
GOTO _main+0
;timer0.c,51 :: goto 0
GOTO 0
;timer0.c,52 :: goto _interrupt
GOTO _interrupt+0
;timer0.c,54 :: }
L_end_bootInterrupt:
RETURN 0
; end of _bootInterrupt
| 23.292929 | 170 | 0.555074 |
beb121b3b7bb3ed15038b58c4ac341685d9b352c | 5,774 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i3-7100_9_0x84_notsx.log_21829_3013.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i3-7100_9_0x84_notsx.log_21829_3013.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i3-7100_9_0x84_notsx.log_21829_3013.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r13
push %r9
push %rbp
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_UC_ht+0x17c3, %rbp
xor $60633, %rcx
movb (%rbp), %bl
nop
xor $50733, %r12
lea addresses_A_ht+0x41a3, %r11
clflush (%r11)
nop
nop
nop
nop
add $33982, %r9
movw $0x6162, (%r11)
nop
nop
sub %r11, %r11
lea addresses_WT_ht+0x151a3, %rsi
lea addresses_D_ht+0x19fa3, %rdi
clflush (%rdi)
nop
nop
and %r11, %r11
mov $55, %rcx
rep movsq
nop
nop
nop
nop
nop
add %rdi, %rdi
lea addresses_WT_ht+0x12e2b, %rsi
lea addresses_normal_ht+0x10a23, %rdi
nop
nop
nop
nop
nop
sub %r12, %r12
mov $52, %rcx
rep movsw
cmp $38218, %r13
lea addresses_UC_ht+0xfac3, %rsi
lea addresses_A_ht+0x17463, %rdi
xor %r13, %r13
mov $14, %rcx
rep movsb
nop
nop
nop
nop
add $6466, %rbx
lea addresses_WC_ht+0x149a3, %rsi
clflush (%rsi)
nop
nop
nop
nop
nop
xor $61767, %rcx
mov $0x6162636465666768, %rdi
movq %rdi, %xmm1
vmovups %ymm1, (%rsi)
nop
nop
inc %r11
lea addresses_WT_ht+0x163a3, %rcx
nop
nop
nop
cmp $15154, %r11
movl $0x61626364, (%rcx)
nop
nop
nop
nop
xor $46711, %r11
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r9
pop %r13
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r13
push %r8
push %rax
push %rbp
push %rcx
// Faulty Load
lea addresses_PSE+0x39a3, %rbp
nop
nop
nop
nop
nop
sub %r13, %r13
mov (%rbp), %r10
lea oracles, %rcx
and $0xff, %r10
shlq $12, %r10
mov (%rcx,%r10,1), %r10
pop %rcx
pop %rbp
pop %rax
pop %r8
pop %r13
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_PSE', 'same': False, 'size': 4, 'congruent': 0, 'NT': False, 'AVXalign': True}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'type': 'addresses_PSE', 'same': True, 'size': 8, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'type': 'addresses_UC_ht', 'same': False, 'size': 1, 'congruent': 3, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_A_ht', 'same': False, 'size': 2, 'congruent': 8, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_WT_ht', 'congruent': 10, 'same': True}, 'dst': {'type': 'addresses_D_ht', 'congruent': 5, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_WT_ht', 'congruent': 1, 'same': False}, 'dst': {'type': 'addresses_normal_ht', 'congruent': 7, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_UC_ht', 'congruent': 1, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 6, 'same': False}, 'OP': 'REPM'}
{'dst': {'type': 'addresses_WC_ht', 'same': False, 'size': 32, 'congruent': 6, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_WT_ht', 'same': False, 'size': 4, 'congruent': 9, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'33': 21829}
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
*/
| 39.547945 | 2,999 | 0.661413 |
7fb223ff69ac74d725200da605ed0a941380c8b3 | 8,398 | asm | Assembly | Transynther/x86/_processed/NONE/_zr_/i7-7700_9_0x48.log_21829_334.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_zr_/i7-7700_9_0x48.log_21829_334.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_zr_/i7-7700_9_0x48.log_21829_334.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r13
push %r15
push %r9
push %rax
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_WC_ht+0x1228, %rsi
lea addresses_WT_ht+0x17192, %rdi
nop
nop
sub $27755, %rax
mov $6, %rcx
rep movsl
nop
nop
nop
nop
nop
xor %r15, %r15
lea addresses_normal_ht+0x104f0, %rsi
nop
nop
nop
nop
nop
xor $20528, %rbx
movw $0x6162, (%rsi)
inc %rdi
lea addresses_WT_ht+0x13bf0, %rsi
lea addresses_UC_ht+0x1404d, %rdi
nop
nop
sub %r9, %r9
mov $69, %rcx
rep movsl
xor %r9, %r9
lea addresses_WT_ht+0x1e0ad, %r9
nop
sub $15585, %rsi
mov $0x6162636465666768, %rdi
movq %rdi, %xmm2
movups %xmm2, (%r9)
nop
dec %rsi
lea addresses_A_ht+0x12af7, %rsi
lea addresses_WT_ht+0xe7b0, %rdi
nop
inc %r13
mov $109, %rcx
rep movsq
xor $16583, %rdi
lea addresses_UC_ht+0x1ccf0, %r15
nop
nop
nop
nop
cmp %rbx, %rbx
mov (%r15), %edi
nop
nop
nop
nop
inc %r13
lea addresses_D_ht+0xb2f0, %rbx
nop
nop
nop
add $61546, %rsi
mov (%rbx), %rax
nop
nop
dec %r15
lea addresses_WC_ht+0x98f0, %rsi
nop
nop
nop
add $17091, %rcx
movl $0x61626364, (%rsi)
nop
nop
add $29252, %r13
lea addresses_normal_ht+0x1b4f0, %rsi
lea addresses_WT_ht+0x19a0, %rdi
nop
nop
nop
nop
nop
and $17069, %r9
mov $115, %rcx
rep movsq
nop
nop
nop
sub %r13, %r13
lea addresses_WT_ht+0x98f0, %rsi
lea addresses_D_ht+0x18e72, %rdi
clflush (%rsi)
nop
nop
nop
nop
nop
and %rbx, %rbx
mov $13, %rcx
rep movsl
nop
nop
nop
nop
xor %r9, %r9
lea addresses_normal_ht+0x1e3d6, %rsi
dec %rbx
movb $0x61, (%rsi)
nop
dec %rbx
lea addresses_D_ht+0x150b0, %rsi
nop
nop
nop
nop
nop
inc %rcx
movups (%rsi), %xmm4
vpextrq $0, %xmm4, %rbx
sub %r13, %r13
lea addresses_D_ht+0xc6b0, %r9
nop
cmp $61616, %rsi
mov $0x6162636465666768, %r13
movq %r13, (%r9)
nop
nop
and $14198, %rsi
lea addresses_WC_ht+0xd108, %rcx
clflush (%rcx)
nop
nop
nop
nop
sub %rsi, %rsi
mov $0x6162636465666768, %r15
movq %r15, %xmm1
and $0xffffffffffffffc0, %rcx
vmovaps %ymm1, (%rcx)
cmp $25962, %rbx
lea addresses_WT_ht+0xda30, %rsi
lea addresses_WC_ht+0x18f0, %rdi
nop
nop
nop
nop
xor $34374, %r13
mov $69, %rcx
rep movsb
nop
nop
nop
nop
nop
cmp $40296, %rax
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rax
pop %r9
pop %r15
pop %r13
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r12
push %r13
push %r8
push %rcx
push %rdi
push %rsi
// Store
lea addresses_UC+0x8ef0, %rcx
nop
nop
nop
sub %r12, %r12
movl $0x51525354, (%rcx)
nop
nop
nop
nop
nop
add %r12, %r12
// Store
lea addresses_PSE+0x2af0, %r11
nop
nop
nop
inc %r13
mov $0x5152535455565758, %rcx
movq %rcx, %xmm1
movntdq %xmm1, (%r11)
nop
nop
nop
xor $50687, %r13
// Faulty Load
lea addresses_WT+0x164f0, %r11
xor $13395, %r8
movups (%r11), %xmm5
vpextrq $0, %xmm5, %rsi
lea oracles, %r12
and $0xff, %rsi
shlq $12, %rsi
mov (%r12,%rsi,1), %rsi
pop %rsi
pop %rdi
pop %rcx
pop %r8
pop %r13
pop %r12
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_WT', 'AVXalign': False, 'congruent': 0, 'size': 1, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC', 'AVXalign': False, 'congruent': 9, 'size': 4, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_PSE', 'AVXalign': False, 'congruent': 9, 'size': 16, 'same': False, 'NT': True}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_WT', 'AVXalign': False, 'congruent': 0, 'size': 16, 'same': True, 'NT': False}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 3, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 1, 'same': True}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'AVXalign': False, 'congruent': 10, 'size': 2, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 8, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT_ht', 'AVXalign': False, 'congruent': 0, 'size': 16, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_A_ht', 'congruent': 0, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 5, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_UC_ht', 'AVXalign': False, 'congruent': 4, 'size': 4, 'same': False, 'NT': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 5, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'AVXalign': False, 'congruent': 10, 'size': 4, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_normal_ht', 'congruent': 9, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 4, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 9, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'AVXalign': False, 'congruent': 1, 'size': 1, 'same': False, 'NT': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 6, 'size': 16, 'same': True, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 2, 'size': 8, 'same': False, 'NT': True}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'AVXalign': True, 'congruent': 2, 'size': 32, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 3, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 9, 'same': False}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
| 32.42471 | 2,999 | 0.65849 |
1a02a5632bb9b83873ae453f8169032d19dbc4a2 | 775 | asm | Assembly | oeis/290/A290233.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/290/A290233.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/290/A290233.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A290233: Binary representation of the diagonal from the origin to the corner of the n-th stage of growth of the two-dimensional cellular automaton defined by "Rule 773", based on the 5-celled von Neumann neighborhood.
; 1,1,111,11,11111,111,1111111,1111,111111111,11111,11111111111,111111,1111111111111,1111111,111111111111111,11111111,11111111111111111,111111111,1111111111111111111,1111111111,111111111111111111111,11111111111,11111111111111111111111,111111111111,1111111111111111111111111,1111111111111,111111111111111111111111111,11111111111111,11111111111111111111111111111,111111111111111,1111111111111111111111111111111,1111111111111111,111111111111111111111111111111111,11111111111111111
add $0,1
dif $0,2
mov $1,10
pow $1,$0
sub $1,10
div $1,9
add $1,1
mov $0,$1
| 64.583333 | 477 | 0.851613 |
8437801413838be86a3c86022fa89875d8db928a | 7,861 | asm | Assembly | Transynther/x86/_processed/NC/_zr_/i3-7100_9_0xca_notsx.log_17750_956.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NC/_zr_/i3-7100_9_0xca_notsx.log_17750_956.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NC/_zr_/i3-7100_9_0xca_notsx.log_17750_956.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r12
push %r13
push %rbp
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_WC_ht+0x11e12, %r12
nop
nop
nop
nop
xor %rbx, %rbx
mov (%r12), %ebp
nop
nop
nop
nop
nop
dec %rbx
lea addresses_normal_ht+0x7bf2, %r13
nop
nop
sub $36442, %rbp
vmovups (%r13), %ymm1
vextracti128 $0, %ymm1, %xmm1
vpextrq $0, %xmm1, %r11
nop
nop
nop
nop
nop
and $46928, %r11
lea addresses_normal_ht+0xf25a, %r12
nop
nop
add $19513, %r10
movb $0x61, (%r12)
nop
nop
dec %rbx
lea addresses_WT_ht+0x1a372, %rbp
nop
nop
nop
nop
nop
and %r12, %r12
mov (%rbp), %r13w
inc %r13
lea addresses_WT_ht+0xfbf3, %rsi
lea addresses_WT_ht+0xb9f2, %rdi
nop
nop
sub %r10, %r10
mov $56, %rcx
rep movsw
nop
nop
nop
nop
sub $2260, %rbp
lea addresses_WC_ht+0x1ff2, %r11
nop
add $38576, %rcx
movb $0x61, (%r11)
nop
nop
nop
nop
nop
cmp $19051, %r11
lea addresses_UC_ht+0x1dde5, %rdi
sub %rsi, %rsi
mov $0x6162636465666768, %r13
movq %r13, %xmm0
movups %xmm0, (%rdi)
nop
nop
nop
nop
dec %rdi
lea addresses_D_ht+0x1a22a, %r11
nop
nop
nop
nop
nop
inc %r13
mov (%r11), %rdi
nop
nop
add %rbx, %rbx
lea addresses_WT_ht+0x19a40, %rsi
lea addresses_normal_ht+0xc5f2, %rdi
nop
and %rbp, %rbp
mov $29, %rcx
rep movsq
nop
nop
nop
nop
lfence
lea addresses_A_ht+0xa280, %r11
clflush (%r11)
nop
nop
nop
nop
sub %r13, %r13
movups (%r11), %xmm1
vpextrq $1, %xmm1, %rsi
nop
nop
cmp $34584, %rdi
lea addresses_normal_ht+0x1ddf2, %rbx
nop
nop
sub $46782, %r12
and $0xffffffffffffffc0, %rbx
movaps (%rbx), %xmm2
vpextrq $0, %xmm2, %rcx
nop
nop
nop
nop
and %rcx, %rcx
lea addresses_UC_ht+0xac72, %rsi
lea addresses_UC_ht+0xba82, %rdi
clflush (%rdi)
nop
nop
nop
nop
add $60925, %r11
mov $114, %rcx
rep movsb
nop
nop
nop
nop
nop
inc %r12
lea addresses_WC_ht+0x199, %r11
nop
nop
nop
nop
nop
sub %r13, %r13
mov (%r11), %ebx
nop
nop
nop
sub $53407, %r11
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r13
pop %r12
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r12
push %r14
push %r15
push %rdi
// Store
lea addresses_A+0xf5f2, %r12
cmp %r11, %r11
mov $0x5152535455565758, %r10
movq %r10, (%r12)
// Exception!!!
nop
nop
mov (0), %r12
nop
nop
nop
xor $44967, %r10
// Store
lea addresses_UC+0x51f2, %r14
nop
nop
nop
add %r15, %r15
mov $0x5152535455565758, %r12
movq %r12, %xmm5
movups %xmm5, (%r14)
cmp %r14, %r14
// Faulty Load
mov $0x5c3e0b00000009f2, %r14
nop
nop
nop
nop
nop
dec %r11
mov (%r14), %r10d
lea oracles, %r15
and $0xff, %r10
shlq $12, %r10
mov (%r15,%r10,1), %r10
pop %rdi
pop %r15
pop %r14
pop %r12
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'same': False, 'congruent': 0, 'NT': False, 'type': 'addresses_NC', 'size': 2, 'AVXalign': False}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 9, 'NT': False, 'type': 'addresses_A', 'size': 8, 'AVXalign': False}}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 11, 'NT': False, 'type': 'addresses_UC', 'size': 16, 'AVXalign': False}}
[Faulty Load]
{'src': {'same': True, 'congruent': 0, 'NT': False, 'type': 'addresses_NC', 'size': 4, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'same': False, 'congruent': 5, 'NT': False, 'type': 'addresses_WC_ht', 'size': 4, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'same': True, 'congruent': 5, 'NT': False, 'type': 'addresses_normal_ht', 'size': 32, 'AVXalign': False}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 2, 'NT': False, 'type': 'addresses_normal_ht', 'size': 1, 'AVXalign': True}}
{'src': {'same': False, 'congruent': 7, 'NT': False, 'type': 'addresses_WT_ht', 'size': 2, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_WT_ht', 'congruent': 0, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_WT_ht', 'congruent': 11, 'same': False}}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 9, 'NT': False, 'type': 'addresses_WC_ht', 'size': 1, 'AVXalign': False}}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 0, 'NT': False, 'type': 'addresses_UC_ht', 'size': 16, 'AVXalign': False}}
{'src': {'same': False, 'congruent': 3, 'NT': False, 'type': 'addresses_D_ht', 'size': 8, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_WT_ht', 'congruent': 0, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_normal_ht', 'congruent': 10, 'same': False}}
{'src': {'same': False, 'congruent': 1, 'NT': False, 'type': 'addresses_A_ht', 'size': 16, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'same': False, 'congruent': 9, 'NT': False, 'type': 'addresses_normal_ht', 'size': 16, 'AVXalign': True}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_UC_ht', 'congruent': 6, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_UC_ht', 'congruent': 4, 'same': True}}
{'src': {'same': False, 'congruent': 0, 'NT': False, 'type': 'addresses_WC_ht', 'size': 4, 'AVXalign': False}, 'OP': 'LOAD'}
{'00': 17750}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
| 31.071146 | 2,999 | 0.656914 |
23ee9c2809f4baf99a6d0b2915ece66e22bc0733 | 892 | asm | Assembly | Windows/Visual Studio/MinMax/MinMax/CalcMinMax.asm | leonhad/masm | f5739a8c8c6c461f9e928576ff36f7991541959b | [
"MIT"
] | 9 | 2020-05-29T14:03:07.000Z | 2021-06-17T07:56:26.000Z | Windows/Visual Studio/MinMax/MinMax/CalcMinMax.asm | leonhad/masm | f5739a8c8c6c461f9e928576ff36f7991541959b | [
"MIT"
] | null | null | null | Windows/Visual Studio/MinMax/MinMax/CalcMinMax.asm | leonhad/masm | f5739a8c8c6c461f9e928576ff36f7991541959b | [
"MIT"
] | 4 | 2021-04-17T17:41:54.000Z | 2022-03-13T16:06:39.000Z | .686
.model flat, c
.const
r4_MinFloat dword 0ff7fffffh
r4_MaxFloat dword 7f7fffffh
.code
CalcMinMax proc
push ebp
mov ebp, esp
xor eax, eax
mov edx, [ebp+8] ; edx = a
mov ecx, [ebp+12] ; ecx = n
test ecx, ecx
jle Done ; jump to Done if n <= 0
fld [r4_MinFloat] ; initial min value
fld [r4_MaxFloat] ; initial max value
@@:
fld real4 ptr [edx] ; load *a
fld st(0) ; duplicate *a on stack
fcomi st(0), st(2) ; compare *a with min
fcmovnb st(0), st(2) ; st(0) = smaller val
fstp st(2) ; save new min value
fcomi st(0), st(2) ; compare *a with max
fcmovb st(0), st(2) ; st(0) = larager val
fstp st(2) ; save new max value
add edx, 4 ; point to next a[i]
dec ecx
jnz @B
mov eax, [ebp+16]
fstp real4 ptr[eax] ; save final min
mov eax, [ebp+20]
fstp real4 ptr[eax] ; save final max
mov eax, 1
Done:
pop ebp
ret
CalcMinMax endp
end
| 18.583333 | 43 | 0.630045 |
0b3e00f3883c0a1ebfcc4893128e87255523c06f | 395 | asm | Assembly | oeis/076/A076127.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/076/A076127.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/076/A076127.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A076127: n-th term is binary string of length t_n with 1's at positions t_i, where t_n = n-th triangular number.
; Submitted by Jon Maiga
; 0,1,101,101001,1010010001,101001000100001,101001000100001000001,1010010001000010000010000001,101001000100001000001000000100000001,101001000100001000001000000100000001000000001
mov $1,1
lpb $0
sub $0,1
mul $1,10
mul $2,$1
add $2,1
lpe
mov $0,$2
| 30.384615 | 177 | 0.782278 |
f9e5b671ce4a101eef0330f56b0aa2c89c651a35 | 461 | asm | Assembly | oeis/105/A105063.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/105/A105063.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/105/A105063.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A105063: Define a(1)=0, a(2)=0, a(3)=8, a(4)=24 and then a(n)=66*a(n-2)+32-a(n-4).
; Submitted by Jon Maiga
; 0,0,8,24,560,1616,36984,106664,2440416,7038240,161030504,464417208,10625572880,30644497520,701126779608,2022072419144,46263741881280,133426135166016,3052705837384904,8804102848537944,201432321525522416
mov $3,1
lpb $0
sub $4,$0
sub $0,$3
add $2,1
trn $4,$0
mov $1,$4
mul $1,64
add $2,$3
add $2,$1
add $4,$2
lpe
mov $0,$1
div $0,8
| 24.263158 | 203 | 0.678959 |
2d40d2996a486d19377e2f90a929e7e95224c4de | 44,361 | asm | Assembly | kill.asm | shahendahamdy/xv6-threads | 3276509c027e47a3536f67e30e8dac9ac7301d75 | [
"MIT-0"
] | null | null | null | kill.asm | shahendahamdy/xv6-threads | 3276509c027e47a3536f67e30e8dac9ac7301d75 | [
"MIT-0"
] | null | null | null | kill.asm | shahendahamdy/xv6-threads | 3276509c027e47a3536f67e30e8dac9ac7301d75 | [
"MIT-0"
] | null | null | null |
_kill: file format elf32-i386
Disassembly of section .text:
00000000 <main>:
#include "stat.h"
#include "user.h"
int
main(int argc, char **argv)
{
0: f3 0f 1e fb endbr32
4: 8d 4c 24 04 lea 0x4(%esp),%ecx
8: 83 e4 f0 and $0xfffffff0,%esp
b: ff 71 fc pushl -0x4(%ecx)
e: 55 push %ebp
f: 89 e5 mov %esp,%ebp
11: 56 push %esi
12: 53 push %ebx
13: 51 push %ecx
14: 83 ec 0c sub $0xc,%esp
17: 8b 01 mov (%ecx),%eax
19: 8b 51 04 mov 0x4(%ecx),%edx
int i;
if(argc < 2){
1c: 83 f8 01 cmp $0x1,%eax
1f: 7e 30 jle 51 <main+0x51>
21: 8d 5a 04 lea 0x4(%edx),%ebx
24: 8d 34 82 lea (%edx,%eax,4),%esi
27: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
2e: 66 90 xchg %ax,%ax
printf(2, "usage: kill pid...\n");
exit();
}
for(i=1; i<argc; i++)
kill(atoi(argv[i]));
30: 83 ec 0c sub $0xc,%esp
33: ff 33 pushl (%ebx)
35: 83 c3 04 add $0x4,%ebx
38: e8 23 02 00 00 call 260 <atoi>
3d: 89 04 24 mov %eax,(%esp)
40: e8 08 05 00 00 call 54d <kill>
for(i=1; i<argc; i++)
45: 83 c4 10 add $0x10,%esp
48: 39 f3 cmp %esi,%ebx
4a: 75 e4 jne 30 <main+0x30>
exit();
4c: e8 cc 04 00 00 call 51d <exit>
printf(2, "usage: kill pid...\n");
51: 50 push %eax
52: 50 push %eax
53: 68 58 08 00 00 push $0x858
58: 6a 02 push $0x2
5a: e8 31 06 00 00 call 690 <printf>
exit();
5f: e8 b9 04 00 00 call 51d <exit>
64: 66 90 xchg %ax,%ax
66: 66 90 xchg %ax,%ax
68: 66 90 xchg %ax,%ax
6a: 66 90 xchg %ax,%ax
6c: 66 90 xchg %ax,%ax
6e: 66 90 xchg %ax,%ax
00000070 <strcpy>:
};
char*
strcpy(char *s, const char *t)
{
70: f3 0f 1e fb endbr32
74: 55 push %ebp
char *os;
os = s;
while((*s++ = *t++) != 0)
75: 31 c0 xor %eax,%eax
{
77: 89 e5 mov %esp,%ebp
79: 53 push %ebx
7a: 8b 4d 08 mov 0x8(%ebp),%ecx
7d: 8b 5d 0c mov 0xc(%ebp),%ebx
while((*s++ = *t++) != 0)
80: 0f b6 14 03 movzbl (%ebx,%eax,1),%edx
84: 88 14 01 mov %dl,(%ecx,%eax,1)
87: 83 c0 01 add $0x1,%eax
8a: 84 d2 test %dl,%dl
8c: 75 f2 jne 80 <strcpy+0x10>
;
return os;
}
8e: 89 c8 mov %ecx,%eax
90: 5b pop %ebx
91: 5d pop %ebp
92: c3 ret
93: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
9a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
000000a0 <strcmp>:
int
strcmp(const char *p, const char *q)
{
a0: f3 0f 1e fb endbr32
a4: 55 push %ebp
a5: 89 e5 mov %esp,%ebp
a7: 53 push %ebx
a8: 8b 4d 08 mov 0x8(%ebp),%ecx
ab: 8b 55 0c mov 0xc(%ebp),%edx
while(*p && *p == *q)
ae: 0f b6 01 movzbl (%ecx),%eax
b1: 0f b6 1a movzbl (%edx),%ebx
b4: 84 c0 test %al,%al
b6: 75 19 jne d1 <strcmp+0x31>
b8: eb 26 jmp e0 <strcmp+0x40>
ba: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
c0: 0f b6 41 01 movzbl 0x1(%ecx),%eax
p++, q++;
c4: 83 c1 01 add $0x1,%ecx
c7: 83 c2 01 add $0x1,%edx
while(*p && *p == *q)
ca: 0f b6 1a movzbl (%edx),%ebx
cd: 84 c0 test %al,%al
cf: 74 0f je e0 <strcmp+0x40>
d1: 38 d8 cmp %bl,%al
d3: 74 eb je c0 <strcmp+0x20>
return (uchar)*p - (uchar)*q;
d5: 29 d8 sub %ebx,%eax
}
d7: 5b pop %ebx
d8: 5d pop %ebp
d9: c3 ret
da: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
e0: 31 c0 xor %eax,%eax
return (uchar)*p - (uchar)*q;
e2: 29 d8 sub %ebx,%eax
}
e4: 5b pop %ebx
e5: 5d pop %ebp
e6: c3 ret
e7: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
ee: 66 90 xchg %ax,%ax
000000f0 <strlen>:
uint
strlen(const char *s)
{
f0: f3 0f 1e fb endbr32
f4: 55 push %ebp
f5: 89 e5 mov %esp,%ebp
f7: 8b 55 08 mov 0x8(%ebp),%edx
int n;
for(n = 0; s[n]; n++)
fa: 80 3a 00 cmpb $0x0,(%edx)
fd: 74 21 je 120 <strlen+0x30>
ff: 31 c0 xor %eax,%eax
101: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
108: 83 c0 01 add $0x1,%eax
10b: 80 3c 02 00 cmpb $0x0,(%edx,%eax,1)
10f: 89 c1 mov %eax,%ecx
111: 75 f5 jne 108 <strlen+0x18>
;
return n;
}
113: 89 c8 mov %ecx,%eax
115: 5d pop %ebp
116: c3 ret
117: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
11e: 66 90 xchg %ax,%ax
for(n = 0; s[n]; n++)
120: 31 c9 xor %ecx,%ecx
}
122: 5d pop %ebp
123: 89 c8 mov %ecx,%eax
125: c3 ret
126: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
12d: 8d 76 00 lea 0x0(%esi),%esi
00000130 <memset>:
void*
memset(void *dst, int c, uint n)
{
130: f3 0f 1e fb endbr32
134: 55 push %ebp
135: 89 e5 mov %esp,%ebp
137: 57 push %edi
138: 8b 55 08 mov 0x8(%ebp),%edx
}
static inline void
stosb(void *addr, int data, int cnt)
{
asm volatile("cld; rep stosb" :
13b: 8b 4d 10 mov 0x10(%ebp),%ecx
13e: 8b 45 0c mov 0xc(%ebp),%eax
141: 89 d7 mov %edx,%edi
143: fc cld
144: f3 aa rep stos %al,%es:(%edi)
stosb(dst, c, n);
return dst;
}
146: 89 d0 mov %edx,%eax
148: 5f pop %edi
149: 5d pop %ebp
14a: c3 ret
14b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
14f: 90 nop
00000150 <strchr>:
char*
strchr(const char *s, char c)
{
150: f3 0f 1e fb endbr32
154: 55 push %ebp
155: 89 e5 mov %esp,%ebp
157: 8b 45 08 mov 0x8(%ebp),%eax
15a: 0f b6 4d 0c movzbl 0xc(%ebp),%ecx
for(; *s; s++)
15e: 0f b6 10 movzbl (%eax),%edx
161: 84 d2 test %dl,%dl
163: 75 16 jne 17b <strchr+0x2b>
165: eb 21 jmp 188 <strchr+0x38>
167: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
16e: 66 90 xchg %ax,%ax
170: 0f b6 50 01 movzbl 0x1(%eax),%edx
174: 83 c0 01 add $0x1,%eax
177: 84 d2 test %dl,%dl
179: 74 0d je 188 <strchr+0x38>
if(*s == c)
17b: 38 d1 cmp %dl,%cl
17d: 75 f1 jne 170 <strchr+0x20>
return (char*)s;
return 0;
}
17f: 5d pop %ebp
180: c3 ret
181: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
return 0;
188: 31 c0 xor %eax,%eax
}
18a: 5d pop %ebp
18b: c3 ret
18c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
00000190 <gets>:
char*
gets(char *buf, int max)
{
190: f3 0f 1e fb endbr32
194: 55 push %ebp
195: 89 e5 mov %esp,%ebp
197: 57 push %edi
198: 56 push %esi
int i, cc;
char c;
for(i=0; i+1 < max; ){
199: 31 f6 xor %esi,%esi
{
19b: 53 push %ebx
19c: 89 f3 mov %esi,%ebx
19e: 83 ec 1c sub $0x1c,%esp
1a1: 8b 7d 08 mov 0x8(%ebp),%edi
for(i=0; i+1 < max; ){
1a4: eb 33 jmp 1d9 <gets+0x49>
1a6: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
1ad: 8d 76 00 lea 0x0(%esi),%esi
cc = read(0, &c, 1);
1b0: 83 ec 04 sub $0x4,%esp
1b3: 8d 45 e7 lea -0x19(%ebp),%eax
1b6: 6a 01 push $0x1
1b8: 50 push %eax
1b9: 6a 00 push $0x0
1bb: e8 75 03 00 00 call 535 <read>
if(cc < 1)
1c0: 83 c4 10 add $0x10,%esp
1c3: 85 c0 test %eax,%eax
1c5: 7e 1c jle 1e3 <gets+0x53>
break;
buf[i++] = c;
1c7: 0f b6 45 e7 movzbl -0x19(%ebp),%eax
1cb: 83 c7 01 add $0x1,%edi
1ce: 88 47 ff mov %al,-0x1(%edi)
if(c == '\n' || c == '\r')
1d1: 3c 0a cmp $0xa,%al
1d3: 74 23 je 1f8 <gets+0x68>
1d5: 3c 0d cmp $0xd,%al
1d7: 74 1f je 1f8 <gets+0x68>
for(i=0; i+1 < max; ){
1d9: 83 c3 01 add $0x1,%ebx
1dc: 89 fe mov %edi,%esi
1de: 3b 5d 0c cmp 0xc(%ebp),%ebx
1e1: 7c cd jl 1b0 <gets+0x20>
1e3: 89 f3 mov %esi,%ebx
break;
}
buf[i] = '\0';
return buf;
}
1e5: 8b 45 08 mov 0x8(%ebp),%eax
buf[i] = '\0';
1e8: c6 03 00 movb $0x0,(%ebx)
}
1eb: 8d 65 f4 lea -0xc(%ebp),%esp
1ee: 5b pop %ebx
1ef: 5e pop %esi
1f0: 5f pop %edi
1f1: 5d pop %ebp
1f2: c3 ret
1f3: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
1f7: 90 nop
1f8: 8b 75 08 mov 0x8(%ebp),%esi
1fb: 8b 45 08 mov 0x8(%ebp),%eax
1fe: 01 de add %ebx,%esi
200: 89 f3 mov %esi,%ebx
buf[i] = '\0';
202: c6 03 00 movb $0x0,(%ebx)
}
205: 8d 65 f4 lea -0xc(%ebp),%esp
208: 5b pop %ebx
209: 5e pop %esi
20a: 5f pop %edi
20b: 5d pop %ebp
20c: c3 ret
20d: 8d 76 00 lea 0x0(%esi),%esi
00000210 <stat>:
int
stat(const char *n, struct stat *st)
{
210: f3 0f 1e fb endbr32
214: 55 push %ebp
215: 89 e5 mov %esp,%ebp
217: 56 push %esi
218: 53 push %ebx
int fd;
int r;
fd = open(n, O_RDONLY);
219: 83 ec 08 sub $0x8,%esp
21c: 6a 00 push $0x0
21e: ff 75 08 pushl 0x8(%ebp)
221: e8 37 03 00 00 call 55d <open>
if(fd < 0)
226: 83 c4 10 add $0x10,%esp
229: 85 c0 test %eax,%eax
22b: 78 2b js 258 <stat+0x48>
return -1;
r = fstat(fd, st);
22d: 83 ec 08 sub $0x8,%esp
230: ff 75 0c pushl 0xc(%ebp)
233: 89 c3 mov %eax,%ebx
235: 50 push %eax
236: e8 3a 03 00 00 call 575 <fstat>
close(fd);
23b: 89 1c 24 mov %ebx,(%esp)
r = fstat(fd, st);
23e: 89 c6 mov %eax,%esi
close(fd);
240: e8 00 03 00 00 call 545 <close>
return r;
245: 83 c4 10 add $0x10,%esp
}
248: 8d 65 f8 lea -0x8(%ebp),%esp
24b: 89 f0 mov %esi,%eax
24d: 5b pop %ebx
24e: 5e pop %esi
24f: 5d pop %ebp
250: c3 ret
251: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
return -1;
258: be ff ff ff ff mov $0xffffffff,%esi
25d: eb e9 jmp 248 <stat+0x38>
25f: 90 nop
00000260 <atoi>:
int
atoi(const char *s)
{
260: f3 0f 1e fb endbr32
264: 55 push %ebp
265: 89 e5 mov %esp,%ebp
267: 53 push %ebx
268: 8b 55 08 mov 0x8(%ebp),%edx
int n;
n = 0;
while('0' <= *s && *s <= '9')
26b: 0f be 02 movsbl (%edx),%eax
26e: 8d 48 d0 lea -0x30(%eax),%ecx
271: 80 f9 09 cmp $0x9,%cl
n = 0;
274: b9 00 00 00 00 mov $0x0,%ecx
while('0' <= *s && *s <= '9')
279: 77 1a ja 295 <atoi+0x35>
27b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
27f: 90 nop
n = n*10 + *s++ - '0';
280: 83 c2 01 add $0x1,%edx
283: 8d 0c 89 lea (%ecx,%ecx,4),%ecx
286: 8d 4c 48 d0 lea -0x30(%eax,%ecx,2),%ecx
while('0' <= *s && *s <= '9')
28a: 0f be 02 movsbl (%edx),%eax
28d: 8d 58 d0 lea -0x30(%eax),%ebx
290: 80 fb 09 cmp $0x9,%bl
293: 76 eb jbe 280 <atoi+0x20>
return n;
}
295: 89 c8 mov %ecx,%eax
297: 5b pop %ebx
298: 5d pop %ebp
299: c3 ret
29a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
000002a0 <memmove>:
void*
memmove(void *vdst, const void *vsrc, int n)
{
2a0: f3 0f 1e fb endbr32
2a4: 55 push %ebp
2a5: 89 e5 mov %esp,%ebp
2a7: 57 push %edi
2a8: 8b 45 10 mov 0x10(%ebp),%eax
2ab: 8b 55 08 mov 0x8(%ebp),%edx
2ae: 56 push %esi
2af: 8b 75 0c mov 0xc(%ebp),%esi
char *dst;
const char *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
2b2: 85 c0 test %eax,%eax
2b4: 7e 0f jle 2c5 <memmove+0x25>
2b6: 01 d0 add %edx,%eax
dst = vdst;
2b8: 89 d7 mov %edx,%edi
2ba: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
*dst++ = *src++;
2c0: a4 movsb %ds:(%esi),%es:(%edi)
while(n-- > 0)
2c1: 39 f8 cmp %edi,%eax
2c3: 75 fb jne 2c0 <memmove+0x20>
return vdst;
}
2c5: 5e pop %esi
2c6: 89 d0 mov %edx,%eax
2c8: 5f pop %edi
2c9: 5d pop %ebp
2ca: c3 ret
2cb: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
2cf: 90 nop
000002d0 <thread_join>:
void* stack;
stack =malloc(4096); //pgsize
return clone(start_routine,arg1,arg2,stack);
}
int thread_join()
{
2d0: f3 0f 1e fb endbr32
2d4: 55 push %ebp
2d5: 89 e5 mov %esp,%ebp
2d7: 83 ec 24 sub $0x24,%esp
void * stackPtr;
int x = join(&stackPtr);
2da: 8d 45 f4 lea -0xc(%ebp),%eax
2dd: 50 push %eax
2de: e8 f2 02 00 00 call 5d5 <join>
return x;
}
2e3: c9 leave
2e4: c3 ret
2e5: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
2ec: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
000002f0 <lock_init>:
void lock_init(struct lock_t *lk){
2f0: f3 0f 1e fb endbr32
2f4: 55 push %ebp
2f5: 89 e5 mov %esp,%ebp
lk->locked=0; //intialize as unnlocked
2f7: 8b 45 08 mov 0x8(%ebp),%eax
2fa: c7 00 00 00 00 00 movl $0x0,(%eax)
}
300: 5d pop %ebp
301: c3 ret
302: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
309: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
00000310 <lock_acquire>:
void lock_acquire(struct lock_t *lk){
310: f3 0f 1e fb endbr32
314: 55 push %ebp
xchg(volatile uint *addr, uint newval)
{
uint result;
// The + in "+m" denotes a read-modify-write operand.
asm volatile("lock; xchgl %0, %1" :
315: b9 01 00 00 00 mov $0x1,%ecx
31a: 89 e5 mov %esp,%ebp
31c: 8b 55 08 mov 0x8(%ebp),%edx
31f: 90 nop
320: 89 c8 mov %ecx,%eax
322: f0 87 02 lock xchg %eax,(%edx)
while(xchg(&lk->locked,1) != 0);
325: 85 c0 test %eax,%eax
327: 75 f7 jne 320 <lock_acquire+0x10>
}
329: 5d pop %ebp
32a: c3 ret
32b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
32f: 90 nop
00000330 <lock_release>:
void lock_release(struct lock_t *lk){
330: f3 0f 1e fb endbr32
334: 55 push %ebp
335: 31 c0 xor %eax,%eax
337: 89 e5 mov %esp,%ebp
339: 8b 55 08 mov 0x8(%ebp),%edx
33c: f0 87 02 lock xchg %eax,(%edx)
xchg(&lk->locked,0) ;
}
33f: 5d pop %ebp
340: c3 ret
341: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
348: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
34f: 90 nop
00000350 <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
350: f3 0f 1e fb endbr32
354: 55 push %ebp
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
355: a1 c4 0b 00 00 mov 0xbc4,%eax
{
35a: 89 e5 mov %esp,%ebp
35c: 57 push %edi
35d: 56 push %esi
35e: 53 push %ebx
35f: 8b 5d 08 mov 0x8(%ebp),%ebx
362: 8b 10 mov (%eax),%edx
bp = (Header*)ap - 1;
364: 8d 4b f8 lea -0x8(%ebx),%ecx
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
367: 39 c8 cmp %ecx,%eax
369: 73 15 jae 380 <free+0x30>
36b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
36f: 90 nop
370: 39 d1 cmp %edx,%ecx
372: 72 14 jb 388 <free+0x38>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
374: 39 d0 cmp %edx,%eax
376: 73 10 jae 388 <free+0x38>
{
378: 89 d0 mov %edx,%eax
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
37a: 8b 10 mov (%eax),%edx
37c: 39 c8 cmp %ecx,%eax
37e: 72 f0 jb 370 <free+0x20>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
380: 39 d0 cmp %edx,%eax
382: 72 f4 jb 378 <free+0x28>
384: 39 d1 cmp %edx,%ecx
386: 73 f0 jae 378 <free+0x28>
break;
if(bp + bp->s.size == p->s.ptr){
388: 8b 73 fc mov -0x4(%ebx),%esi
38b: 8d 3c f1 lea (%ecx,%esi,8),%edi
38e: 39 fa cmp %edi,%edx
390: 74 1e je 3b0 <free+0x60>
bp->s.size += p->s.ptr->s.size;
bp->s.ptr = p->s.ptr->s.ptr;
} else
bp->s.ptr = p->s.ptr;
392: 89 53 f8 mov %edx,-0x8(%ebx)
if(p + p->s.size == bp){
395: 8b 50 04 mov 0x4(%eax),%edx
398: 8d 34 d0 lea (%eax,%edx,8),%esi
39b: 39 f1 cmp %esi,%ecx
39d: 74 28 je 3c7 <free+0x77>
p->s.size += bp->s.size;
p->s.ptr = bp->s.ptr;
} else
p->s.ptr = bp;
39f: 89 08 mov %ecx,(%eax)
freep = p;
}
3a1: 5b pop %ebx
freep = p;
3a2: a3 c4 0b 00 00 mov %eax,0xbc4
}
3a7: 5e pop %esi
3a8: 5f pop %edi
3a9: 5d pop %ebp
3aa: c3 ret
3ab: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
3af: 90 nop
bp->s.size += p->s.ptr->s.size;
3b0: 03 72 04 add 0x4(%edx),%esi
3b3: 89 73 fc mov %esi,-0x4(%ebx)
bp->s.ptr = p->s.ptr->s.ptr;
3b6: 8b 10 mov (%eax),%edx
3b8: 8b 12 mov (%edx),%edx
3ba: 89 53 f8 mov %edx,-0x8(%ebx)
if(p + p->s.size == bp){
3bd: 8b 50 04 mov 0x4(%eax),%edx
3c0: 8d 34 d0 lea (%eax,%edx,8),%esi
3c3: 39 f1 cmp %esi,%ecx
3c5: 75 d8 jne 39f <free+0x4f>
p->s.size += bp->s.size;
3c7: 03 53 fc add -0x4(%ebx),%edx
freep = p;
3ca: a3 c4 0b 00 00 mov %eax,0xbc4
p->s.size += bp->s.size;
3cf: 89 50 04 mov %edx,0x4(%eax)
p->s.ptr = bp->s.ptr;
3d2: 8b 53 f8 mov -0x8(%ebx),%edx
3d5: 89 10 mov %edx,(%eax)
}
3d7: 5b pop %ebx
3d8: 5e pop %esi
3d9: 5f pop %edi
3da: 5d pop %ebp
3db: c3 ret
3dc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
000003e0 <malloc>:
return freep;
}
void*
malloc(uint nbytes)
{
3e0: f3 0f 1e fb endbr32
3e4: 55 push %ebp
3e5: 89 e5 mov %esp,%ebp
3e7: 57 push %edi
3e8: 56 push %esi
3e9: 53 push %ebx
3ea: 83 ec 1c sub $0x1c,%esp
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
3ed: 8b 45 08 mov 0x8(%ebp),%eax
if((prevp = freep) == 0){
3f0: 8b 3d c4 0b 00 00 mov 0xbc4,%edi
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
3f6: 8d 70 07 lea 0x7(%eax),%esi
3f9: c1 ee 03 shr $0x3,%esi
3fc: 83 c6 01 add $0x1,%esi
if((prevp = freep) == 0){
3ff: 85 ff test %edi,%edi
401: 0f 84 a9 00 00 00 je 4b0 <malloc+0xd0>
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
407: 8b 07 mov (%edi),%eax
if(p->s.size >= nunits){
409: 8b 48 04 mov 0x4(%eax),%ecx
40c: 39 f1 cmp %esi,%ecx
40e: 73 6d jae 47d <malloc+0x9d>
410: 81 fe 00 10 00 00 cmp $0x1000,%esi
416: bb 00 10 00 00 mov $0x1000,%ebx
41b: 0f 43 de cmovae %esi,%ebx
p = sbrk(nu * sizeof(Header));
41e: 8d 0c dd 00 00 00 00 lea 0x0(,%ebx,8),%ecx
425: 89 4d e4 mov %ecx,-0x1c(%ebp)
428: eb 17 jmp 441 <malloc+0x61>
42a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
430: 8b 10 mov (%eax),%edx
if(p->s.size >= nunits){
432: 8b 4a 04 mov 0x4(%edx),%ecx
435: 39 f1 cmp %esi,%ecx
437: 73 4f jae 488 <malloc+0xa8>
439: 8b 3d c4 0b 00 00 mov 0xbc4,%edi
43f: 89 d0 mov %edx,%eax
p->s.size = nunits;
}
freep = prevp;
return (void*)(p + 1);
}
if(p == freep)
441: 39 c7 cmp %eax,%edi
443: 75 eb jne 430 <malloc+0x50>
p = sbrk(nu * sizeof(Header));
445: 83 ec 0c sub $0xc,%esp
448: ff 75 e4 pushl -0x1c(%ebp)
44b: e8 65 01 00 00 call 5b5 <sbrk>
if(p == (char*)-1)
450: 83 c4 10 add $0x10,%esp
453: 83 f8 ff cmp $0xffffffff,%eax
456: 74 1b je 473 <malloc+0x93>
hp->s.size = nu;
458: 89 58 04 mov %ebx,0x4(%eax)
free((void*)(hp + 1));
45b: 83 ec 0c sub $0xc,%esp
45e: 83 c0 08 add $0x8,%eax
461: 50 push %eax
462: e8 e9 fe ff ff call 350 <free>
return freep;
467: a1 c4 0b 00 00 mov 0xbc4,%eax
if((p = morecore(nunits)) == 0)
46c: 83 c4 10 add $0x10,%esp
46f: 85 c0 test %eax,%eax
471: 75 bd jne 430 <malloc+0x50>
return 0;
}
}
473: 8d 65 f4 lea -0xc(%ebp),%esp
return 0;
476: 31 c0 xor %eax,%eax
}
478: 5b pop %ebx
479: 5e pop %esi
47a: 5f pop %edi
47b: 5d pop %ebp
47c: c3 ret
if(p->s.size >= nunits){
47d: 89 c2 mov %eax,%edx
47f: 89 f8 mov %edi,%eax
481: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
if(p->s.size == nunits)
488: 39 ce cmp %ecx,%esi
48a: 74 54 je 4e0 <malloc+0x100>
p->s.size -= nunits;
48c: 29 f1 sub %esi,%ecx
48e: 89 4a 04 mov %ecx,0x4(%edx)
p += p->s.size;
491: 8d 14 ca lea (%edx,%ecx,8),%edx
p->s.size = nunits;
494: 89 72 04 mov %esi,0x4(%edx)
freep = prevp;
497: a3 c4 0b 00 00 mov %eax,0xbc4
}
49c: 8d 65 f4 lea -0xc(%ebp),%esp
return (void*)(p + 1);
49f: 8d 42 08 lea 0x8(%edx),%eax
}
4a2: 5b pop %ebx
4a3: 5e pop %esi
4a4: 5f pop %edi
4a5: 5d pop %ebp
4a6: c3 ret
4a7: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
4ae: 66 90 xchg %ax,%ax
base.s.ptr = freep = prevp = &base;
4b0: c7 05 c4 0b 00 00 c8 movl $0xbc8,0xbc4
4b7: 0b 00 00
base.s.size = 0;
4ba: bf c8 0b 00 00 mov $0xbc8,%edi
base.s.ptr = freep = prevp = &base;
4bf: c7 05 c8 0b 00 00 c8 movl $0xbc8,0xbc8
4c6: 0b 00 00
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
4c9: 89 f8 mov %edi,%eax
base.s.size = 0;
4cb: c7 05 cc 0b 00 00 00 movl $0x0,0xbcc
4d2: 00 00 00
if(p->s.size >= nunits){
4d5: e9 36 ff ff ff jmp 410 <malloc+0x30>
4da: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
prevp->s.ptr = p->s.ptr;
4e0: 8b 0a mov (%edx),%ecx
4e2: 89 08 mov %ecx,(%eax)
4e4: eb b1 jmp 497 <malloc+0xb7>
4e6: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
4ed: 8d 76 00 lea 0x0(%esi),%esi
000004f0 <thread_create>:
{
4f0: f3 0f 1e fb endbr32
4f4: 55 push %ebp
4f5: 89 e5 mov %esp,%ebp
4f7: 83 ec 14 sub $0x14,%esp
stack =malloc(4096); //pgsize
4fa: 68 00 10 00 00 push $0x1000
4ff: e8 dc fe ff ff call 3e0 <malloc>
return clone(start_routine,arg1,arg2,stack);
504: 50 push %eax
505: ff 75 10 pushl 0x10(%ebp)
508: ff 75 0c pushl 0xc(%ebp)
50b: ff 75 08 pushl 0x8(%ebp)
50e: e8 ba 00 00 00 call 5cd <clone>
}
513: c9 leave
514: c3 ret
00000515 <fork>:
name: \
movl $SYS_ ## name, %eax; \
int $T_SYSCALL; \
ret
SYSCALL(fork)
515: b8 01 00 00 00 mov $0x1,%eax
51a: cd 40 int $0x40
51c: c3 ret
0000051d <exit>:
SYSCALL(exit)
51d: b8 02 00 00 00 mov $0x2,%eax
522: cd 40 int $0x40
524: c3 ret
00000525 <wait>:
SYSCALL(wait)
525: b8 03 00 00 00 mov $0x3,%eax
52a: cd 40 int $0x40
52c: c3 ret
0000052d <pipe>:
SYSCALL(pipe)
52d: b8 04 00 00 00 mov $0x4,%eax
532: cd 40 int $0x40
534: c3 ret
00000535 <read>:
SYSCALL(read)
535: b8 05 00 00 00 mov $0x5,%eax
53a: cd 40 int $0x40
53c: c3 ret
0000053d <write>:
SYSCALL(write)
53d: b8 10 00 00 00 mov $0x10,%eax
542: cd 40 int $0x40
544: c3 ret
00000545 <close>:
SYSCALL(close)
545: b8 15 00 00 00 mov $0x15,%eax
54a: cd 40 int $0x40
54c: c3 ret
0000054d <kill>:
SYSCALL(kill)
54d: b8 06 00 00 00 mov $0x6,%eax
552: cd 40 int $0x40
554: c3 ret
00000555 <exec>:
SYSCALL(exec)
555: b8 07 00 00 00 mov $0x7,%eax
55a: cd 40 int $0x40
55c: c3 ret
0000055d <open>:
SYSCALL(open)
55d: b8 0f 00 00 00 mov $0xf,%eax
562: cd 40 int $0x40
564: c3 ret
00000565 <mknod>:
SYSCALL(mknod)
565: b8 11 00 00 00 mov $0x11,%eax
56a: cd 40 int $0x40
56c: c3 ret
0000056d <unlink>:
SYSCALL(unlink)
56d: b8 12 00 00 00 mov $0x12,%eax
572: cd 40 int $0x40
574: c3 ret
00000575 <fstat>:
SYSCALL(fstat)
575: b8 08 00 00 00 mov $0x8,%eax
57a: cd 40 int $0x40
57c: c3 ret
0000057d <link>:
SYSCALL(link)
57d: b8 13 00 00 00 mov $0x13,%eax
582: cd 40 int $0x40
584: c3 ret
00000585 <mkdir>:
SYSCALL(mkdir)
585: b8 14 00 00 00 mov $0x14,%eax
58a: cd 40 int $0x40
58c: c3 ret
0000058d <chdir>:
SYSCALL(chdir)
58d: b8 09 00 00 00 mov $0x9,%eax
592: cd 40 int $0x40
594: c3 ret
00000595 <dup>:
SYSCALL(dup)
595: b8 0a 00 00 00 mov $0xa,%eax
59a: cd 40 int $0x40
59c: c3 ret
0000059d <getpid>:
SYSCALL(getpid)
59d: b8 0b 00 00 00 mov $0xb,%eax
5a2: cd 40 int $0x40
5a4: c3 ret
000005a5 <getyear>:
SYSCALL(getyear)
5a5: b8 16 00 00 00 mov $0x16,%eax
5aa: cd 40 int $0x40
5ac: c3 ret
000005ad <getreadcount>:
SYSCALL(getreadcount)
5ad: b8 17 00 00 00 mov $0x17,%eax
5b2: cd 40 int $0x40
5b4: c3 ret
000005b5 <sbrk>:
SYSCALL(sbrk)
5b5: b8 0c 00 00 00 mov $0xc,%eax
5ba: cd 40 int $0x40
5bc: c3 ret
000005bd <sleep>:
SYSCALL(sleep)
5bd: b8 0d 00 00 00 mov $0xd,%eax
5c2: cd 40 int $0x40
5c4: c3 ret
000005c5 <uptime>:
SYSCALL(uptime)
5c5: b8 0e 00 00 00 mov $0xe,%eax
5ca: cd 40 int $0x40
5cc: c3 ret
000005cd <clone>:
SYSCALL(clone)
5cd: b8 18 00 00 00 mov $0x18,%eax
5d2: cd 40 int $0x40
5d4: c3 ret
000005d5 <join>:
SYSCALL(join)
5d5: b8 19 00 00 00 mov $0x19,%eax
5da: cd 40 int $0x40
5dc: c3 ret
5dd: 66 90 xchg %ax,%ax
5df: 90 nop
000005e0 <printint>:
write(fd, &c, 1);
}
static void
printint(int fd, int xx, int base, int sgn)
{
5e0: 55 push %ebp
5e1: 89 e5 mov %esp,%ebp
5e3: 57 push %edi
5e4: 56 push %esi
5e5: 53 push %ebx
5e6: 83 ec 3c sub $0x3c,%esp
5e9: 89 4d c4 mov %ecx,-0x3c(%ebp)
uint x;
neg = 0;
if(sgn && xx < 0){
neg = 1;
x = -xx;
5ec: 89 d1 mov %edx,%ecx
{
5ee: 89 45 b8 mov %eax,-0x48(%ebp)
if(sgn && xx < 0){
5f1: 85 d2 test %edx,%edx
5f3: 0f 89 7f 00 00 00 jns 678 <printint+0x98>
5f9: f6 45 08 01 testb $0x1,0x8(%ebp)
5fd: 74 79 je 678 <printint+0x98>
neg = 1;
5ff: c7 45 bc 01 00 00 00 movl $0x1,-0x44(%ebp)
x = -xx;
606: f7 d9 neg %ecx
} else {
x = xx;
}
i = 0;
608: 31 db xor %ebx,%ebx
60a: 8d 75 d7 lea -0x29(%ebp),%esi
60d: 8d 76 00 lea 0x0(%esi),%esi
do{
buf[i++] = digits[x % base];
610: 89 c8 mov %ecx,%eax
612: 31 d2 xor %edx,%edx
614: 89 cf mov %ecx,%edi
616: f7 75 c4 divl -0x3c(%ebp)
619: 0f b6 92 74 08 00 00 movzbl 0x874(%edx),%edx
620: 89 45 c0 mov %eax,-0x40(%ebp)
623: 89 d8 mov %ebx,%eax
625: 8d 5b 01 lea 0x1(%ebx),%ebx
}while((x /= base) != 0);
628: 8b 4d c0 mov -0x40(%ebp),%ecx
buf[i++] = digits[x % base];
62b: 88 14 1e mov %dl,(%esi,%ebx,1)
}while((x /= base) != 0);
62e: 39 7d c4 cmp %edi,-0x3c(%ebp)
631: 76 dd jbe 610 <printint+0x30>
if(neg)
633: 8b 4d bc mov -0x44(%ebp),%ecx
636: 85 c9 test %ecx,%ecx
638: 74 0c je 646 <printint+0x66>
buf[i++] = '-';
63a: c6 44 1d d8 2d movb $0x2d,-0x28(%ebp,%ebx,1)
buf[i++] = digits[x % base];
63f: 89 d8 mov %ebx,%eax
buf[i++] = '-';
641: ba 2d 00 00 00 mov $0x2d,%edx
while(--i >= 0)
646: 8b 7d b8 mov -0x48(%ebp),%edi
649: 8d 5c 05 d7 lea -0x29(%ebp,%eax,1),%ebx
64d: eb 07 jmp 656 <printint+0x76>
64f: 90 nop
650: 0f b6 13 movzbl (%ebx),%edx
653: 83 eb 01 sub $0x1,%ebx
write(fd, &c, 1);
656: 83 ec 04 sub $0x4,%esp
659: 88 55 d7 mov %dl,-0x29(%ebp)
65c: 6a 01 push $0x1
65e: 56 push %esi
65f: 57 push %edi
660: e8 d8 fe ff ff call 53d <write>
while(--i >= 0)
665: 83 c4 10 add $0x10,%esp
668: 39 de cmp %ebx,%esi
66a: 75 e4 jne 650 <printint+0x70>
putc(fd, buf[i]);
}
66c: 8d 65 f4 lea -0xc(%ebp),%esp
66f: 5b pop %ebx
670: 5e pop %esi
671: 5f pop %edi
672: 5d pop %ebp
673: c3 ret
674: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
neg = 0;
678: c7 45 bc 00 00 00 00 movl $0x0,-0x44(%ebp)
67f: eb 87 jmp 608 <printint+0x28>
681: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
688: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
68f: 90 nop
00000690 <printf>:
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, const char *fmt, ...)
{
690: f3 0f 1e fb endbr32
694: 55 push %ebp
695: 89 e5 mov %esp,%ebp
697: 57 push %edi
698: 56 push %esi
699: 53 push %ebx
69a: 83 ec 2c sub $0x2c,%esp
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
69d: 8b 75 0c mov 0xc(%ebp),%esi
6a0: 0f b6 1e movzbl (%esi),%ebx
6a3: 84 db test %bl,%bl
6a5: 0f 84 b4 00 00 00 je 75f <printf+0xcf>
ap = (uint*)(void*)&fmt + 1;
6ab: 8d 45 10 lea 0x10(%ebp),%eax
6ae: 83 c6 01 add $0x1,%esi
write(fd, &c, 1);
6b1: 8d 7d e7 lea -0x19(%ebp),%edi
state = 0;
6b4: 31 d2 xor %edx,%edx
ap = (uint*)(void*)&fmt + 1;
6b6: 89 45 d0 mov %eax,-0x30(%ebp)
6b9: eb 33 jmp 6ee <printf+0x5e>
6bb: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
6bf: 90 nop
6c0: 89 55 d4 mov %edx,-0x2c(%ebp)
c = fmt[i] & 0xff;
if(state == 0){
if(c == '%'){
state = '%';
6c3: ba 25 00 00 00 mov $0x25,%edx
if(c == '%'){
6c8: 83 f8 25 cmp $0x25,%eax
6cb: 74 17 je 6e4 <printf+0x54>
write(fd, &c, 1);
6cd: 83 ec 04 sub $0x4,%esp
6d0: 88 5d e7 mov %bl,-0x19(%ebp)
6d3: 6a 01 push $0x1
6d5: 57 push %edi
6d6: ff 75 08 pushl 0x8(%ebp)
6d9: e8 5f fe ff ff call 53d <write>
6de: 8b 55 d4 mov -0x2c(%ebp),%edx
} else {
putc(fd, c);
6e1: 83 c4 10 add $0x10,%esp
for(i = 0; fmt[i]; i++){
6e4: 0f b6 1e movzbl (%esi),%ebx
6e7: 83 c6 01 add $0x1,%esi
6ea: 84 db test %bl,%bl
6ec: 74 71 je 75f <printf+0xcf>
c = fmt[i] & 0xff;
6ee: 0f be cb movsbl %bl,%ecx
6f1: 0f b6 c3 movzbl %bl,%eax
if(state == 0){
6f4: 85 d2 test %edx,%edx
6f6: 74 c8 je 6c0 <printf+0x30>
}
} else if(state == '%'){
6f8: 83 fa 25 cmp $0x25,%edx
6fb: 75 e7 jne 6e4 <printf+0x54>
if(c == 'd'){
6fd: 83 f8 64 cmp $0x64,%eax
700: 0f 84 9a 00 00 00 je 7a0 <printf+0x110>
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
706: 81 e1 f7 00 00 00 and $0xf7,%ecx
70c: 83 f9 70 cmp $0x70,%ecx
70f: 74 5f je 770 <printf+0xe0>
printint(fd, *ap, 16, 0);
ap++;
} else if(c == 's'){
711: 83 f8 73 cmp $0x73,%eax
714: 0f 84 d6 00 00 00 je 7f0 <printf+0x160>
s = "(null)";
while(*s != 0){
putc(fd, *s);
s++;
}
} else if(c == 'c'){
71a: 83 f8 63 cmp $0x63,%eax
71d: 0f 84 8d 00 00 00 je 7b0 <printf+0x120>
putc(fd, *ap);
ap++;
} else if(c == '%'){
723: 83 f8 25 cmp $0x25,%eax
726: 0f 84 b4 00 00 00 je 7e0 <printf+0x150>
write(fd, &c, 1);
72c: 83 ec 04 sub $0x4,%esp
72f: c6 45 e7 25 movb $0x25,-0x19(%ebp)
733: 6a 01 push $0x1
735: 57 push %edi
736: ff 75 08 pushl 0x8(%ebp)
739: e8 ff fd ff ff call 53d <write>
putc(fd, c);
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
putc(fd, c);
73e: 88 5d e7 mov %bl,-0x19(%ebp)
write(fd, &c, 1);
741: 83 c4 0c add $0xc,%esp
744: 6a 01 push $0x1
746: 83 c6 01 add $0x1,%esi
749: 57 push %edi
74a: ff 75 08 pushl 0x8(%ebp)
74d: e8 eb fd ff ff call 53d <write>
for(i = 0; fmt[i]; i++){
752: 0f b6 5e ff movzbl -0x1(%esi),%ebx
putc(fd, c);
756: 83 c4 10 add $0x10,%esp
}
state = 0;
759: 31 d2 xor %edx,%edx
for(i = 0; fmt[i]; i++){
75b: 84 db test %bl,%bl
75d: 75 8f jne 6ee <printf+0x5e>
}
}
}
75f: 8d 65 f4 lea -0xc(%ebp),%esp
762: 5b pop %ebx
763: 5e pop %esi
764: 5f pop %edi
765: 5d pop %ebp
766: c3 ret
767: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
76e: 66 90 xchg %ax,%ax
printint(fd, *ap, 16, 0);
770: 83 ec 0c sub $0xc,%esp
773: b9 10 00 00 00 mov $0x10,%ecx
778: 6a 00 push $0x0
77a: 8b 5d d0 mov -0x30(%ebp),%ebx
77d: 8b 45 08 mov 0x8(%ebp),%eax
780: 8b 13 mov (%ebx),%edx
782: e8 59 fe ff ff call 5e0 <printint>
ap++;
787: 89 d8 mov %ebx,%eax
789: 83 c4 10 add $0x10,%esp
state = 0;
78c: 31 d2 xor %edx,%edx
ap++;
78e: 83 c0 04 add $0x4,%eax
791: 89 45 d0 mov %eax,-0x30(%ebp)
794: e9 4b ff ff ff jmp 6e4 <printf+0x54>
799: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
printint(fd, *ap, 10, 1);
7a0: 83 ec 0c sub $0xc,%esp
7a3: b9 0a 00 00 00 mov $0xa,%ecx
7a8: 6a 01 push $0x1
7aa: eb ce jmp 77a <printf+0xea>
7ac: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
putc(fd, *ap);
7b0: 8b 5d d0 mov -0x30(%ebp),%ebx
write(fd, &c, 1);
7b3: 83 ec 04 sub $0x4,%esp
putc(fd, *ap);
7b6: 8b 03 mov (%ebx),%eax
write(fd, &c, 1);
7b8: 6a 01 push $0x1
ap++;
7ba: 83 c3 04 add $0x4,%ebx
write(fd, &c, 1);
7bd: 57 push %edi
7be: ff 75 08 pushl 0x8(%ebp)
putc(fd, *ap);
7c1: 88 45 e7 mov %al,-0x19(%ebp)
write(fd, &c, 1);
7c4: e8 74 fd ff ff call 53d <write>
ap++;
7c9: 89 5d d0 mov %ebx,-0x30(%ebp)
7cc: 83 c4 10 add $0x10,%esp
state = 0;
7cf: 31 d2 xor %edx,%edx
7d1: e9 0e ff ff ff jmp 6e4 <printf+0x54>
7d6: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
7dd: 8d 76 00 lea 0x0(%esi),%esi
putc(fd, c);
7e0: 88 5d e7 mov %bl,-0x19(%ebp)
write(fd, &c, 1);
7e3: 83 ec 04 sub $0x4,%esp
7e6: e9 59 ff ff ff jmp 744 <printf+0xb4>
7eb: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
7ef: 90 nop
s = (char*)*ap;
7f0: 8b 45 d0 mov -0x30(%ebp),%eax
7f3: 8b 18 mov (%eax),%ebx
ap++;
7f5: 83 c0 04 add $0x4,%eax
7f8: 89 45 d0 mov %eax,-0x30(%ebp)
if(s == 0)
7fb: 85 db test %ebx,%ebx
7fd: 74 17 je 816 <printf+0x186>
while(*s != 0){
7ff: 0f b6 03 movzbl (%ebx),%eax
state = 0;
802: 31 d2 xor %edx,%edx
while(*s != 0){
804: 84 c0 test %al,%al
806: 0f 84 d8 fe ff ff je 6e4 <printf+0x54>
80c: 89 75 d4 mov %esi,-0x2c(%ebp)
80f: 89 de mov %ebx,%esi
811: 8b 5d 08 mov 0x8(%ebp),%ebx
814: eb 1a jmp 830 <printf+0x1a0>
s = "(null)";
816: bb 6c 08 00 00 mov $0x86c,%ebx
while(*s != 0){
81b: 89 75 d4 mov %esi,-0x2c(%ebp)
81e: b8 28 00 00 00 mov $0x28,%eax
823: 89 de mov %ebx,%esi
825: 8b 5d 08 mov 0x8(%ebp),%ebx
828: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
82f: 90 nop
write(fd, &c, 1);
830: 83 ec 04 sub $0x4,%esp
s++;
833: 83 c6 01 add $0x1,%esi
836: 88 45 e7 mov %al,-0x19(%ebp)
write(fd, &c, 1);
839: 6a 01 push $0x1
83b: 57 push %edi
83c: 53 push %ebx
83d: e8 fb fc ff ff call 53d <write>
while(*s != 0){
842: 0f b6 06 movzbl (%esi),%eax
845: 83 c4 10 add $0x10,%esp
848: 84 c0 test %al,%al
84a: 75 e4 jne 830 <printf+0x1a0>
84c: 8b 75 d4 mov -0x2c(%ebp),%esi
state = 0;
84f: 31 d2 xor %edx,%edx
851: e9 8e fe ff ff jmp 6e4 <printf+0x54>
| 33.708967 | 60 | 0.41559 |
25fc28dc0e7c2e17bd461b4de20121a45ed6d2d0 | 2,423 | asm | Assembly | src/3_rainbow/rainbow.asm | redconfetti/atari-asm | bff5c0dc5c7437a7d73f1b7b733b661b36aee9b0 | [
"MIT"
] | null | null | null | src/3_rainbow/rainbow.asm | redconfetti/atari-asm | bff5c0dc5c7437a7d73f1b7b733b661b36aee9b0 | [
"MIT"
] | null | null | null | src/3_rainbow/rainbow.asm | redconfetti/atari-asm | bff5c0dc5c7437a7d73f1b7b733b661b36aee9b0 | [
"MIT"
] | null | null | null | processor 6502
include "../include/vcs.h"
include "../include/macro.h"
seg code
org $F000
Start:
CLEAN_START ; macro to safely clear memory and TIA
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Start a new frame by turning on VBLANK and VSYNC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
NextFrame:
lda #2 ; same as binary value %00000010
sta VBLANK ; turn on VBLANK
sta VSYNC ; turn on VSYNC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Generate the three lines of VSYNC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
sta WSYNC ; first scanline
sta WSYNC ; second scanline
sta WSYNC ; third scanline
lda #0
sta VSYNC ; turn off VSYNC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Let the TIA output the recommended 37 scanlines of VBLANK
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ldx #37 ; X = 37 (to count 37 scanlines)
LoopVBlank:
sta WSYNC ; hit WSYNC and wait for the next scanline
dex ; X--
bne LoopVBlank ; loop while X != 0
lda #0
sta VBLANK ; turn off VBLANK
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Draw 192 visible scanlines (kernel)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ldx #192 ; counter for 192 visible scanlines
LoopVisible:
stx COLUBK ; set the background color
sta WSYNC ; wait for the next scanline
dex ; X--
bne LoopVisible ; loop while X != 0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Output 30 more VBLANK lines (overscan) to complete our frame
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
lda #2 ; hit and turn on VBLANK again
sta VBLANK
ldx #30 ; counter for 30 scanlines
LoopOverscan:
sta WSYNC ; wait for the next scanline
dex ; X--
bne LoopOverscan ; loop while X != 0
jmp NextFrame;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Complete my ROM size to 4KB
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
org $FFFC
.word Start
.word Start
| 33.652778 | 76 | 0.383409 |
44dc349aede557d13621728e6fd11d7bddc77740 | 425 | asm | Assembly | programs/oeis/292/A292542.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/292/A292542.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | programs/oeis/292/A292542.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | ; A292542: Number of 4-cycles in the n-Sierpinski tetrahedron graph.
; 3,39,156,624,2496,9984,39936,159744,638976,2555904,10223616,40894464,163577856,654311424,2617245696,10468982784,41875931136,167503724544,670014898176,2680059592704,10720238370816,42880953483264,171523813933056,686095255732224
mul $0,2
mov $2,2
lpb $0
sub $0,1
mul $2,2
mul $4,$3
mov $1,$4
mov $3,$2
mov $4,13
lpe
div $1,12
mul $1,9
add $1,3
| 25 | 227 | 0.752941 |
852e9874094136a70e584bab0bad78831635ca7d | 5,367 | asm | Assembly | Transynther/x86/_processed/AVXALIGN/_st_sm_/i9-9900K_12_0xca.log_1_639.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/AVXALIGN/_st_sm_/i9-9900K_12_0xca.log_1_639.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/AVXALIGN/_st_sm_/i9-9900K_12_0xca.log_1_639.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r14
push %rax
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x80a, %rbp
nop
nop
nop
nop
add $3299, %r14
mov (%rbp), %r11w
nop
nop
sub $60395, %rax
lea addresses_WT_ht+0x19877, %rsi
lea addresses_UC_ht+0x1bc22, %rdi
nop
nop
nop
sub %r10, %r10
mov $119, %rcx
rep movsq
nop
nop
nop
sub $39419, %rbp
lea addresses_UC_ht+0x2a12, %rsi
lea addresses_A_ht+0x594a, %rdi
nop
nop
cmp $55608, %r11
mov $38, %rcx
rep movsb
nop
nop
sub %rcx, %rcx
lea addresses_UC_ht+0x1b08a, %r10
nop
nop
nop
nop
and $811, %rdi
mov $0x6162636465666768, %rax
movq %rax, %xmm5
vmovups %ymm5, (%r10)
nop
nop
nop
nop
nop
cmp $35856, %r14
lea addresses_WC_ht+0xa00a, %r10
nop
nop
nop
and $1002, %rdi
mov $0x6162636465666768, %rcx
movq %rcx, (%r10)
nop
nop
nop
inc %rax
lea addresses_normal_ht+0x1a93a, %r11
cmp %rbp, %rbp
mov (%r11), %cx
nop
nop
mfence
lea addresses_A_ht+0x1c4ce, %rsi
nop
nop
nop
inc %rdi
movb (%rsi), %cl
nop
and %rcx, %rcx
lea addresses_normal_ht+0xc60a, %rcx
nop
nop
nop
nop
nop
sub $57361, %rax
vmovups (%rcx), %ymm7
vextracti128 $1, %ymm7, %xmm7
vpextrq $1, %xmm7, %r10
nop
nop
and %r10, %r10
lea addresses_UC_ht+0x1eb0a, %rsi
lea addresses_WC_ht+0x1370a, %rdi
clflush (%rdi)
nop
nop
xor $22098, %r11
mov $122, %rcx
rep movsq
nop
nop
nop
nop
nop
and $65356, %rdi
lea addresses_WC_ht+0x141aa, %r10
add $32754, %rsi
movb (%r10), %al
nop
sub $54146, %rcx
lea addresses_D_ht+0x11df2, %rsi
lea addresses_D_ht+0x4f0a, %rdi
nop
nop
inc %rbp
mov $86, %rcx
rep movsq
nop
nop
nop
dec %r11
lea addresses_WC_ht+0x1570a, %rdi
nop
nop
nop
nop
and %r14, %r14
movl $0x61626364, (%rdi)
cmp %r11, %r11
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %rax
pop %r14
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r15
push %r8
push %rax
push %rbx
push %rcx
push %rdi
push %rsi
// Store
lea addresses_A+0x816a, %rcx
nop
nop
nop
nop
nop
cmp $59495, %rbx
mov $0x5152535455565758, %r8
movq %r8, %xmm5
vmovups %ymm5, (%rcx)
nop
nop
nop
nop
and $28976, %rax
// Store
lea addresses_D+0x1068a, %r11
nop
sub $33488, %r10
mov $0x5152535455565758, %r8
movq %r8, %xmm1
movups %xmm1, (%r11)
nop
nop
nop
sub %rbx, %rbx
// Store
lea addresses_US+0x1890a, %r8
nop
nop
nop
add %r15, %r15
mov $0x5152535455565758, %rbx
movq %rbx, (%r8)
nop
and %r11, %r11
// Store
lea addresses_D+0x18b0a, %rbx
nop
nop
cmp $30601, %rcx
movb $0x51, (%rbx)
cmp $41736, %r10
// REPMOV
lea addresses_WC+0x1030a, %rsi
lea addresses_D+0x1af0a, %rdi
nop
nop
inc %rbx
mov $5, %rcx
rep movsq
nop
nop
nop
nop
xor $65271, %r10
// Faulty Load
lea addresses_D+0x18b0a, %r10
nop
nop
nop
nop
cmp %rbx, %rbx
mov (%r10), %rax
lea oracles, %r8
and $0xff, %rax
shlq $12, %rax
mov (%r8,%rax,1), %rax
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rax
pop %r8
pop %r15
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'size': 2, 'NT': False, 'type': 'addresses_D', 'same': False, 'AVXalign': False, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'size': 32, 'NT': False, 'type': 'addresses_A', 'same': False, 'AVXalign': False, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'size': 16, 'NT': False, 'type': 'addresses_D', 'same': False, 'AVXalign': False, 'congruent': 7}}
{'OP': 'STOR', 'dst': {'size': 8, 'NT': False, 'type': 'addresses_US', 'same': False, 'AVXalign': False, 'congruent': 7}}
{'OP': 'STOR', 'dst': {'size': 1, 'NT': True, 'type': 'addresses_D', 'same': True, 'AVXalign': False, 'congruent': 0}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_WC', 'congruent': 11}, 'dst': {'same': False, 'type': 'addresses_D', 'congruent': 7}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'size': 8, 'NT': False, 'type': 'addresses_D', 'same': True, 'AVXalign': True, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'size': 2, 'NT': False, 'type': 'addresses_D_ht', 'same': True, 'AVXalign': False, 'congruent': 8}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_WT_ht', 'congruent': 0}, 'dst': {'same': True, 'type': 'addresses_UC_ht', 'congruent': 2}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_UC_ht', 'congruent': 3}, 'dst': {'same': False, 'type': 'addresses_A_ht', 'congruent': 6}}
{'OP': 'STOR', 'dst': {'size': 32, 'NT': False, 'type': 'addresses_UC_ht', 'same': False, 'AVXalign': False, 'congruent': 5}}
{'OP': 'STOR', 'dst': {'size': 8, 'NT': False, 'type': 'addresses_WC_ht', 'same': True, 'AVXalign': False, 'congruent': 6}}
{'OP': 'LOAD', 'src': {'size': 2, 'NT': False, 'type': 'addresses_normal_ht', 'same': False, 'AVXalign': False, 'congruent': 4}}
{'OP': 'LOAD', 'src': {'size': 1, 'NT': False, 'type': 'addresses_A_ht', 'same': False, 'AVXalign': False, 'congruent': 1}}
{'OP': 'LOAD', 'src': {'size': 32, 'NT': False, 'type': 'addresses_normal_ht', 'same': False, 'AVXalign': False, 'congruent': 7}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_UC_ht', 'congruent': 8}, 'dst': {'same': False, 'type': 'addresses_WC_ht', 'congruent': 10}}
{'OP': 'LOAD', 'src': {'size': 1, 'NT': False, 'type': 'addresses_WC_ht', 'same': False, 'AVXalign': False, 'congruent': 3}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_D_ht', 'congruent': 2}, 'dst': {'same': False, 'type': 'addresses_D_ht', 'congruent': 8}}
{'OP': 'STOR', 'dst': {'size': 4, 'NT': True, 'type': 'addresses_WC_ht', 'same': False, 'AVXalign': False, 'congruent': 10}}
{'52': 1}
52
*/
| 20.026119 | 149 | 0.648593 |
34b89a2f6354b259d3549f5ebdfa35801c1529c3 | 6,020 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca.log_21829_222.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca.log_21829_222.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca.log_21829_222.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r13
push %r15
push %r8
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_WC_ht+0xaa4e, %rdx
xor $25435, %r8
movups (%rdx), %xmm6
vpextrq $0, %xmm6, %rsi
inc %r13
lea addresses_UC_ht+0x5e, %rsi
lea addresses_WC_ht+0x3cbe, %rdi
clflush (%rsi)
nop
nop
nop
nop
inc %r13
mov $4, %rcx
rep movsw
nop
nop
sub %rdi, %rdi
lea addresses_D_ht+0x9ace, %rsi
lea addresses_WC_ht+0x64ce, %rdi
clflush (%rdi)
nop
nop
nop
xor $29100, %r13
mov $91, %rcx
rep movsq
nop
nop
nop
cmp %rcx, %rcx
lea addresses_D_ht+0xe9ce, %rcx
nop
nop
nop
and %r15, %r15
mov (%rcx), %r13w
sub %rsi, %rsi
lea addresses_D_ht+0x14f4e, %rcx
nop
nop
nop
nop
cmp $32337, %rdi
mov $0x6162636465666768, %r8
movq %r8, %xmm6
and $0xffffffffffffffc0, %rcx
movntdq %xmm6, (%rcx)
nop
nop
nop
cmp %rcx, %rcx
lea addresses_D_ht+0x2e2e, %rdi
and $2730, %rsi
and $0xffffffffffffffc0, %rdi
movaps (%rdi), %xmm2
vpextrq $0, %xmm2, %rdx
nop
nop
nop
nop
nop
sub $65226, %rsi
lea addresses_normal_ht+0x7f19, %rsi
lea addresses_D_ht+0xb183, %rdi
nop
and %rdx, %rdx
mov $69, %rcx
rep movsb
nop
nop
nop
nop
sub %rdi, %rdi
lea addresses_WC_ht+0x156ce, %rcx
nop
nop
nop
nop
nop
sub %r13, %r13
movups (%rcx), %xmm5
vpextrq $1, %xmm5, %r8
nop
nop
and $19590, %rcx
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %r8
pop %r15
pop %r13
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r15
push %r8
push %r9
push %rax
push %rbp
// Faulty Load
lea addresses_D+0x1f2ce, %r12
nop
xor %rbp, %rbp
movb (%r12), %al
lea oracles, %r12
and $0xff, %rax
shlq $12, %rax
mov (%r12,%rax,1), %rax
pop %rbp
pop %rax
pop %r9
pop %r8
pop %r15
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'size': 1, 'NT': False, 'type': 'addresses_D', 'same': False, 'AVXalign': False, 'congruent': 0}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'size': 1, 'NT': False, 'type': 'addresses_D', 'same': True, 'AVXalign': False, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_WC_ht', 'same': False, 'AVXalign': False, 'congruent': 7}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_UC_ht', 'congruent': 4}, 'dst': {'same': False, 'type': 'addresses_WC_ht', 'congruent': 4}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_D_ht', 'congruent': 10}, 'dst': {'same': False, 'type': 'addresses_WC_ht', 'congruent': 6}}
{'OP': 'LOAD', 'src': {'size': 2, 'NT': True, 'type': 'addresses_D_ht', 'same': True, 'AVXalign': False, 'congruent': 7}}
{'OP': 'STOR', 'dst': {'size': 16, 'NT': True, 'type': 'addresses_D_ht', 'same': False, 'AVXalign': False, 'congruent': 3}}
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_D_ht', 'same': False, 'AVXalign': True, 'congruent': 4}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_normal_ht', 'congruent': 0}, 'dst': {'same': False, 'type': 'addresses_D_ht', 'congruent': 0}}
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_WC_ht', 'same': False, 'AVXalign': False, 'congruent': 5}}
{'36': 21829}
36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
| 40.402685 | 2,999 | 0.659302 |
719dbeb3570f0f2058b42a448cb3a6bc19f4ca85 | 26,920 | asm | Assembly | cpm/ndos/ndos.asm | erikp9000/cpm-ndos | d2e17f3aa11e22d30510278e78814151934355d2 | [
"MIT"
] | null | null | null | cpm/ndos/ndos.asm | erikp9000/cpm-ndos | d2e17f3aa11e22d30510278e78814151934355d2 | [
"MIT"
] | 7 | 2020-06-03T01:12:06.000Z | 2020-06-12T19:11:33.000Z | cpm/ndos/ndos.asm | erikp9000/cpm-ndos | d2e17f3aa11e22d30510278e78814151934355d2 | [
"MIT"
] | null | null | null | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; NDOS.ASM
;;
;; To build NDOS.SPR:
;; RMAC NDOS $PZ SZ
;; LINK NDOS[OS]
;;
;; This file assembles to NDOS.SPR which is a page relocatable
;; file meant to run just below the NIOS.SPR which itself
;; is meant to run just below the BDOS.
;;
;; +-----------------+
;; | BIOS |
;; +-----------------+
;; | BDOS |
;; +-----------------+
;; | NIOS |
;; +-----------------+
;; | NDOS |
;; +-----------------+
;; | TPA |
;; | |
;; +-----------------+
;; | 0005 JMP NDOS+6 |
;; +-----------------+
;; | 0000 JMP BIOS |
;; +-----------------+
;;
;;
;; The NDOS loader loads the NIOS.SPR into the pages just below
;; the BDOS and loads the NDOS.SPR into the pages just below
;; the NIOS. The NDOS finds the NIOS jump table by assuming
;; that the very next page following NDOS is NIOS. After the loader
;; fixes-up all of the relocation bytes, it jumps to the NDOSCOLD
;; entry (NDOS+9). The NDOS updates the BDOS vector on page 0
;; to point to the NDOS which protects the NDOS and BIOS from
;; being overwritten by other transient programs. NDOS also updates
;; the BIOS jump table to point the warm start to the warm
;; entry so that NDOS can load the CCP.
;;
;; NDOS requires a relocatable CCP.COM on drive A.
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
maclib ndos
NDOSVER equ 12h ; packed binary coded decimal
NDOSDSK equ 15 ; drive P is the network drive
RETRYCNT equ 3 ; number of transceive attempts before failure
; NIOS entry points
NIOSINIT equ 0
NIOSSMSG equ 3
NIOSRMSG equ 6
NIOSSTAT equ 9
FCB?EX equ 12 ; extent (0-31)
FCB?S2 equ 14 ; extent counter (0-15)
FCB?RC equ 15 ; records used in this extent (0-127)
FCB?AV equ 16 ; bytes 16-31 are the disk allocation vector
FCB?CR equ 32 ; current record in this extent (0-127)
FCB?R0 equ 33 ; low-byte of random record #
FCB?R1 equ 34 ; high-byte of random record #
FCB?R2 equ 35 ; overflow of R1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Resident Network DOS image starts here
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
firstaddr:
; This makes CCP.COM happy
db 0,22,0,0,0,0 ; serial number
entry: jmp begin ; standard entry point
jmp cold ; cold start entry - hook vectors & init NIOS
jmp warm ; warm start entry - load CCP.COM
; bdosadr and warmst are set by cold from page 0 values
; before cold redirects BDOS calls to NDOS and hooks
; the BIOS warm start vector in the jump table.
bdosadr:jmp 0 ; Original BDOS address
warmst: hlt ; Original BIOS Warm Start - The BIOS
dw 0 ; reloads the BDOS and original CCP from
; the system tracks. Don't call/jmp here
; without restoring the BIOS warm start
; in the BIOS jump table or the next
; warm start will crash the system because
; NDOS will be gone.
restore:jmp remove ; Restore vectors & unload NDOS
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; local variables
fcb:
db 1,'CCP COM',0,0,0,0
db 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
db 0 ; cr
noccpmsg:
db cr,lf,'CCP.COM not found',cr,lf
db '$'
filed:
db cr,lf,'CCP.COM loaded',cr,lf
db '$'
panicmsg:
db cr,lf,cr,lf,'**** NDOS panic '
panicarg:
db 'XX ****',cr,lf
db '$'
functbl:
; BDOS function table
; 0 1 2 3 4 5 6 7
dw gobdos, gobdos, gobdos, gobdos, gobdos, gobdos, gobdos, gobdos
; 8 9 10 11 12 13 14 15
dw gobdos, gobdos, gobdos, gobdos, gobdos,rstdskv,seldskv, openfv
; 16 17 18 19 20 21 22 23
dw closefv, srchfv, srchnv,deletfv, readfv,writefv,creatfv,renamfv
; 24 25 26 27 28 29 30 31
dw gobdos,getdskv,setdmav, allocv, gobdos, gobdos,setatrv,dskprmv
; 32 33 34 35 36 37 38 39
dw gobdos, readrv,writerv, getszv, setrrv, gobdos, gobdos, gobdos
; 40
dw wrtrfv
functblend:
nfuncs equ (functblend-functbl)/2
;
; Fake disk parameter block
;
dpb:
dw 0 ; SPT sectors per track
db 3 ; BSH allocation block shift factor
db 7 ; BLM allocation block mask
db 0 ; EXM extent mask
dw 15 ; DSM drive storage capacity
dw 511 ; DRM directory entries
db 0ffh,0ffh ; AL0,AL1 directory reserved blocks
dw 0 ; CHK size of directory checksum vector
dw 0 ; OFF reserved tracks
;
; Fake allocation vector - represents 16KB which is the "size" of our
; directory. Anyone who looks will conclude that the drive is full but
; we don't have to reserve memory for a meaningless allocation vector.
;
alvs:
db 0ffh,0ffh
; In the eventuality that an app requires drive space to run
; the two bytes above plus the following are needed fo DSM = 242.
;db 0,0,0,0,0,0, 0,0,0,0,0,0,0,0
;db 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0
;db 0
sbuf:
ds 140 ; network send buffer
rbuf:
ds 140 ; network receive buffer
active:
db 0 ; current default drive
params:
dw 0 ; de input parameter
dmaaddr:
dw 0 ; the DMA address
savefcb:
dw 0 ; FCB address for Search for next
fndactive:
db 0ffh ; flag for Search for next
fndextent:
db 0 ; Search file extent flag
status:
dw 0 ; return code
userstk:
dw 0 ; storage for user stack pointer
niospage:
db 0 ; page where NIOS starts
biospage:
db 0 ; page where BIOS starts
backupser:
db 0,22,0,0,0,0 ; backup serial number
ds 16
stack: ; NDOS stack
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; NDOS cold start entry point - NDOS/NIOS loader jumps here
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
cold: lda niospage ; check if this is first time
ora a
jnz doinit ; if we are already loaded, just init NIOS
lxi h,lastaddr ; get last byte of NDOS
mov a,h ; a = last page of NDOS
inr a ; a = first page of NIOS
sta niospage
lhld bdosv+1 ; get BDOS entry address
shld bdosadr+1 ; save original BDOS entry locally
lxi d,warm ; DE points to our warm start
lhld warmv+1 ; get BIOS warm start
inx h ; skip JMP byte in BIOS jump table
mov a,m ; low-byte of warm start function
sta warmst+1
mov m,e ; update BIOS jump table
inx h
mov a,m ; high-byte
sta warmst+2
mov m,d ; update BIOS jump table
mov a,h ; BIOS page
sta biospage
doinit: call init ; initialize the NIOS
; TODO check the return value...
; fall through to warm start
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; NDOS warm start entry point - the BIOS hook comes here
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
warm: lxi sp,stack ; set stack pointer
mvi a,0c3h ; JMP opcode
sta warmv
sta bdosv
lxi h,entry ; get NDOS entry address
shld bdosv+1 ; update BDOS vector so we are protected
lda biospage
mov h,a
mvi l,3
shld warmv+1
;
; Load CCP.COM from default drive
;
mvi a,76h ; opcode for HLT
sta tpa ; store HLT in TPA in case load fails
xra a
mvi c,openf
lxi d,fcb
call resetfcb ; set S2=EX=CR=0
call bdosadr
inr a
jz noccp
lxi d,tpa
loadloop:
push d ; store tpa address
mvi c,setdma
call bdosadr
mvi c,readf
lxi d,fcb
call bdosadr
pop h ; recover tpa address
ora a
jnz done
lxi d,128
dad d ; advance to next block in tpa
xchg ; swap hl and de
jmp loadloop
done:
mvi c,closef
lxi d,fcb
call bdosadr
mvi c,prnstr
lxi d,filed
call bdosadr
lxi d,defdma
mvi c,setdma
call bdosadr
lxi sp,tpa ; set stack pointer
;
; Copy six serial number bytes from backup
; Some programs overwrite the serial number (probably stack)
; which causes CCP.COM to HALT when trying to load a transient program
;
mvi c,6
lxi h,backupser ; backup serial number
lxi d,firstaddr ; start of NDOS
call copybytes
jmp tpa ; start CCP
noccp: mvi c,prnstr
lxi d,noccpmsg
call bdosadr
; fall-through to remove
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; NDOS kill entry point - removes BDOS and BIOS hooks & warm starts
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
remove: lhld warmv+1 ; get BIOS warm start vector
inx h ; skip JMP byte
lda warmst+1 ; get old BIOS warm start
mov m,a ; update BIOS jump table
inx h
lda warmst+2
mov m,a ; update BIOS jump table
rst 0 ; warm start!
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; BDOS/NDOS entry point - the BDOS hook comes here
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
begin: xchg ; swap de into hl
shld params ; save input params
xchg ; swap de back
lxi h,0 ; 0=success
shld status
dad sp ; get user stack pointer
shld userstk ; save user stack pointer
lxi sp,stack ; change to NDOS internal stack
; perform an indirect call by pushing 'return' onto the stack
lxi h,return
push h
mov a,c ; check function code for NDOS functions
cpi n?ver
jz retver
cpi n?smsg
jz smsg
cpi n?rmsg
jz rmsg
cpi n?stats
jz retstats
cpi n?init
jz init
cpi nfuncs
jnc gobdos ; unrecognized function code, goto BDOS
lxi h,functbl ; function table
mov e,a ; copy function code to e
mvi d,0
dad d
dad d ; hl = hl + (2 * (function code))
mov e,m
inx h
mov d,m ; de = function jump vector
lhld params ; restore input params
xchg ; de=params, hl=jump address
pchl ; jump to indexed function
;
; Return status to caller - NDOS calls return through here
;
return:
lhld userstk ; recover user stack pointer into hl
sphl ; set sp from hl
lhld status
mov b,h
mov a,l
ret
;
; We don't handle the function, send it to BDOS
;
gobdos:
lhld userstk ; recover user stack pointer into hl
sphl ; set sp from hl
jmp bdosadr
;
; Return NDOS version
;
; Inputs:
; None
; Outputs:
; a = 10h (1.0)
;
retver: mvi a,NDOSVER
sta status
ret
;
; Initialize the network
;
; Inputs:
; None
; Outputs:
; a = 0(success)/FF(failure)
;
init: mvi a,NIOSINIT
; fall-through to gonios
gonios: lxi h,savestatus
push h ; push return address
mov l,a
lda niospage
mov h,a
pchl ; jump to NIOS function
savestatus:
shld status ; save status
ret ; a = 0(success)/FF(failure)
;
; Send message
;
; Inputs:
; de = pointer to buffer: |LEN|DATA ...|CHK|
; where LEN includes LEN and CHK bytes
; and CHK=0. This function will compute
; CHK and update the buffer.
; LEN = 2 + count of DATA bytes
; Outputs:
; a = 0(success)/FF(failure)
;
smsg: mvi a,NIOSSMSG
jmp gonios
;
; Receive message
;
; Inputs:
; de = pointer to 256-byte buffer
; Outputs:
; a = 0(success)/FF(failure)
; buffer will contain message: |LEN|DATA ...|CHK|
; LEN = 2 + count of DATA bytes
;
rmsg: mvi a,NIOSRMSG
jmp gonios
;
; Return pointer to packet stats
;
; Inputs:
; None
; Outputs:
; hl = pointer
;
retstats:
mvi a,NIOSSTAT
jmp gonios
;
; Set DMA address
;
; Inputs:
; de = DMA address
; Outputs:
; None
;
setdmav:
xchg
shld dmaaddr
xchg
jmp gobdos ; send DMA address to BDOS too
;
; Reset disk system - sets DMA to default address
;
; Inputs:
; None
; Outputs:
; None
;
rstdskv:
lxi h,defdma
shld dmaaddr
xra a
sta active
jmp gobdos ; let BDOS handle the local disks
;
; Select default drive
;
; Inputs:
; e = default disk
; Outputs:
; None
;
seldskv:
mov a,e
sta active ; remember the currently active drive
cpi NDOSDSK ; is it our disk #?
jnz gobdos ; unknown drive, let bdos handle it
ret ; it's the network drive
;
; Get default drive
;
; Inputs:
; None
; Outputs:
; a = default disk
;
getdskv:
lda active
cpi NDOSDSK ; is it our disk #?
jnz gobdos ; unknown drive, let bdos handle it
sta status
ret ; it's the network drive
;
; Get disk parameter block for default drive
;
; Inputs:
; None
; Outputs:
; hl = address of disk param block for current drive
;
dskprmv:
lda active
cpi NDOSDSK ; is it our disk #?
jnz gobdos ; unknown drive, let bdos handle it
lxi h,dpb
shld status
ret
;
; Get allocation for default drive
;
; Inputs:
; None
; Outputs:
; hl = address of allocation vector for current drive
;
allocv:
lda active
cpi NDOSDSK ; is it our disk #?
jnz gobdos ; unknown drive, let bdos handle it
lxi h,alvs
shld status
ret
; internal subroutine to check if FCB at de is selecting the network disk
isnetdsk:
ldax d ; get drive select from FCB
ora a ; is default drive & current user selected?
jz checkactive
cpi '?' ; is default drive & all users selected?
jz checkactive
dcr a ; convert 1-16 to 0-15
jmp checkdisk
checkactive:
lda active ; get selected disk #
checkdisk:
cpi NDOSDSK
rz ; the network disk is selected, return
pop h ; remove return address from stack
jmp gobdos ; goto BDOS
; internal subroutine to copy filename from FCB at de into sbuf+4
getfilename:
lhld params ; hl = FCB address
getfnsrchnv:
lxi d,sbuf+4 ; destination
getfn1:
mvi c,11 ; filename & extension
; ignoring bytes dr (byte 0 of FCB) and ex (byte 12)
inx h ; skip over drive byte
jmp copybytes
; internal subroutine to copy filename from rbuf+5 into DMA
copynamedma:
lhld dmaaddr
xchg ; de is destination
xra a
stax d ; set user code to 0
lxi h,rbuf+5 ; hl is source
mvi c,15 ; get filename, extension, ex, s1, s2, & rc
inx d
call copybytes
; Fill the FCB allocation vector assuming that a block is 1024 bytes
; and that we are using 8-bit block numbers (DSM < 256).
; This enables STAT.COM to show the file size.
; a contains rc
; de points to alloc vector-1
ora a
mvi c,0 ; no blocks allocated
mvi b,16 ; all blocks free
jz cpyfn2
mvi c,16 ; all blocks allocated
mvi b,0 ; no blocks free
jm cpyfn2
; compute # of allocated and free blocks
rrc
rrc
rrc
ani 15 ; clear msb
inr a ; add 1
mov c,a ; c is # allocated blocks
mvi a,16
sub c ; a = 16 - c
mov b,a ; b is # free blocks
cpyfn2:
mov a,c
ora a
jz cpyfn4
mvi a,3 ; use a non-zero block #
cpyfn3:
inx d
stax d
dcr c
jnz cpyfn3
cpyfn4:
mov a,b ; check # free blocks
ora a
rz
xra a ; a=0, free block #
cpyfn5:
inx d
stax d
dcr b
jnz cpyfn5
ret
; internal subroutine to convert register a (0 thru F) to hexadecimal char
getHexChar:
ani 15
cpi 10
jc less
adi 'A'-'0'-10
less:
adi '0'
ret
; send sbuf and get response into rbuf - if there is an error on receive,
; the request is retried.
; This only works because all requests are idempotent, even read & write
; because they include the seek offset in the request.
xcv:
mvi c,RETRYCNT ; C= # of retries
xcv2:
push b ; save retry counter
lxi d,sbuf
call smsg ; updates status, a = 0(success)/FF(timeout)
lxi d,rbuf
call rmsg ; updates status, a = 0(success)/FF(timeout)
pop b ; restore retry counter
ora a
rz ; success
dcr c ; decrement retry counter
jnz xcv2
ret ; timeout or checksum error
; reset record offset params in user's FCB, de = FCB address
resetfcb:
xra a
lxi h,FCB?EX
dad d
mov m,a
lxi h,FCB?S2
dad d
mov m,a
lxi h,FCB?CR
dad d
mov m,a
ret
; advance record offset params in user's FCB, de = FCB address
advfcb:
lhld params
xchg
lxi h,FCB?CR
dad d
inr m ; most-sig bit selects next extent on read/write
ret
; get FCB record count, compute and return file offset in bc
getoffset:
lhld params
xchg ; de = FCB
lxi h,FCB?CR
dad d ; hl points to CR
mov a,m
mov c,a ; c = current record
ora a
jp getoff1 ; check for overflow of CR
;
; on overflow of CR, select next extent
mvi m,0
mvi c,0 ; c = record 0 of new extent
lxi h,FCB?EX
dad d
inr m ; select next EX
mov a,m
ani 20h ; check for overflow
jz getoff1
mvi m,0 ; clear overflow of EX
lxi h,FCB?S2
dad d
inr m ; increment S2
; c = current record modulus 128, now combine S2 and EX into b and move LSB of EX into c
getoff1:
lxi h,FCB?EX
dad d ; hl points to EX
mov a,m
ani 1fh
clc
rar ; lsb of EX in carry
mov b,a ; b is now most sig. 4-bits of EX
jnc getoff2
mov a,c
ori 80h ; c = ((EX & 1)<<7) | (CR & 7Fh)
mov c,a
getoff2:
lxi h,FCB?S2
dad d ; hl points to S2
mov a,m
rlc
rlc
rlc
rlc
ani 0f0h ; a = S2 << 4
ora b
mov b,a ; b = (S2 << 4) | (EX >> 1)
ret
; return bc = random record counter from FCB
; update FCB S2, EX, and CR
getroffset:
lhld params
xchg ; de = FCB
lxi h,FCB?R0
dad d ; hl points to R0
mov c,m ; c = R0
inx h
mov b,m ; b = R1
; TODO R2 is overflow from R1, we should return an error if R2 is non-zero...
lxi h,FCB?CR
dad d ; hl points to CR
mov a,c
ani 07Fh
mov m,a ; save CR
lxi h,FCB?EX
dad d ; hl points to EX
mov a,c
ral ; carry is most-sig bit of CR
mov a,b
ral ; shift carry into EX
ani 1Fh
mov m,a ; save EX
lxi h,FCB?S2
dad d ; hl points to S2
mov a,b
rar
rar
rar
rar
ani 0Fh
mov m,a ; save S2
ret
; setup network send buffer
; call with b=length, c=network command byte, de=FCB address
setupbuf:
mov a,b ; network packet length
sta sbuf
mov a,c ; network command
sta sbuf+1
mov a,e ; FCB address serves as handle
sta sbuf+2
mov a,d
sta sbuf+3
ret
; copy # of bytes in c from hl to de
copybytes:
mov a,m ; read byte at hl
stax d ; write to de
inx h
inx d
dcr c
jnz copybytes
ret
;
; Search for first
;
; Inputs:
; de = FCB address
; Outputs:
; a = 0(success)/FF(failure)
; writes the returned directory entry to dmaaddr
;
srchfv:
mvi a,0ffh
sta fndactive ; reset Search for next signal
call isnetdsk ; doesn't return if not network disk
lhld params
shld savefcb ; save FCB address for Search for next
mvi b,10h ; message length
mvi c,NFNDFST ; network command
call setupbuf
call getfilename ; copy filename from FCB
; hl points to EX-1
inx h
mov a,m
sta fndextent ; save extent filter for Search for next
srchret:
call xcv
ora a
rnz ; xcv sets status
srchrt2:
call copynamedma ; copy matching filename to DMA address
lda rbuf+4 ; status, 0=success, 0xFF=end of directory
sta fndactive ; if done, signal to Search for next
sta status
ret
;
; Search for next
;
; Inputs:
; None
; Outputs:
; a = 0(success)/FF(failure)
; writes the returned directory entry to dmaaddr
;
srchnv:
lda fndactive
ora a
jnz gobdos ; find disk is not network disk
lhld savefcb ; recover FCB address
xchg ; move to de
; If EX was '?', match all extents; else, match only the specified extent
lda fndextent ; EX byte from Search for first
cpi '?'
jnz srchn1 ; get the next filename
; If the file would use multiple extents, we must generate and
; return each extent to the caller or they cannot compute the
; correct file size (e.g., STAT.COM counts extents).
; Presently only handling files with 32 extents (524288 bytes, 512KB)
lxi h,rbuf+5+11 ; extent byte
dcr m
jm srchn1 ; we reported the last extent, get next filename from server
inx h
inx h
inx h
mvi m,80h ; this extent will be full
jmp srchrt2
srchn1:
mvi b,10h ; message length
mvi c,NFNDNXT ; network command
; de already contains FCB address (which we use as a file handle)
call setupbuf
; This allows the caller to change the search filter between Seach for first
; and Search for next. This is a little quirk of CP/M which lets programs
; specify from where in the directory the Search for next will begin.
xchg ; hl = FCB
call getfnsrchnv ; copy filename from FCB
jmp srchret
;
; Open file
;
; Inputs:
; de = FCB
; Outputs:
; a = 0(success)/FF(failure)
;
openfv:
call isnetdsk ; doesn't return if not network disk
call resetfcb
mvi b,10h ; message length
mvi c,NOPENF ; network command
; de contains FCB address (which we use as a file handle)
xcvwithfn:
call setupbuf ; setup sbuf header
call getfilename ; copy filename from FCB
xcvnofn:
call xcv ; send sbuf, get response in rbuf
ora a
rnz ; xcv sets status
lda rbuf+4 ; status
sta status
lhld params ; get uses's FCB
lxi d,FCB?AV ; point to disk allocation vector
dad d
lda rbuf+2 ; get file handle from server
mov m,a ; write to user's FCB
inx h ; next byte of file handle
lda rbuf+3 ; get file handle 2's complement from server
mov m,a ; write to user's FCB
ret
;
; Delete file
;
; Inputs:
; de = FCB
; Outputs:
; a = 0(success)/FF(error)
;
deletfv:
call isnetdsk ; doesn't return if not network disk
mvi b,10h ; message length
mvi c,NDELETF ; network command
jmp xcvwithfn
;
; Create file
;
; Inputs:
; de = FCB
; Outputs:
; a = 0(success)/FF(error)
;
creatfv:
call isnetdsk ; doesn't return if not network disk
call resetfcb
mvi b,10h ; message length
mvi c,NCREATF ; network command
jmp xcvwithfn
;
; Close file
;
; Inputs:
; de = FCB
; Outputs:
; a = 0(success)/FF(failure)
;
closefv:
call isnetdsk ; doesn't return if not network disk
mvi b,5 ; message length
mvi c,NCLOSEF ; network command
; de contains FCB address (which we use as a file handle)
lxi h,FCB?AV
dad d
mov e,m
inx h
mov d,m
call setupbuf ; setup sbuf header
jmp xcvnofn
;
; Read file
;
; Inputs:
; de = FCB
; Outputs:
; a = 0(success)/1(end of file)/FF(failure)
;
readfv:
call isnetdsk ; doesn't return if not network disk
call getoffset ; bc = file offset from FCB S2,EX,CR
call netread
rnz ; error
jmp advfcb ; auto-advance the FCB record counters
; send network file read, bc=file offset
netread:
push b
mvi b,7 ; message length
mvi c,NREADF ; network command
; de contains FCB address, extract file handle
lxi h,FCB?AV
dad d ; point to file handle
mov e,m
inx h
mov d,m
call setupbuf ; setup sbuf header
pop b ; get file offset in bc
mov a,c
sta sbuf+4
mov a,b
sta sbuf+5
call xcv ; transmit sbuf & get response in rbuf
ora a
rnz ; xcv sets status
lda rbuf+4 ; status from server
sta status
ora a ; set/clear Z flag
rnz ; return error code
; copy 128 bytes starting at rbuf+5 to DMA address
mvi c,128 ; # bytes to copy
lxi d,rbuf+5 ; source
lhld dmaaddr ; destination
xchg ; de=destination, hl=source
call copybytes ; copy c bytes from de to hl
xra a
ret
;
; Write file
;
; Inputs:
; de = FCB
; Outputs:
; a = 0(success)/FF(error)
;
writefv:
call isnetdsk ; doesn't return if not network disk
call getoffset ; bc = file offset from FCB S2,EX,CR
call netwrite ; returns a = status
rnz ; error
jmp advfcb ; auto-advance FCB to next record
netwrite:
push b ; save file offset
mvi b,135 ; message length
mvi c,NWRITEF ; network command
; de contains FCB address, extract file handle
lxi h,FCB?AV
dad d ; point to file handle
mov e,m
inx h
mov d,m
call setupbuf ; setup sbuf header
pop b ; get file offset in bc
mov a,c
sta sbuf+4
mov a,b
sta sbuf+5
; copy 128 bytes starting at DMA address to sbuf+6
mvi c,128 ; # bytes to copy
lhld dmaaddr ; source
lxi d,sbuf+6 ; destination
call copybytes
call xcv ; send sbuf, get response in rbuf
ora a ; a=0(success)/FF(timeout)
rnz ; error
lda rbuf+4 ; status from server
sta status
ora a ; set/clear Z flag
ret
;
; Rename file
;
; Inputs:
; de = FCB
; Outputs:
; a = 0(success)/FF(error)
;
renamfv:
call isnetdsk ; doesn't return if not network disk
mvi b,27 ; message length
mvi c,NRENAMF ; network command
; de contains FCB address (which we use as a file handle)
lxi d,0
call setupbuf ; setup sbuf header
call getfilename ; old filename
lhld params ; hl = FCB address
lxi d,16
dad d ; hl = FCB + 16
lxi d,sbuf+4+11 ; destination
call getfn1 ; new filename
jmp xcvnofn
;
; Set random record
;
; Inputs:
; de = FCB
; Outputs:
; random record fields in FCB
;
setrrv:
call isnetdsk ; doesn't return if not network disk
; Read S2(14), EX(12), and CR(32) from FCB
call getoffset ; get file offset in bc
; Store bc in r0(33),r1(34),r2(35) in FCB
lxi h,FCB?R0 ; offset to r0
dad d
mov m,c ; low-byte
inx h
mov m,b ; high-byte
inx h
mvi m,0 ; overflow
ret
;
; Compute file size
;
; Inputs:
; de = FCB
; Outputs:
; random record fields in FCB
;
getszv:
jmp panic
;
; Set file attributes
;
; Inputs:
; de = FCB
; Outputs:
; a = 0(success)/FF(error)
;
setatrv:
jmp panic
;
; Read random
;
; Inputs:
; de = FCB
; Outputs:
; a = 0(success)/FF(error)
;
readrv:
call isnetdsk ; doesn't return if not network disk
call getroffset ; bc = file offset from FCB R0,R1,R2
jmp netread
;
; Write random
;
; Inputs:
; de = FCB
; Outputs:
; a = 0(success)/FF(error)
;
writerv:
call isnetdsk ; doesn't return if not network disk
call getroffset ; bc = file offset from FCB R0,R1,R2
jmp netwrite
;
; Write random w/zero fill
;
; Inputs:
; de = FCB
; Outputs:
; a = 0(success)/FF(error)
;
wrtrfv:
jmp panic
; Panic exit
panic: call isnetdsk ; doesn't return if not network disk
mov a,c ; convert function code to hexadecimal
rrc
rrc
rrc
rrc
call getHexChar
sta panicarg
mov a,c
call getHexChar
sta panicarg+1
mvi c,prnstr
lxi d,panicmsg
call 5
; We are aborting the program because it's trying to do
; something we don't support.
jmp warm ; reload CCP.COM
lastaddr:
end
| 21.24704 | 97 | 0.599629 |
969ec109ac6c4df70937077d90a4050700d556e6 | 346 | asm | Assembly | programs/oeis/029/A029105.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/029/A029105.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/029/A029105.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A029105: Expansion of 1/((1-x)(1-x^5)(1-x^11)(1-x^12)).
; 1,1,1,1,1,2,2,2,2,2,3,4,5,5,5,6,7,8,8,8,9,10,12,13,14,15,16,18,19,20,21,22,24,26,28,30,32,34,36,38,40,42,44,46,49,52,55,58,61,64,67,70,73,76,79,83,87,91,95,99,104
lpb $0
mov $2,$0
sub $0,5
seq $2,25794 ; Expansion of 1/((1-x)(1-x^11)(1-x^12)).
add $1,$2
lpe
add $1,1
mov $0,$1
| 28.833333 | 164 | 0.569364 |
2cf367729d8410e60f75ca07c178901305e5abb8 | 1,317 | asm | Assembly | CS0447/Lab4/jaw280_lab4.asm | jasonawalker/pitt-cs | 2267784b2bda82223c1f4337648b3dacb53670af | [
"MIT"
] | null | null | null | CS0447/Lab4/jaw280_lab4.asm | jasonawalker/pitt-cs | 2267784b2bda82223c1f4337648b3dacb53670af | [
"MIT"
] | null | null | null | CS0447/Lab4/jaw280_lab4.asm | jasonawalker/pitt-cs | 2267784b2bda82223c1f4337648b3dacb53670af | [
"MIT"
] | null | null | null | .data
opcode: .asciiz "\nopcode = "
rs: .asciiz "\nrs = "
rt: .asciiz "\nrt = "
immediate: .asciiz "\nimmediate = "
.text
encode_instruction:
push ra
sll t0, a0, 26
sll t1, a1, 21
sll t2, a2, 16
andi a3, a3, 0x0000FFFF
or t0, t0, t1
or t0, t0, t2
or t0, t0, a3
li v0, 34
move a0, t0
syscall
li v0, 11
li a0, 10
syscall
pop ra
jr ra
decode_instruction:
push ra
#opcoode
push a0
la a0, opcode
li v0, 4
syscall
pop a0
srl t0, a0, 26
push a0
move a0, t0
li v0, 1
syscall
pop a0
#rs
push a0
la a0, rs
li v0, 4
syscall
pop a0
srl t0, a0, 21
push a0
and a0, t0, 0x1f
li v0, 1
syscall
pop a0
#rt
push a0
la a0, rt
li v0, 4
syscall
pop a0
srl t0, a0, 16
push a0
and a0, t0, 0x1f
li v0, 1
syscall
pop a0
#immediste
push a0
la a0, immediate
li v0, 4
syscall
pop a0
move t0, a0
push a0
sll t0, t0, 16
sra t0, t0, 16
move a0, t0
li v0, 1
syscall
pop a0
pop ra
jr ra
.globl main
main:
# addi t0, s1, 123
li a0, 8
li a1, 17
li a2, 8
li a3, 123
jal encode_instruction
# beq t0, zero, -8
li a0, 4
li a1, 8
li a2, 0
li a3, -8
jal encode_instruction
li a0, 0x2228007B
jal decode_instruction
li a0, '\n'
li v0, 11
syscall
li a0, 0x1100fff8
jal decode_instruction
# exit the program cleanly
li v0, 10
syscall
| 10.452381 | 36 | 0.622627 |
536cbf4d9523b77f7b7b44105a860e5977b9adeb | 2,651 | asm | Assembly | source/modules/basic/expressions/logical.asm | paulscottrobson/mega-basic | f71750889136e2fdc4e6053c5696593318162bcf | [
"MIT"
] | 3 | 2019-12-03T06:05:24.000Z | 2021-03-24T01:51:07.000Z | source/modules/basic/expressions/logical.asm | paulscottrobson/mega-basic | f71750889136e2fdc4e6053c5696593318162bcf | [
"MIT"
] | null | null | null | source/modules/basic/expressions/logical.asm | paulscottrobson/mega-basic | f71750889136e2fdc4e6053c5696593318162bcf | [
"MIT"
] | null | null | null | ; *******************************************************************************************
; *******************************************************************************************
;
; Name : logical.asm
; Purpose : Binary Logical Operators
; Date : 21st August 2019
; Review : 1st September 2019
; Author : Paul Robson (paul@robsons.org.uk)
;
; *******************************************************************************************
; *******************************************************************************************
; *******************************************************************************************
;
; Logical Binary Operators
;
; *******************************************************************************************
BinaryOp_And: ;; and
jsr BinaryMakeBothInteger
;
lda XS_Mantissa+0,x
and XS2_Mantissa+0,x
sta XS_Mantissa+0,x
lda XS_Mantissa+1,x
and XS2_Mantissa+1,x
sta XS_Mantissa+1,x
lda XS_Mantissa+2,x
and XS2_Mantissa+2,x
sta XS_Mantissa+2,x
lda XS_Mantissa+3,x
and XS2_Mantissa+3,x
sta XS_Mantissa+3,x
rts
BinaryOp_Or: ;; or
jsr BinaryMakeBothInteger
;
lda XS_Mantissa+0,x
ora XS2_Mantissa+0,x
sta XS_Mantissa+0,x
lda XS_Mantissa+1,x
ora XS2_Mantissa+1,x
sta XS_Mantissa+1,x
lda XS_Mantissa+2,x
ora XS2_Mantissa+2,x
sta XS_Mantissa+2,x
lda XS_Mantissa+3,x
ora XS2_Mantissa+3,x
sta XS_Mantissa+3,x
rts
;
; So I'll be kind to 6502 orientated developers ;-)
;
BinaryOp_Eor: ;; eor
BinaryOp_Xor: ;; xor
jsr BinaryMakeBothInteger
;
lda XS_Mantissa+0,x
eor XS2_Mantissa+0,x
sta XS_Mantissa+0,x
lda XS_Mantissa+1,x
eor XS2_Mantissa+1,x
sta XS_Mantissa+1,x
lda XS_Mantissa+2,x
eor XS2_Mantissa+2,x
sta XS_Mantissa+2,x
lda XS_Mantissa+3,x
eor XS2_Mantissa+3,x
sta XS_Mantissa+3,x
rts
; *******************************************************************************************
;
; Routine to convert both types to integer
;
; *******************************************************************************************
BinaryMakeBothInteger:
phx ; save X
inx6 ; go to next
jsr BinaryMakeInteger ; convert to integer.
plx ; restore X and fall through.
BinaryMakeInteger:
lda XS_Type,x ; get type byte.
and #15 ; check type zero
beq _BMIConvert ; if float convert to integer.
lsr a ; if bit 0 clear it's not an integer
bcc _BMIError
rts
;
_BMIConvert:
.if hasFloat==1
jmp FPUToInteger ; convert to integer
.endif
_BMIError:
jmp TypeError
| 24.321101 | 93 | 0.473406 |
aa340e5cb0b135554a044f0eac306a18bc05c5a3 | 1,409 | asm | Assembly | crackStack.asm | nixpal/kernel32-finder | f065b2348be47211f440b82c4af34571f95a5811 | [
"MIT"
] | null | null | null | crackStack.asm | nixpal/kernel32-finder | f065b2348be47211f440b82c4af34571f95a5811 | [
"MIT"
] | null | null | null | crackStack.asm | nixpal/kernel32-finder | f065b2348be47211f440b82c4af34571f95a5811 | [
"MIT"
] | null | null | null | ; Author: Tarek Ahmed
; All rights reserved
; Email: unix.geek2014@gmail.com
; NullFree
sub esp, 8
xor eax, eax
cdq
xchg edx, ecx
StackWalk :
mov ebx, [esp + ecx]
mov edx, ebx
shr ebx, 28
add ecx, 4
cmp ebx, 7
jne StackWalk
jmp short checking
checkAddress :
push ebp
mov ebp, esp
jmp rev1
reverse:
pop eax
jmp eax
rev1:
call reverse
add eax, 0x1e
push eax
xor edi, edi
push dword ptr FS : [edi]
mov dword ptr fs : [edi] , esp
mov eax, dword ptr ss : [ebp + 8]
xchg eax, esi
mov eax, dword ptr ds : [esi]
xor eax, eax
jmp short cleanseh
xor eax, eax
inc eax
mov esp, dword ptr fs : [edi]
mov esp, dword ptr ss : [esp]
cleanseh :
pop dword ptr fs : [edi]
add esp, 4
pop ebp
ret
checking:
mov [ebp-0xc], ecx
push edx
call checkAddress
test eax, eax
je valid
mov ecx, [ebp-0xc]
jmp short StackWalk
valid :
mov ecx, [ebp-0xc]
mov ax, 0xffff
inc eax
findMZ:
sub edx, eax
mov dx, ax
mov ax, [edx]
cmp ax, 0x5a4d
jne findMZ
xchg edx, ebx
mov edi, [ebx + 0x3c]
add edi, ebx
mov edi, [edi + 0x78]
add edi, ebx
mov edi, [edi + 0xc]
add edi, ebx
add edi, 4
xor eax, eax
push eax
push 0x6c6c642e
push 0x32334c45
mov esi, esp
checkKernel :
mov edx, ecx
mov cl, 8
cld
repe cmpsb
test ecx, ecx
je foundKernel
mov ecx, edx
jmp StackWalk
foundKernel :
| 12.926606 | 34 | 0.620298 |
d1154ddcecd8e7d76f3bdbe6b8fc5abfda96bc48 | 291 | asm | Assembly | 8088/cga/image_display/dbin.asm | reenigne/reenigne | c3eb8b31d7964e78bbe44908987d4be052a74488 | [
"Unlicense"
] | 92 | 2015-04-10T17:45:11.000Z | 2022-03-30T17:58:51.000Z | 8088/cga/image_display/dbin.asm | MS-DOS-stuff/reenigne | 0a113990aef398550c6f14d1c7a33af1cb091887 | [
"Unlicense"
] | 2 | 2017-11-05T07:21:35.000Z | 2018-11-04T23:36:13.000Z | 8088/cga/image_display/dbin.asm | MS-DOS-stuff/reenigne | 0a113990aef398550c6f14d1c7a33af1cb091887 | [
"Unlicense"
] | 18 | 2015-04-11T20:32:44.000Z | 2021-11-06T05:19:57.000Z | %include "../../defaults_bin.asm"
; Set graphics mode
mov ax,6
int 0x10
mov dx,0x3d8
mov al,0x1a
out dx,al
; Copy image data
mov ax,0xb800
mov es,ax
mov ax,cs
mov ds,ax
xor di,di
mov si,imageData
cld
mov cx,4000 + 0x1000
rep movsw
cli
hlt
imageData:
| 12.125 | 35 | 0.628866 |
e131039a6c118f6893dda064cb485d3d4e978e26 | 582 | asm | Assembly | programs/oeis/187/A187206.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/187/A187206.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/187/A187206.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A187206: a(n) = 6*(24*n - 1).
; 138,282,426,570,714,858,1002,1146,1290,1434,1578,1722,1866,2010,2154,2298,2442,2586,2730,2874,3018,3162,3306,3450,3594,3738,3882,4026,4170,4314,4458,4602,4746,4890,5034,5178,5322,5466,5610,5754,5898,6042,6186,6330,6474,6618,6762,6906,7050,7194,7338,7482,7626,7770,7914,8058,8202,8346,8490,8634,8778,8922,9066,9210,9354,9498,9642,9786,9930,10074,10218,10362,10506,10650,10794,10938,11082,11226,11370,11514,11658,11802,11946,12090,12234,12378,12522,12666,12810,12954,13098,13242,13386,13530,13674,13818,13962,14106,14250,14394
mul $0,144
add $0,138
| 97 | 526 | 0.778351 |
47075d855da9f6b036c7a9093cf70f7c34f8cf9c | 8,670 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0xca.log_21829_464.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0xca.log_21829_464.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0xca.log_21829_464.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r12
push %r13
push %r15
push %rax
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x1a2a0, %r13
nop
nop
nop
nop
nop
add $32047, %rbp
movl $0x61626364, (%r13)
sub $12482, %r15
lea addresses_UC_ht+0x158a0, %rsi
lea addresses_A_ht+0xe8a0, %rdi
nop
nop
nop
cmp %r12, %r12
mov $13, %rcx
rep movsl
nop
nop
sub %r12, %r12
lea addresses_A_ht+0x1a620, %rsi
lea addresses_A_ht+0x104e0, %rdi
clflush (%rdi)
nop
nop
nop
nop
xor %rax, %rax
mov $19, %rcx
rep movsb
nop
cmp %r15, %r15
lea addresses_normal_ht+0x4a0, %r15
nop
nop
nop
nop
nop
inc %rax
movb $0x61, (%r15)
nop
nop
nop
nop
nop
dec %rsi
lea addresses_normal_ht+0x8fa0, %rcx
xor $23659, %r12
mov $0x6162636465666768, %r15
movq %r15, %xmm2
movups %xmm2, (%rcx)
nop
nop
nop
nop
cmp %r13, %r13
lea addresses_WC_ht+0x239d, %rax
cmp $17013, %rsi
mov (%rax), %r13d
nop
cmp $62180, %r12
lea addresses_WT_ht+0x17e20, %rbp
nop
nop
nop
nop
nop
lfence
mov $0x6162636465666768, %rax
movq %rax, (%rbp)
nop
nop
nop
nop
xor %rax, %rax
lea addresses_WC_ht+0x10aa0, %rsi
lea addresses_D_ht+0x197a0, %rdi
nop
nop
nop
add $32009, %r15
mov $86, %rcx
rep movsb
nop
xor $7708, %rax
lea addresses_normal_ht+0xd3b0, %rdi
and %r12, %r12
mov (%rdi), %r15
nop
nop
nop
nop
xor $49845, %rsi
lea addresses_normal_ht+0x13ea0, %rsi
lea addresses_WT_ht+0x2af9, %rdi
sub %r12, %r12
mov $54, %rcx
rep movsl
nop
nop
inc %r13
lea addresses_UC_ht+0xaca0, %rbp
clflush (%rbp)
nop
add %r13, %r13
mov $0x6162636465666768, %rsi
movq %rsi, %xmm5
vmovups %ymm5, (%rbp)
nop
nop
nop
nop
cmp $1262, %rdi
lea addresses_UC_ht+0x1948e, %r12
nop
nop
nop
dec %rbp
mov $0x6162636465666768, %r15
movq %r15, %xmm3
vmovups %ymm3, (%r12)
nop
nop
nop
nop
nop
add %r12, %r12
lea addresses_A_ht+0xb348, %rsi
lea addresses_WC_ht+0xd70, %rdi
nop
cmp %r12, %r12
mov $23, %rcx
rep movsq
nop
nop
nop
nop
and %rsi, %rsi
lea addresses_WC_ht+0xf2a0, %rax
nop
nop
and %rbp, %rbp
movb (%rax), %r13b
nop
nop
nop
nop
nop
sub %rdi, %rdi
lea addresses_A_ht+0x176a0, %rbp
nop
nop
nop
nop
add %rdi, %rdi
movw $0x6162, (%rbp)
nop
nop
nop
nop
nop
cmp $57191, %r13
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %rax
pop %r15
pop %r13
pop %r12
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r15
push %r9
push %rax
push %rbx
push %rcx
push %rdx
// Store
lea addresses_WT+0xe0c8, %rdx
nop
and $50626, %r15
mov $0x5152535455565758, %rbx
movq %rbx, %xmm4
movups %xmm4, (%rdx)
nop
nop
nop
nop
nop
add %rbx, %rbx
// Store
lea addresses_D+0xcfa0, %r12
nop
nop
add %r9, %r9
mov $0x5152535455565758, %rax
movq %rax, %xmm0
movups %xmm0, (%r12)
nop
nop
nop
nop
nop
dec %r9
// Store
mov $0xae0, %rax
nop
nop
nop
nop
nop
sub %rbx, %rbx
movw $0x5152, (%rax)
and $50066, %r9
// Faulty Load
lea addresses_RW+0x122a0, %rdx
clflush (%rdx)
nop
nop
nop
sub $43402, %rcx
movups (%rdx), %xmm6
vpextrq $1, %xmm6, %r15
lea oracles, %r9
and $0xff, %r15
shlq $12, %r15
mov (%r9,%r15,1), %r15
pop %rdx
pop %rcx
pop %rbx
pop %rax
pop %r9
pop %r15
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'src': {'congruent': 0, 'AVXalign': False, 'same': False, 'size': 2, 'NT': False, 'type': 'addresses_RW'}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'congruent': 3, 'AVXalign': False, 'same': False, 'size': 16, 'NT': False, 'type': 'addresses_WT'}}
{'OP': 'STOR', 'dst': {'congruent': 8, 'AVXalign': False, 'same': False, 'size': 16, 'NT': False, 'type': 'addresses_D'}}
{'OP': 'STOR', 'dst': {'congruent': 4, 'AVXalign': True, 'same': False, 'size': 2, 'NT': False, 'type': 'addresses_P'}}
[Faulty Load]
{'src': {'congruent': 0, 'AVXalign': False, 'same': True, 'size': 16, 'NT': False, 'type': 'addresses_RW'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'congruent': 10, 'AVXalign': False, 'same': False, 'size': 4, 'NT': False, 'type': 'addresses_D_ht'}}
{'src': {'congruent': 8, 'same': False, 'type': 'addresses_UC_ht'}, 'OP': 'REPM', 'dst': {'congruent': 9, 'same': False, 'type': 'addresses_A_ht'}}
{'src': {'congruent': 5, 'same': False, 'type': 'addresses_A_ht'}, 'OP': 'REPM', 'dst': {'congruent': 4, 'same': False, 'type': 'addresses_A_ht'}}
{'OP': 'STOR', 'dst': {'congruent': 3, 'AVXalign': False, 'same': False, 'size': 1, 'NT': False, 'type': 'addresses_normal_ht'}}
{'OP': 'STOR', 'dst': {'congruent': 5, 'AVXalign': False, 'same': False, 'size': 16, 'NT': False, 'type': 'addresses_normal_ht'}}
{'src': {'congruent': 0, 'AVXalign': False, 'same': False, 'size': 4, 'NT': True, 'type': 'addresses_WC_ht'}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'congruent': 6, 'AVXalign': False, 'same': False, 'size': 8, 'NT': False, 'type': 'addresses_WT_ht'}}
{'src': {'congruent': 11, 'same': False, 'type': 'addresses_WC_ht'}, 'OP': 'REPM', 'dst': {'congruent': 7, 'same': False, 'type': 'addresses_D_ht'}}
{'src': {'congruent': 4, 'AVXalign': False, 'same': False, 'size': 8, 'NT': False, 'type': 'addresses_normal_ht'}, 'OP': 'LOAD'}
{'src': {'congruent': 10, 'same': False, 'type': 'addresses_normal_ht'}, 'OP': 'REPM', 'dst': {'congruent': 0, 'same': False, 'type': 'addresses_WT_ht'}}
{'OP': 'STOR', 'dst': {'congruent': 8, 'AVXalign': False, 'same': False, 'size': 32, 'NT': False, 'type': 'addresses_UC_ht'}}
{'OP': 'STOR', 'dst': {'congruent': 1, 'AVXalign': False, 'same': False, 'size': 32, 'NT': False, 'type': 'addresses_UC_ht'}}
{'src': {'congruent': 3, 'same': False, 'type': 'addresses_A_ht'}, 'OP': 'REPM', 'dst': {'congruent': 4, 'same': True, 'type': 'addresses_WC_ht'}}
{'src': {'congruent': 10, 'AVXalign': False, 'same': False, 'size': 1, 'NT': False, 'type': 'addresses_WC_ht'}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'congruent': 9, 'AVXalign': False, 'same': False, 'size': 2, 'NT': False, 'type': 'addresses_A_ht'}}
{'32': 21829}
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
*/
| 30.636042 | 2,999 | 0.656863 |
5dfbb8e41c12b7ec4667e142028adffe398315de | 416 | asm | Assembly | oeis/103/A103770.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/103/A103770.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/103/A103770.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A103770: A weighted tribonacci sequence, (1,3,9).
; Submitted by Jamie Morken(s1)
; 1,1,4,16,37,121,376,1072,3289,9889,29404,88672,265885,796537,2392240,7174816,21520369,64574977,193709428,581117680,1743420757,5230158649,15690480040,47071742800,141214610761,423644159521,1270933677004
add $0,1
mov $3,1
lpb $0
sub $0,1
div $1,2
add $1,$3
sub $1,$2
mul $1,6
add $2,$1
mul $3,3
lpe
mov $0,$2
div $0,6
| 23.111111 | 202 | 0.713942 |
b37e343002b73434ce768136fdc81d9c42379b07 | 16,655 | asm | Assembly | Appl/Games/Pyramid/pyramid.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 504 | 2018-11-18T03:35:53.000Z | 2022-03-29T01:02:51.000Z | Appl/Games/Pyramid/pyramid.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 96 | 2018-11-19T21:06:50.000Z | 2022-03-06T10:26:48.000Z | Appl/Games/Pyramid/pyramid.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 73 | 2018-11-19T20:46:53.000Z | 2022-03-29T00:59:26.000Z | COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
(c) Copyright GeoWorks 1991-1995. All Rights Reserved.
GEOWORKS CONFIDENTIAL
PROJECT: GEOS
MODULE: Pyramid
FILE: pyramid.asm
AUTHOR: Jon Witort, Jan 17, 1991
ROUTINES:
Name Description
---- -----------
MTD MSG_GEN_PROCESS_OPEN_APPLICATION
Sends the game object a
MSG_GAME_SETUP_STUFF which readies
everything for an exciting session of
pyramid!
INT PyramidCheckIfGameIsOpen
Will check if the varData
ATTR_PYRAMID_GAME_OPEN exists for
MyPlayingTable
INT PyramidMarkGameOpen Will add the varData ATTR_PYRAMID_GAME_OPEN
to MyPlayingTable
INT PyramidSetViewBackgroundColor
Set the background color of the view to
green if on a color display and white
if on a black and white display
MTD MSG_GEN_PROCESS_CLOSE_APPLICATION
Misc shutdown stuff.
INT PyramidUpdateOptions Get options from INI file and update UI.
INT PyramidIgnoreAcceptInput
Ignore or accept input.
REVISION HISTORY:
Name Date Description
---- ---- -----------
Jon 1/7/91 Initial version
jacob 6/15/95 initial Jedi version
stevey 8/8/95 added Undo feature (+comments :)
DESCRIPTION:
Some terminology:
_/\_
_/ \_
_/ \_
_/ \_
_/ \_
_/ \_
_/ Cards \_
_/ (aka Tableau Elements) \_
_/ = decks 4-31 \_
_/ (or A1-G7) \_
/ \
+------------------------------------------+
+--------+ +--------+ +--------+
| | | | | |
| | | TopOf- | | My- |
| MyHand | | MyHand | | Talon |
| | | | | |
|(deck 1)| |(deck 2)| |(deck 3)|
| | | | | |
+--------+ +--------+ +--------+
There's also a MyDiscard deck sitting around that you can't see.
$Id: pyramid.asm,v 1.1 97/04/04 15:15:07 newdeal Exp $
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
;------------------------------------------------------------------------------
; Common GEODE stuff
;------------------------------------------------------------------------------
_Application = 1
include stdapp.def
include initfile.def
include assert.def
;-----------------------------------------------------------------------------
; Product shme
;-----------------------------------------------------------------------------
_JEDI equ FALSE
;------------------------------------------------------------------------------
; Libraries used
;------------------------------------------------------------------------------
UseLib cards.def
;------------------------------------------------------------------------------
; Resources
;------------------------------------------------------------------------------
include myMacros.def
include sizes.def
include pyramid.def
include pyramid.rdef
include pyramidGame.asm
include pyramidDeck.asm
CommonCode segment resource
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
PyramidOpenApplication
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Sends the game object a MSG_GAME_SETUP_STUFF which readies
everything for an exciting session of pyramid!
CALLED BY: MSG_GEN_PROCESS_OPEN_APPLICATION
PASS: cx - AppAttachFlags
dx - Handle of AppLaunchBlock, or 0 if none.
This block contains the name of any document file
passed into the application on invocation. Block
is freed by caller.
bp - Handle of extra state block, or 0 if none.
This is the same block as returned from
MSG_GEN_PROCESS_CLOSE_APPLICATION, in some previous
MSG_META_DETACH. Block is freed by caller.
RETURN: nothing
DESTROYED: ax, cx, dx, bp
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
jon 11/90 initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
PyramidOpenApplication method dynamic PyramidProcessClass,
MSG_GEN_PROCESS_OPEN_APPLICATION
.enter
call PyramidSetViewBackgroundColor
call PyramidCheckIfGameIsOpen ; check for the Lazaurs case
jnc gameNotOpen ; the game isn't open
gameAlreadyOpen::
mov di, segment PyramidProcessClass
mov es, di
mov di, offset PyramidProcessClass
mov ax, MSG_GEN_PROCESS_OPEN_APPLICATION
call ObjCallSuperNoLock
jmp done
gameNotOpen:
test cx, mask AAF_RESTORING_FROM_STATE
jz startingUp
;
; We're restoring from state! Restore card bitmaps.
;
push cx, dx, bp ; save passed values
mov bx, handle MyPlayingTable
mov si, offset MyPlayingTable
mov ax, MSG_GAME_RESTORE_BITMAPS
mov di, mask MF_FIXUP_DS
call ObjMessage
pop cx, dx, bp ; restore passed values
mov di, segment PyramidProcessClass
mov es, di
mov di, offset PyramidProcessClass
mov ax, MSG_GEN_PROCESS_OPEN_APPLICATION
call ObjCallSuperNoLock
jmp markGameOpen
startingUp:
;
; Startup up for 1st time.
;
push cx, dx, bp ; save passed values
mov bx, handle MyPlayingTable
mov si, offset MyPlayingTable
mov ax, MSG_GAME_SETUP_STUFF
mov di, mask MF_FIXUP_DS
call ObjMessage
pop cx, dx, bp ; restore passed values
mov di, segment PyramidProcessClass
mov es, di
mov di, offset PyramidProcessClass
mov ax, MSG_GEN_PROCESS_OPEN_APPLICATION
call ObjCallSuperNoLock
;
; We're not restoring from state, so we need to create a full
; deck and start a new game here
;
CallObject MyHand, MSG_HAND_MAKE_FULL_HAND, MF_FIXUP_DS
CallObject MyPlayingTable, MSG_PYRAMID_NEW_GAME, MF_FORCE_QUEUE
;
; Update options from INI file.
;
call PyramidUpdateOptions
markGameOpen:
;
; Mark game as "open" for avoiding Lazarus bugs.
;
call PyramidMarkGameOpen
done:
.leave
ret
PyramidOpenApplication endm
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
PyramidCheckIfGameIsOpen
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Will check if the varData ATTR_PYRAMID_GAME_OPEN
exists for MyPlayingTable
CALLED BY: PyramidOpenApplication
PASS: nothing
RETURN: carry set if vardata found
carry clear if not found
DESTROYED: nothing
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
PW 7/ 7/93 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
PyramidCheckIfGameIsOpen proc near
uses ax,bx,cx,dx,si,di,bp
.enter
sub sp, size GetVarDataParams
mov bp, sp
mov ss:[bp].GVDP_dataType, \
ATTR_PYRAMID_GAME_OPEN
mov {word} ss:[bp].GVDP_bufferSize, 0
mov bx, handle MyPlayingTable
mov si, offset MyPlayingTable
mov ax, MSG_META_GET_VAR_DATA
mov dx, size GetVarDataParams
mov di, mask MF_CALL or mask MF_STACK
call ObjMessage
add sp, size GetVarDataParams
cmp ax, -1 ; check if not found
stc
jne varDataFound
clc
varDataFound:
.leave
ret
PyramidCheckIfGameIsOpen endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
PyramidMarkGameOpen
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Will add the varData ATTR_PYRAMID_GAME_OPEN to
MyPlayingTable
CALLED BY: PyramidOpenApplication
PASS: nothing
RETURN: nothing
DESTROYED: nothing
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
PW 7/ 7/93 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
PyramidMarkGameOpen proc near
uses ax,bx,cx,dx,si,di,bp
.enter
sub sp, size AddVarDataParams
mov bp, sp
mov ss:[bp].AVDP_dataType, \
ATTR_PYRAMID_GAME_OPEN
mov {word} ss:[bp].AVDP_dataSize, size byte
clrdw ss:[bp].AVDP_data
mov bx, handle MyPlayingTable
mov si, offset MyPlayingTable
mov ax, MSG_META_ADD_VAR_DATA
mov dx, size AddVarDataParams
mov di, mask MF_CALL or mask MF_STACK
call ObjMessage
add sp, size AddVarDataParams
.leave
ret
PyramidMarkGameOpen endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
PyramidSetViewBackgroundColor
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Set the background color of the view to green if on
a color display and white if on a black and white
display
CALLED BY: PyramidOpenApplication
PASS: nothing
RETURN: nothing
DESTROYED: nothing
PSEUDO CODE/STRATEGY:
- get the display mode
- if color, set view color to green
- of monochrome, set to white
REVISION HISTORY:
Name Date Description
---- ---- -----------
srs 6/ 7/93 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
PyramidSetViewBackgroundColor proc near
uses ax,bx,cx,dx,di,si,bp
.enter
;
; Use VUP_QUERY to field to avoid building GenApp object.
;
mov bx, segment GenFieldClass
mov si, offset GenFieldClass
mov ax, MSG_VIS_VUP_QUERY
mov cx, VUQ_DISPLAY_SCHEME ; get display scheme
mov di, mask MF_RECORD
call ObjMessage ; di = event handle
mov cx, di ; cx = event handle
mov bx, handle PyramidApp
mov si, offset PyramidApp
mov ax, MSG_GEN_CALL_PARENT
mov di,mask MF_CALL or mask MF_FIXUP_DS
call ObjMessage ; ah = display type, bp = ptsize
;
; Assume color display.
;
mov cx, ((CF_INDEX or (CMT_DITHER shl offset CMM_MAP_TYPE)) \
shl 8) or C_GREEN
and ah, mask DT_DISP_CLASS
cmp ah, DC_GRAY_1 shl offset DT_DISP_CLASS
jne setColor
mov cx, ((CF_INDEX or (CMT_DITHER shl offset CMM_MAP_TYPE)) \
shl 8) or C_WHITE
setColor:
mov bx, handle PyramidView
mov si, offset PyramidView
mov di, mask MF_FIXUP_DS
mov ax, MSG_GEN_VIEW_SET_COLOR
call ObjMessage
.leave
ret
PyramidSetViewBackgroundColor endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
PyramidCloseApplication
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Misc shutdown stuff.
CALLED BY: MSG_GEN_PROCESS_CLOSE_APPLICATION
PASS: es = segment of PyramidProcessClass
RETURN: nothing
DESTROYED: ax, cx, dx, bp
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
atw 1/ 3/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
PyramidCloseApplication method dynamic PyramidProcessClass,
MSG_GEN_PROCESS_CLOSE_APPLICATION
uses ax, cx, dx, bp, si
.enter
mov bx, handle MyPlayingTable
mov si, offset MyPlayingTable
mov di, mask MF_FIXUP_DS or mask MF_CALL
mov ax, MSG_GAME_SHUTDOWN
call ObjMessage
.leave
mov di, offset PyramidProcessClass
GOTO ObjCallSuperNoLock
PyramidCloseApplication endm
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
PyramidSaveOptions
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: This routine saves the current settings of the options menu
to the .ini file.
CALLED BY: MSG_META_SAVE_OPTIONS
PASS: nothing
RETURN: nothing
DESTROYED: ax, cx, cx, bp
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
atw 1/ 3/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
PyramidSaveOptions method PyramidProcessClass, MSG_META_SAVE_OPTIONS
;
; Save which back
;
mov ax, MSG_GAME_GET_WHICH_BACK
mov bx, handle MyPlayingTable
mov si, offset MyPlayingTable
mov di, mask MF_CALL
call ObjMessage ; cx <- starting level
mov bp, cx ; bp <- value
mov cx, cs
mov ds, cx
mov si, offset pyramidCategoryString
mov dx, offset pyramidWhichBackString
call InitFileWriteInteger
;
; Save the number of cards to flip each time
;
mov ax, MSG_GEN_ITEM_GROUP_GET_SELECTION
mov bx, handle SumToList
mov si, offset SumToList
mov di, mask MF_CALL
call ObjMessage ; ax <- starting level
mov_tr bp, ax ; bp <- value
mov cx, ds
mov si, offset pyramidCategoryString
mov dx, offset pyramidSumString
call InitFileWriteInteger
;
; Save fade mode.
;
mov ax, MSG_GEN_BOOLEAN_GROUP_GET_SELECTED_BOOLEANS
mov bx, handle GameOptions
mov si, offset GameOptions
mov di, mask MF_CALL
call ObjMessage ;LES_ACTUAL_EXCL set if on...
; and ax, 1 ;filter through fade bit ???? jfh
mov bp, ax ; get bools info to integer
mov cx, ds
mov si, offset pyramidCategoryString
mov dx, offset pyramidOptionsString
call InitFileWriteInteger
call InitFileCommit
ret
PyramidSaveOptions endm
pyramidCategoryString char "pyramid",0
pyramidWhichBackString char "whichBack",0
pyramidSumString char "sumTo",0
pyramidOptionsString char "options",0
pyramidStatusBarString char "statusBar",0
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
PyramidUpdateOptions
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Get options from INI file and update UI.
CALLED BY: PyramidOpenApplication
PASS: nothing
RETURN: nothing
DESTROYED: nothing
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
stevey 8/ 8/95 broke out of PyramidOpenApplication
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
PyramidUpdateOptions proc near
uses ax,bx,cx,dx,si,di,bp
.enter
;
; Get which card back we're using.
;
mov cx, cs
mov ds, cx ;DS:SI <- ptr to category string
mov si, offset pyramidCategoryString
mov dx, offset pyramidWhichBackString
call InitFileReadInteger
jc sumTo
mov_trash cx, ax ;cx <- which back
mov ax, MSG_GAME_SET_WHICH_BACK
mov bx, handle MyPlayingTable
mov si, offset MyPlayingTable
clr di
call ObjMessage
sumTo:
;
; Get the sum-to number.
;
mov cx, cs
mov ds, cx
mov si, offset pyramidCategoryString
mov dx, offset pyramidSumString
call InitFileReadInteger
jc hide
mov_tr cx, ax ;cx <- which back
clr dx ; not indeterminate
mov ax, MSG_GEN_ITEM_GROUP_SET_SINGLE_SELECTION
mov bx, handle SumToList
mov si, offset SumToList
clr di
call ObjMessage
hide:
;
; Get options & update UI.
;
mov cx, cs
mov ds, cx
mov si, offset pyramidCategoryString ; category
mov dx, offset pyramidOptionsString ; key
call InitFileReadInteger
jc statusBar
mov_tr cx, ax
clr dx
mov bx, handle GameOptions
mov si, offset GameOptions
mov ax, MSG_GEN_BOOLEAN_GROUP_SET_GROUP_STATE
clr di
call ObjMessage
statusBar:
;
; Set usable or not the "Status Bar"
;
clr ax ; assume FALSE
mov cx, cs
mov ds, cx
mov si, offset pyramidCategoryString ;category
mov dx, offset pyramidStatusBarString ;key
call InitFileReadBoolean ;look into the .ini file
tst ax
jz done ; if not present, do nothing
mov ax, MSG_GEN_SET_USABLE
mov bx, handle StatusBar
mov si, offset StatusBar
mov dl, VUM_DELAYED_VIA_UI_QUEUE
clr di
call ObjMessage
done:
.leave
ret
PyramidUpdateOptions endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
PyramidIgnoreAcceptInput
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Ignore or accept input.
CALLED BY: UTILITY
PASS: ax = MSG_GEN_APPLICATION_ACCEPT_INPUT,
MSG_GEN_APPLICATION_IGNORE_INPUT,
MSG_GEN_APPLICATION_MARK_BUSY, or
MSG_GEN_APPLICATION_MARK_NOT_BUSY
RETURN: nothing
DESTROYED: nothing
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
stevey 8/ 9/95 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
PyramidIgnoreAcceptInput proc near
uses ax,bx,cx,dx,si,di,bp
.enter
mov bx, handle PyramidApp
mov si, offset PyramidApp
mov di, mask MF_CALL
call ObjMessage
.leave
ret
PyramidIgnoreAcceptInput endp
CommonCode ends
| 24.970015 | 80 | 0.572681 |
51cc4ecdc90cd9def10e34370f6b734e5c1d0691 | 819 | asm | Assembly | libsrc/graphics/point.asm | andydansby/z88dk-mk2 | 51c15f1387293809c496f5eaf7b196f8a0e9b66b | [
"ClArtistic"
] | 1 | 2020-09-15T08:35:49.000Z | 2020-09-15T08:35:49.000Z | libsrc/graphics/point.asm | dex4er/deb-z88dk | 9ee4f23444fa6f6043462332a1bff7ae20a8504b | [
"ClArtistic"
] | null | null | null | libsrc/graphics/point.asm | dex4er/deb-z88dk | 9ee4f23444fa6f6043462332a1bff7ae20a8504b | [
"ClArtistic"
] | null | null | null | ;
; Z88 Graphics Functions - Small C+ stubs
;
; Written around the Interlogic Standard Library
;
; Stubs Written by D Morris - 30/9/98
;
;
; $Id: point.asm,v 1.4 2007/08/17 13:52:33 stefano Exp $
;
;Usage: point(struct *pixel)
;Result is true/false
XLIB point
LIB pointxy
LIB swapgfxbk
LIB swapgfxbk1
.point
ld ix,0
add ix,sp
ld l,(ix+2)
ld h,(ix+4)
call swapgfxbk
call pointxy
push af
call swapgfxbk1
pop af
ld hl,1
ret nz ;pixel set
dec hl
ret
| 21 | 62 | 0.391941 |
36729484abdfbdaf22145acc8052c957394c1de3 | 3,022 | asm | Assembly | Transynther/x86/_processed/AVXALIGN/_st_/i9-9900K_12_0xca.log_1_1459.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/AVXALIGN/_st_/i9-9900K_12_0xca.log_1_1459.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/AVXALIGN/_st_/i9-9900K_12_0xca.log_1_1459.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r12
push %r15
push %r8
push %rcx
push %rdx
lea addresses_WT_ht+0x11a7d, %r12
nop
sub %r8, %r8
mov (%r12), %edx
nop
nop
and $20955, %r11
lea addresses_WC_ht+0x1407d, %r15
nop
and %rcx, %rcx
mov $0x6162636465666768, %rdx
movq %rdx, %xmm5
movups %xmm5, (%r15)
nop
nop
nop
xor %r15, %r15
lea addresses_WT_ht+0x907d, %rdx
cmp $24082, %r10
mov $0x6162636465666768, %r12
movq %r12, (%rdx)
nop
add %r11, %r11
pop %rdx
pop %rcx
pop %r8
pop %r15
pop %r12
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r12
push %rbp
push %rbx
push %rcx
push %rdi
push %rdx
push %rsi
// Load
lea addresses_normal+0x19a7d, %rbp
nop
dec %rbx
vmovups (%rbp), %ymm2
vextracti128 $1, %ymm2, %xmm2
vpextrq $1, %xmm2, %r11
nop
nop
sub $21245, %rsi
// Store
lea addresses_normal+0x311d, %rdx
nop
nop
nop
xor %r12, %r12
mov $0x5152535455565758, %rbx
movq %rbx, %xmm5
movups %xmm5, (%rdx)
inc %rbp
// Store
lea addresses_A+0x647d, %rcx
nop
nop
nop
nop
xor $33565, %r12
movl $0x51525354, (%rcx)
nop
nop
nop
nop
xor %rcx, %rcx
// REPMOV
lea addresses_PSE+0x1e43d, %rsi
lea addresses_WT+0x464d, %rdi
nop
nop
nop
nop
nop
xor %r12, %r12
mov $12, %rcx
rep movsl
sub %rdi, %rdi
// Load
lea addresses_D+0x4e7d, %r12
nop
cmp $39178, %rdi
vmovups (%r12), %ymm2
vextracti128 $1, %ymm2, %xmm2
vpextrq $1, %xmm2, %rsi
nop
nop
nop
nop
nop
sub %r11, %r11
// Faulty Load
lea addresses_WT+0x7c7d, %rdi
nop
nop
nop
nop
add $36421, %rdx
movaps (%rdi), %xmm1
vpextrq $1, %xmm1, %rbp
lea oracles, %rdi
and $0xff, %rbp
shlq $12, %rbp
mov (%rdi,%rbp,1), %rbp
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r12
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'size': 1, 'NT': False, 'type': 'addresses_WT', 'same': False, 'AVXalign': False, 'congruent': 0}}
{'OP': 'LOAD', 'src': {'size': 32, 'NT': False, 'type': 'addresses_normal', 'same': False, 'AVXalign': False, 'congruent': 9}}
{'OP': 'STOR', 'dst': {'size': 16, 'NT': False, 'type': 'addresses_normal', 'same': False, 'AVXalign': False, 'congruent': 4}}
{'OP': 'STOR', 'dst': {'size': 4, 'NT': False, 'type': 'addresses_A', 'same': False, 'AVXalign': False, 'congruent': 11}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_PSE', 'congruent': 6}, 'dst': {'same': False, 'type': 'addresses_WT', 'congruent': 3}}
{'OP': 'LOAD', 'src': {'size': 32, 'NT': False, 'type': 'addresses_D', 'same': False, 'AVXalign': False, 'congruent': 9}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_WT', 'same': True, 'AVXalign': True, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'size': 4, 'NT': False, 'type': 'addresses_WT_ht', 'same': True, 'AVXalign': False, 'congruent': 7}}
{'OP': 'STOR', 'dst': {'size': 16, 'NT': False, 'type': 'addresses_WC_ht', 'same': False, 'AVXalign': False, 'congruent': 9}}
{'OP': 'STOR', 'dst': {'size': 8, 'NT': False, 'type': 'addresses_WT_ht', 'same': True, 'AVXalign': False, 'congruent': 8}}
{'33': 1}
33
*/
| 19.248408 | 143 | 0.645268 |
85b56dfbdc594b1056a45d6b334065c687423ed2 | 844 | asm | Assembly | oeis/166/A166637.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/166/A166637.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/166/A166637.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A166637: Totally multiplicative sequence with a(p) = 7*(p-1) for prime p.
; Submitted by Simon Strandgaard
; 1,7,14,49,28,98,42,343,196,196,70,686,84,294,392,2401,112,1372,126,1372,588,490,154,4802,784,588,2744,2058,196,2744,210,16807,980,784,1176,9604,252,882,1176,9604,280,4116,294,3430,5488,1078,322,33614,1764,5488,1568,4116,364,19208,1960,14406,1764,1372,406,19208,420,1470,8232,117649,2352,6860,462,5488,2156,8232,490,67228,504,1764,10976,6174,2940,8232,546,67228,38416,1960,574,28812,3136,2058,2744,24010,616,38416,3528,7546,2940,2254,3528,235298,672,12348,13720,38416
add $0,1
mov $1,1
mov $2,2
mov $4,1
lpb $0
mul $1,$4
mov $3,$0
lpb $3
mov $4,$0
mod $4,$2
add $2,1
cmp $4,0
cmp $4,0
sub $3,$4
lpe
div $0,$2
mov $4,$2
mov $5,$2
lpb $5
add $4,6
sub $5,1
lpe
sub $4,7
lpe
gcd $0,$1
| 28.133333 | 468 | 0.668246 |
b52aab913486279df7112738d0632f709a5593ec | 916 | asm | Assembly | 5/boot_sect_print_hex.asm | luckyagarwal/os_ | f96886f4b9fce02bc46db879825b3909cf1004e5 | [
"MIT"
] | null | null | null | 5/boot_sect_print_hex.asm | luckyagarwal/os_ | f96886f4b9fce02bc46db879825b3909cf1004e5 | [
"MIT"
] | null | null | null | 5/boot_sect_print_hex.asm | luckyagarwal/os_ | f96886f4b9fce02bc46db879825b3909cf1004e5 | [
"MIT"
] | null | null | null | print_hex:
pusha
mov cx,0
hex_loop:
cmp cx, 4
je end
mov ax,dx
and ax,0x000f;to mask the first 3 bit of 0x1234->to 0x0004 ,here are aim is to get the each bit from the given hex decimal!
add al,0x30;here,we are convereting the hex decimal to corresponding ascii value.eg. 0x0004 is now converted into '4'
cmp al,0x39;here if value in ax>9 ,since in hexa decimal we have digits 0-9 and alphabets a,b,c,d,f. so here we are adding 7 more to get the number into alphabet.
jle step2
add al,7
step2:
mov bx,hex_string+5;length of the string is 6+base address
sub bx,cx;initial cx=0 ,to get the exact index of the place where we want to replace '0' with the corresponding digit in the value of dx.eg ,w ewant to replace 0 at index 5 s0 we subtract bx(=base address+5) -(cx=0)
mov [bx],al
ror dx,4
add cx,1
jmp hex_loop
end:
mov bx,hex_string
call print
popa
ret
hex_string:
db '0x0000',0
| 27.757576 | 216 | 0.725983 |
dd9a9daefba7c9047b5c2bcc156c53395a226d71 | 601 | asm | Assembly | programs/oeis/184/A184531.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/184/A184531.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/184/A184531.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A184531: Upper s-Wythoff sequence, where s=5n-4. Complement of A184530.
; 2,9,15,21,27,33,39,46,52,58,64,70,77,83,89,95,101,108,114,120,126,132,139,145,151,157,163,170,176,182,188,194,201,207,213,219,225,231,238,244,250,256,262,269,275,281,287,293,300,306,312,318,324,331,337
mov $1,$0
mul $0,2
mov $2,$1
mov $7,$1
lpb $2
mul $1,2
add $2,5
add $4,$1
mov $6,$1
lpb $4
mov $4,0
mov $5,$2
lpe
mov $2,1
mov $3,6
trn $6,4
lpb $5
trn $5,$3
add $6,2
lpe
lpb $6
add $0,1
sub $6,$3
trn $6,6
lpe
sub $2,1
lpe
lpb $7
add $0,4
sub $7,1
lpe
add $0,2
| 16.694444 | 203 | 0.579035 |
d572d7977d2cf90c8c87d1990ee6dcfd938c2147 | 1,007 | asm | Assembly | introcore/agents/windows/agents/hcall32.asm | hugmyndakassi/hvmi | fa49a34ba32b327c462224db1cf58d96a076a224 | [
"Apache-2.0"
] | 677 | 2020-07-30T13:59:36.000Z | 2022-03-24T11:02:00.000Z | introcore/agents/windows/agents/hcall32.asm | hugmyndakassi/hvmi | fa49a34ba32b327c462224db1cf58d96a076a224 | [
"Apache-2.0"
] | 38 | 2020-08-11T13:59:36.000Z | 2022-02-17T15:03:48.000Z | introcore/agents/windows/agents/hcall32.asm | fengjixuchui/hvmi | 72488e8432d26547876a052d24ea44c3e18279a7 | [
"Apache-2.0"
] | 55 | 2020-07-30T14:11:03.000Z | 2022-03-09T05:40:44.000Z | ;-----------------------------------------------------------------------------
[bits 32]
; Global symbols
global _start
;-----------------------------------------------------------------------------
section .code
;================================================================================================================================
_start: push ebp
mov ebp, esp
push ecx
push edx
push ebx
push esi
push edi
mov eax, [ebp + 8]
mov ecx, [ebp + 12]
mov edx, [ebp + 16]
mov ebx, [ebp + 20]
mov esi, [ebp + 24]
mov edi, [ebp + 28]
vmcall
mov eax, edx
pop edi
pop esi
pop ebx
pop edx
pop ecx
pop ebp
retn 24 | 26.5 | 129 | 0.219464 |
48ecdd61423418e522e55cce969e1ce74487a9ef | 1,964 | asm | Assembly | Working Disassembly/Levels/HCZ/Misc Object Data/Map - Water Rush.asm | TeamASM-Blur/Sonic-3-Blue-Balls-Edition | 7e8a2c5df02271615ff4cae529521e6b1560d6b1 | [
"Apache-2.0"
] | 5 | 2021-07-09T08:17:56.000Z | 2022-02-27T19:57:47.000Z | Working Disassembly/Levels/HCZ/Misc Object Data/Map - Water Rush.asm | TeamASM-Blur/Sonic-3-Blue-Balls-Edition | 7e8a2c5df02271615ff4cae529521e6b1560d6b1 | [
"Apache-2.0"
] | null | null | null | Working Disassembly/Levels/HCZ/Misc Object Data/Map - Water Rush.asm | TeamASM-Blur/Sonic-3-Blue-Balls-Edition | 7e8a2c5df02271615ff4cae529521e6b1560d6b1 | [
"Apache-2.0"
] | null | null | null | Map_22E60C_: dc.w Frame_22E684-Map_22E60C_
dc.w Frame_22E6F8-Map_22E60C_
dc.w Frame_22E614-Map_22E60C_
dc.w Frame_22E646-Map_22E60C_
Frame_22E614: dc.w 8
dc.b $E0, 7, 0,$20,$FF,$E0
dc.b $E0, $F, 0,$18,$FF,$F0
dc.b $E0, $F, 0,$18, 0,$10
dc.b $E0, $F, 0,$18, 0,$30
dc.b 0, $F, 0,$30,$FF,$E0
dc.b 0, $F, 0,$30, 0, 0
dc.b 0, $F, 0,$30, 0,$20
dc.b 0, 7, 0,$30, 0,$40
Frame_22E646: dc.w $A
dc.b $E0, 7, 0,$20,$FF,$E0
dc.b $E0, $F, 0,$18,$FF,$F0
dc.b $E0, $F, 0,$18, 0,$10
dc.b $E0, $F, 0,$18, 0,$30
dc.b 0, $F, 0, 0,$FF,$C0
dc.b 0, 7, 0,$48,$FF,$E0
dc.b 0, 7, 0,$38,$FF,$F0
dc.b 0, $F, 0,$30, 0, 0
dc.b 0, $F, 0,$30, 0,$20
dc.b 0, 7, 0,$30, 0,$40
Frame_22E684: dc.w $13
dc.b $E0, $F, 0, 0,$FF,$C0
dc.b $E0, 7, 0,$10,$FF,$E0
dc.b $E0, $F, 0,$18,$FF,$F0
dc.b $E0, $F, 0,$18, 0,$10
dc.b $E0, $F, 0,$18, 0,$30
dc.b $E0, $F, 0,$18, 0,$50
dc.b $E0, 7, 0,$18, 0,$70
dc.b 0, $F, 0, 0,$FF,$D0
dc.b 0, 7, 0,$28,$FF,$F0
dc.b 0, $F, 0,$30, 0, 0
dc.b 0, $F, 0,$30, 0,$20
dc.b 0, $F, 0,$30, 0,$40
dc.b 0, $F, 0,$30, 0,$60
dc.b $20, $F, 0, 0,$FF,$E0
dc.b $20, 7, 0,$28, 0, 0
dc.b $20, $F, 0,$30, 0,$10
dc.b $20, $F, 0,$30, 0,$30
dc.b $20, $F, 0,$30, 0,$50
dc.b $20, 7, 0,$30, 0,$70
Frame_22E6F8: dc.w $13
dc.b $E0, $F, 0, 0,$FF,$D0
dc.b $E0, 7, 0,$40,$FF,$F0
dc.b $E0, 7, 0,$20, 0, 0
dc.b $E0, $F, 0,$18, 0,$10
dc.b $E0, $F, 0,$18, 0,$30
dc.b $E0, $F, 0,$18, 0,$50
dc.b $E0, 7, 0,$18, 0,$70
dc.b 0, $F, 0, 0,$FF,$E0
dc.b 0, 7, 0,$48, 0, 0
dc.b 0, 7, 0,$38, 0,$10
dc.b 0, $F, 0,$30, 0,$20
dc.b 0, $F, 0,$30, 0,$40
dc.b 0, $F, 0,$30, 0,$60
dc.b $20, $F, 0, 0,$FF,$F0
dc.b $20, 7, 0,$48, 0,$10
dc.b $20, 7, 0,$38, 0,$20
dc.b $20, $F, 0,$30, 0,$30
dc.b $20, $F, 0,$30, 0,$50
dc.b $20, 7, 0,$30, 0,$70
| 30.215385 | 42 | 0.425662 |
c095b044342dbb8dc431d3cffd0f4030ef81d807 | 163 | asm | Assembly | libsrc/_DEVELOPMENT/adt/p_stack/c/sccz80/p_stack_init.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/adt/p_stack/c/sccz80/p_stack_init.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/adt/p_stack/c/sccz80/p_stack_init.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null |
; void p_stack_init(void *p)
SECTION code_adt_p_stack
PUBLIC p_stack_init
defc p_stack_init = asm_p_stack_init
INCLUDE "adt/p_stack/z80/asm_p_stack_init.asm"
| 14.818182 | 46 | 0.815951 |
e0a4f2226ff09ca9f063142cea1bea33ae3aef54 | 7,937 | asm | Assembly | Transynther/x86/_processed/AVXALIGN/_st_zr_sm_/i3-7100_9_0x84_notsx.log_21829_2908.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/AVXALIGN/_st_zr_sm_/i3-7100_9_0x84_notsx.log_21829_2908.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/AVXALIGN/_st_zr_sm_/i3-7100_9_0x84_notsx.log_21829_2908.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r12
push %r14
push %r15
push %r9
push %rax
push %rcx
push %rdi
push %rsi
lea addresses_UC_ht+0xe870, %r12
nop
nop
cmp %r14, %r14
movb (%r12), %r15b
nop
nop
nop
nop
sub %rdi, %rdi
lea addresses_A_ht+0xd30, %r9
nop
nop
cmp $6097, %r14
movw $0x6162, (%r9)
nop
add %r12, %r12
lea addresses_A_ht+0x42ac, %r12
nop
nop
nop
and $59263, %r15
movups (%r12), %xmm3
vpextrq $0, %xmm3, %r14
nop
nop
nop
nop
sub $5027, %rdi
lea addresses_UC_ht+0x188d8, %r14
nop
nop
nop
nop
add %rax, %rax
movb (%r14), %r9b
sub %rdi, %rdi
lea addresses_UC_ht+0x11067, %r9
nop
nop
nop
xor %r12, %r12
mov $0x6162636465666768, %rdi
movq %rdi, (%r9)
nop
nop
nop
cmp %r9, %r9
lea addresses_WT_ht+0x9a70, %rsi
lea addresses_D_ht+0x13f5c, %rdi
nop
nop
add $43275, %r9
mov $75, %rcx
rep movsl
nop
nop
nop
xor $40980, %r15
lea addresses_A_ht+0x15670, %r9
nop
nop
nop
cmp $8388, %r14
movb (%r9), %r12b
nop
nop
nop
nop
dec %r14
lea addresses_D_ht+0x17c70, %rsi
lea addresses_UC_ht+0x10670, %rdi
nop
nop
nop
nop
nop
xor $56747, %r12
mov $70, %rcx
rep movsl
nop
nop
cmp $42809, %r14
lea addresses_normal_ht+0x39f0, %rdi
add $27124, %r9
movb $0x61, (%rdi)
nop
xor %rdi, %rdi
lea addresses_UC_ht+0x15670, %r12
nop
nop
nop
add %rcx, %rcx
mov $0x6162636465666768, %r14
movq %r14, %xmm2
movups %xmm2, (%r12)
inc %r9
lea addresses_normal_ht+0xae70, %rsi
lea addresses_A_ht+0xbfb, %rdi
nop
nop
nop
nop
sub %r14, %r14
mov $12, %rcx
rep movsq
nop
nop
nop
nop
nop
cmp $10824, %rax
pop %rsi
pop %rdi
pop %rcx
pop %rax
pop %r9
pop %r15
pop %r14
pop %r12
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r12
push %r14
push %r8
push %rax
push %rcx
// Load
lea addresses_RW+0x10270, %r8
xor $56087, %r11
movups (%r8), %xmm2
vpextrq $1, %xmm2, %rax
nop
nop
nop
nop
and %r10, %r10
// Store
lea addresses_A+0x16e70, %r12
nop
nop
and $13795, %rcx
movb $0x51, (%r12)
cmp %r11, %r11
// Store
lea addresses_D+0xaa70, %rax
nop
nop
nop
nop
and $22332, %r10
mov $0x5152535455565758, %r12
movq %r12, %xmm4
vmovups %ymm4, (%rax)
nop
nop
nop
and $26613, %r12
// Store
lea addresses_UC+0x1ba70, %rax
add %r10, %r10
movw $0x5152, (%rax)
nop
nop
nop
nop
and %rcx, %rcx
// Store
mov $0x7a20b20000000670, %r14
nop
nop
nop
nop
cmp $37810, %r8
mov $0x5152535455565758, %rcx
movq %rcx, (%r14)
nop
and $57136, %r14
// Faulty Load
mov $0x7a20b20000000670, %rax
nop
nop
nop
add %r8, %r8
mov (%rax), %r11w
lea oracles, %r12
and $0xff, %r11
shlq $12, %r11
mov (%r12,%r11,1), %r11
pop %rcx
pop %rax
pop %r8
pop %r14
pop %r12
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_NC', 'same': False, 'size': 1, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_RW', 'same': False, 'size': 16, 'congruent': 10, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_A', 'same': False, 'size': 1, 'congruent': 10, 'NT': True, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_D', 'same': False, 'size': 32, 'congruent': 10, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_UC', 'same': False, 'size': 2, 'congruent': 9, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_NC', 'same': True, 'size': 8, 'congruent': 0, 'NT': False, 'AVXalign': True}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'type': 'addresses_NC', 'same': True, 'size': 2, 'congruent': 0, 'NT': False, 'AVXalign': True}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'type': 'addresses_UC_ht', 'same': False, 'size': 1, 'congruent': 8, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_A_ht', 'same': False, 'size': 2, 'congruent': 6, 'NT': False, 'AVXalign': True}, 'OP': 'STOR'}
{'src': {'type': 'addresses_A_ht', 'same': False, 'size': 16, 'congruent': 2, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_UC_ht', 'same': False, 'size': 1, 'congruent': 3, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_UC_ht', 'same': False, 'size': 8, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_WT_ht', 'congruent': 9, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 2, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_A_ht', 'same': False, 'size': 1, 'congruent': 11, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_D_ht', 'congruent': 9, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 11, 'same': False}, 'OP': 'REPM'}
{'dst': {'type': 'addresses_normal_ht', 'same': False, 'size': 1, 'congruent': 7, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_UC_ht', 'same': False, 'size': 16, 'congruent': 9, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_normal_ht', 'congruent': 11, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 0, 'same': False}, 'OP': 'REPM'}
{'00': 394, '58': 21435}
00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58
*/
| 32.395918 | 2,999 | 0.65201 |
1d573df83037c4bb1157a7e7fa0215d834261849 | 4,646 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca_notsx.log_21829_905.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca_notsx.log_21829_905.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca_notsx.log_21829_905.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r12
push %r13
push %rbp
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_WC_ht+0x18f7c, %rsi
lea addresses_WC_ht+0x1cec4, %rdi
nop
nop
nop
nop
cmp $3087, %r13
mov $89, %rcx
rep movsl
xor $1678, %rcx
lea addresses_WC_ht+0x1bb44, %r10
nop
nop
nop
xor %rbp, %rbp
mov (%r10), %r12w
nop
sub %rbp, %rbp
lea addresses_D_ht+0x8f44, %rsi
lea addresses_A_ht+0x10eea, %rdi
clflush (%rsi)
nop
nop
nop
nop
sub %rdx, %rdx
mov $31, %rcx
rep movsw
add %rbp, %rbp
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbp
pop %r13
pop %r12
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r12
push %r14
push %r8
push %rbx
push %rdi
// Faulty Load
lea addresses_A+0x18344, %rdi
nop
nop
sub %r12, %r12
mov (%rdi), %r8d
lea oracles, %r14
and $0xff, %r8
shlq $12, %r8
mov (%r14,%r8,1), %r8
pop %rdi
pop %rbx
pop %r8
pop %r14
pop %r12
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_A', 'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 0}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'type': 'addresses_A', 'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'same': False, 'congruent': 3, 'type': 'addresses_WC_ht'}, 'dst': {'same': False, 'congruent': 7, 'type': 'addresses_WC_ht'}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_WC_ht', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 11}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 10, 'type': 'addresses_D_ht'}, 'dst': {'same': False, 'congruent': 0, 'type': 'addresses_A_ht'}}
{'35': 21829}
35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35
*/
| 51.622222 | 2,999 | 0.661644 |
4d4118adabf0113d25db8431912fe9fb59243d75 | 54,884 | asm | Assembly | Gathered CTF writeups/hitcon_quals_2018/eop/eop_disas.asm | mihaid-b/CyberSakura | f60e6b6bfd6898c69b84424b080090ae98f8076c | [
"MIT"
] | 1 | 2022-03-27T06:00:41.000Z | 2022-03-27T06:00:41.000Z | Gathered CTF writeups/hitcon_quals_2018/eop/eop_disas.asm | mihaid-b/CyberSakura | f60e6b6bfd6898c69b84424b080090ae98f8076c | [
"MIT"
] | null | null | null | Gathered CTF writeups/hitcon_quals_2018/eop/eop_disas.asm | mihaid-b/CyberSakura | f60e6b6bfd6898c69b84424b080090ae98f8076c | [
"MIT"
] | 1 | 2022-03-27T06:01:42.000Z | 2022-03-27T06:01:42.000Z | ; ---------------- Node 31 at 0x555555559ADC. Next: 3A ----------------
mov [rbp+iter_14], 0
cmp [rbp+iter_14], 0Fh
jg short END_XOR_555555559B66
mov eax, [rbp+iter_14]
movsxd rdx, eax
lea rax, pwd_1_5555557671A0
movzx ecx, byte ptr [rdx+rax] ; ecx = pwd[0]
mov eax, [rbp+iter_14]
movsxd rdx, eax
lea rax, enc_blk_1_5555557671B0
movzx eax, byte ptr [rdx+rax]
xor ecx, eax ; pwd[0:16] ^= enc_blk_1/2[0:16]
mov eax, [rbp+iter_14]
movsxd rdx, eax
lea rax, pwd_1_5555557671A0
mov [rdx+rax], cl
add [rbp+iter_14], 1
jmp short XOR_LOOP_555555559B26
; ---------------- Node 3A at 0x55555555AE98. Next: 3B ----------------
movzx eax, byte ptr cs:pwd_1_5555557671A0
movzx eax, al
movzx edx, byte ptr cs:pwd_1_5555557671A0+1
movzx edx, dl
shl edx, 8
or edx, eax
movzx eax, byte ptr cs:pwd_1_5555557671A0+2
movzx eax, al
shl eax, 10h
or edx, eax
movzx eax, byte ptr cs:pwd_1_5555557671A0+3
movzx eax, al
shl eax, 18h
or edx, eax ; edx = atoi(pwd_1[0:4])
mov rax, cs:tbl_A_555555767150
mov eax, [rax]
xor eax, edx
mov cs:tmp_A_5555557671C0, eax ; tmp_A = atoi(pwd_1[0:4]) ^ tbl_A[0]
; ---------------- Node 3B at 0x55555555A026. Next: 3 ----------------
movzx eax, byte ptr cs:pwd_1_5555557671A0+4
movzx eax, al
movzx edx, byte ptr cs:pwd_1_5555557671A0+5
movzx edx, dl
shl edx, 8
or edx, eax
movzx eax, byte ptr cs:pwd_1_5555557671A0+6
movzx eax, al
shl eax, 10h
or edx, eax
movzx eax, byte ptr cs:pwd_1_5555557671A0+7
movzx eax, al
shl eax, 18h
or edx, eax ; edx = atoi(pwd[4:8])
mov rax, cs:tbl_A_555555767150
mov eax, [rax+4]
xor eax, edx
mov cs:tmp_B_5555557671C4, eax ; tmp_B = edx = atoi(pwd[4:8]) ^ tbl_A[1]
; ---------------- Node 3 at 0x55555555AFE2. Next: 13 ----------------
movzx eax, byte ptr cs:pwd_2_5555557671A8
movzx eax, al
movzx edx, byte ptr cs:pwd_2_5555557671A8+1
movzx edx, dl
shl edx, 8
or edx, eax
movzx eax, byte ptr cs:pwd_2_5555557671A8+2
movzx eax, al
shl eax, 10h
or edx, eax
movzx eax, byte ptr cs:pwd_2_5555557671A8+3
movzx eax, al
shl eax, 18h
or edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+8]
xor eax, edx
mov cs:tmp_C_5555557671C8, eax ; tmp_C = atoi(pwd_2[0:4]) ^ tbl_A[2]
; ---------------- Node 13 at 0x55555555BC30. Next: 0 ----------------
movzx eax, byte ptr cs:pwd_2_5555557671A8+4
movzx eax, al
movzx edx, byte ptr cs:pwd_2_5555557671A8+5
movzx edx, dl
shl edx, 8
or edx, eax
movzx eax, byte ptr cs:pwd_2_5555557671A8+6
movzx eax, al
shl eax, 10h
or edx, eax
movzx eax, byte ptr cs:pwd_2_5555557671A8+7
movzx eax, al
shl eax, 18h
or edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+0Ch]
xor eax, edx
mov cs:tmp_D_5555557671CC, eax ; tmp_D = atoi(pwd_2[4:8]) ^ tbl_A[3]
; ---------------- Node 0 at 0x55555555A1E6. Next: C ----------------
; ---------------- Node C at 0x55555555BB34. Next: 49 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
movzx edx, dl
mov edx, edx
add rdx, 40h ; sub_A = tbl_A + 0x40
mov edx, [rax+rdx*4] ; edx = sub_A[tmp_A & 0xFF] = sub_A[BYTE_1(tmp_A)]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_A_5555557671C0
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h ; sub_B = tbl_A + 0x140
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax ; ecx = sub_A[tmp_A & 0xFF] ^ sub_B[(tmp_A >> 8) & 0xFF])
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h ; sub_C = tbl_A + 0x240
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 18h
mov edx, edx
add rdx, 340h ; sub_D = tbl_A + 0x340
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax ; tmp_E = sub_A[B1(tmp_A)] ^ sub_B[B2(tmp_A)] ^ sub_C[B3(tmp_A)] ^ sub_D[B4(tmp_A)]
; ---------------- Node 49 at 0x55555555D282. Next: 21 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4] ; a = sub_A[B4(tmp_B)]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_B_5555557671C4
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4] ; b = sub_B[B1(tmp_B)]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4] ; c = sub_C[B2(tmp_B)]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4] ; d = sub_D[B3(tmp_B)]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax ; tmp_F = a ^ b ^ c ^ d
; ---------------- Node 21 at 0x55555555A7D2. Next: 19 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+20h]
add edx, eax ; edx = tmp_E + tmp_F + tbl_A[8]
mov eax, cs:tmp_C_5555557671C8
xor eax, edx
mov cs:tmp_C_5555557671C8, eax ; tmp_C ^= tmp_E + tmp_F + tbl_A[8]
; ---------------- Node 19 at 0x55555555DD88. Next: 1F ----------------
mov eax, cs:tmp_C_5555557671C8
ror eax, 1 ; tmp_C = ror(tmp_C, 1)
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 1F at 0x55555555E1EA. Next: 39 ----------------
mov eax, cs:tmp_D_5555557671CC
rol eax, 1 ; tmp_D = rol(tmp_D, 1)
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 39 at 0x55555555C51E. Next: 47 ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax] ; edx = tmp_F * 2 (32 bit)
mov eax, cs:tmp_E_5555557671D0
add edx, eax ; edx = 2*tmp_F + tmp_E (32 bit)
mov rax, cs:tbl_A_555555767150
mov eax, [rax+24h]
add edx, eax
mov eax, cs:tmp_D_5555557671CC
xor eax, edx
mov cs:tmp_D_5555557671CC, eax ; tmp_D ^= 2*tmp_F + tmp_E + tbl_A[9]
; ---------------- Node 47 at 0x55555555A0EA. Next: 3D ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_C_5555557671C8
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 3D at 0x55555555CCC8. Next: A ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_D_5555557671CC
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node A at 0x55555555DE9A. Next: 71 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+28h]
add edx, eax
mov eax, cs:tmp_A_5555557671C0
xor eax, edx ; tmp_A ^= tmp_E + tmp_F + tbl_A[9]
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 71 at 0x55555555DF3C. Next: 69 ----------------
mov eax, cs:tmp_A_5555557671C0
ror eax, 1 ; ror(tmp_A, 1)
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 69 at 0x555555559F14. Next: 63 ----------------
mov eax, cs:tmp_B_5555557671C4
rol eax, 1 ; rol(tmp_B, 1)
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 63 at 0x55555555BD7C. Next: 76 ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+2Ch]
add edx, eax
mov eax, cs:tmp_B_5555557671C4
xor eax, edx
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 76 at 0x55555555D186. Next: 56 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_A_5555557671C0
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 56 at 0x55555555B1F2. Next: 53 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_B_5555557671C4
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 53 at 0x55555555E0C0. Next: 5B ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+30h]
add edx, eax
mov eax, cs:tmp_C_5555557671C8
xor eax, edx
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 5B at 0x55555555D056. Next: 1E ----------------
mov eax, cs:tmp_C_5555557671C8
ror eax, 1
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 1E at 0x55555555E162. Next: 20 ----------------
mov eax, cs:tmp_D_5555557671CC
rol eax, 1
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 20 at 0x55555555D6FE. Next: 14 ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+34h]
add edx, eax
mov eax, cs:tmp_D_5555557671CC
xor eax, edx
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 14 at 0x55555555E38C. Next: 2F ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_C_5555557671C8
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 2F at 0x55555555DC8C. Next: 42 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_D_5555557671CC
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 42 at 0x55555555ABB0. Next: 11 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+38h]
add edx, eax
mov eax, cs:tmp_A_5555557671C0
xor eax, edx
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 11 at 0x55555555CB44. Next: 5C ----------------
mov eax, cs:tmp_A_5555557671C0
ror eax, 1
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 5C at 0x55555555EA52. Next: 37 ----------------
mov eax, cs:tmp_B_5555557671C4
rol eax, 1
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 37 at 0x55555555A8FC. Next: 1A ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+3Ch]
add edx, eax
mov eax, cs:tmp_B_5555557671C4
xor eax, edx
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 1A at 0x555555559B9E. Next: 4C ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_A_5555557671C0
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 4C at 0x55555555A9A2. Next: 40 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_B_5555557671C4
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 40 at 0x55555555C75E. Next: 41 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+40h]
add edx, eax
mov eax, cs:tmp_C_5555557671C8
xor eax, edx
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 41 at 0x55555555E488. Next: 58 ----------------
mov eax, cs:tmp_C_5555557671C8
ror eax, 1
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 58 at 0x55555555BF1E. Next: 15 ----------------
mov eax, cs:tmp_D_5555557671CC
rol eax, 1
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 15 at 0x55555555A72C. Next: 7B ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+44h]
add edx, eax
mov eax, cs:tmp_D_5555557671CC
xor eax, edx
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 7B at 0x55555555DB16. Next: 2A ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_C_5555557671C8
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 2A at 0x55555555A5A6. Next: 4 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_D_5555557671CC
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 4 at 0x555555559C9A. Next: 78 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+48h]
add edx, eax
mov eax, cs:tmp_A_5555557671C0
xor eax, edx
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 78 at 0x55555555E598. Next: 7A ----------------
mov eax, cs:tmp_A_5555557671C0
ror eax, 1
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 7A at 0x55555555B4E6. Next: 50 ----------------
mov eax, cs:tmp_B_5555557671C4
rol eax, 1
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 50 at 0x55555555D974. Next: 26 ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+4Ch]
add edx, eax
mov eax, cs:tmp_B_5555557671C4
xor eax, edx
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 26 at 0x55555555CBCC. Next: 8 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_A_5555557671C0
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 8 at 0x55555555B69E. Next: 17 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_B_5555557671C4
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 17 at 0x55555555ADF6. Next: 61 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+50h]
add edx, eax
mov eax, cs:tmp_C_5555557671C8
xor eax, edx
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 61 at 0x55555555C1C8. Next: D ----------------
mov eax, cs:tmp_C_5555557671C8
ror eax, 1
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node D at 0x55555555BAAC. Next: 48 ----------------
mov eax, cs:tmp_D_5555557671CC
rol eax, 1
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 48 at 0x55555555B14C. Next: 2D ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+54h]
add edx, eax
mov eax, cs:tmp_D_5555557671CC
xor eax, edx
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 2D at 0x55555555B2EE. Next: F ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_C_5555557671C8
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node F at 0x55555555C398. Next: 6E ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_D_5555557671CC
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 6E at 0x55555555C2F6. Next: 54 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+58h]
add edx, eax
mov eax, cs:tmp_A_5555557671C0
xor eax, edx
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 54 at 0x55555555AB28. Next: 24 ----------------
mov eax, cs:tmp_A_5555557671C0
ror eax, 1
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 24 at 0x55555555D846. Next: 1B ----------------
mov eax, cs:tmp_B_5555557671C4
rol eax, 1
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 1B at 0x55555555A260. Next: 4E ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+5Ch]
add edx, eax
mov eax, cs:tmp_B_5555557671C4
xor eax, edx
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 4E at 0x55555555B79A. Next: 1 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_A_5555557671C0
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 1 at 0x55555555DFC4. Next: 23 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_B_5555557671C4
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 23 at 0x55555555D7A4. Next: 3F ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+60h]
add edx, eax
mov eax, cs:tmp_C_5555557671C8
xor eax, edx
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 3F at 0x55555555C02E. Next: 66 ----------------
mov eax, cs:tmp_C_5555557671C8
ror eax, 1
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 66 at 0x55555555E510. Next: 7 ----------------
mov eax, cs:tmp_D_5555557671CC
rol eax, 1
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 7 at 0x55555555C800. Next: 16 ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+64h]
add edx, eax
mov eax, cs:tmp_D_5555557671CC
xor eax, edx
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 16 at 0x55555555DA1A. Next: 3C ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_C_5555557671C8
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 3C at 0x55555555ACFA. Next: E ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_D_5555557671CC
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node E at 0x55555555E818. Next: 6C ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+68h]
add edx, eax
mov eax, cs:tmp_A_5555557671C0
xor eax, edx
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 6C at 0x55555555E304. Next: 38 ----------------
mov eax, cs:tmp_A_5555557671C0
ror eax, 1
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 38 at 0x55555555E942. Next: 64 ----------------
mov eax, cs:tmp_B_5555557671C4
rol eax, 1
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 64 at 0x55555555D8CE. Next: 35 ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+6Ch]
add edx, eax
mov eax, cs:tmp_B_5555557671C4
xor eax, edx
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 35 at 0x55555555CDC4. Next: 32 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_A_5555557671C0
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 32 at 0x55555555E71C. Next: 10 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_B_5555557671C4
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 10 at 0x55555555D550. Next: 5E ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+70h]
add edx, eax
mov eax, cs:tmp_C_5555557671C8
xor eax, edx
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 5E at 0x55555555BFA6. Next: 74 ----------------
mov eax, cs:tmp_C_5555557671C8
ror eax, 1
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 74 at 0x55555555C6D6. Next: 5D ----------------
mov eax, cs:tmp_D_5555557671CC
rol eax, 1
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 5D at 0x55555555D4AA. Next: 45 ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+74h]
add edx, eax
mov eax, cs:tmp_D_5555557671CC
xor eax, edx
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 45 at 0x55555555EBD6. Next: 25 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_C_5555557671C8
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 25 at 0x55555555B3EA. Next: 44 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_D_5555557671CC
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 44 at 0x55555555D408. Next: 43 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+78h]
add edx, eax
mov eax, cs:tmp_A_5555557671C0
xor eax, edx
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 43 at 0x55555555BA24. Next: 34 ----------------
mov eax, cs:tmp_A_5555557671C0
ror eax, 1
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 34 at 0x55555555C0B6. Next: 4A ----------------
mov eax, cs:tmp_B_5555557671C4
rol eax, 1
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 4A at 0x55555555C9A2. Next: 6F ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+7Ch]
add edx, eax
mov eax, cs:tmp_B_5555557671C4
xor eax, edx
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 6F at 0x55555555EADA. Next: 4D ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_A_5555557671C0
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 4D at 0x55555555CA48. Next: 28 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_B_5555557671C4
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 28 at 0x55555555C250. Next: 12 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+80h]
add edx, eax
mov eax, cs:tmp_C_5555557671C8
xor eax, edx
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 12 at 0x55555555A422. Next: 4B ----------------
mov eax, cs:tmp_C_5555557671C8
ror eax, 1
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 4B at 0x55555555C64E. Next: 65 ----------------
mov eax, cs:tmp_D_5555557671CC
rol eax, 1
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 65 at 0x55555555D0DE. Next: 6B ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+84h]
add edx, eax
mov eax, cs:tmp_D_5555557671CC
xor eax, edx
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 6B at 0x55555555981E. Next: 2E ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_C_5555557671C8
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 2E at 0x55555555BE22. Next: 30 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_D_5555557671CC
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 30 at 0x555555559A36. Next: 77 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+88h]
add edx, eax
mov eax, cs:tmp_A_5555557671C0
xor eax, edx
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 77 at 0x55555555B56E. Next: 62 ----------------
mov eax, cs:tmp_A_5555557671C0
ror eax, 1
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 62 at 0x55555555E9CA. Next: 59 ----------------
mov eax, cs:tmp_B_5555557671C4
rol eax, 1
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 59 at 0x55555555B5F6. Next: 2 ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+8Ch]
add edx, eax
mov eax, cs:tmp_B_5555557671C4
xor eax, edx
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 2 at 0x55555555E620. Next: 6D ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_A_5555557671C0
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_A_5555557671C0
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 6D at 0x55555555B928. Next: 73 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_B_5555557671C4
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_B_5555557671C4
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 73 at 0x555555559DE4. Next: 60 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+90h]
add edx, eax
mov eax, cs:tmp_C_5555557671C8
xor eax, edx
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 60 at 0x55555555A874. Next: 3E ----------------
mov eax, cs:tmp_C_5555557671C8
ror eax, 1
mov cs:tmp_C_5555557671C8, eax
; ---------------- Node 3E at 0x55555555AF5A. Next: 9 ----------------
mov eax, cs:tmp_D_5555557671CC
rol eax, 1
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 9 at 0x55555555AC52. Next: 70 ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+94h]
add edx, eax
mov eax, cs:tmp_D_5555557671CC
xor eax, edx
mov cs:tmp_D_5555557671CC, eax
; ---------------- Node 70 at 0x55555555A4AA. Next: 6A ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
movzx edx, dl
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_C_5555557671C8
shr ecx, 8
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_C_5555557671C8
shr edx, 18h
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_E_5555557671D0, eax
; ---------------- Node 6A at 0x55555555C8A6. Next: 75 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 18h
mov edx, edx
add rdx, 40h
mov edx, [rax+rdx*4]
mov rax, cs:tbl_A_555555767150
mov ecx, cs:tmp_D_5555557671CC
movzx ecx, cl
mov ecx, ecx
add rcx, 140h
mov eax, [rax+rcx*4]
mov ecx, edx
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 8
movzx edx, dl
mov edx, edx
add rdx, 240h
mov eax, [rax+rdx*4]
xor ecx, eax
mov rax, cs:tbl_A_555555767150
mov edx, cs:tmp_D_5555557671CC
shr edx, 10h
movzx edx, dl
mov edx, edx
add rdx, 340h
mov eax, [rax+rdx*4]
xor eax, ecx
mov cs:tmp_F_5555557671D4, eax
; ---------------- Node 75 at 0x55555555B0A6. Next: 27 ----------------
mov edx, cs:tmp_E_5555557671D0
mov eax, cs:tmp_F_5555557671D4
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+98h]
add edx, eax
mov eax, cs:tmp_A_5555557671C0
xor eax, edx
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 27 at 0x55555555BCF4. Next: 72 ----------------
mov eax, cs:tmp_A_5555557671C0
ror eax, 1
mov cs:tmp_A_5555557671C0, eax
; ---------------- Node 72 at 0x55555555E8BA. Next: 55 ----------------
mov eax, cs:tmp_B_5555557671C4
rol eax, 1
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 55 at 0x555555559D3C. Next: 67 ----------------
mov eax, cs:tmp_F_5555557671D4
lea edx, [rax+rax]
mov eax, cs:tmp_E_5555557671D0
add edx, eax
mov rax, cs:tbl_A_555555767150
mov eax, [rax+9Ch]
add edx, eax
mov eax, cs:tmp_B_5555557671C4
xor eax, edx
mov cs:tmp_B_5555557671C4, eax
; ---------------- Node 67 at 0x55555555DC12. Next: 36 ----------------
; ---------------- Node 36 at 0x55555555A306. Next: 2C ----------------
mov rax, cs:tbl_A_555555767150
mov edx, [rax+10h]
mov eax, cs:tmp_C_5555557671C8
xor eax, edx
mov cs:tmp_C_5555557671C8, eax ; tmp_C ^= tbl_A[4]
; ---------------- Node 2C at 0x55555555991A. Next: 68 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, [rax+14h]
mov eax, cs:tmp_D_5555557671CC
xor eax, edx
mov cs:tmp_D_5555557671CC, eax ; tmp_D ^= tbl_A[5]
; ---------------- Node 68 at 0x55555555E272. Next: 4F ----------------
mov rax, cs:tbl_A_555555767150
mov edx, [rax+18h]
mov eax, cs:tmp_A_5555557671C0
xor eax, edx
mov cs:tmp_A_5555557671C0, eax ; tmp_A ^= tbl_A[6]
; ---------------- Node 4F at 0x55555555B896. Next: 57 ----------------
mov rax, cs:tbl_A_555555767150
mov edx, [rax+1Ch]
mov eax, cs:tmp_B_5555557671C4
xor eax, edx
mov cs:tmp_B_5555557671C4, eax ; tmp_B ^= tbl_A[7]
; ---------------- Node 57 at 0x55555555D5F2. Next: 22 ----------------
mov eax, cs:tmp_C_5555557671C8
mov byte ptr cs:enc_blk_1_5555557671B0, al
; ---------------- Node 22 at 0x555555559F9C. Next: 52 ----------------
mov eax, cs:tmp_C_5555557671C8
shr eax, 8
mov byte ptr cs:enc_blk_1_5555557671B0+1, al
; ---------------- Node 52 at 0x55555555DE10. Next: 51 ----------------
mov eax, cs:tmp_C_5555557671C8
shr eax, 10h
mov byte ptr cs:enc_blk_1_5555557671B0+2, al
; ---------------- Node 51 at 0x55555555AA9E. Next: 2B ----------------
mov eax, cs:tmp_C_5555557671C8
shr eax, 18h
mov byte ptr cs:enc_blk_1_5555557671B0+3, al
; ---------------- Node 2B at 0x55555555CFD0. Next: 5A ----------------
mov eax, cs:tmp_D_5555557671CC
mov byte ptr cs:enc_blk_1_5555557671B0+4, al
; ---------------- Node 5A at 0x555555559E8A. Next: 79 ----------------
mov eax, cs:tmp_D_5555557671CC
shr eax, 8
mov byte ptr cs:enc_blk_1_5555557671B0+5, al
; ---------------- Node 79 at 0x55555555D37E. Next: 29 ----------------
mov eax, cs:tmp_D_5555557671CC
shr eax, 10h
mov byte ptr cs:enc_blk_1_5555557671B0+6, al
; ---------------- Node 29 at 0x55555555A6A2. Next: 5 ----------------
mov eax, cs:tmp_D_5555557671CC
shr eax, 18h
mov byte ptr cs:enc_blk_1_5555557671B0+7, al
; ---------------- Node 5 at 0x55555555D678. Next: 33 ----------------
mov eax, cs:tmp_A_5555557671C0
mov byte ptr cs:enc_blk_2_5555557671B8, al
; ---------------- Node 33 at 0x55555555C13E. Next: 6 ----------------
mov eax, cs:tmp_A_5555557671C0
shr eax, 8
mov byte ptr cs:enc_blk_2_5555557671B8+1, al
; ---------------- Node 6 at 0x55555555C494. Next: 5F ----------------
mov eax, cs:tmp_A_5555557671C0
shr eax, 10h
mov byte ptr cs:enc_blk_2_5555557671B8+2, al
; ---------------- Node 5F at 0x5555555599AC. Next: 46 ----------------
mov eax, cs:tmp_A_5555557671C0
shr eax, 18h
mov byte ptr cs:enc_blk_2_5555557671B8+3, al
; ---------------- Node 46 at 0x55555555CF4A. Next: 18 ----------------
mov eax, cs:tmp_B_5555557671C4
mov byte ptr cs:enc_blk_2_5555557671B8+4, al
; ---------------- Node 18 at 0x55555555C5C4. Next: B ----------------
mov eax, cs:tmp_B_5555557671C4
shr eax, 8
mov byte ptr cs:enc_blk_2_5555557671B8+5, al
; ---------------- Node B at 0x55555555A398. Next: 1C ----------------
mov eax, cs:tmp_B_5555557671C4
shr eax, 10h
mov byte ptr cs:enc_blk_2_5555557671B8+6, al
; ---------------- Node 1C at 0x55555555CEC0. Next: 1D ----------------
mov eax, cs:tmp_B_5555557671C4
shr eax, 18h
mov byte ptr cs:enc_blk_2_5555557671B8+7, al
| 32.864671 | 123 | 0.528169 |
2a2e2db492074c054a97a59c104657c409ba6c28 | 736 | asm | Assembly | oeis/241/A241023.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/241/A241023.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/241/A241023.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A241023: Central terms of the triangle in A102413.
; Submitted by Jamie Morken(s4)
; 1,4,16,76,384,2004,10672,57628,314368,1728292,9560016,53144172,296642688,1661529588,9333781872,52566230076,296697618432,1677889961028,9505151782288,53928746972812,306393243712384,1742920028025364,9925790375394096,56584659163097436,322879454150493184,1843983283740252004,10539477427815326032,60283809102230086828,345047287107900244608,1976205583545054417972,11325113338304244306672,64937132817409196429436,372536271982427353841664,2138233401830234768535684,12278354477094960529191696
lpb $0
mov $2,$0
mov $0,0
seq $2,2003 ; a(n) = 2 * Sum_{k=0..n-1} binomial(n-1, k)*binomial(n+k, k).
mov $3,$2
add $3,$2
sub $3,1
lpe
mov $0,$3
add $0,1
| 49.066667 | 484 | 0.809783 |
795d758dd89866ff64ff450a74fb262f989af9fa | 313 | asm | Assembly | programs/oeis/179/A179820.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/179/A179820.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/179/A179820.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A179820: a(n) = n-th triangular number mod (n+2).
; 0,1,3,1,4,1,5,1,6,1,7,1,8,1,9,1,10,1,11,1,12,1,13,1,14,1,15,1,16,1,17,1,18,1,19,1,20,1,21,1,22,1,23,1,24,1,25,1,26,1,27,1,28,1,29,1,30,1,31,1,32,1,33,1,34,1,35,1,36,1,37,1,38,1,39,1,40,1,41,1,42,1,43,1,44,1,45
sub $1,$0
add $0,2
bin $1,2
mod $1,$0
mov $0,$1
| 34.777778 | 211 | 0.578275 |
2a6a12682c2cd95781628518e38e7d6f87c99f17 | 566 | asm | Assembly | oeis/276/A276855.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/276/A276855.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/276/A276855.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A276855: Beatty sequence for (3 + golden ratio).
; Submitted by Jon Maiga
; 0,4,9,13,18,23,27,32,36,41,46,50,55,60,64,69,73,78,83,87,92,96,101,106,110,115,120,124,129,133,138,143,147,152,157,161,166,170,175,180,184,189,193,198,203,207,212,217,221,226,230,235,240,244,249,253,258,263,267,272,277,281,286,290,295,300,304,309,314,318,323,327,332,337,341,346,350,355,360,364,369,374,378,383,387,392,397,401,406,411,415,420,424,429,434,438,443,447,452,457
mov $1,$0
trn $0,1
seq $0,19446 ; a(n) = ceiling(n/tau), where tau = (1+sqrt(5))/2.
mul $1,4
add $0,$1
sub $0,1
| 51.454545 | 376 | 0.69258 |
99cac1b4765ac3bb34b8861c356324979abcddfe | 499 | asm | Assembly | data/baseStats/magikarp.asm | etdv-thevoid/pokemon-rgb-enhanced | 5b244c1cf46aab98b9c820d1b7888814eb7fa53f | [
"MIT"
] | 1 | 2022-01-09T05:28:52.000Z | 2022-01-09T05:28:52.000Z | data/baseStats/magikarp.asm | ETDV-TheVoid/pokemon-rgb-enhanced | 5b244c1cf46aab98b9c820d1b7888814eb7fa53f | [
"MIT"
] | null | null | null | data/baseStats/magikarp.asm | ETDV-TheVoid/pokemon-rgb-enhanced | 5b244c1cf46aab98b9c820d1b7888814eb7fa53f | [
"MIT"
] | null | null | null | db MAGIKARP ; pokedex id
db 20 ; base hp
db 10 ; base attack
db 55 ; base defense
db 80 ; base speed
db 20 ; base special
db WATER ; species type 1
db WATER ; species type 2
db 255 ; catch rate
db 20 ; base exp yield
INCBIN "pic/gsmon/magikarp.pic",0,1 ; 66, sprite dimensions
dw MagikarpPicFront
dw MagikarpPicBack
; attacks known at lvl 0
db SPLASH
db 0
db 0
db 0
db 5 ; growth rate
; learnset
tmlearn 0
tmlearn 0
tmlearn 0
tmlearn 0
tmlearn 0
tmlearn 0
tmlearn 0
db BANK(MagikarpPicFront)
| 17.206897 | 59 | 0.737475 |
a99e7e63e21a5bc793827197a1511a885c264a9f | 1,260 | asm | Assembly | programs/oeis/007/A007582.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/007/A007582.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/007/A007582.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A007582: a(n) = 2^(n-1)*(1+2^n).
; 1,3,10,36,136,528,2080,8256,32896,131328,524800,2098176,8390656,33558528,134225920,536887296,2147516416,8590000128,34359869440,137439215616,549756338176,2199024304128,8796095119360,35184376283136,140737496743936,562949970198528,2251799847239680,9007199321849856,36028797153181696,144115188344291328,576460752840294400,2305843010287435776,9223372039002259456,36893488151714070528,147573952598266347520,590295810375885520896,2361183241469182345216,9444732965808009904128,37778931863094600663040,151115727452103524745216,604462909807864343166976,2417851639230357861040128,9671406556919232420904960,38685626227672531637108736,154742504910681330455412736,618970019642707729635606528,2475880078570795734170337280,9903520314283112567937171456,39614081257132309534260330496,158456325028528956662064611328,633825300114115263698305024000,2535301200456459928893313253376,10141204801825837463773439328256,40564819207303345351494129942528,162259276829213372398777265029120,649037107316853471580710550634496,2596148429267413850294045183574016,10384593717069655329118586696368128,41538374868278621172359158709616640,166153499473114484401206258686754816,664613997892457937028364282443595776
mov $1,2
pow $1,$0
add $1,1
bin $1,2
mov $0,$1
| 140 | 1,176 | 0.915873 |
abc2b376fe760ede74788daa666fc4f5d8aee9c5 | 359 | asm | Assembly | masm/2_loop.asm | oceanwavechina/assembly | 803e4a4c03645fbbc026092b3329ea472e070cab | [
"Apache-2.0"
] | null | null | null | masm/2_loop.asm | oceanwavechina/assembly | 803e4a4c03645fbbc026092b3329ea472e070cab | [
"Apache-2.0"
] | null | null | null | masm/2_loop.asm | oceanwavechina/assembly | 803e4a4c03645fbbc026092b3329ea472e070cab | [
"Apache-2.0"
] | null | null | null | ; 这段代码是演示loop循环的使用，用到了那些寄存器
; 用debug查看loop执行后，如何影响cx(减一)，cs，ip（二者重新指向s处）的
assume cs:pow
pow segment
start:
mov ax, 2 ; 要计算的数据
mov cx, 0bh ; 计数器, 11 是计算2^12, 汇编中数据不能以字母开头，前边要加0
s: add ax, ax ; 要循环的代码块
loop s ; 循环完一次后，检查有没有下次循环，对应 [ (cx) = (cx)-1; if (cx) > 0 goto s else pass;]
mov ax, 4c00h
int 21h
pow ends
end start | 17.95 | 85 | 0.626741 |
c3d1419a38e9a9802237f998d92cf408cb551ea3 | 376 | asm | Assembly | programs/oeis/088/A088921.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/088/A088921.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | programs/oeis/088/A088921.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | ; A088921: The number of 321- and 2143-avoiding permutations of length n.
; 1,2,5,13,33,80,185,411,885,1862,3853,7881,15993,32284,64945,130359,261293,523282,1047397,2095781,4192721,8386792,16775145,33552083,67106213,134214750,268432125,536867201,1073737705,2147479092
mov $1,1
mov $2,1
mov $3,1
lpb $0
sub $0,1
add $2,$4
add $1,$2
mul $3,2
trn $4,1
add $4,$3
lpe
| 25.066667 | 193 | 0.720745 |
3b745d96f5458470d97aa1736b5745c1b451f7b5 | 5,290 | asm | Assembly | Transynther/x86/_processed/NONE/_zr_/i3-7100_9_0x84_notsx.log_21829_1491.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_zr_/i3-7100_9_0x84_notsx.log_21829_1491.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_zr_/i3-7100_9_0x84_notsx.log_21829_1491.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r9
push %rbp
push %rcx
lea addresses_WT_ht+0x120f0, %rcx
nop
nop
nop
nop
nop
sub $64254, %r10
movw $0x6162, (%rcx)
nop
nop
nop
nop
cmp $961, %r9
pop %rcx
pop %rbp
pop %r9
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r13
push %r9
push %rcx
push %rdi
push %rdx
push %rsi
// Load
lea addresses_normal+0x10970, %rdi
nop
add %rsi, %rsi
mov (%rdi), %r13d
// Exception!!!
nop
nop
nop
mov (0), %rdx
nop
nop
nop
xor $50864, %rsi
// Store
lea addresses_WC+0x1baee, %rdx
nop
nop
nop
nop
nop
cmp %r10, %r10
movl $0x51525354, (%rdx)
nop
sub %rsi, %rsi
// Store
lea addresses_WC+0xa970, %rdx
nop
nop
nop
inc %r9
mov $0x5152535455565758, %rdi
movq %rdi, (%rdx)
nop
nop
nop
nop
nop
sub %r9, %r9
// Store
lea addresses_US+0x1a370, %r10
nop
nop
add $47427, %rdi
mov $0x5152535455565758, %rsi
movq %rsi, (%r10)
nop
and $57714, %rcx
// Store
lea addresses_WT+0x16f0, %rsi
sub %r9, %r9
movl $0x51525354, (%rsi)
nop
nop
cmp $42804, %r9
// Faulty Load
lea addresses_A+0xfa70, %rdx
nop
cmp $15923, %rcx
mov (%rdx), %rdi
lea oracles, %rdx
and $0xff, %rdi
shlq $12, %rdi
mov (%rdx,%rdi,1), %rdi
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %r9
pop %r13
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_A', 'same': False, 'size': 32, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_normal', 'same': False, 'size': 4, 'congruent': 8, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_WC', 'same': False, 'size': 4, 'congruent': 1, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_WC', 'same': False, 'size': 8, 'congruent': 7, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_US', 'same': False, 'size': 8, 'congruent': 6, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_WT', 'same': False, 'size': 4, 'congruent': 5, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'type': 'addresses_A', 'same': True, 'size': 8, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'dst': {'type': 'addresses_WT_ht', 'same': False, 'size': 2, 'congruent': 3, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
| 40.381679 | 2,999 | 0.654253 |
992e5fbb959a5d4775b243c9087e5638a665d1aa | 666 | asm | Assembly | FictionTools/z88dk/libsrc/z80_crt0s/z80/sccz80/lpush2.asm | polluks/Puddle-BuildTools | c1762d53a33002b62d8cffe3db129505a387bec3 | [
"BSD-2-Clause"
] | 38 | 2021-06-18T12:56:15.000Z | 2022-03-12T20:38:40.000Z | FictionTools/z88dk/libsrc/z80_crt0s/z80/sccz80/lpush2.asm | polluks/Puddle-BuildTools | c1762d53a33002b62d8cffe3db129505a387bec3 | [
"BSD-2-Clause"
] | 2 | 2021-06-20T16:28:12.000Z | 2021-11-17T21:33:56.000Z | FictionTools/z88dk/libsrc/z80_crt0s/z80/sccz80/lpush2.asm | polluks/Puddle-BuildTools | c1762d53a33002b62d8cffe3db129505a387bec3 | [
"BSD-2-Clause"
] | 6 | 2021-06-18T18:18:36.000Z | 2021-12-22T08:01:32.000Z | ;
; Small C+ Compiler
;
; Long Support Library
;
; 1/3/99 djm
; This routine is used to push longs on the stack for a
; call to a function defined as a pointer. To make the
; routine shorter (by one byte) we could use ix - pop ix/jp(ix)
; but we'd lose 6T - give me your thoughts as to whether it's
; worth it...
; actually use of ix saves us 4T
SECTION code_crt0_sccz80
PUBLIC lpush2
.lpush2
IF __CPU_INTEL__ || __CPU_GBZ80__
pop af
ELSE
pop ix
ENDIF
pop bc
push de
push hl
push bc
IF __CPU_INTEL__ || __CPU_GBZ80__
push af
ret
ELSE
jp (ix)
ENDIF
| 17.076923 | 69 | 0.603604 |
ecec6a7c4f4faaf569baff7864198e1e9f275386 | 824 | asm | Assembly | libsrc/gfx/narrow/xorcircle_callee.asm | ahjelm/z88dk | c4de367f39a76b41f6390ceeab77737e148178fa | [
"ClArtistic"
] | 640 | 2017-01-14T23:33:45.000Z | 2022-03-30T11:28:42.000Z | libsrc/gfx/narrow/xorcircle_callee.asm | C-Chads/z88dk | a4141a8e51205c6414b4ae3263b633c4265778e6 | [
"ClArtistic"
] | 1,600 | 2017-01-15T16:12:02.000Z | 2022-03-31T12:11:12.000Z | libsrc/gfx/narrow/xorcircle_callee.asm | C-Chads/z88dk | a4141a8e51205c6414b4ae3263b633c4265778e6 | [
"ClArtistic"
] | 215 | 2017-01-17T10:43:03.000Z | 2022-03-23T17:25:02.000Z | ; Usage: xorcircle(int x, int y, int radius, int skip);
IF !__CPU_INTEL__ & !__CPU_GBZ80__
SECTION code_graphics
PUBLIC xorcircle_callee
PUBLIC _xorcircle_callee
PUBLIC asm_xorcircle
EXTERN draw_circle
EXTERN xorpixel
EXTERN swapgfxbk
EXTERN __graphics_end
INCLUDE "graphics/grafix.inc"
.xorcircle_callee
._xorcircle_callee
pop af
pop de ; skip
pop bc ;radius
ld d,c
pop bc ; y
pop hl ; x
ld b,l
push af
.asm_xorcircle
push ix
ld ix,xorpixel
IF NEED_swapgfxbk = 1
call swapgfxbk
ENDIF
call draw_circle
IF NEED_swapgfxbk
jp __graphics_end
ELSE
IF !__CPU_INTEL__ & !__CPU_GBZ80__
pop ix
ENDIF
ret
ENDIF
ENDIF
| 17.166667 | 55 | 0.597087 |
bde25d759d6826e6b3be6f814227942af6bd5027 | 2,524 | asm | Assembly | core/nes/GameShell.asm | puzzud/puzl6502 | c38fa015d0d25f2c29f79fa41de10f8cc8c39693 | [
"MIT"
] | null | null | null | core/nes/GameShell.asm | puzzud/puzl6502 | c38fa015d0d25f2c29f79fa41de10f8cc8c39693 | [
"MIT"
] | null | null | null | core/nes/GameShell.asm | puzzud/puzl6502 | c38fa015d0d25f2c29f79fa41de10f8cc8c39693 | [
"MIT"
] | null | null | null | ; GameShell.asm
; NES
!src "puzl/core/nes/nes.asm"
NMIStatus = $01
!set ramCounter = START_OF_RAM
; Move these defines to a VideoSystem.inc file.
UpdateNameTable = zeroPageCounter
UpdateAttributeTable = zeroPageCounter+1
UpdatePaletteTable = zeroPageCounter+2
!set zeroPageCounter = zeroPageCounter+3
;==================================================================
*=$fffa
!zone InitVectors
InitVectors
!word MNIRoutine
!word Reset
!word IRQRoutine
;==================================================================
*=(InitVectors-100);TODO: Determine minus value (block size).
!zone Reset
Reset
sei ; disable IRQs
cld ; disable decimal mode
lda #0
.clearMemory
sta $00,x ;7
sta $0100,x ;28
sta $0200,x
sta $0300,x
sta $0400,x
sta $0500,x
sta $0600,x
sta $0700,x
inx ;5
bne .clearMemory
dex ; ldx #$ff
txs ; Set up stack
; Set up MMC5 Rom banks and such.
lda #$00 ;37
sta MMC5_PRG_MODE
sta MMC5_CHR_MODE
lda #$01
sta MMC5_EXRAM_MODE
lda #%00000000
sta MMC5_NTABLE_MAP
lda #$01
sta MMC5_BKGRD_CHR_BANK_3
lda #$01
sta MMC5_SPR_CHR_BANK_7
lda #$00
sta MMC5_VERT_SPLIT_MODE
sta MMC5_IRQ_STATUS
jmp MainStart
;==================================================================
*=$7ff0
; iNES header.
!raw "NES" ;"NES"
!byte $1a ;$1a
!byte 2 ;2 x 16KB PRG-ROM
!byte 1 ;1 X 8KB CHR-ROM
!byte $50;((5<<4)|(2)) ;ROM control 1
!byte 0 ;ROM control 2
!byte $00
!byte $00
!byte $00
!byte $00
!byte $00
!byte $00
!byte $00
!byte $00
;==================================================================
*=$8000
!zone MainStart
MainStart
jsr MainInitialize
jsr GameInitialize
.mainLoop
lda #0 ;
sta NMIStatus ; Wait for next NMI to end.
.waitNMIEnd
lda NMIStatus ;
beq .waitNMIEnd ; If nonzero, NMI has ended. Else keep waiting.
jsr UpdateInput
jsr IncrementFrameCounter
jsr GameLoop
jsr UpdateVideoMMC5
jmp .mainLoop
;------------------------------------------------------------------
!zone MNIRoutine
MNIRoutine
php
pha
txa
pha
tya
pha
jsr UpdateSprites
jsr UpdateVideo
.NMIFinished
lda #1
sta NMIStatus
pla
tay
pla
tax
pla
plp
rti
;------------------------------------------------------------------
!zone IRQRoutine
IRQRoutine
rti
| 18.028571 | 67 | 0.514263 |
68adbd3cf95000c63c182f5b6fbe72bde4ed005d | 7,856 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_sm_/i7-7700_9_0xca_notsx.log_21829_32.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_sm_/i7-7700_9_0xca_notsx.log_21829_32.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_sm_/i7-7700_9_0xca_notsx.log_21829_32.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r13
push %r14
push %r8
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_UC_ht+0x1db9b, %r10
nop
nop
nop
nop
nop
sub %r13, %r13
mov $0x6162636465666768, %rsi
movq %rsi, %xmm1
movups %xmm1, (%r10)
add $8691, %r14
lea addresses_normal_ht+0x3acb, %r13
nop
nop
nop
nop
add %rdx, %rdx
movb $0x61, (%r13)
cmp %rdx, %rdx
lea addresses_WT_ht+0x770b, %rsi
lea addresses_D_ht+0x63ab, %rdi
nop
nop
dec %r10
mov $58, %rcx
rep movsw
nop
nop
nop
nop
and %r14, %r14
lea addresses_WC_ht+0x88b, %rcx
nop
nop
nop
inc %rdx
mov $0x6162636465666768, %r10
movq %r10, %xmm4
vmovups %ymm4, (%rcx)
nop
nop
nop
cmp $38055, %r14
lea addresses_UC_ht+0x3ffb, %rsi
lea addresses_UC_ht+0x1a6cb, %rdi
nop
cmp $25571, %rdx
mov $27, %rcx
rep movsl
nop
xor $9808, %rdi
lea addresses_WC_ht+0x164cb, %rsi
lea addresses_UC_ht+0x24cb, %rdi
cmp %r8, %r8
mov $124, %rcx
rep movsl
and $27664, %r10
lea addresses_A_ht+0x14367, %r10
nop
nop
nop
inc %r8
mov (%r10), %edi
nop
nop
nop
nop
nop
inc %r14
lea addresses_A_ht+0xccdb, %r14
nop
nop
and %rdi, %rdi
mov $0x6162636465666768, %rdx
movq %rdx, %xmm2
vmovups %ymm2, (%r14)
nop
nop
nop
nop
nop
cmp $9242, %rdx
lea addresses_WT_ht+0x15ecb, %rsi
lea addresses_WC_ht+0x4ccb, %rdi
clflush (%rdi)
nop
nop
add %r14, %r14
mov $114, %rcx
rep movsl
nop
nop
nop
nop
cmp %r13, %r13
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %r8
pop %r14
pop %r13
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r13
push %r14
push %r9
push %rbp
push %rcx
push %rdi
push %rdx
// Load
lea addresses_RW+0x137e7, %rdx
nop
add %rbp, %rbp
mov (%rdx), %r9w
nop
inc %rcx
// Store
lea addresses_PSE+0x34cb, %r13
clflush (%r13)
nop
sub $60923, %rdi
mov $0x5152535455565758, %rbp
movq %rbp, %xmm5
movups %xmm5, (%r13)
nop
nop
xor $45411, %r9
// Store
lea addresses_A+0xd44b, %r9
nop
dec %rcx
mov $0x5152535455565758, %r13
movq %r13, %xmm1
movups %xmm1, (%r9)
nop
nop
nop
nop
nop
sub $55481, %rbp
// Store
lea addresses_WT+0x64cb, %r9
nop
sub $33787, %r13
movb $0x51, (%r9)
nop
nop
nop
xor $20044, %r13
// Store
lea addresses_WC+0x6ccb, %rcx
nop
nop
add %rdi, %rdi
movl $0x51525354, (%rcx)
nop
nop
nop
nop
dec %r13
// Store
lea addresses_PSE+0xafcb, %rcx
clflush (%rcx)
add %r14, %r14
mov $0x5152535455565758, %r13
movq %r13, %xmm5
vmovups %ymm5, (%rcx)
nop
nop
nop
nop
and $24084, %rdx
// Faulty Load
lea addresses_PSE+0x34cb, %r9
nop
nop
nop
nop
nop
sub $3778, %r14
mov (%r9), %edx
lea oracles, %r13
and $0xff, %rdx
shlq $12, %rdx
mov (%r13,%rdx,1), %rdx
pop %rdx
pop %rdi
pop %rcx
pop %rbp
pop %r9
pop %r14
pop %r13
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': True, 'AVXalign': False, 'size': 1, 'congruent': 0, 'same': True, 'type': 'addresses_PSE'}, 'OP': 'LOAD'}
{'src': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 2, 'same': False, 'type': 'addresses_RW'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 0, 'same': True, 'type': 'addresses_PSE'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 5, 'same': False, 'type': 'addresses_A'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 9, 'same': False, 'type': 'addresses_WT'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 11, 'same': False, 'type': 'addresses_WC'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 7, 'same': False, 'type': 'addresses_PSE'}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 0, 'same': True, 'type': 'addresses_PSE'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'dst': {'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 3, 'same': False, 'type': 'addresses_UC_ht'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 9, 'same': False, 'type': 'addresses_normal_ht'}, 'OP': 'STOR'}
{'src': {'congruent': 6, 'same': False, 'type': 'addresses_WT_ht'}, 'dst': {'congruent': 4, 'same': False, 'type': 'addresses_D_ht'}, 'OP': 'REPM'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 5, 'same': False, 'type': 'addresses_WC_ht'}, 'OP': 'STOR'}
{'src': {'congruent': 3, 'same': False, 'type': 'addresses_UC_ht'}, 'dst': {'congruent': 8, 'same': False, 'type': 'addresses_UC_ht'}, 'OP': 'REPM'}
{'src': {'congruent': 11, 'same': False, 'type': 'addresses_WC_ht'}, 'dst': {'congruent': 11, 'same': False, 'type': 'addresses_UC_ht'}, 'OP': 'REPM'}
{'src': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 2, 'same': True, 'type': 'addresses_A_ht'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 4, 'same': False, 'type': 'addresses_A_ht'}, 'OP': 'STOR'}
{'src': {'congruent': 9, 'same': False, 'type': 'addresses_WT_ht'}, 'dst': {'congruent': 11, 'same': False, 'type': 'addresses_WC_ht'}, 'OP': 'REPM'}
{'58': 21829}
58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58
*/
| 32.46281 | 2,999 | 0.655677 |
968373f9a8a2829f2ba7169420c08849bfe5abae | 6,938 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca.log_21829_1438.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca.log_21829_1438.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca.log_21829_1438.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r12
push %r13
push %r14
push %rbp
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_UC_ht+0x11f70, %r10
nop
nop
nop
nop
xor $56745, %rsi
movups (%r10), %xmm7
vpextrq $1, %xmm7, %r12
nop
nop
nop
nop
nop
cmp %r13, %r13
lea addresses_WT_ht+0x165c5, %r12
nop
nop
nop
nop
cmp $28880, %rbp
mov $0x6162636465666768, %r14
movq %r14, %xmm3
vmovups %ymm3, (%r12)
nop
nop
nop
nop
nop
and %r10, %r10
lea addresses_WT_ht+0xf145, %r14
nop
cmp %rdx, %rdx
movl $0x61626364, (%r14)
dec %r12
lea addresses_WC_ht+0x8ba5, %r14
nop
nop
nop
nop
cmp %rbp, %rbp
and $0xffffffffffffffc0, %r14
movaps (%r14), %xmm1
vpextrq $0, %xmm1, %r10
nop
nop
nop
nop
add $50800, %r13
lea addresses_D_ht+0x1bb45, %r10
nop
nop
nop
nop
cmp $30121, %rdx
mov $0x6162636465666768, %rsi
movq %rsi, %xmm5
vmovups %ymm5, (%r10)
nop
xor %r10, %r10
lea addresses_D_ht+0x9d45, %rsi
lea addresses_WT_ht+0x1c845, %rdi
nop
nop
nop
nop
nop
add %r10, %r10
mov $99, %rcx
rep movsq
nop
nop
nop
nop
nop
xor %rdi, %rdi
lea addresses_UC_ht+0x4985, %rsi
lea addresses_WT_ht+0xb471, %rdi
nop
nop
nop
nop
cmp $49897, %r13
mov $76, %rcx
rep movsb
nop
nop
nop
nop
nop
dec %rcx
lea addresses_D_ht+0x12745, %rsi
lea addresses_UC_ht+0x1bc25, %rdi
nop
nop
nop
nop
nop
sub $63402, %rdx
mov $61, %rcx
rep movsl
nop
nop
nop
nop
nop
add $24987, %r12
lea addresses_D_ht+0x4f45, %r14
nop
cmp %rdi, %rdi
mov $0x6162636465666768, %rsi
movq %rsi, %xmm0
vmovups %ymm0, (%r14)
nop
inc %r14
lea addresses_A_ht+0xc345, %rsi
lea addresses_D_ht+0x6345, %rdi
xor $19018, %rbp
mov $70, %rcx
rep movsq
nop
sub $58159, %rdx
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbp
pop %r14
pop %r13
pop %r12
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r14
push %r9
push %rbx
push %rcx
push %rdi
push %rdx
// Store
lea addresses_WT+0x18785, %r14
sub $27930, %rbx
mov $0x5152535455565758, %r9
movq %r9, (%r14)
nop
nop
nop
xor $5540, %rbx
// Faulty Load
lea addresses_normal+0x10345, %r14
nop
nop
nop
sub %rdx, %rdx
mov (%r14), %rbx
lea oracles, %r14
and $0xff, %rbx
shlq $12, %rbx
mov (%r14,%rbx,1), %rbx
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %r9
pop %r14
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'size': 8, 'NT': True, 'type': 'addresses_normal', 'same': False, 'AVXalign': False, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'size': 8, 'NT': False, 'type': 'addresses_WT', 'same': False, 'AVXalign': False, 'congruent': 6}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'size': 8, 'NT': False, 'type': 'addresses_normal', 'same': True, 'AVXalign': False, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_UC_ht', 'same': False, 'AVXalign': False, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'size': 32, 'NT': False, 'type': 'addresses_WT_ht', 'same': False, 'AVXalign': False, 'congruent': 6}}
{'OP': 'STOR', 'dst': {'size': 4, 'NT': False, 'type': 'addresses_WT_ht', 'same': False, 'AVXalign': False, 'congruent': 9}}
{'OP': 'LOAD', 'src': {'size': 16, 'NT': True, 'type': 'addresses_WC_ht', 'same': False, 'AVXalign': True, 'congruent': 5}}
{'OP': 'STOR', 'dst': {'size': 32, 'NT': False, 'type': 'addresses_D_ht', 'same': False, 'AVXalign': False, 'congruent': 8}}
{'OP': 'REPM', 'src': {'same': True, 'type': 'addresses_D_ht', 'congruent': 8}, 'dst': {'same': False, 'type': 'addresses_WT_ht', 'congruent': 8}}
{'OP': 'REPM', 'src': {'same': True, 'type': 'addresses_UC_ht', 'congruent': 4}, 'dst': {'same': False, 'type': 'addresses_WT_ht', 'congruent': 2}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_D_ht', 'congruent': 10}, 'dst': {'same': False, 'type': 'addresses_UC_ht', 'congruent': 4}}
{'OP': 'STOR', 'dst': {'size': 32, 'NT': False, 'type': 'addresses_D_ht', 'same': False, 'AVXalign': False, 'congruent': 8}}
{'OP': 'REPM', 'src': {'same': True, 'type': 'addresses_A_ht', 'congruent': 7}, 'dst': {'same': False, 'type': 'addresses_D_ht', 'congruent': 11}}
{'34': 21829}
34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34
*/
| 34.17734 | 2,999 | 0.661142 |
f8ab856c2d1b9b7da2a1c6c9e2a5c43e3842c790 | 335 | asm | Assembly | programs/oeis/072/A072912.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/072/A072912.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/072/A072912.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A072912: Number of Fibonacci numbers F(k) <= 10^n which end in 0.
; 1,1,1,2,2,2,3,3,3,3,4,4,4,5,5,5,6,6,6,7,7,7,8,8,8,9,9,9,10,10,10,11,11,11,11,12,12,12,13,13,13,14,14,14,15,15,15,16,16,16,17,17,17,18,18,18,18,19,19,19,20,20,20,21,21,21,22,22,22,23,23,23,24,24,24,25,25,25
mul $0,23
mov $1,7
add $1,$0
div $1,72
add $1,1
mov $0,$1
| 33.5 | 207 | 0.61791 |
b40b6501abc603dc3121a449449e3c765778cc4c | 4,272 | asm | Assembly | Breakout.asm | MischaTobias/BreakoutInASM | de8d4ebef79e197e5beb52e5331a3b970587d893 | [
"CC0-1.0"
] | 2 | 2022-02-04T03:45:42.000Z | 2022-02-04T03:45:50.000Z | Breakout.asm | MischaTobias/BreakoutInASM | de8d4ebef79e197e5beb52e5331a3b970587d893 | [
"CC0-1.0"
] | null | null | null | Breakout.asm | MischaTobias/BreakoutInASM | de8d4ebef79e197e5beb52e5331a3b970587d893 | [
"CC0-1.0"
] | null | null | null | //INITIAL VALUES
// BAR
@24397
D=A
@0 //Bar address
M=D
@3
D=A
@1 //Row drawing
M=D
@6
D=A
@2 //Column Drawing
M=D
// BALL
@23823 //Ball initial position
D=A
@7
M=D
@16 //Number for screen painting
D=A
@8
M=D
// Ball Movement values
@9
M=-1
@10
M=-1
//BAR PROCESS
(BAR) //20 (12)
@0 //Bar address
A=M
M=-1
@0 //Bar address
M=M+1
@2 //Column Drawing
M=M-1
D=M
@NEXT
D;JEQ
@BAR
0;JMP
(NEXT)//32 (21) // Value resetting for next bar row.
@26 // 32-6
D=A
@0 //Bar address
M=M+D
@6
D=A
@2 //Column Drawing
M=D
@1 //Row drawing
M=M-1
D=M
@BAR
D;JGT // Loop ending
@96 // 32 + 32 + 32
D=A
@0 //Bar address
M=M-D
// Value resetting for next bar drawing.
@3
D=A
@1 //Row drawing
M=D
(LOOP)//53 (6)
//TIMER
@150
D=A
@6
M=D
@BALL_ERASE
0;JMP
(PRESSED) //59 (24)
//130 left
//132 right
@KBD //55
D=M
@3
M=D
@0
D=M
@4
M=D
@130
D=A
@3
M=M-D
D=M
@LEFT
D;JEQ
@2 //Column Drawing
D=A
@3
M=M-D
D=M
@RIGHT
D;JEQ
@LOOP
0;JMP
(LEFT) //83 (18)
//Erase 3 columns to the right and add 3 to the left. Check row limits.
@24384
D=A
@0
D=D-M
@LOOP
D;JEQ
// Erasing position
@5
D=A
@4
M=M+D
// Moving position to the left
@0
M=M-1
// Values for erasing
@3
D=A
@5
M=D
@BARERASE
0;JMP
(RIGHT) //101 (14)
//Erase 3 columns to the left and add 3 to the right. Check row limits.
@24410
D=A
@0
D=D-M
@LOOP
D;JEQ
// Moving position to the right
@0
M=M+1
// Values for erasing
@3
D=A
@5
M=D
@BARERASE
0;JMP
(BARERASE) //115 (3)
@4 //Bar address
A=M
M=0
(NEXTERASE) //118 (15)
@32
D=A
@4 //Bar address
M=M+D
@5 // Row for erasing
M=M-1
D=M
@BARERASE
D;JGT // Loop ending
// Resetting values for next bar erase.
@3
D=A
@5 // Row for erasing
M=D
@BAR
0;JMP
//BALL PROCESS
(BALL) //133 (20)
@7
A=M
M=-1
@32
D=A
@7
M=M+D
@8
M=M-1
D=M
@BALL
D;JGT
@512
D=A
@7
M=M-D
@16
D=A
@8
M=D
(TIMER) //153 (7)
@6
M=M-1
D=M
@CHECKIFPRESSED
D;JEQ
@TIMER
0;JMP
(CHECKIFPRESSED) //160 (6)
@KBD
D=M
@PRESSED
D;JGT
@LOOP
0;JMP
(BALL_ERASE) //170 (27)
@7
A=M
M=0
@32
D=A
@7
M=M+D
@8
M=M-1
D=M
@BALL_ERASE
D;JGT
@512
D=A
@7
M=M-D
@16
D=A
@8
M=D
//CHANGING POSITION
@9
D=M
D=D+1
@LEFTBALL
D;JEQ
@RIGHTBALL
0;JMP
(LEFTBALL) //197 (4)
@24544
D=A
@11
M=D
(LEFTBALL_LOOP) //201 (18)
@11
D=M
@7
D=D-M
@12
M=D
@32
D=A
@11
M=M-D
@12
D=M
@MOVE_LEFT
D;JLT
@BOUNCE_RIGHT
D;JEQ
@LEFTBALL_LOOP
0;JMP
(MOVE_LEFT) //219 (4)
@7
M=M-1
@CHECK_VERTICAL
0;JMP
(BOUNCE_RIGHT) //223 (4)
@9
M=1
@CHECK_VERTICAL
0;JMP
(RIGHTBALL) //227 (4)
@24575
D=A
@11
M=D
(RIGHTBALL_LOOP) //231 (18)
@11
D=M
@7
D=D-M
@12
M=D
@32
D=A
@11
M=M-D
@12
D=M
@MOVE_RIGHT
D;JLT
@BOUNCE_LEFT
D;JEQ
@RIGHTBALL_LOOP
0;JMP
(MOVE_RIGHT) //249 (4)
@7
M=M+1
@CHECK_VERTICAL
0;JMP
(BOUNCE_LEFT) //253 (4)
@9
M=-1
@CHECK_VERTICAL
0;JMP
(CHECK_VERTICAL) //257 (7)
@10
D=M
D=D+1
@UPBALL
D;JEQ
@DOWNBALL
0;JMP
(UPBALL) //264 (8)
@16415
D=A
@7
D=D-M
@MOVE_UP
D;JLT
@BOUNCE_DOWN
0;JMP
(MOVE_UP) //272 (6)
@32
D=A
@7
M=M-D
@BALL
0;JMP
(BOUNCE_DOWN) //278 (4)
@10
M=1
@BALL
0;JMP
(DOWNBALL) //282 (20)
@23935
D=A
@7
D=D-M
@END
D;JLT
@512
D=A
@7
D=D+M
A=D
D=M
@BOUNCE_UP
D;JLT
@32
D=A
@7
M=M+D
@BALL
0;JMP
(BOUNCE_UP) //302 (4)
@10
M=-1
@BALL
0;JMP
(END) //306 (2)
@END
0;JMP | 11.212598 | 71 | 0.445693 |
ee1d9664da7ffe992f32d5dd640d0e22fa00b5a8 | 1,248 | asm | Assembly | programs/oeis/188/A188862.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/188/A188862.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/188/A188862.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A188862: Number of n X 5 binary arrays without the pattern 0 1 diagonally, vertically or antidiagonally.
; 32,99,178,259,340,421,502,583,664,745,826,907,988,1069,1150,1231,1312,1393,1474,1555,1636,1717,1798,1879,1960,2041,2122,2203,2284,2365,2446,2527,2608,2689,2770,2851,2932,3013,3094,3175,3256,3337,3418,3499,3580,3661,3742,3823,3904,3985,4066,4147,4228,4309,4390,4471,4552,4633,4714,4795,4876,4957,5038,5119,5200,5281,5362,5443,5524,5605,5686,5767,5848,5929,6010,6091,6172,6253,6334,6415,6496,6577,6658,6739,6820,6901,6982,7063,7144,7225,7306,7387,7468,7549,7630,7711,7792,7873,7954,8035,8116,8197,8278,8359,8440,8521,8602,8683,8764,8845,8926,9007,9088,9169,9250,9331,9412,9493,9574,9655,9736,9817,9898,9979,10060,10141,10222,10303,10384,10465,10546,10627,10708,10789,10870,10951,11032,11113,11194,11275,11356,11437,11518,11599,11680,11761,11842,11923,12004,12085,12166,12247,12328,12409,12490,12571,12652,12733,12814,12895,12976,13057,13138,13219,13300,13381,13462,13543,13624,13705,13786,13867,13948,14029,14110,14191,14272,14353,14434,14515,14596,14677,14758,14839,14920,15001,15082,15163,15244,15325,15406,15487,15568,15649,15730,15811,15892,15973,16054,16135
mov $1,2
trn $1,$0
pow $1,3
mul $1,2
add $1,16
mov $2,$0
mul $2,81
add $1,$2
| 104 | 1,062 | 0.791667 |
6d42c2ab75685939f506d2681ba148c90000b024 | 21,687 | asm | Assembly | base/ntos/rtl/i386/largeint.asm | npocmaka/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 17 | 2020-11-13T13:42:52.000Z | 2021-09-16T09:13:13.000Z | base/ntos/rtl/i386/largeint.asm | sancho1952007/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 2 | 2020-10-19T08:02:06.000Z | 2020-10-19T08:23:18.000Z | base/ntos/rtl/i386/largeint.asm | sancho1952007/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 14 | 2020-11-14T09:43:20.000Z | 2021-08-28T08:59:57.000Z | TITLE "Large Integer Arithmetic"
;++
;
; Copyright (c) 1989 Microsoft Corporation
;
; Module Name:
;
; largeint.s
;
; Abstract:
;
; This module implements routines for performing extended integer
; arithmtic.
;
; Author:
;
; David N. Cutler (davec) 24-Aug-1989
;
; Environment:
;
; Any mode.
;
; Revision History:
;
;--
.386p
.xlist
include ks386.inc
include callconv.inc ; calling convention macros
.list
IFNDEF BLDR_KERNEL_RUNTIME
EXTRNP _RtlRaiseStatus, 1
ENDIF
_TEXT$00 SEGMENT DWORD PUBLIC 'CODE'
ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
page ,132
subttl "RtlLargeIntegerAdd"
;++
;
; LARGE_INTEGER
; RtlLargeIntegerAdd (
; IN LARGE_INTEGER Addend1,
; IN LARGE_INTEGER Addend2
; )
;
; Routine Description:
;
; This function adds a signed large integer to a signed large integer and
; returns the signed large integer result.
;
; Arguments:
;
; (TOS+4) = Addend1 - first addend value
; (TOS+12) = Addend2 - second addend value
;
; Return Value:
;
; The large integer result is stored in (edx:eax)
;
;--
cPublicProc _RtlLargeIntegerAdd ,4
cPublicFpo 4,0
mov eax,[esp]+4 ; (eax)=add1.low
add eax,[esp]+12 ; (eax)=sum.low
mov edx,[esp]+8 ; (edx)=add1.hi
adc edx,[esp]+16 ; (edx)=sum.hi
stdRET _RtlLargeIntegerAdd
stdENDP _RtlLargeIntegerAdd
page
subttl "Enlarged Integer Multiply"
;++
;
; LARGE_INTEGER
; RtlEnlargedIntegerMultiply (
; IN LONG Multiplicand,
; IN LONG Multiplier
; )
;
; Routine Description:
;
; This function multiplies a signed integer by an signed integer and
; returns a signed large integer result.
;
; Arguments:
;
; (TOS+4) = Factor1
; (TOS+8) = Factor2
;
; Return Value:
;
; The large integer result is stored in (edx:eax)
;
;--
cPublicProc __RtlEnlargedIntegerMultiply ,2
cPublicFpo 2,0
mov eax,[esp]+4 ; (eax) = factor1
imul dword ptr [esp]+8 ; (edx:eax) = signed result
stdRET __RtlEnlargedIntegerMultiply
stdENDP __RtlEnlargedIntegerMultiply
page
subttl "Enlarged Unsigned Integer Multiply"
;++
;
; LARGE_INTEGER
; RtlEnlargedUnsignedMultiply (
; IN ULONG Multiplicand,
; IN ULONG Multiplier
; )
;
; Routine Description:
;
; This function multiplies an un signed integer by an unsigned integer and
; returns a signed large integer result.
;
; Arguments:
;
; (TOS+4) = Factor1
; (TOS+8) = Factor2
;
; Return Value:
;
; The large integer result is stored in (edx:eax)
;
;--
cPublicProc __RtlEnlargedUnsignedMultiply ,2
cPublicFpo 2,0
mov eax,[esp]+4 ; (eax) = factor1
mul dword ptr [esp]+8 ; (edx:eax) = unsigned result
stdRET __RtlEnlargedUnsignedMultiply
stdENDP __RtlEnlargedUnsignedMultiply
page
subttl "Enlarged Unsigned Integer Divide"
;++
;
; ULONG
; RtlEnlargedUnsignedDivide (
; IN ULARGE_INTEGER Dividend,
; IN ULONG Divisor,
; IN PULONG Remainder
; )
;
;
; Routine Description:
;
; This function divides an unsigned large integer by an unsigned long
; and returns the resultant quotient and optionally the remainder.
;
; Arguments:
;
; Dividend - Supplies the dividend value.
;
; Divisor - Supplies the divisor value.
;
; Remainder - Supplies an optional pointer to a variable that
; receives the remainder.
;
; Return Value:
;
; The unsigned long integer quotient is returned as the function value.
;
;--
cPublicProc __RtlEnlargedUnsignedDivide,4
cPublicFpo 4,0
mov eax, [esp+4] ; (eax) = Dividend.LowPart
mov edx, [esp+8] ; (edx) = Dividend.HighPart
mov ecx, [esp+16] ; (ecx) = pRemainder
div dword ptr [esp+12] ; divide by Divisor
or ecx, ecx ; return remainder?
jnz short @f
stdRET __RtlEnlargedUnsignedDivide ; (eax) = Quotient
align 4
@@: mov [ecx], edx ; save remainder
stdRET __RtlEnlargedUnsignedDivide ; (eax) = Quotient
stdENDP __RtlEnlargedUnsignedDivide
page
subttl "Extended Large Integer Divide"
;++
;
; LARGE_INTEGER
; RtlExtendedLargeIntegerDivide (
; IN LARGE_INTEGER Dividend,
; IN ULONG Divisor,
; OUT PULONG Remainder OPTIONAL
; )
;
; Routine Description:
;
; This routine divides an unsigned 64 bit dividend by a 32 bit divisor
; and returns a 64-bit quotient, and optionally the 32-bit remainder.
;
;
; Arguments:
;
; Dividend - Supplies the 64 bit dividend for the divide operation.
;
; Divisor - Supplies the 32 bit divisor for the divide operation.
;
; Remainder - Supplies an optional pointer to a variable which receives
; the remainder
;
; Return Value:
;
; The 64-bit quotient is returned as the function value.
;
;--
cPublicProc _RtlExtendedLargeIntegerDivide, 4
cPublicFpo 4,3
push esi
push edi
push ebx
mov eax, [esp+16] ; (eax) = Dividend.LowPart
mov edx, [esp+20] ; (edx) = Dividend.HighPart
lid00: mov ebx, [esp+24] ; (ebx) = Divisor
or ebx, ebx
jz short lid_zero ; Attempted a divide by zero
push ebp
mov ecx, 64 ; Loop count
xor esi, esi ; Clear partial remainder
; (edx:eax) = Dividend
; (ebx) = Divisor
; (ecx) = Loop count
; (esi) = partial remainder
align 4
lid10: shl eax, 1 ; (LowPart << 1) | 0
rcl edx, 1 ; (HighPart << 1) | CF
rcl esi, 1 ; (Partial << 1) | CF
sbb edi, edi ; clone CF into edi (0 or -1)
cmp esi, ebx ; check if partial remainder less then divisor
cmc
sbb ebp, ebp ; clone CF intp ebp
or edi, ebp ; merge with remainder of high bit
sub eax, edi ; merge quotient bit
and edi, ebx ; Select divisor or 0
sub esi, edi
dec ecx ; dec interration count
jnz short lid10 ; go around again
pop ebp
pop ebx
pop edi
mov ecx, [esp+20] ; (ecx) = Remainder
or ecx, ecx
jnz short lid20
pop esi
stdRET _RtlExtendedLargeIntegerDivide
align 4
lid20:
mov [ecx], esi ; store remainder
pop esi
stdRET _RtlExtendedLargeIntegerDivide
lid_zero:
IFNDEF BLDR_KERNEL_RUNTIME
stdCall _RtlRaiseStatus, <STATUS_INTEGER_DIVIDE_BY_ZERO>
ENDIF
pop ebx
pop edi
pop esi
stdRET _RtlExtendedLargeIntegerDivide
stdENDP _RtlExtendedLargeIntegerDivide
page
subttl "Extended Magic Divide"
;++
;
; LARGE_INTEGER
; RtlExtendedMagicDivide (
; IN LARGE_INTEGER Dividend,
; IN LARGE_INTEGER MagicDivisor,
; IN CCHAR ShiftCount
; )
;
; Routine Description:
;
; This function divides a signed large integer by an unsigned large integer
; and returns the signed large integer result. The division is performed
; using reciprocal multiplication of a signed large integer value by an
; unsigned large integer fraction which represents the most significant
; 64-bits of the reciprocal divisor rounded up in its least significant bit
; and normalized with respect to bit 63. A shift count is also provided
; which is used to truncate the fractional bits from the result value.
;
; Arguments:
;
; (ebp+8) = Dividend
; (ebp+16) = MagicDivisor value is a 64-bit multiplicative reciprocal
; (ebp+24) = ShiftCount - Right shift adjustment value.
;
; Return Value:
;
; The large integer result is stored in (edx:eax)
;
;--
RemdDiv equ [ebp+8] ; Dividend
RemdRec equ [ebp+16] ; Reciprocal (magic divisor)
RemdShift equ [ebp+24]
RemdTmp1 equ [ebp-4]
RemdTmp2 equ [ebp-8]
RemdTmp3 equ [ebp-12]
cPublicProc _RtlExtendedMagicDivide ,5
push ebp
mov ebp,esp
sub esp,12
push esi
mov esi, RemdDiv+4
test esi,80000000h
jz remd10 ; no sign, no need to negate
neg dword ptr RemdDiv+4
neg dword ptr RemdDiv
sbb dword ptr RemdDiv+4,0 ; negate
remd10: mov eax,RemdRec
mul dword ptr RemdDiv ; (edx:eax) = Div.lo * Rec.lo
mov RemdTmp1,edx
mov eax,RemdRec
mul dword ptr RemdDiv+4 ; (edx:eax) = Div.hi * Rec.lo
mov RemdTmp2,eax
mov RemdTmp3,edx
mov eax,RemdRec+4
mul dword ptr RemdDiv ; (edx:eax) = Div.lo * Rec.hi
;
; Col 0 doesn't matter
; Col 1 = Hi(Div.lo * Rec.lo) + Low(Div.Hi * Rec.lo) + Low(Div.lo * Rec.hi)
; = RemdTmp1 + RemdTmp2 + eax
; -> Only want carry from Col 1
;
xor ecx,ecx ; (ecx) = 0
add eax,RemdTmp1
adc ecx, 0 ; save carry in ecx
add eax,RemdTmp2
adc ecx, 0 ; Save Carry, all we want from Col2
mov RemdTmp1,edx
mov eax,RemdRec+4
mul dword ptr RemdDiv+4 ; (edx:eax) = Div.Hi * Rec.Hi
;
; TOS = carry flag from Col 1
;
; Col 2 = Col1 CF +
; Hi(Div.Hi * Rec.Lo) + Hi(Div.Lo * Rec.Hi) + Low(Div.Hi * Rec.Hi)
; = CF + RemdTmp3 + RemdTmp1 + eax
;
; Col 3 = Col2 CF + Hi(Div.Hi * Rec.Hi)
; = CF + edx
;
add eax,RemdTmp1
adc edx, 0 ; add carry to edx
add eax,RemdTmp3 ; (eax) = col 2
adc edx, 0 ; add carry to edx
add eax, ecx
adc edx, 0 ; (edx) = col 3
;
; (edx:eax) = the high 64 bits of the multiply, shift it right by
; shift count to discard bits to right of virtual decimal pt.
;
; RemdShift could be as large as 63 and still not 0 the result, 386
; will only shift 31 bits at a time, so must do the sift multiple
; times to get correct effect.
;
mov cl,RemdShift
remd20: cmp cl,31
jbe remd30
sub cl,31
shrd eax,edx,31
shr edx,31
jmp remd20
remd30: shrd eax,edx,cl
shr edx,cl
;
; Negate the result if need be
;
test esi,80000000h
jz remd40 ; no sign, go return without negate
neg edx
neg eax
sbb edx,0
;
; Store the result
;
remd40:
; results in (edx:eax)
pop esi
mov esp,ebp
pop ebp
stdRET _RtlExtendedMagicDivide
stdENDP _RtlExtendedMagicDivide
page
subttl "Extended Integer Multiply"
;++
;
; LARGE_INTEGER
; RtlExtendedIntegerMultiply (
; IN LARGE_INTEGER Multiplicand,
; IN ULONG Multiplier
; )
;
; Routine Description:
;
; This function multiplies a signed large integer by a signed integer and
; returns the signed large integer result.
;
; Arguments:
;
; (ebp+8,12)=multiplican (MCAN)
; (ebp+16)=multiplier (MPER)
;
; Return Value:
;
; The large integer result is stored in (edx:eax)
;
;--
ReimMCAN equ <dword ptr [ebp+8]>
ReimMPER equ <dword ptr [ebp+16]>
cPublicProc _RtlExtendedIntegerMultiply ,3
push ebp
mov ebp,esp
push esi
mov esi,ReimMPER
xor esi,ReimMCAN+4 ; (esi) = result sign
test ReimMCAN+4,80000000h
jz short reim10 ; MCAN pos, go look at MPER
neg dword ptr ReimMCAN+4
neg dword ptr ReimMCAN
sbb dword ptr ReimMCAN+4,0 ; negate multiplican
reim10: test ReimMPER,80000000h
jz short reim20 ; MPER pos, go do multiply
neg dword ptr ReimMPER ; negate multiplier
reim20: mov eax,ReimMPER
mul dword ptr ReimMCAN ; (edx:eax) = MPER * MCAN.low
push edx
mov ecx, eax
mov eax,ReimMPER
mul dword ptr ReimMCAN+4 ; (edx:eax) = MPER * MCAN.high
add eax,[esp] ; (eax) = hi part of MPER*MCAN.low
; plus low part of MPER*MCAN.hi
test esi,80000000h
jz short reim30 ; result sign is OK, go return
neg eax
neg ecx
sbb eax,0 ; negate result
reim30: add esp,4 ; clean eax off stack
pop esi ; restore nonvolatile reg
mov edx,eax ; (edx:ecx) = result
mov eax,ecx ; (edx:eax) = result
pop ebp
stdRET _RtlExtendedIntegerMultiply
stdENDP _RtlExtendedIntegerMultiply
page
subttl "Large Integer Shift Left"
;++
;
; LARGE_INTEGER
; RtlLargeIntegerShiftLeft (
; IN LARGE_INTEGER LargeInteger,
; IN CCHAR ShiftCount
; )
;
;
; Routine Description:
;
; This routine does a left logical shift of a large integer by a
; specified amount (ShiftCount) modulo 64.
;
; Arguments:
;
; LargeInteger - Supplies the large integer to be shifted
;
; ShiftCount - Supplies the left shift count
;
; Return Value:
;
; LARGE_INTEGER - Receives the shift large integer result
;
;--
cPublicProc _RtlLargeIntegerShiftLeft,3
cPublicFpo 3,0
mov ecx, [esp+12] ; (ecx) = ShiftCount
and ecx, 3fh ; mod 64
cmp ecx, 32
jnc short sl10
;
; Shift count is less then 32 bits.
;
mov eax, [esp+4] ; (eax) = LargeInteger.LowPart
mov edx, [esp+8] ; (edx) = LargeInteger.HighPart
shld edx, eax, cl
shl eax, cl
stdRET _RtlLargeIntegerShiftLeft
align 4
sl10:
;
; Shift count is greater than or equal 32 bits - low half of result is zero,
; high half is the low half shifted left by remaining count.
;
mov edx, [esp+4] ; (edx) = LargeInteger.LowPart
xor eax, eax ; store lowpart
shl edx, cl ; store highpart
stdRET _RtlLargeIntegerShiftLeft
stdENDP _RtlLargeIntegerShiftLeft
page
subttl "Large Integer Shift Right"
;--
;
;LARGE_INTEGER
;RtlLargeIntegerShiftRight (
; IN LARGE_INTEGER LargeInteger,
; IN CCHAR ShiftCount
; )
;
;Routine Description:
;
; This routine does a right logical shift of a large integer by a
; specified amount (ShiftCount) modulo 64.
;
;Arguments:
;
; LargeInteger - Supplies the large integer to be shifted
;
; ShiftCount - Supplies the right shift count
;
;Return Value:
;
; LARGE_INTEGER - Receives the shift large integer result
;
;--*/
cPublicProc _RtlLargeIntegerShiftRight,3
cPublicFpo 3,0
mov ecx, [esp+12] ; (ecx) = ShiftCount
and ecx, 3fh ; mod 64
cmp ecx, 32
jnc short sr10
;
; Shift count is less then 32 bits.
;
mov eax, [esp+4] ; (eax) = LargeInteger.LowPart
mov edx, [esp+8] ; (edx) = LargeInteger.HighPart
shrd eax, edx, cl
shr edx, cl
stdRET _RtlLargeIntegerShiftRight
align 4
sr10:
;
; Shift count is greater than or equal 32 bits - high half of result is zero,
; low half is the high half shifted right by remaining count.
;
mov eax, [esp+8] ; (eax) = LargeInteger.HighPart
xor edx, edx ; store highpart
shr eax, cl ; store lowpart
stdRET _RtlLargeIntegerShiftRight
stdENDP _RtlLargeIntegerShiftRight
;++
;
;LARGE_INTEGER
;RtlLargeIntegerArithmeticShift (
; IN LARGE_INTEGER LargeInteger,
; IN CCHAR ShiftCount
; )
;
;Routine Description:
;
; This routine does a right arithmetic shift of a large integer by a
; specified amount (ShiftCount) modulo 64.
;
;Arguments:
;
; LargeInteger - Supplies the large integer to be shifted
;
; ShiftCount - Supplies the right shift count
;
;Return Value:
;
; LARGE_INTEGER - Receives the shift large integer result
;
;--
cPublicProc _RtlLargeIntegerArithmeticShift,3
cPublicFpo 3,0
mov ecx, [esp+12] ; (ecx) = ShiftCount
and ecx, 3fh ; mod 64
cmp ecx, 32
jc short sar10
;
; Shift count is greater than or equal 32 bits - high half of result is sign
; bit, low half is the high half shifted right by remaining count.
;
mov eax, [esp+8] ; (eax) = LargeInteger.HighPart
sar eax, cl ; store highpart
bt eax, 31 ; sign bit set?
sbb edx, edx ; duplicate sign bit into highpart
stdRET _RtlLargeIntegerArithmeticShift
align 4
sar10:
;
; Shift count is less then 32 bits.
;
;
mov eax, [esp+4] ; (eax) = LargeInteger.LowPart
mov edx, [esp+8] ; (edx) = LargeInteger.HighPart
shrd eax, edx, cl
sar edx, cl
stdRET _RtlLargeIntegerArithmeticShift
stdENDP _RtlLargeIntegerArithmeticShift,3
page
subttl "Large Integer Negate"
;++
;
; LARGE_INTEGER
; RtlLargeIntegerNegate (
; IN LARGE_INTEGER Subtrahend
; )
;
; Routine Description:
;
; This function negates a signed large integer and returns the signed
; large integer result.
;
; Arguments:
;
; (TOS+4) = Subtrahend
;
; Return Value:
;
; The large integer result is stored in (edx:eax)
;
;--
cPublicProc _RtlLargeIntegerNegate ,2
cPublicFpo 2,0
mov eax,[esp]+4 ; (eax) = lo
mov edx,[esp]+8
neg edx ; (edx) = 2's comp of hi part
neg eax ; if ((eax) == 0) CF = 0
; else CF = 1
sbb edx,0 ; (edx) = (edx) - CF
; (edx:eax) = result
stdRET _RtlLargeIntegerNegate
stdENDP _RtlLargeIntegerNegate
page
subttl "Large Integer Subtract"
;++
;
; LARGE_INTEGER
; RtlLargeIntegerSubtract (
; IN LARGE_INTEGER Minuend,
; IN LARGE_INTEGER Subtrahend
; )
;
; Routine Description:
;
; This function subtracts a signed large integer from a signed large
; integer and returns the signed large integer result.
;
; Arguments:
;
; (TOS+4) = Minuend
; (TOS+12) = Subtrahend
;
; Return Value:
;
; The large integer result is stored in (edx:eax)
;
;--
cPublicProc _RtlLargeIntegerSubtract ,4
cPublicFpo 4,0
mov eax,[esp]+4
sub eax,[esp]+12 ; (eax) = result.low
mov edx,[esp]+8
sbb edx,[esp]+16 ; (edx) = result.high
stdRET _RtlLargeIntegerSubtract
stdENDP _RtlLargeIntegerSubtract
page
subttl "Convert Long to Large Integer"
;++
;
; LARGE_INTEGER
; RtlConvertLongToLargeInteger (
; IN LONG SignedInteger
; )
;
; Routine Description:
;
; This function converts the input signed integer to a signed large
; integer and returns the latter as the result.
;
; Arguments:
;
; (TOS+4) = SignedInteger
;
; Return Value:
;
; The large integer result is stored (edx:eax)
;
;--
cPublicProc ___RtlConvertLongToLargeInteger ,1
cPublicFpo 1,0
mov eax,[esp]+4 ; (eax) = SignedInteger
cdq ; (edx:eax) = signed LargeInt
stdRET ___RtlConvertLongToLargeInteger
stdENDP ___RtlConvertLongToLargeInteger
page
subttl "Convert Ulong to Large Integer"
;++
;
; LARGE_INTEGER
; RtlConvertUlongToLargeInteger (
; IN LONG UnsignedInteger
; )
;
; Routine Description:
;
; This function converts the input unsigned integer to a signed large
; integer and returns the latter as the result.
;
; Arguments:
;
; (TOS+4) = UnsignedInteger
;
; Return Value:
;
; The large integer result is stored in (edx:eax)
;
;--
cPublicProc ___RtlConvertUlongToLargeInteger ,1
cPublicFpo 1,0
mov eax,[esp]+4 ; store low
xor edx,edx ; store 0 in high
stdRET ___RtlConvertUlongToLargeInteger
stdENDP ___RtlConvertUlongToLargeInteger
_TEXT$00 ends
end
| 25.33528 | 83 | 0.554341 |
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