bluelightai-dev/the-stack-dedup-sample · Datasets at Hugging Face

9ead4388f37cb24677ce472a86e5ee90e83d9377

3,616

h

C

src/Watcher.h

jheleniak/btcpool

28ad61f60d529c203db2b58379d851ba20697eae

[ "MIT" ]

null

src/Watcher.h

jheleniak/btcpool

28ad61f60d529c203db2b58379d851ba20697eae

[ "MIT" ]

null

src/Watcher.h

jheleniak/btcpool

28ad61f60d529c203db2b58379d851ba20697eae

[ "MIT" ]

5

2019-10-14T06:57:57.000Z

2020-10-11T20:36:28.000Z

/* The MIT License (MIT) Copyright (c) [2016] [BTC.COM] Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef POOL_WATCHER_H_ #define POOL_WATCHER_H_ #include "Common.h" #include "Kafka.h" #include "Utils.h" #include <event2/event.h> #include <event2/buffer.h> #include <event2/bufferevent.h> #include <event2/listener.h> #include <event2/bufferevent_ssl.h> #include <event2/dns.h> #include <libconfig.h++> #include <bitset> #include <map> #include <set> #include <memory> #include <boost/thread/shared_mutex.hpp> // see PoolWatcherAgent in StratumSession.cc #define BTCCOM_WATCHER_AGENT "__PoolWatcher__" class PoolWatchClient; class ClientContainer; ///////////////////////////////// ClientContainer ////////////////////////////// class ClientContainer { protected: atomic<bool> running_; vector<shared_ptr<PoolWatchClient>> clients_; // libevent2 struct event_base *base_; string kafkaBrokers_; KafkaProducer kafkaProducer_; // produce GBT message IdGenerator gen_; virtual PoolWatchClient * createPoolWatchClient(const libconfig::Setting &config) = 0; virtual bool initInternal() = 0; public: ClientContainer(const libconfig::Config &config); virtual ~ClientContainer(); bool addPools(const libconfig::Setting &config); bool init(); void run(); void stop(); void removeAndCreateClient(PoolWatchClient *client); uint64_t generateJobId() { return gen_.next(); } }; ///////////////////////////////// PoolWatchClient ////////////////////////////// class PoolWatchClient { protected: bool enableTLS_; struct evdns_base *evdnsBase_; struct event *reconnectEvent_; struct bufferevent *bev_; bool handleMessage(); virtual void handleStratumMessage(const string &line) = 0; public: enum State { INIT = 0, CONNECTED = 1, SUBSCRIBED = 2, AUTHENTICATED = 3 }; State state_; ClientContainer *container_; const libconfig::Setting &config_; string poolName_; string poolHost_; uint16_t poolPort_; string workerName_; time_t upTime_; protected: PoolWatchClient( struct event_base *base, ClientContainer *container, const libconfig::Setting &config); public: virtual ~PoolWatchClient(); bool connect(); virtual void onConnected() = 0; void recvData(); void sendData(const char *data, size_t len); inline void sendData(const string &str) { sendData(str.data(), str.size()); } static void readCallback(struct bufferevent *bev, void *ptr); static void eventCallback(struct bufferevent *bev, short events, void *ptr); static void reconnectCallback(evutil_socket_t fd, short events, void *ptr); }; #endif

28.031008

80

0.7276

fa1178a36e9bf0ac5b3691e002d4cf90e2bfd683

4,410

c

C

BBB-firmware/u-boot-v2018.05-rc2/drivers/rtc/isl1208.c

guileschool/BEAGLEBONE-tutorials

eecd83e0c14941b05ad38eeb77e5a50602cc29ca

[ "MIT" ]

4

2018-09-28T04:33:26.000Z

2021-03-10T06:29:55.000Z

BBB-firmware/u-boot-v2018.05-rc2/drivers/rtc/isl1208.c

guileschool/BEAGLEBONE-tutorials

eecd83e0c14941b05ad38eeb77e5a50602cc29ca

[ "MIT" ]

4

2016-08-30T11:30:25.000Z

2020-12-27T09:58:07.000Z

BBB-firmware/u-boot-v2018.05-rc2/drivers/rtc/isl1208.c

guileschool/BEAGLEBONE-tutorials

eecd83e0c14941b05ad38eeb77e5a50602cc29ca

[ "MIT" ]

2

2016-12-30T08:02:57.000Z

2020-05-16T05:59:30.000Z

/* * (C) Copyright 2008 * Tor Krill, Excito Elektronik i Skåne , tor@excito.com * * Modelled after the ds1337 driver * * SPDX-License-Identifier: GPL-2.0+ */ /* * Date & Time support (no alarms) for Intersil * ISL1208 Real Time Clock (RTC). */ #include <common.h> #include <command.h> #include <dm.h> #include <rtc.h> #include <i2c.h> /*---------------------------------------------------------------------*/ #ifdef DEBUG_RTC #define DEBUGR(fmt,args...) printf(fmt ,##args) #else #define DEBUGR(fmt,args...) #endif /*---------------------------------------------------------------------*/ /* * RTC register addresses */ #define RTC_SEC_REG_ADDR 0x0 #define RTC_MIN_REG_ADDR 0x1 #define RTC_HR_REG_ADDR 0x2 #define RTC_DATE_REG_ADDR 0x3 #define RTC_MON_REG_ADDR 0x4 #define RTC_YR_REG_ADDR 0x5 #define RTC_DAY_REG_ADDR 0x6 #define RTC_STAT_REG_ADDR 0x7 /* * RTC control register bits */ /* * RTC status register bits */ #define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */ #define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */ #define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */ #define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */ #define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */ #define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */ /* * Get the current time from the RTC */ static int isl1208_rtc_get(struct udevice *dev, struct rtc_time *tmp) { int ret; uchar buf[8], val; ret = dm_i2c_read(dev, 0, buf, sizeof(buf)); if (ret < 0) return ret; if (buf[RTC_STAT_REG_ADDR] & RTC_STAT_BIT_RTCF) { printf ("### Warning: RTC oscillator has stopped\n"); ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val)); if (ret < 0) return ret; val = val & ~(RTC_STAT_BIT_BAT | RTC_STAT_BIT_RTCF); ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val)); if (ret < 0) return ret; } tmp->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F); tmp->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F); tmp->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F); tmp->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F); tmp->tm_mon = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F); tmp->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) + 2000; tmp->tm_wday = bcd2bin(buf[RTC_DAY_REG_ADDR] & 0x07); tmp->tm_yday = 0; tmp->tm_isdst= 0; DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); return 0; } /* * Set the RTC */ static int isl1208_rtc_set(struct udevice *dev, const struct rtc_time *tmp) { int ret; uchar val, buf[7]; DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); if (tmp->tm_year < 2000 || tmp->tm_year > 2099) printf("WARNING: year should be between 2000 and 2099!\n"); /* enable write */ ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val)); if (ret < 0) return ret; val = val | RTC_STAT_BIT_WRTC; ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val)); if (ret < 0) return ret; buf[RTC_YR_REG_ADDR] = bin2bcd(tmp->tm_year % 100); buf[RTC_MON_REG_ADDR] = bin2bcd(tmp->tm_mon); buf[RTC_DAY_REG_ADDR] = bin2bcd(tmp->tm_wday); buf[RTC_DATE_REG_ADDR] = bin2bcd(tmp->tm_mday); buf[RTC_HR_REG_ADDR] = bin2bcd(tmp->tm_hour) | 0x80; /* 24h clock */ buf[RTC_MIN_REG_ADDR] = bin2bcd(tmp->tm_min); buf[RTC_SEC_REG_ADDR] = bin2bcd(tmp->tm_sec); ret = dm_i2c_write(dev, 0, buf, sizeof(buf)); if (ret < 0) return ret; /* disable write */ ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val)); if (ret < 0) return ret; val = val & ~RTC_STAT_BIT_WRTC; ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val)); if (ret < 0) return ret; return 0; } static int isl1208_rtc_reset(struct udevice *dev) { return 0; } static int isl1208_probe(struct udevice *dev) { i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS); return 0; } static const struct rtc_ops isl1208_rtc_ops = { .get = isl1208_rtc_get, .set = isl1208_rtc_set, .reset = isl1208_rtc_reset, }; static const struct udevice_id isl1208_rtc_ids[] = { { .compatible = "isil,isl1208" }, { } }; U_BOOT_DRIVER(rtc_isl1208) = { .name = "rtc-isl1208", .id = UCLASS_RTC, .probe = isl1208_probe, .of_match = isl1208_rtc_ids, .ops = &isl1208_rtc_ops, };

24.636872

75

0.669161

cfcf6ab099421952ccf5a52fca4823073d64eea1

228

h

C

URJapan/Controller/MainPage/URMainPageViewController.h

superweiyan/URJapan

93a1754354990b51ed7800e68cf24d5acedecd3d

[ "MIT" ]

null

URJapan/Controller/MainPage/URMainPageViewController.h

superweiyan/URJapan

93a1754354990b51ed7800e68cf24d5acedecd3d

[ "MIT" ]

null

URJapan/Controller/MainPage/URMainPageViewController.h

superweiyan/URJapan

93a1754354990b51ed7800e68cf24d5acedecd3d

[ "MIT" ]

null

// // URMainPageViewController.h // URJapan // // Created by lin weiyan on 18/12/2017. // Copyright © 2017 URWY. All rights reserved. // #import <UIKit/UIKit.h> @interface URMainPageViewController : UIViewController @end

16.285714

54

0.714912

cfff888f9d55c163c246e0f0db8b24155eca089f

72,538

c

C

usr.bin/dsynth/build.c

raJeev-M/DragonFlyBSD

2f9f168a13010344973c10c56a71514a10643642

[ "BSD-3-Clause" ]

1

2019-12-22T07:21:10.000Z

usr.bin/dsynth/build.c

raJeev-M/DragonFlyBSD

2f9f168a13010344973c10c56a71514a10643642

[ "BSD-3-Clause" ]

null

usr.bin/dsynth/build.c

raJeev-M/DragonFlyBSD

2f9f168a13010344973c10c56a71514a10643642

[ "BSD-3-Clause" ]

null

/* * Copyright (c) 2019 The DragonFly Project. All rights reserved. * * This code is derived from software contributed to The DragonFly Project * by Matthew Dillon <dillon@backplane.com> * * This code uses concepts and configuration based on 'synth', by * John R. Marino <draco@marino.st>, which was written in ada. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "dsynth.h" worker_t WorkerAry[MAXWORKERS]; int BuildInitialized; int RunningWorkers; int DynamicMaxWorkers; int FailedWorkers; long RunningPkgDepSize; pthread_mutex_t WorkerMutex; pthread_cond_t WorkerCond; static int build_find_leaves(pkg_t *parent, pkg_t *pkg, pkg_t ***build_tailp, int *app, int *hasworkp, int depth, int first, int first_one_only); static int buildCalculateDepiDepth(pkg_t *pkg); static void build_clear_trav(pkg_t *pkg); static void startbuild(pkg_t **build_listp, pkg_t ***build_tailp); static int qsort_depi(const void *pkg1, const void *pkg2); static int qsort_idep(const void *pkg1, const void *pkg2); static void startworker(pkg_t *pkg, worker_t *work); static void cleanworker(worker_t *work); static void waitbuild(int whilematch, int dynamicmax); static void workercomplete(worker_t *work); static void *childBuilderThread(void *arg); static int childInstallPkgDeps(worker_t *work); static size_t childInstallPkgDeps_recurse(FILE *fp, pkglink_t *list, int undoit, int depth, int first_one_only); static void dophase(worker_t *work, wmsg_t *wmsg, int wdog, int phaseid, const char *phase); static void phaseReapAll(void); static void phaseTerminateSignal(int sig); static char *buildskipreason(pkglink_t *parent, pkg_t *pkg); static int buildskipcount_dueto(pkg_t *pkg, int mode); static int mptylogpoll(int ptyfd, int fdlog, wmsg_t *wmsg, time_t *wdog_timep); static int copyfile(char *src, char *dst); static void doHook(pkg_t *pkg, const char *id, const char *path, int waitfor); static void childHookRun(bulk_t *bulk); static worker_t *SigWork; static int MasterPtyFd = -1; static int CopyFileFd = -1; static pid_t SigPid; static const char *WorkerFlavorPrt = ""; /* "" or "@flavor" */ #define MPTY_FAILED -2 #define MPTY_AGAIN -1 #define MPTY_EOF 0 #define MPTY_DATA 1 int BuildTotal; int BuildCount; int BuildSkipCount; int BuildIgnoreCount; int BuildFailCount; int BuildSuccessCount; /* * Initialize the WorkerAry[] */ void DoInitBuild(int slot_override) { worker_t *work; struct stat st; int i; ddassert(slot_override < 0 || MaxWorkers == 1); bzero(WorkerAry, MaxWorkers * sizeof(worker_t)); pthread_mutex_init(&WorkerMutex, NULL); for (i = 0; i < MaxWorkers; ++i) { work = &WorkerAry[i]; work->index = (slot_override >= 0) ? slot_override : i; work->state = WORKER_NONE; asprintf(&work->basedir, "%s/SL%02d", BuildBase, work->index); pthread_cond_init(&work->cond, NULL); } BuildCount = 0; /* * Create required sub-directories. The base directories must already * exist as a dsynth configuration safety. */ if (stat(RepositoryPath, &st) < 0) { if (mkdir(RepositoryPath, 0755) < 0) dfatal("Cannot mkdir %s\n", RepositoryPath); } BuildInitialized = 1; /* * slow-start (increases at a rate of 1 per 5 seconds) */ if (SlowStartOpt > MaxWorkers) DynamicMaxWorkers = MaxWorkers; else if (SlowStartOpt > 0) DynamicMaxWorkers = SlowStartOpt; else DynamicMaxWorkers = MaxWorkers; } /* * Called by the frontend to clean-up any hanging mounts. */ void DoCleanBuild(int resetlogs) { int i; ddassert(BuildInitialized); if (resetlogs) dlogreset(); for (i = 0; i < MaxWorkers; ++i) { DoWorkerUnmounts(&WorkerAry[i]); } } void DoBuild(pkg_t *pkgs) { pkg_t *build_list = NULL; pkg_t **build_tail = &build_list; pkg_t *scan; bulk_t *bulk; int haswork = 1; int first = 1; int newtemplate; time_t startTime; time_t t; int h, m, s; /* * We use our bulk system to run hooks. This will be for * Skipped and Ignored. Success and Failure are handled by * WorkerProcess() which is a separately-exec'd dsynth. */ if (UsingHooks) initbulk(childHookRun, MaxBulk); /* * Count up the packages, not counting dummies */ for (scan = pkgs; scan; scan = scan->bnext) { if ((scan->flags & PKGF_DUMMY) == 0) ++BuildTotal; } doHook(NULL, "hook_run_start", HookRunStart, 1); /* * The pkg and pkg-static binaries are needed. If already present * then assume that the template is also valid, otherwise build * both. */ scan = GetPkgPkg(pkgs); /* * Create our template. The template will be missing pkg * and pkg-static. */ if ((scan->flags & (PKGF_SUCCESS | PKGF_PACKAGED)) == 0) { /* force a fresh template */ newtemplate = DoCreateTemplate(1); } else { newtemplate = DoCreateTemplate(0); } /* * This will clear the screen and set-up our gui, so sleep * a little first in case the user wants to see what was * printed before. */ sleep(2); pthread_mutex_lock(&WorkerMutex); startTime = time(NULL); RunStatsInit(); RunStatsReset(); /* * Build pkg/pkg-static. */ if ((scan->flags & (PKGF_SUCCESS | PKGF_PACKAGED)) == 0) { build_list = scan; build_tail = &scan->build_next; startbuild(&build_list, &build_tail); while (RunningWorkers == 1) waitbuild(1, 0); if (scan->flags & PKGF_NOBUILD) dfatal("Unable to build 'pkg'"); if (scan->flags & PKGF_ERROR) dfatal("Error building 'pkg'"); if ((scan->flags & PKGF_SUCCESS) == 0) dfatal("Error building 'pkg'"); newtemplate = 1; } /* * Install pkg/pkg-static into the template */ if (newtemplate) { char *buf; int rc; asprintf(&buf, "cd %s/Template; " "tar --exclude '+*' --exclude '*/man/*' " "-xvzpf %s/%s > /dev/null 2>&1", BuildBase, RepositoryPath, scan->pkgfile); rc = system(buf); if (rc) dfatal("Command failed: %s\n", buf); freestrp(&buf); } /* * Calculate depi_depth, the longest chain of dependencies * for who depends on me, weighted by powers of two. */ for (scan = pkgs; scan; scan = scan->bnext) { buildCalculateDepiDepth(scan); } /* * Nominal bulk build sequence */ while (haswork) { haswork = 0; fflush(stdout); for (scan = pkgs; scan; scan = scan->bnext) { ddprintf(0, "SCANLEAVES %08x %s\n", scan->flags, scan->portdir); scan->flags |= PKGF_BUILDLOOP; /* * NOTE: We must still find dependencies if PACKAGED * to fill in the gaps, as some of them may * need to be rebuilt. */ if (scan->flags & (PKGF_SUCCESS | PKGF_FAILURE | PKGF_ERROR)) { #if 0 ddprintf(0, "%s: already built\n", scan->portdir); #endif } else { int ap = 0; build_find_leaves(NULL, scan, &build_tail, &ap, &haswork, 0, first, 0); ddprintf(0, "TOPLEVEL %s %08x\n", scan->portdir, ap); } scan->flags &= ~PKGF_BUILDLOOP; build_clear_trav(scan); } first = 0; fflush(stdout); startbuild(&build_list, &build_tail); if (haswork == 0 && RunningWorkers) { waitbuild(RunningWorkers, 1); haswork = 1; } } pthread_mutex_unlock(&WorkerMutex); RunStatsUpdateTop(); RunStatsUpdateLogs(); RunStatsSync(); RunStatsDone(); doHook(NULL, "hook_run_end", HookRunEnd, 1); if (UsingHooks) { while ((bulk = getbulk()) != NULL) freebulk(bulk); donebulk(); } t = time(NULL) - startTime; h = t / 3600; m = t / 60 % 60; s = t % 60; dlog(DLOG_ALL|DLOG_STDOUT, "\n" "Initial queue size: %d\n" " packages built: %d\n" " ignored: %d\n" " skipped: %d\n" " failed: %d\n" "\n" "Duration: %02d:%02d:%02d\n" "\n", BuildTotal, BuildSuccessCount, BuildIgnoreCount, BuildSkipCount, BuildFailCount, h, m, s); } /* * Traverse the packages (pkg) depends on recursively until we find * a leaf to build or report as unbuildable. Calculates and assigns a * dependency count. Returns all parallel-buildable packages. * * (pkg) itself is only added to the list if it is immediately buildable. */ static int build_find_leaves(pkg_t *parent, pkg_t *pkg, pkg_t ***build_tailp, int *app, int *hasworkp, int depth, int first, int first_one_only) { pkglink_t *link; pkg_t *scan; int idep_count = 0; int apsub; int dfirst_one_only; int ndepth; char *buf; ndepth = depth + 1; /* * Already on build list, possibly in-progress, tell caller that * it is not ready. */ ddprintf(ndepth, "sbuild_find_leaves %d %s %08x {\n", depth, pkg->portdir, pkg->flags); if (pkg->flags & PKGF_BUILDLIST) { ddprintf(ndepth, "} (already on build list)\n"); *app |= PKGF_NOTREADY; return (pkg->idep_count); } /* * Check dependencies */ PKGLIST_FOREACH(link, &pkg->idepon_list) { scan = link->pkg; if (scan == NULL) { if (first_one_only) break; continue; } ddprintf(ndepth, "check %s %08x\t", scan->portdir, scan->flags); /* * If this dependency is to a DUMMY node it is a dependency * only on the default flavor which is only the first node * under this one, not all of them. * * NOTE: The depth is not being for complex dependency type * tests like it is in childInstallPkgDeps_recurse(), * so we don't have to hicup it like we do in that * procedure. */ dfirst_one_only = (scan->flags & PKGF_DUMMY) ? 1 : 0; /* * When accounting for a successful build, just bump * idep_count by one. scan->idep_count will heavily * overlap packages that we count down multiple branches. * * We must still recurse through PACKAGED packages as * some of their dependencies might be missing. */ if (scan->flags & PKGF_SUCCESS) { ddprintf(0, "SUCCESS - OK\n"); ++idep_count; if (first_one_only) break; continue; } /* * ERROR includes FAILURE, which is set in numerous situations * including when NOBUILD state is processed. So check for * NOBUILD state first. * * An ERROR in a sub-package causes a NOBUILD in packages * that depend on it. */ if (scan->flags & PKGF_NOBUILD) { ddprintf(0, "NOBUILD - OK " "(propagate failure upward)\n"); *app |= PKGF_NOBUILD_S; if (first_one_only) break; continue; } if (scan->flags & PKGF_ERROR) { ddprintf(0, "ERROR - OK (propagate failure upward)\n"); *app |= PKGF_NOBUILD_S; if (first_one_only) break; continue; } /* * If already on build-list this dependency is not ready. */ if (scan->flags & PKGF_BUILDLIST) { ddprintf(0, " [BUILDLIST]"); *app |= PKGF_NOTREADY; } /* * If not packaged this dependency is not ready for * the caller. */ if ((scan->flags & PKGF_PACKAGED) == 0) { ddprintf(0, " [NOT_PACKAGED]"); *app |= PKGF_NOTREADY; } /* * Reduce search complexity, if we have already processed * scan in the traversal it will either already be on the * build list or it will not be buildable. Either way * the parent is not buildable. */ if (scan->flags & PKGF_BUILDTRAV) { ddprintf(0, " [BUILDTRAV]\n"); *app |= PKGF_NOTREADY; if (first_one_only) break; continue; } /* * Assert on dependency loop */ ++idep_count; if (scan->flags & PKGF_BUILDLOOP) { dfatal("pkg dependency loop %s -> %s", parent->portdir, scan->portdir); } /* * NOTE: For debug tabbing purposes we use (ndepth + 1) * here (i.e. depth + 2) in our iteration. */ scan->flags |= PKGF_BUILDLOOP; apsub = 0; ddprintf(0, " SUBRECURSION {\n"); idep_count += build_find_leaves(pkg, scan, build_tailp, &apsub, hasworkp, ndepth + 1, first, dfirst_one_only); scan->flags &= ~PKGF_BUILDLOOP; *app |= apsub; if (apsub & PKGF_NOBUILD) { ddprintf(ndepth, "} (sub-nobuild)\n"); } else if (apsub & PKGF_ERROR) { ddprintf(ndepth, "} (sub-error)\n"); } else if (apsub & PKGF_NOTREADY) { ddprintf(ndepth, "} (sub-notready)\n"); } else { ddprintf(ndepth, "} (sub-ok)\n"); } if (first_one_only) break; } pkg->idep_count = idep_count; pkg->flags |= PKGF_BUILDTRAV; /* * Incorporate scan results into pkg state. */ if ((pkg->flags & PKGF_NOBUILD) == 0 && (*app & PKGF_NOBUILD)) { *hasworkp = 1; } else if ((pkg->flags & PKGF_ERROR) == 0 && (*app & PKGF_ERROR)) { *hasworkp = 1; } pkg->flags |= *app & ~PKGF_NOTREADY; /* * Clear PACKAGED bit if sub-dependencies aren't clean */ if ((pkg->flags & PKGF_PACKAGED) && (pkg->flags & (PKGF_NOTREADY|PKGF_ERROR|PKGF_NOBUILD))) { pkg->flags &= ~PKGF_PACKAGED; ddassert(pkg->pkgfile); asprintf(&buf, "%s/%s", RepositoryPath, pkg->pkgfile); if (remove(buf) < 0) { dlog(DLOG_ALL, "[XXX] %s DELETE-PACKAGE %s (failed)\n", pkg->portdir, buf); } else { dlog(DLOG_ALL, "[XXX] %s DELETE-PACKAGE %s " "(due to dependencies)\n", pkg->portdir, buf); } freestrp(&buf); *hasworkp = 1; } /* * Set PKGF_NOBUILD_I if there is IGNORE data */ if (pkg->ignore) pkg->flags |= PKGF_NOBUILD_I; /* * Handle propagated flags */ if (pkg->flags & PKGF_ERROR) { /* * This can only happen if the ERROR has already been * processed and accounted for. */ ddprintf(depth, "} (ERROR - %s)\n", pkg->portdir); } else if (*app & PKGF_NOTREADY) { /* * We don't set PKGF_NOTREADY in the pkg, it is strictly * a transient flag propagated via build_find_leaves(). * * Just don't add the package to the list. * * NOTE: Even if NOBUILD is set (meaning we could list it * and let startbuild() finish it up as a skip, we * don't process it to the list because we want to * process all the dependencies, so someone doing a * manual build can get more complete information and * does not have to iterate each failed dependency one * at a time. */ ; } else if (pkg->flags & PKGF_SUCCESS) { ddprintf(depth, "} (SUCCESS - %s)\n", pkg->portdir); } else if (pkg->flags & PKGF_DUMMY) { /* * Just mark dummy packages as successful when all of their * sub-depends (flavors) complete successfully. Note that * dummy packages are not counted in the total, so do not * decrement BuildTotal. */ ddprintf(depth, "} (DUMMY/META - SUCCESS)\n"); pkg->flags |= PKGF_SUCCESS; *hasworkp = 1; if (first) { dlog(DLOG_ALL | DLOG_FILTER, "[XXX] %s META-ALREADY-BUILT\n", pkg->portdir); } else { dlog(DLOG_SUCC, "[XXX] %s meta-node complete\n", pkg->portdir); } } else if (pkg->flags & PKGF_PACKAGED) { /* * We can just mark the pkg successful. If this is * the first pass, we count this as an initial pruning * pass and reduce BuildTotal. */ ddprintf(depth, "} (PACKAGED - SUCCESS)\n"); pkg->flags |= PKGF_SUCCESS; *hasworkp = 1; if (first) { dlog(DLOG_ALL | DLOG_FILTER, "[XXX] %s ALREADY-BUILT\n", pkg->portdir); --BuildTotal; } } else { /* * All dependencies are successful, queue new work * and indicate not-ready to the parent (since our * package has to be built). * * NOTE: The NOBUILD case propagates to here as well * and is ultimately handled by startbuild(). */ *hasworkp = 1; if (pkg->flags & PKGF_NOBUILD_I) ddprintf(depth, "} (ADDLIST(IGNORE/BROKEN) - %s)\n", pkg->portdir); else if (pkg->flags & PKGF_NOBUILD) ddprintf(depth, "} (ADDLIST(NOBUILD) - %s)\n", pkg->portdir); else ddprintf(depth, "} (ADDLIST - %s)\n", pkg->portdir); pkg->flags |= PKGF_BUILDLIST; **build_tailp = pkg; *build_tailp = &pkg->build_next; *app |= PKGF_NOTREADY; } return idep_count; } static void build_clear_trav(pkg_t *pkg) { pkglink_t *link; pkg_t *scan; pkg->flags &= ~PKGF_BUILDTRAV; PKGLIST_FOREACH(link, &pkg->idepon_list) { scan = link->pkg; if (scan && (scan->flags & PKGF_BUILDTRAV)) build_clear_trav(scan); } } /* * Calculate the longest chain of packages that depend on me. The * long the chain, the more important my package is to build earlier * rather than later. */ static int buildCalculateDepiDepth(pkg_t *pkg) { pkglink_t *link; pkg_t *scan; int best_depth = 0; int res; if (pkg->depi_depth) return(pkg->depi_depth + 1); pkg->flags |= PKGF_BUILDLOOP; PKGLIST_FOREACH(link, &pkg->deponi_list) { scan = link->pkg; if (scan && (scan->flags & PKGF_BUILDLOOP) == 0) { res = buildCalculateDepiDepth(scan); if (best_depth < res) best_depth = res; } } pkg->flags &= ~PKGF_BUILDLOOP; pkg->depi_depth = best_depth; return (best_depth + 1); } /* * Take a list of pkg ready to go, sort it, and assign it to worker * slots. This routine blocks in waitbuild() until it can dispose of * the entire list. * * WorkerMutex is held by the caller. */ static void startbuild(pkg_t **build_listp, pkg_t ***build_tailp) { pkg_t *pkg; pkg_t **idep_ary; pkg_t **depi_ary; int count; int idep_index; int depi_index; int i; int n; worker_t *work; static int IterateWorker; /* * Nothing to do */ if (*build_listp == NULL) return; /* * Sort */ count = 0; for (pkg = *build_listp; pkg; pkg = pkg->build_next) ++count; idep_ary = calloc(count, sizeof(pkg_t *)); depi_ary = calloc(count, sizeof(pkg_t *)); count = 0; for (pkg = *build_listp; pkg; pkg = pkg->build_next) { idep_ary[count] = pkg; depi_ary[count] = pkg; ++count; } /* * idep_ary - sorted by #of dependencies this pkg has. * depi_ary - sorted by #of other packages that depend on this pkg. */ qsort(idep_ary, count, sizeof(pkg_t *), qsort_idep); qsort(depi_ary, count, sizeof(pkg_t *), qsort_depi); idep_index = 0; depi_index = 0; /* * Half the workers build based on the highest depi count, * the other half build based on the highest idep count. * * This is an attempt to get projects which many other projects * depend on built first, but to also try to build large projects * (which tend to have a lot of dependencies) earlier rather than * later so the end of the bulk run doesn't inefficiently build * the last few huge projects. * * Loop until we manage to assign slots to everyone. We do not * wait for build completion. * * This is the point where we handle DUMMY packages (these are * dummy unflavored packages which 'cover' all the flavors for * a package). These are not real packages are marked SUCCESS * at this time because their dependencies (the flavors) have all * been built. */ while (idep_index != count || depi_index != count) { pkg_t *pkgi; pkg_t *ipkg; /* * Find candidate to start sorted by depi or idep. */ ipkg = NULL; while (idep_index < count) { ipkg = idep_ary[idep_index]; if ((ipkg->flags & (PKGF_SUCCESS | PKGF_FAILURE | PKGF_ERROR | PKGF_RUNNING)) == 0) { break; } ipkg = NULL; ++idep_index; } pkgi = NULL; while (depi_index < count) { pkgi = depi_ary[depi_index]; if ((pkgi->flags & (PKGF_SUCCESS | PKGF_FAILURE | PKGF_ERROR | PKGF_RUNNING)) == 0) { break; } pkgi = NULL; ++depi_index; } /* * ipkg and pkgi must either both be NULL, or both * be non-NULL. */ if (ipkg == NULL && pkgi == NULL) break; ddassert(ipkg && pkgi); /* * Handle the NOBUILD case right here, there's no point * queueing it anywhere. */ if (ipkg->flags & PKGF_NOBUILD) { char *reason; ipkg->flags |= PKGF_FAILURE; ipkg->flags &= ~PKGF_BUILDLIST; reason = buildskipreason(NULL, ipkg); if (ipkg->flags & PKGF_NOBUILD_I) { ++BuildIgnoreCount; dlog(DLOG_IGN, "[XXX] %s ignored due to %s\n", ipkg->portdir, reason); doHook(ipkg, "hook_pkg_ignored", HookPkgIgnored, 0); } else { ++BuildSkipCount; dlog(DLOG_SKIP, "[XXX] %s skipped due to %s\n", ipkg->portdir, reason); doHook(ipkg, "hook_pkg_skipped", HookPkgSkipped, 0); } free(reason); ++BuildCount; continue; } if (pkgi->flags & PKGF_NOBUILD) { char *reason; pkgi->flags |= PKGF_FAILURE; pkgi->flags &= ~PKGF_BUILDLIST; reason = buildskipreason(NULL, pkgi); if (pkgi->flags & PKGF_NOBUILD_I) { ++BuildIgnoreCount; dlog(DLOG_IGN, "[XXX] %s ignored due to %s\n", pkgi->portdir, reason); doHook(pkgi, "hook_pkg_ignored", HookPkgIgnored, 0); } else { ++BuildSkipCount; dlog(DLOG_SKIP, "[XXX] %s skipped due to %s\n", pkgi->portdir, reason); doHook(pkgi, "hook_pkg_skipped", HookPkgSkipped, 0); } free(reason); ++BuildCount; continue; } /* * Block while no slots are available. waitbuild() * will clean out any DONE states. */ while (RunningWorkers >= DynamicMaxWorkers || RunningWorkers >= MaxWorkers - FailedWorkers) { waitbuild(RunningWorkers, 1); } /* * Find an available worker slot, there should be at * least one. */ for (i = 0; i < MaxWorkers; ++i) { n = IterateWorker % MaxWorkers; work = &WorkerAry[n]; if (work->state == WORKER_DONE || work->state == WORKER_FAILED) { workercomplete(work); } if (work->state == WORKER_NONE || work->state == WORKER_IDLE) { if (n <= MaxWorkers / 2) { startworker(pkgi, work); } else { startworker(ipkg, work); } /*RunStatsUpdate(work);*/ break; } ++IterateWorker; } ddassert(i != MaxWorkers); } RunStatsSync(); /* * We disposed of the whole list */ free(idep_ary); free(depi_ary); *build_listp = NULL; *build_tailp = build_listp; } typedef const pkg_t *pkg_tt; static int qsort_idep(const void *pkg1_arg, const void *pkg2_arg) { const pkg_t *pkg1 = *(const pkg_tt *)pkg1_arg; const pkg_t *pkg2 = *(const pkg_tt *)pkg2_arg; return (pkg2->idep_count - pkg1->idep_count); } static int qsort_depi(const void *pkg1_arg, const void *pkg2_arg) { const pkg_t *pkg1 = *(const pkg_tt *)pkg1_arg; const pkg_t *pkg2 = *(const pkg_tt *)pkg2_arg; return ((pkg2->depi_count * pkg2->depi_depth) - (pkg1->depi_count * pkg1->depi_depth)); } /* * Frontend starts a pkg up on a worker * * WorkerMutex must be held. */ static void startworker(pkg_t *pkg, worker_t *work) { switch(work->state) { case WORKER_NONE: pthread_create(&work->td, NULL, childBuilderThread, work); work->state = WORKER_IDLE; /* fall through */ case WORKER_IDLE: work->pkg_dep_size = childInstallPkgDeps_recurse(NULL, &pkg->idepon_list, 0, 1, 0); childInstallPkgDeps_recurse(NULL, &pkg->idepon_list, 1, 1, 0); RunningPkgDepSize += work->pkg_dep_size; dlog(DLOG_ALL, "[%03d] START %s " "##idep=%02d depi=%02d/%02d dep=%-4.2fG\n", work->index, pkg->portdir, pkg->idep_count, pkg->depi_count, pkg->depi_depth, (double)work->pkg_dep_size / (double)ONEGB); cleanworker(work); pkg->flags |= PKGF_RUNNING; work->pkg = pkg; pthread_cond_signal(&work->cond); ++RunningWorkers; /*RunStatsUpdate(work);*/ break; case WORKER_PENDING: case WORKER_RUNNING: case WORKER_DONE: case WORKER_FAILED: case WORKER_FROZEN: case WORKER_EXITING: default: dfatal("startworker: [%03d] Unexpected state %d for worker %d", work->index, work->state, work->index); break; } } static void cleanworker(worker_t *work) { work->state = WORKER_PENDING; work->flags = 0; work->accum_error = 0; work->start_time = time(NULL); } /* * Frontend finishes up a completed pkg on a worker. * * If the worker is in a FAILED state we clean the pkg out but (for now) * leave it in its failed state so we can debug. At this point * workercomplete() will be called every once in a while on the state * and we have to deal with the NULL pkg. * * WorkerMutex must be held. */ static void workercomplete(worker_t *work) { pkg_t *pkg; time_t t; int h; int m; int s; /* * Steady state FAILED case. */ if (work->state == WORKER_FAILED) { if (work->pkg == NULL) return; } t = time(NULL) - work->start_time; h = t / 3600; m = t / 60 % 60; s = t % 60; /* * Reduce total dep size */ RunningPkgDepSize -= work->pkg_dep_size; RunningPkgDepSize -= work->memuse; work->pkg_dep_size = 0; work->memuse = 0; /* * Process pkg out of the worker */ pkg = work->pkg; if (pkg->flags & (PKGF_ERROR|PKGF_NOBUILD)) { pkg->flags |= PKGF_FAILURE; /* * This NOBUILD condition XXX can occur if the package is * not allowed to be built. */ if (pkg->flags & PKGF_NOBUILD) { char *reason; reason = buildskipreason(NULL, pkg); if (pkg->flags & PKGF_NOBUILD_I) { ++BuildIgnoreCount; dlog(DLOG_SKIP, "[%03d] IGNORD %s - %s\n", work->index, pkg->portdir, reason); doHook(pkg, "hook_pkg_ignored", HookPkgIgnored, 0); } else { ++BuildSkipCount; dlog(DLOG_SKIP, "[%03d] SKIPPD %s - %s\n", work->index, pkg->portdir, reason); doHook(pkg, "hook_pkg_skipped", HookPkgSkipped, 0); } free(reason); } else { char skipbuf[16]; int scount; scount = buildskipcount_dueto(pkg, 1); buildskipcount_dueto(pkg, 0); if (scount) snprintf(skipbuf, sizeof(skipbuf), " (%d)", scount); else skipbuf[0] = 0; ++BuildFailCount; dlog(DLOG_FAIL | DLOG_RED, "[%03d] FAILURE %s%s ##%16.16s %02d:%02d:%02d\n", work->index, pkg->portdir, skipbuf, getphasestr(work->phase), h, m, s); doHook(pkg, "hook_pkg_failure", HookPkgFailure, 0); } } else { pkg->flags |= PKGF_SUCCESS; ++BuildSuccessCount; dlog(DLOG_SUCC | DLOG_GRN, "[%03d] SUCCESS %s ##%02d:%02d:%02d\n", work->index, pkg->portdir, h, m, s); doHook(pkg, "hook_pkg_success", HookPkgSuccess, 0); } ++BuildCount; pkg->flags &= ~PKGF_BUILDLIST; pkg->flags &= ~PKGF_RUNNING; work->pkg = NULL; --RunningWorkers; if (work->state == WORKER_FAILED) { dlog(DLOG_ALL, "[%03d] XXX/XXX WORKER IS IN A FAILED STATE\n", work->index); ++FailedWorkers; } else if (work->flags & WORKERF_FREEZE) { dlog(DLOG_ALL, "[%03d] FROZEN(DEBUG) %s\n", work->index, pkg->portdir); work->state = WORKER_FROZEN; } else { work->state = WORKER_IDLE; } } /* * Wait for one or more workers to complete. * * WorkerMutex must be held. */ static void waitbuild(int whilematch, int dynamicmax) { static time_t wblast_time; static time_t dmlast_time; struct timespec ts; worker_t *work; time_t t; int i; if (whilematch == 0) whilematch = 1; while (RunningWorkers == whilematch) { for (i = 0; i < MaxWorkers; ++i) { work = &WorkerAry[i]; if (work->state == WORKER_DONE || work->state == WORKER_FAILED) { workercomplete(work); } else { pthread_cond_signal(&work->cond); } RunStatsUpdate(work, NULL); } RunStatsUpdateTop(); RunStatsUpdateLogs(); RunStatsSync(); if (RunningWorkers == whilematch) { clock_gettime(CLOCK_REALTIME, &ts); ts.tv_sec += 1; ts.tv_nsec = 0; pthread_cond_timedwait(&WorkerCond, &WorkerMutex, &ts); } /* * Dynamically reduce MaxWorkers based on the load. When * the load exceeds 2 x ncpus we reduce the number of workers * up to 75% of MaxWorkers @ (5 x ncpus) load. * * Dynamically reduce MaxWorkers based on swap use, starting * at 10% swap and up to 75% of MaxWorkers at 40% swap. * * NOTE! Generally speaking this allows more workers to be * configured which helps in two ways. First it allows * a higher build rate for smaller packages. Second * it allows dsynth to ratchet-down the number of slots * when large packages are forcing the load up. * * A high load doesn't hurt efficiency, but swap usage * due to loading the tmpfs in lots of worker slots up * with tons of pkg install's (pre-reqs for a build) * does. Reducing the number of worker slots has a * huge beneficial effect on reducing swap use / paging. */ t = time(NULL); if (dynamicmax && (wblast_time == 0 || (unsigned)(t - wblast_time) >= 5)) { double min_load = 1.5 * NumCores; double max_load = 5.0 * NumCores; double min_swap = 0.10; double max_swap = 0.40; double dload[3]; double dswap; int max1; int max2; int max3; int max_sel; int noswap; wblast_time = t; /* * Cap based on load. This is back-loaded. */ getloadavg(dload, 3); if (dload[0] < min_load) { max1 = MaxWorkers; } else if (dload[0] <= max_load) { max1 = MaxWorkers - MaxWorkers * 0.75 * (dload[0] - min_load) / (max_load - min_load); } else { max1 = MaxWorkers * 25 / 100; } /* * Cap based on swap use. This is back-loaded. */ dswap = getswappct(&noswap); if (dswap < min_swap) { max2 = MaxWorkers; } else if (dswap <= max_swap) { max2 = MaxWorkers - MaxWorkers * 0.75 * (dswap - min_swap) / (max_swap - min_swap); } else { max2 = MaxWorkers * 25 / 100; } /* * Cap based on aggregate pkg-dependency memory * use installed in worker slots. This is * front-loaded. * * Since it can take a while for workers to retire * (to reduce RunningPkgDepSize), just set our * target 1 below the current run count to allow * jobs to retire without being replaced with new * jobs. * * In addition, in order to avoid a paging 'shock', * We enforce a 30 second-per-increment slow-start * once RunningPkgDepSize exceeds 1/2 the target. */ if (RunningPkgDepSize > PkgDepMemoryTarget) { max3 = RunningWorkers - 1; } else if (RunningPkgDepSize > PkgDepMemoryTarget / 2) { if (dmlast_time == 0 || (unsigned)(t - dmlast_time) >= 30) { dmlast_time = t; max3 = RunningWorkers + 1; } else { max3 = RunningWorkers; } } else { max3 = MaxWorkers; } /* * Priority reduction, convert to DynamicMaxWorkers */ max_sel = max1; if (max_sel > max2) max_sel = max2; if (max_sel > max3) max_sel = max3; /* * Restrict to allowed range, and also handle * slow-start. */ if (max_sel < 1) max_sel = 1; if (max_sel > DynamicMaxWorkers + 1) max_sel = DynamicMaxWorkers + 1; if (max_sel > MaxWorkers) max_sel = MaxWorkers; /* * Stop waiting if DynamicMaxWorkers is going to * increase. */ if (DynamicMaxWorkers < max1) whilematch = -1; /* * And adjust */ if (DynamicMaxWorkers != max1) { dlog(DLOG_ALL | DLOG_FILTER, "[XXX] Load=%-6.2f(%2d) " "Swap=%-3.2f%%(%2d) " "Mem=%3.2fG(%2d) " "Adjust Workers %d->%d\n", dload[0], max1, dswap * 100.0, max2, RunningPkgDepSize / (double)ONEGB, max3, DynamicMaxWorkers, max_sel); DynamicMaxWorkers = max_sel; } } } } /* * Worker pthread (WorkerAry) * * This thread belongs to the dsynth master process and handled a worker slot. * (this_thread) -> WORKER fork/exec (WorkerPocess) -> (pty) -> sub-processes. */ static void * childBuilderThread(void *arg) { char *envary[1] = { NULL }; worker_t *work = arg; wmsg_t wmsg; pkg_t *pkg; pid_t pid; int status; int flags; volatile int dowait; char slotbuf[8]; char fdbuf[8]; char flagsbuf[16]; pthread_mutex_lock(&WorkerMutex); while (work->terminate == 0) { dowait = 1; switch(work->state) { case WORKER_IDLE: break; case WORKER_PENDING: /* * Fork the management process for the pkg operation * on this worker slot. * * This process will set up the environment, do the * mounts, will become the reaper, and will process * pipe commands and handle chroot operations. * * NOTE: If SOCK_CLOEXEC is not supported WorkerMutex * is sufficient to interlock F_SETFD FD_CLOEXEC * operations. */ ddassert(work->pkg); if (socketpair(AF_UNIX, SOCK_STREAM | SOCK_CLOEXEC, PF_UNSPEC, work->fds)) { dfatal_errno("socketpair() during worker fork"); } snprintf(slotbuf, sizeof(slotbuf), "%d", work->index); snprintf(fdbuf, sizeof(fdbuf), "3"); /* * Pass global flags and add-in the DEBUGSTOP if * the package is flagged for debugging. */ flags = WorkerProcFlags; if (work->pkg->flags & PKGF_DEBUGSTOP) { flags |= WORKER_PROC_DEBUGSTOP; } else { flags &= ~WORKER_PROC_DEBUGSTOP; } snprintf(flagsbuf, sizeof(flagsbuf), "%d", flags); /* * fds[0] - master * fds[1] - slave * * We pass the salve descriptor in fd 3 and close all * other descriptors for security. */ pthread_mutex_unlock(&WorkerMutex); pid = vfork(); if (pid == 0) { close(work->fds[0]); dup2(work->fds[1], 3); closefrom(4); fcntl(3, F_SETFD, 0); execle(DSynthExecPath, DSynthExecPath, "-p", Profile, "WORKER", slotbuf, fdbuf, work->pkg->portdir, work->pkg->pkgfile, flagsbuf, NULL, envary); write(2, "EXECLE FAILURE\n", 15); _exit(1); } pthread_mutex_lock(&WorkerMutex); close(work->fds[1]); work->phase = PHASE_PENDING; work->lines = 0; work->memuse = 0; work->pid = pid; work->state = WORKER_RUNNING; /* fall through */ case WORKER_RUNNING: /* * Poll for status updates, if NULL is returned * and status is non-zero, the communications link * failed unexpectedly. */ pkg = work->pkg; pthread_mutex_unlock(&WorkerMutex); status = ipcreadmsg(work->fds[0], &wmsg); pthread_mutex_lock(&WorkerMutex); if (status == 0) { /* * Normal message, can include normal * termination which changes us over * to another state. */ dowait = 0; switch(wmsg.cmd) { case WMSG_CMD_INSTALL_PKGS: wmsg.cmd = WMSG_RES_INSTALL_PKGS; wmsg.status = childInstallPkgDeps(work); pthread_mutex_unlock(&WorkerMutex); ipcwritemsg(work->fds[0], &wmsg); pthread_mutex_lock(&WorkerMutex); break; case WMSG_CMD_STATUS_UPDATE: work->phase = wmsg.phase; work->lines = wmsg.lines; if (work->memuse != wmsg.memuse) { RunningPkgDepSize += wmsg.memuse - work->memuse; work->memuse = wmsg.memuse; } break; case WMSG_CMD_SUCCESS: work->flags |= WORKERF_SUCCESS; break; case WMSG_CMD_FAILURE: work->flags |= WORKERF_FAILURE; break; case WMSG_CMD_FREEZEWORKER: work->flags |= WORKERF_FREEZE; break; default: break; } RunStatsUpdate(work, NULL); RunStatsSync(); } else { close(work->fds[0]); pthread_mutex_unlock(&WorkerMutex); while (waitpid(work->pid, &status, 0) < 0 && errno == EINTR) { ; } pthread_mutex_lock(&WorkerMutex); if (work->flags & WORKERF_SUCCESS) { pkg->flags |= PKGF_SUCCESS; work->state = WORKER_DONE; } else if (work->flags & WORKERF_FAILURE) { pkg->flags |= PKGF_FAILURE; work->state = WORKER_DONE; } else { pkg->flags |= PKGF_FAILURE; work->state = WORKER_FAILED; } work->flags |= WORKERF_STATUS_UPDATE; pthread_cond_signal(&WorkerCond); } break; case WORKER_DONE: /* * pkg remains attached until frontend processes the * completion. The frontend will then set the state * back to idle. */ break; case WORKER_FAILED: /* * A worker failure means that the worker did not * send us a WMSG_CMD_SUCCESS or WMSG_CMD_FAILURE * ipc before terminating. * * We just sit in this state until the front-end * does something about it. */ break; case WORKER_FROZEN: /* * A worker getting frozen is debug-related. We * just sit in this state (likely forever). */ break; default: dfatal("worker: [%03d] Unexpected state %d " "for worker %d", work->index, work->state, work->index); /* NOT REACHED */ break; } /* * The dsynth frontend will poll us approximately once * a second (its variable). */ if (dowait) pthread_cond_wait(&work->cond, &WorkerMutex); } /* * Scrap the comm socket if running, this should cause the worker * process to kill its sub-programs and cleanup. */ if (work->state == WORKER_RUNNING) { pthread_mutex_unlock(&WorkerMutex); close(work->fds[0]); while (waitpid(work->pid, &status, 0) < 0 && errno == EINTR); pthread_mutex_lock(&WorkerMutex); } /* * Final handshake */ work->state = WORKER_EXITING; pthread_cond_signal(&WorkerCond); pthread_mutex_unlock(&WorkerMutex); return NULL; } /* * Install all the binary packages (we have already built them) that * the current work package depends on, without duplicates, in a script * which will be run from within the specified work jail. * * Locked by WorkerMutex (global) */ static int childInstallPkgDeps(worker_t *work) { char *buf; FILE *fp; if (PKGLIST_EMPTY(&work->pkg->idepon_list)) return 0; asprintf(&buf, "%s/tmp/dsynth_install_pkgs", work->basedir); fp = fopen(buf, "w"); ddassert(fp != NULL); fprintf(fp, "#!/bin/sh\n"); fprintf(fp, "#\n"); fchmod(fileno(fp), 0755); childInstallPkgDeps_recurse(fp, &work->pkg->idepon_list, 0, 1, 0); childInstallPkgDeps_recurse(fp, &work->pkg->idepon_list, 1, 1, 0); fprintf(fp, "\nexit 0\n"); fclose(fp); freestrp(&buf); return 1; } /* * Recursive child install dependencies. * * first_one_only is only specified if the pkg the list comes from * is a generic unflavored package that has flavors, telling us to * dive the first flavor only. * * However, in nearly all cases this flag will now be zero because * this code now dives the first flavor when encountering a dummy node * and clears nfirst on success. Hence if you are asking why 'nfirst' * is set to 1, and then zero, instead of just being removed entirely, * it is because there might still be an edge case here. */ static size_t childInstallPkgDeps_recurse(FILE *fp, pkglink_t *list, int undoit, int depth, int first_one_only) { pkglink_t *link; pkg_t *pkg; size_t tot = 0; int ndepth; int nfirst; PKGLIST_FOREACH(link, list) { pkg = link->pkg; /* * We don't want to mess up our depth test just below if * a DUMMY node had to be inserted. The nodes under the * dummy node. * * The elements under a dummy node represent all the flabor, * a dependency that directly references a dummy node only * uses the first flavor (first_one_only / nfirst). */ ndepth = (pkg->flags & PKGF_DUMMY) ? depth : depth + 1; nfirst = (pkg->flags & PKGF_DUMMY) ? 1 : 0; /* * We only need all packages for the top-level dependencies. * The deeper ones only need DEP_TYPE_LIB and DEP_TYPE_RUN * (types greater than DEP_TYPE_BUILD) since they are already * built. */ if (depth > 1 && link->dep_type <= DEP_TYPE_BUILD) { if (first_one_only) break; continue; } /* * If this is a dummy node with no package, the originator * is requesting a flavored package. We select the default * flavor which we presume is the first one. */ if (pkg->pkgfile == NULL && (pkg->flags & PKGF_DUMMY)) { pkg_t *spkg = pkg->idepon_list.next->pkg; if (spkg) { if (fp) { fprintf(fp, "echo 'UNFLAVORED %s -> use " "%s'\n", pkg->portdir, spkg->portdir); } pkg = spkg; nfirst = 0; } else { if (fp) { fprintf(fp, "echo 'CANNOT FIND DEFAULT " "FLAVOR FOR %s'\n", pkg->portdir); } } } if (undoit) { if (pkg->dsynth_install_flg == 1) { pkg->dsynth_install_flg = 0; tot += childInstallPkgDeps_recurse(fp, &pkg->idepon_list, undoit, ndepth, nfirst); } if (first_one_only) break; continue; } if (pkg->dsynth_install_flg) { if (DebugOpt >= 2 && pkg->pkgfile && fp) { fprintf(fp, "echo 'AlreadyHave %s'\n", pkg->pkgfile); } if (first_one_only) break; continue; } tot += childInstallPkgDeps_recurse(fp, &pkg->idepon_list, undoit, ndepth, nfirst); if (pkg->dsynth_install_flg) { if (first_one_only) break; continue; } pkg->dsynth_install_flg = 1; /* * Generate package installation command */ if (fp && pkg->pkgfile) { fprintf(fp, "echo 'Installing /packages/All/%s'\n", pkg->pkgfile); fprintf(fp, "pkg install -q -y /packages/All/%s " "|| exit 1\n", pkg->pkgfile); } else if (fp) { fprintf(fp, "echo 'CANNOT FIND PKG FOR %s'\n", pkg->portdir); } if (pkg->pkgfile) { struct stat st; char *path; char *ptr; asprintf(&path, "%s/%s", RepositoryPath, pkg->pkgfile); ptr = strrchr(pkg->pkgfile, '.'); if (stat(path, &st) == 0) { if (strcmp(ptr, ".tar") == 0) tot += st.st_size; else if (strcmp(ptr, ".tgz") == 0) tot += st.st_size * 3; else if (strcmp(ptr, ".txz") == 0) tot += st.st_size * 5; else if (strcmp(ptr, ".tbz") == 0) tot += st.st_size * 3; else tot += st.st_size * 2; } free(path); } if (first_one_only) break; } return tot; } /* * Worker process interactions. * * The worker process is responsible for managing the build of a single * package. It is exec'd by the master dsynth and only loads the * configuration. * * This process does not run in the chroot. It will become the reaper for * all sub-processes and it will enter the chroot to execute various phases. * It catches SIGINTR, SIGHUP, and SIGPIPE and will iterate, terminate, and * reap all sub-process upon kill or exit. * * The command line forwarded to this function is: * * WORKER slot# socketfd portdir/subdir * * TERM=dumb * USER=root * HOME=/root * LANG=C * SSL_NO_VERIFY_PEER=1 * USE_PACKAGE_DEPENDS_ONLY=1 * PORTSDIR=/xports * PORT_DBDIR=/options For ports options * PACKAGE_BUILDING=yes Don't build packages that aren't legally * buildable for a binary repo. * PKG_DBDIR=/var/db/pkg * PKG_CACHEDIR=/var/cache/pkg * PKG_CREATE_VERBOSE=yes Ensure periodic output during packaging * (custom environment) * PATH=/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin * UNAME_s=DragonFly (example) * UNAME_v=DragonFly 5.7-SYNTH (example) * UNAME_p=x86_64 (example) * UNAME_m=x86_64 (example) * UNAME_r=5.7-SYNTH (example) * NO_DEPENDS=yes (conditional based on phase) * DISTDIR=/distfiles * WRKDIRPREFIX=/construction * BATCH=yes * MAKE_JOBS_NUMBER=n * * SETUP: * ldconfig -R * /usr/local/sbin/pkg-static install /packages/All/<the pkg pkg> * /usr/local/sbin/pkg-static install /packages/All/<pkg> * (for all dependencies) * * PHASES: make -C path FLAVOR=flavor <phase> * check-sanity * pkg-depends * fetch-depends * fetch * checksum * extract-depends * extract * patch-depends * patch * build-depends * lib-depends * configure * build * run-depends * stage * test (skipped) * check-plist ('dsynth test blahblah' or 'dsynth -D everything' only) * package e.g. /construction/lang/perl5.28/pkg/perl5-5.28.2.txz * install-mtree (skipped) * install (skipped) * deinstall (skipped) */ void WorkerProcess(int ac, char **av) { wmsg_t wmsg; int fd; int slot; int tmpfd; int pkgpkg = 0; int status; int len; int do_install_phase; char *portdir; char *pkgfile; char *flavor; char *buf; worker_t *work; bulk_t *bulk; pkg_t pkg; buildenv_t *benv; FILE *fp; /* * Parse arguments */ if (ac != 6) { dlog(DLOG_ALL, "WORKER PROCESS %d- bad arguments\n", getpid()); exit(1); } slot = strtol(av[1], NULL, 0); fd = strtol(av[2], NULL, 0); /* master<->slave messaging */ portdir = av[3]; pkgfile = av[4]; flavor = strchr(portdir, '@'); if (flavor) { *flavor++ = 0; asprintf(&buf, "@%s", flavor); WorkerFlavorPrt = buf; buf = NULL; /* safety */ } WorkerProcFlags = strtol(av[5], NULL, 0); bzero(&wmsg, sizeof(wmsg)); setproctitle("[%02d] WORKER STARTUP %s%s", slot, portdir, WorkerFlavorPrt); if (strcmp(portdir, "ports-mgmt/pkg") == 0) pkgpkg = 1; signal(SIGTERM, phaseTerminateSignal); signal(SIGINT, phaseTerminateSignal); signal(SIGHUP, phaseTerminateSignal); /* * Set up the environment */ setenv("TERM", "dumb", 1); setenv("USER", "root", 1); setenv("HOME", "/root", 1); setenv("LANG", "C", 1); setenv("SSL_NO_VERIFY_PEER", "1", 1); addbuildenv("USE_PACKAGE_DEPENDS_ONLY", "yes", BENV_MAKECONF); addbuildenv("PORTSDIR", "/xports", BENV_MAKECONF); addbuildenv("PORT_DBDIR", "/options", BENV_MAKECONF); addbuildenv("PKG_DBDIR", "/var/db/pkg", BENV_MAKECONF); addbuildenv("PKG_CACHEDIR", "/var/cache/pkg", BENV_MAKECONF); addbuildenv("PKG_SUFX", UsePkgSufx, BENV_MAKECONF); if (WorkerProcFlags & WORKER_PROC_DEVELOPER) addbuildenv("DEVELOPER", "1", BENV_MAKECONF); /* * CCache is a horrible unreliable hack but... leave the * mechanism in-place in case someone has a death wish. */ if (UseCCache) { addbuildenv("WITH_CCACHE_BUILD", "yes", BENV_MAKECONF); addbuildenv("CCACHE_DIR", "/ccache", BENV_MAKECONF); } addbuildenv("UID", "0", BENV_MAKECONF); addbuildenv("ARCH", ArchitectureName, BENV_MAKECONF); #ifdef __DragonFly__ addbuildenv("OPSYS", "DragonFly", BENV_MAKECONF); addbuildenv("DFLYVERSION", VersionFromParamHeader, BENV_MAKECONF); addbuildenv("OSVERSION", "9999999", BENV_MAKECONF); #else #error "Need OS-specific data to generate make.conf" #endif addbuildenv("OSREL", ReleaseName, BENV_MAKECONF); addbuildenv("_OSRELEASE", VersionOnlyName, BENV_MAKECONF); setenv("PATH", "/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin", 1); setenv("UNAME_s", OperatingSystemName, 1); setenv("UNAME_v", VersionName, 1); setenv("UNAME_p", ArchitectureName, 1); setenv("UNAME_m", MachineName, 1); setenv("UNAME_r", ReleaseName, 1); addbuildenv("DISTDIR", "/distfiles", BENV_MAKECONF); addbuildenv("WRKDIRPREFIX", "/construction", BENV_MAKECONF); addbuildenv("BATCH", "yes", BENV_MAKECONF); /* * Special consideration * * PACKAGE_BUILDING - Disallow packaging ports which do not allow * for binary distribution. * * PKG_CREATE_VERBOSE - Ensure periodic output during the packaging * process to avoid a watchdog timeout. * */ addbuildenv("PACKAGE_BUILDING", "yes", BENV_MAKECONF); addbuildenv("PKG_CREATE_VERBOSE", "yes", BENV_MAKECONF); asprintf(&buf, "%d", MaxJobs); addbuildenv("MAKE_JOBS_NUMBER", buf, BENV_MAKECONF); freestrp(&buf); if (flavor) setenv("FLAVOR", flavor, 1); /* * Become the reaper */ if (procctl(P_PID, getpid(), PROC_REAP_ACQUIRE, NULL) < 0) dfatal_errno("procctl() - Cannot become reaper"); /* * Initialize a worker structure */ DoInitBuild(slot); bzero(&pkg, sizeof(pkg)); pkg.portdir = portdir; /* sans flavor */ pkg.pkgfile = pkgfile; if (strchr(portdir, '/')) len = strchr(portdir, '/') - portdir; else len = 0; /* * Setup the logfile */ asprintf(&pkg.logfile, "%s/%*.*s___%s%s%s.log", LogsPath, len, len, portdir, ((portdir[len] == '/') ? portdir + len + 1 : portdir + len), (flavor ? "@" : ""), (flavor ? flavor : "")); tmpfd = open(pkg.logfile, O_RDWR|O_CREAT|O_TRUNC, 0666); if (tmpfd >= 0) { if (DebugOpt >= 2) { dlog(DLOG_ALL, "[%03d] %s LOGFILE %s\n", slot, pkg.portdir, pkg.logfile); } close(tmpfd); } else { dlog(DLOG_ALL, "[%03d] LOGFILE %s (create failed)\n", slot, pkg.logfile); } /* * Setup the work structure. Because this is an exec'd sub-process, * there is only one work structure. */ work = &WorkerAry[0]; work->flavor = flavor; work->fds[0] = fd; work->pkg = &pkg; work->start_time = time(NULL); /* * Do mounts */ SigWork = work; setproctitle("[%02d] WORKER MOUNTS %s%s", slot, portdir, WorkerFlavorPrt); DoWorkerMounts(work); /* * Generate an /etc/make.conf in the build base */ asprintf(&buf, "%s/etc/make.conf", work->basedir); fp = fopen(buf, "w"); dassert_errno(fp, "Unable to create %s\n", buf); for (benv = BuildEnv; benv; benv = benv->next) { if (benv->type & BENV_PKGLIST) continue; if ((benv->type & BENV_CMDMASK) == BENV_MAKECONF) { if (DebugOpt >= 2) { dlog(DLOG_ALL, "[%03d] ENV %s=%s\n", slot, benv->label, benv->data); } fprintf(fp, "%s=%s\n", benv->label, benv->data); } } fclose(fp); freestrp(&buf); /* * Set up our hooks */ if (UsingHooks) initbulk(childHookRun, MaxBulk); /* * Start phases */ wmsg.cmd = WMSG_CMD_INSTALL_PKGS; ipcwritemsg(fd, &wmsg); status = ipcreadmsg(fd, &wmsg); if (status < 0 || wmsg.cmd != WMSG_RES_INSTALL_PKGS) dfatal("pkg installation handshake failed"); do_install_phase = wmsg.status; wmsg.cmd = WMSG_CMD_STATUS_UPDATE; wmsg.phase = PHASE_INSTALL_PKGS; wmsg.lines = 0; status = ipcwritemsg(fd, &wmsg); if (pkgpkg) { dophase(work, &wmsg, WDOG5, PHASE_PACKAGE, "package"); } else { if (do_install_phase) { dophase(work, &wmsg, WDOG4, PHASE_INSTALL_PKGS, "setup"); } dophase(work, &wmsg, WDOG2, PHASE_CHECK_SANITY, "check-sanity"); dophase(work, &wmsg, WDOG2, PHASE_PKG_DEPENDS, "pkg-depends"); dophase(work, &wmsg, WDOG7, PHASE_FETCH_DEPENDS, "fetch-depends"); dophase(work, &wmsg, WDOG7, PHASE_FETCH, "fetch"); dophase(work, &wmsg, WDOG2, PHASE_CHECKSUM, "checksum"); dophase(work, &wmsg, WDOG3, PHASE_EXTRACT_DEPENDS, "extract-depends"); dophase(work, &wmsg, WDOG3, PHASE_EXTRACT, "extract"); dophase(work, &wmsg, WDOG2, PHASE_PATCH_DEPENDS, "patch-depends"); dophase(work, &wmsg, WDOG2, PHASE_PATCH, "patch"); dophase(work, &wmsg, WDOG5, PHASE_BUILD_DEPENDS, "build-depends"); dophase(work, &wmsg, WDOG5, PHASE_LIB_DEPENDS, "lib-depends"); dophase(work, &wmsg, WDOG3, PHASE_CONFIGURE, "configure"); dophase(work, &wmsg, WDOG9, PHASE_BUILD, "build"); dophase(work, &wmsg, WDOG5, PHASE_RUN_DEPENDS, "run-depends"); dophase(work, &wmsg, WDOG5, PHASE_STAGE, "stage"); #if 0 dophase(work, &wmsg, WDOG5, PHASE_TEST, "test"); #endif if (WorkerProcFlags & WORKER_PROC_CHECK_PLIST) { dophase(work, &wmsg, WDOG1, PHASE_CHECK_PLIST, "check-plist"); } dophase(work, &wmsg, WDOG5, PHASE_PACKAGE, "package"); #if 0 dophase(work, &wmsg, WDOG5, PHASE_INSTALL_MTREE, "install-mtree"); dophase(work, &wmsg, WDOG5, PHASE_INSTALL, "install"); dophase(work, &wmsg, WDOG5, PHASE_DEINSTALL, "deinstall"); #endif } if (MasterPtyFd >= 0) { close(MasterPtyFd); MasterPtyFd = -1; } setproctitle("[%02d] WORKER CLEANUP %s%s", slot, portdir, WorkerFlavorPrt); /* * Copy the package to the repo. */ if (work->accum_error == 0) { char *b1; char *b2; asprintf(&b1, "%s/construction/%s/pkg/%s", work->basedir, pkg.portdir, pkg.pkgfile); asprintf(&b2, "%s/%s", RepositoryPath, pkg.pkgfile); if (copyfile(b1, b2)) { ++work->accum_error; dlog(DLOG_ALL, "[%03d] %s Unable to copy %s to %s\n", work->index, pkg.portdir, b1, b2); } free(b1); free(b2); } /* * Unmount, unless we are in DebugStopMode. */ if ((WorkerProcFlags & WORKER_PROC_DEBUGSTOP) == 0) DoWorkerUnmounts(work); /* * Send completion status to master dsynth worker thread. */ if (work->accum_error) { wmsg.cmd = WMSG_CMD_FAILURE; } else { wmsg.cmd = WMSG_CMD_SUCCESS; } ipcwritemsg(fd, &wmsg); if (WorkerProcFlags & WORKER_PROC_DEBUGSTOP) { wmsg.cmd = WMSG_CMD_FREEZEWORKER; ipcwritemsg(fd, &wmsg); } if (UsingHooks) { while ((bulk = getbulk()) != NULL) freebulk(bulk); donebulk(); } } static void dophase(worker_t *work, wmsg_t *wmsg, int wdog, int phaseid, const char *phase) { pkg_t *pkg = work->pkg; char buf[1024]; pid_t pid; int status; int ms; pid_t wpid; int wpid_reaped; int fdlog; time_t start_time; time_t last_time; time_t next_time; time_t wdog_time; FILE *fp; if (work->accum_error) return; setproctitle("[%02d] WORKER %-8.8s %s%s", work->index, phase, pkg->portdir, WorkerFlavorPrt); wmsg->phase = phaseid; if (ipcwritemsg(work->fds[0], wmsg) < 0) { dlog(DLOG_ALL, "[%03d] %s Lost Communication with dsynth, " "aborting worker\n", work->index, pkg->portdir); ++work->accum_error; return; } /* * Execute the port make command in chroot on a pty. */ fflush(stdout); fflush(stderr); if (MasterPtyFd >= 0) { int slavefd; /* * NOTE: We can't open the slave in the child because the * master may race a disconnection test. If we open * it in the parent our close() will flush any pending * output not read by the master (which is the same * parent process) and deadlock. * * Solve this by hand-shaking the slave tty to give * the master time to close its slavefd (after this * section). * * Leave the tty defaults intact, which also likely * means it will be in line-buffered mode, so handshake * with a full line. * * TODO: Our handshake probably echos back to the master pty * due to tty echo, and ends up in the log, so just * pass through a newline. */ slavefd = open(ptsname(MasterPtyFd), O_RDWR); dassert_errno(slavefd >= 0, "Cannot open slave pty"); /* * Now do the fork. */ pid = fork(); if (pid == 0) { login_tty(slavefd); /* login_tty() closes slavefd */ } else { close(slavefd); } } else { /* * Initial MasterPtyFd for the slot, just use forkpty(). */ pid = forkpty(&MasterPtyFd, NULL, NULL, NULL); } /* * The slave must make sure the master has time to close slavefd * in the re-use case before going its merry way. The master needs * to set terminal modes and the window as well. */ if (pid == 0) { /* * Slave waits for handshake */ char ttybuf[2]; read(0, ttybuf, 1); } else { /* * We are going through a pty, so set the tty modes to * Set tty modes so we do not get ^M's in the log files. * * This isn't fatal if it doesn't work. Remember that * our output goes through the pty to the management * process which will log it. */ struct termios tio; struct winsize win; if (tcgetattr(MasterPtyFd, &tio) == 0) { tio.c_oflag |= OPOST | ONOCR; tio.c_oflag &= ~(OCRNL | ONLCR); tio.c_iflag |= ICRNL; tio.c_iflag &= ~(INLCR | IGNCR); if (tcsetattr(MasterPtyFd, TCSANOW, &tio)) { printf("tcsetattr failed: %s\n", strerror(errno)); } /* * Give the tty a non-zero columns field. * This fixes at least one port (textproc/po4a) */ if (ioctl(MasterPtyFd, TIOCGWINSZ, &win) == 0) { win.ws_col = 80; ioctl(MasterPtyFd, TIOCSWINSZ, &win); } else { printf("TIOCGWINSZ failed: %s\n", strerror(errno)); } } else { printf("tcgetattr failed: %s\n", strerror(errno)); } /* * Master issues handshake */ write(MasterPtyFd, "\n", 1); } if (pid == 0) { /* * Additional phase-specific environment variables * * - Do not try to process missing depends outside of the * depends phases. Also relies on USE_PACKAGE_DEPENDS_ONLY * in the make.conf. */ switch(phaseid) { case PHASE_CHECK_SANITY: case PHASE_FETCH: case PHASE_CHECKSUM: case PHASE_EXTRACT: case PHASE_PATCH: case PHASE_CONFIGURE: case PHASE_STAGE: case PHASE_TEST: case PHASE_CHECK_PLIST: case PHASE_INSTALL_MTREE: case PHASE_INSTALL: case PHASE_DEINSTALL: break; case PHASE_PKG_DEPENDS: case PHASE_FETCH_DEPENDS: case PHASE_EXTRACT_DEPENDS: case PHASE_PATCH_DEPENDS: case PHASE_BUILD_DEPENDS: case PHASE_LIB_DEPENDS: case PHASE_RUN_DEPENDS: break; default: setenv("NO_DEPENDS", "1", 1); break; } /* * Clean-up, chdir, and chroot. */ closefrom(3); if (chdir(work->basedir) < 0) dfatal_errno("chdir in phase initialization"); if (chroot(work->basedir) < 0) dfatal_errno("chroot in phase initialization"); /* * We have a choice here on how to handle stdin (fd 0). * We can leave it connected to the pty in which case * the build will just block if it tries to ask a * question (and the watchdog will kill it, eventually), * or we can try to EOF the pty, or we can attach /dev/null * to descriptor 0. */ if (NullStdinOpt) { int fd; fd = open("/dev/null", O_RDWR); dassert_errno(fd >= 0, "cannot open /dev/null"); if (fd != 0) { dup2(fd, 0); close(fd); } } /* * Execute the appropriate command. */ switch(phaseid) { case PHASE_INSTALL_PKGS: snprintf(buf, sizeof(buf), "/tmp/dsynth_install_pkgs"); execl(buf, buf, NULL); break; default: snprintf(buf, sizeof(buf), "/xports/%s", pkg->portdir); execl(MAKE_BINARY, MAKE_BINARY, "-C", buf, phase, NULL); break; } _exit(1); } fcntl(MasterPtyFd, F_SETFL, O_NONBLOCK); if (pid < 0) { dlog(DLOG_ALL, "[%03d] %s Fork Failed: %s\n", work->index, pkg->logfile, strerror(errno)); ++work->accum_error; return; } SigPid = pid; fdlog = open(pkg->logfile, O_RDWR|O_CREAT|O_APPEND, 0644); if (fdlog < 0) { dlog(DLOG_ALL, "[%03d] %s Cannot open logfile '%s': %s\n", work->index, pkg->portdir, pkg->logfile, strerror(errno)); } snprintf(buf, sizeof(buf), "----------------------------------------" "---------------------------------------\n" "-- Phase: %s\n" "----------------------------------------" "---------------------------------------\n", phase); write(fdlog, buf, strlen(buf)); start_time = time(NULL); last_time = start_time; wdog_time = start_time; wpid_reaped = 0; status = 0; for (;;) { ms = mptylogpoll(MasterPtyFd, fdlog, wmsg, &wdog_time); if (ms == MPTY_FAILED) { dlog(DLOG_ALL, "[%03d] %s lost pty in phase %s, terminating\n", work->index, pkg->portdir, phase); break; } if (ms == MPTY_EOF) break; /* * Generally speaking update status once a second. * This also allows us to detect if the management * dsynth process has gone away. */ next_time = time(NULL); if (next_time != last_time) { double dload[3]; double dv; int wdog_scaled; /* * Send status update to the worker management thread * in the master dsynth process. Remember, *WE* are * the worker management process sub-fork. */ if (ipcwritemsg(work->fds[0], wmsg) < 0) break; last_time = next_time; /* * Watchdog scaling */ getloadavg(dload, 3); dv = dload[2] / NumCores; if (dv < (double)NumCores) { wdog_scaled = wdog; } else { if (dv > 4.0 * NumCores) dv = 4.0 * NumCores; wdog_scaled = wdog * dv / NumCores; } /* * Watchdog */ if (next_time - wdog_time >= wdog_scaled * 60) { snprintf(buf, sizeof(buf), "\n--------\n" "WATCHDOG TIMEOUT FOR %s in %s " "after %d minutes\n" "Killing pid %d\n" "--------\n", pkg->portdir, phase, wdog_scaled, pid); if (fdlog >= 0) write(fdlog, buf, strlen(buf)); dlog(DLOG_ALL, "[%03d] %s WATCHDOG TIMEOUT in %s " "after %d minutes (%d min scaled)\n", work->index, pkg->portdir, phase, wdog, wdog_scaled); kill(pid, SIGKILL); ++work->accum_error; break; } } /* * Check process exit. Normally the pty will EOF * but if background processes remain we need to * check here to see if our primary exec is done, * so we can break out and reap those processes. * * Generally reap any other processes we have inherited * while we are here. */ do { wpid = wait3(&status, WNOHANG, NULL); } while (wpid > 0 && wpid != pid); if (wpid == pid && WIFEXITED(status)) { wpid_reaped = 1; break; } } next_time = time(NULL); setproctitle("[%02d] WORKER EXITREAP %s%s", work->index, pkg->portdir, WorkerFlavorPrt); /* * We usually get here due to a mpty EOF, but not always as there * could be persistent processes still holding the slave. Finish * up getting the exit status for the main process we are waiting * on and clean out any data left on the MasterPtyFd (as it could * be blocking the exit). */ while (wpid_reaped == 0) { (void)mptylogpoll(MasterPtyFd, fdlog, wmsg, &wdog_time); wpid = waitpid(pid, &status, WNOHANG); if (wpid == pid && WIFEXITED(status)) { wpid_reaped = 1; break; } if (wpid < 0 && errno != EINTR) { break; } /* * Safety. The normal phase waits until the fork/exec'd * pid finishes, causing a pty EOF on exit (the slave * descriptor is closed by the kernel on exit so the * process should already have exited). * * However, it is also possible to get here if the pty fails * for some reason. In this case, make sure that the process * is killed. */ kill(pid, SIGKILL); } /* * Clean out anything left on the pty but don't wait around * because there could be background processes preventing the * slave side from closing. */ while (mptylogpoll(MasterPtyFd, fdlog, wmsg, &wdog_time) == MPTY_DATA) ; /* * Report on the exit condition. If the pid was somehow lost * (probably due to someone gdb'ing the process), assume an error. */ if (wpid_reaped) { if (WEXITSTATUS(status)) { dlog(DLOG_ALL | DLOG_FILTER, "[%03d] %s Build phase '%s' failed exit %d\n", work->index, pkg->portdir, phase, WEXITSTATUS(status)); ++work->accum_error; } } else { dlog(DLOG_ALL, "[%03d] %s Build phase '%s' failed - lost pid\n", work->index, pkg->portdir, phase); ++work->accum_error; } /* * Kill any processes still running (sometimes processes end up in * the background during a dports build), and clean up any other * children that we have inherited. */ phaseReapAll(); /* * After the extraction phase add the space used by /construction * to the memory use. This helps us reduce the amount of paging * we do due to extremely large package extractions (languages, * chromium, etc). * * (dsynth already estimated the space used by the package deps * up front, but this will help us further). */ if (work->accum_error == 0 && phaseid == PHASE_EXTRACT) { struct statfs sfs; char *b1; asprintf(&b1, "%s/construction", work->basedir); if (statfs(b1, &sfs) == 0) { wmsg->memuse = (sfs.f_blocks - sfs.f_bfree) * sfs.f_bsize; ipcwritemsg(work->fds[0], wmsg); } } /* * Update log */ if (fdlog >= 0) { struct stat st; int h; int m; int s; last_time = next_time - start_time; s = last_time % 60; m = last_time / 60 % 60; h = last_time / 3600; fp = fdopen(fdlog, "a"); if (fp == NULL) { dlog(DLOG_ALL, "[%03d] %s Cannot fdopen fdlog: %s %d\n", work->index, pkg->portdir, strerror(errno), fstat(fdlog, &st)); close(fdlog); goto skip; } fprintf(fp, "\n"); if (work->accum_error) { fprintf(fp, "FAILED %02d:%02d:%02d\n", h, m, s); } else { if (phaseid == PHASE_EXTRACT && wmsg->memuse) { fprintf(fp, "Extracted Memory Use: %6.2fM\n", wmsg->memuse / (1024.0 * 1024.0)); } fprintf(fp, "SUCCEEDED %02d:%02d:%02d\n", h, m, s); } last_time = next_time - work->start_time; s = last_time % 60; m = last_time / 60 % 60; h = last_time / 3600; if (phaseid == PHASE_PACKAGE) { fprintf(fp, "TOTAL TIME %02d:%02d:%02d\n", h, m, s); } fprintf(fp, "\n"); fclose(fp); skip: ; } } static void phaseReapAll(void) { struct reaper_status rs; int status; while (procctl(P_PID, getpid(), PROC_REAP_STATUS, &rs) == 0) { if ((rs.flags & PROC_REAP_ACQUIRE) == 0) break; if (rs.pid_head < 0) break; if (kill(rs.pid_head, SIGKILL) == 0) { while (waitpid(rs.pid_head, &status, 0) < 0) ; } } while (wait3(&status, 0, NULL) > 0) ; } static void phaseTerminateSignal(int sig __unused) { if (CopyFileFd >= 0) close(CopyFileFd); if (MasterPtyFd >= 0) close(MasterPtyFd); if (SigPid > 1) kill(SigPid, SIGKILL); phaseReapAll(); if (SigWork) DoWorkerUnmounts(SigWork); exit(1); } static char * buildskipreason(pkglink_t *parent, pkg_t *pkg) { pkglink_t *link; pkg_t *scan; char *reason = NULL; char *ptr; size_t tot; size_t len; pkglink_t stack; if ((pkg->flags & PKGF_NOBUILD_I) && pkg->ignore) asprintf(&reason, "%s ", pkg->ignore); tot = 0; PKGLIST_FOREACH(link, &pkg->idepon_list) { #if 0 if (link->dep_type > DEP_TYPE_BUILD) continue; #endif scan = link->pkg; if (scan == NULL) continue; if ((scan->flags & (PKGF_ERROR | PKGF_NOBUILD)) == 0) continue; if (scan->flags & PKGF_NOBUILD) { stack.pkg = scan; stack.next = parent; ptr = buildskipreason(&stack, scan); len = strlen(scan->portdir) + strlen(ptr) + 8; reason = realloc(reason, tot + len); snprintf(reason + tot, len, "%s->%s", scan->portdir, ptr); free(ptr); } else { len = strlen(scan->portdir) + 8; reason = realloc(reason, tot + len); snprintf(reason + tot, len, "%s", scan->portdir); } /* * Don't try to print the entire graph */ if (parent) break; tot += strlen(reason + tot); reason[tot++] = ' '; reason[tot] = 0; } return (reason); } /* * Count number of packages that would be skipped due to the * specified package having failed. * * Call with mode 1 to count, and mode 0 to clear the * cumulative rscan flag (used to de-duplicate the count). * * Must be serialized. */ static int buildskipcount_dueto(pkg_t *pkg, int mode) { pkglink_t *link; pkg_t *scan; int total; total = 0; PKGLIST_FOREACH(link, &pkg->deponi_list) { scan = link->pkg; if (scan == NULL || scan->rscan == mode) continue; scan->rscan = mode; ++total; total += buildskipcount_dueto(scan, mode); } return total; } /* * The master ptyfd is in non-blocking mode. Drain up to 1024 bytes * and update wmsg->lines and *wdog_timep as appropriate. * * This function will poll, stalling up to 1 second. */ static int mptylogpoll(int ptyfd, int fdlog, wmsg_t *wmsg, time_t *wdog_timep) { struct pollfd pfd; char buf[1024]; ssize_t r; pfd.fd = ptyfd; pfd.events = POLLIN; pfd.revents = 0; poll(&pfd, 1, 1000); if (pfd.revents) { r = read(ptyfd, buf, sizeof(buf)); if (r > 0) { *wdog_timep = time(NULL); if (r > 0 && fdlog >= 0) write(fdlog, buf, r); while (--r >= 0) { if (buf[r] == '\n') ++wmsg->lines; } return MPTY_DATA; } else if (r < 0) { if (errno != EINTR && errno != EAGAIN) return MPTY_FAILED; return MPTY_AGAIN; } else if (r == 0) { return MPTY_EOF; } } return MPTY_AGAIN; } /* * Copy a (package) file from (src) to (dst), use an intermediate file and * rename to ensure that interruption does not leave us with a corrupt * package file. * * This is called by the WORKER process. * * (dsynth management thread -> WORKER process -> sub-processes) */ #define COPYBLKSIZE 32768 static int copyfile(char *src, char *dst) { char *tmp; char *buf; int fd1; int fd2; int error = 0; int mask; ssize_t r; asprintf(&tmp, "%s.new", dst); buf = malloc(COPYBLKSIZE); mask = sigsetmask(sigmask(SIGTERM)|sigmask(SIGINT)|sigmask(SIGHUP)); fd1 = open(src, O_RDONLY|O_CLOEXEC); fd2 = open(tmp, O_RDWR|O_CREAT|O_TRUNC|O_CLOEXEC, 0644); CopyFileFd = fd1; sigsetmask(mask); while ((r = read(fd1, buf, COPYBLKSIZE)) > 0) { if (write(fd2, buf, r) != r) error = 1; } if (r < 0) error = 1; mask = sigsetmask(sigmask(SIGTERM)|sigmask(SIGINT)|sigmask(SIGHUP)); CopyFileFd = -1; close(fd1); close(fd2); sigsetmask(mask); if (error) { remove(tmp); } else { if (rename(tmp, dst)) { error = 1; remove(tmp); } } freestrp(&buf); freestrp(&tmp); return error; } /* * doHook() * * primary process (threaded) - run_start, run_end, pkg_ignored, pkg_skipped * worker process (threaded) - pkg_sucess, pkg_failure * * If waitfor is non-zero this hook will be serialized. */ static void doHook(pkg_t *pkg, const char *id, const char *path, int waitfor) { if (path == NULL) return; while (waitfor && getbulk() != NULL) ; if (pkg) queuebulk(pkg->portdir, id, path, pkg->pkgfile); else queuebulk(NULL, id, path, NULL); while (waitfor && getbulk() != NULL) ; } /* * Execute hook (backend) * * s1 - portdir * s2 - id * s3 - script path * s4 - pkgfile (if applicable) */ static void childHookRun(bulk_t *bulk) { const char *cav[MAXCAC]; buildenv_t benv[MAXCAC]; char buf1[128]; char buf2[128]; char buf3[128]; char buf4[128]; FILE *fp; char *ptr; size_t len; pid_t pid; int cac; int bi; cac = 0; bi = 0; bzero(benv, sizeof(benv)); cav[cac++] = bulk->s3; benv[bi].label = "PROFILE"; benv[bi].data = Profile; ++bi; benv[bi].label = "DIR_PACKAGES"; benv[bi].data = PackagesPath; ++bi; benv[bi].label = "DIR_REPOSITORY"; benv[bi].data = RepositoryPath; ++bi; benv[bi].label = "DIR_PORTS"; benv[bi].data = DPortsPath; ++bi; benv[bi].label = "DIR_OPTIONS"; benv[bi].data = OptionsPath; ++bi; benv[bi].label = "DIR_DISTFILES"; benv[bi].data = DistFilesPath; ++bi; benv[bi].label = "DIR_LOGS"; benv[bi].data = LogsPath; ++bi; benv[bi].label = "DIR_BUILDBASE"; benv[bi].data = BuildBase; ++bi; if (strcmp(bulk->s2, "hook_run_start") == 0) { snprintf(buf1, sizeof(buf1), "%d", BuildTotal); benv[bi].label = "PORTS_QUEUED"; benv[bi].data = buf1; ++bi; } else if (strcmp(bulk->s2, "hook_run_end") == 0) { snprintf(buf1, sizeof(buf1), "%d", BuildSuccessCount); benv[bi].label = "PORTS_BUILT"; benv[bi].data = buf1; ++bi; snprintf(buf2, sizeof(buf2), "%d", BuildFailCount); benv[bi].label = "PORTS_FAILED"; benv[bi].data = buf2; ++bi; snprintf(buf3, sizeof(buf3), "%d", BuildIgnoreCount); benv[bi].label = "PORTS_IGNORED"; benv[bi].data = buf3; ++bi; snprintf(buf4, sizeof(buf4), "%d", BuildSkipCount); benv[bi].label = "PORTS_SKIPPED"; benv[bi].data = buf4; ++bi; } else { /* * success, failure, ignored, skipped */ benv[bi].label = "RESULT"; if (strcmp(bulk->s2, "hook_pkg_success") == 0) { benv[bi].data = "success"; } else if (strcmp(bulk->s2, "hook_pkg_failure") == 0) { benv[bi].data = "failure"; } else if (strcmp(bulk->s2, "hook_pkg_ignored") == 0) { benv[bi].data = "ignored"; } else if (strcmp(bulk->s2, "hook_pkg_skipped") == 0) { benv[bi].data = "skipped"; } else { dfatal("Unknown hook id: %s", bulk->s2); /* NOT REACHED */ } ++bi; /* * For compatibility with synth: * * ORIGIN does not include any @flavor, thus it is suitable * for finding the actual port directory/subdirectory. * * FLAVOR is set to ORIGIN if there is no flavor, otherwise * it is set to only the flavor sans the '@'. */ if ((ptr = strchr(bulk->s1, '@')) != NULL) { snprintf(buf1, sizeof(buf1), "%*.*s", (int)(ptr - bulk->s1), (int)(ptr - bulk->s1), bulk->s1); benv[bi].label = "ORIGIN"; benv[bi].data = buf1; ++bi; benv[bi].label = "FLAVOR"; benv[bi].data = ptr + 1; ++bi; } else { benv[bi].label = "ORIGIN"; benv[bi].data = bulk->s1; ++bi; benv[bi].label = "FLAVOR"; benv[bi].data = bulk->s1; ++bi; } benv[bi].label = "PKGNAME"; benv[bi].data = bulk->s4; ++bi; } benv[bi].label = NULL; benv[bi].data = NULL; fp = dexec_open(cav, cac, &pid, benv, 0, 0); while ((ptr = fgetln(fp, &len)) != NULL) ; if (dexec_close(fp, pid)) { dlog(DLOG_ALL, "[XXX] %s SCRIPT %s (%s)\n", bulk->s1, bulk->s2, bulk->s3); } }

24.740109

79

0.637487

3212fa7b9496669cd899b9b4fe7d1a59a3143a70

8,091

h

C

common/DcgmThread.h

deepio/DCGM

d10273f18fb3d425da752ab6bb7e07af3d18caec

[ "Apache-2.0" ]

85

2021-02-03T19:58:50.000Z

2022-03-21T08:00:11.000Z

common/DcgmThread.h

deepio/DCGM

d10273f18fb3d425da752ab6bb7e07af3d18caec

[ "Apache-2.0" ]

19

2021-03-19T08:13:58.000Z

2022-03-17T02:50:41.000Z

common/DcgmThread.h

deepio/DCGM

d10273f18fb3d425da752ab6bb7e07af3d18caec

[ "Apache-2.0" ]

17

2021-02-04T06:47:30.000Z

2022-03-21T22:14:03.000Z

/* * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DCGMTHREAD_H #define DCGMTHREAD_H #ifndef __linux__ #include <Windows.h> #else #include "errno.h" #include "pthread.h" #include <signal.h> #endif #include <string> #include <atomic> #include <condition_variable> #include <mutex> #define DCGM_THREAD_SIGNUM SIGUSR2 /* Which signal should DcgmThread use to wake wake up threads? */ class DcgmThread { private: std::atomic_bool m_hasRun; /* Has this thread run yet? */ std::atomic_bool m_shouldStop; /* Has our thread been signalled to quit or not? */ std::atomic_bool m_hasExited; /* Has our thread finished running yet? */ std::atomic_bool m_hasStarted; /* Has this thread been started yet? (call to pthread_create was made but pthread might not be running yet) */ #ifndef __linux__ /* Windows specific stuff */ HANDLE m_handle; DWORD m_threadId; #else pthread_t m_pthread; bool m_alreadyJoined; /* Already called pthread_join; calling a second time is undefined behavior */ bool m_sendSignalOnStop; /* Should we send a signal to this thread when someone calls Stop() or StopAndWait() on it? Only set this to true if you have a signal handler installed or it will cause a seg fault in this thread due to an unhandled exception. */ #endif std::mutex m_mutex; /* Mutex used for m_stopCond */ std::condition_variable m_stopCond; /* Condition used to signal that it's time to stop */ std::string m_threadName; /* Textual name of this thread that will appear in gdb */ public: /*************************************************************************/ /* * Constructor * * sendSignalOnStop IN: Should we send a signal to this thread when someone calls Stop() or StopAndWait() on it? Only set this to true if you have a signal handler installed for signal DCGM_THREAD_SIGNUM or it will cause a seg fault in this thread due to an unhandled. exception. Alternatively, you can call DcgmThread::InstallSignalHandler() to mitigate this. threadName IN: Text name for this thread that will appear in GDB and other debugging tools. */ DcgmThread(bool sendSignalOnStop = false, std::string threadName = ""); /*************************************************************************/ /* * Destructor (virtual to satisfy ancient compiler) */ virtual ~DcgmThread(); /*************************************************************************/ /* * Static method for getting the current thread's thread ID on linux/windows * */ static unsigned long GetTid(); /*************************************************************************/ /* * Signal this thread that it should stop at its earliest convenience * * This will invoke the OnStop() method of your derived class if you've * implemented it. */ void Stop(); /*************************************************************************/ /* * Terminate this thread using OS calls to stop it in its tracks */ void Kill(); /*************************************************************************/ /* * Spawn the separate thread and call its run() method * * RETURNS: 0 if OK * !0 on error */ int Start(); /*************************************************************************/ /* * Wait for this thread to exit. Stop() will be called on this * thread before waiting to ask the thread to stop * * timeoutMs IN: Milliseconds to wait for the thread to stop before returning * 0=forever * * RETURNS: 0 if the thread is no longer running * 1 if the thread is still running after timeoutMs */ int StopAndWait(int timeoutMs); /*************************************************************************/ int Wait(int timeoutMs); /* * Wait for this thread to exit. Call StopAndWait() if you actually want to * signal the thread to quit * * timeoutMs IN: Milliseconds to wait for the thread to stop before returning * 0=forever * * RETURNS: 0 if the thread is no longer running * 1 if the thread is still running after timeoutMs */ /*************************************************************************/ /* * Call this method from within your run callback to see if you have * been signaled to stop or not * * 0 = No. Keep running * !0 = Yes. Stop running */ int ShouldStop(); /*************************************************************************/ /* * Implement this virtual method within your class to be run * from the separate thread that is created. * * RETURNS: Nothing. */ virtual void run(void) = 0; /*************************************************************************/ /* * Internal method that only need to be public to satisfy C++ */ void RunInternal(); /*************************************************************************/ /* * Sleep for a specified time * * How long to sleep in microseconds (at least). This will return * immediately if ShouldStop() is true */ void Sleep(long long howLongUsec); /*************************************************************************/ /* * Method to check if the this thread has run yet * * RETURNS: 1 if the thread has started processing * 0 If the thread has not run yet */ int HasRun(); /*************************************************************************/ /* * Method to send a signal to this thread. This can be used to wake * up a thread that's sleeping inside a poll, select..etc. * * WARNING: if you do not have a signal handler installed in your process, * this will cause a segfault in the receiving thread. * * signum IN Signal to send (SIGHUP, SIGUSR1..etc). See signal.h * * RETURNS: Nothing */ void SendSignal(int signum); /*************************************************************************/ /* * Method to check if the this thread has exited * * RETURNS: 1 if the thread has exited * 0 If the thread has not exited yet */ int HasExited(); /*************************************************************************/ /* * Method to install a signal handler for DCGM_THREAD_SIGNUM if one isn't * already installed. * * Note: This routine is not thread safe. * * RETURNS: Nothing. */ static void InstallSignalHandler(); /*************************************************************************/ /* * Implement this virtual method within your derived class if you want a * notification when Stop() gets called on your thread. This allows you to * do any custom signalling to wake your thread up. * * RETURNS: Nothing. */ virtual void OnStop(void) {} private: void resetStatusFlags(); }; #endif /* DCGMTHREAD_H_ */

34.139241

110

0.516376

9a67eaaa37f78c626c42c7d37b5621dbc036523f

1,633

h

C

shill/dbus/supplicant_bss_proxy.h

ascii33/platform2

b78891020724e9ff26b11ca89c2a53f949e99748

[ "BSD-3-Clause" ]

null

shill/dbus/supplicant_bss_proxy.h

ascii33/platform2

b78891020724e9ff26b11ca89c2a53f949e99748

[ "BSD-3-Clause" ]

null

shill/dbus/supplicant_bss_proxy.h

ascii33/platform2

b78891020724e9ff26b11ca89c2a53f949e99748

[ "BSD-3-Clause" ]

null

// Copyright 2018 The Chromium OS Authors. All rights reserved. // Use of this source code is governed by a BSD-style license that can be // found in the LICENSE file. #ifndef SHILL_DBUS_SUPPLICANT_BSS_PROXY_H_ #define SHILL_DBUS_SUPPLICANT_BSS_PROXY_H_ #include <memory> #include <string> #include "shill/data_types.h" #include "shill/refptr_types.h" #include "shill/supplicant/supplicant_bss_proxy_interface.h" #include "supplicant/dbus-proxies.h" namespace shill { class WiFiEndpoint; class SupplicantBSSProxy : public SupplicantBSSProxyInterface { public: SupplicantBSSProxy(const scoped_refptr<dbus::Bus>& bus, const RpcIdentifier& object_path, WiFiEndpoint* wifi_endpoint); SupplicantBSSProxy(const SupplicantBSSProxy&) = delete; SupplicantBSSProxy& operator=(const SupplicantBSSProxy&) = delete; ~SupplicantBSSProxy() override; private: // Signal handlers. void PropertiesChanged(const brillo::VariantDictionary& properties); // Called when signal is connected to the ObjectProxy. void OnSignalConnected(const std::string& interface_name, const std::string& signal_name, bool success); std::unique_ptr<fi::w1::wpa_supplicant1::BSSProxy> bss_proxy_; // We use a bare pointer, because each SupplcantBSSProxy is // owned (using a unique_ptr) by a WiFiEndpoint. This means that if // |wifi_endpoint_| is invalid, then so is |this|. WiFiEndpoint* wifi_endpoint_; base::WeakPtrFactory<SupplicantBSSProxy> weak_factory_{this}; }; } // namespace shill #endif // SHILL_DBUS_SUPPLICANT_BSS_PROXY_H_

32.019608

73

0.73913

9acfd5123867244787e3857b1285bceb1791216c

244

h

C

inc/Activity2.h

saipoor/Activity1

7160455a8469a0b108c5f03d363b0b2357e74119

[ "Apache-2.0" ]

null

inc/Activity2.h

saipoor/Activity1

7160455a8469a0b108c5f03d363b0b2357e74119

[ "Apache-2.0" ]

null

inc/Activity2.h

saipoor/Activity1

7160455a8469a0b108c5f03d363b0b2357e74119

[ "Apache-2.0" ]

null

#ifndef ACTIVITY2_H_INCLUDED #define ACTIVITY2_H_INCLUDED /** * @brief ADC initialisation * * */ void ADC_initialize(void); /** * @brief Reads input from one of the channel * * @return uint16_t */ uint16_t ReadADC(uint8_t); #endif

14.352941

45

0.70082

82b368dbcefc5f604fef14457258c81493a5241c

2,733

h

C

sources/include/trace/events/mmc.h

fuldaros/paperplane_kernel_wileyfox-spark

bea244880d2de50f4ad14bb6fa5777652232c033

[ "Apache-2.0" ]

15

2018-04-02T12:41:27.000Z

2021-06-26T13:13:43.000Z

sources/include/trace/events/mmc.h

fuldaros/paperplane_kernel_wileyfox-spark

bea244880d2de50f4ad14bb6fa5777652232c033

[ "Apache-2.0" ]

1

2017-05-26T04:28:56.000Z

2017-08-13T12:12:31.000Z

sources/include/trace/events/mmc.h

fuldaros/paperplane_kernel_wileyfox-spark

bea244880d2de50f4ad14bb6fa5777652232c033

[ "Apache-2.0" ]

3

2017-06-24T20:23:09.000Z

2018-03-25T04:30:11.000Z

/* * Copyright (C) 2013 Google, Inc. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * */ #undef TRACE_SYSTEM #define TRACE_SYSTEM mmc #if !defined(_TRACE_MMC_H) || defined(TRACE_HEADER_MULTI_READ) #define _TRACE_MMC_H #include <linux/tracepoint.h> #include <linux/mmc/mmc.h> #include <linux/mmc/core.h> /* * Unconditional logging of mmc block erase operations, * including cmd, address, size */ DECLARE_EVENT_CLASS(mmc_blk_erase_class, TP_PROTO(unsigned int cmd, unsigned int addr, unsigned int size), TP_ARGS(cmd, addr, size), TP_STRUCT__entry( __field(unsigned int, cmd) __field(unsigned int, addr) __field(unsigned int, size) ), TP_fast_assign( __entry->cmd = cmd; __entry->addr = addr; __entry->size = size; ), TP_printk("cmd=%u,addr=0x%08x,size=0x%08x", __entry->cmd, __entry->addr, __entry->size) ); DEFINE_EVENT(mmc_blk_erase_class, mmc_blk_erase_start, TP_PROTO(unsigned int cmd, unsigned int addr, unsigned int size), TP_ARGS(cmd, addr, size)); DEFINE_EVENT(mmc_blk_erase_class, mmc_blk_erase_end, TP_PROTO(unsigned int cmd, unsigned int addr, unsigned int size), TP_ARGS(cmd, addr, size)); /* * Logging of start of read or write mmc block operation, * including cmd, address, size */ DECLARE_EVENT_CLASS(mmc_blk_rw_class, TP_PROTO(unsigned int cmd, unsigned int addr, struct mmc_data *data), TP_ARGS(cmd, addr, data), TP_STRUCT__entry( __field(unsigned int, cmd) __field(unsigned int, addr) __field(unsigned int, size) ), TP_fast_assign( __entry->cmd = cmd; __entry->addr = addr; __entry->size = data->blocks; ), TP_printk("cmd=%u,addr=0x%08x,size=0x%08x", __entry->cmd, __entry->addr, __entry->size) ); DEFINE_EVENT_CONDITION(mmc_blk_rw_class, mmc_blk_rw_start, TP_PROTO(unsigned int cmd, unsigned int addr, struct mmc_data *data), TP_ARGS(cmd, addr, data), TP_CONDITION(((cmd == MMC_READ_MULTIPLE_BLOCK) || (cmd == MMC_WRITE_MULTIPLE_BLOCK)) && data)); DEFINE_EVENT_CONDITION(mmc_blk_rw_class, mmc_blk_rw_end, TP_PROTO(unsigned int cmd, unsigned int addr, struct mmc_data *data), TP_ARGS(cmd, addr, data), TP_CONDITION(((cmd == MMC_READ_MULTIPLE_BLOCK) || (cmd == MMC_WRITE_MULTIPLE_BLOCK)) && data)); #endif /* _TRACE_MMC_H */ /* This part must be outside protection */ #include <trace/define_trace.h>

29.706522

71

0.732894

aaad63215f4aa0ff7fb4539a48e954bcd0762191

4,298

c

C

wxWidgets-2.9.1/src/tiff/tools/ycbcr.c

gamekit-developers/gamekit

74c896af5826ebe8fb72f2911015738f38ab7bb2

[ "Zlib", "MIT" ]

241

2015-01-04T00:36:58.000Z

2022-01-06T19:19:23.000Z

wxWidgets-2.9.1/src/tiff/tools/ycbcr.c

gamekit-developers/gamekit

74c896af5826ebe8fb72f2911015738f38ab7bb2

[ "Zlib", "MIT" ]

10

2015-07-10T18:27:17.000Z

2019-06-26T20:59:59.000Z

wxWidgets-2.9.1/src/tiff/tools/ycbcr.c

gamekit-developers/gamekit

74c896af5826ebe8fb72f2911015738f38ab7bb2

[ "Zlib", "MIT" ]

82

2015-01-25T18:02:35.000Z

2022-03-05T12:28:17.000Z

float ycbcrCoeffs[3] = { .299, .587, .114 }; /* default coding range is CCIR Rec 601-1 with no headroom/footroom */ unsigned long refBlackWhite[6] = { 0, 255, 128, 255, 128, 255 }; #define LumaRed ycbcrCoeffs[0] #define LumaGreen ycbcrCoeffs[1] #define LumaBlue ycbcrCoeffs[2] long eRtotal = 0; long eGtotal = 0; long eBtotal = 0; long preveRtotal = 0; long preveGtotal = 0; long preveBtotal = 0; unsigned long AbseRtotal = 0; unsigned long AbseGtotal = 0; unsigned long AbseBtotal = 0; unsigned long eCodes = 0; unsigned long preveCodes = 0; unsigned long eBits = 0; unsigned long preveBits = 0; static void setupLumaTables(); static int abs(int v) { return (v < 0 ? -v : v); } static double pct(int v,double range) { return (v*100. / range); } static void check(int R, int G, int B); float D1, D2; float D3, D4; float D5, D6; int main(int argc, char** argv) { int R, G, B; if (argc > 1) { refBlackWhite[0] = 16; refBlackWhite[1] = 235; refBlackWhite[2] = 128; refBlackWhite[3] = 240; refBlackWhite[4] = 128; refBlackWhite[5] = 240; } D3 = 2 - 2*LumaRed; D4 = 2 - 2*LumaBlue; D1 = 1. / D3; D2 = 1. / D4; D5 = D3*LumaRed / LumaGreen; D6 = D4*LumaBlue / LumaGreen; setupLumaTables(); for (R = 0; R < 256; R++) { for (G = 0; G < 256; G++) for (B = 0; B < 256; B++) check(R, G, B); printf("[%3u] c %u/%u b %u/%u (R %u/%d/%u G %u/%d/%u B %u/%d/%u)\n" , R , eCodes - preveCodes, eCodes , eBits - preveBits, eBits , abs(AbseRtotal - preveRtotal), eRtotal , AbseRtotal , abs(AbseGtotal - preveGtotal), eGtotal , AbseGtotal , abs(AbseBtotal - preveBtotal), eBtotal , AbseBtotal ); preveRtotal = AbseRtotal; preveGtotal = AbseGtotal; preveBtotal = AbseBtotal; preveCodes = eCodes; preveBits = eBits; } printf("%u total codes\n", 256*256*256); printf("total error: %u codes %u bits (R %d/%u G %d/%u B %d/%u)\n" , eCodes , eBits , eRtotal , AbseRtotal , eGtotal , AbseGtotal , eBtotal , AbseBtotal ); return (0); } float *lumaRed; float *lumaGreen; float *lumaBlue; static float* setupLuma(float c) { float *v = (float *)_TIFFmalloc(256 * sizeof (float)); int i; for (i = 0; i < 256; i++) v[i] = c * i; return (v); } static void setupLumaTables(void) { lumaRed = setupLuma(LumaRed); lumaGreen = setupLuma(LumaGreen); lumaBlue = setupLuma(LumaBlue); } static unsigned V2Code(float f, unsigned long RB, unsigned long RW, int CR) { unsigned int c = (unsigned int)((((f)*(RW-RB)/CR)+RB)+.5); return (c > 255 ? 255 : c); } #define Code2V(c, RB, RW, CR) ((((c)-(int)RB)*(float)CR)/(float)(RW-RB)) #define CLAMP(f,min,max) \ (int)((f)+.5 < (min) ? (min) : (f)+.5 > (max) ? (max) : (f)+.5) static void check(int R, int G, int B) { float Y, Cb, Cr; int iY, iCb, iCr; float rY, rCb, rCr; float rR, rG, rB; int eR, eG, eB; Y = lumaRed[R] + lumaGreen[G] + lumaBlue[B]; Cb = (B - Y)*D2; Cr = (R - Y)*D1; iY = V2Code(Y, refBlackWhite[0], refBlackWhite[1], 255); iCb = V2Code(Cb, refBlackWhite[2], refBlackWhite[3], 127); iCr = V2Code(Cr, refBlackWhite[4], refBlackWhite[5], 127); rCb = Code2V(iCb, refBlackWhite[2], refBlackWhite[3], 127); rCr = Code2V(iCr, refBlackWhite[4], refBlackWhite[5], 127); rY = Code2V(iY, refBlackWhite[0], refBlackWhite[1], 255); rR = rY + rCr*D3; rB = rY + rCb*D4; rG = rY - rCb*D6 - rCr*D5; eR = R - CLAMP(rR,0,255); eG = G - CLAMP(rG,0,255); eB = B - CLAMP(rB,0,255); if (abs(eR) > 1 || abs(eG) > 1 || abs(eB) > 1) { printf("R %u G %u B %u", R, G, B); printf(" Y %g Cb %g Cr %g", Y, Cb, Cr); printf(" iY %u iCb %u iCr %u", iY, iCb, iCr); printf("\n -> Y %g Cb %g Cr %g", rY, rCb, rCr); printf(" R %g (%u) G %g (%u) B %g (%u) E=[%d %d %d])\n" , rR, CLAMP(rR,0,255) , rG, CLAMP(rG,0,255) , rB, CLAMP(rB,0,255) , eR, eG, eB ); } eRtotal += eR; eGtotal += eG; eBtotal += eB; AbseRtotal += abs(eR); AbseGtotal += abs(eG); AbseBtotal += abs(eB); if (eR | eG | eB) eCodes++; eBits += abs(eR) + abs(eG) + abs(eB); }

26.530864

73

0.558399

d2df54f36850fac0e9c7a954520c67599ed3b367

2,415

h

C

detox/ios/Detox/Utilities/NSObject+DetoxUtils.h

MateusAndrade/Detox

166e41c3e0e7f34295d1b3da3cd7799dce01897d

[ "MIT" ]

null

detox/ios/Detox/Utilities/NSObject+DetoxUtils.h

MateusAndrade/Detox

166e41c3e0e7f34295d1b3da3cd7799dce01897d

[ "MIT" ]

null

detox/ios/Detox/Utilities/NSObject+DetoxUtils.h

MateusAndrade/Detox

166e41c3e0e7f34295d1b3da3cd7799dce01897d

[ "MIT" ]

null

// // NSObject+DetoxUtils.h // Detox // // Created by Leo Natan on 11/12/20. // Copyright © 2020 Wix. All rights reserved. // #import <Foundation/Foundation.h> NS_ASSUME_NONNULL_BEGIN BOOL __DTXDoulbeEqualToDouble(double a, double b); BOOL __DTXPointEqualToPoint(CGPoint a, CGPoint b); inline __attribute__((__always_inline__)) static double LNLinearInterpolate(CGFloat from, CGFloat to, CGFloat p) { return from + p * (to - from); } @interface NSObject (DetoxUtils) @property (nonatomic, readonly, strong) NSString* accessibilityIdentifier; @property (nonatomic, readonly, nullable) id accessibilityContainer; @property (nonatomic, readonly) UIView* dtx_view; - (CGPoint)dtx_convertRelativePointToViewCoordinateSpace:(CGPoint)relativePoint; @property (nonatomic, readonly) CGRect dtx_bounds; @property (nonatomic, readonly) CGRect dtx_contentBounds; @property (nonatomic, readonly) CGRect dtx_visibleBounds; - (BOOL)dtx_isVisible; - (void)dtx_assertVisibleWithPercent:(nullable NSNumber *)percent; - (BOOL)dtx_isVisibleAtRect:(CGRect)rect percent:(nullable NSNumber *)percent error:(NSError* __strong __nullable * __nullable)error; - (void)dtx_assertVisible; - (void)dtx_assertVisibleAtRect:(CGRect)rect percent:(nullable NSNumber *)percent; - (BOOL)dtx_isFocused; @property (nonatomic, readonly) BOOL dtx_isHittable; - (BOOL)dtx_isHittableAtPoint:(CGPoint)viewPoint error:(NSError* __strong __nullable * __nullable)error; - (void)dtx_assertHittable; - (void)dtx_assertHittableAtPoint:(CGPoint)point; @property (nonatomic, copy, readonly) NSString* dtx_text; @property (nonatomic, copy, readonly) NSString* dtx_placeholder; @property (nonatomic, readonly) BOOL dtx_isEnabled; - (void)dtx_assertEnabled; @property (nonatomic, readonly, copy) NSString* dtx_shortDescription; @property (nonatomic, readonly) CGRect dtx_accessibilityFrame; @property (nonatomic, readonly) CGRect dtx_safeAreaBounds; @property (nonatomic, readonly) CGPoint dtx_accessibilityActivationPoint; @property (nonatomic, readonly) CGPoint dtx_accessibilityActivationPointInViewCoordinateSpace; @property (nonatomic, readonly, class, copy) NSDictionary<NSString*, id>* dtx_genericElementDebugAttributes; @property (nonatomic, readonly, copy) NSDictionary<NSString*, id>* dtx_attributes; @property (nonatomic, readonly, copy) NSDictionary<NSString*, id>* dtx_elementDebugAttributes; @end NS_ASSUME_NONNULL_END

35

108

0.795859

c56d7f43beb08618a0aba4c7227f50575e5eddb4

4,058

h

C

thirdparty/cgal/CGAL-4.13/include/CGAL/NewKernel_d/Wrapper/Sphere_d.h

st4ll1/dust3d

c1de02f7ddcfdacc730cc96740f8073f87e7818c

[ "MIT" ]

7

2016-12-08T08:12:14.000Z

2019-07-31T18:50:24.000Z

thirdparty/cgal/CGAL-4.13/include/CGAL/NewKernel_d/Wrapper/Sphere_d.h

st4ll1/dust3d

c1de02f7ddcfdacc730cc96740f8073f87e7818c

[ "MIT" ]

26

2018-05-18T22:54:03.000Z

2021-12-16T14:07:00.000Z

thirdparty/cgal/CGAL-4.13/include/CGAL/NewKernel_d/Wrapper/Sphere_d.h

st4ll1/dust3d

c1de02f7ddcfdacc730cc96740f8073f87e7818c

[ "MIT" ]

8

2018-07-18T07:11:52.000Z

2019-12-31T20:27:33.000Z

// Copyright (c) 2014 // INRIA Saclay-Ile de France (France) // // This file is part of CGAL (www.cgal.org); you can redistribute it and/or // modify it under the terms of the GNU Lesser General Public License as // published by the Free Software Foundation; either version 3 of the License, // or (at your option) any later version. // // Licensees holding a valid commercial license may use this file in // accordance with the commercial license agreement provided with the software. // // This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE // WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. // // $URL$ // $Id$ // SPDX-License-Identifier: LGPL-3.0+ // // Author(s) : Marc Glisse #ifndef CGAL_WRAPPER_SPHERE_D_H #define CGAL_WRAPPER_SPHERE_D_H #include <CGAL/representation_tags.h> #include <CGAL/assertions.h> #include <boost/type_traits.hpp> #include <CGAL/Kernel/Return_base_tag.h> #include <CGAL/Dimension.h> #ifndef CGAL_CXX11 #include <boost/preprocessor/repetition.hpp> #endif #include <boost/utility/result_of.hpp> namespace CGAL { namespace Wrap { template <class R_> class Sphere_d : public Get_type<typename R_::Kernel_base, Sphere_tag>::type { typedef typename Get_type<R_, FT_tag>::type FT_; typedef typename R_::Kernel_base Kbase; typedef typename Get_type<R_, Point_tag>::type Point_; typedef typename Get_functor<Kbase, Construct_ttag<Sphere_tag> >::type CSBase; typedef typename Get_functor<Kbase, Center_of_sphere_tag>::type COSBase; typedef typename Get_functor<Kbase, Squared_radius_tag>::type SRBase; typedef Sphere_d Self; CGAL_static_assertion((boost::is_same<Self, typename Get_type<R_, Sphere_tag>::type>::value)); public: typedef Tag_true Is_wrapper; typedef typename R_::Default_ambient_dimension Ambient_dimension; typedef typename Increment_dimension<Ambient_dimension,-1>::type Feature_dimension; typedef typename Get_type<Kbase, Sphere_tag>::type Rep; const Rep& rep() const { return *this; } Rep& rep() { return *this; } typedef R_ R; #ifdef CGAL_CXX11 template<class...U,class=typename std::enable_if<!std::is_same<std::tuple<typename std::decay<U>::type...>,std::tuple<Sphere_d> >::value>::type> explicit Sphere_d(U&&...u) : Rep(CSBase()(std::forward<U>(u)...)){} // // called from Construct_point_d // template<class...U> explicit Point_d(Eval_functor&&,U&&...u) // : Rep(Eval_functor(), std::forward<U>(u)...){} template<class F,class...U> explicit Sphere_d(Eval_functor&&,F&&f,U&&...u) : Rep(std::forward<F>(f)(std::forward<U>(u)...)){} #if 0 // the new standard may make this necessary Point_d(Point_d const&)=default; Point_d(Point_d &);//=default; Point_d(Point_d &&)=default; #endif // try not to use these Sphere_d(Rep const& v) : Rep(v) {} Sphere_d(Rep& v) : Rep(static_cast<Rep const&>(v)) {} Sphere_d(Rep&& v) : Rep(std::move(v)) {} #else Sphere_d() : Rep(CSBase()()) {} Sphere_d(Rep const& v) : Rep(v) {} // try not to use it #define CGAL_CODE(Z,N,_) template<BOOST_PP_ENUM_PARAMS(N,class T)> \ explicit Sphere_d(BOOST_PP_ENUM_BINARY_PARAMS(N,T,const&t)) \ : Rep(CSBase()( \ BOOST_PP_ENUM_PARAMS(N,t))) {} \ \ template<class F,BOOST_PP_ENUM_PARAMS(N,class T)> \ Sphere_d(Eval_functor,F const& f,BOOST_PP_ENUM_BINARY_PARAMS(N,T,const&t)) \ : Rep(f(BOOST_PP_ENUM_PARAMS(N,t))) {} /* template<BOOST_PP_ENUM_PARAMS(N,class T)> \ Point_d(Eval_functor,BOOST_PP_ENUM_BINARY_PARAMS(N,T,const&t)) \ : Rep(Eval_functor(), BOOST_PP_ENUM_PARAMS(N,t)) {} */ BOOST_PP_REPEAT_FROM_TO(1,11,CGAL_CODE,_) #undef CGAL_CODE #endif //TODO: if COSBase returns a reference to a base point, cast it to a //reference to a wrapper point. Ugly but should be safe. Point_ center()const{ return Point_(Eval_functor(),COSBase(),rep()); } FT_ squared_radius()const{ return SRBase()(rep()); } }; } //namespace Wrap } //namespace CGAL #endif // CGAL_WRAPPER_SPHERE_D_H

30.742424

173

0.701084

c5945babcbaf9c51424a3d49e500891712f5d7f6

1,167

h

C

connectors/dds4ccm/idl/ndds/ndds_dcps_instance_handleS.h

qinwang13/CIAO

e69add1b5da8e9602bcc85d581ecbf1bd41c49a3

[ "DOC" ]

10

2016-07-20T00:55:50.000Z

2020-10-04T19:07:10.000Z

connectors/dds4ccm/idl/ndds/ndds_dcps_instance_handleS.h

qinwang13/CIAO

e69add1b5da8e9602bcc85d581ecbf1bd41c49a3

[ "DOC" ]

13

2016-09-27T14:08:27.000Z

2020-11-11T10:45:56.000Z

connectors/dds4ccm/idl/ndds/ndds_dcps_instance_handleS.h

qinwang13/CIAO

e69add1b5da8e9602bcc85d581ecbf1bd41c49a3

[ "DOC" ]

12

2016-04-20T09:57:02.000Z

2021-12-24T17:23:45.000Z

// -*- C++ -*- /** * Code generated by the The ACE ORB (TAO) IDL Compiler v1.7.4 * TAO and the TAO IDL Compiler have been developed by: * Center for Distributed Object Computing * Washington University * St. Louis, MO * USA * http://www.cs.wustl.edu/~schmidt/doc-center.html * and * Distributed Object Computing Laboratory * University of California at Irvine * Irvine, CA * USA * http://doc.ece.uci.edu/ * and * Institute for Software Integrated Systems * Vanderbilt University * Nashville, TN * USA * http://www.isis.vanderbilt.edu/ * * Information about TAO is available at: * http://www.dre.vanderbilt.edu/~schmidt/TAO.html **/ // TAO_IDL - Generated from // C:\ACE\latest\ACE_wrappers\TAO\TAO_IDL\be\be_codegen.cpp:471 #ifndef _TAO_IDL_DDS_RTF2_DCPS_I_HANDLES_H_S #define _TAO_IDL_DDS_RTF2_DCPS_I_HANDLES_H_S #include /**/ "ace/pre.h" #include "ndds_dcps_i_handleC.h" #if !defined (ACE_LACKS_PRAGMA_ONCE) # pragma once #endif /* ACE_LACKS_PRAGMA_ONCE */ #include /**/ "ndds_skel_export.h" #include /**/ "ace/post.h" #endif /* ifndef */

24.829787

63

0.656384

d03f45e6af7e5812130492e5e373e04adabc53f0

2,431

c

C

build/glibc-1.09/sysdeps/unix/opendir.c

VivekMaran27/How-to-install-SimpleScalar-on-Ubuntu

2c0d4f4d41087508b304664fe1a6da6f86fb830b

[ "MIT" ]

null

build/glibc-1.09/sysdeps/unix/opendir.c

VivekMaran27/How-to-install-SimpleScalar-on-Ubuntu

2c0d4f4d41087508b304664fe1a6da6f86fb830b

[ "MIT" ]

null

build/glibc-1.09/sysdeps/unix/opendir.c

VivekMaran27/How-to-install-SimpleScalar-on-Ubuntu

2c0d4f4d41087508b304664fe1a6da6f86fb830b

[ "MIT" ]

null

/* Copyright (C) 1991, 1992, 1993, 1994 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or modify it under the terms of the GNU Library General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. The GNU C Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public License for more details. You should have received a copy of the GNU Library General Public License along with the GNU C Library; see the file COPYING.LIB. If not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <ansidecl.h> #include <errno.h> #include <limits.h> #include <stddef.h> #include <stdlib.h> #include <dirent.h> #include <fcntl.h> #include <sys/types.h> #include <sys/stat.h> #include <unistd.h> #include <stdio.h> #include "direct.h" /* This file defines `struct direct'. */ /* Open a directory stream on NAME. */ DIR * DEFUN(opendir, (name), CONST char *name) { DIR *dirp; struct stat statbuf; int fd; if (name[0] == '\0') { /* POSIX.1-1990 says an empty name gets ENOENT; but `open' might like it fine. */ errno = ENOENT; return NULL; } fd = __open (name, O_RDONLY); if (fd < 0) return NULL; if (fcntl (fd, F_SETFD, FD_CLOEXEC) < 0) goto lose; if (fstat (fd, &statbuf) < 0) goto lose; if (! S_ISDIR (statbuf.st_mode)) { errno = ENOTDIR; goto lose; } dirp = (DIR *) calloc (1, sizeof (DIR) + NAME_MAX); /* Zero-fill. */ if (dirp == NULL) lose: { int save = errno; (void) __close (fd); errno = save; return NULL; } #ifdef _STATBUF_ST_BLKSIZE if (statbuf.st_blksize < sizeof (struct direct)) dirp->__allocation = sizeof (struct direct); else dirp->__allocation = statbuf.st_blksize; #else dirp->__allocation = (BUFSIZ < sizeof (struct direct) ? sizeof (struct direct) : BUFSIZ); #endif dirp->__data = (char *) malloc (dirp->__allocation); if (dirp->__data == NULL) { int save = errno; free ((PTR) dirp); (void) __close (fd); errno = save; return NULL; } dirp->__fd = fd; return dirp; }

25.322917

71

0.655697

b7c0cbb57e3fd417a000263c4767f3415c7b8faf

3,207

h

C

CommonLibF4/include/RE/Bethesda/MessageMenuManager.h

shad0wshayd3/CommonLibF4

5d875ec4ac6a6f6307910fb09aeef3dd5ff25fc7

[ "MIT" ]

1

2021-12-19T18:27:00.000Z

CommonLibF4/include/RE/Bethesda/MessageMenuManager.h

shad0wshayd3/CommonLibF4

5d875ec4ac6a6f6307910fb09aeef3dd5ff25fc7

[ "MIT" ]

null

CommonLibF4/include/RE/Bethesda/MessageMenuManager.h

shad0wshayd3/CommonLibF4

5d875ec4ac6a6f6307910fb09aeef3dd5ff25fc7

[ "MIT" ]

null

#pragma once #include "RE/Bethesda/BSLock.h" #include "RE/Bethesda/BSStringT.h" #include "RE/Bethesda/BSTArray.h" #include "RE/Bethesda/BSTSingleton.h" #include "RE/Bethesda/BSTSmartPointer.h" #include "RE/Bethesda/UIMessage.h" namespace RE { enum class UI_DEPTH_PRIORITY; enum class WARNING_TYPES { kDefault, kSystem, kCombat, kAnimation, kAI, kScripts, kSaveLoad, kDialogue, kQuests, kPackages, kEditor, kModels, kTextures, kPlugins, kMasterFile, kForms, kMagic, kShaders, kRendering, kPathfinding, kMenus, kAudio, kCells, kHavok, kFaceGen, kWater, kInGameMessage, kMemory, kPerformance, kLootJoy, kVATS, kDismember, kCompanion, kWorkshop, }; class alignas(0x10) IMessageBoxCallback : public BSIntrusiveRefCounted // 00 { public: static constexpr auto RTTI{ RTTI::IMessageBoxCallback }; static constexpr auto VTABLE{ VTABLE::IMessageBoxCallback }; virtual ~IMessageBoxCallback() = default; // 00 // add virtual void operator()(std::uint8_t a_buttonIdx) = 0; // 01 }; static_assert(sizeof(IMessageBoxCallback) == 0x10); class __declspec(novtable) MessageBoxData : public IUIMessageData // 00 { public: static constexpr auto RTTI{ RTTI::MessageBoxData }; static constexpr auto VTABLE{ VTABLE::MessageBoxData }; // members BSStringT<char> headerText; // 18 BSStringT<char> bodyText; // 28 BSTArray<BSStringT<char>> buttonText; // 38 stl::enumeration<WARNING_TYPES, std::uint32_t> warningContext; // 50 BSTSmartPointer<IMessageBoxCallback> callback; // 58 stl::enumeration<UI_DEPTH_PRIORITY, std::uint32_t> menuDepth; // 60 bool modal; // 64 bool ensureUnique; // 65 }; static_assert(sizeof(MessageBoxData) == 0x68); class MessageMenuManager : public BSTSingletonSDM<MessageMenuManager> // 00 { public: [[nodiscard]] static MessageMenuManager* GetSingleton() { REL::Relocation<MessageMenuManager**> singleton{ REL::ID(959572) }; return *singleton; } void Create( const char* a_headerText, const char* a_bodyText, IMessageBoxCallback* a_callback, WARNING_TYPES a_warningContext, const char* a_button1Text = nullptr, const char* a_button2Text = nullptr, const char* a_button3Text = nullptr, const char* a_button4Text = nullptr, bool a_ensureUnique = false) { using func_t = decltype(&MessageMenuManager::Create); REL::Relocation<func_t> func{ REL::ID(89563) }; return func(this, a_headerText, a_bodyText, a_callback, a_warningContext, a_button1Text, a_button2Text, a_button3Text, a_button4Text, a_ensureUnique); } // members BSReadWriteLock messageRWLock; // 04 BSTArray<MessageBoxData*> messages; // 10 stl::enumeration<WARNING_TYPES, std::uint32_t> currentWarningContext; // 28 bool disabledWarnings[34]; // 2C }; static_assert(sizeof(MessageMenuManager) == 0x50); }

26.94958

153

0.649205

315725999b8e847a1ad64742c9c728c8d5e844b2

1,637

c

C

pith/search.c

duke-m/alpine

6278103d269e6882bb26a770c1f25bcd3e20ff13

[ "Apache-2.0" ]

null

pith/search.c

duke-m/alpine

6278103d269e6882bb26a770c1f25bcd3e20ff13

[ "Apache-2.0" ]

null

pith/search.c

duke-m/alpine

6278103d269e6882bb26a770c1f25bcd3e20ff13

[ "Apache-2.0" ]

1

2020-05-20T11:58:08.000Z

#if !defined(lint) && !defined(DOS) static char rcsid[] = "$Id: search.c 854 2007-12-07 17:44:43Z hubert@u.washington.edu $"; #endif /* * ======================================================================== * Copyright 2013-2016 Eduardo Chappa * Copyright 2006 University of Washington * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * ======================================================================== */ #include "../pith/headers.h" #include "../pith/search.h" SEARCHSET * build_searchset(MAILSTREAM *stream) { long i, run; SEARCHSET *ret_s = NULL, **set; MESSAGECACHE *mc; if(!stream) return(NULL); for(i = 1L, set = &ret_s, run = 0L; i <= stream->nmsgs; i++){ if(!((mc = mail_elt(stream, i)) && mc->sequence)){ /* end of run */ if(run){ /* run in progress */ set = &(*set)->next; run = 0L; } } else if(run++){ /* next in run */ (*set)->last = i; } else{ /* start of new run */ *set = mail_newsearchset(); /* * Leave off (*set)->last until we get more than one msg * in the run, to avoid 607:607 in SEARCH. */ (*set)->first = (*set)->last = i; } } return(ret_s); } int in_searchset(SEARCHSET *srch, long unsigned int num) { SEARCHSET *s; unsigned long i; if(srch) for(s = srch; s; s = s->next) for(i = s->first; i <= s->last; i++){ if(i == num) return 1; } return 0; }

22.736111

89

0.515577

2eae2c769b5612b4565d81b167d4dd06ca2dc73c

1,575

c

C

src/interfaces/ecpg/preproc/c_keywords.c

YangHao666666/hawq

10cff8350f1ba806c6fec64eb67e0e6f6f24786c

[ "Artistic-1.0-Perl", "ISC", "bzip2-1.0.5", "TCL", "Apache-2.0", "BSD-3-Clause-No-Nuclear-License-2014", "MIT", "PostgreSQL", "BSD-3-Clause" ]

450

2015-09-05T09:12:51.000Z

2018-08-30T01:45:36.000Z

src/interfaces/ecpg/preproc/c_keywords.c

YangHao666666/hawq

10cff8350f1ba806c6fec64eb67e0e6f6f24786c

[ "Artistic-1.0-Perl", "ISC", "bzip2-1.0.5", "TCL", "Apache-2.0", "BSD-3-Clause-No-Nuclear-License-2014", "MIT", "PostgreSQL", "BSD-3-Clause" ]

1,274

2015-09-22T20:06:16.000Z

2018-08-31T22:14:00.000Z

src/interfaces/ecpg/preproc/c_keywords.c

YangHao666666/hawq

10cff8350f1ba806c6fec64eb67e0e6f6f24786c

[ "Artistic-1.0-Perl", "ISC", "bzip2-1.0.5", "TCL", "Apache-2.0", "BSD-3-Clause-No-Nuclear-License-2014", "MIT", "PostgreSQL", "BSD-3-Clause" ]

278

2015-09-21T19:15:06.000Z

2018-08-31T00:36:51.000Z

/*------------------------------------------------------------------------- * * keywords.c * lexical token lookup for reserved words in postgres embedded SQL * * $PostgreSQL: pgsql/src/interfaces/ecpg/preproc/c_keywords.c,v 1.23 2009/06/11 14:49:13 momjian Exp $ * § *------------------------------------------------------------------------- */ #include "postgres_fe.h" #include <ctype.h> #include "extern.h" #include "preproc.h" /* * List of (keyword-name, keyword-token-value) pairs. * * !!WARNING!!: This list must be sorted, because binary * search is used to locate entries. */ static const ScanKeyword ScanCKeywords[] = { /* name, value, category */ /* * category is not needed in ecpg, it is only here so we can share the * data structure with the backend */ {"VARCHAR", VARCHAR, 0}, {"auto", S_AUTO, 0}, {"bool", SQL_BOOL, 0}, {"char", CHAR_P, 0}, {"const", S_CONST, 0}, {"enum", ENUM_P, 0}, {"extern", S_EXTERN, 0}, {"float", FLOAT_P, 0}, {"hour", HOUR_P, 0}, {"int", INT_P, 0}, {"long", SQL_LONG, 0}, {"minute", MINUTE_P, 0}, {"month", MONTH_P, 0}, {"register", S_REGISTER, 0}, {"second", SECOND_P, 0}, {"short", SQL_SHORT, 0}, {"signed", SQL_SIGNED, 0}, {"static", S_STATIC, 0}, {"struct", SQL_STRUCT, 0}, {"to", TO, 0}, {"typedef", S_TYPEDEF, 0}, {"union", UNION, 0}, {"unsigned", SQL_UNSIGNED, 0}, {"varchar", VARCHAR, 0}, {"volatile", S_VOLATILE, 0}, {"year", YEAR_P, 0}, }; const ScanKeyword * ScanCKeywordLookup(const char *text) { return DoLookup(text, &ScanCKeywords[0], endof(ScanCKeywords) - 1); }

25

103

0.570159

2c385d136d9f5c995bfcd3aafd66ffb9b3037255

4,962

h

C

CallTraceForWeChat/CallTraceForWeChat/WeChat_Headers/EJBindingGfx.h

ceekay1991/CallTraceForWeChat

5767cb6f781821b6bf9facc8c87e58e15fa88541

[ "MIT" ]

30

2020-03-22T12:30:21.000Z

2022-02-09T08:49:13.000Z

CallTraceForWeChat/CallTraceForWeChat/WeChat_Headers/EJBindingGfx.h

ceekay1991/CallTraceForWeChat

5767cb6f781821b6bf9facc8c87e58e15fa88541

[ "MIT" ]

null

CallTraceForWeChat/CallTraceForWeChat/WeChat_Headers/EJBindingGfx.h

ceekay1991/CallTraceForWeChat

5767cb6f781821b6bf9facc8c87e58e15fa88541

[ "MIT" ]

8

2020-03-22T12:30:23.000Z

2020-09-22T04:01:47.000Z

// // Generated by class-dump 3.5 (64 bit) (Debug version compiled Sep 17 2017 16:24:48). // // class-dump is Copyright (C) 1997-1998, 2000-2001, 2004-2015 by Steve Nygard. // #import "EJBindingBase.h" @class EJCanvasContextWebGL; @interface EJBindingGfx : EJBindingBase { EJCanvasContextWebGL *renderingContext; struct GfxHandler _handler; struct _sg_state_t _sg; struct map<unsigned long long, OpaqueJSValue *, std::__1::less<unsigned long long>, std::__1::allocator<std::__1::pair<const unsigned long long, OpaqueJSValue *>>> _textureIndexToGfxHandler; } + (void *)_ptr_to_func_queryGlyphBitmapInfo; + (void *)_ptr_to_func_queryFeatures; + (void *)_ptr_to_func_commit; + (void *)_ptr_to_func_endPass; + (void *)_ptr_to_func_draw; + (void *)_ptr_to_func_applyUniforms; + (void *)_ptr_to_func_applyBindings; + (void *)_ptr_to_func_applyPipeline; + (void *)_ptr_to_func_beginPass; + (void *)_ptr_to_func_beginDefaultPass; + (void *)_ptr_to_func_makePipeline; + (void *)_ptr_to_func_updateImage; + (void *)_ptr_to_func_makeImage; + (void *)_ptr_to_func_makeShader; + (void *)_ptr_to_func_updateBuffer; + (void *)_ptr_to_func_makeBuffer; + (void *)_ptr_to_func_makePass; + (void *)_ptr_to_func_createNativeBuffer; - (id).cxx_construct; - (void).cxx_destruct; - (struct OpaqueJSValue *)_func_queryGlyphBitmapInfo:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_queryFeatures:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_commit:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_endPass:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_draw:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_applyUniforms:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_applyBindings:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_applyPipeline:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_beginPass:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_beginDefaultPass:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_makePipeline:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_updateImage:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_makeImage:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_makeShader:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_updateBuffer:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_makeBuffer:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_makePass:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (struct OpaqueJSValue *)_func_createNativeBuffer:(struct OpaqueJSContext *)arg1 argc:(unsigned long long)arg2 argv:(const struct OpaqueJSValue **)arg3 exception:(const struct OpaqueJSValue **)arg4; - (void)dealloc; - (void)createWithJSObject:(struct OpaqueJSValue *)arg1 scriptView:(id)arg2; - (id)initWithRenderingContext:(id)arg1 options:(id)arg2; - (struct _sg_state_t *)get_sg_state; @end

77.53125

201

0.784966

c8ab0d11bd86866eff2d5b3fc7cc2d9008eb7ba2

1,369

h

C

console.h

hammadahmad120/Inventory-System

8920d8c2dbfa87e5d52af2d567a3d0a9fa1ddf19

[ "MIT" ]

null

console.h

hammadahmad120/Inventory-System

8920d8c2dbfa87e5d52af2d567a3d0a9fa1ddf19

[ "MIT" ]

null

console.h

hammadahmad120/Inventory-System

8920d8c2dbfa87e5d52af2d567a3d0a9fa1ddf19

[ "MIT" ]

null

#ifndef _CONSOLE_H #define _CONSOLE_H #include<Windows.h> #include<iostream> using namespace std; #ifndef ENTER #define ENTER 13 #endif #ifndef ESCAPE #define ESCAPE 27 #endif #ifndef BACKSPACE #define BACKSPACE 8 #endif #ifndef UDLR #define UDLR 224 #endif #ifndef _COLOR_ENUMERATION #define _COLOR_ENUMERATION enum color{ BLACK, BLUE, GREEN, AQUA, RED, PURPLE, YELLOW, WHITE, GRAY, LIGHT_BLUE, LIGHT_GREEN, LIGHT_AQUA, LIGHT_RED, LIGHT_PURPLE, LIGHT_YELLOW, BRIGHT_WHITE }; #endif #ifndef _MOUSE_STATE_STRUCT #define _MOUSE_STATE_STRUCT struct MouseState{ enum Button { Left = FROM_LEFT_1ST_BUTTON_PRESSED, Middle = FROM_LEFT_2ND_BUTTON_PRESSED, Right = RIGHTMOST_BUTTON_PRESSED }; enum State{ Move = MOUSE_MOVED, Click = 0, DoubleClick = DOUBLE_CLICK, Nothing }; int x; int y; State state; Button button; }; #endif #ifndef _BUTTON_INFO_STRUCT #define _BUTTON_INFO_STRUCT struct ButtonInfo{ string b_name; COORD pos; }; #endif void SetEntireConsoleColor(color BColor, color FColor); void gotoxy(int x, int y); void gotoxy(COORD _coord); void SetTextColor(color BColor, color FColor); MouseState GetMouseState(); int ProceedMenuButtonsKAM(ButtonInfo *buttons, int no_of_buttons, color b_color, color f_color, color button_color, bool left_mouse_button_active = true, int active_b = 0); #endif

12.915094

65

0.755296

c8be3ae01780ecea5389b98926d8d84d9dc27862

29,521

c

C

apps/dexterity_wixel_no_sleep_debug/dexterity_wixel.c

tzachi-dar/adrien_de_croy-dexterity-wixel

ae1adad6e348a998144e8bd0af01beacdb43c926

[ "MIT" ]

2

2016-06-13T20:05:34.000Z

2016-08-23T17:01:16.000Z

apps/dexterity_wixel_no_sleep_debug/dexterity_wixel.c

tzachi-dar/adrien_de_croy-dexterity-wixel

ae1adad6e348a998144e8bd0af01beacdb43c926

[ "MIT" ]

null

apps/dexterity_wixel_no_sleep_debug/dexterity_wixel.c

tzachi-dar/adrien_de_croy-dexterity-wixel

ae1adad6e348a998144e8bd0af01beacdb43c926

[ "MIT" ]

null

/** DEXCOM_G4_RX: == Description == A Wixel running this app appears to the USB host as a Virtual COM Port, with USB product ID 0x2200. To view the output of this app, connect to the Wixel's virtual COM port using a terminal program. Be sure to set your terminal's line width to 120 characters or more to avoid line wrapping. The app uses the radio_queue libray to receive packets. It does not transmit any packets. The output from this app takes the following format: The red LED indicates activity on the radio channel (packets being received). Since every radio packet has a chance of being lost, there is no guarantee that this app will pick up all the packets being sent, and some of what it does pick up will be corrupted (indicated by a failed CRC check). == Parameters == radio_channel: See description in radio_link.h. */ /** Dependencies **************************************************************/ #include <wixel.h> #include <usb.h> #include <usb_com.h> #include <radio_registers.h> #include <radio_queue.h> #include <stdio.h> #include <string.h> #include <ctype.h> #include <uart0.h> #include <gpio.h> static volatile BIT do_sleep = 0; static volatile BIT is_sleeping = 0; static volatile BIT do_verbose = 1; static volatile BIT do_binary = 0; static volatile int start_channel = 0; static volatile BIT do_close_usb = 1; static volatile uint32 last_packet = -285000; // forward prototypes int doServices(uint8 bWithProtocol); #define USB_COMMAND_MAXLEN (32) #define NUM_CHANNELS (4) // frequency offsets for each channel - seed to 0. static uint8 fOffset[NUM_CHANNELS] = {0xCE,0xD5,0xE6,0xE5}; static uint8 nChannels[NUM_CHANNELS] = { 0, 100, 199, 209 }; // store RF config in FLASH, and retrieve it from here to put it in proper location (also incidentally in flash). // this allows persistent storage of RF params that will survive a restart of the wixel (although not a reload of wixel app obviously). // TO-DO get this working with DMA - need to erase memory block first, then write this to it. uint8 XDATA RF_Params[50]; uint16 getRFParamOffset(unsigned char XDATA* pAddr) { unsigned char XDATA* p = 0; return pAddr - p; } uint8 checkRFParamAddr(uint16 addr) { // reserved range 1 if(addr >= 0xDF20 && addr <= 0xDF22) return 0; // reserved range 2 if(addr >= 0xDF27 && addr <= 0xDF2D) return 0; // allowed range if(addr >= 0xDF00 && addr <= 0xDF31) return 1; // disallowed return 0; } void StoreRFParam(uint16 addr, uint8 val) { if(checkRFParamAddr(addr)) RF_Params[addr - 0xDF00] = val; } uint8 SetRFParam(uint16 addr, uint8 val) { if(checkRFParamAddr(addr)) { char XDATA *p = 0; p+=addr; *p = val; StoreRFParam(addr, val); return 1; } return 0; } uint8 GetRFParam(uint16 addr) { char XDATA *p = 0; p+=addr; return *p; } void LoadRFParam(unsigned char XDATA* addr, uint8 default_val) { uint16 addr_offset = getRFParamOffset(addr); if(checkRFParamAddr(addr_offset)) { uint8 val = default_val; if(RF_Params[49] == 1) val = RF_Params[addr_offset - 0xDF00]; SetRFParam(addr_offset, val); } /* else *addr = default_val; */ } void dex_RadioSettings() { // Transmit power: one of the highest settings, but not the highest. LoadRFParam(&PA_TABLE0, 0x00); //??????????????????????????? FE // Set the center frequency of channel 0 to 2403.47 MHz. // Freq = 24/2^16*(0xFREQ) = 2403.47 MHz // FREQ[23:0] = 2^16*(fCarrier/fRef) = 2^16*(2400.156/24) = 0x6401AA //IOCFG2 = 0x0E; //RX_SYMBOL_TICK //IOCFG1 = 0x16; //RX_HARD_DATA[1] //IOCFG0 = 0x1D; //Preamble Quality Reached LoadRFParam(&IOCFG0, 0x0E); LoadRFParam(&FREQ2, 0x65); LoadRFParam(&FREQ1, 0x0A); LoadRFParam(&FREQ0, 0xAA); LoadRFParam(&SYNC1, 0xD3); LoadRFParam(&SYNC0, 0x91); LoadRFParam(&ADDR, 0x00); // Controls the FREQ_IF used for RX. // This is affected by MDMCFG2.DEM_DCFILT_OFF according to p.212 of datasheet. LoadRFParam(&FSCTRL1, 0x0A); // Intermediate Freq. Fif = FRef x FREQ_IF / 2^10 = 24000000 * 10/1024 = 234375 for 0x0F = 351562.5 LoadRFParam(&FSCTRL0, 0x00); // base freq offset. This is 1/214 th of the allowable range of frequency compensation // which depends on the FOCCFG param for fraction of channel bandwidth to swing (currently 1/8th, maybe should be 1/4). // Sets the data rate (symbol rate) used in TX and RX. See Sec 13.5 of the datasheet. // Also sets the channel bandwidth. // We tried different data rates: 375 kbps was pretty good, but 400 kbps and above caused lots of packet errors. // NOTE: If you change this, you must change RSSI_OFFSET in radio_registers.h // Dexcom states channel bandwidth (not spacing) = 334.7 kHz E = 1, M = 0 (MDMCFG4 = 4B) // = 24000000 / 8 x (4 + 0) x 2 ^ 1 // = 24000000 / 64 = 375000 LoadRFParam(&MDMCFG4, 0x4B); // 375kHz BW, DRATE_EXP = 11. // Rdata = (256+DRATE_M) x 2 ^ DRATE_E // ------------------------ x Fref = FRef x (256 + DRATE_M) x 2 ^ (DRATE_E-28) // 2 ^ 28 // in our case = 24000000 * (256+17) x 2 ^ (-17) = (24000000 / 131072) * 273 = 49987.79 LoadRFParam(&MDMCFG3, 0x11); // DRATE_M = 0x11 = 17. // MDMCFG2.DEM_DCFILT_OFF, 0, enable digital DC blocking filter before // demodulator. This affects the FREQ_IF according to p.212 of datasheet. // MDMCFC2.MANCHESTER_EN, 0 is required because we are using MSK (see Sec 13.9.2) // MDMCFG2.MOD_FORMAT, 111: MSK modulation // MDMCFG2.SYNC_MODE, 011: 30/32 sync bits received, no requirement on Carrier sense LoadRFParam(&MDMCFG2, 0x73); // MDMCFG1.FEC_EN = 0 : 0=Disable Forward Error Correction // MDMCFG1.NUM_PREAMBLE = 000 : Minimum number of preamble bytes is 2. // MDMCFG1.CHANSPC_E = 3 : Channel spacing exponent. // MDMCFG0.CHANSPC_M = 0x55 : Channel spacing mantissa. // Channel spacing = (256 + CHANSPC_M)*2^(CHANSPC_E) * f_ref / 2^18 // = 24000000 x (341) x 2^(3-18) = 24000000 x 341 / 2^15 // = 249755Hz. LoadRFParam(&MDMCFG1, 0x03); // no FEC, preamble bytes = 2 (AAAA), CHANSPC_E = 3 LoadRFParam(&MDMCFG0, 0x55); // CHANSPC_M = 0x55 = 85 LoadRFParam(&DEVIATN, 0x00); // See Sec 13.9.2. LoadRFParam(&FREND1, 0xB6); LoadRFParam(&FREND0, 0x10); // F0CFG and BSCFG configure details of the PID loop used to correct the // bit rate and frequency of the signal (RX only I believe). LoadRFParam(&FOCCFG, 0x0A); // allow range of +/1 FChan/4 = 375000/4 = 93750. No CS GATE LoadRFParam(&BSCFG, 0x6C); // AGC Control: // This affects many things, including: // Carrier Sense Absolute Threshold (Sec 13.10.5). // Carrier Sense Relative Threshold (Sec 13.10.6). LoadRFParam(&AGCCTRL2, 0x44); LoadRFParam(&AGCCTRL1, 0x00); LoadRFParam(&AGCCTRL0, 0xB2); // Frequency Synthesizer registers that are not fully documented. LoadRFParam(&FSCAL3, 0xA9); LoadRFParam(&FSCAL2, 0x0A); LoadRFParam(&FSCAL1, 0x20); LoadRFParam(&FSCAL0, 0x0D); // Mostly-undocumented test settings. // NOTE: The datasheet says TEST1 must be 0x31, but SmartRF Studio recommends 0x11. LoadRFParam(&TEST2, 0x81); LoadRFParam(&TEST1, 0x35); LoadRFParam(&TEST0, 0x0B); // Packet control settings. LoadRFParam(&PKTCTRL1, 0x04); LoadRFParam(&PKTCTRL0, 0x05); // enable CRC flagging and variable length packets. Probably could use fix length for our case, since all are same length. // but that would require changing the library code, since it sets up buffers etc etc, and I'm too lazy. RF_Params[49] = 1; } uint8 min8(uint8 a, uint8 b) { if(a < b) return a; return b; } typedef struct _Dexcom_packet { uint8 len; uint32 dest_addr; uint32 src_addr; uint8 port; uint8 device_info; uint8 txId; uint16 raw; uint16 filtered; uint8 battery; uint8 unknown; uint8 checksum; int8 RSSI; uint8 LQI; } Dexcom_packet; int8 getPacketRSSI(Dexcom_packet* p) { // RSSI_OFFSET for 489 kbaud is closer to 73 than 71 return (p->RSSI/2)-73; } uint8 getPacketPassedChecksum(Dexcom_packet* p) { return ((p->LQI & 0x80)==0x80) ? 1:0; } void openUart() { uart0Init(); uart0SetBaudRate(9600); uart0SetParity(0); uart0SetStopBits(1); } /** Functions *****************************************************************/ /* the function that puts the system to sleep (PM2) and configures sleep timer to wake it again in 250 seconds.*/ void makeAllOutputs(BIT value) { int i = 0; for (;i < 16; i++) { setDigitalOutput(i, value); } } // use power mode 1 #define SLEEP_MODE_USING (0x01) // ISR for catching Sleep Timer interrupts ISR (ST, 0) { IRCON &= ~0x80; // clear IRCON.STIF SLEEP &= ~SLEEP_MODE_USING; // clear SLEEP.MODE IEN0 &= ~0x20; // clear IEN0.STIE WORIRQ &= ~0x11; // clear Sleep timer EVENT0_MASK and EVENT0_FLAG WORCTRL &= ~0x03; // Set timer resolution back to 1 period. if(do_close_usb) { // wake up USB again usbPoll(); } // we not sleeping no more is_sleeping = 0; } void goToSleep (uint16 seconds) { unsigned char temp; // The wixel docs note that any input pins consume ~30uA makeAllOutputs(LOW); IEN0 |= 0x20; // Enable global ST interrupt [IEN0.STIE] WORIRQ |= 0x10; // enable sleep timer interrupt [EVENT0_MASK] /* the sleep mode i've chosen is PM2. According to the CC251132 datasheet, typical power consumption from the SoC should be around 0.5uA */ /*The SLEEP.MODE will be cleared to 00 by HW when power mode is entered, thus interrupts are enabled during power modes. All interrupts not to be used to wake up from power modes must be disabled before setting SLEEP.MODE!=00.*/ // sleep power mode 2 is incompatible with USB - as USB registers lose state in this mode. SLEEP |= SLEEP_MODE_USING; // SLEEP.MODE = PM2 if(do_close_usb) { // disable the USB module SLEEP &= ~(1<<7); // Disable the USB module (SLEEP.USB_EN = 0). disableUsbPullup(); usbDeviceState = USB_STATE_DETACHED; } // Reset timer, update EVENT0, and enter PM2 // WORCTRL[2] = Reset Timer // WORCTRL[1:0] = Sleep Timer resolution // 00 = 1 period // 01 = 2^5 periods // 10 = 2^10 periods // 11 = 2^15 periods // t(event0) = (1/32768)*(WOREVT1 << 8 + WOREVT0) * timer res // e.g. WOREVT1=0,WOREVT0=1,res=2^15 ~= 0.9766 second WORCTRL |= 0x04; // Reset // Wait for 2x+ve edge on 32kHz clock temp = WORTIME0; while (temp == WORTIME0) {}; temp = WORTIME0; while (temp == WORTIME0) {}; WORCTRL |= 0x03; // 2^15 periods WOREVT1 = (seconds >> 8); WOREVT0 = (seconds & 0xff); //300=293 s PCON |= 0x01; // PCON.IDLE = 1; is_sleeping = 1; } void updateLedsold() { if (do_sleep) { if(is_sleeping) { LED_YELLOW((getMs()&0x00000F00) == 0x100); } else { LED_GREEN((getMs()&0x00000380) == 0x80); } } // LED_YELLOW(radioQueueRxCurrentPacket()); // LED_RED(0); } void updateLeds() { if(getMs() - last_packet > 285000) { LED_GREEN((getMs()&0x00000380) == 0x80); } else { LED_GREEN(0); } } // This is called by printf and printPacket. void putchar(char c) { usbComTxSendByte(c); } char nibbleToAscii(uint8 nibble) { nibble &= 0xF; if (nibble <= 0x9){ return '0' + nibble; } else{ return 'A' + (nibble - 0xA); } } uint8 bit_reverse_byte(uint8 in) { uint8 bRet = 0; if(in & 0x01) bRet |= 0x80; if(in & 0x02) bRet |= 0x40; if(in & 0x04) bRet |= 0x20; if(in & 0x08) bRet |= 0x10; if(in & 0x10) bRet |= 0x08; if(in & 0x20) bRet |= 0x04; if(in & 0x40) bRet |= 0x02; if(in & 0x80) bRet |= 0x01; return bRet; } void bit_reverse_bytes(uint8* buf, uint8 nLen) { uint8 i = 0; for(; i < nLen; i++) { buf[i] = bit_reverse_byte(buf[i]); } } uint32 dex_num_decoder(uint16 usShortFloat) { uint16 usReversed = usShortFloat; uint8 usExponent = 0; uint32 usMantissa = 0; bit_reverse_bytes((uint8*)&usReversed, 2); usExponent = ((usReversed & 0xE000) >> 13); usMantissa = (usReversed & 0x1FFF); return usMantissa << usExponent; } char SrcNameTable[32] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'J', 'K', 'L', 'M', 'N', 'P', 'Q', 'R', 'S', 'T', 'U', 'W', 'X', 'Y' }; void dexcom_src_to_ascii(uint32 src, char addr[6]) { addr[0] = SrcNameTable[(src >> 20) & 0x1F]; addr[1] = SrcNameTable[(src >> 15) & 0x1F]; addr[2] = SrcNameTable[(src >> 10) & 0x1F]; addr[3] = SrcNameTable[(src >> 5) & 0x1F]; addr[4] = SrcNameTable[(src >> 0) & 0x1F]; addr[5] = 0; } typedef struct _RawRecord { uint8 size; uint32 tickcount; uint8 src_addr[6]; uint16 raw; uint16 filtered; uint8 battery; int8 RSSI; uint8 txid; } RawRecord; void print_packet(Dexcom_packet* pPkt) { uint8 txid = (pPkt->txId & 0xFC) >> 2; if(do_binary) { XDATA RawRecord Record; Record.size = sizeof(Record); Record.tickcount = getMs(); dexcom_src_to_ascii(pPkt->src_addr, Record.src_addr); Record.raw = dex_num_decoder(pPkt->raw); Record.filtered = 2 * dex_num_decoder(pPkt->filtered); Record.battery = pPkt->battery; Record.RSSI = getPacketRSSI(pPkt); Record.txid = txid; // wait for sufficient output buffer on USB while(usbComTxAvailable() < sizeof(Record)) doServices(0); usbComTxSend((const uint8 XDATA*)&Record, sizeof(Record)); } else { char srcAddr[6]; dexcom_src_to_ascii(pPkt->src_addr, srcAddr); // WARNING this is snir only code !!! // if(!strcmp(srcAddr,"63EWA")) { printf("%s %lu %lu %hhu %hhi %hhu\r\n", srcAddr, dex_num_decoder(pPkt->raw), 2 * dex_num_decoder(pPkt->filtered), pPkt->battery, getPacketRSSI(pPkt), txid); // } } } typedef struct _usb_command { uint8 usbCommandBuffer[USB_COMMAND_MAXLEN]; uint8 nCurReadPos; } t_usb_command; uint8 init_usb_command(t_usb_command* pCmd) { if(!pCmd) return 0; memset(pCmd->usbCommandBuffer, 0, USB_COMMAND_MAXLEN); pCmd->nCurReadPos = 0; return 0; } static t_usb_command usb_command; int usb_command_is(char* command) { uint8 len = strlen(command); if(len != usb_command.nCurReadPos) return 0; return memcmp(command, usb_command.usbCommandBuffer, len)==0; } uint8 Hex1ToUint4(char c) { if(c >= '0' && c <= '9') return c-'0'; if(c >= 'A' && c <= 'F') return c + 10 -'A'; if(c >= 'a' && c <= 'f') return c + 10 -'a'; return 0; } uint8 Hex2ToUint8(char* c) { uint8 r = 0; r += Hex1ToUint4(c[0]); r <<=4; r += Hex1ToUint4(c[1]); return r; } uint16 Hex4ToUint16(char* c) { uint16 r = 0; r += Hex1ToUint4(c[0]); r <<=4; r += Hex1ToUint4(c[1]); r <<=4; r += Hex1ToUint4(c[2]); r <<=4; r += Hex1ToUint4(c[3]); return r; } // return code dictates whether to cancel out of current packet wait operation. // primarily this is so if you change the start channel, it will actually start using that new start channel // otherwise there's an infinite wait on when it may fail the initial start channel wait, which if it's interfered with may be forever. int doUsbCommand() { if(usb_command_is("HELLO")) { printf("OK WIXEL Dexterity 1.0\r\n"); printf("OK current tick %lu\r\n", getMs()); printf("OK sleep mode is %s\r\n", (do_sleep)?"ON":"OFF"); return 1; } if(usb_command_is("BOOTLOADER")) { printf("OK entering bootloader mode\r\n"); requestBootloaderSoon(); return 1; } if(usb_command_is("SLEEP ON")) { do_sleep = 1; printf("OK sleep mode on\r\n"); return 1; } if(usb_command_is("SLEEP OFF")) { do_sleep = 0; printf("OK sleep mode off\r\n"); return 1; } if(usb_command_is("SHOW RF CONFIG")) { int i = 0; while(i < sizeof(RF_Params)) { uint16 addr = 0xDF00 + i; if(usbComTxAvailable() > 12) { if(checkRFParamAddr(addr)) { printf("OK "); printf("%04X ", addr); printf("%02X\r\n", GetRFParam(addr)); } i++; } doServices(0); } return 1; } if(memcmp(usb_command.usbCommandBuffer, "GETRFPARAM", 10) == 0) { //ok, we're being asked to get an RF parameter from the host. Cool! // need to get the address, should be next param if(usb_command.usbCommandBuffer[10] == ' ' && usb_command.nCurReadPos == 15) { uint16 addr = Hex4ToUint16(&usb_command.usbCommandBuffer[11]); if(checkRFParamAddr(addr)) { printf("OK "); printf("%04X ", addr); printf("%02X\r\n", GetRFParam(addr)); } else { printf("NO address out of range\r\n"); } return 1; } } if(memcmp(usb_command.usbCommandBuffer, "SETRFPARAM", 10) == 0) { //ok, we're being asked to set an RF parameter from the host. Cool! if(usb_command.usbCommandBuffer[10] == ' ' && usb_command.usbCommandBuffer[15] == ' ' && usb_command.nCurReadPos == 18) { uint16 addr = Hex4ToUint16(&usb_command.usbCommandBuffer[11]); uint8 val = Hex2ToUint8(&usb_command.usbCommandBuffer[16]); if(SetRFParam(addr, val)) { printf("OK "); printf("%04X ", addr); printf("%02X\r\n", GetRFParam(addr)); } else { printf("NO address out of range\r\n"); } return 1; } } if(usb_command_is("GET OFFSETS")) { int i = 0; for(; i < NUM_CHANNELS; i++) { printf("OK OFFSET[%u] = %02X\r\n", i, fOffset[i]); } return 1; } if(usb_command_is("VERBOSE")) { do_verbose = 1; printf("OK VERBOSE MODE ON\r\n"); return 1; } if(usb_command_is("BINARY")) { do_binary = 1; printf("OK BINARY PACKETS ON\r\n"); return 1; } if(usb_command_is("GETSTARTCHANNEL")) { printf("OK starting from channel %i(%d)\r\n", start_channel, nChannels[start_channel]); return 1; } if(memcmp(usb_command.usbCommandBuffer, "SETSTARTCHANNEL ", 16) == 0) { //ok, we're being asked to set an RF parameter from the host. Cool! if(usb_command.nCurReadPos == 17) { uint8 val = Hex1ToUint4(usb_command.usbCommandBuffer[16]); if(val < NUM_CHANNELS) { start_channel = val; printf("OK starting from channel %i(%d)\r\n", start_channel, nChannels[start_channel]); } else { printf("NO channel out of range (0 - 3 allowed)\r\n"); } return 0; } } printf("NO unrecognised command\r\n"); return 1; } int usbControlProtocolService() { // ok this is where we check if there's anything happening incoming on the COM port. int nRet = 1; while(usbComRxAvailable()) { uint8 b = usbComRxReceiveByte(); if(b == '\r' || b == '\n') { // ok we got the end of a command; if(usb_command.nCurReadPos) { // do the command nRet = doUsbCommand(); init_usb_command(&usb_command); // break out if we got a breaking command if(!nRet) return nRet; } } else if(usb_command.nCurReadPos < USB_COMMAND_MAXLEN) { usb_command.usbCommandBuffer[usb_command.nCurReadPos++]=b; } else { // clear command if there was anything init_usb_command(&usb_command); printf("INVALID COMMAND\r\n"); } } return nRet; } int doServices(uint8 bWithProtocol) { boardService(); updateLeds(); usbComService(); if(bWithProtocol) return usbControlProtocolService(); return 1; } void swap_channel(uint8 channel, uint8 newFSCTRL0) { do { RFST = 4; //SIDLE } while (MARCSTATE != 0x01); // update this, since offset can change based on channel FSCTRL0 = newFSCTRL0; CHANNR = channel; RFST = 2; //RX } // channel is the channel index = 0...3 int WaitForPacket(uint32 milliseconds, Dexcom_packet* pkt, uint8 channel) { uint32 start = getMs(); uint8 XDATA * packet = 0; int nRet = 0; // safety first if(channel >= NUM_CHANNELS) return -1; swap_channel(nChannels[channel], fOffset[channel]); if(do_verbose) printf("[%lu] starting wait for packet on channel %d(%d) - will wait for %lu ms until [%lu] \r\n", start, channel, (int)CHANNR, milliseconds, start + milliseconds); while (!milliseconds || (getMs() - start) < milliseconds) { if(!doServices(1)) return -1; // cancel wait, and cancel calling function if (packet = radioQueueRxCurrentPacket()) { uint8 len = packet[0]; if(radioCrcPassed()) { fOffset[channel] += FREQEST; // there's a packet! memcpy(pkt, packet, min8(len+2, sizeof(Dexcom_packet))); // +2 because we append RSSI and LQI to packet buffer, which isn't shown in len if(do_verbose) printf("[%lu] received packet channel %d(%d) RSSI %d offset %02X bytes %hhu\r\n", getMs(), channel, (int)CHANNR, getPacketRSSI(pkt), fOffset[channel], len); nRet = 1; // subtract channel index from transaction ID. This normalises it so the same transaction id is for all transmissions of a same packet // and makes masking the last 2 bits safe regardless of which channel the packet was acquired on pkt->txId -= channel; } else { nRet = 2; if(do_verbose) printf("[%lu] CRC failure channel %d(%d) RSSI %d %hhu bytes received\r\n", getMs(), channel, (int)CHANNR, (int)((int8)(RSSI))/2 - 73, len); } // pull the packet off the queue radioQueueRxDoneWithPacket(); return nRet; } } if(do_verbose) printf("[%lu] timed out waiting for packet on channel %d(%d)\r\n", getMs(), channel, (int)CHANNR); return nRet; } #define PACKET_WAIT 299200 uint32 calculate_first_packet_delay(uint32 last_packet) { XDATA uint32 next_packet; XDATA uint32 now = getMs(); printf("last_packet = %lu\r\n", last_packet); if(last_packet == 0) { return 0; } next_packet = last_packet + PACKET_WAIT; while(next_packet < now ) { // This writing should pass maxinteger ?????? next_packet += PACKET_WAIT; } printf("next_packet = %lu (don't forget the 150)\r\n", next_packet); return next_packet - now + 150; } int get_packet(Dexcom_packet* pPkt) { // initial delay is infinite (unless receive cancelled by protocol on USB) int nChannel = 0; XDATA static uint32 last_packet = 0; uint32 delay = calculate_first_packet_delay(last_packet); uint8 channel_0_timed_out = 0; XDATA uint8 packet_captured = 0; // start channel is the channel we initially do our infinite wait on. for(nChannel = start_channel; nChannel < NUM_CHANNELS; nChannel++) { // initial receive packet call blocks forever. switch(WaitForPacket(delay, pPkt, nChannel)) { case 1: // got a packet that passed CRC if(channel_0_timed_out) { if(do_verbose) printf("[%lu] YES GOT A PACKET AFTER BETTER WAITING %d(%d) \r\n", getMs(), nChannel, (int)CHANNR); } packet_captured++; last_packet = getMs() - nChannel * 500; break; case 0: // timed out if(nChannel == 0) { channel_0_timed_out = 1; } break; case 2: // crc error break; case -1: // cancelled by protocol on USB (e.g. start channel changed) { if(do_verbose) printf("[%lu] wait for packet on channel %d(%d) abandoned\r\n", getMs(), nChannel, (int)CHANNR); break; } } // ok, no packet this time, set new delay and try to next channel delay = 600; } if(do_verbose) { if(packet_captured) { printf("[%lu] This packet was captured %d times\r\n", getMs(), (int)packet_captured); } else { printf("[%lu] Missed a packet all togeather\r\n",getMs()); } } if(packet_captured) { return 1; } return 0; } void LineStateChangeCallback(uint8 state) { LED_YELLOW(state & ACM_CONTROL_LINE_DTR); } extern void basicUsbInit(); void main() { systemInit(); usbInit(); usbComRequestLineStateChangeNotification(LineStateChangeCallback); // we actually only use USB, so no point wasting power on UART0 // openUart(); init_usb_command(&usb_command); setRadioRegistersInitFunc(dex_RadioSettings); radioQueueInit(); radioQueueAllowCrcErrors = 1; // these are reset in radioQueueInit and radioMacInit after our init func was already called MCSM1 = 0; // after RX go to idle, we don't transmit while (1) { Dexcom_packet Pkt; memset(&Pkt, 0, sizeof(Dexcom_packet)); if(!get_packet(&Pkt)) continue; // ok, we got a packet print_packet(&Pkt); last_packet = getMs(); // can't safely sleep if we didn't get a packet! if (do_sleep) { uint8 savedPICTL = PICTL; BIT savedP0IE = P0IE; RFST = 4; //SIDLE LED_RED(1); LED_YELLOW(1); LED_GREEN(1); delayMs(80); doServices(1); LED_RED(0); LED_YELLOW(0); LED_GREEN(0); goToSleep(280); //~295 s PICTL = savedPICTL; P0IE = savedP0IE; // Enable suspend detection and disable any other weird features. USBPOW = 1; // Enable the USB common interrupts we care about: Reset, Resume, Suspend. // Without this, we USBCIF.SUSPENDIF will not get set (the datasheet is incomplete). USBCIE = 0b0111; // bootstrap radio again radioMacInit(); MCSM1 = 0; // after RX go to idle, we don't transmit radioMacStrobe(); // watchdog mode??? this will do a reset? // WDCTL=0x0B; // delayMs(50); //wait for reset } else { LED_RED(1); LED_YELLOW(1); LED_GREEN(1); delayMs(80); doServices(1); LED_RED(0); LED_YELLOW(0); LED_GREEN(0); } } }

30.402678

177

0.552251

c8cf231c153bfb02b64f84ec7219a00780d98801

129

h

C

SpringBoard/SBWorkspaceDeactivatingEntity.h

LacertosusRepo/headers

f3eef2127548c631b325a0b28c907cc59b1716ac

[ "Unlicense", "Apache-2.0", "OpenSSL", "BSD-3-Clause" ]

182

2016-03-28T00:30:04.000Z

2022-03-31T02:04:58.000Z

SpringBoard/SBWorkspaceDeactivatingEntity.h

LacertosusRepo/headers

f3eef2127548c631b325a0b28c907cc59b1716ac

[ "Unlicense", "Apache-2.0", "OpenSSL", "BSD-3-Clause" ]

36

2016-05-09T09:45:41.000Z

2022-03-06T04:02:42.000Z

SpringBoard/SBWorkspaceDeactivatingEntity.h

LacertosusRepo/headers

f3eef2127548c631b325a0b28c907cc59b1716ac

[ "Unlicense", "Apache-2.0", "OpenSSL", "BSD-3-Clause" ]

69

2016-04-16T19:48:18.000Z

2022-02-28T09:05:05.000Z

#import "SBWorkspaceEntity.h" @interface SBWorkspaceDeactivatingEntity : SBWorkspaceEntity - (BOOL)isDeactivatingEntity; @end

16.125

60

0.821705

eab649599512ca6ea8fb3971a09c0327d97415ef

10,848

h

C

core/proteinstructure/mrf_sampler.h

tecdatalab/legacy

9b5286d3375fff691a80ceb44172549e9a6bdee5

[ "Apache-2.0" ]

null

core/proteinstructure/mrf_sampler.h

tecdatalab/legacy

9b5286d3375fff691a80ceb44172549e9a6bdee5

[ "Apache-2.0" ]

null

core/proteinstructure/mrf_sampler.h

tecdatalab/legacy

9b5286d3375fff691a80ceb44172549e9a6bdee5

[ "Apache-2.0" ]

null

#ifndef _MRF_SAMPLER_H_ #define _MRF_SAMPLER_H_ #include <map> #include <utility> #include <vector> #include "../em/density_lattice.h" #include "mrf_features.h" #include "pdb.h" #include "transformable_pdb.h" using std::pair; using std::vector; // Instances of this class are used to generate data files that sample different // positions of PDB units fittted into an EM map. These files will contain // features that are later used to train models using an MRF framework. // The sampling process starts by finding the best position for each unit, // with the help of the c-alpha trace, and then samples a small number of // positions close to the best location (short_rotation_* parameters) as well // as a more widespread sampling (using long_rotation_*). // For each unit X, a file called X.mrf is created with CC, RMSD and Overlap // features, and for each neighbor pair X-Y an analog X-Y.mrf is created // with pairwise shape and physics-based features. // The small sampling is intended to generate close to native data points, // while the long sampling should generate a varied enough dataset by sampling // across the whole rotational space. class mrf_sampler { public: // pdb_unit_files: Each atomic description of the units e.g. A.pdb, B.pdb, etc // calpha_trace_file: Best arrangement of the PDB units that can be fitted // into the complete_map_file. All the pdb_unit_files can be superimposed // onto this description of the c-alpha trace // em_unit_files: Analog to pdb_unit_files, but MRC EM maps instead // complete_map_file: Map that matches the c-alpha trace // contour_level: Contour value applied to all EM maps, normally from EMDB, // unit_labels: Used to later identify the neighbor relations. Must be in the // same order as the PDB and EM units provided // neighbors: edges between units, used to generate pairwise features // short_rotation_degree_range: from the initial structure +- these number // of degrees // short_rotation_step: starting from -(short_rotation_degree_range) add this // step value until getting to +(short_rotation_degree_range) // short_translation_range/step: analog to the rotation range, but this is // +- angstroms in translations following the step size parameter // long_rotation_step: same thing but without the range parameter because we // sample all 360 degrees // long_translation_range/step: same thing but for the long type of sampling. // output_prefix: adds a prefix to sample files // pdb_output_prefix: if non-empty triggers the generation of PDB files // (with filenames having this prefix) for each singleton transformation. // If provided, pairwise files are not generated. mrf_sampler(vector<string> pdb_unit_files, string calpha_trace_file, vector<string> em_unit_files, string complete_map_file, double contour_level, vector<string> unit_labels, vector<pair<string, string> > neighbors, double short_rotation_degree_range, double short_rotation_step, double short_translation_range, double short_translation_step, double long_rotation_step, double long_translation_range, double long_translation_step, string output_prefix, string pdb_output_prefix); // Density lattices are allocated dynamically, release them. ~mrf_sampler(); // Main function that starts the process of sampling and generating the // one and two-body feature files. // swapping_enabled: true when alternate conformations for each position // need to be generated. e.g. if there are 3 units A,B,C with swapping_enabled // conformations of B and C placed at A's center are generated, but no // conformations with A in its intended position are created. void generate_feature_files(bool swapping_enabled); private: // Loads all em map units and the reference map into instance variables. void initialize_em_maps(string reference_map_filename, vector<string> em_unit_filenames); // Set the aligned_units instance member by transforming the input PDBs to // optimally align to the c-alpha trace. void initialize_pdb_units(vector<string> pdb_filenames, vector<string> labels, pdb& calpha_template); // Called at the end of initialize_pdb_units in order to create all the // point_transformations needed in case unit swapping is enabled during // the sampling process. void initialize_swap_transformations(); // These two methods generate the CC, overlap and RMSD values. // The first one iterates over all units and transformation and calls // the second one that is in charge of computing the values for a single // unit and transformation. // swapping_enabled: as described in generate_feature_files void generate_one_body_files(double alpha_center, double beta_center, double gamma_center, double alpha_plus_minus, double beta_plus_minus, double gamma_plus_minus, double translation_plus_minus, double rotation_step, double translation_step, bool append_to_file, bool swapping_enabled); // base_transformation: The x,y,z,alpha,beta,gamma sampled // applied_transformation: Contains base_transformation but it also // has additional adjustments like moves to the centroid mrf_one_body_features calculate_one_body_features(size_t unit_index, point_transformation& base_transformation, point_transformation_sequence& applied_transformation); // Generate a single PDB file by modifying protein[unit_index] with // the transformation given and storing it in // <pdb_prefix>-<unit_label>-<file_sequence_number>.pdb void generate_singleton_pdb(size_t unit_index, point_transformation_sequence& applied_transformation, string pdb_prefix, size_t file_sequence_number); // Iteration over all edges in the mrf and 6D transformation for each // of the 2 units involved. Similar to the previous methods, the second // one computes the features for a particular transformation of the 2 // vertices in the graph // swapping_enabled: as described in generate_feature_files void generate_two_body_files(double alpha_center, double beta_center, double gamma_center, double alpha_plus_minus, double beta_plus_minus, double gamma_plus_minus, double translation_plus_minus, double rotation_step, double translation_step, bool append_to_file, bool swapping_enabled); // left_pdb and right_pdb have been already transformed. The // point_transformations are provided as parameters to correctly // initialize the mrf_two_body_features instance. // Note: base vs applied transformations are the analog to what // is done with the one-body features mrf_two_body_features calculate_two_body_features( size_t left_index, size_t right_index, point_transformation& base_left_transformation, point_transformation& base_right_transformation, point_transformation_sequence& applied_left_transformation, point_transformation_sequence& applied_right_transformation); // Converts unit indices to actual hash table keys to retrieve the appropriate // transformation that moves move_from_unit to move_to_unit point_transformation get_swap_transformation(size_t move_from_unit, size_t move_to_unit); // If no swapping is done, a single base_transformation is applied to each unit // with adjustments done to move to the centroid first. // If swapping is enabled then the function returns not just a single // transformation_sequence but (total_units - 1), each representing the swap of // one unit by another. // Return value: If no swapping, a vector with one pair, where the unit_index // is the same as the one input. If swapping is enabled, unit_indices will be // all except the unit_index input along with the transformation. vector<pair<size_t, point_transformation_sequence> > get_all_adjusted_transformations(size_t unit_index, point_transformation base_transformation, bool swapping_enabled); // Since transformations are calculated from each unit's centroid, // this method adds three point_transformations to the sequence: // a translation to the centroid, the actual transformation and // a translation that negates the original centroid move. void add_centroid_adjusted_transformation(size_t unit_index, point_transformation transformation, point_transformation_sequence* sequence); // It should be a PDB ID referenced from the EMDB entry that provides // the best fitted superimposition of the c-alpha atoms into the map pdb calpha_trace; // Matches calpha_trace, loaded from an EM map obtained directly from // the EMDB. density_lattice* reference_em; // Normally the same value for the reference map found in the EMDB entry. double contour_level; // Full atomic PDB fragments that have been transformed to align as well // as possible to the c-alpha trace. These are considered to be the starting // atomic positions for sampling purposes. vector<transformable_pdb> aligned_units; // Transformations applied to input PDBs to optimally align them to // the calpha_trace vector<point_transformation> alignment_transformations; // Each density lattice represents an EM map, in the same order as the units. // These maps will normally be created from simulated EM map files. vector<density_lattice*> em_units; // For each map and the contour_level provided, we precompute the boundaries // of the EM surfaces vector<density_vector> em_min_boundaries; vector<density_vector> em_max_boundaries; // MRF Graph description. Node names and edges. vector<string> unit_labels; vector<pair<string,string> > neighbors; // Keep track of sequence numbers used to generate PDB files. This is just // to make the output files have the same number in their filename as the // row number each transformation has in the sampling output files. vector<int> transformation_counts; // Quick reference to determine what unit index corresponds to each label map<string, size_t> label_indices; // Keys are X-Y where X and Y are unit labels. Values associated to keys // are translations that move X's centroid to Y's centroid. // This used when generating samples for units that are swapped, becoming // negative examples. map<string, point_transformation> swap_transformations; // Sampling parameters. double short_rotation_degree_range; double short_rotation_step; double short_translation_range; double short_translation_step; double long_rotation_step; double long_translation_range; double long_translation_step; // Files created have this prefix. string output_prefix; // Same for PDB files string pdb_output_prefix; }; #endif

53.70297

81

0.766132

d97b97f1bd286310b2f977dc12ba8a029e80c18a

6,065

c

C

third_party/bass24-linux/modtest/modtest.c

flynn-nrg/tornado-amiga

bb973063b44ee217b7c9b6f9afcdf4bd1e0beee9

[ "BSD-2-Clause" ]

31

2019-06-23T15:16:45.000Z

2022-02-18T16:45:42.000Z

third_party/bass24-linux/modtest/modtest.c

flynn-nrg/tornado-amiga

bb973063b44ee217b7c9b6f9afcdf4bd1e0beee9

[ "BSD-2-Clause" ]

1

2019-10-26T18:11:37.000Z

third_party/bass24-linux/modtest/modtest.c

flynn-nrg/tornado-amiga

bb973063b44ee217b7c9b6f9afcdf4bd1e0beee9

[ "BSD-2-Clause" ]

5

2019-10-26T12:48:39.000Z

2021-12-01T20:16:07.000Z

/* BASS MOD music test Copyright (c) 1999-2014 Un4seen Developments Ltd. */ #include <gtk/gtk.h> #include <glade/glade.h> #include <string.h> #include <regex.h> #include "bass.h" // path to glade file #ifndef GLADE_PATH #define GLADE_PATH "" #endif GladeXML *glade; GtkWidget *win=0; GtkWidget *filesel; DWORD music; // the HMUSIC channel // display error messages void Error(const char *es) { GtkWidget *dialog=gtk_message_dialog_new(GTK_WINDOW(win),GTK_DIALOG_DESTROY_WITH_PARENT, GTK_MESSAGE_ERROR,GTK_BUTTONS_OK,"%s\n(error code: %d)",es,BASS_ErrorGetCode()); gtk_dialog_run(GTK_DIALOG(dialog)); gtk_widget_destroy(dialog); } #define GetWidget(id) glade_xml_get_widget(glade,id) void WindowDestroy(GtkObject *obj, gpointer data) { gtk_main_quit(); } gboolean FileExtensionFilter(const GtkFileFilterInfo *info, gpointer data) { return !regexec((regex_t*)data,info->filename,0,NULL,0); } DWORD GetFlags() { DWORD flags=BASS_MUSIC_POSRESET; // stop notes when seeking switch (gtk_combo_box_get_active(GTK_COMBO_BOX(GetWidget("interpolation")))) { case 0: flags|=BASS_MUSIC_NONINTER; // no interpolation break; case 2: flags|=BASS_MUSIC_SINCINTER; // sinc interpolation break; } switch (gtk_combo_box_get_active(GTK_COMBO_BOX(GetWidget("ramping")))) { case 1: flags|=BASS_MUSIC_RAMP; // ramping break; case 2: flags|=BASS_MUSIC_RAMPS; // "sensitive" ramping break; } switch (gtk_combo_box_get_active(GTK_COMBO_BOX(GetWidget("surround")))) { case 1: flags|=BASS_MUSIC_SURROUND; // surround break; case 2: flags|=BASS_MUSIC_SURROUND2; // "mode2" break; } return flags; } void OpenClicked(GtkButton *obj, gpointer data) { int resp=gtk_dialog_run(GTK_DIALOG(filesel)); gtk_widget_hide(filesel); if (resp==GTK_RESPONSE_ACCEPT) { char *file=gtk_file_chooser_get_filename(GTK_FILE_CHOOSER(filesel)); BASS_MusicFree(music); // free the current music music=BASS_MusicLoad(FALSE,file,0,0,GetFlags(),1); // load the new music if (music) { // success DWORD length=BASS_ChannelGetLength(music,BASS_POS_MUSIC_ORDER); // get the order length gtk_button_set_label(obj,file); { char text[100],*ctype=""; BASS_CHANNELINFO info; int channels=0; while (BASS_ChannelGetAttributeEx(music,BASS_ATTRIB_MUSIC_VOL_CHAN+channels,0,0)) channels++; // count channels BASS_ChannelGetInfo(music,&info); switch (info.ctype&~BASS_CTYPE_MUSIC_MO3) { case BASS_CTYPE_MUSIC_MOD: ctype="MOD"; break; case BASS_CTYPE_MUSIC_MTM: ctype="MTM"; break; case BASS_CTYPE_MUSIC_S3M: ctype="S3M"; break; case BASS_CTYPE_MUSIC_XM: ctype="XM"; break; case BASS_CTYPE_MUSIC_IT: ctype="IT"; break; } snprintf(text,sizeof(text),"name: %s, format: %dch %s%s",BASS_ChannelGetTags(music,BASS_TAG_MUSIC_NAME),channels,ctype,info.ctype&BASS_CTYPE_MUSIC_MO3?" (MO3)":""); gtk_label_set_text(GTK_LABEL(GetWidget("info")),text); } gtk_range_set_range(GTK_RANGE(GetWidget("position")),0,length-1); // update scroller range BASS_ChannelPlay(music,FALSE); // start it } else { // failed gtk_button_set_label(obj,"click here to open a file..."); gtk_label_set_text(GTK_LABEL(GetWidget("info")),""); gtk_label_set_text(GTK_LABEL(GetWidget("posdisplay")),""); Error("Can't play the file"); } g_free(file); } } void PlayClicked(GtkButton *obj, gpointer data) { if (BASS_ChannelIsActive(music)==BASS_ACTIVE_PLAYING) BASS_ChannelPause(music); else BASS_ChannelPlay(music,FALSE); } gboolean PositionChange(GtkRange *range, GtkScrollType scroll, gdouble value, gpointer data) { BASS_ChannelSetPosition(music,value,BASS_POS_MUSIC_ORDER); // set the position return FALSE; } void FlagChanged(GtkComboBox *obj, gpointer data) { BASS_ChannelFlags(music,GetFlags(),-1); // update flags } gboolean TimerProc(gpointer data) { char text[16]; QWORD pos=BASS_ChannelGetPosition(music,BASS_POS_MUSIC_ORDER); if (pos!=(QWORD)-1) { gtk_range_set_value(GTK_RANGE(GetWidget("position")),LOWORD(pos)); sprintf(text,"%03d.%03d",LOWORD(pos),HIWORD(pos)); gtk_label_set_text(GTK_LABEL(GetWidget("posdisplay")),text); } return TRUE; } int main(int argc, char* argv[]) { regex_t fregex; gtk_init(&argc,&argv); // check the correct BASS was loaded if (HIWORD(BASS_GetVersion())!=BASSVERSION) { Error("An incorrect version of BASS was loaded"); return 0; } // initialize default output device if (!BASS_Init(-1,44100,0,NULL,NULL)) { Error("Can't initialize device"); return 0; } // initialize GUI glade=glade_xml_new(GLADE_PATH"modtest.glade",NULL,NULL); if (!glade) return 0; win=GetWidget("window1"); if (!win) return 0; glade_xml_signal_autoconnect(glade); gtk_combo_box_set_active(GTK_COMBO_BOX(GetWidget("interpolation")),1); gtk_combo_box_set_active(GTK_COMBO_BOX(GetWidget("ramping")),2); gtk_combo_box_set_active(GTK_COMBO_BOX(GetWidget("surround")),0); { // initialize file selector GtkFileFilter *filter; filesel=gtk_file_chooser_dialog_new("Open File",GTK_WINDOW(win),GTK_FILE_CHOOSER_ACTION_OPEN, GTK_STOCK_CANCEL,GTK_RESPONSE_CANCEL,GTK_STOCK_OPEN,GTK_RESPONSE_ACCEPT,NULL); filter=gtk_file_filter_new(); gtk_file_filter_set_name(filter,"mo3/it/xm/s3m/mtm/mod/umx"); regcomp(&fregex,"\\.(mo3|it|xm|s3m|mtm|mod|umx)$",REG_ICASE|REG_NOSUB|REG_EXTENDED); gtk_file_filter_add_custom(filter,GTK_FILE_FILTER_FILENAME,FileExtensionFilter,&fregex,NULL); gtk_file_chooser_add_filter(GTK_FILE_CHOOSER(filesel),filter); filter=gtk_file_filter_new(); gtk_file_filter_set_name(filter,"All files"); gtk_file_filter_add_pattern(filter,"*"); gtk_file_chooser_add_filter(GTK_FILE_CHOOSER(filesel),filter); } g_timeout_add(100,TimerProc,NULL); gtk_main(); gtk_widget_destroy(filesel); regfree(&fregex); BASS_Free(); return 0; }

29.019139

169

0.714262

96bffaad1e8e4dcfb1042cfe2364a5c13abd7ac1

2,771

c

C

usr/src/lib/libgen/common/bufsplit.c

AsahiOS/gate

283d47da4e17a5871d9d575e7ffb81e8f6c52e51

[ "MIT" ]

null

usr/src/lib/libgen/common/bufsplit.c

AsahiOS/gate

283d47da4e17a5871d9d575e7ffb81e8f6c52e51

[ "MIT" ]

null

usr/src/lib/libgen/common/bufsplit.c

AsahiOS/gate

283d47da4e17a5871d9d575e7ffb81e8f6c52e51

[ "MIT" ]

1

2020-12-30T00:04:16.000Z

/* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright 2008 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ /* Copyright (c) 1988 AT&T */ /* All Rights Reserved */ #pragma ident "%Z%%M% %I% %E% SMI" /* * Split buffer into fields delimited by tabs and newlines. * Fill pointer array with pointers to fields. * Return the number of fields assigned to the array[]. * The remainder of the array elements point to the end of the buffer. * * Note: * The delimiters are changed to null-bytes in the buffer and array of * pointers is only valid while the buffer is intact. */ #include <sys/types.h> #include <stdlib.h> #include <string.h> #include <thread.h> #include <pthread.h> #ifndef _REENTRANT static char *bsplitchar = "\t\n"; /* characters that separate fields */ #endif #ifdef _REENTRANT static char ** _get_bsplitchar(thread_key_t *keyp) { static char *init_bsplitchar = "\t\n"; char **strp; if (thr_keycreate_once(keyp, free) != 0) return (NULL); strp = pthread_getspecific(*keyp); if (strp == NULL) { strp = malloc(sizeof (char *)); if (thr_setspecific(*keyp, strp) != 0) { if (strp) (void) free(strp); strp = NULL; } if (strp != NULL) *strp = init_bsplitchar; } return (strp); } #endif /* _REENTRANT */ size_t bufsplit(char *buf, size_t dim, char **array) { #ifdef _REENTRANT static thread_key_t key = THR_ONCE_KEY; char **bsplitchar = _get_bsplitchar(&key); #define bsplitchar (*bsplitchar) #endif /* _REENTRANT */ unsigned numsplit; int i; if (!buf) return (0); if (!dim ^ !array) return (0); if (buf && !dim && !array) { bsplitchar = buf; return (1); } numsplit = 0; while (numsplit < dim) { array[numsplit] = buf; numsplit++; buf = strpbrk(buf, bsplitchar); if (buf) *(buf++) = '\0'; else break; if (*buf == '\0') { break; } } buf = strrchr(array[numsplit-1], '\0'); for (i = numsplit; i < dim; i++) array[i] = buf; return (numsplit); }

24.095652

71

0.672681

e7a8646c3aaed4714feca23a28cc8a652371d611

271

h

C

OrganicQuest/KnowledgePageViewController.h

cfourt/OQ

fa38896682bfa200dd86db22f5ed429f98c23114

[ "Apache-2.0" ]

null

OrganicQuest/KnowledgePageViewController.h

cfourt/OQ

fa38896682bfa200dd86db22f5ed429f98c23114

[ "Apache-2.0" ]

null

OrganicQuest/KnowledgePageViewController.h

cfourt/OQ

fa38896682bfa200dd86db22f5ed429f98c23114

[ "Apache-2.0" ]

null

// // KnowledgePageViewController.h // OrganicQuest // // Created by Connor on 1/26/14. // Copyright (c) 2014 Connor. All rights reserved. // #import <UIKit/UIKit.h> @interface KnowledgePageViewController : UIPageViewController -(BOOL)prefersStatusBarHidden; @end

18.066667

61

0.741697

37bc7dea8f1ab7f4f8bc3ca4ea957198e72515a2

2,471

h

C

catboost/libs/logging/logging.h

r1nadeg/04_catboost

6755bbbd1496540b92ded57eea1974f64bef87c5

[ "Apache-2.0" ]

null

catboost/libs/logging/logging.h

r1nadeg/04_catboost

6755bbbd1496540b92ded57eea1974f64bef87c5

[ "Apache-2.0" ]

null

catboost/libs/logging/logging.h

r1nadeg/04_catboost

6755bbbd1496540b92ded57eea1974f64bef87c5

[ "Apache-2.0" ]

1

2018-08-06T14:13:12.000Z

#pragma once #include "logging_level.h" #include <library/logger/global/global.h> #include <util/generic/singleton.h> class TMatrixnetLogSettings { Y_DECLARE_SINGLETON_FRIEND(); TMatrixnetLogSettings() = default; public: using TSelf = TMatrixnetLogSettings; inline static TSelf& GetRef() { return *Singleton<TSelf>(); } bool OutputExtendedInfo = false; TLogPriority LogPriority = TLOG_WARNING; }; struct TMatrixnetMessageFormater { static bool CheckLoggingContext(TLog& logger, const TLogRecordContext& context); static TSimpleSharedPtr<TLogElement> StartRecord(TLog& logger, const TLogRecordContext& context, TSimpleSharedPtr<TLogElement> earlier); }; inline void SetLogingLevel(ELoggingLevel level) { switch (level) { case ELoggingLevel::Silent:{ TMatrixnetLogSettings::GetRef().LogPriority = TLOG_WARNING; break; } case ELoggingLevel::Verbose: { TMatrixnetLogSettings::GetRef().LogPriority = TLOG_NOTICE; break; } case ELoggingLevel::Info: { TMatrixnetLogSettings::GetRef().LogPriority = TLOG_INFO; break; } case ELoggingLevel::Debug: { TMatrixnetLogSettings::GetRef().LogPriority = TLOG_DEBUG; break; } default:{ ythrow yexception() << "Unknown logging level " << level; } } } inline void SetSilentLogingMode() { SetLogingLevel(ELoggingLevel::Silent); } inline void SetVerboseLogingMode() { SetLogingLevel(ELoggingLevel::Debug); } using TCustomLoggingFunction = void(*)(const char*, size_t len); void SetCustomLoggingFunction(TCustomLoggingFunction func); void RestoreOriginalLogger(); #define MATRIXNET_FATAL_LOG SINGLETON_CHECKED_GENERIC_LOG(TGlobalLog, TMatrixnetMessageFormater, TLOG_CRIT, "CRITICAL_INFO") #define MATRIXNET_ERROR_LOG SINGLETON_CHECKED_GENERIC_LOG(TGlobalLog, TMatrixnetMessageFormater, TLOG_ERR, "ERROR") #define MATRIXNET_WARNING_LOG SINGLETON_CHECKED_GENERIC_LOG(TGlobalLog, TMatrixnetMessageFormater, TLOG_WARNING, "WARNING") #define MATRIXNET_NOTICE_LOG SINGLETON_CHECKED_GENERIC_LOG(TGlobalLog, TMatrixnetMessageFormater, TLOG_NOTICE, "NOTICE") #define MATRIXNET_INFO_LOG SINGLETON_CHECKED_GENERIC_LOG(TGlobalLog, TMatrixnetMessageFormater, TLOG_INFO, "INFO") #define MATRIXNET_DEBUG_LOG SINGLETON_CHECKED_GENERIC_LOG(TGlobalLog, TMatrixnetMessageFormater, TLOG_DEBUG, "DEBUG")

34.319444

140

0.736949

534c8b34f6b13f22e9fd8bdf19b7fb10dfaf0c6b

1,813

h

C

PrivateFrameworks/ScreenReader/SCRWorkspaceInjector.h

phatblat/macOSPrivateFrameworks

9047371eb80f925642c8a7c4f1e00095aec66044

[ "MIT" ]

17

2018-11-13T04:02:58.000Z

2022-01-20T09:27:13.000Z

PrivateFrameworks/ScreenReader/SCRWorkspaceInjector.h

phatblat/macOSPrivateFrameworks

9047371eb80f925642c8a7c4f1e00095aec66044

[ "MIT" ]

3

2018-04-06T02:02:27.000Z

2018-10-02T01:12:10.000Z

PrivateFrameworks/ScreenReader/SCRWorkspaceInjector.h

phatblat/macOSPrivateFrameworks

9047371eb80f925642c8a7c4f1e00095aec66044

[ "MIT" ]

1

2018-09-28T13:54:23.000Z

// // Generated by class-dump 3.5 (64 bit). // // class-dump is Copyright (C) 1997-1998, 2000-2001, 2004-2013 by Steve Nygard. // #import "NSObject.h" @interface SCRWorkspaceInjector : NSObject { } + (BOOL)shouldInitializeHotspots; + (BOOL)shouldUnmuteAudio; + (BOOL)shouldObserveFunctionRow; + (BOOL)shouldUpdateConsoleEnabled; + (BOOL)shouldRegisterForSleepWakeNotifications; + (BOOL)shouldRegisterForNotifications; + (BOOL)shouldRegisterForEventHandlerTargets; + (id)systemKeyManager; + (id)siriObserver; + (id)eventFactory; + (id)applicationManager; + (id)observerManager; + (id)rotorManager; + (id)gestureManager; + (id)contextualHelpManager; + (id)brailleFocusManager; + (id)visualManager; + (id)mouse; + (id)outputManager; + (id)userDefaults; + (id)workspace; + (void)_breakRelationShipsWithWorkspace:(id)arg1 userDefaults:(id)arg2 outputManager:(id)arg3 mouse:(id)arg4 visualsManager:(id)arg5 contextualHelpManager:(id)arg6 gestureManager:(id)arg7 rotorManager:(id)arg8 observerManager:(id)arg9 applicationManager:(id)arg10 eventFactory:(id)arg11 siriObserver:(id)arg12 systemKeyManager:(id)arg13; + (void)_setupRelationShipsWithWorkspace:(id)arg1 userDefaults:(id)arg2 outputManager:(id)arg3 mouse:(id)arg4 visualsManager:(id)arg5 contextualHelpManager:(id)arg6 gestureManager:(id)arg7 rotorManager:(id)arg8 observerManager:(id)arg9 applicationManager:(id)arg10 eventFactory:(id)arg11 siriObserver:(id)arg12 systemKeyManager:(id)arg13 brailleFocusManager:(id)arg14 shouldRegisterForEventHandlerTargets:(BOOL)arg15 shouldRegisterForNotifications:(BOOL)arg16 shouldRegisterForSleepWakeNotifications:(BOOL)arg17 shouldUpdateConsoleEnabled:(BOOL)arg18 shouldObserveFunctionRow:(BOOL)arg19 shouldUnmuteAudio:(BOOL)arg20 shouldInitializeHotspots:(BOOL)arg21; + (void)tearDown; + (void)setup; @end

44.219512

655

0.801434

63e3e3f38642529bfb97423140cf75db09be5368

98,990

c

C

Source/Lib/Codec/EbRateControlProcess.c

luofalei/SVT-AV1

a6c1f81989c6cab0f477adfa867d5ff3dad2725c

[ "BSD-2-Clause-Patent" ]

null

Source/Lib/Codec/EbRateControlProcess.c

luofalei/SVT-AV1

a6c1f81989c6cab0f477adfa867d5ff3dad2725c

[ "BSD-2-Clause-Patent" ]

null

Source/Lib/Codec/EbRateControlProcess.c

luofalei/SVT-AV1

a6c1f81989c6cab0f477adfa867d5ff3dad2725c

[ "BSD-2-Clause-Patent" ]

1

2019-09-29T22:31:10.000Z

/* * Copyright(c) 2019 Intel Corporation * SPDX - License - Identifier: BSD - 2 - Clause - Patent */ /* * Copyright (c) 2016, Alliance for Open Media. All rights reserved * * This source code is subject to the terms of the BSD 2 Clause License and * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License * was not distributed with this source code in the LICENSE file, you can * obtain it at www.aomedia.org/license/software. If the Alliance for Open * Media Patent License 1.0 was not distributed with this source code in the * PATENTS file, you can obtain it at www.aomedia.org/license/patent. */ #include <stdlib.h> #include "EbDefinitions.h" #include "EbRateControlProcess.h" #include "EbSystemResourceManager.h" #include "EbSequenceControlSet.h" #include "EbPictureControlSet.h" #include "EbUtility.h" #include "EbErrorCodes.h" #include "EbEntropyCoding.h" #include "EbRateControlResults.h" #include "EbRateControlTasks.h" #include "RateControlModel.h" static uint8_t QP_OFFSET_LAYER_ARRAY[MAX_TEMPORAL_LAYERS] = { 1, 2, 4, 5, 6, 7 }; /***************************** * Internal Typedefs *****************************/ void RateControlLayerReset( RateControlLayerContext_t *rateControlLayerPtr, PictureControlSet_t *picture_control_set_ptr, RateControlContext_t *rateControlContextPtr, uint32_t pictureAreaInPixel, EbBool wasUsed) { SequenceControlSet_t *sequence_control_set_ptr = (SequenceControlSet_t*)picture_control_set_ptr->sequence_control_set_wrapper_ptr->object_ptr; uint32_t sliceNum; uint32_t temporal_layer_index; uint64_t totalFrameInInterval; uint64_t sumBitsPerSw = 0; rateControlLayerPtr->target_bit_rate = picture_control_set_ptr->parent_pcs_ptr->target_bit_rate*rate_percentage_layer_array[sequence_control_set_ptr->static_config.hierarchical_levels][rateControlLayerPtr->temporalIndex] / 100; // update this based on temporal layers rateControlLayerPtr->frame_rate = sequence_control_set_ptr->frame_rate; totalFrameInInterval = sequence_control_set_ptr->static_config.intra_period_length + 1; if (sequence_control_set_ptr->static_config.look_ahead_distance != 0 && sequence_control_set_ptr->intra_period_length != -1) { if (picture_control_set_ptr->picture_number % ((sequence_control_set_ptr->intra_period_length + 1)) == 0) { totalFrameInInterval = 0; for (temporal_layer_index = 0; temporal_layer_index < EB_MAX_TEMPORAL_LAYERS; temporal_layer_index++) { rateControlContextPtr->frames_in_interval[temporal_layer_index] = picture_control_set_ptr->parent_pcs_ptr->frames_in_interval[temporal_layer_index]; totalFrameInInterval += picture_control_set_ptr->parent_pcs_ptr->frames_in_interval[temporal_layer_index]; sumBitsPerSw += picture_control_set_ptr->parent_pcs_ptr->bits_per_sw_per_layer[temporal_layer_index]; } #if ADAPTIVE_PERCENTAGE rateControlLayerPtr->target_bit_rate = picture_control_set_ptr->parent_pcs_ptr->target_bit_rate* picture_control_set_ptr->parent_pcs_ptr->bits_per_sw_per_layer[rateControlLayerPtr->temporalIndex] / sumBitsPerSw; #endif } } if (rateControlLayerPtr->temporalIndex == 0) { rateControlLayerPtr->coeffAveragingWeight1 = 5; rateControlLayerPtr->frame_rate = rateControlLayerPtr->frame_rate >> 5; } else if (rateControlLayerPtr->temporalIndex == 1) { rateControlLayerPtr->coeffAveragingWeight1 = 5; rateControlLayerPtr->frame_rate = rateControlLayerPtr->frame_rate >> 5; } else if (rateControlLayerPtr->temporalIndex == 2) { rateControlLayerPtr->coeffAveragingWeight1 = 5; rateControlLayerPtr->frame_rate = rateControlLayerPtr->frame_rate >> 4; } else if (rateControlLayerPtr->temporalIndex == 3) { rateControlLayerPtr->coeffAveragingWeight1 = 5; rateControlLayerPtr->frame_rate = rateControlLayerPtr->frame_rate >> 3; } else if (rateControlLayerPtr->temporalIndex == 4) { rateControlLayerPtr->coeffAveragingWeight1 = 5; rateControlLayerPtr->frame_rate = rateControlLayerPtr->frame_rate >> 2; } else if (rateControlLayerPtr->temporalIndex == 5) { rateControlLayerPtr->coeffAveragingWeight1 = 3; rateControlLayerPtr->frame_rate = rateControlLayerPtr->frame_rate >> 1; } if (sequence_control_set_ptr->static_config.intra_period_length != -1) { rateControlLayerPtr->frame_rate = sequence_control_set_ptr->frame_rate * rateControlContextPtr->frames_in_interval[rateControlLayerPtr->temporalIndex] / totalFrameInInterval; } rateControlLayerPtr->coeffAveragingWeight2 = 16 - rateControlLayerPtr->coeffAveragingWeight1; if (rateControlLayerPtr->frame_rate == 0) { // no frame in that layer rateControlLayerPtr->frame_rate = 1 << RC_PRECISION; } rateControlLayerPtr->channelBitRate = (((rateControlLayerPtr->target_bit_rate << (2 * RC_PRECISION)) / rateControlLayerPtr->frame_rate) + RC_PRECISION_OFFSET) >> RC_PRECISION; rateControlLayerPtr->channelBitRate = (uint64_t)MAX((int64_t)1, (int64_t)rateControlLayerPtr->channelBitRate); rateControlLayerPtr->ecBitConstraint = rateControlLayerPtr->channelBitRate; // This is only for the initial frame, because the feedback is from packetization now and all of these are considered // considering the bits for slice header // *Note - only one-slice-per picture is supported for UHD sliceNum = 1; rateControlLayerPtr->ecBitConstraint -= SLICE_HEADER_BITS_NUM * sliceNum; rateControlLayerPtr->ecBitConstraint = MAX(1, rateControlLayerPtr->ecBitConstraint); rateControlLayerPtr->previousBitConstraint = rateControlLayerPtr->channelBitRate; rateControlLayerPtr->bitConstraint = rateControlLayerPtr->channelBitRate; rateControlLayerPtr->difTotalAndEcBits = 0; rateControlLayerPtr->frameSameSADMinQpCount = 0; rateControlLayerPtr->maxQp = picture_control_set_ptr->picture_qp; rateControlLayerPtr->alpha = 1 << (RC_PRECISION - 1); { if (!wasUsed) { rateControlLayerPtr->sameSADCount = 0; rateControlLayerPtr->kCoeff = 3 << RC_PRECISION; rateControlLayerPtr->previousKCoeff = 3 << RC_PRECISION; rateControlLayerPtr->cCoeff = (rateControlLayerPtr->channelBitRate << (2 * RC_PRECISION)) / pictureAreaInPixel / CCOEFF_INIT_FACT; rateControlLayerPtr->previousCCoeff = (rateControlLayerPtr->channelBitRate << (2 * RC_PRECISION)) / pictureAreaInPixel / CCOEFF_INIT_FACT; // These are for handling Pred structure 2, when for higher temporal layer, frames can arrive in different orders // They should be modifed in a way that gets these from previous layers rateControlLayerPtr->previousFrameQp = 32; rateControlLayerPtr->previousFrameBitActual = 1200; rateControlLayerPtr->previousFrameQuantizedCoeffBitActual = 1000; rateControlLayerPtr->previousFrameSadMe = 10000000; rateControlLayerPtr->previousFrameQp = picture_control_set_ptr->picture_qp; rateControlLayerPtr->deltaQpFraction = 0; rateControlLayerPtr->previousFrameAverageQp = picture_control_set_ptr->picture_qp; rateControlLayerPtr->previousCalculatedFrameQp = picture_control_set_ptr->picture_qp; rateControlLayerPtr->calculatedFrameQp = picture_control_set_ptr->picture_qp; rateControlLayerPtr->criticalStates = 0; } else { rateControlLayerPtr->sameSADCount = 0; rateControlLayerPtr->criticalStates = 0; } } } void RateControlLayerResetPart2( RateControlLayerContext_t *rateControlLayerPtr, PictureControlSet_t *picture_control_set_ptr) { // update this based on temporal layers rateControlLayerPtr->maxQp = (uint32_t)CLIP3(0, 63, (int32_t)(picture_control_set_ptr->picture_qp + QP_OFFSET_LAYER_ARRAY[rateControlLayerPtr->temporalIndex]));; { // These are for handling Pred structure 2, when for higher temporal layer, frames can arrive in different orders // They should be modifed in a way that gets these from previous layers rateControlLayerPtr->previousFrameQp = rateControlLayerPtr->maxQp; rateControlLayerPtr->previousFrameAverageQp = rateControlLayerPtr->maxQp; rateControlLayerPtr->previousCalculatedFrameQp = rateControlLayerPtr->maxQp; rateControlLayerPtr->calculatedFrameQp = rateControlLayerPtr->maxQp; } } EbErrorType HighLevelRateControlContextCtor( HighLevelRateControlContext_t **entry_dbl_ptr) { HighLevelRateControlContext_t *entryPtr; EB_MALLOC(HighLevelRateControlContext_t*, entryPtr, sizeof(HighLevelRateControlContext_t), EB_N_PTR); *entry_dbl_ptr = entryPtr; return EB_ErrorNone; } EbErrorType rate_control_layer_context_ctor( RateControlLayerContext_t **entry_dbl_ptr) { RateControlLayerContext_t *entryPtr; EB_MALLOC(RateControlLayerContext_t*, entryPtr, sizeof(RateControlLayerContext_t), EB_N_PTR); *entry_dbl_ptr = entryPtr; entryPtr->firstFrame = 1; entryPtr->firstNonIntraFrame = 1; entryPtr->feedbackArrived = EB_FALSE; return EB_ErrorNone; } EbErrorType rate_control_interval_param_context_ctor( RateControlIntervalParamContext_t **entry_dbl_ptr) { uint32_t temporalIndex; EbErrorType return_error = EB_ErrorNone; RateControlIntervalParamContext_t *entryPtr; EB_MALLOC(RateControlIntervalParamContext_t*, entryPtr, sizeof(RateControlIntervalParamContext_t), EB_N_PTR); *entry_dbl_ptr = entryPtr; entryPtr->inUse = EB_FALSE; entryPtr->wasUsed = EB_FALSE; entryPtr->lastGop = EB_FALSE; entryPtr->processedFramesNumber = 0; EB_MALLOC(RateControlLayerContext_t**, entryPtr->rateControlLayerArray, sizeof(RateControlLayerContext_t*)*EB_MAX_TEMPORAL_LAYERS, EB_N_PTR); for (temporalIndex = 0; temporalIndex < EB_MAX_TEMPORAL_LAYERS; temporalIndex++) { return_error = rate_control_layer_context_ctor(&entryPtr->rateControlLayerArray[temporalIndex]); entryPtr->rateControlLayerArray[temporalIndex]->temporalIndex = temporalIndex; entryPtr->rateControlLayerArray[temporalIndex]->frame_rate = 1 << RC_PRECISION; if (return_error == EB_ErrorInsufficientResources) { return EB_ErrorInsufficientResources; } } entryPtr->min_target_rate_assigned = EB_FALSE; entryPtr->intraFramesQp = 0; entryPtr->nextGopIntraFrameQp = 0; entryPtr->firstPicPredBits = 0; entryPtr->firstPicActualBits = 0; entryPtr->firstPicPredQp = 0; entryPtr->firstPicActualQp = 0; entryPtr->firstPicActualQpAssigned = EB_FALSE; entryPtr->scene_change_in_gop = EB_FALSE; entryPtr->extraApBitRatioI = 0; return EB_ErrorNone; } EbErrorType rate_control_coded_frames_stats_context_ctor( CodedFramesStatsEntry_t **entry_dbl_ptr, uint64_t picture_number) { CodedFramesStatsEntry_t *entryPtr; EB_MALLOC(CodedFramesStatsEntry_t*, entryPtr, sizeof(CodedFramesStatsEntry_t), EB_N_PTR); *entry_dbl_ptr = entryPtr; entryPtr->picture_number = picture_number; entryPtr->frameTotalBitActual = -1; return EB_ErrorNone; } EbErrorType rate_control_context_ctor( RateControlContext_t **context_dbl_ptr, EbFifo_t *rate_control_input_tasks_fifo_ptr, EbFifo_t *rate_control_output_results_fifo_ptr, int32_t intra_period_length) { uint32_t temporalIndex; uint32_t intervalIndex; #if OVERSHOOT_STAT_PRINT uint32_t pictureIndex; #endif EbErrorType return_error = EB_ErrorNone; RateControlContext_t *context_ptr; EB_MALLOC(RateControlContext_t*, context_ptr, sizeof(RateControlContext_t), EB_N_PTR); *context_dbl_ptr = context_ptr; context_ptr->rate_control_input_tasks_fifo_ptr = rate_control_input_tasks_fifo_ptr; context_ptr->rate_control_output_results_fifo_ptr = rate_control_output_results_fifo_ptr; // High level RC return_error = HighLevelRateControlContextCtor( &context_ptr->highLevelRateControlPtr); if (return_error == EB_ErrorInsufficientResources) { return EB_ErrorInsufficientResources; } for (temporalIndex = 0; temporalIndex < EB_MAX_TEMPORAL_LAYERS; temporalIndex++) { context_ptr->frames_in_interval[temporalIndex] = 0; } EB_MALLOC(RateControlIntervalParamContext_t**, context_ptr->rateControlParamQueue, sizeof(RateControlIntervalParamContext_t*)*PARALLEL_GOP_MAX_NUMBER, EB_N_PTR); context_ptr->rateControlParamQueueHeadIndex = 0; for (intervalIndex = 0; intervalIndex < PARALLEL_GOP_MAX_NUMBER; intervalIndex++) { return_error = rate_control_interval_param_context_ctor( &context_ptr->rateControlParamQueue[intervalIndex]); context_ptr->rateControlParamQueue[intervalIndex]->firstPoc = (intervalIndex*(uint32_t)(intra_period_length + 1)); context_ptr->rateControlParamQueue[intervalIndex]->lastPoc = ((intervalIndex + 1)*(uint32_t)(intra_period_length + 1)) - 1; if (return_error == EB_ErrorInsufficientResources) { return EB_ErrorInsufficientResources; } } #if OVERSHOOT_STAT_PRINT context_ptr->codedFramesStatQueueHeadIndex = 0; context_ptr->codedFramesStatQueueTailIndex = 0; EB_MALLOC(CodedFramesStatsEntry_t**, context_ptr->codedFramesStatQueue, sizeof(CodedFramesStatsEntry_t*)*CODED_FRAMES_STAT_QUEUE_MAX_DEPTH, EB_N_PTR); for (pictureIndex = 0; pictureIndex < CODED_FRAMES_STAT_QUEUE_MAX_DEPTH; ++pictureIndex) { return_error = rate_control_coded_frames_stats_context_ctor( &context_ptr->codedFramesStatQueue[pictureIndex], pictureIndex); if (return_error == EB_ErrorInsufficientResources) { return EB_ErrorInsufficientResources; } } context_ptr->maxBitActualPerSw = 0; context_ptr->maxBitActualPerGop = 0; #endif context_ptr->baseLayerFramesAvgQp = 0; context_ptr->baseLayerIntraFramesAvgQp = 0; context_ptr->intraCoefRate = 4; context_ptr->extraBits = 0; context_ptr->extraBitsGen = 0; context_ptr->maxRateAdjustDeltaQP = 0; return EB_ErrorNone; } void HighLevelRcInputPictureMode2( PictureParentControlSet_t *picture_control_set_ptr, SequenceControlSet_t *sequence_control_set_ptr, EncodeContext_t *encode_context_ptr, RateControlContext_t *context_ptr, HighLevelRateControlContext_t *highLevelRateControlPtr) { EbBool end_of_sequence_flag = EB_TRUE; HlRateControlHistogramEntry_t *hlRateControlHistogramPtrTemp; // Queue variables uint32_t queueEntryIndexTemp; uint32_t queueEntryIndexTemp2; uint32_t queueEntryIndexHeadTemp; uint64_t minLaBitDistance; uint32_t selectedRefQpTableIndex; uint32_t selectedRefQp; #if RC_UPDATE_TARGET_RATE uint32_t selectedOrgRefQp; #endif uint32_t previous_selected_ref_qp = encode_context_ptr->previous_selected_ref_qp; uint64_t max_coded_poc = encode_context_ptr->max_coded_poc; uint32_t max_coded_poc_selected_ref_qp = encode_context_ptr->max_coded_poc_selected_ref_qp; uint32_t refQpIndex; uint32_t refQpIndexTemp; uint32_t refQpTableIndex; uint32_t areaInPixel; uint32_t numOfFullLcus; uint32_t qpSearchMin; uint32_t qpSearchMax; int32_t qpStep = 1; EbBool bestQpFound; uint32_t temporal_layer_index; EbBool tables_updated; uint64_t bitConstraintPerSw = 0; RateControlTables_t *rateControlTablesPtr; EbBitNumber *sadBitsArrayPtr; EbBitNumber *intraSadBitsArrayPtr; uint32_t pred_bits_ref_qp; for (temporal_layer_index = 0; temporal_layer_index < EB_MAX_TEMPORAL_LAYERS; temporal_layer_index++) { picture_control_set_ptr->bits_per_sw_per_layer[temporal_layer_index] = 0; } picture_control_set_ptr->total_bits_per_gop = 0; areaInPixel = sequence_control_set_ptr->luma_width * sequence_control_set_ptr->luma_height;; eb_block_on_mutex(sequence_control_set_ptr->encode_context_ptr->rate_table_update_mutex); tables_updated = sequence_control_set_ptr->encode_context_ptr->rate_control_tables_array_updated; picture_control_set_ptr->percentage_updated = EB_FALSE; if (sequence_control_set_ptr->static_config.look_ahead_distance != 0) { // Increamenting the head of the hl_rate_control_historgram_queue and clean up the entores hlRateControlHistogramPtrTemp = (encode_context_ptr->hl_rate_control_historgram_queue[encode_context_ptr->hl_rate_control_historgram_queue_head_index]); while ((hlRateControlHistogramPtrTemp->lifeCount == 0) && hlRateControlHistogramPtrTemp->passedToHlrc) { eb_block_on_mutex(sequence_control_set_ptr->encode_context_ptr->hl_rate_control_historgram_queue_mutex); // Reset the Reorder Queue Entry hlRateControlHistogramPtrTemp->picture_number += INITIAL_RATE_CONTROL_REORDER_QUEUE_MAX_DEPTH; hlRateControlHistogramPtrTemp->lifeCount = -1; hlRateControlHistogramPtrTemp->passedToHlrc = EB_FALSE; hlRateControlHistogramPtrTemp->isCoded = EB_FALSE; hlRateControlHistogramPtrTemp->totalNumBitsCoded = 0; // Increment the Reorder Queue head Ptr encode_context_ptr->hl_rate_control_historgram_queue_head_index = (encode_context_ptr->hl_rate_control_historgram_queue_head_index == HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH - 1) ? 0 : encode_context_ptr->hl_rate_control_historgram_queue_head_index + 1; eb_release_mutex(sequence_control_set_ptr->encode_context_ptr->hl_rate_control_historgram_queue_mutex); hlRateControlHistogramPtrTemp = encode_context_ptr->hl_rate_control_historgram_queue[encode_context_ptr->hl_rate_control_historgram_queue_head_index]; } // For the case that number of frames in the sliding window is less than size of the look ahead or intra Refresh. i.e. end of sequence if ((picture_control_set_ptr->frames_in_sw < MIN(sequence_control_set_ptr->static_config.look_ahead_distance + 1, (uint32_t)sequence_control_set_ptr->intra_period_length + 1))) { selectedRefQp = max_coded_poc_selected_ref_qp; // Update the QP for the sliding window based on the status of RC if ((context_ptr->extraBitsGen > (int64_t)(context_ptr->virtualBufferSize << 3))) { selectedRefQp = (uint32_t)MAX((int32_t)selectedRefQp - 2, 0); } else if ((context_ptr->extraBitsGen > (int64_t)(context_ptr->virtualBufferSize << 2))) { selectedRefQp = (uint32_t)MAX((int32_t)selectedRefQp - 1, 0); } if ((context_ptr->extraBitsGen < -(int64_t)(context_ptr->virtualBufferSize << 2))) { selectedRefQp += 2; } else if ((context_ptr->extraBitsGen < -(int64_t)(context_ptr->virtualBufferSize << 1))) { selectedRefQp += 1; } if ((picture_control_set_ptr->frames_in_sw < (uint32_t)(sequence_control_set_ptr->intra_period_length + 1)) && (picture_control_set_ptr->picture_number % ((sequence_control_set_ptr->intra_period_length + 1)) == 0)) { selectedRefQp = (uint32_t)CLIP3( sequence_control_set_ptr->static_config.min_qp_allowed, sequence_control_set_ptr->static_config.max_qp_allowed, selectedRefQp + 1); } queueEntryIndexHeadTemp = (int32_t)(picture_control_set_ptr->picture_number - encode_context_ptr->hl_rate_control_historgram_queue[encode_context_ptr->hl_rate_control_historgram_queue_head_index]->picture_number); queueEntryIndexHeadTemp += encode_context_ptr->hl_rate_control_historgram_queue_head_index; queueEntryIndexHeadTemp = (queueEntryIndexHeadTemp > HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH - 1) ? queueEntryIndexHeadTemp - HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH : queueEntryIndexHeadTemp; queueEntryIndexTemp = queueEntryIndexHeadTemp; { hlRateControlHistogramPtrTemp = (encode_context_ptr->hl_rate_control_historgram_queue[queueEntryIndexTemp]); refQpIndexTemp = selectedRefQp + QP_OFFSET_LAYER_ARRAY[hlRateControlHistogramPtrTemp->temporal_layer_index]; refQpIndexTemp = (uint32_t)CLIP3( sequence_control_set_ptr->static_config.min_qp_allowed, sequence_control_set_ptr->static_config.max_qp_allowed, refQpIndexTemp); if (hlRateControlHistogramPtrTemp->slice_type == I_SLICE) { refQpIndexTemp = (uint32_t)MAX((int32_t)refQpIndexTemp + RC_INTRA_QP_OFFSET, 0); } hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] = 0; rateControlTablesPtr = &encode_context_ptr->rate_control_tables_array[refQpIndexTemp]; sadBitsArrayPtr = rateControlTablesPtr->sadBitsArray[hlRateControlHistogramPtrTemp->temporal_layer_index]; intraSadBitsArrayPtr = rateControlTablesPtr->intraSadBitsArray[hlRateControlHistogramPtrTemp->temporal_layer_index]; pred_bits_ref_qp = 0; numOfFullLcus = 0; if (hlRateControlHistogramPtrTemp->slice_type == I_SLICE) { // Loop over block in the frame and calculated the predicted bits at reg QP { unsigned i; uint32_t accum = 0; for (i = 0; i < NUMBER_OF_INTRA_SAD_INTERVALS; ++i) { accum += (uint32_t)(hlRateControlHistogramPtrTemp->ois_distortion_histogram[i] * intraSadBitsArrayPtr[i]); } pred_bits_ref_qp = accum; numOfFullLcus = hlRateControlHistogramPtrTemp->full_sb_count; } hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] += pred_bits_ref_qp; } else { { unsigned i; uint32_t accum = 0; for (i = 0; i < NUMBER_OF_SAD_INTERVALS; ++i) { accum += (uint32_t)(hlRateControlHistogramPtrTemp->me_distortion_histogram[i] * sadBitsArrayPtr[i]); } pred_bits_ref_qp = accum; numOfFullLcus = hlRateControlHistogramPtrTemp->full_sb_count; } hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] += pred_bits_ref_qp; } // Scale for in complete // pred_bits_ref_qp is normalized based on the area because of the LCUs at the picture boundries hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] = hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] * (uint64_t)areaInPixel / (numOfFullLcus << 12); // Store the pred_bits_ref_qp for the first frame in the window to PCS picture_control_set_ptr->pred_bits_ref_qp[refQpIndexTemp] = hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp]; } } else { // Loop over the QPs and find the best QP minLaBitDistance = MAX_UNSIGNED_VALUE; qpSearchMin = (uint8_t)CLIP3( sequence_control_set_ptr->static_config.min_qp_allowed, sequence_control_set_ptr->static_config.max_qp_allowed, (uint32_t)MAX((int32_t)sequence_control_set_ptr->qp - 20, 0)); qpSearchMax = (uint8_t)CLIP3( sequence_control_set_ptr->static_config.min_qp_allowed, sequence_control_set_ptr->static_config.max_qp_allowed, sequence_control_set_ptr->qp + 20); for (refQpTableIndex = qpSearchMin; refQpTableIndex < qpSearchMax; refQpTableIndex++) { highLevelRateControlPtr->predBitsRefQpPerSw[refQpTableIndex] = 0; } bitConstraintPerSw = highLevelRateControlPtr->bitConstraintPerSw * picture_control_set_ptr->frames_in_sw / (sequence_control_set_ptr->static_config.look_ahead_distance + 1); // Update the target rate for the sliding window based on the status of RC if ((context_ptr->extraBitsGen > (int64_t)(context_ptr->virtualBufferSize * 10))) { bitConstraintPerSw = bitConstraintPerSw * 130 / 100; } else if ((context_ptr->extraBitsGen > (int64_t)(context_ptr->virtualBufferSize << 3))) { bitConstraintPerSw = bitConstraintPerSw * 120 / 100; } else if ((context_ptr->extraBitsGen > (int64_t)(context_ptr->virtualBufferSize << 2))) { bitConstraintPerSw = bitConstraintPerSw * 110 / 100; } if ((context_ptr->extraBitsGen < -(int64_t)(context_ptr->virtualBufferSize << 3))) { bitConstraintPerSw = bitConstraintPerSw * 80 / 100; } else if ((context_ptr->extraBitsGen < -(int64_t)(context_ptr->virtualBufferSize << 2))) { bitConstraintPerSw = bitConstraintPerSw * 90 / 100; } // Loop over proper QPs and find the Predicted bits for that QP. Find the QP with the closest total predicted rate to target bits for the sliding window. previous_selected_ref_qp = CLIP3( qpSearchMin, qpSearchMax, previous_selected_ref_qp); refQpTableIndex = previous_selected_ref_qp; selectedRefQpTableIndex = refQpTableIndex; selectedRefQp = ref_qp_list_table[selectedRefQpTableIndex]; bestQpFound = EB_FALSE; while (refQpTableIndex >= qpSearchMin && refQpTableIndex <= qpSearchMax && !bestQpFound) { refQpIndex = CLIP3( sequence_control_set_ptr->static_config.min_qp_allowed, sequence_control_set_ptr->static_config.max_qp_allowed, ref_qp_list_table[refQpTableIndex]); highLevelRateControlPtr->predBitsRefQpPerSw[refQpIndex] = 0; // Finding the predicted bits for each frame in the sliding window at the reference Qp(s) queueEntryIndexHeadTemp = (int32_t)(picture_control_set_ptr->picture_number - encode_context_ptr->hl_rate_control_historgram_queue[encode_context_ptr->hl_rate_control_historgram_queue_head_index]->picture_number); queueEntryIndexHeadTemp += encode_context_ptr->hl_rate_control_historgram_queue_head_index; queueEntryIndexHeadTemp = (queueEntryIndexHeadTemp > HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH - 1) ? queueEntryIndexHeadTemp - HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH : queueEntryIndexHeadTemp; queueEntryIndexTemp = queueEntryIndexHeadTemp; // This is set to false, so the last frame would go inside the loop end_of_sequence_flag = EB_FALSE; while (!end_of_sequence_flag && queueEntryIndexTemp <= queueEntryIndexHeadTemp + sequence_control_set_ptr->static_config.look_ahead_distance) { queueEntryIndexTemp2 = (queueEntryIndexTemp > HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH - 1) ? queueEntryIndexTemp - HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH : queueEntryIndexTemp; hlRateControlHistogramPtrTemp = (encode_context_ptr->hl_rate_control_historgram_queue[queueEntryIndexTemp2]); refQpIndexTemp = refQpIndex + QP_OFFSET_LAYER_ARRAY[hlRateControlHistogramPtrTemp->temporal_layer_index]; refQpIndexTemp = (uint32_t)CLIP3( sequence_control_set_ptr->static_config.min_qp_allowed, sequence_control_set_ptr->static_config.max_qp_allowed, refQpIndexTemp); if (hlRateControlHistogramPtrTemp->slice_type == I_SLICE) { refQpIndexTemp = (uint32_t)MAX((int32_t)refQpIndexTemp + RC_INTRA_QP_OFFSET, 0); } hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] = 0; if (refQpTableIndex == previous_selected_ref_qp) { hlRateControlHistogramPtrTemp->lifeCount--; } if (hlRateControlHistogramPtrTemp->isCoded) { // If the frame is already coded, use the actual number of bits hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] = hlRateControlHistogramPtrTemp->totalNumBitsCoded; } else { rateControlTablesPtr = &encode_context_ptr->rate_control_tables_array[refQpIndexTemp]; sadBitsArrayPtr = rateControlTablesPtr->sadBitsArray[hlRateControlHistogramPtrTemp->temporal_layer_index]; intraSadBitsArrayPtr = rateControlTablesPtr->intraSadBitsArray[0]; pred_bits_ref_qp = 0; numOfFullLcus = 0; if (hlRateControlHistogramPtrTemp->slice_type == I_SLICE) { // Loop over block in the frame and calculated the predicted bits at reg QP unsigned i; uint32_t accum = 0; for (i = 0; i < NUMBER_OF_INTRA_SAD_INTERVALS; ++i) { accum += (uint32_t)(hlRateControlHistogramPtrTemp->ois_distortion_histogram[i] * intraSadBitsArrayPtr[i]); } pred_bits_ref_qp = accum; numOfFullLcus = hlRateControlHistogramPtrTemp->full_sb_count; hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] += pred_bits_ref_qp; } else { unsigned i; uint32_t accum = 0; uint32_t accumIntra = 0; for (i = 0; i < NUMBER_OF_SAD_INTERVALS; ++i) { accum += (uint32_t)(hlRateControlHistogramPtrTemp->me_distortion_histogram[i] * sadBitsArrayPtr[i]); accumIntra += (uint32_t)(hlRateControlHistogramPtrTemp->ois_distortion_histogram[i] * intraSadBitsArrayPtr[i]); } if (accum > accumIntra * 3) pred_bits_ref_qp = accumIntra; else pred_bits_ref_qp = accum; numOfFullLcus = hlRateControlHistogramPtrTemp->full_sb_count; hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] += pred_bits_ref_qp; } // Scale for in complete LCSs // pred_bits_ref_qp is normalized based on the area because of the LCUs at the picture boundries hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] = hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] * (uint64_t)areaInPixel / (numOfFullLcus << 12); } highLevelRateControlPtr->predBitsRefQpPerSw[refQpIndex] += hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp]; // Store the pred_bits_ref_qp for the first frame in the window to PCS if (queueEntryIndexHeadTemp == queueEntryIndexTemp2) picture_control_set_ptr->pred_bits_ref_qp[refQpIndexTemp] = hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp]; end_of_sequence_flag = hlRateControlHistogramPtrTemp->end_of_sequence_flag; queueEntryIndexTemp++; } if (minLaBitDistance >= (uint64_t)ABS((int64_t)highLevelRateControlPtr->predBitsRefQpPerSw[refQpIndex] - (int64_t)bitConstraintPerSw)) { minLaBitDistance = (uint64_t)ABS((int64_t)highLevelRateControlPtr->predBitsRefQpPerSw[refQpIndex] - (int64_t)bitConstraintPerSw); selectedRefQpTableIndex = refQpTableIndex; selectedRefQp = refQpIndex; } else { bestQpFound = EB_TRUE; } if (refQpTableIndex == previous_selected_ref_qp) { if (highLevelRateControlPtr->predBitsRefQpPerSw[refQpIndex] > bitConstraintPerSw) { qpStep = +1; } else { qpStep = -1; } } refQpTableIndex = (uint32_t)(refQpTableIndex + qpStep); } } #if RC_UPDATE_TARGET_RATE selectedOrgRefQp = selectedRefQp; if (sequence_control_set_ptr->intra_period_length != -1 && picture_control_set_ptr->picture_number % ((sequence_control_set_ptr->intra_period_length + 1)) == 0 && (int32_t)picture_control_set_ptr->frames_in_sw > sequence_control_set_ptr->intra_period_length) { if (picture_control_set_ptr->picture_number > 0) { picture_control_set_ptr->intra_selected_org_qp = (uint8_t)selectedRefQp; } else { selectedOrgRefQp = selectedRefQp + 1; selectedRefQp = selectedRefQp + 1; } refQpIndex = selectedRefQp; highLevelRateControlPtr->predBitsRefQpPerSw[refQpIndex] = 0; if (highLevelRateControlPtr->predBitsRefQpPerSw[refQpIndex] == 0) { // Finding the predicted bits for each frame in the sliding window at the reference Qp(s) //queueEntryIndexTemp = encode_context_ptr->hl_rate_control_historgram_queue_head_index; queueEntryIndexHeadTemp = (int32_t)(picture_control_set_ptr->picture_number - encode_context_ptr->hl_rate_control_historgram_queue[encode_context_ptr->hl_rate_control_historgram_queue_head_index]->picture_number); queueEntryIndexHeadTemp += encode_context_ptr->hl_rate_control_historgram_queue_head_index; queueEntryIndexHeadTemp = (queueEntryIndexHeadTemp > HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH - 1) ? queueEntryIndexHeadTemp - HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH : queueEntryIndexHeadTemp; queueEntryIndexTemp = queueEntryIndexHeadTemp; // This is set to false, so the last frame would go inside the loop end_of_sequence_flag = EB_FALSE; while (!end_of_sequence_flag && //queueEntryIndexTemp <= encode_context_ptr->hl_rate_control_historgram_queue_head_index+sequence_control_set_ptr->static_config.look_ahead_distance){ queueEntryIndexTemp <= queueEntryIndexHeadTemp + sequence_control_set_ptr->static_config.look_ahead_distance) { queueEntryIndexTemp2 = (queueEntryIndexTemp > HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH - 1) ? queueEntryIndexTemp - HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH : queueEntryIndexTemp; hlRateControlHistogramPtrTemp = (encode_context_ptr->hl_rate_control_historgram_queue[queueEntryIndexTemp2]); refQpIndexTemp = refQpIndex + QP_OFFSET_LAYER_ARRAY[hlRateControlHistogramPtrTemp->temporal_layer_index]; refQpIndexTemp = (uint32_t)CLIP3( sequence_control_set_ptr->static_config.min_qp_allowed, sequence_control_set_ptr->static_config.max_qp_allowed, refQpIndexTemp); if (hlRateControlHistogramPtrTemp->slice_type == I_SLICE) { refQpIndexTemp = (uint32_t)MAX((int32_t)refQpIndexTemp + RC_INTRA_QP_OFFSET, 0); } hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] = 0; if (hlRateControlHistogramPtrTemp->isCoded) { hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] = hlRateControlHistogramPtrTemp->totalNumBitsCoded; } else { rateControlTablesPtr = &encode_context_ptr->rate_control_tables_array[refQpIndexTemp]; sadBitsArrayPtr = rateControlTablesPtr->sadBitsArray[hlRateControlHistogramPtrTemp->temporal_layer_index]; intraSadBitsArrayPtr = rateControlTablesPtr->intraSadBitsArray[hlRateControlHistogramPtrTemp->temporal_layer_index]; pred_bits_ref_qp = 0; numOfFullLcus = 0; if (hlRateControlHistogramPtrTemp->slice_type == I_SLICE) { // Loop over block in the frame and calculated the predicted bits at reg QP { unsigned i; uint32_t accum = 0; for (i = 0; i < NUMBER_OF_INTRA_SAD_INTERVALS; ++i) { accum += (uint32_t)(hlRateControlHistogramPtrTemp->ois_distortion_histogram[i] * intraSadBitsArrayPtr[i]); } pred_bits_ref_qp = accum; numOfFullLcus = hlRateControlHistogramPtrTemp->full_sb_count; } hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] += pred_bits_ref_qp; } else { unsigned i; uint32_t accum = 0; uint32_t accumIntra = 0; for (i = 0; i < NUMBER_OF_SAD_INTERVALS; ++i) { accum += (uint32_t)(hlRateControlHistogramPtrTemp->me_distortion_histogram[i] * sadBitsArrayPtr[i]); accumIntra += (uint32_t)(hlRateControlHistogramPtrTemp->ois_distortion_histogram[i] * intraSadBitsArrayPtr[i]); } if (accum > accumIntra * 3) pred_bits_ref_qp = accumIntra; else pred_bits_ref_qp = accum; numOfFullLcus = hlRateControlHistogramPtrTemp->full_sb_count; hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] += pred_bits_ref_qp; } // Scale for in complete // pred_bits_ref_qp is normalized based on the area because of the LCUs at the picture boundries hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] = hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp] * (uint64_t)areaInPixel / (numOfFullLcus << 12); } highLevelRateControlPtr->predBitsRefQpPerSw[refQpIndex] += hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp]; // Store the pred_bits_ref_qp for the first frame in the window to PCS // if(encode_context_ptr->hl_rate_control_historgram_queue_head_index == queueEntryIndexTemp2) if (queueEntryIndexHeadTemp == queueEntryIndexTemp2) picture_control_set_ptr->pred_bits_ref_qp[refQpIndexTemp] = hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp]; end_of_sequence_flag = hlRateControlHistogramPtrTemp->end_of_sequence_flag; queueEntryIndexTemp++; } } } #endif picture_control_set_ptr->tables_updated = tables_updated; EbBool expensiveISlice = EB_FALSE; // Looping over the window to find the percentage of bit allocation in each layer if ((sequence_control_set_ptr->intra_period_length != -1) && ((int32_t)picture_control_set_ptr->frames_in_sw > sequence_control_set_ptr->intra_period_length) && ((int32_t)picture_control_set_ptr->frames_in_sw > sequence_control_set_ptr->intra_period_length)) { uint64_t iSliceBits = 0; if (picture_control_set_ptr->picture_number % ((sequence_control_set_ptr->intra_period_length + 1)) == 0) { queueEntryIndexHeadTemp = (int32_t)(picture_control_set_ptr->picture_number - encode_context_ptr->hl_rate_control_historgram_queue[encode_context_ptr->hl_rate_control_historgram_queue_head_index]->picture_number); queueEntryIndexHeadTemp += encode_context_ptr->hl_rate_control_historgram_queue_head_index; queueEntryIndexHeadTemp = (queueEntryIndexHeadTemp > HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH - 1) ? queueEntryIndexHeadTemp - HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH : queueEntryIndexHeadTemp; queueEntryIndexTemp = queueEntryIndexHeadTemp; // This is set to false, so the last frame would go inside the loop end_of_sequence_flag = EB_FALSE; while (!end_of_sequence_flag && queueEntryIndexTemp <= queueEntryIndexHeadTemp + sequence_control_set_ptr->intra_period_length) { queueEntryIndexTemp2 = (queueEntryIndexTemp > HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH - 1) ? queueEntryIndexTemp - HIGH_LEVEL_RATE_CONTROL_HISTOGRAM_QUEUE_MAX_DEPTH : queueEntryIndexTemp; hlRateControlHistogramPtrTemp = (encode_context_ptr->hl_rate_control_historgram_queue[queueEntryIndexTemp2]); refQpIndexTemp = selectedRefQp + QP_OFFSET_LAYER_ARRAY[hlRateControlHistogramPtrTemp->temporal_layer_index]; refQpIndexTemp = (uint32_t)CLIP3( sequence_control_set_ptr->static_config.min_qp_allowed, sequence_control_set_ptr->static_config.max_qp_allowed, refQpIndexTemp); if (hlRateControlHistogramPtrTemp->slice_type == I_SLICE) { refQpIndexTemp = (uint32_t)MAX((int32_t)refQpIndexTemp + RC_INTRA_QP_OFFSET, 0); } if (queueEntryIndexTemp == queueEntryIndexHeadTemp) { iSliceBits = hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp]; } picture_control_set_ptr->total_bits_per_gop += hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp]; picture_control_set_ptr->bits_per_sw_per_layer[hlRateControlHistogramPtrTemp->temporal_layer_index] += hlRateControlHistogramPtrTemp->pred_bits_ref_qp[refQpIndexTemp]; picture_control_set_ptr->percentage_updated = EB_TRUE; end_of_sequence_flag = hlRateControlHistogramPtrTemp->end_of_sequence_flag; queueEntryIndexTemp++; } if (iSliceBits * 100 > 85 * picture_control_set_ptr->total_bits_per_gop) { expensiveISlice = EB_TRUE; } if (picture_control_set_ptr->total_bits_per_gop == 0) { for (temporal_layer_index = 0; temporal_layer_index < EB_MAX_TEMPORAL_LAYERS; temporal_layer_index++) { picture_control_set_ptr->bits_per_sw_per_layer[temporal_layer_index] = rate_percentage_layer_array[sequence_control_set_ptr->static_config.hierarchical_levels][temporal_layer_index]; } } } } else { for (temporal_layer_index = 0; temporal_layer_index < EB_MAX_TEMPORAL_LAYERS; temporal_layer_index++) { picture_control_set_ptr->bits_per_sw_per_layer[temporal_layer_index] = rate_percentage_layer_array[sequence_control_set_ptr->static_config.hierarchical_levels][temporal_layer_index]; } } if (expensiveISlice) { if (tables_updated) { selectedRefQp = (uint32_t)MAX((int32_t)selectedRefQp - 1, 0); } else { selectedRefQp = (uint32_t)MAX((int32_t)selectedRefQp - 3, 0); } selectedRefQp = (uint32_t)CLIP3( sequence_control_set_ptr->static_config.min_qp_allowed, sequence_control_set_ptr->static_config.max_qp_allowed, selectedRefQp); } // Set the QP previous_selected_ref_qp = selectedRefQp; if (picture_control_set_ptr->picture_number > max_coded_poc && picture_control_set_ptr->temporal_layer_index < 2 && !picture_control_set_ptr->end_of_sequence_region) { max_coded_poc = picture_control_set_ptr->picture_number; max_coded_poc_selected_ref_qp = previous_selected_ref_qp; encode_context_ptr->previous_selected_ref_qp = previous_selected_ref_qp; encode_context_ptr->max_coded_poc = max_coded_poc; encode_context_ptr->max_coded_poc_selected_ref_qp = max_coded_poc_selected_ref_qp; } picture_control_set_ptr->best_pred_qp = (uint8_t)CLIP3( sequence_control_set_ptr->static_config.min_qp_allowed, sequence_control_set_ptr->static_config.max_qp_allowed, selectedRefQp + QP_OFFSET_LAYER_ARRAY[picture_control_set_ptr->temporal_layer_index]); if (picture_control_set_ptr->slice_type == I_SLICE) { picture_control_set_ptr->best_pred_qp = (uint8_t)MAX((int32_t)picture_control_set_ptr->best_pred_qp + RC_INTRA_QP_OFFSET, 0); } #if RC_UPDATE_TARGET_RATE if (picture_control_set_ptr->picture_number == 0) { highLevelRateControlPtr->prevIntraSelectedRefQp = selectedRefQp; highLevelRateControlPtr->prevIntraOrgSelectedRefQp = selectedRefQp; } if (sequence_control_set_ptr->intra_period_length != -1) { if (picture_control_set_ptr->picture_number % ((sequence_control_set_ptr->intra_period_length + 1)) == 0) { highLevelRateControlPtr->prevIntraSelectedRefQp = selectedRefQp; highLevelRateControlPtr->prevIntraOrgSelectedRefQp = selectedOrgRefQp; } } #endif picture_control_set_ptr->target_bits_best_pred_qp = picture_control_set_ptr->pred_bits_ref_qp[picture_control_set_ptr->best_pred_qp]; //if (picture_control_set_ptr->slice_type == 2) // { //printf("\nTID: %d\t", picture_control_set_ptr->temporal_layer_index); //printf("%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\n", // picture_control_set_ptr->picture_number, // picture_control_set_ptr->best_pred_qp, // (int32_t)picture_control_set_ptr->target_bits_best_pred_qp, // (int32_t)highLevelRateControlPtr->predBitsRefQpPerSw[selectedRefQp - 1], // (int32_t)highLevelRateControlPtr->predBitsRefQpPerSw[selectedRefQp], // (int32_t)highLevelRateControlPtr->predBitsRefQpPerSw[selectedRefQp + 1], // (int32_t)highLevelRateControlPtr->bitConstraintPerSw, // (int32_t)bitConstraintPerSw, // (int32_t)highLevelRateControlPtr->virtualBufferLevel); //} } eb_release_mutex(sequence_control_set_ptr->encode_context_ptr->rate_table_update_mutex); } #if ADD_DELTA_QP_SUPPORT || NEW_QPS static const uint8_t quantizer_to_qindex[] = { 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188, 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 249, 255, }; #endif #if NEW_QPS #define MAX_Q_INDEX 255 #define MIN_Q_INDEX 0 extern int16_t av1_ac_quant_Q3(int32_t qindex, int32_t delta, aom_bit_depth_t bit_depth); // These functions use formulaic calculations to make playing with the // quantizer tables easier. If necessary they can be replaced by lookup // tables if and when things settle down in the experimental bitstream double av1_convert_qindex_to_q(int32_t qindex, aom_bit_depth_t bit_depth) { // Convert the index to a real Q value (scaled down to match old Q values) switch (bit_depth) { case AOM_BITS_8: return av1_ac_quant_Q3(qindex, 0, bit_depth) / 4.0; case AOM_BITS_10: return av1_ac_quant_Q3(qindex, 0, bit_depth) / 16.0; case AOM_BITS_12: return av1_ac_quant_Q3(qindex, 0, bit_depth) / 64.0; default: assert(0 && "bit_depth should be AOM_BITS_8, AOM_BITS_10 or AOM_BITS_12"); return -1.0; } } int32_t av1_compute_qdelta(double qstart, double qtarget, aom_bit_depth_t bit_depth) { int32_t start_index = MAX_Q_INDEX; int32_t target_index = MAX_Q_INDEX; int32_t i; // Convert the average q value to an index. for (i = MIN_Q_INDEX; i < MAX_Q_INDEX; ++i) { start_index = i; if (av1_convert_qindex_to_q(i, bit_depth) >= qstart) break; } // Convert the q target to an index for (i = MIN_Q_INDEX; i < MAX_Q_INDEX; ++i) { target_index = i; if (av1_convert_qindex_to_q(i, bit_depth) >= qtarget) break; } return target_index - start_index; } #endif #if CONTENT_BASED_QPS typedef struct { // Rate targetting variables int base_frame_target; // A baseline frame target before adjustment // for previous under or over shoot. int this_frame_target; // Actual frame target after rc adjustment. int projected_frame_size; int sb64_target_rate; int last_q[FRAME_TYPES]; // Separate values for Intra/Inter int last_boosted_qindex; // Last boosted GF/KF/ARF q int last_kf_qindex; // Q index of the last key frame coded. int gfu_boost; int kf_boost; // double rate_correction_factors[RATE_FACTOR_LEVELS]; int frames_since_golden; int frames_till_gf_update_due; int min_gf_interval; int max_gf_interval; int static_scene_max_gf_interval; int baseline_gf_interval; int constrained_gf_group; int frames_to_key; int frames_since_key; int this_key_frame_forced; int next_key_frame_forced; int source_alt_ref_pending; int source_alt_ref_active; int is_src_frame_alt_ref; int sframe_due; // Length of the bi-predictive frame group interval int bipred_group_interval; // NOTE: Different types of frames may have different bits allocated // accordingly, aiming to achieve the overall optimal RD performance. int is_bwd_ref_frame; int is_last_bipred_frame; int is_bipred_frame; int is_src_frame_ext_arf; int avg_frame_bandwidth; // Average frame size target for clip int min_frame_bandwidth; // Minimum allocation used for any frame int max_frame_bandwidth; // Maximum burst rate allowed for a frame. int ni_av_qi; int ni_tot_qi; int ni_frames; int avg_frame_qindex[FRAME_TYPES]; double tot_q; double avg_q; int64_t buffer_level; int64_t bits_off_target; int64_t vbr_bits_off_target; int64_t vbr_bits_off_target_fast; int decimation_factor; int decimation_count; int rolling_target_bits; int rolling_actual_bits; int long_rolling_target_bits; int long_rolling_actual_bits; int rate_error_estimate; int64_t total_actual_bits; int64_t total_target_bits; int64_t total_target_vs_actual; int worst_quality; int best_quality; int64_t starting_buffer_level; int64_t optimal_buffer_level; int64_t maximum_buffer_size; // rate control history for last frame(1) and the frame before(2). // -1: undershot // 1: overshoot // 0: not initialized. int rc_1_frame; int rc_2_frame; int q_1_frame; int q_2_frame; // Auto frame-scaling variables. // int rf_level_maxq[RATE_FACTOR_LEVELS]; float_t arf_boost_factor; // Q index used for ALT frame int arf_q; } RATE_CONTROL; #define STATIC_MOTION_THRESH 95 enum { INTER_NORMAL = 0, INTER_LOW = 1, INTER_HIGH = 2, GF_ARF_LOW = 3, GF_ARF_STD = 4, KF_STD = 5, RATE_FACTOR_LEVELS = 6 } RATE_FACTOR_LEVEL; enum { KF_UPDATE = 0, LF_UPDATE = 1, GF_UPDATE = 2, ARF_UPDATE = 3, OVERLAY_UPDATE = 4, BRF_UPDATE = 5, // Backward Reference Frame LAST_BIPRED_UPDATE = 6, // Last Bi-predictive Frame BIPRED_UPDATE = 7, // Bi-predictive Frame, but not the last one INTNL_OVERLAY_UPDATE = 8, // Internal Overlay Frame INTNL_ARF_UPDATE = 9, // Internal Altref Frame (candidate for ALTREF2) FRAME_UPDATE_TYPES = 10 } FRAME_UPDATE_TYPE; // that are not marked as coded with 0,0 motion in the first pass. #define STATIC_KF_GROUP_THRESH 99 #define ASSIGN_MINQ_TABLE(bit_depth, name) \ do { \ switch (bit_depth) { \ case AOM_BITS_8: name = name##_8; break; \ case AOM_BITS_10: name = name##_10; break; \ case AOM_BITS_12: name = name##_12; break; \ default: \ assert(0 && \ "bit_depth should be AOM_BITS_8, AOM_BITS_10" \ " or AOM_BITS_12"); \ name = NULL; \ } \ } while (0) // Tables relating active max Q to active min Q static int kf_low_motion_minq_8[QINDEX_RANGE]; static int kf_high_motion_minq_8[QINDEX_RANGE]; static int arfgf_low_motion_minq_8[QINDEX_RANGE]; static int arfgf_high_motion_minq_8[QINDEX_RANGE]; static int inter_minq_8[QINDEX_RANGE]; static int rtc_minq_8[QINDEX_RANGE]; static int kf_low_motion_minq_10[QINDEX_RANGE]; static int kf_high_motion_minq_10[QINDEX_RANGE]; static int arfgf_low_motion_minq_10[QINDEX_RANGE]; static int arfgf_high_motion_minq_10[QINDEX_RANGE]; static int inter_minq_10[QINDEX_RANGE]; static int rtc_minq_10[QINDEX_RANGE]; static int kf_low_motion_minq_12[QINDEX_RANGE]; static int kf_high_motion_minq_12[QINDEX_RANGE]; static int arfgf_low_motion_minq_12[QINDEX_RANGE]; static int arfgf_high_motion_minq_12[QINDEX_RANGE]; static int inter_minq_12[QINDEX_RANGE]; static int rtc_minq_12[QINDEX_RANGE]; static int gf_high = 2000; static int gf_low = 400; static int kf_high = 5000; static int kf_low = 400; // Functions to compute the active minq lookup table entries based on a // formulaic approach to facilitate easier adjustment of the Q tables. // The formulae were derived from computing a 3rd order polynomial best // fit to the original data (after plotting real maxq vs minq (not q index)) static int get_minq_index(double maxq, double x3, double x2, double x1, aom_bit_depth_t bit_depth) { int i; const double minqtarget = AOMMIN(((x3 * maxq + x2) * maxq + x1) * maxq, maxq); // Special case handling to deal with the step from q2.0 // down to lossless mode represented by q 1.0. if (minqtarget <= 2.0) return 0; for (i = 0; i < QINDEX_RANGE; i++) { if (minqtarget <= av1_convert_qindex_to_q(i, bit_depth)) return i; } return QINDEX_RANGE - 1; } static void init_minq_luts(int *kf_low_m, int *kf_high_m, int *arfgf_low, int *arfgf_high, int *inter, int *rtc, aom_bit_depth_t bit_depth) { int i; for (i = 0; i < QINDEX_RANGE; i++) { const double maxq = av1_convert_qindex_to_q(i, bit_depth); kf_low_m[i] = get_minq_index(maxq, 0.000001, -0.0004, 0.150, bit_depth); kf_high_m[i] = get_minq_index(maxq, 0.0000021, -0.00125, 0.45, bit_depth); arfgf_low[i] = get_minq_index(maxq, 0.0000015, -0.0009, 0.30, bit_depth); arfgf_high[i] = get_minq_index(maxq, 0.0000021, -0.00125, 0.55, bit_depth); inter[i] = get_minq_index(maxq, 0.00000271, -0.00113, 0.90, bit_depth); rtc[i] = get_minq_index(maxq, 0.00000271, -0.00113, 0.70, bit_depth); } } void av1_rc_init_minq_luts(void) { init_minq_luts(kf_low_motion_minq_8, kf_high_motion_minq_8, arfgf_low_motion_minq_8, arfgf_high_motion_minq_8, inter_minq_8, rtc_minq_8, AOM_BITS_8); init_minq_luts(kf_low_motion_minq_10, kf_high_motion_minq_10, arfgf_low_motion_minq_10, arfgf_high_motion_minq_10, inter_minq_10, rtc_minq_10, AOM_BITS_10); init_minq_luts(kf_low_motion_minq_12, kf_high_motion_minq_12, arfgf_low_motion_minq_12, arfgf_high_motion_minq_12, inter_minq_12, rtc_minq_12, AOM_BITS_12); } static int get_active_quality(int q, int gfu_boost, int low, int high, int *low_motion_minq, int *high_motion_minq) { if (gfu_boost > high) { return low_motion_minq[q]; } else if (gfu_boost < low) { return high_motion_minq[q]; } else { const int gap = high - low; const int offset = high - gfu_boost; const int qdiff = high_motion_minq[q] - low_motion_minq[q]; const int adjustment = ((offset * qdiff) + (gap >> 1)) / gap; return low_motion_minq[q] + adjustment; } } static int get_kf_active_quality(const RATE_CONTROL *const rc, int q, aom_bit_depth_t bit_depth) { int *kf_low_motion_minq; int *kf_high_motion_minq; ASSIGN_MINQ_TABLE(bit_depth, kf_low_motion_minq); ASSIGN_MINQ_TABLE(bit_depth, kf_high_motion_minq); return get_active_quality(q, rc->kf_boost, kf_low, kf_high, kf_low_motion_minq, kf_high_motion_minq); } static int get_gf_active_quality(const RATE_CONTROL *const rc, int q, aom_bit_depth_t bit_depth) { int *arfgf_low_motion_minq; int *arfgf_high_motion_minq; ASSIGN_MINQ_TABLE(bit_depth, arfgf_low_motion_minq); ASSIGN_MINQ_TABLE(bit_depth, arfgf_high_motion_minq); return get_active_quality(q, rc->gfu_boost, gf_low, gf_high, arfgf_low_motion_minq, arfgf_high_motion_minq); } static int get_gf_high_motion_quality(int q, aom_bit_depth_t bit_depth) { int *arfgf_high_motion_minq; ASSIGN_MINQ_TABLE(bit_depth, arfgf_high_motion_minq); return arfgf_high_motion_minq[q]; } static int adaptive_qindex_calc( PictureControlSet_t *picture_control_set_ptr, RATE_CONTROL *rc, int qindex) { SequenceControlSet_t *sequence_control_set_ptr = picture_control_set_ptr->parent_pcs_ptr->sequence_control_set_ptr; const Av1Common *const cm = picture_control_set_ptr->parent_pcs_ptr->av1_cm; const int cq_level = qindex; int active_best_quality; int active_worst_quality = qindex; int q; int is_src_frame_alt_ref, refresh_golden_frame, refresh_alt_ref_frame, new_bwdref_update_rule, is_intrl_arf_boost, rf_level, update_type, this_height; is_src_frame_alt_ref = 0; refresh_golden_frame = frame_is_intra_only(picture_control_set_ptr->parent_pcs_ptr) ? 1: 0; refresh_alt_ref_frame = (picture_control_set_ptr->parent_pcs_ptr->temporal_layer_index == 0) ? 1 : 0; is_intrl_arf_boost = (picture_control_set_ptr->parent_pcs_ptr->temporal_layer_index > 0 && picture_control_set_ptr->parent_pcs_ptr->is_used_as_reference_flag) ? 1 : 0; new_bwdref_update_rule = (picture_control_set_ptr->slice_type != P_SLICE)? 1 : 0; rf_level = (frame_is_intra_only(picture_control_set_ptr->parent_pcs_ptr)) ? KF_STD : (picture_control_set_ptr->parent_pcs_ptr->temporal_layer_index == 0) ? GF_ARF_STD : picture_control_set_ptr->parent_pcs_ptr->is_used_as_reference_flag ? GF_ARF_LOW : INTER_NORMAL; update_type = (frame_is_intra_only(picture_control_set_ptr->parent_pcs_ptr)) ? KF_UPDATE : (picture_control_set_ptr->parent_pcs_ptr->temporal_layer_index == 0) ? ARF_UPDATE : picture_control_set_ptr->parent_pcs_ptr->is_used_as_reference_flag ? INTNL_ARF_UPDATE : LF_UPDATE; this_height = (frame_is_intra_only(picture_control_set_ptr->parent_pcs_ptr)) ? 0 : picture_control_set_ptr->parent_pcs_ptr->hierarchical_levels - picture_control_set_ptr->parent_pcs_ptr->temporal_layer_index; const int bit_depth = sequence_control_set_ptr->static_config.encoder_bit_depth; if (frame_is_intra_only(picture_control_set_ptr->parent_pcs_ptr)) { // Not forced keyframe. double q_adj_factor = 1.0; double q_val; rc->worst_quality = MAXQ; rc->best_quality = MINQ; // cross multiplication to derive kf_boost from non_moving_average_score; kf_boost range is [kf_low,kf_high], and non_moving_average_score range [NON_MOVING_SCORE_0,NON_MOVING_SCORE_3] rc->kf_boost = (((NON_MOVING_SCORE_3 - picture_control_set_ptr->parent_pcs_ptr->non_moving_index_average) * (kf_high - kf_low)) / NON_MOVING_SCORE_3) + kf_low; // Baseline value derived from cpi->active_worst_quality and kf boost. active_best_quality = get_kf_active_quality(rc, active_worst_quality, bit_depth); if (picture_control_set_ptr->parent_pcs_ptr->kf_zeromotion_pct >= STATIC_KF_GROUP_THRESH) { active_best_quality /= 3; } // Allow somewhat lower kf minq with small image formats. if ((cm->width * cm->height) <= (352 * 288)) { q_adj_factor -= 0.25; } // Make a further adjustment based on the kf zero motion measure. q_adj_factor += 0.05 - (0.001 * (double)picture_control_set_ptr->parent_pcs_ptr->kf_zeromotion_pct/*(double)cpi->twopass.kf_zeromotion_pct*/); // Convert the adjustment factor to a qindex delta // on active_best_quality. q_val = av1_convert_qindex_to_q(active_best_quality, bit_depth); active_best_quality += av1_compute_qdelta(q_val, q_val * q_adj_factor, bit_depth); } else if (!is_src_frame_alt_ref && (refresh_golden_frame || is_intrl_arf_boost || refresh_alt_ref_frame)) { rc->gfu_boost = (((NON_MOVING_SCORE_3 - picture_control_set_ptr->parent_pcs_ptr->non_moving_index_average) * (gf_high - gf_low)) / NON_MOVING_SCORE_3) + gf_low; rc->arf_boost_factor = 1; q = active_worst_quality; // non ref frame or repeated frames with re-encode if (!refresh_alt_ref_frame && !is_intrl_arf_boost) { active_best_quality = cq_level; } else { // base layer if (update_type == ARF_UPDATE) { active_best_quality = get_gf_active_quality(rc, q, bit_depth); //*arf_q = active_best_quality; rc->arf_q = active_best_quality; const int min_boost = get_gf_high_motion_quality(q, bit_depth); const int boost = min_boost - active_best_quality; active_best_quality = min_boost - (int)(boost * rc->arf_boost_factor); } else { active_best_quality = rc->arf_q; } // non Based Ref frames && !P if (new_bwdref_update_rule && is_intrl_arf_boost) { while (this_height < picture_control_set_ptr->parent_pcs_ptr->hierarchical_levels /*gf_group->pyramid_height*/) { active_best_quality = (active_best_quality + cq_level + 1) / 2; ++this_height; } } else { // Modify best quality for second level arfs. For mode AOM_Q this // becomes the baseline frame q. if (rf_level == GF_ARF_LOW) active_best_quality = (active_best_quality + cq_level + 1) / 2; } } } else { active_best_quality = cq_level; } q = active_best_quality; clamp(q, active_best_quality, active_worst_quality); return q; } #endif void* rate_control_kernel(void *input_ptr){ // Context RateControlContext_t *context_ptr = (RateControlContext_t*)input_ptr; // EncodeContext_t *encode_context_ptr; RateControlIntervalParamContext_t *rateControlParamPtr; RateControlIntervalParamContext_t *prevGopRateControlParamPtr; RateControlIntervalParamContext_t *nextGopRateControlParamPtr; PictureControlSet_t *picture_control_set_ptr; PictureParentControlSet_t *parentPictureControlSetPtr; // Config SequenceControlSet_t *sequence_control_set_ptr; // Input EbObjectWrapper_t *rateControlTasksWrapperPtr; RateControlTasks_t *rateControlTasksPtr; // Output EbObjectWrapper_t *rateControlResultsWrapperPtr; RateControlResults_t *rateControlResultsPtr; // SB Loop variables LargestCodingUnit_t *sb_ptr; uint32_t lcuCodingOrder; uint64_t totalNumberOfFbFrames = 0; RATE_CONTROL_TASKTYPES taskType; EbRateControlModel *rc_model_ptr; #if CONTENT_BASED_QPS RATE_CONTROL rc; #endif rate_control_model_ctor(&rc_model_ptr); for (;;) { // Get RateControl Task eb_get_full_object( context_ptr->rate_control_input_tasks_fifo_ptr, &rateControlTasksWrapperPtr); rateControlTasksPtr = (RateControlTasks_t*)rateControlTasksWrapperPtr->object_ptr; taskType = rateControlTasksPtr->taskType; // Modify these for different temporal layers later switch (taskType) { case RC_PICTURE_MANAGER_RESULT: picture_control_set_ptr = (PictureControlSet_t*)rateControlTasksPtr->pictureControlSetWrapperPtr->object_ptr; sequence_control_set_ptr = (SequenceControlSet_t*)picture_control_set_ptr->sequence_control_set_wrapper_ptr->object_ptr; // High level RC if (picture_control_set_ptr->picture_number == 0) { rate_control_model_init(rc_model_ptr, sequence_control_set_ptr); context_ptr->highLevelRateControlPtr->target_bit_rate = sequence_control_set_ptr->static_config.target_bit_rate; context_ptr->highLevelRateControlPtr->frame_rate = sequence_control_set_ptr->frame_rate; context_ptr->highLevelRateControlPtr->channelBitRatePerFrame = (uint64_t)MAX((int64_t)1, (int64_t)((context_ptr->highLevelRateControlPtr->target_bit_rate << RC_PRECISION) / context_ptr->highLevelRateControlPtr->frame_rate)); context_ptr->highLevelRateControlPtr->channelBitRatePerSw = context_ptr->highLevelRateControlPtr->channelBitRatePerFrame * (sequence_control_set_ptr->static_config.look_ahead_distance + 1); context_ptr->highLevelRateControlPtr->bitConstraintPerSw = context_ptr->highLevelRateControlPtr->channelBitRatePerSw; #if RC_UPDATE_TARGET_RATE context_ptr->highLevelRateControlPtr->previousUpdatedBitConstraintPerSw = context_ptr->highLevelRateControlPtr->channelBitRatePerSw; #endif #if CONTENT_BASED_QPS av1_rc_init_minq_luts(); #endif int32_t totalFrameInInterval = sequence_control_set_ptr->intra_period_length; uint32_t gopPeriod = (1 << picture_control_set_ptr->parent_pcs_ptr->hierarchical_levels); context_ptr->frame_rate = sequence_control_set_ptr->frame_rate; while (totalFrameInInterval >= 0) { if (totalFrameInInterval % (gopPeriod) == 0) context_ptr->frames_in_interval[0] ++; else if (totalFrameInInterval % (gopPeriod >> 1) == 0) context_ptr->frames_in_interval[1] ++; else if (totalFrameInInterval % (gopPeriod >> 2) == 0) context_ptr->frames_in_interval[2] ++; else if (totalFrameInInterval % (gopPeriod >> 3) == 0) context_ptr->frames_in_interval[3] ++; else if (totalFrameInInterval % (gopPeriod >> 4) == 0) context_ptr->frames_in_interval[4] ++; else if (totalFrameInInterval % (gopPeriod >> 5) == 0) context_ptr->frames_in_interval[5] ++; totalFrameInInterval--; } context_ptr->virtualBufferSize = (((uint64_t)sequence_control_set_ptr->static_config.target_bit_rate * 3) << RC_PRECISION) / (context_ptr->frame_rate); context_ptr->rateAveragePeriodinFrames = (uint64_t)sequence_control_set_ptr->static_config.intra_period_length + 1; context_ptr->virtualBufferLevelInitialValue = context_ptr->virtualBufferSize >> 1; context_ptr->virtualBufferLevel = context_ptr->virtualBufferSize >> 1; context_ptr->previousVirtualBufferLevel = context_ptr->virtualBufferSize >> 1; context_ptr->vbFillThreshold1 = (context_ptr->virtualBufferSize * 6) >> 3; context_ptr->vbFillThreshold2 = (context_ptr->virtualBufferSize << 3) >> 3; context_ptr->baseLayerFramesAvgQp = sequence_control_set_ptr->qp; context_ptr->baseLayerIntraFramesAvgQp = sequence_control_set_ptr->qp; } if (sequence_control_set_ptr->static_config.rate_control_mode) { picture_control_set_ptr->parent_pcs_ptr->intra_selected_org_qp = 0; HighLevelRcInputPictureMode2( picture_control_set_ptr->parent_pcs_ptr, sequence_control_set_ptr, sequence_control_set_ptr->encode_context_ptr, context_ptr, context_ptr->highLevelRateControlPtr); } // Frame level RC if (sequence_control_set_ptr->intra_period_length == -1 || sequence_control_set_ptr->static_config.rate_control_mode == 0) { rateControlParamPtr = context_ptr->rateControlParamQueue[0]; prevGopRateControlParamPtr = context_ptr->rateControlParamQueue[0]; nextGopRateControlParamPtr = context_ptr->rateControlParamQueue[0]; } else { uint32_t intervalIndexTemp = 0; EbBool intervalFound = EB_FALSE; while ((intervalIndexTemp < PARALLEL_GOP_MAX_NUMBER) && !intervalFound) { if (picture_control_set_ptr->picture_number >= context_ptr->rateControlParamQueue[intervalIndexTemp]->firstPoc && picture_control_set_ptr->picture_number <= context_ptr->rateControlParamQueue[intervalIndexTemp]->lastPoc) { intervalFound = EB_TRUE; } else { intervalIndexTemp++; } } CHECK_REPORT_ERROR( intervalIndexTemp != PARALLEL_GOP_MAX_NUMBER, sequence_control_set_ptr->encode_context_ptr->app_callback_ptr, EB_ENC_RC_ERROR2); rateControlParamPtr = context_ptr->rateControlParamQueue[intervalIndexTemp]; prevGopRateControlParamPtr = (intervalIndexTemp == 0) ? context_ptr->rateControlParamQueue[PARALLEL_GOP_MAX_NUMBER - 1] : context_ptr->rateControlParamQueue[intervalIndexTemp - 1]; nextGopRateControlParamPtr = (intervalIndexTemp == PARALLEL_GOP_MAX_NUMBER - 1) ? context_ptr->rateControlParamQueue[0] : context_ptr->rateControlParamQueue[intervalIndexTemp + 1]; } if (sequence_control_set_ptr->static_config.rate_control_mode == 0) { // if RC mode is 0, fixed QP is used // QP scaling based on POC number for Flat IPPP structure #if NEW_QPS picture_control_set_ptr->parent_pcs_ptr->base_qindex = quantizer_to_qindex[picture_control_set_ptr->picture_qp]; #endif if ( sequence_control_set_ptr->static_config.enable_qp_scaling_flag && picture_control_set_ptr->parent_pcs_ptr->qp_on_the_fly == EB_FALSE) { #if NEW_QPS const int32_t qindex = quantizer_to_qindex[(uint8_t)sequence_control_set_ptr->qp]; const double q_val = av1_convert_qindex_to_q(qindex, (aom_bit_depth_t)sequence_control_set_ptr->static_config.encoder_bit_depth); #if CONTENT_BASED_QPS if (picture_control_set_ptr->slice_type == I_SLICE) { int32_t new_qindex = adaptive_qindex_calc( picture_control_set_ptr, &rc, qindex); picture_control_set_ptr->parent_pcs_ptr->base_qindex = (uint8_t)CLIP3( (int32_t)quantizer_to_qindex[sequence_control_set_ptr->static_config.min_qp_allowed], (int32_t)quantizer_to_qindex[sequence_control_set_ptr->static_config.max_qp_allowed], (int32_t)(new_qindex)); } #else if (picture_control_set_ptr->slice_type == I_SLICE) { const int32_t delta_qindex = av1_compute_qdelta( q_val, q_val * 0.25, (aom_bit_depth_t)sequence_control_set_ptr->static_config.encoder_bit_depth); picture_control_set_ptr->parent_pcs_ptr->base_qindex = (uint8_t)CLIP3( (int32_t)quantizer_to_qindex[sequence_control_set_ptr->static_config.min_qp_allowed], (int32_t)quantizer_to_qindex[sequence_control_set_ptr->static_config.max_qp_allowed], (int32_t)(qindex + delta_qindex)); } #endif else { #if NEW_PRED_STRUCT const double delta_rate_new[2][6] = { { 0.40, 0.7, 0.85, 1.0, 1.0, 1.0 }, { 0.35, 0.6, 0.8, 0.9, 1.0, 1.0 } }; #else const double delta_rate_new[6] = { 0.40, 0.7, 0.85, 1.0, 1.0, 1.0 }; #endif const int32_t delta_qindex = av1_compute_qdelta( q_val, #if NEW_PRED_STRUCT q_val * delta_rate_new[picture_control_set_ptr->parent_pcs_ptr->hierarchical_levels == 4][picture_control_set_ptr->parent_pcs_ptr->temporal_layer_index], #else q_val * delta_rate_new[picture_control_set_ptr->parent_pcs_ptr->temporal_layer_index], #endif (aom_bit_depth_t)sequence_control_set_ptr->static_config.encoder_bit_depth); picture_control_set_ptr->parent_pcs_ptr->base_qindex = (uint8_t)CLIP3( (int32_t)quantizer_to_qindex[sequence_control_set_ptr->static_config.min_qp_allowed], (int32_t)quantizer_to_qindex[sequence_control_set_ptr->static_config.max_qp_allowed], (int32_t)(qindex + delta_qindex)); } #endif picture_control_set_ptr->picture_qp = (uint8_t)CLIP3((int32_t)sequence_control_set_ptr->static_config.min_qp_allowed, (int32_t)sequence_control_set_ptr->static_config.max_qp_allowed, picture_control_set_ptr->parent_pcs_ptr->base_qindex >> 2); } else if (picture_control_set_ptr->parent_pcs_ptr->qp_on_the_fly == EB_TRUE) { picture_control_set_ptr->picture_qp = (uint8_t)CLIP3((int32_t)sequence_control_set_ptr->static_config.min_qp_allowed, (int32_t)sequence_control_set_ptr->static_config.max_qp_allowed, picture_control_set_ptr->parent_pcs_ptr->picture_qp); #if NEW_QPS picture_control_set_ptr->parent_pcs_ptr->base_qindex = quantizer_to_qindex[picture_control_set_ptr->picture_qp]; #endif } picture_control_set_ptr->parent_pcs_ptr->picture_qp = picture_control_set_ptr->picture_qp; } else { picture_control_set_ptr->picture_qp = rate_control_get_quantizer(rc_model_ptr, picture_control_set_ptr->parent_pcs_ptr); if (picture_control_set_ptr->picture_number == rateControlParamPtr->firstPoc && picture_control_set_ptr->picture_number != 0 && !prevGopRateControlParamPtr->scene_change_in_gop) { int16_t deltaApQp = (int16_t)prevGopRateControlParamPtr->firstPicActualQp - (int16_t)prevGopRateControlParamPtr->firstPicPredQp; int64_t extraApBitRatio = (prevGopRateControlParamPtr->firstPicPredBits != 0) ? (((int64_t)prevGopRateControlParamPtr->firstPicActualBits - (int64_t)prevGopRateControlParamPtr->firstPicPredBits) * 100) / ((int64_t)prevGopRateControlParamPtr->firstPicPredBits) : 0; extraApBitRatio += (int64_t)deltaApQp * 15; if (extraApBitRatio > 200) { picture_control_set_ptr->picture_qp = picture_control_set_ptr->picture_qp + 3; } else if (extraApBitRatio > 100) { picture_control_set_ptr->picture_qp = picture_control_set_ptr->picture_qp + 2; } else if (extraApBitRatio > 50) { picture_control_set_ptr->picture_qp++; } } if (picture_control_set_ptr->picture_number == rateControlParamPtr->firstPoc && picture_control_set_ptr->picture_number != 0) { uint8_t qpIncAllowed = 3; uint8_t qpDecAllowed = 4; if (picture_control_set_ptr->parent_pcs_ptr->intra_selected_org_qp + 10 <= prevGopRateControlParamPtr->firstPicActualQp) { qpDecAllowed = (uint8_t)(prevGopRateControlParamPtr->firstPicActualQp - picture_control_set_ptr->parent_pcs_ptr->intra_selected_org_qp) >> 1; } if (picture_control_set_ptr->parent_pcs_ptr->intra_selected_org_qp >= prevGopRateControlParamPtr->firstPicActualQp + 10) { qpIncAllowed = (uint8_t)(picture_control_set_ptr->parent_pcs_ptr->intra_selected_org_qp - prevGopRateControlParamPtr->firstPicActualQp) * 2 / 3; if (prevGopRateControlParamPtr->firstPicActualQp <= 15) qpIncAllowed += 5; else if (prevGopRateControlParamPtr->firstPicActualQp <= 20) qpIncAllowed += 4; else if (prevGopRateControlParamPtr->firstPicActualQp <= 25) qpIncAllowed += 3; } else if (prevGopRateControlParamPtr->scene_change_in_gop) { qpIncAllowed = 5; } if (picture_control_set_ptr->parent_pcs_ptr->end_of_sequence_region) { qpIncAllowed += 2; qpDecAllowed += 4; } picture_control_set_ptr->picture_qp = (uint8_t)CLIP3( (uint32_t)MAX((int32_t)prevGopRateControlParamPtr->firstPicActualQp - (int32_t)qpDecAllowed, 0), (uint32_t)prevGopRateControlParamPtr->firstPicActualQp + qpIncAllowed, picture_control_set_ptr->picture_qp); } // Scene change if (picture_control_set_ptr->slice_type == I_SLICE && picture_control_set_ptr->picture_number != rateControlParamPtr->firstPoc) { if (nextGopRateControlParamPtr->firstPicActualQpAssigned) { picture_control_set_ptr->picture_qp = (uint8_t)CLIP3( (uint32_t)MAX((int32_t)nextGopRateControlParamPtr->firstPicActualQp - (int32_t)1, 0), (uint32_t)nextGopRateControlParamPtr->firstPicActualQp + 8, picture_control_set_ptr->picture_qp); } else { if (rateControlParamPtr->firstPicActualQp < 20) { picture_control_set_ptr->picture_qp = (uint8_t)CLIP3( (uint32_t)MAX((int32_t)rateControlParamPtr->firstPicActualQp - (int32_t)4, 0), (uint32_t)rateControlParamPtr->firstPicActualQp + 10, picture_control_set_ptr->picture_qp); } else { picture_control_set_ptr->picture_qp = (uint8_t)CLIP3( (uint32_t)MAX((int32_t)rateControlParamPtr->firstPicActualQp - (int32_t)4, 0), (uint32_t)rateControlParamPtr->firstPicActualQp + 8, picture_control_set_ptr->picture_qp); } } } picture_control_set_ptr->picture_qp = (uint8_t)CLIP3( sequence_control_set_ptr->static_config.min_qp_allowed, sequence_control_set_ptr->static_config.max_qp_allowed, picture_control_set_ptr->picture_qp); #if NEW_QPS picture_control_set_ptr->parent_pcs_ptr->base_qindex = quantizer_to_qindex[picture_control_set_ptr->picture_qp]; #endif } picture_control_set_ptr->parent_pcs_ptr->picture_qp = picture_control_set_ptr->picture_qp; if (picture_control_set_ptr->parent_pcs_ptr->temporal_layer_index == 0 && sequence_control_set_ptr->static_config.look_ahead_distance != 0) { context_ptr->baseLayerFramesAvgQp = (3 * context_ptr->baseLayerFramesAvgQp + picture_control_set_ptr->picture_qp + 2) >> 2; } if (picture_control_set_ptr->slice_type == I_SLICE) { if (picture_control_set_ptr->picture_number == rateControlParamPtr->firstPoc) { rateControlParamPtr->firstPicPredQp = (uint16_t)picture_control_set_ptr->parent_pcs_ptr->best_pred_qp; rateControlParamPtr->firstPicActualQp = (uint16_t)picture_control_set_ptr->picture_qp; rateControlParamPtr->scene_change_in_gop = picture_control_set_ptr->parent_pcs_ptr->scene_change_in_gop; rateControlParamPtr->firstPicActualQpAssigned = EB_TRUE; } { if (picture_control_set_ptr->picture_number == rateControlParamPtr->firstPoc) { if (sequence_control_set_ptr->static_config.look_ahead_distance != 0) { context_ptr->baseLayerIntraFramesAvgQp = (3 * context_ptr->baseLayerIntraFramesAvgQp + picture_control_set_ptr->picture_qp + 2) >> 2; } } if (picture_control_set_ptr->picture_number == rateControlParamPtr->firstPoc) { rateControlParamPtr->intraFramesQp = picture_control_set_ptr->picture_qp; rateControlParamPtr->nextGopIntraFrameQp = picture_control_set_ptr->picture_qp; } } } picture_control_set_ptr->parent_pcs_ptr->average_qp = 0; for (lcuCodingOrder = 0; lcuCodingOrder < sequence_control_set_ptr->sb_tot_cnt; ++lcuCodingOrder) { sb_ptr = picture_control_set_ptr->sb_ptr_array[lcuCodingOrder]; #if ADD_DELTA_QP_SUPPORT sb_ptr->qp = quantizer_to_qindex[picture_control_set_ptr->picture_qp]; #else sb_ptr->qp = (uint8_t)picture_control_set_ptr->picture_qp; #endif picture_control_set_ptr->parent_pcs_ptr->average_qp += sb_ptr->qp; } // Get Empty Rate Control Results Buffer eb_get_empty_object( context_ptr->rate_control_output_results_fifo_ptr, &rateControlResultsWrapperPtr); rateControlResultsPtr = (RateControlResults_t*)rateControlResultsWrapperPtr->object_ptr; rateControlResultsPtr->pictureControlSetWrapperPtr = rateControlTasksPtr->pictureControlSetWrapperPtr; // Post Full Rate Control Results eb_post_full_object(rateControlResultsWrapperPtr); // Release Rate Control Tasks eb_release_object(rateControlTasksWrapperPtr); break; case RC_PACKETIZATION_FEEDBACK_RESULT: parentPictureControlSetPtr = (PictureParentControlSet_t*)rateControlTasksPtr->pictureControlSetWrapperPtr->object_ptr; sequence_control_set_ptr = (SequenceControlSet_t*)parentPictureControlSetPtr->sequence_control_set_wrapper_ptr->object_ptr; if (sequence_control_set_ptr->static_config.rate_control_mode) { rate_control_update_model(rc_model_ptr, parentPictureControlSetPtr); } // Frame level RC if (sequence_control_set_ptr->intra_period_length == -1 || sequence_control_set_ptr->static_config.rate_control_mode == 0) { rateControlParamPtr = context_ptr->rateControlParamQueue[0]; prevGopRateControlParamPtr = context_ptr->rateControlParamQueue[0]; if (parentPictureControlSetPtr->slice_type == I_SLICE) { if (parentPictureControlSetPtr->total_num_bits > MAX_BITS_PER_FRAME) { context_ptr->maxRateAdjustDeltaQP++; } else if (context_ptr->maxRateAdjustDeltaQP > 0 && parentPictureControlSetPtr->total_num_bits < MAX_BITS_PER_FRAME * 85 / 100) { context_ptr->maxRateAdjustDeltaQP--; } context_ptr->maxRateAdjustDeltaQP = CLIP3(0, 63, context_ptr->maxRateAdjustDeltaQP); context_ptr->maxRateAdjustDeltaQP = 0; } } else { uint32_t intervalIndexTemp = 0; EbBool intervalFound = EB_FALSE; while ((intervalIndexTemp < PARALLEL_GOP_MAX_NUMBER) && !intervalFound) { if (parentPictureControlSetPtr->picture_number >= context_ptr->rateControlParamQueue[intervalIndexTemp]->firstPoc && parentPictureControlSetPtr->picture_number <= context_ptr->rateControlParamQueue[intervalIndexTemp]->lastPoc) { intervalFound = EB_TRUE; } else { intervalIndexTemp++; } } CHECK_REPORT_ERROR( intervalIndexTemp != PARALLEL_GOP_MAX_NUMBER, sequence_control_set_ptr->encode_context_ptr->app_callback_ptr, EB_ENC_RC_ERROR2); rateControlParamPtr = context_ptr->rateControlParamQueue[intervalIndexTemp]; prevGopRateControlParamPtr = (intervalIndexTemp == 0) ? context_ptr->rateControlParamQueue[PARALLEL_GOP_MAX_NUMBER - 1] : context_ptr->rateControlParamQueue[intervalIndexTemp - 1]; } if (sequence_control_set_ptr->static_config.rate_control_mode != 0) { context_ptr->previousVirtualBufferLevel = context_ptr->virtualBufferLevel; context_ptr->virtualBufferLevel = (int64_t)context_ptr->previousVirtualBufferLevel + (int64_t)parentPictureControlSetPtr->total_num_bits - (int64_t)context_ptr->highLevelRateControlPtr->channelBitRatePerFrame; } // Queue variables #if OVERSHOOT_STAT_PRINT if (sequence_control_set_ptr->intra_period_length != -1) { int32_t queueEntryIndex; uint32_t queueEntryIndexTemp; uint32_t queueEntryIndexTemp2; CodedFramesStatsEntry_t *queueEntryPtr; EbBool moveSlideWondowFlag = EB_TRUE; EbBool end_of_sequence_flag = EB_TRUE; uint32_t frames_in_sw; // Determine offset from the Head Ptr queueEntryIndex = (int32_t)(parentPictureControlSetPtr->picture_number - context_ptr->codedFramesStatQueue[context_ptr->codedFramesStatQueueHeadIndex]->picture_number); queueEntryIndex += context_ptr->codedFramesStatQueueHeadIndex; queueEntryIndex = (queueEntryIndex > CODED_FRAMES_STAT_QUEUE_MAX_DEPTH - 1) ? queueEntryIndex - CODED_FRAMES_STAT_QUEUE_MAX_DEPTH : queueEntryIndex; queueEntryPtr = context_ptr->codedFramesStatQueue[queueEntryIndex]; queueEntryPtr->frameTotalBitActual = (uint64_t)parentPictureControlSetPtr->total_num_bits; queueEntryPtr->picture_number = parentPictureControlSetPtr->picture_number; queueEntryPtr->end_of_sequence_flag = parentPictureControlSetPtr->end_of_sequence_flag; context_ptr->rateAveragePeriodinFrames = (uint64_t)sequence_control_set_ptr->static_config.intra_period_length + 1; //printf("\n0_POC: %d\n", // queueEntryPtr->picture_number); moveSlideWondowFlag = EB_TRUE; while (moveSlideWondowFlag) { // printf("\n1_POC: %d\n", // queueEntryPtr->picture_number); // Check if the sliding window condition is valid queueEntryIndexTemp = context_ptr->codedFramesStatQueueHeadIndex; if (context_ptr->codedFramesStatQueue[queueEntryIndexTemp]->frameTotalBitActual != -1) { end_of_sequence_flag = context_ptr->codedFramesStatQueue[queueEntryIndexTemp]->end_of_sequence_flag; } else { end_of_sequence_flag = EB_FALSE; } while (moveSlideWondowFlag && !end_of_sequence_flag && queueEntryIndexTemp < context_ptr->codedFramesStatQueueHeadIndex + context_ptr->rateAveragePeriodinFrames) { // printf("\n2_POC: %d\n", // queueEntryPtr->picture_number); queueEntryIndexTemp2 = (queueEntryIndexTemp > CODED_FRAMES_STAT_QUEUE_MAX_DEPTH - 1) ? queueEntryIndexTemp - CODED_FRAMES_STAT_QUEUE_MAX_DEPTH : queueEntryIndexTemp; moveSlideWondowFlag = (EbBool)(moveSlideWondowFlag && (context_ptr->codedFramesStatQueue[queueEntryIndexTemp2]->frameTotalBitActual != -1)); if (context_ptr->codedFramesStatQueue[queueEntryIndexTemp2]->frameTotalBitActual != -1) { // check if it is the last frame. If we have reached the last frame, we would output the buffered frames in the Queue. end_of_sequence_flag = context_ptr->codedFramesStatQueue[queueEntryIndexTemp]->end_of_sequence_flag; } else { end_of_sequence_flag = EB_FALSE; } queueEntryIndexTemp = (queueEntryIndexTemp == CODED_FRAMES_STAT_QUEUE_MAX_DEPTH - 1) ? 0 : queueEntryIndexTemp + 1; } if (moveSlideWondowFlag) { //get a new entry spot queueEntryPtr = (context_ptr->codedFramesStatQueue[context_ptr->codedFramesStatQueueHeadIndex]); queueEntryIndexTemp = context_ptr->codedFramesStatQueueHeadIndex; // This is set to false, so the last frame would go inside the loop end_of_sequence_flag = EB_FALSE; frames_in_sw = 0; context_ptr->totalBitActualPerSw = 0; while (!end_of_sequence_flag && queueEntryIndexTemp < context_ptr->codedFramesStatQueueHeadIndex + context_ptr->rateAveragePeriodinFrames) { frames_in_sw++; queueEntryIndexTemp2 = (queueEntryIndexTemp > CODED_FRAMES_STAT_QUEUE_MAX_DEPTH - 1) ? queueEntryIndexTemp - CODED_FRAMES_STAT_QUEUE_MAX_DEPTH : queueEntryIndexTemp; context_ptr->totalBitActualPerSw += context_ptr->codedFramesStatQueue[queueEntryIndexTemp2]->frameTotalBitActual; end_of_sequence_flag = context_ptr->codedFramesStatQueue[queueEntryIndexTemp2]->end_of_sequence_flag; queueEntryIndexTemp = (queueEntryIndexTemp == CODED_FRAMES_STAT_QUEUE_MAX_DEPTH - 1) ? 0 : queueEntryIndexTemp + 1; } // //if(frames_in_sw == context_ptr->rateAveragePeriodinFrames) // printf("POC:%d\t %.3f\n", queueEntryPtr->picture_number, (double)context_ptr->totalBitActualPerSw*(sequence_control_set_ptr->frame_rate>> RC_PRECISION)/(double)frames_in_sw/1000); if (frames_in_sw == (uint32_t)sequence_control_set_ptr->intra_period_length + 1) { context_ptr->maxBitActualPerSw = MAX(context_ptr->maxBitActualPerSw, context_ptr->totalBitActualPerSw*(sequence_control_set_ptr->frame_rate >> RC_PRECISION) / frames_in_sw / 1000); if (queueEntryPtr->picture_number % ((sequence_control_set_ptr->intra_period_length + 1)) == 0) { context_ptr->maxBitActualPerGop = MAX(context_ptr->maxBitActualPerGop, context_ptr->totalBitActualPerSw*(sequence_control_set_ptr->frame_rate >> RC_PRECISION) / frames_in_sw / 1000); if (context_ptr->totalBitActualPerSw > sequence_control_set_ptr->static_config.maxBufferSize) { printf("\nPOC:%d\tOvershoot:%.0f%% \n", (int32_t)queueEntryPtr->picture_number, (double)((int64_t)context_ptr->totalBitActualPerSw * 100 / (int64_t)sequence_control_set_ptr->static_config.maxBufferSize - 100)); } } } if (frames_in_sw == context_ptr->rateAveragePeriodinFrames - 1) { printf("\n%d MAX\n", (int32_t)context_ptr->maxBitActualPerSw); printf("\n%d GopMa\n", (int32_t)context_ptr->maxBitActualPerGop); } // Reset the Queue Entry queueEntryPtr->picture_number += CODED_FRAMES_STAT_QUEUE_MAX_DEPTH; queueEntryPtr->frameTotalBitActual = -1; // Increment the Reorder Queue head Ptr context_ptr->codedFramesStatQueueHeadIndex = (context_ptr->codedFramesStatQueueHeadIndex == CODED_FRAMES_STAT_QUEUE_MAX_DEPTH - 1) ? 0 : context_ptr->codedFramesStatQueueHeadIndex + 1; queueEntryPtr = (context_ptr->codedFramesStatQueue[context_ptr->codedFramesStatQueueHeadIndex]); } } } #endif totalNumberOfFbFrames++; // Release the SequenceControlSet eb_release_object(parentPictureControlSetPtr->sequence_control_set_wrapper_ptr); // Release the input buffer eb_release_object(parentPictureControlSetPtr->input_picture_wrapper_ptr); // Release the ParentPictureControlSet eb_release_object(rateControlTasksPtr->pictureControlSetWrapperPtr); // Release Rate Control Tasks eb_release_object(rateControlTasksWrapperPtr); break; case RC_ENTROPY_CODING_ROW_FEEDBACK_RESULT: // Extract bits-per-lcu-row // Release Rate Control Tasks eb_release_object(rateControlTasksWrapperPtr); break; default: picture_control_set_ptr = (PictureControlSet_t*)rateControlTasksPtr->pictureControlSetWrapperPtr->object_ptr; sequence_control_set_ptr = (SequenceControlSet_t*)picture_control_set_ptr->sequence_control_set_wrapper_ptr->object_ptr; //encode_context_ptr = sequence_control_set_ptr->encode_context_ptr; //CHECK_REPORT_ERROR_NC( // encode_context_ptr->app_callback_ptr, // EB_ENC_RC_ERROR1); break; } } return EB_NULL; }

51.800105

262

0.645277

634fd53bfe48dd1b873c036bc4dfa35416c2d1cb

12,111

c

C

c/fp2.c

zerjioang/core

ae092583a4b333dd975438a720da7cccfcd27707

[ "Apache-2.0" ]

133

2019-09-04T14:42:38.000Z

2022-03-24T12:21:32.000Z

c/fp2.c

zerjioang/core

ae092583a4b333dd975438a720da7cccfcd27707

[ "Apache-2.0" ]

40

2019-10-02T15:01:38.000Z

2022-03-16T13:35:43.000Z

c/fp2.c

zerjioang/core

ae092583a4b333dd975438a720da7cccfcd27707

[ "Apache-2.0" ]

53

2019-09-09T18:50:20.000Z

2022-03-22T07:17:08.000Z

/* * Copyright (c) 2012-2020 MIRACL UK Ltd. * * This file is part of MIRACL Core * (see https://github.com/miracl/core). * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* CORE Fp^2 functions */ /* SU=m, m is Stack Usage (no lazy )*/ /* FP2 elements are of the form a+ib, where i is sqrt(-1) */ #include "fp2_YYY.h" /* test x==0 ? */ /* SU= 8 */ int FP2_YYY_iszilch(FP2_YYY *x) { return (FP_YYY_iszilch(&(x->a)) & FP_YYY_iszilch(&(x->b))); } /* Move b to a if d=1 */ void FP2_YYY_cmove(FP2_YYY *f, FP2_YYY *g, int d) { FP_YYY_cmove(&(f->a), &(g->a), d); FP_YYY_cmove(&(f->b), &(g->b), d); } /* test x==1 ? */ /* SU= 48 */ int FP2_YYY_isunity(FP2_YYY *x) { FP_YYY one; FP_YYY_one(&one); return (FP_YYY_equals(&(x->a), &one) & FP_YYY_iszilch(&(x->b))); } /* SU= 8 */ /* Fully reduce a and b mod Modulus */ void FP2_YYY_reduce(FP2_YYY *w) { FP_YYY_reduce(&(w->a)); FP_YYY_reduce(&(w->b)); } /* return 1 if x==y, else 0 */ /* SU= 16 */ int FP2_YYY_equals(FP2_YYY *x, FP2_YYY *y) { return (FP_YYY_equals(&(x->a), &(y->a)) & FP_YYY_equals(&(x->b), &(y->b))); } // Is x lexically larger than p-x? // return -1 for no, 0 if x=0, 1 for yes int FP2_YYY_islarger(FP2_YYY *x) { int cmp; if (FP2_YYY_iszilch(x)) return 0; cmp=FP_YYY_islarger(&(x->b)); if (cmp!=0) return cmp; return FP_YYY_islarger(&(x->a)); } void FP2_YYY_toBytes(char *b,FP2_YYY *x) { FP_YYY_toBytes(b,&(x->b)); FP_YYY_toBytes(&b[MODBYTES_XXX],&(x->a)); } void FP2_YYY_fromBytes(FP2_YYY *x,char *b) { FP_YYY_fromBytes(&(x->b),b); FP_YYY_fromBytes(&(x->a),&b[MODBYTES_XXX]); } /* Create FP2 from two FPs */ /* SU= 16 */ void FP2_YYY_from_FPs(FP2_YYY *w, FP_YYY *x, FP_YYY *y) { FP_YYY_copy(&(w->a), x); FP_YYY_copy(&(w->b), y); } /* Create FP2 from two BIGS */ /* SU= 16 */ void FP2_YYY_from_BIGs(FP2_YYY *w, BIG_XXX x, BIG_XXX y) { FP_YYY_nres(&(w->a), x); FP_YYY_nres(&(w->b), y); } /* Create FP2 from two ints */ void FP2_YYY_from_ints(FP2_YYY *w, int xa, int xb) { FP_YYY a,b; FP_YYY_from_int(&a,xa); FP_YYY_from_int(&b,xb); FP2_YYY_from_FPs(w,&a,&b); // BIG_XXX a, b; // BIG_XXX_zero(a); BIG_XXX_inc(a, xa); BIG_XXX_norm(a); // BIG_XXX_zero(b); BIG_XXX_inc(b, xb); BIG_XXX_norm(b); // FP2_YYY_from_BIGs(w, a, b); } /* Create FP2 from FP */ /* SU= 8 */ void FP2_YYY_from_FP(FP2_YYY *w, FP_YYY *x) { FP_YYY_copy(&(w->a), x); FP_YYY_zero(&(w->b)); } /* Create FP2 from BIG */ /* SU= 8 */ void FP2_YYY_from_BIG(FP2_YYY *w, BIG_XXX x) { FP_YYY_nres(&(w->a), x); FP_YYY_zero(&(w->b)); } /* FP2 copy w=x */ /* SU= 16 */ void FP2_YYY_copy(FP2_YYY *w, FP2_YYY *x) { if (w == x) return; FP_YYY_copy(&(w->a), &(x->a)); FP_YYY_copy(&(w->b), &(x->b)); } /* FP2 set w=0 */ /* SU= 8 */ void FP2_YYY_zero(FP2_YYY *w) { FP_YYY_zero(&(w->a)); FP_YYY_zero(&(w->b)); } /* FP2 set w=1 */ /* SU= 48 */ void FP2_YYY_one(FP2_YYY *w) { FP_YYY one; FP_YYY_one(&one); FP2_YYY_from_FP(w, &one); } void FP2_YYY_rcopy(FP2_YYY *w,const BIG_XXX a,const BIG_XXX b) { FP_YYY_rcopy(&(w->a),a); FP_YYY_rcopy(&(w->b),b); } int FP2_YYY_sign(FP2_YYY *w) { int p1,p2; p1=FP_YYY_sign(&(w->a)); p2=FP_YYY_sign(&(w->b)); #ifdef BIG_ENDIAN_SIGN_YYY p2 ^= (p1 ^ p2)&FP_YYY_iszilch(&(w->b)); return p2; #else p1 ^= (p1 ^ p2)&FP_YYY_iszilch(&(w->a)); return p1; #endif } /* Set w=-x */ /* SU= 88 */ void FP2_YYY_neg(FP2_YYY *w, FP2_YYY *x) { /* Just one neg! */ FP_YYY m, t; FP_YYY_add(&m, &(x->a), &(x->b)); FP_YYY_neg(&m, &m); FP_YYY_add(&t, &m, &(x->b)); FP_YYY_add(&(w->b), &m, &(x->a)); FP_YYY_copy(&(w->a), &t); } /* Set w=conj(x) */ /* SU= 16 */ void FP2_YYY_conj(FP2_YYY *w, FP2_YYY *x) { FP_YYY_copy(&(w->a), &(x->a)); FP_YYY_neg(&(w->b), &(x->b)); FP_YYY_norm(&(w->b)); } /* Set w=x+y */ /* SU= 16 */ void FP2_YYY_add(FP2_YYY *w, FP2_YYY *x, FP2_YYY *y) { FP_YYY_add(&(w->a), &(x->a), &(y->a)); FP_YYY_add(&(w->b), &(x->b), &(y->b)); } /* Set w=x-y */ /* Input y MUST be normed */ void FP2_YYY_sub(FP2_YYY *w, FP2_YYY *x, FP2_YYY *y) { FP2_YYY m; FP2_YYY_neg(&m, y); FP2_YYY_add(w, x, &m); } /* Set w=s*x, where s is FP */ /* SU= 16 */ void FP2_YYY_pmul(FP2_YYY *w, FP2_YYY *x, FP_YYY *s) { FP_YYY_mul(&(w->a), &(x->a), s); FP_YYY_mul(&(w->b), &(x->b), s); } /* SU= 16 */ /* Set w=s*x, where s is int */ void FP2_YYY_imul(FP2_YYY *w, FP2_YYY *x, int s) { FP_YYY_imul(&(w->a), &(x->a), s); FP_YYY_imul(&(w->b), &(x->b), s); } /* Set w=x^2 */ /* SU= 128 */ void FP2_YYY_sqr(FP2_YYY *w, FP2_YYY *x) { FP_YYY w1, w3, mb; FP_YYY_add(&w1, &(x->a), &(x->b)); FP_YYY_neg(&mb, &(x->b)); FP_YYY_add(&w3, &(x->a), &(x->a)); FP_YYY_norm(&w3); FP_YYY_mul(&(w->b), &w3, &(x->b)); FP_YYY_add(&(w->a), &(x->a), &mb); FP_YYY_norm(&w1); FP_YYY_norm(&(w->a)); FP_YYY_mul(&(w->a), &w1, &(w->a)); /* w->a#2 w->a=1 w1&w2=6 w1*w2=2 */ } /* Set w=x*y */ /* Inputs MUST be normed */ /* Now uses Lazy reduction */ void FP2_YYY_mul(FP2_YYY *w, FP2_YYY *x, FP2_YYY *y) { DBIG_XXX A, B, E, F, pR; BIG_XXX C, D, p; BIG_XXX_rcopy(p, Modulus_YYY); BIG_XXX_dsucopy(pR, p); // reduce excesses of a and b as required (so product < pR) if ((sign64)(x->a.XES + x->b.XES) * (y->a.XES + y->b.XES) > (sign64)FEXCESS_YYY) { #ifdef DEBUG_REDUCE printf("FP2 Product too large - reducing it\n"); #endif if (x->a.XES > 1) FP_YYY_reduce(&(x->a)); if (x->b.XES > 1) FP_YYY_reduce(&(x->b)); } BIG_XXX_mul(A, x->a.g, y->a.g); BIG_XXX_mul(B, x->b.g, y->b.g); BIG_XXX_add(C, x->a.g, x->b.g); BIG_XXX_norm(C); BIG_XXX_add(D, y->a.g, y->b.g); BIG_XXX_norm(D); BIG_XXX_mul(E, C, D); BIG_XXX_dadd(F, A, B); BIG_XXX_dsub(B, pR, B); // BIG_XXX_dadd(A, A, B); // A<pR? Not necessarily, but <2pR BIG_XXX_dsub(E, E, F); // E<pR ? Yes BIG_XXX_dnorm(A); FP_YYY_mod(w->a.g, A); w->a.XES = 3; // may drift above 2p... BIG_XXX_dnorm(E); FP_YYY_mod(w->b.g, E); w->b.XES = 2; } /* output FP2 in hex format [a,b] */ /* SU= 16 */ void FP2_YYY_output(FP2_YYY *w) { BIG_XXX bx, by; FP2_YYY_reduce(w); FP_YYY_redc(bx, &(w->a)); FP_YYY_redc(by, &(w->b)); printf("["); BIG_XXX_output(bx); printf(","); BIG_XXX_output(by); printf("]"); FP_YYY_nres(&(w->a), bx); FP_YYY_nres(&(w->b), by); } /* SU= 8 */ void FP2_YYY_rawoutput(FP2_YYY *w) { printf("["); BIG_XXX_rawoutput(w->a.g); printf(","); BIG_XXX_rawoutput(w->b.g); printf("]"); } /* Set w=1/x */ /* SU= 128 */ void FP2_YYY_inv(FP2_YYY *w, FP2_YYY *x, FP_YYY *h) { BIG_XXX m, b; FP_YYY w1, w2; FP2_YYY_norm(x); FP_YYY_sqr(&w1, &(x->a)); FP_YYY_sqr(&w2, &(x->b)); FP_YYY_add(&w1, &w1, &w2); FP_YYY_inv(&w1, &w1, h); FP_YYY_mul(&(w->a), &(x->a), &w1); FP_YYY_neg(&w1, &w1); FP_YYY_norm(&w1); FP_YYY_mul(&(w->b), &(x->b), &w1); } /* Set w=x/2 */ /* SU= 16 */ void FP2_YYY_div2(FP2_YYY *w, FP2_YYY *x) { FP_YYY_div2(&(w->a), &(x->a)); FP_YYY_div2(&(w->b), &(x->b)); } /* Set w*=(1+sqrt(-1)) */ /* where X^2-(1+sqrt(-1)) is irreducible for FP4, assumes p=3 mod 8 */ /* Input MUST be normed */ void FP2_YYY_mul_ip(FP2_YYY *w) { FP2_YYY t; int i = QNRI_YYY; FP2_YYY_copy(&t, w); FP2_YYY_times_i(w); // add 2^i.t while (i > 0) { FP2_YYY_add(&t, &t, &t); FP2_YYY_norm(&t); i--; } FP2_YYY_add(w, &t, w); #if TOWER_YYY == POSITOWER FP2_YYY_norm(w); FP2_YYY_neg(w, w); // *** #endif // Output NOT normed, so use with care } /* Set w/=(1+sqrt(-1)) */ /* SU= 88 */ void FP2_YYY_div_ip(FP2_YYY *w) { FP2_YYY z; FP2_YYY_norm(w); FP2_YYY_from_ints(&z, (1 << QNRI_YYY), 1); FP2_YYY_inv(&z, &z, NULL); FP2_YYY_mul(w, &z, w); #if TOWER_YYY == POSITOWER FP2_YYY_neg(w, w); // *** #endif } /* SU= 8 */ /* normalise a and b components of w */ void FP2_YYY_norm(FP2_YYY *w) { FP_YYY_norm(&(w->a)); FP_YYY_norm(&(w->b)); } /* Set w=a^b mod m */ /* SU= 208 */ /* void FP2_YYY_pow(FP2_YYY *r, FP2_YYY* a, BIG_XXX b) { FP2_YYY w; FP_YYY one; BIG_XXX z, zilch; int bt; BIG_XXX_norm(b); BIG_XXX_copy(z, b); FP2_YYY_copy(&w, a); FP_YYY_one(&one); BIG_XXX_zero(zilch); FP2_YYY_from_FP(r, &one); while (1) { bt = BIG_XXX_parity(z); BIG_XXX_shr(z, 1); if (bt) FP2_YYY_mul(r, r, &w); if (BIG_XXX_comp(z, zilch) == 0) break; FP2_YYY_sqr(&w, &w); } FP2_YYY_reduce(r); } */ /* test for x a QR */ int FP2_YYY_qr(FP2_YYY *x, FP_YYY *h) { /* test x^(p^2-1)/2 = 1 */ FP2_YYY c; FP2_YYY_conj(&c,x); FP2_YYY_mul(&c,&c,x); return FP_YYY_qr(&(c.a),h); } /* sqrt(a+ib) = sqrt(a+sqrt(a*a-n*b*b)/2)+ib/(2*sqrt(a+sqrt(a*a-n*b*b)/2)) */ void FP2_YYY_sqrt(FP2_YYY *w, FP2_YYY *u, FP_YYY *h) { FP_YYY w1, w2, w3, w4, hint; FP2_YYY nw; int sgn,qr; FP2_YYY_copy(w, u); if (FP2_YYY_iszilch(w)) return; FP_YYY_sqr(&w1, &(w->b)); FP_YYY_sqr(&w2, &(w->a)); FP_YYY_add(&w1, &w1, &w2); FP_YYY_norm(&w1); FP_YYY_sqrt(&w1, &w1,h); FP_YYY_add(&w2, &(w->a), &w1); FP_YYY_norm(&w2); FP_YYY_div2(&w2, &w2); FP_YYY_div2(&w1,&(w->b)); // w1=b/2 qr=FP_YYY_qr(&w2,&hint); // only exp! // tweak hint FP_YYY_neg(&w3,&hint); FP_YYY_norm(&w3); // QNR = -1 FP_YYY_neg(&w4,&w2); FP_YYY_norm(&w4); FP_YYY_cmove(&w2,&w4,1-qr); FP_YYY_cmove(&hint,&w3,1-qr); FP_YYY_sqrt(&(w->a),&w2,&hint); // a=sqrt(w2) FP_YYY_inv(&w3,&w2,&hint); // w3=1/w2 FP_YYY_mul(&w3,&w3,&(w->a)); // w3=1/sqrt(w2) FP_YYY_mul(&(w->b),&w3,&w1); // b=(b/2)*1/sqrt(w2) FP_YYY_copy(&w4,&(w->a)); FP_YYY_cmove(&(w->a),&(w->b),1-qr); FP_YYY_cmove(&(w->b),&w4,1-qr); /* FP_YYY_sqrt(&(w->a),&w2,&hint); // a=sqrt(w2) FP_YYY_inv(&w3,&w2,&hint); // w3=1/w2 FP_YYY_mul(&w3,&w3,&(w->a)); // w3=1/sqrt(w2) FP_YYY_mul(&(w->b),&w3,&w1); // b=(b/2)*1/sqrt(w2) // tweak hint FP_YYY_neg(&hint,&hint); FP_YYY_norm(&hint); // QNR = -1 FP_YYY_neg(&w2,&w2); FP_YYY_norm(&w2); FP_YYY_sqrt(&w4,&w2,&hint); // w4=sqrt(w2) FP_YYY_inv(&w3,&w2,&hint); // w3=1/w2 FP_YYY_mul(&w3,&w3,&w4); // w3=1/sqrt(w2) FP_YYY_mul(&w3,&w3,&w1); // w3=(b/2)*1/sqrt(w2) FP_YYY_cmove(&(w->a),&w3,1-qr); FP_YYY_cmove(&(w->b),&w4,1-qr); */ sgn=FP2_YYY_sign(w); FP2_YYY_neg(&nw,w); FP2_YYY_norm(&nw); FP2_YYY_cmove(w,&nw,sgn); /* FP_YYY_sub(&w3, &(w->a), &w1); FP_YYY_norm(&w3); FP_YYY_div2(&w3, &w3); FP_YYY_cmove(&w2,&w3,FP_YYY_qr(&w3,NULL)); // one or the other will be a QR FP_YYY_invsqrt(&w3,&(w->a),&w2); FP_YYY_mul(&w3,&w3,&(w->a)); FP_YYY_div2(&w2,&w3); FP_YYY_mul(&(w->b), &(w->b), &w2); sgn=FP2_YYY_sign(w); FP2_YYY_neg(&nw,w); FP2_YYY_norm(&nw); FP2_YYY_cmove(w,&nw,sgn); */ } /* New stuff for ECp4 support */ /* Input MUST be normed */ void FP2_YYY_times_i(FP2_YYY *w) { FP_YYY z; FP_YYY_copy(&z, &(w->a)); FP_YYY_neg(&(w->a), &(w->b)); FP_YYY_copy(&(w->b), &z); // Output NOT normed, so use with care } void FP2_YYY_rand(FP2_YYY *x,csprng *rng) { FP_YYY_rand(&(x->a),rng); FP_YYY_rand(&(x->b),rng); }

21.980036

84

0.547436

ebb925f10469657f2d8734eebd78c471e6b41de2

2,147

h

C

plugin/lib/HbPluginManager.h

hasboeuf/hb

d812f2ef56d7c79983701f1f673ce666b189b638

[ "MIT" ]

1

2019-03-23T22:41:16.000Z

plugin/lib/HbPluginManager.h

hasboeuf/hb

d812f2ef56d7c79983701f1f673ce666b189b638

[ "MIT" ]

null

plugin/lib/HbPluginManager.h

hasboeuf/hb

d812f2ef56d7c79983701f1f673ce666b189b638

[ "MIT" ]

null

#ifndef HBPLUGINMANAGER_H #define HBPLUGINMANAGER_H /*! \file HbPluginManager.h */ // Qt #include <QtCore/QHash> #include <QtCore/QObject> // Local #include <HbPlugin.h> #include <HbPluginInfo.h> class QPluginLoader; namespace hb { namespace plugin { class IHbPlugin; class HbPluginPlatform; /*! * HbPluginManager handles plugins. * Scan folders, seek for libraries, load plugins. */ class HB_PLUGIN_DECL HbPluginManager : public QObject { Q_OBJECT public: explicit HbPluginManager(HbPluginPlatform* platformService, QObject* parent = nullptr); /*! * Load plugin contained in folder path. * \param folder_path Folder path. */ void load(const QString& folder_path); /*! * Unload all plugins previously loaded. */ void unload(); /*! * Load a specific plugin. * \param plugin_path Path to the library to load. */ void loadPluginFromPath(const QString& plugin_path); /*! * Load a specific plugin. * \param plugin_name Plugin name. */ void loadPluginFromName(const QString& plugin_name); /*! * Unload a specific plugin. * \param plugin_name Plugin name. */ void unloadPlugin(const QString& plugin_name); /*! * Get a specific plugin. * \param plugin_name Plugin name. */ IHbPlugin* plugin(const QString& plugin_name) const; /*! * Return previously scanned plugins info. * \return Plugin info list. */ QList<HbPluginInfo*> pluginInfoList(); void onPluginStateChanged(); signals: /*! * Triggered when the state has changed. * To HbPluginManager. */ void pluginStateChanged(const HbPluginInfo& plugin_info); private: void scanFolder(const QString& folder_path); HbPluginInfo* scanPlugin(const QString& plugin_path); bool loadPlugin(const QString& plugin_name); HbPluginPlatform* mPlatformService; QString mPath; QHash<QString, HbPluginInfo*> mPluginsInfo; QHash<QString, QPluginLoader*> mPluginsLoaders; QHash<QString, IHbPlugin*> mPlugins; }; } // namespace plugin } // namespace hb #endif // HBPLUGINMANAGER_H

22.6

91

0.680019

9dc66fe438f65ee4dddb9b4d41842a49322a09b0

1,043

c

C

srcs/common/mt_isspace.c

JonathanDUFOUR/minitalk

b4b8a23b6d90f781a6bfa421e9143e5755863a9a

[ "MIT" ]

null

srcs/common/mt_isspace.c

JonathanDUFOUR/minitalk

b4b8a23b6d90f781a6bfa421e9143e5755863a9a

[ "MIT" ]

null

srcs/common/mt_isspace.c

JonathanDUFOUR/minitalk

b4b8a23b6d90f781a6bfa421e9143e5755863a9a

[ "MIT" ]

null

/* ************************************************************************** */ /* */ /* ::: :::::::: */ /* mt_isspace.c :+: :+: :+: */ /* +:+ +:+ +:+ */ /* By: jodufour <jodufour@student.42.fr> +#+ +:+ +#+ */ /* +#+#+#+#+#+ +#+ */ /* Created: 2021/06/23 00:37:31 by jodufour #+# #+# */ /* Updated: 2021/06/23 00:39:26 by jodufour ### ########.fr */ /* */ /* ************************************************************************** */ #include <stdbool.h> bool mt_isspace(char const c) { return (c == '\f' || c == '\t' || c == '\n' || c == '\r' || c == '\v' || c == ' '); }

43.458333

80

0.153404

17815065e9537a390f93b5dbc8b6e243740fb435

7,087

h

C

tensorflow/lite/micro/kernels/generic_fast/fully_connected/fully_connected_ops.h

jakob1111996/tensorflow

af583ca24e7592e09ba4fbc65e25e32bea3311cc

[ "Apache-2.0" ]

1

2021-06-16T08:45:17.000Z

tensorflow/lite/micro/kernels/generic_fast/fully_connected/fully_connected_ops.h

jakob1111996/tensorflow

af583ca24e7592e09ba4fbc65e25e32bea3311cc

[ "Apache-2.0" ]

null

tensorflow/lite/micro/kernels/generic_fast/fully_connected/fully_connected_ops.h

jakob1111996/tensorflow

af583ca24e7592e09ba4fbc65e25e32bea3311cc

[ "Apache-2.0" ]

null

/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. ==============================================================================*/ #ifndef TENSORFLOW_LITE_MICRO_KERNELS_GENERIC_FAST_FULLY_CONNECTED_FULLY_CONNECTED_OPS_H_ #define TENSORFLOW_LITE_MICRO_KERNELS_GENERIC_FAST_FULLY_CONNECTED_FULLY_CONNECTED_OPS_H_ #include "tensorflow/lite/c/builtin_op_data.h" #include "tensorflow/lite/kernels/internal/common.h" #include "tensorflow/lite/kernels/internal/cppmath.h" #include "tensorflow/lite/kernels/internal/quantization_util.h" #include "tensorflow/lite/kernels/internal/reference/fully_connected.h" #include "tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h" #include "tensorflow/lite/kernels/internal/tensor_ctypes.h" #include "tensorflow/lite/kernels/internal/types.h" #include "tensorflow/lite/kernels/kernel_util.h" #include "tensorflow/lite/micro/kernels/generic_fast/fully_connected/fully_connected_op_data.h" #include "tensorflow/lite/micro/kernels/kernel_util.h" namespace tflite { namespace { template <typename T> TfLiteStatus EvalQuantized(TfLiteContext* context, TfLiteFullyConnectedParams* params, OpData* opData, const TfLiteTensor* input, const TfLiteTensor* weights, const TfLiteTensor* bias, TfLiteTensor* output) { // Get input info const T* input_data = GetTensorData<T>(input); // Get weights info const T* weights_data = GetTensorData<T>(weights); const int32_t weights_offset = -weights->params.zero_point; RuntimeShape weights_shape = GetTensorShape(weights); TFLITE_DCHECK_GE(weights_shape.DimensionsCount(), 2); const int weights_dim_count = weights_shape.DimensionsCount(); const int accum_depth = weights_shape.Dims(weights_dim_count - 1); // Get output info T* output_data = GetTensorData<T>(output); const int32_t output_offset = output->params.zero_point; RuntimeShape output_shape = GetTensorShape(output); TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 2); const int32_t output_multiplier = opData->output_multiplier; const int output_shift = -opData->output_shift; const int32_t output_activation_min = opData->output_activation_min; const int32_t output_activation_max = opData->output_activation_max; TFLITE_DCHECK_LE(output_activation_min, output_activation_max); const int batches = output_shape.Dims(0); const int output_depth = output_shape.Dims(1); TFLITE_DCHECK_LE(output_depth, weights_shape.Dims(weights_dim_count - 2)); // Get factor pre-computed in the Prepare-phase const int32_t* sum_of_weights_factor = opData->sum_of_weights_factor; for (int b = 0; b < batches; ++b) { // Pre-compute factor for this output-batch int32_t sum_of_inputs_factor = 0; if (weights_offset != 0) { for (int d = 0; d < accum_depth; ++d) { sum_of_inputs_factor += input_data[d]; } sum_of_inputs_factor *= weights_offset; } // Calculate output-nodes using pre-computed factors KernelCore<T>::run(output_data, input_data, weights_data, sum_of_weights_factor, sum_of_inputs_factor, accum_depth, output_depth, output_offset, output_multiplier, output_shift, output_activation_min, output_activation_max); output_data += output_depth; input_data += accum_depth; } return kTfLiteOk; } TfLiteStatus EvalQuantizedInt8(TfLiteContext* context, TfLiteFullyConnectedParams* params, OpData* opData, const TfLiteTensor* input, const TfLiteTensor* weights, const TfLiteTensor* bias, TfLiteTensor* output) { return EvalQuantized<int8_t>(context, params, opData, input, weights, bias, output); } TfLiteStatus EvalQuantizedUInt8(TfLiteContext* context, TfLiteFullyConnectedParams* params, OpData* opData, const TfLiteTensor* input, const TfLiteTensor* weights, const TfLiteTensor* bias, TfLiteTensor* output) { return EvalQuantized<uint8_t>(context, params, opData, input, weights, bias, output); } TfLiteStatus EvalQuantizedUint8WithOutputInt16( TfLiteContext* context, TfLiteFullyConnectedParams* params, OpData* opData, const TfLiteTensor* input, const TfLiteTensor* weights, const TfLiteTensor* bias, TfLiteTensor* output) { tflite::FullyConnectedParams op_params; op_params.input_offset = -input->params.zero_point; op_params.weights_offset = -weights->params.zero_point; op_params.output_offset = output->params.zero_point; op_params.output_multiplier = opData->output_multiplier; // Legacy ops used mixed left and right shifts. Now all are +ve-means-left. op_params.output_shift = -opData->output_shift; op_params.quantized_activation_min = opData->output_activation_min; op_params.quantized_activation_max = opData->output_activation_max; reference_ops::FullyConnected( op_params, GetTensorShape(input), GetTensorData<uint8_t>(input), GetTensorShape(weights), GetTensorData<uint8_t>(weights), GetTensorShape(bias), GetTensorData<int32_t>(bias), GetTensorShape(output), GetTensorData<int16_t>(output)); return kTfLiteOk; } TfLiteStatus EvalFloat(TfLiteContext* context, TfLiteFullyConnectedParams* params, OpData* opData, const TfLiteTensor* input, const TfLiteTensor* weights, const TfLiteTensor* bias, TfLiteTensor* output) { float output_activation_min, output_activation_max; CalculateActivationRange(params->activation, &output_activation_min, &output_activation_max); tflite::FullyConnectedParams op_params; op_params.float_activation_min = output_activation_min; op_params.float_activation_max = output_activation_max; tflite::reference_ops::FullyConnected( op_params, GetTensorShape(input), GetTensorData<float>(input), GetTensorShape(weights), GetTensorData<float>(weights), GetTensorShape(bias), GetTensorData<float>(bias), GetTensorShape(output), GetTensorData<float>(output)); return kTfLiteOk; } } // namespace } // namespace tflite #endif // TENSORFLOW_LITE_MICRO_KERNELS_GENERIC_FAST_FULLY_CONNECTED_FULLY_CONNECTED_OPS_H_

46.933775

95

0.712572

c4b9e596719c32b67110a6e2f187b4c9ed6f0500

3,969

h

C

plat/intel/soc/common/include/socfpga_mailbox.h

TinkerBoard2-Android/external-arm-trusted-firmware

cabe6937f2c9d0a50e4631c0545bddd650233ae8

[ "BSD-3-Clause" ]

null

plat/intel/soc/common/include/socfpga_mailbox.h

TinkerBoard2-Android/external-arm-trusted-firmware

cabe6937f2c9d0a50e4631c0545bddd650233ae8

[ "BSD-3-Clause" ]

null

plat/intel/soc/common/include/socfpga_mailbox.h

TinkerBoard2-Android/external-arm-trusted-firmware

cabe6937f2c9d0a50e4631c0545bddd650233ae8

[ "BSD-3-Clause" ]

null

/* * Copyright (c) 2019, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef SOCFPGA_MBOX_H #define SOCFPGA_MBOX_H #include <lib/utils_def.h> #define MBOX_OFFSET 0xffa30000 #define MBOX_MAX_JOB_ID 0xf #define MBOX_ATF_CLIENT_ID 0x1 #define MBOX_JOB_ID 0x1 /* Mailbox interrupt flags and masks */ #define MBOX_INT_FLAG_COE 0x1 #define MBOX_INT_FLAG_RIE 0x2 #define MBOX_INT_FLAG_UAE 0x100 #define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) #define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8))) /* Mailbox response and status */ #define MBOX_RESP_BUFFER_SIZE 16 #define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff) #define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) #define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) #define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) #define MBOX_STATUS_UA_MASK (1<<8) /* Mailbox command and response */ #define MBOX_CMD_FREE_OFFSET 0x14 #define MBOX_CMD_BUFFER_SIZE 32 #define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) #define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) #define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) #define MBOX_INDIRECT (1 << 11) #define MBOX_INSUFFICIENT_BUFFER -2 #define MBOX_CIN 0x00 #define MBOX_ROUT 0x04 #define MBOX_URG 0x08 #define MBOX_INT 0x0C #define MBOX_COUT 0x20 #define MBOX_RIN 0x24 #define MBOX_STATUS 0x2C #define MBOX_CMD_BUFFER 0x40 #define MBOX_RESP_BUFFER 0xC0 #define MBOX_RESP_BUFFER_SIZE 16 #define MBOX_RESP_OK 0 #define MBOX_RESP_INVALID_CMD 1 #define MBOX_RESP_UNKNOWN_BR 2 #define MBOX_RESP_UNKNOWN 3 #define MBOX_RESP_NOT_CONFIGURED 256 /* Mailbox SDM doorbell */ #define MBOX_DOORBELL_TO_SDM 0x400 #define MBOX_DOORBELL_FROM_SDM 0x480 /* Mailbox QSPI commands */ #define MBOX_CMD_RESTART 2 #define MBOX_CMD_QSPI_OPEN 50 #define MBOX_CMD_QSPI_CLOSE 51 #define MBOX_CMD_QSPI_DIRECT 59 #define MBOX_CMD_GET_IDCODE 16 #define MBOX_CMD_QSPI_SET_CS 52 /* Mailbox CANCEL command */ #define MBOX_CMD_CANCEL 0x3 /* Mailbox REBOOT commands */ #define MBOX_CMD_REBOOT_HPS 71 /* Generic error handling */ #define MBOX_TIMEOUT -2047 #define MBOX_NO_RESPONSE -2 #define MBOX_WRONG_ID -3 /* Mailbox status */ #define RECONFIG_STATUS_STATE 0 #define RECONFIG_STATUS_PIN_STATUS 2 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3 #define PIN_STATUS_NSTATUS (U(1) << 31) #define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) #define SOFTFUNC_STATUS_INIT_DONE (1 << 1) #define SOFTFUNC_STATUS_CONF_DONE (1 << 0) #define MBOX_CFGSTAT_STATE_IDLE 0x00000000 #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 #define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 #define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 #define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 #define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 /* Mailbox reconfiguration commands */ #define MBOX_CONFIG_STATUS 4 #define MBOX_RECONFIG 6 #define MBOX_RECONFIG_DATA 8 #define MBOX_RECONFIG_STATUS 9 void mailbox_set_int(int interrupt_input); int mailbox_init(void); void mailbox_set_qspi_close(void); void mailbox_set_qspi_open(void); void mailbox_set_qspi_direct(void); int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent, uint32_t *response, int resp_len); int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent); int mailbox_read_response(int job_id, uint32_t *response, int resp_len); int mailbox_get_qspi_clock(void); void mailbox_reset_cold(void); void mailbox_clear_response(void); uint32_t intel_mailbox_get_config_status(uint32_t cmd); int intel_mailbox_is_fpga_not_ready(void); #endif /* SOCFPGA_MBOX_H */

31.5

72

0.794659

ae62aefd54134e126be15ca5b395cce7ae9bee0e

4,031

h

C

include/sig/gs_tri_intersection.h

wedusk101/sig

56c37286bbf6b37d8a4e1add8f38f4f566f3b7d0

[ "Apache-2.0" ]

null

include/sig/gs_tri_intersection.h

wedusk101/sig

56c37286bbf6b37d8a4e1add8f38f4f566f3b7d0

[ "Apache-2.0" ]

null

include/sig/gs_tri_intersection.h

wedusk101/sig

56c37286bbf6b37d8a4e1add8f38f4f566f3b7d0

[ "Apache-2.0" ]

null

/*======================================================================= Copyright (c) 2020 Marcelo Kallmann. This software is distributed under the Apache License, Version 2.0. All copies must contain the full copyright notice licence.txt located at the base folder of the distribution. =======================================================================*/ # ifndef GS_TRI_INTERSECTION_H # define GS_TRI_INTERSECTION_H /** \file gs_tri_intersection.h * triangle-triangle intersection computations */ # include <sig/gs_vec.h> //===== wrapper functions based on GsVec/GsPnt types ===== bool triangles_intersect ( const GsPnt& a, const GsPnt& b, const GsPnt& c, const GsPnt& d, const GsPnt& e, const GsPnt& f ); bool triangles_intersect ( const GsPnt& a, const GsPnt& b, const GsPnt& c, const GsPnt& d, const GsPnt& e, const GsPnt& f, GsPnt& x1, GsPnt& x2, bool* coplanar ); bool triangles_intersect ( const GsPnt2& a, const GsPnt2& b, const GsPnt2& c, const GsPnt2& d, const GsPnt2& e, const GsPnt2& f ); bool coplanar_triangles_intersect ( const GsPnt& a, const GsPnt& b, const GsPnt& c, const GsPnt& d, const GsPnt& e, const GsPnt& f, const GsVec& n1, const GsVec& n2 ); //===== original intersection tests from JGT repository (under MIT License) ===== /*! Three-dimensional Triangle-Triangle Overlap Test. Returns 1 if the triangles (including their boundary) intersect, otherwise 0. */ int gs_tri_tri_overlap_test_3d ( double p1[3], double q1[3], double r1[3], double p2[3], double q2[3], double r2[3] ); /*! Three-dimensional Triangle-Triangle Overlap Test. Additionaly computes the segment of intersection of the two triangles if it exists. Parameter coplanar returns whether the triangles are coplanar, and source and target are the endpoints of the line segment of intersection. Returns 1 if the triangles (including their boundary) intersect, otherwise 0. */ int gs_tri_tri_intersection_test_3d ( double p1[3], double q1[3], double r1[3], double p2[3], double q2[3], double r2[3], int* coplanar, double source[3], double target[3] ); /*! Three-dimensional Triangle-Triangle Overlap Test for co-planar triangles. N1 and N2 are the normal vectors of the triangles. Returns 1 if the triangles (including their boundary) intersect, otherwise 0. */ int gs_coplanar_tri_tri3d ( double p1[3], double q1[3], double r1[3], double p2[3], double q2[3], double r2[3], double N1[3], double N2[3] ); // Two dimensional Triangle-Triangle Overlap Test int gs_tri_tri_overlap_test_2d ( double p1[2], double q1[2], double r1[2], double p2[2], double q2[2], double r2[2] ); /* Triangle-Triangle Overlap Test Routines * July, 2002 * Updated December 2003 * * This file contains C implementation of algorithms for * performing two and three-dimensional triangle-triangle intersection test * The algorithms and underlying theory are described in * * "Fast and Robust Triangle-Triangle Overlap Test * Using Orientation Predicates" P. Guigue - O. Devillers * * Journal of Graphics Tools, 8(1), 2003 * * Several geometric predicates are defined. Their parameters are all * points. Each point is an array of two or three double precision * floating point numbers. The geometric predicates implemented in * this file are: * * int tri_tri_overlap_test_3d(p1,q1,r1,p2,q2,r2) * int tri_tri_overlap_test_2d(p1,q1,r1,p2,q2,r2) * * int tri_tri_intersection_test_3d(p1,q1,r1,p2,q2,r2,coplanar,source,target) * * is a version that computes the segment of intersection when * the triangles overlap (and are not coplanar) * * each function returns 1 if the triangles (including their * boundary) intersect, otherwise 0 * * Other information are available from the Web page * http://www.acm.org/jgt/papers/GuigueDevillers03/ */ //================================ End of File ================================================= # endif // GS_TRI_INTERSECTION_H

41.989583

96

0.679236

aee43341a83e613204602109ff1c0baf8db2368f

3,160

h

C

chrome/credential_provider/gaiacp/scoped_user_profile.h

sarang-apps/darshan_browser

173649bb8a7c656dc60784d19e7bb73e07c20daa

[ "BSD-3-Clause-No-Nuclear-License-2014", "BSD-3-Clause" ]

null

chrome/credential_provider/gaiacp/scoped_user_profile.h

sarang-apps/darshan_browser

173649bb8a7c656dc60784d19e7bb73e07c20daa

[ "BSD-3-Clause-No-Nuclear-License-2014", "BSD-3-Clause" ]

null

chrome/credential_provider/gaiacp/scoped_user_profile.h

sarang-apps/darshan_browser

173649bb8a7c656dc60784d19e7bb73e07c20daa

[ "BSD-3-Clause-No-Nuclear-License-2014", "BSD-3-Clause" ]

null

// Copyright 2018 The Chromium Authors. All rights reserved. // Use of this source code is governed by a BSD-style license that can be // found in the LICENSE file. #ifndef CHROME_CREDENTIAL_PROVIDER_GAIACP_SCOPED_USER_PROFILE_H_ #define CHROME_CREDENTIAL_PROVIDER_GAIACP_SCOPED_USER_PROFILE_H_ #include <string> #include "base/callback.h" #include "base/strings/string16.h" #include "base/values.h" #include "base/win/scoped_handle.h" namespace credential_provider { class FakeScopedUserProfileFactory; // Class that ensure an account's user profile and its home directory are // properly created. class ScopedUserProfile { public: static std::unique_ptr<ScopedUserProfile> Create( const base::string16& sid, const base::string16& domain, const base::string16& username, const base::string16& password); virtual ~ScopedUserProfile(); // Saves Gaia information to the account's KHCU registry hive. virtual HRESULT SaveAccountInfo(const base::Value& properties); protected: // This constructor is used by the derived fake class to bypass the // initialization code in the public constructor that will fail because the // tests are not running elevated. ScopedUserProfile(); HRESULT ExtractAssociationInformation( const base::Value& properties, base::string16* sid, base::string16* id, base::string16* email, base::string16* token_handle, base::string16* last_online_login_millis); HRESULT RegisterAssociation(const base::string16& sid, const base::string16& id, const base::string16& email, const base::string16& token_handle, const base::string16& last_online_login_millis); private: friend class FakeScopedUserProfileFactory; bool IsValid(); // Waits for the specified user's profile to be created. The credprov // does not have backup/restore privileges, so cannot call LoadUserProfile() // directly. winlogon.exe does have the privileges, but somehow they do // not get transferred. // // Another option is CreateProcessWithLogonW(...LOGON_WITH_PROFILE...), // however a process running as SYSTEM is not permitted to call this. The // workaround used in this class is to simply wait for the user's profile // directory and registry hive to be loaded by the system itself. This // code must be run after the credprov tells winlogon to log the user in. ScopedUserProfile(const base::string16& sid, const base::string16& domain, const base::string16& username, const base::string16& password); bool WaitForProfileCreation(const base::string16& sid); base::win::ScopedHandle token_; // Gets storage of the function pointer used to create instances of this // class for tests. using CreatorFunc = decltype(Create); using CreatorCallback = base::RepeatingCallback<CreatorFunc>; static CreatorCallback* GetCreatorFunctionStorage(); }; } // namespace credential_provider #endif // CHROME_CREDENTIAL_PROVIDER_GAIACP_SCOPED_USER_PROFILE_H_

36.321839

78

0.716139

8351ff576eaf0b2afd34516ec10bfe5d44bef724

981

h

C

ios/Pods/Headers/Public/libksygpulive/KSYBeautifyProFilter.h

matinzd/react-native-rtmpview

2e8e21dd06e7baa7665d19cb843d1f163f0c9e11

[ "MIT" ]

100

2018-04-09T22:35:07.000Z

2022-02-25T02:04:11.000Z

ios/Pods/Headers/Public/libksygpulive/KSYBeautifyProFilter.h

matinzd/react-native-rtmpview

2e8e21dd06e7baa7665d19cb843d1f163f0c9e11

[ "MIT" ]

20

2018-07-06T16:05:07.000Z

2021-05-12T00:06:18.000Z

ios/Pods/Headers/Public/libksygpulive/KSYBeautifyProFilter.h

matinzd/react-native-rtmpview

2e8e21dd06e7baa7665d19cb843d1f163f0c9e11

[ "MIT" ]

17

2018-05-05T16:52:02.000Z

2021-12-16T09:26:04.000Z

// // KSYBeautifyProFilter.h // GPUImage // // Created by gene on 16/12/8. // Copyright © 2016年 Brad Larson. All rights reserved. // #import <GPUImage/GPUImage.h> @interface KSYBeautifyProFilter : GPUImageFilterGroup /// init - (id)init; /** @abstract 初始化并指定 1~4 的index来创建对应美颜滤镜 @param idx 效果的索引 (非法值无效) */ - (id)initWithIdx:(NSInteger)idx; /// show version of this filter +(void) showVersion; /// grindRatio ranges from 0.0 to 1.0, with 0.5 as the normal level @property(readwrite,nonatomic) CGFloat grindRatio; /// whitenRatio ranges from 0.0 to 1.0, with 0.3 as the normal level @property(readwrite,nonatomic) CGFloat whitenRatio; #pragma mark /// ruddyRatio ranges from -1.0 to 1.0, with -0.3 as the normal level @property(readwrite,nonatomic) CGFloat ruddyRatio; /** 几组推荐的效果参数美白：whitenRatio=1.0,ruddyRatio=0.0; 粉嫩：whitenRatio=0.3,ruddyRatio=-0.3；红润：whitenRatio=0.3,ruddyRatio=0.4；其中init 效果参数默认是粉嫩，磨皮参数默认是0.5； */ @end

23.357143

69

0.698267

0314161398e87661261610ff4fe061df0e7b5d2b

4,950

h

C

include/pbcopper/parallel/FireAndForget.h

PacificBiosciences/pbcopper

ba98ddd79371c2218ca5110d07d5f881c995ff93

[ "BSD-3-Clause-Clear" ]

5

2018-01-15T13:40:30.000Z

2021-01-19T18:28:30.000Z

include/pbcopper/parallel/FireAndForget.h

PacificBiosciences/pbcopper

ba98ddd79371c2218ca5110d07d5f881c995ff93

[ "BSD-3-Clause-Clear" ]

4

2016-09-20T20:25:14.000Z

2020-12-22T19:21:49.000Z

include/pbcopper/parallel/FireAndForget.h

PacificBiosciences/pbcopper

ba98ddd79371c2218ca5110d07d5f881c995ff93

[ "BSD-3-Clause-Clear" ]

7

2017-05-15T08:47:02.000Z

2021-04-28T18:38:09.000Z

#ifndef PBCOPPER_PARALLEL_FIREANDFORGET_H #define PBCOPPER_PARALLEL_FIREANDFORGET_H #include <pbcopper/PbcopperConfig.h> #include <atomic> #include <condition_variable> #include <cstddef> #include <cstdint> #include <exception> #include <functional> #include <future> #include <mutex> #include <queue> #include <stdexcept> #include <boost/optional.hpp> namespace PacBio { namespace Parallel { class FireAndForget { private: typedef boost::optional<std::packaged_task<void()>> TTask; public: FireAndForget(const size_t size, const size_t mul = 2) : exc{nullptr} , numThreads{size} , sz{size * mul} , abort{false} , thrown{false} , acceptingJobs{true} { for (size_t i = 0; i < size; ++i) { threads.emplace_back(std::thread([this]() { TTask task; do { try { task = PopTask(); // Check if queue should be aborted and // if there is a task if (!abort && task) { // Execute task (*task)(); // Check for the return value / exception task->get_future().get(); }; } catch (...) { std::lock_guard<std::mutex> g(m); // If there is an exception, signal to abort queue abort = true; // And store exception exc = std::current_exception(); popped.notify_one(); } } while (!abort && task); // Stop if there are no tasks or abort has been signaled })); } } ~FireAndForget() noexcept(false) { if (exc && !thrown) { std::rethrow_exception(exc); } } template <typename F, typename... Args> void ProduceWith(F&& f, Args&&... args) { if (!acceptingJobs) { throw std::runtime_error( "FireAndForget error: Cannot dispatch jobs to finalized thread pool!"); } std::packaged_task<void()> task{std::bind(std::forward<F>(f), std::forward<Args>(args)...)}; { std::unique_lock<std::mutex> lk(m); if (exc) { thrown = true; std::rethrow_exception(exc); } popped.wait(lk, [&task, this]() { if (exc) { std::rethrow_exception(exc); } if (head.size() < sz) { head.emplace(std::move(task)); return true; } return false; }); } pushed.notify_one(); } void Finalize() { acceptingJobs = false; { std::lock_guard<std::mutex> g(m); // Push boost::none to signal that there are no further tasks head.emplace(boost::none); } // Let all workers know that they should look that there is no further work pushed.notify_all(); // Wait for all threads to join and do not continue before all tasks // have been finished. for (auto& thread : threads) { thread.join(); } // Is there a final exception, throw if so.. if (exc) { thrown = true; std::rethrow_exception(exc); } } size_t NumThreads() const { return numThreads; } private: TTask PopTask() { TTask task(boost::none); { std::unique_lock<std::mutex> lk(m); pushed.wait(lk, [&task, this]() { if (head.empty()) { return false; } if ((task = std::move(head.front()))) { head.pop(); } return true; }); } popped.notify_one(); return task; } std::vector<std::thread> threads; std::queue<TTask> head; std::condition_variable popped; std::condition_variable pushed; std::exception_ptr exc; std::mutex m; size_t numThreads; size_t sz; std::atomic_bool abort; std::atomic_bool thrown; std::atomic_bool acceptingJobs; }; /// /// \brief Use an existing FireAndForget to dispatch [0, numEntries) callbacks. /// Returns after all dispatched jobs finished. /// /// \param faf reference to FaF, nullptr allowed /// \param numEntries number of submissions /// \param callback function to be dispatched to FaF /// void Dispatch(Parallel::FireAndForget* faf, int32_t numEntries, const std::function<void(int32_t)>& callback); } // namespace Parallel } // namespace PacBio #endif // PBCOPPER_PARALLEL_FIREANDFORGET_H

27.348066

100

0.501818

eaaafdbb21efef24d113d784f918c317aaa53476

934

c

C

kernel/nvidia/drivers/video/tegra/host/t124/cg_regs.c

rubedos/l4t_R32.5.1_viper

6aed0062084d9031546f946e63fc74303555e0a6

[ "MIT" ]

null

kernel/nvidia/drivers/video/tegra/host/t124/cg_regs.c

rubedos/l4t_R32.5.1_viper

6aed0062084d9031546f946e63fc74303555e0a6

[ "MIT" ]

null

kernel/nvidia/drivers/video/tegra/host/t124/cg_regs.c

rubedos/l4t_R32.5.1_viper

6aed0062084d9031546f946e63fc74303555e0a6

[ "MIT" ]

null

/* * Copyright (c) 2014, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. * * This file is autogenerated. Do not edit. */ static struct nvhost_gating_register __attribute__((__unused__)) t12x_vic_gating_registers[] = { /* NV_PVIC_MISC_PRI_VIC_CG */ { .addr = 0x000016d0, .prod = 0x00040044, .disable = 0x000f003f }, {} };

35.923077

79

0.735546

88d8f423cd0e5b4e610669c404b54cbf8cc41a6e

5,360

c

C

ext/isomorfeus_ferret_ext/test_file_deleter.c

isomorfeus/isomorfeus-ferret

adda871f6bc5bcad3cb1bff63512258a401231f0

[ "ICU", "BSD-2-Clause", "Apache-2.0" ]

null

ext/isomorfeus_ferret_ext/test_file_deleter.c

isomorfeus/isomorfeus-ferret

adda871f6bc5bcad3cb1bff63512258a401231f0

[ "ICU", "BSD-2-Clause", "Apache-2.0" ]

null

ext/isomorfeus_ferret_ext/test_file_deleter.c

isomorfeus/isomorfeus-ferret

adda871f6bc5bcad3cb1bff63512258a401231f0

[ "ICU", "BSD-2-Clause", "Apache-2.0" ]

null

#include "frt_index.h" #include "testhelper.h" #include <limits.h> #include "test.h" static const char *content_f = "content"; static const char *id_f = "id"; const FrtConfig lucene_config = { 0x100000, /* chunk size is 1Mb */ 0x1000000, /* Max memory used for buffer is 16 Mb */ FRT_INDEX_INTERVAL, /* index interval */ FRT_SKIP_INTERVAL, /* skip interval */ 10, /* default merge factor */ 10, /* max_buffered_docs */ INT_MAX, /* max_merged_docs */ 10000, /* maximum field length (number of terms) */ true /* use compound file by default */ }; static FrtFieldInfos *prep_fis(void) { return frt_fis_new(FRT_STORE_NO, FRT_COMPRESSION_NONE, FRT_INDEX_YES, FRT_TERM_VECTOR_NO); } static void create_index(FrtStore *store) { FrtFieldInfos *fis = prep_fis(); frt_index_create(store, fis); frt_fis_deref(fis); } static FrtIndexWriter *create_iw_lucene(FrtStore *store) { create_index(store); return frt_iw_open(NULL, store, frt_whitespace_analyzer_new(false), &lucene_config); } static void add_doc(FrtIndexWriter *iw, int id) { FrtDocument *doc = frt_doc_new(); rb_encoding *enc = rb_enc_find("ASCII-8BIT"); frt_doc_add_field(doc, frt_df_add_data(frt_df_new(rb_intern(content_f)), frt_estrdup("aaa"), enc))->destroy_data = true; frt_doc_add_field(doc, frt_df_add_data(frt_df_new(rb_intern(id_f)), frt_strfmt("%d", id), enc))->destroy_data = true; frt_iw_add_doc(iw, doc); frt_doc_destroy(doc); } static void add_docs(FrtIndexWriter *iw, int count) { int i; for (i = 0; i < count; i++) { add_doc(iw, i); } } static void copy_file(FrtStore *store, const char *src, const char *dest) { FrtInStream *is = store->open_input(store, src); FrtOutStream *os = store->new_output(store, dest); frt_is2os_copy_bytes(is, os, frt_is_length(is)); frt_is_close(is); frt_os_close(os); } /* * Verify we can read the pre-XXX file format, do searches * against it, and add documents to it. */ static void test_delete_leftover_files(TestCase *tc, void *data) { FrtStore *store = (FrtStore *)data; FrtIndexWriter *iw = create_iw_lucene(store); FrtIndexReader *ir; char *store_before, *store_after; add_docs(iw, 35); frt_iw_close(iw); /* Delete one doc so we get a .del file: */ ir = frt_ir_open(NULL, store); frt_ir_delete_doc(ir, 7); Aiequal(1, ir->max_doc(ir) - ir->num_docs(ir)); /* Set one norm so we get a .s0 file: */ frt_ir_set_norm(ir, 21, rb_intern(content_f), 12); frt_ir_close(ir); store_before = frt_store_to_s(store); /* Create a bogus separate norms file for a * segment/field that actually has a separate norms file * already: */ copy_file(store, "_2_1.s0", "_2_2.s0"); /* Create a bogus separate norms file for a * segment/field that actually has a separate norms file * already, using the "not compound file" extension: */ copy_file(store, "_2_1.s0", "_2_2.f0"); /* Create a bogus separate norms file for a * segment/field that does not have a separate norms * file already: */ copy_file(store, "_2_1.s0", "_1_1.s0"); /* Create a bogus separate norms file for a * segment/field that does not have a separate norms * file already using the "not compound file" extension: */ copy_file(store, "_2_1.s0", "_1_1.f0"); /* Create a bogus separate del file for a * segment that already has a separate del file: */ copy_file(store, "_0_0.del", "_0_1.del"); /* Create a bogus separate del file for a * segment that does not yet have a separate del file: */ copy_file(store, "_0_0.del", "_1_1.del"); /* Create a bogus separate del file for a * non-existent segment: */ copy_file(store, "_0_0.del", "_188_1.del"); /* Create a bogus segment file: */ copy_file(store, "_0.cfs", "_188.cfs"); /* Create a bogus frq file when the CFS already exists: */ copy_file(store, "_0.cfs", "_0.frq"); /* Create a bogus frq file when the CFS already exists: */ copy_file(store, "_0.cfs", "_0.frq"); copy_file(store, "_0.cfs", "_0.prx"); copy_file(store, "_0.cfs", "_0.fdx"); copy_file(store, "_0.cfs", "_0.fdt"); copy_file(store, "_0.cfs", "_0.tfx"); copy_file(store, "_0.cfs", "_0.tix"); copy_file(store, "_0.cfs", "_0.tis"); /* Create some old segments file: */ copy_file(store, "segments_5", "segments"); copy_file(store, "segments_5", "segments_2"); /* Open & close a writer: should delete the above files and nothing more: */ frt_iw_close(frt_iw_open(NULL, store, frt_whitespace_analyzer_new(false), &lucene_config)); store_after = frt_store_to_s(store); Asequal(store_before, store_after); free(store_before); free(store_after); } /*************************************************************************** * * IndexFileDeleterSuite * ***************************************************************************/ TestSuite *ts_file_deleter(TestSuite *suite) { FrtStore *store = frt_open_ram_store(NULL); suite = ADD_SUITE(suite); tst_run_test(suite, test_delete_leftover_files, store); frt_store_close(store); return suite; }

31.715976

95

0.633582

bb1a8d24f128acd4f8b049807ed96c320fed8f38

8,205

h

C

Source/Runtime/Public/Containers/LinkedList.h

ValtoForks/BlueshiftEngine

a6684aa3bf9b4bd22d5cc4d4b6647fea6b074fee

[ "Apache-2.0" ]

410

2017-03-03T08:56:54.000Z

2022-03-29T07:18:46.000Z

Source/Runtime/Public/Containers/LinkedList.h

kbb-uran/BlueshiftEngine

beb690093ca643c38437831c93581e29686ff508

[ "Apache-2.0" ]

31

2017-03-05T11:37:44.000Z

2021-09-15T21:28:34.000Z

Source/Runtime/Public/Containers/LinkedList.h

kbb-uran/BlueshiftEngine

beb690093ca643c38437831c93581e29686ff508

[ "Apache-2.0" ]

48

2017-03-18T05:28:21.000Z

2022-03-05T12:27:17.000Z

// Copyright(c) 2017 POLYGONTEK // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http ://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. #pragma once BE_NAMESPACE_BEGIN #pragma once class LinkNode { public: LinkNode *m_pNext; LinkNode *m_pPrev; void PushFront(LinkNode *pParent) { Append(pParent); } void PushBack(LinkNode *pParent) { Insert(pParent); } void MoveTo(LinkNode *pTo) { if (m_pNext != this) { pTo->m_pPrev->m_pNext = m_pNext; m_pNext->m_pPrev = pTo->m_pPrev; pTo->m_pPrev = m_pPrev; m_pPrev->m_pNext = pTo; m_pPrev = m_pNext = this; } } bool Empty() { return (this == m_pNext); } void Initialize() { m_pPrev = m_pNext = this; } void Append(LinkNode *pLink) { m_pNext = pLink->m_pNext; m_pPrev = pLink; pLink->m_pNext->m_pPrev = this; pLink->m_pNext = this; } void Insert(LinkNode *pLink) { m_pPrev = pLink->m_pPrev; m_pNext = pLink; pLink->m_pPrev->m_pNext = this; pLink->m_pPrev = this; } void Remove() { m_pNext->m_pPrev = m_pPrev; m_pPrev->m_pNext = m_pNext; } }; //#define LINK_POINTER( link, type, member) (( type *)(( char *)link - ( size_t)&(( type *)0)->member)) #define LinkedList(type, member) linked_list<type, offsetof(type, member)> template <typename TYPE, size_t offset = 0> class _linked_list { public: typedef TYPE &reference; typedef TYPE *pointer; typedef TYPE value_type; protected: LinkNode m_list; public: class iterator : public std::iterator<std::bidirectional_iterator_tag, TYPE> { // iterator for mutable list public: iterator() {} iterator(reference value) { m_ptr = &value; } explicit iterator(LinkNode *pLink) { m_ptr = (pointer)((char *)pLink - offset); } LinkNode* ToLinkPtr() const { return (LinkNode *)((char *)m_ptr + offset); } reference operator*() { // return designated value return *m_ptr; } //pointer operator->( ) const //{ // return pointer to class object // return ( &**this); //} iterator& operator++() { // preincrement m_ptr = iterator(ToLinkPtr()->m_pNext).m_ptr; return (*this); } iterator operator++(int) { // postincrement iterator _Tmp = *this; ++*this; return (_Tmp); } iterator& operator--() { // predecrement m_ptr = iterator(ToLinkPtr()->m_pPrev).m_ptr; return (*this); } iterator operator--(int) { // postdecrement iterator _Tmp = *this; --*this; return (_Tmp); } bool operator==(const iterator& _Right) const { // test for iterator equality return (m_ptr == _Right.m_ptr); } bool operator!=(const iterator& _Right) const { // test for iterator inequality return (!(*this == _Right)); } protected: pointer m_ptr; }; class reverse_iterator : public std::iterator<std::bidirectional_iterator_tag, TYPE> { // iterator for mutable list public: reverse_iterator() {} reverse_iterator(reference value) { m_ptr = value; } explicit reverse_iterator(LinkNode *pLink) { m_ptr = (pointer)((char *)pLink - offset); } LinkNode* ToLinkPtr() const { return (LinkNode *)((char *)m_ptr + offset); } reference operator*() { // return designated value return *m_ptr; } //pointer operator->( ) const //{ // return pointer to class object // return ( &**this); //} reverse_iterator& operator++() { // preincrement m_ptr = reverse_iterator(ToLinkPtr()->m_pPrev).m_ptr; return (*this); } reverse_iterator operator++(int) { // postincrement reverse_iterator _Tmp = *this; ++*this; return (_Tmp); } reverse_iterator& operator--() { // predecrement m_ptr = reverse_iterator(ToLinkPtr()->m_pNext).m_ptr; return (*this); } reverse_iterator operator--(int) { // postdecrement reverse_iterator _Tmp = *this; --*this; return (_Tmp); } bool operator==(const reverse_iterator& _Right) const { // test for iterator equality return (m_ptr == _Right.m_ptr); } bool operator!=(const reverse_iterator& _Right) const { // test for iterator inequality return (!(*this == _Right)); } protected: pointer m_ptr; }; _linked_list() { m_list.Initialize(); } void push_front(reference element) { iterator(element).ToLinkPtr()->Append(&m_list); } void push_back(reference element) { iterator(element).ToLinkPtr()->Insert(&m_list); } reference front() { return *iterator(m_list.m_pNext); } reference back() { return *iterator(m_list.m_pPrev); } void pop_front() { m_list.m_pNext->Remove(); } void pop_back() { m_list.m_pPrev->Remove(); } bool empty() { return m_list.Empty() != 0; } iterator begin() { return iterator(m_list.m_pNext); } iterator end() { return iterator(&m_list); } reverse_iterator rbegin() { // return iterator for beginning of reversed mutable sequence return (reverse_iterator(m_list.m_pPrev)); } reverse_iterator rend() { // return iterator for end of reversed mutable sequence return reverse_iterator(&m_list); } iterator insert(iterator where, reference element) { iterator(element).ToLinkPtr()->Insert(where.ToLinkPtr()); return iterator(element); } static iterator erase(iterator where) { (where++).ToLinkPtr()->Remove(); return where; } static iterator iterator_to(reference element) { return iterator(element); } void clear() { m_list.Initialize(); } }; template <typename TYPE, size_t offset = 0> class linked_list : public _linked_list<TYPE, offset> { protected: long m_nSize; public: typedef _linked_list<TYPE, offset> Super; typedef typename Super::iterator iterator; typedef typename Super::reference reference; linked_list() { m_nSize = 0; } void push_front(reference element) { Super::push_front(element); m_nSize++; } void push_back(reference element) { Super::push_back(element); m_nSize++; } void pop_front() { Super::pop_front(); m_nSize--; } void pop_back() { Super::pop_back(); m_nSize--; } bool empty() { return m_nSize == 0; } iterator insert(iterator where, reference element) { m_nSize++; return Super::insert(where, element); } iterator erase(iterator where) { m_nSize--; return Super::erase(where); } void clear() { m_nSize = 0; Super::clear(); } size_t size() { return m_nSize; } }; BE_NAMESPACE_END

21.311688

103

0.546984

b73bb41495680fb646125ccd0d8515f71e0ee918

9,893

h

C

Core/Inc/main.h

longhuarst/clhbot_v1_horizon

c4a47e6b8ff7dc3291bf04766782bffafc4157fc

[ "MIT" ]

null

Core/Inc/main.h

longhuarst/clhbot_v1_horizon

c4a47e6b8ff7dc3291bf04766782bffafc4157fc

[ "MIT" ]

null

Core/Inc/main.h

longhuarst/clhbot_v1_horizon

c4a47e6b8ff7dc3291bf04766782bffafc4157fc

[ "MIT" ]

null

/** ****************************************************************************** * @file : main.h * @brief : Header for main.c file. * This file contains the common defines of the application. ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * * COPYRIGHT(c) 2018 STMicroelectronics * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __MAIN_H__ #define __MAIN_H__ /* Includes ------------------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Private define ------------------------------------------------------------*/ #define STEP_CH3_M1_Pin GPIO_PIN_2 #define STEP_CH3_M1_GPIO_Port GPIOE #define STEP_CH3_M2_Pin GPIO_PIN_3 #define STEP_CH3_M2_GPIO_Port GPIOE #define STEP_CH3_M3_Pin GPIO_PIN_4 #define STEP_CH3_M3_GPIO_Port GPIOE #define STEP_CH3_EN_Pin GPIO_PIN_5 #define STEP_CH3_EN_GPIO_Port GPIOE #define STEP_CH3_RESET_Pin GPIO_PIN_6 #define STEP_CH3_RESET_GPIO_Port GPIOE #define STEP_CH3_DIR_Pin GPIO_PIN_13 #define STEP_CH3_DIR_GPIO_Port GPIOC #define STEP_CH2_ST_Pin GPIO_PIN_0 #define STEP_CH2_ST_GPIO_Port GPIOF #define STEP_CH2_M1_Pin GPIO_PIN_1 #define STEP_CH2_M1_GPIO_Port GPIOF #define STEP_CH2_M2_Pin GPIO_PIN_2 #define STEP_CH2_M2_GPIO_Port GPIOF #define STEP_CH2_M3_Pin GPIO_PIN_3 #define STEP_CH2_M3_GPIO_Port GPIOF #define STEP_CH2_EN_Pin GPIO_PIN_4 #define STEP_CH2_EN_GPIO_Port GPIOF #define STEP_CH2_RESET_Pin GPIO_PIN_5 #define STEP_CH2_RESET_GPIO_Port GPIOF #define STEP_CH2_DIR_Pin GPIO_PIN_6 #define STEP_CH2_DIR_GPIO_Port GPIOF #define STEP_CH1_ST_Pin GPIO_PIN_7 #define STEP_CH1_ST_GPIO_Port GPIOF #define STEP_CH1_M1_Pin GPIO_PIN_8 #define STEP_CH1_M1_GPIO_Port GPIOF #define STEP_CH1_M2_Pin GPIO_PIN_1 #define STEP_CH1_M2_GPIO_Port GPIOC #define STEP_CH1_M3_Pin GPIO_PIN_2 #define STEP_CH1_M3_GPIO_Port GPIOC #define STEP_CH1_EN_Pin GPIO_PIN_3 #define STEP_CH1_EN_GPIO_Port GPIOC #define STEP_CH1_RESET_Pin GPIO_PIN_0 #define STEP_CH1_RESET_GPIO_Port GPIOA #define STEP_CH1_DIR_Pin GPIO_PIN_1 #define STEP_CH1_DIR_GPIO_Port GPIOA #define INPUT_CH0_Pin GPIO_PIN_4 #define INPUT_CH0_GPIO_Port GPIOA #define INPUT_CH1_Pin GPIO_PIN_5 #define INPUT_CH1_GPIO_Port GPIOA #define INPUT_CH2_Pin GPIO_PIN_6 #define INPUT_CH2_GPIO_Port GPIOA #define INPUT_CH3_Pin GPIO_PIN_7 #define INPUT_CH3_GPIO_Port GPIOA #define INPUT_CH4_Pin GPIO_PIN_4 #define INPUT_CH4_GPIO_Port GPIOC #define INPUT_CH5_Pin GPIO_PIN_5 #define INPUT_CH5_GPIO_Port GPIOC #define INPUT_CH6_Pin GPIO_PIN_0 #define INPUT_CH6_GPIO_Port GPIOB #define INPUT_CH7_Pin GPIO_PIN_1 #define INPUT_CH7_GPIO_Port GPIOB #define SPPCA_RST_Pin GPIO_PIN_12 #define SPPCA_RST_GPIO_Port GPIOF #define SPPCA_INT_Pin GPIO_PIN_13 #define SPPCA_INT_GPIO_Port GPIOF #define OLED_CS2_Pin GPIO_PIN_14 #define OLED_CS2_GPIO_Port GPIOF #define OLED_FCO_Pin GPIO_PIN_15 #define OLED_FCO_GPIO_Port GPIOF #define OLED_CS1_Pin GPIO_PIN_0 #define OLED_CS1_GPIO_Port GPIOG #define OLED_DC_Pin GPIO_PIN_1 #define OLED_DC_GPIO_Port GPIOG #define OUTPUT_CH0_Pin GPIO_PIN_7 #define OUTPUT_CH0_GPIO_Port GPIOE #define OUTPUT_CH1_Pin GPIO_PIN_8 #define OUTPUT_CH1_GPIO_Port GPIOE #define PWM_OUT_CH8_Pin GPIO_PIN_9 #define PWM_OUT_CH8_GPIO_Port GPIOE #define OLED_RES_Pin GPIO_PIN_10 #define OLED_RES_GPIO_Port GPIOE #define PWM_OUT_CH7_Pin GPIO_PIN_11 #define PWM_OUT_CH7_GPIO_Port GPIOE #define OLED_SDA_Pin GPIO_PIN_12 #define OLED_SDA_GPIO_Port GPIOE #define PWM_OUT_CH6_Pin GPIO_PIN_13 #define PWM_OUT_CH6_GPIO_Port GPIOE #define PWM_OUT_CH5_Pin GPIO_PIN_14 #define PWM_OUT_CH5_GPIO_Port GPIOE #define OLED_SCL_Pin GPIO_PIN_15 #define OLED_SCL_GPIO_Port GPIOE #define OUTPUT_CH2_Pin GPIO_PIN_10 #define OUTPUT_CH2_GPIO_Port GPIOB #define OUTPUT_CH3_Pin GPIO_PIN_11 #define OUTPUT_CH3_GPIO_Port GPIOB #define OUTPUT_CH4_Pin GPIO_PIN_12 #define OUTPUT_CH4_GPIO_Port GPIOB #define OUTPUT_CH5_Pin GPIO_PIN_13 #define OUTPUT_CH5_GPIO_Port GPIOB #define OUTPUT_CH6_Pin GPIO_PIN_14 #define OUTPUT_CH6_GPIO_Port GPIOB #define OUTPUT_CH7_Pin GPIO_PIN_15 #define OUTPUT_CH7_GPIO_Port GPIOB #define LED0_Pin GPIO_PIN_10 #define LED0_GPIO_Port GPIOD #define LED1_Pin GPIO_PIN_11 #define LED1_GPIO_Port GPIOD #define LED2_Pin GPIO_PIN_12 #define LED2_GPIO_Port GPIOD #define RS485_CH1_SHDN_Pin GPIO_PIN_14 #define RS485_CH1_SHDN_GPIO_Port GPIOD #define Limit_SW_CH1_Pin GPIO_PIN_15 #define Limit_SW_CH1_GPIO_Port GPIOD #define Limit_SW_CH2_Pin GPIO_PIN_2 #define Limit_SW_CH2_GPIO_Port GPIOG #define Limit_SW_CH3_Pin GPIO_PIN_3 #define Limit_SW_CH3_GPIO_Port GPIOG #define Limit_SW_CH4_Pin GPIO_PIN_4 #define Limit_SW_CH4_GPIO_Port GPIOG #define Proximity_SW_CH1_Pin GPIO_PIN_5 #define Proximity_SW_CH1_GPIO_Port GPIOG #define Proximity_SW_CH2_Pin GPIO_PIN_6 #define Proximity_SW_CH2_GPIO_Port GPIOG #define Proximity_SW_CH3_Pin GPIO_PIN_7 #define Proximity_SW_CH3_GPIO_Port GPIOG #define Proximity_SW_CH4_Pin GPIO_PIN_8 #define Proximity_SW_CH4_GPIO_Port GPIOG #define PWM_OUT_CH4_Pin GPIO_PIN_6 #define PWM_OUT_CH4_GPIO_Port GPIOC #define PWM_OUT_CH3_Pin GPIO_PIN_7 #define PWM_OUT_CH3_GPIO_Port GPIOC #define PWM_OUT_CH2_Pin GPIO_PIN_8 #define PWM_OUT_CH2_GPIO_Port GPIOC #define PWM_OUT_CH1_Pin GPIO_PIN_9 #define PWM_OUT_CH1_GPIO_Port GPIOC #define RS485_CH1_RE_Pin GPIO_PIN_8 #define RS485_CH1_RE_GPIO_Port GPIOA #define STEP_CH6_CLK_Pin GPIO_PIN_15 #define STEP_CH6_CLK_GPIO_Port GPIOA #define STEP_CH6_ST_Pin GPIO_PIN_10 #define STEP_CH6_ST_GPIO_Port GPIOC #define STEP_CH6_M1_Pin GPIO_PIN_11 #define STEP_CH6_M1_GPIO_Port GPIOC #define STEP_CH6_M2_Pin GPIO_PIN_12 #define STEP_CH6_M2_GPIO_Port GPIOC #define STEP_CH6_M3_Pin GPIO_PIN_0 #define STEP_CH6_M3_GPIO_Port GPIOD #define STEP_CH6_EN_Pin GPIO_PIN_1 #define STEP_CH6_EN_GPIO_Port GPIOD #define STEP_CH6_RESET_Pin GPIO_PIN_2 #define STEP_CH6_RESET_GPIO_Port GPIOD #define STEP_CH6_DIR_Pin GPIO_PIN_3 #define STEP_CH6_DIR_GPIO_Port GPIOD #define STEP_CH5_ST_Pin GPIO_PIN_4 #define STEP_CH5_ST_GPIO_Port GPIOD #define STEP_CH5_M1_Pin GPIO_PIN_5 #define STEP_CH5_M1_GPIO_Port GPIOD #define STEP_CH5_M2_Pin GPIO_PIN_6 #define STEP_CH5_M2_GPIO_Port GPIOD #define STEP_CH5_M3_Pin GPIO_PIN_7 #define STEP_CH5_M3_GPIO_Port GPIOD #define STEP_CH5_EN_Pin GPIO_PIN_9 #define STEP_CH5_EN_GPIO_Port GPIOG #define STEP_CH5_RESET_Pin GPIO_PIN_10 #define STEP_CH5_RESET_GPIO_Port GPIOG #define STEP_CH5_DIR_Pin GPIO_PIN_11 #define STEP_CH5_DIR_GPIO_Port GPIOG #define STEP_CH4_ST_Pin GPIO_PIN_12 #define STEP_CH4_ST_GPIO_Port GPIOG #define STEP_CH4_M1_Pin GPIO_PIN_13 #define STEP_CH4_M1_GPIO_Port GPIOG #define STEP_CH4_M2_Pin GPIO_PIN_14 #define STEP_CH4_M2_GPIO_Port GPIOG #define STEP_CH4_M3_Pin GPIO_PIN_15 #define STEP_CH4_M3_GPIO_Port GPIOG #define STEP_CH1_CLK_Pin GPIO_PIN_3 #define STEP_CH1_CLK_GPIO_Port GPIOB #define STEP_CH4_EN_Pin GPIO_PIN_4 #define STEP_CH4_EN_GPIO_Port GPIOB #define STEP_CH4_RESET_Pin GPIO_PIN_5 #define STEP_CH4_RESET_GPIO_Port GPIOB #define STEP_CH5_CLK_Pin GPIO_PIN_6 #define STEP_CH5_CLK_GPIO_Port GPIOB #define STEP_CH4_CLK_Pin GPIO_PIN_7 #define STEP_CH4_CLK_GPIO_Port GPIOB #define STEP_CH2_CLK_Pin GPIO_PIN_8 #define STEP_CH2_CLK_GPIO_Port GPIOB #define STEP_CH3_CLK_Pin GPIO_PIN_9 #define STEP_CH3_CLK_GPIO_Port GPIOB #define STEP_CH4_DIR_Pin GPIO_PIN_0 #define STEP_CH4_DIR_GPIO_Port GPIOE #define STEP_CH3_ST_Pin GPIO_PIN_1 #define STEP_CH3_ST_GPIO_Port GPIOE /* ########################## Assert Selection ############################## */ /** * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ #ifdef __cplusplus extern "C" { #endif void _Error_Handler(char *, int); #define Error_Handler() _Error_Handler(__FILE__, __LINE__) #ifdef __cplusplus } #endif #endif /* __MAIN_H__ */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

37.332075

84

0.797736

5b7b47f18b885bb07312245759269c5aac4da228

143

h

C

myLib/Classes/model/aaModel.h

gumengli123456/repos

3b77f7b2f2d765a92efc7fdead6cf22fa8a16236

[ "MIT" ]

null

myLib/Classes/model/aaModel.h

gumengli123456/repos

3b77f7b2f2d765a92efc7fdead6cf22fa8a16236

[ "MIT" ]

null

myLib/Classes/model/aaModel.h

gumengli123456/repos

3b77f7b2f2d765a92efc7fdead6cf22fa8a16236

[ "MIT" ]

null

// // aaModel.h // myLib // // Created by gumengli on 2018/3/15. // #import <Foundation/Foundation.h> @interface aaModel : NSObject @end

11

37

0.65035

1746b9ced577530a031e3b69f671475b4c18ac49

258

h

C

MB/Tools/TTXHUD/TTXMessageHUD/TTXMessageHUD.h

wxhemiao/MyBlaire

911a2367868fafea58c1c5eff4b0142aae4c2f78

[ "MIT" ]

null

MB/Tools/TTXHUD/TTXMessageHUD/TTXMessageHUD.h

wxhemiao/MyBlaire

911a2367868fafea58c1c5eff4b0142aae4c2f78

[ "MIT" ]

null

MB/Tools/TTXHUD/TTXMessageHUD/TTXMessageHUD.h

wxhemiao/MyBlaire

911a2367868fafea58c1c5eff4b0142aae4c2f78

[ "MIT" ]

null

// // Created by Tongtong Xu on 14-5-16. // Copyright (c) 2014年 Beijing Luxi Information Technology Co. Ltd. All rights reserved. // #import <UIKit/UIKit.h> @interface TTXMessageHUD : NSObject + (void)showMessageHUDWithMessage:(NSString *)message; @end

21.5

89

0.732558

c0a74077f2abe0581ee5412f3141bf92a22eb3fd

480

h

C

cmake-build-debug/exampleConfig.h

KPO-2020-2021/zad5_1-GrzegorzWojnarowicz

1e3f6817f18c07b13fe80224e05df645b8b4b34a

[ "Unlicense" ]

null

cmake-build-debug/exampleConfig.h

KPO-2020-2021/zad5_1-GrzegorzWojnarowicz

1e3f6817f18c07b13fe80224e05df645b8b4b34a

[ "Unlicense" ]

null

cmake-build-debug/exampleConfig.h

KPO-2020-2021/zad5_1-GrzegorzWojnarowicz

1e3f6817f18c07b13fe80224e05df645b8b4b34a

[ "Unlicense" ]

1

2021-12-07T22:11:13.000Z

/* * This file contains definitions made in CMakeLists.txt * that we want available in the source code. * In the source code, include "exampleConfig.h" (no .in suffix). * This header file will be generated, and filled with the * right definition values. Change the namings as you wish, * but make sure they match up with whats in CMakeLists.txt. */ #define PROJECT_VERSION_MAJOR #define PROJECT_VERSION_MINOR #define PROJECT_VERSION_PATCH #define PROJECT_VERSION_TWEAK

36.923077

65

0.772917

c0f5531621bcf49e5c362315c2b1a24b7ac2a282

692

h

C

LFDemo/Test/JSContext/CGHJSTimer.h

wulinfeng198810/LFDemo

2e637f6e7521a9d654b8b7d8672fedd554685bd4

[ "MIT" ]

null

LFDemo/Test/JSContext/CGHJSTimer.h

wulinfeng198810/LFDemo

2e637f6e7521a9d654b8b7d8672fedd554685bd4

[ "MIT" ]

null

LFDemo/Test/JSContext/CGHJSTimer.h

wulinfeng198810/LFDemo

2e637f6e7521a9d654b8b7d8672fedd554685bd4

[ "MIT" ]

null

// // CGHJSTimer.h // MiniProgramExample // // Created by wulinfeng on 2020/3/17. // Copyright © 2020 wulinfeng. All rights reserved. // #import <Foundation/Foundation.h> #import <JavaScriptCore/JavaScriptCore.h> NS_ASSUME_NONNULL_BEGIN @protocol CGHJSTimerExport <JSExport> - (void)clearTimeout:(NSString *)identifier; - (void)clearInterval:(NSString *)identifier; - (NSString *)setTimeout:(JSValue *)callback :(double)ms; - (NSString *)setInterval:(JSValue *)callback :(double)ms; @end @interface CGHJSTimer : NSObject <CGHJSTimerExport> - (void)registerInto:(JSContext*)jsContext forKeyedSubscript:(NSString *)forKeyedSubscript; - (void)clearAllTimers; @end NS_ASSUME_NONNULL_END

25.62963

91

0.763006

8d74b540f58b22e211db83c4c9aa61342c53c1dc

388

h

C

openair2/LAYER2/RLC/rlc_proto_agent_primitives.h

AManTw/oai5g

93e5617d68431a477e803af2fa66290fd52470d2

[ "Apache-2.0" ]

null

openair2/LAYER2/RLC/rlc_proto_agent_primitives.h

AManTw/oai5g

93e5617d68431a477e803af2fa66290fd52470d2

[ "Apache-2.0" ]

null

openair2/LAYER2/RLC/rlc_proto_agent_primitives.h

AManTw/oai5g

93e5617d68431a477e803af2fa66290fd52470d2

[ "Apache-2.0" ]

null

#ifndef __PROTO_AGENT_RLC_PRIMITIVES_H__ #define __PROTO_AGENT_RLC_PRIMITIVES_H__ #include "RRC/LTE/rrc_defs.h" #include "LAYER2/PROTO_AGENT/proto_agent.h" // PROTO AGENT pthread_t async_server_thread; int async_server_thread_finalize(void); void async_server_thread_init(void); pthread_mutex_t async_server_lock; pthread_cond_t async_server_notify; int async_server_shutdown; #endif

22.823529

43

0.858247

ae22d2ab34ba1bd69b683727ed639c48e2d47000

5,164

c

C

core/src/threads.c

IoTPanic/verbose-carcrash

5bbbbca184907eaf6de5efdcc714c3202522a03a

[ "BSD-2-Clause" ]

1

2020-03-18T02:50:06.000Z

core/src/threads.c

IoTPanic/verbose-carcrash

5bbbbca184907eaf6de5efdcc714c3202522a03a

[ "BSD-2-Clause" ]

1

2020-03-15T11:25:26.000Z

2020-03-16T16:06:58.000Z

core/src/threads.c

IoTPanic/verbose-carcrash

5bbbbca184907eaf6de5efdcc714c3202522a03a

[ "BSD-2-Clause" ]

null

#include <stdint.h> #include "threads.h" #include "config.h" #include "malloc.h" #include "reg.h" #define THREAD_PSP 0xFFFFFFFD /* Thread Control Block */ typedef struct { void *stack; void *orig_stack; uint8_t in_use; } tcb_t; static tcb_t tasks[MAX_TASKS]; static int lastTask; /* Caution: Without naked attribute, GCC will normally push r7 which is used * for stack pointer. If so, after restoring the tasks' context, we will get * wrong stack pointer. PendSV handles calling convention itself. */ void __attribute__((naked)) pendsv_handler() { /* Save the old task's context[1] */ asm volatile("mrs r0, psp\n" "stmdb r0!, {r4-r11, lr}\n"); /* To save the last task's sp from r0 into its tcb*/ asm volatile("mov %0, r0\n" : "=r"(tasks[lastTask].stack)); /* Find a new task to run */ while (1) { lastTask++; if (lastTask == MAX_TASKS) lastTask = 0; if (tasks[lastTask].in_use) { /* Move the task's stack pointer address into r0 */ asm volatile("mov r0, %0\n" : : "r"(tasks[lastTask].stack)); /* Restore the new task's context and jump to the task */ asm volatile("ldmia r0!, {r4-r11, lr}\n" "msr psp, r0\n" "bx lr\n"); } } } /* As PendSV does, this function also switches context and * maintain assembly on its own. This avoids the compiler * modifying register at prologue/epilogue sequences and * corrupts inline-assembly usage. */ void __attribute__((naked)) thread_start() { lastTask = 0; CONTROL_Type user_ctx = { .b.nPRIV = 1, .b.SPSEL = 1 }; /* Reset APSR before context switch * Make sure we have a _clean_ PSR for the task. */ asm volatile("mov r0, #0\n" "msr APSR_nzcvq, r0\n"); /* Load user task's context and jump to the task */ __set_PSP((uint32_t) tasks[lastTask].stack); __set_CONTROL(user_ctx.w); __ISB(); /* This is how we simulate stack handling that pendsv_handler * does. Thread_create sets 17 entries in stack, and the 9 * entries we pop here will be pushed back in pendsv_handler * in the same order. * * * pop {r4-r11, lr} * ldr r0, [sp] * stack * offset ------- * | 16 | <- Reset value of PSR * ------- * | 15 | <- Task entry * ------- * | 14 | <- LR for task * ------- * | ... | register * ------- ------- * | 9 | <- Task argument ----> | r0 | * psp after pop--< ------- * | 8 | <- EXC_RETURN ----> | lr | * ------- ------- * | 7 | | r11 | * ------- ------- * | ... | | ... | * ------- ------- * | 0 | | r4 | * psp -> ------- ------- * * Instead of "pop {r0}", use "ldr r0, [sp]" to ensure consistent * with the way how PendSV saves _old_ context[1]. */ asm volatile("pop {r4-r11, lr}\n" "ldr r0, [sp]\n"); /* Okay, we are ready to run first task, get address from * stack[15]. We just pop 9 register so #24 comes from * (15 - 9) * sizeof(entry of sp) = 6 * 4. */ asm volatile("ldr pc, [sp, #24]\n"); /* Never reach here */ while(1); } int thread_create(void (*run)(void *), void *userdata) { /* Find a free thing */ int threadId = 0; uint32_t *stack; for (threadId = 0; threadId < MAX_TASKS; threadId++) { if (tasks[threadId].in_use == 0) break; } if (threadId == MAX_TASKS) return -1; /* Create the stack */ stack = (uint32_t *) malloc(STACK_SIZE * sizeof(uint32_t)); tasks[threadId].orig_stack = stack; if (stack == 0) return -1; stack += STACK_SIZE - 17; /* End of stack, minus what we are about to push */ stack[8] = (unsigned int) THREAD_PSP; stack[9] = (unsigned int) userdata; stack[14] = (unsigned) &thread_self_terminal; stack[15] = (unsigned int) run; stack[16] = (unsigned int) 0x01000000; /* PSR Thumb bit */ /* Construct the control block */ tasks[threadId].stack = stack; tasks[threadId].in_use = 1; return threadId; } void thread_kill(int thread_id) { tasks[thread_id].in_use = 0; /* Free the stack */ free(tasks[thread_id].orig_stack); } void thread_self_terminal() { /* This will kill the stack. * For now, disable context switches to save ourselves. */ __disable_irq(); thread_kill(lastTask); __enable_irq(); /* And now wait for death to kick in */ while (1); } /* [1] Exception entry only saves R0-R4, R12, LR, PC and xPSR, * which means PendSV has to save other context (R4-R11) itself to * complete context switch. * Also, pushing LR (=EXC_RETURN) into thread stack before switching * task is needed in order to perform exception return next time the task * is selected to run. * Reference: * Cortex-M4 Devices: Generic User Guide (ARM DUI 0553A): * 2.3.7 Exception entry and return */

28.688889

78

0.554222

c46a4b28a71ca322d8802709175bc51ed7aec526

3,241

h

C

include/colour_image.h

grial1/ATIPI

c491f0b569765eff4444d69c145b9989939b359c

[ "Apache-2.0" ]

null

include/colour_image.h

grial1/ATIPI

c491f0b569765eff4444d69c145b9989939b359c

[ "Apache-2.0" ]

null

include/colour_image.h

grial1/ATIPI

c491f0b569765eff4444d69c145b9989939b359c

[ "Apache-2.0" ]

null

/** @file colour_image.h * Interfaz de la clase ColourImage * Parseo de imagenes en formato PPM a tres * objetos de tipo GreyImage (ColourImage) * @see http://netpbm.sourceforge.net/doc/pgm.html */ #ifndef ATIPI_INCLUDE_COLOUR_IMAGE_H_ #define ATIPI_INCLUDE_COLOUR_IMAGE_H_ #include "grey_image.h" /// @brief Enumeracion de colores enum Colour {RED = 0, GREEN = 1, BLUE = 2}; /** * @class ColourImage * @brief Objeto imagen a color (RGB) */ class ColourImage { public: ColourImage(); /// < Constructor por defecto ColourImage(int height, int width); /// < Constructor ColourImage(const GreyImage& oRed, const GreyImage& oGreen, const GreyImage& oBlue); /// < Constructor ColourImage(const ColourImage& oImg); /// < Copy Constructor ColourImage& operator=(const ColourImage& oImg);/// < Copy Assigment ColourImage(const char* imageFile); /// < Constructor ~ColourImage(); /// < Destructor ///@brief Método de acceso int16_t& getRedPixel(size_t row, size_t col) { return (*oRed)(row, col ); }; ///@brief Método de acceso int16_t& getGreenPixel(size_t row, size_t col) { return (*oGreen)(row, col ); }; ///@brief Método de acceso int16_t& getBluePixel(size_t row, size_t col) { return (*oBlue)(row, col ); }; ///@brief Método de acceso GreyImage& getRedImage() const { return (*oRed); }; ///@brief Método de acceso GreyImage& getGreenImage() const { return (*oGreen); }; ///@brief Método de acceso GreyImage& getBlueImage() const { return (*oBlue); }; /// @brief Operador de adición ColourImage& operator+=(const ColourImage& oDer); /// @brief Operador de substracción ColourImage& operator-=(const ColourImage& oDer); ///@brief Método para guardar imageMat en un archivo PGM void save(const char* fileName) const; ///@brief Accessor const int getWidth() const { return oRed->getWidth(); }; ///@brief Accessor const int getHeight() const { return oRed->getHeight(); }; ///@brief Accessor const tuple<int, int> getShape() const { return tuple<int, int>(oRed->getWidth(), oRed->getHeight()); }; /// @brief Transformation of colour planes void transform(); /// @brief Undo transformation of colour planes void undoTransform(); private: GreyImage* oRed = nullptr; /// < Tono de rojo GreyImage* oGreen = nullptr; /// < Tono de verde GreyImage* oBlue = nullptr; /// < Tono de azul }; /** * @brief Operador de adición * @param oIzq [in] - Operando derecho * @param oDer [in] - Operando derecho * @returns Resultado de la suma */ ColourImage& operator+(const ColourImage& oIzq, const ColourImage& oDer); /** * @brief Operador de substracción * @param oIzq [in] - Operando derecho * @param oDer [in] - Operando derecho * @returns Resultado de la resta */ ColourImage& operator-(const ColourImage& oIzq, const ColourImage& oDer); #endif /// < ATIPI_INCLUDE_COLOUR_IMAGE_H_

38.129412

112

0.614625

855fb44be9cc60d1ca464e197265f2862b656d81

1,430

h

C

Source/ModuleModelLoader.h

JorxSS/SalsaEngine

c4914060a77ebc886d1414617d44fc01a94dc563

[ "MIT" ]

null

Source/ModuleModelLoader.h

JorxSS/SalsaEngine

c4914060a77ebc886d1414617d44fc01a94dc563

[ "MIT" ]

null

Source/ModuleModelLoader.h

JorxSS/SalsaEngine

c4914060a77ebc886d1414617d44fc01a94dc563

[ "MIT" ]

1

2019-12-02T19:50:38.000Z

#ifndef __MODULEMODELLOADER_H__ #define __MODULEMODELLOADER_H__ #include "Module.h" #include "Mesh.h" #include "assimp/Importer.hpp" #include "assimp/scene.h" #include "assimp/postprocess.h" #include "assimp/Logger.hpp" #include "assimp/LogStream.hpp" #include "MathGeoLib.h" #include "Geometry/AABB.h" using namespace std; class myStream : public Assimp::LogStream { public: myStream(){} ~myStream(){} void write(const char* message) { LOG("ASSIMP:: %s\n", message); } }; class ModuleModelLoader : public Module { public: vector<Texture> textures_loaded; // stores all the textures loaded so far, optimization to make sure textures aren't loaded more than once. vector<Mesh> meshes; string directory; vector<int> textureWidth; vector<int> textureHeight; ModuleModelLoader(); ~ModuleModelLoader(); void Draw(); bool Init(); bool CleanUp(); void SwitchModel(const char*); void SwitchTexture(const char*); void RenderAABB(); aiVector3D modelPosition; aiVector3D modelScale; aiVector3D modelRotation; bool model = false; AABB modelBox; int npolys = 0; int nvertex = 0; int nmeshes= 0; private: void Load(const char*); void processNode(aiNode*, const aiScene*); Mesh processMesh(aiMesh*, const aiScene*); vector<Texture> loadMaterialTextures(aiMaterial*, aiTextureType, string); string GetModelDirectory(const char*); string GetFilename(const char*); }; #endif // __MODULEMODELLOADER_H__

21.343284

140

0.745455

8bc7f0321cb17933c8931879be716f0648a995f0

8,392

h

C

sourceCode/various/uiThread.h

mdecourse/CoppeliaSimLib

934e65b4b6ea5a07d08919ae35c50fd3ae960ef2

[ "RSA-MD" ]

null

sourceCode/various/uiThread.h

mdecourse/CoppeliaSimLib

934e65b4b6ea5a07d08919ae35c50fd3ae960ef2

[ "RSA-MD" ]

null

sourceCode/various/uiThread.h

mdecourse/CoppeliaSimLib

934e65b4b6ea5a07d08919ae35c50fd3ae960ef2

[ "RSA-MD" ]

null

#pragma once #include "3Vector.h" #include "4Vector.h" #include "7Vector.h" #include "sceneObject.h" struct SUIThreadCommand { int cmdId; std::vector<bool> boolParams; std::vector<int> intParams; std::vector<unsigned int> uintParams; std::vector<float> floatParams; std::vector<void*> objectParams; std::vector<std::string> stringParams; std::vector<C3Vector> posParams; std::vector<C4Vector> quatParams; std::vector<C7Vector> transfParams; }; enum { VMESSAGEBOX_OKELI =0, VMESSAGEBOX_YES_NO =1, VMESSAGEBOX_YES_NO_CANCEL =2, VMESSAGEBOX_OK_CANCEL =3, }; enum{ VMESSAGEBOX_REPLY_CANCEL =0, VMESSAGEBOX_REPLY_NO =1, VMESSAGEBOX_REPLY_YES =2, VMESSAGEBOX_REPLY_OK =3, VMESSAGEBOX_REPLY_ERROR =4, }; enum { OPEN_OR_CLOSE_UITHREADCMD=0, CREATE_DEFAULT_MENU_BAR_UITHREADCMD, KEEP_THUMBNAIL_QUESTION_DLG_UITHREADCMD, SELECT_THUMBNAIL_DLG_UITHREADCMD, HEIGHTFIELD_DIMENSION_DLG_UITHREADCMD, OPEN_MODAL_SCRIPT_SIMULATION_PARAMETERS_UITHREADCMD, OPEN_MODAL_MODEL_PROPERTIES_UITHREADCMD, REFRESH_DIALOGS_UITHREADCMD, CALL_DIALOG_FUNCTION_UITHREADCMD, PLUS_CVU_CMD_UITHREADCMD, PLUS_HVUD_CMD_UITHREADCMD, TOGGLE_VISUALIZATION_UITHREADCMD, VISUALIZATION_OFF_UITHREADCMD, VISUALIZATION_ON_UITHREADCMD, // FLASH_STATUSBAR_UITHREADCMD, OPEN_HIERARCHY_UITHREADCMD, CLOSE_HIERARCHY_UITHREADCMD, MAIN_WINDOW_START_MWUITHREADCMD, MAIN_WINDOW_NON_EDIT_MODE_DLG_CLOSE_MWUITHREADCMD, MAIN_WINDOW_NON_EDIT_MODE_DLG_REOPEN_MWUITHREADCMD, MAIN_WINDOW_VIEW_SELECTOR_DLG_CLOSE_MWUITHREADCMD, MAIN_WINDOW_VIEW_SELECTOR_DLG_REOPEN_MWUITHREADCMD, MAIN_WINDOW_PAGE_SELECTOR_DLG_CLOSE_MWUITHREADCMD, MAIN_WINDOW_PAGE_SELECTOR_DLG_REOPEN_MWUITHREADCMD, MAIN_WINDOW_SET_FULLSCREEN_MWTHREADCMD, MAIN_WINDOW_ACTIVATE_MWUITHREADCMD, MAIN_WINDOW_CLOSE_DLG_MWUITHREADCMD, MAIN_WINDOW_OPEN_DLG_OR_BRING_TO_FRONT_MWUITHREADCMD, MAIN_WINDOW_END_MWUITHREADCMD, SERIAL_PORT_START_SPUITHREADCMD, SERIAL_PORT_ALT_OPEN_SPUITHREADCMD, SERIAL_PORT_ALT_CLOSE_SPUITHREADCMD, SERIAL_PORT_ALT_CHECK_SPUITHREADCMD, SERIAL_PORT_ALT_SEND_SPUITHREADCMD, SERIAL_PORT_ALT_RECEIVE_SPUITHREADCMD, SERIAL_PORT_END_SPUITHREADCMD, DISPLAY_CONVEX_DECOMPOSITION_DIALOG_UITHREADCMD, SHOW_HIDE_EMERGENCY_STOP_BUTTON_UITHREADCMD, DISPLAY_MESH_DECIMATION_DIALOG_UITHREADCMD, DISPLAY_MESH_INSIDE_EXTRACTION_ITERATIONS_DIALOG_UITHREADCMD, DISPLAY_OR_HIDE_PROGRESS_DIALOG_UITHREADCMD, PLUGIN_START_PLUGUITHREADCMD, PLUGIN_LOAD_AND_START_PLUGUITHREADCMD, PLUGIN_STOP_AND_UNLOAD_PLUGUITHREADCMD, PLUGIN_END_PLUGUITHREADCMD, DESTROY_GL_TEXTURE_UITHREADCMD, DISPLAY_FILE_DLG_UITHREADCMD, DISPLAY_MSG_WITH_CHECKBOX_UITHREADCMD, DISPLAY_MSGBOX_UITHREADCMD, DETECT_VISION_SENSOR_ENTITY_UITHREADCMD, DISPLAY_SAVE_DLG_UITHREADCMD, DISPLAY_OPEN_DLG_UITHREADCMD, DISPLAY_OPEN_DLG_MULTIFILE_UITHREADCMD, DLG_INPUT_GET_FLOAT_UITHREADCMD, CREATE_GL_CONTEXT_FBO_TEXTURE_IF_NEEDED_UITHREADCMD, SET_FILEDIALOG_NATIVE_UITHREADCMD, SHOW_PRIMITIVE_SHAPE_DLG_UITHREADCMD, LOG_MSG_TO_STATUSBAR_UITHREADCMD, CLEAR_STATUSBAR_UITHREADCMD, NO_SIGNAL_SLOT_EXIT_UITHREADCMD, INSTANCE_ABOUT_TO_BE_CREATED_UITHREADCMD, INSTANCE_WAS_JUST_CREATED_UITHREADCMD, INSTANCE_ABOUT_TO_CHANGE_UITHREADCMD, INSTANCE_HAS_CHANGE_UITHREADCMD, INSTANCE_ABOUT_TO_BE_DESTROYED_UITHREADCMD, NEW_SCENE_NAME_UITHREADCMD, SIMULATION_ABOUT_TO_START_UITHREADCMD, SIMULATION_JUST_ENDED_UITHREADCMD, EDIT_MODE_ABOUT_TO_START_UITHREADCMD, EDIT_MODE_JUST_ENDED_UITHREADCMD, COPY_TEXT_TO_CLIPBOARD_UITHREADCMD, INSTANCE_PASS_FROM_UITHREAD_UITHREADCMD, MENUBAR_COLOR_UITHREADCMD, }; #ifndef SIM_WITH_QT class CUiThread { #else #include <QObject> class CUiThread : public QObject { Q_OBJECT #endif public: CUiThread(); virtual ~CUiThread(); bool executeCommandViaUiThread(SUIThreadCommand* cmdIn,SUIThreadCommand* cmdOut); void showOrHideProgressBar(bool show,float pos=999.0f,const char* txt=nullptr); bool showOrHideEmergencyStop(bool show,const char* txt); #ifndef SIM_WITH_QT void processGuiEventsUntilQuit_noSignalSlots(); #endif private: int _frameId; int _lastFrameId; #ifdef SIM_WITH_QT signals: void _executeCommandViaUiThread(SUIThreadCommand* cmdIn,SUIThreadCommand* cmdOut); private slots: void __executeCommandViaUiThread(SUIThreadCommand* cmdIn,SUIThreadCommand* cmdOut); #else void __executeCommandViaUiThread(SUIThreadCommand* cmdIn,SUIThreadCommand* cmdOut); VMutex _noSigSlotMutex; int _noSigSlot_cnter; SUIThreadCommand* _noSigSlot_cmdIn; SUIThreadCommand* _noSigSlot_cmdOut; #endif #ifdef SIM_WITH_GUI public: int getLastFrameId(); void setLastFrameId(int fid); void requestSceneRender_wait(); bool messageBox_checkbox(void* parentWidget,const char* title,const char* message,const char* checkboxMessage,bool isWarning); void setFileDialogsNative(int n); std::string getOpenFileName(void* parentWidget,unsigned short option,const char* title,const char* startPath,const char* initFilename,bool allowAnyFile,const char* extensionName,const char* extension1,const char* extension2="",const char* extension3="",const char* extension4="",const char* extension5="",const char* extension6="",const char* extension7="",const char* extension8="",const char* extension9="",const char* extension10=""); bool getOpenFileNames(std::vector<std::string>& files,void* parentWidget,unsigned short option,const char* title,const char* startPath,const char* initFilename,bool allowAnyFile,const char* extensionName,const char* extension1,const char* extension2="",const char* extension3="",const char* extension4="",const char* extension5="",const char* extension6="",const char* extension7="",const char* extension8="",const char* extension9="",const char* extension10=""); std::string getSaveFileName(void* parentWidget,unsigned short option,const char* title,const char* startPath,const char* initFilename,bool allowAnyFile,const char* extensionName,const char* extension1,const char* extension2="",const char* extension3="",const char* extension4="",const char* extension5="",const char* extension6="",const char* extension7="",const char* extension8="",const char* extension9="",const char* extension10=""); std::string getOpenOrSaveFileName_api(int mode,const char* title,const char* startPath,const char* initName,const char* extName,const char* ext); bool showPrimitiveShapeDialog(int type,const C3Vector* optionalSizesIn,C3Vector& sizes,int subdiv[3],int& faces,int& sides,int& discSubdiv,bool& smooth,int& openEnds,bool& dynamic,bool& pure,bool& cone,float& density); unsigned short messageBox_informationSystemModal(void* parentWidget,const char* title,const char* message,unsigned short flags,unsigned short defaultAnswer); unsigned short messageBox_information(void* parentWidget,const char* title,const char* message,unsigned short flags,unsigned short defaultAnswer); unsigned short messageBox_question(void* parentWidget,const char* title,const char* message,unsigned short flags,unsigned short defaultAnswer); unsigned short messageBox_warning(void* parentWidget,const char* title,const char* message,unsigned short flags,unsigned short defaultAnswer); unsigned short messageBox_critical(void* parentWidget,const char* title,const char* message,unsigned short flags,unsigned short defaultAnswer); bool dialogInputGetFloat(void* parentWidget,const char* title,const char* msg,float def,float minV,float maxV,int decimals,float* outFloat); private: unsigned short _messageBox(int type,void* parentWidget,const char* title,const char* message,unsigned short flags,unsigned short defaultAnswer); signals: void _requestSceneRender_wait(); private slots: void __requestSceneRender_wait(); #endif };

43.937173

467

0.765729

f5dc915b9f697c4d6773eaa07206c77058b086b8

1,028

h

C

Pods/SSBaseKit/SSBaseKit/AMDBase/View/AMDBaseCell.h

xie244135119/ChooseSkuDemo

751dd9cb4bdf35a575a9a727ba6376fdc107f9e3

[ "MIT" ]

1

2019-09-20T02:22:59.000Z

Pods/SSBaseKit/SSBaseKit/AMDBase/View/AMDBaseCell.h

xie244135119/ChooseSkuDemo

751dd9cb4bdf35a575a9a727ba6376fdc107f9e3

[ "MIT" ]

null

Pods/SSBaseKit/SSBaseKit/AMDBase/View/AMDBaseCell.h

xie244135119/ChooseSkuDemo

751dd9cb4bdf35a575a9a727ba6376fdc107f9e3

[ "MIT" ]

null

// // AMDBaseCell.h // AppMicroDistribution // 父类单元格 // Created by SunSet on 15-5-20. // Copyright (c) 2015年 SunSet. All rights reserved. // #import <UIKit/UIKit.h> @interface AMDBaseCell : UITableViewCell /* * 下方的属性只有当可以支持滑动的时候才可用 * supportSlide 是否支持cell滑动默认不支持 * 当cell支持滑动的时候,视图需要添加到 contentInfoView 上面 * rightSlideView 当支持cell滑动的时候,显示的视图 * 注： tableView 属性必须要设置 */ @property(nonatomic,weak) UIView *contentInfoView; //自定义内部视图 @property(nonatomic,weak) UIView *rightSlideView; //右侧编辑视图 @property(nonatomic,weak) UIPanGestureRecognizer *slidePanGestureRecognizer; //滑动手势 @property(nonatomic,weak) UITableView *tableView; //绑定的表单 @property(nonatomic) BOOL isInEditing; //当前单元格是否处于编辑状态 // 根据需要返回实例方法 // 仅当需要实现滑动效果的时候需要使用的返回实例化 - (id)initWithStyle:(UITableViewCellStyle)style reuseIdentifier:(NSString *)reuseIdentifier supportSlide:(BOOL)supportSlide cellFrame:(CGRect)frame; // 恢复cell初始状态 - (void)reset; // 隐藏遮挡视图 - (void)hideHitView; @end

21.87234

83

0.720817

eb554397d4485e3e41a14377e0c706be97673ab3

929

h

C

src/gui_font.h

entuland/trianglecenters

4c576214469e7150a1a0ed679c3dcfc26a7d1bce

[ "MIT" ]

null

src/gui_font.h

entuland/trianglecenters

4c576214469e7150a1a0ed679c3dcfc26a7d1bce

[ "MIT" ]

null

src/gui_font.h

entuland/trianglecenters

4c576214469e7150a1a0ed679c3dcfc26a7d1bce

[ "MIT" ]

null

#ifndef GUI_FONT_H #define GUI_FONT_H #include "gui_common.h" #include <string> #include <vector> #include <map> namespace GUI { class Font { class FontExcep {}; public: Font(std::string FontFileName); SDL_Surface* GetChar(std::string Character, RGBColor Foreground, RGBColor Background, int PixSize); bool BadFont() {return badfont;} private: Font& operator=(Font&) { return *this;} Font(Font&) {} std::map<std::string, std::vector<size_t> > IntImage; bool badfont; }; Uint16 RenderLine(std::string line, SDL_Surface* dest, Uint16 X, Uint16 Y, Font& font, RGBColor ForeCol, RGBColor BackCol, int PixSize); int LineLen(std::string line, Font& font, int PixSize); std::string StringVideoSpecs(); Font* GetFont(bool fixed = false); } // namespace GUI #endif // GUI_FONT_H

24.447368

81

0.615716

6bf778afe75207050037a7759025697ada53e482

4,399

c

C

svn_sensor/PC/SD_read_packet/sdpktrdr.c

GliderWinchItems/embed

cc72aa7d8208db3871a15e38185e1e125fa7de47

[ "MIT" ]

1

2019-07-18T07:22:19.000Z

svn_sensor/PC/SD_read_packet/sdpktrdr.c

GliderWinchItems/embed

cc72aa7d8208db3871a15e38185e1e125fa7de47

[ "MIT" ]

null

svn_sensor/PC/SD_read_packet/sdpktrdr.c

GliderWinchItems/embed

cc72aa7d8208db3871a15e38185e1e125fa7de47

[ "MIT" ]

2

2019-04-03T01:44:46.000Z

2020-04-01T07:41:41.000Z

/************************************************************************************ sdpktrdr.c--SD card packet reader 06-14-2013 *************************************************************************************/ /* // Example-- cd ~/svn_sensor/PC/SD_read_packet Laptop: gcc -Wall sdpktrdr.c packet_extract.c packet_print.c -o sdpktrdr -lm && sudo ./sdpktrdr /dev/sdb Desktop: gcc -Wall sdpktrdr.c packet_extract.c packet_print.c -o sdpktrdr -lm && sudo ./sdpktrdr /dev/sdf */ #define _LARGEFILE64_SOURCE #include <sys/types.h> #include <unistd.h> #include <sys/stat.h> #include <fcntl.h> #include <stdio.h> #include <stdlib.h> #include <string.h> #include <time.h> #include "packet_extract.h" #include "packet_print.h" #define BLOCKSIZE 512 unsigned char BlockBuff[BLOCKSIZE]; // Current sd block struct PKTP pktp; // Current pid, packet size, packet pointer /******************************************************************************** main ********************************************************************************/ int main (int argc, char **argv) { // FILE *fp; int fd; int blknum; int blkmax; int count; int i; off64_t o_pos; off64_t o_blk; int readct; int err; unsigned long long pid_prev; int sw_1st = 1; printf ("'sdpktrdr.c' - 06-14-2013, now 01-27-2014\n"); if (argc != 2) { printf("Need sd card device: %u, e.g. /dev/sdf\n",argc); return -1; } // fp = fopen( *(argv+1), "rb"); fd = open( *(argv+1), O_RDONLY); if (fd < 0) { printf ("\nOPEN FAIL: %u %s %d\n",argc,*(argv+1),fd); return -1; } o_pos = lseek64 (fd,(off64_t)0,SEEK_END); blkmax = o_pos/512; printf("Success: %u %s, SEEK_END returned (blocks) %d \n",argc,*(argv+1),blkmax); while (1==1) { printf("\nEnter: block_number and count: \n"); scanf("%u %u",&blknum,&count); printf ("start at block %u, count %u\n",blknum,count); sw_1st = 0; // Previous block block packet ct 1st time switch if ((count > 0) && (blknum < blkmax) ) // Check for a fat fingers entry. { // Here, it is OK. for (i = 0; i < count; i++) // Grind through the number of blocks requested { o_blk = blknum; o_blk = o_blk << 9; o_pos = lseek64(fd,o_blk,SEEK_SET); // Byte offset seek if (o_pos < 0) // In case something went awry { // Here, lseek returned an error. printf("seek error: %lld for block: %u, %llu\n",(unsigned long long)o_pos, blknum, (unsigned long long)o_blk/512); continue; } /* Read the block */ readct = read (fd, &BlockBuff[0], 512); if (readct != 512) { // Here, for some reason we didn't get the length expected from an sd card. printf("Read was not 512 bytes. It was %d\n",readct); continue; } /* Get first packet in the block */ err = packet_extract_first(&pktp, &BlockBuff[0]); if (err != 0) { // Here, finding a packet failed. // packet_print_hex(&BlockBuff[0]); if ( sdblk_allzero(&BlockBuff[0]) == 0 ) { printf("Block %u is all zeroes\n",blknum); } else { // Something other than all zeroes packet_changelines(&BlockBuff[0]); // Print change lines printf ("\nPacket err: %d, pid %llu, ct %u\n",err,pktp.pid,pktp.ct); } } else { // Here, it looks OK so far. if (sw_1st == 0) { // Here, take care of 1st time (skip difference in pid's) printf ("block_number %u pid: %llu\n",blknum,pktp.pid); sw_1st = 1; } else printf ("block_number %u pid: %llu prior block packet count %lld\n",blknum,pktp.pid,(pid_prev-pktp.pid)); packet_print(&pktp); // Nice formatted printout. } /* Go through the other packets in the block */ while (pktp.p > &BlockBuff[0]) { err = packet_extract_next(&pktp); if (err != 0) { if ( sdblk_allzero(&BlockBuff[0]) == 0 ) { printf("Block %u is all zeroes\n",blknum); } else { // Something other than all zeroes packet_changelines(&BlockBuff[0]); // Print change lines printf ("\nPacket err: %d, pid %llu, ct %u\n",err,pktp.pid,pktp.ct); } } else { packet_print(&pktp); } } pid_prev = pktp.pid; blknum += 1; } } else { // Here, the count and/or block number are out of bounds, (obviously due to fat fingers). printf ("Count must be greater than zero and block number less than %d\n",blkmax); } } return 0; }

27.322981

129

0.564901

fedb13734e998ee3f6639038ffa14d06fc5507b4

367

h

C

Microsoft.ReactNative.Cxx/UI.Xaml.Controls.h

mganandraj/react-native-windows-dbg

bc29156de6a984795a4956790adf53f4f9037df3

[ "MIT" ]

null

Microsoft.ReactNative.Cxx/UI.Xaml.Controls.h

mganandraj/react-native-windows-dbg

bc29156de6a984795a4956790adf53f4f9037df3

[ "MIT" ]

null

Microsoft.ReactNative.Cxx/UI.Xaml.Controls.h

mganandraj/react-native-windows-dbg

bc29156de6a984795a4956790adf53f4f9037df3

[ "MIT" ]

null

// Copyright (c) Microsoft Corporation. // Licensed under the MIT License. #pragma once #ifdef USE_WINUI3 #include <winrt/Microsoft.UI.Xaml.Controls.h> namespace winrt::Microsoft::UI::Xaml::Controls { using IControl7 = Control; } // namespace winrt::Microsoft::UI::Xaml::Controls #else #include <winrt/Windows.UI.Xaml.Controls.h> #endif // USE_WINUI3

26.214286

52

0.722071

6b69e6408f81349448715749e170289ec671342d

3,570

h

C

cpp/common/dataStructures/StructParser.h

ProkopHapala/SimpleSimulationEngine

240f9b7e85b3a6eda7a27dc15fe3f7b8c08774c5

[ "MIT" ]

26

2016-12-04T04:45:12.000Z

2022-03-24T09:39:28.000Z

cpp/common/dataStructures/StructParser.h

ProkopHapala/SimpleSimulationEngine

240f9b7e85b3a6eda7a27dc15fe3f7b8c08774c5

[ "MIT" ]

null

cpp/common/dataStructures/StructParser.h

ProkopHapala/SimpleSimulationEngine

240f9b7e85b3a6eda7a27dc15fe3f7b8c08774c5

[ "MIT" ]

2

2019-02-09T12:31:06.000Z

2019-04-28T02:24:50.000Z

#ifndef StructParser_h #define StructParser_h #include <vector> #include <cstdio> #include <cstring> #include "parsing.h" namespace parsing{ class StructParser{ public: std::vector<ParserItem> items; int ich; int nch; char * str; // params char cOPEN = '{'; char cCLOSE = '}'; char cNEXT = ';'; void parseString( int nch_, char * str_ ){ str = str_; nch = nch_; ich = 0; //printf( "%s\n", str ); parse( 0, 0, -1 ); } int parse( int ich0, int level, int parent ){ int oi = ich0; ich = oi; int nbranch = 0; int iCur = -1; //printf( "%s\n", str ); //printf( "ich0 %i level %i \n", ich0, level ); while( ich < nch ){ char ch = str[ich]; //printf( "%i : %c\n", ich, ch ); if (ch==cNEXT){ if( iCur<0 ){ items.push_back( (ParserItem){oi,ich-oi,0,0,0, level, parent} ); printf("LEAF item[%i] %i %i : %.*s\n", items.size()-1, level, parent, ich-oi,str+oi ); }else{ items[iCur].nch = ich-oi; //printf( " finished %i \n", ich ); } nbranch++; iCur = -1; oi = ich+1; //} }else if (ch==cOPEN) { iCur = items.size(); items.push_back( (ParserItem){oi,0,ich-oi,0,0,level, parent} ); printf("NODE item[%i] %i %i : %.*s\n", items.size()-1, level, parent, ich-oi,str+oi ); parse( ich+1, level+1, iCur ); }else if (ch==cCLOSE) { if( parent>=0 ){ items[parent].nbranch = nbranch; items[parent].nitem = items.size()-parent; } return 0; } ich++; } return 0; } int get( const char * name ){ // use like: parser.get( "Name1.Name3.Name6" ); // fast search for named item within string const char * id = name; int nch = strchr( id, '.') - id; int iit = 0; while(iit < items.size() ){ ParserItem& it = items[iit]; if( strncmp( id, str+it.ibeg, nch ) == 0 ){ // found id += nch; nch = strchr( id, '.') - id; }else{ iit += it.nitem; // skip all sub-items } } return iit; } void printItemStruct(){ for( int i=0; i<items.size(); i++ ){ //for( ParserItem& item : items ){ ParserItem& it = items[i]; //printf("%03i (%04i,%02i) %02i(%02i,%02i) : ", i, it.ibeg, it.iend-it.ibeg, it.level, it.nbranch, it.nitem ); printf("%03i (%04i,%04i) (%02i,%02i) %03i %03i : ", i, it.ibeg, it.nch, it.nbranch,it.nitem, it.level, it.parent ); printf("%*c" , 4*it.level, ' ' ); //printf("%.*s\n", it.iend-it.ibeg, str + it.ibeg ); if( (it.nbranch+it.nitem)>0 ){ printf("%.*s", it.nch_name, str + it.ibeg ); printf("|" ); //printf("%.*s\n", it.iend-it.ibeg-it.nch_name, str + it.ibeg+it.nch_name ); printf("%.*s\n", it.nch-it.nch_name, str + it.ibeg+it.nch_name ); }else{ //printf("%.*s\n", it.iend-it.ibeg, str + it.ibeg ); printf("%.*s\n", it.nch, str + it.ibeg ); } } } }; } #endif

30.512821

128

0.427731

b14f307561e198f87b39d90defbc779255850b9e

1,555

h

C

include/libraries/amisslmaster.h

bocke/amissl

6f64d81d1face433ba9656427ae64b9a2fc9e066

[ "BSD-3-Clause" ]

null

include/libraries/amisslmaster.h

bocke/amissl

6f64d81d1face433ba9656427ae64b9a2fc9e066

[ "BSD-3-Clause" ]

null

include/libraries/amisslmaster.h

bocke/amissl

6f64d81d1face433ba9656427ae64b9a2fc9e066

[ "BSD-3-Clause" ]

null

#ifndef LIBRARIES_AMISSLMASTER_H #define LIBRARIES_AMISSLMASTER_H #define AMISSL_V2 0x01 /* OBSOLETE NAME */ #define AMISSL_V096g 0x01 /* AmiSSL v2 */ #define AMISSL_V097g 0x02 /* AmiSSL v3.6/3.7 */ #define AMISSL_V097m 0x03 /* unreleased version */ #define AMISSL_V098y 0x04 /* unreleased version */ #define AMISSL_V102f 0x05 /* unreleased version */ #define AMISSL_V110c 0x06 /* unreleased version */ #define AMISSL_V110d 0x07 /* AmiSSL v4.0 */ #define AMISSL_V110e 0x08 /* AmiSSL v4.1 */ #define AMISSL_V110g 0x09 /* AmiSSL v4.2 */ #define AMISSL_V111a_OBS 0x0a /* AmiSSL v4.3 (obsolete incompatible API) */ #define AMISSL_V111d 0x0b /* AmiSSL v4.4/4.5 */ #define AMISSL_V111g 0x0c /* AmiSSL v4.6 */ #define AMISSL_V111i 0x0d /* AmiSSL v4.7 */ #define AMISSL_V111j 0x0e /* AmiSSL v4.8 */ #define AMISSL_V111k 0x0f /* AmiSSL v4.9 */ #define AMISSL_V111l 0x10 /* AmiSSL v4.10/4.11 */ #define AMISSL_V111m 0x11 /* AmiSSL v4.12 */ #define AMISSL_V300 0x12 /* AmiSSL v5.0 */ #define AMISSL_V10x AMISSL_V102f /* Latest minimum AmiSSL/OpenSSL 1.0.x compatible version */ #define AMISSL_V11x AMISSL_V110d /* Latest minimum AmiSSL/OpenSSL 1.1.x compatible version */ #define AMISSL_V3xx AMISSL_V300 /* Latest minimum AmiSSL/OpenSSL 3.x.x compatible version */ #define AMISSL_CURRENT_VERSION AMISSL_V300 #define AMISSLMASTER_MIN_VERSION 5 #endif /* !LIBRARIES_AMISSLMASTER_H */

47.121212

101

0.667524

38972863907dbd4de9c58e58726bc3401df1e577

2,422

h

C

ios/library/WhirlyGlobe-MaplyComponent/include/vector_styles/MaplyVectorStyleSimple.h

bacem86/WhirlyGlobe-1

79cf79d7e88e405cf476e638c17aa09bb79b06df

[ "Apache-2.0" ]

null

ios/library/WhirlyGlobe-MaplyComponent/include/vector_styles/MaplyVectorStyleSimple.h

bacem86/WhirlyGlobe-1

79cf79d7e88e405cf476e638c17aa09bb79b06df

[ "Apache-2.0" ]

null

ios/library/WhirlyGlobe-MaplyComponent/include/vector_styles/MaplyVectorStyleSimple.h

bacem86/WhirlyGlobe-1

79cf79d7e88e405cf476e638c17aa09bb79b06df

[ "Apache-2.0" ]

null

/* MaplyVectorStyleSimple.m * WhirlyGlobe-MaplyComponent * * Created by Steve Gifford on 3/15/16. * Copyright 2011-2022 mousebird consulting * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #import <Foundation/Foundation.h> #import "vector_tiles/MapboxVectorTiles.h" /** Simple default style to see something in vector tile data. A simple vector style that displays each layer in a random color. Use this as a starting point for your own style. */ @interface MaplyVectorStyleSimpleGenerator : NSObject<MaplyVectorStyleDelegate> @property (nonatomic,weak) NSObject<MaplyRenderControllerProtocol> *viewC; /// Initialize with a map view controller - (id)initWithViewC:(NSObject<MaplyRenderControllerProtocol> *)viewC; /// uuid for the styles - (long long)generateID; @end /** Base class for the simple vector style. */ @interface MaplyVectorStyleSimple : NSObject<MaplyVectorStyle> /// Unique Identifier for this style @property (nonatomic) long long uuid; /// Set if this geometry is additive (e.g. sticks around) rather than replacement @property (nonatomic) bool geomAdditive; /// Priority for sorting among layers @property (nonatomic) int drawPriority; @property (nonatomic,weak) NSObject<MaplyRenderControllerProtocol> *viewC; - (id)initWithGen:(MaplyVectorStyleSimpleGenerator *)gen viewC:(NSObject<MaplyRenderControllerProtocol> *)viewC; @end /** Simple filled polygon with a random color. */ @interface MaplyVectorStyleSimplePolygon : MaplyVectorStyleSimple @property (nonatomic,strong) UIColor *color; @end /** Simple point we'll convert to a label. */ @interface MaplyVectorStyleSimplePoint : MaplyVectorStyleSimple @property (nonatomic,strong) UIFont *font; @end /** Simple linear with a random color. */ @interface MaplyVectorStyleSimpleLinear : MaplyVectorStyleSimple @property (nonatomic,strong) UIColor *color; @end

28.162791

112

0.756813

38db6c4635c20b84269b2af03e3b904be5875c02

3,623

h

C

libBKPLPlot/qsastimeP.h

rsuchecki/biokanga

ef0fa1cf58fb2903ae18d14e5b0f84de7b7e744e

[ "MIT" ]

null

libBKPLPlot/qsastimeP.h

rsuchecki/biokanga

ef0fa1cf58fb2903ae18d14e5b0f84de7b7e744e

[ "MIT" ]

null

libBKPLPlot/qsastimeP.h

rsuchecki/biokanga

ef0fa1cf58fb2903ae18d14e5b0f84de7b7e744e

[ "MIT" ]

null

#ifndef _QSASTIMEP_H_ #define _QSASTIMEP_H_ // Declaration of private structures within libqsastime which the user does // not need to acccess. // Also definition of functions within libqsastime that are needed // for testing of libqsastime, but which are not normally needed for anything // else #include "qsastime.h" typedef struct MJDtimeStruct { // // MJD starts at 0h, so truncating MJD always gives the same day whatever the time (unlike JD). // The MJD base day is arbitrary, i.e. seconds can be greater than one day or even negative. // int base_day; // integer part of MJD used as default double time_sec; // seconds from start of base_day }MJDtime; struct QSASConfigStruct { // Values used to define the transformation between broken down time // and continuous time for the public API of libqsastime, // continuous_time_qsas, broken_down_time_qsas, and strfqsas. // scale multiplies the continuous time variable to convert the units to // days. double scale; // offset1 and offset2 (in days) specifies the amount to add to the // scaled continuous time to derive the MJD time value that is used // internally by libqsastime. Normally epoch1 is an integral // value (which can be exactly stored in a double for a very wide // range of integers) and offset2 is normally a non-integral value // whose absolute value is less than 1. This arrangement allows the // continuous time variable in the API to be stored as a single double // without compromising numerical precision if epoch1 and epoch2 // are chosen wisely. double offset1, offset2; // The various bits of ccontrol are used as independent switches to // control optional additional corrections which define the // transformation between continuous time and broken-down time. // // If bit 0 (the lowest order bit of ccontrol) is 1 the Julian // proleptic calendar is used for broken-down time. Otherwise the // Gregorian proleptic calendar is used for broken-down time. // // If bit 1 is 1, an additional correction for the difference // between atomic-clock based times and UTC is applied to the broken-down // times. // // We reserve other bits of ccontrol for future use. int ccontrol; // index keeps track of latest bhunt_search index. int index; }; // Set if the qsastime library is being tested. /* #undef TEST_QSASTIME */ #ifdef TEST_QSASTIME #define QSASTIME_static #else //#define QSASTIME_static static #define QSASTIME_static #endif QSASTIME_static void bhunt_search( const void *key, const void *base, int n, size_t size, int *low, int ( *ge )( const void *keyval, const void *datum ) ); QSASTIME_static int setFromUT( int year, int month, int day, int hour, int min, double sec, MJDtime *MJD, int forceJulian ); QSASTIME_static void breakDownMJD( int *year, int *month, int *day, int *hour, int *min, double *sec, const MJDtime *MJD, int forceJulian ); QSASTIME_static size_t strfMJD( char * buf, size_t len, const char *format, const MJDtime *MJD, int forceJulian, int if60secformat ); QSASTIME_static void normalize_MJD( MJDtime *MJD ); QSASTIME_static const char * getDayOfWeek( const MJDtime *MJD ); QSASTIME_static const char * getLongDayOfWeek( const MJDtime *MJD ); QSASTIME_static const char * getMonth( int m ); QSASTIME_static const char * getLongMonth( int m ); QSASTIME_static void getYAD( int *year, int *ifleapyear, int *doy, const MJDtime *MJD, int forceJulian ); #endif

42.623529

156

0.714601

75b7e6ebe239be20500f2fb5bd08d36cdcd7f5ca

242

c

C

packages/PIPS/validation/Semantics-New/Pointer.sub/typedef03.c

DVSR1966/par4all

86b33ca9da736e832b568c5637a2381f360f1996

[ "MIT" ]

51

2015-01-31T01:51:39.000Z

2022-02-18T02:01:50.000Z

packages/PIPS/validation/Semantics-New/Pointer.sub/typedef03.c

DVSR1966/par4all

86b33ca9da736e832b568c5637a2381f360f1996

[ "MIT" ]

7

2017-05-29T09:29:00.000Z

2019-03-11T16:01:39.000Z

packages/PIPS/validation/Semantics-New/Pointer.sub/typedef03.c

DVSR1966/par4all

86b33ca9da736e832b568c5637a2381f360f1996

[ "MIT" ]

12

2015-03-26T08:05:38.000Z

2022-02-18T02:01:51.000Z

typedef unsigned char BYTE; typedef unsigned char *P_BYTE; int main() { BYTE a[10], b[10]; P_BYTE p0, q1; BYTE *q0, *p1; p0=a; q0=p0+1; *p0 = 0; *q0 = 0; p1=b; q1=p1+1; *p1 = 0; *q1 = 0; return 0; }

8.962963

30

0.487603

0e74eb16c3f8d705c3f91e98c2184f032471cb4e

2,482

h

C

src/hg/inc/contigAcc.h

andypohl/kent

af7a004c8f3fa909cd8c2cfc2e5bea60e3421cd1

[ "MIT" ]

171

2015-04-22T15:16:02.000Z

2022-03-18T20:21:53.000Z

src/hg/inc/contigAcc.h

andypohl/kent

af7a004c8f3fa909cd8c2cfc2e5bea60e3421cd1

[ "MIT" ]

60

2016-10-03T15:15:06.000Z

2022-03-30T15:21:52.000Z

src/hg/inc/contigAcc.h

andypohl/kent

af7a004c8f3fa909cd8c2cfc2e5bea60e3421cd1

[ "MIT" ]

80

2015-04-16T10:39:48.000Z

2022-03-29T16:36:30.000Z

/* contigAcc.h was originally generated by the autoSql program, which also * generated contigAcc.c and contigAcc.sql. This header links the database and * the RAM representation of objects. */ /* Copyright (C) 2004 The Regents of the University of California * See kent/LICENSE or http://genome.ucsc.edu/license/ for licensing information. */ #ifndef CONTIGACC_H #define CONTIGACC_H #define CONTIGACC_NUM_COLS 2 struct contigAcc /* Map a contig to its accession. */ { struct contigAcc *next; /* Next in singly linked list. */ char *contig; /* Contig name */ char *acc; /* Genbank accession */ }; void contigAccStaticLoad(char **row, struct contigAcc *ret); /* Load a row from contigAcc table into ret. The contents of ret will * be replaced at the next call to this function. */ struct contigAcc *contigAccLoad(char **row); /* Load a contigAcc from row fetched with select * from contigAcc * from database. Dispose of this with contigAccFree(). */ struct contigAcc *contigAccLoadAll(char *fileName); /* Load all contigAcc from whitespace-separated file. * Dispose of this with contigAccFreeList(). */ struct contigAcc *contigAccLoadAllByChar(char *fileName, char chopper); /* Load all contigAcc from chopper separated file. * Dispose of this with contigAccFreeList(). */ #define contigAccLoadAllByTab(a) contigAccLoadAllByChar(a, '\t'); /* Load all contigAcc from tab separated file. * Dispose of this with contigAccFreeList(). */ struct contigAcc *contigAccCommaIn(char **pS, struct contigAcc *ret); /* Create a contigAcc out of a comma separated string. * This will fill in ret if non-null, otherwise will * return a new contigAcc */ void contigAccFree(struct contigAcc **pEl); /* Free a single dynamically allocated contigAcc such as created * with contigAccLoad(). */ void contigAccFreeList(struct contigAcc **pList); /* Free a list of dynamically allocated contigAcc's */ void contigAccOutput(struct contigAcc *el, FILE *f, char sep, char lastSep); /* Print out contigAcc. Separate fields with sep. Follow last field with lastSep. */ #define contigAccTabOut(el,f) contigAccOutput(el,f,'\t','\n'); /* Print out contigAcc as a line in a tab-separated file. */ #define contigAccCommaOut(el,f) contigAccOutput(el,f,',',','); /* Print out contigAcc as a comma separated list including final comma. */ /* -------------------------------- End autoSql Generated Code -------------------------------- */ #endif /* CONTIGACC_H */

37.606061

98

0.717969

8a5403547ea4911c30086d112d3eca7e62a8c9b5

12,653

h

C

arch/arm/src/samd5e5/sam_config.h

eenurkka/incubator-nuttx

5c3d6bba6d9ec5015896c3019cd2064696373210

[ "Apache-2.0" ]

1,006

2019-12-17T23:45:41.000Z

2022-03-31T19:42:44.000Z

arch/arm/src/samd5e5/sam_config.h

eenurkka/incubator-nuttx

5c3d6bba6d9ec5015896c3019cd2064696373210

[ "Apache-2.0" ]

2,661

2019-12-21T15:16:09.000Z

2022-03-31T22:30:04.000Z

arch/arm/src/samd5e5/sam_config.h

eenurkka/incubator-nuttx

5c3d6bba6d9ec5015896c3019cd2064696373210

[ "Apache-2.0" ]

613

2019-12-21T10:17:37.000Z

2022-03-28T09:42:20.000Z

/**************************************************************************** * arch/arm/src/samd5e5/sam_config.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_CONFIG_H #define __ARCH_ARM_SRC_SAMD5E5_SAM_CONFIG_H /**************************************************************************** * Included Files ****************************************************************************/ #include <nuttx/config.h> /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ /* How many SERCOM peripherals are configured as USART peripherals? */ #define SAMD5E5_HAVE_USART0 1 #define SAMD5E5_HAVE_USART1 1 #define SAMD5E5_HAVE_USART2 1 #define SAMD5E5_HAVE_USART3 1 #define SAMD5E5_HAVE_USART4 1 #define SAMD5E5_HAVE_USART5 1 #define SAMD5E5_HAVE_USART6 1 #define SAMD5E5_HAVE_USART7 1 #if !defined(CONFIG_SAMD5E5_SERCOM0) || !defined(CONFIG_SAMD5E5_SERCOM0_ISUSART) || \ !defined(CONFIG_USART0_SERIALDRIVER) # undef SAMD5E5_HAVE_USART0 # undef CONFIG_SAMD5E5_SERCOM0_ISUSART # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART0_FLOWCONTROL # undef CONFIG_USART0_IRDAMODE # undef CONFIG_USART0_RS485MODE #endif #if !defined(CONFIG_SAMD5E5_SERCOM1) || !defined(CONFIG_SAMD5E5_SERCOM1_ISUSART) || \ !defined(CONFIG_USART1_SERIALDRIVER) # undef SAMD5E5_HAVE_USART1 # undef CONFIG_SAMD5E5_SERCOM1_ISUSART # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART1_FLOWCONTROL # undef CONFIG_USART1_IRDAMODE # undef CONFIG_USART1_RS485MODE #endif #if !defined(CONFIG_SAMD5E5_SERCOM2) || !defined(CONFIG_SAMD5E5_SERCOM2_ISUSART) || \ !defined(CONFIG_USART2_SERIALDRIVER) # undef SAMD5E5_HAVE_USART2 # undef CONFIG_SAMD5E5_SERCOM2_ISUSART # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART2_FLOWCONTROL # undef CONFIG_USART2_IRDAMODE # undef CONFIG_USART2_RS485MODE #endif #if !defined(CONFIG_SAMD5E5_SERCOM3) || !defined(CONFIG_SAMD5E5_SERCOM3_ISUSART) || \ !defined(CONFIG_USART3_SERIALDRIVER) # undef SAMD5E5_HAVE_USART3 # undef CONFIG_SAMD5E5_SERCOM3_ISUSART # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART3_FLOWCONTROL # undef CONFIG_USART3_IRDAMODE # undef CONFIG_USART3_RS485MODE #endif #if !defined(CONFIG_SAMD5E5_SERCOM4) || !defined(CONFIG_SAMD5E5_SERCOM4_ISUSART) || \ !defined(CONFIG_USART4_SERIALDRIVER) # undef SAMD5E5_HAVE_USART4 # undef CONFIG_SAMD5E5_SERCOM4_ISUSART # undef CONFIG_USART4_SERIAL_CONSOLE # undef CONFIG_USART4_FLOWCONTROL # undef CONFIG_USART4_IRDAMODE # undef CONFIG_USART4_RS485MODE #endif #if !defined(CONFIG_SAMD5E5_SERCOM5) || !defined(CONFIG_SAMD5E5_SERCOM5_ISUSART) || \ !defined(CONFIG_USART5_SERIALDRIVER) # undef SAMD5E5_HAVE_USART5 # undef CONFIG_SAMD5E5_SERCOM5_ISUSART # undef CONFIG_USART5_SERIAL_CONSOLE # undef CONFIG_USART5_FLOWCONTROL # undef CONFIG_USART5_IRDAMODE # undef CONFIG_USART5_RS485MODE #endif #if !defined(CONFIG_SAMD5E5_SERCOM6) || !defined(CONFIG_SAMD5E5_SERCOM6_ISUSART) || \ !defined(CONFIG_USART6_SERIALDRIVER) # undef SAMD5E5_HAVE_USART6 # undef CONFIG_SAMD5E5_SERCOM6_ISUSART # undef CONFIG_USART6_SERIAL_CONSOLE # undef CONFIG_USART6_FLOWCONTROL # undef CONFIG_USART6_IRDAMODE # undef CONFIG_USART6_RS485MODE #endif #if !defined(CONFIG_SAMD5E5_SERCOM7) || !defined(CONFIG_SAMD5E5_SERCOM7_ISUSART) || \ !defined(CONFIG_USART7_SERIALDRIVER) # undef SAMD5E5_HAVE_USART7 # undef CONFIG_SAMD5E5_SERCOM7_ISUSART # undef CONFIG_USART7_SERIAL_CONSOLE # undef CONFIG_USART7_FLOWCONTROL # undef CONFIG_USART7_IRDAMODE # undef CONFIG_USART7_RS485MODE #endif /* Are any USARTs enabled? */ #undef SAMD5E5_HAVE_USART #if defined(SAMD5E5_HAVE_USART0) || defined(SAMD5E5_HAVE_USART1) || \ defined(SAMD5E5_HAVE_USART2) || defined(SAMD5E5_HAVE_USART3) || \ defined(SAMD5E5_HAVE_USART4) || defined(SAMD5E5_HAVE_USART5) || \ defined(SAMD5E5_HAVE_USART6) || defined(SAMD5E5_HAVE_USART7) # define SAMD5E5_HAVE_USART 1 #endif /* Is there a serial console? There should be at most one defined. * It could be on any USARTn, n=0-5 - OR - there might not be any * serial console at all. */ #if defined(CONFIG_USART0_SERIAL_CONSOLE) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE # undef CONFIG_USART5_SERIAL_CONSOLE # undef CONFIG_USART6_SERIAL_CONSOLE # undef CONFIG_USART7_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 #elif defined(CONFIG_USART1_SERIAL_CONSOLE) # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE # undef CONFIG_USART5_SERIAL_CONSOLE # undef CONFIG_USART6_SERIAL_CONSOLE # undef CONFIG_USART7_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 #elif defined(CONFIG_USART2_SERIAL_CONSOLE) # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE # undef CONFIG_USART5_SERIAL_CONSOLE # undef CONFIG_USART6_SERIAL_CONSOLE # undef CONFIG_USART7_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 #elif defined(CONFIG_USART3_SERIAL_CONSOLE) # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE # undef CONFIG_USART5_SERIAL_CONSOLE # undef CONFIG_USART6_SERIAL_CONSOLE # undef CONFIG_USART7_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 #elif defined(CONFIG_USART4_SERIAL_CONSOLE) # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART5_SERIAL_CONSOLE # undef CONFIG_USART6_SERIAL_CONSOLE # undef CONFIG_USART7_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 #elif defined(CONFIG_USART5_SERIAL_CONSOLE) # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE # undef CONFIG_USART6_SERIAL_CONSOLE # undef CONFIG_USART7_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 #elif defined(CONFIG_USART6_SERIAL_CONSOLE) # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE # undef CONFIG_USART5_SERIAL_CONSOLE # undef CONFIG_USART7_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 #elif defined(CONFIG_USART7_SERIAL_CONSOLE) # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE # undef CONFIG_USART5_SERIAL_CONSOLE # undef CONFIG_USART6_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 #else # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE # undef CONFIG_USART5_SERIAL_CONSOLE # undef CONFIG_USART6_SERIAL_CONSOLE # undef CONFIG_USART7_SERIAL_CONSOLE # undef HAVE_SERIAL_CONSOLE #endif /* Are any SERCOM peripherals are configured as SPI peripherals? */ #define SAMD5E5_HAVE_SPI0 1 #define SAMD5E5_HAVE_SPI1 1 #define SAMD5E5_HAVE_SPI2 1 #define SAMD5E5_HAVE_SPI3 1 #define SAMD5E5_HAVE_SPI4 1 #define SAMD5E5_HAVE_SPI5 1 #define SAMD5E5_HAVE_SPI6 1 #define SAMD5E5_HAVE_SPI7 1 #if !defined(CONFIG_SAMD5E5_SERCOM0) || !defined(CONFIG_SAMD5E5_SERCOM0_ISSPI) # undef SAMD5E5_HAVE_SPI0 # undef CONFIG_SAMD5E5_SERCOM0_ISSPI #endif #if !defined(CONFIG_SAMD5E5_SERCOM1) || !defined(CONFIG_SAMD5E5_SERCOM1_ISSPI) # undef SAMD5E5_HAVE_SPI1 # undef CONFIG_SAMD5E5_SERCOM1_ISSPI #endif #if !defined(CONFIG_SAMD5E5_SERCOM2) || !defined(CONFIG_SAMD5E5_SERCOM2_ISSPI) # undef SAMD5E5_HAVE_SPI2 # undef CONFIG_SAMD5E5_SERCOM2_ISSPI #endif #if !defined(CONFIG_SAMD5E5_SERCOM3) || !defined(CONFIG_SAMD5E5_SERCOM3_ISSPI) # undef SAMD5E5_HAVE_SPI3 # undef CONFIG_SAMD5E5_SERCOM3_ISSPI #endif #if !defined(CONFIG_SAMD5E5_SERCOM4) || !defined(CONFIG_SAMD5E5_SERCOM4_ISSPI) # undef SAMD5E5_HAVE_SPI4 # undef CONFIG_SAMD5E5_SERCOM4_ISSPI #endif #if !defined(CONFIG_SAMD5E5_SERCOM5) || !defined(CONFIG_SAMD5E5_SERCOM5_ISSPI) # undef SAMD5E5_HAVE_SPI5 # undef CONFIG_SAMD5E5_SERCOM5_ISSPI #endif #if !defined(CONFIG_SAMD5E5_SERCOM6) || !defined(CONFIG_SAMD5E5_SERCOM6_ISSPI) # undef SAMD5E5_HAVE_SPI6 # undef CONFIG_SAMD5E5_SERCOM6_ISSPI #endif #if !defined(CONFIG_SAMD5E5_SERCOM7) || !defined(CONFIG_SAMD5E5_SERCOM7_ISSPI) # undef SAMD5E5_HAVE_SPI7 # undef CONFIG_SAMD5E5_SERCOM7_ISSPI #endif /* Are any SERCOMs configured for SPI? */ #undef SAMD5E5_HAVE_SPI #if defined(SAMD5E5_HAVE_SPI0) || defined(SAMD5E5_HAVE_SPI1) || \ defined(SAMD5E5_HAVE_SPI2) || defined(SAMD5E5_HAVE_SPI3) || \ defined(SAMD5E5_HAVE_SPI4) || defined(SAMD5E5_HAVE_SPI5) || \ defined(SAMD5E5_HAVE_SPI6) || defined(SAMD5E5_HAVE_SPI7) # define SAMD5E5_HAVE_SPI 1 #endif /* Are any SERCOM peripherals are configured as I2C peripherals? */ #define SAMD5E5_HAVE_I2C0_MASTER 1 #define SAMD5E5_HAVE_I2C1_MASTER 1 #define SAMD5E5_HAVE_I2C2_MASTER 1 #define SAMD5E5_HAVE_I2C3_MASTER 1 #define SAMD5E5_HAVE_I2C4_MASTER 1 #define SAMD5E5_HAVE_I2C5_MASTER 1 #define SAMD5E5_HAVE_I2C6_MASTER 1 #define SAMD5E5_HAVE_I2C7_MASTER 1 #if !defined(CONFIG_SAMD5E5_SERCOM0) || !defined(CONFIG_SAMD5E5_SERCOM0_ISI2C) # undef SAMD5E5_HAVE_I2C0_MASTER # undef CONFIG_SAMD5E5_SERCOM0_ISI2C #endif #if !defined(CONFIG_SAMD5E5_SERCOM1) || !defined(CONFIG_SAMD5E5_SERCOM1_ISI2C) # undef SAMD5E5_HAVE_I2C1_MASTER # undef CONFIG_SAMD5E5_SERCOM1_ISI2C #endif #if !defined(CONFIG_SAMD5E5_SERCOM2) || !defined(CONFIG_SAMD5E5_SERCOM2_ISI2C) # undef SAMD5E5_HAVE_I2C2_MASTER # undef CONFIG_SAMD5E5_SERCOM2_ISI2C #endif #if !defined(CONFIG_SAMD5E5_SERCOM3) || !defined(CONFIG_SAMD5E5_SERCOM3_ISI2C) # undef SAMD5E5_HAVE_I2C3_MASTER # undef CONFIG_SAMD5E5_SERCOM3_ISI2C #endif #if !defined(CONFIG_SAMD5E5_SERCOM4) || !defined(CONFIG_SAMD5E5_SERCOM4_ISI2C) # undef SAMD5E5_HAVE_I2C4_MASTER # undef CONFIG_SAMD5E5_SERCOM4_ISI2C #endif #if !defined(CONFIG_SAMD5E5_SERCOM5) || !defined(CONFIG_SAMD5E5_SERCOM5_ISI2C) # undef SAMD5E5_HAVE_I2C5_MASTER # undef CONFIG_SAMD5E5_SERCOM5_ISI2C #endif #if !defined(CONFIG_SAMD5E5_SERCOM6) || !defined(CONFIG_SAMD5E5_SERCOM6_ISI2C) # undef SAMD5E5_HAVE_I2C6_MASTER # undef CONFIG_SAMD5E5_SERCOM6_ISI2C #endif #if !defined(CONFIG_SAMD5E5_SERCOM7) || !defined(CONFIG_SAMD5E5_SERCOM7_ISI2C) # undef SAMD5E5_HAVE_I2C7_MASTER # undef CONFIG_SAMD5E5_SERCOM7_ISI2C #endif /* Are any SERCOMs configured for I2C? */ #undef SAMD5E5_HAVE_I2C_MASTER #if defined(SAMD5E5_HAVE_I2C0_MASTER) || defined(SAMD5E5_HAVE_I2C1_MASTER) || \ defined(SAMD5E5_HAVE_I2C2_MASTER) || defined(SAMD5E5_HAVE_I2C3_MASTER) || \ defined(SAMD5E5_HAVE_I2C4_MASTER) || defined(SAMD5E5_HAVE_I2C5_MASTER) || \ defined(SAMD5E5_HAVE_I2C6_MASTER) || defined(SAMD5E5_HAVE_I2C7_MASTER) # define SAMD5E5_HAVE_I2C_MASTER 1 #endif /**************************************************************************** * Public Types ****************************************************************************/ /**************************************************************************** * Public Data ****************************************************************************/ /**************************************************************************** * Public Functions Prototypes ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_CONFIG_H */

35.245125

85

0.764325

0e57761c36ca8ad55e23bcd30eab082074efe402

1,163

c

C

ft_strmap.c

Hollyol/libft

7fb8f04df11f844c82e459e5ee32b720cb3f99a8

[ "MIT" ]

null

ft_strmap.c

Hollyol/libft

7fb8f04df11f844c82e459e5ee32b720cb3f99a8

[ "MIT" ]

null

ft_strmap.c

Hollyol/libft

7fb8f04df11f844c82e459e5ee32b720cb3f99a8

[ "MIT" ]

null

/* ************************************************************************** */ /* */ /* ::: :::::::: */ /* ft_strmap.c :+: :+: :+: */ /* +:+ +:+ +:+ */ /* By: xapadoan <marvin@42.fr> +#+ +:+ +#+ */ /* +#+#+#+#+#+ +#+ */ /* Created: 2018/11/08 14:18:25 by xapadoan #+# #+# */ /* Updated: 2018/11/19 12:27:13 by xapadoan ### ########.fr */ /* */ /* ************************************************************************** */ #include "libft.h" char *ft_strmap(char const *s, char (*f)(char)) { char *dest; int i; if (!s || !(dest = (char *)malloc((ft_strlen(s) + 1) * sizeof(char)))) return (NULL); i = 0; while (*s != '\0') dest[i++] = (*f)(*s++); dest[i] = '\0'; return (dest); }

41.535714

80

0.198624

c40cc5dae05abef08f82b701001989f60887aa8d

326

h

C

PrivateFrameworks/PassKitCore/PKMicaResizableView-Protocol.h

phatblat/macOSPrivateFrameworks

9047371eb80f925642c8a7c4f1e00095aec66044

[ "MIT" ]

17

2018-11-13T04:02:58.000Z

2022-01-20T09:27:13.000Z

PrivateFrameworks/PassKitUIFoundation/PKMicaResizableView-Protocol.h

phatblat/macOSPrivateFrameworks

9047371eb80f925642c8a7c4f1e00095aec66044

[ "MIT" ]

3

2018-04-06T02:02:27.000Z

2018-10-02T01:12:10.000Z

PrivateFrameworks/PassKitCore/PKMicaResizableView-Protocol.h

phatblat/macOSPrivateFrameworks

9047371eb80f925642c8a7c4f1e00095aec66044

[ "MIT" ]

1

2018-09-28T13:54:23.000Z

// // Generated by class-dump 3.5 (64 bit). // // class-dump is Copyright (C) 1997-1998, 2000-2001, 2004-2013 by Steve Nygard. // #import "NSObject.h" @protocol PKMicaResizableView <NSObject> - (struct CGSize)boundsSizeToMatchPointScale:(double)arg1; - (double)pointScaleToMatchBoundsSize:(struct CGSize)arg1; @end

23.285714

83

0.723926

b889a1ff9c41d3b7687320b59ec42b3400e89845

20,901

c

C

vendors/renesas/rx_driver_package/v125/r_bsp/mcu/rx72t/mcu_interrupts.c

nateglims/amazon-freertos

5cc32eb29d935f124101a3584c6d29aa1f5d687d

[ "MIT" ]

2,637

2017-11-29T18:41:48.000Z

2022-03-29T01:03:36.000Z

vendors/renesas/rx_driver_package/v125/r_bsp/mcu/rx72t/mcu_interrupts.c

nateglims/amazon-freertos

5cc32eb29d935f124101a3584c6d29aa1f5d687d

[ "MIT" ]

1,926

2017-11-29T21:42:02.000Z

2022-03-31T22:12:50.000Z

vendors/renesas/rx_driver_package/v125/r_bsp/mcu/rx72t/mcu_interrupts.c

nateglims/amazon-freertos

5cc32eb29d935f124101a3584c6d29aa1f5d687d

[ "MIT" ]

1,384

2017-11-29T19:04:27.000Z

2022-03-29T14:40:27.000Z

/*********************************************************************************************************************** * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all * applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of * this software. By using this software, you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * * Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** * File Name : mcu_interrupts.c * Description : This module is the control of the interrupt enable. ***********************************************************************************************************************/ /********************************************************************************************************************** * History : DD.MM.YYYY Version Description * : 31.10.2018 1.00 First Release * : 28.02.2019 2.00 Deleted the following functions. * (The following functions moved to the common file (r_bsp_interrupts.c).) * - bsp_interrupt_open * - bsp_interrupt_group_enable_disable * (And, changed the function name to bsp_gr_int_enable_disable.h.) * - R_BSP_InterruptWrite * - R_BSP_InterruptRead * - R_BSP_InterruptControl * Deleted the following definition. * (The following definition moved to the common file (r_bsp_common.h).) * - INTERNAL_NOT_USED(p) * Replaced the setting of IEN bit. * Added support for GNUC and ICCRX. * Fixed coding style. * Added support Group BE0 interrupts. * Modified the bsp_interrupt_group_enable_disable function. * Added the group_be0_handler_isr function. ***********************************************************************************************************************/ /*********************************************************************************************************************** Includes <System Includes> , "Project Includes" ***********************************************************************************************************************/ /* Access to r_bsp. */ #include "platform.h" /*********************************************************************************************************************** Macro definitions ***********************************************************************************************************************/ /* Let FPSW EV, EO, EZ, EU, EX=1 (FPU exceptions enabled.) */ #define BSP_PRV_FPU_EXCEPTIONS_ENABLE (0x00007C00) /*********************************************************************************************************************** Typedef definitions ***********************************************************************************************************************/ /*********************************************************************************************************************** Exported global variables (to be accessed by other files) ***********************************************************************************************************************/ /*********************************************************************************************************************** Private global variables and functions ***********************************************************************************************************************/ R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl0_handler_isr, VECT(ICU,GROUPBL0)) R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl1_handler_isr, VECT(ICU,GROUPBL1)) R_BSP_PRAGMA_STATIC_INTERRUPT(group_al0_handler_isr, VECT(ICU,GROUPAL0)) R_BSP_PRAGMA_STATIC_INTERRUPT(group_be0_handler_isr, VECT(ICU,GROUPBE0)) /*********************************************************************************************************************** * Function Name: bsp_interrupt_enable_disable * Description : Either enables or disables an interrupt. * Arguments : vector - * Which vector to enable or disable. * enable - * Whether to enable or disable the interrupt. * Return Value : BSP_INT_SUCCESS - * Interrupt enabled or disabled. * BSP_INT_ERR_UNSUPPORTED - * API does not support enabling/disabling for this vector. ***********************************************************************************************************************/ bsp_int_err_t bsp_interrupt_enable_disable (bsp_int_src_t vector, bool enable) { #ifdef __FPU uint32_t tmp_fpsw; #endif bsp_int_err_t err = BSP_INT_SUCCESS; switch (vector) { case (BSP_INT_SRC_BUS_ERROR): if (true == enable) { /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ /* Clear any pending interrupts */ IR(BSC,BUSERR) = 0; /* Make this the highest priority interrupt (adjust as necessary for your application */ IPR(BSC,BUSERR) = 0x0F; /* Enable the interrupt in the ICU*/ R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); /* Enable illegal address interrupt in the BSC */ BSC.BEREN.BIT.IGAEN = 1; /* Enable timeout detection enable. */ BSC.BEREN.BIT.TOEN = 1; } else { /* Disable the bus error interrupt. */ /* Disable the interrupt in the ICU*/ R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); /* Disable illegal address interrupt in the BSC */ BSC.BEREN.BIT.IGAEN = 0; /* Disable timeout detection enable. */ BSC.BEREN.BIT.TOEN = 0; } break; #ifdef __FPU case (BSP_INT_SRC_EXC_FPU): /* Get current FPSW. */ tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); if (true == enable) { /* Set the FPU exception flags. */ R_BSP_SET_FPSW((tmp_fpsw | (uint32_t)BSP_PRV_FPU_EXCEPTIONS_ENABLE)); } else { /* Clear only the FPU exception flags. */ R_BSP_SET_FPSW((tmp_fpsw & (uint32_t)~BSP_PRV_FPU_EXCEPTIONS_ENABLE)); } break; #endif case (BSP_INT_SRC_EXC_NMI_PIN): if (true == enable) { /* Enable NMI pin interrupt (cannot undo!) */ ICU.NMIER.BIT.NMIEN = 1; } else { /* NMI pin interrupts cannot be disabled after being enabled. */ err = BSP_INT_ERR_UNSUPPORTED; } break; default: err = BSP_INT_ERR_UNSUPPORTED; break; } return err; } /* End of function bsp_interrupt_enable_disable() */ /*********************************************************************************************************************** * Function Name: group_bl0_handler_isr * Description : Interrupt handler for Group BL0 interrupts. The way this code works is that for each possible interrupt * in this group the following will be performed: * 1) Test to see if an interrupt is requested for this source * 2) If an interrupt is requested then the registered callback is called (if one is registered) * NOTE: The interrupt request flag must be cleared in the peripheral. * Arguments : None * Return Value : None ***********************************************************************************************************************/ R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl0_handler_isr (void) { /* BL0 IS3 */ if (1 == ICU.GRPBL0.BIT.IS3) { /* BSP_INT_SRC_BL0_SCI1_ERI1 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_ERI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS2 */ if (1 == ICU.GRPBL0.BIT.IS2) { /* BSP_INT_SRC_BL0_SCI1_TEI1 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS11 */ if (1 == ICU.GRPBL0.BIT.IS11) { /* BSP_INT_SRC_BL0_SCI5_ERI5 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_ERI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS10 */ if (1 == ICU.GRPBL0.BIT.IS10) { /* BSP_INT_SRC_BL0_SCI5_TEI5 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_TEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS13 */ if (1 == ICU.GRPBL0.BIT.IS13) { /* BSP_INT_SRC_BL0_SCI6_ERI6 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_ERI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS12 */ if (1 == ICU.GRPBL0.BIT.IS12) { /* BSP_INT_SRC_BL0_SCI6_TEI6 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_TEI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS17 */ if (1 == ICU.GRPBL0.BIT.IS17) { /* BSP_INT_SRC_BL0_SCI12_ERI12 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_ERI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS16 */ if (1 == ICU.GRPBL0.BIT.IS16) { /* BSP_INT_SRC_BL0_SCI12_TEI12 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_TEI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS118 */ if (1 == ICU.GRPBL0.BIT.IS18) { /* BSP_INT_SRC_BL0_SCI12_SCIX0 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS19 */ if (1 == ICU.GRPBL0.BIT.IS19) { /* BSP_INT_SRC_BL0_SCI12_SCIX1 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS20 */ if (1 == ICU.GRPBL0.BIT.IS20) { /* BSP_INT_SRC_BL0_SCI12_SCIX2 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS21 */ if (1 == ICU.GRPBL0.BIT.IS21) { /* BSP_INT_SRC_BL0_SCI12_SCIX3 */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS26 */ if (1 == ICU.GRPBL0.BIT.IS26) { /* BSP_INT_SRC_BL0_CAC_FERRI */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_FERRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS27 */ if (1 == ICU.GRPBL0.BIT.IS27) { /* BSP_INT_SRC_BL0_CAC_MENDI */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_MENDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS28 */ if (1 == ICU.GRPBL0.BIT.IS28) { /* BSP_INT_SRC_BL0_CAC_OVFI */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_OVFI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL0 IS29 */ if (1 == ICU.GRPBL0.BIT.IS29) { /* BSP_INT_SRC_BL0_DOC_DOPCI */ R_BSP_InterruptControl(BSP_INT_SRC_BL0_DOC_DOPCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } } /* End of function group_bl0_handler_isr() */ /*********************************************************************************************************************** * Function Name: group_bl1_handler_isr * Description : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt * in this group the following will be performed: * 1) Test to see if an interrupt is requested for this source * 2) If an interrupt is requested then the registered callback is called (if one is registered) * NOTE: The interrupt request flag must be cleared in the peripheral. * Arguments : None * Return Value : None ***********************************************************************************************************************/ R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl1_handler_isr (void) { /* BL1 IS0 */ if (1 == ICU.GRPBL1.BIT.IS0) { /* BSP_INT_SRC_BL1_POEG_POEGGAI */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS1 */ if (1 == ICU.GRPBL1.BIT.IS1) { /* BSP_INT_SRC_BL1_POEG_POEGGBI */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS2 */ if (1 == ICU.GRPBL1.BIT.IS2) { /* BSP_INT_SRC_BL1_POEG_POEGGCI */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS3 */ if (1 == ICU.GRPBL1.BIT.IS3) { /* BSP_INT_SRC_BL1_POEG_POEGGDI */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS8 */ if (1 == ICU.GRPBL1.BIT.IS8) { /* BSP_INT_SRC_BL1_POE3_OEI5 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS9 */ if (1 == ICU.GRPBL1.BIT.IS9) { /* BSP_INT_SRC_BL1_POE3_OEI1 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS10 */ if (1 == ICU.GRPBL1.BIT.IS10) { /* BSP_INT_SRC_BL1_POE3_OEI2 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS11 */ if (1 == ICU.GRPBL1.BIT.IS11) { /* BSP_INT_SRC_BL1_POE3_OEI3 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS12 */ if (1 == ICU.GRPBL1.BIT.IS12) { /* BSP_INT_SRC_BL1_POE3_OEI4 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS14 */ if (1 == ICU.GRPBL1.BIT.IS14) { /* BSP_INT_SRC_BL1_RIIC0_EEI0 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_EEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS13 */ if (1 == ICU.GRPBL1.BIT.IS13) { /* BSP_INT_SRC_BL1_RIIC0_TEI0 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS18 */ if (1 == ICU.GRPBL1.BIT.IS18) { /* BSP_INT_SRC_BL1_S12AD2_S12CMPAI2 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD2_S12CMPAI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS19 */ if (1 == ICU.GRPBL1.BIT.IS19) { /* BSP_INT_SRC_BL1_S12AD2_S12CMPBI2 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD2_S12CMPBI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS20 */ if (1 == ICU.GRPBL1.BIT.IS20) { /* BSP_INT_SRC_BL1_S12AD0_S12CMPAI */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS21 */ if (1 == ICU.GRPBL1.BIT.IS21) { /* BSP_INT_SRC_BL1_S12AD0_S12CMPBI */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS22 */ if (1 == ICU.GRPBL1.BIT.IS22) { /* BSP_INT_SRC_BL1_S12AD1_S12CMPAI1 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS23 */ if (1 == ICU.GRPBL1.BIT.IS23) { /* BSP_INT_SRC_BL1_S12AD1_S12CMPBI1 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS25 */ if (1 == ICU.GRPBL1.BIT.IS25) { /* BSP_INT_SRC_BL1_SCI8_ERI8 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_SCI8_ERI8, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS24 */ if (1 == ICU.GRPBL1.BIT.IS24) { /* BSP_INT_SRC_BL1_SCI8_TEI8 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_SCI8_TEI8, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS27 */ if (1 == ICU.GRPBL1.BIT.IS27) { /* BSP_INT_SRC_BL1_SCI9_ERI9 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_SCI9_ERI9, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* BL1 IS26 */ if (1 == ICU.GRPBL1.BIT.IS26) { /* BSP_INT_SRC_BL1_SCI9_TEI9 */ R_BSP_InterruptControl(BSP_INT_SRC_BL1_SCI9_TEI9, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } } /* End of function group_bl1_handler_isr() */ /*********************************************************************************************************************** * Function Name: group_al0_handler_isr * Description : Interrupt handler for Group AL0 interrupts. The way this code works is that for each possible interrupt * in this group the following will be performed: * 1) Test to see if an interrupt is requested for this source * 2) If an interrupt is requested then the registered callback is called (if one is registered) * NOTE: The interrupt request flag must be cleared in the peripheral. * Arguments : None * Return Value : None ***********************************************************************************************************************/ R_BSP_ATTRIB_STATIC_INTERRUPT void group_al0_handler_isr (void) { /* AL0 IS13 */ if (1 == ICU.GRPAL0.BIT.IS13) { /* BSP_INT_SRC_AL0_SCI11_ERI11 */ R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI11_ERI11, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* AL0 IS12 */ if (1 == ICU.GRPAL0.BIT.IS12) { /* BSP_INT_SRC_AL0_SCI11_TEI11 */ R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI11_TEI11, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* AL0 IS17 */ if (1 == ICU.GRPAL0.BIT.IS17) { /* BSP_INT_SRC_AL0_RSPI0_SPEI0 */ R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } /* AL0 IS16 */ if (1 == ICU.GRPAL0.BIT.IS16) { /* BSP_INT_SRC_AL0_RSPI0_SPII0 */ R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPII0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } } /* End of function group_al0_handler_isr() */ /*********************************************************************************************************************** * Function Name: group_be0_handler_isr * Description : Interrupt handler for Group BE0 interrupts. The way this code works is that for each possible interrupt * in this group the following will be performed: * 1) Test to see if an interrupt is requested for this source * 2) If an interrupt is requested then the registered callback is called (if one is registered) * NOTE: The interrupt request flag must be cleared in the peripheral. * Arguments : None * Return Value : None ***********************************************************************************************************************/ R_BSP_ATTRIB_STATIC_INTERRUPT void group_be0_handler_isr (void) { /* BE0 IS0 */ if (1 == ICU.GRPBE0.BIT.IS0) { /* Clear the interrupt status flag. */ ICU.GCRBE0.BIT.CLR0 = 1; /* BSP_INT_SRC_BE0_CAN0_ERS0 */ R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN0_ERS0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); } } /* End of function group_be0_handler_isr() */

40.505814

120

0.547916

b488cd3f21065070deec359a0e5f6ef6c1f06746

799

h

C

example/ios/ScanKitFrameWork.framework/Headers/HmsScanFormat.h

zgr5566/flutter_customized_scan

b9c5d7b930532b1b235f48d7a0061b8eeba743ac

[ "MIT" ]

2

2021-04-16T07:09:49.000Z

2021-04-29T09:21:16.000Z

example/ios/ScanKitFrameWork.framework/Headers/HmsScanFormat.h

zgr5566/flutter_customized_scan

b9c5d7b930532b1b235f48d7a0061b8eeba743ac

[ "MIT" ]

2

2020-10-12T01:16:09.000Z

2021-02-04T07:28:18.000Z

example/ios/ScanKitFrameWork.framework/Headers/HmsScanFormat.h

zgr5566/flutter_customized_scan

b9c5d7b930532b1b235f48d7a0061b8eeba743ac

[ "MIT" ]

1

2021-04-16T07:09:53.000Z

// // // Copyright (c) Huawei Technologies Co., Ltd. 2020-2028. All rights reserved. // #import <Foundation/Foundation.h> typedef NS_ENUM(int, HMSScanFormatTypeCode) { AZTEC = 1 << 0, CODABAR = 1 << 1, CODE_39 = 1 << 2, CODE_93 = 1 << 3, CODE_128 = 1 << 4, DATA_MATRIX = 1 << 5, EAN_8 = 1 << 6, EAN_13 = 1 << 7, ITF = 1 << 8, PDF_417 = 1 << 9, QR_CODE = 1 << 10, UPC_A = 1 << 11, UPC_E = 1 << 12, ALL = (1<<13)-1 }; @interface HmsScanOptions : NSObject @property (nonatomic, assign) unsigned int scanFormatType; @property (nonatomic, assign) BOOL photoMode; - (instancetype)initWithScanFormatType:(unsigned int)type Photo:(BOOL)photo; @end

24.212121

79

0.529412

3592079c5c8f4e741d4fd9ea14fc9fe741e7b8bf

6,796

h

C

lib/gft/include/gft_bzlib.h

ademirtc/bandeirantes

2dfc2ceadb555c1c40991520f450745bedf88c77

[ "MIT" ]

null

lib/gft/include/gft_bzlib.h

ademirtc/bandeirantes

2dfc2ceadb555c1c40991520f450745bedf88c77

[ "MIT" ]

null

lib/gft/include/gft_bzlib.h

ademirtc/bandeirantes

2dfc2ceadb555c1c40991520f450745bedf88c77

[ "MIT" ]

null

/*-------------------------------------------------------------*/ /*--- Public header file for the library. ---*/ /*--- bzlib.h ---*/ /*-------------------------------------------------------------*/ /* ------------------------------------------------------------------ This file is part of bzip2/libbzip2, a program and library for lossless, block-sorting data compression. bzip2/libbzip2 version 1.0.4 of 20 December 2006 Copyright (C) 1996-2006 Julian Seward <jseward@bzip.org> Please read the WARNING, DISCLAIMER and PATENTS sections in the README file. This program is released under the terms of the license contained in the file LICENSE. ------------------------------------------------------------------ */ #ifndef _gft_BZLIB_H #define _gft_BZLIB_H #ifdef __cplusplus extern "C" { #endif #define gft_BZ_RUN 0 #define gft_BZ_FLUSH 1 #define gft_BZ_FINISH 2 #define gft_BZ_OK 0 #define gft_BZ_RUN_OK 1 #define gft_BZ_FLUSH_OK 2 #define gft_BZ_FINISH_OK 3 #define gft_BZ_STREAM_END 4 #define gft_BZ_SEQUENCE_ERROR (-1) #define gft_BZ_PARAM_ERROR (-2) #define gft_BZ_MEM_ERROR (-3) #define gft_BZ_DATA_ERROR (-4) #define gft_BZ_DATA_ERROR_MAGIC (-5) #define gft_BZ_IO_ERROR (-6) #define gft_BZ_UNEXPECTED_EOF (-7) #define gft_BZ_OUTBUFF_FULL (-8) #define gft_BZ_CONFIG_ERROR (-9) typedef struct { char *next_in; unsigned int avail_in; unsigned int total_in_lo32; unsigned int total_in_hi32; char *next_out; unsigned int avail_out; unsigned int total_out_lo32; unsigned int total_out_hi32; void *state; void *(*bzalloc)(void *,int,int); void (*bzfree)(void *,void *); void *opaque; } bz_stream; #ifndef gft_BZ_IMPORT #define gft_BZ_EXPORT #endif #ifndef gft_BZ_NO_STDIO /* Need a definitition for FILE */ #include <stdio.h> #endif //#ifdef _WIN32 //# include <windows.h> //# ifdef small // /* windows.h define small to char */ //# undef small //# endif //# ifdef gft_BZ_EXPORT //# define gft_BZ_API(func) WINAPI func //# define gft_BZ_EXTERN extern //# else // /* import windows dll dynamically */ //# define gft_BZ_API(func) (WINAPI * func) //# define gft_BZ_EXTERN //# endif //#else //# define gft_BZ_API(func) func //# define gft_BZ_EXTERN extern //#endif # define gft_BZ_API(func) func # define gft_BZ_EXTERN extern /*-- Core (low-level) library functions --*/ gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzCompressInit) ( bz_stream* strm, int blockSize100k, int verbosity, int workFactor ); gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzCompress) ( bz_stream* strm, int action ); gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzCompressEnd) ( bz_stream* strm ); gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzDecompressInit) ( bz_stream *strm, int verbosity, int small ); gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzDecompress) ( bz_stream* strm ); gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzDecompressEnd) ( bz_stream *strm ); /*-- High(er) level library functions --*/ #ifndef gft_BZ_NO_STDIO #define gft_BZ_MAX_UNUSED 5000 typedef void gft_BZFILE; gft_BZ_EXTERN gft_BZFILE* gft_BZ_API(gft_BZ2_bzReadOpen) ( int* bzerror, FILE* f, int verbosity, int small, void* unused, int nUnused ); gft_BZ_EXTERN void gft_BZ_API(gft_BZ2_bzReadClose) ( int* bzerror, gft_BZFILE* b ); gft_BZ_EXTERN void gft_BZ_API(gft_BZ2_bzReadGetUnused) ( int* bzerror, gft_BZFILE* b, void** unused, int* nUnused ); gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzRead) ( int* bzerror, gft_BZFILE* b, void* buf, int len ); gft_BZ_EXTERN gft_BZFILE* gft_BZ_API(gft_BZ2_bzWriteOpen) ( int* bzerror, FILE* f, int blockSize100k, int verbosity, int workFactor ); gft_BZ_EXTERN void gft_BZ_API(gft_BZ2_bzWrite) ( int* bzerror, gft_BZFILE* b, void* buf, int len ); gft_BZ_EXTERN void gft_BZ_API(gft_BZ2_bzWriteClose) ( int* bzerror, gft_BZFILE* b, int abandon, unsigned int* nbytes_in, unsigned int* nbytes_out ); gft_BZ_EXTERN void gft_BZ_API(gft_BZ2_bzWriteClose64) ( int* bzerror, gft_BZFILE* b, int abandon, unsigned int* nbytes_in_lo32, unsigned int* nbytes_in_hi32, unsigned int* nbytes_out_lo32, unsigned int* nbytes_out_hi32 ); #endif /*-- Utility functions --*/ gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzBuffToBuffCompress) ( char* dest, unsigned int* destLen, char* source, unsigned int sourceLen, int blockSize100k, int verbosity, int workFactor ); gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzBuffToBuffDecompress) ( char* dest, unsigned int* destLen, char* source, unsigned int sourceLen, int small, int verbosity ); /*-- Code contributed by Yoshioka Tsuneo (tsuneo@rr.iij4u.or.jp) to support better zlib compatibility. This code is not _officially_ part of libbzip2 (yet); I haven't tested it, documented it, or considered the threading-safeness of it. If this code breaks, please contact both Yoshioka and me. --*/ gft_BZ_EXTERN const char * gft_BZ_API(gft_BZ2_bzlibVersion) ( void ); #ifndef gft_BZ_NO_STDIO gft_BZ_EXTERN gft_BZFILE * gft_BZ_API(gft_BZ2_bzopen) ( const char *path, const char *mode ); gft_BZ_EXTERN gft_BZFILE * gft_BZ_API(gft_BZ2_bzdopen) ( int fd, const char *mode ); gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzread) ( gft_BZFILE* b, void* buf, int len ); gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzwrite) ( gft_BZFILE* b, void* buf, int len ); gft_BZ_EXTERN int gft_BZ_API(gft_BZ2_bzflush) ( gft_BZFILE* b ); gft_BZ_EXTERN void gft_BZ_API(gft_BZ2_bzclose) ( gft_BZFILE* b ); gft_BZ_EXTERN const char * gft_BZ_API(gft_BZ2_bzerror) ( gft_BZFILE *b, int *errnum ); #endif #ifdef __cplusplus } #endif #endif /*-------------------------------------------------------------*/ /*--- end bzlib.h ---*/ /*-------------------------------------------------------------*/

23.845614

72

0.581519

98b70489fa21f6ea713cd6cc0d241f3e4e22be87

580

h

C

src/tools/cameraProj.h

TheSpyGeek/Green-Engine

cdfbd55410ee5d90cbeb51390f2ae9a4e84f4792

[ "MIT" ]

1

2021-07-04T12:33:49.000Z

src/tools/cameraProj.h

TheSpyGeek/Green-Engine

cdfbd55410ee5d90cbeb51390f2ae9a4e84f4792

[ "MIT" ]

2

2019-10-29T11:46:09.000Z

2019-11-21T20:44:02.000Z

src/tools/cameraProj.h

TheSpyGeek/Green-Engine

cdfbd55410ee5d90cbeb51390f2ae9a4e84f4792

[ "MIT" ]

null

#ifndef CAMERA_PROJECTIVE_H #define CAMERA_PROJECTIVE_H #include "camera.h" #include <string> class CameraProj : public Camera { public: CameraProj(int id, std::string name = "Camera Projective", glm::vec3 pos = glm::vec3(0.0,0.0,5.0), glm::vec3 u = glm::vec3(0.0,1.0,0.0), glm::vec3 direction = glm::vec3(0.0,0.0,0.0), float fov = 45.f, float n = 0.1f, float f = 100.f); virtual glm::mat4 getProj(float aspect = 16./9.); virtual void createUI(char *ID); protected: float fovy; float near; float far; }; #endif

20

242

0.615517

722aa22c448dbb402ce0ac861f7f61d3daafb72b

1,217

h

C

SystemTimer.h

NDMDevel/LinearChopperFirmware

aff50433e69a8d1624c8d51c8012c4fe37890f54

[ "MIT" ]

null

SystemTimer.h

NDMDevel/LinearChopperFirmware

aff50433e69a8d1624c8d51c8012c4fe37890f54

[ "MIT" ]

null

SystemTimer.h

NDMDevel/LinearChopperFirmware

aff50433e69a8d1624c8d51c8012c4fe37890f54

[ "MIT" ]

null

/* * File: SystemTimer.h * Author: Damian * * Created on December 12, 2019, 8:39 PM */ #ifndef SYSTEMTIMER_H #define SYSTEMTIMER_H #include <stdint.h> extern uint8_t system_counter; extern uint8_t system_seconds; extern uint8_t system_minutes; //this timer increments system_counter with an interval of 100ms #define TIMER_RESET(T) T = ((uint8_t)((uint8_t)~system_counter)+((uint8_t)1)) #define TIMER_ELAPSE(T,TE) ((uint8_t)(system_counter + T) >= ((uint8_t)TE)) //these macros must be used for counting seconds: #define TIMER_RESET_SEC(T) T = ((uint8_t)((uint8_t)~system_seconds)+((uint8_t)1)) #define TIMER_ELAPSE_SEC(T,TE) ((uint8_t)(system_seconds + T) >= ((uint8_t)TE)) //these macros must be used for counting minutes: #define TIMER_RESET_MIN(T) T = ((uint8_t)((uint8_t)~system_minutes)+((uint8_t)1)) #define TIMER_ELAPSE_MIN(T,TE) ((uint8_t)(system_minutes + T) >= ((uint8_t)TE)) //this macros must be used only with TIMER_RESET/TIMER_ELAPSE 100ms period #define t200ms 2 #define t300ms 3 #define t400ms 4 #define t500ms 5 #define t1s 10 #define t2s 20 #define t5s 50 #define t10s 100 void TMR1_SystemTimer_ISR(void); #endif /* SYSTEMTIMER_H */

27.659091

82

0.709942

3785dc8c87f6db8959396afa8b0bad13b25e3ce4

531,814

h

C

include/APE_DEVICE.h

meklort/bcm5719-fw

b9cfab4a0c3b839b520735e4a183ca83d5e2f124

[ "BSD-3-Clause" ]

45

2019-04-11T15:03:34.000Z

2022-03-03T20:42:33.000Z

include/APE_DEVICE.h

meklort/bcm5719-fw

b9cfab4a0c3b839b520735e4a183ca83d5e2f124

[ "BSD-3-Clause" ]

16

2020-01-15T04:09:41.000Z

2022-02-25T15:45:34.000Z

include/APE_DEVICE.h

meklort/bcm5719-fw

b9cfab4a0c3b839b520735e4a183ca83d5e2f124

[ "BSD-3-Clause" ]

10

2019-05-03T01:19:52.000Z

2022-03-18T03:34:49.000Z

//////////////////////////////////////////////////////////////////////////////// /// /// @file APE_DEVICE.h /// /// @project ape /// /// @brief APE_DEVICE /// //////////////////////////////////////////////////////////////////////////////// /// //////////////////////////////////////////////////////////////////////////////// /// /// @copyright Copyright (c) 2021, Evan Lojewski /// @cond /// /// All rights reserved. /// /// Redistribution and use in source and binary forms, with or without /// modification, are permitted provided that the following conditions are met: /// 1. Redistributions of source code must retain the above copyright notice, /// this list of conditions and the following disclaimer. /// 2. Redistributions in binary form must reproduce the above copyright notice, /// this list of conditions and the following disclaimer in the documentation /// and/or other materials provided with the distribution. /// 3. Neither the name of the <organization> nor the /// names of its contributors may be used to endorse or promote products /// derived from this software without specific prior written permission. /// //////////////////////////////////////////////////////////////////////////////// /// /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" /// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE /// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE /// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE /// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR /// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF /// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS /// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN /// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE /// POSSIBILITY OF SUCH DAMAGE. /// @endcond //////////////////////////////////////////////////////////////////////////////// /** @defgroup APE_DEVICE_H APE_DEVICE */ /** @addtogroup APE_DEVICE_H * @{ */ #ifndef APE_DEVICE_H #define APE_DEVICE_H #include <types.h> #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ void init_APE_DEVICE_sim(void* base); void init_APE_DEVICE(void); #include <CXXRegister.h> typedef CXXRegister<uint8_t, 0, 8> APE_DEVICE_H_uint8_t; typedef CXXRegister<uint16_t, 0, 16> APE_DEVICE_H_uint16_t; typedef CXXRegister<uint32_t, 0, 32> APE_DEVICE_H_uint32_t; #define APE_DEVICE_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> #define APE_DEVICE_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> #define APE_DEVICE_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> #define register_container struct #define volatile #define BITFIELD_BEGIN(__type__, __name__) struct { #define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; #define BITFIELD_END(__type__, __name__) } __name__; #else /* Firmware Data types */ typedef uint8_t APE_DEVICE_H_uint8_t; typedef uint16_t APE_DEVICE_H_uint16_t; typedef uint32_t APE_DEVICE_H_uint32_t; #define register_container union #define BITFIELD_BEGIN(__type__, __name__) struct { #define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; #define BITFIELD_END(__type__, __name__) } __name__; #endif /* !CXX_SIMULATOR */ #define REG_DEVICE_BASE ((volatile void*)0xa0040000) /* Device Registers, function 0 */ #define REG_DEVICE_SIZE (sizeof(DEVICE_t)) #define REG_DEVICE_MISCELLANEOUS_HOST_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa0040068) /* */ #define DEVICE_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x1u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x2u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x4u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x8u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 4u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x10u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 5u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x20u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 5u) & 0x20u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x40u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__reg__) (((__reg__) & 0x40) >> 6u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__val__) (((__val__) << 6u) & 0x40u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x80u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__reg__) (((__reg__) & 0x80) >> 7u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__val__) (((__val__) << 7u) & 0x80u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x100u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__val__) (((__val__) << 8u) & 0x100u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x200u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__reg__) (((__reg__) & 0x200) >> 9u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__val__) (((__val__) << 9u) & 0x200u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x400u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__reg__) (((__reg__) & 0x400) >> 10u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__val__) (((__val__) << 10u) & 0x400u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x800u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__reg__) (((__reg__) & 0x800) >> 11u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__val__) (((__val__) << 11u) & 0x800u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x1000u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__reg__) (((__reg__) & 0x1000) >> 12u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__val__) (((__val__) << 12u) & 0x1000u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x2000u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__reg__) (((__reg__) & 0x2000) >> 13u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__val__) (((__val__) << 13u) & 0x2000u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x4000u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__reg__) (((__reg__) & 0x4000) >> 14u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__val__) (((__val__) << 14u) & 0x4000u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x8000u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__reg__) (((__reg__) & 0x8000) >> 15u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__val__) (((__val__) << 15u) & 0x8000u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_SHIFT 16u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_MASK 0xff0000u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__reg__) (((__reg__) & 0xff0000) >> 16u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__val__) (((__val__) << 16u) & 0xff0000u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_0 0x0u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_1 0x1u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_2 0x2u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_SHIFT 24u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_MASK 0xf000000u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__reg__) (((__reg__) & 0xf000000) >> 24u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__val__) (((__val__) << 24u) & 0xf000000u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_A 0x0u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_B 0x1u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_C 0x2u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 28u #define DEVICE_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xf0000000u #define GET_DEVICE_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__reg__) (((__reg__) & 0xf0000000) >> 28u) #define SET_DEVICE_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__val__) (((__val__) << 28u) & 0xf0000000u) #define DEVICE_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_NEW_PRODUCT_MAPPING 0xfu /** @brief Register definition for @ref DEVICE_t.MiscellaneousHostControl. */ typedef register_container RegDEVICEMiscellaneousHostControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Setting this bit will clear interrupt as long as the mask interrupt bit is not set. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClearInterrupt, 0, 1) /** @brief Setting this bit will mask future interrupt events from being generated. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MaskInterrupt, 1, 1) /** @brief Set this bit to enable endian byte swapping when accessing through PCIE target interface. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableEndianByteSwap, 2, 1) /** @brief Set this bit to enable endian word swapping when accessing through PCIE target interface. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableEndianWordSwap, 3, 1) /** @brief Set this bit to enable PCI state register read/ write capability, otherwise the register is read only. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnablePCIStateRegisterRead_DIV_WriteCapability, 4, 1) /** @brief Set this bit enable clock control register read/ write capability, otherwise, the clock control register is read only. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableClockControlRegisterRead_DIV_WriteCapability, 5, 1) /** @brief Set this bit to enable word swapping when accessing registers through the PCI target device. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableRegisterWordSwap, 6, 1) /** @brief Set this bit to enable indirect addressing mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableIndirectAccess, 7, 1) /** @brief When set, the interrupt is masked. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MaskInterruptMode, 8, 1) /** @brief When set, an unique 8-bit tag value will be inserted into the Status block status tag. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTaggedStatusMode, 9, 1) /** @brief Set this bit to enable RCB check. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RCBCheck, 10, 1) /** @brief Set this bit to enable the interrupt check. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InterruptCheck, 11, 1) /** @brief Set this bit to enable the byte enable rule check. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ByteEnableRuleCheck, 12, 1) /** @brief Set this bit to enable crossing 4 KB boundary check. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BoundaryCheck, 13, 1) /** @brief Set this bit to enable log header due to overflow. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LogHeaderOverflow, 14, 1) /** @brief Set this bit to enable TLP minor error tolerance (ATTR/TC/LOCK command). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTLPMinorErrorTolerance, 15, 1) /** @brief Metal Rev Number */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MetalRevID, 16, 8) /** @brief External All Layer Revision ID. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AllLayerID, 24, 4) /** @brief Product ID. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ProductID, 28, 4) #elif defined(__BIG_ENDIAN__) /** @brief Product ID. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ProductID, 28, 4) /** @brief External All Layer Revision ID. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AllLayerID, 24, 4) /** @brief Metal Rev Number */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MetalRevID, 16, 8) /** @brief Set this bit to enable TLP minor error tolerance (ATTR/TC/LOCK command). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTLPMinorErrorTolerance, 15, 1) /** @brief Set this bit to enable log header due to overflow. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LogHeaderOverflow, 14, 1) /** @brief Set this bit to enable crossing 4 KB boundary check. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BoundaryCheck, 13, 1) /** @brief Set this bit to enable the byte enable rule check. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ByteEnableRuleCheck, 12, 1) /** @brief Set this bit to enable the interrupt check. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InterruptCheck, 11, 1) /** @brief Set this bit to enable RCB check. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RCBCheck, 10, 1) /** @brief When set, an unique 8-bit tag value will be inserted into the Status block status tag. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTaggedStatusMode, 9, 1) /** @brief When set, the interrupt is masked. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MaskInterruptMode, 8, 1) /** @brief Set this bit to enable indirect addressing mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableIndirectAccess, 7, 1) /** @brief Set this bit to enable word swapping when accessing registers through the PCI target device. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableRegisterWordSwap, 6, 1) /** @brief Set this bit enable clock control register read/ write capability, otherwise, the clock control register is read only. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableClockControlRegisterRead_DIV_WriteCapability, 5, 1) /** @brief Set this bit to enable PCI state register read/ write capability, otherwise the register is read only. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnablePCIStateRegisterRead_DIV_WriteCapability, 4, 1) /** @brief Set this bit to enable endian word swapping when accessing through PCIE target interface. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableEndianWordSwap, 3, 1) /** @brief Set this bit to enable endian byte swapping when accessing through PCIE target interface. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableEndianByteSwap, 2, 1) /** @brief Setting this bit will mask future interrupt events from being generated. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MaskInterrupt, 1, 1) /** @brief Setting this bit will clear interrupt as long as the mask interrupt bit is not set. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClearInterrupt, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "MiscellaneousHostControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEMiscellaneousHostControl_t() { /** @brief constructor for @ref DEVICE_t.MiscellaneousHostControl. */ r32.setName("MiscellaneousHostControl"); bits.ClearInterrupt.setBaseRegister(&r32); bits.ClearInterrupt.setName("ClearInterrupt"); bits.MaskInterrupt.setBaseRegister(&r32); bits.MaskInterrupt.setName("MaskInterrupt"); bits.EnableEndianByteSwap.setBaseRegister(&r32); bits.EnableEndianByteSwap.setName("EnableEndianByteSwap"); bits.EnableEndianWordSwap.setBaseRegister(&r32); bits.EnableEndianWordSwap.setName("EnableEndianWordSwap"); bits.EnablePCIStateRegisterRead_DIV_WriteCapability.setBaseRegister(&r32); bits.EnablePCIStateRegisterRead_DIV_WriteCapability.setName("EnablePCIStateRegisterRead_DIV_WriteCapability"); bits.EnableClockControlRegisterRead_DIV_WriteCapability.setBaseRegister(&r32); bits.EnableClockControlRegisterRead_DIV_WriteCapability.setName("EnableClockControlRegisterRead_DIV_WriteCapability"); bits.EnableRegisterWordSwap.setBaseRegister(&r32); bits.EnableRegisterWordSwap.setName("EnableRegisterWordSwap"); bits.EnableIndirectAccess.setBaseRegister(&r32); bits.EnableIndirectAccess.setName("EnableIndirectAccess"); bits.MaskInterruptMode.setBaseRegister(&r32); bits.MaskInterruptMode.setName("MaskInterruptMode"); bits.EnableTaggedStatusMode.setBaseRegister(&r32); bits.EnableTaggedStatusMode.setName("EnableTaggedStatusMode"); bits.RCBCheck.setBaseRegister(&r32); bits.RCBCheck.setName("RCBCheck"); bits.InterruptCheck.setBaseRegister(&r32); bits.InterruptCheck.setName("InterruptCheck"); bits.ByteEnableRuleCheck.setBaseRegister(&r32); bits.ByteEnableRuleCheck.setName("ByteEnableRuleCheck"); bits.BoundaryCheck.setBaseRegister(&r32); bits.BoundaryCheck.setName("BoundaryCheck"); bits.LogHeaderOverflow.setBaseRegister(&r32); bits.LogHeaderOverflow.setName("LogHeaderOverflow"); bits.EnableTLPMinorErrorTolerance.setBaseRegister(&r32); bits.EnableTLPMinorErrorTolerance.setName("EnableTLPMinorErrorTolerance"); bits.MetalRevID.setBaseRegister(&r32); bits.MetalRevID.setName("MetalRevID"); bits.MetalRevID.addEnum("0", 0x0); bits.MetalRevID.addEnum("1", 0x1); bits.MetalRevID.addEnum("2", 0x2); bits.AllLayerID.setBaseRegister(&r32); bits.AllLayerID.setName("AllLayerID"); bits.AllLayerID.addEnum("A", 0x0); bits.AllLayerID.addEnum("B", 0x1); bits.AllLayerID.addEnum("C", 0x2); bits.ProductID.setBaseRegister(&r32); bits.ProductID.setName("ProductID"); bits.ProductID.addEnum("New Product Mapping", 0xf); } RegDEVICEMiscellaneousHostControl_t& operator=(const RegDEVICEMiscellaneousHostControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEMiscellaneousHostControl_t; #define REG_DEVICE_PCI_STATE ((volatile APE_DEVICE_H_uint32_t*)0xa0040070) /* */ #define DEVICE_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5u #define DEVICE_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x20u #define GET_DEVICE_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__val__) (((__val__) << 5u) & 0x20u) #define DEVICE_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6u #define DEVICE_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x40u #define GET_DEVICE_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__reg__) (((__reg__) & 0x40) >> 6u) #define SET_DEVICE_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__val__) (((__val__) << 6u) & 0x40u) #define DEVICE_PCI_STATE_VPD_AVAILABLE_SHIFT 7u #define DEVICE_PCI_STATE_VPD_AVAILABLE_MASK 0x80u #define GET_DEVICE_PCI_STATE_VPD_AVAILABLE(__reg__) (((__reg__) & 0x80) >> 7u) #define SET_DEVICE_PCI_STATE_VPD_AVAILABLE(__val__) (((__val__) << 7u) & 0x80u) #define DEVICE_PCI_STATE_FLAT_VIEW_SHIFT 8u #define DEVICE_PCI_STATE_FLAT_VIEW_MASK 0x100u #define GET_DEVICE_PCI_STATE_FLAT_VIEW(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_PCI_STATE_FLAT_VIEW(__val__) (((__val__) << 8u) & 0x100u) #define DEVICE_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9u #define DEVICE_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0xe00u #define GET_DEVICE_PCI_STATE_MAX_PCI_TARGET_RETRY(__reg__) (((__reg__) & 0xe00) >> 9u) #define SET_DEVICE_PCI_STATE_MAX_PCI_TARGET_RETRY(__val__) (((__val__) << 9u) & 0xe00u) #define DEVICE_PCI_STATE_CONFIG_RETRY_SHIFT 15u #define DEVICE_PCI_STATE_CONFIG_RETRY_MASK 0x8000u #define GET_DEVICE_PCI_STATE_CONFIG_RETRY(__reg__) (((__reg__) & 0x8000) >> 15u) #define SET_DEVICE_PCI_STATE_CONFIG_RETRY(__val__) (((__val__) << 15u) & 0x8000u) #define DEVICE_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_SHIFT 16u #define DEVICE_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_MASK 0x10000u #define GET_DEVICE_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) #define SET_DEVICE_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) #define DEVICE_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_SHIFT 17u #define DEVICE_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_MASK 0x20000u #define GET_DEVICE_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__reg__) (((__reg__) & 0x20000) >> 17u) #define SET_DEVICE_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__val__) (((__val__) << 17u) & 0x20000u) #define DEVICE_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_SHIFT 18u #define DEVICE_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_MASK 0x40000u #define GET_DEVICE_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) #define SET_DEVICE_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) #define DEVICE_PCI_STATE_GENERATE_RESET_PLUS_SHIFT 19u #define DEVICE_PCI_STATE_GENERATE_RESET_PLUS_MASK 0x80000u #define GET_DEVICE_PCI_STATE_GENERATE_RESET_PLUS(__reg__) (((__reg__) & 0x80000) >> 19u) #define SET_DEVICE_PCI_STATE_GENERATE_RESET_PLUS(__val__) (((__val__) << 19u) & 0x80000u) /** @brief Register definition for @ref DEVICE_t.PciState. */ typedef register_container RegDEVICEPciState_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_0, 0, 5) /** @brief Enable PCI ROM base address register to be visible to the PCI host */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIExpansionROMDesired, 5, 1) /** @brief Force PCI Retry for accesses to Expansion ROM region if enabled */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIExpansionROMRetry, 6, 1) /** @brief This bit reads as 1 if the VPD region of the NVRAM can be accessed by the host */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, VPDAvailable, 7, 1) /** @brief Asserted if the Base Address register presents a 32 MB PCI Address map flat view, otherwise, indicates a 64 KB PCI Address map in standard view */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlatView, 8, 1) /** @brief Indicates the number of PCI clock cycles before Retry occurs, in multiple of 8. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MaxPCITargetRetry, 9, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_14_12, 12, 3) /** @brief When asserted, forces all config access to be retried. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ConfigRetry, 15, 1) /** @brief When this bit is set the APE control registers may be written. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEControlRegisterWriteEnable, 16, 1) /** @brief When this bit is set the APE shared memory region may be written. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APESharedMemoryWriteEnable, 17, 1) /** @brief When this bit is set the APE program space may be written. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEProgramSpaceWriteEnable, 18, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GenerateResetPlus, 19, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_20, 20, 12) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_20, 20, 12) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GenerateResetPlus, 19, 1) /** @brief When this bit is set the APE program space may be written. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEProgramSpaceWriteEnable, 18, 1) /** @brief When this bit is set the APE shared memory region may be written. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APESharedMemoryWriteEnable, 17, 1) /** @brief When this bit is set the APE control registers may be written. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEControlRegisterWriteEnable, 16, 1) /** @brief When asserted, forces all config access to be retried. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ConfigRetry, 15, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_14_12, 12, 3) /** @brief Indicates the number of PCI clock cycles before Retry occurs, in multiple of 8. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MaxPCITargetRetry, 9, 3) /** @brief Asserted if the Base Address register presents a 32 MB PCI Address map flat view, otherwise, indicates a 64 KB PCI Address map in standard view */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlatView, 8, 1) /** @brief This bit reads as 1 if the VPD region of the NVRAM can be accessed by the host */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, VPDAvailable, 7, 1) /** @brief Force PCI Retry for accesses to Expansion ROM region if enabled */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIExpansionROMRetry, 6, 1) /** @brief Enable PCI ROM base address register to be visible to the PCI host */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIExpansionROMDesired, 5, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_0, 0, 5) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciState"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciState_t() { /** @brief constructor for @ref DEVICE_t.PciState. */ r32.setName("PciState"); bits.PCIExpansionROMDesired.setBaseRegister(&r32); bits.PCIExpansionROMDesired.setName("PCIExpansionROMDesired"); bits.PCIExpansionROMRetry.setBaseRegister(&r32); bits.PCIExpansionROMRetry.setName("PCIExpansionROMRetry"); bits.VPDAvailable.setBaseRegister(&r32); bits.VPDAvailable.setName("VPDAvailable"); bits.FlatView.setBaseRegister(&r32); bits.FlatView.setName("FlatView"); bits.MaxPCITargetRetry.setBaseRegister(&r32); bits.MaxPCITargetRetry.setName("MaxPCITargetRetry"); bits.ConfigRetry.setBaseRegister(&r32); bits.ConfigRetry.setName("ConfigRetry"); bits.APEControlRegisterWriteEnable.setBaseRegister(&r32); bits.APEControlRegisterWriteEnable.setName("APEControlRegisterWriteEnable"); bits.APESharedMemoryWriteEnable.setBaseRegister(&r32); bits.APESharedMemoryWriteEnable.setName("APESharedMemoryWriteEnable"); bits.APEProgramSpaceWriteEnable.setBaseRegister(&r32); bits.APEProgramSpaceWriteEnable.setName("APEProgramSpaceWriteEnable"); bits.GenerateResetPlus.setBaseRegister(&r32); bits.GenerateResetPlus.setName("GenerateResetPlus"); } RegDEVICEPciState_t& operator=(const RegDEVICEPciState_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciState_t; #define REG_DEVICE_REGISTER_BASE ((volatile APE_DEVICE_H_uint32_t*)0xa0040078) /* Local controller memory address of a register than can be written or read by writing to the register data register. */ /** @brief Register definition for @ref DEVICE_t.RegisterBase. */ typedef register_container RegDEVICERegisterBase_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RegisterBase"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERegisterBase_t() { /** @brief constructor for @ref DEVICE_t.RegisterBase. */ r32.setName("RegisterBase"); } RegDEVICERegisterBase_t& operator=(const RegDEVICERegisterBase_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERegisterBase_t; #define REG_DEVICE_MEMORY_BASE ((volatile APE_DEVICE_H_uint32_t*)0xa004007c) /* Local controller memory address of the NIC memory region that can be accessed via Memory Window data register. */ /** @brief Register definition for @ref DEVICE_t.MemoryBase. */ typedef register_container RegDEVICEMemoryBase_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "MemoryBase"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEMemoryBase_t() { /** @brief constructor for @ref DEVICE_t.MemoryBase. */ r32.setName("MemoryBase"); } RegDEVICEMemoryBase_t& operator=(const RegDEVICEMemoryBase_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEMemoryBase_t; #define REG_DEVICE_REGISTER_DATA ((volatile APE_DEVICE_H_uint32_t*)0xa0040080) /* Register Data at the location pointed by the Register Base Register. */ /** @brief Register definition for @ref DEVICE_t.RegisterData. */ typedef register_container RegDEVICERegisterData_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RegisterData"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERegisterData_t() { /** @brief constructor for @ref DEVICE_t.RegisterData. */ r32.setName("RegisterData"); } RegDEVICERegisterData_t& operator=(const RegDEVICERegisterData_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERegisterData_t; #define REG_DEVICE_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX ((volatile APE_DEVICE_H_uint32_t*)0xa0040088) /* UNDI Receive Return Ring Consumer Index Mailbox */ /** @brief Register definition for @ref DEVICE_t.UndiReceiveReturnRingConsumerIndex. */ typedef register_container RegDEVICEUndiReceiveReturnRingConsumerIndex_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "UndiReceiveReturnRingConsumerIndex"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEUndiReceiveReturnRingConsumerIndex_t() { /** @brief constructor for @ref DEVICE_t.UndiReceiveReturnRingConsumerIndex. */ r32.setName("UndiReceiveReturnRingConsumerIndex"); } RegDEVICEUndiReceiveReturnRingConsumerIndex_t& operator=(const RegDEVICEUndiReceiveReturnRingConsumerIndex_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEUndiReceiveReturnRingConsumerIndex_t; #define REG_DEVICE_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOW ((volatile APE_DEVICE_H_uint32_t*)0xa004008c) /* UNDI Receive Return Ring Consumer Index Mailbox */ /** @brief Register definition for @ref DEVICE_t.UndiReceiveReturnRingConsumerIndexLow. */ typedef register_container RegDEVICEUndiReceiveReturnRingConsumerIndexLow_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "UndiReceiveReturnRingConsumerIndexLow"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEUndiReceiveReturnRingConsumerIndexLow_t() { /** @brief constructor for @ref DEVICE_t.UndiReceiveReturnRingConsumerIndexLow. */ r32.setName("UndiReceiveReturnRingConsumerIndexLow"); } RegDEVICEUndiReceiveReturnRingConsumerIndexLow_t& operator=(const RegDEVICEUndiReceiveReturnRingConsumerIndexLow_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEUndiReceiveReturnRingConsumerIndexLow_t; #define REG_DEVICE_LINK_STATUS_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa00400bc) /* PCIe standard register. */ #define DEVICE_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_SHIFT 16u #define DEVICE_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_MASK 0xf0000u #define GET_DEVICE_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__reg__) (((__reg__) & 0xf0000) >> 16u) #define SET_DEVICE_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__val__) (((__val__) << 16u) & 0xf0000u) #define DEVICE_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_1_0 0x1u #define DEVICE_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_2_0 0x2u #define DEVICE_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20u #define DEVICE_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x3f00000u #define GET_DEVICE_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__reg__) (((__reg__) & 0x3f00000) >> 20u) #define SET_DEVICE_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__val__) (((__val__) << 20u) & 0x3f00000u) /** @brief Register definition for @ref DEVICE_t.LinkStatusControl. */ typedef register_container RegDEVICELinkStatusControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NegotiatedLinkSpeed, 16, 4) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NegotiatedLinkWidth, 20, 6) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_26, 26, 6) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_26, 26, 6) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NegotiatedLinkWidth, 20, 6) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NegotiatedLinkSpeed, 16, 4) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "LinkStatusControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICELinkStatusControl_t() { /** @brief constructor for @ref DEVICE_t.LinkStatusControl. */ r32.setName("LinkStatusControl"); bits.NegotiatedLinkSpeed.setBaseRegister(&r32); bits.NegotiatedLinkSpeed.setName("NegotiatedLinkSpeed"); bits.NegotiatedLinkSpeed.addEnum("PCIe 1.0", 0x1); bits.NegotiatedLinkSpeed.addEnum("PCIe 2.0", 0x2); bits.NegotiatedLinkWidth.setBaseRegister(&r32); bits.NegotiatedLinkWidth.setName("NegotiatedLinkWidth"); } RegDEVICELinkStatusControl_t& operator=(const RegDEVICELinkStatusControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICELinkStatusControl_t; #define REG_DEVICE_APE_MEMORY_BASE ((volatile APE_DEVICE_H_uint32_t*)0xa00400f8) /* APE Memory address to read/write using the APE Memory Data register.. */ /** @brief Register definition for @ref DEVICE_t.ApeMemoryBase. */ typedef register_container RegDEVICEApeMemoryBase_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ApeMemoryBase"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEApeMemoryBase_t() { /** @brief constructor for @ref DEVICE_t.ApeMemoryBase. */ r32.setName("ApeMemoryBase"); } RegDEVICEApeMemoryBase_t& operator=(const RegDEVICEApeMemoryBase_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEApeMemoryBase_t; #define REG_DEVICE_APE_MEMORY_DATA ((volatile APE_DEVICE_H_uint32_t*)0xa00400fc) /* APE Memory value at the location pointed by the Memory Base Register. */ /** @brief Register definition for @ref DEVICE_t.ApeMemoryData. */ typedef register_container RegDEVICEApeMemoryData_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ApeMemoryData"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEApeMemoryData_t() { /** @brief constructor for @ref DEVICE_t.ApeMemoryData. */ r32.setName("ApeMemoryData"); } RegDEVICEApeMemoryData_t& operator=(const RegDEVICEApeMemoryData_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEApeMemoryData_t; #define REG_DEVICE_160 ((volatile APE_DEVICE_H_uint32_t*)0xa0040160) /* Unknown register. */ /** @brief Register definition for @ref DEVICE_t.160. */ typedef register_container RegDEVICE160_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "160"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE160_t() { /** @brief constructor for @ref DEVICE_t.160. */ r32.setName("160"); } RegDEVICE160_t& operator=(const RegDEVICE160_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE160_t; #define REG_DEVICE_EMAC_MODE ((volatile APE_DEVICE_H_uint32_t*)0xa0040400) /* */ #define DEVICE_EMAC_MODE_GLOBAL_RESET_SHIFT 0u #define DEVICE_EMAC_MODE_GLOBAL_RESET_MASK 0x1u #define GET_DEVICE_EMAC_MODE_GLOBAL_RESET(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_EMAC_MODE_GLOBAL_RESET(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_EMAC_MODE_HALF_DUPLEX_SHIFT 1u #define DEVICE_EMAC_MODE_HALF_DUPLEX_MASK 0x2u #define GET_DEVICE_EMAC_MODE_HALF_DUPLEX(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_EMAC_MODE_HALF_DUPLEX(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_EMAC_MODE_PORT_MODE_SHIFT 2u #define DEVICE_EMAC_MODE_PORT_MODE_MASK 0xcu #define GET_DEVICE_EMAC_MODE_PORT_MODE(__reg__) (((__reg__) & 0xc) >> 2u) #define SET_DEVICE_EMAC_MODE_PORT_MODE(__val__) (((__val__) << 2u) & 0xcu) #define DEVICE_EMAC_MODE_PORT_MODE_NONE 0x0u #define DEVICE_EMAC_MODE_PORT_MODE_10_DIV_100 0x1u #define DEVICE_EMAC_MODE_PORT_MODE_1000 0x2u #define DEVICE_EMAC_MODE_PORT_MODE_TBI 0x3u #define DEVICE_EMAC_MODE_LOOPBACK_MODE_SHIFT 4u #define DEVICE_EMAC_MODE_LOOPBACK_MODE_MASK 0x10u #define GET_DEVICE_EMAC_MODE_LOOPBACK_MODE(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_EMAC_MODE_LOOPBACK_MODE(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_EMAC_MODE_TAGGED_MAC_CONTROL_SHIFT 7u #define DEVICE_EMAC_MODE_TAGGED_MAC_CONTROL_MASK 0x80u #define GET_DEVICE_EMAC_MODE_TAGGED_MAC_CONTROL(__reg__) (((__reg__) & 0x80) >> 7u) #define SET_DEVICE_EMAC_MODE_TAGGED_MAC_CONTROL(__val__) (((__val__) << 7u) & 0x80u) #define DEVICE_EMAC_MODE_ENABLE_TX_BURSTING_SHIFT 8u #define DEVICE_EMAC_MODE_ENABLE_TX_BURSTING_MASK 0x100u #define GET_DEVICE_EMAC_MODE_ENABLE_TX_BURSTING(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_EMAC_MODE_ENABLE_TX_BURSTING(__val__) (((__val__) << 8u) & 0x100u) #define DEVICE_EMAC_MODE_MAX_DEFER_SHIFT 9u #define DEVICE_EMAC_MODE_MAX_DEFER_MASK 0x200u #define GET_DEVICE_EMAC_MODE_MAX_DEFER(__reg__) (((__reg__) & 0x200) >> 9u) #define SET_DEVICE_EMAC_MODE_MAX_DEFER(__val__) (((__val__) << 9u) & 0x200u) #define DEVICE_EMAC_MODE_ENABLE_RX_STATISTICS_SHIFT 11u #define DEVICE_EMAC_MODE_ENABLE_RX_STATISTICS_MASK 0x800u #define GET_DEVICE_EMAC_MODE_ENABLE_RX_STATISTICS(__reg__) (((__reg__) & 0x800) >> 11u) #define SET_DEVICE_EMAC_MODE_ENABLE_RX_STATISTICS(__val__) (((__val__) << 11u) & 0x800u) #define DEVICE_EMAC_MODE_CLEAR_RX_STATISTICS_SHIFT 12u #define DEVICE_EMAC_MODE_CLEAR_RX_STATISTICS_MASK 0x1000u #define GET_DEVICE_EMAC_MODE_CLEAR_RX_STATISTICS(__reg__) (((__reg__) & 0x1000) >> 12u) #define SET_DEVICE_EMAC_MODE_CLEAR_RX_STATISTICS(__val__) (((__val__) << 12u) & 0x1000u) #define DEVICE_EMAC_MODE_FLUSH_RX_STATISTICS_SHIFT 13u #define DEVICE_EMAC_MODE_FLUSH_RX_STATISTICS_MASK 0x2000u #define GET_DEVICE_EMAC_MODE_FLUSH_RX_STATISTICS(__reg__) (((__reg__) & 0x2000) >> 13u) #define SET_DEVICE_EMAC_MODE_FLUSH_RX_STATISTICS(__val__) (((__val__) << 13u) & 0x2000u) #define DEVICE_EMAC_MODE_ENABLE_TX_STATISTICS_SHIFT 14u #define DEVICE_EMAC_MODE_ENABLE_TX_STATISTICS_MASK 0x4000u #define GET_DEVICE_EMAC_MODE_ENABLE_TX_STATISTICS(__reg__) (((__reg__) & 0x4000) >> 14u) #define SET_DEVICE_EMAC_MODE_ENABLE_TX_STATISTICS(__val__) (((__val__) << 14u) & 0x4000u) #define DEVICE_EMAC_MODE_CLEAR_TX_STATISTICS_SHIFT 15u #define DEVICE_EMAC_MODE_CLEAR_TX_STATISTICS_MASK 0x8000u #define GET_DEVICE_EMAC_MODE_CLEAR_TX_STATISTICS(__reg__) (((__reg__) & 0x8000) >> 15u) #define SET_DEVICE_EMAC_MODE_CLEAR_TX_STATISTICS(__val__) (((__val__) << 15u) & 0x8000u) #define DEVICE_EMAC_MODE_FLUSH_TX_STATISTICS_SHIFT 16u #define DEVICE_EMAC_MODE_FLUSH_TX_STATISTICS_MASK 0x10000u #define GET_DEVICE_EMAC_MODE_FLUSH_TX_STATISTICS(__reg__) (((__reg__) & 0x10000) >> 16u) #define SET_DEVICE_EMAC_MODE_FLUSH_TX_STATISTICS(__val__) (((__val__) << 16u) & 0x10000u) #define DEVICE_EMAC_MODE_SEND_CONFIG_COMMAND_SHIFT 17u #define DEVICE_EMAC_MODE_SEND_CONFIG_COMMAND_MASK 0x20000u #define GET_DEVICE_EMAC_MODE_SEND_CONFIG_COMMAND(__reg__) (((__reg__) & 0x20000) >> 17u) #define SET_DEVICE_EMAC_MODE_SEND_CONFIG_COMMAND(__val__) (((__val__) << 17u) & 0x20000u) #define DEVICE_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_SHIFT 18u #define DEVICE_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_MASK 0x40000u #define GET_DEVICE_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) #define SET_DEVICE_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) #define DEVICE_EMAC_MODE_ACPI_POWER_ON_ENABLE_SHIFT 19u #define DEVICE_EMAC_MODE_ACPI_POWER_ON_ENABLE_MASK 0x80000u #define GET_DEVICE_EMAC_MODE_ACPI_POWER_ON_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) #define SET_DEVICE_EMAC_MODE_ACPI_POWER_ON_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) #define DEVICE_EMAC_MODE_ENABLE_TCE_SHIFT 21u #define DEVICE_EMAC_MODE_ENABLE_TCE_MASK 0x200000u #define GET_DEVICE_EMAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x200000) >> 21u) #define SET_DEVICE_EMAC_MODE_ENABLE_TCE(__val__) (((__val__) << 21u) & 0x200000u) #define DEVICE_EMAC_MODE_ENABLE_RDE_SHIFT 22u #define DEVICE_EMAC_MODE_ENABLE_RDE_MASK 0x400000u #define GET_DEVICE_EMAC_MODE_ENABLE_RDE(__reg__) (((__reg__) & 0x400000) >> 22u) #define SET_DEVICE_EMAC_MODE_ENABLE_RDE(__val__) (((__val__) << 22u) & 0x400000u) #define DEVICE_EMAC_MODE_ENABLE_FHDE_SHIFT 23u #define DEVICE_EMAC_MODE_ENABLE_FHDE_MASK 0x800000u #define GET_DEVICE_EMAC_MODE_ENABLE_FHDE(__reg__) (((__reg__) & 0x800000) >> 23u) #define SET_DEVICE_EMAC_MODE_ENABLE_FHDE(__val__) (((__val__) << 23u) & 0x800000u) #define DEVICE_EMAC_MODE_KEEP_FRAME_IN_WOL_SHIFT 24u #define DEVICE_EMAC_MODE_KEEP_FRAME_IN_WOL_MASK 0x1000000u #define GET_DEVICE_EMAC_MODE_KEEP_FRAME_IN_WOL(__reg__) (((__reg__) & 0x1000000) >> 24u) #define SET_DEVICE_EMAC_MODE_KEEP_FRAME_IN_WOL(__val__) (((__val__) << 24u) & 0x1000000u) #define DEVICE_EMAC_MODE_HALT_INTERESTING_PACKET_PME_SHIFT 25u #define DEVICE_EMAC_MODE_HALT_INTERESTING_PACKET_PME_MASK 0x2000000u #define GET_DEVICE_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__reg__) (((__reg__) & 0x2000000) >> 25u) #define SET_DEVICE_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__val__) (((__val__) << 25u) & 0x2000000u) #define DEVICE_EMAC_MODE_FREE_RUNNING_ACPI_SHIFT 26u #define DEVICE_EMAC_MODE_FREE_RUNNING_ACPI_MASK 0x4000000u #define GET_DEVICE_EMAC_MODE_FREE_RUNNING_ACPI(__reg__) (((__reg__) & 0x4000000) >> 26u) #define SET_DEVICE_EMAC_MODE_FREE_RUNNING_ACPI(__val__) (((__val__) << 26u) & 0x4000000u) #define DEVICE_EMAC_MODE_ENABLE_APE_RX_PATH_SHIFT 27u #define DEVICE_EMAC_MODE_ENABLE_APE_RX_PATH_MASK 0x8000000u #define GET_DEVICE_EMAC_MODE_ENABLE_APE_RX_PATH(__reg__) (((__reg__) & 0x8000000) >> 27u) #define SET_DEVICE_EMAC_MODE_ENABLE_APE_RX_PATH(__val__) (((__val__) << 27u) & 0x8000000u) #define DEVICE_EMAC_MODE_ENABLE_APE_TX_PATH_SHIFT 28u #define DEVICE_EMAC_MODE_ENABLE_APE_TX_PATH_MASK 0x10000000u #define GET_DEVICE_EMAC_MODE_ENABLE_APE_TX_PATH(__reg__) (((__reg__) & 0x10000000) >> 28u) #define SET_DEVICE_EMAC_MODE_ENABLE_APE_TX_PATH(__val__) (((__val__) << 28u) & 0x10000000u) #define DEVICE_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_SHIFT 29u #define DEVICE_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_MASK 0x20000000u #define GET_DEVICE_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__reg__) (((__reg__) & 0x20000000) >> 29u) #define SET_DEVICE_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__val__) (((__val__) << 29u) & 0x20000000u) /** @brief Register definition for @ref DEVICE_t.EmacMode. */ typedef register_container RegDEVICEEmacMode_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief When this bit is set to 1, the MAC state machine is reset. This is a self-clearing bit. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GlobalReset, 0, 1) /** @brief When set, the MII/GMII interface is configured to operate in half-duplex mode and the CSMA/ CD state machines in the MAC are set to half-duplex mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HalfDuplex, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PortMode, 2, 2) /** @brief When set, an internal loopback path is enabled from the transmit MAC to the receive MAC. This bit is provided for diagnostic purposes only. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LoopbackMode, 4, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_6_5, 5, 2) /** @brief Allow the MAC to receive tagged MAC control packets. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TaggedMACControl, 7, 1) /** @brief Enable transmit bursting in gigabit half-duplex mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTXBursting, 8, 1) /** @brief Enable Max Deferral checking statistic. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MaxDefer, 9, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_10_10, 10, 1) /** @brief Enable receive statistics external updates. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableRXStatistics, 11, 1) /** @brief Clear receive statistics internal RAM. This bit is self-clearing. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClearRXStatistics, 12, 1) /** @brief Write receive statistics to external memory. This bit is self-clearing. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlushRXStatistics, 13, 1) /** @brief Enable transmit statistics external updates. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTXStatistics, 14, 1) /** @brief Clear transmit statistics internal RAM. This bit is self-clearing. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClearTXStatistics, 15, 1) /** @brief Write transmit statistics to external memory. This bit is self-clearing. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlushTXStatistics, 16, 1) /** @brief Send config commands when in TBI mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SendConfigCommand, 17, 1) /** @brief Enable Magic Packet detection. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MagicPacketDetectionEnable, 18, 1) /** @brief Enable Wake on LAN filters when in powerdown mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ACPIPowerOnEnable, 19, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_20_20, 20, 1) /** @brief Enable Transmit DMA engine. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTCE, 21, 1) /** @brief Enable RDMA engine. Must be set for normal operation. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableRDE, 22, 1) /** @brief Enable receive Frame Header DMA engine. Must be set for normal operation. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableFHDE, 23, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, KeepFrameInWOL, 24, 1) /** @brief When this bit is set, the WOL signal will not be asserted on an interesting packet match. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HaltInterestingPacketPME, 25, 1) /** @brief When this bit is set, the ACPI state machine will continue running when a match is found. When this bit is clear, the ACPI state machine will halt when a match is found. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Free_RunningACPI, 26, 1) /** @brief This bit must be written a 1 for APE subsystem to receive packets from the EMAC. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableAPERXPath, 27, 1) /** @brief This bit must be written a 1 for the EMAC to transmit APE packets. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableAPETXPath, 28, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACLoopbackModeControl, 29, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_30, 30, 2) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_30, 30, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACLoopbackModeControl, 29, 1) /** @brief This bit must be written a 1 for the EMAC to transmit APE packets. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableAPETXPath, 28, 1) /** @brief This bit must be written a 1 for APE subsystem to receive packets from the EMAC. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableAPERXPath, 27, 1) /** @brief When this bit is set, the ACPI state machine will continue running when a match is found. When this bit is clear, the ACPI state machine will halt when a match is found. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Free_RunningACPI, 26, 1) /** @brief When this bit is set, the WOL signal will not be asserted on an interesting packet match. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HaltInterestingPacketPME, 25, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, KeepFrameInWOL, 24, 1) /** @brief Enable receive Frame Header DMA engine. Must be set for normal operation. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableFHDE, 23, 1) /** @brief Enable RDMA engine. Must be set for normal operation. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableRDE, 22, 1) /** @brief Enable Transmit DMA engine. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTCE, 21, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_20_20, 20, 1) /** @brief Enable Wake on LAN filters when in powerdown mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ACPIPowerOnEnable, 19, 1) /** @brief Enable Magic Packet detection. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MagicPacketDetectionEnable, 18, 1) /** @brief Send config commands when in TBI mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SendConfigCommand, 17, 1) /** @brief Write transmit statistics to external memory. This bit is self-clearing. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlushTXStatistics, 16, 1) /** @brief Clear transmit statistics internal RAM. This bit is self-clearing. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClearTXStatistics, 15, 1) /** @brief Enable transmit statistics external updates. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTXStatistics, 14, 1) /** @brief Write receive statistics to external memory. This bit is self-clearing. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlushRXStatistics, 13, 1) /** @brief Clear receive statistics internal RAM. This bit is self-clearing. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClearRXStatistics, 12, 1) /** @brief Enable receive statistics external updates. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableRXStatistics, 11, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_10_10, 10, 1) /** @brief Enable Max Deferral checking statistic. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MaxDefer, 9, 1) /** @brief Enable transmit bursting in gigabit half-duplex mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTXBursting, 8, 1) /** @brief Allow the MAC to receive tagged MAC control packets. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TaggedMACControl, 7, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_6_5, 5, 2) /** @brief When set, an internal loopback path is enabled from the transmit MAC to the receive MAC. This bit is provided for diagnostic purposes only. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LoopbackMode, 4, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PortMode, 2, 2) /** @brief When set, the MII/GMII interface is configured to operate in half-duplex mode and the CSMA/ CD state machines in the MAC are set to half-duplex mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HalfDuplex, 1, 1) /** @brief When this bit is set to 1, the MAC state machine is reset. This is a self-clearing bit. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GlobalReset, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EmacMode"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEmacMode_t() { /** @brief constructor for @ref DEVICE_t.EmacMode. */ r32.setName("EmacMode"); bits.GlobalReset.setBaseRegister(&r32); bits.GlobalReset.setName("GlobalReset"); bits.HalfDuplex.setBaseRegister(&r32); bits.HalfDuplex.setName("HalfDuplex"); bits.PortMode.setBaseRegister(&r32); bits.PortMode.setName("PortMode"); bits.PortMode.addEnum("None", 0x0); bits.PortMode.addEnum("10/100", 0x1); bits.PortMode.addEnum("1000", 0x2); bits.PortMode.addEnum("TBI", 0x3); bits.LoopbackMode.setBaseRegister(&r32); bits.LoopbackMode.setName("LoopbackMode"); bits.TaggedMACControl.setBaseRegister(&r32); bits.TaggedMACControl.setName("TaggedMACControl"); bits.EnableTXBursting.setBaseRegister(&r32); bits.EnableTXBursting.setName("EnableTXBursting"); bits.MaxDefer.setBaseRegister(&r32); bits.MaxDefer.setName("MaxDefer"); bits.EnableRXStatistics.setBaseRegister(&r32); bits.EnableRXStatistics.setName("EnableRXStatistics"); bits.ClearRXStatistics.setBaseRegister(&r32); bits.ClearRXStatistics.setName("ClearRXStatistics"); bits.FlushRXStatistics.setBaseRegister(&r32); bits.FlushRXStatistics.setName("FlushRXStatistics"); bits.EnableTXStatistics.setBaseRegister(&r32); bits.EnableTXStatistics.setName("EnableTXStatistics"); bits.ClearTXStatistics.setBaseRegister(&r32); bits.ClearTXStatistics.setName("ClearTXStatistics"); bits.FlushTXStatistics.setBaseRegister(&r32); bits.FlushTXStatistics.setName("FlushTXStatistics"); bits.SendConfigCommand.setBaseRegister(&r32); bits.SendConfigCommand.setName("SendConfigCommand"); bits.MagicPacketDetectionEnable.setBaseRegister(&r32); bits.MagicPacketDetectionEnable.setName("MagicPacketDetectionEnable"); bits.ACPIPowerOnEnable.setBaseRegister(&r32); bits.ACPIPowerOnEnable.setName("ACPIPowerOnEnable"); bits.EnableTCE.setBaseRegister(&r32); bits.EnableTCE.setName("EnableTCE"); bits.EnableRDE.setBaseRegister(&r32); bits.EnableRDE.setName("EnableRDE"); bits.EnableFHDE.setBaseRegister(&r32); bits.EnableFHDE.setName("EnableFHDE"); bits.KeepFrameInWOL.setBaseRegister(&r32); bits.KeepFrameInWOL.setName("KeepFrameInWOL"); bits.HaltInterestingPacketPME.setBaseRegister(&r32); bits.HaltInterestingPacketPME.setName("HaltInterestingPacketPME"); bits.Free_RunningACPI.setBaseRegister(&r32); bits.Free_RunningACPI.setName("Free_RunningACPI"); bits.EnableAPERXPath.setBaseRegister(&r32); bits.EnableAPERXPath.setName("EnableAPERXPath"); bits.EnableAPETXPath.setBaseRegister(&r32); bits.EnableAPETXPath.setName("EnableAPETXPath"); bits.MACLoopbackModeControl.setBaseRegister(&r32); bits.MACLoopbackModeControl.setName("MACLoopbackModeControl"); } RegDEVICEEmacMode_t& operator=(const RegDEVICEEmacMode_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEmacMode_t; #define REG_DEVICE_EMAC_STATUS ((volatile APE_DEVICE_H_uint32_t*)0xa0040404) /* */ #define DEVICE_EMAC_STATUS_PCS_SYNCED_SHIFT 0u #define DEVICE_EMAC_STATUS_PCS_SYNCED_MASK 0x1u #define GET_DEVICE_EMAC_STATUS_PCS_SYNCED(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_EMAC_STATUS_PCS_SYNCED(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_EMAC_STATUS_SIGNAL_DETECT_SHIFT 1u #define DEVICE_EMAC_STATUS_SIGNAL_DETECT_MASK 0x2u #define GET_DEVICE_EMAC_STATUS_SIGNAL_DETECT(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_EMAC_STATUS_SIGNAL_DETECT(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_EMAC_STATUS_RECEIVED_CONFIGURATION_SHIFT 2u #define DEVICE_EMAC_STATUS_RECEIVED_CONFIGURATION_MASK 0x4u #define GET_DEVICE_EMAC_STATUS_RECEIVED_CONFIGURATION(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_EMAC_STATUS_RECEIVED_CONFIGURATION(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_EMAC_STATUS_CONFIGURATION_CHANGED_SHIFT 3u #define DEVICE_EMAC_STATUS_CONFIGURATION_CHANGED_MASK 0x8u #define GET_DEVICE_EMAC_STATUS_CONFIGURATION_CHANGED(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_EMAC_STATUS_CONFIGURATION_CHANGED(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_EMAC_STATUS_SYNC_CHANGED_SHIFT 4u #define DEVICE_EMAC_STATUS_SYNC_CHANGED_MASK 0x10u #define GET_DEVICE_EMAC_STATUS_SYNC_CHANGED(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_EMAC_STATUS_SYNC_CHANGED(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_EMAC_STATUS_PORT_DETECT_ERROR_SHIFT 10u #define DEVICE_EMAC_STATUS_PORT_DETECT_ERROR_MASK 0x400u #define GET_DEVICE_EMAC_STATUS_PORT_DETECT_ERROR(__reg__) (((__reg__) & 0x400) >> 10u) #define SET_DEVICE_EMAC_STATUS_PORT_DETECT_ERROR(__val__) (((__val__) << 10u) & 0x400u) #define DEVICE_EMAC_STATUS_LINK_STATE_CHANGED_SHIFT 12u #define DEVICE_EMAC_STATUS_LINK_STATE_CHANGED_MASK 0x1000u #define GET_DEVICE_EMAC_STATUS_LINK_STATE_CHANGED(__reg__) (((__reg__) & 0x1000) >> 12u) #define SET_DEVICE_EMAC_STATUS_LINK_STATE_CHANGED(__val__) (((__val__) << 12u) & 0x1000u) #define DEVICE_EMAC_STATUS_MI_COMPLETION_SHIFT 22u #define DEVICE_EMAC_STATUS_MI_COMPLETION_MASK 0x400000u #define GET_DEVICE_EMAC_STATUS_MI_COMPLETION(__reg__) (((__reg__) & 0x400000) >> 22u) #define SET_DEVICE_EMAC_STATUS_MI_COMPLETION(__val__) (((__val__) << 22u) & 0x400000u) #define DEVICE_EMAC_STATUS_MI_INTERRUPT_SHIFT 23u #define DEVICE_EMAC_STATUS_MI_INTERRUPT_MASK 0x800000u #define GET_DEVICE_EMAC_STATUS_MI_INTERRUPT(__reg__) (((__reg__) & 0x800000) >> 23u) #define SET_DEVICE_EMAC_STATUS_MI_INTERRUPT(__val__) (((__val__) << 23u) & 0x800000u) #define DEVICE_EMAC_STATUS_AP_ERROR_SHIFT 24u #define DEVICE_EMAC_STATUS_AP_ERROR_MASK 0x1000000u #define GET_DEVICE_EMAC_STATUS_AP_ERROR(__reg__) (((__reg__) & 0x1000000) >> 24u) #define SET_DEVICE_EMAC_STATUS_AP_ERROR(__val__) (((__val__) << 24u) & 0x1000000u) #define DEVICE_EMAC_STATUS_ODI_ERROR_SHIFT 25u #define DEVICE_EMAC_STATUS_ODI_ERROR_MASK 0x2000000u #define GET_DEVICE_EMAC_STATUS_ODI_ERROR(__reg__) (((__reg__) & 0x2000000) >> 25u) #define SET_DEVICE_EMAC_STATUS_ODI_ERROR(__val__) (((__val__) << 25u) & 0x2000000u) #define DEVICE_EMAC_STATUS_RX_STAT_OVERRUN_SHIFT 26u #define DEVICE_EMAC_STATUS_RX_STAT_OVERRUN_MASK 0x4000000u #define GET_DEVICE_EMAC_STATUS_RX_STAT_OVERRUN(__reg__) (((__reg__) & 0x4000000) >> 26u) #define SET_DEVICE_EMAC_STATUS_RX_STAT_OVERRUN(__val__) (((__val__) << 26u) & 0x4000000u) #define DEVICE_EMAC_STATUS_TX_STAT_OVERRUN_SHIFT 27u #define DEVICE_EMAC_STATUS_TX_STAT_OVERRUN_MASK 0x8000000u #define GET_DEVICE_EMAC_STATUS_TX_STAT_OVERRUN(__reg__) (((__reg__) & 0x8000000) >> 27u) #define SET_DEVICE_EMAC_STATUS_TX_STAT_OVERRUN(__val__) (((__val__) << 27u) & 0x8000000u) /** @brief Register definition for @ref DEVICE_t.EmacStatus. */ typedef register_container RegDEVICEEmacStatus_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCSSynced, 0, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SignalDetect, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ReceivedConfiguration, 2, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ConfigurationChanged, 3, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SyncChanged, 4, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_9_5, 5, 5) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PortDetectError, 10, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_11_11, 11, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkStateChanged, 12, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_21_13, 13, 9) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MICompletion, 22, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MIInterrupt, 23, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APError, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ODIError, 25, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXStatOverrun, 26, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TXStatOverrun, 27, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_28, 28, 4) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_28, 28, 4) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TXStatOverrun, 27, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXStatOverrun, 26, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ODIError, 25, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APError, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MIInterrupt, 23, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MICompletion, 22, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_21_13, 13, 9) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkStateChanged, 12, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_11_11, 11, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PortDetectError, 10, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_9_5, 5, 5) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SyncChanged, 4, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ConfigurationChanged, 3, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ReceivedConfiguration, 2, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SignalDetect, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCSSynced, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EmacStatus"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEmacStatus_t() { /** @brief constructor for @ref DEVICE_t.EmacStatus. */ r32.setName("EmacStatus"); bits.PCSSynced.setBaseRegister(&r32); bits.PCSSynced.setName("PCSSynced"); bits.SignalDetect.setBaseRegister(&r32); bits.SignalDetect.setName("SignalDetect"); bits.ReceivedConfiguration.setBaseRegister(&r32); bits.ReceivedConfiguration.setName("ReceivedConfiguration"); bits.ConfigurationChanged.setBaseRegister(&r32); bits.ConfigurationChanged.setName("ConfigurationChanged"); bits.SyncChanged.setBaseRegister(&r32); bits.SyncChanged.setName("SyncChanged"); bits.PortDetectError.setBaseRegister(&r32); bits.PortDetectError.setName("PortDetectError"); bits.LinkStateChanged.setBaseRegister(&r32); bits.LinkStateChanged.setName("LinkStateChanged"); bits.MICompletion.setBaseRegister(&r32); bits.MICompletion.setName("MICompletion"); bits.MIInterrupt.setBaseRegister(&r32); bits.MIInterrupt.setName("MIInterrupt"); bits.APError.setBaseRegister(&r32); bits.APError.setName("APError"); bits.ODIError.setBaseRegister(&r32); bits.ODIError.setName("ODIError"); bits.RXStatOverrun.setBaseRegister(&r32); bits.RXStatOverrun.setName("RXStatOverrun"); bits.TXStatOverrun.setBaseRegister(&r32); bits.TXStatOverrun.setName("TXStatOverrun"); } RegDEVICEEmacStatus_t& operator=(const RegDEVICEEmacStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEmacStatus_t; #define REG_DEVICE_EMAC_EVENT ((volatile APE_DEVICE_H_uint32_t*)0xa0040408) /* */ #define DEVICE_EMAC_EVENT_PORT_DETECT_ERROR_SHIFT 10u #define DEVICE_EMAC_EVENT_PORT_DETECT_ERROR_MASK 0x400u #define GET_DEVICE_EMAC_EVENT_PORT_DETECT_ERROR(__reg__) (((__reg__) & 0x400) >> 10u) #define SET_DEVICE_EMAC_EVENT_PORT_DETECT_ERROR(__val__) (((__val__) << 10u) & 0x400u) #define DEVICE_EMAC_EVENT_LINK_STATE_CHANGED_SHIFT 12u #define DEVICE_EMAC_EVENT_LINK_STATE_CHANGED_MASK 0x1000u #define GET_DEVICE_EMAC_EVENT_LINK_STATE_CHANGED(__reg__) (((__reg__) & 0x1000) >> 12u) #define SET_DEVICE_EMAC_EVENT_LINK_STATE_CHANGED(__val__) (((__val__) << 12u) & 0x1000u) #define DEVICE_EMAC_EVENT_MI_COMPLETION_SHIFT 22u #define DEVICE_EMAC_EVENT_MI_COMPLETION_MASK 0x400000u #define GET_DEVICE_EMAC_EVENT_MI_COMPLETION(__reg__) (((__reg__) & 0x400000) >> 22u) #define SET_DEVICE_EMAC_EVENT_MI_COMPLETION(__val__) (((__val__) << 22u) & 0x400000u) #define DEVICE_EMAC_EVENT_MI_INTERRUPT_SHIFT 23u #define DEVICE_EMAC_EVENT_MI_INTERRUPT_MASK 0x800000u #define GET_DEVICE_EMAC_EVENT_MI_INTERRUPT(__reg__) (((__reg__) & 0x800000) >> 23u) #define SET_DEVICE_EMAC_EVENT_MI_INTERRUPT(__val__) (((__val__) << 23u) & 0x800000u) #define DEVICE_EMAC_EVENT_AP_ERROR_SHIFT 24u #define DEVICE_EMAC_EVENT_AP_ERROR_MASK 0x1000000u #define GET_DEVICE_EMAC_EVENT_AP_ERROR(__reg__) (((__reg__) & 0x1000000) >> 24u) #define SET_DEVICE_EMAC_EVENT_AP_ERROR(__val__) (((__val__) << 24u) & 0x1000000u) #define DEVICE_EMAC_EVENT_ODI_ERROR_SHIFT 25u #define DEVICE_EMAC_EVENT_ODI_ERROR_MASK 0x2000000u #define GET_DEVICE_EMAC_EVENT_ODI_ERROR(__reg__) (((__reg__) & 0x2000000) >> 25u) #define SET_DEVICE_EMAC_EVENT_ODI_ERROR(__val__) (((__val__) << 25u) & 0x2000000u) #define DEVICE_EMAC_EVENT_RX_STAT_OVERRUN_SHIFT 26u #define DEVICE_EMAC_EVENT_RX_STAT_OVERRUN_MASK 0x4000000u #define GET_DEVICE_EMAC_EVENT_RX_STAT_OVERRUN(__reg__) (((__reg__) & 0x4000000) >> 26u) #define SET_DEVICE_EMAC_EVENT_RX_STAT_OVERRUN(__val__) (((__val__) << 26u) & 0x4000000u) #define DEVICE_EMAC_EVENT_TX_STAT_OVERRUN_SHIFT 27u #define DEVICE_EMAC_EVENT_TX_STAT_OVERRUN_MASK 0x8000000u #define GET_DEVICE_EMAC_EVENT_TX_STAT_OVERRUN(__reg__) (((__reg__) & 0x8000000) >> 27u) #define SET_DEVICE_EMAC_EVENT_TX_STAT_OVERRUN(__val__) (((__val__) << 27u) & 0x8000000u) /** @brief Register definition for @ref DEVICE_t.EmacEvent. */ typedef register_container RegDEVICEEmacEvent_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_9_0, 0, 10) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PortDetectError, 10, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_11_11, 11, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkStateChanged, 12, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_21_13, 13, 9) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MICompletion, 22, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MIInterrupt, 23, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APError, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ODIError, 25, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXStatOverrun, 26, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TXStatOverrun, 27, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_28, 28, 4) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_28, 28, 4) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TXStatOverrun, 27, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXStatOverrun, 26, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ODIError, 25, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APError, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MIInterrupt, 23, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MICompletion, 22, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_21_13, 13, 9) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkStateChanged, 12, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_11_11, 11, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PortDetectError, 10, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_9_0, 0, 10) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EmacEvent"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEmacEvent_t() { /** @brief constructor for @ref DEVICE_t.EmacEvent. */ r32.setName("EmacEvent"); bits.PortDetectError.setBaseRegister(&r32); bits.PortDetectError.setName("PortDetectError"); bits.LinkStateChanged.setBaseRegister(&r32); bits.LinkStateChanged.setName("LinkStateChanged"); bits.MICompletion.setBaseRegister(&r32); bits.MICompletion.setName("MICompletion"); bits.MIInterrupt.setBaseRegister(&r32); bits.MIInterrupt.setName("MIInterrupt"); bits.APError.setBaseRegister(&r32); bits.APError.setName("APError"); bits.ODIError.setBaseRegister(&r32); bits.ODIError.setName("ODIError"); bits.RXStatOverrun.setBaseRegister(&r32); bits.RXStatOverrun.setName("RXStatOverrun"); bits.TXStatOverrun.setBaseRegister(&r32); bits.TXStatOverrun.setName("TXStatOverrun"); } RegDEVICEEmacEvent_t& operator=(const RegDEVICEEmacEvent_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEmacEvent_t; #define REG_DEVICE_LED_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa004040c) /* */ #define DEVICE_LED_CONTROL_OVERRIDE_LINK_SHIFT 0u #define DEVICE_LED_CONTROL_OVERRIDE_LINK_MASK 0x1u #define GET_DEVICE_LED_CONTROL_OVERRIDE_LINK(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_LED_CONTROL_OVERRIDE_LINK(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_LED_CONTROL_LED_1000_SHIFT 1u #define DEVICE_LED_CONTROL_LED_1000_MASK 0x2u #define GET_DEVICE_LED_CONTROL_LED_1000(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_LED_CONTROL_LED_1000(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_LED_CONTROL_LED_100_SHIFT 2u #define DEVICE_LED_CONTROL_LED_100_MASK 0x4u #define GET_DEVICE_LED_CONTROL_LED_100(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_LED_CONTROL_LED_100(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_LED_CONTROL_LED_10_SHIFT 3u #define DEVICE_LED_CONTROL_LED_10_MASK 0x8u #define GET_DEVICE_LED_CONTROL_LED_10(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_LED_CONTROL_LED_10(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_LED_CONTROL_OVERRIDE_TRAFFIC_SHIFT 4u #define DEVICE_LED_CONTROL_OVERRIDE_TRAFFIC_MASK 0x10u #define GET_DEVICE_LED_CONTROL_OVERRIDE_TRAFFIC(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_LED_CONTROL_OVERRIDE_TRAFFIC(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_LED_CONTROL_LED_TRAFFIC_BLINK_SHIFT 5u #define DEVICE_LED_CONTROL_LED_TRAFFIC_BLINK_MASK 0x20u #define GET_DEVICE_LED_CONTROL_LED_TRAFFIC_BLINK(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_LED_CONTROL_LED_TRAFFIC_BLINK(__val__) (((__val__) << 5u) & 0x20u) #define DEVICE_LED_CONTROL_LED_TRAFFIC_SHIFT 6u #define DEVICE_LED_CONTROL_LED_TRAFFIC_MASK 0x40u #define GET_DEVICE_LED_CONTROL_LED_TRAFFIC(__reg__) (((__reg__) & 0x40) >> 6u) #define SET_DEVICE_LED_CONTROL_LED_TRAFFIC(__val__) (((__val__) << 6u) & 0x40u) #define DEVICE_LED_CONTROL_LED_STATUS_1000_SHIFT 7u #define DEVICE_LED_CONTROL_LED_STATUS_1000_MASK 0x80u #define GET_DEVICE_LED_CONTROL_LED_STATUS_1000(__reg__) (((__reg__) & 0x80) >> 7u) #define SET_DEVICE_LED_CONTROL_LED_STATUS_1000(__val__) (((__val__) << 7u) & 0x80u) #define DEVICE_LED_CONTROL_LED_STATUS_100_SHIFT 8u #define DEVICE_LED_CONTROL_LED_STATUS_100_MASK 0x100u #define GET_DEVICE_LED_CONTROL_LED_STATUS_100(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_LED_CONTROL_LED_STATUS_100(__val__) (((__val__) << 8u) & 0x100u) #define DEVICE_LED_CONTROL_LED_STATUS_10_SHIFT 9u #define DEVICE_LED_CONTROL_LED_STATUS_10_MASK 0x200u #define GET_DEVICE_LED_CONTROL_LED_STATUS_10(__reg__) (((__reg__) & 0x200) >> 9u) #define SET_DEVICE_LED_CONTROL_LED_STATUS_10(__val__) (((__val__) << 9u) & 0x200u) #define DEVICE_LED_CONTROL_LED_STATUS_TRAFFIC_SHIFT 10u #define DEVICE_LED_CONTROL_LED_STATUS_TRAFFIC_MASK 0x400u #define GET_DEVICE_LED_CONTROL_LED_STATUS_TRAFFIC(__reg__) (((__reg__) & 0x400) >> 10u) #define SET_DEVICE_LED_CONTROL_LED_STATUS_TRAFFIC(__val__) (((__val__) << 10u) & 0x400u) #define DEVICE_LED_CONTROL_LED_MODE_SHIFT 11u #define DEVICE_LED_CONTROL_LED_MODE_MASK 0x1800u #define GET_DEVICE_LED_CONTROL_LED_MODE(__reg__) (((__reg__) & 0x1800) >> 11u) #define SET_DEVICE_LED_CONTROL_LED_MODE(__val__) (((__val__) << 11u) & 0x1800u) #define DEVICE_LED_CONTROL_LED_MODE_MAC 0x0u #define DEVICE_LED_CONTROL_LED_MODE_PHY_MODE_1 0x1u #define DEVICE_LED_CONTROL_LED_MODE_PHY_MODE_2 0x2u #define DEVICE_LED_CONTROL_LED_MODE_PHY_MODE_3 0x3u #define DEVICE_LED_CONTROL_MAC_MODE_SHIFT 13u #define DEVICE_LED_CONTROL_MAC_MODE_MASK 0x2000u #define GET_DEVICE_LED_CONTROL_MAC_MODE(__reg__) (((__reg__) & 0x2000) >> 13u) #define SET_DEVICE_LED_CONTROL_MAC_MODE(__val__) (((__val__) << 13u) & 0x2000u) #define DEVICE_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_SHIFT 14u #define DEVICE_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_MASK 0x4000u #define GET_DEVICE_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__reg__) (((__reg__) & 0x4000) >> 14u) #define SET_DEVICE_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__val__) (((__val__) << 14u) & 0x4000u) #define DEVICE_LED_CONTROL_BLINK_PERIOD_SHIFT 19u #define DEVICE_LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000u #define GET_DEVICE_LED_CONTROL_BLINK_PERIOD(__reg__) (((__reg__) & 0x7ff80000) >> 19u) #define SET_DEVICE_LED_CONTROL_BLINK_PERIOD(__val__) (((__val__) << 19u) & 0x7ff80000u) #define DEVICE_LED_CONTROL_OVERRIDE_BLINK_RATE_SHIFT 31u #define DEVICE_LED_CONTROL_OVERRIDE_BLINK_RATE_MASK 0x80000000u #define GET_DEVICE_LED_CONTROL_OVERRIDE_BLINK_RATE(__reg__) (((__reg__) & 0x80000000) >> 31u) #define SET_DEVICE_LED_CONTROL_OVERRIDE_BLINK_RATE(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref DEVICE_t.LedControl. */ typedef register_container RegDEVICELedControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief If set, overrides hardware control of the three link LEDs. The LEDs will be controlled via bits [3:1]. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, OverrideLink, 0, 1) /** @brief If set along with the LED Override bit, turns on the 1000 Mbps LED. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LED1000, 1, 1) /** @brief If set along with the LED Override bit, turns on the 100 Mbps LED. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LED100, 2, 1) /** @brief If set along with the LED Override bit, turns on the 10 Mbps LED. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LED10, 3, 1) /** @brief If set, overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bits [6:5]. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, OverrideTraffic, 4, 1) /** @brief If set along with the Override Traffic bit and Traffic LED bit, the Traffic LED will blink with the blink rate specified in Override Blink Rate (bit 31) and Blink Period (bits [30:19]) fields. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDTrafficBlink, 5, 1) /** @brief If set along with the Override Traffic bit, the Traffic LED is turned on. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDTraffic, 6, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDStatus1000, 7, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDStatus100, 8, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDStatus10, 9, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDStatusTraffic, 10, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDMode, 11, 2) /** @brief When this bit is set, the traffic LED blinks only when traffic is addressed for the device (The LED_MODE field must be set to 00 before enabling this bit). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACMode, 13, 1) /** @brief When this bit is set, the Link LED is solid green when there is a link and blinks when there is traffic. (The LED_MODE field must be set to 00 before enabling this bit). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SharedTraffic_DIV_LinkLEDMode, 14, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_18_15, 15, 4) /** @brief Specifies the period of each blink cycle (on+off) for Traffic LED in milliseconds. Must be a nonzero value. This 12-bit field is reset to 0x040, giving a default blink period of approximately 15.9Hz. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BlinkPeriod, 19, 12) /** @brief If set, the blink rate for the Traffic LED is determined by the Blink Period field (bit 30 to bit 19). This bit is rest to 1. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, OverrideBlinkRate, 31, 1) #elif defined(__BIG_ENDIAN__) /** @brief If set, the blink rate for the Traffic LED is determined by the Blink Period field (bit 30 to bit 19). This bit is rest to 1. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, OverrideBlinkRate, 31, 1) /** @brief Specifies the period of each blink cycle (on+off) for Traffic LED in milliseconds. Must be a nonzero value. This 12-bit field is reset to 0x040, giving a default blink period of approximately 15.9Hz. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BlinkPeriod, 19, 12) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_18_15, 15, 4) /** @brief When this bit is set, the Link LED is solid green when there is a link and blinks when there is traffic. (The LED_MODE field must be set to 00 before enabling this bit). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SharedTraffic_DIV_LinkLEDMode, 14, 1) /** @brief When this bit is set, the traffic LED blinks only when traffic is addressed for the device (The LED_MODE field must be set to 00 before enabling this bit). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACMode, 13, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDMode, 11, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDStatusTraffic, 10, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDStatus10, 9, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDStatus100, 8, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDStatus1000, 7, 1) /** @brief If set along with the Override Traffic bit, the Traffic LED is turned on. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDTraffic, 6, 1) /** @brief If set along with the Override Traffic bit and Traffic LED bit, the Traffic LED will blink with the blink rate specified in Override Blink Rate (bit 31) and Blink Period (bits [30:19]) fields. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LEDTrafficBlink, 5, 1) /** @brief If set, overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bits [6:5]. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, OverrideTraffic, 4, 1) /** @brief If set along with the LED Override bit, turns on the 10 Mbps LED. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LED10, 3, 1) /** @brief If set along with the LED Override bit, turns on the 100 Mbps LED. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LED100, 2, 1) /** @brief If set along with the LED Override bit, turns on the 1000 Mbps LED. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LED1000, 1, 1) /** @brief If set, overrides hardware control of the three link LEDs. The LEDs will be controlled via bits [3:1]. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, OverrideLink, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "LedControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICELedControl_t() { /** @brief constructor for @ref DEVICE_t.LedControl. */ r32.setName("LedControl"); bits.OverrideLink.setBaseRegister(&r32); bits.OverrideLink.setName("OverrideLink"); bits.LED1000.setBaseRegister(&r32); bits.LED1000.setName("LED1000"); bits.LED100.setBaseRegister(&r32); bits.LED100.setName("LED100"); bits.LED10.setBaseRegister(&r32); bits.LED10.setName("LED10"); bits.OverrideTraffic.setBaseRegister(&r32); bits.OverrideTraffic.setName("OverrideTraffic"); bits.LEDTrafficBlink.setBaseRegister(&r32); bits.LEDTrafficBlink.setName("LEDTrafficBlink"); bits.LEDTraffic.setBaseRegister(&r32); bits.LEDTraffic.setName("LEDTraffic"); bits.LEDStatus1000.setBaseRegister(&r32); bits.LEDStatus1000.setName("LEDStatus1000"); bits.LEDStatus100.setBaseRegister(&r32); bits.LEDStatus100.setName("LEDStatus100"); bits.LEDStatus10.setBaseRegister(&r32); bits.LEDStatus10.setName("LEDStatus10"); bits.LEDStatusTraffic.setBaseRegister(&r32); bits.LEDStatusTraffic.setName("LEDStatusTraffic"); bits.LEDMode.setBaseRegister(&r32); bits.LEDMode.setName("LEDMode"); bits.LEDMode.addEnum("MAC", 0x0); bits.LEDMode.addEnum("PHY Mode 1", 0x1); bits.LEDMode.addEnum("PHY Mode 2", 0x2); bits.LEDMode.addEnum("PHY Mode 3", 0x3); bits.MACMode.setBaseRegister(&r32); bits.MACMode.setName("MACMode"); bits.SharedTraffic_DIV_LinkLEDMode.setBaseRegister(&r32); bits.SharedTraffic_DIV_LinkLEDMode.setName("SharedTraffic_DIV_LinkLEDMode"); bits.BlinkPeriod.setBaseRegister(&r32); bits.BlinkPeriod.setName("BlinkPeriod"); bits.OverrideBlinkRate.setBaseRegister(&r32); bits.OverrideBlinkRate.setName("OverrideBlinkRate"); } RegDEVICELedControl_t& operator=(const RegDEVICELedControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICELedControl_t; #define REG_DEVICE_EMAC_MAC_ADDRESSES_0_HIGH ((volatile APE_DEVICE_H_uint32_t*)0xa0040410) /* Upper 2-bytes of this node's MAC address. */ /** @brief Register definition for @ref DEVICE_t.EmacMacAddresses0High. */ typedef register_container RegDEVICEEmacMacAddresses0High_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EmacMacAddresses0High"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEmacMacAddresses0High_t() { /** @brief constructor for @ref DEVICE_t.EmacMacAddresses0High. */ r32.setName("EmacMacAddresses0High"); } RegDEVICEEmacMacAddresses0High_t& operator=(const RegDEVICEEmacMacAddresses0High_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEmacMacAddresses0High_t; #define REG_DEVICE_EMAC_MAC_ADDRESSES_0_LOW ((volatile APE_DEVICE_H_uint32_t*)0xa0040414) /* Lower 4-byte of this node's MAC address. */ /** @brief Register definition for @ref DEVICE_t.EmacMacAddresses0Low. */ typedef register_container RegDEVICEEmacMacAddresses0Low_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EmacMacAddresses0Low"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEmacMacAddresses0Low_t() { /** @brief constructor for @ref DEVICE_t.EmacMacAddresses0Low. */ r32.setName("EmacMacAddresses0Low"); } RegDEVICEEmacMacAddresses0Low_t& operator=(const RegDEVICEEmacMacAddresses0Low_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEmacMacAddresses0Low_t; #define REG_DEVICE_EMAC_MAC_ADDRESSES_1_HIGH ((volatile APE_DEVICE_H_uint32_t*)0xa0040418) /* Upper 2-bytes of this node's MAC address. */ /** @brief Register definition for @ref DEVICE_t.EmacMacAddresses1High. */ typedef register_container RegDEVICEEmacMacAddresses1High_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EmacMacAddresses1High"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEmacMacAddresses1High_t() { /** @brief constructor for @ref DEVICE_t.EmacMacAddresses1High. */ r32.setName("EmacMacAddresses1High"); } RegDEVICEEmacMacAddresses1High_t& operator=(const RegDEVICEEmacMacAddresses1High_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEmacMacAddresses1High_t; #define REG_DEVICE_EMAC_MAC_ADDRESSES_1_LOW ((volatile APE_DEVICE_H_uint32_t*)0xa004041c) /* Lower 4-byte of this node's MAC address. */ /** @brief Register definition for @ref DEVICE_t.EmacMacAddresses1Low. */ typedef register_container RegDEVICEEmacMacAddresses1Low_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EmacMacAddresses1Low"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEmacMacAddresses1Low_t() { /** @brief constructor for @ref DEVICE_t.EmacMacAddresses1Low. */ r32.setName("EmacMacAddresses1Low"); } RegDEVICEEmacMacAddresses1Low_t& operator=(const RegDEVICEEmacMacAddresses1Low_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEmacMacAddresses1Low_t; #define REG_DEVICE_EMAC_MAC_ADDRESSES_2_HIGH ((volatile APE_DEVICE_H_uint32_t*)0xa0040420) /* Upper 2-bytes of this node's MAC address. */ /** @brief Register definition for @ref DEVICE_t.EmacMacAddresses2High. */ typedef register_container RegDEVICEEmacMacAddresses2High_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EmacMacAddresses2High"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEmacMacAddresses2High_t() { /** @brief constructor for @ref DEVICE_t.EmacMacAddresses2High. */ r32.setName("EmacMacAddresses2High"); } RegDEVICEEmacMacAddresses2High_t& operator=(const RegDEVICEEmacMacAddresses2High_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEmacMacAddresses2High_t; #define REG_DEVICE_EMAC_MAC_ADDRESSES_2_LOW ((volatile APE_DEVICE_H_uint32_t*)0xa0040424) /* Lower 4-byte of this node's MAC address. */ /** @brief Register definition for @ref DEVICE_t.EmacMacAddresses2Low. */ typedef register_container RegDEVICEEmacMacAddresses2Low_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EmacMacAddresses2Low"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEmacMacAddresses2Low_t() { /** @brief constructor for @ref DEVICE_t.EmacMacAddresses2Low. */ r32.setName("EmacMacAddresses2Low"); } RegDEVICEEmacMacAddresses2Low_t& operator=(const RegDEVICEEmacMacAddresses2Low_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEmacMacAddresses2Low_t; #define REG_DEVICE_EMAC_MAC_ADDRESSES_3_HIGH ((volatile APE_DEVICE_H_uint32_t*)0xa0040428) /* Upper 2-bytes of this node's MAC address. */ /** @brief Register definition for @ref DEVICE_t.EmacMacAddresses3High. */ typedef register_container RegDEVICEEmacMacAddresses3High_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EmacMacAddresses3High"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEmacMacAddresses3High_t() { /** @brief constructor for @ref DEVICE_t.EmacMacAddresses3High. */ r32.setName("EmacMacAddresses3High"); } RegDEVICEEmacMacAddresses3High_t& operator=(const RegDEVICEEmacMacAddresses3High_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEmacMacAddresses3High_t; #define REG_DEVICE_EMAC_MAC_ADDRESSES_3_LOW ((volatile APE_DEVICE_H_uint32_t*)0xa004042c) /* Lower 4-byte of this node's MAC address. */ /** @brief Register definition for @ref DEVICE_t.EmacMacAddresses3Low. */ typedef register_container RegDEVICEEmacMacAddresses3Low_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EmacMacAddresses3Low"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEmacMacAddresses3Low_t() { /** @brief constructor for @ref DEVICE_t.EmacMacAddresses3Low. */ r32.setName("EmacMacAddresses3Low"); } RegDEVICEEmacMacAddresses3Low_t& operator=(const RegDEVICEEmacMacAddresses3Low_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEmacMacAddresses3Low_t; #define REG_DEVICE_WOL_PATTERN_POINTER ((volatile APE_DEVICE_H_uint32_t*)0xa0040430) /* Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */ /** @brief Register definition for @ref DEVICE_t.WolPatternPointer. */ typedef register_container RegDEVICEWolPatternPointer_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "WolPatternPointer"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEWolPatternPointer_t() { /** @brief constructor for @ref DEVICE_t.WolPatternPointer. */ r32.setName("WolPatternPointer"); } RegDEVICEWolPatternPointer_t& operator=(const RegDEVICEWolPatternPointer_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEWolPatternPointer_t; #define REG_DEVICE_WOL_PATTERN_CFG ((volatile APE_DEVICE_H_uint32_t*)0xa0040434) /* */ /** @brief Register definition for @ref DEVICE_t.WolPatternCfg. */ typedef register_container RegDEVICEWolPatternCfg_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "WolPatternCfg"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEWolPatternCfg_t() { /** @brief constructor for @ref DEVICE_t.WolPatternCfg. */ r32.setName("WolPatternCfg"); } RegDEVICEWolPatternCfg_t& operator=(const RegDEVICEWolPatternCfg_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEWolPatternCfg_t; #define REG_DEVICE_438 ((volatile APE_DEVICE_H_uint32_t*)0xa0040438) /* Unknown register. */ /** @brief Register definition for @ref DEVICE_t.438. */ typedef register_container RegDEVICE438_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "438"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE438_t() { /** @brief constructor for @ref DEVICE_t.438. */ r32.setName("438"); } RegDEVICE438_t& operator=(const RegDEVICE438_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE438_t; #define REG_DEVICE_MTU_SIZE ((volatile APE_DEVICE_H_uint32_t*)0xa004043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */ #define DEVICE_MTU_SIZE_MTU_SHIFT 0u #define DEVICE_MTU_SIZE_MTU_MASK 0xffffu #define GET_DEVICE_MTU_SIZE_MTU(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_MTU_SIZE_MTU(__val__) (((__val__) << 0u) & 0xffffu) /** @brief Register definition for @ref DEVICE_t.MtuSize. */ typedef register_container RegDEVICEMtuSize_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MTU, 0, 16) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) /** @brief 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MTU, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "MtuSize"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEMtuSize_t() { /** @brief constructor for @ref DEVICE_t.MtuSize. */ r32.setName("MtuSize"); bits.MTU.setBaseRegister(&r32); bits.MTU.setName("MTU"); } RegDEVICEMtuSize_t& operator=(const RegDEVICEMtuSize_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEMtuSize_t; #define REG_DEVICE_MII_COMMUNICATION ((volatile APE_DEVICE_H_uint32_t*)0xa004044c) /* */ #define DEVICE_MII_COMMUNICATION_TRANSACTION_DATA_SHIFT 0u #define DEVICE_MII_COMMUNICATION_TRANSACTION_DATA_MASK 0xffffu #define GET_DEVICE_MII_COMMUNICATION_TRANSACTION_DATA(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_MII_COMMUNICATION_TRANSACTION_DATA(__val__) (((__val__) << 0u) & 0xffffu) #define DEVICE_MII_COMMUNICATION_REGISTER_ADDRESS_SHIFT 16u #define DEVICE_MII_COMMUNICATION_REGISTER_ADDRESS_MASK 0x1f0000u #define GET_DEVICE_MII_COMMUNICATION_REGISTER_ADDRESS(__reg__) (((__reg__) & 0x1f0000) >> 16u) #define SET_DEVICE_MII_COMMUNICATION_REGISTER_ADDRESS(__val__) (((__val__) << 16u) & 0x1f0000u) #define DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SHIFT 21u #define DEVICE_MII_COMMUNICATION_PHY_ADDRESS_MASK 0x3e00000u #define GET_DEVICE_MII_COMMUNICATION_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e00000) >> 21u) #define SET_DEVICE_MII_COMMUNICATION_PHY_ADDRESS(__val__) (((__val__) << 21u) & 0x3e00000u) #define DEVICE_MII_COMMUNICATION_PHY_ADDRESS_PHY_0 0x1u #define DEVICE_MII_COMMUNICATION_PHY_ADDRESS_PHY_1 0x2u #define DEVICE_MII_COMMUNICATION_PHY_ADDRESS_PHY_2 0x3u #define DEVICE_MII_COMMUNICATION_PHY_ADDRESS_PHY_3 0x4u #define DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0 0x8u #define DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SGMII_1 0x9u #define DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SGMII_2 0xau #define DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SGMII_3 0xbu #define DEVICE_MII_COMMUNICATION_COMMAND_SHIFT 26u #define DEVICE_MII_COMMUNICATION_COMMAND_MASK 0xc000000u #define GET_DEVICE_MII_COMMUNICATION_COMMAND(__reg__) (((__reg__) & 0xc000000) >> 26u) #define SET_DEVICE_MII_COMMUNICATION_COMMAND(__val__) (((__val__) << 26u) & 0xc000000u) #define DEVICE_MII_COMMUNICATION_COMMAND_WRITE 0x1u #define DEVICE_MII_COMMUNICATION_COMMAND_READ 0x2u #define DEVICE_MII_COMMUNICATION_READ_FAILED_SHIFT 28u #define DEVICE_MII_COMMUNICATION_READ_FAILED_MASK 0x10000000u #define GET_DEVICE_MII_COMMUNICATION_READ_FAILED(__reg__) (((__reg__) & 0x10000000) >> 28u) #define SET_DEVICE_MII_COMMUNICATION_READ_FAILED(__val__) (((__val__) << 28u) & 0x10000000u) #define DEVICE_MII_COMMUNICATION_START_DIV_BUSY_SHIFT 29u #define DEVICE_MII_COMMUNICATION_START_DIV_BUSY_MASK 0x20000000u #define GET_DEVICE_MII_COMMUNICATION_START_DIV_BUSY(__reg__) (((__reg__) & 0x20000000) >> 29u) #define SET_DEVICE_MII_COMMUNICATION_START_DIV_BUSY(__val__) (((__val__) << 29u) & 0x20000000u) /** @brief Register definition for @ref DEVICE_t.MiiCommunication. */ typedef register_container RegDEVICEMiiCommunication_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief When configured for a write command, the data stored at this location is written to the PHY at the specified PHY and register address. During a read command, the data returned by the PHY is stored at this location. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TransactionData, 0, 16) /** @brief Address of the register to be read or written. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RegisterAddress, 16, 5) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PHYAddress, 21, 5) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Command, 26, 2) /** @brief When set, the transceiver device did not drive the bus during the attempted read transaction. Valid after the Start/Busy bit is cleared. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ReadFailed, 28, 1) /** @brief Set this bit to start a transaction. While it is high, it indicates that the current transaction is still ongoing. If enabled, generates an attention via EMAC Status Register MI Completion bit (bit 22). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Start_DIV_Busy, 29, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_30, 30, 2) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_30, 30, 2) /** @brief Set this bit to start a transaction. While it is high, it indicates that the current transaction is still ongoing. If enabled, generates an attention via EMAC Status Register MI Completion bit (bit 22). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Start_DIV_Busy, 29, 1) /** @brief When set, the transceiver device did not drive the bus during the attempted read transaction. Valid after the Start/Busy bit is cleared. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ReadFailed, 28, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Command, 26, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PHYAddress, 21, 5) /** @brief Address of the register to be read or written. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RegisterAddress, 16, 5) /** @brief When configured for a write command, the data stored at this location is written to the PHY at the specified PHY and register address. During a read command, the data returned by the PHY is stored at this location. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TransactionData, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "MiiCommunication"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEMiiCommunication_t() { /** @brief constructor for @ref DEVICE_t.MiiCommunication. */ r32.setName("MiiCommunication"); bits.TransactionData.setBaseRegister(&r32); bits.TransactionData.setName("TransactionData"); bits.RegisterAddress.setBaseRegister(&r32); bits.RegisterAddress.setName("RegisterAddress"); bits.PHYAddress.setBaseRegister(&r32); bits.PHYAddress.setName("PHYAddress"); bits.PHYAddress.addEnum("PHY 0", 0x1); bits.PHYAddress.addEnum("PHY 1", 0x2); bits.PHYAddress.addEnum("PHY 2", 0x3); bits.PHYAddress.addEnum("PHY 3", 0x4); bits.PHYAddress.addEnum("SGMII 0", 0x8); bits.PHYAddress.addEnum("SGMII 1", 0x9); bits.PHYAddress.addEnum("SGMII 2", 0xa); bits.PHYAddress.addEnum("SGMII 3", 0xb); bits.Command.setBaseRegister(&r32); bits.Command.setName("Command"); bits.Command.addEnum("Write", 0x1); bits.Command.addEnum("Read", 0x2); bits.ReadFailed.setBaseRegister(&r32); bits.ReadFailed.setName("ReadFailed"); bits.Start_DIV_Busy.setBaseRegister(&r32); bits.Start_DIV_Busy.setName("Start_DIV_Busy"); } RegDEVICEMiiCommunication_t& operator=(const RegDEVICEMiiCommunication_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEMiiCommunication_t; #define REG_DEVICE_MII_MODE ((volatile APE_DEVICE_H_uint32_t*)0xa0040454) /* */ #define DEVICE_MII_MODE_PHY_ADDRESS_SHIFT 5u #define DEVICE_MII_MODE_PHY_ADDRESS_MASK 0x3e0u #define GET_DEVICE_MII_MODE_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e0) >> 5u) #define SET_DEVICE_MII_MODE_PHY_ADDRESS(__val__) (((__val__) << 5u) & 0x3e0u) #define DEVICE_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_SHIFT 15u #define DEVICE_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_MASK 0x8000u #define GET_DEVICE_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__reg__) (((__reg__) & 0x8000) >> 15u) #define SET_DEVICE_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__val__) (((__val__) << 15u) & 0x8000u) #define DEVICE_MII_MODE_MII_CLOCK_COUNT_SHIFT 16u #define DEVICE_MII_MODE_MII_CLOCK_COUNT_MASK 0x1f0000u #define GET_DEVICE_MII_MODE_MII_CLOCK_COUNT(__reg__) (((__reg__) & 0x1f0000) >> 16u) #define SET_DEVICE_MII_MODE_MII_CLOCK_COUNT(__val__) (((__val__) << 16u) & 0x1f0000u) /** @brief Register definition for @ref DEVICE_t.MiiMode. */ typedef register_container RegDEVICEMiiMode_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_0, 0, 5) /** @brief This field specifies the PHY Address. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PHYAddress, 5, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_14_10, 10, 5) /** @brief Enable ~500Khz constant MII management interface (MDIO/MDC) frequency regardless core clock frequency. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ConstantMDIO_DIV_MDCClockSpeed, 15, 1) /** @brief Counter to divide CORE_CLK (62.5 MHz) to generate the MI clock. CORE_CLK/2/(MII Clock Count + 1). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MIIClockCount, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Counter to divide CORE_CLK (62.5 MHz) to generate the MI clock. CORE_CLK/2/(MII Clock Count + 1). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MIIClockCount, 16, 5) /** @brief Enable ~500Khz constant MII management interface (MDIO/MDC) frequency regardless core clock frequency. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ConstantMDIO_DIV_MDCClockSpeed, 15, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_14_10, 10, 5) /** @brief This field specifies the PHY Address. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PHYAddress, 5, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_0, 0, 5) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "MiiMode"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEMiiMode_t() { /** @brief constructor for @ref DEVICE_t.MiiMode. */ r32.setName("MiiMode"); bits.PHYAddress.setBaseRegister(&r32); bits.PHYAddress.setName("PHYAddress"); bits.ConstantMDIO_DIV_MDCClockSpeed.setBaseRegister(&r32); bits.ConstantMDIO_DIV_MDCClockSpeed.setName("ConstantMDIO_DIV_MDCClockSpeed"); bits.MIIClockCount.setBaseRegister(&r32); bits.MIIClockCount.setName("MIIClockCount"); } RegDEVICEMiiMode_t& operator=(const RegDEVICEMiiMode_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEMiiMode_t; #define REG_DEVICE_TRANSMIT_MAC_MODE ((volatile APE_DEVICE_H_uint32_t*)0xa004045c) /* */ #define DEVICE_TRANSMIT_MAC_MODE_RESET_SHIFT 0u #define DEVICE_TRANSMIT_MAC_MODE_RESET_MASK 0x1u #define GET_DEVICE_TRANSMIT_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_TRANSMIT_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_TDE_SHIFT 1u #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_TDE_MASK 0x2u #define GET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_TDE(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_TDE(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_SHIFT 4u #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_MASK 0x10u #define GET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_SHIFT 5u #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_MASK 0x20u #define GET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__val__) (((__val__) << 5u) & 0x20u) #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_SHIFT 6u #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_MASK 0x40u #define GET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__reg__) (((__reg__) & 0x40) >> 6u) #define SET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__val__) (((__val__) << 6u) & 0x40u) #define DEVICE_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_SHIFT 7u #define DEVICE_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_MASK 0x80u #define GET_DEVICE_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) #define SET_DEVICE_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__val__) (((__val__) << 7u) & 0x80u) #define DEVICE_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_SHIFT 8u #define DEVICE_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_MASK 0x100u #define GET_DEVICE_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_SHIFT 9u #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_MASK 0x200u #define GET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__reg__) (((__reg__) & 0x200) >> 9u) #define SET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__val__) (((__val__) << 9u) & 0x200u) #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_SHIFT 10u #define DEVICE_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_MASK 0x400u #define GET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__reg__) (((__reg__) & 0x400) >> 10u) #define SET_DEVICE_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__val__) (((__val__) << 10u) & 0x400u) /** @brief Register definition for @ref DEVICE_t.TransmitMacMode. */ typedef register_container RegDEVICETransmitMacMode_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief When this bit is set to 1, the Transmit MAC state machine will be reset. This is a self-clearing bit. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Reset, 0, 1) /** @brief Used to be enable TDE in legacy-same purpose. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTDE, 1, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_3_2, 2, 2) /** @brief MAC will send 802.3x flow control frames. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableFlowControl, 4, 1) /** @brief MAC will use larger than normal back-off algorithm. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableBigBackoff, 5, 1) /** @brief When set, the Pause time value set in the transmitted PAUSE frames is 0xFFFF. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableLongPause, 6, 1) /** @brief When set, transmission of packets by the MAC is enabled only when link is up. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkAwareEnable, 7, 1) /** @brief When set, TXMBUF corruption lockup fix is enabled. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TxMBUFCorruptionLockupFixEnable, 8, 1) /** @brief A value 1 enables the TX ESP offload feature. When 0, offloaded ESP packet gets dropped. This value must be static. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTXESPOffload, 9, 1) /** @brief A value 1 enables the TX AH offload feature. When 0, offloaded AH packet gets dropped. This value must be static. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTXAHOffload, 10, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_11, 11, 21) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_11, 11, 21) /** @brief A value 1 enables the TX AH offload feature. When 0, offloaded AH packet gets dropped. This value must be static. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTXAHOffload, 10, 1) /** @brief A value 1 enables the TX ESP offload feature. When 0, offloaded ESP packet gets dropped. This value must be static. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTXESPOffload, 9, 1) /** @brief When set, TXMBUF corruption lockup fix is enabled. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TxMBUFCorruptionLockupFixEnable, 8, 1) /** @brief When set, transmission of packets by the MAC is enabled only when link is up. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkAwareEnable, 7, 1) /** @brief When set, the Pause time value set in the transmitted PAUSE frames is 0xFFFF. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableLongPause, 6, 1) /** @brief MAC will use larger than normal back-off algorithm. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableBigBackoff, 5, 1) /** @brief MAC will send 802.3x flow control frames. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableFlowControl, 4, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_3_2, 2, 2) /** @brief Used to be enable TDE in legacy-same purpose. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableTDE, 1, 1) /** @brief When this bit is set to 1, the Transmit MAC state machine will be reset. This is a self-clearing bit. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Reset, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "TransmitMacMode"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICETransmitMacMode_t() { /** @brief constructor for @ref DEVICE_t.TransmitMacMode. */ r32.setName("TransmitMacMode"); bits.Reset.setBaseRegister(&r32); bits.Reset.setName("Reset"); bits.EnableTDE.setBaseRegister(&r32); bits.EnableTDE.setName("EnableTDE"); bits.EnableFlowControl.setBaseRegister(&r32); bits.EnableFlowControl.setName("EnableFlowControl"); bits.EnableBigBackoff.setBaseRegister(&r32); bits.EnableBigBackoff.setName("EnableBigBackoff"); bits.EnableLongPause.setBaseRegister(&r32); bits.EnableLongPause.setName("EnableLongPause"); bits.LinkAwareEnable.setBaseRegister(&r32); bits.LinkAwareEnable.setName("LinkAwareEnable"); bits.TxMBUFCorruptionLockupFixEnable.setBaseRegister(&r32); bits.TxMBUFCorruptionLockupFixEnable.setName("TxMBUFCorruptionLockupFixEnable"); bits.EnableTXESPOffload.setBaseRegister(&r32); bits.EnableTXESPOffload.setName("EnableTXESPOffload"); bits.EnableTXAHOffload.setBaseRegister(&r32); bits.EnableTXAHOffload.setName("EnableTXAHOffload"); } RegDEVICETransmitMacMode_t& operator=(const RegDEVICETransmitMacMode_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICETransmitMacMode_t; #define REG_DEVICE_TRANSMIT_MAC_STATUS ((volatile APE_DEVICE_H_uint32_t*)0xa0040460) /* */ #define DEVICE_TRANSMIT_MAC_STATUS_XOFFED_SHIFT 0u #define DEVICE_TRANSMIT_MAC_STATUS_XOFFED_MASK 0x1u #define GET_DEVICE_TRANSMIT_MAC_STATUS_XOFFED(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_TRANSMIT_MAC_STATUS_XOFFED(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_TRANSMIT_MAC_STATUS_SENT_XOFF_SHIFT 1u #define DEVICE_TRANSMIT_MAC_STATUS_SENT_XOFF_MASK 0x2u #define GET_DEVICE_TRANSMIT_MAC_STATUS_SENT_XOFF(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_TRANSMIT_MAC_STATUS_SENT_XOFF(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_TRANSMIT_MAC_STATUS_SENT_XON_SHIFT 2u #define DEVICE_TRANSMIT_MAC_STATUS_SENT_XON_MASK 0x4u #define GET_DEVICE_TRANSMIT_MAC_STATUS_SENT_XON(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_TRANSMIT_MAC_STATUS_SENT_XON(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_TRANSMIT_MAC_STATUS_LINK_UP_SHIFT 3u #define DEVICE_TRANSMIT_MAC_STATUS_LINK_UP_MASK 0x8u #define GET_DEVICE_TRANSMIT_MAC_STATUS_LINK_UP(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_TRANSMIT_MAC_STATUS_LINK_UP(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_TRANSMIT_MAC_STATUS_ODI_UNDERRUN_SHIFT 4u #define DEVICE_TRANSMIT_MAC_STATUS_ODI_UNDERRUN_MASK 0x10u #define GET_DEVICE_TRANSMIT_MAC_STATUS_ODI_UNDERRUN(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_TRANSMIT_MAC_STATUS_ODI_UNDERRUN(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_TRANSMIT_MAC_STATUS_ODI_OVERRUN_SHIFT 5u #define DEVICE_TRANSMIT_MAC_STATUS_ODI_OVERRUN_MASK 0x20u #define GET_DEVICE_TRANSMIT_MAC_STATUS_ODI_OVERRUN(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_TRANSMIT_MAC_STATUS_ODI_OVERRUN(__val__) (((__val__) << 5u) & 0x20u) /** @brief Register definition for @ref DEVICE_t.TransmitMacStatus. */ typedef register_container RegDEVICETransmitMacStatus_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, XOFFED, 0, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SentXOFF, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SentXON, 2, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkUp, 3, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ODIUnderrun, 4, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ODIOverrun, 5, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_6, 6, 26) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_6, 6, 26) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ODIOverrun, 5, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ODIUnderrun, 4, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkUp, 3, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SentXON, 2, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SentXOFF, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, XOFFED, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "TransmitMacStatus"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICETransmitMacStatus_t() { /** @brief constructor for @ref DEVICE_t.TransmitMacStatus. */ r32.setName("TransmitMacStatus"); bits.XOFFED.setBaseRegister(&r32); bits.XOFFED.setName("XOFFED"); bits.SentXOFF.setBaseRegister(&r32); bits.SentXOFF.setName("SentXOFF"); bits.SentXON.setBaseRegister(&r32); bits.SentXON.setName("SentXON"); bits.LinkUp.setBaseRegister(&r32); bits.LinkUp.setName("LinkUp"); bits.ODIUnderrun.setBaseRegister(&r32); bits.ODIUnderrun.setName("ODIUnderrun"); bits.ODIOverrun.setBaseRegister(&r32); bits.ODIOverrun.setName("ODIOverrun"); } RegDEVICETransmitMacStatus_t& operator=(const RegDEVICETransmitMacStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICETransmitMacStatus_t; #define REG_DEVICE_TRANSMIT_MAC_LENGTHS ((volatile APE_DEVICE_H_uint32_t*)0xa0040464) /* */ #define DEVICE_TRANSMIT_MAC_LENGTHS_SLOT_TIME_LENGTH_SHIFT 0u #define DEVICE_TRANSMIT_MAC_LENGTHS_SLOT_TIME_LENGTH_MASK 0xffu #define GET_DEVICE_TRANSMIT_MAC_LENGTHS_SLOT_TIME_LENGTH(__reg__) (((__reg__) & 0xff) >> 0u) #define SET_DEVICE_TRANSMIT_MAC_LENGTHS_SLOT_TIME_LENGTH(__val__) (((__val__) << 0u) & 0xffu) #define DEVICE_TRANSMIT_MAC_LENGTHS_IPG_LENGTH_SHIFT 8u #define DEVICE_TRANSMIT_MAC_LENGTHS_IPG_LENGTH_MASK 0xf00u #define GET_DEVICE_TRANSMIT_MAC_LENGTHS_IPG_LENGTH(__reg__) (((__reg__) & 0xf00) >> 8u) #define SET_DEVICE_TRANSMIT_MAC_LENGTHS_IPG_LENGTH(__val__) (((__val__) << 8u) & 0xf00u) #define DEVICE_TRANSMIT_MAC_LENGTHS_IPG_CRS_LENGTH_SHIFT 12u #define DEVICE_TRANSMIT_MAC_LENGTHS_IPG_CRS_LENGTH_MASK 0x3000u #define GET_DEVICE_TRANSMIT_MAC_LENGTHS_IPG_CRS_LENGTH(__reg__) (((__reg__) & 0x3000) >> 12u) #define SET_DEVICE_TRANSMIT_MAC_LENGTHS_IPG_CRS_LENGTH(__val__) (((__val__) << 12u) & 0x3000u) #define DEVICE_TRANSMIT_MAC_LENGTHS_HTX2B_JUMBO_FRAME_LENGTH_SHIFT 16u #define DEVICE_TRANSMIT_MAC_LENGTHS_HTX2B_JUMBO_FRAME_LENGTH_MASK 0xff0000u #define GET_DEVICE_TRANSMIT_MAC_LENGTHS_HTX2B_JUMBO_FRAME_LENGTH(__reg__) (((__reg__) & 0xff0000) >> 16u) #define SET_DEVICE_TRANSMIT_MAC_LENGTHS_HTX2B_JUMBO_FRAME_LENGTH(__val__) (((__val__) << 16u) & 0xff0000u) #define DEVICE_TRANSMIT_MAC_LENGTHS_HTX2B_COUNT_DOWN_VALUE_SHIFT 24u #define DEVICE_TRANSMIT_MAC_LENGTHS_HTX2B_COUNT_DOWN_VALUE_MASK 0xff000000u #define GET_DEVICE_TRANSMIT_MAC_LENGTHS_HTX2B_COUNT_DOWN_VALUE(__reg__) (((__reg__) & 0xff000000) >> 24u) #define SET_DEVICE_TRANSMIT_MAC_LENGTHS_HTX2B_COUNT_DOWN_VALUE(__val__) (((__val__) << 24u) & 0xff000000u) /** @brief Register definition for @ref DEVICE_t.TransmitMacLengths. */ typedef register_container RegDEVICETransmitMacLengths_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief When multiplied by 2, this field indicates the number of bytes in the slot time. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SlotTimeLength, 0, 8) /** @brief When multiplied by 2, this field indicates the number of bytes in the entire IPG. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, IPGLength, 8, 4) /** @brief When multiplied by 2, this field indicates the number of bytes from the end of the interpacket gap (IPG) during which incoming carrier is ignored. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, IPGCRSLength, 12, 2) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_14, 14, 2) /** @brief This value + 1500 is used by hardware as the maximum standard frame length for HTX2B. A frame with a length larger than that is a jumbo frame for HTX2B. The length is the effective length of a composed L2 frame as seen from the wire, including the L2 header, L2 payload, and the FCS (CRC) field. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HTX2BJumboFrameLength, 16, 8) /** @brief HT2XB Count Down Value */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HTX2BCountDownValue, 24, 8) #elif defined(__BIG_ENDIAN__) /** @brief HT2XB Count Down Value */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HTX2BCountDownValue, 24, 8) /** @brief This value + 1500 is used by hardware as the maximum standard frame length for HTX2B. A frame with a length larger than that is a jumbo frame for HTX2B. The length is the effective length of a composed L2 frame as seen from the wire, including the L2 header, L2 payload, and the FCS (CRC) field. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HTX2BJumboFrameLength, 16, 8) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_14, 14, 2) /** @brief When multiplied by 2, this field indicates the number of bytes from the end of the interpacket gap (IPG) during which incoming carrier is ignored. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, IPGCRSLength, 12, 2) /** @brief When multiplied by 2, this field indicates the number of bytes in the entire IPG. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, IPGLength, 8, 4) /** @brief When multiplied by 2, this field indicates the number of bytes in the slot time. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SlotTimeLength, 0, 8) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "TransmitMacLengths"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICETransmitMacLengths_t() { /** @brief constructor for @ref DEVICE_t.TransmitMacLengths. */ r32.setName("TransmitMacLengths"); bits.SlotTimeLength.setBaseRegister(&r32); bits.SlotTimeLength.setName("SlotTimeLength"); bits.IPGLength.setBaseRegister(&r32); bits.IPGLength.setName("IPGLength"); bits.IPGCRSLength.setBaseRegister(&r32); bits.IPGCRSLength.setName("IPGCRSLength"); bits.HTX2BJumboFrameLength.setBaseRegister(&r32); bits.HTX2BJumboFrameLength.setName("HTX2BJumboFrameLength"); bits.HTX2BCountDownValue.setBaseRegister(&r32); bits.HTX2BCountDownValue.setName("HTX2BCountDownValue"); } RegDEVICETransmitMacLengths_t& operator=(const RegDEVICETransmitMacLengths_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICETransmitMacLengths_t; #define REG_DEVICE_RECEIVE_MAC_MODE ((volatile APE_DEVICE_H_uint32_t*)0xa0040468) /* */ #define DEVICE_RECEIVE_MAC_MODE_RESET_SHIFT 0u #define DEVICE_RECEIVE_MAC_MODE_RESET_MASK 0x1u #define GET_DEVICE_RECEIVE_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_RECEIVE_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_RECEIVE_MAC_MODE_ENABLE_SHIFT 1u #define DEVICE_RECEIVE_MAC_MODE_ENABLE_MASK 0x2u #define GET_DEVICE_RECEIVE_MAC_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_RECEIVE_MAC_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_SHIFT 8u #define DEVICE_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_MASK 0x100u #define GET_DEVICE_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__val__) (((__val__) << 8u) & 0x100u) #define DEVICE_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_SHIFT 25u #define DEVICE_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_MASK 0x2000000u #define GET_DEVICE_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x2000000) >> 25u) #define SET_DEVICE_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__val__) (((__val__) << 25u) & 0x2000000u) /** @brief Register definition for @ref DEVICE_t.ReceiveMacMode. */ typedef register_container RegDEVICEReceiveMacMode_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief When this bit is set to 1, the Receive MAC state machine will be reset. This is a self-clearing bit. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Reset, 0, 1) /** @brief This bit controls whether the Receive MAC state machine is active or not. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Enable, 1, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_2, 2, 6) /** @brief When set, no source address or MC hashing checking will be performed on incoming frames. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PromiscuousMode, 8, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_24_9, 9, 16) /** @brief When set, no source address or MC hashing checking will be performed on incoming frames on APE filter path. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEPromiscuousMode, 25, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_26, 26, 6) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_26, 26, 6) /** @brief When set, no source address or MC hashing checking will be performed on incoming frames on APE filter path. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEPromiscuousMode, 25, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_24_9, 9, 16) /** @brief When set, no source address or MC hashing checking will be performed on incoming frames. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PromiscuousMode, 8, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_2, 2, 6) /** @brief This bit controls whether the Receive MAC state machine is active or not. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Enable, 1, 1) /** @brief When this bit is set to 1, the Receive MAC state machine will be reset. This is a self-clearing bit. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Reset, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ReceiveMacMode"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEReceiveMacMode_t() { /** @brief constructor for @ref DEVICE_t.ReceiveMacMode. */ r32.setName("ReceiveMacMode"); bits.Reset.setBaseRegister(&r32); bits.Reset.setName("Reset"); bits.Enable.setBaseRegister(&r32); bits.Enable.setName("Enable"); bits.PromiscuousMode.setBaseRegister(&r32); bits.PromiscuousMode.setName("PromiscuousMode"); bits.APEPromiscuousMode.setBaseRegister(&r32); bits.APEPromiscuousMode.setName("APEPromiscuousMode"); } RegDEVICEReceiveMacMode_t& operator=(const RegDEVICEReceiveMacMode_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEReceiveMacMode_t; #define REG_DEVICE_RECEIVE_MAC_STATUS ((volatile APE_DEVICE_H_uint32_t*)0xa004046c) /* */ #define DEVICE_RECEIVE_MAC_STATUS_REMOTE_TX_XOFFED_SHIFT 0u #define DEVICE_RECEIVE_MAC_STATUS_REMOTE_TX_XOFFED_MASK 0x1u #define GET_DEVICE_RECEIVE_MAC_STATUS_REMOTE_TX_XOFFED(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_RECEIVE_MAC_STATUS_REMOTE_TX_XOFFED(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_RECEIVE_MAC_STATUS_XOFF_RECEIVED_SHIFT 1u #define DEVICE_RECEIVE_MAC_STATUS_XOFF_RECEIVED_MASK 0x2u #define GET_DEVICE_RECEIVE_MAC_STATUS_XOFF_RECEIVED(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_RECEIVE_MAC_STATUS_XOFF_RECEIVED(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_RECEIVE_MAC_STATUS_XON_RECEIVED_SHIFT 2u #define DEVICE_RECEIVE_MAC_STATUS_XON_RECEIVED_MASK 0x4u #define GET_DEVICE_RECEIVE_MAC_STATUS_XON_RECEIVED(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_RECEIVE_MAC_STATUS_XON_RECEIVED(__val__) (((__val__) << 2u) & 0x4u) /** @brief Register definition for @ref DEVICE_t.ReceiveMacStatus. */ typedef register_container RegDEVICEReceiveMacStatus_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RemoteTXXOFFED, 0, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, XOFFReceived, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, XONReceived, 2, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_3, 3, 29) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_3, 3, 29) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, XONReceived, 2, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, XOFFReceived, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RemoteTXXOFFED, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ReceiveMacStatus"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEReceiveMacStatus_t() { /** @brief constructor for @ref DEVICE_t.ReceiveMacStatus. */ r32.setName("ReceiveMacStatus"); bits.RemoteTXXOFFED.setBaseRegister(&r32); bits.RemoteTXXOFFED.setName("RemoteTXXOFFED"); bits.XOFFReceived.setBaseRegister(&r32); bits.XOFFReceived.setName("XOFFReceived"); bits.XONReceived.setBaseRegister(&r32); bits.XONReceived.setName("XONReceived"); } RegDEVICEReceiveMacStatus_t& operator=(const RegDEVICEReceiveMacStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEReceiveMacStatus_t; #define REG_DEVICE_PERFECT_MATCH1_HIGH ((volatile APE_DEVICE_H_uint32_t*)0xa0040540) /* */ #define DEVICE_PERFECT_MATCH1_HIGH_HIGH_SHIFT 0u #define DEVICE_PERFECT_MATCH1_HIGH_HIGH_MASK 0xffffu #define GET_DEVICE_PERFECT_MATCH1_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_PERFECT_MATCH1_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) /** @brief Register definition for @ref DEVICE_t.PerfectMatch1High. */ typedef register_container RegDEVICEPerfectMatch1High_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Upper two bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, High, 0, 16) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) /** @brief Upper two bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, High, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PerfectMatch1High"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPerfectMatch1High_t() { /** @brief constructor for @ref DEVICE_t.PerfectMatch1High. */ r32.setName("PerfectMatch1High"); bits.High.setBaseRegister(&r32); bits.High.setName("High"); } RegDEVICEPerfectMatch1High_t& operator=(const RegDEVICEPerfectMatch1High_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPerfectMatch1High_t; #define REG_DEVICE_PERFECT_MATCH1_LOW ((volatile APE_DEVICE_H_uint32_t*)0xa0040544) /* */ #define DEVICE_PERFECT_MATCH1_LOW_LOW_SHIFT 0u #define DEVICE_PERFECT_MATCH1_LOW_LOW_MASK 0xffffffffu #define GET_DEVICE_PERFECT_MATCH1_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) #define SET_DEVICE_PERFECT_MATCH1_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) /** @brief Register definition for @ref DEVICE_t.PerfectMatch1Low. */ typedef register_container RegDEVICEPerfectMatch1Low_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Lower four bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Low, 0, 32) #elif defined(__BIG_ENDIAN__) /** @brief Lower four bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Low, 0, 32) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PerfectMatch1Low"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPerfectMatch1Low_t() { /** @brief constructor for @ref DEVICE_t.PerfectMatch1Low. */ r32.setName("PerfectMatch1Low"); bits.Low.setBaseRegister(&r32); bits.Low.setName("Low"); } RegDEVICEPerfectMatch1Low_t& operator=(const RegDEVICEPerfectMatch1Low_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPerfectMatch1Low_t; #define REG_DEVICE_PERFECT_MATCH2_HIGH ((volatile APE_DEVICE_H_uint32_t*)0xa0040548) /* */ #define DEVICE_PERFECT_MATCH2_HIGH_HIGH_SHIFT 0u #define DEVICE_PERFECT_MATCH2_HIGH_HIGH_MASK 0xffffu #define GET_DEVICE_PERFECT_MATCH2_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_PERFECT_MATCH2_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) /** @brief Register definition for @ref DEVICE_t.PerfectMatch2High. */ typedef register_container RegDEVICEPerfectMatch2High_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Upper two bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, High, 0, 16) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) /** @brief Upper two bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, High, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PerfectMatch2High"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPerfectMatch2High_t() { /** @brief constructor for @ref DEVICE_t.PerfectMatch2High. */ r32.setName("PerfectMatch2High"); bits.High.setBaseRegister(&r32); bits.High.setName("High"); } RegDEVICEPerfectMatch2High_t& operator=(const RegDEVICEPerfectMatch2High_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPerfectMatch2High_t; #define REG_DEVICE_PERFECT_MATCH2_LOW ((volatile APE_DEVICE_H_uint32_t*)0xa004054c) /* */ #define DEVICE_PERFECT_MATCH2_LOW_LOW_SHIFT 0u #define DEVICE_PERFECT_MATCH2_LOW_LOW_MASK 0xffffffffu #define GET_DEVICE_PERFECT_MATCH2_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) #define SET_DEVICE_PERFECT_MATCH2_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) /** @brief Register definition for @ref DEVICE_t.PerfectMatch2Low. */ typedef register_container RegDEVICEPerfectMatch2Low_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Lower four bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Low, 0, 32) #elif defined(__BIG_ENDIAN__) /** @brief Lower four bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Low, 0, 32) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PerfectMatch2Low"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPerfectMatch2Low_t() { /** @brief constructor for @ref DEVICE_t.PerfectMatch2Low. */ r32.setName("PerfectMatch2Low"); bits.Low.setBaseRegister(&r32); bits.Low.setName("Low"); } RegDEVICEPerfectMatch2Low_t& operator=(const RegDEVICEPerfectMatch2Low_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPerfectMatch2Low_t; #define REG_DEVICE_PERFECT_MATCH3_HIGH ((volatile APE_DEVICE_H_uint32_t*)0xa0040550) /* */ #define DEVICE_PERFECT_MATCH3_HIGH_HIGH_SHIFT 0u #define DEVICE_PERFECT_MATCH3_HIGH_HIGH_MASK 0xffffu #define GET_DEVICE_PERFECT_MATCH3_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_PERFECT_MATCH3_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) /** @brief Register definition for @ref DEVICE_t.PerfectMatch3High. */ typedef register_container RegDEVICEPerfectMatch3High_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Upper two bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, High, 0, 16) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) /** @brief Upper two bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, High, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PerfectMatch3High"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPerfectMatch3High_t() { /** @brief constructor for @ref DEVICE_t.PerfectMatch3High. */ r32.setName("PerfectMatch3High"); bits.High.setBaseRegister(&r32); bits.High.setName("High"); } RegDEVICEPerfectMatch3High_t& operator=(const RegDEVICEPerfectMatch3High_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPerfectMatch3High_t; #define REG_DEVICE_PERFECT_MATCH3_LOW ((volatile APE_DEVICE_H_uint32_t*)0xa0040554) /* */ #define DEVICE_PERFECT_MATCH3_LOW_LOW_SHIFT 0u #define DEVICE_PERFECT_MATCH3_LOW_LOW_MASK 0xffffffffu #define GET_DEVICE_PERFECT_MATCH3_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) #define SET_DEVICE_PERFECT_MATCH3_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) /** @brief Register definition for @ref DEVICE_t.PerfectMatch3Low. */ typedef register_container RegDEVICEPerfectMatch3Low_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Lower four bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Low, 0, 32) #elif defined(__BIG_ENDIAN__) /** @brief Lower four bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Low, 0, 32) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PerfectMatch3Low"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPerfectMatch3Low_t() { /** @brief constructor for @ref DEVICE_t.PerfectMatch3Low. */ r32.setName("PerfectMatch3Low"); bits.Low.setBaseRegister(&r32); bits.Low.setName("Low"); } RegDEVICEPerfectMatch3Low_t& operator=(const RegDEVICEPerfectMatch3Low_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPerfectMatch3Low_t; #define REG_DEVICE_PERFECT_MATCH4_HIGH ((volatile APE_DEVICE_H_uint32_t*)0xa0040558) /* */ #define DEVICE_PERFECT_MATCH4_HIGH_HIGH_SHIFT 0u #define DEVICE_PERFECT_MATCH4_HIGH_HIGH_MASK 0xffffu #define GET_DEVICE_PERFECT_MATCH4_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_PERFECT_MATCH4_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) /** @brief Register definition for @ref DEVICE_t.PerfectMatch4High. */ typedef register_container RegDEVICEPerfectMatch4High_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Upper two bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, High, 0, 16) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) /** @brief Upper two bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, High, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PerfectMatch4High"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPerfectMatch4High_t() { /** @brief constructor for @ref DEVICE_t.PerfectMatch4High. */ r32.setName("PerfectMatch4High"); bits.High.setBaseRegister(&r32); bits.High.setName("High"); } RegDEVICEPerfectMatch4High_t& operator=(const RegDEVICEPerfectMatch4High_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPerfectMatch4High_t; #define REG_DEVICE_PERFECT_MATCH4_LOW ((volatile APE_DEVICE_H_uint32_t*)0xa004055c) /* */ #define DEVICE_PERFECT_MATCH4_LOW_LOW_SHIFT 0u #define DEVICE_PERFECT_MATCH4_LOW_LOW_MASK 0xffffffffu #define GET_DEVICE_PERFECT_MATCH4_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) #define SET_DEVICE_PERFECT_MATCH4_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) /** @brief Register definition for @ref DEVICE_t.PerfectMatch4Low. */ typedef register_container RegDEVICEPerfectMatch4Low_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Lower four bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Low, 0, 32) #elif defined(__BIG_ENDIAN__) /** @brief Lower four bytes of the MAC */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Low, 0, 32) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PerfectMatch4Low"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPerfectMatch4Low_t() { /** @brief constructor for @ref DEVICE_t.PerfectMatch4Low. */ r32.setName("PerfectMatch4Low"); bits.Low.setBaseRegister(&r32); bits.Low.setName("Low"); } RegDEVICEPerfectMatch4Low_t& operator=(const RegDEVICEPerfectMatch4Low_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPerfectMatch4Low_t; #define REG_DEVICE_SGMII_STATUS ((volatile APE_DEVICE_H_uint32_t*)0xa00405b4) /* This register reflects various status of the respective SGMII port when enabled. */ #define DEVICE_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 0u #define DEVICE_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x1u #define GET_DEVICE_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_SGMII_STATUS_LINK_STATUS_SHIFT 1u #define DEVICE_SGMII_STATUS_LINK_STATUS_MASK 0x2u #define GET_DEVICE_SGMII_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_SGMII_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_SGMII_STATUS_DUPLEX_STATUS_SHIFT 2u #define DEVICE_SGMII_STATUS_DUPLEX_STATUS_MASK 0x4u #define GET_DEVICE_SGMII_STATUS_DUPLEX_STATUS(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_SGMII_STATUS_DUPLEX_STATUS(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_SGMII_STATUS_SPEED_1000_SHIFT 3u #define DEVICE_SGMII_STATUS_SPEED_1000_MASK 0x8u #define GET_DEVICE_SGMII_STATUS_SPEED_1000(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_SGMII_STATUS_SPEED_1000(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_SGMII_STATUS_SPEED_100_SHIFT 4u #define DEVICE_SGMII_STATUS_SPEED_100_MASK 0x10u #define GET_DEVICE_SGMII_STATUS_SPEED_100(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_SGMII_STATUS_SPEED_100(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_SGMII_STATUS_NEXT_PAGE_RX_SHIFT 5u #define DEVICE_SGMII_STATUS_NEXT_PAGE_RX_MASK 0x20u #define GET_DEVICE_SGMII_STATUS_NEXT_PAGE_RX(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_SGMII_STATUS_NEXT_PAGE_RX(__val__) (((__val__) << 5u) & 0x20u) #define DEVICE_SGMII_STATUS_PAUSE_RX_SHIFT 6u #define DEVICE_SGMII_STATUS_PAUSE_RX_MASK 0x40u #define GET_DEVICE_SGMII_STATUS_PAUSE_RX(__reg__) (((__reg__) & 0x40) >> 6u) #define SET_DEVICE_SGMII_STATUS_PAUSE_RX(__val__) (((__val__) << 6u) & 0x40u) #define DEVICE_SGMII_STATUS_PAUSE_TX_SHIFT 7u #define DEVICE_SGMII_STATUS_PAUSE_TX_MASK 0x80u #define GET_DEVICE_SGMII_STATUS_PAUSE_TX(__reg__) (((__reg__) & 0x80) >> 7u) #define SET_DEVICE_SGMII_STATUS_PAUSE_TX(__val__) (((__val__) << 7u) & 0x80u) #define DEVICE_SGMII_STATUS_MEDIA_SELECTION_MODE_SHIFT 8u #define DEVICE_SGMII_STATUS_MEDIA_SELECTION_MODE_MASK 0x100u #define GET_DEVICE_SGMII_STATUS_MEDIA_SELECTION_MODE(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_SGMII_STATUS_MEDIA_SELECTION_MODE(__val__) (((__val__) << 8u) & 0x100u) #define DEVICE_SGMII_STATUS_MEDIA_SELECTION_MODE_COPPER 0x0u #define DEVICE_SGMII_STATUS_MEDIA_SELECTION_MODE_SGMII 0x1u #define DEVICE_SGMII_STATUS_PCS_CRS_DETECT_SHIFT 9u #define DEVICE_SGMII_STATUS_PCS_CRS_DETECT_MASK 0x200u #define GET_DEVICE_SGMII_STATUS_PCS_CRS_DETECT(__reg__) (((__reg__) & 0x200) >> 9u) #define SET_DEVICE_SGMII_STATUS_PCS_CRS_DETECT(__val__) (((__val__) << 9u) & 0x200u) #define DEVICE_SGMII_STATUS_EXTERNAL_CRS_DETECT_SHIFT 10u #define DEVICE_SGMII_STATUS_EXTERNAL_CRS_DETECT_MASK 0x400u #define GET_DEVICE_SGMII_STATUS_EXTERNAL_CRS_DETECT(__reg__) (((__reg__) & 0x400) >> 10u) #define SET_DEVICE_SGMII_STATUS_EXTERNAL_CRS_DETECT(__val__) (((__val__) << 10u) & 0x400u) #define DEVICE_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_SHIFT 16u #define DEVICE_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_MASK 0xffff0000u #define GET_DEVICE_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__reg__) (((__reg__) & 0xffff0000) >> 16u) #define SET_DEVICE_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__val__) (((__val__) << 16u) & 0xffff0000u) /** @brief Register definition for @ref DEVICE_t.SgmiiStatus. */ typedef register_container RegDEVICESgmiiStatus_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Auto-negotiation process has completed. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AutonegotiationComplete, 0, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkStatus, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DuplexStatus, 2, 1) /** @brief The SGMII Link currently operable at 1 Gbps data speed. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Speed1000, 3, 1) /** @brief The SGMII Link currently operable at 100mbps data speed. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Speed100, 4, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NextPageRX, 5, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PauseRX, 6, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PauseTX, 7, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MediaSelectionMode, 8, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCSCRSDetect, 9, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ExternalCRSDetect, 10, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_11, 11, 5) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkPartnerAutonegotiationCapability, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkPartnerAutonegotiationCapability, 16, 16) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_11, 11, 5) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ExternalCRSDetect, 10, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCSCRSDetect, 9, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MediaSelectionMode, 8, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PauseTX, 7, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PauseRX, 6, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NextPageRX, 5, 1) /** @brief The SGMII Link currently operable at 100mbps data speed. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Speed100, 4, 1) /** @brief The SGMII Link currently operable at 1 Gbps data speed. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Speed1000, 3, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DuplexStatus, 2, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkStatus, 1, 1) /** @brief Auto-negotiation process has completed. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AutonegotiationComplete, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "SgmiiStatus"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICESgmiiStatus_t() { /** @brief constructor for @ref DEVICE_t.SgmiiStatus. */ r32.setName("SgmiiStatus"); bits.AutonegotiationComplete.setBaseRegister(&r32); bits.AutonegotiationComplete.setName("AutonegotiationComplete"); bits.LinkStatus.setBaseRegister(&r32); bits.LinkStatus.setName("LinkStatus"); bits.DuplexStatus.setBaseRegister(&r32); bits.DuplexStatus.setName("DuplexStatus"); bits.Speed1000.setBaseRegister(&r32); bits.Speed1000.setName("Speed1000"); bits.Speed100.setBaseRegister(&r32); bits.Speed100.setName("Speed100"); bits.NextPageRX.setBaseRegister(&r32); bits.NextPageRX.setName("NextPageRX"); bits.PauseRX.setBaseRegister(&r32); bits.PauseRX.setName("PauseRX"); bits.PauseTX.setBaseRegister(&r32); bits.PauseTX.setName("PauseTX"); bits.MediaSelectionMode.setBaseRegister(&r32); bits.MediaSelectionMode.setName("MediaSelectionMode"); bits.MediaSelectionMode.addEnum("Copper", 0x0); bits.MediaSelectionMode.addEnum("SGMII", 0x1); bits.PCSCRSDetect.setBaseRegister(&r32); bits.PCSCRSDetect.setName("PCSCRSDetect"); bits.ExternalCRSDetect.setBaseRegister(&r32); bits.ExternalCRSDetect.setName("ExternalCRSDetect"); bits.LinkPartnerAutonegotiationCapability.setBaseRegister(&r32); bits.LinkPartnerAutonegotiationCapability.setName("LinkPartnerAutonegotiationCapability"); } RegDEVICESgmiiStatus_t& operator=(const RegDEVICESgmiiStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICESgmiiStatus_t; #define REG_DEVICE_RECEIVE_LIST_PLACEMENT_MODE ((volatile APE_DEVICE_H_uint32_t*)0xa0042000) /* */ #define DEVICE_RECEIVE_LIST_PLACEMENT_MODE_RESET_SHIFT 0u #define DEVICE_RECEIVE_LIST_PLACEMENT_MODE_RESET_MASK 0x1u #define GET_DEVICE_RECEIVE_LIST_PLACEMENT_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_RECEIVE_LIST_PLACEMENT_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_RECEIVE_LIST_PLACEMENT_MODE_ENABLE_SHIFT 1u #define DEVICE_RECEIVE_LIST_PLACEMENT_MODE_ENABLE_MASK 0x2u #define GET_DEVICE_RECEIVE_LIST_PLACEMENT_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_RECEIVE_LIST_PLACEMENT_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_RECEIVE_LIST_PLACEMENT_MODE_CLASS_ZERO_ATTENTION_ENABLE_SHIFT 2u #define DEVICE_RECEIVE_LIST_PLACEMENT_MODE_CLASS_ZERO_ATTENTION_ENABLE_MASK 0x4u #define GET_DEVICE_RECEIVE_LIST_PLACEMENT_MODE_CLASS_ZERO_ATTENTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_RECEIVE_LIST_PLACEMENT_MODE_CLASS_ZERO_ATTENTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_RECEIVE_LIST_PLACEMENT_MODE_MAPPING_OUT_OF_RANGE_ATTENTION_ENABLE_SHIFT 3u #define DEVICE_RECEIVE_LIST_PLACEMENT_MODE_MAPPING_OUT_OF_RANGE_ATTENTION_ENABLE_MASK 0x8u #define GET_DEVICE_RECEIVE_LIST_PLACEMENT_MODE_MAPPING_OUT_OF_RANGE_ATTENTION_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_RECEIVE_LIST_PLACEMENT_MODE_MAPPING_OUT_OF_RANGE_ATTENTION_ENABLE(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_RECEIVE_LIST_PLACEMENT_MODE_STATS_OVERFLOW_ATTENTION_ENABLE_SHIFT 4u #define DEVICE_RECEIVE_LIST_PLACEMENT_MODE_STATS_OVERFLOW_ATTENTION_ENABLE_MASK 0x10u #define GET_DEVICE_RECEIVE_LIST_PLACEMENT_MODE_STATS_OVERFLOW_ATTENTION_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_RECEIVE_LIST_PLACEMENT_MODE_STATS_OVERFLOW_ATTENTION_ENABLE(__val__) (((__val__) << 4u) & 0x10u) /** @brief Register definition for @ref DEVICE_t.ReceiveListPlacementMode. */ typedef register_container RegDEVICEReceiveListPlacementMode_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief When this bit is set to 1, the Receive List Placement state machine is reset. This is a self clearing bit. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Reset, 0, 1) /** @brief This bit controls whether the Receive List Placement state machine is active or not. When set to 0, it completes the current operation and cleanly halts. Until it is completely halted, it remains one when read. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Enable, 1, 1) /** @brief Enable attention for zero class field. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClassZeroAttentionEnable, 2, 1) /** @brief Enable attention for mapping out of range error. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MappingoutofRangeAttentionEnable, 3, 1) /** @brief Enable attention for statistics overflow. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, StatsOverflowAttentionEnable, 4, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_5, 5, 27) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_5, 5, 27) /** @brief Enable attention for statistics overflow. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, StatsOverflowAttentionEnable, 4, 1) /** @brief Enable attention for mapping out of range error. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MappingoutofRangeAttentionEnable, 3, 1) /** @brief Enable attention for zero class field. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClassZeroAttentionEnable, 2, 1) /** @brief This bit controls whether the Receive List Placement state machine is active or not. When set to 0, it completes the current operation and cleanly halts. Until it is completely halted, it remains one when read. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Enable, 1, 1) /** @brief When this bit is set to 1, the Receive List Placement state machine is reset. This is a self clearing bit. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Reset, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ReceiveListPlacementMode"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEReceiveListPlacementMode_t() { /** @brief constructor for @ref DEVICE_t.ReceiveListPlacementMode. */ r32.setName("ReceiveListPlacementMode"); bits.Reset.setBaseRegister(&r32); bits.Reset.setName("Reset"); bits.Enable.setBaseRegister(&r32); bits.Enable.setName("Enable"); bits.ClassZeroAttentionEnable.setBaseRegister(&r32); bits.ClassZeroAttentionEnable.setName("ClassZeroAttentionEnable"); bits.MappingoutofRangeAttentionEnable.setBaseRegister(&r32); bits.MappingoutofRangeAttentionEnable.setName("MappingoutofRangeAttentionEnable"); bits.StatsOverflowAttentionEnable.setBaseRegister(&r32); bits.StatsOverflowAttentionEnable.setName("StatsOverflowAttentionEnable"); } RegDEVICEReceiveListPlacementMode_t& operator=(const RegDEVICEReceiveListPlacementMode_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEReceiveListPlacementMode_t; #define REG_DEVICE_RECEIVE_LIST_PLACEMENT_STATUS ((volatile APE_DEVICE_H_uint32_t*)0xa0042004) /* */ #define DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_CLASS_ZERO_ATTENTION_SHIFT 2u #define DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_CLASS_ZERO_ATTENTION_MASK 0x4u #define GET_DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_CLASS_ZERO_ATTENTION(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_CLASS_ZERO_ATTENTION(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_MAPPING_OUT_OF_RANGE_ATTENTION_SHIFT 3u #define DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_MAPPING_OUT_OF_RANGE_ATTENTION_MASK 0x8u #define GET_DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_MAPPING_OUT_OF_RANGE_ATTENTION(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_MAPPING_OUT_OF_RANGE_ATTENTION(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_STATS_OVERFLOW_ATTENTION_SHIFT 4u #define DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_STATS_OVERFLOW_ATTENTION_MASK 0x10u #define GET_DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_STATS_OVERFLOW_ATTENTION(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_RECEIVE_LIST_PLACEMENT_STATUS_STATS_OVERFLOW_ATTENTION(__val__) (((__val__) << 4u) & 0x10u) /** @brief Register definition for @ref DEVICE_t.ReceiveListPlacementStatus. */ typedef register_container RegDEVICEReceiveListPlacementStatus_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_1_0, 0, 2) /** @brief Class field extracted from frame descriptor is zero. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClassZeroAttention, 2, 1) /** @brief Class of service mapping is out of the range of the active queue number. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MappingoutofRangeAttention, 3, 1) /** @brief A statistics managed by Receive List Placement has overflowed. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, StatsOverflowAttention, 4, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_5, 5, 27) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_5, 5, 27) /** @brief A statistics managed by Receive List Placement has overflowed. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, StatsOverflowAttention, 4, 1) /** @brief Class of service mapping is out of the range of the active queue number. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MappingoutofRangeAttention, 3, 1) /** @brief Class field extracted from frame descriptor is zero. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClassZeroAttention, 2, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_1_0, 0, 2) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ReceiveListPlacementStatus"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEReceiveListPlacementStatus_t() { /** @brief constructor for @ref DEVICE_t.ReceiveListPlacementStatus. */ r32.setName("ReceiveListPlacementStatus"); bits.ClassZeroAttention.setBaseRegister(&r32); bits.ClassZeroAttention.setName("ClassZeroAttention"); bits.MappingoutofRangeAttention.setBaseRegister(&r32); bits.MappingoutofRangeAttention.setName("MappingoutofRangeAttention"); bits.StatsOverflowAttention.setBaseRegister(&r32); bits.StatsOverflowAttention.setName("StatsOverflowAttention"); } RegDEVICEReceiveListPlacementStatus_t& operator=(const RegDEVICEReceiveListPlacementStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEReceiveListPlacementStatus_t; #define REG_DEVICE_CPMU_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa0043600) /* */ #define DEVICE_CPMU_CONTROL_CPMU_SOFTWARE_RESET_SHIFT 0u #define DEVICE_CPMU_CONTROL_CPMU_SOFTWARE_RESET_MASK 0x1u #define GET_DEVICE_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 1u #define DEVICE_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x2u #define GET_DEVICE_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_CPMU_CONTROL_POWER_DOWN_SHIFT 2u #define DEVICE_CPMU_CONTROL_POWER_DOWN_MASK 0x4u #define GET_DEVICE_CPMU_CONTROL_POWER_DOWN(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_CPMU_CONTROL_POWER_DOWN(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_SHIFT 4u #define DEVICE_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_MASK 0x10u #define GET_DEVICE_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_SHIFT 5u #define DEVICE_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_MASK 0x20u #define GET_DEVICE_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__val__) (((__val__) << 5u) & 0x20u) #define DEVICE_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_SHIFT 9u #define DEVICE_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_MASK 0x200u #define GET_DEVICE_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) #define SET_DEVICE_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__val__) (((__val__) << 9u) & 0x200u) #define DEVICE_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_SHIFT 10u #define DEVICE_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_MASK 0x400u #define GET_DEVICE_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) #define SET_DEVICE_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) #define DEVICE_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_SHIFT 14u #define DEVICE_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_MASK 0x4000u #define GET_DEVICE_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x4000) >> 14u) #define SET_DEVICE_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__val__) (((__val__) << 14u) & 0x4000u) #define DEVICE_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_SHIFT 16u #define DEVICE_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_MASK 0x10000u #define GET_DEVICE_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) #define SET_DEVICE_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) #define DEVICE_CPMU_CONTROL_LEGACY_TIMER_ENABLE_SHIFT 18u #define DEVICE_CPMU_CONTROL_LEGACY_TIMER_ENABLE_MASK 0x40000u #define GET_DEVICE_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) #define SET_DEVICE_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) #define DEVICE_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_SHIFT 19u #define DEVICE_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_MASK 0x80000u #define GET_DEVICE_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x80000) >> 19u) #define SET_DEVICE_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 19u) & 0x80000u) #define DEVICE_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_SHIFT 28u #define DEVICE_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_MASK 0x10000000u #define GET_DEVICE_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__reg__) (((__reg__) & 0x10000000) >> 28u) #define SET_DEVICE_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref DEVICE_t.CpmuControl. */ typedef register_container RegDEVICECpmuControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMUSoftwareReset, 0, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMURegisterSoftwareReset, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerDown, 2, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_3_3, 3, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APESleepModeEnable, 4, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEDeepSleepModeEnable, 5, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_8_6, 6, 3) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkIdlePowerModeEnable, 9, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkAwarePowerModeEnable, 10, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_13_11, 11, 3) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkSpeedPowerModeEnable, 14, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_15, 15, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPHY10MBReceiveOnlyModeEnable, 16, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_17_17, 17, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LegacyTimerEnable, 18, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SGMII_DIV_PCSPowerDown, 19, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_27_20, 20, 8) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SoftwareControlledGPHYForceDLLOn, 28, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_29, 29, 3) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_29, 29, 3) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SoftwareControlledGPHYForceDLLOn, 28, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_27_20, 20, 8) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SGMII_DIV_PCSPowerDown, 19, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LegacyTimerEnable, 18, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_17_17, 17, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPHY10MBReceiveOnlyModeEnable, 16, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_15, 15, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkSpeedPowerModeEnable, 14, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_13_11, 11, 3) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkAwarePowerModeEnable, 10, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkIdlePowerModeEnable, 9, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_8_6, 6, 3) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEDeepSleepModeEnable, 5, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APESleepModeEnable, 4, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_3_3, 3, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerDown, 2, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMURegisterSoftwareReset, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMUSoftwareReset, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "CpmuControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICECpmuControl_t() { /** @brief constructor for @ref DEVICE_t.CpmuControl. */ r32.setName("CpmuControl"); bits.CPMUSoftwareReset.setBaseRegister(&r32); bits.CPMUSoftwareReset.setName("CPMUSoftwareReset"); bits.CPMURegisterSoftwareReset.setBaseRegister(&r32); bits.CPMURegisterSoftwareReset.setName("CPMURegisterSoftwareReset"); bits.PowerDown.setBaseRegister(&r32); bits.PowerDown.setName("PowerDown"); bits.APESleepModeEnable.setBaseRegister(&r32); bits.APESleepModeEnable.setName("APESleepModeEnable"); bits.APEDeepSleepModeEnable.setBaseRegister(&r32); bits.APEDeepSleepModeEnable.setName("APEDeepSleepModeEnable"); bits.LinkIdlePowerModeEnable.setBaseRegister(&r32); bits.LinkIdlePowerModeEnable.setName("LinkIdlePowerModeEnable"); bits.LinkAwarePowerModeEnable.setBaseRegister(&r32); bits.LinkAwarePowerModeEnable.setName("LinkAwarePowerModeEnable"); bits.LinkSpeedPowerModeEnable.setBaseRegister(&r32); bits.LinkSpeedPowerModeEnable.setName("LinkSpeedPowerModeEnable"); bits.GPHY10MBReceiveOnlyModeEnable.setBaseRegister(&r32); bits.GPHY10MBReceiveOnlyModeEnable.setName("GPHY10MBReceiveOnlyModeEnable"); bits.LegacyTimerEnable.setBaseRegister(&r32); bits.LegacyTimerEnable.setName("LegacyTimerEnable"); bits.SGMII_DIV_PCSPowerDown.setBaseRegister(&r32); bits.SGMII_DIV_PCSPowerDown.setName("SGMII_DIV_PCSPowerDown"); bits.SoftwareControlledGPHYForceDLLOn.setBaseRegister(&r32); bits.SoftwareControlledGPHYForceDLLOn.setName("SoftwareControlledGPHYForceDLLOn"); } RegDEVICECpmuControl_t& operator=(const RegDEVICECpmuControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICECpmuControl_t; #define REG_DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE_H_uint32_t*)0xa0043604) /* */ #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u #define GET_DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) #define SET_DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_62_5MHZ 0x0u #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u #define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu /** @brief Register definition for @ref DEVICE_t.NoLinkPowerModeClockPolicy. */ typedef register_container RegDEVICENoLinkPowerModeClockPolicy_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) /** @brief Software Controlled MAC Core Clock Speed Select. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Software Controlled MAC Core Clock Speed Select. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "NoLinkPowerModeClockPolicy"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICENoLinkPowerModeClockPolicy_t() { /** @brief constructor for @ref DEVICE_t.NoLinkPowerModeClockPolicy. */ r32.setName("NoLinkPowerModeClockPolicy"); bits.MACClockSwitch.setBaseRegister(&r32); bits.MACClockSwitch.setName("MACClockSwitch"); bits.MACClockSwitch.addEnum("62.5MHz", 0x0); bits.MACClockSwitch.addEnum("60.0MHz", 0x1); bits.MACClockSwitch.addEnum("30.0MHz", 0x3); bits.MACClockSwitch.addEnum("15.0MHz", 0x5); bits.MACClockSwitch.addEnum("7.5MHz", 0x7); bits.MACClockSwitch.addEnum("3.75MHz", 0x9); bits.MACClockSwitch.addEnum("12.5MHz", 0x11); bits.MACClockSwitch.addEnum("6.25MHz", 0x13); bits.MACClockSwitch.addEnum("3.125MHz", 0x15); bits.MACClockSwitch.addEnum("1.563MHz", 0x17); bits.MACClockSwitch.addEnum("12.5MHz/1.25MHz", 0x1f); } RegDEVICENoLinkPowerModeClockPolicy_t& operator=(const RegDEVICENoLinkPowerModeClockPolicy_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICENoLinkPowerModeClockPolicy_t; #define REG_DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE_H_uint32_t*)0xa0043610) /* */ #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u #define GET_DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) #define SET_DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_781KHZ 0x19u #define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu /** @brief Register definition for @ref DEVICE_t.LinkAwarePowerModeClockPolicy. */ typedef register_container RegDEVICELinkAwarePowerModeClockPolicy_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) /** @brief Software Controlled MAC Core Clock Speed Select. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Software Controlled MAC Core Clock Speed Select. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "LinkAwarePowerModeClockPolicy"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICELinkAwarePowerModeClockPolicy_t() { /** @brief constructor for @ref DEVICE_t.LinkAwarePowerModeClockPolicy. */ r32.setName("LinkAwarePowerModeClockPolicy"); bits.MACClockSwitch.setBaseRegister(&r32); bits.MACClockSwitch.setName("MACClockSwitch"); bits.MACClockSwitch.addEnum("60.0MHz", 0x1); bits.MACClockSwitch.addEnum("30.0MHz", 0x3); bits.MACClockSwitch.addEnum("15.0MHz", 0x5); bits.MACClockSwitch.addEnum("7.5MHz", 0x7); bits.MACClockSwitch.addEnum("3.75MHz", 0x9); bits.MACClockSwitch.addEnum("12.5MHz", 0x11); bits.MACClockSwitch.addEnum("6.25MHz", 0x13); bits.MACClockSwitch.addEnum("3.125MHz", 0x15); bits.MACClockSwitch.addEnum("1.563MHz", 0x17); bits.MACClockSwitch.addEnum("781kHz", 0x19); bits.MACClockSwitch.addEnum("12.5MHz/1.25MHz", 0x1f); } RegDEVICELinkAwarePowerModeClockPolicy_t& operator=(const RegDEVICELinkAwarePowerModeClockPolicy_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICELinkAwarePowerModeClockPolicy_t; #define REG_DEVICE_D0U_CLOCK_POLICY ((volatile APE_DEVICE_H_uint32_t*)0xa0043614) /* */ #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u #define GET_DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) #define SET_DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_781KHZ 0x19u #define DEVICE_D0U_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu /** @brief Register definition for @ref DEVICE_t.D0uClockPolicy. */ typedef register_container RegDEVICED0uClockPolicy_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) /** @brief Software Controlled MAC Core Clock Speed Select. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Software Controlled MAC Core Clock Speed Select. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "D0uClockPolicy"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICED0uClockPolicy_t() { /** @brief constructor for @ref DEVICE_t.D0uClockPolicy. */ r32.setName("D0uClockPolicy"); bits.MACClockSwitch.setBaseRegister(&r32); bits.MACClockSwitch.setName("MACClockSwitch"); bits.MACClockSwitch.addEnum("60.0MHz", 0x1); bits.MACClockSwitch.addEnum("30.0MHz", 0x3); bits.MACClockSwitch.addEnum("15.0MHz", 0x5); bits.MACClockSwitch.addEnum("7.5MHz", 0x7); bits.MACClockSwitch.addEnum("3.75MHz", 0x9); bits.MACClockSwitch.addEnum("12.5MHz", 0x11); bits.MACClockSwitch.addEnum("6.25MHz", 0x13); bits.MACClockSwitch.addEnum("3.125MHz", 0x15); bits.MACClockSwitch.addEnum("1.563MHz", 0x17); bits.MACClockSwitch.addEnum("781kHz", 0x19); bits.MACClockSwitch.addEnum("12.5MHz/1.25MHz", 0x1f); } RegDEVICED0uClockPolicy_t& operator=(const RegDEVICED0uClockPolicy_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICED0uClockPolicy_t; #define REG_DEVICE_APE_CLK_POLICY ((volatile APE_DEVICE_H_uint32_t*)0xa004361c) /* */ #define DEVICE_APE_CLK_POLICY_LAPM_APE_CLOCK_SWITCH_SHIFT 0u #define DEVICE_APE_CLK_POLICY_LAPM_APE_CLOCK_SWITCH_MASK 0x1fu #define GET_DEVICE_APE_CLK_POLICY_LAPM_APE_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f) >> 0u) #define SET_DEVICE_APE_CLK_POLICY_LAPM_APE_CLOCK_SWITCH(__val__) (((__val__) << 0u) & 0x1fu) #define DEVICE_APE_CLK_POLICY_LAPM_APE_CLOCK_SWITCH_25_MHZ 0x11u #define DEVICE_APE_CLK_POLICY_LAPM_APE_CLOCK_SWITCH_12_5_MHZ 0x13u #define DEVICE_APE_CLK_POLICY_LAPM_APE_CLOCK_SWITCH_6_25_MHZ 0x15u #define DEVICE_APE_CLK_POLICY_LAPM_APE_CLOCK_SWITCH_3_125_MHZ 0x17u #define DEVICE_APE_CLK_POLICY_LAPM_APE_CLOCK_SWITCH_1_563_MHZ 0x19u #define DEVICE_APE_CLK_POLICY_APE_CLOCK_SWITCH_SHIFT 8u #define DEVICE_APE_CLK_POLICY_APE_CLOCK_SWITCH_MASK 0x1f00u #define GET_DEVICE_APE_CLK_POLICY_APE_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f00) >> 8u) #define SET_DEVICE_APE_CLK_POLICY_APE_CLOCK_SWITCH(__val__) (((__val__) << 8u) & 0x1f00u) #define DEVICE_APE_CLK_POLICY_APE_CLOCK_SWITCH_62_5_MHZ 0x0u #define DEVICE_APE_CLK_POLICY_APE_CLOCK_SWITCH_25_MHZ 0x9u #define DEVICE_APE_CLK_POLICY_APE_CLOCK_SWITCH_12_5_MHZ 0x13u #define DEVICE_APE_CLK_POLICY_APE_CLOCK_SWITCH_6_25_MHZ 0x15u #define DEVICE_APE_CLK_POLICY_APE_CLOCK_SWITCH_3_125_MHZ 0x17u #define DEVICE_APE_CLK_POLICY_APE_CLOCK_SWITCH_1_563_MHZ 0x19u #define DEVICE_APE_CLK_POLICY_APE_CLOCK_SWITCH_125_MHZ 0x1eu #define DEVICE_APE_CLK_POLICY_CLOCK_OVERRIDE_APE_CLOCK_SWITCH_SHIFT 16u #define DEVICE_APE_CLK_POLICY_CLOCK_OVERRIDE_APE_CLOCK_SWITCH_MASK 0x1f0000u #define GET_DEVICE_APE_CLK_POLICY_CLOCK_OVERRIDE_APE_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) #define SET_DEVICE_APE_CLK_POLICY_CLOCK_OVERRIDE_APE_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) #define DEVICE_APE_CLK_POLICY_CLOCK_OVERRIDE_APE_CLOCK_SWITCH_62_5_MHZ 0x0u #define DEVICE_APE_CLK_POLICY_CLOCK_OVERRIDE_APE_CLOCK_SWITCH_25_MHZ 0x9u #define DEVICE_APE_CLK_POLICY_CLOCK_OVERRIDE_APE_CLOCK_SWITCH_12_5_MHZ 0x13u #define DEVICE_APE_CLK_POLICY_CLOCK_OVERRIDE_APE_CLOCK_SWITCH_6_25_MHZ 0x15u #define DEVICE_APE_CLK_POLICY_CLOCK_OVERRIDE_APE_CLOCK_SWITCH_3_125_MHZ 0x17u #define DEVICE_APE_CLK_POLICY_CLOCK_OVERRIDE_APE_CLOCK_SWITCH_1_563_MHZ 0x19u #define DEVICE_APE_CLK_POLICY_CLOCK_OVERRIDE_APE_CLOCK_SWITCH_125_MHZ 0x1eu #define DEVICE_APE_CLK_POLICY_FORCE_APE_HCLK_DISABLE_SHIFT 27u #define DEVICE_APE_CLK_POLICY_FORCE_APE_HCLK_DISABLE_MASK 0x8000000u #define GET_DEVICE_APE_CLK_POLICY_FORCE_APE_HCLK_DISABLE(__reg__) (((__reg__) & 0x8000000) >> 27u) #define SET_DEVICE_APE_CLK_POLICY_FORCE_APE_HCLK_DISABLE(__val__) (((__val__) << 27u) & 0x8000000u) #define DEVICE_APE_CLK_POLICY_FORCE_APE_FCLK_DISABLE_SHIFT 28u #define DEVICE_APE_CLK_POLICY_FORCE_APE_FCLK_DISABLE_MASK 0x10000000u #define GET_DEVICE_APE_CLK_POLICY_FORCE_APE_FCLK_DISABLE(__reg__) (((__reg__) & 0x10000000) >> 28u) #define SET_DEVICE_APE_CLK_POLICY_FORCE_APE_FCLK_DISABLE(__val__) (((__val__) << 28u) & 0x10000000u) #define DEVICE_APE_CLK_POLICY_APE_CLOCK_SPEED_OVERRIDE_ENABLE_SHIFT 29u #define DEVICE_APE_CLK_POLICY_APE_CLOCK_SPEED_OVERRIDE_ENABLE_MASK 0x20000000u #define GET_DEVICE_APE_CLK_POLICY_APE_CLOCK_SPEED_OVERRIDE_ENABLE(__reg__) (((__reg__) & 0x20000000) >> 29u) #define SET_DEVICE_APE_CLK_POLICY_APE_CLOCK_SPEED_OVERRIDE_ENABLE(__val__) (((__val__) << 29u) & 0x20000000u) #define DEVICE_APE_CLK_POLICY_APE_DEEP_SLEEP_MODE_ENABLE_SHIFT 30u #define DEVICE_APE_CLK_POLICY_APE_DEEP_SLEEP_MODE_ENABLE_MASK 0x40000000u #define GET_DEVICE_APE_CLK_POLICY_APE_DEEP_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x40000000) >> 30u) #define SET_DEVICE_APE_CLK_POLICY_APE_DEEP_SLEEP_MODE_ENABLE(__val__) (((__val__) << 30u) & 0x40000000u) #define DEVICE_APE_CLK_POLICY_APE_SLEEP_MODE_ENABLE_SHIFT 31u #define DEVICE_APE_CLK_POLICY_APE_SLEEP_MODE_ENABLE_MASK 0x80000000u #define GET_DEVICE_APE_CLK_POLICY_APE_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) #define SET_DEVICE_APE_CLK_POLICY_APE_SLEEP_MODE_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref DEVICE_t.ApeClkPolicy. */ typedef register_container RegDEVICEApeClkPolicy_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Software Controlled APE Clock Speed Select inLink Aware Power mode */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LAPMAPEClockSwitch, 0, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_5, 5, 3) /** @brief Software Controlled APE Clock Speed Select */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEClockSwitch, 8, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_13, 13, 3) /** @brief Software Controlled APE Clock Speed Select for Clock Override. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClockOverrideAPEClockSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_26_21, 21, 6) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceAPEHCLKDisable, 27, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceAPEFCLKDisable, 28, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEClockSpeedOverrideEnable, 29, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEDeepSleepmodeEnable, 30, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APESleepmodeEnable, 31, 1) #elif defined(__BIG_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APESleepmodeEnable, 31, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEDeepSleepmodeEnable, 30, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEClockSpeedOverrideEnable, 29, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceAPEFCLKDisable, 28, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceAPEHCLKDisable, 27, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_26_21, 21, 6) /** @brief Software Controlled APE Clock Speed Select for Clock Override. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ClockOverrideAPEClockSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_13, 13, 3) /** @brief Software Controlled APE Clock Speed Select */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEClockSwitch, 8, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_5, 5, 3) /** @brief Software Controlled APE Clock Speed Select inLink Aware Power mode */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LAPMAPEClockSwitch, 0, 5) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ApeClkPolicy"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEApeClkPolicy_t() { /** @brief constructor for @ref DEVICE_t.ApeClkPolicy. */ r32.setName("ApeClkPolicy"); bits.LAPMAPEClockSwitch.setBaseRegister(&r32); bits.LAPMAPEClockSwitch.setName("LAPMAPEClockSwitch"); bits.LAPMAPEClockSwitch.addEnum("25 MHz", 0x11); bits.LAPMAPEClockSwitch.addEnum("12.5 MHz", 0x13); bits.LAPMAPEClockSwitch.addEnum("6.25 MHz", 0x15); bits.LAPMAPEClockSwitch.addEnum("3.125 MHz", 0x17); bits.LAPMAPEClockSwitch.addEnum("1.563 MHz", 0x19); bits.APEClockSwitch.setBaseRegister(&r32); bits.APEClockSwitch.setName("APEClockSwitch"); bits.APEClockSwitch.addEnum("62.5 MHz", 0x0); bits.APEClockSwitch.addEnum("25 MHz", 0x9); bits.APEClockSwitch.addEnum("12.5 MHz", 0x13); bits.APEClockSwitch.addEnum("6.25 MHz", 0x15); bits.APEClockSwitch.addEnum("3.125 MHz", 0x17); bits.APEClockSwitch.addEnum("1.563 MHz", 0x19); bits.APEClockSwitch.addEnum("125 MHz", 0x1e); bits.ClockOverrideAPEClockSwitch.setBaseRegister(&r32); bits.ClockOverrideAPEClockSwitch.setName("ClockOverrideAPEClockSwitch"); bits.ClockOverrideAPEClockSwitch.addEnum("62.5 MHz", 0x0); bits.ClockOverrideAPEClockSwitch.addEnum("25 MHz", 0x9); bits.ClockOverrideAPEClockSwitch.addEnum("12.5 MHz", 0x13); bits.ClockOverrideAPEClockSwitch.addEnum("6.25 MHz", 0x15); bits.ClockOverrideAPEClockSwitch.addEnum("3.125 MHz", 0x17); bits.ClockOverrideAPEClockSwitch.addEnum("1.563 MHz", 0x19); bits.ClockOverrideAPEClockSwitch.addEnum("125 MHz", 0x1e); bits.ForceAPEHCLKDisable.setBaseRegister(&r32); bits.ForceAPEHCLKDisable.setName("ForceAPEHCLKDisable"); bits.ForceAPEFCLKDisable.setBaseRegister(&r32); bits.ForceAPEFCLKDisable.setName("ForceAPEFCLKDisable"); bits.APEClockSpeedOverrideEnable.setBaseRegister(&r32); bits.APEClockSpeedOverrideEnable.setName("APEClockSpeedOverrideEnable"); bits.APEDeepSleepmodeEnable.setBaseRegister(&r32); bits.APEDeepSleepmodeEnable.setName("APEDeepSleepmodeEnable"); bits.APESleepmodeEnable.setBaseRegister(&r32); bits.APESleepmodeEnable.setName("APESleepmodeEnable"); } RegDEVICEApeClkPolicy_t& operator=(const RegDEVICEApeClkPolicy_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEApeClkPolicy_t; #define REG_DEVICE_APE_SLEEP_STATE_CLOCK_POLICY ((volatile APE_DEVICE_H_uint32_t*)0xa0043620) /* */ #define DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_SLEEP_FCLK_SWITCH_SHIFT 0u #define DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_SLEEP_FCLK_SWITCH_MASK 0x1fu #define GET_DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_SLEEP_FCLK_SWITCH(__reg__) (((__reg__) & 0x1f) >> 0u) #define SET_DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_SLEEP_FCLK_SWITCH(__val__) (((__val__) << 0u) & 0x1fu) #define DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_DEEP_SLEEP_FCLK_SWITCH_SHIFT 16u #define DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_DEEP_SLEEP_FCLK_SWITCH_MASK 0x1f0000u #define GET_DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_DEEP_SLEEP_FCLK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) #define SET_DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_DEEP_SLEEP_FCLK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) #define DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_SLEEP_HCLK_DISABLE_SHIFT 31u #define DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_SLEEP_HCLK_DISABLE_MASK 0x80000000u #define GET_DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_SLEEP_HCLK_DISABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) #define SET_DEVICE_APE_SLEEP_STATE_CLOCK_POLICY_APE_SLEEP_HCLK_DISABLE(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref DEVICE_t.ApeSleepStateClockPolicy. */ typedef register_container RegDEVICEApeSleepStateClockPolicy_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Software Controlled APE Clock Speed Select */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APESleepFCLKSwitch, 0, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_5, 5, 11) /** @brief Software Controlled APE Clock Speed Select */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEDeepSleepFCLKSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_30_21, 21, 10) /** @brief Software Controlled APE HCLK shutoff in sleep and deep sleep state */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APESleepHCLKDisable, 31, 1) #elif defined(__BIG_ENDIAN__) /** @brief Software Controlled APE HCLK shutoff in sleep and deep sleep state */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APESleepHCLKDisable, 31, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_30_21, 21, 10) /** @brief Software Controlled APE Clock Speed Select */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEDeepSleepFCLKSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_5, 5, 11) /** @brief Software Controlled APE Clock Speed Select */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APESleepFCLKSwitch, 0, 5) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ApeSleepStateClockPolicy"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEApeSleepStateClockPolicy_t() { /** @brief constructor for @ref DEVICE_t.ApeSleepStateClockPolicy. */ r32.setName("ApeSleepStateClockPolicy"); bits.APESleepFCLKSwitch.setBaseRegister(&r32); bits.APESleepFCLKSwitch.setName("APESleepFCLKSwitch"); bits.APEDeepSleepFCLKSwitch.setBaseRegister(&r32); bits.APEDeepSleepFCLKSwitch.setName("APEDeepSleepFCLKSwitch"); bits.APESleepHCLKDisable.setBaseRegister(&r32); bits.APESleepHCLKDisable.setName("APESleepHCLKDisable"); } RegDEVICEApeSleepStateClockPolicy_t& operator=(const RegDEVICEApeSleepStateClockPolicy_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEApeSleepStateClockPolicy_t; #define REG_DEVICE_CLOCK_SPEED_OVERRIDE_POLICY ((volatile APE_DEVICE_H_uint32_t*)0xa0043624) /* */ #define DEVICE_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u #define DEVICE_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u #define GET_DEVICE_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) #define SET_DEVICE_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) #define DEVICE_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_SHIFT 31u #define DEVICE_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_MASK 0x80000000u #define GET_DEVICE_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__reg__) (((__reg__) & 0x80000000) >> 31u) #define SET_DEVICE_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref DEVICE_t.ClockSpeedOverridePolicy. */ typedef register_container RegDEVICEClockSpeedOverridePolicy_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) /** @brief Software Controlled MAC Core Clock Speed Select */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_30_21, 21, 10) /** @brief Enable MAC clock speed override */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSpeedOverrideEnabled, 31, 1) #elif defined(__BIG_ENDIAN__) /** @brief Enable MAC clock speed override */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSpeedOverrideEnabled, 31, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_30_21, 21, 10) /** @brief Software Controlled MAC Core Clock Speed Select */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSwitch, 16, 5) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ClockSpeedOverridePolicy"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEClockSpeedOverridePolicy_t() { /** @brief constructor for @ref DEVICE_t.ClockSpeedOverridePolicy. */ r32.setName("ClockSpeedOverridePolicy"); bits.MACClockSwitch.setBaseRegister(&r32); bits.MACClockSwitch.setName("MACClockSwitch"); bits.MACClockSpeedOverrideEnabled.setBaseRegister(&r32); bits.MACClockSpeedOverrideEnabled.setName("MACClockSpeedOverrideEnabled"); } RegDEVICEClockSpeedOverridePolicy_t& operator=(const RegDEVICEClockSpeedOverridePolicy_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEClockSpeedOverridePolicy_t; #define REG_DEVICE_STATUS ((volatile APE_DEVICE_H_uint32_t*)0xa004362c) /* */ #define DEVICE_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_SHIFT 0u #define DEVICE_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_MASK 0xfu #define GET_DEVICE_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__reg__) (((__reg__) & 0xf) >> 0u) #define SET_DEVICE_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__val__) (((__val__) << 0u) & 0xfu) #define DEVICE_STATUS_CPMU_POWER_STATE_SHIFT 4u #define DEVICE_STATUS_CPMU_POWER_STATE_MASK 0x70u #define GET_DEVICE_STATUS_CPMU_POWER_STATE(__reg__) (((__reg__) & 0x70) >> 4u) #define SET_DEVICE_STATUS_CPMU_POWER_STATE(__val__) (((__val__) << 4u) & 0x70u) #define DEVICE_STATUS_ENERGY_DETECT_STATUS_SHIFT 7u #define DEVICE_STATUS_ENERGY_DETECT_STATUS_MASK 0x80u #define GET_DEVICE_STATUS_ENERGY_DETECT_STATUS(__reg__) (((__reg__) & 0x80) >> 7u) #define SET_DEVICE_STATUS_ENERGY_DETECT_STATUS(__val__) (((__val__) << 7u) & 0x80u) #define DEVICE_STATUS_POWER_STATE_SHIFT 8u #define DEVICE_STATUS_POWER_STATE_MASK 0x300u #define GET_DEVICE_STATUS_POWER_STATE(__reg__) (((__reg__) & 0x300) >> 8u) #define SET_DEVICE_STATUS_POWER_STATE(__val__) (((__val__) << 8u) & 0x300u) #define DEVICE_STATUS_VMAIN_POWER_STATUS_SHIFT 13u #define DEVICE_STATUS_VMAIN_POWER_STATUS_MASK 0x2000u #define GET_DEVICE_STATUS_VMAIN_POWER_STATUS(__reg__) (((__reg__) & 0x2000) >> 13u) #define SET_DEVICE_STATUS_VMAIN_POWER_STATUS(__val__) (((__val__) << 13u) & 0x2000u) #define DEVICE_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_SHIFT 14u #define DEVICE_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_MASK 0x4000u #define GET_DEVICE_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x4000) >> 14u) #define SET_DEVICE_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 14u) & 0x4000u) #define DEVICE_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_SHIFT 15u #define DEVICE_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_MASK 0x8000u #define GET_DEVICE_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x8000) >> 15u) #define SET_DEVICE_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 15u) & 0x8000u) #define DEVICE_STATUS_NCSI_DLL_LOCK_STATUS_SHIFT 16u #define DEVICE_STATUS_NCSI_DLL_LOCK_STATUS_MASK 0x10000u #define GET_DEVICE_STATUS_NCSI_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x10000) >> 16u) #define SET_DEVICE_STATUS_NCSI_DLL_LOCK_STATUS(__val__) (((__val__) << 16u) & 0x10000u) #define DEVICE_STATUS_GPHY_DLL_LOCK_STATUS_SHIFT 17u #define DEVICE_STATUS_GPHY_DLL_LOCK_STATUS_MASK 0x20000u #define GET_DEVICE_STATUS_GPHY_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x20000) >> 17u) #define SET_DEVICE_STATUS_GPHY_DLL_LOCK_STATUS(__val__) (((__val__) << 17u) & 0x20000u) #define DEVICE_STATUS_LINK_IDLE_STATUS_SHIFT 18u #define DEVICE_STATUS_LINK_IDLE_STATUS_MASK 0x40000u #define GET_DEVICE_STATUS_LINK_IDLE_STATUS(__reg__) (((__reg__) & 0x40000) >> 18u) #define SET_DEVICE_STATUS_LINK_IDLE_STATUS(__val__) (((__val__) << 18u) & 0x40000u) #define DEVICE_STATUS_ETHERNET_LINK_STATUS_SHIFT 19u #define DEVICE_STATUS_ETHERNET_LINK_STATUS_MASK 0x180000u #define GET_DEVICE_STATUS_ETHERNET_LINK_STATUS(__reg__) (((__reg__) & 0x180000) >> 19u) #define SET_DEVICE_STATUS_ETHERNET_LINK_STATUS(__val__) (((__val__) << 19u) & 0x180000u) #define DEVICE_STATUS_ETHERNET_LINK_STATUS_1000_MB 0x0u #define DEVICE_STATUS_ETHERNET_LINK_STATUS_100_MB 0x1u #define DEVICE_STATUS_ETHERNET_LINK_STATUS_10_MB 0x2u #define DEVICE_STATUS_ETHERNET_LINK_STATUS_NO_LINK 0x3u #define DEVICE_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_SHIFT 21u #define DEVICE_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_MASK 0x200000u #define GET_DEVICE_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x200000) >> 21u) #define SET_DEVICE_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 21u) & 0x200000u) #define DEVICE_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_SHIFT 22u #define DEVICE_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_MASK 0x400000u #define GET_DEVICE_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x400000) >> 22u) #define SET_DEVICE_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 22u) & 0x400000u) #define DEVICE_STATUS_APE_STATUS_SHIFT 23u #define DEVICE_STATUS_APE_STATUS_MASK 0x1800000u #define GET_DEVICE_STATUS_APE_STATUS(__reg__) (((__reg__) & 0x1800000) >> 23u) #define SET_DEVICE_STATUS_APE_STATUS(__val__) (((__val__) << 23u) & 0x1800000u) #define DEVICE_STATUS_APE_STATUS_ACTIVE 0x0u #define DEVICE_STATUS_APE_STATUS_SLEEP 0x1u #define DEVICE_STATUS_APE_STATUS_DEEP_SLEEP 0x2u #define DEVICE_STATUS_FUNCTION_ENABLE_SHIFT 25u #define DEVICE_STATUS_FUNCTION_ENABLE_MASK 0x3e000000u #define GET_DEVICE_STATUS_FUNCTION_ENABLE(__reg__) (((__reg__) & 0x3e000000) >> 25u) #define SET_DEVICE_STATUS_FUNCTION_ENABLE(__val__) (((__val__) << 25u) & 0x3e000000u) #define DEVICE_STATUS_FUNCTION_NUMBER_SHIFT 30u #define DEVICE_STATUS_FUNCTION_NUMBER_MASK 0xc0000000u #define GET_DEVICE_STATUS_FUNCTION_NUMBER(__reg__) (((__reg__) & 0xc0000000) >> 30u) #define SET_DEVICE_STATUS_FUNCTION_NUMBER(__val__) (((__val__) << 30u) & 0xc0000000u) /** @brief Register definition for @ref DEVICE_t.Status. */ typedef register_container RegDEVICEStatus_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerManagementStateMachineState, 0, 4) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMUPowerState, 4, 3) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnergyDetectStatus, 7, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerState, 8, 2) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_12_10, 10, 3) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, VMAINPowerStatus, 13, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, WOLMagicPacketDetectionEnablePort0, 14, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, WOLACPIDetectionEnablePort0, 15, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NCSIDLLLockStatus, 16, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPHYDLLLockStatus, 17, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkIdleStatus, 18, 1) /** @brief EthernetLink Status */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EthernetLinkStatus, 19, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, WOLMagicPacketDetectionEnablePort1, 21, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, WOLACPIDetectionEnablePort1, 22, 1) /** @brief APE Engine Status */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEStatus, 23, 2) /** @brief Function Enable input from System BIOS */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FunctionEnable, 25, 5) /** @brief PCIE function number */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FunctionNumber, 30, 2) #elif defined(__BIG_ENDIAN__) /** @brief PCIE function number */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FunctionNumber, 30, 2) /** @brief Function Enable input from System BIOS */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FunctionEnable, 25, 5) /** @brief APE Engine Status */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEStatus, 23, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, WOLACPIDetectionEnablePort1, 22, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, WOLMagicPacketDetectionEnablePort1, 21, 1) /** @brief EthernetLink Status */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EthernetLinkStatus, 19, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LinkIdleStatus, 18, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPHYDLLLockStatus, 17, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NCSIDLLLockStatus, 16, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, WOLACPIDetectionEnablePort0, 15, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, WOLMagicPacketDetectionEnablePort0, 14, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, VMAINPowerStatus, 13, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_12_10, 10, 3) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerState, 8, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnergyDetectStatus, 7, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMUPowerState, 4, 3) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerManagementStateMachineState, 0, 4) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "Status"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEStatus_t() { /** @brief constructor for @ref DEVICE_t.Status. */ r32.setName("Status"); bits.PowerManagementStateMachineState.setBaseRegister(&r32); bits.PowerManagementStateMachineState.setName("PowerManagementStateMachineState"); bits.CPMUPowerState.setBaseRegister(&r32); bits.CPMUPowerState.setName("CPMUPowerState"); bits.EnergyDetectStatus.setBaseRegister(&r32); bits.EnergyDetectStatus.setName("EnergyDetectStatus"); bits.PowerState.setBaseRegister(&r32); bits.PowerState.setName("PowerState"); bits.VMAINPowerStatus.setBaseRegister(&r32); bits.VMAINPowerStatus.setName("VMAINPowerStatus"); bits.WOLMagicPacketDetectionEnablePort0.setBaseRegister(&r32); bits.WOLMagicPacketDetectionEnablePort0.setName("WOLMagicPacketDetectionEnablePort0"); bits.WOLACPIDetectionEnablePort0.setBaseRegister(&r32); bits.WOLACPIDetectionEnablePort0.setName("WOLACPIDetectionEnablePort0"); bits.NCSIDLLLockStatus.setBaseRegister(&r32); bits.NCSIDLLLockStatus.setName("NCSIDLLLockStatus"); bits.GPHYDLLLockStatus.setBaseRegister(&r32); bits.GPHYDLLLockStatus.setName("GPHYDLLLockStatus"); bits.LinkIdleStatus.setBaseRegister(&r32); bits.LinkIdleStatus.setName("LinkIdleStatus"); bits.EthernetLinkStatus.setBaseRegister(&r32); bits.EthernetLinkStatus.setName("EthernetLinkStatus"); bits.EthernetLinkStatus.addEnum("1000 Mb", 0x0); bits.EthernetLinkStatus.addEnum("100 Mb", 0x1); bits.EthernetLinkStatus.addEnum("10 Mb", 0x2); bits.EthernetLinkStatus.addEnum("No Link", 0x3); bits.WOLMagicPacketDetectionEnablePort1.setBaseRegister(&r32); bits.WOLMagicPacketDetectionEnablePort1.setName("WOLMagicPacketDetectionEnablePort1"); bits.WOLACPIDetectionEnablePort1.setBaseRegister(&r32); bits.WOLACPIDetectionEnablePort1.setName("WOLACPIDetectionEnablePort1"); bits.APEStatus.setBaseRegister(&r32); bits.APEStatus.setName("APEStatus"); bits.APEStatus.addEnum("Active", 0x0); bits.APEStatus.addEnum("Sleep", 0x1); bits.APEStatus.addEnum("Deep Sleep", 0x2); bits.FunctionEnable.setBaseRegister(&r32); bits.FunctionEnable.setName("FunctionEnable"); bits.FunctionNumber.setBaseRegister(&r32); bits.FunctionNumber.setName("FunctionNumber"); } RegDEVICEStatus_t& operator=(const RegDEVICEStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEStatus_t; #define REG_DEVICE_CLOCK_STATUS ((volatile APE_DEVICE_H_uint32_t*)0xa0043630) /* */ /** @brief Register definition for @ref DEVICE_t.ClockStatus. */ typedef register_container RegDEVICEClockStatus_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ClockStatus"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEClockStatus_t() { /** @brief constructor for @ref DEVICE_t.ClockStatus. */ r32.setName("ClockStatus"); } RegDEVICEClockStatus_t& operator=(const RegDEVICEClockStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEClockStatus_t; #define REG_DEVICE_GPHY_CONTROL_STATUS ((volatile APE_DEVICE_H_uint32_t*)0xa0043638) /* */ #define DEVICE_GPHY_CONTROL_STATUS_GPHY_IDDQ_SHIFT 0u #define DEVICE_GPHY_CONTROL_STATUS_GPHY_IDDQ_MASK 0x1u #define GET_DEVICE_GPHY_CONTROL_STATUS_GPHY_IDDQ(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_GPHY_CONTROL_STATUS_GPHY_IDDQ(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_GPHY_CONTROL_STATUS_BIAS_IDDQ_SHIFT 1u #define DEVICE_GPHY_CONTROL_STATUS_BIAS_IDDQ_MASK 0x2u #define GET_DEVICE_GPHY_CONTROL_STATUS_BIAS_IDDQ(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_GPHY_CONTROL_STATUS_BIAS_IDDQ(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_SHIFT 2u #define DEVICE_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_MASK 0x4u #define GET_DEVICE_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 3u #define DEVICE_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x8u #define GET_DEVICE_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_GPHY_CONTROL_STATUS_POWER_DOWN_SHIFT 4u #define DEVICE_GPHY_CONTROL_STATUS_POWER_DOWN_MASK 0x10u #define GET_DEVICE_GPHY_CONTROL_STATUS_POWER_DOWN(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_GPHY_CONTROL_STATUS_POWER_DOWN(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_SHIFT 15u #define DEVICE_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_MASK 0x8000u #define GET_DEVICE_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x8000) >> 15u) #define SET_DEVICE_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 15u) & 0x8000u) #define DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS_SHIFT 22u #define DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS_MASK 0x400000u #define GET_DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x400000) >> 22u) #define SET_DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS(__val__) (((__val__) << 22u) & 0x400000u) #define DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS_SHIFT 23u #define DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS_MASK 0x800000u #define GET_DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x800000) >> 23u) #define SET_DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS(__val__) (((__val__) << 23u) & 0x800000u) #define DEVICE_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_SHIFT 25u #define DEVICE_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_MASK 0x2000000u #define GET_DEVICE_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x2000000) >> 25u) #define SET_DEVICE_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__val__) (((__val__) << 25u) & 0x2000000u) #define DEVICE_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_SHIFT 26u #define DEVICE_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_MASK 0x4000000u #define GET_DEVICE_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__reg__) (((__reg__) & 0x4000000) >> 26u) #define SET_DEVICE_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__val__) (((__val__) << 26u) & 0x4000000u) #define DEVICE_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_SHIFT 27u #define DEVICE_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_MASK 0x8000000u #define GET_DEVICE_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__reg__) (((__reg__) & 0x8000000) >> 27u) #define SET_DEVICE_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__val__) (((__val__) << 27u) & 0x8000000u) #define DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE__SHIFT 28u #define DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE__MASK 0x10000000u #define GET_DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE_(__reg__) (((__reg__) & 0x10000000) >> 28u) #define SET_DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE_(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref DEVICE_t.GphyControlStatus. */ typedef register_container RegDEVICEGphyControlStatus_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief When this bit is set, GPHY will be powered down. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPHYIDDQ, 0, 1) /** @brief When this bit is set, BIAS will be powered down. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BIASIDDQ, 1, 1) /** @brief Software reset for all the CPMU logic expect for registers. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMUSoftwareReset, 2, 1) /** @brief Software reset for resetting all the registers to default. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMURegisterSoftwareReset, 3, 1) /** @brief Force CPMU into Low Power State, LAN function will be powered down (GPHY, PCIE, IPSEC, APE). This bit is cleared by a rising edge of PERST_L. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerDown, 4, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_14_5, 5, 10) /** @brief Setting this bit will powerdown SGMII-PCS module. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SGMII_DIV_PCSPowerDown, 15, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_21_16, 16, 6) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIePLLLockStatus, 22, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPHYPLLLockStatus, 23, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_24_24, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NCSIPLLLockStatus, 25, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TLPClockSource, 26, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SwitchingRegulatorPowerDown, 27, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, KeepNCSIPLLonduringlowpowermode_, 28, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_29, 29, 3) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_29, 29, 3) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, KeepNCSIPLLonduringlowpowermode_, 28, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SwitchingRegulatorPowerDown, 27, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TLPClockSource, 26, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NCSIPLLLockStatus, 25, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_24_24, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPHYPLLLockStatus, 23, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIePLLLockStatus, 22, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_21_16, 16, 6) /** @brief Setting this bit will powerdown SGMII-PCS module. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SGMII_DIV_PCSPowerDown, 15, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_14_5, 5, 10) /** @brief Force CPMU into Low Power State, LAN function will be powered down (GPHY, PCIE, IPSEC, APE). This bit is cleared by a rising edge of PERST_L. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerDown, 4, 1) /** @brief Software reset for resetting all the registers to default. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMURegisterSoftwareReset, 3, 1) /** @brief Software reset for all the CPMU logic expect for registers. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMUSoftwareReset, 2, 1) /** @brief When this bit is set, BIAS will be powered down. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BIASIDDQ, 1, 1) /** @brief When this bit is set, GPHY will be powered down. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPHYIDDQ, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "GphyControlStatus"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEGphyControlStatus_t() { /** @brief constructor for @ref DEVICE_t.GphyControlStatus. */ r32.setName("GphyControlStatus"); bits.GPHYIDDQ.setBaseRegister(&r32); bits.GPHYIDDQ.setName("GPHYIDDQ"); bits.BIASIDDQ.setBaseRegister(&r32); bits.BIASIDDQ.setName("BIASIDDQ"); bits.CPMUSoftwareReset.setBaseRegister(&r32); bits.CPMUSoftwareReset.setName("CPMUSoftwareReset"); bits.CPMURegisterSoftwareReset.setBaseRegister(&r32); bits.CPMURegisterSoftwareReset.setName("CPMURegisterSoftwareReset"); bits.PowerDown.setBaseRegister(&r32); bits.PowerDown.setName("PowerDown"); bits.SGMII_DIV_PCSPowerDown.setBaseRegister(&r32); bits.SGMII_DIV_PCSPowerDown.setName("SGMII_DIV_PCSPowerDown"); bits.PCIePLLLockStatus.setBaseRegister(&r32); bits.PCIePLLLockStatus.setName("PCIePLLLockStatus"); bits.GPHYPLLLockStatus.setBaseRegister(&r32); bits.GPHYPLLLockStatus.setName("GPHYPLLLockStatus"); bits.NCSIPLLLockStatus.setBaseRegister(&r32); bits.NCSIPLLLockStatus.setName("NCSIPLLLockStatus"); bits.TLPClockSource.setBaseRegister(&r32); bits.TLPClockSource.setName("TLPClockSource"); bits.SwitchingRegulatorPowerDown.setBaseRegister(&r32); bits.SwitchingRegulatorPowerDown.setName("SwitchingRegulatorPowerDown"); bits.KeepNCSIPLLonduringlowpowermode_.setBaseRegister(&r32); bits.KeepNCSIPLLonduringlowpowermode_.setName("KeepNCSIPLLonduringlowpowermode_"); } RegDEVICEGphyControlStatus_t& operator=(const RegDEVICEGphyControlStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEGphyControlStatus_t; #define REG_DEVICE_CHIP_ID ((volatile APE_DEVICE_H_uint32_t*)0xa0043658) /* */ /** @brief Register definition for @ref DEVICE_t.ChipId. */ typedef register_container RegDEVICEChipId_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ChipId"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEChipId_t() { /** @brief constructor for @ref DEVICE_t.ChipId. */ r32.setName("ChipId"); } RegDEVICEChipId_t& operator=(const RegDEVICEChipId_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEChipId_t; #define REG_DEVICE_MUTEX_REQUEST ((volatile APE_DEVICE_H_uint32_t*)0xa004365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ #define DEVICE_MUTEX_REQUEST_REQUEST_SHIFT 0u #define DEVICE_MUTEX_REQUEST_REQUEST_MASK 0xffffu #define GET_DEVICE_MUTEX_REQUEST_REQUEST(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_MUTEX_REQUEST_REQUEST(__val__) (((__val__) << 0u) & 0xffffu) /** @brief Register definition for @ref DEVICE_t.MutexRequest. */ typedef register_container RegDEVICEMutexRequest_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Request, 0, 16) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Request, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "MutexRequest"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEMutexRequest_t() { /** @brief constructor for @ref DEVICE_t.MutexRequest. */ r32.setName("MutexRequest"); bits.Request.setBaseRegister(&r32); bits.Request.setName("Request"); } RegDEVICEMutexRequest_t& operator=(const RegDEVICEMutexRequest_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEMutexRequest_t; #define REG_DEVICE_MUTEX_GRANT ((volatile APE_DEVICE_H_uint32_t*)0xa0043660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ #define DEVICE_MUTEX_GRANT_GRANTED_SHIFT 0u #define DEVICE_MUTEX_GRANT_GRANTED_MASK 0xffffu #define GET_DEVICE_MUTEX_GRANT_GRANTED(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_MUTEX_GRANT_GRANTED(__val__) (((__val__) << 0u) & 0xffffu) /** @brief Register definition for @ref DEVICE_t.MutexGrant. */ typedef register_container RegDEVICEMutexGrant_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Granted, 0, 16) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Granted, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "MutexGrant"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEMutexGrant_t() { /** @brief constructor for @ref DEVICE_t.MutexGrant. */ r32.setName("MutexGrant"); bits.Granted.setBaseRegister(&r32); bits.Granted.setName("Granted"); } RegDEVICEMutexGrant_t& operator=(const RegDEVICEMutexGrant_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEMutexGrant_t; #define REG_DEVICE_GPHY_STRAP ((volatile APE_DEVICE_H_uint32_t*)0xa0043664) /* */ #define DEVICE_GPHY_STRAP_TXMBUF_ECC_ENABLE_SHIFT 2u #define DEVICE_GPHY_STRAP_TXMBUF_ECC_ENABLE_MASK 0x4u #define GET_DEVICE_GPHY_STRAP_TXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_GPHY_STRAP_TXMBUF_ECC_ENABLE(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_GPHY_STRAP_RXMBUF_ECC_ENABLE_SHIFT 3u #define DEVICE_GPHY_STRAP_RXMBUF_ECC_ENABLE_MASK 0x8u #define GET_DEVICE_GPHY_STRAP_RXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_GPHY_STRAP_RXMBUF_ECC_ENABLE(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_SHIFT 4u #define DEVICE_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_MASK 0x10u #define GET_DEVICE_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE_SHIFT 8u #define DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE_MASK 0x100u #define GET_DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE(__val__) (((__val__) << 8u) & 0x100u) /** @brief Register definition for @ref DEVICE_t.GphyStrap. */ typedef register_container RegDEVICEGphyStrap_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_1_0, 0, 2) /** @brief Enable TXMBUF ECC. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TXMBUFECCEnable, 2, 1) /** @brief Enable RXMBUF ECC. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXMBUFECCEnable, 3, 1) /** @brief Enable ECC for rxcpu scratchpad. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXCPUSPADECCEnable, 4, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_5, 5, 3) /** @brief Enable APE CM3 Big Endian Setting */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APECM3BigEndianEnable, 8, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_9, 9, 23) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_9, 9, 23) /** @brief Enable APE CM3 Big Endian Setting */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APECM3BigEndianEnable, 8, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_5, 5, 3) /** @brief Enable ECC for rxcpu scratchpad. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXCPUSPADECCEnable, 4, 1) /** @brief Enable RXMBUF ECC. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXMBUFECCEnable, 3, 1) /** @brief Enable TXMBUF ECC. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TXMBUFECCEnable, 2, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_1_0, 0, 2) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "GphyStrap"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEGphyStrap_t() { /** @brief constructor for @ref DEVICE_t.GphyStrap. */ r32.setName("GphyStrap"); bits.TXMBUFECCEnable.setBaseRegister(&r32); bits.TXMBUFECCEnable.setName("TXMBUFECCEnable"); bits.RXMBUFECCEnable.setBaseRegister(&r32); bits.RXMBUFECCEnable.setName("RXMBUFECCEnable"); bits.RXCPUSPADECCEnable.setBaseRegister(&r32); bits.RXCPUSPADECCEnable.setName("RXCPUSPADECCEnable"); bits.APECM3BigEndianEnable.setBaseRegister(&r32); bits.APECM3BigEndianEnable.setName("APECM3BigEndianEnable"); } RegDEVICEGphyStrap_t& operator=(const RegDEVICEGphyStrap_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEGphyStrap_t; #define REG_DEVICE_FLASH_CLOCK_CONTROL_POLICY ((volatile APE_DEVICE_H_uint32_t*)0xa004366c) /* */ #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_SHIFT 0u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_MASK 0x3u #define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH(__reg__) (((__reg__) & 0x3) >> 0u) #define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH(__val__) (((__val__) << 0u) & 0x3u) #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_62_5_MHZ_NCSI_DLL 0x0u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_25_MHZ 0x3u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_SHIFT 4u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_MASK 0x70u #define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY(__reg__) (((__reg__) & 0x70) >> 4u) #define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY(__val__) (((__val__) << 4u) & 0x70u) #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_62_5_MHZ_NCSI_DLL 0x0u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_25_MHZ 0x3u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_SHIFT 8u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_MASK 0x700u #define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY(__reg__) (((__reg__) & 0x700) >> 8u) #define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY(__val__) (((__val__) << 8u) & 0x700u) #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_62_5_MHZ_NCSI_DLL 0x0u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_25_MHZ 0x3u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_SHIFT 12u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_MASK 0xff000u #define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY(__reg__) (((__reg__) & 0xff000) >> 12u) #define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY(__val__) (((__val__) << 12u) & 0xff000u) #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_4_8MHZ 0x0u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_1250_MHZ 0x1u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_125_MHZ 0xau #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE_SHIFT 28u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE_MASK 0x10000000u #define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE(__reg__) (((__reg__) & 0x10000000) >> 28u) #define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE(__val__) (((__val__) << 28u) & 0x10000000u) #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE_SHIFT 29u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE_MASK 0x20000000u #define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE(__reg__) (((__reg__) & 0x20000000) >> 29u) #define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE(__val__) (((__val__) << 29u) & 0x20000000u) #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE_SHIFT 30u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE_MASK 0x40000000u #define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE(__reg__) (((__reg__) & 0x40000000) >> 30u) #define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE(__val__) (((__val__) << 30u) & 0x40000000u) #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE_SHIFT 31u #define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE_MASK 0x80000000u #define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE(__reg__) (((__reg__) & 0x80000000) >> 31u) #define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref DEVICE_t.FlashClockControlPolicy. */ typedef register_container RegDEVICEFlashClockControlPolicy_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Software Controlled Flash Clock Speed */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, OverrideFlashClockSwitch, 0, 2) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_3_2, 2, 2) /** @brief Software Controlled Flash Clock Speed */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashClockPolicy, 4, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_7, 7, 1) /** @brief Software Controlled Flash Clock Speed */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashIdleClockPolicy, 8, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_11_11, 11, 1) /** @brief Software Controlled EAV Clock Speed Select */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EAVClockPolicy, 12, 8) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_27_20, 20, 8) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceEAVClockDisable, 28, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashIdlemodeEnable, 29, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceFlashClockDisable, 30, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashClockSpeedOverride, 31, 1) #elif defined(__BIG_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashClockSpeedOverride, 31, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceFlashClockDisable, 30, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashIdlemodeEnable, 29, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceEAVClockDisable, 28, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_27_20, 20, 8) /** @brief Software Controlled EAV Clock Speed Select */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EAVClockPolicy, 12, 8) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_11_11, 11, 1) /** @brief Software Controlled Flash Clock Speed */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashIdleClockPolicy, 8, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_7, 7, 1) /** @brief Software Controlled Flash Clock Speed */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashClockPolicy, 4, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_3_2, 2, 2) /** @brief Software Controlled Flash Clock Speed */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, OverrideFlashClockSwitch, 0, 2) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "FlashClockControlPolicy"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEFlashClockControlPolicy_t() { /** @brief constructor for @ref DEVICE_t.FlashClockControlPolicy. */ r32.setName("FlashClockControlPolicy"); bits.OverrideFlashClockSwitch.setBaseRegister(&r32); bits.OverrideFlashClockSwitch.setName("OverrideFlashClockSwitch"); bits.OverrideFlashClockSwitch.addEnum("62.5 MHz NCSI DLL", 0x0); bits.OverrideFlashClockSwitch.addEnum("25 MHz", 0x3); bits.FlashClockPolicy.setBaseRegister(&r32); bits.FlashClockPolicy.setName("FlashClockPolicy"); bits.FlashClockPolicy.addEnum("62.5 MHz NCSI DLL", 0x0); bits.FlashClockPolicy.addEnum("25 MHz", 0x3); bits.FlashIdleClockPolicy.setBaseRegister(&r32); bits.FlashIdleClockPolicy.setName("FlashIdleClockPolicy"); bits.FlashIdleClockPolicy.addEnum("62.5 MHz NCSI DLL", 0x0); bits.FlashIdleClockPolicy.addEnum("25 MHz", 0x3); bits.EAVClockPolicy.setBaseRegister(&r32); bits.EAVClockPolicy.setName("EAVClockPolicy"); bits.EAVClockPolicy.addEnum("4.8MHz", 0x0); bits.EAVClockPolicy.addEnum("1250 MHz", 0x1); bits.EAVClockPolicy.addEnum("125 MHz", 0xa); bits.ForceEAVClockDisable.setBaseRegister(&r32); bits.ForceEAVClockDisable.setName("ForceEAVClockDisable"); bits.FlashIdlemodeEnable.setBaseRegister(&r32); bits.FlashIdlemodeEnable.setName("FlashIdlemodeEnable"); bits.ForceFlashClockDisable.setBaseRegister(&r32); bits.ForceFlashClockDisable.setName("ForceFlashClockDisable"); bits.FlashClockSpeedOverride.setBaseRegister(&r32); bits.FlashClockSpeedOverride.setName("FlashClockSpeedOverride"); } RegDEVICEFlashClockControlPolicy_t& operator=(const RegDEVICEFlashClockControlPolicy_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEFlashClockControlPolicy_t; #define REG_DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE_H_uint32_t*)0xa004367c) /* */ #define DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_SHIFT 4u #define DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_MASK 0x10u #define GET_DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_SHIFT 5u #define DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_MASK 0x20u #define GET_DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__val__) (((__val__) << 5u) & 0x20u) /** @brief Register definition for @ref DEVICE_t.TopLevelMiscellaneousControl1. */ typedef register_container RegDEVICETopLevelMiscellaneousControl1_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_3_0, 0, 4) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NCSIClockOutputDisable, 4, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LowPowerIDDQMode, 5, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_6, 6, 26) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_6, 6, 26) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LowPowerIDDQMode, 5, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NCSIClockOutputDisable, 4, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_3_0, 0, 4) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "TopLevelMiscellaneousControl1"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICETopLevelMiscellaneousControl1_t() { /** @brief constructor for @ref DEVICE_t.TopLevelMiscellaneousControl1. */ r32.setName("TopLevelMiscellaneousControl1"); bits.NCSIClockOutputDisable.setBaseRegister(&r32); bits.NCSIClockOutputDisable.setName("NCSIClockOutputDisable"); bits.LowPowerIDDQMode.setBaseRegister(&r32); bits.LowPowerIDDQMode.setName("LowPowerIDDQMode"); } RegDEVICETopLevelMiscellaneousControl1_t& operator=(const RegDEVICETopLevelMiscellaneousControl1_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICETopLevelMiscellaneousControl1_t; #define REG_DEVICE_EEE_MODE ((volatile APE_DEVICE_H_uint32_t*)0xa00436b0) /* */ #define DEVICE_EEE_MODE_RX_CPU_ALLOW_LPI_SHIFT 0u #define DEVICE_EEE_MODE_RX_CPU_ALLOW_LPI_MASK 0x1u #define GET_DEVICE_EEE_MODE_RX_CPU_ALLOW_LPI(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_EEE_MODE_RX_CPU_ALLOW_LPI(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_EEE_MODE_DRIVE_ALLOW_LPI_SHIFT 1u #define DEVICE_EEE_MODE_DRIVE_ALLOW_LPI_MASK 0x2u #define GET_DEVICE_EEE_MODE_DRIVE_ALLOW_LPI(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_EEE_MODE_DRIVE_ALLOW_LPI(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_EEE_MODE_APE_TX_DETECTION_ENABLE_SHIFT 2u #define DEVICE_EEE_MODE_APE_TX_DETECTION_ENABLE_MASK 0x4u #define GET_DEVICE_EEE_MODE_APE_TX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_EEE_MODE_APE_TX_DETECTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_SHIFT 3u #define DEVICE_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_MASK 0x8u #define GET_DEVICE_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_SHIFT 4u #define DEVICE_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_MASK 0x10u #define GET_DEVICE_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_SHIFT 5u #define DEVICE_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_MASK 0x20u #define GET_DEVICE_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__val__) (((__val__) << 5u) & 0x20u) #define DEVICE_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_SHIFT 6u #define DEVICE_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_MASK 0x40u #define GET_DEVICE_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40) >> 6u) #define SET_DEVICE_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__val__) (((__val__) << 6u) & 0x40u) #define DEVICE_EEE_MODE_USER_LPI_ENABLE_SHIFT 7u #define DEVICE_EEE_MODE_USER_LPI_ENABLE_MASK 0x80u #define GET_DEVICE_EEE_MODE_USER_LPI_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) #define SET_DEVICE_EEE_MODE_USER_LPI_ENABLE(__val__) (((__val__) << 7u) & 0x80u) #define DEVICE_EEE_MODE_TX_LPI_ENABLE_SHIFT 8u #define DEVICE_EEE_MODE_TX_LPI_ENABLE_MASK 0x100u #define GET_DEVICE_EEE_MODE_TX_LPI_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_EEE_MODE_TX_LPI_ENABLE(__val__) (((__val__) << 8u) & 0x100u) #define DEVICE_EEE_MODE_RX_LPI_ENABLE_SHIFT 9u #define DEVICE_EEE_MODE_RX_LPI_ENABLE_MASK 0x200u #define GET_DEVICE_EEE_MODE_RX_LPI_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) #define SET_DEVICE_EEE_MODE_RX_LPI_ENABLE(__val__) (((__val__) << 9u) & 0x200u) #define DEVICE_EEE_MODE_AUTO_WAKE_ENABLE_SHIFT 10u #define DEVICE_EEE_MODE_AUTO_WAKE_ENABLE_MASK 0x400u #define GET_DEVICE_EEE_MODE_AUTO_WAKE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) #define SET_DEVICE_EEE_MODE_AUTO_WAKE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) #define DEVICE_EEE_MODE_BLOCK_TIME_SHIFT 11u #define DEVICE_EEE_MODE_BLOCK_TIME_MASK 0x7f800u #define GET_DEVICE_EEE_MODE_BLOCK_TIME(__reg__) (((__reg__) & 0x7f800) >> 11u) #define SET_DEVICE_EEE_MODE_BLOCK_TIME(__val__) (((__val__) << 11u) & 0x7f800u) #define DEVICE_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_SHIFT 19u #define DEVICE_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_MASK 0x80000u #define GET_DEVICE_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) #define SET_DEVICE_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) /** @brief Register definition for @ref DEVICE_t.EeeMode. */ typedef register_container RegDEVICEEeeMode_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXCPUAllowLPI, 0, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DriveAllowLPI, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APETXDetectionEnable, 2, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EEELinkIdleDetectionEnable, 3, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIeL1ExitDetectionEnable, 4, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXCPUAllowLPIEnable, 5, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SendIndexDetectionEnable, 6, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, UserLPIEnable, 7, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TXLPIEnable, 8, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXLPIEnable, 9, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AutoWakeEnable, 10, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BlockTime, 11, 8) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DriveAllowLPIEnable, 19, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_20, 20, 12) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_20, 20, 12) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DriveAllowLPIEnable, 19, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BlockTime, 11, 8) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AutoWakeEnable, 10, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXLPIEnable, 9, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TXLPIEnable, 8, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, UserLPIEnable, 7, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SendIndexDetectionEnable, 6, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXCPUAllowLPIEnable, 5, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIeL1ExitDetectionEnable, 4, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EEELinkIdleDetectionEnable, 3, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APETXDetectionEnable, 2, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DriveAllowLPI, 1, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXCPUAllowLPI, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EeeMode"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEeeMode_t() { /** @brief constructor for @ref DEVICE_t.EeeMode. */ r32.setName("EeeMode"); bits.RXCPUAllowLPI.setBaseRegister(&r32); bits.RXCPUAllowLPI.setName("RXCPUAllowLPI"); bits.DriveAllowLPI.setBaseRegister(&r32); bits.DriveAllowLPI.setName("DriveAllowLPI"); bits.APETXDetectionEnable.setBaseRegister(&r32); bits.APETXDetectionEnable.setName("APETXDetectionEnable"); bits.EEELinkIdleDetectionEnable.setBaseRegister(&r32); bits.EEELinkIdleDetectionEnable.setName("EEELinkIdleDetectionEnable"); bits.PCIeL1ExitDetectionEnable.setBaseRegister(&r32); bits.PCIeL1ExitDetectionEnable.setName("PCIeL1ExitDetectionEnable"); bits.RXCPUAllowLPIEnable.setBaseRegister(&r32); bits.RXCPUAllowLPIEnable.setName("RXCPUAllowLPIEnable"); bits.SendIndexDetectionEnable.setBaseRegister(&r32); bits.SendIndexDetectionEnable.setName("SendIndexDetectionEnable"); bits.UserLPIEnable.setBaseRegister(&r32); bits.UserLPIEnable.setName("UserLPIEnable"); bits.TXLPIEnable.setBaseRegister(&r32); bits.TXLPIEnable.setName("TXLPIEnable"); bits.RXLPIEnable.setBaseRegister(&r32); bits.RXLPIEnable.setName("RXLPIEnable"); bits.AutoWakeEnable.setBaseRegister(&r32); bits.AutoWakeEnable.setName("AutoWakeEnable"); bits.BlockTime.setBaseRegister(&r32); bits.BlockTime.setName("BlockTime"); bits.DriveAllowLPIEnable.setBaseRegister(&r32); bits.DriveAllowLPIEnable.setName("DriveAllowLPIEnable"); } RegDEVICEEeeMode_t& operator=(const RegDEVICEEeeMode_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEeeMode_t; #define REG_DEVICE_EEE_LINK_IDLE_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa00436bc) /* */ #define DEVICE_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_SHIFT 2u #define DEVICE_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_MASK 0x4u #define GET_DEVICE_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__val__) (((__val__) << 2u) & 0x4u) /** @brief Register definition for @ref DEVICE_t.EeeLinkIdleControl. */ typedef register_container RegDEVICEEeeLinkIdleControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_1_0, 0, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DebugUARTIdle, 2, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_3, 3, 29) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_3, 3, 29) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DebugUARTIdle, 2, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_1_0, 0, 2) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EeeLinkIdleControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEeeLinkIdleControl_t() { /** @brief constructor for @ref DEVICE_t.EeeLinkIdleControl. */ r32.setName("EeeLinkIdleControl"); bits.DebugUARTIdle.setBaseRegister(&r32); bits.DebugUARTIdle.setName("DebugUARTIdle"); } RegDEVICEEeeLinkIdleControl_t& operator=(const RegDEVICEEeeLinkIdleControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEeeLinkIdleControl_t; #define REG_DEVICE_EEE_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa00436d0) /* */ #define DEVICE_EEE_CONTROL_EXIT_TIME_SHIFT 0u #define DEVICE_EEE_CONTROL_EXIT_TIME_MASK 0xffffu #define GET_DEVICE_EEE_CONTROL_EXIT_TIME(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_EEE_CONTROL_EXIT_TIME(__val__) (((__val__) << 0u) & 0xffffu) #define DEVICE_EEE_CONTROL_EXIT_TIME_16_5_US 0x19du #define DEVICE_EEE_CONTROL_EXIT_TIME_20_1_US 0x1f8u #define DEVICE_EEE_CONTROL_EXIT_TIME_36_US 0x384u #define DEVICE_EEE_CONTROL_MINIMUM_ASSERT_SHIFT 16u #define DEVICE_EEE_CONTROL_MINIMUM_ASSERT_MASK 0xffff0000u #define GET_DEVICE_EEE_CONTROL_MINIMUM_ASSERT(__reg__) (((__reg__) & 0xffff0000) >> 16u) #define SET_DEVICE_EEE_CONTROL_MINIMUM_ASSERT(__val__) (((__val__) << 16u) & 0xffff0000u) /** @brief Register definition for @ref DEVICE_t.EeeControl. */ typedef register_container RegDEVICEEeeControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ExitTime, 0, 16) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MinimumAssert, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MinimumAssert, 16, 16) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ExitTime, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EeeControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEeeControl_t() { /** @brief constructor for @ref DEVICE_t.EeeControl. */ r32.setName("EeeControl"); bits.ExitTime.setBaseRegister(&r32); bits.ExitTime.setName("ExitTime"); bits.ExitTime.addEnum("16.5 us", 0x19d); bits.ExitTime.addEnum("20.1 us", 0x1f8); bits.ExitTime.addEnum("36 us", 0x384); bits.MinimumAssert.setBaseRegister(&r32); bits.MinimumAssert.setName("MinimumAssert"); } RegDEVICEEeeControl_t& operator=(const RegDEVICEEeeControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEeeControl_t; #define REG_DEVICE_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE_H_uint32_t*)0xa00436f0) /* */ #define DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST_SHIFT 0u #define DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST_MASK 0xffffu #define GET_DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST(__val__) (((__val__) << 0u) & 0xffffu) /** @brief Register definition for @ref DEVICE_t.GlobalMutexRequest. */ typedef register_container RegDEVICEGlobalMutexRequest_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Request, 0, 16) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Request, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "GlobalMutexRequest"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEGlobalMutexRequest_t() { /** @brief constructor for @ref DEVICE_t.GlobalMutexRequest. */ r32.setName("GlobalMutexRequest"); bits.Request.setBaseRegister(&r32); bits.Request.setName("Request"); } RegDEVICEGlobalMutexRequest_t& operator=(const RegDEVICEGlobalMutexRequest_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEGlobalMutexRequest_t; #define REG_DEVICE_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE_H_uint32_t*)0xa00436f4) /* */ #define DEVICE_GLOBAL_MUTEX_GRANT_GRANTED_SHIFT 0u #define DEVICE_GLOBAL_MUTEX_GRANT_GRANTED_MASK 0xffffu #define GET_DEVICE_GLOBAL_MUTEX_GRANT_GRANTED(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_GLOBAL_MUTEX_GRANT_GRANTED(__val__) (((__val__) << 0u) & 0xffffu) /** @brief Register definition for @ref DEVICE_t.GlobalMutexGrant. */ typedef register_container RegDEVICEGlobalMutexGrant_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Granted, 0, 16) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16) /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Granted, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "GlobalMutexGrant"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEGlobalMutexGrant_t() { /** @brief constructor for @ref DEVICE_t.GlobalMutexGrant. */ r32.setName("GlobalMutexGrant"); bits.Granted.setBaseRegister(&r32); bits.Granted.setName("Granted"); } RegDEVICEGlobalMutexGrant_t& operator=(const RegDEVICEGlobalMutexGrant_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEGlobalMutexGrant_t; #define REG_DEVICE_TEMPERATURE_MONITOR_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa00436fc) /* */ #define DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE_SHIFT 0u #define DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE_MASK 0x1u #define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST_SHIFT 1u #define DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST_MASK 0xfeu #define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST(__reg__) (((__reg__) & 0xfe) >> 1u) #define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST(__val__) (((__val__) << 1u) & 0xfeu) #define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA_SHIFT 8u #define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA_MASK 0xff00u #define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA(__reg__) (((__reg__) & 0xff00) >> 8u) #define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA(__val__) (((__val__) << 8u) & 0xff00u) #define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD_SHIFT 17u #define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD_MASK 0x20000u #define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD(__reg__) (((__reg__) & 0x20000) >> 17u) #define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD(__val__) (((__val__) << 17u) & 0x20000u) #define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN_SHIFT 18u #define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN_MASK 0x40000u #define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN(__reg__) (((__reg__) & 0x40000) >> 18u) #define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN(__val__) (((__val__) << 18u) & 0x40000u) /** @brief Register definition for @ref DEVICE_t.TemperatureMonitorControl. */ typedef register_container RegDEVICETemperatureMonitorControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ADCTestEnable, 0, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BiasAdjust, 1, 7) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureData, 8, 8) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_16_16, 16, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureMonitorHold, 17, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureMonitorPowerDown, 18, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_19, 19, 13) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_19, 19, 13) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureMonitorPowerDown, 18, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureMonitorHold, 17, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_16_16, 16, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureData, 8, 8) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BiasAdjust, 1, 7) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ADCTestEnable, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "TemperatureMonitorControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICETemperatureMonitorControl_t() { /** @brief constructor for @ref DEVICE_t.TemperatureMonitorControl. */ r32.setName("TemperatureMonitorControl"); bits.ADCTestEnable.setBaseRegister(&r32); bits.ADCTestEnable.setName("ADCTestEnable"); bits.BiasAdjust.setBaseRegister(&r32); bits.BiasAdjust.setName("BiasAdjust"); bits.TemperatureData.setBaseRegister(&r32); bits.TemperatureData.setName("TemperatureData"); bits.TemperatureMonitorHold.setBaseRegister(&r32); bits.TemperatureMonitorHold.setName("TemperatureMonitorHold"); bits.TemperatureMonitorPowerDown.setBaseRegister(&r32); bits.TemperatureMonitorPowerDown.setName("TemperatureMonitorPowerDown"); } RegDEVICETemperatureMonitorControl_t& operator=(const RegDEVICETemperatureMonitorControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICETemperatureMonitorControl_t; #define REG_DEVICE_MEMORY_ARBITER_MODE ((volatile APE_DEVICE_H_uint32_t*)0xa0044000) /* */ #define DEVICE_MEMORY_ARBITER_MODE_ENABLE_SHIFT 1u #define DEVICE_MEMORY_ARBITER_MODE_ENABLE_MASK 0x2u #define GET_DEVICE_MEMORY_ARBITER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_MEMORY_ARBITER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) /** @brief Register definition for @ref DEVICE_t.MemoryArbiterMode. */ typedef register_container RegDEVICEMemoryArbiterMode_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Enable, 1, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_2, 2, 30) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_2, 2, 30) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Enable, 1, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "MemoryArbiterMode"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEMemoryArbiterMode_t() { /** @brief constructor for @ref DEVICE_t.MemoryArbiterMode. */ r32.setName("MemoryArbiterMode"); bits.Enable.setBaseRegister(&r32); bits.Enable.setName("Enable"); } RegDEVICEMemoryArbiterMode_t& operator=(const RegDEVICEMemoryArbiterMode_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEMemoryArbiterMode_t; #define REG_DEVICE_BUFFER_MANAGER_MODE ((volatile APE_DEVICE_H_uint32_t*)0xa0044400) /* */ #define DEVICE_BUFFER_MANAGER_MODE_ENABLE_SHIFT 1u #define DEVICE_BUFFER_MANAGER_MODE_ENABLE_MASK 0x2u #define GET_DEVICE_BUFFER_MANAGER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_BUFFER_MANAGER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_SHIFT 2u #define DEVICE_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_MASK 0x4u #define GET_DEVICE_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_SHIFT 5u #define DEVICE_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_MASK 0x20u #define GET_DEVICE_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__val__) (((__val__) << 5u) & 0x20u) /** @brief Register definition for @ref DEVICE_t.BufferManagerMode. */ typedef register_container RegDEVICEBufferManagerMode_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1) /** @brief This bit controls whether the Buffer Manager is active or not. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Enable, 1, 1) /** @brief When this bit is set to 1, an internal attention is generated when an error occurs. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AttentionEnable, 2, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_3, 3, 2) /** @brief When this bit is set, it will cause the RXMBUF allocation and deallocation pointer to reset back to the RXMBUF base. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ResetRXMBUFPointer, 5, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_6, 6, 26) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_6, 6, 26) /** @brief When this bit is set, it will cause the RXMBUF allocation and deallocation pointer to reset back to the RXMBUF base. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ResetRXMBUFPointer, 5, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_3, 3, 2) /** @brief When this bit is set to 1, an internal attention is generated when an error occurs. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AttentionEnable, 2, 1) /** @brief This bit controls whether the Buffer Manager is active or not. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Enable, 1, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "BufferManagerMode"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEBufferManagerMode_t() { /** @brief constructor for @ref DEVICE_t.BufferManagerMode. */ r32.setName("BufferManagerMode"); bits.Enable.setBaseRegister(&r32); bits.Enable.setName("Enable"); bits.AttentionEnable.setBaseRegister(&r32); bits.AttentionEnable.setName("AttentionEnable"); bits.ResetRXMBUFPointer.setBaseRegister(&r32); bits.ResetRXMBUFPointer.setName("ResetRXMBUFPointer"); } RegDEVICEBufferManagerMode_t& operator=(const RegDEVICEBufferManagerMode_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEBufferManagerMode_t; #define REG_DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa0044910) /* */ #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_SHIFT 16u #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_MASK 0x30000u #define GET_DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__reg__) (((__reg__) & 0x30000) >> 16u) #define SET_DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__val__) (((__val__) << 16u) & 0x30000u) #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_128B 0x0u #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_256B 0x1u #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_512B 0x2u #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_4K 0x3u #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_SHIFT 18u #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_MASK 0xc0000u #define GET_DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__reg__) (((__reg__) & 0xc0000) >> 18u) #define SET_DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__val__) (((__val__) << 18u) & 0xc0000u) #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_128B 0x0u #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_256B 0x1u #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_512B 0x2u #define DEVICE_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_4K 0x3u /** @brief Register definition for @ref DEVICE_t.LsoNonlsoBdReadDmaCorruptionEnableControl. */ typedef register_container RegDEVICELsoNonlsoBdReadDmaCorruptionEnableControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIRequestBurstLengthforBDRDMAEngine, 16, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIRequestBurstLengthforNonLSORDMAEngine, 18, 2) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_20, 20, 12) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_20, 20, 12) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIRequestBurstLengthforNonLSORDMAEngine, 18, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIRequestBurstLengthforBDRDMAEngine, 16, 2) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "LsoNonlsoBdReadDmaCorruptionEnableControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICELsoNonlsoBdReadDmaCorruptionEnableControl_t() { /** @brief constructor for @ref DEVICE_t.LsoNonlsoBdReadDmaCorruptionEnableControl. */ r32.setName("LsoNonlsoBdReadDmaCorruptionEnableControl"); bits.PCIRequestBurstLengthforBDRDMAEngine.setBaseRegister(&r32); bits.PCIRequestBurstLengthforBDRDMAEngine.setName("PCIRequestBurstLengthforBDRDMAEngine"); bits.PCIRequestBurstLengthforBDRDMAEngine.addEnum("128B", 0x0); bits.PCIRequestBurstLengthforBDRDMAEngine.addEnum("256B", 0x1); bits.PCIRequestBurstLengthforBDRDMAEngine.addEnum("512B", 0x2); bits.PCIRequestBurstLengthforBDRDMAEngine.addEnum("4K", 0x3); bits.PCIRequestBurstLengthforNonLSORDMAEngine.setBaseRegister(&r32); bits.PCIRequestBurstLengthforNonLSORDMAEngine.setName("PCIRequestBurstLengthforNonLSORDMAEngine"); bits.PCIRequestBurstLengthforNonLSORDMAEngine.addEnum("128B", 0x0); bits.PCIRequestBurstLengthforNonLSORDMAEngine.addEnum("256B", 0x1); bits.PCIRequestBurstLengthforNonLSORDMAEngine.addEnum("512B", 0x2); bits.PCIRequestBurstLengthforNonLSORDMAEngine.addEnum("4K", 0x3); } RegDEVICELsoNonlsoBdReadDmaCorruptionEnableControl_t& operator=(const RegDEVICELsoNonlsoBdReadDmaCorruptionEnableControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICELsoNonlsoBdReadDmaCorruptionEnableControl_t; #define REG_DEVICE_RX_RISC_MODE ((volatile APE_DEVICE_H_uint32_t*)0xa0045000) /* */ #define DEVICE_RX_RISC_MODE_RESET_SHIFT 0u #define DEVICE_RX_RISC_MODE_RESET_MASK 0x1u #define GET_DEVICE_RX_RISC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_RX_RISC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_RX_RISC_MODE_SINGLE_STEP_SHIFT 1u #define DEVICE_RX_RISC_MODE_SINGLE_STEP_MASK 0x2u #define GET_DEVICE_RX_RISC_MODE_SINGLE_STEP(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_RX_RISC_MODE_SINGLE_STEP(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_RX_RISC_MODE_PAGE_0_DATA_HALT_SHIFT 2u #define DEVICE_RX_RISC_MODE_PAGE_0_DATA_HALT_MASK 0x4u #define GET_DEVICE_RX_RISC_MODE_PAGE_0_DATA_HALT(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_RX_RISC_MODE_PAGE_0_DATA_HALT(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_RX_RISC_MODE_PAGE_0_INSTR_HALT_SHIFT 3u #define DEVICE_RX_RISC_MODE_PAGE_0_INSTR_HALT_MASK 0x8u #define GET_DEVICE_RX_RISC_MODE_PAGE_0_INSTR_HALT(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_RX_RISC_MODE_PAGE_0_INSTR_HALT(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_RX_RISC_MODE_ENABLE_DATA_CACHE_SHIFT 5u #define DEVICE_RX_RISC_MODE_ENABLE_DATA_CACHE_MASK 0x20u #define GET_DEVICE_RX_RISC_MODE_ENABLE_DATA_CACHE(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_RX_RISC_MODE_ENABLE_DATA_CACHE(__val__) (((__val__) << 5u) & 0x20u) #define DEVICE_RX_RISC_MODE_ROM_FAIL_SHIFT 6u #define DEVICE_RX_RISC_MODE_ROM_FAIL_MASK 0x40u #define GET_DEVICE_RX_RISC_MODE_ROM_FAIL(__reg__) (((__reg__) & 0x40) >> 6u) #define SET_DEVICE_RX_RISC_MODE_ROM_FAIL(__val__) (((__val__) << 6u) & 0x40u) #define DEVICE_RX_RISC_MODE_ENABLE_WATCHDOG_SHIFT 7u #define DEVICE_RX_RISC_MODE_ENABLE_WATCHDOG_MASK 0x80u #define GET_DEVICE_RX_RISC_MODE_ENABLE_WATCHDOG(__reg__) (((__reg__) & 0x80) >> 7u) #define SET_DEVICE_RX_RISC_MODE_ENABLE_WATCHDOG(__val__) (((__val__) << 7u) & 0x80u) #define DEVICE_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_SHIFT 8u #define DEVICE_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_MASK 0x100u #define GET_DEVICE_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__val__) (((__val__) << 8u) & 0x100u) #define DEVICE_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_SHIFT 9u #define DEVICE_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_MASK 0x200u #define GET_DEVICE_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x200) >> 9u) #define SET_DEVICE_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__val__) (((__val__) << 9u) & 0x200u) #define DEVICE_RX_RISC_MODE_HALT_SHIFT 10u #define DEVICE_RX_RISC_MODE_HALT_MASK 0x400u #define GET_DEVICE_RX_RISC_MODE_HALT(__reg__) (((__reg__) & 0x400) >> 10u) #define SET_DEVICE_RX_RISC_MODE_HALT(__val__) (((__val__) << 10u) & 0x400u) #define DEVICE_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_SHIFT 11u #define DEVICE_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_MASK 0x800u #define GET_DEVICE_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__reg__) (((__reg__) & 0x800) >> 11u) #define SET_DEVICE_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__val__) (((__val__) << 11u) & 0x800u) #define DEVICE_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_SHIFT 12u #define DEVICE_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_MASK 0x1000u #define GET_DEVICE_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__reg__) (((__reg__) & 0x1000) >> 12u) #define SET_DEVICE_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__val__) (((__val__) << 12u) & 0x1000u) #define DEVICE_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_SHIFT 13u #define DEVICE_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_MASK 0x2000u #define GET_DEVICE_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x2000) >> 13u) #define SET_DEVICE_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__val__) (((__val__) << 13u) & 0x2000u) #define DEVICE_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_SHIFT 14u #define DEVICE_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_MASK 0x4000u #define GET_DEVICE_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x4000) >> 14u) #define SET_DEVICE_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__val__) (((__val__) << 14u) & 0x4000u) /** @brief Register definition for @ref DEVICE_t.RxRiscMode. */ typedef register_container RegDEVICERxRiscMode_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Self-clearing bit which resets only the RX RISC. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Reset, 0, 1) /** @brief Advances the RX RISC's PC for one cycle. If halting condition still exists, the RX RISC will again halt; otherwise, it will resume normal operation. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SingleStep, 1, 1) /** @brief When set, data references to the first 256 bytes of SRAM force the RX RISC to halt and cause bit 3 in the RX RISC state register to be latched. Cleared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Page0DataHalt, 2, 1) /** @brief When set, instruction references to the first 256 bytes of SRAM force the RX RISC to halt and cause bit 4 in the RX RISC state register to be latched. Cleared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Page0InstrHalt, 3, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_4, 4, 1) /** @brief Enables the data cache. Cleared on reset. Note: Firmware developers should take care to clear this bit before polling internal SRAM memory locations, because the RX RISC processor uses a two-element LRU caching algorithm, which is not affected by writes from the PCI interface. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableDataCache, 5, 1) /** @brief Asserted on reset. Cleared by ROM code after it successfully loads code from NVRAM. Afterwards, this bit can be used by software for any purpose. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ROMFail, 6, 1) /** @brief Enables watchdog interrupt state machine. Used in conjunction with Watchdog Clear register, Watchdog Saved PC register and Watchdog Vector register. Cleared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableWatchdog, 7, 1) /** @brief Enables prefetch logic within the instruction cache. When disabled only a single cache line is read on a cache miss. Cleared on reset. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableInstructionCache, 8, 1) /** @brief Self-clearing bit which forces the instruction cache to flush. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlushInstructionCache, 9, 1) /** @brief Set by TX RISC or the host to halt the RX RISC. Cleared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Halt, 10, 1) /** @brief When set, the condition that causes RX RISC state bit 5 to be set, also halts the RX RISC. Set by reset. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InvalidDataAccessHalt, 11, 1) /** @brief When set, the condition that causes RX RISC state bit 6 to be set, also halts the RX RISC. Set by reset. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InvalidInstructionAccessHalt, 12, 1) /** @brief When set, if the MA raises the trap signal to this processor, it will halt. CLeared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableMemoryAddressTrapHalt, 13, 1) /** @brief When set, if the GRC raises the trap signal to this processor, it will halt. CLeared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableRegisterAddressTrapHalt, 14, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_15, 15, 17) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_15, 15, 17) /** @brief When set, if the GRC raises the trap signal to this processor, it will halt. CLeared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableRegisterAddressTrapHalt, 14, 1) /** @brief When set, if the MA raises the trap signal to this processor, it will halt. CLeared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableMemoryAddressTrapHalt, 13, 1) /** @brief When set, the condition that causes RX RISC state bit 6 to be set, also halts the RX RISC. Set by reset. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InvalidInstructionAccessHalt, 12, 1) /** @brief When set, the condition that causes RX RISC state bit 5 to be set, also halts the RX RISC. Set by reset. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InvalidDataAccessHalt, 11, 1) /** @brief Set by TX RISC or the host to halt the RX RISC. Cleared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Halt, 10, 1) /** @brief Self-clearing bit which forces the instruction cache to flush. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlushInstructionCache, 9, 1) /** @brief Enables prefetch logic within the instruction cache. When disabled only a single cache line is read on a cache miss. Cleared on reset. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableInstructionCache, 8, 1) /** @brief Enables watchdog interrupt state machine. Used in conjunction with Watchdog Clear register, Watchdog Saved PC register and Watchdog Vector register. Cleared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableWatchdog, 7, 1) /** @brief Asserted on reset. Cleared by ROM code after it successfully loads code from NVRAM. Afterwards, this bit can be used by software for any purpose. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ROMFail, 6, 1) /** @brief Enables the data cache. Cleared on reset. Note: Firmware developers should take care to clear this bit before polling internal SRAM memory locations, because the RX RISC processor uses a two-element LRU caching algorithm, which is not affected by writes from the PCI interface. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EnableDataCache, 5, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_4, 4, 1) /** @brief When set, instruction references to the first 256 bytes of SRAM force the RX RISC to halt and cause bit 4 in the RX RISC state register to be latched. Cleared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Page0InstrHalt, 3, 1) /** @brief When set, data references to the first 256 bytes of SRAM force the RX RISC to halt and cause bit 3 in the RX RISC state register to be latched. Cleared on reset and Watchdog interrupt. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Page0DataHalt, 2, 1) /** @brief Advances the RX RISC's PC for one cycle. If halting condition still exists, the RX RISC will again halt; otherwise, it will resume normal operation. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SingleStep, 1, 1) /** @brief Self-clearing bit which resets only the RX RISC. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Reset, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscMode"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscMode_t() { /** @brief constructor for @ref DEVICE_t.RxRiscMode. */ r32.setName("RxRiscMode"); bits.Reset.setBaseRegister(&r32); bits.Reset.setName("Reset"); bits.SingleStep.setBaseRegister(&r32); bits.SingleStep.setName("SingleStep"); bits.Page0DataHalt.setBaseRegister(&r32); bits.Page0DataHalt.setName("Page0DataHalt"); bits.Page0InstrHalt.setBaseRegister(&r32); bits.Page0InstrHalt.setName("Page0InstrHalt"); bits.EnableDataCache.setBaseRegister(&r32); bits.EnableDataCache.setName("EnableDataCache"); bits.ROMFail.setBaseRegister(&r32); bits.ROMFail.setName("ROMFail"); bits.EnableWatchdog.setBaseRegister(&r32); bits.EnableWatchdog.setName("EnableWatchdog"); bits.EnableInstructionCache.setBaseRegister(&r32); bits.EnableInstructionCache.setName("EnableInstructionCache"); bits.FlushInstructionCache.setBaseRegister(&r32); bits.FlushInstructionCache.setName("FlushInstructionCache"); bits.Halt.setBaseRegister(&r32); bits.Halt.setName("Halt"); bits.InvalidDataAccessHalt.setBaseRegister(&r32); bits.InvalidDataAccessHalt.setName("InvalidDataAccessHalt"); bits.InvalidInstructionAccessHalt.setBaseRegister(&r32); bits.InvalidInstructionAccessHalt.setName("InvalidInstructionAccessHalt"); bits.EnableMemoryAddressTrapHalt.setBaseRegister(&r32); bits.EnableMemoryAddressTrapHalt.setName("EnableMemoryAddressTrapHalt"); bits.EnableRegisterAddressTrapHalt.setBaseRegister(&r32); bits.EnableRegisterAddressTrapHalt.setName("EnableRegisterAddressTrapHalt"); } RegDEVICERxRiscMode_t& operator=(const RegDEVICERxRiscMode_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscMode_t; #define REG_DEVICE_RX_RISC_STATUS ((volatile APE_DEVICE_H_uint32_t*)0xa0045004) /* */ #define DEVICE_RX_RISC_STATUS_HARDWARE_BREAKPOINT_SHIFT 0u #define DEVICE_RX_RISC_STATUS_HARDWARE_BREAKPOINT_MASK 0x1u #define GET_DEVICE_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_SHIFT 1u #define DEVICE_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_MASK 0x2u #define GET_DEVICE_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_RX_RISC_STATUS_INVALID_INSTRUCTION_SHIFT 2u #define DEVICE_RX_RISC_STATUS_INVALID_INSTRUCTION_MASK 0x4u #define GET_DEVICE_RX_RISC_STATUS_INVALID_INSTRUCTION(__reg__) (((__reg__) & 0x4) >> 2u) #define SET_DEVICE_RX_RISC_STATUS_INVALID_INSTRUCTION(__val__) (((__val__) << 2u) & 0x4u) #define DEVICE_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_SHIFT 3u #define DEVICE_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_MASK 0x8u #define GET_DEVICE_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__reg__) (((__reg__) & 0x8) >> 3u) #define SET_DEVICE_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__val__) (((__val__) << 3u) & 0x8u) #define DEVICE_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_SHIFT 4u #define DEVICE_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_MASK 0x10u #define GET_DEVICE_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__reg__) (((__reg__) & 0x10) >> 4u) #define SET_DEVICE_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__val__) (((__val__) << 4u) & 0x10u) #define DEVICE_RX_RISC_STATUS_INVALID_DATA_ACCESS_SHIFT 5u #define DEVICE_RX_RISC_STATUS_INVALID_DATA_ACCESS_MASK 0x20u #define GET_DEVICE_RX_RISC_STATUS_INVALID_DATA_ACCESS(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_RX_RISC_STATUS_INVALID_DATA_ACCESS(__val__) (((__val__) << 5u) & 0x20u) #define DEVICE_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_SHIFT 6u #define DEVICE_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_MASK 0x40u #define GET_DEVICE_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__reg__) (((__reg__) & 0x40) >> 6u) #define SET_DEVICE_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__val__) (((__val__) << 6u) & 0x40u) #define DEVICE_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_SHIFT 7u #define DEVICE_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_MASK 0x80u #define GET_DEVICE_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__reg__) (((__reg__) & 0x80) >> 7u) #define SET_DEVICE_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__val__) (((__val__) << 7u) & 0x80u) #define DEVICE_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_SHIFT 8u #define DEVICE_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_MASK 0x100u #define GET_DEVICE_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__val__) (((__val__) << 8u) & 0x100u) #define DEVICE_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_SHIFT 9u #define DEVICE_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_MASK 0x200u #define GET_DEVICE_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__reg__) (((__reg__) & 0x200) >> 9u) #define SET_DEVICE_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__val__) (((__val__) << 9u) & 0x200u) #define DEVICE_RX_RISC_STATUS_HALTED_SHIFT 10u #define DEVICE_RX_RISC_STATUS_HALTED_MASK 0x400u #define GET_DEVICE_RX_RISC_STATUS_HALTED(__reg__) (((__reg__) & 0x400) >> 10u) #define SET_DEVICE_RX_RISC_STATUS_HALTED(__val__) (((__val__) << 10u) & 0x400u) #define DEVICE_RX_RISC_STATUS_UNKNOWN_SHIFT 11u #define DEVICE_RX_RISC_STATUS_UNKNOWN_MASK 0x800u #define GET_DEVICE_RX_RISC_STATUS_UNKNOWN(__reg__) (((__reg__) & 0x800) >> 11u) #define SET_DEVICE_RX_RISC_STATUS_UNKNOWN(__val__) (((__val__) << 11u) & 0x800u) #define DEVICE_RX_RISC_STATUS_DATA_ACCESS_STALL_SHIFT 14u #define DEVICE_RX_RISC_STATUS_DATA_ACCESS_STALL_MASK 0x4000u #define GET_DEVICE_RX_RISC_STATUS_DATA_ACCESS_STALL(__reg__) (((__reg__) & 0x4000) >> 14u) #define SET_DEVICE_RX_RISC_STATUS_DATA_ACCESS_STALL(__val__) (((__val__) << 14u) & 0x4000u) #define DEVICE_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_SHIFT 15u #define DEVICE_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_MASK 0x8000u #define GET_DEVICE_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__reg__) (((__reg__) & 0x8000) >> 15u) #define SET_DEVICE_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__val__) (((__val__) << 15u) & 0x8000u) #define DEVICE_RX_RISC_STATUS_BLOCKING_READ_SHIFT 31u #define DEVICE_RX_RISC_STATUS_BLOCKING_READ_MASK 0x80000000u #define GET_DEVICE_RX_RISC_STATUS_BLOCKING_READ(__reg__) (((__reg__) & 0x80000000) >> 31u) #define SET_DEVICE_RX_RISC_STATUS_BLOCKING_READ(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref DEVICE_t.RxRiscStatus. */ typedef register_container RegDEVICERxRiscStatus_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief When enabled in mode register, indicates hardware breakpoint has been reached. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HardwareBreakpoint, 0, 1) /** @brief When enabled in mode register, indicates hardware breakpoint has been reached. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HaltInstructionExecuted, 1, 1) /** @brief Invalid instruction fetched. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InvalidInstruction, 2, 1) /** @brief When enabled in mode register, indicates data reference within lower 256 bytes of SRAM. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Page0DataRefeence, 3, 1) /** @brief When enabled in mode register, indicates the address in the PC is within the lower 256 bytes of SRAM. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Page0InstructionReference, 4, 1) /** @brief Data reference to illegal location. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InvalidDataAccess, 5, 1) /** @brief Program Counter (PC) is set to invalid location in processor address space. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InvalidInstructionFetch, 6, 1) /** @brief Load or Store instruction was executed with the least significant two address bits not valid for the width of the operation (e.g., Load word or Load Half-word from an odd byte address). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BadMemoryAlignment, 7, 1) /** @brief A signal was received from the Memory Arbiter indicating that some BCM5700 block, possibly this processor, accessed a memory location that triggered a software trap. The MA registers are used to configure memory address trapping. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MemoryAddressTrap, 8, 1) /** @brief A signal was received from the Global Resources block indicating that this processor accessed a register location that triggered a software trap. The GRC registers are used to configure register address trapping. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RegisterAddressTrap, 9, 1) /** @brief The RX RISC was explicitly halted via bit 10 in the RX RISC Mode register. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Halted, 10, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Unknown, 11, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_13_12, 12, 2) /** @brief The processor is currently stalled due to a data access. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataAccessStall, 14, 1) /** @brief The processor is currently stalled due to an instruction fetch. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InstructionFetchStall, 15, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_30_16, 16, 15) /** @brief A blocking data cache miss occurred, causing the RX RISC to stall while data is fetched from external (to the RX RISC) memory. This is intended as a debugging tool. No state is saved other than the fact that the miss occurred. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BlockingRead, 31, 1) #elif defined(__BIG_ENDIAN__) /** @brief A blocking data cache miss occurred, causing the RX RISC to stall while data is fetched from external (to the RX RISC) memory. This is intended as a debugging tool. No state is saved other than the fact that the miss occurred. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BlockingRead, 31, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_30_16, 16, 15) /** @brief The processor is currently stalled due to an instruction fetch. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InstructionFetchStall, 15, 1) /** @brief The processor is currently stalled due to a data access. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataAccessStall, 14, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_13_12, 12, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Unknown, 11, 1) /** @brief The RX RISC was explicitly halted via bit 10 in the RX RISC Mode register. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Halted, 10, 1) /** @brief A signal was received from the Global Resources block indicating that this processor accessed a register location that triggered a software trap. The GRC registers are used to configure register address trapping. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RegisterAddressTrap, 9, 1) /** @brief A signal was received from the Memory Arbiter indicating that some BCM5700 block, possibly this processor, accessed a memory location that triggered a software trap. The MA registers are used to configure memory address trapping. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MemoryAddressTrap, 8, 1) /** @brief Load or Store instruction was executed with the least significant two address bits not valid for the width of the operation (e.g., Load word or Load Half-word from an odd byte address). */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BadMemoryAlignment, 7, 1) /** @brief Program Counter (PC) is set to invalid location in processor address space. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InvalidInstructionFetch, 6, 1) /** @brief Data reference to illegal location. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InvalidDataAccess, 5, 1) /** @brief When enabled in mode register, indicates the address in the PC is within the lower 256 bytes of SRAM. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Page0InstructionReference, 4, 1) /** @brief When enabled in mode register, indicates data reference within lower 256 bytes of SRAM. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Page0DataRefeence, 3, 1) /** @brief Invalid instruction fetched. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, InvalidInstruction, 2, 1) /** @brief When enabled in mode register, indicates hardware breakpoint has been reached. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HaltInstructionExecuted, 1, 1) /** @brief When enabled in mode register, indicates hardware breakpoint has been reached. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HardwareBreakpoint, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscStatus"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscStatus_t() { /** @brief constructor for @ref DEVICE_t.RxRiscStatus. */ r32.setName("RxRiscStatus"); bits.HardwareBreakpoint.setBaseRegister(&r32); bits.HardwareBreakpoint.setName("HardwareBreakpoint"); bits.HaltInstructionExecuted.setBaseRegister(&r32); bits.HaltInstructionExecuted.setName("HaltInstructionExecuted"); bits.InvalidInstruction.setBaseRegister(&r32); bits.InvalidInstruction.setName("InvalidInstruction"); bits.Page0DataRefeence.setBaseRegister(&r32); bits.Page0DataRefeence.setName("Page0DataRefeence"); bits.Page0InstructionReference.setBaseRegister(&r32); bits.Page0InstructionReference.setName("Page0InstructionReference"); bits.InvalidDataAccess.setBaseRegister(&r32); bits.InvalidDataAccess.setName("InvalidDataAccess"); bits.InvalidInstructionFetch.setBaseRegister(&r32); bits.InvalidInstructionFetch.setName("InvalidInstructionFetch"); bits.BadMemoryAlignment.setBaseRegister(&r32); bits.BadMemoryAlignment.setName("BadMemoryAlignment"); bits.MemoryAddressTrap.setBaseRegister(&r32); bits.MemoryAddressTrap.setName("MemoryAddressTrap"); bits.RegisterAddressTrap.setBaseRegister(&r32); bits.RegisterAddressTrap.setName("RegisterAddressTrap"); bits.Halted.setBaseRegister(&r32); bits.Halted.setName("Halted"); bits.Unknown.setBaseRegister(&r32); bits.Unknown.setName("Unknown"); bits.DataAccessStall.setBaseRegister(&r32); bits.DataAccessStall.setName("DataAccessStall"); bits.InstructionFetchStall.setBaseRegister(&r32); bits.InstructionFetchStall.setName("InstructionFetchStall"); bits.BlockingRead.setBaseRegister(&r32); bits.BlockingRead.setName("BlockingRead"); } RegDEVICERxRiscStatus_t& operator=(const RegDEVICERxRiscStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscStatus_t; #define REG_DEVICE_RX_RISC_EVENT_MASK ((volatile APE_DEVICE_H_uint32_t*)0xa0045008) /* */ /** @brief Register definition for @ref DEVICE_t.RxRiscEventMask. */ typedef register_container RegDEVICERxRiscEventMask_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscEventMask"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscEventMask_t() { /** @brief constructor for @ref DEVICE_t.RxRiscEventMask. */ r32.setName("RxRiscEventMask"); } RegDEVICERxRiscEventMask_t& operator=(const RegDEVICERxRiscEventMask_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscEventMask_t; #define REG_DEVICE_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE_H_uint32_t*)0xa004501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ /** @brief Register definition for @ref DEVICE_t.RxRiscProgramCounter. */ typedef register_container RegDEVICERxRiscProgramCounter_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscProgramCounter"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscProgramCounter_t() { /** @brief constructor for @ref DEVICE_t.RxRiscProgramCounter. */ r32.setName("RxRiscProgramCounter"); } RegDEVICERxRiscProgramCounter_t& operator=(const RegDEVICERxRiscProgramCounter_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscProgramCounter_t; #define REG_DEVICE_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE_H_uint32_t*)0xa0045020) /* This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed. */ /** @brief Register definition for @ref DEVICE_t.RxRiscCurrentInstruction. */ typedef register_container RegDEVICERxRiscCurrentInstruction_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscCurrentInstruction"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscCurrentInstruction_t() { /** @brief constructor for @ref DEVICE_t.RxRiscCurrentInstruction. */ r32.setName("RxRiscCurrentInstruction"); } RegDEVICERxRiscCurrentInstruction_t& operator=(const RegDEVICERxRiscCurrentInstruction_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscCurrentInstruction_t; #define REG_DEVICE_RX_RISC_INTERRUPT_ENABLE ((volatile APE_DEVICE_H_uint32_t*)0xa0045028) /* Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can’t respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero. */ /** @brief Register definition for @ref DEVICE_t.RxRiscInterruptEnable. */ typedef register_container RegDEVICERxRiscInterruptEnable_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscInterruptEnable"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscInterruptEnable_t() { /** @brief constructor for @ref DEVICE_t.RxRiscInterruptEnable. */ r32.setName("RxRiscInterruptEnable"); } RegDEVICERxRiscInterruptEnable_t& operator=(const RegDEVICERxRiscInterruptEnable_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscInterruptEnable_t; #define REG_DEVICE_RX_RISC_INTERRUPT_VECTOR ((volatile APE_DEVICE_H_uint32_t*)0xa004502c) /* This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input. */ /** @brief Register definition for @ref DEVICE_t.RxRiscInterruptVector. */ typedef register_container RegDEVICERxRiscInterruptVector_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscInterruptVector"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscInterruptVector_t() { /** @brief constructor for @ref DEVICE_t.RxRiscInterruptVector. */ r32.setName("RxRiscInterruptVector"); } RegDEVICERxRiscInterruptVector_t& operator=(const RegDEVICERxRiscInterruptVector_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscInterruptVector_t; #define REG_DEVICE_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE_H_uint32_t*)0xa0045034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ /** @brief Register definition for @ref DEVICE_t.RxRiscHardwareBreakpoint. */ typedef register_container RegDEVICERxRiscHardwareBreakpoint_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscHardwareBreakpoint"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscHardwareBreakpoint_t() { /** @brief constructor for @ref DEVICE_t.RxRiscHardwareBreakpoint. */ r32.setName("RxRiscHardwareBreakpoint"); } RegDEVICERxRiscHardwareBreakpoint_t& operator=(const RegDEVICERxRiscHardwareBreakpoint_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscHardwareBreakpoint_t; #define REG_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS ((volatile APE_DEVICE_H_uint32_t*)0xa0045048) /* This register indicates that address and branch type of the last branch that was taken. This register is for debug use only. */ #define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_SHIFT 1u #define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_MASK 0x2u #define GET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE(__reg__) (((__reg__) & 0x2) >> 1u) #define SET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE(__val__) (((__val__) << 1u) & 0x2u) #define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_JUMP 0x0u #define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_BRANCH 0x1u #define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS_SHIFT 2u #define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS_MASK 0xfffffffcu #define GET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS(__reg__) (((__reg__) & 0xfffffffc) >> 2u) #define SET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS(__val__) (((__val__) << 2u) & 0xfffffffcu) /** @brief Register definition for @ref DEVICE_t.RxRiscLastBranchAddress. */ typedef register_container RegDEVICERxRiscLastBranchAddress_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1) /** @brief This indicates the jump or branch type. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 1, 1) /** @brief This value indicates the address of the last branch that was taken. An offset as indicated by the type field must be subtracted from this value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LastBranchAddress, 2, 30) #elif defined(__BIG_ENDIAN__) /** @brief This value indicates the address of the last branch that was taken. An offset as indicated by the type field must be subtracted from this value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LastBranchAddress, 2, 30) /** @brief This indicates the jump or branch type. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 1, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscLastBranchAddress"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscLastBranchAddress_t() { /** @brief constructor for @ref DEVICE_t.RxRiscLastBranchAddress. */ r32.setName("RxRiscLastBranchAddress"); bits.Type.setBaseRegister(&r32); bits.Type.setName("Type"); bits.Type.addEnum("Jump", 0x0); bits.Type.addEnum("Branch", 0x1); bits.LastBranchAddress.setBaseRegister(&r32); bits.LastBranchAddress.setName("LastBranchAddress"); } RegDEVICERxRiscLastBranchAddress_t& operator=(const RegDEVICERxRiscLastBranchAddress_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscLastBranchAddress_t; #define REG_DEVICE_RX_RISC_REGISTER_0 ((volatile APE_DEVICE_H_uint32_t*)0xa0045200) /* $zero (R0) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister0. */ typedef register_container RegDEVICERxRiscRegister0_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister0"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister0_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister0. */ r32.setName("RxRiscRegister0"); } RegDEVICERxRiscRegister0_t& operator=(const RegDEVICERxRiscRegister0_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister0_t; #define REG_DEVICE_RX_RISC_REGISTER_1 ((volatile APE_DEVICE_H_uint32_t*)0xa0045204) /* $at (R1) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister1. */ typedef register_container RegDEVICERxRiscRegister1_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister1"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister1_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister1. */ r32.setName("RxRiscRegister1"); } RegDEVICERxRiscRegister1_t& operator=(const RegDEVICERxRiscRegister1_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister1_t; #define REG_DEVICE_RX_RISC_REGISTER_2 ((volatile APE_DEVICE_H_uint32_t*)0xa0045208) /* $v0 (R2) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister2. */ typedef register_container RegDEVICERxRiscRegister2_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister2"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister2_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister2. */ r32.setName("RxRiscRegister2"); } RegDEVICERxRiscRegister2_t& operator=(const RegDEVICERxRiscRegister2_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister2_t; #define REG_DEVICE_RX_RISC_REGISTER_3 ((volatile APE_DEVICE_H_uint32_t*)0xa004520c) /* $v1 (R3) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister3. */ typedef register_container RegDEVICERxRiscRegister3_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister3"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister3_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister3. */ r32.setName("RxRiscRegister3"); } RegDEVICERxRiscRegister3_t& operator=(const RegDEVICERxRiscRegister3_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister3_t; #define REG_DEVICE_RX_RISC_REGISTER_4 ((volatile APE_DEVICE_H_uint32_t*)0xa0045210) /* $a0 (R4) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister4. */ typedef register_container RegDEVICERxRiscRegister4_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister4"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister4_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister4. */ r32.setName("RxRiscRegister4"); } RegDEVICERxRiscRegister4_t& operator=(const RegDEVICERxRiscRegister4_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister4_t; #define REG_DEVICE_RX_RISC_REGISTER_5 ((volatile APE_DEVICE_H_uint32_t*)0xa0045214) /* $a1 (R5) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister5. */ typedef register_container RegDEVICERxRiscRegister5_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister5"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister5_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister5. */ r32.setName("RxRiscRegister5"); } RegDEVICERxRiscRegister5_t& operator=(const RegDEVICERxRiscRegister5_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister5_t; #define REG_DEVICE_RX_RISC_REGISTER_6 ((volatile APE_DEVICE_H_uint32_t*)0xa0045218) /* $a2 (R6) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister6. */ typedef register_container RegDEVICERxRiscRegister6_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister6"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister6_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister6. */ r32.setName("RxRiscRegister6"); } RegDEVICERxRiscRegister6_t& operator=(const RegDEVICERxRiscRegister6_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister6_t; #define REG_DEVICE_RX_RISC_REGISTER_7 ((volatile APE_DEVICE_H_uint32_t*)0xa004521c) /* $a3 (R7) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister7. */ typedef register_container RegDEVICERxRiscRegister7_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister7"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister7_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister7. */ r32.setName("RxRiscRegister7"); } RegDEVICERxRiscRegister7_t& operator=(const RegDEVICERxRiscRegister7_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister7_t; #define REG_DEVICE_RX_RISC_REGISTER_8 ((volatile APE_DEVICE_H_uint32_t*)0xa0045220) /* $t0 (R8) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister8. */ typedef register_container RegDEVICERxRiscRegister8_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister8"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister8_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister8. */ r32.setName("RxRiscRegister8"); } RegDEVICERxRiscRegister8_t& operator=(const RegDEVICERxRiscRegister8_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister8_t; #define REG_DEVICE_RX_RISC_REGISTER_9 ((volatile APE_DEVICE_H_uint32_t*)0xa0045224) /* $t1 (R9) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister9. */ typedef register_container RegDEVICERxRiscRegister9_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister9"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister9_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister9. */ r32.setName("RxRiscRegister9"); } RegDEVICERxRiscRegister9_t& operator=(const RegDEVICERxRiscRegister9_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister9_t; #define REG_DEVICE_RX_RISC_REGISTER_10 ((volatile APE_DEVICE_H_uint32_t*)0xa0045228) /* $t2 (R10) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister10. */ typedef register_container RegDEVICERxRiscRegister10_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister10"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister10_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister10. */ r32.setName("RxRiscRegister10"); } RegDEVICERxRiscRegister10_t& operator=(const RegDEVICERxRiscRegister10_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister10_t; #define REG_DEVICE_RX_RISC_REGISTER_11 ((volatile APE_DEVICE_H_uint32_t*)0xa004522c) /* $t3 (R11) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister11. */ typedef register_container RegDEVICERxRiscRegister11_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister11"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister11_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister11. */ r32.setName("RxRiscRegister11"); } RegDEVICERxRiscRegister11_t& operator=(const RegDEVICERxRiscRegister11_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister11_t; #define REG_DEVICE_RX_RISC_REGISTER_12 ((volatile APE_DEVICE_H_uint32_t*)0xa0045230) /* $t4 (R12) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister12. */ typedef register_container RegDEVICERxRiscRegister12_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister12"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister12_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister12. */ r32.setName("RxRiscRegister12"); } RegDEVICERxRiscRegister12_t& operator=(const RegDEVICERxRiscRegister12_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister12_t; #define REG_DEVICE_RX_RISC_REGISTER_13 ((volatile APE_DEVICE_H_uint32_t*)0xa0045234) /* $t5 (R13) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister13. */ typedef register_container RegDEVICERxRiscRegister13_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister13"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister13_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister13. */ r32.setName("RxRiscRegister13"); } RegDEVICERxRiscRegister13_t& operator=(const RegDEVICERxRiscRegister13_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister13_t; #define REG_DEVICE_RX_RISC_REGISTER_14 ((volatile APE_DEVICE_H_uint32_t*)0xa0045238) /* $t6 (R14) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister14. */ typedef register_container RegDEVICERxRiscRegister14_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister14"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister14_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister14. */ r32.setName("RxRiscRegister14"); } RegDEVICERxRiscRegister14_t& operator=(const RegDEVICERxRiscRegister14_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister14_t; #define REG_DEVICE_RX_RISC_REGISTER_15 ((volatile APE_DEVICE_H_uint32_t*)0xa004523c) /* $t7 (R15) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister15. */ typedef register_container RegDEVICERxRiscRegister15_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister15"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister15_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister15. */ r32.setName("RxRiscRegister15"); } RegDEVICERxRiscRegister15_t& operator=(const RegDEVICERxRiscRegister15_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister15_t; #define REG_DEVICE_RX_RISC_REGISTER_16 ((volatile APE_DEVICE_H_uint32_t*)0xa0045240) /* $s0 (R16) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister16. */ typedef register_container RegDEVICERxRiscRegister16_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister16"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister16_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister16. */ r32.setName("RxRiscRegister16"); } RegDEVICERxRiscRegister16_t& operator=(const RegDEVICERxRiscRegister16_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister16_t; #define REG_DEVICE_RX_RISC_REGISTER_17 ((volatile APE_DEVICE_H_uint32_t*)0xa0045244) /* $s1 (R17) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister17. */ typedef register_container RegDEVICERxRiscRegister17_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister17"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister17_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister17. */ r32.setName("RxRiscRegister17"); } RegDEVICERxRiscRegister17_t& operator=(const RegDEVICERxRiscRegister17_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister17_t; #define REG_DEVICE_RX_RISC_REGISTER_18 ((volatile APE_DEVICE_H_uint32_t*)0xa0045248) /* $s2 (R18) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister18. */ typedef register_container RegDEVICERxRiscRegister18_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister18"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister18_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister18. */ r32.setName("RxRiscRegister18"); } RegDEVICERxRiscRegister18_t& operator=(const RegDEVICERxRiscRegister18_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister18_t; #define REG_DEVICE_RX_RISC_REGISTER_19 ((volatile APE_DEVICE_H_uint32_t*)0xa004524c) /* $s3 (R19) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister19. */ typedef register_container RegDEVICERxRiscRegister19_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister19"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister19_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister19. */ r32.setName("RxRiscRegister19"); } RegDEVICERxRiscRegister19_t& operator=(const RegDEVICERxRiscRegister19_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister19_t; #define REG_DEVICE_RX_RISC_REGISTER_20 ((volatile APE_DEVICE_H_uint32_t*)0xa0045250) /* $s4 (R20) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister20. */ typedef register_container RegDEVICERxRiscRegister20_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister20"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister20_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister20. */ r32.setName("RxRiscRegister20"); } RegDEVICERxRiscRegister20_t& operator=(const RegDEVICERxRiscRegister20_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister20_t; #define REG_DEVICE_RX_RISC_REGISTER_21 ((volatile APE_DEVICE_H_uint32_t*)0xa0045254) /* $s5 (R21) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister21. */ typedef register_container RegDEVICERxRiscRegister21_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister21"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister21_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister21. */ r32.setName("RxRiscRegister21"); } RegDEVICERxRiscRegister21_t& operator=(const RegDEVICERxRiscRegister21_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister21_t; #define REG_DEVICE_RX_RISC_REGISTER_22 ((volatile APE_DEVICE_H_uint32_t*)0xa0045258) /* $s6 (R22) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister22. */ typedef register_container RegDEVICERxRiscRegister22_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister22"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister22_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister22. */ r32.setName("RxRiscRegister22"); } RegDEVICERxRiscRegister22_t& operator=(const RegDEVICERxRiscRegister22_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister22_t; #define REG_DEVICE_RX_RISC_REGISTER_23 ((volatile APE_DEVICE_H_uint32_t*)0xa004525c) /* $s7 (R23) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister23. */ typedef register_container RegDEVICERxRiscRegister23_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister23"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister23_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister23. */ r32.setName("RxRiscRegister23"); } RegDEVICERxRiscRegister23_t& operator=(const RegDEVICERxRiscRegister23_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister23_t; #define REG_DEVICE_RX_RISC_REGISTER_24 ((volatile APE_DEVICE_H_uint32_t*)0xa0045260) /* $t8 (R24) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister24. */ typedef register_container RegDEVICERxRiscRegister24_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister24"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister24_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister24. */ r32.setName("RxRiscRegister24"); } RegDEVICERxRiscRegister24_t& operator=(const RegDEVICERxRiscRegister24_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister24_t; #define REG_DEVICE_RX_RISC_REGISTER_25 ((volatile APE_DEVICE_H_uint32_t*)0xa0045264) /* $t9 (R25) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister25. */ typedef register_container RegDEVICERxRiscRegister25_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister25"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister25_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister25. */ r32.setName("RxRiscRegister25"); } RegDEVICERxRiscRegister25_t& operator=(const RegDEVICERxRiscRegister25_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister25_t; #define REG_DEVICE_RX_RISC_REGISTER_26 ((volatile APE_DEVICE_H_uint32_t*)0xa0045268) /* $k0 (R26) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister26. */ typedef register_container RegDEVICERxRiscRegister26_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister26"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister26_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister26. */ r32.setName("RxRiscRegister26"); } RegDEVICERxRiscRegister26_t& operator=(const RegDEVICERxRiscRegister26_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister26_t; #define REG_DEVICE_RX_RISC_REGISTER_27 ((volatile APE_DEVICE_H_uint32_t*)0xa004526c) /* $k1 (R27) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister27. */ typedef register_container RegDEVICERxRiscRegister27_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister27"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister27_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister27. */ r32.setName("RxRiscRegister27"); } RegDEVICERxRiscRegister27_t& operator=(const RegDEVICERxRiscRegister27_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister27_t; #define REG_DEVICE_RX_RISC_REGISTER_28 ((volatile APE_DEVICE_H_uint32_t*)0xa0045270) /* $gp (R28) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister28. */ typedef register_container RegDEVICERxRiscRegister28_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister28"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister28_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister28. */ r32.setName("RxRiscRegister28"); } RegDEVICERxRiscRegister28_t& operator=(const RegDEVICERxRiscRegister28_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister28_t; #define REG_DEVICE_RX_RISC_REGISTER_29 ((volatile APE_DEVICE_H_uint32_t*)0xa0045274) /* $sp (R29) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister29. */ typedef register_container RegDEVICERxRiscRegister29_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister29"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister29_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister29. */ r32.setName("RxRiscRegister29"); } RegDEVICERxRiscRegister29_t& operator=(const RegDEVICERxRiscRegister29_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister29_t; #define REG_DEVICE_RX_RISC_REGISTER_30 ((volatile APE_DEVICE_H_uint32_t*)0xa0045278) /* $fp (R30) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister30. */ typedef register_container RegDEVICERxRiscRegister30_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister30"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister30_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister30. */ r32.setName("RxRiscRegister30"); } RegDEVICERxRiscRegister30_t& operator=(const RegDEVICERxRiscRegister30_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister30_t; #define REG_DEVICE_RX_RISC_REGISTER_31 ((volatile APE_DEVICE_H_uint32_t*)0xa004527c) /* $ra (R31) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister31. */ typedef register_container RegDEVICERxRiscRegister31_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxRiscRegister31"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxRiscRegister31_t() { /** @brief constructor for @ref DEVICE_t.RxRiscRegister31. */ r32.setName("RxRiscRegister31"); } RegDEVICERxRiscRegister31_t& operator=(const RegDEVICERxRiscRegister31_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscRegister31_t; #define REG_DEVICE_6408 ((volatile APE_DEVICE_H_uint32_t*)0xa0046408) /* */ /** @brief Register definition for @ref DEVICE_t.6408. */ typedef register_container RegDEVICE6408_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "6408"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE6408_t() { /** @brief constructor for @ref DEVICE_t.6408. */ r32.setName("6408"); } RegDEVICE6408_t& operator=(const RegDEVICE6408_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE6408_t; #define REG_DEVICE_PCI_POWER_CONSUMPTION_INFO ((volatile APE_DEVICE_H_uint32_t*)0xa0046410) /* This undocumented register is used to set PCIe Power Consumption information as reported in configuration space. It is loaded from NVM configuration data. */ /** @brief Register definition for @ref DEVICE_t.PciPowerConsumptionInfo. */ typedef register_container RegDEVICEPciPowerConsumptionInfo_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciPowerConsumptionInfo"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciPowerConsumptionInfo_t() { /** @brief constructor for @ref DEVICE_t.PciPowerConsumptionInfo. */ r32.setName("PciPowerConsumptionInfo"); } RegDEVICEPciPowerConsumptionInfo_t& operator=(const RegDEVICEPciPowerConsumptionInfo_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciPowerConsumptionInfo_t; #define REG_DEVICE_PCI_POWER_DISSIPATED_INFO ((volatile APE_DEVICE_H_uint32_t*)0xa0046414) /* This undocumented register is used to set PCIe Power Dissipated information as reported in configuration space. It is loaded from NVM configuration data. */ /** @brief Register definition for @ref DEVICE_t.PciPowerDissipatedInfo. */ typedef register_container RegDEVICEPciPowerDissipatedInfo_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciPowerDissipatedInfo"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciPowerDissipatedInfo_t() { /** @brief constructor for @ref DEVICE_t.PciPowerDissipatedInfo. */ r32.setName("PciPowerDissipatedInfo"); } RegDEVICEPciPowerDissipatedInfo_t& operator=(const RegDEVICEPciPowerDissipatedInfo_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciPowerDissipatedInfo_t; #define REG_DEVICE_PCI_VPD_REQUEST ((volatile APE_DEVICE_H_uint32_t*)0xa004642c) /* This undocumented register appears to be used to implement the PCI VPD capability. It is set to the VPD offset which was requested by the host by writing to the VPD register. */ #define DEVICE_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_SHIFT 16u #define DEVICE_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_MASK 0x7fff0000u #define GET_DEVICE_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__reg__) (((__reg__) & 0x7fff0000) >> 16u) #define SET_DEVICE_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__val__) (((__val__) << 16u) & 0x7fff0000u) /** @brief Register definition for @ref DEVICE_t.PciVpdRequest. */ typedef register_container RegDEVICEPciVpdRequest_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RequestedVPDOffset, 16, 15) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_31, 31, 1) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_31, 31, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RequestedVPDOffset, 16, 15) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciVpdRequest"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciVpdRequest_t() { /** @brief constructor for @ref DEVICE_t.PciVpdRequest. */ r32.setName("PciVpdRequest"); bits.RequestedVPDOffset.setBaseRegister(&r32); bits.RequestedVPDOffset.setName("RequestedVPDOffset"); } RegDEVICEPciVpdRequest_t& operator=(const RegDEVICEPciVpdRequest_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciVpdRequest_t; #define REG_DEVICE_PCI_VPD_RESPONSE ((volatile APE_DEVICE_H_uint32_t*)0xa0046430) /* This undocumented register appears to be used to implement the PCI VPD capability. Bootcode writes the 32 bits of data loaded from the word requested by */ /** @brief Register definition for @ref DEVICE_t.PciVpdResponse. */ typedef register_container RegDEVICEPciVpdResponse_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciVpdResponse"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciVpdResponse_t() { /** @brief constructor for @ref DEVICE_t.PciVpdResponse. */ r32.setName("PciVpdResponse"); } RegDEVICEPciVpdResponse_t& operator=(const RegDEVICEPciVpdResponse_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciVpdResponse_t; #define REG_DEVICE_PCI_VENDOR_DEVICE_ID ((volatile APE_DEVICE_H_uint32_t*)0xa0046434) /* This is the undocumented register used to set the PCI Vendor/Device ID, which is configurable from NVM. */ #define DEVICE_PCI_VENDOR_DEVICE_ID_DEVICE_ID_SHIFT 0u #define DEVICE_PCI_VENDOR_DEVICE_ID_DEVICE_ID_MASK 0xffffu #define GET_DEVICE_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__val__) (((__val__) << 0u) & 0xffffu) #define DEVICE_PCI_VENDOR_DEVICE_ID_VENDOR_ID_SHIFT 16u #define DEVICE_PCI_VENDOR_DEVICE_ID_VENDOR_ID_MASK 0xffff0000u #define GET_DEVICE_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) #define SET_DEVICE_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__val__) (((__val__) << 16u) & 0xffff0000u) /** @brief Register definition for @ref DEVICE_t.PciVendorDeviceId. */ typedef register_container RegDEVICEPciVendorDeviceId_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DeviceID, 0, 16) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, VendorID, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, VendorID, 16, 16) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DeviceID, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciVendorDeviceId"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciVendorDeviceId_t() { /** @brief constructor for @ref DEVICE_t.PciVendorDeviceId. */ r32.setName("PciVendorDeviceId"); bits.DeviceID.setBaseRegister(&r32); bits.DeviceID.setName("DeviceID"); bits.VendorID.setBaseRegister(&r32); bits.VendorID.setName("VendorID"); } RegDEVICEPciVendorDeviceId_t& operator=(const RegDEVICEPciVendorDeviceId_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciVendorDeviceId_t; #define REG_DEVICE_PCI_SUBSYSTEM_ID ((volatile APE_DEVICE_H_uint32_t*)0xa0046438) /* This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */ #define DEVICE_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0u #define DEVICE_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_MASK 0xffffu #define GET_DEVICE_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__reg__) (((__reg__) & 0xffff) >> 0u) #define SET_DEVICE_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__val__) (((__val__) << 0u) & 0xffffu) #define DEVICE_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_SHIFT 16u #define DEVICE_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_MASK 0xffff0000u #define GET_DEVICE_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) #define SET_DEVICE_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__val__) (((__val__) << 16u) & 0xffff0000u) /** @brief Register definition for @ref DEVICE_t.PciSubsystemId. */ typedef register_container RegDEVICEPciSubsystemId_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SubsystemVendorID, 0, 16) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SubsystemID, 16, 16) #elif defined(__BIG_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SubsystemID, 16, 16) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SubsystemVendorID, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciSubsystemId"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciSubsystemId_t() { /** @brief constructor for @ref DEVICE_t.PciSubsystemId. */ r32.setName("PciSubsystemId"); bits.SubsystemVendorID.setBaseRegister(&r32); bits.SubsystemVendorID.setName("SubsystemVendorID"); bits.SubsystemID.setBaseRegister(&r32); bits.SubsystemID.setName("SubsystemID"); } RegDEVICEPciSubsystemId_t& operator=(const RegDEVICEPciSubsystemId_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciSubsystemId_t; #define REG_DEVICE_PCI_CLASS_CODE_REVISION ((volatile APE_DEVICE_H_uint32_t*)0xa004643c) /* This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */ /** @brief Register definition for @ref DEVICE_t.PciClassCodeRevision. */ typedef register_container RegDEVICEPciClassCodeRevision_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciClassCodeRevision"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciClassCodeRevision_t() { /** @brief constructor for @ref DEVICE_t.PciClassCodeRevision. */ r32.setName("PciClassCodeRevision"); } RegDEVICEPciClassCodeRevision_t& operator=(const RegDEVICEPciClassCodeRevision_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciClassCodeRevision_t; #define REG_DEVICE_64C0 ((volatile APE_DEVICE_H_uint32_t*)0xa00464c0) /* */ /** @brief Register definition for @ref DEVICE_t.64c0. */ typedef register_container RegDEVICE64c0_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "64c0"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE64c0_t() { /** @brief constructor for @ref DEVICE_t.64c0. */ r32.setName("64c0"); } RegDEVICE64c0_t& operator=(const RegDEVICE64c0_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE64c0_t; #define REG_DEVICE_64C4 ((volatile APE_DEVICE_H_uint32_t*)0xa00464c4) /* */ /** @brief Register definition for @ref DEVICE_t.64c4. */ typedef register_container RegDEVICE64c4_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "64c4"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE64c4_t() { /** @brief constructor for @ref DEVICE_t.64c4. */ r32.setName("64c4"); } RegDEVICE64c4_t& operator=(const RegDEVICE64c4_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE64c4_t; #define REG_DEVICE_64C8 ((volatile APE_DEVICE_H_uint32_t*)0xa00464c8) /* */ /** @brief Register definition for @ref DEVICE_t.64c8. */ typedef register_container RegDEVICE64c8_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "64c8"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE64c8_t() { /** @brief constructor for @ref DEVICE_t.64c8. */ r32.setName("64c8"); } RegDEVICE64c8_t& operator=(const RegDEVICE64c8_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE64c8_t; #define REG_DEVICE_64DC ((volatile APE_DEVICE_H_uint32_t*)0xa00464dc) /* */ /** @brief Register definition for @ref DEVICE_t.64dc. */ typedef register_container RegDEVICE64dc_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "64dc"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE64dc_t() { /** @brief constructor for @ref DEVICE_t.64dc. */ r32.setName("64dc"); } RegDEVICE64dc_t& operator=(const RegDEVICE64dc_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE64dc_t; #define REG_DEVICE_PCI_SERIAL_NUMBER_LOW ((volatile APE_DEVICE_H_uint32_t*)0xa0046504) /* This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ /** @brief Register definition for @ref DEVICE_t.PciSerialNumberLow. */ typedef register_container RegDEVICEPciSerialNumberLow_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciSerialNumberLow"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciSerialNumberLow_t() { /** @brief constructor for @ref DEVICE_t.PciSerialNumberLow. */ r32.setName("PciSerialNumberLow"); } RegDEVICEPciSerialNumberLow_t& operator=(const RegDEVICEPciSerialNumberLow_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciSerialNumberLow_t; #define REG_DEVICE_PCI_SERIAL_NUMBER_HIGH ((volatile APE_DEVICE_H_uint32_t*)0xa0046508) /* This sets the high 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ /** @brief Register definition for @ref DEVICE_t.PciSerialNumberHigh. */ typedef register_container RegDEVICEPciSerialNumberHigh_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciSerialNumberHigh"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciSerialNumberHigh_t() { /** @brief constructor for @ref DEVICE_t.PciSerialNumberHigh. */ r32.setName("PciSerialNumberHigh"); } RegDEVICEPciSerialNumberHigh_t& operator=(const RegDEVICEPciSerialNumberHigh_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciSerialNumberHigh_t; #define REG_DEVICE_PCI_POWER_BUDGET_0 ((volatile APE_DEVICE_H_uint32_t*)0xa0046510) /* Used to report power budget capability data to the host. The values are loaded from NVM, and up to eight values may be specified. */ #define DEVICE_PCI_POWER_BUDGET_0_BASE_POWER_SHIFT 0u #define DEVICE_PCI_POWER_BUDGET_0_BASE_POWER_MASK 0xffu #define GET_DEVICE_PCI_POWER_BUDGET_0_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) #define SET_DEVICE_PCI_POWER_BUDGET_0_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) #define DEVICE_PCI_POWER_BUDGET_0_DATA_SCALE_SHIFT 8u #define DEVICE_PCI_POWER_BUDGET_0_DATA_SCALE_MASK 0x300u #define GET_DEVICE_PCI_POWER_BUDGET_0_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) #define SET_DEVICE_PCI_POWER_BUDGET_0_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) #define DEVICE_PCI_POWER_BUDGET_0_DATA_SCALE_1_0X 0x0u #define DEVICE_PCI_POWER_BUDGET_0_DATA_SCALE_0_1X 0x1u #define DEVICE_PCI_POWER_BUDGET_0_DATA_SCALE_0_01X 0x2u #define DEVICE_PCI_POWER_BUDGET_0_DATA_SCALE_0_001X 0x3u #define DEVICE_PCI_POWER_BUDGET_0_PM_SUB_STATE_SHIFT 10u #define DEVICE_PCI_POWER_BUDGET_0_PM_SUB_STATE_MASK 0x1c00u #define GET_DEVICE_PCI_POWER_BUDGET_0_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) #define SET_DEVICE_PCI_POWER_BUDGET_0_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) #define DEVICE_PCI_POWER_BUDGET_0_PM_STATE_SHIFT 13u #define DEVICE_PCI_POWER_BUDGET_0_PM_STATE_MASK 0x6000u #define GET_DEVICE_PCI_POWER_BUDGET_0_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) #define SET_DEVICE_PCI_POWER_BUDGET_0_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) #define DEVICE_PCI_POWER_BUDGET_0_PM_STATE_D0 0x0u #define DEVICE_PCI_POWER_BUDGET_0_PM_STATE_D1 0x1u #define DEVICE_PCI_POWER_BUDGET_0_PM_STATE_D2 0x2u #define DEVICE_PCI_POWER_BUDGET_0_PM_STATE_D3 0x3u #define DEVICE_PCI_POWER_BUDGET_0_TYPE_SHIFT 15u #define DEVICE_PCI_POWER_BUDGET_0_TYPE_MASK 0x38000u #define GET_DEVICE_PCI_POWER_BUDGET_0_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) #define SET_DEVICE_PCI_POWER_BUDGET_0_TYPE(__val__) (((__val__) << 15u) & 0x38000u) #define DEVICE_PCI_POWER_BUDGET_0_TYPE_PME_AUX 0x0u #define DEVICE_PCI_POWER_BUDGET_0_TYPE_AUXILIARY 0x1u #define DEVICE_PCI_POWER_BUDGET_0_TYPE_IDLE 0x2u #define DEVICE_PCI_POWER_BUDGET_0_TYPE_SUSTAINED 0x3u #define DEVICE_PCI_POWER_BUDGET_0_TYPE_MAXIMUM 0x7u #define DEVICE_PCI_POWER_BUDGET_0_POWER_RAIL_SHIFT 18u #define DEVICE_PCI_POWER_BUDGET_0_POWER_RAIL_MASK 0x1c0000u #define GET_DEVICE_PCI_POWER_BUDGET_0_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) #define SET_DEVICE_PCI_POWER_BUDGET_0_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) #define DEVICE_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_12V 0x0u #define DEVICE_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_3_3V 0x1u #define DEVICE_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u #define DEVICE_PCI_POWER_BUDGET_0_POWER_RAIL_THERMAL 0x7u /** @brief Register definition for @ref DEVICE_t.PciPowerBudget0. */ typedef register_container RegDEVICEPciPowerBudget0_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciPowerBudget0"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciPowerBudget0_t() { /** @brief constructor for @ref DEVICE_t.PciPowerBudget0. */ r32.setName("PciPowerBudget0"); bits.BasePower.setBaseRegister(&r32); bits.BasePower.setName("BasePower"); bits.DataScale.setBaseRegister(&r32); bits.DataScale.setName("DataScale"); bits.DataScale.addEnum("1.0x", 0x0); bits.DataScale.addEnum("0.1x", 0x1); bits.DataScale.addEnum("0.01x", 0x2); bits.DataScale.addEnum("0.001x", 0x3); bits.PMSubState.setBaseRegister(&r32); bits.PMSubState.setName("PMSubState"); bits.PMState.setBaseRegister(&r32); bits.PMState.setName("PMState"); bits.PMState.addEnum("D0", 0x0); bits.PMState.addEnum("D1", 0x1); bits.PMState.addEnum("D2", 0x2); bits.PMState.addEnum("D3", 0x3); bits.Type.setBaseRegister(&r32); bits.Type.setName("Type"); bits.Type.addEnum("PME Aux", 0x0); bits.Type.addEnum("Auxiliary", 0x1); bits.Type.addEnum("Idle", 0x2); bits.Type.addEnum("Sustained", 0x3); bits.Type.addEnum("Maximum", 0x7); bits.PowerRail.setBaseRegister(&r32); bits.PowerRail.setName("PowerRail"); bits.PowerRail.addEnum("Power 12V", 0x0); bits.PowerRail.addEnum("Power 3.3V", 0x1); bits.PowerRail.addEnum("Power 1.5V or 1.8V", 0x2); bits.PowerRail.addEnum("Thermal", 0x7); } RegDEVICEPciPowerBudget0_t& operator=(const RegDEVICEPciPowerBudget0_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciPowerBudget0_t; #define REG_DEVICE_PCI_POWER_BUDGET_1 ((volatile APE_DEVICE_H_uint32_t*)0xa0046514) /* See */ #define DEVICE_PCI_POWER_BUDGET_1_BASE_POWER_SHIFT 0u #define DEVICE_PCI_POWER_BUDGET_1_BASE_POWER_MASK 0xffu #define GET_DEVICE_PCI_POWER_BUDGET_1_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) #define SET_DEVICE_PCI_POWER_BUDGET_1_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) #define DEVICE_PCI_POWER_BUDGET_1_DATA_SCALE_SHIFT 8u #define DEVICE_PCI_POWER_BUDGET_1_DATA_SCALE_MASK 0x300u #define GET_DEVICE_PCI_POWER_BUDGET_1_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) #define SET_DEVICE_PCI_POWER_BUDGET_1_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) #define DEVICE_PCI_POWER_BUDGET_1_DATA_SCALE_1_0X 0x0u #define DEVICE_PCI_POWER_BUDGET_1_DATA_SCALE_0_1X 0x1u #define DEVICE_PCI_POWER_BUDGET_1_DATA_SCALE_0_01X 0x2u #define DEVICE_PCI_POWER_BUDGET_1_DATA_SCALE_0_001X 0x3u #define DEVICE_PCI_POWER_BUDGET_1_PM_SUB_STATE_SHIFT 10u #define DEVICE_PCI_POWER_BUDGET_1_PM_SUB_STATE_MASK 0x1c00u #define GET_DEVICE_PCI_POWER_BUDGET_1_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) #define SET_DEVICE_PCI_POWER_BUDGET_1_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) #define DEVICE_PCI_POWER_BUDGET_1_PM_STATE_SHIFT 13u #define DEVICE_PCI_POWER_BUDGET_1_PM_STATE_MASK 0x6000u #define GET_DEVICE_PCI_POWER_BUDGET_1_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) #define SET_DEVICE_PCI_POWER_BUDGET_1_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) #define DEVICE_PCI_POWER_BUDGET_1_PM_STATE_D0 0x0u #define DEVICE_PCI_POWER_BUDGET_1_PM_STATE_D1 0x1u #define DEVICE_PCI_POWER_BUDGET_1_PM_STATE_D2 0x2u #define DEVICE_PCI_POWER_BUDGET_1_PM_STATE_D3 0x3u #define DEVICE_PCI_POWER_BUDGET_1_TYPE_SHIFT 15u #define DEVICE_PCI_POWER_BUDGET_1_TYPE_MASK 0x38000u #define GET_DEVICE_PCI_POWER_BUDGET_1_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) #define SET_DEVICE_PCI_POWER_BUDGET_1_TYPE(__val__) (((__val__) << 15u) & 0x38000u) #define DEVICE_PCI_POWER_BUDGET_1_TYPE_PME_AUX 0x0u #define DEVICE_PCI_POWER_BUDGET_1_TYPE_AUXILIARY 0x1u #define DEVICE_PCI_POWER_BUDGET_1_TYPE_IDLE 0x2u #define DEVICE_PCI_POWER_BUDGET_1_TYPE_SUSTAINED 0x3u #define DEVICE_PCI_POWER_BUDGET_1_TYPE_MAXIMUM 0x7u #define DEVICE_PCI_POWER_BUDGET_1_POWER_RAIL_SHIFT 18u #define DEVICE_PCI_POWER_BUDGET_1_POWER_RAIL_MASK 0x1c0000u #define GET_DEVICE_PCI_POWER_BUDGET_1_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) #define SET_DEVICE_PCI_POWER_BUDGET_1_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) #define DEVICE_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_12V 0x0u #define DEVICE_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_3_3V 0x1u #define DEVICE_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u #define DEVICE_PCI_POWER_BUDGET_1_POWER_RAIL_THERMAL 0x7u /** @brief Register definition for @ref DEVICE_t.PciPowerBudget1. */ typedef register_container RegDEVICEPciPowerBudget1_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciPowerBudget1"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciPowerBudget1_t() { /** @brief constructor for @ref DEVICE_t.PciPowerBudget1. */ r32.setName("PciPowerBudget1"); bits.BasePower.setBaseRegister(&r32); bits.BasePower.setName("BasePower"); bits.DataScale.setBaseRegister(&r32); bits.DataScale.setName("DataScale"); bits.DataScale.addEnum("1.0x", 0x0); bits.DataScale.addEnum("0.1x", 0x1); bits.DataScale.addEnum("0.01x", 0x2); bits.DataScale.addEnum("0.001x", 0x3); bits.PMSubState.setBaseRegister(&r32); bits.PMSubState.setName("PMSubState"); bits.PMState.setBaseRegister(&r32); bits.PMState.setName("PMState"); bits.PMState.addEnum("D0", 0x0); bits.PMState.addEnum("D1", 0x1); bits.PMState.addEnum("D2", 0x2); bits.PMState.addEnum("D3", 0x3); bits.Type.setBaseRegister(&r32); bits.Type.setName("Type"); bits.Type.addEnum("PME Aux", 0x0); bits.Type.addEnum("Auxiliary", 0x1); bits.Type.addEnum("Idle", 0x2); bits.Type.addEnum("Sustained", 0x3); bits.Type.addEnum("Maximum", 0x7); bits.PowerRail.setBaseRegister(&r32); bits.PowerRail.setName("PowerRail"); bits.PowerRail.addEnum("Power 12V", 0x0); bits.PowerRail.addEnum("Power 3.3V", 0x1); bits.PowerRail.addEnum("Power 1.5V or 1.8V", 0x2); bits.PowerRail.addEnum("Thermal", 0x7); } RegDEVICEPciPowerBudget1_t& operator=(const RegDEVICEPciPowerBudget1_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciPowerBudget1_t; #define REG_DEVICE_PCI_POWER_BUDGET_2 ((volatile APE_DEVICE_H_uint32_t*)0xa0046518) /* See */ #define DEVICE_PCI_POWER_BUDGET_2_BASE_POWER_SHIFT 0u #define DEVICE_PCI_POWER_BUDGET_2_BASE_POWER_MASK 0xffu #define GET_DEVICE_PCI_POWER_BUDGET_2_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) #define SET_DEVICE_PCI_POWER_BUDGET_2_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) #define DEVICE_PCI_POWER_BUDGET_2_DATA_SCALE_SHIFT 8u #define DEVICE_PCI_POWER_BUDGET_2_DATA_SCALE_MASK 0x300u #define GET_DEVICE_PCI_POWER_BUDGET_2_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) #define SET_DEVICE_PCI_POWER_BUDGET_2_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) #define DEVICE_PCI_POWER_BUDGET_2_DATA_SCALE_1_0X 0x0u #define DEVICE_PCI_POWER_BUDGET_2_DATA_SCALE_0_1X 0x1u #define DEVICE_PCI_POWER_BUDGET_2_DATA_SCALE_0_01X 0x2u #define DEVICE_PCI_POWER_BUDGET_2_DATA_SCALE_0_001X 0x3u #define DEVICE_PCI_POWER_BUDGET_2_PM_SUB_STATE_SHIFT 10u #define DEVICE_PCI_POWER_BUDGET_2_PM_SUB_STATE_MASK 0x1c00u #define GET_DEVICE_PCI_POWER_BUDGET_2_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) #define SET_DEVICE_PCI_POWER_BUDGET_2_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) #define DEVICE_PCI_POWER_BUDGET_2_PM_STATE_SHIFT 13u #define DEVICE_PCI_POWER_BUDGET_2_PM_STATE_MASK 0x6000u #define GET_DEVICE_PCI_POWER_BUDGET_2_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) #define SET_DEVICE_PCI_POWER_BUDGET_2_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) #define DEVICE_PCI_POWER_BUDGET_2_PM_STATE_D0 0x0u #define DEVICE_PCI_POWER_BUDGET_2_PM_STATE_D1 0x1u #define DEVICE_PCI_POWER_BUDGET_2_PM_STATE_D2 0x2u #define DEVICE_PCI_POWER_BUDGET_2_PM_STATE_D3 0x3u #define DEVICE_PCI_POWER_BUDGET_2_TYPE_SHIFT 15u #define DEVICE_PCI_POWER_BUDGET_2_TYPE_MASK 0x38000u #define GET_DEVICE_PCI_POWER_BUDGET_2_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) #define SET_DEVICE_PCI_POWER_BUDGET_2_TYPE(__val__) (((__val__) << 15u) & 0x38000u) #define DEVICE_PCI_POWER_BUDGET_2_TYPE_PME_AUX 0x0u #define DEVICE_PCI_POWER_BUDGET_2_TYPE_AUXILIARY 0x1u #define DEVICE_PCI_POWER_BUDGET_2_TYPE_IDLE 0x2u #define DEVICE_PCI_POWER_BUDGET_2_TYPE_SUSTAINED 0x3u #define DEVICE_PCI_POWER_BUDGET_2_TYPE_MAXIMUM 0x7u #define DEVICE_PCI_POWER_BUDGET_2_POWER_RAIL_SHIFT 18u #define DEVICE_PCI_POWER_BUDGET_2_POWER_RAIL_MASK 0x1c0000u #define GET_DEVICE_PCI_POWER_BUDGET_2_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) #define SET_DEVICE_PCI_POWER_BUDGET_2_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) #define DEVICE_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_12V 0x0u #define DEVICE_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_3_3V 0x1u #define DEVICE_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u #define DEVICE_PCI_POWER_BUDGET_2_POWER_RAIL_THERMAL 0x7u /** @brief Register definition for @ref DEVICE_t.PciPowerBudget2. */ typedef register_container RegDEVICEPciPowerBudget2_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciPowerBudget2"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciPowerBudget2_t() { /** @brief constructor for @ref DEVICE_t.PciPowerBudget2. */ r32.setName("PciPowerBudget2"); bits.BasePower.setBaseRegister(&r32); bits.BasePower.setName("BasePower"); bits.DataScale.setBaseRegister(&r32); bits.DataScale.setName("DataScale"); bits.DataScale.addEnum("1.0x", 0x0); bits.DataScale.addEnum("0.1x", 0x1); bits.DataScale.addEnum("0.01x", 0x2); bits.DataScale.addEnum("0.001x", 0x3); bits.PMSubState.setBaseRegister(&r32); bits.PMSubState.setName("PMSubState"); bits.PMState.setBaseRegister(&r32); bits.PMState.setName("PMState"); bits.PMState.addEnum("D0", 0x0); bits.PMState.addEnum("D1", 0x1); bits.PMState.addEnum("D2", 0x2); bits.PMState.addEnum("D3", 0x3); bits.Type.setBaseRegister(&r32); bits.Type.setName("Type"); bits.Type.addEnum("PME Aux", 0x0); bits.Type.addEnum("Auxiliary", 0x1); bits.Type.addEnum("Idle", 0x2); bits.Type.addEnum("Sustained", 0x3); bits.Type.addEnum("Maximum", 0x7); bits.PowerRail.setBaseRegister(&r32); bits.PowerRail.setName("PowerRail"); bits.PowerRail.addEnum("Power 12V", 0x0); bits.PowerRail.addEnum("Power 3.3V", 0x1); bits.PowerRail.addEnum("Power 1.5V or 1.8V", 0x2); bits.PowerRail.addEnum("Thermal", 0x7); } RegDEVICEPciPowerBudget2_t& operator=(const RegDEVICEPciPowerBudget2_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciPowerBudget2_t; #define REG_DEVICE_PCI_POWER_BUDGET_3 ((volatile APE_DEVICE_H_uint32_t*)0xa004651c) /* See */ #define DEVICE_PCI_POWER_BUDGET_3_BASE_POWER_SHIFT 0u #define DEVICE_PCI_POWER_BUDGET_3_BASE_POWER_MASK 0xffu #define GET_DEVICE_PCI_POWER_BUDGET_3_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) #define SET_DEVICE_PCI_POWER_BUDGET_3_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) #define DEVICE_PCI_POWER_BUDGET_3_DATA_SCALE_SHIFT 8u #define DEVICE_PCI_POWER_BUDGET_3_DATA_SCALE_MASK 0x300u #define GET_DEVICE_PCI_POWER_BUDGET_3_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) #define SET_DEVICE_PCI_POWER_BUDGET_3_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) #define DEVICE_PCI_POWER_BUDGET_3_DATA_SCALE_1_0X 0x0u #define DEVICE_PCI_POWER_BUDGET_3_DATA_SCALE_0_1X 0x1u #define DEVICE_PCI_POWER_BUDGET_3_DATA_SCALE_0_01X 0x2u #define DEVICE_PCI_POWER_BUDGET_3_DATA_SCALE_0_001X 0x3u #define DEVICE_PCI_POWER_BUDGET_3_PM_SUB_STATE_SHIFT 10u #define DEVICE_PCI_POWER_BUDGET_3_PM_SUB_STATE_MASK 0x1c00u #define GET_DEVICE_PCI_POWER_BUDGET_3_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) #define SET_DEVICE_PCI_POWER_BUDGET_3_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) #define DEVICE_PCI_POWER_BUDGET_3_PM_STATE_SHIFT 13u #define DEVICE_PCI_POWER_BUDGET_3_PM_STATE_MASK 0x6000u #define GET_DEVICE_PCI_POWER_BUDGET_3_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) #define SET_DEVICE_PCI_POWER_BUDGET_3_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) #define DEVICE_PCI_POWER_BUDGET_3_PM_STATE_D0 0x0u #define DEVICE_PCI_POWER_BUDGET_3_PM_STATE_D1 0x1u #define DEVICE_PCI_POWER_BUDGET_3_PM_STATE_D2 0x2u #define DEVICE_PCI_POWER_BUDGET_3_PM_STATE_D3 0x3u #define DEVICE_PCI_POWER_BUDGET_3_TYPE_SHIFT 15u #define DEVICE_PCI_POWER_BUDGET_3_TYPE_MASK 0x38000u #define GET_DEVICE_PCI_POWER_BUDGET_3_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) #define SET_DEVICE_PCI_POWER_BUDGET_3_TYPE(__val__) (((__val__) << 15u) & 0x38000u) #define DEVICE_PCI_POWER_BUDGET_3_TYPE_PME_AUX 0x0u #define DEVICE_PCI_POWER_BUDGET_3_TYPE_AUXILIARY 0x1u #define DEVICE_PCI_POWER_BUDGET_3_TYPE_IDLE 0x2u #define DEVICE_PCI_POWER_BUDGET_3_TYPE_SUSTAINED 0x3u #define DEVICE_PCI_POWER_BUDGET_3_TYPE_MAXIMUM 0x7u #define DEVICE_PCI_POWER_BUDGET_3_POWER_RAIL_SHIFT 18u #define DEVICE_PCI_POWER_BUDGET_3_POWER_RAIL_MASK 0x1c0000u #define GET_DEVICE_PCI_POWER_BUDGET_3_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) #define SET_DEVICE_PCI_POWER_BUDGET_3_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) #define DEVICE_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_12V 0x0u #define DEVICE_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_3_3V 0x1u #define DEVICE_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u #define DEVICE_PCI_POWER_BUDGET_3_POWER_RAIL_THERMAL 0x7u /** @brief Register definition for @ref DEVICE_t.PciPowerBudget3. */ typedef register_container RegDEVICEPciPowerBudget3_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciPowerBudget3"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciPowerBudget3_t() { /** @brief constructor for @ref DEVICE_t.PciPowerBudget3. */ r32.setName("PciPowerBudget3"); bits.BasePower.setBaseRegister(&r32); bits.BasePower.setName("BasePower"); bits.DataScale.setBaseRegister(&r32); bits.DataScale.setName("DataScale"); bits.DataScale.addEnum("1.0x", 0x0); bits.DataScale.addEnum("0.1x", 0x1); bits.DataScale.addEnum("0.01x", 0x2); bits.DataScale.addEnum("0.001x", 0x3); bits.PMSubState.setBaseRegister(&r32); bits.PMSubState.setName("PMSubState"); bits.PMState.setBaseRegister(&r32); bits.PMState.setName("PMState"); bits.PMState.addEnum("D0", 0x0); bits.PMState.addEnum("D1", 0x1); bits.PMState.addEnum("D2", 0x2); bits.PMState.addEnum("D3", 0x3); bits.Type.setBaseRegister(&r32); bits.Type.setName("Type"); bits.Type.addEnum("PME Aux", 0x0); bits.Type.addEnum("Auxiliary", 0x1); bits.Type.addEnum("Idle", 0x2); bits.Type.addEnum("Sustained", 0x3); bits.Type.addEnum("Maximum", 0x7); bits.PowerRail.setBaseRegister(&r32); bits.PowerRail.setName("PowerRail"); bits.PowerRail.addEnum("Power 12V", 0x0); bits.PowerRail.addEnum("Power 3.3V", 0x1); bits.PowerRail.addEnum("Power 1.5V or 1.8V", 0x2); bits.PowerRail.addEnum("Thermal", 0x7); } RegDEVICEPciPowerBudget3_t& operator=(const RegDEVICEPciPowerBudget3_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciPowerBudget3_t; #define REG_DEVICE_PCI_POWER_BUDGET_4 ((volatile APE_DEVICE_H_uint32_t*)0xa0046520) /* See */ #define DEVICE_PCI_POWER_BUDGET_4_BASE_POWER_SHIFT 0u #define DEVICE_PCI_POWER_BUDGET_4_BASE_POWER_MASK 0xffu #define GET_DEVICE_PCI_POWER_BUDGET_4_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) #define SET_DEVICE_PCI_POWER_BUDGET_4_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) #define DEVICE_PCI_POWER_BUDGET_4_DATA_SCALE_SHIFT 8u #define DEVICE_PCI_POWER_BUDGET_4_DATA_SCALE_MASK 0x300u #define GET_DEVICE_PCI_POWER_BUDGET_4_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) #define SET_DEVICE_PCI_POWER_BUDGET_4_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) #define DEVICE_PCI_POWER_BUDGET_4_DATA_SCALE_1_0X 0x0u #define DEVICE_PCI_POWER_BUDGET_4_DATA_SCALE_0_1X 0x1u #define DEVICE_PCI_POWER_BUDGET_4_DATA_SCALE_0_01X 0x2u #define DEVICE_PCI_POWER_BUDGET_4_DATA_SCALE_0_001X 0x3u #define DEVICE_PCI_POWER_BUDGET_4_PM_SUB_STATE_SHIFT 10u #define DEVICE_PCI_POWER_BUDGET_4_PM_SUB_STATE_MASK 0x1c00u #define GET_DEVICE_PCI_POWER_BUDGET_4_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) #define SET_DEVICE_PCI_POWER_BUDGET_4_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) #define DEVICE_PCI_POWER_BUDGET_4_PM_STATE_SHIFT 13u #define DEVICE_PCI_POWER_BUDGET_4_PM_STATE_MASK 0x6000u #define GET_DEVICE_PCI_POWER_BUDGET_4_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) #define SET_DEVICE_PCI_POWER_BUDGET_4_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) #define DEVICE_PCI_POWER_BUDGET_4_PM_STATE_D0 0x0u #define DEVICE_PCI_POWER_BUDGET_4_PM_STATE_D1 0x1u #define DEVICE_PCI_POWER_BUDGET_4_PM_STATE_D2 0x2u #define DEVICE_PCI_POWER_BUDGET_4_PM_STATE_D3 0x3u #define DEVICE_PCI_POWER_BUDGET_4_TYPE_SHIFT 15u #define DEVICE_PCI_POWER_BUDGET_4_TYPE_MASK 0x38000u #define GET_DEVICE_PCI_POWER_BUDGET_4_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) #define SET_DEVICE_PCI_POWER_BUDGET_4_TYPE(__val__) (((__val__) << 15u) & 0x38000u) #define DEVICE_PCI_POWER_BUDGET_4_TYPE_PME_AUX 0x0u #define DEVICE_PCI_POWER_BUDGET_4_TYPE_AUXILIARY 0x1u #define DEVICE_PCI_POWER_BUDGET_4_TYPE_IDLE 0x2u #define DEVICE_PCI_POWER_BUDGET_4_TYPE_SUSTAINED 0x3u #define DEVICE_PCI_POWER_BUDGET_4_TYPE_MAXIMUM 0x7u #define DEVICE_PCI_POWER_BUDGET_4_POWER_RAIL_SHIFT 18u #define DEVICE_PCI_POWER_BUDGET_4_POWER_RAIL_MASK 0x1c0000u #define GET_DEVICE_PCI_POWER_BUDGET_4_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) #define SET_DEVICE_PCI_POWER_BUDGET_4_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) #define DEVICE_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_12V 0x0u #define DEVICE_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_3_3V 0x1u #define DEVICE_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u #define DEVICE_PCI_POWER_BUDGET_4_POWER_RAIL_THERMAL 0x7u /** @brief Register definition for @ref DEVICE_t.PciPowerBudget4. */ typedef register_container RegDEVICEPciPowerBudget4_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciPowerBudget4"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciPowerBudget4_t() { /** @brief constructor for @ref DEVICE_t.PciPowerBudget4. */ r32.setName("PciPowerBudget4"); bits.BasePower.setBaseRegister(&r32); bits.BasePower.setName("BasePower"); bits.DataScale.setBaseRegister(&r32); bits.DataScale.setName("DataScale"); bits.DataScale.addEnum("1.0x", 0x0); bits.DataScale.addEnum("0.1x", 0x1); bits.DataScale.addEnum("0.01x", 0x2); bits.DataScale.addEnum("0.001x", 0x3); bits.PMSubState.setBaseRegister(&r32); bits.PMSubState.setName("PMSubState"); bits.PMState.setBaseRegister(&r32); bits.PMState.setName("PMState"); bits.PMState.addEnum("D0", 0x0); bits.PMState.addEnum("D1", 0x1); bits.PMState.addEnum("D2", 0x2); bits.PMState.addEnum("D3", 0x3); bits.Type.setBaseRegister(&r32); bits.Type.setName("Type"); bits.Type.addEnum("PME Aux", 0x0); bits.Type.addEnum("Auxiliary", 0x1); bits.Type.addEnum("Idle", 0x2); bits.Type.addEnum("Sustained", 0x3); bits.Type.addEnum("Maximum", 0x7); bits.PowerRail.setBaseRegister(&r32); bits.PowerRail.setName("PowerRail"); bits.PowerRail.addEnum("Power 12V", 0x0); bits.PowerRail.addEnum("Power 3.3V", 0x1); bits.PowerRail.addEnum("Power 1.5V or 1.8V", 0x2); bits.PowerRail.addEnum("Thermal", 0x7); } RegDEVICEPciPowerBudget4_t& operator=(const RegDEVICEPciPowerBudget4_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciPowerBudget4_t; #define REG_DEVICE_PCI_POWER_BUDGET_5 ((volatile APE_DEVICE_H_uint32_t*)0xa0046524) /* See */ #define DEVICE_PCI_POWER_BUDGET_5_BASE_POWER_SHIFT 0u #define DEVICE_PCI_POWER_BUDGET_5_BASE_POWER_MASK 0xffu #define GET_DEVICE_PCI_POWER_BUDGET_5_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) #define SET_DEVICE_PCI_POWER_BUDGET_5_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) #define DEVICE_PCI_POWER_BUDGET_5_DATA_SCALE_SHIFT 8u #define DEVICE_PCI_POWER_BUDGET_5_DATA_SCALE_MASK 0x300u #define GET_DEVICE_PCI_POWER_BUDGET_5_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) #define SET_DEVICE_PCI_POWER_BUDGET_5_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) #define DEVICE_PCI_POWER_BUDGET_5_DATA_SCALE_1_0X 0x0u #define DEVICE_PCI_POWER_BUDGET_5_DATA_SCALE_0_1X 0x1u #define DEVICE_PCI_POWER_BUDGET_5_DATA_SCALE_0_01X 0x2u #define DEVICE_PCI_POWER_BUDGET_5_DATA_SCALE_0_001X 0x3u #define DEVICE_PCI_POWER_BUDGET_5_PM_SUB_STATE_SHIFT 10u #define DEVICE_PCI_POWER_BUDGET_5_PM_SUB_STATE_MASK 0x1c00u #define GET_DEVICE_PCI_POWER_BUDGET_5_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) #define SET_DEVICE_PCI_POWER_BUDGET_5_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) #define DEVICE_PCI_POWER_BUDGET_5_PM_STATE_SHIFT 13u #define DEVICE_PCI_POWER_BUDGET_5_PM_STATE_MASK 0x6000u #define GET_DEVICE_PCI_POWER_BUDGET_5_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) #define SET_DEVICE_PCI_POWER_BUDGET_5_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) #define DEVICE_PCI_POWER_BUDGET_5_PM_STATE_D0 0x0u #define DEVICE_PCI_POWER_BUDGET_5_PM_STATE_D1 0x1u #define DEVICE_PCI_POWER_BUDGET_5_PM_STATE_D2 0x2u #define DEVICE_PCI_POWER_BUDGET_5_PM_STATE_D3 0x3u #define DEVICE_PCI_POWER_BUDGET_5_TYPE_SHIFT 15u #define DEVICE_PCI_POWER_BUDGET_5_TYPE_MASK 0x38000u #define GET_DEVICE_PCI_POWER_BUDGET_5_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) #define SET_DEVICE_PCI_POWER_BUDGET_5_TYPE(__val__) (((__val__) << 15u) & 0x38000u) #define DEVICE_PCI_POWER_BUDGET_5_TYPE_PME_AUX 0x0u #define DEVICE_PCI_POWER_BUDGET_5_TYPE_AUXILIARY 0x1u #define DEVICE_PCI_POWER_BUDGET_5_TYPE_IDLE 0x2u #define DEVICE_PCI_POWER_BUDGET_5_TYPE_SUSTAINED 0x3u #define DEVICE_PCI_POWER_BUDGET_5_TYPE_MAXIMUM 0x7u #define DEVICE_PCI_POWER_BUDGET_5_POWER_RAIL_SHIFT 18u #define DEVICE_PCI_POWER_BUDGET_5_POWER_RAIL_MASK 0x1c0000u #define GET_DEVICE_PCI_POWER_BUDGET_5_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) #define SET_DEVICE_PCI_POWER_BUDGET_5_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) #define DEVICE_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_12V 0x0u #define DEVICE_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_3_3V 0x1u #define DEVICE_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u #define DEVICE_PCI_POWER_BUDGET_5_POWER_RAIL_THERMAL 0x7u /** @brief Register definition for @ref DEVICE_t.PciPowerBudget5. */ typedef register_container RegDEVICEPciPowerBudget5_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciPowerBudget5"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciPowerBudget5_t() { /** @brief constructor for @ref DEVICE_t.PciPowerBudget5. */ r32.setName("PciPowerBudget5"); bits.BasePower.setBaseRegister(&r32); bits.BasePower.setName("BasePower"); bits.DataScale.setBaseRegister(&r32); bits.DataScale.setName("DataScale"); bits.DataScale.addEnum("1.0x", 0x0); bits.DataScale.addEnum("0.1x", 0x1); bits.DataScale.addEnum("0.01x", 0x2); bits.DataScale.addEnum("0.001x", 0x3); bits.PMSubState.setBaseRegister(&r32); bits.PMSubState.setName("PMSubState"); bits.PMState.setBaseRegister(&r32); bits.PMState.setName("PMState"); bits.PMState.addEnum("D0", 0x0); bits.PMState.addEnum("D1", 0x1); bits.PMState.addEnum("D2", 0x2); bits.PMState.addEnum("D3", 0x3); bits.Type.setBaseRegister(&r32); bits.Type.setName("Type"); bits.Type.addEnum("PME Aux", 0x0); bits.Type.addEnum("Auxiliary", 0x1); bits.Type.addEnum("Idle", 0x2); bits.Type.addEnum("Sustained", 0x3); bits.Type.addEnum("Maximum", 0x7); bits.PowerRail.setBaseRegister(&r32); bits.PowerRail.setName("PowerRail"); bits.PowerRail.addEnum("Power 12V", 0x0); bits.PowerRail.addEnum("Power 3.3V", 0x1); bits.PowerRail.addEnum("Power 1.5V or 1.8V", 0x2); bits.PowerRail.addEnum("Thermal", 0x7); } RegDEVICEPciPowerBudget5_t& operator=(const RegDEVICEPciPowerBudget5_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciPowerBudget5_t; #define REG_DEVICE_PCI_POWER_BUDGET_6 ((volatile APE_DEVICE_H_uint32_t*)0xa0046528) /* See */ #define DEVICE_PCI_POWER_BUDGET_6_BASE_POWER_SHIFT 0u #define DEVICE_PCI_POWER_BUDGET_6_BASE_POWER_MASK 0xffu #define GET_DEVICE_PCI_POWER_BUDGET_6_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) #define SET_DEVICE_PCI_POWER_BUDGET_6_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) #define DEVICE_PCI_POWER_BUDGET_6_DATA_SCALE_SHIFT 8u #define DEVICE_PCI_POWER_BUDGET_6_DATA_SCALE_MASK 0x300u #define GET_DEVICE_PCI_POWER_BUDGET_6_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) #define SET_DEVICE_PCI_POWER_BUDGET_6_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) #define DEVICE_PCI_POWER_BUDGET_6_DATA_SCALE_1_0X 0x0u #define DEVICE_PCI_POWER_BUDGET_6_DATA_SCALE_0_1X 0x1u #define DEVICE_PCI_POWER_BUDGET_6_DATA_SCALE_0_01X 0x2u #define DEVICE_PCI_POWER_BUDGET_6_DATA_SCALE_0_001X 0x3u #define DEVICE_PCI_POWER_BUDGET_6_PM_SUB_STATE_SHIFT 10u #define DEVICE_PCI_POWER_BUDGET_6_PM_SUB_STATE_MASK 0x1c00u #define GET_DEVICE_PCI_POWER_BUDGET_6_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) #define SET_DEVICE_PCI_POWER_BUDGET_6_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) #define DEVICE_PCI_POWER_BUDGET_6_PM_STATE_SHIFT 13u #define DEVICE_PCI_POWER_BUDGET_6_PM_STATE_MASK 0x6000u #define GET_DEVICE_PCI_POWER_BUDGET_6_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) #define SET_DEVICE_PCI_POWER_BUDGET_6_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) #define DEVICE_PCI_POWER_BUDGET_6_PM_STATE_D0 0x0u #define DEVICE_PCI_POWER_BUDGET_6_PM_STATE_D1 0x1u #define DEVICE_PCI_POWER_BUDGET_6_PM_STATE_D2 0x2u #define DEVICE_PCI_POWER_BUDGET_6_PM_STATE_D3 0x3u #define DEVICE_PCI_POWER_BUDGET_6_TYPE_SHIFT 15u #define DEVICE_PCI_POWER_BUDGET_6_TYPE_MASK 0x38000u #define GET_DEVICE_PCI_POWER_BUDGET_6_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) #define SET_DEVICE_PCI_POWER_BUDGET_6_TYPE(__val__) (((__val__) << 15u) & 0x38000u) #define DEVICE_PCI_POWER_BUDGET_6_TYPE_PME_AUX 0x0u #define DEVICE_PCI_POWER_BUDGET_6_TYPE_AUXILIARY 0x1u #define DEVICE_PCI_POWER_BUDGET_6_TYPE_IDLE 0x2u #define DEVICE_PCI_POWER_BUDGET_6_TYPE_SUSTAINED 0x3u #define DEVICE_PCI_POWER_BUDGET_6_TYPE_MAXIMUM 0x7u #define DEVICE_PCI_POWER_BUDGET_6_POWER_RAIL_SHIFT 18u #define DEVICE_PCI_POWER_BUDGET_6_POWER_RAIL_MASK 0x1c0000u #define GET_DEVICE_PCI_POWER_BUDGET_6_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) #define SET_DEVICE_PCI_POWER_BUDGET_6_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) #define DEVICE_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_12V 0x0u #define DEVICE_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_3_3V 0x1u #define DEVICE_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u #define DEVICE_PCI_POWER_BUDGET_6_POWER_RAIL_THERMAL 0x7u /** @brief Register definition for @ref DEVICE_t.PciPowerBudget6. */ typedef register_container RegDEVICEPciPowerBudget6_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciPowerBudget6"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciPowerBudget6_t() { /** @brief constructor for @ref DEVICE_t.PciPowerBudget6. */ r32.setName("PciPowerBudget6"); bits.BasePower.setBaseRegister(&r32); bits.BasePower.setName("BasePower"); bits.DataScale.setBaseRegister(&r32); bits.DataScale.setName("DataScale"); bits.DataScale.addEnum("1.0x", 0x0); bits.DataScale.addEnum("0.1x", 0x1); bits.DataScale.addEnum("0.01x", 0x2); bits.DataScale.addEnum("0.001x", 0x3); bits.PMSubState.setBaseRegister(&r32); bits.PMSubState.setName("PMSubState"); bits.PMState.setBaseRegister(&r32); bits.PMState.setName("PMState"); bits.PMState.addEnum("D0", 0x0); bits.PMState.addEnum("D1", 0x1); bits.PMState.addEnum("D2", 0x2); bits.PMState.addEnum("D3", 0x3); bits.Type.setBaseRegister(&r32); bits.Type.setName("Type"); bits.Type.addEnum("PME Aux", 0x0); bits.Type.addEnum("Auxiliary", 0x1); bits.Type.addEnum("Idle", 0x2); bits.Type.addEnum("Sustained", 0x3); bits.Type.addEnum("Maximum", 0x7); bits.PowerRail.setBaseRegister(&r32); bits.PowerRail.setName("PowerRail"); bits.PowerRail.addEnum("Power 12V", 0x0); bits.PowerRail.addEnum("Power 3.3V", 0x1); bits.PowerRail.addEnum("Power 1.5V or 1.8V", 0x2); bits.PowerRail.addEnum("Thermal", 0x7); } RegDEVICEPciPowerBudget6_t& operator=(const RegDEVICEPciPowerBudget6_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciPowerBudget6_t; #define REG_DEVICE_PCI_POWER_BUDGET_7 ((volatile APE_DEVICE_H_uint32_t*)0xa004652c) /* See */ #define DEVICE_PCI_POWER_BUDGET_7_BASE_POWER_SHIFT 0u #define DEVICE_PCI_POWER_BUDGET_7_BASE_POWER_MASK 0xffu #define GET_DEVICE_PCI_POWER_BUDGET_7_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) #define SET_DEVICE_PCI_POWER_BUDGET_7_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) #define DEVICE_PCI_POWER_BUDGET_7_DATA_SCALE_SHIFT 8u #define DEVICE_PCI_POWER_BUDGET_7_DATA_SCALE_MASK 0x300u #define GET_DEVICE_PCI_POWER_BUDGET_7_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) #define SET_DEVICE_PCI_POWER_BUDGET_7_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) #define DEVICE_PCI_POWER_BUDGET_7_DATA_SCALE_1_0X 0x0u #define DEVICE_PCI_POWER_BUDGET_7_DATA_SCALE_0_1X 0x1u #define DEVICE_PCI_POWER_BUDGET_7_DATA_SCALE_0_01X 0x2u #define DEVICE_PCI_POWER_BUDGET_7_DATA_SCALE_0_001X 0x3u #define DEVICE_PCI_POWER_BUDGET_7_PM_SUB_STATE_SHIFT 10u #define DEVICE_PCI_POWER_BUDGET_7_PM_SUB_STATE_MASK 0x1c00u #define GET_DEVICE_PCI_POWER_BUDGET_7_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) #define SET_DEVICE_PCI_POWER_BUDGET_7_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) #define DEVICE_PCI_POWER_BUDGET_7_PM_STATE_SHIFT 13u #define DEVICE_PCI_POWER_BUDGET_7_PM_STATE_MASK 0x6000u #define GET_DEVICE_PCI_POWER_BUDGET_7_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) #define SET_DEVICE_PCI_POWER_BUDGET_7_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) #define DEVICE_PCI_POWER_BUDGET_7_PM_STATE_D0 0x0u #define DEVICE_PCI_POWER_BUDGET_7_PM_STATE_D1 0x1u #define DEVICE_PCI_POWER_BUDGET_7_PM_STATE_D2 0x2u #define DEVICE_PCI_POWER_BUDGET_7_PM_STATE_D3 0x3u #define DEVICE_PCI_POWER_BUDGET_7_TYPE_SHIFT 15u #define DEVICE_PCI_POWER_BUDGET_7_TYPE_MASK 0x38000u #define GET_DEVICE_PCI_POWER_BUDGET_7_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) #define SET_DEVICE_PCI_POWER_BUDGET_7_TYPE(__val__) (((__val__) << 15u) & 0x38000u) #define DEVICE_PCI_POWER_BUDGET_7_TYPE_PME_AUX 0x0u #define DEVICE_PCI_POWER_BUDGET_7_TYPE_AUXILIARY 0x1u #define DEVICE_PCI_POWER_BUDGET_7_TYPE_IDLE 0x2u #define DEVICE_PCI_POWER_BUDGET_7_TYPE_SUSTAINED 0x3u #define DEVICE_PCI_POWER_BUDGET_7_TYPE_MAXIMUM 0x7u #define DEVICE_PCI_POWER_BUDGET_7_POWER_RAIL_SHIFT 18u #define DEVICE_PCI_POWER_BUDGET_7_POWER_RAIL_MASK 0x1c0000u #define GET_DEVICE_PCI_POWER_BUDGET_7_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) #define SET_DEVICE_PCI_POWER_BUDGET_7_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) #define DEVICE_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_12V 0x0u #define DEVICE_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_3_3V 0x1u #define DEVICE_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u #define DEVICE_PCI_POWER_BUDGET_7_POWER_RAIL_THERMAL 0x7u /** @brief Register definition for @ref DEVICE_t.PciPowerBudget7. */ typedef register_container RegDEVICEPciPowerBudget7_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11) /** @brief Specifies the thermal load or power rail of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerRail, 18, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 15, 3) /** @brief Specifies the power management state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMState, 13, 2) /** @brief Specifies the power management sub state of the operating condition being described. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMSubState, 10, 3) /** @brief Specifies the scale to apply to the Base Power value. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DataScale, 8, 2) /** @brief Specifies in watts the base power value in the given operating condition. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BasePower, 0, 8) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "PciPowerBudget7"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEPciPowerBudget7_t() { /** @brief constructor for @ref DEVICE_t.PciPowerBudget7. */ r32.setName("PciPowerBudget7"); bits.BasePower.setBaseRegister(&r32); bits.BasePower.setName("BasePower"); bits.DataScale.setBaseRegister(&r32); bits.DataScale.setName("DataScale"); bits.DataScale.addEnum("1.0x", 0x0); bits.DataScale.addEnum("0.1x", 0x1); bits.DataScale.addEnum("0.01x", 0x2); bits.DataScale.addEnum("0.001x", 0x3); bits.PMSubState.setBaseRegister(&r32); bits.PMSubState.setName("PMSubState"); bits.PMState.setBaseRegister(&r32); bits.PMState.setName("PMState"); bits.PMState.addEnum("D0", 0x0); bits.PMState.addEnum("D1", 0x1); bits.PMState.addEnum("D2", 0x2); bits.PMState.addEnum("D3", 0x3); bits.Type.setBaseRegister(&r32); bits.Type.setName("Type"); bits.Type.addEnum("PME Aux", 0x0); bits.Type.addEnum("Auxiliary", 0x1); bits.Type.addEnum("Idle", 0x2); bits.Type.addEnum("Sustained", 0x3); bits.Type.addEnum("Maximum", 0x7); bits.PowerRail.setBaseRegister(&r32); bits.PowerRail.setName("PowerRail"); bits.PowerRail.addEnum("Power 12V", 0x0); bits.PowerRail.addEnum("Power 3.3V", 0x1); bits.PowerRail.addEnum("Power 1.5V or 1.8V", 0x2); bits.PowerRail.addEnum("Thermal", 0x7); } RegDEVICEPciPowerBudget7_t& operator=(const RegDEVICEPciPowerBudget7_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEPciPowerBudget7_t; #define REG_DEVICE_6530 ((volatile APE_DEVICE_H_uint32_t*)0xa0046530) /* */ /** @brief Register definition for @ref DEVICE_t.6530. */ typedef register_container RegDEVICE6530_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "6530"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE6530_t() { /** @brief constructor for @ref DEVICE_t.6530. */ r32.setName("6530"); } RegDEVICE6530_t& operator=(const RegDEVICE6530_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE6530_t; #define REG_DEVICE_6550 ((volatile APE_DEVICE_H_uint32_t*)0xa0046550) /* The LSB in this undocumented and unknown register is set if the device is a LOM (LAN-on-Motherboard) design (i.e., builtin to a system and not an expansion card). */ /** @brief Register definition for @ref DEVICE_t.6550. */ typedef register_container RegDEVICE6550_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "6550"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE6550_t() { /** @brief constructor for @ref DEVICE_t.6550. */ r32.setName("6550"); } RegDEVICE6550_t& operator=(const RegDEVICE6550_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE6550_t; #define REG_DEVICE_65F4 ((volatile APE_DEVICE_H_uint32_t*)0xa00465f4) /* */ /** @brief Register definition for @ref DEVICE_t.65f4. */ typedef register_container RegDEVICE65f4_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "65f4"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE65f4_t() { /** @brief constructor for @ref DEVICE_t.65f4. */ r32.setName("65f4"); } RegDEVICE65f4_t& operator=(const RegDEVICE65f4_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE65f4_t; #define REG_DEVICE_GRC_MODE_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa0046800) /* */ #define DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP_SHIFT 16u #define DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP_MASK 0x10000u #define GET_DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP(__reg__) (((__reg__) & 0x10000) >> 16u) #define SET_DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP(__val__) (((__val__) << 16u) & 0x10000u) #define DEVICE_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_SHIFT 19u #define DEVICE_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_MASK 0x80000u #define GET_DEVICE_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) #define SET_DEVICE_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) #define DEVICE_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_SHIFT 21u #define DEVICE_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_MASK 0x200000u #define GET_DEVICE_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__reg__) (((__reg__) & 0x200000) >> 21u) #define SET_DEVICE_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__val__) (((__val__) << 21u) & 0x200000u) #define DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_SHIFT 22u #define DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_MASK 0x400000u #define GET_DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__reg__) (((__reg__) & 0x400000) >> 22u) #define SET_DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__val__) (((__val__) << 22u) & 0x400000u) #define DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_SHIFT 29u #define DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_MASK 0x20000000u #define GET_DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__reg__) (((__reg__) & 0x20000000) >> 29u) #define SET_DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__val__) (((__val__) << 29u) & 0x20000000u) #define DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_SHIFT 31u #define DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_MASK 0x80000000u #define GET_DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__reg__) (((__reg__) & 0x80000000) >> 31u) #define SET_DEVICE_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref DEVICE_t.GrcModeControl. */ typedef register_container RegDEVICEGrcModeControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) /** @brief The host stack is ready to receive data from the NIC. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HostStackUp, 16, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_18_17, 17, 2) /** @brief Write 1 to this bit to enable Time Sync Mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TimeSyncModeEnable, 19, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_20_20, 20, 1) /** @brief The host must set this bit before attempting to update the Flash or SEEPROM. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NVRAMWriteEnable, 21, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIeTL_DIV_DL_DIV_PLMapping1, 22, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_28_23, 23, 6) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIeTL_DIV_DL_DIV_PLMapping2, 29, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_30_30, 30, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIeTL_DIV_DL_DIV_PLMapping3, 31, 1) #elif defined(__BIG_ENDIAN__) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIeTL_DIV_DL_DIV_PLMapping3, 31, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_30_30, 30, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIeTL_DIV_DL_DIV_PLMapping2, 29, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_28_23, 23, 6) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIeTL_DIV_DL_DIV_PLMapping1, 22, 1) /** @brief The host must set this bit before attempting to update the Flash or SEEPROM. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NVRAMWriteEnable, 21, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_20_20, 20, 1) /** @brief Write 1 to this bit to enable Time Sync Mode. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TimeSyncModeEnable, 19, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_18_17, 17, 2) /** @brief The host stack is ready to receive data from the NIC. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HostStackUp, 16, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "GrcModeControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEGrcModeControl_t() { /** @brief constructor for @ref DEVICE_t.GrcModeControl. */ r32.setName("GrcModeControl"); bits.HostStackUp.setBaseRegister(&r32); bits.HostStackUp.setName("HostStackUp"); bits.TimeSyncModeEnable.setBaseRegister(&r32); bits.TimeSyncModeEnable.setName("TimeSyncModeEnable"); bits.NVRAMWriteEnable.setBaseRegister(&r32); bits.NVRAMWriteEnable.setName("NVRAMWriteEnable"); bits.PCIeTL_DIV_DL_DIV_PLMapping1.setBaseRegister(&r32); bits.PCIeTL_DIV_DL_DIV_PLMapping1.setName("PCIeTL_DIV_DL_DIV_PLMapping1"); bits.PCIeTL_DIV_DL_DIV_PLMapping2.setBaseRegister(&r32); bits.PCIeTL_DIV_DL_DIV_PLMapping2.setName("PCIeTL_DIV_DL_DIV_PLMapping2"); bits.PCIeTL_DIV_DL_DIV_PLMapping3.setBaseRegister(&r32); bits.PCIeTL_DIV_DL_DIV_PLMapping3.setName("PCIeTL_DIV_DL_DIV_PLMapping3"); } RegDEVICEGrcModeControl_t& operator=(const RegDEVICEGrcModeControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEGrcModeControl_t; #define REG_DEVICE_MISCELLANEOUS_CONFIG ((volatile APE_DEVICE_H_uint32_t*)0xa0046804) /* */ #define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 0u #define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x1u #define GET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x1) >> 0u) #define SET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 0u) & 0x1u) #define DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER_SHIFT 1u #define DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER_MASK 0xfeu #define GET_DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER(__reg__) (((__reg__) & 0xfe) >> 1u) #define SET_DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER(__val__) (((__val__) << 1u) & 0xfeu) #define DEVICE_MISCELLANEOUS_CONFIG_BOND_ID_SHIFT 13u #define DEVICE_MISCELLANEOUS_CONFIG_BOND_ID_MASK 0x1e000u #define GET_DEVICE_MISCELLANEOUS_CONFIG_BOND_ID(__reg__) (((__reg__) & 0x1e000) >> 13u) #define SET_DEVICE_MISCELLANEOUS_CONFIG_BOND_ID(__val__) (((__val__) << 13u) & 0x1e000u) #define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_SHIFT 17u #define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_MASK 0x60000u #define GET_DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE(__reg__) (((__reg__) & 0x60000) >> 17u) #define SET_DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE(__val__) (((__val__) << 17u) & 0x60000u) #define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D0 0x0u #define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D1 0x1u #define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D2 0x2u #define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D3 0x3u #define DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE_SHIFT 19u #define DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE_MASK 0x80000u #define GET_DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE(__reg__) (((__reg__) & 0x80000) >> 19u) #define SET_DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE(__val__) (((__val__) << 19u) & 0x80000u) #define DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN_SHIFT 20u #define DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN_MASK 0x100000u #define GET_DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN(__reg__) (((__reg__) & 0x100000) >> 20u) #define SET_DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN(__val__) (((__val__) << 20u) & 0x100000u) #define DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET_SHIFT 29u #define DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET_MASK 0x20000000u #define GET_DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET(__reg__) (((__reg__) & 0x20000000) >> 29u) #define SET_DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET(__val__) (((__val__) << 29u) & 0x20000000u) /** @brief Register definition for @ref DEVICE_t.MiscellaneousConfig. */ typedef register_container RegDEVICEMiscellaneousConfig_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Write 1 to this bit resets the CORE_CLK blocks in the device. This is a self-clearing bit. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GRCReset, 0, 1) /** @brief Local Core clock frequency in MHz, minus 1, which should correspond to each advance of the timer. Reset to all 1. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TimerPrescaler, 1, 7) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_12_8, 8, 5) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BondID, 13, 4) /** @brief Indicates the current power state of the device. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerState, 17, 2) /** @brief State of PME Enable for this device. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMEENState, 19, 1) /** @brief Setting this bit will power down the device (power consumption is ~20 mW). This bit is cleared by PCI reset. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Powerdown, 20, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_28_21, 21, 8) /** @brief Setting this bit will prevent reset to PCIE block. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DisableGRCReset, 29, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_30, 30, 2) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_30, 30, 2) /** @brief Setting this bit will prevent reset to PCIE block. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DisableGRCReset, 29, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_28_21, 21, 8) /** @brief Setting this bit will power down the device (power consumption is ~20 mW). This bit is cleared by PCI reset. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Powerdown, 20, 1) /** @brief State of PME Enable for this device. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMEENState, 19, 1) /** @brief Indicates the current power state of the device. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerState, 17, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BondID, 13, 4) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_12_8, 8, 5) /** @brief Local Core clock frequency in MHz, minus 1, which should correspond to each advance of the timer. Reset to all 1. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TimerPrescaler, 1, 7) /** @brief Write 1 to this bit resets the CORE_CLK blocks in the device. This is a self-clearing bit. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GRCReset, 0, 1) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "MiscellaneousConfig"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEMiscellaneousConfig_t() { /** @brief constructor for @ref DEVICE_t.MiscellaneousConfig. */ r32.setName("MiscellaneousConfig"); bits.GRCReset.setBaseRegister(&r32); bits.GRCReset.setName("GRCReset"); bits.TimerPrescaler.setBaseRegister(&r32); bits.TimerPrescaler.setName("TimerPrescaler"); bits.BondID.setBaseRegister(&r32); bits.BondID.setName("BondID"); bits.PowerState.setBaseRegister(&r32); bits.PowerState.setName("PowerState"); bits.PowerState.addEnum("D0", 0x0); bits.PowerState.addEnum("D1", 0x1); bits.PowerState.addEnum("D2", 0x2); bits.PowerState.addEnum("D3", 0x3); bits.PMEENState.setBaseRegister(&r32); bits.PMEENState.setName("PMEENState"); bits.Powerdown.setBaseRegister(&r32); bits.Powerdown.setName("Powerdown"); bits.DisableGRCReset.setBaseRegister(&r32); bits.DisableGRCReset.setName("DisableGRCReset"); } RegDEVICEMiscellaneousConfig_t& operator=(const RegDEVICEMiscellaneousConfig_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEMiscellaneousConfig_t; #define REG_DEVICE_MISCELLANEOUS_LOCAL_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa0046808) /* */ #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT_SHIFT 5u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT_MASK 0x20u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT(__reg__) (((__reg__) & 0x20) >> 5u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT(__val__) (((__val__) << 5u) & 0x20u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE_SHIFT 6u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE_MASK 0x40u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x40) >> 6u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE(__val__) (((__val__) << 6u) & 0x40u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_SHIFT 7u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_MASK 0x80u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT(__reg__) (((__reg__) & 0x80) >> 7u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT(__val__) (((__val__) << 7u) & 0x80u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_SHIFT 8u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_MASK 0x100u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__reg__) (((__reg__) & 0x100) >> 8u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__val__) (((__val__) << 8u) & 0x100u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_SHIFT 9u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_MASK 0x200u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__reg__) (((__reg__) & 0x200) >> 9u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__val__) (((__val__) << 9u) & 0x200u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_SHIFT 10u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_MASK 0x400u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__reg__) (((__reg__) & 0x400) >> 10u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__val__) (((__val__) << 10u) & 0x400u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_SHIFT 11u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_MASK 0x800u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__val__) (((__val__) << 11u) & 0x800u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_SHIFT 12u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_MASK 0x1000u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x1000) >> 12u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__val__) (((__val__) << 12u) & 0x1000u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_SHIFT 13u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_MASK 0x2000u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x2000) >> 13u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__val__) (((__val__) << 13u) & 0x2000u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_SHIFT 14u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_MASK 0x4000u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__reg__) (((__reg__) & 0x4000) >> 14u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__val__) (((__val__) << 14u) & 0x4000u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_SHIFT 15u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_MASK 0x8000u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__reg__) (((__reg__) & 0x8000) >> 15u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__val__) (((__val__) << 15u) & 0x8000u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_SHIFT 16u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_MASK 0x10000u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__reg__) (((__reg__) & 0x10000) >> 16u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__val__) (((__val__) << 16u) & 0x10000u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN_SHIFT 17u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN_MASK 0xfe0000u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN(__reg__) (((__reg__) & 0xfe0000) >> 17u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN(__val__) (((__val__) << 17u) & 0xfe0000u) #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_SHIFT 24u #define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_MASK 0x1000000u #define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__reg__) (((__reg__) & 0x1000000) >> 24u) #define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__val__) (((__val__) << 24u) & 0x1000000u) /** @brief Register definition for @ref DEVICE_t.MiscellaneousLocalControl. */ typedef register_container RegDEVICEMiscellaneousLocalControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_0, 0, 5) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3Input, 5, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3OutputEnable, 6, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3Output, 7, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO0Input, 8, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO1Input, 9, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO2Input, 10, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO0OutputEnable, 11, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO1OutputEnable, 12, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO2OutputEnable, 13, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO0Output, 14, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO1Output, 15, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO2Output, 16, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIOIn, 17, 7) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AutoSEEPROMAccess, 24, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_25, 25, 7) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_25, 25, 7) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AutoSEEPROMAccess, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIOIn, 17, 7) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO2Output, 16, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO1Output, 15, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO0Output, 14, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO2OutputEnable, 13, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO1OutputEnable, 12, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO0OutputEnable, 11, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO2Input, 10, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO1Input, 9, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO0Input, 8, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3Output, 7, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3OutputEnable, 6, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3Input, 5, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_0, 0, 5) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "MiscellaneousLocalControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEMiscellaneousLocalControl_t() { /** @brief constructor for @ref DEVICE_t.MiscellaneousLocalControl. */ r32.setName("MiscellaneousLocalControl"); bits.GPIO3Input.setBaseRegister(&r32); bits.GPIO3Input.setName("GPIO3Input"); bits.GPIO3OutputEnable.setBaseRegister(&r32); bits.GPIO3OutputEnable.setName("GPIO3OutputEnable"); bits.GPIO3Output.setBaseRegister(&r32); bits.GPIO3Output.setName("GPIO3Output"); bits.GPIO0Input.setBaseRegister(&r32); bits.GPIO0Input.setName("GPIO0Input"); bits.GPIO1Input.setBaseRegister(&r32); bits.GPIO1Input.setName("GPIO1Input"); bits.GPIO2Input.setBaseRegister(&r32); bits.GPIO2Input.setName("GPIO2Input"); bits.GPIO0OutputEnable.setBaseRegister(&r32); bits.GPIO0OutputEnable.setName("GPIO0OutputEnable"); bits.GPIO1OutputEnable.setBaseRegister(&r32); bits.GPIO1OutputEnable.setName("GPIO1OutputEnable"); bits.GPIO2OutputEnable.setBaseRegister(&r32); bits.GPIO2OutputEnable.setName("GPIO2OutputEnable"); bits.GPIO0Output.setBaseRegister(&r32); bits.GPIO0Output.setName("GPIO0Output"); bits.GPIO1Output.setBaseRegister(&r32); bits.GPIO1Output.setName("GPIO1Output"); bits.GPIO2Output.setBaseRegister(&r32); bits.GPIO2Output.setName("GPIO2Output"); bits.APEGPIOIn.setBaseRegister(&r32); bits.APEGPIOIn.setName("APEGPIOIn"); bits.AutoSEEPROMAccess.setBaseRegister(&r32); bits.AutoSEEPROMAccess.setName("AutoSEEPROMAccess"); } RegDEVICEMiscellaneousLocalControl_t& operator=(const RegDEVICEMiscellaneousLocalControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEMiscellaneousLocalControl_t; #define REG_DEVICE_TIMER ((volatile APE_DEVICE_H_uint32_t*)0xa004680c) /* 32-bit free-running counter */ /** @brief Register definition for @ref DEVICE_t.Timer. */ typedef register_container RegDEVICETimer_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "Timer"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICETimer_t() { /** @brief constructor for @ref DEVICE_t.Timer. */ r32.setName("Timer"); } RegDEVICETimer_t& operator=(const RegDEVICETimer_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICETimer_t; #define REG_DEVICE_RX_CPU_EVENT ((volatile APE_DEVICE_H_uint32_t*)0xa0046810) /* */ #define DEVICE_RX_CPU_EVENT_MAC_ATTENTION_SHIFT 25u #define DEVICE_RX_CPU_EVENT_MAC_ATTENTION_MASK 0x2000000u #define GET_DEVICE_RX_CPU_EVENT_MAC_ATTENTION(__reg__) (((__reg__) & 0x2000000) >> 25u) #define SET_DEVICE_RX_CPU_EVENT_MAC_ATTENTION(__val__) (((__val__) << 25u) & 0x2000000u) #define DEVICE_RX_CPU_EVENT_RX_CPU_ATTENTION_SHIFT 26u #define DEVICE_RX_CPU_EVENT_RX_CPU_ATTENTION_MASK 0x4000000u #define GET_DEVICE_RX_CPU_EVENT_RX_CPU_ATTENTION(__reg__) (((__reg__) & 0x4000000) >> 26u) #define SET_DEVICE_RX_CPU_EVENT_RX_CPU_ATTENTION(__val__) (((__val__) << 26u) & 0x4000000u) #define DEVICE_RX_CPU_EVENT_TIMER_SHIFT 29u #define DEVICE_RX_CPU_EVENT_TIMER_MASK 0x20000000u #define GET_DEVICE_RX_CPU_EVENT_TIMER(__reg__) (((__reg__) & 0x20000000) >> 29u) #define SET_DEVICE_RX_CPU_EVENT_TIMER(__val__) (((__val__) << 29u) & 0x20000000u) #define DEVICE_RX_CPU_EVENT_VPD_ATTENTION_SHIFT 30u #define DEVICE_RX_CPU_EVENT_VPD_ATTENTION_MASK 0x40000000u #define GET_DEVICE_RX_CPU_EVENT_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) #define SET_DEVICE_RX_CPU_EVENT_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) /** @brief Register definition for @ref DEVICE_t.RxCpuEvent. */ typedef register_container RegDEVICERxCpuEvent_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_24_0, 0, 25) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACAttention, 25, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXCPUAttention, 26, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_28_27, 27, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Timer, 29, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, VPDAttention, 30, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_31, 31, 1) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_31, 31, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, VPDAttention, 30, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Timer, 29, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_28_27, 27, 2) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXCPUAttention, 26, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACAttention, 25, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_24_0, 0, 25) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxCpuEvent"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxCpuEvent_t() { /** @brief constructor for @ref DEVICE_t.RxCpuEvent. */ r32.setName("RxCpuEvent"); bits.MACAttention.setBaseRegister(&r32); bits.MACAttention.setName("MACAttention"); bits.RXCPUAttention.setBaseRegister(&r32); bits.RXCPUAttention.setName("RXCPUAttention"); bits.Timer.setBaseRegister(&r32); bits.Timer.setName("Timer"); bits.VPDAttention.setBaseRegister(&r32); bits.VPDAttention.setName("VPDAttention"); } RegDEVICERxCpuEvent_t& operator=(const RegDEVICERxCpuEvent_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxCpuEvent_t; #define REG_DEVICE_6838 ((volatile APE_DEVICE_H_uint32_t*)0xa0046838) /* Unknown. Used by PXE agent. */ /** @brief Register definition for @ref DEVICE_t.6838. */ typedef register_container RegDEVICE6838_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "6838"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE6838_t() { /** @brief constructor for @ref DEVICE_t.6838. */ r32.setName("6838"); } RegDEVICE6838_t& operator=(const RegDEVICE6838_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE6838_t; #define REG_DEVICE_MDI_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa0046844) /* The register manual only mentions this in the changelog; it was removed from the manual in a previous revision. :| */ /** @brief Register definition for @ref DEVICE_t.MdiControl. */ typedef register_container RegDEVICEMdiControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "MdiControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEMdiControl_t() { /** @brief constructor for @ref DEVICE_t.MdiControl. */ r32.setName("MdiControl"); } RegDEVICEMdiControl_t& operator=(const RegDEVICEMdiControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEMdiControl_t; #define REG_DEVICE_RX_CPU_EVENT_ENABLE ((volatile APE_DEVICE_H_uint32_t*)0xa004684c) /* */ #define DEVICE_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_SHIFT 30u #define DEVICE_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_MASK 0x40000000u #define GET_DEVICE_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) #define SET_DEVICE_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) /** @brief Register definition for @ref DEVICE_t.RxCpuEventEnable. */ typedef register_container RegDEVICERxCpuEventEnable_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_29_0, 0, 30) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, VPDAttention, 30, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_31, 31, 1) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_31, 31, 1) /** @brief */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, VPDAttention, 30, 1) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_29_0, 0, 30) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "RxCpuEventEnable"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICERxCpuEventEnable_t() { /** @brief constructor for @ref DEVICE_t.RxCpuEventEnable. */ r32.setName("RxCpuEventEnable"); bits.VPDAttention.setBaseRegister(&r32); bits.VPDAttention.setName("VPDAttention"); } RegDEVICERxCpuEventEnable_t& operator=(const RegDEVICERxCpuEventEnable_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICERxCpuEventEnable_t; #define REG_DEVICE_FAST_BOOT_PROGRAM_COUNTER ((volatile APE_DEVICE_H_uint32_t*)0xa0046894) /* */ #define DEVICE_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_SHIFT 0u #define DEVICE_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_MASK 0x7fffffffu #define GET_DEVICE_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__reg__) (((__reg__) & 0x7fffffff) >> 0u) #define SET_DEVICE_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__val__) (((__val__) << 0u) & 0x7fffffffu) #define DEVICE_FAST_BOOT_PROGRAM_COUNTER_ENABLE_SHIFT 31u #define DEVICE_FAST_BOOT_PROGRAM_COUNTER_ENABLE_MASK 0x80000000u #define GET_DEVICE_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) #define SET_DEVICE_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref DEVICE_t.FastBootProgramCounter. */ typedef register_container RegDEVICEFastBootProgramCounter_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief This field is used by the CPU to keep track of the location of the phase 1 boot code in RX MBUF. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ProgramCounter, 0, 31) /** @brief This bit is used by the CPU to keep track of whether or not there is valid phase 1 boot code stored in the RX MBUF. If the bit is set, then RXMBUF contains valid boot code. Otherwise, it is assumed that RXMBUF does not contain valid boot code. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Enable, 31, 1) #elif defined(__BIG_ENDIAN__) /** @brief This bit is used by the CPU to keep track of whether or not there is valid phase 1 boot code stored in the RX MBUF. If the bit is set, then RXMBUF contains valid boot code. Otherwise, it is assumed that RXMBUF does not contain valid boot code. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Enable, 31, 1) /** @brief This field is used by the CPU to keep track of the location of the phase 1 boot code in RX MBUF. */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ProgramCounter, 0, 31) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "FastBootProgramCounter"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEFastBootProgramCounter_t() { /** @brief constructor for @ref DEVICE_t.FastBootProgramCounter. */ r32.setName("FastBootProgramCounter"); bits.ProgramCounter.setBaseRegister(&r32); bits.ProgramCounter.setName("ProgramCounter"); bits.Enable.setBaseRegister(&r32); bits.Enable.setName("Enable"); } RegDEVICEFastBootProgramCounter_t& operator=(const RegDEVICEFastBootProgramCounter_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEFastBootProgramCounter_t; #define REG_DEVICE_EXPANSION_ROM_ADDR ((volatile APE_DEVICE_H_uint32_t*)0xa00468ec) /* Expansion ROM base address, expect to be d- word aligned. */ /** @brief Register definition for @ref DEVICE_t.ExpansionRomAddr. */ typedef register_container RegDEVICEExpansionRomAddr_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "ExpansionRomAddr"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEExpansionRomAddr_t() { /** @brief constructor for @ref DEVICE_t.ExpansionRomAddr. */ r32.setName("ExpansionRomAddr"); } RegDEVICEExpansionRomAddr_t& operator=(const RegDEVICEExpansionRomAddr_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEExpansionRomAddr_t; #define REG_DEVICE_68F0 ((volatile APE_DEVICE_H_uint32_t*)0xa00468f0) /* */ /** @brief Register definition for @ref DEVICE_t.68f0. */ typedef register_container RegDEVICE68f0_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "68f0"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE68f0_t() { /** @brief constructor for @ref DEVICE_t.68f0. */ r32.setName("68f0"); } RegDEVICE68f0_t& operator=(const RegDEVICE68f0_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE68f0_t; #define REG_DEVICE_EAV_REF_CLOCK_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa0046908) /* */ #define DEVICE_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SHIFT 16u #define DEVICE_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_MASK 0x30000u #define GET_DEVICE_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__reg__) (((__reg__) & 0x30000) >> 16u) #define SET_DEVICE_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__val__) (((__val__) << 16u) & 0x30000u) #define DEVICE_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_0_ 0x0u #define DEVICE_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_1_ 0x1u #define DEVICE_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_0_ 0x2u #define DEVICE_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_1_ 0x3u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SHIFT 18u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_MASK 0x1c0000u #define GET_DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__reg__) (((__reg__) & 0x1c0000) >> 18u) #define SET_DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__val__) (((__val__) << 18u) & 0x1c0000u) #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_NOT_USED 0x0u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_0_ 0x4u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_1_ 0x5u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_0_ 0x6u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_1_ 0x7u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SHIFT 21u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_MASK 0xe00000u #define GET_DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__reg__) (((__reg__) & 0xe00000) >> 21u) #define SET_DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__val__) (((__val__) << 21u) & 0xe00000u) #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_NOT_USED 0x0u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_0_ 0x4u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_1_ 0x5u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_0_ 0x6u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_1_ 0x7u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SHIFT 24u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_MASK 0x7000000u #define GET_DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__reg__) (((__reg__) & 0x7000000) >> 24u) #define SET_DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__val__) (((__val__) << 24u) & 0x7000000u) #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_NOT_USED 0x0u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_0_ 0x4u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_1_ 0x5u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_0_ 0x6u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_1_ 0x7u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SHIFT 27u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_MASK 0x38000000u #define GET_DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__reg__) (((__reg__) & 0x38000000) >> 27u) #define SET_DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__val__) (((__val__) << 27u) & 0x38000000u) #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_NOT_USED 0x0u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_0_ 0x4u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_1_ 0x5u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_0_ 0x6u #define DEVICE_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_1_ 0x7u /** @brief Register definition for @ref DEVICE_t.EavRefClockControl. */ typedef register_container RegDEVICEEavRefClockControl_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) /** @brief The MAC/Port dedicated TimeSync_GPIO pin is mapped via this field */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TimesyncGPIOMapping, 16, 2) /** @brief APE_GPIO[0] pin is mapped to 1588 input/ output via this field */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIO0Mapping, 18, 3) /** @brief APE_GPIO[1] pin is mapped to 1588 input/ output via this field */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIO1Mapping, 21, 3) /** @brief APE_GPIO[2] pin is mapped to 1588 input/ output via this field */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIO2Mapping, 24, 3) /** @brief APE_GPIO[3] pin is mapped to 1588 input/ output via this field */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIO3Mapping, 27, 3) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_30, 30, 2) #elif defined(__BIG_ENDIAN__) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_30, 30, 2) /** @brief APE_GPIO[3] pin is mapped to 1588 input/ output via this field */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIO3Mapping, 27, 3) /** @brief APE_GPIO[2] pin is mapped to 1588 input/ output via this field */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIO2Mapping, 24, 3) /** @brief APE_GPIO[1] pin is mapped to 1588 input/ output via this field */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIO1Mapping, 21, 3) /** @brief APE_GPIO[0] pin is mapped to 1588 input/ output via this field */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIO0Mapping, 18, 3) /** @brief The MAC/Port dedicated TimeSync_GPIO pin is mapped via this field */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TimesyncGPIOMapping, 16, 2) /** @brief Padding */ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16) #else #error Unknown Endian #endif BITFIELD_END(APE_DEVICE_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "EavRefClockControl"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICEEavRefClockControl_t() { /** @brief constructor for @ref DEVICE_t.EavRefClockControl. */ r32.setName("EavRefClockControl"); bits.TimesyncGPIOMapping.setBaseRegister(&r32); bits.TimesyncGPIOMapping.setName("TimesyncGPIOMapping"); bits.TimesyncGPIOMapping.addEnum("Snap-Shot[0]", 0x0); bits.TimesyncGPIOMapping.addEnum("Snap-Shot[1]", 0x1); bits.TimesyncGPIOMapping.addEnum("Time Watchdog[0]", 0x2); bits.TimesyncGPIOMapping.addEnum("Time Watchdog[1]", 0x3); bits.APEGPIO0Mapping.setBaseRegister(&r32); bits.APEGPIO0Mapping.setName("APEGPIO0Mapping"); bits.APEGPIO0Mapping.addEnum("Not Used", 0x0); bits.APEGPIO0Mapping.addEnum("Snap-Shot[0]", 0x4); bits.APEGPIO0Mapping.addEnum("Snap-Shot[1]", 0x5); bits.APEGPIO0Mapping.addEnum("Time Watchdog[0]", 0x6); bits.APEGPIO0Mapping.addEnum("Time Watchdog[1]", 0x7); bits.APEGPIO1Mapping.setBaseRegister(&r32); bits.APEGPIO1Mapping.setName("APEGPIO1Mapping"); bits.APEGPIO1Mapping.addEnum("Not Used", 0x0); bits.APEGPIO1Mapping.addEnum("Snap-Shot[0]", 0x4); bits.APEGPIO1Mapping.addEnum("Snap-Shot[1]", 0x5); bits.APEGPIO1Mapping.addEnum("Time Watchdog[0]", 0x6); bits.APEGPIO1Mapping.addEnum("Time Watchdog[1]", 0x7); bits.APEGPIO2Mapping.setBaseRegister(&r32); bits.APEGPIO2Mapping.setName("APEGPIO2Mapping"); bits.APEGPIO2Mapping.addEnum("Not Used", 0x0); bits.APEGPIO2Mapping.addEnum("Snap-Shot[0]", 0x4); bits.APEGPIO2Mapping.addEnum("Snap-Shot[1]", 0x5); bits.APEGPIO2Mapping.addEnum("Time Watchdog[0]", 0x6); bits.APEGPIO2Mapping.addEnum("Time Watchdog[1]", 0x7); bits.APEGPIO3Mapping.setBaseRegister(&r32); bits.APEGPIO3Mapping.setName("APEGPIO3Mapping"); bits.APEGPIO3Mapping.addEnum("Not Used", 0x0); bits.APEGPIO3Mapping.addEnum("Snap-Shot[0]", 0x4); bits.APEGPIO3Mapping.addEnum("Snap-Shot[1]", 0x5); bits.APEGPIO3Mapping.addEnum("Time Watchdog[0]", 0x6); bits.APEGPIO3Mapping.addEnum("Time Watchdog[1]", 0x7); } RegDEVICEEavRefClockControl_t& operator=(const RegDEVICEEavRefClockControl_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICEEavRefClockControl_t; #define REG_DEVICE_7C04 ((volatile APE_DEVICE_H_uint32_t*)0xa0047c04) /* PCIe Transaction Cfg */ /** @brief Register definition for @ref DEVICE_t.7c04. */ typedef register_container RegDEVICE7c04_t { /** @brief 32bit direct register access. */ APE_DEVICE_H_uint32_t r32; #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "7c04"; } /** @brief Print register value. */ void print(void) { r32.print(); } RegDEVICE7c04_t() { /** @brief constructor for @ref DEVICE_t.7c04. */ r32.setName("7c04"); } RegDEVICE7c04_t& operator=(const RegDEVICE7c04_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ } RegDEVICE7c04_t; /** @brief Component definition for @ref DEVICE. */ typedef struct DEVICE_t { /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_0[26]; /** @brief */ RegDEVICEMiscellaneousHostControl_t MiscellaneousHostControl; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_108[1]; /** @brief */ RegDEVICEPciState_t PciState; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_116[1]; /** @brief Local controller memory address of a register than can be written or read by writing to the register data register. */ RegDEVICERegisterBase_t RegisterBase; /** @brief Local controller memory address of the NIC memory region that can be accessed via Memory Window data register. */ RegDEVICEMemoryBase_t MemoryBase; /** @brief Register Data at the location pointed by the Register Base Register. */ RegDEVICERegisterData_t RegisterData; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_132[1]; /** @brief UNDI Receive Return Ring Consumer Index Mailbox */ RegDEVICEUndiReceiveReturnRingConsumerIndex_t UndiReceiveReturnRingConsumerIndex; /** @brief UNDI Receive Return Ring Consumer Index Mailbox */ RegDEVICEUndiReceiveReturnRingConsumerIndexLow_t UndiReceiveReturnRingConsumerIndexLow; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_144[11]; /** @brief PCIe standard register. */ RegDEVICELinkStatusControl_t LinkStatusControl; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_192[14]; /** @brief APE Memory address to read/write using the APE Memory Data register.. */ RegDEVICEApeMemoryBase_t ApeMemoryBase; /** @brief APE Memory value at the location pointed by the Memory Base Register. */ RegDEVICEApeMemoryData_t ApeMemoryData; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_256[24]; /** @brief Unknown register. */ RegDEVICE160_t _160; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_356[167]; /** @brief */ RegDEVICEEmacMode_t EmacMode; /** @brief */ RegDEVICEEmacStatus_t EmacStatus; /** @brief */ RegDEVICEEmacEvent_t EmacEvent; /** @brief */ RegDEVICELedControl_t LedControl; /** @brief Upper 2-bytes of this node's MAC address. */ RegDEVICEEmacMacAddresses0High_t EmacMacAddresses0High; /** @brief Lower 4-byte of this node's MAC address. */ RegDEVICEEmacMacAddresses0Low_t EmacMacAddresses0Low; /** @brief Upper 2-bytes of this node's MAC address. */ RegDEVICEEmacMacAddresses1High_t EmacMacAddresses1High; /** @brief Lower 4-byte of this node's MAC address. */ RegDEVICEEmacMacAddresses1Low_t EmacMacAddresses1Low; /** @brief Upper 2-bytes of this node's MAC address. */ RegDEVICEEmacMacAddresses2High_t EmacMacAddresses2High; /** @brief Lower 4-byte of this node's MAC address. */ RegDEVICEEmacMacAddresses2Low_t EmacMacAddresses2Low; /** @brief Upper 2-bytes of this node's MAC address. */ RegDEVICEEmacMacAddresses3High_t EmacMacAddresses3High; /** @brief Lower 4-byte of this node's MAC address. */ RegDEVICEEmacMacAddresses3Low_t EmacMacAddresses3Low; /** @brief Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */ RegDEVICEWolPatternPointer_t WolPatternPointer; /** @brief */ RegDEVICEWolPatternCfg_t WolPatternCfg; /** @brief Unknown register. */ RegDEVICE438_t _438; /** @brief 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */ RegDEVICEMtuSize_t MtuSize; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_1088[3]; /** @brief */ RegDEVICEMiiCommunication_t MiiCommunication; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_1104[1]; /** @brief */ RegDEVICEMiiMode_t MiiMode; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_1112[1]; /** @brief */ RegDEVICETransmitMacMode_t TransmitMacMode; /** @brief */ RegDEVICETransmitMacStatus_t TransmitMacStatus; /** @brief */ RegDEVICETransmitMacLengths_t TransmitMacLengths; /** @brief */ RegDEVICEReceiveMacMode_t ReceiveMacMode; /** @brief */ RegDEVICEReceiveMacStatus_t ReceiveMacStatus; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_1136[52]; /** @brief */ RegDEVICEPerfectMatch1High_t PerfectMatch1High; /** @brief */ RegDEVICEPerfectMatch1Low_t PerfectMatch1Low; /** @brief */ RegDEVICEPerfectMatch2High_t PerfectMatch2High; /** @brief */ RegDEVICEPerfectMatch2Low_t PerfectMatch2Low; /** @brief */ RegDEVICEPerfectMatch3High_t PerfectMatch3High; /** @brief */ RegDEVICEPerfectMatch3Low_t PerfectMatch3Low; /** @brief */ RegDEVICEPerfectMatch4High_t PerfectMatch4High; /** @brief */ RegDEVICEPerfectMatch4Low_t PerfectMatch4Low; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_1376[21]; /** @brief This register reflects various status of the respective SGMII port when enabled. */ RegDEVICESgmiiStatus_t SgmiiStatus; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_1464[1682]; /** @brief */ RegDEVICEReceiveListPlacementMode_t ReceiveListPlacementMode; /** @brief */ RegDEVICEReceiveListPlacementStatus_t ReceiveListPlacementStatus; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_8200[1406]; /** @brief */ RegDEVICECpmuControl_t CpmuControl; /** @brief */ RegDEVICENoLinkPowerModeClockPolicy_t NoLinkPowerModeClockPolicy; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_13832[2]; /** @brief */ RegDEVICELinkAwarePowerModeClockPolicy_t LinkAwarePowerModeClockPolicy; /** @brief */ RegDEVICED0uClockPolicy_t D0uClockPolicy; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_13848[1]; /** @brief */ RegDEVICEApeClkPolicy_t ApeClkPolicy; /** @brief */ RegDEVICEApeSleepStateClockPolicy_t ApeSleepStateClockPolicy; /** @brief */ RegDEVICEClockSpeedOverridePolicy_t ClockSpeedOverridePolicy; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_13864[1]; /** @brief */ RegDEVICEStatus_t Status; /** @brief */ RegDEVICEClockStatus_t ClockStatus; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_13876[1]; /** @brief */ RegDEVICEGphyControlStatus_t GphyControlStatus; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_13884[7]; /** @brief */ RegDEVICEChipId_t ChipId; /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ RegDEVICEMutexRequest_t MutexRequest; /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ RegDEVICEMutexGrant_t MutexGrant; /** @brief */ RegDEVICEGphyStrap_t GphyStrap; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_13928[1]; /** @brief */ RegDEVICEFlashClockControlPolicy_t FlashClockControlPolicy; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_13936[3]; /** @brief */ RegDEVICETopLevelMiscellaneousControl1_t TopLevelMiscellaneousControl1; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_13952[12]; /** @brief */ RegDEVICEEeeMode_t EeeMode; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_14004[2]; /** @brief */ RegDEVICEEeeLinkIdleControl_t EeeLinkIdleControl; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_14016[4]; /** @brief */ RegDEVICEEeeControl_t EeeControl; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_14036[7]; /** @brief */ RegDEVICEGlobalMutexRequest_t GlobalMutexRequest; /** @brief */ RegDEVICEGlobalMutexGrant_t GlobalMutexGrant; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_14072[1]; /** @brief */ RegDEVICETemperatureMonitorControl_t TemperatureMonitorControl; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_14080[576]; /** @brief */ RegDEVICEMemoryArbiterMode_t MemoryArbiterMode; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_16388[255]; /** @brief */ RegDEVICEBufferManagerMode_t BufferManagerMode; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_17412[323]; /** @brief */ RegDEVICELsoNonlsoBdReadDmaCorruptionEnableControl_t LsoNonlsoBdReadDmaCorruptionEnableControl; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_18708[443]; /** @brief */ RegDEVICERxRiscMode_t RxRiscMode; /** @brief */ RegDEVICERxRiscStatus_t RxRiscStatus; /** @brief */ RegDEVICERxRiscEventMask_t RxRiscEventMask; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_20492[4]; /** @brief The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ RegDEVICERxRiscProgramCounter_t RxRiscProgramCounter; /** @brief This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed. */ RegDEVICERxRiscCurrentInstruction_t RxRiscCurrentInstruction; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_20516[1]; /** @brief Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can’t respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero. */ RegDEVICERxRiscInterruptEnable_t RxRiscInterruptEnable; /** @brief This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input. */ RegDEVICERxRiscInterruptVector_t RxRiscInterruptVector; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_20528[1]; /** @brief This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ RegDEVICERxRiscHardwareBreakpoint_t RxRiscHardwareBreakpoint; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_20536[4]; /** @brief This register indicates that address and branch type of the last branch that was taken. This register is for debug use only. */ RegDEVICERxRiscLastBranchAddress_t RxRiscLastBranchAddress; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_20556[109]; /** @brief $zero (R0) */ RegDEVICERxRiscRegister0_t RxRiscRegister0; /** @brief $at (R1) */ RegDEVICERxRiscRegister1_t RxRiscRegister1; /** @brief $v0 (R2) */ RegDEVICERxRiscRegister2_t RxRiscRegister2; /** @brief $v1 (R3) */ RegDEVICERxRiscRegister3_t RxRiscRegister3; /** @brief $a0 (R4) */ RegDEVICERxRiscRegister4_t RxRiscRegister4; /** @brief $a1 (R5) */ RegDEVICERxRiscRegister5_t RxRiscRegister5; /** @brief $a2 (R6) */ RegDEVICERxRiscRegister6_t RxRiscRegister6; /** @brief $a3 (R7) */ RegDEVICERxRiscRegister7_t RxRiscRegister7; /** @brief $t0 (R8) */ RegDEVICERxRiscRegister8_t RxRiscRegister8; /** @brief $t1 (R9) */ RegDEVICERxRiscRegister9_t RxRiscRegister9; /** @brief $t2 (R10) */ RegDEVICERxRiscRegister10_t RxRiscRegister10; /** @brief $t3 (R11) */ RegDEVICERxRiscRegister11_t RxRiscRegister11; /** @brief $t4 (R12) */ RegDEVICERxRiscRegister12_t RxRiscRegister12; /** @brief $t5 (R13) */ RegDEVICERxRiscRegister13_t RxRiscRegister13; /** @brief $t6 (R14) */ RegDEVICERxRiscRegister14_t RxRiscRegister14; /** @brief $t7 (R15) */ RegDEVICERxRiscRegister15_t RxRiscRegister15; /** @brief $s0 (R16) */ RegDEVICERxRiscRegister16_t RxRiscRegister16; /** @brief $s1 (R17) */ RegDEVICERxRiscRegister17_t RxRiscRegister17; /** @brief $s2 (R18) */ RegDEVICERxRiscRegister18_t RxRiscRegister18; /** @brief $s3 (R19) */ RegDEVICERxRiscRegister19_t RxRiscRegister19; /** @brief $s4 (R20) */ RegDEVICERxRiscRegister20_t RxRiscRegister20; /** @brief $s5 (R21) */ RegDEVICERxRiscRegister21_t RxRiscRegister21; /** @brief $s6 (R22) */ RegDEVICERxRiscRegister22_t RxRiscRegister22; /** @brief $s7 (R23) */ RegDEVICERxRiscRegister23_t RxRiscRegister23; /** @brief $t8 (R24) */ RegDEVICERxRiscRegister24_t RxRiscRegister24; /** @brief $t9 (R25) */ RegDEVICERxRiscRegister25_t RxRiscRegister25; /** @brief $k0 (R26) */ RegDEVICERxRiscRegister26_t RxRiscRegister26; /** @brief $k1 (R27) */ RegDEVICERxRiscRegister27_t RxRiscRegister27; /** @brief $gp (R28) */ RegDEVICERxRiscRegister28_t RxRiscRegister28; /** @brief $sp (R29) */ RegDEVICERxRiscRegister29_t RxRiscRegister29; /** @brief $fp (R30) */ RegDEVICERxRiscRegister30_t RxRiscRegister30; /** @brief $ra (R31) */ RegDEVICERxRiscRegister31_t RxRiscRegister31; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_21120[1122]; /** @brief */ RegDEVICE6408_t _6408; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_25612[1]; /** @brief This undocumented register is used to set PCIe Power Consumption information as reported in configuration space. It is loaded from NVM configuration data. */ RegDEVICEPciPowerConsumptionInfo_t PciPowerConsumptionInfo; /** @brief This undocumented register is used to set PCIe Power Dissipated information as reported in configuration space. It is loaded from NVM configuration data. */ RegDEVICEPciPowerDissipatedInfo_t PciPowerDissipatedInfo; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_25624[5]; /** @brief This undocumented register appears to be used to implement the PCI VPD capability. It is set to the VPD offset which was requested by the host by writing to the VPD register. */ RegDEVICEPciVpdRequest_t PciVpdRequest; /** @brief This undocumented register appears to be used to implement the PCI VPD capability. Bootcode writes the 32 bits of data loaded from the word requested by */ RegDEVICEPciVpdResponse_t PciVpdResponse; /** @brief This is the undocumented register used to set the PCI Vendor/Device ID, which is configurable from NVM. */ RegDEVICEPciVendorDeviceId_t PciVendorDeviceId; /** @brief This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */ RegDEVICEPciSubsystemId_t PciSubsystemId; /** @brief This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */ RegDEVICEPciClassCodeRevision_t PciClassCodeRevision; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_25664[32]; /** @brief */ RegDEVICE64c0_t _64c0; /** @brief */ RegDEVICE64c4_t _64c4; /** @brief */ RegDEVICE64c8_t _64c8; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_25804[4]; /** @brief */ RegDEVICE64dc_t _64dc; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_25824[9]; /** @brief This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ RegDEVICEPciSerialNumberLow_t PciSerialNumberLow; /** @brief This sets the high 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ RegDEVICEPciSerialNumberHigh_t PciSerialNumberHigh; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_25868[1]; /** @brief Used to report power budget capability data to the host. The values are loaded from NVM, and up to eight values may be specified. */ RegDEVICEPciPowerBudget0_t PciPowerBudget0; /** @brief See */ RegDEVICEPciPowerBudget1_t PciPowerBudget1; /** @brief See */ RegDEVICEPciPowerBudget2_t PciPowerBudget2; /** @brief See */ RegDEVICEPciPowerBudget3_t PciPowerBudget3; /** @brief See */ RegDEVICEPciPowerBudget4_t PciPowerBudget4; /** @brief See */ RegDEVICEPciPowerBudget5_t PciPowerBudget5; /** @brief See */ RegDEVICEPciPowerBudget6_t PciPowerBudget6; /** @brief See */ RegDEVICEPciPowerBudget7_t PciPowerBudget7; /** @brief */ RegDEVICE6530_t _6530; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_25908[7]; /** @brief The LSB in this undocumented and unknown register is set if the device is a LOM (LAN-on-Motherboard) design (i.e., builtin to a system and not an expansion card). */ RegDEVICE6550_t _6550; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_25940[40]; /** @brief */ RegDEVICE65f4_t _65f4; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_26104[130]; /** @brief */ RegDEVICEGrcModeControl_t GrcModeControl; /** @brief */ RegDEVICEMiscellaneousConfig_t MiscellaneousConfig; /** @brief */ RegDEVICEMiscellaneousLocalControl_t MiscellaneousLocalControl; /** @brief 32-bit free-running counter */ RegDEVICETimer_t Timer; /** @brief */ RegDEVICERxCpuEvent_t RxCpuEvent; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_26644[9]; /** @brief Unknown. Used by PXE agent. */ RegDEVICE6838_t _6838; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_26684[2]; /** @brief The register manual only mentions this in the changelog; it was removed from the manual in a previous revision. :| */ RegDEVICEMdiControl_t MdiControl; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_26696[1]; /** @brief */ RegDEVICERxCpuEventEnable_t RxCpuEventEnable; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_26704[17]; /** @brief */ RegDEVICEFastBootProgramCounter_t FastBootProgramCounter; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_26776[21]; /** @brief Expansion ROM base address, expect to be d- word aligned. */ RegDEVICEExpansionRomAddr_t ExpansionRomAddr; /** @brief */ RegDEVICE68f0_t _68f0; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_26868[5]; /** @brief */ RegDEVICEEavRefClockControl_t EavRefClockControl; /** @brief Reserved bytes to pad out data structure. */ APE_DEVICE_H_uint32_t reserved_26892[1214]; /** @brief PCIe Transaction Cfg */ RegDEVICE7c04_t _7c04; #ifdef CXX_SIMULATOR typedef uint32_t (*callback_t)(uint32_t, uint32_t, void*); callback_t mIndexReadCallback; void* mIndexReadCallbackArgs; callback_t mIndexWriteCallback; void* mIndexWriteCallbackArgs; DEVICE_t() : mIndexReadCallback(0), mIndexReadCallbackArgs(0), mIndexWriteCallback(0), mIndexWriteCallbackArgs(0) { for(int i = 0; i < 26; i++) { reserved_0[i].setComponentOffset(0x0 + (i * 4)); } MiscellaneousHostControl.r32.setComponentOffset(0x68); for(int i = 0; i < 1; i++) { reserved_108[i].setComponentOffset(0x6c + (i * 4)); } PciState.r32.setComponentOffset(0x70); for(int i = 0; i < 1; i++) { reserved_116[i].setComponentOffset(0x74 + (i * 4)); } RegisterBase.r32.setComponentOffset(0x78); MemoryBase.r32.setComponentOffset(0x7c); RegisterData.r32.setComponentOffset(0x80); for(int i = 0; i < 1; i++) { reserved_132[i].setComponentOffset(0x84 + (i * 4)); } UndiReceiveReturnRingConsumerIndex.r32.setComponentOffset(0x88); UndiReceiveReturnRingConsumerIndexLow.r32.setComponentOffset(0x8c); for(int i = 0; i < 11; i++) { reserved_144[i].setComponentOffset(0x90 + (i * 4)); } LinkStatusControl.r32.setComponentOffset(0xbc); for(int i = 0; i < 14; i++) { reserved_192[i].setComponentOffset(0xc0 + (i * 4)); } ApeMemoryBase.r32.setComponentOffset(0xf8); ApeMemoryData.r32.setComponentOffset(0xfc); for(int i = 0; i < 24; i++) { reserved_256[i].setComponentOffset(0x100 + (i * 4)); } _160.r32.setComponentOffset(0x160); for(int i = 0; i < 167; i++) { reserved_356[i].setComponentOffset(0x164 + (i * 4)); } EmacMode.r32.setComponentOffset(0x400); EmacStatus.r32.setComponentOffset(0x404); EmacEvent.r32.setComponentOffset(0x408); LedControl.r32.setComponentOffset(0x40c); EmacMacAddresses0High.r32.setComponentOffset(0x410); EmacMacAddresses0Low.r32.setComponentOffset(0x414); EmacMacAddresses1High.r32.setComponentOffset(0x418); EmacMacAddresses1Low.r32.setComponentOffset(0x41c); EmacMacAddresses2High.r32.setComponentOffset(0x420); EmacMacAddresses2Low.r32.setComponentOffset(0x424); EmacMacAddresses3High.r32.setComponentOffset(0x428); EmacMacAddresses3Low.r32.setComponentOffset(0x42c); WolPatternPointer.r32.setComponentOffset(0x430); WolPatternCfg.r32.setComponentOffset(0x434); _438.r32.setComponentOffset(0x438); MtuSize.r32.setComponentOffset(0x43c); for(int i = 0; i < 3; i++) { reserved_1088[i].setComponentOffset(0x440 + (i * 4)); } MiiCommunication.r32.setComponentOffset(0x44c); for(int i = 0; i < 1; i++) { reserved_1104[i].setComponentOffset(0x450 + (i * 4)); } MiiMode.r32.setComponentOffset(0x454); for(int i = 0; i < 1; i++) { reserved_1112[i].setComponentOffset(0x458 + (i * 4)); } TransmitMacMode.r32.setComponentOffset(0x45c); TransmitMacStatus.r32.setComponentOffset(0x460); TransmitMacLengths.r32.setComponentOffset(0x464); ReceiveMacMode.r32.setComponentOffset(0x468); ReceiveMacStatus.r32.setComponentOffset(0x46c); for(int i = 0; i < 52; i++) { reserved_1136[i].setComponentOffset(0x470 + (i * 4)); } PerfectMatch1High.r32.setComponentOffset(0x540); PerfectMatch1Low.r32.setComponentOffset(0x544); PerfectMatch2High.r32.setComponentOffset(0x548); PerfectMatch2Low.r32.setComponentOffset(0x54c); PerfectMatch3High.r32.setComponentOffset(0x550); PerfectMatch3Low.r32.setComponentOffset(0x554); PerfectMatch4High.r32.setComponentOffset(0x558); PerfectMatch4Low.r32.setComponentOffset(0x55c); for(int i = 0; i < 21; i++) { reserved_1376[i].setComponentOffset(0x560 + (i * 4)); } SgmiiStatus.r32.setComponentOffset(0x5b4); for(int i = 0; i < 1682; i++) { reserved_1464[i].setComponentOffset(0x5b8 + (i * 4)); } ReceiveListPlacementMode.r32.setComponentOffset(0x2000); ReceiveListPlacementStatus.r32.setComponentOffset(0x2004); for(int i = 0; i < 1406; i++) { reserved_8200[i].setComponentOffset(0x2008 + (i * 4)); } CpmuControl.r32.setComponentOffset(0x3600); NoLinkPowerModeClockPolicy.r32.setComponentOffset(0x3604); for(int i = 0; i < 2; i++) { reserved_13832[i].setComponentOffset(0x3608 + (i * 4)); } LinkAwarePowerModeClockPolicy.r32.setComponentOffset(0x3610); D0uClockPolicy.r32.setComponentOffset(0x3614); for(int i = 0; i < 1; i++) { reserved_13848[i].setComponentOffset(0x3618 + (i * 4)); } ApeClkPolicy.r32.setComponentOffset(0x361c); ApeSleepStateClockPolicy.r32.setComponentOffset(0x3620); ClockSpeedOverridePolicy.r32.setComponentOffset(0x3624); for(int i = 0; i < 1; i++) { reserved_13864[i].setComponentOffset(0x3628 + (i * 4)); } Status.r32.setComponentOffset(0x362c); ClockStatus.r32.setComponentOffset(0x3630); for(int i = 0; i < 1; i++) { reserved_13876[i].setComponentOffset(0x3634 + (i * 4)); } GphyControlStatus.r32.setComponentOffset(0x3638); for(int i = 0; i < 7; i++) { reserved_13884[i].setComponentOffset(0x363c + (i * 4)); } ChipId.r32.setComponentOffset(0x3658); MutexRequest.r32.setComponentOffset(0x365c); MutexGrant.r32.setComponentOffset(0x3660); GphyStrap.r32.setComponentOffset(0x3664); for(int i = 0; i < 1; i++) { reserved_13928[i].setComponentOffset(0x3668 + (i * 4)); } FlashClockControlPolicy.r32.setComponentOffset(0x366c); for(int i = 0; i < 3; i++) { reserved_13936[i].setComponentOffset(0x3670 + (i * 4)); } TopLevelMiscellaneousControl1.r32.setComponentOffset(0x367c); for(int i = 0; i < 12; i++) { reserved_13952[i].setComponentOffset(0x3680 + (i * 4)); } EeeMode.r32.setComponentOffset(0x36b0); for(int i = 0; i < 2; i++) { reserved_14004[i].setComponentOffset(0x36b4 + (i * 4)); } EeeLinkIdleControl.r32.setComponentOffset(0x36bc); for(int i = 0; i < 4; i++) { reserved_14016[i].setComponentOffset(0x36c0 + (i * 4)); } EeeControl.r32.setComponentOffset(0x36d0); for(int i = 0; i < 7; i++) { reserved_14036[i].setComponentOffset(0x36d4 + (i * 4)); } GlobalMutexRequest.r32.setComponentOffset(0x36f0); GlobalMutexGrant.r32.setComponentOffset(0x36f4); for(int i = 0; i < 1; i++) { reserved_14072[i].setComponentOffset(0x36f8 + (i * 4)); } TemperatureMonitorControl.r32.setComponentOffset(0x36fc); for(int i = 0; i < 576; i++) { reserved_14080[i].setComponentOffset(0x3700 + (i * 4)); } MemoryArbiterMode.r32.setComponentOffset(0x4000); for(int i = 0; i < 255; i++) { reserved_16388[i].setComponentOffset(0x4004 + (i * 4)); } BufferManagerMode.r32.setComponentOffset(0x4400); for(int i = 0; i < 323; i++) { reserved_17412[i].setComponentOffset(0x4404 + (i * 4)); } LsoNonlsoBdReadDmaCorruptionEnableControl.r32.setComponentOffset(0x4910); for(int i = 0; i < 443; i++) { reserved_18708[i].setComponentOffset(0x4914 + (i * 4)); } RxRiscMode.r32.setComponentOffset(0x5000); RxRiscStatus.r32.setComponentOffset(0x5004); RxRiscEventMask.r32.setComponentOffset(0x5008); for(int i = 0; i < 4; i++) { reserved_20492[i].setComponentOffset(0x500c + (i * 4)); } RxRiscProgramCounter.r32.setComponentOffset(0x501c); RxRiscCurrentInstruction.r32.setComponentOffset(0x5020); for(int i = 0; i < 1; i++) { reserved_20516[i].setComponentOffset(0x5024 + (i * 4)); } RxRiscInterruptEnable.r32.setComponentOffset(0x5028); RxRiscInterruptVector.r32.setComponentOffset(0x502c); for(int i = 0; i < 1; i++) { reserved_20528[i].setComponentOffset(0x5030 + (i * 4)); } RxRiscHardwareBreakpoint.r32.setComponentOffset(0x5034); for(int i = 0; i < 4; i++) { reserved_20536[i].setComponentOffset(0x5038 + (i * 4)); } RxRiscLastBranchAddress.r32.setComponentOffset(0x5048); for(int i = 0; i < 109; i++) { reserved_20556[i].setComponentOffset(0x504c + (i * 4)); } RxRiscRegister0.r32.setComponentOffset(0x5200); RxRiscRegister1.r32.setComponentOffset(0x5204); RxRiscRegister2.r32.setComponentOffset(0x5208); RxRiscRegister3.r32.setComponentOffset(0x520c); RxRiscRegister4.r32.setComponentOffset(0x5210); RxRiscRegister5.r32.setComponentOffset(0x5214); RxRiscRegister6.r32.setComponentOffset(0x5218); RxRiscRegister7.r32.setComponentOffset(0x521c); RxRiscRegister8.r32.setComponentOffset(0x5220); RxRiscRegister9.r32.setComponentOffset(0x5224); RxRiscRegister10.r32.setComponentOffset(0x5228); RxRiscRegister11.r32.setComponentOffset(0x522c); RxRiscRegister12.r32.setComponentOffset(0x5230); RxRiscRegister13.r32.setComponentOffset(0x5234); RxRiscRegister14.r32.setComponentOffset(0x5238); RxRiscRegister15.r32.setComponentOffset(0x523c); RxRiscRegister16.r32.setComponentOffset(0x5240); RxRiscRegister17.r32.setComponentOffset(0x5244); RxRiscRegister18.r32.setComponentOffset(0x5248); RxRiscRegister19.r32.setComponentOffset(0x524c); RxRiscRegister20.r32.setComponentOffset(0x5250); RxRiscRegister21.r32.setComponentOffset(0x5254); RxRiscRegister22.r32.setComponentOffset(0x5258); RxRiscRegister23.r32.setComponentOffset(0x525c); RxRiscRegister24.r32.setComponentOffset(0x5260); RxRiscRegister25.r32.setComponentOffset(0x5264); RxRiscRegister26.r32.setComponentOffset(0x5268); RxRiscRegister27.r32.setComponentOffset(0x526c); RxRiscRegister28.r32.setComponentOffset(0x5270); RxRiscRegister29.r32.setComponentOffset(0x5274); RxRiscRegister30.r32.setComponentOffset(0x5278); RxRiscRegister31.r32.setComponentOffset(0x527c); for(int i = 0; i < 1122; i++) { reserved_21120[i].setComponentOffset(0x5280 + (i * 4)); } _6408.r32.setComponentOffset(0x6408); for(int i = 0; i < 1; i++) { reserved_25612[i].setComponentOffset(0x640c + (i * 4)); } PciPowerConsumptionInfo.r32.setComponentOffset(0x6410); PciPowerDissipatedInfo.r32.setComponentOffset(0x6414); for(int i = 0; i < 5; i++) { reserved_25624[i].setComponentOffset(0x6418 + (i * 4)); } PciVpdRequest.r32.setComponentOffset(0x642c); PciVpdResponse.r32.setComponentOffset(0x6430); PciVendorDeviceId.r32.setComponentOffset(0x6434); PciSubsystemId.r32.setComponentOffset(0x6438); PciClassCodeRevision.r32.setComponentOffset(0x643c); for(int i = 0; i < 32; i++) { reserved_25664[i].setComponentOffset(0x6440 + (i * 4)); } _64c0.r32.setComponentOffset(0x64c0); _64c4.r32.setComponentOffset(0x64c4); _64c8.r32.setComponentOffset(0x64c8); for(int i = 0; i < 4; i++) { reserved_25804[i].setComponentOffset(0x64cc + (i * 4)); } _64dc.r32.setComponentOffset(0x64dc); for(int i = 0; i < 9; i++) { reserved_25824[i].setComponentOffset(0x64e0 + (i * 4)); } PciSerialNumberLow.r32.setComponentOffset(0x6504); PciSerialNumberHigh.r32.setComponentOffset(0x6508); for(int i = 0; i < 1; i++) { reserved_25868[i].setComponentOffset(0x650c + (i * 4)); } PciPowerBudget0.r32.setComponentOffset(0x6510); PciPowerBudget1.r32.setComponentOffset(0x6514); PciPowerBudget2.r32.setComponentOffset(0x6518); PciPowerBudget3.r32.setComponentOffset(0x651c); PciPowerBudget4.r32.setComponentOffset(0x6520); PciPowerBudget5.r32.setComponentOffset(0x6524); PciPowerBudget6.r32.setComponentOffset(0x6528); PciPowerBudget7.r32.setComponentOffset(0x652c); _6530.r32.setComponentOffset(0x6530); for(int i = 0; i < 7; i++) { reserved_25908[i].setComponentOffset(0x6534 + (i * 4)); } _6550.r32.setComponentOffset(0x6550); for(int i = 0; i < 40; i++) { reserved_25940[i].setComponentOffset(0x6554 + (i * 4)); } _65f4.r32.setComponentOffset(0x65f4); for(int i = 0; i < 130; i++) { reserved_26104[i].setComponentOffset(0x65f8 + (i * 4)); } GrcModeControl.r32.setComponentOffset(0x6800); MiscellaneousConfig.r32.setComponentOffset(0x6804); MiscellaneousLocalControl.r32.setComponentOffset(0x6808); Timer.r32.setComponentOffset(0x680c); RxCpuEvent.r32.setComponentOffset(0x6810); for(int i = 0; i < 9; i++) { reserved_26644[i].setComponentOffset(0x6814 + (i * 4)); } _6838.r32.setComponentOffset(0x6838); for(int i = 0; i < 2; i++) { reserved_26684[i].setComponentOffset(0x683c + (i * 4)); } MdiControl.r32.setComponentOffset(0x6844); for(int i = 0; i < 1; i++) { reserved_26696[i].setComponentOffset(0x6848 + (i * 4)); } RxCpuEventEnable.r32.setComponentOffset(0x684c); for(int i = 0; i < 17; i++) { reserved_26704[i].setComponentOffset(0x6850 + (i * 4)); } FastBootProgramCounter.r32.setComponentOffset(0x6894); for(int i = 0; i < 21; i++) { reserved_26776[i].setComponentOffset(0x6898 + (i * 4)); } ExpansionRomAddr.r32.setComponentOffset(0x68ec); _68f0.r32.setComponentOffset(0x68f0); for(int i = 0; i < 5; i++) { reserved_26868[i].setComponentOffset(0x68f4 + (i * 4)); } EavRefClockControl.r32.setComponentOffset(0x6908); for(int i = 0; i < 1214; i++) { reserved_26892[i].setComponentOffset(0x690c + (i * 4)); } _7c04.r32.setComponentOffset(0x7c04); } void print() { for(int i = 0; i < 26; i++) { reserved_0[i].print(); } MiscellaneousHostControl.print(); for(int i = 0; i < 1; i++) { reserved_108[i].print(); } PciState.print(); for(int i = 0; i < 1; i++) { reserved_116[i].print(); } RegisterBase.print(); MemoryBase.print(); RegisterData.print(); for(int i = 0; i < 1; i++) { reserved_132[i].print(); } UndiReceiveReturnRingConsumerIndex.print(); UndiReceiveReturnRingConsumerIndexLow.print(); for(int i = 0; i < 11; i++) { reserved_144[i].print(); } LinkStatusControl.print(); for(int i = 0; i < 14; i++) { reserved_192[i].print(); } ApeMemoryBase.print(); ApeMemoryData.print(); for(int i = 0; i < 24; i++) { reserved_256[i].print(); } _160.print(); for(int i = 0; i < 167; i++) { reserved_356[i].print(); } EmacMode.print(); EmacStatus.print(); EmacEvent.print(); LedControl.print(); EmacMacAddresses0High.print(); EmacMacAddresses0Low.print(); EmacMacAddresses1High.print(); EmacMacAddresses1Low.print(); EmacMacAddresses2High.print(); EmacMacAddresses2Low.print(); EmacMacAddresses3High.print(); EmacMacAddresses3Low.print(); WolPatternPointer.print(); WolPatternCfg.print(); _438.print(); MtuSize.print(); for(int i = 0; i < 3; i++) { reserved_1088[i].print(); } MiiCommunication.print(); for(int i = 0; i < 1; i++) { reserved_1104[i].print(); } MiiMode.print(); for(int i = 0; i < 1; i++) { reserved_1112[i].print(); } TransmitMacMode.print(); TransmitMacStatus.print(); TransmitMacLengths.print(); ReceiveMacMode.print(); ReceiveMacStatus.print(); for(int i = 0; i < 52; i++) { reserved_1136[i].print(); } PerfectMatch1High.print(); PerfectMatch1Low.print(); PerfectMatch2High.print(); PerfectMatch2Low.print(); PerfectMatch3High.print(); PerfectMatch3Low.print(); PerfectMatch4High.print(); PerfectMatch4Low.print(); for(int i = 0; i < 21; i++) { reserved_1376[i].print(); } SgmiiStatus.print(); for(int i = 0; i < 1682; i++) { reserved_1464[i].print(); } ReceiveListPlacementMode.print(); ReceiveListPlacementStatus.print(); for(int i = 0; i < 1406; i++) { reserved_8200[i].print(); } CpmuControl.print(); NoLinkPowerModeClockPolicy.print(); for(int i = 0; i < 2; i++) { reserved_13832[i].print(); } LinkAwarePowerModeClockPolicy.print(); D0uClockPolicy.print(); for(int i = 0; i < 1; i++) { reserved_13848[i].print(); } ApeClkPolicy.print(); ApeSleepStateClockPolicy.print(); ClockSpeedOverridePolicy.print(); for(int i = 0; i < 1; i++) { reserved_13864[i].print(); } Status.print(); ClockStatus.print(); for(int i = 0; i < 1; i++) { reserved_13876[i].print(); } GphyControlStatus.print(); for(int i = 0; i < 7; i++) { reserved_13884[i].print(); } ChipId.print(); MutexRequest.print(); MutexGrant.print(); GphyStrap.print(); for(int i = 0; i < 1; i++) { reserved_13928[i].print(); } FlashClockControlPolicy.print(); for(int i = 0; i < 3; i++) { reserved_13936[i].print(); } TopLevelMiscellaneousControl1.print(); for(int i = 0; i < 12; i++) { reserved_13952[i].print(); } EeeMode.print(); for(int i = 0; i < 2; i++) { reserved_14004[i].print(); } EeeLinkIdleControl.print(); for(int i = 0; i < 4; i++) { reserved_14016[i].print(); } EeeControl.print(); for(int i = 0; i < 7; i++) { reserved_14036[i].print(); } GlobalMutexRequest.print(); GlobalMutexGrant.print(); for(int i = 0; i < 1; i++) { reserved_14072[i].print(); } TemperatureMonitorControl.print(); for(int i = 0; i < 576; i++) { reserved_14080[i].print(); } MemoryArbiterMode.print(); for(int i = 0; i < 255; i++) { reserved_16388[i].print(); } BufferManagerMode.print(); for(int i = 0; i < 323; i++) { reserved_17412[i].print(); } LsoNonlsoBdReadDmaCorruptionEnableControl.print(); for(int i = 0; i < 443; i++) { reserved_18708[i].print(); } RxRiscMode.print(); RxRiscStatus.print(); RxRiscEventMask.print(); for(int i = 0; i < 4; i++) { reserved_20492[i].print(); } RxRiscProgramCounter.print(); RxRiscCurrentInstruction.print(); for(int i = 0; i < 1; i++) { reserved_20516[i].print(); } RxRiscInterruptEnable.print(); RxRiscInterruptVector.print(); for(int i = 0; i < 1; i++) { reserved_20528[i].print(); } RxRiscHardwareBreakpoint.print(); for(int i = 0; i < 4; i++) { reserved_20536[i].print(); } RxRiscLastBranchAddress.print(); for(int i = 0; i < 109; i++) { reserved_20556[i].print(); } RxRiscRegister0.print(); RxRiscRegister1.print(); RxRiscRegister2.print(); RxRiscRegister3.print(); RxRiscRegister4.print(); RxRiscRegister5.print(); RxRiscRegister6.print(); RxRiscRegister7.print(); RxRiscRegister8.print(); RxRiscRegister9.print(); RxRiscRegister10.print(); RxRiscRegister11.print(); RxRiscRegister12.print(); RxRiscRegister13.print(); RxRiscRegister14.print(); RxRiscRegister15.print(); RxRiscRegister16.print(); RxRiscRegister17.print(); RxRiscRegister18.print(); RxRiscRegister19.print(); RxRiscRegister20.print(); RxRiscRegister21.print(); RxRiscRegister22.print(); RxRiscRegister23.print(); RxRiscRegister24.print(); RxRiscRegister25.print(); RxRiscRegister26.print(); RxRiscRegister27.print(); RxRiscRegister28.print(); RxRiscRegister29.print(); RxRiscRegister30.print(); RxRiscRegister31.print(); for(int i = 0; i < 1122; i++) { reserved_21120[i].print(); } _6408.print(); for(int i = 0; i < 1; i++) { reserved_25612[i].print(); } PciPowerConsumptionInfo.print(); PciPowerDissipatedInfo.print(); for(int i = 0; i < 5; i++) { reserved_25624[i].print(); } PciVpdRequest.print(); PciVpdResponse.print(); PciVendorDeviceId.print(); PciSubsystemId.print(); PciClassCodeRevision.print(); for(int i = 0; i < 32; i++) { reserved_25664[i].print(); } _64c0.print(); _64c4.print(); _64c8.print(); for(int i = 0; i < 4; i++) { reserved_25804[i].print(); } _64dc.print(); for(int i = 0; i < 9; i++) { reserved_25824[i].print(); } PciSerialNumberLow.print(); PciSerialNumberHigh.print(); for(int i = 0; i < 1; i++) { reserved_25868[i].print(); } PciPowerBudget0.print(); PciPowerBudget1.print(); PciPowerBudget2.print(); PciPowerBudget3.print(); PciPowerBudget4.print(); PciPowerBudget5.print(); PciPowerBudget6.print(); PciPowerBudget7.print(); _6530.print(); for(int i = 0; i < 7; i++) { reserved_25908[i].print(); } _6550.print(); for(int i = 0; i < 40; i++) { reserved_25940[i].print(); } _65f4.print(); for(int i = 0; i < 130; i++) { reserved_26104[i].print(); } GrcModeControl.print(); MiscellaneousConfig.print(); MiscellaneousLocalControl.print(); Timer.print(); RxCpuEvent.print(); for(int i = 0; i < 9; i++) { reserved_26644[i].print(); } _6838.print(); for(int i = 0; i < 2; i++) { reserved_26684[i].print(); } MdiControl.print(); for(int i = 0; i < 1; i++) { reserved_26696[i].print(); } RxCpuEventEnable.print(); for(int i = 0; i < 17; i++) { reserved_26704[i].print(); } FastBootProgramCounter.print(); for(int i = 0; i < 21; i++) { reserved_26776[i].print(); } ExpansionRomAddr.print(); _68f0.print(); for(int i = 0; i < 5; i++) { reserved_26868[i].print(); } EavRefClockControl.print(); for(int i = 0; i < 1214; i++) { reserved_26892[i].print(); } _7c04.print(); } uint32_t read(int offset) { return mIndexReadCallback(0, offset, mIndexReadCallbackArgs); } void write(int offset, uint32_t value) { (void)mIndexWriteCallback(value, offset, mIndexWriteCallbackArgs); } #endif /* CXX_SIMULATOR */ } DEVICE_t; /** @brief Device Registers, function 0 */ extern volatile DEVICE_t DEVICE; #ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ #undef volatile #endif /* CXX_SIMULATOR */ #undef register_container #undef BITFIELD_BEGIN #undef BITFIELD_MEMBER #undef BITFIELD_END #ifndef CXX_SIMULATOR _Static_assert(sizeof(DEVICE_t) == 31752, "sizeof(DEVICE_t) must be 31752"); #endif #endif /* !APE_DEVICE_H */ /** @} */

49.301381

1,080

0.725526

e6b807974e3c39e757209695e20eb47e096cb010

388

h

C

uicure/include/uicure.h

highfestiva/life

b05b592502d72980ab55e13e84330b74a966f377

[ "BSD-3-Clause" ]

9

2019-09-03T18:33:31.000Z

2022-02-04T04:00:02.000Z

uicure/include/uicure.h

highfestiva/life

b05b592502d72980ab55e13e84330b74a966f377

[ "BSD-3-Clause" ]

null

uicure/include/uicure.h

highfestiva/life

b05b592502d72980ab55e13e84330b74a966f377

[ "BSD-3-Clause" ]

null

// Author: Jonas Byström // Copyright (c) Pixel Doctrine #pragma once #include "../../lepra/include/lepratypes.h" #include "../../lepra/include/log.h" namespace cure { class RuntimeVariableScope; } namespace UiCure { using namespace lepra; void Init(); void Shutdown(); void SetDefault(cure::RuntimeVariableScope* settings); cure::RuntimeVariableScope* GetSettings(); }

11.411765

54

0.713918

8eb66296b7ebdf7c794bf8be0e7983a9a0cb6042

1,819

h

C

Doom/src/Doom/Components/Transform.h

Shturm0weak/OpenGL_Engine

6e6570f8dd9000724274942fff5a100f0998b780

[ "MIT" ]

126

2020-10-20T21:39:53.000Z

2022-01-25T14:43:44.000Z

Doom/src/Doom/Components/Transform.h

Shturm0weak/2D_OpenGL_Engine

6e6570f8dd9000724274942fff5a100f0998b780

[ "MIT" ]

2

2021-01-07T17:29:19.000Z

2021-08-14T14:04:28.000Z

Doom/src/Doom/Components/Transform.h

Shturm0weak/2D_OpenGL_Engine

6e6570f8dd9000724274942fff5a100f0998b780

[ "MIT" ]

16

2021-01-09T09:08:40.000Z

2022-01-25T14:43:46.000Z

#pragma once #include "../ECS/Component.h" namespace Doom { class Irenderer; class RectangleCollider2D; class DOOM_API Transform : public Component { private: glm::mat4 m_ScaleMat4 = glm::mat4(1.f); glm::mat4 m_PosMat4 = glm::mat4(1.f); glm::mat4 m_ViewMat4 = glm::mat4(1.f); glm::vec3 m_Rotation = glm::vec3(0.0); glm::vec3 m_PrevPosition; void Copy(const Transform& rhs); friend class ComponentManager; friend class RectangleCollider2D; friend class DirectionalLight; friend class Renderer3D; friend class SpriteRenderer; friend class Instancing; friend class Batch; friend class Editor; friend class CubeCollider3D; friend class Renderer; friend class Ray3D; friend class GameObject; friend class SphereCollider; friend class World; friend class ViewPort; public: glm::mat4 GetTransform(); glm::vec3 GetRotation(); glm::vec3 GetPosition(); glm::vec3 GetScale(); Transform(const Transform& rhs); Transform(){} Transform(GameObject* owner); ~Transform() {} void operator=(const Transform& rhs); static Component* Create(); void Move(glm::vec3 dir = glm::vec3(0.0f)); void Rotate(glm::vec3 angles = glm::vec3(0.0f), bool isRad = false); void Scale(glm::vec3 scale = glm::vec3(1.0f)); void Translate(glm::vec3 pos = glm::vec3(0.0f)); void RotateOnce(glm::vec3 angles = glm::vec3(0.0f), bool isRad = false); void RotateOnce(glm::vec3 direction, glm::vec3 axis); void Move(float x = 0.0f, float y = 0.0f, float z = 0.0f); void Rotate(float x = 0.0f, float y = 0.0f, float z = 0.0f, bool isRad = false); void Scale(float x = 0.0f, float y = 0.0f, float z = 0.0f); void Translate(float x = 0.0f, float y = 0.0f, float z = 0.0f); void RotateOnce(float x = 0.0f, float y = 0.0f, float z = 0.0f, bool isRad = false); }; }

26.75

86

0.682793

e6fbafeb245d9dc2814a24000dd893b7aeaf905c

5,066

h

C

include/dx_azure_iot.h

bawilless/AzureSphereDevX

fc91b4313a025c0d2056f9dc1c4bcbf9788538b1

[ "MIT" ]

5

2021-09-03T10:21:01.000Z

2022-01-20T18:21:29.000Z

include/dx_azure_iot.h

bawilless/AzureSphereDevX

fc91b4313a025c0d2056f9dc1c4bcbf9788538b1

[ "MIT" ]

8

2021-06-30T18:58:31.000Z

2021-08-24T23:35:32.000Z

include/dx_azure_iot.h

bawilless/AzureSphereDevX

fc91b4313a025c0d2056f9dc1c4bcbf9788538b1

[ "MIT" ]

4

2021-12-16T05:01:58.000Z

2022-02-03T10:50:02.000Z

/* Copyright (c) Microsoft Corporation. All rights reserved. Licensed under the MIT License. */ #pragma once #include "azure_prov_client/prov_client_const.h" #include "azure_prov_client/prov_device_ll_client.h" #include "azure_prov_client/prov_security_factory.h" #include "azure_prov_client/prov_transport.h" #include "azure_prov_client/prov_transport_mqtt_client.h" #include "dx_config.h" #include "dx_device_twins.h" #include "dx_direct_methods.h" #include "dx_terminate.h" #include "dx_timer.h" #include "dx_utilities.h" #include "dx_avnet_iot_connect.h" #include "iothubtransportmqtt.h" #include <applibs/log.h> #include <azure_prov_client/iothub_security_factory.h> #include <azure_sphere_provisioning.h> #include <errno.h> #include <iothub_client_options.h> #include <iothub_device_client_ll.h> #include <iothubtransportmqtt.h> #include <stdio.h> #include <stdlib.h> #include <time.h> #include "iothub_client_core_common.h" #ifndef IOT_HUB_POLL_TIME_SECONDS #define IOT_HUB_POLL_TIME_SECONDS 0 #endif #ifndef IOT_HUB_POLL_TIME_NANOSECONDS #define IOT_HUB_POLL_TIME_NANOSECONDS 100000000 #endif typedef struct DX_MESSAGE_PROPERTY { const char *key; const char *value; } DX_MESSAGE_PROPERTY; typedef struct DX_MESSAGE_CONTENT_PROPERTIES { const char *contentEncoding; const char *contentType; } DX_MESSAGE_CONTENT_PROPERTIES; /// <summary> /// Check if there is a network connection and an authenticated connection to Azure IoT Hub/Central /// </summary> /// <param name=""></param> /// <returns></returns> bool dx_isAzureConnected(void); /// <summary> /// Send message to Azure IoT Hub/Central with application and content properties. /// Application and content properties can be NULL if not required. /// </summary> /// <param name="msg"></param> /// <param name="messageProperties"></param> /// <param name="messagePropertyCount"></param> /// <param name="messageContentProperties"></param> /// <returns></returns> bool dx_azurePublish(const void *message, size_t messageLength, DX_MESSAGE_PROPERTY **messageProperties, size_t messagePropertyCount, DX_MESSAGE_CONTENT_PROPERTIES *messageContentProperties); /// <summary> /// Exposed for Device Twins. Not for general use. /// </summary> /// <param name=""></param> /// <returns></returns> IOTHUB_DEVICE_CLIENT_LL_HANDLE dx_azureClientHandleGet(void); /// <summary> /// Initialise Azure IoT Hub/Connection connection, passing in network interface for connecting testing and IoT Plug and Play model id. /// Cloud to device messages is also enabled. For information on Plug and Play see /// https://docs.microsoft.com/en-us/azure/iot-pnp/overview-iot-plug-and-play /// </summary> /// <param name="dx_config"></param> /// <param name="networkInterface"></param> /// <param name="plugAndPlayModelId"></param> void dx_azureConnect(DX_USER_CONFIG *userConfig, const char *networkInterface, const char *plugAndPlayModelId); /// <summary> /// Stop Cloud to device messaging. Device twins and direct method messages will not be recieved or processed. /// </summary> /// <param name=""></param> void dx_azureToDeviceStop(void); /// <summary> /// Register for new message recieved from Azure IoT /// </summary> /// <param name="messageReceivedCallback"></param> void dx_azureRegisterMessageReceivedNotification(IOTHUBMESSAGE_DISPOSITION_RESULT (*messageReceivedCallback)(IOTHUB_MESSAGE_HANDLE message, void *context)); /// <summary> /// Register to be notified of change in Azure IoT Connection status /// Up to 5 callbacks can be registered /// </summary> /// <param name="connectionStatusCallback"></param> /// <returns></returns> bool dx_azureRegisterConnectionChangedNotification(void (*connectionStatusCallback)(bool connected)); /// <summary> /// Unregister a callback to be notified of change in Azure IoT Connection status /// </summary> /// <param name="connectionStatusCallback"></param> void dx_azureUnregisterConnectionChangedNotification(void (*connectionStatusCallback)(bool connected)); /// <summary> /// Register Device Twin callback to process an Azure IoT device twin message /// </summary> /// <param name="deviceTwinCallbackHandler"></param> void dx_azureRegisterDeviceTwinCallback(void (*deviceTwinCallbackHandler)(DEVICE_TWIN_UPDATE_STATE updateState, const unsigned char *payload, size_t payloadSize, void *userContextCallback)); /// <summary> /// Register Direct Method callback to process an Azure IoT direct method message /// </summary> /// <param name="directMethodCallbackHandler"></param> void dx_azureRegisterDirectMethodCallback(int (*directMethodCallbackHandler)(const char *method_name, const unsigned char *payload, size_t payloadSize, unsigned char **responsePayload, size_t *responsePayloadSize, void *userContextCallback));

40.528

156

0.726017

fc282bea3da8b7681c2bf31deee672fe98217c14

2,879

h

C

src/ui/GuiData.h

halfmvsq/antropy

41e6f485a3914bae6a5ad90d60578b028b573d01

[ "Apache-2.0" ]

null

src/ui/GuiData.h

halfmvsq/antropy

41e6f485a3914bae6a5ad90d60578b028b573d01

[ "Apache-2.0" ]

null

src/ui/GuiData.h

halfmvsq/antropy

41e6f485a3914bae6a5ad90d60578b028b573d01

[ "Apache-2.0" ]

null

#ifndef GUI_DATA_H #define GUI_DATA_H #include <glm/vec2.hpp> #include <imgui/imgui.h> #include <uuid.h> #include <string> #include <unordered_map> /** * @brief Data for the user interface */ struct GuiData { /// Global setting to turn on/off rendering of the UI windows bool m_renderUiWindows = false; /// Global setting to turn on/off rendering of the UI overlays (crosshairs, anatomical labels) bool m_renderUiOverlays = false; // Flags to show specific UI windows bool m_showImagePropertiesWindow = true; //!< Show image properties window bool m_showSegmentationsWindow = false; //!< Show segmentations window bool m_showLandmarksWindow = false; //!< Show landmarks window bool m_showAnnotationsWindow = false; //!< Show annotations window bool m_showSettingsWindow = false; //!< Show settings window bool m_showInspectionWindow = true; //!< Show cursor inspection window bool m_showOpacityBlenderWindow = false; //!< Show opacity blender window bool m_showDemoWindow = false; //!< Show ImGui demo window /// Map of imageUid to boolean of whether its image color map window is shown. /// (The color map window is shown as a popup from the Image Properties window) std::unordered_map< uuids::uuid, bool > m_showImageColormapWindow; // Show the color map windows for the difference, cross-correlation, and histogram metric views bool m_showDifferenceColormapWindow = false; //!< Show difference colormap window bool m_showCorrelationColormapWindow = false; //!< Show correlation colormap window bool m_showJointHistogramColormapWindow = false; //!< Show joint histogram colormap window void setCoordsPrecisionFormat(); void setTxPrecisionFormat(); /// Precision format string used for spatial coordinates std::string m_coordsPrecisionFormat = "%0.3f"; uint32_t m_coordsPrecision = 3; /// Precision format string used for image transformations std::string m_txPrecisionFormat = "%0.3f"; uint32_t m_txPrecision = 3; /// Precision format string used for image values std::string m_imageValuePrecisionFormat = "%0.3f"; uint32_t m_imageValuePrecision = 3; // Pointers to fonts allocated by ImGui ImFont* m_cousineFont = nullptr; //!< Main ImGui font ImFont* m_forkAwesomeFont = nullptr; //!< Icons font // Font data, using raw pointers used because ImGui takes ownership and deletes them. char* m_cousineFontData = nullptr; char* m_forkAwesomeFontData = nullptr; bool m_showMainMenuBar = true; glm::vec2 m_mainMenuBarDims{ 0.0f, 0.0f }; bool m_showModeToolbar = true; bool m_isModeToolbarHorizontal = false; int m_modeToolbarCorner = 1; glm::vec2 m_modeToolbarDockDims{ 0.0f, 0.0f }; // Corners: -1 custom, 0 top-left, 1 top-right, 2 bottom-left, 3 bottom-right }; #endif // GUI_DATA_H

37.38961

99

0.724904

112ea8b2299ca723f366a7847a94cfaf40e32c9a

29,890

c

C

openswan/openswan-2.4.0rc4.quilt/linux/net/ipsec/ipsec_mast.c

nakedible/vpnease-l2tp

0fcda6a757f2bc5c37f4753b3cd8b1c6d282db5c

[ "WTFPL" ]

5

2015-04-16T08:36:17.000Z

2017-05-12T17:20:12.000Z

openswan/openswan-2.4.0rc4.quilt/linux/net/ipsec/ipsec_mast.c

nakedible/vpnease-l2tp

0fcda6a757f2bc5c37f4753b3cd8b1c6d282db5c

[ "WTFPL" ]

null

openswan/openswan-2.4.0rc4.quilt/linux/net/ipsec/ipsec_mast.c

nakedible/vpnease-l2tp

0fcda6a757f2bc5c37f4753b3cd8b1c6d282db5c

[ "WTFPL" ]

4

2015-03-19T14:39:51.000Z

2019-01-23T08:22:55.000Z

/* * IPSEC MAST code. * Copyright (C) 1996, 1997 John Ioannidis. * Copyright (C) 1998, 1999, 2000, 2001, 2002 Richard Guy Briggs. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. See <http://www.fsf.org/copyleft/gpl.txt>. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. */ char ipsec_mast_c_version[] = "RCSID $Id: ipsec_mast.c,v 1.7 2005/04/29 05:10:22 mcr Exp $"; #define __NO_VERSION__ #include <linux/module.h> #include <linux/config.h> /* for CONFIG_IP_FORWARD */ #include <linux/version.h> #include <linux/kernel.h> /* printk() */ #include "freeswan/ipsec_param.h" #ifdef MALLOC_SLAB # include <linux/slab.h> /* kmalloc() */ #else /* MALLOC_SLAB */ # include <linux/malloc.h> /* kmalloc() */ #endif /* MALLOC_SLAB */ #include <linux/errno.h> /* error codes */ #include <linux/types.h> /* size_t */ #include <linux/interrupt.h> /* mark_bh */ #include <linux/netdevice.h> /* struct device, struct net_device_stats, dev_queue_xmit() and other headers */ #include <linux/etherdevice.h> /* eth_type_trans */ #include <linux/ip.h> /* struct iphdr */ #include <linux/tcp.h> /* struct tcphdr */ #include <linux/udp.h> /* struct udphdr */ #include <linux/skbuff.h> #include <freeswan.h> #include <linux/in6.h> #include <net/dst.h> #undef dev_kfree_skb #define dev_kfree_skb(a,b) kfree_skb(a) #define PHYSDEV_TYPE #include <net/icmp.h> /* icmp_send() */ #include <net/ip.h> #include <linux/netfilter_ipv4.h> #include <linux/if_arp.h> #include "freeswan/radij.h" #include "freeswan/ipsec_life.h" #include "freeswan/ipsec_xform.h" #include "freeswan/ipsec_eroute.h" #include "freeswan/ipsec_encap.h" #include "freeswan/ipsec_radij.h" #include "freeswan/ipsec_sa.h" #include "freeswan/ipsec_tunnel.h" #include "freeswan/ipsec_mast.h" #include "freeswan/ipsec_ipe4.h" #include "freeswan/ipsec_ah.h" #include "freeswan/ipsec_esp.h" #include <pfkeyv2.h> #include <pfkey.h> #include "freeswan/ipsec_proto.h" int ipsec_maxdevice_count = -1; DEBUG_NO_STATIC int ipsec_mast_open(struct net_device *dev) { struct ipsecpriv *prv = dev->priv; /* * Can't open until attached. */ KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_open: " "dev = %s, prv->dev = %s\n", dev->name, prv->dev?prv->dev->name:"NONE"); if (prv->dev == NULL) return -ENODEV; KLIPS_INC_USE; return 0; } DEBUG_NO_STATIC int ipsec_mast_close(struct net_device *dev) { KLIPS_DEC_USE; return 0; } static inline int ipsec_mast_xmit2(struct sk_buff *skb) { return ip_send(skb); } enum ipsec_xmit_value ipsec_mast_send(struct ipsec_xmit_state*ixs) { /* new route/dst cache code from James Morris */ ixs->skb->dev = ixs->physdev; /*skb_orphan(ixs->skb);*/ if((ixs->error = ip_route_output(&ixs->route, ixs->skb->nh.iph->daddr, ixs->pass ? 0 : ixs->skb->nh.iph->saddr, RT_TOS(ixs->skb->nh.iph->tos), ixs->physdev->iflink /* rgb: should this be 0? */))) { ixs->stats->tx_errors++; KLIPS_PRINT(debug_mast & DB_MAST_XMIT, "klips_debug:ipsec_xmit_send: " "ip_route_output failed with error code %d, rt->u.dst.dev=%s, dropped\n", ixs->error, ixs->route->u.dst.dev->name); return IPSEC_XMIT_ROUTEERR; } if(ixs->dev == ixs->route->u.dst.dev) { ip_rt_put(ixs->route); /* This is recursion, drop it. */ ixs->stats->tx_errors++; KLIPS_PRINT(debug_mast & DB_MAST_XMIT, "klips_debug:ipsec_xmit_send: " "suspect recursion, dev=rt->u.dst.dev=%s, dropped\n", ixs->dev->name); return IPSEC_XMIT_RECURSDETECT; } dst_release(ixs->skb->dst); ixs->skb->dst = &ixs->route->u.dst; ixs->stats->tx_bytes += ixs->skb->len; if(ixs->skb->len < ixs->skb->nh.raw - ixs->skb->data) { ixs->stats->tx_errors++; printk(KERN_WARNING "klips_error:ipsec_xmit_send: " "tried to __skb_pull nh-data=%ld, %d available. This should never happen, please report.\n", (unsigned long)(ixs->skb->nh.raw - ixs->skb->data), ixs->skb->len); return IPSEC_XMIT_PUSHPULLERR; } __skb_pull(ixs->skb, ixs->skb->nh.raw - ixs->skb->data); #ifdef SKB_RESET_NFCT nf_conntrack_put(ixs->skb->nfct); ixs->skb->nfct = NULL; #ifdef CONFIG_NETFILTER_DEBUG ixs->skb->nf_debug = 0; #endif /* CONFIG_NETFILTER_DEBUG */ #endif /* SKB_RESET_NFCT */ KLIPS_PRINT(debug_mast & DB_MAST_XMIT, "klips_debug:ipsec_xmit_send: " "...done, calling ip_send() on device:%s\n", ixs->skb->dev ? ixs->skb->dev->name : "NULL"); KLIPS_IP_PRINT(debug_mast & DB_MAST_XMIT, ixs->skb->nh.iph); { int err; err = NF_HOOK(PF_INET, NF_IP_LOCAL_OUT, ixs->skb, NULL, ixs->route->u.dst.dev, ipsec_mast_xmit2); if(err != NET_XMIT_SUCCESS && err != NET_XMIT_CN) { if(net_ratelimit()) printk(KERN_ERR "klips_error:ipsec_xmit_send: " "ip_send() failed, err=%d\n", -err); ixs->stats->tx_errors++; ixs->stats->tx_aborted_errors++; ixs->skb = NULL; return IPSEC_XMIT_IPSENDFAILURE; } } ixs->stats->tx_packets++; ixs->skb = NULL; return IPSEC_XMIT_OK; } void ipsec_mast_cleanup(struct ipsec_xmit_state*ixs) { #if defined(HAS_NETIF_QUEUE) || defined (HAVE_NETIF_QUEUE) netif_wake_queue(ixs->dev); #else /* defined(HAS_NETIF_QUEUE) || defined (HAVE_NETIF_QUEUE) */ ixs->dev->tbusy = 0; #endif /* defined(HAS_NETIF_QUEUE) || defined (HAVE_NETIF_QUEUE) */ if(ixs->saved_header) { kfree(ixs->saved_header); } if(ixs->skb) { dev_kfree_skb(ixs->skb, FREE_WRITE); } if(ixs->oskb) { dev_kfree_skb(ixs->oskb, FREE_WRITE); } if (ixs->ips.ips_ident_s.data) { kfree(ixs->ips.ips_ident_s.data); } if (ixs->ips.ips_ident_d.data) { kfree(ixs->ips.ips_ident_d.data); } } #if 0 /* * This function assumes it is being called from dev_queue_xmit() * and that skb is filled properly by that function. */ int ipsec_mast_start_xmit(struct sk_buff *skb, struct net_device *dev, IPsecSAref_t SAref) { struct ipsec_xmit_state ixs_mem; struct ipsec_xmit_state *ixs = &ixs_mem; enum ipsec_xmit_value stat = IPSEC_XMIT_OK; /* dev could be a mast device, but should be optional, I think... */ /* SAref is also optional, but one of the two must be present. */ /* I wonder if it could accept no device or saref and guess? */ /* ipsec_xmit_sanity_check_dev(ixs); */ ipsec_xmit_sanity_check_skb(ixs); ipsec_xmit_adjust_hard_header(ixs); stat = ipsec_xmit_encap_bundle(ixs); if(stat != IPSEC_XMIT_OK) { /* SA processing failed */ } ipsec_xmit_hard_header_restore(); } #endif DEBUG_NO_STATIC struct net_device_stats * ipsec_mast_get_stats(struct net_device *dev) { return &(((struct ipsecpriv *)(dev->priv))->mystats); } /* * Revectored calls. * For each of these calls, a field exists in our private structure. */ DEBUG_NO_STATIC int ipsec_mast_hard_header(struct sk_buff *skb, struct net_device *dev, unsigned short type, void *daddr, void *saddr, unsigned len) { struct ipsecpriv *prv = dev->priv; struct net_device *tmp; int ret; struct net_device_stats *stats; /* This device's statistics */ if(skb == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_hard_header: " "no skb...\n"); return -ENODATA; } if(dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_hard_header: " "no device...\n"); return -ENODEV; } KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_hard_header: " "skb->dev=%s dev=%s.\n", skb->dev ? skb->dev->name : "NULL", dev->name); if(prv == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_hard_header: " "no private space associated with dev=%s\n", dev->name ? dev->name : "NULL"); return -ENODEV; } stats = (struct net_device_stats *) &(prv->mystats); if(prv->dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_hard_header: " "no physical device associated with dev=%s\n", dev->name ? dev->name : "NULL"); stats->tx_dropped++; return -ENODEV; } /* check if we have to send a IPv6 packet. It might be a Router Solicitation, where the building of the packet happens in reverse order: 1. ll hdr, 2. IPv6 hdr, 3. ICMPv6 hdr -> skb->nh.raw is still uninitialized when this function is called!! If this is no IPv6 packet, we can print debugging messages, otherwise we skip all debugging messages and just build the ll header */ if(type != ETH_P_IPV6) { /* execute this only, if we don't have to build the header for a IPv6 packet */ if(!prv->hard_header) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_hard_header: " "physical device has been detached, packet dropped 0p%p->0p%p len=%d type=%d dev=%s->NULL ", saddr, daddr, len, type, dev->name); KLIPS_PRINTMORE(debug_mast & DB_MAST_REVEC, "ip=%08x->%08x\n", (__u32)ntohl(skb->nh.iph->saddr), (__u32)ntohl(skb->nh.iph->daddr) ); stats->tx_dropped++; return -ENODEV; } #define da ((struct net_device *)(prv->dev))->dev_addr KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_hard_header: " "Revectored 0p%p->0p%p len=%d type=%d dev=%s->%s dev_addr=%02x:%02x:%02x:%02x:%02x:%02x ", saddr, daddr, len, type, dev->name, prv->dev->name, da[0], da[1], da[2], da[3], da[4], da[5]); KLIPS_PRINTMORE(debug_mast & DB_MAST_REVEC, "ip=%08x->%08x\n", (__u32)ntohl(skb->nh.iph->saddr), (__u32)ntohl(skb->nh.iph->daddr) ); } else { KLIPS_PRINT(debug_mast, "klips_debug:ipsec_mast_hard_header: " "is IPv6 packet, skip debugging messages, only revector and build linklocal header.\n"); } tmp = skb->dev; skb->dev = prv->dev; ret = prv->hard_header(skb, prv->dev, type, (void *)daddr, (void *)saddr, len); skb->dev = tmp; return ret; } DEBUG_NO_STATIC int ipsec_mast_rebuild_header(struct sk_buff *skb) { struct ipsecpriv *prv = skb->dev->priv; struct net_device *tmp; int ret; struct net_device_stats *stats; /* This device's statistics */ if(skb->dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_rebuild_header: " "no device..."); return -ENODEV; } if(prv == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_rebuild_header: " "no private space associated with dev=%s", skb->dev->name ? skb->dev->name : "NULL"); return -ENODEV; } stats = (struct net_device_stats *) &(prv->mystats); if(prv->dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_rebuild_header: " "no physical device associated with dev=%s", skb->dev->name ? skb->dev->name : "NULL"); stats->tx_dropped++; return -ENODEV; } if(!prv->rebuild_header) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_rebuild_header: " "physical device has been detached, packet dropped skb->dev=%s->NULL ", skb->dev->name); KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "ip=%08x->%08x\n", (__u32)ntohl(skb->nh.iph->saddr), (__u32)ntohl(skb->nh.iph->daddr) ); stats->tx_dropped++; return -ENODEV; } KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast: " "Revectored rebuild_header dev=%s->%s ", skb->dev->name, prv->dev->name); KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "ip=%08x->%08x\n", (__u32)ntohl(skb->nh.iph->saddr), (__u32)ntohl(skb->nh.iph->daddr) ); tmp = skb->dev; skb->dev = prv->dev; ret = prv->rebuild_header(skb); skb->dev = tmp; return ret; } DEBUG_NO_STATIC int ipsec_mast_set_mac_address(struct net_device *dev, void *addr) { struct ipsecpriv *prv = dev->priv; struct net_device_stats *stats; /* This device's statistics */ if(dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_set_mac_address: " "no device..."); return -ENODEV; } if(prv == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_set_mac_address: " "no private space associated with dev=%s", dev->name ? dev->name : "NULL"); return -ENODEV; } stats = (struct net_device_stats *) &(prv->mystats); if(prv->dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_set_mac_address: " "no physical device associated with dev=%s", dev->name ? dev->name : "NULL"); stats->tx_dropped++; return -ENODEV; } if(!prv->set_mac_address) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_set_mac_address: " "physical device has been detached, cannot set - skb->dev=%s->NULL\n", dev->name); return -ENODEV; } KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_set_mac_address: " "Revectored dev=%s->%s addr=0p%p\n", dev->name, prv->dev->name, addr); return prv->set_mac_address(prv->dev, addr); } DEBUG_NO_STATIC void ipsec_mast_cache_update(struct hh_cache *hh, struct net_device *dev, unsigned char * haddr) { struct ipsecpriv *prv = dev->priv; struct net_device_stats *stats; /* This device's statistics */ if(dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_cache_update: " "no device..."); return; } if(prv == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_cache_update: " "no private space associated with dev=%s", dev->name ? dev->name : "NULL"); return; } stats = (struct net_device_stats *) &(prv->mystats); if(prv->dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_cache_update: " "no physical device associated with dev=%s", dev->name ? dev->name : "NULL"); stats->tx_dropped++; return; } if(!prv->header_cache_update) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_cache_update: " "physical device has been detached, cannot set - skb->dev=%s->NULL\n", dev->name); return; } KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast: " "Revectored cache_update\n"); prv->header_cache_update(hh, prv->dev, haddr); return; } DEBUG_NO_STATIC int ipsec_mast_neigh_setup(struct neighbour *n) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_neigh_setup:\n"); if (n->nud_state == NUD_NONE) { n->ops = &arp_broken_ops; n->output = n->ops->output; } return 0; } DEBUG_NO_STATIC int ipsec_mast_neigh_setup_dev(struct net_device *dev, struct neigh_parms *p) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_neigh_setup_dev: " "setting up %s\n", dev ? dev->name : "NULL"); if (p->tbl->family == AF_INET) { p->neigh_setup = ipsec_mast_neigh_setup; p->ucast_probes = 0; p->mcast_probes = 0; } return 0; } /* * We call the attach routine to attach another device. */ DEBUG_NO_STATIC int ipsec_mast_attach(struct net_device *dev, struct net_device *physdev) { int i; struct ipsecpriv *prv = dev->priv; if(dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_attach: " "no device..."); return -ENODEV; } if(prv == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_attach: " "no private space associated with dev=%s", dev->name ? dev->name : "NULL"); return -ENODATA; } prv->dev = physdev; prv->hard_start_xmit = physdev->hard_start_xmit; prv->get_stats = physdev->get_stats; if (physdev->hard_header) { prv->hard_header = physdev->hard_header; dev->hard_header = ipsec_mast_hard_header; } else dev->hard_header = NULL; if (physdev->rebuild_header) { prv->rebuild_header = physdev->rebuild_header; dev->rebuild_header = ipsec_mast_rebuild_header; } else dev->rebuild_header = NULL; if (physdev->set_mac_address) { prv->set_mac_address = physdev->set_mac_address; dev->set_mac_address = ipsec_mast_set_mac_address; } else dev->set_mac_address = NULL; if (physdev->header_cache_update) { prv->header_cache_update = physdev->header_cache_update; dev->header_cache_update = ipsec_mast_cache_update; } else dev->header_cache_update = NULL; dev->hard_header_len = physdev->hard_header_len; /* prv->neigh_setup = physdev->neigh_setup; */ dev->neigh_setup = ipsec_mast_neigh_setup_dev; dev->mtu = 16260; /* 0xfff0; */ /* dev->mtu; */ prv->mtu = physdev->mtu; #ifdef PHYSDEV_TYPE dev->type = physdev->type; /* ARPHRD_MAST; */ #endif /* PHYSDEV_TYPE */ dev->addr_len = physdev->addr_len; for (i=0; i<dev->addr_len; i++) { dev->dev_addr[i] = physdev->dev_addr[i]; } #ifdef CONFIG_KLIPS_DEBUG if(debug_mast & DB_MAST_INIT) { printk(KERN_INFO "klips_debug:ipsec_mast_attach: " "physical device %s being attached has HW address: %2x", physdev->name, physdev->dev_addr[0]); for (i=1; i < physdev->addr_len; i++) { printk(":%02x", physdev->dev_addr[i]); } printk("\n"); } #endif /* CONFIG_KLIPS_DEBUG */ return 0; } /* * We call the detach routine to detach the ipsec mast from another device. */ DEBUG_NO_STATIC int ipsec_mast_detach(struct net_device *dev) { int i; struct ipsecpriv *prv = dev->priv; if(dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_detach: " "no device..."); return -ENODEV; } if(prv == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_REVEC, "klips_debug:ipsec_mast_detach: " "no private space associated with dev=%s", dev->name ? dev->name : "NULL"); return -ENODATA; } KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_detach: " "physical device %s being detached from virtual device %s\n", prv->dev ? prv->dev->name : "NULL", dev->name); prv->dev = NULL; prv->hard_start_xmit = NULL; prv->get_stats = NULL; prv->hard_header = NULL; #ifdef DETACH_AND_DOWN dev->hard_header = NULL; #endif /* DETACH_AND_DOWN */ prv->rebuild_header = NULL; #ifdef DETACH_AND_DOWN dev->rebuild_header = NULL; #endif /* DETACH_AND_DOWN */ prv->set_mac_address = NULL; #ifdef DETACH_AND_DOWN dev->set_mac_address = NULL; #endif /* DETACH_AND_DOWN */ prv->header_cache_update = NULL; #ifdef DETACH_AND_DOWN dev->header_cache_update = NULL; #endif /* DETACH_AND_DOWN */ #ifdef DETACH_AND_DOWN dev->neigh_setup = NULL; #endif /* DETACH_AND_DOWN */ dev->hard_header_len = 0; #ifdef DETACH_AND_DOWN dev->mtu = 0; #endif /* DETACH_AND_DOWN */ prv->mtu = 0; for (i=0; i<MAX_ADDR_LEN; i++) { dev->dev_addr[i] = 0; } dev->addr_len = 0; #ifdef PHYSDEV_TYPE dev->type = ARPHRD_VOID; /* ARPHRD_MAST; */ #endif /* PHYSDEV_TYPE */ return 0; } /* * We call the clear routine to detach all ipsec masts from other devices. */ DEBUG_NO_STATIC int ipsec_mast_clear(void) { int i; struct net_device *ipsecdev = NULL, *prvdev; struct ipsecpriv *prv; char name[9]; int ret; KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_clear: .\n"); for(i = 0; i < IPSEC_NUM_IF; i++) { sprintf(name, IPSEC_DEV_FORMAT, i); if((ipsecdev = ipsec_dev_get(name)) != NULL) { if((prv = (struct ipsecpriv *)(ipsecdev->priv))) { prvdev = (struct net_device *)(prv->dev); if(prvdev) { KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_clear: " "physical device for device %s is %s\n", name, prvdev->name); if((ret = ipsec_mast_detach(ipsecdev))) { KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_clear: " "error %d detatching device %s from device %s.\n", ret, name, prvdev->name); return ret; } } } } } return 0; } DEBUG_NO_STATIC int ipsec_mast_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { struct ipsecmastconf *cf = (struct ipsecmastconf *)&ifr->ifr_data; struct ipsecpriv *prv = dev->priv; struct net_device *them; /* physical device */ #ifdef CONFIG_IP_ALIAS char *colon; char realphysname[IFNAMSIZ]; #endif /* CONFIG_IP_ALIAS */ if(dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_ioctl: " "device not supplied.\n"); return -ENODEV; } KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_ioctl: " "tncfg service call #%d for dev=%s\n", cmd, dev->name ? dev->name : "NULL"); switch (cmd) { /* attach a virtual ipsec? device to a physical device */ case IPSEC_SET_DEV: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_ioctl: " "calling ipsec_mast_attatch...\n"); #ifdef CONFIG_IP_ALIAS /* If this is an IP alias interface, get its real physical name */ strncpy(realphysname, cf->cf_name, IFNAMSIZ); realphysname[IFNAMSIZ-1] = 0; colon = strchr(realphysname, ':'); if (colon) *colon = 0; them = ipsec_dev_get(realphysname); #else /* CONFIG_IP_ALIAS */ them = ipsec_dev_get(cf->cf_name); #endif /* CONFIG_IP_ALIAS */ if (them == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_ioctl: " "physical device %s requested is null\n", cf->cf_name); return -ENXIO; } #if 0 if (them->flags & IFF_UP) { KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_ioctl: " "physical device %s requested is not up.\n", cf->cf_name); return -ENXIO; } #endif if (prv && prv->dev) { KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_ioctl: " "virtual device is already connected to %s.\n", prv->dev->name ? prv->dev->name : "NULL"); return -EBUSY; } return ipsec_mast_attach(dev, them); case IPSEC_DEL_DEV: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_ioctl: " "calling ipsec_mast_detatch.\n"); if (! prv->dev) { KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_ioctl: " "physical device not connected.\n"); return -ENODEV; } return ipsec_mast_detach(dev); case IPSEC_CLR_DEV: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_ioctl: " "calling ipsec_mast_clear.\n"); return ipsec_mast_clear(); default: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_ioctl: " "unknown command %d.\n", cmd); return -EOPNOTSUPP; } } int ipsec_mast_device_event(struct notifier_block *unused, unsigned long event, void *ptr) { struct net_device *dev = ptr; struct net_device *ipsec_dev; struct ipsecpriv *priv; char name[9]; int i; if (dev == NULL) { KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "dev=NULL for event type %ld.\n", event); return(NOTIFY_DONE); } /* check for loopback devices */ if (dev && (dev->flags & IFF_LOOPBACK)) { return(NOTIFY_DONE); } switch (event) { case NETDEV_DOWN: /* look very carefully at the scope of these compiler directives before changing anything... -- RGB */ case NETDEV_UNREGISTER: switch (event) { case NETDEV_DOWN: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "NETDEV_DOWN dev=%s flags=%x\n", dev->name, dev->flags); if(strncmp(dev->name, "ipsec", strlen("ipsec")) == 0) { printk(KERN_CRIT "IPSEC EVENT: KLIPS device %s shut down.\n", dev->name); } break; case NETDEV_UNREGISTER: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "NETDEV_UNREGISTER dev=%s flags=%x\n", dev->name, dev->flags); break; } /* find the attached physical device and detach it. */ for(i = 0; i < IPSEC_NUM_IF; i++) { sprintf(name, IPSEC_DEV_FORMAT, i); ipsec_dev = ipsec_dev_get(name); if(ipsec_dev) { priv = (struct ipsecpriv *)(ipsec_dev->priv); if(priv) { ; if(((struct net_device *)(priv->dev)) == dev) { /* dev_close(ipsec_dev); */ /* return */ ipsec_mast_detach(ipsec_dev); KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "device '%s' has been detached.\n", ipsec_dev->name); break; } } else { KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "device '%s' has no private data space!\n", ipsec_dev->name); } } } break; case NETDEV_UP: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "NETDEV_UP dev=%s\n", dev->name); break; case NETDEV_REBOOT: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "NETDEV_REBOOT dev=%s\n", dev->name); break; case NETDEV_CHANGE: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "NETDEV_CHANGE dev=%s flags=%x\n", dev->name, dev->flags); break; case NETDEV_REGISTER: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "NETDEV_REGISTER dev=%s\n", dev->name); break; case NETDEV_CHANGEMTU: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "NETDEV_CHANGEMTU dev=%s to mtu=%d\n", dev->name, dev->mtu); break; case NETDEV_CHANGEADDR: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "NETDEV_CHANGEADDR dev=%s\n", dev->name); break; case NETDEV_GOING_DOWN: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "NETDEV_GOING_DOWN dev=%s\n", dev->name); break; case NETDEV_CHANGENAME: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "NETDEV_CHANGENAME dev=%s\n", dev->name); break; default: KLIPS_PRINT(debug_mast & DB_MAST_INIT, "klips_debug:ipsec_mast_device_event: " "event type %ld unrecognised for dev=%s\n", event, dev->name); break; } return NOTIFY_DONE; } /* * Called when an ipsec mast device is initialized. * The ipsec mast device structure is passed to us. */ int ipsec_mast_init(struct net_device *dev) { int i; KLIPS_PRINT(debug_mast, "klips_debug:ipsec_mast_init: " "allocating %lu bytes initialising device: %s\n", (unsigned long) sizeof(struct ipsecpriv), dev->name ? dev->name : "NULL"); /* Add our mast functions to the device */ dev->open = ipsec_mast_open; dev->stop = ipsec_mast_close; dev->hard_start_xmit = ipsec_mast_start_xmit; dev->get_stats = ipsec_mast_get_stats; dev->priv = kmalloc(sizeof(struct ipsecpriv), GFP_KERNEL); if (dev->priv == NULL) return -ENOMEM; memset((caddr_t)(dev->priv), 0, sizeof(struct ipsecpriv)); for(i = 0; i < sizeof(zeroes); i++) { ((__u8*)(zeroes))[i] = 0; } dev->set_multicast_list = NULL; dev->do_ioctl = ipsec_mast_ioctl; dev->hard_header = NULL; dev->rebuild_header = NULL; dev->set_mac_address = NULL; dev->header_cache_update= NULL; dev->neigh_setup = ipsec_mast_neigh_setup_dev; dev->hard_header_len = 0; dev->mtu = 0; dev->addr_len = 0; dev->type = ARPHRD_VOID; /* ARPHRD_MAST; */ /* ARPHRD_ETHER; */ dev->tx_queue_len = 10; /* Small queue */ memset((caddr_t)(dev->broadcast),0xFF, ETH_ALEN); /* what if this is not attached to ethernet? */ /* New-style flags. */ dev->flags = IFF_NOARP /* 0 */ /* Petr Novak */; dev_init_buffers(dev); /* We're done. Have I forgotten anything? */ return 0; } /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ /* Module specific interface (but it links with the rest of IPSEC) */ /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ int ipsec_mast_probe(struct net_device *dev) { ipsec_mast_init(dev); return 0; } int ipsec_mast_init_devices(void) { return 0; } /* void */ int ipsec_mast_cleanup_devices(void) { int error = 0; int i; char name[10]; struct net_device *dev_mast; for(i = 0; i < ipsec_mastdevice_count; i++) { sprintf(name, MAST_DEV_FORMAT, i); if((dev_mast = ipsec_dev_get(name)) == NULL) { break; } unregister_netdev(dev_mast); kfree(dev_mast->priv); dev_mast->priv=NULL; } return error; } /* * $Log: ipsec_mast.c,v $ * Revision 1.7 2005/04/29 05:10:22 mcr * removed from extraenous includes to make unit testing easier. * * Revision 1.6 2004/12/03 21:25:57 mcr * compile time fixes for running on 2.6. * still experimental. * * Revision 1.5 2004/08/03 18:19:08 mcr * in 2.6, use "net_device" instead of #define device->net_device. * this probably breaks 2.0 compiles. * * Revision 1.4 2004/07/10 19:11:18 mcr * CONFIG_IPSEC -> CONFIG_KLIPS. * * Revision 1.3 2003/10/31 02:27:55 mcr * pulled up port-selector patches and sa_id elimination. * * Revision 1.2.4.1 2003/10/29 01:30:41 mcr * elimited "struct sa_id". * * Revision 1.2 2003/06/22 20:06:17 mcr * refactored mast code still had lots of ipsecX junk in it. * * Revision 1.1 2003/02/12 19:31:12 rgb * Refactored from ipsec_tunnel.c * */

27.346752

111

0.657477

52fe825e6bf3db222d4ddeff51ad63201cff194d

7,976

c

C

src/mpid/dcmfd/src/misc/mpix.c

grondo/mvapich2-cce

ec084d8e07db1cf2ac1352ee4c604ae7dbae55cb

[ "Intel", "mpich2", "Unlicense" ]

1

2021-11-11T15:42:30.000Z

src/mpid/dcmfd/src/misc/mpix.c

grondo/mvapich2-cce

ec084d8e07db1cf2ac1352ee4c604ae7dbae55cb

[ "Intel", "mpich2", "Unlicense" ]

null

src/mpid/dcmfd/src/misc/mpix.c

grondo/mvapich2-cce

ec084d8e07db1cf2ac1352ee4c604ae7dbae55cb

[ "Intel", "mpich2", "Unlicense" ]

null

/* (C)Copyright IBM Corp. 2007, 2008 */ /** * \file src/misc/mpix.c * \brief Blue Gene extensions to the MPI Spec */ #include "mpidimpl.h" #include "mpix.h" #pragma weak PMI_torus2rank = MPIX_torus2rank unsigned MPIX_torus2rank (unsigned x, unsigned y, unsigned z, unsigned t) { size_t rank; DCMF_Network network = DCMF_TORUS_NETWORK; DCMF_NetworkCoord_t addr; addr.network = DCMF_TORUS_NETWORK; addr.torus.x = x; addr.torus.y = y; addr.torus.z = z; addr.torus.t = t; if (DCMF_Messager_network2rank(&addr, &rank, &network) == DCMF_SUCCESS) return rank; return (unsigned) -1; } #pragma weak PMI_Comm_torus2rank = MPIX_Comm_torus2rank unsigned MPIX_Comm_torus2rank (MPI_Comm comm, unsigned x, unsigned y, unsigned z, unsigned t) { int rank, worldrank = MPIX_torus2rank(x, y, z, t); if (comm == MPI_COMM_WORLD) rank = worldrank; else { MPI_Group group_a, worldgroup; PMPI_Comm_group (comm, &group_a); PMPI_Comm_group (MPI_COMM_WORLD, &worldgroup); PMPI_Group_translate_ranks (worldgroup, 1, &worldrank, group_a, &rank); } return rank; } #pragma weak PMI_rank2torus = MPIX_rank2torus void MPIX_rank2torus (unsigned rank, unsigned *x, unsigned *y, unsigned *z, unsigned *t) { DCMF_NetworkCoord_t addr; if (DCMF_Messager_rank2network(rank, DCMF_DEFAULT_NETWORK, &addr) != DCMF_SUCCESS) abort(); *x = addr.torus.x; *y = addr.torus.y; *z = addr.torus.z; *t = addr.torus.t; } #pragma weak PMI_Comm_rank2torus = MPIX_Comm_rank2torus void MPIX_Comm_rank2torus(MPI_Comm comm, unsigned rank, unsigned *x, unsigned *y, unsigned *z, unsigned *t) { int worldrank; if (comm == MPI_COMM_WORLD) worldrank = rank; else { MPI_Group group_a, worldgroup; PMPI_Comm_group (comm, &group_a); PMPI_Comm_group (MPI_COMM_WORLD, &worldgroup); PMPI_Group_translate_ranks (group_a, 1, (int*)&rank, worldgroup, &worldrank); } MPIX_rank2torus (worldrank, x, y, z, t); } /** * \brief Compare each elemt of two four-element arrays * \param[in] A The first array * \param[in] B The first array * \returns MPI_SUCCESS (does not return on failure) */ #define CMP_4(A,B) \ ({ \ assert(A[0] == B[0]); \ assert(A[1] == B[1]); \ assert(A[2] == B[2]); \ assert(A[3] == B[3]); \ MPI_SUCCESS; \ }) #pragma weak PMI_Cart_comm_create = MPIX_Cart_comm_create int MPIX_Cart_comm_create(MPI_Comm *cart_comm) { int result; int rank, numprocs, dims[4], wrap[4], coords[4]; int new_rank, new_dims[4], new_wrap[4], new_coords[4]; DCMF_Hardware_t pers; *cart_comm = MPI_COMM_NULL; PMPI_Comm_rank(MPI_COMM_WORLD, &rank); PMPI_Comm_size(MPI_COMM_WORLD, &numprocs); DCMF_Hardware(&pers); dims[3] = pers.xSize; dims[2] = pers.ySize; dims[1] = pers.zSize; dims[0] = pers.tSize; /* This only works if MPI_COMM_WORLD is the full partition */ if (dims[3] * dims[2] * dims[1] * dims[0] != numprocs) return MPI_ERR_TOPOLOGY; wrap[3] = pers.xTorus; wrap[2] = pers.yTorus; wrap[1] = pers.zTorus; wrap[0] = pers.tTorus; coords[3] = pers.xCoord; coords[2] = pers.yCoord; coords[1] = pers.zCoord; coords[0] = pers.tCoord; result = PMPI_Cart_create( MPI_COMM_WORLD, 4, dims, wrap, 0, cart_comm ); if (result != MPI_SUCCESS) return result; PMPI_Comm_rank(*cart_comm, &new_rank); PMPI_Cart_get (*cart_comm, 4, new_dims, new_wrap, new_coords); CMP_4(dims, new_dims); CMP_4(wrap, new_wrap); CMP_4(coords, new_coords); return MPI_SUCCESS; } #pragma weak PMI_Pset_same_comm_create = MPIX_Pset_same_comm_create int MPIX_Pset_same_comm_create(MPI_Comm *pset_comm) { int key, color; DCMF_Hardware_t pers; DCMF_Hardware(&pers); /* All items of the same color are grouped in the same communicator */ color = pers.idOfPset; /* The key implies the new rank */ key = pers.rankInPset*pers.tSize + pers.tCoord; return PMPI_Comm_split(MPI_COMM_WORLD, color, key, pset_comm); } #pragma weak PMI_Pset_diff_comm_create = MPIX_Pset_diff_comm_create int MPIX_Pset_diff_comm_create(MPI_Comm *pset_comm) { int key, color; DCMF_Hardware_t pers; DCMF_Hardware(&pers); /* The key implies the new rank */ key = pers.idOfPset; /* All items of the same color are grouped in the same communicator */ color = pers.rankInPset*pers.tSize + pers.tCoord; return PMPI_Comm_split(MPI_COMM_WORLD, color, key, pset_comm); } #pragma weak MPID_Dump_stacks = MPIX_Dump_stacks extern int backtrace(void **buffer, int size); /**< GlibC backtrace support */ extern char **backtrace_symbols(void *const *buffer, int size); /**< GlibC backtrace support */ void MPIX_Dump_stacks() { void *array[32]; size_t i; size_t size = backtrace(array, 32); char **strings = backtrace_symbols(array, size); fprintf(stderr, "Dumping %zd frames:\n", size - 1); for (i = 1; i < size; i++) { if (strings != NULL) fprintf(stderr, "\tFrame %zd: %p: %s\n", i, array[i], strings[i]); else fprintf(stderr, "\tFrame %zd: %p\n", i, array[i]); } free(strings); /* Since this is not allocated by MPIU_Malloc, do not use MPIU_Free */ } #pragma weak PMI_Get_properties = MPIX_Get_properties int MPIX_Get_properties(MPI_Comm comm, int * array) { int i; MPID_Comm * comm_ptr; MPID_Comm_get_ptr(comm, comm_ptr); if (!comm_ptr || comm == MPI_COMM_NULL) return MPI_ERR_COMM; for (i = 0; i < MPIDO_MAX_NUM_BITS; i++) array[i] = MPIDO_INFO_ISSET(&(comm_ptr->dcmf.properties), i); return MPI_SUCCESS; } #pragma weak PMI_Get_property = MPIX_Get_property int MPIX_Get_property(MPI_Comm comm, int prop, int * result) { MPID_Comm * comm_ptr; MPID_Comm_get_ptr(comm, comm_ptr); if (!comm_ptr || comm == MPI_COMM_NULL) return MPI_ERR_COMM; if (prop < 0 || prop > MPIDO_MAX_NUM_BITS) return MPI_ERR_ARG; *result = MPIDO_INFO_ISSET(&(comm_ptr->dcmf.properties), prop); return MPI_SUCCESS; } #pragma weak PMI_Set_property = MPIX_Set_property int MPIX_Set_property(MPI_Comm comm, int prop, int value) { MPID_Comm * comm_ptr; MPID_Comm_get_ptr(comm, comm_ptr); if (!comm_ptr || comm == MPI_COMM_NULL) return MPI_ERR_COMM; if (prop < 0 || prop > MPIDO_MAX_NUM_BITS) return MPI_ERR_ARG; if (!value) MPIDO_INFO_UNSET(&(comm_ptr->dcmf.properties), prop); else MPIDO_INFO_SET(&(comm_ptr->dcmf.properties), prop); /* if we are attempting changing a communicator property */ if (prop == MPIDO_TREE_COMM || prop == MPIDO_RECT_COMM || prop == MPIDO_IRREG_COMM) MPIDI_Comm_setup_properties(comm_ptr, 0); return MPI_SUCCESS; } int MPIX_Get_coll_protocol(MPI_Comm comm, char * protocol, int length) { MPID_Comm * comm_ptr; MPID_Comm_get_ptr(comm, comm_ptr); if (!comm_ptr || comm == MPI_COMM_NULL) return MPI_ERR_COMM; if (!protocol || length <= 0) return MPI_ERR_ARG; if (comm_ptr->dcmf.last_algorithm >= MPIDO_COLL_PROP) { strncpy(protocol, mpido_algorithms[comm_ptr->dcmf.last_algorithm - MPIDO_COLL_PROP], length); } return MPI_SUCCESS; }

27.503448

95

0.613591

50cf8ee25432eebdaf68136f032c1ff2c8843979

218

c

C

C-Programming_Basic/hello_world.c

gautamtarika/C-Proggramming-Basics

05dfe3cc8d44554b12afe08b9a86a018a7bac9b0

[ "MIT" ]

2

2020-08-26T12:51:34.000Z

2020-08-26T14:07:21.000Z

C-Programming_Basic/hello_world.c

gautamtarika/C-Proggramming-Basics

05dfe3cc8d44554b12afe08b9a86a018a7bac9b0

[ "MIT" ]

null

C-Programming_Basic/hello_world.c

gautamtarika/C-Proggramming-Basics

05dfe3cc8d44554b12afe08b9a86a018a7bac9b0

[ "MIT" ]

4

2020-08-26T12:57:44.000Z

2020-09-01T08:48:33.000Z

#include <stdio.h> int main() { printf("Hello World"); return 0; } //" stdio.h " is the header file which needs to be included before writing program. //" printf("") " is used to print the desired output.

16.769231

84

0.646789

7421aae321c1dc0d5eab25ac08a3802fcd3df1ef

1,666

h

C

libs/capture/capture_format.h

MarioHenze/cgv

bacb2d270b1eecbea1e933b8caad8d7e11d807c2

[ "BSD-3-Clause" ]

11

2017-09-30T12:21:55.000Z

2021-04-29T21:31:57.000Z

libs/capture/capture_format.h

MarioHenze/cgv

bacb2d270b1eecbea1e933b8caad8d7e11d807c2

[ "BSD-3-Clause" ]

2

2017-07-11T11:20:08.000Z

2018-03-27T12:09:02.000Z

libs/capture/capture_format.h

MarioHenze/cgv

bacb2d270b1eecbea1e933b8caad8d7e11d807c2

[ "BSD-3-Clause" ]

24

2018-03-27T11:46:16.000Z

2021-05-01T20:28:34.000Z

#pragma once #include <string> #include "lib_begin.h" namespace capture { /// different input streams enum InputStreams { IS_NONE = 0, IS_COLOR = 1, IS_DEPTH = 2, IS_INFRARED = 4, IS_PLAYER_INDEX = 8, IS_SKELETON = 16, IS_COLOR_AND_DEPTH = IS_COLOR | IS_DEPTH, IS_DEPTH_AND_PLAYER_INDEX = IS_DEPTH | IS_PLAYER_INDEX, IS_ALL = 31 }; /// different pixel formats enum PixelFormat { PF_INFRARED8, PF_INFRARED16, PF_LONG_INFRARED8, PF_LONG_INFRARED16, PF_COLOR, PF_COLOR_RAW, PF_COLOR_BAYER, PF_COLOR_YUV, PF_COLOR_YUV2, PF_COLOR_RGB24, PF_COLOR_BGR24, PF_COLOR_RGB32, PF_COLOR_BGR32, PF_DEPTH, PF_DEPTH_RAW, PF_DEPTH8, PF_DEPTH12, PF_DEPTH16, PF_RGBD, PF_RGBD32, }; /// convert pixel format to string extern CGV_API const std::string& to_string(PixelFormat pf); /// return pixel size in bytes extern CGV_API unsigned get_pixel_size(PixelFormat pf); /// struct to store the size of an image in pixels struct image_size { /// width of the image int width; /// height of the image int height; }; /// struct to store the format of an image struct image_format : public image_size { /// pixel format of image PixelFormat pixel_format; /// return the number of bytes needed to store the image size_t get_image_size() const { return width*height*get_pixel_size(pixel_format); } }; /// struct to store the format of an image stream struct image_stream_format : public image_format { /// number of frames per second float fps; /// return the number of bytes per seconded needed to stream uncompressed video data size_t get_data_rate() const { return size_t(fps*get_image_size()); } }; } #include <cgv/config/lib_end.h>

18.931818

85

0.747299

92e4fdeb3b70d9157c58cd39e3f782bf3f9f1e24

843

h

C

JHOptionView/JHOptionView/JHOptionView/DB/Area.h

iOSHJH/JHOptionView

adc3e2f1f7b6d614169aa6d3d547159c0a5410b6

[ "Apache-2.0" ]

1

2017-07-28T12:05:33.000Z

JHOptionView/JHOptionView/JHOptionView/DB/Area.h

iOSHJH/JHOptionView

adc3e2f1f7b6d614169aa6d3d547159c0a5410b6

[ "Apache-2.0" ]

null

JHOptionView/JHOptionView/JHOptionView/DB/Area.h

iOSHJH/JHOptionView

adc3e2f1f7b6d614169aa6d3d547159c0a5410b6

[ "Apache-2.0" ]

null

// // Area.h // JHOptionView // // Created by 黄俊煌 on 2017/7/28. // Copyright © 2017年 yunshi. All rights reserved. // #import <Foundation/Foundation.h> /* { "position" : "tr_0 tr_440000", "sort" : 5, "id" : 440100, "level" : 2, "area_name" : "广州市", "short_name" : "广州", "lng" : "113.28064", "lat" : "23.125177", "pid" : 440000 } */ @interface Area : NSObject /** 地区id*/ @property (nonatomic, copy) NSString *id; /** 地区名*/ @property (nonatomic, copy) NSString *area_name; /** 当前地区的上级地区id*/ @property (nonatomic, copy) NSString *pid; /** 地区名简称*/ @property (nonatomic, copy) NSString *short_name; @property (nonatomic, copy) NSString *lng; @property (nonatomic, copy) NSString *lat; @property (nonatomic, copy) NSString *level; @property (nonatomic, copy) NSString *position; @property (nonatomic, copy) NSString *sort; @end

20.071429

50

0.654804

dab0e4f0dd0b04e58684db9c1aceefb7a91c4aeb

1,694

h

C

miika_nlu/venv/Lib/site-packages/torch/include/ATen/ops/multinomial.h

NimBuzz01/Project-Miika_SDGP

08ad1aafafbe9f47c59bd1568b8ac367fefe5503

[ "MIT" ]

null

miika_nlu/venv/Lib/site-packages/torch/include/ATen/ops/multinomial.h

NimBuzz01/Project-Miika_SDGP

08ad1aafafbe9f47c59bd1568b8ac367fefe5503

[ "MIT" ]

null

miika_nlu/venv/Lib/site-packages/torch/include/ATen/ops/multinomial.h

NimBuzz01/Project-Miika_SDGP

08ad1aafafbe9f47c59bd1568b8ac367fefe5503

[ "MIT" ]

null

#pragma once // @generated by tools/codegen/gen.py from Function.h #include <ATen/Context.h> #include <ATen/DeviceGuard.h> #include <ATen/TensorUtils.h> #include <ATen/TracerMode.h> #include <ATen/core/Generator.h> #include <ATen/core/Reduction.h> #include <ATen/core/Tensor.h> #include <c10/core/Scalar.h> #include <c10/core/Storage.h> #include <c10/core/TensorOptions.h> #include <c10/util/Deprecated.h> #include <c10/util/Optional.h> #include <ATen/ops/multinomial_ops.h> namespace at { // aten::multinomial.out(Tensor self, int num_samples, bool replacement=False, *, Generator? generator=None, Tensor(a!) out) -> Tensor(a!) TORCH_API inline at::Tensor & multinomial_out(at::Tensor & out, const at::Tensor & self, int64_t num_samples, bool replacement=false, c10::optional<at::Generator> generator=c10::nullopt) { return at::_ops::multinomial_out::call(self, num_samples, replacement, generator, out); } // aten::multinomial.out(Tensor self, int num_samples, bool replacement=False, *, Generator? generator=None, Tensor(a!) out) -> Tensor(a!) TORCH_API inline at::Tensor & multinomial_outf(const at::Tensor & self, int64_t num_samples, bool replacement, c10::optional<at::Generator> generator, at::Tensor & out) { return at::_ops::multinomial_out::call(self, num_samples, replacement, generator, out); } // aten::multinomial(Tensor self, int num_samples, bool replacement=False, *, Generator? generator=None) -> Tensor TORCH_API inline at::Tensor multinomial(const at::Tensor & self, int64_t num_samples, bool replacement=false, c10::optional<at::Generator> generator=c10::nullopt) { return at::_ops::multinomial::call(self, num_samples, replacement, generator); } }

41.317073

188

0.746753

dd797c3fce7f895648f1a63c347a712ab4b34f3d

1,731

c

C

Openharmony v1.0/third_party/ltp/testcases/kernel/syscalls/timer_create/timer_create03.c

clkbit123/TheOpenHarmony

0e6bcd9dee9f1a2481d762966b8bbd24baad6159

[ "MIT" ]

1

2022-02-15T08:51:55.000Z

hihope_neptune-oh_hid/00_src/v0.3/third_party/ltp/testcases/kernel/syscalls/timer_create/timer_create03.c

dawmlight/vendor_oh_fun

bc9fb50920f06cd4c27399f60076f5793043c77d

[ "Apache-2.0" ]

null

hihope_neptune-oh_hid/00_src/v0.3/third_party/ltp/testcases/kernel/syscalls/timer_create/timer_create03.c

dawmlight/vendor_oh_fun

bc9fb50920f06cd4c27399f60076f5793043c77d

[ "Apache-2.0" ]

null

// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2019 SUSE LLC * * Author: Christian Amann <camann@suse.com> */ /* * Regression test for CVE-2017-18344: * * In kernels prior to 4.14.8 sigevent.sigev_notify is not * properly verified when calling timer_create(2) with the * field being set to (SIGEV_SIGNAL | SIGEV_THREAD_ID). * This can be used to read arbitrary kernel memory. * * For more info see: https://nvd.nist.gov/vuln/detail/CVE-2017-18344 * or commit: cef31d9af908 * * This test uses an unused number instead of SIGEV_THREAD_ID to check * if this field gets verified correctly. */ #include <errno.h> #include <signal.h> #include <time.h> #include "tst_test.h" #include "lapi/common_timers.h" #define RANDOM_UNUSED_NUMBER (54321) static void run(void) { struct sigevent evp; clock_t clock = CLOCK_MONOTONIC; kernel_timer_t created_timer_id; memset(&evp, 0, sizeof(evp)); evp.sigev_signo = SIGALRM; evp.sigev_notify = SIGEV_SIGNAL | RANDOM_UNUSED_NUMBER; evp._sigev_un._tid = getpid(); TEST(tst_syscall(__NR_timer_create, clock, &evp, &created_timer_id)); if (TST_RET != 0) { if (TST_ERR == EINVAL) { tst_res(TPASS | TTERRNO, "timer_create() failed as expected"); } else { tst_res(TFAIL | TTERRNO, "timer_create() unexpectedly failed"); } return; } tst_res(TFAIL, "timer_create() succeeded for invalid notification type"); TEST(tst_syscall(__NR_timer_delete, created_timer_id)); if (TST_RET != 0) { tst_res(TFAIL | TTERRNO, "Failed to delete timer %s", get_clock_str(clock)); } } static struct tst_test test = { .test_all = run, .tags = (const struct tst_tag[]) { {"CVE", "2017-18344"}, {"linux-git", "cef31d9af908"}, {} } };

23.712329

70

0.699596

c1ceaf6830fd95e33f5ca91d26d8631c801d24b1

1,190

h

C

spring/limbcenter/circlefit/mystuff.h

RobertJaro/SpringProject

c1ca42650e5dfc6918b7e239fd52b02402ccb1c0

[ "Apache-2.0" ]

null

spring/limbcenter/circlefit/mystuff.h

RobertJaro/SpringProject

c1ca42650e5dfc6918b7e239fd52b02402ccb1c0

[ "Apache-2.0" ]

null

spring/limbcenter/circlefit/mystuff.h

RobertJaro/SpringProject

c1ca42650e5dfc6918b7e239fd52b02402ccb1c0

[ "Apache-2.0" ]

null

#include <iostream> #include <cmath> #include <limits> #include <iomanip> #include <cstdlib> using namespace std; // define precision by commenting out one of the two lines: typedef double reals; // defines reals as double (standard for scientific calculations) //typedef long double reals; // defines reals as long double // Note: long double is an 80-bit format (more accurate, but more memory demanding and slower) typedef long long integers; // next define some frequently used constants: const reals One=1.0,Two=2.0,Three=3.0,Four=4.0,Five=5.0,Six=6.0,Ten=10.0; const reals Pi=3.141592653; const reals Dtor=Pi/180.0; const reals REAL_MAX=numeric_limits<reals>::max(); const reals REAL_MIN=numeric_limits<reals>::min(); const reals REAL_EPSILON=numeric_limits<reals>::epsilon(); // next define some frequently used functions: template<typename T> inline T SQR(T t) { return t*t; }; reals pythag(reals a, reals b) { reals absa=abs(a), absb=abs(b); if (absa > absb) return absa*sqrt(One+SQR(absb/absa)); else return (absb == 0.0 ? 0.0 : absb*sqrt(One+SQR(absa/absb))); } //#include "RandomNormalPair.cpp" // routine for generating normal random numbers

29.02439

96

0.723529

de352ca68171360f4beff302e33f73c2d30c8c38

768

h

C

DEM/Low/src/Animation/Graph/AnimGraphNode.h

niello/deusexmachina

2f698054fe82d8b40a0a0e58b86d64ffed0de06c

[ "MIT" ]

15

2019-05-07T11:26:13.000Z

2022-01-12T18:26:45.000Z

DEM/Low/src/Animation/Graph/AnimGraphNode.h

niello/deusexmachina

2f698054fe82d8b40a0a0e58b86d64ffed0de06c

[ "MIT" ]

16

2021-10-04T17:15:31.000Z

2022-03-20T09:34:29.000Z

DEM/Low/src/Animation/Graph/AnimGraphNode.h

niello/deusexmachina

2f698054fe82d8b40a0a0e58b86d64ffed0de06c

[ "MIT" ]

2

2019-04-28T23:27:48.000Z

2019-05-07T11:26:18.000Z

#pragma once #include <StdDEM.h> // Base for all animation graph nodes // TODO: use serialization to save and load graphs?! namespace DEM::Anim { using PAnimGraphNode = std::unique_ptr<class CAnimGraphNode>; class CAnimationController; class CPoseBuffer; struct CAnimationInitContext; struct CAnimationUpdateContext; class CAnimGraphNode { public: virtual ~CAnimGraphNode() = default; //???default node must skip Update and return reference pose from eval? virtual void Init(CAnimationInitContext& Context) = 0; virtual void Update(CAnimationUpdateContext& Context, float dt) = 0; virtual void EvaluatePose(CPoseBuffer& Output) = 0; virtual float GetAnimationLengthScaled() const { return 0.f; } virtual bool IsActive() const { return true; } }; }

23.272727

72

0.764323

6ec67231983f5450d1fdafa3dd429781c986828a

72

h

C

ms2pip/models/TMT.h

xiaoping-yang/ms2pip_c

061fcd8aa8c315b775ac64f5c1f7dfe0a09bdea9

[ "Apache-2.0" ]

14

2018-08-21T04:58:22.000Z

2022-03-21T11:40:12.000Z

ms2pip/models/TMT.h

xiaoping-yang/ms2pip_c

061fcd8aa8c315b775ac64f5c1f7dfe0a09bdea9

[ "Apache-2.0" ]

69

2018-05-23T12:52:16.000Z

2022-03-14T20:42:49.000Z

ms2pip/models/TMT.h

xiaoping-yang/ms2pip_c

061fcd8aa8c315b775ac64f5c1f7dfe0a09bdea9

[ "Apache-2.0" ]

10

2019-04-28T01:24:10.000Z

2022-03-04T18:37:47.000Z

float score_TMT_B(unsigned int* v); float score_TMT_Y(unsigned int* v);

24

35

0.777778

20874aa5f39d159b067fd8ac45007f43009f4da6

5,794

h

C

src/gotoh.h

tobiasrausch/alfred

180f8bb0eb246a51d3c51d4342f7a832d8559255

[ "BSD-3-Clause" ]

100

2017-04-26T11:17:10.000Z

2022-02-03T22:48:53.000Z

src/gotoh.h

tobiasrausch/alfred

180f8bb0eb246a51d3c51d4342f7a832d8559255

[ "BSD-3-Clause" ]

38

2017-08-13T02:52:45.000Z

2022-01-11T07:57:06.000Z

src/gotoh.h

tobiasrausch/bamStats

1b81205171a69906f6bdef735188e8d463af5180

[ "BSD-3-Clause" ]

11

2017-12-28T09:21:58.000Z

2021-02-16T08:30:47.000Z

#ifndef GOTOH_H #define GOTOH_H #include <boost/dynamic_bitset.hpp> #include <iostream> #include "align.h" namespace bamstats { template<typename TAlign1, typename TAlign2, typename TAlignConfig, typename TScoreObject> inline int gotohScore(TAlign1 const& a1, TAlign2 const& a2, TAlignConfig const& ac, TScoreObject const& sc) { typedef typename TScoreObject::TValue TScoreValue; // DP variables std::size_t m = _size(a1, 1); std::size_t n = _size(a2, 1); std::vector<TScoreValue> s(n+1, 0); std::vector<TScoreValue> v(n+1, 0); TScoreValue newhoz = 0; TScoreValue prevsub = 0; // Create profile typedef boost::multi_array<float, 2> TProfile; TProfile p1; TProfile p2; if ((_size(a1, 0) != 1) || (_size(a2, 0) != 1)) { _createProfile(a1, p1); _createProfile(a2, p2); } // DP for(std::size_t row = 0; row <= m; ++row) { for(std::size_t col = 0; col <= n; ++col) { // Initialization if ((row == 0) && (col == 0)) { s[0] = 0; v[0] = -sc.inf; newhoz = -sc.inf; } else if (row == 0) { v[col] = -sc.inf; s[col] = _horizontalGap(ac, 0, m, sc.go + col * sc.ge); newhoz = _horizontalGap(ac, 0, m, sc.go + col * sc.ge); } else if (col == 0) { newhoz = -sc.inf; s[0] = _verticalGap(ac, 0, n, sc.go + row * sc.ge); if (row - 1 == 0) prevsub = 0; else prevsub = _verticalGap(ac, 0, n, sc.go + (row - 1) * sc.ge); v[0] = _verticalGap(ac, 0, n, sc.go + row * sc.ge); } else { // Recursion TScoreValue prevhoz = newhoz; TScoreValue prevver = v[col]; TScoreValue prevprevsub = prevsub; prevsub = s[col]; newhoz = std::max(s[col-1] + _horizontalGap(ac, row, m, sc.go + sc.ge), prevhoz + _horizontalGap(ac, row, m, sc.ge)); v[col] = std::max(prevsub + _verticalGap(ac, col, n, sc.go + sc.ge), prevver + _verticalGap(ac, col, n, sc.ge)); s[col] = std::max(std::max(prevprevsub + _score(a1, a2, p1, p2, row-1, col-1, sc), newhoz), v[col]); } } } // Score return s[n]; } template<typename TAlign1, typename TAlign2, typename TAlign, typename TAlignConfig, typename TScoreObject> inline int gotoh(TAlign1 const& a1, TAlign2 const& a2, TAlign& align, TAlignConfig const& ac, TScoreObject const& sc) { typedef typename TScoreObject::TValue TScoreValue; // DP variables std::size_t m = _size(a1, 1); std::size_t n = _size(a2, 1); std::vector<TScoreValue> s(n+1, 0); std::vector<TScoreValue> v(n+1, 0); TScoreValue newhoz = 0; TScoreValue prevsub = 0; // Trace Matrix std::size_t mf = n+1; typedef boost::dynamic_bitset<> TBitSet; TBitSet bit1( (m+1) * (n+1), false); TBitSet bit2( (m+1) * (n+1), false); TBitSet bit3( (m+1) * (n+1), false); TBitSet bit4( (m+1) * (n+1), false); // Create profile typedef boost::multi_array<float, 2> TProfile; TProfile p1; TProfile p2; if ((_size(a1, 0) != 1) || (_size(a2, 0) != 1)) { _createProfile(a1, p1); _createProfile(a2, p2); } // DP for(std::size_t row = 0; row <= m; ++row) { for(std::size_t col = 0; col <= n; ++col) { // Initialization if ((row == 0) && (col == 0)) { s[0] = 0; v[0] = -sc.inf; newhoz = -sc.inf; bit1[0] = true; bit2[0] = true; } else if (row == 0) { v[col] = -sc.inf; s[col] = _horizontalGap(ac, 0, m, sc.go + col * sc.ge); newhoz = _horizontalGap(ac, 0, m, sc.go + col * sc.ge); bit3[col] = true; } else if (col == 0) { newhoz = -sc.inf; s[0] = _verticalGap(ac, 0, n, sc.go + row * sc.ge); if (row - 1 == 0) prevsub = 0; else prevsub = _verticalGap(ac, 0, n, sc.go + (row - 1) * sc.ge); v[0] = _verticalGap(ac, 0, n, sc.go + row * sc.ge); bit4[row * mf] = true; } else { // Recursion TScoreValue prevhoz = newhoz; TScoreValue prevver = v[col]; TScoreValue prevprevsub = prevsub; prevsub = s[col]; newhoz = std::max(s[col-1] + _horizontalGap(ac, row, m, sc.go + sc.ge), prevhoz + _horizontalGap(ac, row, m, sc.ge)); v[col] = std::max(prevsub + _verticalGap(ac, col, n, sc.go + sc.ge), prevver + _verticalGap(ac, col, n, sc.ge)); s[col] = std::max(std::max(prevprevsub + _score(a1, a2, p1, p2, row-1, col-1, sc), newhoz), v[col]); // Trace if (s[col] == newhoz) bit3[row * mf + col] = true; else if (s[col] == v[col]) bit4[row * mf + col] = true; if (newhoz != prevhoz + _horizontalGap(ac, row, m, sc.ge)) bit1[row * mf + col] = true; if (v[col] != prevver + _verticalGap(ac, col, n, sc.ge)) bit2[row * mf + col] = true; } } } // Trace-back using pointers std::size_t row = m; std::size_t col = n; char lastMatrix = 's'; typedef std::vector<char> TTrace; TTrace btr; while ((row>0) || (col>0)) { if (lastMatrix == 's') { if (bit3[row * mf + col]) lastMatrix = 'h'; else if (bit4[row * mf + col]) lastMatrix = 'v'; else { --row; --col; btr.push_back('s'); } } else if (lastMatrix == 'h') { if (bit1[row * mf + col]) lastMatrix = 's'; --col; btr.push_back('h'); } else if (lastMatrix == 'v') { if (bit2[row * mf + col]) lastMatrix = 's'; --row; btr.push_back('v'); } } // Create alignment _createAlignment(btr, a1, a2, align); // Score return s[n]; } template<typename TAlign1, typename TAlign2, typename TAlign, typename TAlignConfig> inline int gotoh(TAlign1 const& a1, TAlign2 const& a2, TAlign& align, TAlignConfig const& ac) { DnaScore<int> dnasc; return gotoh(a1, a2, align, ac, dnasc); } template<typename TAlign1, typename TAlign2, typename TAlign> inline int gotoh(TAlign1 const& a1, TAlign2 const& a2, TAlign& align) { AlignConfig<false, false> ac; return gotoh(a1, a2, align, ac); } } #endif

29.712821

120

0.581291

f5bbf79aee4a9dd69c2707c9e53b9d5d67026b74

1,440

h

C

inetsrv/iis/admin/movesite/mbase.h

npocmaka/Windows-Server-2003

5c6fe3db626b63a384230a1aa6b92ac416b0765f

[ "Unlicense" ]

17

2020-11-13T13:42:52.000Z

2021-09-16T09:13:13.000Z

inetsrv/iis/admin/movesite/mbase.h

sancho1952007/Windows-Server-2003

5c6fe3db626b63a384230a1aa6b92ac416b0765f

[ "Unlicense" ]

2

2020-10-19T08:02:06.000Z

2020-10-19T08:23:18.000Z

inetsrv/iis/admin/movesite/mbase.h

sancho1952007/Windows-Server-2003

5c6fe3db626b63a384230a1aa6b92ac416b0765f

[ "Unlicense" ]

14

2020-11-14T09:43:20.000Z

2021-08-28T08:59:57.000Z

#ifndef __METAEXP_MBASE__ #define __METAEXP_MBASE__ #include <atlbase.h> #include <initguid.h> #include <comdef.h> #include <iadmw.h> // COM Interface header file. #include "common.h" void TraceProperty( PMETADATA_RECORD pmRec, WCHAR* pwszMDPath ); HRESULT EnumProperties(IMSAdminBase* pIMetaSource, METADATA_HANDLE hKeySource, wchar_t* SourceMDPath, IMSAdminBase* pIMetaTarget, METADATA_HANDLE hKeyTarget, wchar_t* TargetMDPath ); HRESULT CreateAndCopyKey( IMSAdminBase* pIMetaSource, METADATA_HANDLE hMDSourceHandle, //metabase handle to the source key. wchar_t* pszMDSourcePath, //path of the source relative to hMDSourceHandle. IMSAdminBase* pIMetaTarget, METADATA_HANDLE hMDDestHandle, //metabase handle to the destination. wchar_t* pszMDDestPath, //path of the destination, relative to hMDDestHandle. BOOL bMDCopySubKeys //whether to copy all subkey data ); HRESULT CopyIISConfig(COSERVERINFO *pCoServerInfoSource,COSERVERINFO *pCoServerInfoTarget, WCHAR *pwszSourceKey, _bstr_t &bstrTargetKey ); HRESULT AppPoolFixUp(COSERVERINFO *pCoServerInfo, WCHAR * pwszKey, WCHAR * pwszAppPoolID ); HRESULT CreateAppPool(IMSAdminBase* pIMeta,METADATA_HANDLE hKey,WCHAR *pAppPoolID); HRESULT ApplyMBFixUp(COSERVERINFO *pCoServerInfo, WCHAR * pwszKey, WCHAR * pwszAppPoolID, PXCOPYTASKITEM pXCOPYList, WCHAR * pwszServerBinding, BOOL bApplyFPSE); #endif

40

114

0.771528

4090738a8165a38d86080e1aae0b1a6980637a6c

6,384

h

C

services/bluetooth_standard/stack/src/avctp/avctp_int.h

openharmony-sig-ci/communication_bluetooth

c9d9614e881224abfb423505e25e72163dd25df3

[ "Apache-2.0" ]

null

services/bluetooth_standard/stack/src/avctp/avctp_int.h

openharmony-sig-ci/communication_bluetooth

c9d9614e881224abfb423505e25e72163dd25df3

[ "Apache-2.0" ]

null

services/bluetooth_standard/stack/src/avctp/avctp_int.h

openharmony-sig-ci/communication_bluetooth

c9d9614e881224abfb423505e25e72163dd25df3

[ "Apache-2.0" ]

1

2021-09-13T11:16:33.000Z

/* * Copyright (C) 2021 Huawei Device Co., Ltd. * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef AVCTP_INT_H #define AVCTP_INT_H #include "avctp.h" #ifdef __cplusplus extern "C" { #endif /***************************************************************************** * Macro Define ****************************************************************************/ #define AVCT_MAX_DEVICES 6 /* The max number of peer devices tha can connected. */ #define AVCT_MAX_CONNECTS 14 /* The max number of connect session for app. */ /* State define for L2CAP channel */ typedef enum { AVCT_CH_IDLE = 0, /* no connection */ AVCT_CH_CONN, /* connection is requested */ AVCT_CH_CFG, /* config state */ AVCT_CH_OPENED, /* opened */ AVCT_CH_BUSY, /* l2cap channel is busy.can't send message */ } AvctChSt; /* message packet header length */ #define AVCT_PKG_HDR_LEN_SINGLE 3 #define AVCT_PKG_HDR_LEN_START 4 #define AVCT_PKG_HDR_LEN_CONTINUE 1 #define AVCT_PKG_HDR_LEN_END 1 /* message packet type */ #define AVCT_PKT_TYPE_SINGLE 0 /* single packet */ #define AVCT_PKT_TYPE_START 1 /* start packet */ #define AVCT_PKT_TYPE_CONTINUE 2 /* continue packet */ #define AVCT_PKT_TYPE_END 3 /* end packet */ /* Command/Response/REJ indicator. */ #define AVCT_CMD 0 /* Command message */ #define AVCT_RSP 2 /* Response message */ #define AVCT_REJ 3 /* Message rejected */ #define AVCT_CONN_UNALLOC 0 /* connect unallocated */ #define AVCT_CONN_ALLOC 1 /* connect allocated */ #define AVCT_CONN_BIND 2 /* connect Binded */ #define AVCT_ALLOC_CTRL (1 << 0) /* allocated ctrl */ #define AVCT_ALLOC_BR (1 << 1) /* allocated br */ #define AVCT_L2C_CFG_REQ (1 << 0) /* config requesed */ #define AVCT_L2C_CFG_RSP (1 << 1) /* config responsed */ #define AVCT_CH_CTRL 0 /* Control channel */ #define AVCT_CH_BR 1 /* Browsing channel */ #define WAIT_TIME (-1) #define AVCT_PARSE_SIGNLE_HDR(p, label, cr, ipid, pid) \ do { \ (label) = *(p) >> 4; \ (cr) = (*(p) >> 1) & 1; \ (ipid) = (*(p)) & 1; \ (pid) = (uint16_t)((p)[1] << 8) + (uint16_t)((p)[2]); \ } while (0) #define BT_ADDR_FMT_ASC(addr) addr[0], addr[1], addr[2], addr[3], addr[4], addr[5] #define BT_ADDR_FMT_DSC(addr) addr[5], addr[4], addr[3], addr[2], addr[1], addr[0] #define AVCT_START_PKT_PID_OFFSET 2 #define AVCT_START_PKT_PID_SIZE 2 #define AVCT_32BYTE 32 #define BT_ADDR_LENGTH 6 /***************************************************************************** * Data Types ****************************************************************************/ /* channel control block type */ typedef struct { uint16_t peerMtu; /* Control l2c mtu from peer device */ uint16_t chResult; /* Connection result from L2CAP */ uint16_t chId; /* Channel ID from L2CAP */ uint8_t chState; /* Channel state */ uint8_t chCfgSt; /* Channel config state.There are two state(ind/cfm) */ uint8_t stState; /* The state table state */ uint8_t ia; /* Int(AVCT_INIT) or Acp(AVCT_ACP) */ Packet *rxMsg; /* The point to the message being reassembled */ } AvctCbCh; /* device control block type */ typedef struct { BtAddr peerAddr; /* BD address of peer device */ AvctCbCh *cbCtrl; /* Associated ctrl channel ControlBlock */ AvctCbCh *cbBr; /* Associated browser channel ControlBlock */ uint8_t bindCnt; /* The count of connection which is binded to the device */ uint8_t chLink; /* 0:unlink, 1: ctrl linked 3:ctrl and br channe has been linked. */ bool alloced; /* false:unalloc, true :alloced */ } AvctCbDev; /* connection session control block */ typedef struct { AvctConnectParam connParam; /* Connection creation parameters from app */ AvctCbDev *cbDev; /* The point to the device ControlBlock */ uint8_t status; /* 0:unalloc; 1:alloc;2 :binded */ uint8_t connId; /* Connection Id */ } AvctCbConn; /* Channel Management service for AVCT */ typedef struct { AvctCbConn cbConn[AVCT_MAX_CONNECTS]; /* Connection control blocks */ AvctCbDev cbDev[AVCT_MAX_DEVICES]; /* Device control blocks */ uint16_t rxMtu; /* Receive MTU for control channel */ uint16_t rxMtuBr; /* Receive MTU for browsing channel */ uint16_t role; bool registered; } AvctChMng; /* data type to send */ typedef struct { Packet *buf; /* Packet buffer point */ AvctCbConn *cbConn; /* The point to the connection control block */ uint8_t label; /* Transaction lable from app */ uint8_t cr; /* command / response */ } AvctTxMsg; /* state table event data */ typedef union { AvctTxMsg txMsg; /* Message to transfer */ Packet *buf; /* Packet buffer point */ AvctCbConn *cbConn; /* The point to the connection control block */ uint16_t result; /* Deal result */ } AvctEvtData; typedef struct { BtAddr addr; /* peer address */ uint16_t aclHandle; /* aclHandle */ uint16_t lcid; /* L2CAP link channel ID */ uint8_t id; /* id */ uint16_t psm; /* psm */ } AvctRevConnParam; /***************************************************************************** * Globle Variable ****************************************************************************/ extern AvctChMng g_avctMng; /***************************************************************************** * Extern Function Declare ****************************************************************************/ extern uint8_t AvctAsyncProcess(void (*callback)(void *context), void *context); #ifdef __cplusplus } #endif #endif /* AVCTP_INT_H */

37.775148

90

0.582863

915501055a107305cb0244522a77c56519d38fc2

3,413

h

C

src/Daggy/CFileDataAggregator.h

n-bes/daggy

5e6f4603eb78fc518166e3559bfc05b6a70d5946

[ "MIT" ]

null

src/Daggy/CFileDataAggregator.h

n-bes/daggy

5e6f4603eb78fc518166e3559bfc05b6a70d5946

[ "MIT" ]

null

src/Daggy/CFileDataAggregator.h

n-bes/daggy

5e6f4603eb78fc518166e3559bfc05b6a70d5946

[ "MIT" ]

null

/* MIT License Copyright (c) 2020 Mikhail Milovidov Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #pragma once #include <memory> #include <DaggyCore/IDataAggregator.h> #include <QMetaEnum> class QFile; class CFileDataAggregator : public daggycore::IDataAggregator { Q_OBJECT public: enum ConsoleMessageType {CommError, CommStat, ProvError, ProvStat, AppStat}; Q_ENUM(ConsoleMessageType) CFileDataAggregator(QString output_folder, QString data_sources_name, QObject* parent = nullptr); ~CFileDataAggregator(); daggycore::Result prepare() override; daggycore::Result free() override; public slots: void onDataProviderStateChanged(const QString provider_id, const int state) override; void onDataProviderError(const QString provider_id, const std::error_code error_code) override; void onCommandStateChanged(const QString provider_id, const QString command_id, const daggycore::Command::State state, const int exit_code) override; void onCommandStream(const QString provider_id, const QString command_id, const daggycore::Command::Stream stream) override; void onCommandError(const QString provider_id, const QString command_id, const std::error_code error_code) override; protected: void printAppMessage ( const QString& message ); void printProviderMessage ( const ConsoleMessageType& message_type, const QString& provider_id, const QString& source_message ); void printCommandMessage ( const ConsoleMessageType& message_type, const QString& provider_id, const QString& command_id, const QString& command_message ); QString currentConsoleTime() const; private: bool writeToFile ( const QString& provider_id, const QString& command_id, const daggycore::Command::Stream& stream ); const QString output_folder_; const QString data_sources_name_; const QMetaEnum console_message_type_; const QMetaEnum provider_state_; const QMetaEnum command_state_; QMap<QString, std::shared_ptr<QFile>> stream_files_; };

33.460784

80

0.692353

72c1baccce7d87484cd83f52062539e98aa822d4

578

h

C

PrivateFrameworks/TextInputCore/TISKPathEvent.h

phatblat/macOSPrivateFrameworks

9047371eb80f925642c8a7c4f1e00095aec66044

[ "MIT" ]

17

2018-11-13T04:02:58.000Z

2022-01-20T09:27:13.000Z

PrivateFrameworks/TextInputCore/TISKPathEvent.h

phatblat/macOSPrivateFrameworks

9047371eb80f925642c8a7c4f1e00095aec66044

[ "MIT" ]

3

2018-04-06T02:02:27.000Z

2018-10-02T01:12:10.000Z

PrivateFrameworks/TextInputCore/TISKPathEvent.h

phatblat/macOSPrivateFrameworks

9047371eb80f925642c8a7c4f1e00095aec66044

[ "MIT" ]

1

2018-09-28T13:54:23.000Z

// // Generated by class-dump 3.5 (64 bit). // // class-dump is Copyright (C) 1997-1998, 2000-2001, 2004-2013 by Steve Nygard. // #import <TextInputCore/TISKEvent.h> @class TIKeyboardCandidate, TIKeyboardTouchEvent; @interface TISKPathEvent : TISKEvent { TIKeyboardCandidate *_candidate; TIKeyboardTouchEvent *_pathTouchUp; } - (void).cxx_destruct; - (id)description; - (void)reportInterKeyTiming:(id)arg1 previousEvent:(id)arg2; - (void)reportToSession:(id)arg1; - (id)init:(id)arg1 candidate:(id)arg2 order:(long long)arg3; - (BOOL)isMissingATouch; @end

22.230769

83

0.724913

2976b4c887c0ea3da8607b7934e3c0aae2b69411

6,062

c

C

tutorials/3/C/dce.c

wsun23/ncstate_ece566_spring2022

419d05720622d9886ebb32bb1ed41c4036913d5b

[ "MIT" ]

null

tutorials/3/C/dce.c

wsun23/ncstate_ece566_spring2022

419d05720622d9886ebb32bb1ed41c4036913d5b

[ "MIT" ]

null

tutorials/3/C/dce.c

wsun23/ncstate_ece566_spring2022

419d05720622d9886ebb32bb1ed41c4036913d5b

[ "MIT" ]

null

#include <unistd.h> #include <stdio.h> #include <stdlib.h> #include "llvm-c/Core.h" #include "llvm-c/BitReader.h" #include "llvm-c/BitWriter.h" #include "llvm-c/Analysis.h" #include "worklist.h" #include "stats.h" LLVMStatisticsRef Dead; LLVMStatisticsRef WorkList; int DCE_count=0; void NoOptimization(LLVMModuleRef Module) { printf("NoOptimization is running!\n"); worklist_t worklist = worklist_create(); for (LLVMValueRef F = LLVMGetFirstFunction(Module); F!=NULL; F=LLVMGetNextFunction(F)) { // Use each function, F for(LLVMBasicBlockRef BB=LLVMGetFirstBasicBlock(F); BB!=NULL; BB = LLVMGetNextBasicBlock(BB)) { // get each basic block in F for (LLVMValueRef I = LLVMGetFirstInstruction(BB); I != NULL; I = LLVMGetNextInstruction(I)) { if (isDead(I)) worklist_insert(worklist,I); // // loop over all instructions // LLVMUseRef use; // fprintf(stderr,"All users of the instruction: "); // LLVMDumpValue(I); // for(use = LLVMGetFirstUse(I); // use!=NULL; // use = LLVMGetNextUse(use)) // { // LLVMValueRef user = LLVMGetUser(use); // LLVMDumpValue(user); // } // // for(unsigned op=0; op< LLVMGetNumOperands(I); op++) { // // LLVMValueRef definition = LLVMGetOperand(I,op); // // fprintf(stderr,"Definition of op=%d is:",op); // // LLVMDumpValue(definition); // // } // for(unsigned op=0; op< LLVMGetNumOperands(I); op++) { // LLVMValueRef definition = LLVMGetOperand(I,op); // fprintf(stderr,"Definition of op=%d is:\n",op); // LLVMDumpValue(definition); // if(LLVMIsAInstruction(definition)) { // fprintf(stderr,"Is an instruction!\n"); // } // } } } while(!worklist_empty(worklist)) { LLVMValueRef I = worklist_pop(worklist); if (isDead(I)) { fprintf(stderr,"Delete: "); LLVMDumpValue(I); for(unsigned i=0; i<LLVMGetNumOperands(I); i++) { LLVMValueRef J = LLVMGetOperand(I,i); // Add to worklist only if J is an instruction // Note, J still has one use (in I) so the isDead // would return false, so we’d better not check that. // This forces us to check in the if statement above. if (LLVMIsAInstruction(J)) worklist_insert(worklist,J); } DCE_count++; LLVMInstructionEraseFromParent(I); } } } worklist_destroy(worklist); } int isDead(LLVMValueRef I) { if (LLVMGetFirstUse(I)!=NULL) return 0; LLVMOpcode opcode = LLVMGetInstructionOpcode(I); switch(opcode) { // when in doubt, keep it! add opcode here to remove: case LLVMFNeg: case LLVMAdd: case LLVMFAdd: case LLVMSub: case LLVMFSub: case LLVMMul: case LLVMFMul: case LLVMUDiv: case LLVMSDiv: case LLVMFDiv: case LLVMURem: case LLVMSRem: case LLVMFRem: case LLVMShl: case LLVMLShr: case LLVMAShr: case LLVMAnd: case LLVMOr: case LLVMXor: case LLVMAlloca: case LLVMGetElementPtr: case LLVMTrunc: case LLVMZExt: case LLVMSExt: case LLVMFPToUI: case LLVMFPToSI: case LLVMUIToFP: case LLVMSIToFP: case LLVMFPTrunc: case LLVMFPExt: case LLVMPtrToInt: case LLVMIntToPtr: case LLVMBitCast: case LLVMAddrSpaceCast: case LLVMICmp: case LLVMFCmp: case LLVMPHI: case LLVMSelect: case LLVMExtractElement: case LLVMInsertElement: case LLVMShuffleVector: case LLVMExtractValue: case LLVMInsertValue: // Success! return 1; case LLVMLoad: if(!LLVMGetVolatile(I)) return 1; // Success // all others must be kept default: break; } return 0; } void RunDeadCodeElimination(LLVMModuleRef Module) { } int main(int argc, char **argv) { /* some basic error handling */ if (argc < 3) { fprintf(stderr, "Not enough files specified.\n"); return 0; } LLVMMemoryBufferRef Buff = NULL; char *outMessage = NULL; /* 1. Read contents of object file from command line argv[1] */ LLVMCreateMemoryBufferWithContentsOfFile(argv[1], &Buff, &outMessage); LLVMModuleRef Module = NULL; /* 2. Try to parse buffer into a legal Module */ if (!Buff || LLVMParseBitcode(Buff, &Module, &outMessage)) { /* handle error */ printf("Error opening file: %s\n", outMessage); return 1; } LLVMEnableStatistics(); LLVMPassManagerRef PM = LLVMCreatePassManager(); LLVMAddScalarReplAggregatesPass(PM); LLVMRunPassManager(PM, Module); Dead = LLVMStatisticsCreate("Dead", "Dead instructions"); WorkList = LLVMStatisticsCreate("WorkList", "Instructions added to worklist"); /* 3. Do optimization on Module */ NoOptimization(Module); //RunDeadCodeElimination(Module); // LLVMDumpModule(Module); /* 4. Save result to a new file (argv[2]) to preserve original */ char *msg; LLVMBool res = LLVMVerifyModule(Module, LLVMPrintMessageAction, &msg); if (!res) LLVMWriteBitcodeToFile(Module, argv[2]); else fprintf(stderr, "Error: %s not created.\n", argv[2]); LLVMPrintStatistics(); return 0; }

30.31

82

0.548169

349770c2bd92bd0af539a0ead553ca1b1adc5702

4,345

h

C

onviflibs/gsoap/gsoap-2.8/gsoap/samples/wcf/Basic/TransportSecurity/soapBasicHttpBinding_USCOREICalculatorProxy.h

KobeBryand/onvif-qt-server-client

ccc3193b3cbc1f45b1fd9ce7928ae99864d07708

[ "Apache-2.0" ]

157

2016-08-03T11:49:59.000Z

2022-03-01T03:00:29.000Z

onviflibs/gsoap/gsoap-2.8/gsoap/samples/wcf/Basic/TransportSecurity/soapBasicHttpBinding_USCOREICalculatorProxy.h

ouzance/onvif-qt-server-client

ccc3193b3cbc1f45b1fd9ce7928ae99864d07708

[ "Apache-2.0" ]

9

2017-02-03T15:00:27.000Z

2020-12-04T23:31:43.000Z

onviflibs/gsoap/gsoap-2.8/gsoap/samples/wcf/Basic/TransportSecurity/soapBasicHttpBinding_USCOREICalculatorProxy.h

ouzance/onvif-qt-server-client

ccc3193b3cbc1f45b1fd9ce7928ae99864d07708

[ "Apache-2.0" ]

88

2016-08-29T10:54:39.000Z

2022-03-10T17:42:40.000Z

/* soapBasicHttpBinding_USCOREICalculatorProxy.h Generated by gSOAP 2.8.17r from calculator.h Copyright(C) 2000-2014, Robert van Engelen, Genivia Inc. All Rights Reserved. The generated code is released under one of the following licenses: GPL or Genivia's license for commercial use. This program is released under the GPL with the additional exemption that compiling, linking, and/or using OpenSSL is allowed. */ #ifndef soapBasicHttpBinding_USCOREICalculatorProxy_H #define soapBasicHttpBinding_USCOREICalculatorProxy_H #include "soapH.h" class SOAP_CMAC BasicHttpBinding_USCOREICalculatorProxy { public: struct soap *soap; bool own; /// Endpoint URL of service 'BasicHttpBinding_USCOREICalculatorProxy' (change as needed) const char *soap_endpoint; /// Constructor BasicHttpBinding_USCOREICalculatorProxy(); /// Constructor to use/share an engine state BasicHttpBinding_USCOREICalculatorProxy(struct soap*); /// Constructor with endpoint URL BasicHttpBinding_USCOREICalculatorProxy(const char *url); /// Constructor with engine input+output mode control BasicHttpBinding_USCOREICalculatorProxy(soap_mode iomode); /// Constructor with URL and input+output mode control BasicHttpBinding_USCOREICalculatorProxy(const char *url, soap_mode iomode); /// Constructor with engine input and output mode control BasicHttpBinding_USCOREICalculatorProxy(soap_mode imode, soap_mode omode); /// Destructor frees deserialized data virtual ~BasicHttpBinding_USCOREICalculatorProxy(); /// Initializer used by constructors virtual void BasicHttpBinding_USCOREICalculatorProxy_init(soap_mode imode, soap_mode omode); /// Delete all deserialized data (with soap_destroy and soap_end) virtual void destroy(); /// Delete all deserialized data and reset to default virtual void reset(); /// Disables and removes SOAP Header from message virtual void soap_noheader(); /// Get SOAP Header structure (NULL when absent) virtual const SOAP_ENV__Header *soap_header(); /// Get SOAP Fault structure (NULL when absent) virtual const SOAP_ENV__Fault *soap_fault(); /// Get SOAP Fault string (NULL when absent) virtual const char *soap_fault_string(); /// Get SOAP Fault detail as string (NULL when absent) virtual const char *soap_fault_detail(); /// Close connection (normally automatic, except for send_X ops) virtual int soap_close_socket(); /// Force close connection (can kill a thread blocked on IO) virtual int soap_force_close_socket(); /// Print fault virtual void soap_print_fault(FILE*); #ifndef WITH_LEAN /// Print fault to stream #ifndef WITH_COMPAT virtual void soap_stream_fault(std::ostream&); #endif /// Put fault into buffer virtual char *soap_sprint_fault(char *buf, size_t len); #endif /// Web service operation 'Add' (returns error code or SOAP_OK) virtual int Add(_mssamt__Add *mssamt__Add, _mssamt__AddResponse *mssamt__AddResponse) { return this->Add(NULL, NULL, mssamt__Add, mssamt__AddResponse); } virtual int Add(const char *endpoint, const char *soap_action, _mssamt__Add *mssamt__Add, _mssamt__AddResponse *mssamt__AddResponse); /// Web service operation 'Subtract' (returns error code or SOAP_OK) virtual int Subtract(_mssamt__Subtract *mssamt__Subtract, _mssamt__SubtractResponse *mssamt__SubtractResponse) { return this->Subtract(NULL, NULL, mssamt__Subtract, mssamt__SubtractResponse); } virtual int Subtract(const char *endpoint, const char *soap_action, _mssamt__Subtract *mssamt__Subtract, _mssamt__SubtractResponse *mssamt__SubtractResponse); /// Web service operation 'Multiply' (returns error code or SOAP_OK) virtual int Multiply(_mssamt__Multiply *mssamt__Multiply, _mssamt__MultiplyResponse *mssamt__MultiplyResponse) { return this->Multiply(NULL, NULL, mssamt__Multiply, mssamt__MultiplyResponse); } virtual int Multiply(const char *endpoint, const char *soap_action, _mssamt__Multiply *mssamt__Multiply, _mssamt__MultiplyResponse *mssamt__MultiplyResponse); /// Web service operation 'Divide' (returns error code or SOAP_OK) virtual int Divide(_mssamt__Divide *mssamt__Divide, _mssamt__DivideResponse *mssamt__DivideResponse) { return this->Divide(NULL, NULL, mssamt__Divide, mssamt__DivideResponse); } virtual int Divide(const char *endpoint, const char *soap_action, _mssamt__Divide *mssamt__Divide, _mssamt__DivideResponse *mssamt__DivideResponse); }; #endif

51.72619

194

0.806444

711a48599eda1c65ce6218f417cf51048724ae0b

839

h

C

avro/src/utils.h

fboranek/serialization_examples

bceefd262e2de09d1f76e094070a66e82782ac5f

[ "BSL-1.0" ]

null

avro/src/utils.h

fboranek/serialization_examples

bceefd262e2de09d1f76e094070a66e82782ac5f

[ "BSL-1.0" ]

null

avro/src/utils.h

fboranek/serialization_examples

bceefd262e2de09d1f76e094070a66e82782ac5f

[ "BSL-1.0" ]

null

// // Author : Frantisek Boranek // License : Boost Software License (http://www.boost.org/users/license.html) // #pragma once #include <cassert> #include <fstream> #include <iostream> #include <vector> #include "avro/Compiler.hh" #include "avro/ValidSchema.hh" #include "Person.v1.hpp" #include "Person.v2.hpp" avro::ValidSchema readSchema(const std::string& filename); // serialize to string template<class P> std::string serializeToString(const P& person) { std::stringstream ss; std::unique_ptr<avro::OutputStream> out = avro::ostreamOutputStream(ss); avro::EncoderPtr e = avro::binaryEncoder(); e->init(*out); avro::encode(*e, person); e->flush(); return ss.str(); } void print(const avro_v1::Person& person); void print(const avro_v2::Person& person); void printBinary(const std::string& data);

22.675676

78

0.703218

513bea111641de11ae098db69ba77ae0b9f1e784

1,430

h

C

TrackingTools/MeasurementDet/interface/TrajectoryMeasurementGroup.h

ckamtsikis/cmssw

ea19fe642bb7537cbf58451dcf73aa5fd1b66250

[ "Apache-2.0" ]

852

2015-01-11T21:03:51.000Z

2022-03-25T21:14:00.000Z

TrackingTools/MeasurementDet/interface/TrajectoryMeasurementGroup.h

ckamtsikis/cmssw

ea19fe642bb7537cbf58451dcf73aa5fd1b66250

[ "Apache-2.0" ]

30,371

2015-01-02T00:14:40.000Z

2022-03-31T23:26:05.000Z

TrackingTools/MeasurementDet/interface/TrajectoryMeasurementGroup.h

ckamtsikis/cmssw

ea19fe642bb7537cbf58451dcf73aa5fd1b66250

[ "Apache-2.0" ]

3,240

2015-01-02T05:53:18.000Z

2022-03-31T17:24:21.000Z

#ifndef TrajectoryMeasurementGroup_H #define TrajectoryMeasurementGroup_H #include "TrackingTools/PatternTools/interface/TrajectoryMeasurement.h" #include "TrackingTools/DetLayers/interface/DetGroup.h" #include <vector> #include <utility> /** A class that facilitates grouping of trajectory measurements * according to the group of Dets from which they come. * Functionally equivalent to * pair<vector<TrajectoryMeasurement>, vector<DetWithState> > * but with a more convenient interface. * Used as a return type for the CompositeDet::groupedMeasurements method. */ class TrajectoryMeasurementGroup { public: TrajectoryMeasurementGroup() {} TrajectoryMeasurementGroup(const std::vector<TrajectoryMeasurement>& meas, const DetGroup& dg) : measurements_(meas), detGroup_(dg) {} TrajectoryMeasurementGroup(std::vector<TrajectoryMeasurement>&& meas, const DetGroup& dg) : measurements_(std::move(meas)), detGroup_(dg) {} TrajectoryMeasurementGroup(std::vector<TrajectoryMeasurement>&& meas, DetGroup&& dg) : measurements_(std::move(meas)), detGroup_(std::move(dg)) {} const std::vector<TrajectoryMeasurement>& measurements() const { return measurements_; } std::vector<TrajectoryMeasurement>& measurements() { return measurements_; } const DetGroup& detGroup() const { return detGroup_; } private: std::vector<TrajectoryMeasurement> measurements_; DetGroup detGroup_; }; #endif

37.631579

96

0.770629

1fb159f73c7577a4325752ab7438859e97a7d43e

4,501

h

C

Libraries/RobsJuceModules/rosic/legacy/MovedToRAPT/rosic_OnePoleFilterStereo.h

RobinSchmidt/RS-MET-Preliminary

6c01cbaad7cce3daa3293c444dd9e4b74e5ebfbe

[ "FTL" ]

34

2017-04-19T18:26:02.000Z

2022-02-15T17:47:26.000Z

Libraries/RobsJuceModules/rosic/legacy/MovedToRAPT/rosic_OnePoleFilterStereo.h

RobinSchmidt/RS-MET-Preliminary

6c01cbaad7cce3daa3293c444dd9e4b74e5ebfbe

[ "FTL" ]

307

2017-05-04T21:45:01.000Z

2022-02-03T00:59:01.000Z

Libraries/RobsJuceModules/rosic/legacy/MovedToRAPT/rosic_OnePoleFilterStereo.h

RobinSchmidt/RS-MET-Preliminary

6c01cbaad7cce3daa3293c444dd9e4b74e5ebfbe

[ "FTL" ]

4

2017-09-05T17:04:31.000Z

2021-12-15T21:24:28.000Z

#ifndef rosic_OnePoleFilterStereo_h #define rosic_OnePoleFilterStereo_h //// rosic-indcludes: //#include "../math/rosic_ComplexFunctions.h" namespace rosic { /** This is an implementation of a simple one-pole filter unit. */ class OnePoleFilterStereo { public: /** This is an enumeration of the available filter modes. */ enum modes { BYPASS = 0, LOWPASS, HIGHPASS, LOWSHELV, HIGHSHELV, ALLPASS }; //--------------------------------------------------------------------------------------------- // construction/destruction: /** Constructor. */ OnePoleFilterStereo(); //--------------------------------------------------------------------------------------------- // parameter settings: /** Sets the sample-rate. */ void setSampleRate(double newSampleRate); /** Chooses the filter mode. See the enumeration for available modes. */ void setMode(int newMode); /** Sets the cutoff-frequency for this filter. */ void setCutoff(double newCutoff); /** This will set the time constant 'tau' for the case, when lowpass mode is chosen. This is the time, it takes for the impulse response to die away to 1/e = 0.368... or equivalently, the time it takes for the step response to raise to 1-1/e = 0.632... */ void setLowpassTimeConstant(double newTimeConstant) { setCutoff(1.0/(2*PI*newTimeConstant)); } /** Sets the gain factor for the shelving modes (this is not in decibels). */ void setShelvingGain(double newGain); /** Sets the gain for the shelving modes in decibels. */ void setShelvingGainInDb(double newGainDb); /** Sets the filter coefficients manually. */ void setCoeffs(double newB0, double newB1, double newA1); /** Sets up the internal state variables for both channels. */ void setState(double newX1L, double newX1R, double newY1L, double newY1R); //--------------------------------------------------------------------------------------------- // inquiry: /** Returns the value of the filters transfer function at the complex value z. */ Complex getTransferFunctionAt(Complex z); /** Returns the value of the magnitude response of the filter at the given frequency. */ double getMagnitudeAt(double frequency); //--------------------------------------------------------------------------------------------- // audio processing: /** Calculates a single filtered output-sample. */ INLINE double getSample(double in); /** Calculates a single filtered output-sample. */ INLINE void getSampleFrameStereo(double *inL, double *inR, double *outL, double *outR); //--------------------------------------------------------------------------------------------- // others: /** Resets the internal buffers (for the \f$ x[n-1], y[n-1] \f$-samples) to zero. */ void resetBuffers(); //============================================================================================= protected: // buffering: double x1L, x1R, y1L, y1R; // filter coefficients: double b0; // feedforward coeffs double b1; double a1; // feedback coeff // filter parameters: double cutoff; double shelvingGain; int mode; double sampleRate; double sampleRateRec; // reciprocal of the sampleRate // internal functions: void calcCoeffs(); // calculates filter coefficients from filter parameters // declare friends: friend class FunctionNodeLowpass6; }; //----------------------------------------------------------------------------------------------- // from here: definitions of the functions to be inlined, i.e. all functions which are supposed // to be called at audio-rate (they can't be put into the .cpp file): INLINE double OnePoleFilterStereo::getSample(double in) { // calculate the output sample: y1L = b0*in + b1*x1L + a1*y1L + TINY; // update the buffer variables: x1L = in; return y1L; } INLINE void OnePoleFilterStereo::getSampleFrameStereo(double *inL, double *inR, double *outL, double *outR) { // calculate the output sample: y1L = b0*(*inL) + b1*x1L + a1*y1L + TINY; y1R = b0*(*inR) + b1*x1R + a1*y1R + TINY; // update the buffer variables: x1L = *inL; x1R = *inR; // store the output into its slots: *outL = y1L; *outR = y1R; } } // end namespace rosic #endif // rosic_OnePoleFilterStereo_h

29.418301

99

0.559209

e55c80ede75a5b53d993044437ce54f5fe77372b

229

h

C

qy2018/qy2018/classes/Mine/ViewController/SettingController.h

2952883085/qy2018

011fca5a4ad4ad07f43ab5793fcbfee81587de2b

[ "Apache-2.0" ]

null

qy2018/qy2018/classes/Mine/ViewController/SettingController.h

2952883085/qy2018

011fca5a4ad4ad07f43ab5793fcbfee81587de2b

[ "Apache-2.0" ]

null

qy2018/qy2018/classes/Mine/ViewController/SettingController.h

2952883085/qy2018

011fca5a4ad4ad07f43ab5793fcbfee81587de2b

[ "Apache-2.0" ]

null

// // SettingController.h // qy2018 // // Created by zxy on 2018/4/3. // Copyright © 2018年 foxconn. All rights reserved. // #import "NavigationBaseController.h" @interface SettingController : NavigationBaseController @end

16.357143

55

0.724891

059415da3e4c7576ab3899e93db03a5f49c2d910

941

h

C

Upper_1/Classes/Controller/UPActAsistDetailController.h

AmazingFM/UpperPS

7d3f40c7f1bb8b4d0fd1092ccf9d3a2bde83db86

[ "Apache-2.0" ]

null

Upper_1/Classes/Controller/UPActAsistDetailController.h

AmazingFM/UpperPS

7d3f40c7f1bb8b4d0fd1092ccf9d3a2bde83db86

[ "Apache-2.0" ]

null

Upper_1/Classes/Controller/UPActAsistDetailController.h

AmazingFM/UpperPS

7d3f40c7f1bb8b4d0fd1092ccf9d3a2bde83db86

[ "Apache-2.0" ]

null

// // UPActAsistDetailController.h // Upper // // Created by 张永明 on 16/11/18. // Copyright © 2016年 aries365.com. All rights reserved. // #import "UPBaseViewController.h" #import "UPCells.h" typedef NS_ENUM(NSInteger, UPActType) { UPActTypeJuhui, UPActTypeXinqu, UPActTypeZhuanye }; //@interface UPActHelpItem : NSObject // //@property (nonatomic, copy) NSString *name; //@property (nonatomic, copy) NSString *desc; //@property (nonatomic, copy) NSString *place; //@property (nonatomic, copy) NSString *tips; // //- (CGFloat)size; // //@end // //@interface UPActHelpCell : UITableViewCell // //- (void)setItem:(UPActHelpItem *)item; //@end @interface UPActAsistDetailController : UPBaseViewController @property (nonatomic) UPActType type; @property (nonatomic, retain) UITableView *mainTable; @property (nonatomic, retain) NSMutableArray<UPInfoCellItem *> *itemArray; - (instancetype)initWithType:(UPActType)type; @end

21.386364

74

0.726886

ba790bb29285cce635c059bceb9374db19bbc0b4

2,742

h

C

src/yoctoircd.h

ajungren/yoctoircd

79a80d51ce1f730b3bd82f50fae384fbdc0d446f

[ "Apache-2.0" ]

1

2020-11-30T05:15:14.000Z

src/yoctoircd.h

ajungren/yoctoircd

79a80d51ce1f730b3bd82f50fae384fbdc0d446f

[ "Apache-2.0" ]

null

src/yoctoircd.h

ajungren/yoctoircd

79a80d51ce1f730b3bd82f50fae384fbdc0d446f

[ "Apache-2.0" ]

null

/* * This file is part of YoctoIRCd. * Copyright (C) 2012 Ayron Jungren * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __YOCTOIRCD_H #define __YOCTOIRCD_H #define _XOPEN_SOURCE 500 #include <stdio.h> #include <stdint.h> #include <stdlib.h> #include <signal.h> #include "../config.h" #if !defined YOCTO_MOD_HTTP && !defined YOCTO_MOD_IRC #error You have not enabled any modules; please edit config.h and enable at least one #endif /***** Program Information *****/ #define YOCTO_NAME "YoctoIRCd" #define YOCTO_VERSION "0.1-git" /***** Type definitions *****/ typedef struct { char *motd_path, *server_address, *server_name, *chroot_folder, *set_user, *set_group; uint16_t port, server_address_length, server_name_length, timeout; } config_t; typedef struct { char *config_path, **motd; int devnull, socket; struct sigaction child_signal_action; } globals_t; /***** Global variables *****/ extern config_t *config; extern globals_t *globals; #ifdef YOCTO_CONCRETE_EXTERNS config_t *config; globals_t *globals; #endif /***** Function prototypes *****/ void child_signal_handler(int signum); void daemonize(void); void do_chroot(const char *path); char *fread_all(FILE *handle, uint64_t maximum_length); void free_config(config_t *config); void free_motd(char **motd); gid_t get_group(const char *group); uid_t get_user(const char *user); void parent_signal_handler(int signum); config_t *parse_config(const char *path); char **parse_motd(const char *path); void set_group(gid_t gid); void set_user(uid_t uid); char **split_lines(char *string); void start_child(int socket); void start_server(int socket); void write_wrapper(int handle, const char *buffer, size_t length); /***** Macros *****/ #define safe_free(pointer) \ if(pointer != NULL) { \ free(pointer); \ pointer = NULL; \ } #define safe_malloc(pointer, size) \ pointer = malloc(size); \ if(pointer == NULL) { \ perror("Could not allocate memory"); \ exit(EXIT_FAILURE); \ } #define safe_realloc(pointer, size) \ pointer = realloc(pointer, size); \ if(pointer == NULL) { \ perror("Could not reallocate memory"); \ exit(EXIT_FAILURE); \ } #endif

25.867925

90

0.707148

d74f5edf54a3b891aa6c59f3014ba2172a1c79ca

2,570

c

C

Section9/Challenge2/main.c

tslothorst/Learning-C

6e8c1dd71969b6f6cc8993e88ea5a008ccb8fbc1

[ "MIT" ]

1

2021-05-05T14:39:39.000Z

Section9/Challenge2/main.c

tslothorst/Learning-C

6e8c1dd71969b6f6cc8993e88ea5a008ccb8fbc1

[ "MIT" ]

null

Section9/Challenge2/main.c

tslothorst/Learning-C

6e8c1dd71969b6f6cc8993e88ea5a008ccb8fbc1

[ "MIT" ]

null

#include <stdio.h> #include <stdbool.h> #include <conio.h> #include <stdlib.h> void drawBoard(char a[]); void drawDevide(); bool checkForWin(char a[]); void makeMove(char a[], int userInput, char mark, int player); int main() { char board[10] = { 'o', '1', '2', '3', '4', '5', '6', '7', '8', '9' }; int userInput; int player =1; char mark; while(!checkForWin(board)) { drawBoard(board); // change turns player = (player % 2) ? 1 : 2; // get input printf("Player %d, enter a number: ", player); scanf("%d", &userInput); // set the correct character based on player turn mark = (player == 1) ? 'X' : 'O'; makeMove(board,userInput,mark,player); player++; } if (checkForWin(board)) printf("==>\aPlayer %d win ", --player); else printf("==>\aGame draw"); return 0; } void drawBoard (char a[]) { system("cls"); printf("Play Tic Tac Toe\n \n"); printf(" %c | %c | %c \n", a[1], a[2], a[3]); drawDevide(); printf(" %c | %c | %c \n", a[4], a[5], a[6]); drawDevide(); printf(" %c | %c | %c \n", a[7], a[8], a[9]); } void drawDevide() { printf("\n---------------\n"); } bool checkForWin(char a[]) { if (a[1] == a[2] && a[2] == a[3]) { return true; } if (a[4] == a[5] && a[5] == a[6]){ return true;} if (a[7] == a[8] && a[8] == a[9]){ return true;} if (a[1] == a[4] && a[4] == a[7]){ return true;} if (a[2] == a[5] && a[5] == a[8]){ return true;} if (a[3] == a[6] && a[6] == a[9]){ return true;} if (a[1] == a[5] && a[5] == a[9]){ return true;} if (a[3] == a[5] && a[5] == a[7]){ return true;} return false; } void makeMove(char a[], int userInput, char mark, int player){ if (userInput == 1 && a[1] == '1'){ a[1] = mark; } if (userInput == 2 && a[2] == '2'){ a[2] = mark; } if (userInput == 3 && a[3] == '3'){ a[3] = mark; } if (userInput == 4 && a[4] == '4'){ a[4] = mark; } if (userInput == 5 && a[5] == '5'){ a[5] = mark; } if (userInput == 6 && a[6] == '6'){ a[6] = mark; } if (userInput == 7 && a[7] == '7'){ a[7] = mark; } if (userInput == 8 && a[8] == '8'){ a[8] = mark; } if (userInput == 9 && a[9] == '9'){ a[9] = mark; } else { printf("Illegal move"); player--; getch(); } }

19.618321

74

0.419844

a752c9d970890db36dd45aa623429358c3c71c37

3,628

c

C

myy/helpers/matrices.c

Miouyouyou/QuickProtoGL

90e12b5179b0b69292772b42745c76251985d232

[ "MIT" ]

null

myy/helpers/matrices.c

Miouyouyou/QuickProtoGL

90e12b5179b0b69292772b42745c76251985d232

[ "MIT" ]

null

myy/helpers/matrices.c

Miouyouyou/QuickProtoGL

90e12b5179b0b69292772b42745c76251985d232

[ "MIT" ]

null

#include <myy/helpers/log.h> #include <myy/helpers/matrices.h> #include <stdint.h> void myy_matrix_4x4_print (union myy_4x4_matrix const * __restrict const matrix) { LOG( " X | Y | Z | W \n" "[%10.4f |%10.4f |%10.4f |%10.4f ] * X\n" "[%10.4f |%10.4f |%10.4f |%10.4f ] * Y\n" "[%10.4f |%10.4f |%10.4f |%10.4f ] * Z\n" "[%10.4f |%10.4f |%10.4f |%10.4f ] * W\n" " + | + | + | + \n" " ↓ | ↓ | ↓ | ↓ \n" "[ x | y | z | w ]\n", matrix->row.x.X, matrix->row.x.Y, matrix->row.x.Z, matrix->row.x.W, matrix->row.y.X, matrix->row.y.Y, matrix->row.y.Z, matrix->row.y.W, matrix->row.z.X, matrix->row.z.Y, matrix->row.z.Z, matrix->row.z.W, matrix->row.w.X, matrix->row.w.Y, matrix->row.w.Z, matrix->row.w.W ); } void myy_matrix_4x4_identity (union myy_4x4_matrix * __restrict const matrix) { union myy_4x4_matrix const identity_4x4 = { .vec_rows = { {1.0f,0.0f,0.0f,0.0f}, {0.0f,1.0f,0.0f,0.0f}, {0.0f,0.0f,1.0f,0.0f}, {0.0f,0.0f,0.0f,1.0f} } }; *matrix = identity_4x4; } void myy_matrix_4x4_translate (union myy_4x4_matrix * __restrict const matrix, vec4 translation) { matrix->vec_rows[m_w] += translation; } void myy_matrix_4x4_mult (union myy_4x4_matrix * __restrict const matrix_stack, union myy_4x4_matrix const * __restrict const new_matrix) { union myy_4x4_matrix result_matrix = {0}; for ( unsigned int d = m_x; d < n_4x4_matrix_dimensions; d++ ) { vec4 const matrix_row = matrix_stack->vec_rows[d]; float const x = matrix_row[0], y = matrix_row[1], z = matrix_row[2], w = matrix_row[3]; result_matrix.vec_rows[d] = new_matrix->vec_rows[m_x] * x + new_matrix->vec_rows[m_y] * y + new_matrix->vec_rows[m_z] * z + new_matrix->vec_rows[m_w] * w; } *matrix_stack = result_matrix; } void myy_matrix_4x4_ortho_layered_window_coords (union myy_4x4_matrix * __restrict const matrix, unsigned int const width, unsigned int const height, unsigned int const layers) { union myy_4x4_matrix const ortho_matrix = { .vec_rows = { {2.0f/width, 0, 0, 0}, {0, -2.0f/height, 0, 0}, {0, 0, 1.0f/layers, 0}, {-1.0f, 1.0f, 0, 1.0f} } }; myy_matrix_4x4_print(&ortho_matrix); *matrix = ortho_matrix; } void myy_matrix_4x4_ortho_layered (union myy_4x4_matrix * __restrict const matrix, unsigned int const width, unsigned int const height, unsigned int const layers) { union myy_4x4_matrix const ortho_matrix = { .vec_rows = { {2.0f/width, 0, 0, 0}, {0, 2.0f/height, 0, 0}, {0, 0, 1.0f/layers, 0}, {-1.0f, -1.0f, 0, 1.0f} } }; myy_matrix_4x4_print(&ortho_matrix); *matrix = ortho_matrix; } vec4 myy_vec4_4x4_matrix_mult (vec4 const * __restrict const vector, union myy_4x4_matrix const * __restrict const matrix) { float x = vector[0][vec_x], y = vector[0][vec_y], z = vector[0][vec_z], w = vector[0][vec_w]; return matrix->vec_rows[m_x] * x + matrix->vec_rows[m_y] * y + matrix->vec_rows[m_z] * z + matrix->vec_rows[m_w] * w; } vec4 myy_3i16_vector_4x4_matrix_mult (int16_t const * __restrict const vector, union myy_4x4_matrix const * __restrict const matrix, int16_t w_value) { float x = vector[vec_x], y = vector[vec_y], z = vector[vec_z], w = w_value; return matrix->vec_rows[m_x] * x + matrix->vec_rows[m_y] * y + matrix->vec_rows[m_z] * z + matrix->vec_rows[m_w] * w; } void myy_vec4_print(vec4 const vector) { LOG("%f, %f, %f, %f\n", vector[vec_x], vector[vec_y], vector[vec_z], vector[vec_w]); }

24.348993

70

0.620452

a79054c277d1d9e7eaded7125f666a55ef272669

252

c

C

xboot/src/lib/libc/ctype/isspace.c

LoongPenguin/Linux_210

d941ed620798fb9c96b5d06764fb1dcb68057513

[ "Apache-2.0" ]

null

xboot/src/lib/libc/ctype/isspace.c

LoongPenguin/Linux_210

d941ed620798fb9c96b5d06764fb1dcb68057513

[ "Apache-2.0" ]

null

xboot/src/lib/libc/ctype/isspace.c

LoongPenguin/Linux_210

d941ed620798fb9c96b5d06764fb1dcb68057513

[ "Apache-2.0" ]

null

/* * libc/ctype/isspace.c */ #include <xboot/module.h> #include <ctype.h> /* * Checks if a byte is a space byte */ int isspace(int c) { return (c == -1 ? 0 : (((const char *)__const_ctype + 1)[(unsigned char)c] & _S)); } EXPORT_SYMBOL(isspace);

15.75

83

0.615079

be4a22765706f72d001ecfdd1f5e9186c63913f0

518

h

C

AudioPlayer/lib-tools/Player/View/PlayerView/SongSheet/ListTable.h

PureRunner/AudioPlayer

1ad9011f36c402cfd1242559caf392ad1556acfe

[ "MIT" ]

1

2018-11-08T03:11:28.000Z

AudioPlayer/lib-tools/Player/View/PlayerView/SongSheet/ListTable.h

PureRunner/AudioPlayer

1ad9011f36c402cfd1242559caf392ad1556acfe

[ "MIT" ]

null

AudioPlayer/lib-tools/Player/View/PlayerView/SongSheet/ListTable.h

PureRunner/AudioPlayer

1ad9011f36c402cfd1242559caf392ad1556acfe

[ "MIT" ]

null

// // ListTable.h // AudioPlayer // // Created by shuai pan on 2017/3/6. // Copyright © 2017年 ClaudeLi. All rights reserved. // #import <UIKit/UIKit.h> @class MusicModel; @interface ListTable : UIView @property (nonatomic ,assign)CGFloat listTableHeight; /** * 歌单列表更新 * songs：歌单参数 */ - (void)updateSongSheet:(NSArray *)songs; /** * 歌单列表回调 * selectBlock：歌单选择回调 * closeListBlock：歌单关闭回调 */ - (void)selectSongSheet:(void(^)(MusicModel *model))selectBlock closeList:(void(^)(void))closeListBlock; @end

15.235294

104

0.69112

571f1c4c5f77515b28e6462d6b5e5d8293692b5b

4,601

c

C

bin/fdisk/main.c

cwolsen7905/UbixOS

2f6063103347a8e8c369aacdd1399911bb4a4776

[ "BSD-3-Clause" ]

null

bin/fdisk/main.c

cwolsen7905/UbixOS

2f6063103347a8e8c369aacdd1399911bb4a4776

[ "BSD-3-Clause" ]

null

bin/fdisk/main.c

cwolsen7905/UbixOS

2f6063103347a8e8c369aacdd1399911bb4a4776

[ "BSD-3-Clause" ]

null

/*- * Copyright (c) 2002-2018 The UbixOS Project. * All rights reserved. * * This was developed by Christopher W. Olsen for the UbixOS Project. * * Redistribution and use in source and binary forms, with or without modification, are permitted * provided that the following conditions are met: * * 1) Redistributions of source code must retain the above copyright notice, this list of * conditions, the following disclaimer and the list of authors. * 2) Redistributions in binary form must reproduce the above copyright notice, this list of * conditions, the following disclaimer and the list of authors in the documentation and/or * other materials provided with the distribution. * 3) Neither the name of the UbixOS Project nor the names of its contributors may be used to * endorse or promote products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include <stdio.h> #include <stdlib.h> #include <unistd.h> #include <sys/sys.h> #include <string.h> #include "ubixfs.h" struct dos_partition { unsigned char dp_flag; /* bootstrap flags */ unsigned char dp_shd; /* starting head */ unsigned char dp_ssect; /* starting sector */ unsigned char dp_scyl; /* starting cylinder */ unsigned char dp_type; /* partition type */ unsigned char dp_ehd; /* end head */ unsigned char dp_esect; /* end sector */ unsigned char dp_ecyl; /* end cylinder */ uint32_t dp_start; /* absolute starting sector number */ uint32_t dp_size; /* partition size in sectors */ }; int main(int argc, char **argv) { FILE *fd; FILE *mbr; struct dos_partition *d = 0x0; char *data = (char *) malloc(512); int i = 0x0; char buf[256]; d = (struct dos_partition *) (data + 0x1BE); printf("Ubix Disk Editor Version 1.0\n"); printf("(c) 2004 Ubix Corp \n\n"); if (argc >= 2) { printf("Drive Info (%s):\n", argv[1]); fd = fopen(argv[1], "rb"); } else { printf("Drive Info (ad0):\n"); fd = fopen("devfs:ad0", "rb"); } if (fd->size == 0x0) { printf("Invalid Device\n"); exit(0x1); } fseek(fd, 0, 0); fread(data, 512, 1, fd); if (argc >= 3) { i = atoi(argv[2]); if (i == 0) { mbr = fopen("sys:mrb", "rb"); fseek(mbr, 0, 0); fread(data, 512, 1, mbr); printf("Installing Ubix MBR\n"); } else { i--; printf("d[%i].dp_type = %i, ", i, d[i].dp_type); printf("New Value: "); gets((char *) &buf); d[i].dp_type = atoi(buf); printf("d[%i].dp_start: %i, ", i, d[i].dp_start); printf("New Value: "); gets((char *) &buf); d[i].dp_start = atoi(buf); printf("d[%i].dp_size: %i, ", i, d[i].dp_size); printf("New Value: "); gets((char *) &buf); d[i].dp_size = atoi(buf); printf("d[%i].dp_type: 0x%X\n", i, d[i].dp_type); printf("d[%i].dp_start: %i\n", i, d[i].dp_start); printf("d[%i].dp_size: %i\n", i, d[i].dp_size); } fseek(fd, 0, 0); fwrite(data, 512, 1, fd); } else { printf("Partition Table:\n"); for (i = 0; i < 4; i++) { if (d[i].dp_type != 0x0) { printf("d[%i].dp_type: 0x%X\n", i, d[i].dp_type); printf("d[%i].dp_start: %i\n", i, d[i].dp_start); printf("d[%i].dp_size: %i\n", i, d[i].dp_size); } } } fclose(fd); return (0); } /*** $Log: main.c,v $ Revision 1.2 2006/10/12 15:00:26 reddawg More changes Revision 1.1.1.1 2006/06/01 12:46:09 reddawg ubix2 Revision 1.2 2005/10/12 00:13:28 reddawg Removed Revision 1.1.1.1 2005/09/26 17:13:58 reddawg no message Revision 1.9 2004/08/15 00:33:02 reddawg Wow the ide driver works again Revision 1.8 2004/06/01 01:30:43 reddawg No more warnings and organized make files Revision 1.7 2004/05/24 13:54:52 reddawg Clean Up END ***/

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