hexsha stringlengths 40 40 | size int64 5 1.05M | ext stringclasses 588
values | lang stringclasses 305
values | max_stars_repo_path stringlengths 3 363 | max_stars_repo_name stringlengths 5 118 | max_stars_repo_head_hexsha stringlengths 40 40 | max_stars_repo_licenses listlengths 1 10 | max_stars_count float64 1 191k ⌀ | max_stars_repo_stars_event_min_datetime stringdate 2015-01-01 00:00:35 2022-03-31 23:43:49 ⌀ | max_stars_repo_stars_event_max_datetime stringdate 2015-01-01 12:37:38 2022-03-31 23:59:52 ⌀ | max_issues_repo_path stringlengths 3 363 | max_issues_repo_name stringlengths 5 118 | max_issues_repo_head_hexsha stringlengths 40 40 | max_issues_repo_licenses listlengths 1 10 | max_issues_count float64 1 134k ⌀ | max_issues_repo_issues_event_min_datetime stringlengths 24 24 ⌀ | max_issues_repo_issues_event_max_datetime stringlengths 24 24 ⌀ | max_forks_repo_path stringlengths 3 363 | max_forks_repo_name stringlengths 5 135 | max_forks_repo_head_hexsha stringlengths 40 40 | max_forks_repo_licenses listlengths 1 10 | max_forks_count float64 1 105k ⌀ | max_forks_repo_forks_event_min_datetime stringdate 2015-01-01 00:01:02 2022-03-31 23:27:27 ⌀ | max_forks_repo_forks_event_max_datetime stringdate 2015-01-03 08:55:07 2022-03-31 23:59:24 ⌀ | content stringlengths 5 1.05M | avg_line_length float64 1.13 1.04M | max_line_length int64 1 1.05M | alphanum_fraction float64 0 1 |
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13ef79f0e0b2679b74baf88c1f0db95edb72a917 | 100,969 | h | C | classes/display/cl857d.h | Lyude/open-gpu-doc | eb6eff64e157c60a146d000bd35dd341e3497602 | [
"MIT"
] | 1,043 | 2019-04-24T20:15:31.000Z | 2022-03-28T11:49:55.000Z | classes/display/cl857d.h | Lyude/open-gpu-doc | eb6eff64e157c60a146d000bd35dd341e3497602 | [
"MIT"
] | 2 | 2019-08-08T14:53:21.000Z | 2020-12-11T01:51:38.000Z | classes/display/cl857d.h | Lyude/open-gpu-doc | eb6eff64e157c60a146d000bd35dd341e3497602 | [
"MIT"
] | 77 | 2019-05-06T09:18:41.000Z | 2022-03-17T09:02:44.000Z | /*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl857d_h_
#define _cl857d_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV857D_CORE_CHANNEL_DMA (0x0000857D)
#define NV857D_CORE_NOTIFIER_2 0x00000000
#define NV857D_CORE_NOTIFIER_2_SIZEOF 0x00000124
#define NV857D_CORE_NOTIFIER_2_COMPLETION_0 0x00000000
#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE 0:0
#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_R0 15:1
#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_TIMESTAMP 29:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO 2:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA 20:20
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS 21:21
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA 22:22
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2 0x00000002
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_R2 31:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_3 0x00000003
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_3_R3 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_4 0x00000004
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_4_R4 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_5 0x00000005
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_5_R5 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_6 0x00000006
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_6_R6 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_7 0x00000007
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_7_R7 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_8 0x00000008
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_8_R8 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9 0x00000009
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_R0 31:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10 0x0000000A
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11 0x0000000B
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_R0 31:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12 0x0000000C
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13 0x0000000D
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_R0 31:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14 0x0000000E
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15 0x0000000F
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_R0 31:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16 0x00000010
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17 0x00000011
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18 2:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A 4:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B 5:5
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS 7:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI 9:9
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A 10:10
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B 11:11
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ 12:12
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_R0 31:14
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18 0x00000012
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19 0x00000013
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18 2:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A 4:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B 5:5
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS 7:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI 9:9
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A 10:10
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B 11:11
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ 12:12
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_R0 31:14
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20 0x00000014
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21 0x00000015
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18 2:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A 4:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B 5:5
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS 7:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI 9:9
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A 10:10
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B 11:11
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ 12:12
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_R0 31:14
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22 0x00000016
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23 0x00000017
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18 2:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A 4:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B 5:5
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS 7:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI 9:9
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A 10:10
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B 11:11
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ 12:12
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_R0 31:14
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24 0x00000018
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25 0x00000019
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18 2:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A 4:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B 5:5
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS 7:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI 9:9
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A 10:10
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B 11:11
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ 12:12
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_R0 31:14
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26 0x0000001A
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27 0x0000001B
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18 2:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A 4:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B 5:5
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS 7:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI 9:9
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A 10:10
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B 11:11
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ 12:12
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_R0 31:14
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28 0x0000001C
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29 0x0000001D
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18 2:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A 4:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B 5:5
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS 7:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI 9:9
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A 10:10
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B 11:11
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ 12:12
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_R0 31:14
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30 0x0000001E
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31 0x0000001F
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18 2:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24 3:3
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A 4:4
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B 5:5
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS 7:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI 9:9
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A 10:10
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B 11:11
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ 12:12
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_R0 31:14
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32 0x00000020
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33 0x00000021
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_R0 31:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34 0x00000022
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35 0x00000023
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_R0 31:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36 0x00000024
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37 0x00000025
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_R0 31:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38 0x00000026
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39 0x00000027
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC 1:1
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED 6:6
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_R0 31:7
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40 0x00000028
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40_R1 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41 0x00000029
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_R0 31:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42 0x0000002A
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R1 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R2 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43 0x0000002B
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R3 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R4 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44 0x0000002C
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R5 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R6 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45 0x0000002D
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45_R7 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46 0x0000002E
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46_R8 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47 0x0000002F
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47_R9 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48 0x00000030
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48_R10 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49 0x00000031
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_R0 31:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50 0x00000032
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R1 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R2 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51 0x00000033
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R3 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R4 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52 0x00000034
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R5 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R6 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53 0x00000035
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53_R7 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54 0x00000036
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54_R8 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55 0x00000037
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55_R9 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56 0x00000038
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56_R10 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57 0x00000039
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_R0 31:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58 0x0000003A
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R1 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R2 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59 0x0000003B
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R3 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R4 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60 0x0000003C
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R5 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R6 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61 0x0000003D
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61_R7 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62 0x0000003E
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62_R8 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63 0x0000003F
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63_R9 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64 0x00000040
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64_R10 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65 0x00000041
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE 0:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_FALSE 0x00000000
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_TRUE 0x00000001
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_R0 31:2
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66 0x00000042
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R1 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R2 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67 0x00000043
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R3 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R4 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68 0x00000044
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP444 14:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R5 15:15
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP422 30:16
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R6 31:31
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69 0x00000045
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69_R7 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70 0x00000046
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70_R8 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71 0x00000047
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71_R9 31:0
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72 0x00000048
#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72_R10 31:0
// dma opcode instructions
#define NV857D_DMA 0x00000000
#define NV857D_DMA_OPCODE 31:29
#define NV857D_DMA_OPCODE_METHOD 0x00000000
#define NV857D_DMA_OPCODE_JUMP 0x00000001
#define NV857D_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NV857D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NV857D_DMA_OPCODE 31:29
#define NV857D_DMA_OPCODE_METHOD 0x00000000
#define NV857D_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NV857D_DMA_METHOD_COUNT 27:18
#define NV857D_DMA_METHOD_OFFSET 11:2
#define NV857D_DMA_DATA 31:0
#define NV857D_DMA_DATA_NOP 0x00000000
#define NV857D_DMA_OPCODE 31:29
#define NV857D_DMA_OPCODE_JUMP 0x00000001
#define NV857D_DMA_JUMP_OFFSET 11:2
#define NV857D_DMA_OPCODE 31:29
#define NV857D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NV857D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NV857D_PUT (0x00000000)
#define NV857D_PUT_PTR 11:2
#define NV857D_GET (0x00000004)
#define NV857D_GET_PTR 11:2
#define NV857D_UPDATE (0x00000080)
#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0
#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1 8:8
#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NV857D_UPDATE_INTERLOCK_WITH_BASE0 1:1
#define NV857D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000)
#define NV857D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001)
#define NV857D_UPDATE_INTERLOCK_WITH_BASE1 9:9
#define NV857D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000)
#define NV857D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001)
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000)
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001)
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1 10:10
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000)
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001)
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000)
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001)
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 11:11
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000)
#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001)
#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY 31:31
#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000)
#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001)
#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30
#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000)
#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001)
#define NV857D_UPDATE_INHIBIT_INTERRUPTS 29:29
#define NV857D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000)
#define NV857D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001)
#define NV857D_SET_NOTIFIER_CONTROL (0x00000084)
#define NV857D_SET_NOTIFIER_CONTROL_MODE 30:30
#define NV857D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NV857D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NV857D_SET_NOTIFIER_CONTROL_OFFSET 11:2
#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY 31:31
#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000)
#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001)
#define NV857D_SET_CONTEXT_DMA_NOTIFIER (0x00000088)
#define NV857D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
#define NV857D_GET_CAPABILITIES (0x0000008C)
#define NV857D_GET_CAPABILITIES_DUMMY 31:0
#define NV857D_SET_SPARE (0x000003BC)
#define NV857D_SET_SPARE_UNUSED 31:0
#define NV857D_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004)
#define NV857D_SET_SPARE_NOOP_UNUSED 31:0
#define NV857D_DAC_SET_CONTROL(a) (0x00000400 + (a)*0x00000080)
#define NV857D_DAC_SET_CONTROL_OWNER 3:0
#define NV857D_DAC_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV857D_DAC_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV857D_DAC_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV857D_DAC_SET_CONTROL_SUB_OWNER 5:4
#define NV857D_DAC_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV857D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV857D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV857D_DAC_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV857D_DAC_SET_CONTROL_PROTOCOL 13:8
#define NV857D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M (0x00000001)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J (0x00000002)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI (0x00000003)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M (0x00000004)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N (0x00000005)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN (0x00000006)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M (0x00000007)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J (0x00000008)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI (0x00000009)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M (0x0000000A)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N (0x0000000B)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN (0x0000000C)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60 (0x0000000D)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50 (0x0000000E)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50 (0x0000000F)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60 (0x00000010)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50 (0x00000011)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60 (0x00000012)
#define NV857D_DAC_SET_CONTROL_PROTOCOL_CUSTOM (0x0000003F)
#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD 14:14
#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE (0x00000000)
#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE (0x00000001)
#define NV857D_DAC_SET_POLARITY(a) (0x00000404 + (a)*0x00000080)
#define NV857D_DAC_SET_POLARITY_HSYNC 0:0
#define NV857D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE (0x00000000)
#define NV857D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE (0x00000001)
#define NV857D_DAC_SET_POLARITY_VSYNC 1:1
#define NV857D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE (0x00000000)
#define NV857D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE (0x00000001)
#define NV857D_DAC_SET_POLARITY_RESERVED 31:2
#define NV857D_DAC_SET_ENCODE_QUALITY(a) (0x00000420 + (a)*0x00000080)
#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS 7:7
#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375 (0x00000000)
#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75 (0x00000001)
#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN 2:0
#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0 (0x00000000)
#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625 (0x00000001)
#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125 (0x00000002)
#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25 (0x00000003)
#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5 (0x00000004)
#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0 (0x00000005)
#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN 6:4
#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0 (0x00000000)
#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625 (0x00000001)
#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125 (0x00000002)
#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25 (0x00000003)
#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5 (0x00000004)
#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0 (0x00000005)
#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH 15:8
#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH 23:16
#define NV857D_DAC_SET_ENCODE_QUALITY_TINT 31:24
#define NV857D_DAC_UPDATE_ENCODER_PRESET(a) (0x0000047C + (a)*0x00000080)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL 5:0
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT (0x00000000)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M (0x00000001)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J (0x00000002)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI (0x00000003)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M (0x00000004)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N (0x00000005)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN (0x00000006)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M (0x00000007)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J (0x00000008)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI (0x00000009)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M (0x0000000A)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N (0x0000000B)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN (0x0000000C)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60 (0x0000000D)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50 (0x0000000E)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50 (0x0000000F)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60 (0x00000010)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50 (0x00000011)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60 (0x00000012)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM (0x0000003F)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT 6:6
#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB (0x00000000)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV (0x00000001)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R 7:7
#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE (0x00000000)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE (0x00000001)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G 8:8
#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE (0x00000000)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE (0x00000001)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B 9:9
#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE (0x00000000)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE (0x00000001)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH 12:10
#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE (0x00000000)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358 (0x00000001)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358 (0x00000002)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443 (0x00000003)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443 (0x00000004)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW 13:13
#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6 (0x00000000)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4 (0x00000001)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER 15:15
#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW (0x00000000)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE (0x00000001)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER 16:16
#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW (0x00000000)
#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE (0x00000001)
#define NV857D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040)
#define NV857D_SOR_SET_CONTROL_OWNER 3:0
#define NV857D_SOR_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV857D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV857D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV857D_SOR_SET_CONTROL_SUB_OWNER 5:4
#define NV857D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV857D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV857D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV857D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV857D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NV857D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003)
#define NV857D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004)
#define NV857D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NV857D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007)
#define NV857D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008)
#define NV857D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009)
#define NV857D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12
#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13
#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20
#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000)
#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001)
#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002)
#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH 19:16
#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000)
#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001)
#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002)
#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003)
#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004)
#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005)
#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006)
#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007)
#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008)
#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009)
#define NV857D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0x00000040)
#define NV857D_PIOR_SET_CONTROL_OWNER 3:0
#define NV857D_PIOR_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV857D_PIOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV857D_PIOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV857D_PIOR_SET_CONTROL_SUB_OWNER 5:4
#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV857D_PIOR_SET_CONTROL_PROTOCOL 11:8
#define NV857D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000)
#define NV857D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001)
#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY 12:12
#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY 13:13
#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH 19:16
#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000)
#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001)
#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002)
#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003)
#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004)
#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005)
#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006)
#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007)
#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008)
#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009)
#define NV857D_HEAD_SET_PRESENT_CONTROL(a) (0x00000800 + (a)*0x00000400)
#define NV857D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0
#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8
#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000)
#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001)
#define NV857D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4
#define NV857D_HEAD_SET_PIXEL_CLOCK(a) (0x00000804 + (a)*0x00000400)
#define NV857D_HEAD_SET_PIXEL_CLOCK_FREQUENCY 21:0
#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE 23:22
#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25 (0x00000000)
#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28 (0x00000001)
#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM (0x00000002)
#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001 24:24
#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE (0x00000000)
#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE (0x00000001)
#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER 25:25
#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE (0x00000000)
#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE (0x00000001)
#define NV857D_HEAD_SET_CONTROL(a) (0x00000808 + (a)*0x00000400)
#define NV857D_HEAD_SET_CONTROL_STRUCTURE 2:1
#define NV857D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000)
#define NV857D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001)
#define NV857D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000810 + (a)*0x00000400)
#define NV857D_HEAD_SET_OVERSCAN_COLOR_RED 9:0
#define NV857D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10
#define NV857D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20
#define NV857D_HEAD_SET_RASTER_SIZE(a) (0x00000814 + (a)*0x00000400)
#define NV857D_HEAD_SET_RASTER_SIZE_WIDTH 14:0
#define NV857D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16
#define NV857D_HEAD_SET_RASTER_SYNC_END(a) (0x00000818 + (a)*0x00000400)
#define NV857D_HEAD_SET_RASTER_SYNC_END_X 14:0
#define NV857D_HEAD_SET_RASTER_SYNC_END_Y 30:16
#define NV857D_HEAD_SET_RASTER_BLANK_END(a) (0x0000081C + (a)*0x00000400)
#define NV857D_HEAD_SET_RASTER_BLANK_END_X 14:0
#define NV857D_HEAD_SET_RASTER_BLANK_END_Y 30:16
#define NV857D_HEAD_SET_RASTER_BLANK_START(a) (0x00000820 + (a)*0x00000400)
#define NV857D_HEAD_SET_RASTER_BLANK_START_X 14:0
#define NV857D_HEAD_SET_RASTER_BLANK_START_Y 30:16
#define NV857D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000824 + (a)*0x00000400)
#define NV857D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0
#define NV857D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16
#define NV857D_HEAD_SET_RASTER_VERT_BLANK_DMI(a) (0x00000828 + (a)*0x00000400)
#define NV857D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION 11:0
#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000082C + (a)*0x00000400)
#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0
#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10
#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20
#define NV857D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400)
#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31
#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001)
#define NV857D_HEAD_SET_BASE_LUT_LO_MODE 30:30
#define NV857D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000)
#define NV857D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001)
#define NV857D_HEAD_SET_BASE_LUT_LO_ORIGIN 7:2
#define NV857D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400)
#define NV857D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0
#define NV857D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000848 + (a)*0x00000400)
#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31
#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001)
#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE 30:30
#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000)
#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001)
#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN 7:2
#define NV857D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000084C + (a)*0x00000400)
#define NV857D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0
#define NV857D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000085C + (a)*0x00000400)
#define NV857D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0
#define NV857D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
#define NV857D_HEAD_SET_OFFSET_ORIGIN 31:0
#define NV857D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0x00000400)
#define NV857D_HEAD_SET_SIZE_WIDTH 14:0
#define NV857D_HEAD_SET_SIZE_HEIGHT 30:16
#define NV857D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0x00000400)
#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV857D_HEAD_SET_STORAGE_PITCH 19:8
#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT 20:20
#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV857D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0x00000400)
#define NV857D_HEAD_SET_PARAMS_FORMAT 15:8
#define NV857D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NV857D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F)
#define NV857D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E)
#define NV857D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV857D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV857D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV857D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NV857D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NV857D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0
#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X8_AA (0x00000003)
#define NV857D_HEAD_SET_PARAMS_GAMMA 2:2
#define NV857D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000)
#define NV857D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001)
#define NV857D_HEAD_SET_PARAMS_RESERVED0 22:16
#define NV857D_HEAD_SET_PARAMS_RESERVED1 24:24
#define NV857D_HEAD_SET_CONTEXT_DMAS_ISO(a,b) (0x00000874 + (a)*0x00000400 + (b)*0x00000004)
#define NV857D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
#define NV857D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0x00000400)
#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31
#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000)
#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001)
#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24
#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000)
#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001)
#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26
#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000)
#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001)
#define NV857D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8
#define NV857D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16
#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28
#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000)
#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001)
#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002)
#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER 5:4
#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE (0x00000000)
#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH (0x00000003)
#define NV857D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0x00000400)
#define NV857D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0
#define NV857D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000089C + (a)*0x00000400)
#define NV857D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0
#define NV857D_HEAD_SET_DITHER_CONTROL(a) (0x000008A0 + (a)*0x00000400)
#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0
#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000)
#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001)
#define NV857D_HEAD_SET_DITHER_CONTROL_BITS 2:1
#define NV857D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000)
#define NV857D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001)
#define NV857D_HEAD_SET_DITHER_CONTROL_MODE 6:3
#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000)
#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001)
#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002)
#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003)
#define NV857D_HEAD_SET_DITHER_CONTROL_PHASE 8:7
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x000008A4 + (a)*0x00000400)
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000)
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001)
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002)
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003)
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004)
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000)
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001)
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002)
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16
#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24
#define NV857D_HEAD_SET_PROCAMP(a) (0x000008A8 + (a)*0x00000400)
#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0
#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000)
#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001)
#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002)
#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2
#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000)
#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001)
#define NV857D_HEAD_SET_PROCAMP_SAT_COS 19:8
#define NV857D_HEAD_SET_PROCAMP_SAT_SINE 31:20
#define NV857D_HEAD_SET_PROCAMP_TRANSITION 4:3
#define NV857D_HEAD_SET_PROCAMP_TRANSITION_HARD (0x00000000)
#define NV857D_HEAD_SET_PROCAMP_TRANSITION_NTSC (0x00000001)
#define NV857D_HEAD_SET_PROCAMP_TRANSITION_PAL (0x00000002)
#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5
#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000)
#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001)
#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6
#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000)
#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001)
#define NV857D_HEAD_SET_VIEWPORT_POINT_IN(a,b) (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
#define NV857D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0
#define NV857D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16
#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000008C8 + (a)*0x00000400)
#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0
#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16
#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000008D4 + (a)*0x00000400)
#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0
#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16
#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000008D8 + (a)*0x00000400)
#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0
#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16
#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000008DC + (a)*0x00000400)
#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0
#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x00000900 + (a)*0x00000400)
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000)
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001)
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000)
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001)
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003)
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005)
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X8_AA (0x00000003)
#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x00000904 + (a)*0x00000400)
#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0
#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000)
#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001)
#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8
#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001)
#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003)
#define NV857D_HEAD_SET_PROCESSING(a) (0x00000910 + (a)*0x00000400)
#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0
#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000)
#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001)
#define NV857D_HEAD_SET_CONVERSION(a) (0x00000914 + (a)*0x00000400)
#define NV857D_HEAD_SET_CONVERSION_GAIN 15:0
#define NV857D_HEAD_SET_CONVERSION_OFS 31:16
#define NV857D_HEAD_SET_SPARE(a) (0x00000BBC + (a)*0x00000400)
#define NV857D_HEAD_SET_SPARE_UNUSED 31:0
#define NV857D_HEAD_SET_SPARE_NOOP(a,b) (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004)
#define NV857D_HEAD_SET_SPARE_NOOP_UNUSED 31:0
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl857d_h
| 89.990196 | 126 | 0.69347 |
063202b14d8609144cbdfc50883ce95afe0c70d4 | 595 | h | C | WasteMobile/ModelManager/WastePiece.h | bcgov/eForWaste | 09c624901d2784e5e7989211b922a932d27638dc | [
"Apache-2.0"
] | null | null | null | WasteMobile/ModelManager/WastePiece.h | bcgov/eForWaste | 09c624901d2784e5e7989211b922a932d27638dc | [
"Apache-2.0"
] | 5 | 2020-04-17T19:37:31.000Z | 2022-01-10T22:20:45.000Z | WasteMobile/ModelManager/WastePiece.h | bcgov/eForWaste | 09c624901d2784e5e7989211b922a932d27638dc | [
"Apache-2.0"
] | null | null | null | //
// WastePiece.h
// WasteMobile
//
// Created by Jack Wong on 2016-10-04.
// Copyright © 2016 Salus Systems. All rights reserved.
//
#import <Foundation/Foundation.h>
#import <CoreData/CoreData.h>
@class BorderlineCode, ButtEndCode, CheckerStatusCode, CommentCode, DecayTypeCode, MaterialKindCode, ScaleGradeCode, ScaleSpeciesCode, TopEndCode, WasteClassCode, WastePlot;
NS_ASSUME_NONNULL_BEGIN
@interface WastePiece : NSManagedObject
// Insert code here to declare functionality of your managed object subclass
@end
NS_ASSUME_NONNULL_END
#import "WastePiece+CoreDataProperties.h"
| 23.8 | 173 | 0.789916 |
fa34e78f2b158566fdb4b28f00b26080c12debc8 | 200 | h | C | ffmpeg/ffmpeg/ViewController.h | kk07self/ffmpeg_study | 3ab75979a27ab477e90f6ae70dd845517cd3219d | [
"MIT"
] | 1 | 2020-04-20T06:40:59.000Z | 2020-04-20T06:40:59.000Z | ffmpeg/ffmpeg/ViewController.h | kk07self/ffmpeg_study | 3ab75979a27ab477e90f6ae70dd845517cd3219d | [
"MIT"
] | null | null | null | ffmpeg/ffmpeg/ViewController.h | kk07self/ffmpeg_study | 3ab75979a27ab477e90f6ae70dd845517cd3219d | [
"MIT"
] | null | null | null | //
// ViewController.h
// ffmpeg
//
// Created by K K on 2019/8/20.
// Copyright © 2019 K K. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface ViewController : UIViewController
@end
| 12.5 | 46 | 0.66 |
3c12af6b4b46787cf31c7069abb5b71958220a3b | 3,659 | h | C | cinn/frontend/op_mapper_registry.h | SunNy820828449/CINN | 6384f730867132508c2c60f5ff2aae12959143d7 | [
"Apache-2.0"
] | 57 | 2020-10-09T12:18:48.000Z | 2022-03-12T07:58:55.000Z | cinn/frontend/op_mapper_registry.h | SunNy820828449/CINN | 6384f730867132508c2c60f5ff2aae12959143d7 | [
"Apache-2.0"
] | 380 | 2020-10-09T08:28:08.000Z | 2022-03-31T09:17:36.000Z | cinn/frontend/op_mapper_registry.h | SunNy820828449/CINN | 6384f730867132508c2c60f5ff2aae12959143d7 | [
"Apache-2.0"
] | 34 | 2020-10-09T08:46:45.000Z | 2022-03-05T09:29:54.000Z | // Copyright (c) 2021 CINN Authors. All Rights Reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <functional>
#include <memory>
#include <string>
#include <unordered_map>
#include <variant>
#include "cinn/common/common.h"
#include "cinn/common/macros.h"
#include "cinn/common/target.h"
#include "cinn/common/type.h"
#include "cinn/frontend/net_builder.h"
#include "cinn/frontend/paddle/cpp/op_desc.h"
#include "cinn/frontend/syntax.h"
#include "cinn/hlir/framework/scope.h"
#include "cinn/utils/registry.h"
namespace cinn {
namespace frontend {
class OpMapperContext {
public:
OpMapperContext(const hlir::framework::Scope& scope,
const common::Target& target,
NetBuilder* builder,
std::unordered_map<std::string, Variable>* var_map,
std::unordered_map<std::string, std::string>* var_model_to_program_map)
: scope_(scope),
target_(target),
builder_(builder),
var_map_(var_map),
var_model_to_program_map_(var_model_to_program_map) {}
const auto& Scope() const { return scope_; }
const auto& Target() const { return target_; }
NetBuilder* Builder() const { return builder_; }
// add Variable into local var_map
void AddVar(const std::string& name, const Variable& var, bool replace = false) const;
// get Variable from local var_map or scope
Variable GetVar(const std::string& name) const;
// add map from paddle name to cinn name into var_model_to_program_map
void AddVarModelToProgram(const std::string& name, const std::string& id) const;
struct FeedInfo {
std::vector<int> shape;
common::Type type;
};
void AddFeedInfo(const std::string& name, const FeedInfo& info);
const FeedInfo& GetFeedInfo(const std::string& name) const;
private:
const hlir::framework::Scope& scope_;
const common::Target& target_;
NetBuilder* builder_{nullptr};
std::unordered_map<std::string, Variable>* var_map_{nullptr};
// map from var in Paddle model to var name in program.
std::unordered_map<std::string, std::string>* var_model_to_program_map_{nullptr};
std::unordered_map<std::string, FeedInfo> feed_info_map_;
};
class OpMapper {
public:
using OpMapperFunc = std::function<void(const paddle::cpp::OpDesc&, const OpMapperContext&)>;
OpMapper() = default;
OpMapper& Set(const OpMapperFunc& kernel) {
kernel_ = kernel;
return *this;
}
void Run(const paddle::cpp::OpDesc& op_desc, const OpMapperContext& ctx) const { kernel_(op_desc, ctx); }
std::string name;
private:
OpMapperFunc kernel_;
};
class OpMapperRegistry : public Registry<OpMapper> {
public:
OpMapperRegistry() = default;
private:
CINN_DISALLOW_COPY_AND_ASSIGN(OpMapperRegistry);
};
#define UNIQUE_OPMAPPER_NAME(OpName) static ::cinn::frontend::OpMapper& __op_mapper_registrar_##OpName
#define CINN_REGISTER_OP_MAPPER(OpName, Kernel) \
CINN_STR_CONCAT(UNIQUE_OPMAPPER_NAME(OpName), __COUNTER__) = \
::cinn::frontend::OpMapperRegistry::Global()->__REGISTER_OR_GET__(#OpName).Set(Kernel);
} // namespace frontend
} // namespace cinn
| 30.747899 | 107 | 0.716589 |
966aa33aa0ba94571af86e7f38f34974d91468fd | 3,397 | h | C | Frameworks/VVOSC.framework/Versions/A/Headers/OSCAddressSpace.h | andreacremaschi/Megabuffer | ffc8549ac11ccbaba578e82770d6489def9bcf2f | [
"BSD-2-Clause"
] | 1 | 2019-03-23T10:03:46.000Z | 2019-03-23T10:03:46.000Z | Frameworks/VVOSC.framework/Versions/A/Headers/OSCAddressSpace.h | andreacremaschi/Megabuffer | ffc8549ac11ccbaba578e82770d6489def9bcf2f | [
"BSD-2-Clause"
] | null | null | null | Frameworks/VVOSC.framework/Versions/A/Headers/OSCAddressSpace.h | andreacremaschi/Megabuffer | ffc8549ac11ccbaba578e82770d6489def9bcf2f | [
"BSD-2-Clause"
] | null | null | null |
#if IPHONE
#import <UIKit/UIKit.h>
#else
#import <Cocoa/Cocoa.h>
#endif
#import "OSCNode.h"
// OSCAddressSpace delegate protocol
@protocol OSCAddressSpaceDelegateProtocol
- (void) nodeRenamed:(OSCNode *)n;
- (void) dispatchReplyOrError:(OSCMessage *)m; // this method is called by nodes in the address space. the passed message is a reply or error in response to a query which should be sent out an output.
@end
// this is the main instance of OSCAddressSpace. it is auto-created when this class is initialized
extern id _mainAddressSpace;
/// OSCAddressSpace is a representation of the OSC address space described in the OSC spec. It is a subclass of OSCNode. This class is optional- it's not needed for basic OSC message sending/receiving.
/*!
There should only ever be one instance of OSCAddressSpace, and you shouldn't explicitly create it. Just call [OSCAddressSpace class] (or any other OSCAddressSpace method) and it will be automatically created. This main instance may be retrieved by the class method +[OSCAddressSpace mainAddressSpace] or by the class variable _mainAddressSpace.
OSCAddressSpace is your application's main way of dealing with the OSC address space- if you need to dispatch a message, set, rename, or delete a node, you should do via the main instance of this class.
*/
@interface OSCAddressSpace : OSCNode {
id delegate;
}
/// Returns the main instance of the OSC address space (and creates it if necessary)
+ (id) mainAddressSpace;
+ (void) refreshMenu;
#if !IPHONE
+ (NSMenu *) makeMenuForNode:(OSCNode *)n withTarget:(id)t action:(SEL)a;
+ (NSMenu *) makeMenuForNode:(OSCNode *)n ofType:(NSIndexSet *)ts withTarget:(id)t action:(SEL)a;
#endif
/// Renames 'before' to 'after'. Sub-nodes stay with their owners! Can also be though of as a "move".
- (void) renameAddress:(NSString *)before to:(NSString *)after;
- (void) renameAddressArray:(NSArray *)before toArray:(NSArray *)after;
/// If 'n' is nil, the node at the passed address will be deleted (as will any of its sub-nodes)
- (void) setNode:(OSCNode *)n forAddress:(NSString *)a;
- (void) setNode:(OSCNode *)n forAddress:(NSString *)a createIfMissing:(BOOL)c;
- (void) setNode:(OSCNode *)n forAddressArray:(NSArray *)a;
- (void) setNode:(OSCNode *)n forAddressArray:(NSArray *)a createIfMissing:(BOOL)c;
// this method is called whenever a node is added to another node
- (void) nodeRenamed:(OSCNode *)n;
/// Unlike a normal OSCNode, this method finds the destination node and then dispatches the msg. If the destination is itself, it just calls the super.
- (void) dispatchMessage:(OSCMessage *)m;
// This method gets called by an OSCNode inside me (or by me), and you probably won't need to ever call this method. The passed message is a reply or error that needs to be sent back in response to a query. The passed OSCMessage contains the IP address and port of the destination. This method just passes the data on to the addres space's delegate- it does NOT actually send anything out, this is something you'll have to implement in the delegate.
- (void) _dispatchReplyOrError:(OSCMessage *)m;
- (void) addDelegate:(id)d forPath:(NSString *)p;
- (void) removeDelegate:(id)d forPath:(NSString *)p;
/*
- (void) addQueryDelegate:(id)d forPath:(NSString *)p;
- (void) removeQueryDelegate:(id)d forPath:(NSString *)p;
*/
@property (assign, readwrite) id delegate;
@end
| 43.551282 | 452 | 0.746835 |
3265b4be1b58415b58145210368c23bbe674190b | 450 | c | C | all-code/code/mem/memperf/bind_to_cpu.c | Qasak/csapp-notes-and_labs | 9a8959972df27a921bc7ff866c4b5f137b876281 | [
"MIT"
] | 1 | 2021-04-06T08:41:40.000Z | 2021-04-06T08:41:40.000Z | code/mem/memperf/bind_to_cpu.c | fengxiaohu/CSAPP | e8d9a61bd2eb860ec764ad30127d11736d137f0b | [
"Apache-2.0"
] | null | null | null | code/mem/memperf/bind_to_cpu.c | fengxiaohu/CSAPP | e8d9a61bd2eb860ec764ad30127d11736d137f0b | [
"Apache-2.0"
] | null | null | null | #include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/smp.h>
#include <linux/errno.h>
asmlinkage int sys_bind_to_cpu(unsigned long mask)
{
if (!mask || !(mask & cpu_present_map))
return -EINVAL;
current->processor_mask = mask;
if ( !(mask & (1<<current->processor)) ) {
int i = 0;
for(i = 0; !(mask & (1<<i)); i++) ;
current->last_processor = i;
need_resched = 1;
}
return 0;
}
| 22.5 | 50 | 0.575556 |
c5ad08d4a6080d7f0299f6f2dc6d24dba3309ca7 | 3,525 | h | C | erizo/src/third_party/webrtc/src/webrtc/modules/remote_bitrate_estimator/packet_arrival_map.h | nowjean/licode | 8c58f8ec3378e9d645af9eb1ca0802e2a33a92a9 | [
"MIT"
] | null | null | null | erizo/src/third_party/webrtc/src/webrtc/modules/remote_bitrate_estimator/packet_arrival_map.h | nowjean/licode | 8c58f8ec3378e9d645af9eb1ca0802e2a33a92a9 | [
"MIT"
] | null | null | null | erizo/src/third_party/webrtc/src/webrtc/modules/remote_bitrate_estimator/packet_arrival_map.h | nowjean/licode | 8c58f8ec3378e9d645af9eb1ca0802e2a33a92a9 | [
"MIT"
] | null | null | null | /*
* Copyright (c) 2021 The WebRTC project authors. All Rights Reserved.
*
* Use of this source code is governed by a BSD-style license
* that can be found in the LICENSE file in the root of the source
* tree. An additional intellectual property rights grant can be found
* in the file PATENTS. All contributing project authors may
* be found in the AUTHORS file in the root of the source tree.
*/
#ifndef MODULES_REMOTE_BITRATE_ESTIMATOR_PACKET_ARRIVAL_MAP_H_
#define MODULES_REMOTE_BITRATE_ESTIMATOR_PACKET_ARRIVAL_MAP_H_
#include <cstddef>
#include <cstdint>
#include <deque>
#include "webrtc/rtc_base/checks.h"
namespace webrtc {
// PacketArrivalTimeMap is an optimized map of packet sequence number to arrival
// time, limited in size to never exceed `kMaxNumberOfPackets`. It will grow as
// needed, and remove old packets, and will expand to allow earlier packets to
// be added (out-of-order).
//
// Not yet received packets have the arrival time zero. The queue will not span
// larger than necessary and the last packet should always be received. The
// first packet in the queue doesn't have to be received in case of receiving
// packets out-of-order.
class PacketArrivalTimeMap {
public:
// Impossible to request feedback older than what can be represented by 15
// bits.
static constexpr size_t kMaxNumberOfPackets = (1 << 15);
// Indicates if the packet with `sequence_number` has already been received.
bool has_received(int64_t sequence_number) const;
// Returns the sequence number of the first entry in the map, i.e. the
// sequence number that a `begin()` iterator would represent.
int64_t begin_sequence_number() const { return begin_sequence_number_; }
// Returns the sequence number of the element just after the map, i.e. the
// sequence number that an `end()` iterator would represent.
int64_t end_sequence_number() const {
return begin_sequence_number_ + arrival_times.size();
}
// Returns an element by `sequence_number`, which must be valid, i.e.
// between [begin_sequence_number, end_sequence_number).
int64_t get(int64_t sequence_number) {
int64_t pos = sequence_number - begin_sequence_number_;
RTC_DCHECK(pos >= 0 && pos < static_cast<int64_t>(arrival_times.size()));
return arrival_times[pos];
}
// Clamps `sequence_number` between [begin_sequence_number,
// end_sequence_number].
int64_t clamp(int64_t sequence_number) const;
// Erases all elements from the beginning of the map until `sequence_number`.
void EraseTo(int64_t sequence_number);
// Records the fact that a packet with `sequence_number` arrived at
// `arrival_time_ms`.
void AddPacket(int64_t sequence_number, int64_t arrival_time_ms);
// Removes packets from the beginning of the map as long as they are received
// before `sequence_number` and with an age older than `arrival_time_limit`
void RemoveOldPackets(int64_t sequence_number, int64_t arrival_time_limit);
private:
// Deque representing unwrapped sequence number -> time, where the index +
// `begin_sequence_number_` represents the packet's sequence number.
std::deque<int64_t> arrival_times;
// The unwrapped sequence number for the first element in
// `arrival_times`.
int64_t begin_sequence_number_ = 0;
// Indicates if this map has had any packet added to it. The first packet
// decides the initial sequence number.
bool has_seen_packet_ = false;
};
} // namespace webrtc
#endif // MODULES_REMOTE_BITRATE_ESTIMATOR_PACKET_ARRIVAL_MAP_H_
| 39.606742 | 80 | 0.759433 |
3077328eb9e36b365606f27447e4acfb19f93796 | 8,365 | h | C | src/TNL/Meshes/GridDetails/GridTraverser.h | grinisrit/tnl-dev | 4403b2dca895e2c32636395d6f1c1210c7afcefd | [
"MIT"
] | null | null | null | src/TNL/Meshes/GridDetails/GridTraverser.h | grinisrit/tnl-dev | 4403b2dca895e2c32636395d6f1c1210c7afcefd | [
"MIT"
] | null | null | null | src/TNL/Meshes/GridDetails/GridTraverser.h | grinisrit/tnl-dev | 4403b2dca895e2c32636395d6f1c1210c7afcefd | [
"MIT"
] | null | null | null | // Copyright (c) 2004-2022 Tomáš Oberhuber et al.
//
// This file is part of TNL - Template Numerical Library (https://tnl-project.org/)
//
// SPDX-License-Identifier: MIT
#pragma once
#include <TNL/Meshes/Grid.h>
#include <TNL/Pointers/SharedPointer.h>
namespace TNL {
namespace Meshes {
/****
* This is only a helper class for Traverser specializations for Grid.
*/
template< typename Grid >
class GridTraverser
{};
enum GridTraverserMode
{
synchronousMode,
asynchronousMode
};
/****
* 1D grid, Devices::Host
*/
template< typename Real, typename Index >
class GridTraverser< Meshes::Grid< 1, Real, Devices::Host, Index > >
{
public:
using GridType = Meshes::Grid< 1, Real, Devices::Host, Index >;
using GridPointer = Pointers::SharedPointer< GridType >;
using RealType = Real;
using DeviceType = Devices::Host;
using IndexType = Index;
using CoordinatesType = typename GridType::CoordinatesType;
template< typename GridEntity, typename EntitiesProcessor, typename UserData, bool processOnlyBoundaryEntities >
static void
processEntities( const GridPointer& gridPointer,
const CoordinatesType& begin,
const CoordinatesType& end,
UserData& userData,
GridTraverserMode mode = synchronousMode,
const int& stream = 0 );
};
/****
* 1D grid, Devices::Cuda
*/
template< typename Real, typename Index >
class GridTraverser< Meshes::Grid< 1, Real, Devices::Cuda, Index > >
{
public:
using GridType = Meshes::Grid< 1, Real, Devices::Cuda, Index >;
using GridPointer = Pointers::SharedPointer< GridType >;
using RealType = Real;
using DeviceType = Devices::Cuda;
using IndexType = Index;
using CoordinatesType = typename GridType::CoordinatesType;
template< typename GridEntity, typename EntitiesProcessor, typename UserData, bool processOnlyBoundaryEntities >
static void
processEntities( const GridPointer& gridPointer,
const CoordinatesType& begin,
const CoordinatesType& end,
UserData& userData,
GridTraverserMode mode = synchronousMode,
const int& stream = 0 );
};
/****
* 2D grid, Devices::Host
*/
template< typename Real, typename Index >
class GridTraverser< Meshes::Grid< 2, Real, Devices::Host, Index > >
{
public:
using GridType = Meshes::Grid< 2, Real, Devices::Host, Index >;
using GridPointer = Pointers::SharedPointer< GridType >;
using RealType = Real;
using DeviceType = Devices::Host;
using IndexType = Index;
using CoordinatesType = typename GridType::CoordinatesType;
template< typename GridEntity,
typename EntitiesProcessor,
typename UserData,
bool processOnlyBoundaryEntities,
int XOrthogonalBoundary = 1,
int YOrthogonalBoundary = 1,
typename... GridEntityParameters >
static void
processEntities( const GridPointer& gridPointer,
const CoordinatesType& begin,
const CoordinatesType& end,
UserData& userData,
// FIXME: hack around nvcc bug (error: default argument not at end of parameter list)
// GridTraverserMode mode = synchronousMode,
GridTraverserMode mode,
// const int& stream = 0,
const int& stream,
// gridEntityParameters are passed to GridEntity's constructor
// (i.e. orientation and basis for faces)
const GridEntityParameters&... gridEntityParameters );
};
/****
* 2D grid, Devices::Cuda
*/
template< typename Real, typename Index >
class GridTraverser< Meshes::Grid< 2, Real, Devices::Cuda, Index > >
{
public:
using GridType = Meshes::Grid< 2, Real, Devices::Cuda, Index >;
using GridPointer = Pointers::SharedPointer< GridType >;
using RealType = Real;
using DeviceType = Devices::Cuda;
using IndexType = Index;
using CoordinatesType = typename GridType::CoordinatesType;
template< typename GridEntity,
typename EntitiesProcessor,
typename UserData,
bool processOnlyBoundaryEntities,
int XOrthogonalBoundary = 1,
int YOrthogonalBoundary = 1,
typename... GridEntityParameters >
static void
processEntities( const GridPointer& gridPointer,
const CoordinatesType& begin,
const CoordinatesType& end,
UserData& userData,
// FIXME: hack around nvcc bug (error: default argument not at end of parameter list)
// GridTraverserMode mode = synchronousMode,
GridTraverserMode mode,
// const int& stream = 0,
const int& stream,
// gridEntityParameters are passed to GridEntity's constructor
// (i.e. orientation and basis for faces)
const GridEntityParameters&... gridEntityParameters );
};
/****
* 3D grid, Devices::Host
*/
template< typename Real, typename Index >
class GridTraverser< Meshes::Grid< 3, Real, Devices::Host, Index > >
{
public:
using GridType = Meshes::Grid< 3, Real, Devices::Host, Index >;
using GridPointer = Pointers::SharedPointer< GridType >;
using RealType = Real;
using DeviceType = Devices::Host;
using IndexType = Index;
using CoordinatesType = typename GridType::CoordinatesType;
template< typename GridEntity,
typename EntitiesProcessor,
typename UserData,
bool processOnlyBoundaryEntities,
int XOrthogonalBoundary = 1,
int YOrthogonalBoundary = 1,
int ZOrthogonalBoundary = 1,
typename... GridEntityParameters >
static void
processEntities( const GridPointer& gridPointer,
const CoordinatesType& begin,
const CoordinatesType& end,
UserData& userData,
// FIXME: hack around nvcc bug (error: default argument not at end of parameter list)
// GridTraverserMode mode = synchronousMode,
GridTraverserMode mode,
// const int& stream = 0,
const int& stream,
// gridEntityParameters are passed to GridEntity's constructor
// (i.e. orientation and basis for faces and edges)
const GridEntityParameters&... gridEntityParameters );
};
/****
* 3D grid, Devices::Cuda
*/
template< typename Real, typename Index >
class GridTraverser< Meshes::Grid< 3, Real, Devices::Cuda, Index > >
{
public:
using GridType = Meshes::Grid< 3, Real, Devices::Cuda, Index >;
using GridPointer = Pointers::SharedPointer< GridType >;
using RealType = Real;
using DeviceType = Devices::Cuda;
using IndexType = Index;
using CoordinatesType = typename GridType::CoordinatesType;
template< typename GridEntity,
typename EntitiesProcessor,
typename UserData,
bool processOnlyBoundaryEntities,
int XOrthogonalBoundary = 1,
int YOrthogonalBoundary = 1,
int ZOrthogonalBoundary = 1,
typename... GridEntityParameters >
static void
processEntities( const GridPointer& gridPointer,
const CoordinatesType& begin,
const CoordinatesType& end,
UserData& userData,
// FIXME: hack around nvcc bug (error: default argument not at end of parameter list)
// GridTraverserMode mode = synchronousMode,
GridTraverserMode mode,
// const int& stream = 0,
const int& stream,
// gridEntityParameters are passed to GridEntity's constructor
// (i.e. orientation and basis for faces and edges)
const GridEntityParameters&... gridEntityParameters );
};
} // namespace Meshes
} // namespace TNL
#include <TNL/Meshes/GridDetails/GridTraverser_1D.hpp>
#include <TNL/Meshes/GridDetails/GridTraverser_2D.hpp>
#include <TNL/Meshes/GridDetails/GridTraverser_3D.hpp>
| 36.688596 | 115 | 0.624029 |
d6b24f23d78d15b7e425ecff44a31c1a41f364cb | 4,583 | h | C | stage-3/tree.h | LucasHagen/compilers | d60417b0611782b47cef633fbebba95ddeba4408 | [
"MIT"
] | null | null | null | stage-3/tree.h | LucasHagen/compilers | d60417b0611782b47cef633fbebba95ddeba4408 | [
"MIT"
] | null | null | null | stage-3/tree.h | LucasHagen/compilers | d60417b0611782b47cef633fbebba95ddeba4408 | [
"MIT"
] | 1 | 2021-04-17T22:51:45.000Z | 2021-04-17T22:51:45.000Z | #ifndef TREE_H
#define TREE_H
/*
Authors:
- Gabriel Pakulski da Silva - 00274701
- Lucas Sonntag Hagen - 00274698
*/
#include "lexeme.h"
#define NODE_TYPE_TER_OP 0
#define NODE_TYPE_BIN_OP 1
#define NODE_TYPE_UN_OP 2
#define NODE_TYPE_IF 3
#define NODE_TYPE_FOR 4
#define NODE_TYPE_WHILE 5
#define NODE_TYPE_FUNC_CALL 6
#define NODE_TYPE_FUNC_DECL 7
#define NODE_TYPE_VAR_ACCESS 8
#define NODE_TYPE_VAR_DECL 9
#define NODE_TYPE_VAR_ATTR 10
#define NODE_TYPE_INPUT 11
#define NODE_TYPE_OUTPUT 12
#define NODE_TYPE_SHIFT_LEFT 13
#define NODE_TYPE_SHIFT_RIGHT 14
#define NODE_TYPE_RETURN 15
#define NODE_TYPE_BREAK 16
#define NODE_TYPE_CONTINUE 17
#define NODE_TYPE_LITERAL 18
#define NODE_TYPE_FUNC_PARAM 19
#define NODE_TYPE_GLOBAL_VAR_DECL 20
#define NODE_TYPE_COMMAND_BLOCK 21
struct node_command_block {
struct node* command;
};
struct node_if {
struct node* condition;
struct node* n_true;
struct node* n_false;
};
struct node_bin_op {
struct lexeme* op;
struct node* left;
struct node* right;
};
struct node_un_op {
struct lexeme* op;
struct node* operand;
};
struct node_for {
struct node* setup;
struct node* condition;
struct node* increment;
struct node* code;
};
struct node_while {
struct node* condition;
struct node* code;
};
struct node_call_access {
struct lexeme* identifier;
struct node* index_or_param;
};
struct node_func_decl {
struct lexeme* identifier;
struct node* param;
struct node* code;
struct lexeme* type;
int is_static;
};
struct node_var_decl {
struct lexeme* identifier;
struct node* size;
struct lexeme* type;
int is_static;
int is_const;
struct node* value;
};
struct node_var_attr {
struct lexeme* identifier;
struct node* index;
struct node* value;
};
struct node_io {
struct node* params;
};
struct node_shift {
struct node* var;
struct node* count;
};
struct node_literal {
struct lexeme* literal;
};
typedef struct node {
int type;
struct node* seq;
union {
struct node_if n_if;
struct node_bin_op n_bin_op;
struct node_un_op n_un_op;
struct node_for n_for;
struct node_while n_while;
struct node_call_access n_call_or_access;
struct node_func_decl n_func_decl;
struct node_var_decl n_var_decl;
struct node_var_attr n_var_attr;
struct node_io n_io;
struct node_shift n_shift;
struct node_literal n_literal;
struct node_command_block n_cmd_block;
};
} Node;
/**
* Creates a new node structure and allocates the nedded memory
*
* @param lexeme Main Lexeme
*/
Node* new_node(int type);
/**
* Frees memory previously allocated to the AST structure
*
* @param arvore AST Pointer
*/
void free_tree(Node* root);
/**
* Frees memory allocated for a Lexeme
*
* @param lex Lexeme Pointer
* @return Allways 0, to override old pointer
*/
int free_lexeme(Lexeme* lex);
/**
* Prints a Lexeme's value
*
* @param lex Lexeme
*/
void free_node(Node* node);
// ===== CREATE SPECIFIC NODES FOR EACH THING =====
struct node* create_node_ter_op(Node* condition, Node* ifTrue, Node* ifFalse);
struct node* create_node_bin_op(Lexeme* op, Node* left, Node* right);
struct node* create_node_un_op(Lexeme* op, Node* operand);
struct node* create_node_if(Node* condition, Node* ifTrue, Node* ifFalse);
struct node* create_node_for(Node* setup, Node* condition, Node* increment, Node* code);
struct node* create_node_while(Node* condition, Node* code);
struct node* create_node_func_call(Lexeme* identifier, Node* parameters);
struct node* create_node_func_decl(Lexeme* identifier, Lexeme* type, int is_static, Node* parameters, Node* code);
struct node* create_node_func_param(Lexeme* identifier, Lexeme* type, int is_const);
struct node* create_node_var_access(Lexeme* identifier, Node* index);
struct node* create_node_var_decl(Lexeme* identifier, Node* size, Lexeme* type, int is_static, int is_const, Node* value);
struct node* create_node_global_var_decl(Lexeme* identifier, Node* size, Lexeme* type, int is_static, Node* value);
struct node* create_node_var_attr(Lexeme* identifier, Node* index, Node* value);
struct node* create_node_input(Node* input);
struct node* create_node_output(Node* output);
struct node* create_node_shift_left();
struct node* create_node_shift_right();
struct node* create_node_return(Node* expression);
struct node* create_node_break();
struct node* create_node_continue();
struct node* create_node_literal(Lexeme* value);
struct node* create_node_command_block(Node* first_command);
#endif // TREE_H
| 24.248677 | 122 | 0.744927 |
d098659b147505ae1ee0aafa7e72ac29aaed7913 | 4,464 | h | C | src/nbytes.h | LostinAllThatCode/nBytes | eba05cd9fa886ed48877efc70491e4e0594bb302 | [
"MIT"
] | null | null | null | src/nbytes.h | LostinAllThatCode/nBytes | eba05cd9fa886ed48877efc70491e4e0594bb302 | [
"MIT"
] | null | null | null | src/nbytes.h | LostinAllThatCode/nBytes | eba05cd9fa886ed48877efc70491e4e0594bb302 | [
"MIT"
] | null | null | null | #ifndef INCLUDE_GUARD_NBYTES_H
#define INCLUDE_GUARD_NBYTES_H
#define NBYTES_DEBUGGING 1
// C-Standard library stuff
#define _CRT_SECURE_NO_WARNINGS
#include <math.h>
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdarg.h>
#include <stdlib.h>
#include <assert.h>
#include <string.h>
#include <inttypes.h>
#include <time.h>
#include "shared.c"
#include "math.c"
#define STB_RECT_PACK_IMPLEMENTATION
#include "stb/stb_rect_pack.h"
#define STB_TRUETYPE_IMPLEMENTATION
#include "stb/stb_truetype.h"
#define STB_IMAGE_WRITE_IMPLEMENTATION
#include "stb/stb_image_write.h"
#define STB_IMAGE_IMPLEMENTATION
#include "stb/stb_image.h"
#include "fonts.c"
#include "keys.h"
#include "resman.h"
typedef enum EventType {
EVENT_NONE,
EVENT_KEY_DOWN,
EVENT_KEY_UP,
EVENT_MOUSE_DOWN,
EVENT_MOUSE_UP,
EVENT_MOUSE_MOVE,
EVENT_HOTKEY_PRESSED,
EVENT_FILE_ADDED,
EVENT_FILE_REMOVED,
EVENT_FILE_CONTENT_CHANGED,
} EventType;
typedef struct Event {
EventType type;
union {
struct {
int vk;
int repeat;
bool down;
} key;
struct {
int btn;
bool down;
int2 pos;
} mouse;
struct {
int id;
int keymod;
} hotkey;
struct {
const char *name;
} file;
};
} Event;
typedef struct Mouse {
int2 screen;
int2 relative;
int2 delta;
int wheel, wheel_delta;
struct {
int2 screen;
int2 relative;
int2 delta;
int wheel, wheel_delta;
} prev_state;
} Mouse;
typedef struct Time {
int ticks_per_sec;
int start_ticks;
int delta_ticks;
int delta_nsecs;
int delta_usecs;
int delta_msecs;
float delta_secs;
uint64_t ticks;
uint64_t nsecs;
uint64_t usecs;
uint64_t msecs;
double secs;
} Time;
typedef struct Display {
int dpi;
int2 size;
int refresh_rate;
} Display;
typedef struct Window {
bool hidden;
bool focus;
bool borderless_fullscreen;
bool focused;
bool resized;
bool moved;
int2 size;
int2 pos;
const char *title;
struct {
bool vsync;
/* Changes to the following variables will have no effect after initialization of the window */
int major;
int minor;
int core_profile;
int debug;
const char *debug_msg;
int debug_msg_len;
} opengl;
struct {
bool hidden;
bool focus;
bool borderless_fullscreen;
int2 size;
int2 pos;
const char *title;
struct {
bool vsync;
} opengl;
} prev_state;
} Window;
#define NBYTES_DEFAULT_OPENGL_MAJOR 3
#define NBYTES_DEFAULT_OPENGL_MINOR 3
#define NBYTES_DEFAULT_WINDOW_POS 0x80000000
#define NBYTES_DEFAULT_WINDOW_WIDTH 800
#define NBYTES_DEFAULT_WINDOW_HEIGHT 600
#define NBYTES_DEFAULT_TITLE "nBytes"
#define NBYTES_NUM_MAX_EVENTS 512
#define NBYTES_NUM_MAX_KEYS 256
typedef struct App {
bool quit;
int num_updates;
Event events[NBYTES_NUM_MAX_EVENTS];
int num_events;
int keymod;
Keystate keys[NBYTES_NUM_MAX_KEYS];
Time time;
Mouse mouse;
Display display;
Window window;
ResourceManager rsm;
const char *error;
} App;
extern App app;
#if defined OS_WINDOWS
#include "win32_platform.c"
#include "win32_app.c"
#include "win32_resman.c"
#elif defined OS_LINUX
#error Implementation missing! @TODO: OS_LINUX
#else
#error Fatal Error: This platform is not supported or not identified as a supported one!
#endif
bool
nbytes_update()
{
if(app.quit) {
nbytes_free_window();
nbytes_update_events();
return false;
} else {
nbytes_update_rsm();
nbytes_update_events();
nbytes_update_window();
nbytes_update_time();
app.num_updates++;
return !app.quit;
}
}
bool
nbytes_init()
{
#if NBYTES_DEBUGGING
nbytes_init_debugging();
#endif
if(!nbytes_init_window()) { return false; }
if(!nbytes_init_display()) { return false; };
if(!nbytes_init_time()) { return false; };
if(!nbytes_init_rsm()) { return false; }
return nbytes_update();
}
void
nbytes_check_prefined_hotkeys()
{
// exit application
if(app.keys[KEY_ESC].pressed) {
app.quit = true;
}
// toggle vsync
if(app.keys[KEY_V].pressed) {
app.window.opengl.vsync = !app.window.opengl.vsync;
}
// toggle borderless fullscreen
if(app.keys[KEY_F].pressed) {
app.window.borderless_fullscreen = !app.window.borderless_fullscreen;
}
}
void
nbytes_limit_framerate(uint64_t next_tick_us)
{
if(!app.window.opengl.vsync) {
int64_t ms_sleep = (int64_t)(next_tick_us - app.time.usecs) / 1000;
if (ms_sleep > 0) {
#if OS_WINDOWS
// TODO: @Cleanup
timeBeginPeriod(1);
Sleep(ms_sleep);
timeEndPeriod(1);
#endif
}
}
}
#endif
| 17.302326 | 97 | 0.728047 |
a929f5f4f361b996143bef47c01ad3512bf89c3d | 5,580 | h | C | Samples/DeviceProtectionSample/utils.h | jeremypoulter/DeveloperToolsForUPnP | 7334c4d978063ae0816c9089e4fe5fe892c31e16 | [
"Apache-2.0"
] | 5 | 2015-10-09T08:50:29.000Z | 2018-04-06T05:51:20.000Z | Samples/DeviceProtectionSample/utils.h | jeremypoulter/DeveloperToolsForUPnP | 7334c4d978063ae0816c9089e4fe5fe892c31e16 | [
"Apache-2.0"
] | 1 | 2016-03-01T11:33:15.000Z | 2016-03-07T10:33:59.000Z | Samples/DeviceProtectionSample/utils.h | jeremypoulter/DeveloperToolsForUPnP | 7334c4d978063ae0816c9089e4fe5fe892c31e16 | [
"Apache-2.0"
] | 10 | 2015-04-01T16:36:36.000Z | 2021-11-01T08:30:09.000Z | /*
Copyright 2006 - 2011 Intel Corporation
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef __MeshUtils__
#define __MeshUtils__
#include "ILibParsers.h"
#include "ILibWebClient.h"
#include "ILibWebServer.h"
#include <openssl/pem.h>
//#include <openssl/err.h>
#include <openssl/pkcs7.h>
#include <openssl/pkcs12.h>
#include <openssl/conf.h>
#include <openssl/x509v3.h>
#include <openssl/engine.h>
#if defined(WIN32)
#define snprintf _snprintf
#endif
// Debugging features
#if defined(_DEBUG)
char spareDebugMemory[4000];
int spareDebugLen;
// Display & log
//#define MSG(x) printf("%s",x);//mdb_addevent(x, (int)strlen(x));
//#define MSG2(t,x) spareDebugLen = snprintf(spareDebugMemory,4000,t,x);printf("%s",spareDebugMemory);//mdb_addevent(spareDebugMemory, spareDebugLen);
//#define MSG3(t,x,y) spareDebugLen = snprintf(spareDebugMemory,4000,t,x,y);printf("%s",spareDebugMemory);//mdb_addevent(spareDebugMemory, spareDebugLen);
//#define MSG4(t,x,y,z) spareDebugLen = snprintf(spareDebugMemory,4000,t,x,y,z);printf("%s",spareDebugMemory);//mdb_addevent(spareDebugMemory, spareDebugLen);
//#define MSG5(t,x,y,z,a) spareDebugLen = snprintf(spareDebugMemory,4000,t,x,y,z,a);printf("%s",spareDebugMemory);//mdb_addevent(spareDebugMemory, spareDebugLen);
// Display only
#define MSG(x) printf(x);fflush(NULL);
#define MSG2(t,x) printf(t,x);fflush(NULL);
#define MSG3(t,x,y) printf(t,x,y);fflush(NULL);
#define MSG4(t,x,y,z) printf(t,x,y,z);fflush(NULL);
#define MSG5(t,x,y,z,a) printf(t,x,y,z,a);fflush(NULL);
#define DEBUGSTATEMENT(x) x
#if defined(_POSIX)
//#include <mcheck.h>
#endif
#else
#define MSG(x)
#define MSG2(t,x)
#define MSG3(t,x,y)
#define MSG4(t,x,y,z)
#define MSG5(t,x,y,z,a)
#define DEBUGSTATEMENT(x)
#endif
#define UTIL_HASHSIZE 32
#define MAX_TOKEN_SIZE 1024
#define SMALL_TOKEN_SIZE 256
#define NONCE_SIZE 32
#define HALF_NONCE_SIZE 16
enum CERTIFICATE_TYPES
{
CERTIFICATE_ROOT = 1,
CERTIFICATE_TLS_SERVER = 2,
CERTIFICATE_TLS_CLIENT = 3,
};
// Certificate structure
struct util_cert
{
X509 *x509;
EVP_PKEY *pkey;
};
// General methods
void util_openssl_init();
void util_openssl_uninit();
void util_free(char* ptr);
void util_tohex(char* data, int len, char* out);
int util_hexToint(char *hexString, int hexStringLength);
void util_startChronometer();
long util_readChronometer();
unsigned long util_gettime();
// File and data methods
//int util_compress(char* inbuf, unsigned int inbuflen, char** outbuf, unsigned int headersize);
//int util_decompress(char* inbuf, unsigned int inbuflen, char** outbuf, unsigned int headersize);
size_t util_writefile(char* filename, char* data, int datalen);
size_t util_readfile(char* filename, char** data);
int util_deletefile(char* filename);
#ifdef _POSIX
int util_readfile2(char* filename, char** data);
#endif
// Certificate & crypto methods
void util_freecert(struct util_cert* cert);
int util_to_p12(struct util_cert cert, char *password, char** data);
int util_from_p12(char* data, int datalen, char* password, struct util_cert* cert);
int util_to_cer(struct util_cert cert, char** data);
int util_from_cer(char* data, int datalen, struct util_cert* cert);
int util_mkCert(struct util_cert *rootcert, struct util_cert* cert, int bits, int days, char* name, enum CERTIFICATE_TYPES certtype);
void util_printcert(struct util_cert cert);
void util_printcert_pk(struct util_cert cert);
void util_sendcert(struct ILibWebServer_Session *sender, struct util_cert cert);
void util_md5(char* data, int datalen, char* result);
void util_md5hex(char* data, int datalen, char *out);
void util_sha256(char* data, int datalen, char* result);
int util_sha256file(char* filename, char* result);
int util_keyhash(struct util_cert cert, char* result);
int util_keyhash2(X509* cert, char* result);
int util_sign(struct util_cert cert, char* data, int datalen, char** signature);
int util_verify(char* signature, int signlen, struct util_cert* cert, char** data);
int util_encrypt(struct util_cert cert, char* data, int datalen, char** encdata);
int util_encrypt2(STACK_OF(X509) *certs, char* data, int datalen, char** encdata);
int util_decrypt(char* encdata, int encdatalen, struct util_cert cert, char** data);
void util_random(int length, char* result);
void util_randomtext(int length, char* result);
// Symetric Crypto methods
void util_nodesessionkey(char* nodeid, char* key);
int util_cipher(char* key, unsigned int iv, char* nodeid, char* data, int datalen, char** result, int sendresponsekey);
int util_decipher(char* data, int datalen, char** result, char* nodeid);
void util_genusagekey(char* inkey, char* outkey, char usage);
// Network security methods
int util_antiflood(int rate, int interval);
int util_ExtractWwwAuthenticate(char *wwwAuthenticate, void *request);
void util_GenerateAuthorizationHeader(void *request, char *requestType, char *uri, char *authorization, char* cnonce);
unsigned int util_getiv();
int util_checkiv(unsigned int iv);
#endif
| 37.959184 | 166 | 0.745341 |
655ee00ad09ffebc8f045f225c01b9182570b78c | 11,084 | c | C | qemu-shack-ibtc/roms/seabios/src/cdrom.c | silverneko/HWs | 84d19316e01c3bb7b2fcf1fa9ad3dff99c01b543 | [
"MIT"
] | null | null | null | qemu-shack-ibtc/roms/seabios/src/cdrom.c | silverneko/HWs | 84d19316e01c3bb7b2fcf1fa9ad3dff99c01b543 | [
"MIT"
] | null | null | null | qemu-shack-ibtc/roms/seabios/src/cdrom.c | silverneko/HWs | 84d19316e01c3bb7b2fcf1fa9ad3dff99c01b543 | [
"MIT"
] | 1 | 2018-05-15T00:12:19.000Z | 2018-05-15T00:12:19.000Z | // Support for booting from cdroms (the "El Torito" spec).
//
// Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
// Copyright (C) 2002 MandrakeSoft S.A.
//
// This file may be distributed under the terms of the GNU LGPLv3 license.
#include "disk.h" // cdrom_13
#include "util.h" // memset
#include "bregs.h" // struct bregs
#include "biosvar.h" // GET_EBDA
#include "ata.h" // ATA_CMD_REQUEST_SENSE
#include "blockcmd.h" // CDB_CMD_REQUEST_SENSE
/****************************************************************
* CD emulation
****************************************************************/
struct drive_s *cdemu_drive_gf VAR16VISIBLE;
u8 *cdemu_buf_fl VAR16VISIBLE;
static int
cdemu_read(struct disk_op_s *op)
{
u16 ebda_seg = get_ebda_seg();
struct drive_s *drive_g;
drive_g = GLOBALFLAT2GLOBAL(GET_EBDA2(ebda_seg, cdemu.emulated_drive_gf));
struct disk_op_s dop;
dop.drive_g = drive_g;
dop.command = op->command;
dop.lba = GET_EBDA2(ebda_seg, cdemu.ilba) + op->lba / 4;
int count = op->count;
op->count = 0;
u8 *cdbuf_fl = GET_GLOBAL(cdemu_buf_fl);
if (op->lba & 3) {
// Partial read of first block.
dop.count = 1;
dop.buf_fl = cdbuf_fl;
int ret = process_op(&dop);
if (ret)
return ret;
u8 thiscount = 4 - (op->lba & 3);
if (thiscount > count)
thiscount = count;
count -= thiscount;
memcpy_fl(op->buf_fl, cdbuf_fl + (op->lba & 3) * 512, thiscount * 512);
op->buf_fl += thiscount * 512;
op->count += thiscount;
dop.lba++;
}
if (count > 3) {
// Read n number of regular blocks.
dop.count = count / 4;
dop.buf_fl = op->buf_fl;
int ret = process_op(&dop);
op->count += dop.count * 4;
if (ret)
return ret;
u8 thiscount = count & ~3;
count &= 3;
op->buf_fl += thiscount * 512;
dop.lba += thiscount / 4;
}
if (count) {
// Partial read on last block.
dop.count = 1;
dop.buf_fl = cdbuf_fl;
int ret = process_op(&dop);
if (ret)
return ret;
u8 thiscount = count;
memcpy_fl(op->buf_fl, cdbuf_fl, thiscount * 512);
op->count += thiscount;
}
return DISK_RET_SUCCESS;
}
int
process_cdemu_op(struct disk_op_s *op)
{
if (!CONFIG_CDROM_EMU)
return 0;
switch (op->command) {
case CMD_READ:
return cdemu_read(op);
case CMD_WRITE:
case CMD_FORMAT:
return DISK_RET_EWRITEPROTECT;
case CMD_VERIFY:
case CMD_RESET:
case CMD_SEEK:
case CMD_ISREADY:
return DISK_RET_SUCCESS;
default:
op->count = 0;
return DISK_RET_EPARAM;
}
}
void
cdemu_setup(void)
{
if (!CONFIG_CDROM_EMU)
return;
cdemu_drive_gf = NULL;
cdemu_buf_fl = NULL;
if (!Drives.cdcount)
return;
struct drive_s *drive_g = malloc_fseg(sizeof(*drive_g));
u8 *buf = malloc_low(CDROM_SECTOR_SIZE);
if (!drive_g || !buf) {
warn_noalloc();
free(drive_g);
free(buf);
return;
}
cdemu_drive_gf = drive_g;
cdemu_buf_fl = buf;
memset(drive_g, 0, sizeof(*drive_g));
drive_g->type = DTYPE_CDEMU;
drive_g->blksize = DISK_SECTOR_SIZE;
drive_g->sectors = (u64)-1;
}
struct eltorito_s {
u8 size;
u8 media;
u8 emulated_drive;
u8 controller_index;
u32 ilba;
u16 device_spec;
u16 buffer_segment;
u16 load_segment;
u16 sector_count;
u8 cylinders;
u8 sectors;
u8 heads;
};
#define SET_INT13ET(regs,var,val) \
SET_FARVAR((regs)->ds, ((struct eltorito_s*)((regs)->si+0))->var, (val))
// ElTorito - Terminate disk emu
void
cdemu_134b(struct bregs *regs)
{
// FIXME ElTorito Hardcoded
u16 ebda_seg = get_ebda_seg();
SET_INT13ET(regs, size, 0x13);
SET_INT13ET(regs, media, GET_EBDA2(ebda_seg, cdemu.media));
SET_INT13ET(regs, emulated_drive
, GET_EBDA2(ebda_seg, cdemu.emulated_extdrive));
struct drive_s *drive_gf = GET_EBDA2(ebda_seg, cdemu.emulated_drive_gf);
u8 cntl_id = 0;
if (drive_gf)
cntl_id = GET_GLOBALFLAT(drive_gf->cntl_id);
SET_INT13ET(regs, controller_index, cntl_id / 2);
SET_INT13ET(regs, device_spec, cntl_id % 2);
SET_INT13ET(regs, ilba, GET_EBDA2(ebda_seg, cdemu.ilba));
SET_INT13ET(regs, buffer_segment, GET_EBDA2(ebda_seg, cdemu.buffer_segment));
SET_INT13ET(regs, load_segment, GET_EBDA2(ebda_seg, cdemu.load_segment));
SET_INT13ET(regs, sector_count, GET_EBDA2(ebda_seg, cdemu.sector_count));
SET_INT13ET(regs, cylinders, GET_EBDA2(ebda_seg, cdemu.lchs.cylinders));
SET_INT13ET(regs, sectors, GET_EBDA2(ebda_seg, cdemu.lchs.spt));
SET_INT13ET(regs, heads, GET_EBDA2(ebda_seg, cdemu.lchs.heads));
// If we have to terminate emulation
if (regs->al == 0x00) {
// FIXME ElTorito Various. Should be handled accordingly to spec
SET_EBDA2(ebda_seg, cdemu.active, 0x00); // bye bye
// XXX - update floppy/hd count.
}
disk_ret(regs, DISK_RET_SUCCESS);
}
/****************************************************************
* CD booting
****************************************************************/
static int
atapi_is_ready(struct disk_op_s *op)
{
dprintf(6, "atapi_is_ready (drive=%p)\n", op->drive_g);
/* Retry READ CAPACITY for 5 seconds unless MEDIUM NOT PRESENT is
* reported by the device. If the device reports "IN PROGRESS",
* 30 seconds is added. */
struct cdbres_read_capacity info;
int in_progress = 0;
u64 end = calc_future_tsc(5000);
for (;;) {
if (check_tsc(end)) {
dprintf(1, "read capacity failed\n");
return -1;
}
int ret = cdb_read_capacity(op, &info);
if (!ret)
// Success
break;
struct cdbres_request_sense sense;
ret = cdb_get_sense(op, &sense);
if (ret)
// Error - retry.
continue;
// Sense succeeded.
if (sense.asc == 0x3a) { /* MEDIUM NOT PRESENT */
dprintf(1, "Device reports MEDIUM NOT PRESENT\n");
return -1;
}
if (sense.asc == 0x04 && sense.ascq == 0x01 && !in_progress) {
/* IN PROGRESS OF BECOMING READY */
printf("Waiting for device to detect medium... ");
/* Allow 30 seconds more */
end = calc_future_tsc(30000);
in_progress = 1;
}
}
u32 blksize = ntohl(info.blksize), sectors = ntohl(info.sectors);
if (blksize != GET_GLOBAL(op->drive_g->blksize)) {
printf("Unsupported sector size %u\n", blksize);
return -1;
}
dprintf(6, "sectors=%u\n", sectors);
printf("%dMB medium detected\n", sectors>>(20-11));
return 0;
}
int
cdrom_boot(int cdid)
{
struct disk_op_s dop;
memset(&dop, 0, sizeof(dop));
dop.drive_g = getDrive(EXTTYPE_CD, cdid);
if (!dop.drive_g)
return 1;
int ret = atapi_is_ready(&dop);
if (ret)
dprintf(1, "atapi_is_ready returned %d\n", ret);
// Read the Boot Record Volume Descriptor
u8 buffer[2048];
dop.lba = 0x11;
dop.count = 1;
dop.buf_fl = MAKE_FLATPTR(GET_SEG(SS), buffer);
ret = cdb_read(&dop);
if (ret)
return 3;
// Validity checks
if (buffer[0])
return 4;
if (strcmp((char*)&buffer[1], "CD001\001EL TORITO SPECIFICATION") != 0)
return 5;
// ok, now we calculate the Boot catalog address
u32 lba = *(u32*)&buffer[0x47];
// And we read the Boot Catalog
dop.lba = lba;
dop.count = 1;
ret = cdb_read(&dop);
if (ret)
return 7;
// Validation entry
if (buffer[0x00] != 0x01)
return 8; // Header
if (buffer[0x01] != 0x00)
return 9; // Platform
if (buffer[0x1E] != 0x55)
return 10; // key 1
if (buffer[0x1F] != 0xAA)
return 10; // key 2
// Initial/Default Entry
if (buffer[0x20] != 0x88)
return 11; // Bootable
u16 ebda_seg = get_ebda_seg();
u8 media = buffer[0x21];
SET_EBDA2(ebda_seg, cdemu.media, media);
SET_EBDA2(ebda_seg, cdemu.emulated_drive_gf, dop.drive_g);
u16 boot_segment = *(u16*)&buffer[0x22];
if (!boot_segment)
boot_segment = 0x07C0;
SET_EBDA2(ebda_seg, cdemu.load_segment, boot_segment);
SET_EBDA2(ebda_seg, cdemu.buffer_segment, 0x0000);
u16 nbsectors = *(u16*)&buffer[0x26];
SET_EBDA2(ebda_seg, cdemu.sector_count, nbsectors);
lba = *(u32*)&buffer[0x28];
SET_EBDA2(ebda_seg, cdemu.ilba, lba);
// And we read the image in memory
dop.lba = lba;
dop.count = DIV_ROUND_UP(nbsectors, 4);
dop.buf_fl = MAKE_FLATPTR(boot_segment, 0);
ret = cdb_read(&dop);
if (ret)
return 12;
if (media == 0) {
// No emulation requested - return success.
SET_EBDA2(ebda_seg, cdemu.emulated_extdrive, EXTSTART_CD + cdid);
return 0;
}
// Emulation of a floppy/harddisk requested
if (! CONFIG_CDROM_EMU || !cdemu_drive_gf)
return 13;
// Set emulated drive id and increase bios installed hardware
// number of devices
if (media < 4) {
// Floppy emulation
SET_EBDA2(ebda_seg, cdemu.emulated_extdrive, 0x00);
// XXX - get and set actual floppy count.
SETBITS_BDA(equipment_list_flags, 0x41);
switch (media) {
case 0x01: // 1.2M floppy
SET_EBDA2(ebda_seg, cdemu.lchs.spt, 15);
SET_EBDA2(ebda_seg, cdemu.lchs.cylinders, 80);
SET_EBDA2(ebda_seg, cdemu.lchs.heads, 2);
break;
case 0x02: // 1.44M floppy
SET_EBDA2(ebda_seg, cdemu.lchs.spt, 18);
SET_EBDA2(ebda_seg, cdemu.lchs.cylinders, 80);
SET_EBDA2(ebda_seg, cdemu.lchs.heads, 2);
break;
case 0x03: // 2.88M floppy
SET_EBDA2(ebda_seg, cdemu.lchs.spt, 36);
SET_EBDA2(ebda_seg, cdemu.lchs.cylinders, 80);
SET_EBDA2(ebda_seg, cdemu.lchs.heads, 2);
break;
}
} else {
// Harddrive emulation
SET_EBDA2(ebda_seg, cdemu.emulated_extdrive, 0x80);
SET_BDA(hdcount, GET_BDA(hdcount) + 1);
// Peak at partition table to get chs.
struct mbr_s *mbr = (void*)0;
u8 sptcyl = GET_FARVAR(boot_segment, mbr->partitions[0].last.sptcyl);
u8 cyllow = GET_FARVAR(boot_segment, mbr->partitions[0].last.cyllow);
u8 heads = GET_FARVAR(boot_segment, mbr->partitions[0].last.heads);
SET_EBDA2(ebda_seg, cdemu.lchs.spt, sptcyl & 0x3f);
SET_EBDA2(ebda_seg, cdemu.lchs.cylinders
, ((sptcyl<<2)&0x300) + cyllow + 1);
SET_EBDA2(ebda_seg, cdemu.lchs.heads, heads + 1);
}
// everything is ok, so from now on, the emulation is active
SET_EBDA2(ebda_seg, cdemu.active, 0x01);
dprintf(6, "cdemu media=%d\n", media);
return 0;
}
| 29.091864 | 81 | 0.587062 |
b79ef84361fb5f6c74b747603d042ae26a9bff34 | 93 | c | C | t/testcases/before/declaration-comment-column.c | Linkerist/poem | 506685ca6628f6696e59ef30f9c2f67f3101ded5 | [
"MIT"
] | 1 | 2018-03-22T11:16:44.000Z | 2018-03-22T11:16:44.000Z | t/testcases/before/declaration-comment-column.c | Linkerist/poem | 506685ca6628f6696e59ef30f9c2f67f3101ded5 | [
"MIT"
] | null | null | null | t/testcases/before/declaration-comment-column.c | Linkerist/poem | 506685ca6628f6696e59ef30f9c2f67f3101ded5 | [
"MIT"
] | null | null | null | void function(void); // line comment
void function(void) // line comment
{
}
void main()
{
}
| 11.625 | 36 | 0.666667 |
a24deb96a0894e2a5e4042febbeba26b3bb2bd69 | 52,429 | h | C | ext/eigen/include/Eigen/src/SVD/BDCSVD.h | johannes-braun/graphics_utilities | 191772a3ff1c14eea74b9b5614b6226cf1f8abb7 | [
"MIT"
] | 87 | 2015-01-21T08:29:56.000Z | 2022-03-28T07:11:53.000Z | inc/Eigen3/Eigen/src/SVD/BDCSVD.h | lkeegan/blockCG | 2f7aad8c4ce24cf104b672b2ea9cbf573ffb8cdc | [
"MIT"
] | 9 | 2020-06-03T21:11:44.000Z | 2022-01-22T08:46:36.000Z | inc/Eigen3/Eigen/src/SVD/BDCSVD.h | lkeegan/blockCG | 2f7aad8c4ce24cf104b672b2ea9cbf573ffb8cdc | [
"MIT"
] | 54 | 2015-02-09T10:02:00.000Z | 2022-03-07T10:44:14.000Z | // This file is part of Eigen, a lightweight C++ template library
// for linear algebra.
//
// We used the "A Divide-And-Conquer Algorithm for the Bidiagonal SVD"
// research report written by Ming Gu and Stanley C.Eisenstat
// The code variable names correspond to the names they used in their
// report
//
// Copyright (C) 2013 Gauthier Brun <brun.gauthier@gmail.com>
// Copyright (C) 2013 Nicolas Carre <nicolas.carre@ensimag.fr>
// Copyright (C) 2013 Jean Ceccato <jean.ceccato@ensimag.fr>
// Copyright (C) 2013 Pierre Zoppitelli <pierre.zoppitelli@ensimag.fr>
// Copyright (C) 2013 Jitse Niesen <jitse@maths.leeds.ac.uk>
// Copyright (C) 2014-2017 Gael Guennebaud <gael.guennebaud@inria.fr>
//
// Source Code Form is subject to the terms of the Mozilla
// Public License v. 2.0. If a copy of the MPL was not distributed
// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.
#ifndef EIGEN_BDCSVD_H
#define EIGEN_BDCSVD_H
// #define EIGEN_BDCSVD_DEBUG_VERBOSE
// #define EIGEN_BDCSVD_SANITY_CHECKS
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
#undef eigen_internal_assert
#define eigen_internal_assert(X) assert(X);
#endif
namespace Eigen {
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
IOFormat bdcsvdfmt(8, 0, ", ", "\n", " [", "]");
#endif
template<typename _MatrixType> class BDCSVD;
namespace internal {
template<typename _MatrixType>
struct traits<BDCSVD<_MatrixType> >
{
typedef _MatrixType MatrixType;
};
} // end namespace internal
/** \ingroup SVD_Module
*
*
* \class BDCSVD
*
* \brief class Bidiagonal Divide and Conquer SVD
*
* \tparam _MatrixType the type of the matrix of which we are computing the SVD decomposition
*
* This class first reduces the input matrix to bi-diagonal form using class UpperBidiagonalization,
* and then performs a divide-and-conquer diagonalization. Small blocks are diagonalized using class JacobiSVD.
* You can control the switching size with the setSwitchSize() method, default is 16.
* For small matrice (<16), it is thus preferable to directly use JacobiSVD. For larger ones, BDCSVD is highly
* recommended and can several order of magnitude faster.
*
* \warning this algorithm is unlikely to provide accurate result when compiled with unsafe math optimizations.
* For instance, this concerns Intel's compiler (ICC), which performs such optimization by default unless
* you compile with the \c -fp-model \c precise option. Likewise, the \c -ffast-math option of GCC or clang will
* significantly degrade the accuracy.
*
* \sa class JacobiSVD
*/
template<typename _MatrixType>
class BDCSVD : public SVDBase<BDCSVD<_MatrixType> >
{
typedef SVDBase<BDCSVD> Base;
public:
using Base::rows;
using Base::cols;
using Base::computeU;
using Base::computeV;
typedef _MatrixType MatrixType;
typedef typename MatrixType::Scalar Scalar;
typedef typename NumTraits<typename MatrixType::Scalar>::Real RealScalar;
typedef typename NumTraits<RealScalar>::Literal Literal;
enum {
RowsAtCompileTime = MatrixType::RowsAtCompileTime,
ColsAtCompileTime = MatrixType::ColsAtCompileTime,
DiagSizeAtCompileTime = EIGEN_SIZE_MIN_PREFER_DYNAMIC(RowsAtCompileTime, ColsAtCompileTime),
MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,
MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime,
MaxDiagSizeAtCompileTime = EIGEN_SIZE_MIN_PREFER_FIXED(MaxRowsAtCompileTime, MaxColsAtCompileTime),
MatrixOptions = MatrixType::Options
};
typedef typename Base::MatrixUType MatrixUType;
typedef typename Base::MatrixVType MatrixVType;
typedef typename Base::SingularValuesType SingularValuesType;
typedef Matrix<Scalar, Dynamic, Dynamic, ColMajor> MatrixX;
typedef Matrix<RealScalar, Dynamic, Dynamic, ColMajor> MatrixXr;
typedef Matrix<RealScalar, Dynamic, 1> VectorType;
typedef Array<RealScalar, Dynamic, 1> ArrayXr;
typedef Array<Index,1,Dynamic> ArrayXi;
typedef Ref<ArrayXr> ArrayRef;
typedef Ref<ArrayXi> IndicesRef;
/** \brief Default Constructor.
*
* The default constructor is useful in cases in which the user intends to
* perform decompositions via BDCSVD::compute(const MatrixType&).
*/
BDCSVD() : m_algoswap(16), m_numIters(0)
{}
/** \brief Default Constructor with memory preallocation
*
* Like the default constructor but with preallocation of the internal data
* according to the specified problem size.
* \sa BDCSVD()
*/
BDCSVD(Index rows, Index cols, unsigned int computationOptions = 0)
: m_algoswap(16), m_numIters(0)
{
allocate(rows, cols, computationOptions);
}
/** \brief Constructor performing the decomposition of given matrix.
*
* \param matrix the matrix to decompose
* \param computationOptions optional parameter allowing to specify if you want full or thin U or V unitaries to be computed.
* By default, none is computed. This is a bit - field, the possible bits are #ComputeFullU, #ComputeThinU,
* #ComputeFullV, #ComputeThinV.
*
* Thin unitaries are only available if your matrix type has a Dynamic number of columns (for example MatrixXf). They also are not
* available with the (non - default) FullPivHouseholderQR preconditioner.
*/
BDCSVD(const MatrixType& matrix, unsigned int computationOptions = 0)
: m_algoswap(16), m_numIters(0)
{
compute(matrix, computationOptions);
}
~BDCSVD()
{
}
/** \brief Method performing the decomposition of given matrix using custom options.
*
* \param matrix the matrix to decompose
* \param computationOptions optional parameter allowing to specify if you want full or thin U or V unitaries to be computed.
* By default, none is computed. This is a bit - field, the possible bits are #ComputeFullU, #ComputeThinU,
* #ComputeFullV, #ComputeThinV.
*
* Thin unitaries are only available if your matrix type has a Dynamic number of columns (for example MatrixXf). They also are not
* available with the (non - default) FullPivHouseholderQR preconditioner.
*/
BDCSVD& compute(const MatrixType& matrix, unsigned int computationOptions);
/** \brief Method performing the decomposition of given matrix using current options.
*
* \param matrix the matrix to decompose
*
* This method uses the current \a computationOptions, as already passed to the constructor or to compute(const MatrixType&, unsigned int).
*/
BDCSVD& compute(const MatrixType& matrix)
{
return compute(matrix, this->m_computationOptions);
}
void setSwitchSize(int s)
{
eigen_assert(s>3 && "BDCSVD the size of the algo switch has to be greater than 3");
m_algoswap = s;
}
private:
void allocate(Index rows, Index cols, unsigned int computationOptions);
void divide(Index firstCol, Index lastCol, Index firstRowW, Index firstColW, Index shift);
void computeSVDofM(Index firstCol, Index n, MatrixXr& U, VectorType& singVals, MatrixXr& V);
void computeSingVals(const ArrayRef& col0, const ArrayRef& diag, const IndicesRef& perm, VectorType& singVals, ArrayRef shifts, ArrayRef mus);
void perturbCol0(const ArrayRef& col0, const ArrayRef& diag, const IndicesRef& perm, const VectorType& singVals, const ArrayRef& shifts, const ArrayRef& mus, ArrayRef zhat);
void computeSingVecs(const ArrayRef& zhat, const ArrayRef& diag, const IndicesRef& perm, const VectorType& singVals, const ArrayRef& shifts, const ArrayRef& mus, MatrixXr& U, MatrixXr& V);
void deflation43(Index firstCol, Index shift, Index i, Index size);
void deflation44(Index firstColu , Index firstColm, Index firstRowW, Index firstColW, Index i, Index j, Index size);
void deflation(Index firstCol, Index lastCol, Index k, Index firstRowW, Index firstColW, Index shift);
template<typename HouseholderU, typename HouseholderV, typename NaiveU, typename NaiveV>
void copyUV(const HouseholderU &householderU, const HouseholderV &householderV, const NaiveU &naiveU, const NaiveV &naivev);
void structured_update(Block<MatrixXr,Dynamic,Dynamic> A, const MatrixXr &B, Index n1);
static RealScalar secularEq(RealScalar x, const ArrayRef& col0, const ArrayRef& diag, const IndicesRef &perm, const ArrayRef& diagShifted, RealScalar shift);
protected:
MatrixXr m_naiveU, m_naiveV;
MatrixXr m_computed;
Index m_nRec;
ArrayXr m_workspace;
ArrayXi m_workspaceI;
int m_algoswap;
bool m_isTranspose, m_compU, m_compV;
using Base::m_singularValues;
using Base::m_diagSize;
using Base::m_computeFullU;
using Base::m_computeFullV;
using Base::m_computeThinU;
using Base::m_computeThinV;
using Base::m_matrixU;
using Base::m_matrixV;
using Base::m_isInitialized;
using Base::m_nonzeroSingularValues;
public:
int m_numIters;
}; //end class BDCSVD
// Method to allocate and initialize matrix and attributes
template<typename MatrixType>
void BDCSVD<MatrixType>::allocate(Eigen::Index rows, Eigen::Index cols, unsigned int computationOptions)
{
m_isTranspose = (cols > rows);
if (Base::allocate(rows, cols, computationOptions))
return;
m_computed = MatrixXr::Zero(m_diagSize + 1, m_diagSize );
m_compU = computeV();
m_compV = computeU();
if (m_isTranspose)
std::swap(m_compU, m_compV);
if (m_compU) m_naiveU = MatrixXr::Zero(m_diagSize + 1, m_diagSize + 1 );
else m_naiveU = MatrixXr::Zero(2, m_diagSize + 1 );
if (m_compV) m_naiveV = MatrixXr::Zero(m_diagSize, m_diagSize);
m_workspace.resize((m_diagSize+1)*(m_diagSize+1)*3);
m_workspaceI.resize(3*m_diagSize);
}// end allocate
template<typename MatrixType>
BDCSVD<MatrixType>& BDCSVD<MatrixType>::compute(const MatrixType& matrix, unsigned int computationOptions)
{
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "\n\n\n======================================================================================================================\n\n\n";
#endif
allocate(matrix.rows(), matrix.cols(), computationOptions);
using std::abs;
const RealScalar considerZero = (std::numeric_limits<RealScalar>::min)();
//**** step -1 - If the problem is too small, directly falls back to JacobiSVD and return
if(matrix.cols() < m_algoswap)
{
// FIXME this line involves temporaries
JacobiSVD<MatrixType> jsvd(matrix,computationOptions);
if(computeU()) m_matrixU = jsvd.matrixU();
if(computeV()) m_matrixV = jsvd.matrixV();
m_singularValues = jsvd.singularValues();
m_nonzeroSingularValues = jsvd.nonzeroSingularValues();
m_isInitialized = true;
return *this;
}
//**** step 0 - Copy the input matrix and apply scaling to reduce over/under-flows
RealScalar scale = matrix.cwiseAbs().maxCoeff();
if(scale==Literal(0)) scale = Literal(1);
MatrixX copy;
if (m_isTranspose) copy = matrix.adjoint()/scale;
else copy = matrix/scale;
//**** step 1 - Bidiagonalization
// FIXME this line involves temporaries
internal::UpperBidiagonalization<MatrixX> bid(copy);
//**** step 2 - Divide & Conquer
m_naiveU.setZero();
m_naiveV.setZero();
// FIXME this line involves a temporary matrix
m_computed.topRows(m_diagSize) = bid.bidiagonal().toDenseMatrix().transpose();
m_computed.template bottomRows<1>().setZero();
divide(0, m_diagSize - 1, 0, 0, 0);
//**** step 3 - Copy singular values and vectors
for (int i=0; i<m_diagSize; i++)
{
RealScalar a = abs(m_computed.coeff(i, i));
m_singularValues.coeffRef(i) = a * scale;
if (a<considerZero)
{
m_nonzeroSingularValues = i;
m_singularValues.tail(m_diagSize - i - 1).setZero();
break;
}
else if (i == m_diagSize - 1)
{
m_nonzeroSingularValues = i + 1;
break;
}
}
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
// std::cout << "m_naiveU\n" << m_naiveU << "\n\n";
// std::cout << "m_naiveV\n" << m_naiveV << "\n\n";
#endif
if(m_isTranspose) copyUV(bid.householderV(), bid.householderU(), m_naiveV, m_naiveU);
else copyUV(bid.householderU(), bid.householderV(), m_naiveU, m_naiveV);
m_isInitialized = true;
return *this;
}// end compute
template<typename MatrixType>
template<typename HouseholderU, typename HouseholderV, typename NaiveU, typename NaiveV>
void BDCSVD<MatrixType>::copyUV(const HouseholderU &householderU, const HouseholderV &householderV, const NaiveU &naiveU, const NaiveV &naiveV)
{
// Note exchange of U and V: m_matrixU is set from m_naiveV and vice versa
if (computeU())
{
Index Ucols = m_computeThinU ? m_diagSize : householderU.cols();
m_matrixU = MatrixX::Identity(householderU.cols(), Ucols);
m_matrixU.topLeftCorner(m_diagSize, m_diagSize) = naiveV.template cast<Scalar>().topLeftCorner(m_diagSize, m_diagSize);
householderU.applyThisOnTheLeft(m_matrixU); // FIXME this line involves a temporary buffer
}
if (computeV())
{
Index Vcols = m_computeThinV ? m_diagSize : householderV.cols();
m_matrixV = MatrixX::Identity(householderV.cols(), Vcols);
m_matrixV.topLeftCorner(m_diagSize, m_diagSize) = naiveU.template cast<Scalar>().topLeftCorner(m_diagSize, m_diagSize);
householderV.applyThisOnTheLeft(m_matrixV); // FIXME this line involves a temporary buffer
}
}
/** \internal
* Performs A = A * B exploiting the special structure of the matrix A. Splitting A as:
* A = [A1]
* [A2]
* such that A1.rows()==n1, then we assume that at least half of the columns of A1 and A2 are zeros.
* We can thus pack them prior to the the matrix product. However, this is only worth the effort if the matrix is large
* enough.
*/
template<typename MatrixType>
void BDCSVD<MatrixType>::structured_update(Block<MatrixXr,Dynamic,Dynamic> A, const MatrixXr &B, Index n1)
{
Index n = A.rows();
if(n>100)
{
// If the matrices are large enough, let's exploit the sparse structure of A by
// splitting it in half (wrt n1), and packing the non-zero columns.
Index n2 = n - n1;
Map<MatrixXr> A1(m_workspace.data() , n1, n);
Map<MatrixXr> A2(m_workspace.data()+ n1*n, n2, n);
Map<MatrixXr> B1(m_workspace.data()+ n*n, n, n);
Map<MatrixXr> B2(m_workspace.data()+2*n*n, n, n);
Index k1=0, k2=0;
for(Index j=0; j<n; ++j)
{
if( (A.col(j).head(n1).array()!=Literal(0)).any() )
{
A1.col(k1) = A.col(j).head(n1);
B1.row(k1) = B.row(j);
++k1;
}
if( (A.col(j).tail(n2).array()!=Literal(0)).any() )
{
A2.col(k2) = A.col(j).tail(n2);
B2.row(k2) = B.row(j);
++k2;
}
}
A.topRows(n1).noalias() = A1.leftCols(k1) * B1.topRows(k1);
A.bottomRows(n2).noalias() = A2.leftCols(k2) * B2.topRows(k2);
}
else
{
Map<MatrixXr,Aligned> tmp(m_workspace.data(),n,n);
tmp.noalias() = A*B;
A = tmp;
}
}
// The divide algorithm is done "in place", we are always working on subsets of the same matrix. The divide methods takes as argument the
// place of the submatrix we are currently working on.
//@param firstCol : The Index of the first column of the submatrix of m_computed and for m_naiveU;
//@param lastCol : The Index of the last column of the submatrix of m_computed and for m_naiveU;
// lastCol + 1 - firstCol is the size of the submatrix.
//@param firstRowW : The Index of the first row of the matrix W that we are to change. (see the reference paper section 1 for more information on W)
//@param firstRowW : Same as firstRowW with the column.
//@param shift : Each time one takes the left submatrix, one must add 1 to the shift. Why? Because! We actually want the last column of the U submatrix
// to become the first column (*coeff) and to shift all the other columns to the right. There are more details on the reference paper.
template<typename MatrixType>
void BDCSVD<MatrixType>::divide (Eigen::Index firstCol, Eigen::Index lastCol, Eigen::Index firstRowW, Eigen::Index firstColW, Eigen::Index shift)
{
// requires rows = cols + 1;
using std::pow;
using std::sqrt;
using std::abs;
const Index n = lastCol - firstCol + 1;
const Index k = n/2;
const RealScalar considerZero = (std::numeric_limits<RealScalar>::min)();
RealScalar alphaK;
RealScalar betaK;
RealScalar r0;
RealScalar lambda, phi, c0, s0;
VectorType l, f;
// We use the other algorithm which is more efficient for small
// matrices.
if (n < m_algoswap)
{
// FIXME this line involves temporaries
JacobiSVD<MatrixXr> b(m_computed.block(firstCol, firstCol, n + 1, n), ComputeFullU | (m_compV ? ComputeFullV : 0));
if (m_compU)
m_naiveU.block(firstCol, firstCol, n + 1, n + 1).real() = b.matrixU();
else
{
m_naiveU.row(0).segment(firstCol, n + 1).real() = b.matrixU().row(0);
m_naiveU.row(1).segment(firstCol, n + 1).real() = b.matrixU().row(n);
}
if (m_compV) m_naiveV.block(firstRowW, firstColW, n, n).real() = b.matrixV();
m_computed.block(firstCol + shift, firstCol + shift, n + 1, n).setZero();
m_computed.diagonal().segment(firstCol + shift, n) = b.singularValues().head(n);
return;
}
// We use the divide and conquer algorithm
alphaK = m_computed(firstCol + k, firstCol + k);
betaK = m_computed(firstCol + k + 1, firstCol + k);
// The divide must be done in that order in order to have good results. Divide change the data inside the submatrices
// and the divide of the right submatrice reads one column of the left submatrice. That's why we need to treat the
// right submatrix before the left one.
divide(k + 1 + firstCol, lastCol, k + 1 + firstRowW, k + 1 + firstColW, shift);
divide(firstCol, k - 1 + firstCol, firstRowW, firstColW + 1, shift + 1);
if (m_compU)
{
lambda = m_naiveU(firstCol + k, firstCol + k);
phi = m_naiveU(firstCol + k + 1, lastCol + 1);
}
else
{
lambda = m_naiveU(1, firstCol + k);
phi = m_naiveU(0, lastCol + 1);
}
r0 = sqrt((abs(alphaK * lambda) * abs(alphaK * lambda)) + abs(betaK * phi) * abs(betaK * phi));
if (m_compU)
{
l = m_naiveU.row(firstCol + k).segment(firstCol, k);
f = m_naiveU.row(firstCol + k + 1).segment(firstCol + k + 1, n - k - 1);
}
else
{
l = m_naiveU.row(1).segment(firstCol, k);
f = m_naiveU.row(0).segment(firstCol + k + 1, n - k - 1);
}
if (m_compV) m_naiveV(firstRowW+k, firstColW) = Literal(1);
if (r0<considerZero)
{
c0 = Literal(1);
s0 = Literal(0);
}
else
{
c0 = alphaK * lambda / r0;
s0 = betaK * phi / r0;
}
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(m_naiveU.allFinite());
assert(m_naiveV.allFinite());
assert(m_computed.allFinite());
#endif
if (m_compU)
{
MatrixXr q1 (m_naiveU.col(firstCol + k).segment(firstCol, k + 1));
// we shiftW Q1 to the right
for (Index i = firstCol + k - 1; i >= firstCol; i--)
m_naiveU.col(i + 1).segment(firstCol, k + 1) = m_naiveU.col(i).segment(firstCol, k + 1);
// we shift q1 at the left with a factor c0
m_naiveU.col(firstCol).segment( firstCol, k + 1) = (q1 * c0);
// last column = q1 * - s0
m_naiveU.col(lastCol + 1).segment(firstCol, k + 1) = (q1 * ( - s0));
// first column = q2 * s0
m_naiveU.col(firstCol).segment(firstCol + k + 1, n - k) = m_naiveU.col(lastCol + 1).segment(firstCol + k + 1, n - k) * s0;
// q2 *= c0
m_naiveU.col(lastCol + 1).segment(firstCol + k + 1, n - k) *= c0;
}
else
{
RealScalar q1 = m_naiveU(0, firstCol + k);
// we shift Q1 to the right
for (Index i = firstCol + k - 1; i >= firstCol; i--)
m_naiveU(0, i + 1) = m_naiveU(0, i);
// we shift q1 at the left with a factor c0
m_naiveU(0, firstCol) = (q1 * c0);
// last column = q1 * - s0
m_naiveU(0, lastCol + 1) = (q1 * ( - s0));
// first column = q2 * s0
m_naiveU(1, firstCol) = m_naiveU(1, lastCol + 1) *s0;
// q2 *= c0
m_naiveU(1, lastCol + 1) *= c0;
m_naiveU.row(1).segment(firstCol + 1, k).setZero();
m_naiveU.row(0).segment(firstCol + k + 1, n - k - 1).setZero();
}
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(m_naiveU.allFinite());
assert(m_naiveV.allFinite());
assert(m_computed.allFinite());
#endif
m_computed(firstCol + shift, firstCol + shift) = r0;
m_computed.col(firstCol + shift).segment(firstCol + shift + 1, k) = alphaK * l.transpose().real();
m_computed.col(firstCol + shift).segment(firstCol + shift + k + 1, n - k - 1) = betaK * f.transpose().real();
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
ArrayXr tmp1 = (m_computed.block(firstCol+shift, firstCol+shift, n, n)).jacobiSvd().singularValues();
#endif
// Second part: try to deflate singular values in combined matrix
deflation(firstCol, lastCol, k, firstRowW, firstColW, shift);
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
ArrayXr tmp2 = (m_computed.block(firstCol+shift, firstCol+shift, n, n)).jacobiSvd().singularValues();
std::cout << "\n\nj1 = " << tmp1.transpose().format(bdcsvdfmt) << "\n";
std::cout << "j2 = " << tmp2.transpose().format(bdcsvdfmt) << "\n\n";
std::cout << "err: " << ((tmp1-tmp2).abs()>1e-12*tmp2.abs()).transpose() << "\n";
static int count = 0;
std::cout << "# " << ++count << "\n\n";
assert((tmp1-tmp2).matrix().norm() < 1e-14*tmp2.matrix().norm());
// assert(count<681);
// assert(((tmp1-tmp2).abs()<1e-13*tmp2.abs()).all());
#endif
// Third part: compute SVD of combined matrix
MatrixXr UofSVD, VofSVD;
VectorType singVals;
computeSVDofM(firstCol + shift, n, UofSVD, singVals, VofSVD);
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(UofSVD.allFinite());
assert(VofSVD.allFinite());
#endif
if (m_compU)
structured_update(m_naiveU.block(firstCol, firstCol, n + 1, n + 1), UofSVD, (n+2)/2);
else
{
Map<Matrix<RealScalar,2,Dynamic>,Aligned> tmp(m_workspace.data(),2,n+1);
tmp.noalias() = m_naiveU.middleCols(firstCol, n+1) * UofSVD;
m_naiveU.middleCols(firstCol, n + 1) = tmp;
}
if (m_compV) structured_update(m_naiveV.block(firstRowW, firstColW, n, n), VofSVD, (n+1)/2);
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(m_naiveU.allFinite());
assert(m_naiveV.allFinite());
assert(m_computed.allFinite());
#endif
m_computed.block(firstCol + shift, firstCol + shift, n, n).setZero();
m_computed.block(firstCol + shift, firstCol + shift, n, n).diagonal() = singVals;
}// end divide
// Compute SVD of m_computed.block(firstCol, firstCol, n + 1, n); this block only has non-zeros in
// the first column and on the diagonal and has undergone deflation, so diagonal is in increasing
// order except for possibly the (0,0) entry. The computed SVD is stored U, singVals and V, except
// that if m_compV is false, then V is not computed. Singular values are sorted in decreasing order.
//
// TODO Opportunities for optimization: better root finding algo, better stopping criterion, better
// handling of round-off errors, be consistent in ordering
// For instance, to solve the secular equation using FMM, see http://www.stat.uchicago.edu/~lekheng/courses/302/classics/greengard-rokhlin.pdf
template <typename MatrixType>
void BDCSVD<MatrixType>::computeSVDofM(Eigen::Index firstCol, Eigen::Index n, MatrixXr& U, VectorType& singVals, MatrixXr& V)
{
const RealScalar considerZero = (std::numeric_limits<RealScalar>::min)();
using std::abs;
ArrayRef col0 = m_computed.col(firstCol).segment(firstCol, n);
m_workspace.head(n) = m_computed.block(firstCol, firstCol, n, n).diagonal();
ArrayRef diag = m_workspace.head(n);
diag(0) = Literal(0);
// Allocate space for singular values and vectors
singVals.resize(n);
U.resize(n+1, n+1);
if (m_compV) V.resize(n, n);
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
if (col0.hasNaN() || diag.hasNaN())
std::cout << "\n\nHAS NAN\n\n";
#endif
// Many singular values might have been deflated, the zero ones have been moved to the end,
// but others are interleaved and we must ignore them at this stage.
// To this end, let's compute a permutation skipping them:
Index actual_n = n;
while(actual_n>1 && diag(actual_n-1)==Literal(0)) {--actual_n; eigen_internal_assert(col0(actual_n)==Literal(0)); }
Index m = 0; // size of the deflated problem
for(Index k=0;k<actual_n;++k)
if(abs(col0(k))>considerZero)
m_workspaceI(m++) = k;
Map<ArrayXi> perm(m_workspaceI.data(),m);
Map<ArrayXr> shifts(m_workspace.data()+1*n, n);
Map<ArrayXr> mus(m_workspace.data()+2*n, n);
Map<ArrayXr> zhat(m_workspace.data()+3*n, n);
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "computeSVDofM using:\n";
std::cout << " z: " << col0.transpose() << "\n";
std::cout << " d: " << diag.transpose() << "\n";
#endif
// Compute singVals, shifts, and mus
computeSingVals(col0, diag, perm, singVals, shifts, mus);
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << " j: " << (m_computed.block(firstCol, firstCol, n, n)).jacobiSvd().singularValues().transpose().reverse() << "\n\n";
std::cout << " sing-val: " << singVals.transpose() << "\n";
std::cout << " mu: " << mus.transpose() << "\n";
std::cout << " shift: " << shifts.transpose() << "\n";
{
std::cout << "\n\n mus: " << mus.head(actual_n).transpose() << "\n\n";
std::cout << " check1 (expect0) : " << ((singVals.array()-(shifts+mus)) / singVals.array()).head(actual_n).transpose() << "\n\n";
assert((((singVals.array()-(shifts+mus)) / singVals.array()).head(actual_n) >= 0).all());
std::cout << " check2 (>0) : " << ((singVals.array()-diag) / singVals.array()).head(actual_n).transpose() << "\n\n";
assert((((singVals.array()-diag) / singVals.array()).head(actual_n) >= 0).all());
}
#endif
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(singVals.allFinite());
assert(mus.allFinite());
assert(shifts.allFinite());
#endif
// Compute zhat
perturbCol0(col0, diag, perm, singVals, shifts, mus, zhat);
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << " zhat: " << zhat.transpose() << "\n";
#endif
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(zhat.allFinite());
#endif
computeSingVecs(zhat, diag, perm, singVals, shifts, mus, U, V);
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "U^T U: " << (U.transpose() * U - MatrixXr(MatrixXr::Identity(U.cols(),U.cols()))).norm() << "\n";
std::cout << "V^T V: " << (V.transpose() * V - MatrixXr(MatrixXr::Identity(V.cols(),V.cols()))).norm() << "\n";
#endif
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(m_naiveU.allFinite());
assert(m_naiveV.allFinite());
assert(m_computed.allFinite());
assert(U.allFinite());
assert(V.allFinite());
// assert((U.transpose() * U - MatrixXr(MatrixXr::Identity(U.cols(),U.cols()))).norm() < 100*NumTraits<RealScalar>::epsilon() * n);
// assert((V.transpose() * V - MatrixXr(MatrixXr::Identity(V.cols(),V.cols()))).norm() < 100*NumTraits<RealScalar>::epsilon() * n);
#endif
// Because of deflation, the singular values might not be completely sorted.
// Fortunately, reordering them is a O(n) problem
for(Index i=0; i<actual_n-1; ++i)
{
if(singVals(i)>singVals(i+1))
{
using std::swap;
swap(singVals(i),singVals(i+1));
U.col(i).swap(U.col(i+1));
if(m_compV) V.col(i).swap(V.col(i+1));
}
}
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
{
bool singular_values_sorted = (((singVals.segment(1,actual_n-1)-singVals.head(actual_n-1))).array() >= 0).all();
if(!singular_values_sorted)
std::cout << "Singular values are not sorted: " << singVals.segment(1,actual_n).transpose() << "\n";
assert(singular_values_sorted);
}
#endif
// Reverse order so that singular values in increased order
// Because of deflation, the zeros singular-values are already at the end
singVals.head(actual_n).reverseInPlace();
U.leftCols(actual_n).rowwise().reverseInPlace();
if (m_compV) V.leftCols(actual_n).rowwise().reverseInPlace();
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
JacobiSVD<MatrixXr> jsvd(m_computed.block(firstCol, firstCol, n, n) );
std::cout << " * j: " << jsvd.singularValues().transpose() << "\n\n";
std::cout << " * sing-val: " << singVals.transpose() << "\n";
// std::cout << " * err: " << ((jsvd.singularValues()-singVals)>1e-13*singVals.norm()).transpose() << "\n";
#endif
}
template <typename MatrixType>
typename BDCSVD<MatrixType>::RealScalar BDCSVD<MatrixType>::secularEq(RealScalar mu, const ArrayRef& col0, const ArrayRef& diag, const IndicesRef &perm, const ArrayRef& diagShifted, RealScalar shift)
{
Index m = perm.size();
RealScalar res = Literal(1);
for(Index i=0; i<m; ++i)
{
Index j = perm(i);
// The following expression could be rewritten to involve only a single division,
// but this would make the expression more sensitive to overflow.
res += (col0(j) / (diagShifted(j) - mu)) * (col0(j) / (diag(j) + shift + mu));
}
return res;
}
template <typename MatrixType>
void BDCSVD<MatrixType>::computeSingVals(const ArrayRef& col0, const ArrayRef& diag, const IndicesRef &perm,
VectorType& singVals, ArrayRef shifts, ArrayRef mus)
{
using std::abs;
using std::swap;
using std::sqrt;
Index n = col0.size();
Index actual_n = n;
// Note that here actual_n is computed based on col0(i)==0 instead of diag(i)==0 as above
// because 1) we have diag(i)==0 => col0(i)==0 and 2) if col0(i)==0, then diag(i) is already a singular value.
while(actual_n>1 && col0(actual_n-1)==Literal(0)) --actual_n;
for (Index k = 0; k < n; ++k)
{
if (col0(k) == Literal(0) || actual_n==1)
{
// if col0(k) == 0, then entry is deflated, so singular value is on diagonal
// if actual_n==1, then the deflated problem is already diagonalized
singVals(k) = k==0 ? col0(0) : diag(k);
mus(k) = Literal(0);
shifts(k) = k==0 ? col0(0) : diag(k);
continue;
}
// otherwise, use secular equation to find singular value
RealScalar left = diag(k);
RealScalar right; // was: = (k != actual_n-1) ? diag(k+1) : (diag(actual_n-1) + col0.matrix().norm());
if(k==actual_n-1)
right = (diag(actual_n-1) + col0.matrix().norm());
else
{
// Skip deflated singular values,
// recall that at this stage we assume that z[j]!=0 and all entries for which z[j]==0 have been put aside.
// This should be equivalent to using perm[]
Index l = k+1;
while(col0(l)==Literal(0)) { ++l; eigen_internal_assert(l<actual_n); }
right = diag(l);
}
// first decide whether it's closer to the left end or the right end
RealScalar mid = left + (right-left) / Literal(2);
RealScalar fMid = secularEq(mid, col0, diag, perm, diag, Literal(0));
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "right-left = " << right-left << "\n";
// std::cout << "fMid = " << fMid << " " << secularEq(mid-left, col0, diag, perm, ArrayXr(diag-left), left)
// << " " << secularEq(mid-right, col0, diag, perm, ArrayXr(diag-right), right) << "\n";
std::cout << " = " << secularEq(left+RealScalar(0.000001)*(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.1) *(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.2) *(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.3) *(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.4) *(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.49) *(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.5) *(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.51) *(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.6) *(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.7) *(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.8) *(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.9) *(right-left), col0, diag, perm, diag, 0)
<< " " << secularEq(left+RealScalar(0.999999)*(right-left), col0, diag, perm, diag, 0) << "\n";
#endif
RealScalar shift = (k == actual_n-1 || fMid > Literal(0)) ? left : right;
// measure everything relative to shift
Map<ArrayXr> diagShifted(m_workspace.data()+4*n, n);
diagShifted = diag - shift;
// initial guess
RealScalar muPrev, muCur;
if (shift == left)
{
muPrev = (right - left) * RealScalar(0.1);
if (k == actual_n-1) muCur = right - left;
else muCur = (right - left) * RealScalar(0.5);
}
else
{
muPrev = -(right - left) * RealScalar(0.1);
muCur = -(right - left) * RealScalar(0.5);
}
RealScalar fPrev = secularEq(muPrev, col0, diag, perm, diagShifted, shift);
RealScalar fCur = secularEq(muCur, col0, diag, perm, diagShifted, shift);
if (abs(fPrev) < abs(fCur))
{
swap(fPrev, fCur);
swap(muPrev, muCur);
}
// rational interpolation: fit a function of the form a / mu + b through the two previous
// iterates and use its zero to compute the next iterate
bool useBisection = fPrev*fCur>Literal(0);
while (fCur!=Literal(0) && abs(muCur - muPrev) > Literal(8) * NumTraits<RealScalar>::epsilon() * numext::maxi<RealScalar>(abs(muCur), abs(muPrev)) && abs(fCur - fPrev)>NumTraits<RealScalar>::epsilon() && !useBisection)
{
++m_numIters;
// Find a and b such that the function f(mu) = a / mu + b matches the current and previous samples.
RealScalar a = (fCur - fPrev) / (Literal(1)/muCur - Literal(1)/muPrev);
RealScalar b = fCur - a / muCur;
// And find mu such that f(mu)==0:
RealScalar muZero = -a/b;
RealScalar fZero = secularEq(muZero, col0, diag, perm, diagShifted, shift);
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert((std::isfinite)(fZero));
#endif
muPrev = muCur;
fPrev = fCur;
muCur = muZero;
fCur = fZero;
if (shift == left && (muCur < Literal(0) || muCur > right - left)) useBisection = true;
if (shift == right && (muCur < -(right - left) || muCur > Literal(0))) useBisection = true;
if (abs(fCur)>abs(fPrev)) useBisection = true;
}
// fall back on bisection method if rational interpolation did not work
if (useBisection)
{
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "useBisection for k = " << k << ", actual_n = " << actual_n << "\n";
#endif
RealScalar leftShifted, rightShifted;
if (shift == left)
{
// to avoid overflow, we must have mu > max(real_min, |z(k)|/sqrt(real_max)),
// the factor 2 is to be more conservative
leftShifted = numext::maxi<RealScalar>( (std::numeric_limits<RealScalar>::min)(), Literal(2) * abs(col0(k)) / sqrt((std::numeric_limits<RealScalar>::max)()) );
// check that we did it right:
eigen_internal_assert( (numext::isfinite)( (col0(k)/leftShifted)*(col0(k)/(diag(k)+shift+leftShifted)) ) );
// I don't understand why the case k==0 would be special there:
// if (k == 0) rightShifted = right - left; else
rightShifted = (k==actual_n-1) ? right : ((right - left) * RealScalar(0.51)); // theoretically we can take 0.5, but let's be safe
}
else
{
leftShifted = -(right - left) * RealScalar(0.51);
if(k+1<n)
rightShifted = -numext::maxi<RealScalar>( (std::numeric_limits<RealScalar>::min)(), abs(col0(k+1)) / sqrt((std::numeric_limits<RealScalar>::max)()) );
else
rightShifted = -(std::numeric_limits<RealScalar>::min)();
}
RealScalar fLeft = secularEq(leftShifted, col0, diag, perm, diagShifted, shift);
#if defined EIGEN_INTERNAL_DEBUGGING || defined EIGEN_BDCSVD_SANITY_CHECKS
RealScalar fRight = secularEq(rightShifted, col0, diag, perm, diagShifted, shift);
#endif
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
if(!(std::isfinite)(fLeft))
std::cout << "f(" << leftShifted << ") =" << fLeft << " ; " << left << " " << shift << " " << right << "\n";
assert((std::isfinite)(fLeft));
if(!(std::isfinite)(fRight))
std::cout << "f(" << rightShifted << ") =" << fRight << " ; " << left << " " << shift << " " << right << "\n";
// assert((std::isfinite)(fRight));
#endif
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
if(!(fLeft * fRight<0))
{
std::cout << "f(leftShifted) using leftShifted=" << leftShifted << " ; diagShifted(1:10):" << diagShifted.head(10).transpose() << "\n ; "
<< "left==shift=" << bool(left==shift) << " ; left-shift = " << (left-shift) << "\n";
std::cout << "k=" << k << ", " << fLeft << " * " << fRight << " == " << fLeft * fRight << " ; "
<< "[" << left << " .. " << right << "] -> [" << leftShifted << " " << rightShifted << "], shift=" << shift << " , f(right)=" << secularEq(0, col0, diag, perm, diagShifted, shift) << " == " << secularEq(right, col0, diag, perm, diag, 0) << "\n";
}
#endif
eigen_internal_assert(fLeft * fRight < Literal(0));
while (rightShifted - leftShifted > Literal(2) * NumTraits<RealScalar>::epsilon() * numext::maxi<RealScalar>(abs(leftShifted), abs(rightShifted)))
{
RealScalar midShifted = (leftShifted + rightShifted) / Literal(2);
fMid = secularEq(midShifted, col0, diag, perm, diagShifted, shift);
eigen_internal_assert((numext::isfinite)(fMid));
if (fLeft * fMid < Literal(0))
{
rightShifted = midShifted;
}
else
{
leftShifted = midShifted;
fLeft = fMid;
}
}
muCur = (leftShifted + rightShifted) / Literal(2);
}
singVals[k] = shift + muCur;
shifts[k] = shift;
mus[k] = muCur;
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
if(k+1<n)
std::cout << "found " << singVals[k] << " == " << shift << " + " << muCur << " from " << diag(k) << " .. " << diag(k+1) << "\n";
#endif
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(k==0 || singVals[k]>=singVals[k-1]);
assert(singVals[k]>=diag(k));
#endif
// perturb singular value slightly if it equals diagonal entry to avoid division by zero later
// (deflation is supposed to avoid this from happening)
// - this does no seem to be necessary anymore -
// if (singVals[k] == left) singVals[k] *= 1 + NumTraits<RealScalar>::epsilon();
// if (singVals[k] == right) singVals[k] *= 1 - NumTraits<RealScalar>::epsilon();
}
}
// zhat is perturbation of col0 for which singular vectors can be computed stably (see Section 3.1)
template <typename MatrixType>
void BDCSVD<MatrixType>::perturbCol0
(const ArrayRef& col0, const ArrayRef& diag, const IndicesRef &perm, const VectorType& singVals,
const ArrayRef& shifts, const ArrayRef& mus, ArrayRef zhat)
{
using std::sqrt;
Index n = col0.size();
Index m = perm.size();
if(m==0)
{
zhat.setZero();
return;
}
Index last = perm(m-1);
// The offset permits to skip deflated entries while computing zhat
for (Index k = 0; k < n; ++k)
{
if (col0(k) == Literal(0)) // deflated
zhat(k) = Literal(0);
else
{
// see equation (3.6)
RealScalar dk = diag(k);
RealScalar prod = (singVals(last) + dk) * (mus(last) + (shifts(last) - dk));
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
if(prod<0) {
std::cout << "k = " << k << " ; z(k)=" << col0(k) << ", diag(k)=" << dk << "\n";
std::cout << "prod = " << "(" << singVals(last) << " + " << dk << ") * (" << mus(last) << " + (" << shifts(last) << " - " << dk << "))" << "\n";
std::cout << " = " << singVals(last) + dk << " * " << mus(last) + (shifts(last) - dk) << "\n";
}
assert(prod>=0);
#endif
for(Index l = 0; l<m; ++l)
{
Index i = perm(l);
if(i!=k)
{
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
if(i>=k && (l==0 || l-1>=m))
{
std::cout << "Error in perturbCol0\n";
std::cout << " " << k << "/" << n << " " << l << "/" << m << " " << i << "/" << n << " ; " << col0(k) << " " << diag(k) << " " << "\n";
std::cout << " " <<diag(i) << "\n";
Index j = (i<k /*|| l==0*/) ? i : perm(l-1);
std::cout << " " << "j=" << j << "\n";
}
#endif
Index j = i<k ? i : perm(l-1);
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
if(!(dk!=Literal(0) || diag(i)!=Literal(0)))
{
std::cout << "k=" << k << ", i=" << i << ", l=" << l << ", perm.size()=" << perm.size() << "\n";
}
assert(dk!=Literal(0) || diag(i)!=Literal(0));
#endif
prod *= ((singVals(j)+dk) / ((diag(i)+dk))) * ((mus(j)+(shifts(j)-dk)) / ((diag(i)-dk)));
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(prod>=0);
#endif
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
if(i!=k && std::abs(((singVals(j)+dk)*(mus(j)+(shifts(j)-dk)))/((diag(i)+dk)*(diag(i)-dk)) - 1) > 0.9 )
std::cout << " " << ((singVals(j)+dk)*(mus(j)+(shifts(j)-dk)))/((diag(i)+dk)*(diag(i)-dk)) << " == (" << (singVals(j)+dk) << " * " << (mus(j)+(shifts(j)-dk))
<< ") / (" << (diag(i)+dk) << " * " << (diag(i)-dk) << ")\n";
#endif
}
}
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "zhat(" << k << ") = sqrt( " << prod << ") ; " << (singVals(last) + dk) << " * " << mus(last) + shifts(last) << " - " << dk << "\n";
#endif
RealScalar tmp = sqrt(prod);
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert((std::isfinite)(tmp));
#endif
zhat(k) = col0(k) > Literal(0) ? tmp : -tmp;
}
}
}
// compute singular vectors
template <typename MatrixType>
void BDCSVD<MatrixType>::computeSingVecs
(const ArrayRef& zhat, const ArrayRef& diag, const IndicesRef &perm, const VectorType& singVals,
const ArrayRef& shifts, const ArrayRef& mus, MatrixXr& U, MatrixXr& V)
{
Index n = zhat.size();
Index m = perm.size();
for (Index k = 0; k < n; ++k)
{
if (zhat(k) == Literal(0))
{
U.col(k) = VectorType::Unit(n+1, k);
if (m_compV) V.col(k) = VectorType::Unit(n, k);
}
else
{
U.col(k).setZero();
for(Index l=0;l<m;++l)
{
Index i = perm(l);
U(i,k) = zhat(i)/(((diag(i) - shifts(k)) - mus(k)) )/( (diag(i) + singVals[k]));
}
U(n,k) = Literal(0);
U.col(k).normalize();
if (m_compV)
{
V.col(k).setZero();
for(Index l=1;l<m;++l)
{
Index i = perm(l);
V(i,k) = diag(i) * zhat(i) / (((diag(i) - shifts(k)) - mus(k)) )/( (diag(i) + singVals[k]));
}
V(0,k) = Literal(-1);
V.col(k).normalize();
}
}
}
U.col(n) = VectorType::Unit(n+1, n);
}
// page 12_13
// i >= 1, di almost null and zi non null.
// We use a rotation to zero out zi applied to the left of M
template <typename MatrixType>
void BDCSVD<MatrixType>::deflation43(Eigen::Index firstCol, Eigen::Index shift, Eigen::Index i, Eigen::Index size)
{
using std::abs;
using std::sqrt;
using std::pow;
Index start = firstCol + shift;
RealScalar c = m_computed(start, start);
RealScalar s = m_computed(start+i, start);
RealScalar r = numext::hypot(c,s);
if (r == Literal(0))
{
m_computed(start+i, start+i) = Literal(0);
return;
}
m_computed(start,start) = r;
m_computed(start+i, start) = Literal(0);
m_computed(start+i, start+i) = Literal(0);
JacobiRotation<RealScalar> J(c/r,-s/r);
if (m_compU) m_naiveU.middleRows(firstCol, size+1).applyOnTheRight(firstCol, firstCol+i, J);
else m_naiveU.applyOnTheRight(firstCol, firstCol+i, J);
}// end deflation 43
// page 13
// i,j >= 1, i!=j and |di - dj| < epsilon * norm2(M)
// We apply two rotations to have zj = 0;
// TODO deflation44 is still broken and not properly tested
template <typename MatrixType>
void BDCSVD<MatrixType>::deflation44(Eigen::Index firstColu , Eigen::Index firstColm, Eigen::Index firstRowW, Eigen::Index firstColW, Eigen::Index i, Eigen::Index j, Eigen::Index size)
{
using std::abs;
using std::sqrt;
using std::conj;
using std::pow;
RealScalar c = m_computed(firstColm+i, firstColm);
RealScalar s = m_computed(firstColm+j, firstColm);
RealScalar r = sqrt(numext::abs2(c) + numext::abs2(s));
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "deflation 4.4: " << i << "," << j << " -> " << c << " " << s << " " << r << " ; "
<< m_computed(firstColm + i-1, firstColm) << " "
<< m_computed(firstColm + i, firstColm) << " "
<< m_computed(firstColm + i+1, firstColm) << " "
<< m_computed(firstColm + i+2, firstColm) << "\n";
std::cout << m_computed(firstColm + i-1, firstColm + i-1) << " "
<< m_computed(firstColm + i, firstColm+i) << " "
<< m_computed(firstColm + i+1, firstColm+i+1) << " "
<< m_computed(firstColm + i+2, firstColm+i+2) << "\n";
#endif
if (r==Literal(0))
{
m_computed(firstColm + i, firstColm + i) = m_computed(firstColm + j, firstColm + j);
return;
}
c/=r;
s/=r;
m_computed(firstColm + i, firstColm) = r;
m_computed(firstColm + j, firstColm + j) = m_computed(firstColm + i, firstColm + i);
m_computed(firstColm + j, firstColm) = Literal(0);
JacobiRotation<RealScalar> J(c,-s);
if (m_compU) m_naiveU.middleRows(firstColu, size+1).applyOnTheRight(firstColu + i, firstColu + j, J);
else m_naiveU.applyOnTheRight(firstColu+i, firstColu+j, J);
if (m_compV) m_naiveV.middleRows(firstRowW, size).applyOnTheRight(firstColW + i, firstColW + j, J);
}// end deflation 44
// acts on block from (firstCol+shift, firstCol+shift) to (lastCol+shift, lastCol+shift) [inclusive]
template <typename MatrixType>
void BDCSVD<MatrixType>::deflation(Eigen::Index firstCol, Eigen::Index lastCol, Eigen::Index k, Eigen::Index firstRowW, Eigen::Index firstColW, Eigen::Index shift)
{
using std::sqrt;
using std::abs;
const Index length = lastCol + 1 - firstCol;
Block<MatrixXr,Dynamic,1> col0(m_computed, firstCol+shift, firstCol+shift, length, 1);
Diagonal<MatrixXr> fulldiag(m_computed);
VectorBlock<Diagonal<MatrixXr>,Dynamic> diag(fulldiag, firstCol+shift, length);
const RealScalar considerZero = (std::numeric_limits<RealScalar>::min)();
RealScalar maxDiag = diag.tail((std::max)(Index(1),length-1)).cwiseAbs().maxCoeff();
RealScalar epsilon_strict = numext::maxi<RealScalar>(considerZero,NumTraits<RealScalar>::epsilon() * maxDiag);
RealScalar epsilon_coarse = Literal(8) * NumTraits<RealScalar>::epsilon() * numext::maxi<RealScalar>(col0.cwiseAbs().maxCoeff(), maxDiag);
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(m_naiveU.allFinite());
assert(m_naiveV.allFinite());
assert(m_computed.allFinite());
#endif
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "\ndeflate:" << diag.head(k+1).transpose() << " | " << diag.segment(k+1,length-k-1).transpose() << "\n";
#endif
//condition 4.1
if (diag(0) < epsilon_coarse)
{
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "deflation 4.1, because " << diag(0) << " < " << epsilon_coarse << "\n";
#endif
diag(0) = epsilon_coarse;
}
//condition 4.2
for (Index i=1;i<length;++i)
if (abs(col0(i)) < epsilon_strict)
{
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "deflation 4.2, set z(" << i << ") to zero because " << abs(col0(i)) << " < " << epsilon_strict << " (diag(" << i << ")=" << diag(i) << ")\n";
#endif
col0(i) = Literal(0);
}
//condition 4.3
for (Index i=1;i<length; i++)
if (diag(i) < epsilon_coarse)
{
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "deflation 4.3, cancel z(" << i << ")=" << col0(i) << " because diag(" << i << ")=" << diag(i) << " < " << epsilon_coarse << "\n";
#endif
deflation43(firstCol, shift, i, length);
}
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(m_naiveU.allFinite());
assert(m_naiveV.allFinite());
assert(m_computed.allFinite());
#endif
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "to be sorted: " << diag.transpose() << "\n\n";
std::cout << " : " << col0.transpose() << "\n\n";
#endif
{
// Check for total deflation
// If we have a total deflation, then we have to consider col0(0)==diag(0) as a singular value during sorting
bool total_deflation = (col0.tail(length-1).array()<considerZero).all();
// Sort the diagonal entries, since diag(1:k-1) and diag(k:length) are already sorted, let's do a sorted merge.
// First, compute the respective permutation.
Index *permutation = m_workspaceI.data();
{
permutation[0] = 0;
Index p = 1;
// Move deflated diagonal entries at the end.
for(Index i=1; i<length; ++i)
if(abs(diag(i))<considerZero)
permutation[p++] = i;
Index i=1, j=k+1;
for( ; p < length; ++p)
{
if (i > k) permutation[p] = j++;
else if (j >= length) permutation[p] = i++;
else if (diag(i) < diag(j)) permutation[p] = j++;
else permutation[p] = i++;
}
}
// If we have a total deflation, then we have to insert diag(0) at the right place
if(total_deflation)
{
for(Index i=1; i<length; ++i)
{
Index pi = permutation[i];
if(abs(diag(pi))<considerZero || diag(0)<diag(pi))
permutation[i-1] = permutation[i];
else
{
permutation[i-1] = 0;
break;
}
}
}
// Current index of each col, and current column of each index
Index *realInd = m_workspaceI.data()+length;
Index *realCol = m_workspaceI.data()+2*length;
for(int pos = 0; pos< length; pos++)
{
realCol[pos] = pos;
realInd[pos] = pos;
}
for(Index i = total_deflation?0:1; i < length; i++)
{
const Index pi = permutation[length - (total_deflation ? i+1 : i)];
const Index J = realCol[pi];
using std::swap;
// swap diagonal and first column entries:
swap(diag(i), diag(J));
if(i!=0 && J!=0) swap(col0(i), col0(J));
// change columns
if (m_compU) m_naiveU.col(firstCol+i).segment(firstCol, length + 1).swap(m_naiveU.col(firstCol+J).segment(firstCol, length + 1));
else m_naiveU.col(firstCol+i).segment(0, 2) .swap(m_naiveU.col(firstCol+J).segment(0, 2));
if (m_compV) m_naiveV.col(firstColW + i).segment(firstRowW, length).swap(m_naiveV.col(firstColW + J).segment(firstRowW, length));
//update real pos
const Index realI = realInd[i];
realCol[realI] = J;
realCol[pi] = i;
realInd[J] = realI;
realInd[i] = pi;
}
}
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "sorted: " << diag.transpose().format(bdcsvdfmt) << "\n";
std::cout << " : " << col0.transpose() << "\n\n";
#endif
//condition 4.4
{
Index i = length-1;
while(i>0 && (abs(diag(i))<considerZero || abs(col0(i))<considerZero)) --i;
for(; i>1;--i)
if( (diag(i) - diag(i-1)) < NumTraits<RealScalar>::epsilon()*maxDiag )
{
#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE
std::cout << "deflation 4.4 with i = " << i << " because " << diag(i) << " - " << diag(i-1) << " == " << (diag(i) - diag(i-1)) << " < " << NumTraits<RealScalar>::epsilon()*/*diag(i)*/maxDiag << "\n";
#endif
eigen_internal_assert(abs(diag(i) - diag(i-1))<epsilon_coarse && " diagonal entries are not properly sorted");
deflation44(firstCol, firstCol + shift, firstRowW, firstColW, i-1, i, length);
}
}
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
for(Index j=2;j<length;++j)
assert(diag(j-1)<=diag(j) || abs(diag(j))<considerZero);
#endif
#ifdef EIGEN_BDCSVD_SANITY_CHECKS
assert(m_naiveU.allFinite());
assert(m_naiveV.allFinite());
assert(m_computed.allFinite());
#endif
}//end deflation
#ifndef EIGEN_CUDACC
/** \svd_module
*
* \return the singular value decomposition of \c *this computed by Divide & Conquer algorithm
*
* \sa class BDCSVD
*/
template<typename Derived>
BDCSVD<typename MatrixBase<Derived>::PlainObject>
MatrixBase<Derived>::bdcSvd(unsigned int computationOptions) const
{
return BDCSVD<PlainObject>(*this, computationOptions);
}
#endif
} // end namespace Eigen
#endif
| 39.718939 | 265 | 0.632741 |
2ea6cce21fa080de161277270d772385561e1c08 | 1,002 | c | C | 17-pthreads-monitors/01-queue/queue.c | jtrindade/isel-so-2021-2-li41n | a2dcf1e7fd8ef1b0e34296997606d002a3c9ec72 | [
"MIT"
] | 3 | 2021-03-16T20:03:44.000Z | 2021-03-21T11:41:08.000Z | 17-pthreads-monitors/01-queue/queue.c | jtrindade/isel-so-2021-2-li41n | a2dcf1e7fd8ef1b0e34296997606d002a3c9ec72 | [
"MIT"
] | null | null | null | 17-pthreads-monitors/01-queue/queue.c | jtrindade/isel-so-2021-2-li41n | a2dcf1e7fd8ef1b0e34296997606d002a3c9ec72 | [
"MIT"
] | null | null | null | #include "queue.h"
typedef struct queue_node {
list_entry_t entry;
void * item;
} queue_node_t;
void queue_init(queue_t * queue) {
pthread_mutex_init(&queue->lock, NULL);
init_list_head(&queue->head);
queue->size = 0;
}
void queue_cleanup(queue_t * queue) {
pthread_mutex_destroy(&queue->lock);
}
void queue_put(queue_t * queue, void * item) {
queue_node_t * pnode = (queue_node_t *)malloc(sizeof(queue_node_t));
pnode->item = item;
pthread_mutex_lock(&queue->lock);
{
insert_list_last(&queue->head, &pnode->entry);
queue->size++;
}
pthread_mutex_unlock(&queue->lock);
}
void * queue_get(queue_t * queue) {
void * item = NULL;
pthread_mutex_lock(&queue->lock);
{
if (queue->size > 0) {
list_entry_t * pentry = remove_list_first(&queue->head);
queue_node_t * pnode = container_of(pentry, queue_node_t, entry);
item = pnode->item;
free(pnode);
queue->size--;
}
}
pthread_mutex_unlock(&queue->lock);
return item;
}
| 22.772727 | 70 | 0.661677 |
c8920ba296791b2eb944dd9d6fb6de59fbb82735 | 3,642 | h | C | arm_compute/graph/PassManager.h | alexjung/ComputeLibrary | a9d47c17791ebce45427ea6331bd6e35f7d721f4 | [
"MIT"
] | 1 | 2021-07-20T02:30:35.000Z | 2021-07-20T02:30:35.000Z | arm_compute/graph/PassManager.h | alexjung/ComputeLibrary | a9d47c17791ebce45427ea6331bd6e35f7d721f4 | [
"MIT"
] | null | null | null | arm_compute/graph/PassManager.h | alexjung/ComputeLibrary | a9d47c17791ebce45427ea6331bd6e35f7d721f4 | [
"MIT"
] | 1 | 2020-05-28T02:56:34.000Z | 2020-05-28T02:56:34.000Z | /*
* Copyright (c) 2018-2019 ARM Limited.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef ARM_COMPUTE_GRAPH_PASSMANAGER_H
#define ARM_COMPUTE_GRAPH_PASSMANAGER_H
#include "arm_compute/graph/IGraphMutator.h"
#include <memory>
#include <vector>
namespace arm_compute
{
namespace graph
{
// Forward declarations
class Graph;
/** Pass manager
*
* Responsible for performing the mutating graph passes with a given order
**/
class PassManager final
{
public:
/** Constructor */
PassManager();
/** Prevent instances of this class from being copied (As this class contains pointers) */
PassManager(const PassManager &) = delete;
/** Default move constructor */
PassManager(PassManager &&) = default;
/** Prevent instances of this class from being copied (As this class contains pointers) */
PassManager &operator=(const PassManager &) = delete;
/** Default move assignment operator */
PassManager &operator=(PassManager &&) = default;
/** Mutation passes accessors
*
* @return Returns the vector with the mutation passes that are to be executed on a graph
*/
const std::vector<std::unique_ptr<IGraphMutator>> &passes() const;
/** Accessor of a pass at a given index
*
* @param[in] index Index of the requested pass
*
* @return A pointer to the given pass if exists else nullptr
*/
IGraphMutator *pass(size_t index);
/** Appends a mutation pass
*
* @param[in] pass Pass to append
* @param[in] conditional (Optional) Append pass if true else false. Defaults to true.
*/
void append(std::unique_ptr<IGraphMutator> pass, bool conditional = true);
/** Clears all the passes */
void clear();
/** Runs all the mutation passes on a given graph
*
* @param[in, out] g Graph to run the mutations on
*/
void run_all(Graph &g);
/** Runs a mutation passes of a specific type on a given graph
*
* @param[in, out] g Graph to run the mutation on
* @param[in] type Type of the mutations to execute
*/
void run_type(Graph &g, IGraphMutator::MutationType type);
/** Runs a specific mutation pass on a given graph
*
* @param[in, out] g Graph to run the mutation on
* @param[in] index Index of the mutation to execute
*/
void run_index(Graph &g, size_t index);
private:
std::vector<std::unique_ptr<IGraphMutator>> _passes; /**< Vector of graph passes */
};
} // namespace graph
} // namespace arm_compute
#endif /* ARM_COMPUTE_GRAPH_PASSMANAGER_H */
| 36.42 | 94 | 0.69687 |
0887a61cbe84c248cf84ea255169c600e58ddac9 | 1,548 | h | C | System/Library/PrivateFrameworks/TSReading.framework/TSDSVGToBezierPathConverter.h | zhangkn/iOS14Header | 4323e9459ed6f6f5504ecbea2710bfd6c3d7c946 | [
"MIT"
] | 1 | 2020-11-04T15:43:01.000Z | 2020-11-04T15:43:01.000Z | System/Library/PrivateFrameworks/TSReading.framework/TSDSVGToBezierPathConverter.h | zhangkn/iOS14Header | 4323e9459ed6f6f5504ecbea2710bfd6c3d7c946 | [
"MIT"
] | null | null | null | System/Library/PrivateFrameworks/TSReading.framework/TSDSVGToBezierPathConverter.h | zhangkn/iOS14Header | 4323e9459ed6f6f5504ecbea2710bfd6c3d7c946 | [
"MIT"
] | null | null | null | /*
* This header is generated by classdump-dyld 1.0
* on Sunday, September 27, 2020 at 12:26:36 PM Mountain Standard Time
* Operating System: Version 14.0 (Build 18A373)
* Image Source: /System/Library/PrivateFrameworks/TSReading.framework/TSReading
* classdump-dyld is licensed under GPLv3, Copyright © 2013-2016 by Elias Limneos.
*/
#import <TSReading/TSReading-Structs.h>
#import <libobjc.A.dylib/NSXMLParserDelegate.h>
@class TSDBezierPath, NSString;
@interface TSDSVGToBezierPathConverter : NSObject <NSXMLParserDelegate> {
TSDBezierPath* mFileBezierPath;
NSString* mHiddenOnTag;
unsigned long long mHiddenOnTagNestedCount;
CGAffineTransform mGroupedAffineTransform;
unsigned long long mGroupedAffineTransformNestedCount;
BOOL mViewBoxFound;
CGRect mViewBox;
BOOL mUsesEvenOdd;
}
@property (readonly) unsigned long long hash;
@property (readonly) Class superclass;
@property (copy,readonly) NSString * description;
@property (copy,readonly) NSString * debugDescription;
+(CGPathRef)newPathFromSVGPathString:(id)arg1 ;
+(CGAffineTransform)transformFromSVGTransformAttributeString:(id)arg1 ;
+(CGPathRef)newPathFromSVGPathString:(id)arg1 shouldClosePathAtEnd:(BOOL)arg2 ;
+(CGPathRef)newPathFromSVGPolylineString:(id)arg1 ;
+(CGPathRef)newPathFromSVGPolygonString:(id)arg1 ;
-(void)parser:(id)arg1 didEndElement:(id)arg2 namespaceURI:(id)arg3 qualifiedName:(id)arg4 ;
-(void)parser:(id)arg1 didStartElement:(id)arg2 namespaceURI:(id)arg3 qualifiedName:(id)arg4 attributes:(id)arg5 ;
-(id)bezierPathFromSVGData:(id)arg1 ;
@end
| 37.756098 | 114 | 0.80168 |
ae77ff7b94a333002e84ed3c3d4e6f3c046c99b0 | 6,135 | h | C | Plugins/org.commontk.dah.core/ctkDicomAppHostingTypes.h | lassoan/CTK | ba271a053217d26e90dee35837cd3979c3bb5b8b | [
"Apache-2.0"
] | 1 | 2015-05-13T02:09:20.000Z | 2015-05-13T02:09:20.000Z | Plugins/org.commontk.dah.core/ctkDicomAppHostingTypes.h | medInria/CTK | 00694c9f8a0da6ee28fb079902e6a8c3ec428058 | [
"Apache-2.0"
] | null | null | null | Plugins/org.commontk.dah.core/ctkDicomAppHostingTypes.h | medInria/CTK | 00694c9f8a0da6ee28fb079902e6a8c3ec428058 | [
"Apache-2.0"
] | 1 | 2018-10-21T12:09:24.000Z | 2018-10-21T12:09:24.000Z | /*=============================================================================
Library: CTK
Copyright (c) German Cancer Research Center,
Division of Medical and Biological Informatics
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
=============================================================================*/
#ifndef CTKDICOMAPPHOSTINGTYPES_H
#define CTKDICOMAPPHOSTINGTYPES_H
// Qt includes
#include <QString>
#include <QList>
#ifdef ERROR
# error Try to reorder include files (this one first) \
or write #undef ERROR before including this header. \
Cause of this problem may be dcmimage.h, which indirectly \
includes windows.h.
#endif
#include <org_commontk_dah_core_Export.h>
/**
* \brief Typedefs and classes defined in the interfaces of DICOM Supplement 118.
*
*/
namespace ctkDicomAppHosting {
//----------------------------------------------------------------------------
enum State {
IDLE,
INPROGRESS,
COMPLETED,
SUSPENDED,
CANCELED,
EXIT
};
//----------------------------------------------------------------------------
enum StatusType {
INFORMATION,
WARNING,
ERROR,
FATALERROR
};
//----------------------------------------------------------------------------
struct Status {
Status():statusType(INFORMATION){}
StatusType statusType;
QString codingSchemeDesignator;
QString codeValue;
QString codeMeaning;
};
//----------------------------------------------------------------------------
struct ObjectLocator {
ObjectLocator():length(0), offset(0){}
QString locator;
QString source;
QString transferSyntax;
qint64 length;
qint64 offset;
QString URI;
};
//----------------------------------------------------------------------------
struct ObjectDescriptor {
QString descriptorUUID;
QString mimeType;
QString classUID;
QString transferSyntaxUID;
QString modality;
};
//----------------------------------------------------------------------------
typedef QList<ObjectDescriptor> ArrayOfObjectDescriptors;
//----------------------------------------------------------------------------
struct Series {
QString seriesUID;
ArrayOfObjectDescriptors objectDescriptors;
};
//----------------------------------------------------------------------------
struct Study {
QString studyUID;
ArrayOfObjectDescriptors objectDescriptors;
QList<Series> series;
};
//----------------------------------------------------------------------------
struct Patient {
QString name;
QString id;
QString assigningAuthority;
QString sex;
QString birthDate;
ArrayOfObjectDescriptors objectDescriptors;
QList<Study> studies;
};
//----------------------------------------------------------------------------
struct AvailableData {
ArrayOfObjectDescriptors objectDescriptors;
QList<Patient> patients;
};
}
//----------------------------------------------------------------------------
// Comparison operators
bool org_commontk_dah_core_EXPORT operator ==(const ctkDicomAppHosting::Status& left,
const ctkDicomAppHosting::Status& right);
bool org_commontk_dah_core_EXPORT operator !=(const ctkDicomAppHosting::Status& left,
const ctkDicomAppHosting::Status& right);
bool org_commontk_dah_core_EXPORT operator ==(const ctkDicomAppHosting::ObjectLocator& left,
const ctkDicomAppHosting::ObjectLocator& right);
bool org_commontk_dah_core_EXPORT operator !=(const ctkDicomAppHosting::ObjectLocator& left,
const ctkDicomAppHosting::ObjectLocator& right);
bool org_commontk_dah_core_EXPORT operator ==(const ctkDicomAppHosting::ObjectDescriptor& left,
const ctkDicomAppHosting::ObjectDescriptor& right);
bool org_commontk_dah_core_EXPORT operator !=(const ctkDicomAppHosting::ObjectDescriptor& left,
const ctkDicomAppHosting::ObjectDescriptor& right);
bool org_commontk_dah_core_EXPORT operator ==(const ctkDicomAppHosting::Series& left,
const ctkDicomAppHosting::Series& right);
bool org_commontk_dah_core_EXPORT operator !=(const ctkDicomAppHosting::Series& left,
const ctkDicomAppHosting::Series& right);
bool org_commontk_dah_core_EXPORT operator ==(const ctkDicomAppHosting::Study& left,
const ctkDicomAppHosting::Study& right);
bool org_commontk_dah_core_EXPORT operator !=(const ctkDicomAppHosting::Study& left,
const ctkDicomAppHosting::Study& right);
bool org_commontk_dah_core_EXPORT operator ==(const ctkDicomAppHosting::Patient& left,
const ctkDicomAppHosting::Patient& right);
bool org_commontk_dah_core_EXPORT operator !=(const ctkDicomAppHosting::Patient& left,
const ctkDicomAppHosting::Patient& right);
bool org_commontk_dah_core_EXPORT operator ==(const ctkDicomAppHosting::AvailableData& left,
const ctkDicomAppHosting::AvailableData& right);
bool org_commontk_dah_core_EXPORT operator !=(const ctkDicomAppHosting::AvailableData& left,
const ctkDicomAppHosting::AvailableData& right);
#endif // CTKDICOMAPPHOSTINGTYPES
| 35.877193 | 97 | 0.557457 |
b7dc31d906a8c2ed63f7aef9d18d5078a401fa63 | 730 | c | C | STM/Ex2/LED_Speed.c | crazymousethief/University-Course | fcf53fb23472200646a9e0c155931d75c9873d94 | [
"MIT"
] | null | null | null | STM/Ex2/LED_Speed.c | crazymousethief/University-Course | fcf53fb23472200646a9e0c155931d75c9873d94 | [
"MIT"
] | null | null | null | STM/Ex2/LED_Speed.c | crazymousethief/University-Course | fcf53fb23472200646a9e0c155931d75c9873d94 | [
"MIT"
] | null | null | null | #include <reg52.h>
sbit up = P3^5;
sbit down = P3^4;
int s = 1;
void delay_100ms(unsigned, void (*)(void));
void UD();
void main() {
P0 = 0x00;
while (1) {
delay_100ms(s, UD);
P0 = ~P0;
}
}
void UD() {
if (up == 0 && s != 1) {
while (1) {if (up == 1) break;}
s--;
}
if (down == 0 && s != 10) {
while (1) {if (down == 1) break;}
s++;
}
}
void delay_100ms(unsigned i, void (*f)(void)) {
unsigned num = 0;
TMOD = 0x02;
TH0 = 0x70;
TL0 = 0x70;
TR0 = 1;
for (;;) {
f();
if (TF0) {
TF0 = 0;
num++;
}
if (num == 640*i) return;
}
}
| 18.717949 | 50 | 0.375342 |
d3e423af3124d1bfec4c6c07149d8509f329a075 | 809,599 | h | C | Chip/inc/kinetis/MK20DZ10.h | 498143049/smartcar | b1e58dacbe88a883034f48ae008df0b97d108e2a | [
"MIT"
] | null | null | null | Chip/inc/kinetis/MK20DZ10.h | 498143049/smartcar | b1e58dacbe88a883034f48ae008df0b97d108e2a | [
"MIT"
] | null | null | null | Chip/inc/kinetis/MK20DZ10.h | 498143049/smartcar | b1e58dacbe88a883034f48ae008df0b97d108e2a | [
"MIT"
] | null | null | null | /*
** ###################################################################
** Processors: MK20DN512ZVLK10
** MK20DX256ZVLK10
** MK20DN512ZVLL10
** MK20DX256ZVLL10
** MK20DN512ZVLQ10
** MK20DX128ZVLQ10
** MK20DX256ZVLQ10
** MK20DN512ZVMB10
** MK20DX256ZVMB10
** MK20DN512ZVMC10
** MK20DX256ZVMC10
** MK20DN512ZVMD10
** MK20DX256ZVMD10
** MK20DX128ZVMD10
**
** Compilers: Freescale C/C++ for Embedded ARM
** GNU ARM C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K20P144M100SF2RM, Rev. 5, 8 May 2011
** Version: rev. 1.1, 2011-06-15
**
** Abstract:
** This header file implements peripheral memory map for MK20DZ10
** processor.
**
** Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2011-03-30)
** Initial version.
** Changes with respect to the previous MK10NxxVMD100 header file:
** RTC - CCR register removed. Replaced by IER register.
** CRC - added CTRLHU register for 8-bit access to the CTRL register.
** FB - bit FB_CSCR_EXALE renamed to FB_CSCR_EXTS.
** SIM- bit group FSIZE in SIM_FCFG1 split into groups PFSIZE and NVMSIZE.
** Added registers for core modules - CoreDebug, DWT, ETB, ETF, ETM, FPB, ITM, TPIU.
** - rev. 1.1 (2011-06-15)
** Registers updated according to the new reference manual revision - Rev. 5, 8 May 2011
** I2S - bit SSIEN in I2S_CR register renamed to I2SEN.
** SDHC - bit VOLTSEL in SDHC_VENDOR register removed.
** TSI - registers TSI_CNTR1 to TSI_CNTR15, bit group CNTN renamed to CTN1, bit group CNTN1 renamed to CTN.
**
** ###################################################################
*/
/**
* @file MK20DZ10.h
* @version 1.1
* @date 2011-06-15
* @brief Peripheral memory map for MK20DZ10
*
* This header file implements peripheral memory map for MK20DZ10 processor.
*/
/* ----------------------------------------------------------------------------
-- MCU activation
---------------------------------------------------------------------------- */
/* Prevention from multiple including the same memory map */
#if !defined(MCU_MK20DZ10) /* Check if memory map has not been already included */
#define MCU_MK20DZ10
/* Check if another memory map has not been also included */
#if (defined(MCU_ACTIVE))
#error MK20DZ10 memory map: There is already included another memory map. Only one memory map can be included.
#endif /* (defined(MCU_ACTIVE)) */
#define MCU_ACTIVE
#include <stdint.h>
/** Memory map version 1.1 */
#define MCU_MEM_MAP_VERSION 0x0101u
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/**
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
typedef enum {
INT_Initial_Stack_Pointer = 0, /**< Initial stack pointer */
INT_Initial_Program_Counter = 1, /**< Initial program counter */
INT_NMI = 2, /**< Non-maskable interrupt */
INT_Hard_Fault = 3, /**< Hard fault exception */
INT_Mem_Manage_Fault = 4, /**< Memory Manage Fault */
INT_Bus_Fault = 5, /**< Bus fault exception */
INT_Usage_Fault = 6, /**< Usage fault exception */
INT_Reserved7 = 7, /**< Reserved interrupt 7 */
INT_Reserved8 = 8, /**< Reserved interrupt 8 */
INT_Reserved9 = 9, /**< Reserved interrupt 9 */
INT_Reserved10 = 10, /**< Reserved interrupt 10 */
INT_SVCall = 11, /**< A supervisor call exception */
INT_DebugMonitor = 12, /**< Debug Monitor */
INT_Reserved13 = 13, /**< Reserved interrupt 13 */
INT_PendableSrvReq = 14, /**< PendSV exception - request for system level service */
INT_SysTick = 15, /**< SysTick Interrupt */
INT_DMA0 = 16, /**< DMA Channel 0 Transfer Complete */
INT_DMA1 = 17, /**< DMA Channel 1 Transfer Complete */
INT_DMA2 = 18, /**< DMA Channel 2 Transfer Complete */
INT_DMA3 = 19, /**< DMA Channel 3 Transfer Complete */
INT_DMA4 = 20, /**< DMA Channel 4 Transfer Complete */
INT_DMA5 = 21, /**< DMA Channel 5 Transfer Complete */
INT_DMA6 = 22, /**< DMA Channel 6 Transfer Complete */
INT_DMA7 = 23, /**< DMA Channel 7 Transfer Complete */
INT_DMA8 = 24, /**< DMA Channel 8 Transfer Complete */
INT_DMA9 = 25, /**< DMA Channel 9 Transfer Complete */
INT_DMA10 = 26, /**< DMA Channel 10 Transfer Complete */
INT_DMA11 = 27, /**< DMA Channel 11 Transfer Complete */
INT_DMA12 = 28, /**< DMA Channel 12 Transfer Complete */
INT_DMA13 = 29, /**< DMA Channel 13 Transfer Complete */
INT_DMA14 = 30, /**< DMA Channel 14 Transfer Complete */
INT_DMA15 = 31, /**< DMA Channel 15 Transfer Complete */
INT_DMA_Error = 32, /**< DMA Error Interrupt */
INT_MCM = 33, /**< Normal Interrupt */
INT_FTFL = 34, /**< FTFL Interrupt */
INT_Read_Collision = 35, /**< Read Collision Interrupt */
INT_LVD_LVW = 36, /**< Low Voltage Detect, Low Voltage Warning */
INT_LLW = 37, /**< Low Leakage Wakeup */
INT_Watchdog = 38, /**< WDOG Interrupt */
INT_Reserved39 = 39, /**< Reserved interrupt 39 */
INT_I2C0 = 40, /**< I2C0 interrupt */
INT_I2C1 = 41, /**< I2C1 interrupt */
INT_SPI0 = 42, /**< SPI0 Interrupt */
INT_SPI1 = 43, /**< SPI1 Interrupt */
INT_SPI2 = 44, /**< SPI2 Interrupt */
INT_CAN0_ORed_Message_buffer = 45, /**< CAN0 OR'd Message Buffers Interrupt */
INT_CAN0_Bus_Off = 46, /**< CAN0 Bus Off Interrupt */
INT_CAN0_Error = 47, /**< CAN0 Error Interrupt */
INT_CAN0_Tx_Warning = 48, /**< CAN0 Tx Warning Interrupt */
INT_CAN0_Rx_Warning = 49, /**< CAN0 Rx Warning Interrupt */
INT_CAN0_Wake_Up = 50, /**< CAN0 Wake Up Interrupt */
INT_Reserved51 = 51, /**< Reserved interrupt 51 */
INT_Reserved52 = 52, /**< Reserved interrupt 52 */
INT_CAN1_ORed_Message_buffer = 53, /**< CAN1 OR'd Message Buffers Interrupt */
INT_CAN1_Bus_Off = 54, /**< CAN1 Bus Off Interrupt */
INT_CAN1_Error = 55, /**< CAN1 Error Interrupt */
INT_CAN1_Tx_Warning = 56, /**< CAN1 Tx Warning Interrupt */
INT_CAN1_Rx_Warning = 57, /**< CAN1 Rx Warning Interrupt */
INT_CAN1_Wake_Up = 58, /**< CAN1 Wake Up Interrupt */
INT_Reserved59 = 59, /**< Reserved interrupt 59 */
INT_Reserved60 = 60, /**< Reserved interrupt 60 */
INT_UART0_RX_TX = 61, /**< UART0 Receive/Transmit interrupt */
INT_UART0_ERR = 62, /**< UART0 Error interrupt */
INT_UART1_RX_TX = 63, /**< UART1 Receive/Transmit interrupt */
INT_UART1_ERR = 64, /**< UART1 Error interrupt */
INT_UART2_RX_TX = 65, /**< UART2 Receive/Transmit interrupt */
INT_UART2_ERR = 66, /**< UART2 Error interrupt */
INT_UART3_RX_TX = 67, /**< UART3 Receive/Transmit interrupt */
INT_UART3_ERR = 68, /**< UART3 Error interrupt */
INT_UART4_RX_TX = 69, /**< UART4 Receive/Transmit interrupt */
INT_UART4_ERR = 70, /**< UART4 Error interrupt */
INT_UART5_RX_TX = 71, /**< UART5 Receive/Transmit interrupt */
INT_UART5_ERR = 72, /**< UART5 Error interrupt */
INT_ADC0 = 73, /**< ADC0 interrupt */
INT_ADC1 = 74, /**< ADC1 interrupt */
INT_CMP0 = 75, /**< CMP0 interrupt */
INT_CMP1 = 76, /**< CMP1 interrupt */
INT_CMP2 = 77, /**< CMP2 interrupt */
INT_FTM0 = 78, /**< FTM0 fault, overflow and channels interrupt */
INT_FTM1 = 79, /**< FTM1 fault, overflow and channels interrupt */
INT_FTM2 = 80, /**< FTM2 fault, overflow and channels interrupt */
INT_CMT = 81, /**< CMT interrupt */
INT_RTC = 82, /**< RTC interrupt */
INT_Reserved83 = 83, /**< Reserved interrupt 83 */
INT_PIT0 = 84, /**< PIT timer channel 0 interrupt */
INT_PIT1 = 85, /**< PIT timer channel 1 interrupt */
INT_PIT2 = 86, /**< PIT timer channel 2 interrupt */
INT_PIT3 = 87, /**< PIT timer channel 3 interrupt */
INT_PDB0 = 88, /**< PDB0 Interrupt */
INT_USB0 = 89, /**< USB0 interrupt */
INT_USBDCD = 90, /**< USBDCD Interrupt */
INT_Reserved91 = 91, /**< Reserved interrupt 91 */
INT_Reserved92 = 92, /**< Reserved interrupt 92 */
INT_Reserved93 = 93, /**< Reserved interrupt 93 */
INT_Reserved94 = 94, /**< Reserved interrupt 94 */
INT_I2S0 = 95, /**< I2S0 Interrupt */
INT_SDHC = 96, /**< SDHC Interrupt */
INT_DAC0 = 97, /**< DAC0 interrupt */
INT_DAC1 = 98, /**< DAC1 interrupt */
INT_TSI0 = 99, /**< TSI0 Interrupt */
INT_MCG = 100, /**< MCG Interrupt */
INT_LPTimer = 101, /**< LPTimer interrupt */
INT_Reserved102 = 102, /**< Reserved interrupt 102 */
INT_PORTA = 103, /**< Port A interrupt */
INT_PORTB = 104, /**< Port B interrupt */
INT_PORTC = 105, /**< Port C interrupt */
INT_PORTD = 106, /**< Port D interrupt */
INT_PORTE = 107, /**< Port E interrupt */
INT_Reserved108 = 108, /**< Reserved interrupt 108 */
INT_Reserved109 = 109, /**< Reserved interrupt 109 */
INT_Reserved110 = 110, /**< Reserved interrupt 110 */
INT_Reserved111 = 111, /**< Reserved interrupt 111 */
INT_Reserved112 = 112, /**< Reserved interrupt 112 */
INT_Reserved113 = 113, /**< Reserved interrupt 113 */
INT_Reserved114 = 114, /**< Reserved interrupt 114 */
INT_Reserved115 = 115, /**< Reserved interrupt 115 */
INT_Reserved116 = 116, /**< Reserved interrupt 116 */
INT_Reserved117 = 117, /**< Reserved interrupt 117 */
INT_Reserved118 = 118, /**< Reserved interrupt 118 */
INT_Reserved119 = 119 /**< Reserved interrupt 119 */
} IRQInterruptIndex;
/**
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Peripheral type defines
---------------------------------------------------------------------------- */
/**
* @addtogroup Peripheral_defines Peripheral type defines
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC
---------------------------------------------------------------------------- */
/**
* @addtogroup ADC_Peripheral ADC
* @{
*/
/** ADC - Peripheral register structure */
typedef struct ADC_MemMap {
uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
uint32_t CV1; /**< Compare value registers, offset: 0x18 */
uint32_t CV2; /**< Compare value registers, offset: 0x1C */
uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
uint32_t PGA; /**< ADC PGA register, offset: 0x50 */
uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
} volatile *ADC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register accessors */
#define ADC_SC1_REG(base,index) ((base)->SC1[index])
#define ADC_CFG1_REG(base) ((base)->CFG1)
#define ADC_CFG2_REG(base) ((base)->CFG2)
#define ADC_R_REG(base,index) ((base)->R[index])
#define ADC_CV1_REG(base) ((base)->CV1)
#define ADC_CV2_REG(base) ((base)->CV2)
#define ADC_SC2_REG(base) ((base)->SC2)
#define ADC_SC3_REG(base) ((base)->SC3)
#define ADC_OFS_REG(base) ((base)->OFS)
#define ADC_PG_REG(base) ((base)->PG)
#define ADC_MG_REG(base) ((base)->MG)
#define ADC_CLPD_REG(base) ((base)->CLPD)
#define ADC_CLPS_REG(base) ((base)->CLPS)
#define ADC_CLP4_REG(base) ((base)->CLP4)
#define ADC_CLP3_REG(base) ((base)->CLP3)
#define ADC_CLP2_REG(base) ((base)->CLP2)
#define ADC_CLP1_REG(base) ((base)->CLP1)
#define ADC_CLP0_REG(base) ((base)->CLP0)
#define ADC_PGA_REG(base) ((base)->PGA)
#define ADC_CLMD_REG(base) ((base)->CLMD)
#define ADC_CLMS_REG(base) ((base)->CLMS)
#define ADC_CLM4_REG(base) ((base)->CLM4)
#define ADC_CLM3_REG(base) ((base)->CLM3)
#define ADC_CLM2_REG(base) ((base)->CLM2)
#define ADC_CLM1_REG(base) ((base)->CLM1)
#define ADC_CLM0_REG(base) ((base)->CLM0)
/**
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/* SC1 Bit Fields */
#define ADC_SC1_ADCH_MASK 0x1Fu
#define ADC_SC1_ADCH_SHIFT 0
#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
#define ADC_SC1_DIFF_MASK 0x20u
#define ADC_SC1_DIFF_SHIFT 5
#define ADC_SC1_AIEN_MASK 0x40u
#define ADC_SC1_AIEN_SHIFT 6
#define ADC_SC1_COCO_MASK 0x80u
#define ADC_SC1_COCO_SHIFT 7
/* CFG1 Bit Fields */
#define ADC_CFG1_ADICLK_MASK 0x3u
#define ADC_CFG1_ADICLK_SHIFT 0
#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
#define ADC_CFG1_MODE_MASK 0xCu
#define ADC_CFG1_MODE_SHIFT 2
#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
#define ADC_CFG1_ADLSMP_MASK 0x10u
#define ADC_CFG1_ADLSMP_SHIFT 4
#define ADC_CFG1_ADIV_MASK 0x60u
#define ADC_CFG1_ADIV_SHIFT 5
#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
#define ADC_CFG1_ADLPC_MASK 0x80u
#define ADC_CFG1_ADLPC_SHIFT 7
/* CFG2 Bit Fields */
#define ADC_CFG2_ADLSTS_MASK 0x3u
#define ADC_CFG2_ADLSTS_SHIFT 0
#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
#define ADC_CFG2_ADHSC_MASK 0x4u
#define ADC_CFG2_ADHSC_SHIFT 2
#define ADC_CFG2_ADACKEN_MASK 0x8u
#define ADC_CFG2_ADACKEN_SHIFT 3
#define ADC_CFG2_MUXSEL_MASK 0x10u
#define ADC_CFG2_MUXSEL_SHIFT 4
/* R Bit Fields */
#define ADC_R_D_MASK 0xFFFFu
#define ADC_R_D_SHIFT 0
#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
/* CV1 Bit Fields */
#define ADC_CV1_CV_MASK 0xFFFFu
#define ADC_CV1_CV_SHIFT 0
#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
/* CV2 Bit Fields */
#define ADC_CV2_CV_MASK 0xFFFFu
#define ADC_CV2_CV_SHIFT 0
#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
/* SC2 Bit Fields */
#define ADC_SC2_REFSEL_MASK 0x3u
#define ADC_SC2_REFSEL_SHIFT 0
#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
#define ADC_SC2_DMAEN_MASK 0x4u
#define ADC_SC2_DMAEN_SHIFT 2
#define ADC_SC2_ACREN_MASK 0x8u
#define ADC_SC2_ACREN_SHIFT 3
#define ADC_SC2_ACFGT_MASK 0x10u
#define ADC_SC2_ACFGT_SHIFT 4
#define ADC_SC2_ACFE_MASK 0x20u
#define ADC_SC2_ACFE_SHIFT 5
#define ADC_SC2_ADTRG_MASK 0x40u
#define ADC_SC2_ADTRG_SHIFT 6
#define ADC_SC2_ADACT_MASK 0x80u
#define ADC_SC2_ADACT_SHIFT 7
/* SC3 Bit Fields */
#define ADC_SC3_AVGS_MASK 0x3u
#define ADC_SC3_AVGS_SHIFT 0
#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
#define ADC_SC3_AVGE_MASK 0x4u
#define ADC_SC3_AVGE_SHIFT 2
#define ADC_SC3_ADCO_MASK 0x8u
#define ADC_SC3_ADCO_SHIFT 3
#define ADC_SC3_CALF_MASK 0x40u
#define ADC_SC3_CALF_SHIFT 6
#define ADC_SC3_CAL_MASK 0x80u
#define ADC_SC3_CAL_SHIFT 7
/* OFS Bit Fields */
#define ADC_OFS_OFS_MASK 0xFFFFu
#define ADC_OFS_OFS_SHIFT 0
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
/* PG Bit Fields */
#define ADC_PG_PG_MASK 0xFFFFu
#define ADC_PG_PG_SHIFT 0
#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
/* MG Bit Fields */
#define ADC_MG_MG_MASK 0xFFFFu
#define ADC_MG_MG_SHIFT 0
#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
/* CLPD Bit Fields */
#define ADC_CLPD_CLPD_MASK 0x3Fu
#define ADC_CLPD_CLPD_SHIFT 0
#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
/* CLPS Bit Fields */
#define ADC_CLPS_CLPS_MASK 0x3Fu
#define ADC_CLPS_CLPS_SHIFT 0
#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
/* CLP4 Bit Fields */
#define ADC_CLP4_CLP4_MASK 0x3FFu
#define ADC_CLP4_CLP4_SHIFT 0
#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
/* CLP3 Bit Fields */
#define ADC_CLP3_CLP3_MASK 0x1FFu
#define ADC_CLP3_CLP3_SHIFT 0
#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
/* CLP2 Bit Fields */
#define ADC_CLP2_CLP2_MASK 0xFFu
#define ADC_CLP2_CLP2_SHIFT 0
#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
/* CLP1 Bit Fields */
#define ADC_CLP1_CLP1_MASK 0x7Fu
#define ADC_CLP1_CLP1_SHIFT 0
#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
/* CLP0 Bit Fields */
#define ADC_CLP0_CLP0_MASK 0x3Fu
#define ADC_CLP0_CLP0_SHIFT 0
#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
/* PGA Bit Fields */
#define ADC_PGA_PGAG_MASK 0xF0000u
#define ADC_PGA_PGAG_SHIFT 16
#define ADC_PGA_PGAG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PGA_PGAG_SHIFT))&ADC_PGA_PGAG_MASK)
#define ADC_PGA_PGAEN_MASK 0x800000u
#define ADC_PGA_PGAEN_SHIFT 23
/* CLMD Bit Fields */
#define ADC_CLMD_CLMD_MASK 0x3Fu
#define ADC_CLMD_CLMD_SHIFT 0
#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
/* CLMS Bit Fields */
#define ADC_CLMS_CLMS_MASK 0x3Fu
#define ADC_CLMS_CLMS_SHIFT 0
#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
/* CLM4 Bit Fields */
#define ADC_CLM4_CLM4_MASK 0x3FFu
#define ADC_CLM4_CLM4_SHIFT 0
#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
/* CLM3 Bit Fields */
#define ADC_CLM3_CLM3_MASK 0x1FFu
#define ADC_CLM3_CLM3_SHIFT 0
#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
/* CLM2 Bit Fields */
#define ADC_CLM2_CLM2_MASK 0xFFu
#define ADC_CLM2_CLM2_SHIFT 0
#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
/* CLM1 Bit Fields */
#define ADC_CLM1_CLM1_MASK 0x7Fu
#define ADC_CLM1_CLM1_SHIFT 0
#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
/* CLM0 Bit Fields */
#define ADC_CLM0_CLM0_MASK 0x3Fu
#define ADC_CLM0_CLM0_SHIFT 0
#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
/**
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base pointer */
#define ADC0_BASE_PTR ((ADC_MemMapPtr)0x4003B000u)
/** Peripheral ADC1 base pointer */
#define ADC1_BASE_PTR ((ADC_MemMapPtr)0x400BB000u)
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register instance definitions */
/* ADC0 */
#define ADC0_SC1A ADC_SC1_REG(ADC0_BASE_PTR,0)
#define ADC0_SC1B ADC_SC1_REG(ADC0_BASE_PTR,1)
#define ADC0_CFG1 ADC_CFG1_REG(ADC0_BASE_PTR)
#define ADC0_CFG2 ADC_CFG2_REG(ADC0_BASE_PTR)
#define ADC0_RA ADC_R_REG(ADC0_BASE_PTR,0)
#define ADC0_RB ADC_R_REG(ADC0_BASE_PTR,1)
#define ADC0_CV1 ADC_CV1_REG(ADC0_BASE_PTR)
#define ADC0_CV2 ADC_CV2_REG(ADC0_BASE_PTR)
#define ADC0_SC2 ADC_SC2_REG(ADC0_BASE_PTR)
#define ADC0_SC3 ADC_SC3_REG(ADC0_BASE_PTR)
#define ADC0_OFS ADC_OFS_REG(ADC0_BASE_PTR)
#define ADC0_PG ADC_PG_REG(ADC0_BASE_PTR)
#define ADC0_MG ADC_MG_REG(ADC0_BASE_PTR)
#define ADC0_CLPD ADC_CLPD_REG(ADC0_BASE_PTR)
#define ADC0_CLPS ADC_CLPS_REG(ADC0_BASE_PTR)
#define ADC0_CLP4 ADC_CLP4_REG(ADC0_BASE_PTR)
#define ADC0_CLP3 ADC_CLP3_REG(ADC0_BASE_PTR)
#define ADC0_CLP2 ADC_CLP2_REG(ADC0_BASE_PTR)
#define ADC0_CLP1 ADC_CLP1_REG(ADC0_BASE_PTR)
#define ADC0_CLP0 ADC_CLP0_REG(ADC0_BASE_PTR)
#define ADC0_PGA ADC_PGA_REG(ADC0_BASE_PTR)
#define ADC0_CLMD ADC_CLMD_REG(ADC0_BASE_PTR)
#define ADC0_CLMS ADC_CLMS_REG(ADC0_BASE_PTR)
#define ADC0_CLM4 ADC_CLM4_REG(ADC0_BASE_PTR)
#define ADC0_CLM3 ADC_CLM3_REG(ADC0_BASE_PTR)
#define ADC0_CLM2 ADC_CLM2_REG(ADC0_BASE_PTR)
#define ADC0_CLM1 ADC_CLM1_REG(ADC0_BASE_PTR)
#define ADC0_CLM0 ADC_CLM0_REG(ADC0_BASE_PTR)
/* ADC1 */
#define ADC1_SC1A ADC_SC1_REG(ADC1_BASE_PTR,0)
#define ADC1_SC1B ADC_SC1_REG(ADC1_BASE_PTR,1)
#define ADC1_CFG1 ADC_CFG1_REG(ADC1_BASE_PTR)
#define ADC1_CFG2 ADC_CFG2_REG(ADC1_BASE_PTR)
#define ADC1_RA ADC_R_REG(ADC1_BASE_PTR,0)
#define ADC1_RB ADC_R_REG(ADC1_BASE_PTR,1)
#define ADC1_CV1 ADC_CV1_REG(ADC1_BASE_PTR)
#define ADC1_CV2 ADC_CV2_REG(ADC1_BASE_PTR)
#define ADC1_SC2 ADC_SC2_REG(ADC1_BASE_PTR)
#define ADC1_SC3 ADC_SC3_REG(ADC1_BASE_PTR)
#define ADC1_OFS ADC_OFS_REG(ADC1_BASE_PTR)
#define ADC1_PG ADC_PG_REG(ADC1_BASE_PTR)
#define ADC1_MG ADC_MG_REG(ADC1_BASE_PTR)
#define ADC1_CLPD ADC_CLPD_REG(ADC1_BASE_PTR)
#define ADC1_CLPS ADC_CLPS_REG(ADC1_BASE_PTR)
#define ADC1_CLP4 ADC_CLP4_REG(ADC1_BASE_PTR)
#define ADC1_CLP3 ADC_CLP3_REG(ADC1_BASE_PTR)
#define ADC1_CLP2 ADC_CLP2_REG(ADC1_BASE_PTR)
#define ADC1_CLP1 ADC_CLP1_REG(ADC1_BASE_PTR)
#define ADC1_CLP0 ADC_CLP0_REG(ADC1_BASE_PTR)
#define ADC1_PGA ADC_PGA_REG(ADC1_BASE_PTR)
#define ADC1_CLMD ADC_CLMD_REG(ADC1_BASE_PTR)
#define ADC1_CLMS ADC_CLMS_REG(ADC1_BASE_PTR)
#define ADC1_CLM4 ADC_CLM4_REG(ADC1_BASE_PTR)
#define ADC1_CLM3 ADC_CLM3_REG(ADC1_BASE_PTR)
#define ADC1_CLM2 ADC_CLM2_REG(ADC1_BASE_PTR)
#define ADC1_CLM1 ADC_CLM1_REG(ADC1_BASE_PTR)
#define ADC1_CLM0 ADC_CLM0_REG(ADC1_BASE_PTR)
/* ADC - Register array accessors */
#define ADC0_SC1(index) ADC_SC1_REG(ADC0_BASE_PTR,index)
#define ADC1_SC1(index) ADC_SC1_REG(ADC1_BASE_PTR,index)
#define ADC0_R(index) ADC_R_REG(ADC0_BASE_PTR,index)
#define ADC1_R(index) ADC_R_REG(ADC1_BASE_PTR,index)
/**
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/**
* @}
*/ /* end of group ADC_Peripheral */
/* ----------------------------------------------------------------------------
-- AIPS
---------------------------------------------------------------------------- */
/**
* @addtogroup AIPS_Peripheral AIPS
* @{
*/
/** AIPS - Peripheral register structure */
typedef struct AIPS_MemMap {
uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
uint8_t RESERVED_0[28];
uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
uint8_t RESERVED_1[16];
uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
} volatile *AIPS_MemMapPtr;
/* ----------------------------------------------------------------------------
-- AIPS - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
* @{
*/
/* AIPS - Register accessors */
#define AIPS_MPRA_REG(base) ((base)->MPRA)
#define AIPS_PACRA_REG(base) ((base)->PACRA)
#define AIPS_PACRB_REG(base) ((base)->PACRB)
#define AIPS_PACRC_REG(base) ((base)->PACRC)
#define AIPS_PACRD_REG(base) ((base)->PACRD)
#define AIPS_PACRE_REG(base) ((base)->PACRE)
#define AIPS_PACRF_REG(base) ((base)->PACRF)
#define AIPS_PACRG_REG(base) ((base)->PACRG)
#define AIPS_PACRH_REG(base) ((base)->PACRH)
#define AIPS_PACRI_REG(base) ((base)->PACRI)
#define AIPS_PACRJ_REG(base) ((base)->PACRJ)
#define AIPS_PACRK_REG(base) ((base)->PACRK)
#define AIPS_PACRL_REG(base) ((base)->PACRL)
#define AIPS_PACRM_REG(base) ((base)->PACRM)
#define AIPS_PACRN_REG(base) ((base)->PACRN)
#define AIPS_PACRO_REG(base) ((base)->PACRO)
#define AIPS_PACRP_REG(base) ((base)->PACRP)
/**
* @}
*/ /* end of group AIPS_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- AIPS Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup AIPS_Register_Masks AIPS Register Masks
* @{
*/
/* MPRA Bit Fields */
#define AIPS_MPRA_MPL5_MASK 0x100u
#define AIPS_MPRA_MPL5_SHIFT 8
#define AIPS_MPRA_MTW5_MASK 0x200u
#define AIPS_MPRA_MTW5_SHIFT 9
#define AIPS_MPRA_MTR5_MASK 0x400u
#define AIPS_MPRA_MTR5_SHIFT 10
#define AIPS_MPRA_MPL4_MASK 0x1000u
#define AIPS_MPRA_MPL4_SHIFT 12
#define AIPS_MPRA_MTW4_MASK 0x2000u
#define AIPS_MPRA_MTW4_SHIFT 13
#define AIPS_MPRA_MTR4_MASK 0x4000u
#define AIPS_MPRA_MTR4_SHIFT 14
#define AIPS_MPRA_MPL3_MASK 0x10000u
#define AIPS_MPRA_MPL3_SHIFT 16
#define AIPS_MPRA_MTW3_MASK 0x20000u
#define AIPS_MPRA_MTW3_SHIFT 17
#define AIPS_MPRA_MTR3_MASK 0x40000u
#define AIPS_MPRA_MTR3_SHIFT 18
#define AIPS_MPRA_MPL2_MASK 0x100000u
#define AIPS_MPRA_MPL2_SHIFT 20
#define AIPS_MPRA_MTW2_MASK 0x200000u
#define AIPS_MPRA_MTW2_SHIFT 21
#define AIPS_MPRA_MTR2_MASK 0x400000u
#define AIPS_MPRA_MTR2_SHIFT 22
#define AIPS_MPRA_MPL1_MASK 0x1000000u
#define AIPS_MPRA_MPL1_SHIFT 24
#define AIPS_MPRA_MTW1_MASK 0x2000000u
#define AIPS_MPRA_MTW1_SHIFT 25
#define AIPS_MPRA_MTR1_MASK 0x4000000u
#define AIPS_MPRA_MTR1_SHIFT 26
#define AIPS_MPRA_MPL0_MASK 0x10000000u
#define AIPS_MPRA_MPL0_SHIFT 28
#define AIPS_MPRA_MTW0_MASK 0x20000000u
#define AIPS_MPRA_MTW0_SHIFT 29
#define AIPS_MPRA_MTR0_MASK 0x40000000u
#define AIPS_MPRA_MTR0_SHIFT 30
/* PACRA Bit Fields */
#define AIPS_PACRA_TP7_MASK 0x1u
#define AIPS_PACRA_TP7_SHIFT 0
#define AIPS_PACRA_WP7_MASK 0x2u
#define AIPS_PACRA_WP7_SHIFT 1
#define AIPS_PACRA_SP7_MASK 0x4u
#define AIPS_PACRA_SP7_SHIFT 2
#define AIPS_PACRA_TP6_MASK 0x10u
#define AIPS_PACRA_TP6_SHIFT 4
#define AIPS_PACRA_WP6_MASK 0x20u
#define AIPS_PACRA_WP6_SHIFT 5
#define AIPS_PACRA_SP6_MASK 0x40u
#define AIPS_PACRA_SP6_SHIFT 6
#define AIPS_PACRA_TP5_MASK 0x100u
#define AIPS_PACRA_TP5_SHIFT 8
#define AIPS_PACRA_WP5_MASK 0x200u
#define AIPS_PACRA_WP5_SHIFT 9
#define AIPS_PACRA_SP5_MASK 0x400u
#define AIPS_PACRA_SP5_SHIFT 10
#define AIPS_PACRA_TP4_MASK 0x1000u
#define AIPS_PACRA_TP4_SHIFT 12
#define AIPS_PACRA_WP4_MASK 0x2000u
#define AIPS_PACRA_WP4_SHIFT 13
#define AIPS_PACRA_SP4_MASK 0x4000u
#define AIPS_PACRA_SP4_SHIFT 14
#define AIPS_PACRA_TP3_MASK 0x10000u
#define AIPS_PACRA_TP3_SHIFT 16
#define AIPS_PACRA_WP3_MASK 0x20000u
#define AIPS_PACRA_WP3_SHIFT 17
#define AIPS_PACRA_SP3_MASK 0x40000u
#define AIPS_PACRA_SP3_SHIFT 18
#define AIPS_PACRA_TP2_MASK 0x100000u
#define AIPS_PACRA_TP2_SHIFT 20
#define AIPS_PACRA_WP2_MASK 0x200000u
#define AIPS_PACRA_WP2_SHIFT 21
#define AIPS_PACRA_SP2_MASK 0x400000u
#define AIPS_PACRA_SP2_SHIFT 22
#define AIPS_PACRA_TP1_MASK 0x1000000u
#define AIPS_PACRA_TP1_SHIFT 24
#define AIPS_PACRA_WP1_MASK 0x2000000u
#define AIPS_PACRA_WP1_SHIFT 25
#define AIPS_PACRA_SP1_MASK 0x4000000u
#define AIPS_PACRA_SP1_SHIFT 26
#define AIPS_PACRA_TP0_MASK 0x10000000u
#define AIPS_PACRA_TP0_SHIFT 28
#define AIPS_PACRA_WP0_MASK 0x20000000u
#define AIPS_PACRA_WP0_SHIFT 29
#define AIPS_PACRA_SP0_MASK 0x40000000u
#define AIPS_PACRA_SP0_SHIFT 30
/* PACRB Bit Fields */
#define AIPS_PACRB_TP7_MASK 0x1u
#define AIPS_PACRB_TP7_SHIFT 0
#define AIPS_PACRB_WP7_MASK 0x2u
#define AIPS_PACRB_WP7_SHIFT 1
#define AIPS_PACRB_SP7_MASK 0x4u
#define AIPS_PACRB_SP7_SHIFT 2
#define AIPS_PACRB_TP6_MASK 0x10u
#define AIPS_PACRB_TP6_SHIFT 4
#define AIPS_PACRB_WP6_MASK 0x20u
#define AIPS_PACRB_WP6_SHIFT 5
#define AIPS_PACRB_SP6_MASK 0x40u
#define AIPS_PACRB_SP6_SHIFT 6
#define AIPS_PACRB_TP5_MASK 0x100u
#define AIPS_PACRB_TP5_SHIFT 8
#define AIPS_PACRB_WP5_MASK 0x200u
#define AIPS_PACRB_WP5_SHIFT 9
#define AIPS_PACRB_SP5_MASK 0x400u
#define AIPS_PACRB_SP5_SHIFT 10
#define AIPS_PACRB_TP4_MASK 0x1000u
#define AIPS_PACRB_TP4_SHIFT 12
#define AIPS_PACRB_WP4_MASK 0x2000u
#define AIPS_PACRB_WP4_SHIFT 13
#define AIPS_PACRB_SP4_MASK 0x4000u
#define AIPS_PACRB_SP4_SHIFT 14
#define AIPS_PACRB_TP3_MASK 0x10000u
#define AIPS_PACRB_TP3_SHIFT 16
#define AIPS_PACRB_WP3_MASK 0x20000u
#define AIPS_PACRB_WP3_SHIFT 17
#define AIPS_PACRB_SP3_MASK 0x40000u
#define AIPS_PACRB_SP3_SHIFT 18
#define AIPS_PACRB_TP2_MASK 0x100000u
#define AIPS_PACRB_TP2_SHIFT 20
#define AIPS_PACRB_WP2_MASK 0x200000u
#define AIPS_PACRB_WP2_SHIFT 21
#define AIPS_PACRB_SP2_MASK 0x400000u
#define AIPS_PACRB_SP2_SHIFT 22
#define AIPS_PACRB_TP1_MASK 0x1000000u
#define AIPS_PACRB_TP1_SHIFT 24
#define AIPS_PACRB_WP1_MASK 0x2000000u
#define AIPS_PACRB_WP1_SHIFT 25
#define AIPS_PACRB_SP1_MASK 0x4000000u
#define AIPS_PACRB_SP1_SHIFT 26
#define AIPS_PACRB_TP0_MASK 0x10000000u
#define AIPS_PACRB_TP0_SHIFT 28
#define AIPS_PACRB_WP0_MASK 0x20000000u
#define AIPS_PACRB_WP0_SHIFT 29
#define AIPS_PACRB_SP0_MASK 0x40000000u
#define AIPS_PACRB_SP0_SHIFT 30
/* PACRC Bit Fields */
#define AIPS_PACRC_TP7_MASK 0x1u
#define AIPS_PACRC_TP7_SHIFT 0
#define AIPS_PACRC_WP7_MASK 0x2u
#define AIPS_PACRC_WP7_SHIFT 1
#define AIPS_PACRC_SP7_MASK 0x4u
#define AIPS_PACRC_SP7_SHIFT 2
#define AIPS_PACRC_TP6_MASK 0x10u
#define AIPS_PACRC_TP6_SHIFT 4
#define AIPS_PACRC_WP6_MASK 0x20u
#define AIPS_PACRC_WP6_SHIFT 5
#define AIPS_PACRC_SP6_MASK 0x40u
#define AIPS_PACRC_SP6_SHIFT 6
#define AIPS_PACRC_TP5_MASK 0x100u
#define AIPS_PACRC_TP5_SHIFT 8
#define AIPS_PACRC_WP5_MASK 0x200u
#define AIPS_PACRC_WP5_SHIFT 9
#define AIPS_PACRC_SP5_MASK 0x400u
#define AIPS_PACRC_SP5_SHIFT 10
#define AIPS_PACRC_TP4_MASK 0x1000u
#define AIPS_PACRC_TP4_SHIFT 12
#define AIPS_PACRC_WP4_MASK 0x2000u
#define AIPS_PACRC_WP4_SHIFT 13
#define AIPS_PACRC_SP4_MASK 0x4000u
#define AIPS_PACRC_SP4_SHIFT 14
#define AIPS_PACRC_TP3_MASK 0x10000u
#define AIPS_PACRC_TP3_SHIFT 16
#define AIPS_PACRC_WP3_MASK 0x20000u
#define AIPS_PACRC_WP3_SHIFT 17
#define AIPS_PACRC_SP3_MASK 0x40000u
#define AIPS_PACRC_SP3_SHIFT 18
#define AIPS_PACRC_TP2_MASK 0x100000u
#define AIPS_PACRC_TP2_SHIFT 20
#define AIPS_PACRC_WP2_MASK 0x200000u
#define AIPS_PACRC_WP2_SHIFT 21
#define AIPS_PACRC_SP2_MASK 0x400000u
#define AIPS_PACRC_SP2_SHIFT 22
#define AIPS_PACRC_TP1_MASK 0x1000000u
#define AIPS_PACRC_TP1_SHIFT 24
#define AIPS_PACRC_WP1_MASK 0x2000000u
#define AIPS_PACRC_WP1_SHIFT 25
#define AIPS_PACRC_SP1_MASK 0x4000000u
#define AIPS_PACRC_SP1_SHIFT 26
#define AIPS_PACRC_TP0_MASK 0x10000000u
#define AIPS_PACRC_TP0_SHIFT 28
#define AIPS_PACRC_WP0_MASK 0x20000000u
#define AIPS_PACRC_WP0_SHIFT 29
#define AIPS_PACRC_SP0_MASK 0x40000000u
#define AIPS_PACRC_SP0_SHIFT 30
/* PACRD Bit Fields */
#define AIPS_PACRD_TP7_MASK 0x1u
#define AIPS_PACRD_TP7_SHIFT 0
#define AIPS_PACRD_WP7_MASK 0x2u
#define AIPS_PACRD_WP7_SHIFT 1
#define AIPS_PACRD_SP7_MASK 0x4u
#define AIPS_PACRD_SP7_SHIFT 2
#define AIPS_PACRD_TP6_MASK 0x10u
#define AIPS_PACRD_TP6_SHIFT 4
#define AIPS_PACRD_WP6_MASK 0x20u
#define AIPS_PACRD_WP6_SHIFT 5
#define AIPS_PACRD_SP6_MASK 0x40u
#define AIPS_PACRD_SP6_SHIFT 6
#define AIPS_PACRD_TP5_MASK 0x100u
#define AIPS_PACRD_TP5_SHIFT 8
#define AIPS_PACRD_WP5_MASK 0x200u
#define AIPS_PACRD_WP5_SHIFT 9
#define AIPS_PACRD_SP5_MASK 0x400u
#define AIPS_PACRD_SP5_SHIFT 10
#define AIPS_PACRD_TP4_MASK 0x1000u
#define AIPS_PACRD_TP4_SHIFT 12
#define AIPS_PACRD_WP4_MASK 0x2000u
#define AIPS_PACRD_WP4_SHIFT 13
#define AIPS_PACRD_SP4_MASK 0x4000u
#define AIPS_PACRD_SP4_SHIFT 14
#define AIPS_PACRD_TP3_MASK 0x10000u
#define AIPS_PACRD_TP3_SHIFT 16
#define AIPS_PACRD_WP3_MASK 0x20000u
#define AIPS_PACRD_WP3_SHIFT 17
#define AIPS_PACRD_SP3_MASK 0x40000u
#define AIPS_PACRD_SP3_SHIFT 18
#define AIPS_PACRD_TP2_MASK 0x100000u
#define AIPS_PACRD_TP2_SHIFT 20
#define AIPS_PACRD_WP2_MASK 0x200000u
#define AIPS_PACRD_WP2_SHIFT 21
#define AIPS_PACRD_SP2_MASK 0x400000u
#define AIPS_PACRD_SP2_SHIFT 22
#define AIPS_PACRD_TP1_MASK 0x1000000u
#define AIPS_PACRD_TP1_SHIFT 24
#define AIPS_PACRD_WP1_MASK 0x2000000u
#define AIPS_PACRD_WP1_SHIFT 25
#define AIPS_PACRD_SP1_MASK 0x4000000u
#define AIPS_PACRD_SP1_SHIFT 26
#define AIPS_PACRD_TP0_MASK 0x10000000u
#define AIPS_PACRD_TP0_SHIFT 28
#define AIPS_PACRD_WP0_MASK 0x20000000u
#define AIPS_PACRD_WP0_SHIFT 29
#define AIPS_PACRD_SP0_MASK 0x40000000u
#define AIPS_PACRD_SP0_SHIFT 30
/* PACRE Bit Fields */
#define AIPS_PACRE_TP7_MASK 0x1u
#define AIPS_PACRE_TP7_SHIFT 0
#define AIPS_PACRE_WP7_MASK 0x2u
#define AIPS_PACRE_WP7_SHIFT 1
#define AIPS_PACRE_SP7_MASK 0x4u
#define AIPS_PACRE_SP7_SHIFT 2
#define AIPS_PACRE_TP6_MASK 0x10u
#define AIPS_PACRE_TP6_SHIFT 4
#define AIPS_PACRE_WP6_MASK 0x20u
#define AIPS_PACRE_WP6_SHIFT 5
#define AIPS_PACRE_SP6_MASK 0x40u
#define AIPS_PACRE_SP6_SHIFT 6
#define AIPS_PACRE_TP5_MASK 0x100u
#define AIPS_PACRE_TP5_SHIFT 8
#define AIPS_PACRE_WP5_MASK 0x200u
#define AIPS_PACRE_WP5_SHIFT 9
#define AIPS_PACRE_SP5_MASK 0x400u
#define AIPS_PACRE_SP5_SHIFT 10
#define AIPS_PACRE_TP4_MASK 0x1000u
#define AIPS_PACRE_TP4_SHIFT 12
#define AIPS_PACRE_WP4_MASK 0x2000u
#define AIPS_PACRE_WP4_SHIFT 13
#define AIPS_PACRE_SP4_MASK 0x4000u
#define AIPS_PACRE_SP4_SHIFT 14
#define AIPS_PACRE_TP3_MASK 0x10000u
#define AIPS_PACRE_TP3_SHIFT 16
#define AIPS_PACRE_WP3_MASK 0x20000u
#define AIPS_PACRE_WP3_SHIFT 17
#define AIPS_PACRE_SP3_MASK 0x40000u
#define AIPS_PACRE_SP3_SHIFT 18
#define AIPS_PACRE_TP2_MASK 0x100000u
#define AIPS_PACRE_TP2_SHIFT 20
#define AIPS_PACRE_WP2_MASK 0x200000u
#define AIPS_PACRE_WP2_SHIFT 21
#define AIPS_PACRE_SP2_MASK 0x400000u
#define AIPS_PACRE_SP2_SHIFT 22
#define AIPS_PACRE_TP1_MASK 0x1000000u
#define AIPS_PACRE_TP1_SHIFT 24
#define AIPS_PACRE_WP1_MASK 0x2000000u
#define AIPS_PACRE_WP1_SHIFT 25
#define AIPS_PACRE_SP1_MASK 0x4000000u
#define AIPS_PACRE_SP1_SHIFT 26
#define AIPS_PACRE_TP0_MASK 0x10000000u
#define AIPS_PACRE_TP0_SHIFT 28
#define AIPS_PACRE_WP0_MASK 0x20000000u
#define AIPS_PACRE_WP0_SHIFT 29
#define AIPS_PACRE_SP0_MASK 0x40000000u
#define AIPS_PACRE_SP0_SHIFT 30
/* PACRF Bit Fields */
#define AIPS_PACRF_TP7_MASK 0x1u
#define AIPS_PACRF_TP7_SHIFT 0
#define AIPS_PACRF_WP7_MASK 0x2u
#define AIPS_PACRF_WP7_SHIFT 1
#define AIPS_PACRF_SP7_MASK 0x4u
#define AIPS_PACRF_SP7_SHIFT 2
#define AIPS_PACRF_TP6_MASK 0x10u
#define AIPS_PACRF_TP6_SHIFT 4
#define AIPS_PACRF_WP6_MASK 0x20u
#define AIPS_PACRF_WP6_SHIFT 5
#define AIPS_PACRF_SP6_MASK 0x40u
#define AIPS_PACRF_SP6_SHIFT 6
#define AIPS_PACRF_TP5_MASK 0x100u
#define AIPS_PACRF_TP5_SHIFT 8
#define AIPS_PACRF_WP5_MASK 0x200u
#define AIPS_PACRF_WP5_SHIFT 9
#define AIPS_PACRF_SP5_MASK 0x400u
#define AIPS_PACRF_SP5_SHIFT 10
#define AIPS_PACRF_TP4_MASK 0x1000u
#define AIPS_PACRF_TP4_SHIFT 12
#define AIPS_PACRF_WP4_MASK 0x2000u
#define AIPS_PACRF_WP4_SHIFT 13
#define AIPS_PACRF_SP4_MASK 0x4000u
#define AIPS_PACRF_SP4_SHIFT 14
#define AIPS_PACRF_TP3_MASK 0x10000u
#define AIPS_PACRF_TP3_SHIFT 16
#define AIPS_PACRF_WP3_MASK 0x20000u
#define AIPS_PACRF_WP3_SHIFT 17
#define AIPS_PACRF_SP3_MASK 0x40000u
#define AIPS_PACRF_SP3_SHIFT 18
#define AIPS_PACRF_TP2_MASK 0x100000u
#define AIPS_PACRF_TP2_SHIFT 20
#define AIPS_PACRF_WP2_MASK 0x200000u
#define AIPS_PACRF_WP2_SHIFT 21
#define AIPS_PACRF_SP2_MASK 0x400000u
#define AIPS_PACRF_SP2_SHIFT 22
#define AIPS_PACRF_TP1_MASK 0x1000000u
#define AIPS_PACRF_TP1_SHIFT 24
#define AIPS_PACRF_WP1_MASK 0x2000000u
#define AIPS_PACRF_WP1_SHIFT 25
#define AIPS_PACRF_SP1_MASK 0x4000000u
#define AIPS_PACRF_SP1_SHIFT 26
#define AIPS_PACRF_TP0_MASK 0x10000000u
#define AIPS_PACRF_TP0_SHIFT 28
#define AIPS_PACRF_WP0_MASK 0x20000000u
#define AIPS_PACRF_WP0_SHIFT 29
#define AIPS_PACRF_SP0_MASK 0x40000000u
#define AIPS_PACRF_SP0_SHIFT 30
/* PACRG Bit Fields */
#define AIPS_PACRG_TP7_MASK 0x1u
#define AIPS_PACRG_TP7_SHIFT 0
#define AIPS_PACRG_WP7_MASK 0x2u
#define AIPS_PACRG_WP7_SHIFT 1
#define AIPS_PACRG_SP7_MASK 0x4u
#define AIPS_PACRG_SP7_SHIFT 2
#define AIPS_PACRG_TP6_MASK 0x10u
#define AIPS_PACRG_TP6_SHIFT 4
#define AIPS_PACRG_WP6_MASK 0x20u
#define AIPS_PACRG_WP6_SHIFT 5
#define AIPS_PACRG_SP6_MASK 0x40u
#define AIPS_PACRG_SP6_SHIFT 6
#define AIPS_PACRG_TP5_MASK 0x100u
#define AIPS_PACRG_TP5_SHIFT 8
#define AIPS_PACRG_WP5_MASK 0x200u
#define AIPS_PACRG_WP5_SHIFT 9
#define AIPS_PACRG_SP5_MASK 0x400u
#define AIPS_PACRG_SP5_SHIFT 10
#define AIPS_PACRG_TP4_MASK 0x1000u
#define AIPS_PACRG_TP4_SHIFT 12
#define AIPS_PACRG_WP4_MASK 0x2000u
#define AIPS_PACRG_WP4_SHIFT 13
#define AIPS_PACRG_SP4_MASK 0x4000u
#define AIPS_PACRG_SP4_SHIFT 14
#define AIPS_PACRG_TP3_MASK 0x10000u
#define AIPS_PACRG_TP3_SHIFT 16
#define AIPS_PACRG_WP3_MASK 0x20000u
#define AIPS_PACRG_WP3_SHIFT 17
#define AIPS_PACRG_SP3_MASK 0x40000u
#define AIPS_PACRG_SP3_SHIFT 18
#define AIPS_PACRG_TP2_MASK 0x100000u
#define AIPS_PACRG_TP2_SHIFT 20
#define AIPS_PACRG_WP2_MASK 0x200000u
#define AIPS_PACRG_WP2_SHIFT 21
#define AIPS_PACRG_SP2_MASK 0x400000u
#define AIPS_PACRG_SP2_SHIFT 22
#define AIPS_PACRG_TP1_MASK 0x1000000u
#define AIPS_PACRG_TP1_SHIFT 24
#define AIPS_PACRG_WP1_MASK 0x2000000u
#define AIPS_PACRG_WP1_SHIFT 25
#define AIPS_PACRG_SP1_MASK 0x4000000u
#define AIPS_PACRG_SP1_SHIFT 26
#define AIPS_PACRG_TP0_MASK 0x10000000u
#define AIPS_PACRG_TP0_SHIFT 28
#define AIPS_PACRG_WP0_MASK 0x20000000u
#define AIPS_PACRG_WP0_SHIFT 29
#define AIPS_PACRG_SP0_MASK 0x40000000u
#define AIPS_PACRG_SP0_SHIFT 30
/* PACRH Bit Fields */
#define AIPS_PACRH_TP7_MASK 0x1u
#define AIPS_PACRH_TP7_SHIFT 0
#define AIPS_PACRH_WP7_MASK 0x2u
#define AIPS_PACRH_WP7_SHIFT 1
#define AIPS_PACRH_SP7_MASK 0x4u
#define AIPS_PACRH_SP7_SHIFT 2
#define AIPS_PACRH_TP6_MASK 0x10u
#define AIPS_PACRH_TP6_SHIFT 4
#define AIPS_PACRH_WP6_MASK 0x20u
#define AIPS_PACRH_WP6_SHIFT 5
#define AIPS_PACRH_SP6_MASK 0x40u
#define AIPS_PACRH_SP6_SHIFT 6
#define AIPS_PACRH_TP5_MASK 0x100u
#define AIPS_PACRH_TP5_SHIFT 8
#define AIPS_PACRH_WP5_MASK 0x200u
#define AIPS_PACRH_WP5_SHIFT 9
#define AIPS_PACRH_SP5_MASK 0x400u
#define AIPS_PACRH_SP5_SHIFT 10
#define AIPS_PACRH_TP4_MASK 0x1000u
#define AIPS_PACRH_TP4_SHIFT 12
#define AIPS_PACRH_WP4_MASK 0x2000u
#define AIPS_PACRH_WP4_SHIFT 13
#define AIPS_PACRH_SP4_MASK 0x4000u
#define AIPS_PACRH_SP4_SHIFT 14
#define AIPS_PACRH_TP3_MASK 0x10000u
#define AIPS_PACRH_TP3_SHIFT 16
#define AIPS_PACRH_WP3_MASK 0x20000u
#define AIPS_PACRH_WP3_SHIFT 17
#define AIPS_PACRH_SP3_MASK 0x40000u
#define AIPS_PACRH_SP3_SHIFT 18
#define AIPS_PACRH_TP2_MASK 0x100000u
#define AIPS_PACRH_TP2_SHIFT 20
#define AIPS_PACRH_WP2_MASK 0x200000u
#define AIPS_PACRH_WP2_SHIFT 21
#define AIPS_PACRH_SP2_MASK 0x400000u
#define AIPS_PACRH_SP2_SHIFT 22
#define AIPS_PACRH_TP1_MASK 0x1000000u
#define AIPS_PACRH_TP1_SHIFT 24
#define AIPS_PACRH_WP1_MASK 0x2000000u
#define AIPS_PACRH_WP1_SHIFT 25
#define AIPS_PACRH_SP1_MASK 0x4000000u
#define AIPS_PACRH_SP1_SHIFT 26
#define AIPS_PACRH_TP0_MASK 0x10000000u
#define AIPS_PACRH_TP0_SHIFT 28
#define AIPS_PACRH_WP0_MASK 0x20000000u
#define AIPS_PACRH_WP0_SHIFT 29
#define AIPS_PACRH_SP0_MASK 0x40000000u
#define AIPS_PACRH_SP0_SHIFT 30
/* PACRI Bit Fields */
#define AIPS_PACRI_TP7_MASK 0x1u
#define AIPS_PACRI_TP7_SHIFT 0
#define AIPS_PACRI_WP7_MASK 0x2u
#define AIPS_PACRI_WP7_SHIFT 1
#define AIPS_PACRI_SP7_MASK 0x4u
#define AIPS_PACRI_SP7_SHIFT 2
#define AIPS_PACRI_TP6_MASK 0x10u
#define AIPS_PACRI_TP6_SHIFT 4
#define AIPS_PACRI_WP6_MASK 0x20u
#define AIPS_PACRI_WP6_SHIFT 5
#define AIPS_PACRI_SP6_MASK 0x40u
#define AIPS_PACRI_SP6_SHIFT 6
#define AIPS_PACRI_TP5_MASK 0x100u
#define AIPS_PACRI_TP5_SHIFT 8
#define AIPS_PACRI_WP5_MASK 0x200u
#define AIPS_PACRI_WP5_SHIFT 9
#define AIPS_PACRI_SP5_MASK 0x400u
#define AIPS_PACRI_SP5_SHIFT 10
#define AIPS_PACRI_TP4_MASK 0x1000u
#define AIPS_PACRI_TP4_SHIFT 12
#define AIPS_PACRI_WP4_MASK 0x2000u
#define AIPS_PACRI_WP4_SHIFT 13
#define AIPS_PACRI_SP4_MASK 0x4000u
#define AIPS_PACRI_SP4_SHIFT 14
#define AIPS_PACRI_TP3_MASK 0x10000u
#define AIPS_PACRI_TP3_SHIFT 16
#define AIPS_PACRI_WP3_MASK 0x20000u
#define AIPS_PACRI_WP3_SHIFT 17
#define AIPS_PACRI_SP3_MASK 0x40000u
#define AIPS_PACRI_SP3_SHIFT 18
#define AIPS_PACRI_TP2_MASK 0x100000u
#define AIPS_PACRI_TP2_SHIFT 20
#define AIPS_PACRI_WP2_MASK 0x200000u
#define AIPS_PACRI_WP2_SHIFT 21
#define AIPS_PACRI_SP2_MASK 0x400000u
#define AIPS_PACRI_SP2_SHIFT 22
#define AIPS_PACRI_TP1_MASK 0x1000000u
#define AIPS_PACRI_TP1_SHIFT 24
#define AIPS_PACRI_WP1_MASK 0x2000000u
#define AIPS_PACRI_WP1_SHIFT 25
#define AIPS_PACRI_SP1_MASK 0x4000000u
#define AIPS_PACRI_SP1_SHIFT 26
#define AIPS_PACRI_TP0_MASK 0x10000000u
#define AIPS_PACRI_TP0_SHIFT 28
#define AIPS_PACRI_WP0_MASK 0x20000000u
#define AIPS_PACRI_WP0_SHIFT 29
#define AIPS_PACRI_SP0_MASK 0x40000000u
#define AIPS_PACRI_SP0_SHIFT 30
/* PACRJ Bit Fields */
#define AIPS_PACRJ_TP7_MASK 0x1u
#define AIPS_PACRJ_TP7_SHIFT 0
#define AIPS_PACRJ_WP7_MASK 0x2u
#define AIPS_PACRJ_WP7_SHIFT 1
#define AIPS_PACRJ_SP7_MASK 0x4u
#define AIPS_PACRJ_SP7_SHIFT 2
#define AIPS_PACRJ_TP6_MASK 0x10u
#define AIPS_PACRJ_TP6_SHIFT 4
#define AIPS_PACRJ_WP6_MASK 0x20u
#define AIPS_PACRJ_WP6_SHIFT 5
#define AIPS_PACRJ_SP6_MASK 0x40u
#define AIPS_PACRJ_SP6_SHIFT 6
#define AIPS_PACRJ_TP5_MASK 0x100u
#define AIPS_PACRJ_TP5_SHIFT 8
#define AIPS_PACRJ_WP5_MASK 0x200u
#define AIPS_PACRJ_WP5_SHIFT 9
#define AIPS_PACRJ_SP5_MASK 0x400u
#define AIPS_PACRJ_SP5_SHIFT 10
#define AIPS_PACRJ_TP4_MASK 0x1000u
#define AIPS_PACRJ_TP4_SHIFT 12
#define AIPS_PACRJ_WP4_MASK 0x2000u
#define AIPS_PACRJ_WP4_SHIFT 13
#define AIPS_PACRJ_SP4_MASK 0x4000u
#define AIPS_PACRJ_SP4_SHIFT 14
#define AIPS_PACRJ_TP3_MASK 0x10000u
#define AIPS_PACRJ_TP3_SHIFT 16
#define AIPS_PACRJ_WP3_MASK 0x20000u
#define AIPS_PACRJ_WP3_SHIFT 17
#define AIPS_PACRJ_SP3_MASK 0x40000u
#define AIPS_PACRJ_SP3_SHIFT 18
#define AIPS_PACRJ_TP2_MASK 0x100000u
#define AIPS_PACRJ_TP2_SHIFT 20
#define AIPS_PACRJ_WP2_MASK 0x200000u
#define AIPS_PACRJ_WP2_SHIFT 21
#define AIPS_PACRJ_SP2_MASK 0x400000u
#define AIPS_PACRJ_SP2_SHIFT 22
#define AIPS_PACRJ_TP1_MASK 0x1000000u
#define AIPS_PACRJ_TP1_SHIFT 24
#define AIPS_PACRJ_WP1_MASK 0x2000000u
#define AIPS_PACRJ_WP1_SHIFT 25
#define AIPS_PACRJ_SP1_MASK 0x4000000u
#define AIPS_PACRJ_SP1_SHIFT 26
#define AIPS_PACRJ_TP0_MASK 0x10000000u
#define AIPS_PACRJ_TP0_SHIFT 28
#define AIPS_PACRJ_WP0_MASK 0x20000000u
#define AIPS_PACRJ_WP0_SHIFT 29
#define AIPS_PACRJ_SP0_MASK 0x40000000u
#define AIPS_PACRJ_SP0_SHIFT 30
/* PACRK Bit Fields */
#define AIPS_PACRK_TP7_MASK 0x1u
#define AIPS_PACRK_TP7_SHIFT 0
#define AIPS_PACRK_WP7_MASK 0x2u
#define AIPS_PACRK_WP7_SHIFT 1
#define AIPS_PACRK_SP7_MASK 0x4u
#define AIPS_PACRK_SP7_SHIFT 2
#define AIPS_PACRK_TP6_MASK 0x10u
#define AIPS_PACRK_TP6_SHIFT 4
#define AIPS_PACRK_WP6_MASK 0x20u
#define AIPS_PACRK_WP6_SHIFT 5
#define AIPS_PACRK_SP6_MASK 0x40u
#define AIPS_PACRK_SP6_SHIFT 6
#define AIPS_PACRK_TP5_MASK 0x100u
#define AIPS_PACRK_TP5_SHIFT 8
#define AIPS_PACRK_WP5_MASK 0x200u
#define AIPS_PACRK_WP5_SHIFT 9
#define AIPS_PACRK_SP5_MASK 0x400u
#define AIPS_PACRK_SP5_SHIFT 10
#define AIPS_PACRK_TP4_MASK 0x1000u
#define AIPS_PACRK_TP4_SHIFT 12
#define AIPS_PACRK_WP4_MASK 0x2000u
#define AIPS_PACRK_WP4_SHIFT 13
#define AIPS_PACRK_SP4_MASK 0x4000u
#define AIPS_PACRK_SP4_SHIFT 14
#define AIPS_PACRK_TP3_MASK 0x10000u
#define AIPS_PACRK_TP3_SHIFT 16
#define AIPS_PACRK_WP3_MASK 0x20000u
#define AIPS_PACRK_WP3_SHIFT 17
#define AIPS_PACRK_SP3_MASK 0x40000u
#define AIPS_PACRK_SP3_SHIFT 18
#define AIPS_PACRK_TP2_MASK 0x100000u
#define AIPS_PACRK_TP2_SHIFT 20
#define AIPS_PACRK_WP2_MASK 0x200000u
#define AIPS_PACRK_WP2_SHIFT 21
#define AIPS_PACRK_SP2_MASK 0x400000u
#define AIPS_PACRK_SP2_SHIFT 22
#define AIPS_PACRK_TP1_MASK 0x1000000u
#define AIPS_PACRK_TP1_SHIFT 24
#define AIPS_PACRK_WP1_MASK 0x2000000u
#define AIPS_PACRK_WP1_SHIFT 25
#define AIPS_PACRK_SP1_MASK 0x4000000u
#define AIPS_PACRK_SP1_SHIFT 26
#define AIPS_PACRK_TP0_MASK 0x10000000u
#define AIPS_PACRK_TP0_SHIFT 28
#define AIPS_PACRK_WP0_MASK 0x20000000u
#define AIPS_PACRK_WP0_SHIFT 29
#define AIPS_PACRK_SP0_MASK 0x40000000u
#define AIPS_PACRK_SP0_SHIFT 30
/* PACRL Bit Fields */
#define AIPS_PACRL_TP7_MASK 0x1u
#define AIPS_PACRL_TP7_SHIFT 0
#define AIPS_PACRL_WP7_MASK 0x2u
#define AIPS_PACRL_WP7_SHIFT 1
#define AIPS_PACRL_SP7_MASK 0x4u
#define AIPS_PACRL_SP7_SHIFT 2
#define AIPS_PACRL_TP6_MASK 0x10u
#define AIPS_PACRL_TP6_SHIFT 4
#define AIPS_PACRL_WP6_MASK 0x20u
#define AIPS_PACRL_WP6_SHIFT 5
#define AIPS_PACRL_SP6_MASK 0x40u
#define AIPS_PACRL_SP6_SHIFT 6
#define AIPS_PACRL_TP5_MASK 0x100u
#define AIPS_PACRL_TP5_SHIFT 8
#define AIPS_PACRL_WP5_MASK 0x200u
#define AIPS_PACRL_WP5_SHIFT 9
#define AIPS_PACRL_SP5_MASK 0x400u
#define AIPS_PACRL_SP5_SHIFT 10
#define AIPS_PACRL_TP4_MASK 0x1000u
#define AIPS_PACRL_TP4_SHIFT 12
#define AIPS_PACRL_WP4_MASK 0x2000u
#define AIPS_PACRL_WP4_SHIFT 13
#define AIPS_PACRL_SP4_MASK 0x4000u
#define AIPS_PACRL_SP4_SHIFT 14
#define AIPS_PACRL_TP3_MASK 0x10000u
#define AIPS_PACRL_TP3_SHIFT 16
#define AIPS_PACRL_WP3_MASK 0x20000u
#define AIPS_PACRL_WP3_SHIFT 17
#define AIPS_PACRL_SP3_MASK 0x40000u
#define AIPS_PACRL_SP3_SHIFT 18
#define AIPS_PACRL_TP2_MASK 0x100000u
#define AIPS_PACRL_TP2_SHIFT 20
#define AIPS_PACRL_WP2_MASK 0x200000u
#define AIPS_PACRL_WP2_SHIFT 21
#define AIPS_PACRL_SP2_MASK 0x400000u
#define AIPS_PACRL_SP2_SHIFT 22
#define AIPS_PACRL_TP1_MASK 0x1000000u
#define AIPS_PACRL_TP1_SHIFT 24
#define AIPS_PACRL_WP1_MASK 0x2000000u
#define AIPS_PACRL_WP1_SHIFT 25
#define AIPS_PACRL_SP1_MASK 0x4000000u
#define AIPS_PACRL_SP1_SHIFT 26
#define AIPS_PACRL_TP0_MASK 0x10000000u
#define AIPS_PACRL_TP0_SHIFT 28
#define AIPS_PACRL_WP0_MASK 0x20000000u
#define AIPS_PACRL_WP0_SHIFT 29
#define AIPS_PACRL_SP0_MASK 0x40000000u
#define AIPS_PACRL_SP0_SHIFT 30
/* PACRM Bit Fields */
#define AIPS_PACRM_TP7_MASK 0x1u
#define AIPS_PACRM_TP7_SHIFT 0
#define AIPS_PACRM_WP7_MASK 0x2u
#define AIPS_PACRM_WP7_SHIFT 1
#define AIPS_PACRM_SP7_MASK 0x4u
#define AIPS_PACRM_SP7_SHIFT 2
#define AIPS_PACRM_TP6_MASK 0x10u
#define AIPS_PACRM_TP6_SHIFT 4
#define AIPS_PACRM_WP6_MASK 0x20u
#define AIPS_PACRM_WP6_SHIFT 5
#define AIPS_PACRM_SP6_MASK 0x40u
#define AIPS_PACRM_SP6_SHIFT 6
#define AIPS_PACRM_TP5_MASK 0x100u
#define AIPS_PACRM_TP5_SHIFT 8
#define AIPS_PACRM_WP5_MASK 0x200u
#define AIPS_PACRM_WP5_SHIFT 9
#define AIPS_PACRM_SP5_MASK 0x400u
#define AIPS_PACRM_SP5_SHIFT 10
#define AIPS_PACRM_TP4_MASK 0x1000u
#define AIPS_PACRM_TP4_SHIFT 12
#define AIPS_PACRM_WP4_MASK 0x2000u
#define AIPS_PACRM_WP4_SHIFT 13
#define AIPS_PACRM_SP4_MASK 0x4000u
#define AIPS_PACRM_SP4_SHIFT 14
#define AIPS_PACRM_TP3_MASK 0x10000u
#define AIPS_PACRM_TP3_SHIFT 16
#define AIPS_PACRM_WP3_MASK 0x20000u
#define AIPS_PACRM_WP3_SHIFT 17
#define AIPS_PACRM_SP3_MASK 0x40000u
#define AIPS_PACRM_SP3_SHIFT 18
#define AIPS_PACRM_TP2_MASK 0x100000u
#define AIPS_PACRM_TP2_SHIFT 20
#define AIPS_PACRM_WP2_MASK 0x200000u
#define AIPS_PACRM_WP2_SHIFT 21
#define AIPS_PACRM_SP2_MASK 0x400000u
#define AIPS_PACRM_SP2_SHIFT 22
#define AIPS_PACRM_TP1_MASK 0x1000000u
#define AIPS_PACRM_TP1_SHIFT 24
#define AIPS_PACRM_WP1_MASK 0x2000000u
#define AIPS_PACRM_WP1_SHIFT 25
#define AIPS_PACRM_SP1_MASK 0x4000000u
#define AIPS_PACRM_SP1_SHIFT 26
#define AIPS_PACRM_TP0_MASK 0x10000000u
#define AIPS_PACRM_TP0_SHIFT 28
#define AIPS_PACRM_WP0_MASK 0x20000000u
#define AIPS_PACRM_WP0_SHIFT 29
#define AIPS_PACRM_SP0_MASK 0x40000000u
#define AIPS_PACRM_SP0_SHIFT 30
/* PACRN Bit Fields */
#define AIPS_PACRN_TP7_MASK 0x1u
#define AIPS_PACRN_TP7_SHIFT 0
#define AIPS_PACRN_WP7_MASK 0x2u
#define AIPS_PACRN_WP7_SHIFT 1
#define AIPS_PACRN_SP7_MASK 0x4u
#define AIPS_PACRN_SP7_SHIFT 2
#define AIPS_PACRN_TP6_MASK 0x10u
#define AIPS_PACRN_TP6_SHIFT 4
#define AIPS_PACRN_WP6_MASK 0x20u
#define AIPS_PACRN_WP6_SHIFT 5
#define AIPS_PACRN_SP6_MASK 0x40u
#define AIPS_PACRN_SP6_SHIFT 6
#define AIPS_PACRN_TP5_MASK 0x100u
#define AIPS_PACRN_TP5_SHIFT 8
#define AIPS_PACRN_WP5_MASK 0x200u
#define AIPS_PACRN_WP5_SHIFT 9
#define AIPS_PACRN_SP5_MASK 0x400u
#define AIPS_PACRN_SP5_SHIFT 10
#define AIPS_PACRN_TP4_MASK 0x1000u
#define AIPS_PACRN_TP4_SHIFT 12
#define AIPS_PACRN_WP4_MASK 0x2000u
#define AIPS_PACRN_WP4_SHIFT 13
#define AIPS_PACRN_SP4_MASK 0x4000u
#define AIPS_PACRN_SP4_SHIFT 14
#define AIPS_PACRN_TP3_MASK 0x10000u
#define AIPS_PACRN_TP3_SHIFT 16
#define AIPS_PACRN_WP3_MASK 0x20000u
#define AIPS_PACRN_WP3_SHIFT 17
#define AIPS_PACRN_SP3_MASK 0x40000u
#define AIPS_PACRN_SP3_SHIFT 18
#define AIPS_PACRN_TP2_MASK 0x100000u
#define AIPS_PACRN_TP2_SHIFT 20
#define AIPS_PACRN_WP2_MASK 0x200000u
#define AIPS_PACRN_WP2_SHIFT 21
#define AIPS_PACRN_SP2_MASK 0x400000u
#define AIPS_PACRN_SP2_SHIFT 22
#define AIPS_PACRN_TP1_MASK 0x1000000u
#define AIPS_PACRN_TP1_SHIFT 24
#define AIPS_PACRN_WP1_MASK 0x2000000u
#define AIPS_PACRN_WP1_SHIFT 25
#define AIPS_PACRN_SP1_MASK 0x4000000u
#define AIPS_PACRN_SP1_SHIFT 26
#define AIPS_PACRN_TP0_MASK 0x10000000u
#define AIPS_PACRN_TP0_SHIFT 28
#define AIPS_PACRN_WP0_MASK 0x20000000u
#define AIPS_PACRN_WP0_SHIFT 29
#define AIPS_PACRN_SP0_MASK 0x40000000u
#define AIPS_PACRN_SP0_SHIFT 30
/* PACRO Bit Fields */
#define AIPS_PACRO_TP7_MASK 0x1u
#define AIPS_PACRO_TP7_SHIFT 0
#define AIPS_PACRO_WP7_MASK 0x2u
#define AIPS_PACRO_WP7_SHIFT 1
#define AIPS_PACRO_SP7_MASK 0x4u
#define AIPS_PACRO_SP7_SHIFT 2
#define AIPS_PACRO_TP6_MASK 0x10u
#define AIPS_PACRO_TP6_SHIFT 4
#define AIPS_PACRO_WP6_MASK 0x20u
#define AIPS_PACRO_WP6_SHIFT 5
#define AIPS_PACRO_SP6_MASK 0x40u
#define AIPS_PACRO_SP6_SHIFT 6
#define AIPS_PACRO_TP5_MASK 0x100u
#define AIPS_PACRO_TP5_SHIFT 8
#define AIPS_PACRO_WP5_MASK 0x200u
#define AIPS_PACRO_WP5_SHIFT 9
#define AIPS_PACRO_SP5_MASK 0x400u
#define AIPS_PACRO_SP5_SHIFT 10
#define AIPS_PACRO_TP4_MASK 0x1000u
#define AIPS_PACRO_TP4_SHIFT 12
#define AIPS_PACRO_WP4_MASK 0x2000u
#define AIPS_PACRO_WP4_SHIFT 13
#define AIPS_PACRO_SP4_MASK 0x4000u
#define AIPS_PACRO_SP4_SHIFT 14
#define AIPS_PACRO_TP3_MASK 0x10000u
#define AIPS_PACRO_TP3_SHIFT 16
#define AIPS_PACRO_WP3_MASK 0x20000u
#define AIPS_PACRO_WP3_SHIFT 17
#define AIPS_PACRO_SP3_MASK 0x40000u
#define AIPS_PACRO_SP3_SHIFT 18
#define AIPS_PACRO_TP2_MASK 0x100000u
#define AIPS_PACRO_TP2_SHIFT 20
#define AIPS_PACRO_WP2_MASK 0x200000u
#define AIPS_PACRO_WP2_SHIFT 21
#define AIPS_PACRO_SP2_MASK 0x400000u
#define AIPS_PACRO_SP2_SHIFT 22
#define AIPS_PACRO_TP1_MASK 0x1000000u
#define AIPS_PACRO_TP1_SHIFT 24
#define AIPS_PACRO_WP1_MASK 0x2000000u
#define AIPS_PACRO_WP1_SHIFT 25
#define AIPS_PACRO_SP1_MASK 0x4000000u
#define AIPS_PACRO_SP1_SHIFT 26
#define AIPS_PACRO_TP0_MASK 0x10000000u
#define AIPS_PACRO_TP0_SHIFT 28
#define AIPS_PACRO_WP0_MASK 0x20000000u
#define AIPS_PACRO_WP0_SHIFT 29
#define AIPS_PACRO_SP0_MASK 0x40000000u
#define AIPS_PACRO_SP0_SHIFT 30
/* PACRP Bit Fields */
#define AIPS_PACRP_TP7_MASK 0x1u
#define AIPS_PACRP_TP7_SHIFT 0
#define AIPS_PACRP_WP7_MASK 0x2u
#define AIPS_PACRP_WP7_SHIFT 1
#define AIPS_PACRP_SP7_MASK 0x4u
#define AIPS_PACRP_SP7_SHIFT 2
#define AIPS_PACRP_TP6_MASK 0x10u
#define AIPS_PACRP_TP6_SHIFT 4
#define AIPS_PACRP_WP6_MASK 0x20u
#define AIPS_PACRP_WP6_SHIFT 5
#define AIPS_PACRP_SP6_MASK 0x40u
#define AIPS_PACRP_SP6_SHIFT 6
#define AIPS_PACRP_TP5_MASK 0x100u
#define AIPS_PACRP_TP5_SHIFT 8
#define AIPS_PACRP_WP5_MASK 0x200u
#define AIPS_PACRP_WP5_SHIFT 9
#define AIPS_PACRP_SP5_MASK 0x400u
#define AIPS_PACRP_SP5_SHIFT 10
#define AIPS_PACRP_TP4_MASK 0x1000u
#define AIPS_PACRP_TP4_SHIFT 12
#define AIPS_PACRP_WP4_MASK 0x2000u
#define AIPS_PACRP_WP4_SHIFT 13
#define AIPS_PACRP_SP4_MASK 0x4000u
#define AIPS_PACRP_SP4_SHIFT 14
#define AIPS_PACRP_TP3_MASK 0x10000u
#define AIPS_PACRP_TP3_SHIFT 16
#define AIPS_PACRP_WP3_MASK 0x20000u
#define AIPS_PACRP_WP3_SHIFT 17
#define AIPS_PACRP_SP3_MASK 0x40000u
#define AIPS_PACRP_SP3_SHIFT 18
#define AIPS_PACRP_TP2_MASK 0x100000u
#define AIPS_PACRP_TP2_SHIFT 20
#define AIPS_PACRP_WP2_MASK 0x200000u
#define AIPS_PACRP_WP2_SHIFT 21
#define AIPS_PACRP_SP2_MASK 0x400000u
#define AIPS_PACRP_SP2_SHIFT 22
#define AIPS_PACRP_TP1_MASK 0x1000000u
#define AIPS_PACRP_TP1_SHIFT 24
#define AIPS_PACRP_WP1_MASK 0x2000000u
#define AIPS_PACRP_WP1_SHIFT 25
#define AIPS_PACRP_SP1_MASK 0x4000000u
#define AIPS_PACRP_SP1_SHIFT 26
#define AIPS_PACRP_TP0_MASK 0x10000000u
#define AIPS_PACRP_TP0_SHIFT 28
#define AIPS_PACRP_WP0_MASK 0x20000000u
#define AIPS_PACRP_WP0_SHIFT 29
#define AIPS_PACRP_SP0_MASK 0x40000000u
#define AIPS_PACRP_SP0_SHIFT 30
/**
* @}
*/ /* end of group AIPS_Register_Masks */
/* AIPS - Peripheral instance base addresses */
/** Peripheral AIPS0 base pointer */
#define AIPS0_BASE_PTR ((AIPS_MemMapPtr)0x40000000u)
/** Peripheral AIPS1 base pointer */
#define AIPS1_BASE_PTR ((AIPS_MemMapPtr)0x40080000u)
/* ----------------------------------------------------------------------------
-- AIPS - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
* @{
*/
/* AIPS - Register instance definitions */
/* AIPS0 */
#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0_BASE_PTR)
/* AIPS1 */
#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1_BASE_PTR)
/**
* @}
*/ /* end of group AIPS_Register_Accessor_Macros */
/**
* @}
*/ /* end of group AIPS_Peripheral */
/* ----------------------------------------------------------------------------
-- AXBS
---------------------------------------------------------------------------- */
/**
* @addtogroup AXBS_Peripheral AXBS
* @{
*/
/** AXBS - Peripheral register structure */
typedef struct AXBS_MemMap {
struct { /* offset: 0x0, array step: 0x100 */
uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
uint8_t RESERVED_0[12];
uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
uint8_t RESERVED_1[236];
} SLAVE[5];
uint8_t RESERVED_0[768];
uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
uint8_t RESERVED_1[252];
uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
uint8_t RESERVED_2[252];
uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
uint8_t RESERVED_3[508];
uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
uint8_t RESERVED_4[252];
uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
} volatile *AXBS_MemMapPtr;
/* ----------------------------------------------------------------------------
-- AXBS - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
* @{
*/
/* AXBS - Register accessors */
#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
/**
* @}
*/ /* end of group AXBS_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- AXBS Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup AXBS_Register_Masks AXBS Register Masks
* @{
*/
/* PRS Bit Fields */
#define AXBS_PRS_M0_MASK 0x7u
#define AXBS_PRS_M0_SHIFT 0
#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
#define AXBS_PRS_M1_MASK 0x70u
#define AXBS_PRS_M1_SHIFT 4
#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
#define AXBS_PRS_M2_MASK 0x700u
#define AXBS_PRS_M2_SHIFT 8
#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
#define AXBS_PRS_M3_MASK 0x7000u
#define AXBS_PRS_M3_SHIFT 12
#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
#define AXBS_PRS_M4_MASK 0x70000u
#define AXBS_PRS_M4_SHIFT 16
#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
#define AXBS_PRS_M5_MASK 0x700000u
#define AXBS_PRS_M5_SHIFT 20
#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
/* CRS Bit Fields */
#define AXBS_CRS_PARK_MASK 0x7u
#define AXBS_CRS_PARK_SHIFT 0
#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
#define AXBS_CRS_PCTL_MASK 0x30u
#define AXBS_CRS_PCTL_SHIFT 4
#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
#define AXBS_CRS_ARB_MASK 0x300u
#define AXBS_CRS_ARB_SHIFT 8
#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
#define AXBS_CRS_HLP_MASK 0x40000000u
#define AXBS_CRS_HLP_SHIFT 30
#define AXBS_CRS_RO_MASK 0x80000000u
#define AXBS_CRS_RO_SHIFT 31
/* MGPCR0 Bit Fields */
#define AXBS_MGPCR0_AULB_MASK 0x7u
#define AXBS_MGPCR0_AULB_SHIFT 0
#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
/* MGPCR1 Bit Fields */
#define AXBS_MGPCR1_AULB_MASK 0x7u
#define AXBS_MGPCR1_AULB_SHIFT 0
#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
/* MGPCR2 Bit Fields */
#define AXBS_MGPCR2_AULB_MASK 0x7u
#define AXBS_MGPCR2_AULB_SHIFT 0
#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
/* MGPCR4 Bit Fields */
#define AXBS_MGPCR4_AULB_MASK 0x7u
#define AXBS_MGPCR4_AULB_SHIFT 0
#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
/* MGPCR5 Bit Fields */
#define AXBS_MGPCR5_AULB_MASK 0x7u
#define AXBS_MGPCR5_AULB_SHIFT 0
#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
/**
* @}
*/ /* end of group AXBS_Register_Masks */
/* AXBS - Peripheral instance base addresses */
/** Peripheral AXBS base pointer */
#define AXBS_BASE_PTR ((AXBS_MemMapPtr)0x40004000u)
/* ----------------------------------------------------------------------------
-- AXBS - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
* @{
*/
/* AXBS - Register instance definitions */
/* AXBS */
#define AXBS_PRS0 AXBS_PRS_REG(AXBS_BASE_PTR,0)
#define AXBS_CRS0 AXBS_CRS_REG(AXBS_BASE_PTR,0)
#define AXBS_PRS1 AXBS_PRS_REG(AXBS_BASE_PTR,1)
#define AXBS_CRS1 AXBS_CRS_REG(AXBS_BASE_PTR,1)
#define AXBS_PRS2 AXBS_PRS_REG(AXBS_BASE_PTR,2)
#define AXBS_CRS2 AXBS_CRS_REG(AXBS_BASE_PTR,2)
#define AXBS_PRS3 AXBS_PRS_REG(AXBS_BASE_PTR,3)
#define AXBS_CRS3 AXBS_CRS_REG(AXBS_BASE_PTR,3)
#define AXBS_PRS4 AXBS_PRS_REG(AXBS_BASE_PTR,4)
#define AXBS_CRS4 AXBS_CRS_REG(AXBS_BASE_PTR,4)
#define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS_BASE_PTR)
#define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS_BASE_PTR)
#define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS_BASE_PTR)
#define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS_BASE_PTR)
#define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS_BASE_PTR)
/* AXBS - Register array accessors */
#define AXBS_PRS(index) AXBS_PRS_REG(AXBS_BASE_PTR,index)
#define AXBS_CRS(index) AXBS_CRS_REG(AXBS_BASE_PTR,index)
/**
* @}
*/ /* end of group AXBS_Register_Accessor_Macros */
/**
* @}
*/ /* end of group AXBS_Peripheral */
/* ----------------------------------------------------------------------------
-- CAN
---------------------------------------------------------------------------- */
/**
* @addtogroup CAN_Peripheral CAN
* @{
*/
/** CAN - Peripheral register structure */
typedef struct CAN_MemMap {
uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */
uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
uint8_t RESERVED_0[4];
uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
uint32_t RX14MASK; /**< Rx 14 Mask Register, offset: 0x14 */
uint32_t RX15MASK; /**< Rx 15 Mask Register, offset: 0x18 */
uint32_t ECR; /**< Error Counter, offset: 0x1C */
uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */
uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */
uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */
uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */
uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */
uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */
uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */
uint8_t RESERVED_1[8];
uint32_t CRCR; /**< CRC Register, offset: 0x44 */
uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */
uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
uint8_t RESERVED_2[48];
struct { /* offset: 0x80, array step: 0x10 */
uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
} MB[16];
uint8_t RESERVED_3[1792];
uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
} volatile *CAN_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CAN - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
* @{
*/
/* CAN - Register accessors */
#define CAN_MCR_REG(base) ((base)->MCR)
#define CAN_CTRL1_REG(base) ((base)->CTRL1)
#define CAN_TIMER_REG(base) ((base)->TIMER)
#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
#define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
#define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
#define CAN_ECR_REG(base) ((base)->ECR)
#define CAN_ESR1_REG(base) ((base)->ESR1)
#define CAN_IMASK2_REG(base) ((base)->IMASK2)
#define CAN_IMASK1_REG(base) ((base)->IMASK1)
#define CAN_IFLAG2_REG(base) ((base)->IFLAG2)
#define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
#define CAN_CTRL2_REG(base) ((base)->CTRL2)
#define CAN_ESR2_REG(base) ((base)->ESR2)
#define CAN_CRCR_REG(base) ((base)->CRCR)
#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
#define CAN_RXFIR_REG(base) ((base)->RXFIR)
#define CAN_CS_REG(base,index) ((base)->MB[index].CS)
#define CAN_ID_REG(base,index) ((base)->MB[index].ID)
#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
/**
* @}
*/ /* end of group CAN_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CAN Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup CAN_Register_Masks CAN Register Masks
* @{
*/
/* MCR Bit Fields */
#define CAN_MCR_MAXMB_MASK 0x7Fu
#define CAN_MCR_MAXMB_SHIFT 0
#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
#define CAN_MCR_IDAM_MASK 0x300u
#define CAN_MCR_IDAM_SHIFT 8
#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
#define CAN_MCR_AEN_MASK 0x1000u
#define CAN_MCR_AEN_SHIFT 12
#define CAN_MCR_LPRIOEN_MASK 0x2000u
#define CAN_MCR_LPRIOEN_SHIFT 13
#define CAN_MCR_IRMQ_MASK 0x10000u
#define CAN_MCR_IRMQ_SHIFT 16
#define CAN_MCR_SRXDIS_MASK 0x20000u
#define CAN_MCR_SRXDIS_SHIFT 17
#define CAN_MCR_DOZE_MASK 0x40000u
#define CAN_MCR_DOZE_SHIFT 18
#define CAN_MCR_LPMACK_MASK 0x100000u
#define CAN_MCR_LPMACK_SHIFT 20
#define CAN_MCR_WRNEN_MASK 0x200000u
#define CAN_MCR_WRNEN_SHIFT 21
#define CAN_MCR_SLFWAK_MASK 0x400000u
#define CAN_MCR_SLFWAK_SHIFT 22
#define CAN_MCR_SUPV_MASK 0x800000u
#define CAN_MCR_SUPV_SHIFT 23
#define CAN_MCR_FRZACK_MASK 0x1000000u
#define CAN_MCR_FRZACK_SHIFT 24
#define CAN_MCR_SOFTRST_MASK 0x2000000u
#define CAN_MCR_SOFTRST_SHIFT 25
#define CAN_MCR_WAKMSK_MASK 0x4000000u
#define CAN_MCR_WAKMSK_SHIFT 26
#define CAN_MCR_NOTRDY_MASK 0x8000000u
#define CAN_MCR_NOTRDY_SHIFT 27
#define CAN_MCR_HALT_MASK 0x10000000u
#define CAN_MCR_HALT_SHIFT 28
#define CAN_MCR_RFEN_MASK 0x20000000u
#define CAN_MCR_RFEN_SHIFT 29
#define CAN_MCR_FRZ_MASK 0x40000000u
#define CAN_MCR_FRZ_SHIFT 30
#define CAN_MCR_MDIS_MASK 0x80000000u
#define CAN_MCR_MDIS_SHIFT 31
/* CTRL1 Bit Fields */
#define CAN_CTRL1_PROPSEG_MASK 0x7u
#define CAN_CTRL1_PROPSEG_SHIFT 0
#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
#define CAN_CTRL1_LOM_MASK 0x8u
#define CAN_CTRL1_LOM_SHIFT 3
#define CAN_CTRL1_LBUF_MASK 0x10u
#define CAN_CTRL1_LBUF_SHIFT 4
#define CAN_CTRL1_TSYN_MASK 0x20u
#define CAN_CTRL1_TSYN_SHIFT 5
#define CAN_CTRL1_BOFFREC_MASK 0x40u
#define CAN_CTRL1_BOFFREC_SHIFT 6
#define CAN_CTRL1_SMP_MASK 0x80u
#define CAN_CTRL1_SMP_SHIFT 7
#define CAN_CTRL1_RWRNMSK_MASK 0x400u
#define CAN_CTRL1_RWRNMSK_SHIFT 10
#define CAN_CTRL1_TWRNMSK_MASK 0x800u
#define CAN_CTRL1_TWRNMSK_SHIFT 11
#define CAN_CTRL1_LPB_MASK 0x1000u
#define CAN_CTRL1_LPB_SHIFT 12
#define CAN_CTRL1_CLKSRC_MASK 0x2000u
#define CAN_CTRL1_CLKSRC_SHIFT 13
#define CAN_CTRL1_ERRMSK_MASK 0x4000u
#define CAN_CTRL1_ERRMSK_SHIFT 14
#define CAN_CTRL1_BOFFMSK_MASK 0x8000u
#define CAN_CTRL1_BOFFMSK_SHIFT 15
#define CAN_CTRL1_PSEG2_MASK 0x70000u
#define CAN_CTRL1_PSEG2_SHIFT 16
#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
#define CAN_CTRL1_PSEG1_MASK 0x380000u
#define CAN_CTRL1_PSEG1_SHIFT 19
#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
#define CAN_CTRL1_RJW_MASK 0xC00000u
#define CAN_CTRL1_RJW_SHIFT 22
#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
#define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
#define CAN_CTRL1_PRESDIV_SHIFT 24
#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
/* TIMER Bit Fields */
#define CAN_TIMER_TIMER_MASK 0xFFFFu
#define CAN_TIMER_TIMER_SHIFT 0
#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
/* RXMGMASK Bit Fields */
#define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
#define CAN_RXMGMASK_MG_SHIFT 0
#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
/* RX14MASK Bit Fields */
#define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
#define CAN_RX14MASK_RX14M_SHIFT 0
#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
/* RX15MASK Bit Fields */
#define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
#define CAN_RX15MASK_RX15M_SHIFT 0
#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
/* ECR Bit Fields */
#define CAN_ECR_TXERRCNT_MASK 0xFFu
#define CAN_ECR_TXERRCNT_SHIFT 0
#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
#define CAN_ECR_RXERRCNT_MASK 0xFF00u
#define CAN_ECR_RXERRCNT_SHIFT 8
#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
/* ESR1 Bit Fields */
#define CAN_ESR1_WAKINT_MASK 0x1u
#define CAN_ESR1_WAKINT_SHIFT 0
#define CAN_ESR1_ERRINT_MASK 0x2u
#define CAN_ESR1_ERRINT_SHIFT 1
#define CAN_ESR1_BOFFINT_MASK 0x4u
#define CAN_ESR1_BOFFINT_SHIFT 2
#define CAN_ESR1_RX_MASK 0x8u
#define CAN_ESR1_RX_SHIFT 3
#define CAN_ESR1_FLTCONF_MASK 0x30u
#define CAN_ESR1_FLTCONF_SHIFT 4
#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
#define CAN_ESR1_TX_MASK 0x40u
#define CAN_ESR1_TX_SHIFT 6
#define CAN_ESR1_IDLE_MASK 0x80u
#define CAN_ESR1_IDLE_SHIFT 7
#define CAN_ESR1_RXWRN_MASK 0x100u
#define CAN_ESR1_RXWRN_SHIFT 8
#define CAN_ESR1_TXWRN_MASK 0x200u
#define CAN_ESR1_TXWRN_SHIFT 9
#define CAN_ESR1_STFERR_MASK 0x400u
#define CAN_ESR1_STFERR_SHIFT 10
#define CAN_ESR1_FRMERR_MASK 0x800u
#define CAN_ESR1_FRMERR_SHIFT 11
#define CAN_ESR1_CRCERR_MASK 0x1000u
#define CAN_ESR1_CRCERR_SHIFT 12
#define CAN_ESR1_ACKERR_MASK 0x2000u
#define CAN_ESR1_ACKERR_SHIFT 13
#define CAN_ESR1_BIT0ERR_MASK 0x4000u
#define CAN_ESR1_BIT0ERR_SHIFT 14
#define CAN_ESR1_BIT1ERR_MASK 0x8000u
#define CAN_ESR1_BIT1ERR_SHIFT 15
#define CAN_ESR1_RWRNINT_MASK 0x10000u
#define CAN_ESR1_RWRNINT_SHIFT 16
#define CAN_ESR1_TWRNINT_MASK 0x20000u
#define CAN_ESR1_TWRNINT_SHIFT 17
#define CAN_ESR1_SYNCH_MASK 0x40000u
#define CAN_ESR1_SYNCH_SHIFT 18
/* IMASK2 Bit Fields */
#define CAN_IMASK2_BUFHM_MASK 0xFFFFFFFFu
#define CAN_IMASK2_BUFHM_SHIFT 0
#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUFHM_SHIFT))&CAN_IMASK2_BUFHM_MASK)
/* IMASK1 Bit Fields */
#define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
#define CAN_IMASK1_BUFLM_SHIFT 0
#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
/* IFLAG2 Bit Fields */
#define CAN_IFLAG2_BUFHI_MASK 0xFFFFFFFFu
#define CAN_IFLAG2_BUFHI_SHIFT 0
#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUFHI_SHIFT))&CAN_IFLAG2_BUFHI_MASK)
/* IFLAG1 Bit Fields */
#define CAN_IFLAG1_BUF4TO0I_MASK 0x1Fu
#define CAN_IFLAG1_BUF4TO0I_SHIFT 0
#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO0I_SHIFT))&CAN_IFLAG1_BUF4TO0I_MASK)
#define CAN_IFLAG1_BUF5I_MASK 0x20u
#define CAN_IFLAG1_BUF5I_SHIFT 5
#define CAN_IFLAG1_BUF6I_MASK 0x40u
#define CAN_IFLAG1_BUF6I_SHIFT 6
#define CAN_IFLAG1_BUF7I_MASK 0x80u
#define CAN_IFLAG1_BUF7I_SHIFT 7
#define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
#define CAN_IFLAG1_BUF31TO8I_SHIFT 8
#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
/* CTRL2 Bit Fields */
#define CAN_CTRL2_EACEN_MASK 0x10000u
#define CAN_CTRL2_EACEN_SHIFT 16
#define CAN_CTRL2_RRS_MASK 0x20000u
#define CAN_CTRL2_RRS_SHIFT 17
#define CAN_CTRL2_MRP_MASK 0x40000u
#define CAN_CTRL2_MRP_SHIFT 18
#define CAN_CTRL2_TASD_MASK 0xF80000u
#define CAN_CTRL2_TASD_SHIFT 19
#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
#define CAN_CTRL2_RFFN_MASK 0xF000000u
#define CAN_CTRL2_RFFN_SHIFT 24
#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
#define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
#define CAN_CTRL2_WRMFRZ_SHIFT 28
/* ESR2 Bit Fields */
#define CAN_ESR2_IMB_MASK 0x2000u
#define CAN_ESR2_IMB_SHIFT 13
#define CAN_ESR2_VPS_MASK 0x4000u
#define CAN_ESR2_VPS_SHIFT 14
#define CAN_ESR2_LPTM_MASK 0x7F0000u
#define CAN_ESR2_LPTM_SHIFT 16
#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
/* CRCR Bit Fields */
#define CAN_CRCR_TXCRC_MASK 0x7FFFu
#define CAN_CRCR_TXCRC_SHIFT 0
#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
#define CAN_CRCR_MBCRC_MASK 0x7F0000u
#define CAN_CRCR_MBCRC_SHIFT 16
#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
/* RXFGMASK Bit Fields */
#define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
#define CAN_RXFGMASK_FGM_SHIFT 0
#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
/* RXFIR Bit Fields */
#define CAN_RXFIR_IDHIT_MASK 0x1FFu
#define CAN_RXFIR_IDHIT_SHIFT 0
#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
/* CS Bit Fields */
#define CAN_CS_TIME_STAMP_MASK 0xFFFFu
#define CAN_CS_TIME_STAMP_SHIFT 0
#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
#define CAN_CS_DLC_MASK 0xF0000u
#define CAN_CS_DLC_SHIFT 16
#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
#define CAN_CS_RTR_MASK 0x100000u
#define CAN_CS_RTR_SHIFT 20
#define CAN_CS_IDE_MASK 0x200000u
#define CAN_CS_IDE_SHIFT 21
#define CAN_CS_SRR_MASK 0x400000u
#define CAN_CS_SRR_SHIFT 22
#define CAN_CS_CODE_MASK 0xF000000u
#define CAN_CS_CODE_SHIFT 24
#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
/* ID Bit Fields */
#define CAN_ID_EXT_MASK 0x3FFFFu
#define CAN_ID_EXT_SHIFT 0
#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
#define CAN_ID_STD_MASK 0x1FFC0000u
#define CAN_ID_STD_SHIFT 18
#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
#define CAN_ID_PRIO_MASK 0xE0000000u
#define CAN_ID_PRIO_SHIFT 29
#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
/* WORD0 Bit Fields */
#define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
#define CAN_WORD0_DATA_BYTE_3_SHIFT 0
#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
#define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
#define CAN_WORD0_DATA_BYTE_2_SHIFT 8
#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
#define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
#define CAN_WORD0_DATA_BYTE_1_SHIFT 16
#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
#define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
#define CAN_WORD0_DATA_BYTE_0_SHIFT 24
#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
/* WORD1 Bit Fields */
#define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
#define CAN_WORD1_DATA_BYTE_7_SHIFT 0
#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
#define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
#define CAN_WORD1_DATA_BYTE_6_SHIFT 8
#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
#define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
#define CAN_WORD1_DATA_BYTE_5_SHIFT 16
#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
#define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
#define CAN_WORD1_DATA_BYTE_4_SHIFT 24
#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
/* RXIMR Bit Fields */
#define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
#define CAN_RXIMR_MI_SHIFT 0
#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
/**
* @}
*/ /* end of group CAN_Register_Masks */
/* CAN - Peripheral instance base addresses */
/** Peripheral CAN0 base pointer */
#define CAN0_BASE_PTR ((CAN_MemMapPtr)0x40024000u)
/** Peripheral CAN1 base pointer */
#define CAN1_BASE_PTR ((CAN_MemMapPtr)0x400A4000u)
/* ----------------------------------------------------------------------------
-- CAN - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
* @{
*/
/* CAN - Register instance definitions */
/* CAN0 */
#define CAN0_MCR CAN_MCR_REG(CAN0_BASE_PTR)
#define CAN0_CTRL1 CAN_CTRL1_REG(CAN0_BASE_PTR)
#define CAN0_TIMER CAN_TIMER_REG(CAN0_BASE_PTR)
#define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0_BASE_PTR)
#define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0_BASE_PTR)
#define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0_BASE_PTR)
#define CAN0_ECR CAN_ECR_REG(CAN0_BASE_PTR)
#define CAN0_ESR1 CAN_ESR1_REG(CAN0_BASE_PTR)
#define CAN0_IMASK2 CAN_IMASK2_REG(CAN0_BASE_PTR)
#define CAN0_IMASK1 CAN_IMASK1_REG(CAN0_BASE_PTR)
#define CAN0_IFLAG2 CAN_IFLAG2_REG(CAN0_BASE_PTR)
#define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0_BASE_PTR)
#define CAN0_CTRL2 CAN_CTRL2_REG(CAN0_BASE_PTR)
#define CAN0_ESR2 CAN_ESR2_REG(CAN0_BASE_PTR)
#define CAN0_CRCR CAN_CRCR_REG(CAN0_BASE_PTR)
#define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0_BASE_PTR)
#define CAN0_RXFIR CAN_RXFIR_REG(CAN0_BASE_PTR)
#define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0_BASE_PTR,0)
#define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0_BASE_PTR,1)
#define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0_BASE_PTR,2)
#define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0_BASE_PTR,3)
#define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0_BASE_PTR,4)
#define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0_BASE_PTR,5)
#define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0_BASE_PTR,6)
#define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0_BASE_PTR,7)
#define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0_BASE_PTR,8)
#define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0_BASE_PTR,9)
#define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0_BASE_PTR,10)
#define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0_BASE_PTR,11)
#define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0_BASE_PTR,12)
#define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0_BASE_PTR,13)
#define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0_BASE_PTR,14)
#define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0_BASE_PTR,15)
#define CAN0_CS0 CAN_CS_REG(CAN0_BASE_PTR,0)
#define CAN0_CS1 CAN_CS_REG(CAN0_BASE_PTR,1)
#define CAN0_CS2 CAN_CS_REG(CAN0_BASE_PTR,2)
#define CAN0_CS3 CAN_CS_REG(CAN0_BASE_PTR,3)
#define CAN0_CS4 CAN_CS_REG(CAN0_BASE_PTR,4)
#define CAN0_CS5 CAN_CS_REG(CAN0_BASE_PTR,5)
#define CAN0_CS6 CAN_CS_REG(CAN0_BASE_PTR,6)
#define CAN0_CS7 CAN_CS_REG(CAN0_BASE_PTR,7)
#define CAN0_CS8 CAN_CS_REG(CAN0_BASE_PTR,8)
#define CAN0_CS9 CAN_CS_REG(CAN0_BASE_PTR,9)
#define CAN0_CS10 CAN_CS_REG(CAN0_BASE_PTR,10)
#define CAN0_CS11 CAN_CS_REG(CAN0_BASE_PTR,11)
#define CAN0_CS12 CAN_CS_REG(CAN0_BASE_PTR,12)
#define CAN0_CS13 CAN_CS_REG(CAN0_BASE_PTR,13)
#define CAN0_CS14 CAN_CS_REG(CAN0_BASE_PTR,14)
#define CAN0_CS15 CAN_CS_REG(CAN0_BASE_PTR,15)
#define CAN0_ID0 CAN_ID_REG(CAN0_BASE_PTR,0)
#define CAN0_ID1 CAN_ID_REG(CAN0_BASE_PTR,1)
#define CAN0_ID2 CAN_ID_REG(CAN0_BASE_PTR,2)
#define CAN0_ID3 CAN_ID_REG(CAN0_BASE_PTR,3)
#define CAN0_ID4 CAN_ID_REG(CAN0_BASE_PTR,4)
#define CAN0_ID5 CAN_ID_REG(CAN0_BASE_PTR,5)
#define CAN0_ID6 CAN_ID_REG(CAN0_BASE_PTR,6)
#define CAN0_ID7 CAN_ID_REG(CAN0_BASE_PTR,7)
#define CAN0_ID8 CAN_ID_REG(CAN0_BASE_PTR,8)
#define CAN0_ID9 CAN_ID_REG(CAN0_BASE_PTR,9)
#define CAN0_ID10 CAN_ID_REG(CAN0_BASE_PTR,10)
#define CAN0_ID11 CAN_ID_REG(CAN0_BASE_PTR,11)
#define CAN0_ID12 CAN_ID_REG(CAN0_BASE_PTR,12)
#define CAN0_ID13 CAN_ID_REG(CAN0_BASE_PTR,13)
#define CAN0_ID14 CAN_ID_REG(CAN0_BASE_PTR,14)
#define CAN0_ID15 CAN_ID_REG(CAN0_BASE_PTR,15)
#define CAN0_WORD00 CAN_WORD0_REG(CAN0_BASE_PTR,0)
#define CAN0_WORD01 CAN_WORD0_REG(CAN0_BASE_PTR,1)
#define CAN0_WORD02 CAN_WORD0_REG(CAN0_BASE_PTR,2)
#define CAN0_WORD03 CAN_WORD0_REG(CAN0_BASE_PTR,3)
#define CAN0_WORD04 CAN_WORD0_REG(CAN0_BASE_PTR,4)
#define CAN0_WORD05 CAN_WORD0_REG(CAN0_BASE_PTR,5)
#define CAN0_WORD06 CAN_WORD0_REG(CAN0_BASE_PTR,6)
#define CAN0_WORD07 CAN_WORD0_REG(CAN0_BASE_PTR,7)
#define CAN0_WORD08 CAN_WORD0_REG(CAN0_BASE_PTR,8)
#define CAN0_WORD09 CAN_WORD0_REG(CAN0_BASE_PTR,9)
#define CAN0_WORD010 CAN_WORD0_REG(CAN0_BASE_PTR,10)
#define CAN0_WORD011 CAN_WORD0_REG(CAN0_BASE_PTR,11)
#define CAN0_WORD012 CAN_WORD0_REG(CAN0_BASE_PTR,12)
#define CAN0_WORD013 CAN_WORD0_REG(CAN0_BASE_PTR,13)
#define CAN0_WORD014 CAN_WORD0_REG(CAN0_BASE_PTR,14)
#define CAN0_WORD015 CAN_WORD0_REG(CAN0_BASE_PTR,15)
#define CAN0_WORD10 CAN_WORD1_REG(CAN0_BASE_PTR,0)
#define CAN0_WORD11 CAN_WORD1_REG(CAN0_BASE_PTR,1)
#define CAN0_WORD12 CAN_WORD1_REG(CAN0_BASE_PTR,2)
#define CAN0_WORD13 CAN_WORD1_REG(CAN0_BASE_PTR,3)
#define CAN0_WORD14 CAN_WORD1_REG(CAN0_BASE_PTR,4)
#define CAN0_WORD15 CAN_WORD1_REG(CAN0_BASE_PTR,5)
#define CAN0_WORD16 CAN_WORD1_REG(CAN0_BASE_PTR,6)
#define CAN0_WORD17 CAN_WORD1_REG(CAN0_BASE_PTR,7)
#define CAN0_WORD18 CAN_WORD1_REG(CAN0_BASE_PTR,8)
#define CAN0_WORD19 CAN_WORD1_REG(CAN0_BASE_PTR,9)
#define CAN0_WORD110 CAN_WORD1_REG(CAN0_BASE_PTR,10)
#define CAN0_WORD111 CAN_WORD1_REG(CAN0_BASE_PTR,11)
#define CAN0_WORD112 CAN_WORD1_REG(CAN0_BASE_PTR,12)
#define CAN0_WORD113 CAN_WORD1_REG(CAN0_BASE_PTR,13)
#define CAN0_WORD114 CAN_WORD1_REG(CAN0_BASE_PTR,14)
#define CAN0_WORD115 CAN_WORD1_REG(CAN0_BASE_PTR,15)
/* CAN1 */
#define CAN1_MCR CAN_MCR_REG(CAN1_BASE_PTR)
#define CAN1_CTRL1 CAN_CTRL1_REG(CAN1_BASE_PTR)
#define CAN1_TIMER CAN_TIMER_REG(CAN1_BASE_PTR)
#define CAN1_RXMGMASK CAN_RXMGMASK_REG(CAN1_BASE_PTR)
#define CAN1_RX14MASK CAN_RX14MASK_REG(CAN1_BASE_PTR)
#define CAN1_RX15MASK CAN_RX15MASK_REG(CAN1_BASE_PTR)
#define CAN1_ECR CAN_ECR_REG(CAN1_BASE_PTR)
#define CAN1_ESR1 CAN_ESR1_REG(CAN1_BASE_PTR)
#define CAN1_IMASK2 CAN_IMASK2_REG(CAN1_BASE_PTR)
#define CAN1_IMASK1 CAN_IMASK1_REG(CAN1_BASE_PTR)
#define CAN1_IFLAG2 CAN_IFLAG2_REG(CAN1_BASE_PTR)
#define CAN1_IFLAG1 CAN_IFLAG1_REG(CAN1_BASE_PTR)
#define CAN1_CTRL2 CAN_CTRL2_REG(CAN1_BASE_PTR)
#define CAN1_ESR2 CAN_ESR2_REG(CAN1_BASE_PTR)
#define CAN1_CRCR CAN_CRCR_REG(CAN1_BASE_PTR)
#define CAN1_RXFGMASK CAN_RXFGMASK_REG(CAN1_BASE_PTR)
#define CAN1_RXFIR CAN_RXFIR_REG(CAN1_BASE_PTR)
#define CAN1_RXIMR0 CAN_RXIMR_REG(CAN1_BASE_PTR,0)
#define CAN1_RXIMR1 CAN_RXIMR_REG(CAN1_BASE_PTR,1)
#define CAN1_RXIMR2 CAN_RXIMR_REG(CAN1_BASE_PTR,2)
#define CAN1_RXIMR3 CAN_RXIMR_REG(CAN1_BASE_PTR,3)
#define CAN1_RXIMR4 CAN_RXIMR_REG(CAN1_BASE_PTR,4)
#define CAN1_RXIMR5 CAN_RXIMR_REG(CAN1_BASE_PTR,5)
#define CAN1_RXIMR6 CAN_RXIMR_REG(CAN1_BASE_PTR,6)
#define CAN1_RXIMR7 CAN_RXIMR_REG(CAN1_BASE_PTR,7)
#define CAN1_RXIMR8 CAN_RXIMR_REG(CAN1_BASE_PTR,8)
#define CAN1_RXIMR9 CAN_RXIMR_REG(CAN1_BASE_PTR,9)
#define CAN1_RXIMR10 CAN_RXIMR_REG(CAN1_BASE_PTR,10)
#define CAN1_RXIMR11 CAN_RXIMR_REG(CAN1_BASE_PTR,11)
#define CAN1_RXIMR12 CAN_RXIMR_REG(CAN1_BASE_PTR,12)
#define CAN1_RXIMR13 CAN_RXIMR_REG(CAN1_BASE_PTR,13)
#define CAN1_RXIMR14 CAN_RXIMR_REG(CAN1_BASE_PTR,14)
#define CAN1_RXIMR15 CAN_RXIMR_REG(CAN1_BASE_PTR,15)
#define CAN1_CS0 CAN_CS_REG(CAN1_BASE_PTR,0)
#define CAN1_CS1 CAN_CS_REG(CAN1_BASE_PTR,1)
#define CAN1_CS2 CAN_CS_REG(CAN1_BASE_PTR,2)
#define CAN1_CS3 CAN_CS_REG(CAN1_BASE_PTR,3)
#define CAN1_CS4 CAN_CS_REG(CAN1_BASE_PTR,4)
#define CAN1_CS5 CAN_CS_REG(CAN1_BASE_PTR,5)
#define CAN1_CS6 CAN_CS_REG(CAN1_BASE_PTR,6)
#define CAN1_CS7 CAN_CS_REG(CAN1_BASE_PTR,7)
#define CAN1_CS8 CAN_CS_REG(CAN1_BASE_PTR,8)
#define CAN1_CS9 CAN_CS_REG(CAN1_BASE_PTR,9)
#define CAN1_CS10 CAN_CS_REG(CAN1_BASE_PTR,10)
#define CAN1_CS11 CAN_CS_REG(CAN1_BASE_PTR,11)
#define CAN1_CS12 CAN_CS_REG(CAN1_BASE_PTR,12)
#define CAN1_CS13 CAN_CS_REG(CAN1_BASE_PTR,13)
#define CAN1_CS14 CAN_CS_REG(CAN1_BASE_PTR,14)
#define CAN1_CS15 CAN_CS_REG(CAN1_BASE_PTR,15)
#define CAN1_ID0 CAN_ID_REG(CAN1_BASE_PTR,0)
#define CAN1_ID1 CAN_ID_REG(CAN1_BASE_PTR,1)
#define CAN1_ID2 CAN_ID_REG(CAN1_BASE_PTR,2)
#define CAN1_ID3 CAN_ID_REG(CAN1_BASE_PTR,3)
#define CAN1_ID4 CAN_ID_REG(CAN1_BASE_PTR,4)
#define CAN1_ID5 CAN_ID_REG(CAN1_BASE_PTR,5)
#define CAN1_ID6 CAN_ID_REG(CAN1_BASE_PTR,6)
#define CAN1_ID7 CAN_ID_REG(CAN1_BASE_PTR,7)
#define CAN1_ID8 CAN_ID_REG(CAN1_BASE_PTR,8)
#define CAN1_ID9 CAN_ID_REG(CAN1_BASE_PTR,9)
#define CAN1_ID10 CAN_ID_REG(CAN1_BASE_PTR,10)
#define CAN1_ID11 CAN_ID_REG(CAN1_BASE_PTR,11)
#define CAN1_ID12 CAN_ID_REG(CAN1_BASE_PTR,12)
#define CAN1_ID13 CAN_ID_REG(CAN1_BASE_PTR,13)
#define CAN1_ID14 CAN_ID_REG(CAN1_BASE_PTR,14)
#define CAN1_ID15 CAN_ID_REG(CAN1_BASE_PTR,15)
#define CAN1_WORD00 CAN_WORD0_REG(CAN1_BASE_PTR,0)
#define CAN1_WORD01 CAN_WORD0_REG(CAN1_BASE_PTR,1)
#define CAN1_WORD02 CAN_WORD0_REG(CAN1_BASE_PTR,2)
#define CAN1_WORD03 CAN_WORD0_REG(CAN1_BASE_PTR,3)
#define CAN1_WORD04 CAN_WORD0_REG(CAN1_BASE_PTR,4)
#define CAN1_WORD05 CAN_WORD0_REG(CAN1_BASE_PTR,5)
#define CAN1_WORD06 CAN_WORD0_REG(CAN1_BASE_PTR,6)
#define CAN1_WORD07 CAN_WORD0_REG(CAN1_BASE_PTR,7)
#define CAN1_WORD08 CAN_WORD0_REG(CAN1_BASE_PTR,8)
#define CAN1_WORD09 CAN_WORD0_REG(CAN1_BASE_PTR,9)
#define CAN1_WORD010 CAN_WORD0_REG(CAN1_BASE_PTR,10)
#define CAN1_WORD011 CAN_WORD0_REG(CAN1_BASE_PTR,11)
#define CAN1_WORD012 CAN_WORD0_REG(CAN1_BASE_PTR,12)
#define CAN1_WORD013 CAN_WORD0_REG(CAN1_BASE_PTR,13)
#define CAN1_WORD014 CAN_WORD0_REG(CAN1_BASE_PTR,14)
#define CAN1_WORD015 CAN_WORD0_REG(CAN1_BASE_PTR,15)
#define CAN1_WORD10 CAN_WORD1_REG(CAN1_BASE_PTR,0)
#define CAN1_WORD11 CAN_WORD1_REG(CAN1_BASE_PTR,1)
#define CAN1_WORD12 CAN_WORD1_REG(CAN1_BASE_PTR,2)
#define CAN1_WORD13 CAN_WORD1_REG(CAN1_BASE_PTR,3)
#define CAN1_WORD14 CAN_WORD1_REG(CAN1_BASE_PTR,4)
#define CAN1_WORD15 CAN_WORD1_REG(CAN1_BASE_PTR,5)
#define CAN1_WORD16 CAN_WORD1_REG(CAN1_BASE_PTR,6)
#define CAN1_WORD17 CAN_WORD1_REG(CAN1_BASE_PTR,7)
#define CAN1_WORD18 CAN_WORD1_REG(CAN1_BASE_PTR,8)
#define CAN1_WORD19 CAN_WORD1_REG(CAN1_BASE_PTR,9)
#define CAN1_WORD110 CAN_WORD1_REG(CAN1_BASE_PTR,10)
#define CAN1_WORD111 CAN_WORD1_REG(CAN1_BASE_PTR,11)
#define CAN1_WORD112 CAN_WORD1_REG(CAN1_BASE_PTR,12)
#define CAN1_WORD113 CAN_WORD1_REG(CAN1_BASE_PTR,13)
#define CAN1_WORD114 CAN_WORD1_REG(CAN1_BASE_PTR,14)
#define CAN1_WORD115 CAN_WORD1_REG(CAN1_BASE_PTR,15)
/* CAN - Register array accessors */
#define CAN0_CS(index) CAN_CS_REG(CAN0_BASE_PTR,index)
#define CAN1_CS(index) CAN_CS_REG(CAN1_BASE_PTR,index)
#define CAN0_ID(index) CAN_ID_REG(CAN0_BASE_PTR,index)
#define CAN1_ID(index) CAN_ID_REG(CAN1_BASE_PTR,index)
#define CAN0_WORD0(index) CAN_WORD0_REG(CAN0_BASE_PTR,index)
#define CAN1_WORD0(index) CAN_WORD0_REG(CAN1_BASE_PTR,index)
#define CAN0_WORD1(index) CAN_WORD1_REG(CAN0_BASE_PTR,index)
#define CAN1_WORD1(index) CAN_WORD1_REG(CAN1_BASE_PTR,index)
#define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0_BASE_PTR,index)
#define CAN1_RXIMR(index) CAN_RXIMR_REG(CAN1_BASE_PTR,index)
/**
* @}
*/ /* end of group CAN_Register_Accessor_Macros */
/**
* @}
*/ /* end of group CAN_Peripheral */
/* ----------------------------------------------------------------------------
-- CMP
---------------------------------------------------------------------------- */
/**
* @addtogroup CMP_Peripheral CMP
* @{
*/
/** CMP - Peripheral register structure */
typedef struct CMP_MemMap {
uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
} volatile *CMP_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CMP - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
* @{
*/
/* CMP - Register accessors */
#define CMP_CR0_REG(base) ((base)->CR0)
#define CMP_CR1_REG(base) ((base)->CR1)
#define CMP_FPR_REG(base) ((base)->FPR)
#define CMP_SCR_REG(base) ((base)->SCR)
#define CMP_DACCR_REG(base) ((base)->DACCR)
#define CMP_MUXCR_REG(base) ((base)->MUXCR)
/**
* @}
*/ /* end of group CMP_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/* CR0 Bit Fields */
#define CMP_CR0_HYSTCTR_MASK 0x3u
#define CMP_CR0_HYSTCTR_SHIFT 0
#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
#define CMP_CR0_FILTER_CNT_MASK 0x70u
#define CMP_CR0_FILTER_CNT_SHIFT 4
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
/* CR1 Bit Fields */
#define CMP_CR1_EN_MASK 0x1u
#define CMP_CR1_EN_SHIFT 0
#define CMP_CR1_OPE_MASK 0x2u
#define CMP_CR1_OPE_SHIFT 1
#define CMP_CR1_COS_MASK 0x4u
#define CMP_CR1_COS_SHIFT 2
#define CMP_CR1_INV_MASK 0x8u
#define CMP_CR1_INV_SHIFT 3
#define CMP_CR1_PMODE_MASK 0x10u
#define CMP_CR1_PMODE_SHIFT 4
#define CMP_CR1_WE_MASK 0x40u
#define CMP_CR1_WE_SHIFT 6
#define CMP_CR1_SE_MASK 0x80u
#define CMP_CR1_SE_SHIFT 7
/* FPR Bit Fields */
#define CMP_FPR_FILT_PER_MASK 0xFFu
#define CMP_FPR_FILT_PER_SHIFT 0
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
/* SCR Bit Fields */
#define CMP_SCR_COUT_MASK 0x1u
#define CMP_SCR_COUT_SHIFT 0
#define CMP_SCR_CFF_MASK 0x2u
#define CMP_SCR_CFF_SHIFT 1
#define CMP_SCR_CFR_MASK 0x4u
#define CMP_SCR_CFR_SHIFT 2
#define CMP_SCR_IEF_MASK 0x8u
#define CMP_SCR_IEF_SHIFT 3
#define CMP_SCR_IER_MASK 0x10u
#define CMP_SCR_IER_SHIFT 4
#define CMP_SCR_SMELB_MASK 0x20u
#define CMP_SCR_SMELB_SHIFT 5
#define CMP_SCR_DMAEN_MASK 0x40u
#define CMP_SCR_DMAEN_SHIFT 6
/* DACCR Bit Fields */
#define CMP_DACCR_VOSEL_MASK 0x3Fu
#define CMP_DACCR_VOSEL_SHIFT 0
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
#define CMP_DACCR_VRSEL_MASK 0x40u
#define CMP_DACCR_VRSEL_SHIFT 6
#define CMP_DACCR_DACEN_MASK 0x80u
#define CMP_DACCR_DACEN_SHIFT 7
/* MUXCR Bit Fields */
#define CMP_MUXCR_MSEL_MASK 0x7u
#define CMP_MUXCR_MSEL_SHIFT 0
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
#define CMP_MUXCR_PSEL_MASK 0x38u
#define CMP_MUXCR_PSEL_SHIFT 3
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
#define CMP_MUXCR_MEN_MASK 0x40u
#define CMP_MUXCR_MEN_SHIFT 6
#define CMP_MUXCR_PEN_MASK 0x80u
#define CMP_MUXCR_PEN_SHIFT 7
/**
* @}
*/ /* end of group CMP_Register_Masks */
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP0 base pointer */
#define CMP0_BASE_PTR ((CMP_MemMapPtr)0x40073000u)
/** Peripheral CMP1 base pointer */
#define CMP1_BASE_PTR ((CMP_MemMapPtr)0x40073008u)
/** Peripheral CMP2 base pointer */
#define CMP2_BASE_PTR ((CMP_MemMapPtr)0x40073010u)
/* ----------------------------------------------------------------------------
-- CMP - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
* @{
*/
/* CMP - Register instance definitions */
/* CMP0 */
#define CMP0_CR0 CMP_CR0_REG(CMP0_BASE_PTR)
#define CMP0_CR1 CMP_CR1_REG(CMP0_BASE_PTR)
#define CMP0_FPR CMP_FPR_REG(CMP0_BASE_PTR)
#define CMP0_SCR CMP_SCR_REG(CMP0_BASE_PTR)
#define CMP0_DACCR CMP_DACCR_REG(CMP0_BASE_PTR)
#define CMP0_MUXCR CMP_MUXCR_REG(CMP0_BASE_PTR)
/* CMP1 */
#define CMP1_CR0 CMP_CR0_REG(CMP1_BASE_PTR)
#define CMP1_CR1 CMP_CR1_REG(CMP1_BASE_PTR)
#define CMP1_FPR CMP_FPR_REG(CMP1_BASE_PTR)
#define CMP1_SCR CMP_SCR_REG(CMP1_BASE_PTR)
#define CMP1_DACCR CMP_DACCR_REG(CMP1_BASE_PTR)
#define CMP1_MUXCR CMP_MUXCR_REG(CMP1_BASE_PTR)
/* CMP2 */
#define CMP2_CR0 CMP_CR0_REG(CMP2_BASE_PTR)
#define CMP2_CR1 CMP_CR1_REG(CMP2_BASE_PTR)
#define CMP2_FPR CMP_FPR_REG(CMP2_BASE_PTR)
#define CMP2_SCR CMP_SCR_REG(CMP2_BASE_PTR)
#define CMP2_DACCR CMP_DACCR_REG(CMP2_BASE_PTR)
#define CMP2_MUXCR CMP_MUXCR_REG(CMP2_BASE_PTR)
/**
* @}
*/ /* end of group CMP_Register_Accessor_Macros */
/**
* @}
*/ /* end of group CMP_Peripheral */
/* ----------------------------------------------------------------------------
-- CMT
---------------------------------------------------------------------------- */
/**
* @addtogroup CMT_Peripheral CMT
* @{
*/
/** CMT - Peripheral register structure */
typedef struct CMT_MemMap {
uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
} volatile *CMT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CMT - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
* @{
*/
/* CMT - Register accessors */
#define CMT_CGH1_REG(base) ((base)->CGH1)
#define CMT_CGL1_REG(base) ((base)->CGL1)
#define CMT_CGH2_REG(base) ((base)->CGH2)
#define CMT_CGL2_REG(base) ((base)->CGL2)
#define CMT_OC_REG(base) ((base)->OC)
#define CMT_MSC_REG(base) ((base)->MSC)
#define CMT_CMD1_REG(base) ((base)->CMD1)
#define CMT_CMD2_REG(base) ((base)->CMD2)
#define CMT_CMD3_REG(base) ((base)->CMD3)
#define CMT_CMD4_REG(base) ((base)->CMD4)
#define CMT_PPS_REG(base) ((base)->PPS)
#define CMT_DMA_REG(base) ((base)->DMA)
/**
* @}
*/ /* end of group CMT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CMT Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup CMT_Register_Masks CMT Register Masks
* @{
*/
/* CGH1 Bit Fields */
#define CMT_CGH1_PH_MASK 0xFFu
#define CMT_CGH1_PH_SHIFT 0
#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
/* CGL1 Bit Fields */
#define CMT_CGL1_PL_MASK 0xFFu
#define CMT_CGL1_PL_SHIFT 0
#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
/* CGH2 Bit Fields */
#define CMT_CGH2_SH_MASK 0xFFu
#define CMT_CGH2_SH_SHIFT 0
#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
/* CGL2 Bit Fields */
#define CMT_CGL2_SL_MASK 0xFFu
#define CMT_CGL2_SL_SHIFT 0
#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
/* OC Bit Fields */
#define CMT_OC_IROPEN_MASK 0x20u
#define CMT_OC_IROPEN_SHIFT 5
#define CMT_OC_CMTPOL_MASK 0x40u
#define CMT_OC_CMTPOL_SHIFT 6
#define CMT_OC_IROL_MASK 0x80u
#define CMT_OC_IROL_SHIFT 7
/* MSC Bit Fields */
#define CMT_MSC_MCGEN_MASK 0x1u
#define CMT_MSC_MCGEN_SHIFT 0
#define CMT_MSC_EOCIE_MASK 0x2u
#define CMT_MSC_EOCIE_SHIFT 1
#define CMT_MSC_FSK_MASK 0x4u
#define CMT_MSC_FSK_SHIFT 2
#define CMT_MSC_BASE_MASK 0x8u
#define CMT_MSC_BASE_SHIFT 3
#define CMT_MSC_EXSPC_MASK 0x10u
#define CMT_MSC_EXSPC_SHIFT 4
#define CMT_MSC_CMTDIV_MASK 0x60u
#define CMT_MSC_CMTDIV_SHIFT 5
#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
#define CMT_MSC_EOCF_MASK 0x80u
#define CMT_MSC_EOCF_SHIFT 7
/* CMD1 Bit Fields */
#define CMT_CMD1_MB_MASK 0xFFu
#define CMT_CMD1_MB_SHIFT 0
#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
/* CMD2 Bit Fields */
#define CMT_CMD2_MB_MASK 0xFFu
#define CMT_CMD2_MB_SHIFT 0
#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
/* CMD3 Bit Fields */
#define CMT_CMD3_SB_MASK 0xFFu
#define CMT_CMD3_SB_SHIFT 0
#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
/* CMD4 Bit Fields */
#define CMT_CMD4_SB_MASK 0xFFu
#define CMT_CMD4_SB_SHIFT 0
#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
/* PPS Bit Fields */
#define CMT_PPS_PPSDIV_MASK 0xFu
#define CMT_PPS_PPSDIV_SHIFT 0
#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
/* DMA Bit Fields */
#define CMT_DMA_DMA_MASK 0x1u
#define CMT_DMA_DMA_SHIFT 0
/**
* @}
*/ /* end of group CMT_Register_Masks */
/* CMT - Peripheral instance base addresses */
/** Peripheral CMT base pointer */
#define CMT_BASE_PTR ((CMT_MemMapPtr)0x40062000u)
/* ----------------------------------------------------------------------------
-- CMT - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
* @{
*/
/* CMT - Register instance definitions */
/* CMT */
#define CMT_CGH1 CMT_CGH1_REG(CMT_BASE_PTR)
#define CMT_CGL1 CMT_CGL1_REG(CMT_BASE_PTR)
#define CMT_CGH2 CMT_CGH2_REG(CMT_BASE_PTR)
#define CMT_CGL2 CMT_CGL2_REG(CMT_BASE_PTR)
#define CMT_OC CMT_OC_REG(CMT_BASE_PTR)
#define CMT_MSC CMT_MSC_REG(CMT_BASE_PTR)
#define CMT_CMD1 CMT_CMD1_REG(CMT_BASE_PTR)
#define CMT_CMD2 CMT_CMD2_REG(CMT_BASE_PTR)
#define CMT_CMD3 CMT_CMD3_REG(CMT_BASE_PTR)
#define CMT_CMD4 CMT_CMD4_REG(CMT_BASE_PTR)
#define CMT_PPS CMT_PPS_REG(CMT_BASE_PTR)
#define CMT_DMA CMT_DMA_REG(CMT_BASE_PTR)
/**
* @}
*/ /* end of group CMT_Register_Accessor_Macros */
/**
* @}
*/ /* end of group CMT_Peripheral */
/* ----------------------------------------------------------------------------
-- CRC
---------------------------------------------------------------------------- */
/**
* @addtogroup CRC_Peripheral CRC
* @{
*/
/** CRC - Peripheral register structure */
typedef struct CRC_MemMap {
union { /* offset: 0x0 */
uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
struct { /* offset: 0x0 */
uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
} ACCESS16BIT;
struct { /* offset: 0x0 */
uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
} ACCESS8BIT;
};
union { /* offset: 0x4 */
uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
struct { /* offset: 0x4 */
uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
} GPOLY_ACCESS16BIT;
struct { /* offset: 0x4 */
uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
} GPOLY_ACCESS8BIT;
};
union { /* offset: 0x8 */
uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
struct { /* offset: 0x8 */
uint8_t RESERVED_0[3];
uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
} CTRL_ACCESS8BIT;
};
} volatile *CRC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CRC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
* @{
*/
/* CRC - Register accessors */
#define CRC_CRC_REG(base) ((base)->CRC)
#define CRC_CRCL_REG(base) ((base)->ACCESS16BIT.CRCL)
#define CRC_CRCH_REG(base) ((base)->ACCESS16BIT.CRCH)
#define CRC_CRCLL_REG(base) ((base)->ACCESS8BIT.CRCLL)
#define CRC_CRCLU_REG(base) ((base)->ACCESS8BIT.CRCLU)
#define CRC_CRCHL_REG(base) ((base)->ACCESS8BIT.CRCHL)
#define CRC_CRCHU_REG(base) ((base)->ACCESS8BIT.CRCHU)
#define CRC_GPOLY_REG(base) ((base)->GPOLY)
#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
#define CRC_CTRL_REG(base) ((base)->CTRL)
#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
/**
* @}
*/ /* end of group CRC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CRC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup CRC_Register_Masks CRC Register Masks
* @{
*/
/* CRC Bit Fields */
#define CRC_CRC_LL_MASK 0xFFu
#define CRC_CRC_LL_SHIFT 0
#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
#define CRC_CRC_LU_MASK 0xFF00u
#define CRC_CRC_LU_SHIFT 8
#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
#define CRC_CRC_HL_MASK 0xFF0000u
#define CRC_CRC_HL_SHIFT 16
#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
#define CRC_CRC_HU_MASK 0xFF000000u
#define CRC_CRC_HU_SHIFT 24
#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
/* CRCL Bit Fields */
#define CRC_CRCL_CRCL_MASK 0xFFFFu
#define CRC_CRCL_CRCL_SHIFT 0
#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
/* CRCH Bit Fields */
#define CRC_CRCH_CRCH_MASK 0xFFFFu
#define CRC_CRCH_CRCH_SHIFT 0
#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
/* CRCLL Bit Fields */
#define CRC_CRCLL_CRCLL_MASK 0xFFu
#define CRC_CRCLL_CRCLL_SHIFT 0
#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
/* CRCLU Bit Fields */
#define CRC_CRCLU_CRCLU_MASK 0xFFu
#define CRC_CRCLU_CRCLU_SHIFT 0
#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
/* CRCHL Bit Fields */
#define CRC_CRCHL_CRCHL_MASK 0xFFu
#define CRC_CRCHL_CRCHL_SHIFT 0
#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
/* CRCHU Bit Fields */
#define CRC_CRCHU_CRCHU_MASK 0xFFu
#define CRC_CRCHU_CRCHU_SHIFT 0
#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
/* GPOLY Bit Fields */
#define CRC_GPOLY_LOW_MASK 0xFFFFu
#define CRC_GPOLY_LOW_SHIFT 0
#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
#define CRC_GPOLY_HIGH_SHIFT 16
#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
/* GPOLYL Bit Fields */
#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
#define CRC_GPOLYL_GPOLYL_SHIFT 0
#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
/* GPOLYH Bit Fields */
#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
#define CRC_GPOLYH_GPOLYH_SHIFT 0
#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
/* GPOLYLL Bit Fields */
#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
/* GPOLYLU Bit Fields */
#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
/* GPOLYHL Bit Fields */
#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
/* GPOLYHU Bit Fields */
#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
/* CTRL Bit Fields */
#define CRC_CTRL_TCRC_MASK 0x1000000u
#define CRC_CTRL_TCRC_SHIFT 24
#define CRC_CTRL_WAS_MASK 0x2000000u
#define CRC_CTRL_WAS_SHIFT 25
#define CRC_CTRL_FXOR_MASK 0x4000000u
#define CRC_CTRL_FXOR_SHIFT 26
#define CRC_CTRL_TOTR_MASK 0x30000000u
#define CRC_CTRL_TOTR_SHIFT 28
#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
#define CRC_CTRL_TOT_MASK 0xC0000000u
#define CRC_CTRL_TOT_SHIFT 30
#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
/* CTRLHU Bit Fields */
#define CRC_CTRLHU_TCRC_MASK 0x1u
#define CRC_CTRLHU_TCRC_SHIFT 0
#define CRC_CTRLHU_WAS_MASK 0x2u
#define CRC_CTRLHU_WAS_SHIFT 1
#define CRC_CTRLHU_FXOR_MASK 0x4u
#define CRC_CTRLHU_FXOR_SHIFT 2
#define CRC_CTRLHU_TOTR_MASK 0x30u
#define CRC_CTRLHU_TOTR_SHIFT 4
#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
#define CRC_CTRLHU_TOT_MASK 0xC0u
#define CRC_CTRLHU_TOT_SHIFT 6
#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
/**
* @}
*/ /* end of group CRC_Register_Masks */
/* CRC - Peripheral instance base addresses */
/** Peripheral CRC base pointer */
#define CRC_BASE_PTR ((CRC_MemMapPtr)0x40032000u)
/* ----------------------------------------------------------------------------
-- CRC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
* @{
*/
/* CRC - Register instance definitions */
/* CRC */
#define CRC_CRC CRC_CRC_REG(CRC_BASE_PTR)
#define CRC_GPOLY CRC_GPOLY_REG(CRC_BASE_PTR)
#define CRC_CTRL CRC_CTRL_REG(CRC_BASE_PTR)
#define CRC_CRCL CRC_CRCL_REG(CRC_BASE_PTR)
#define CRC_CRCH CRC_CRCH_REG(CRC_BASE_PTR)
#define CRC_CRCLL CRC_CRCLL_REG(CRC_BASE_PTR)
#define CRC_CRCLU CRC_CRCLU_REG(CRC_BASE_PTR)
#define CRC_CRCHL CRC_CRCHL_REG(CRC_BASE_PTR)
#define CRC_CRCHU CRC_CRCHU_REG(CRC_BASE_PTR)
#define CRC_GPOLYL CRC_GPOLYL_REG(CRC_BASE_PTR)
#define CRC_GPOLYH CRC_GPOLYH_REG(CRC_BASE_PTR)
#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC_BASE_PTR)
#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC_BASE_PTR)
#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC_BASE_PTR)
#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC_BASE_PTR)
#define CRC_CTRLHU CRC_CTRLHU_REG(CRC_BASE_PTR)
/**
* @}
*/ /* end of group CRC_Register_Accessor_Macros */
/**
* @}
*/ /* end of group CRC_Peripheral */
/* ----------------------------------------------------------------------------
-- CoreDebug
---------------------------------------------------------------------------- */
/**
* @addtogroup CoreDebug_Peripheral CoreDebug
* @{
*/
/** CoreDebug - Peripheral register structure */
typedef struct CoreDebug_MemMap {
union { /* offset: 0x0 */
uint32_t base_DHCSR_Read; /**< Debug Halting Control and Status Register, offset: 0x0 */
uint32_t base_DHCSR_Write; /**< Debug Halting Control and Status Register, offset: 0x0 */
};
uint32_t base_DCRSR; /**< Debug Core Register Selector Register, offset: 0x4 */
uint32_t base_DCRDR; /**< Debug Core Register Data Register, offset: 0x8 */
uint32_t base_DEMCR; /**< Debug Exception and Monitor Control Register, offset: 0xC */
} volatile *CoreDebug_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CoreDebug - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros
* @{
*/
/* CoreDebug - Register accessors */
#define CoreDebug_base_DHCSR_Read_REG(base) ((base)->base_DHCSR_Read)
#define CoreDebug_base_DHCSR_Write_REG(base) ((base)->base_DHCSR_Write)
#define CoreDebug_base_DCRSR_REG(base) ((base)->base_DCRSR)
#define CoreDebug_base_DCRDR_REG(base) ((base)->base_DCRDR)
#define CoreDebug_base_DEMCR_REG(base) ((base)->base_DEMCR)
/**
* @}
*/ /* end of group CoreDebug_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CoreDebug Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup CoreDebug_Register_Masks CoreDebug Register Masks
* @{
*/
/**
* @}
*/ /* end of group CoreDebug_Register_Masks */
/* CoreDebug - Peripheral instance base addresses */
/** Peripheral CoreDebug base pointer */
#define CoreDebug_BASE_PTR ((CoreDebug_MemMapPtr)0xE000EDF0u)
/* ----------------------------------------------------------------------------
-- CoreDebug - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros
* @{
*/
/* CoreDebug - Register instance definitions */
/* CoreDebug */
#define DHCSR_Read CoreDebug_base_DHCSR_Read_REG(CoreDebug_BASE_PTR)
#define DHCSR_Write CoreDebug_base_DHCSR_Write_REG(CoreDebug_BASE_PTR)
#define DCRSR CoreDebug_base_DCRSR_REG(CoreDebug_BASE_PTR)
#define DCRDR CoreDebug_base_DCRDR_REG(CoreDebug_BASE_PTR)
#define DEMCR CoreDebug_base_DEMCR_REG(CoreDebug_BASE_PTR)
/**
* @}
*/ /* end of group CoreDebug_Register_Accessor_Macros */
/**
* @}
*/ /* end of group CoreDebug_Peripheral */
/* ----------------------------------------------------------------------------
-- DAC
---------------------------------------------------------------------------- */
/**
* @addtogroup DAC_Peripheral DAC
* @{
*/
/** DAC - Peripheral register structure */
typedef struct DAC_MemMap {
struct { /* offset: 0x0, array step: 0x2 */
uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
} DAT[16];
uint8_t SR; /**< DAC Status Register, offset: 0x20 */
uint8_t C0; /**< DAC Control Register, offset: 0x21 */
uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
} volatile *DAC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DAC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
* @{
*/
/* DAC - Register accessors */
#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
#define DAC_SR_REG(base) ((base)->SR)
#define DAC_C0_REG(base) ((base)->C0)
#define DAC_C1_REG(base) ((base)->C1)
#define DAC_C2_REG(base) ((base)->C2)
/**
* @}
*/ /* end of group DAC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DAC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup DAC_Register_Masks DAC Register Masks
* @{
*/
/* DATL Bit Fields */
#define DAC_DATL_DATA_MASK 0xFFu
#define DAC_DATL_DATA_SHIFT 0
#define DAC_DATL_DATA(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA_SHIFT))&DAC_DATL_DATA_MASK)
/* DATH Bit Fields */
#define DAC_DATH_DATA_MASK 0xFu
#define DAC_DATH_DATA_SHIFT 0
#define DAC_DATH_DATA(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA_SHIFT))&DAC_DATH_DATA_MASK)
/* SR Bit Fields */
#define DAC_SR_DACBFRPBF_MASK 0x1u
#define DAC_SR_DACBFRPBF_SHIFT 0
#define DAC_SR_DACBFRPTF_MASK 0x2u
#define DAC_SR_DACBFRPTF_SHIFT 1
#define DAC_SR_DACBFWMF_MASK 0x4u
#define DAC_SR_DACBFWMF_SHIFT 2
/* C0 Bit Fields */
#define DAC_C0_DACBBIEN_MASK 0x1u
#define DAC_C0_DACBBIEN_SHIFT 0
#define DAC_C0_DACBTIEN_MASK 0x2u
#define DAC_C0_DACBTIEN_SHIFT 1
#define DAC_C0_DACBWIEN_MASK 0x4u
#define DAC_C0_DACBWIEN_SHIFT 2
#define DAC_C0_LPEN_MASK 0x8u
#define DAC_C0_LPEN_SHIFT 3
#define DAC_C0_DACSWTRG_MASK 0x10u
#define DAC_C0_DACSWTRG_SHIFT 4
#define DAC_C0_DACTRGSEL_MASK 0x20u
#define DAC_C0_DACTRGSEL_SHIFT 5
#define DAC_C0_DACRFS_MASK 0x40u
#define DAC_C0_DACRFS_SHIFT 6
#define DAC_C0_DACEN_MASK 0x80u
#define DAC_C0_DACEN_SHIFT 7
/* C1 Bit Fields */
#define DAC_C1_DACBFEN_MASK 0x1u
#define DAC_C1_DACBFEN_SHIFT 0
#define DAC_C1_DACBFMD_MASK 0x6u
#define DAC_C1_DACBFMD_SHIFT 1
#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
#define DAC_C1_DACBFWM_MASK 0x18u
#define DAC_C1_DACBFWM_SHIFT 3
#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
#define DAC_C1_DMAEN_MASK 0x80u
#define DAC_C1_DMAEN_SHIFT 7
/* C2 Bit Fields */
#define DAC_C2_DACBFUP_MASK 0xFu
#define DAC_C2_DACBFUP_SHIFT 0
#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
#define DAC_C2_DACBFRP_MASK 0xF0u
#define DAC_C2_DACBFRP_SHIFT 4
#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
/**
* @}
*/ /* end of group DAC_Register_Masks */
/* DAC - Peripheral instance base addresses */
/** Peripheral DAC0 base pointer */
#define DAC0_BASE_PTR ((DAC_MemMapPtr)0x400CC000u)
/** Peripheral DAC1 base pointer */
#define DAC1_BASE_PTR ((DAC_MemMapPtr)0x400CD000u)
/* ----------------------------------------------------------------------------
-- DAC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
* @{
*/
/* DAC - Register instance definitions */
/* DAC0 */
#define DAC0_DAT0L DAC_DATL_REG(DAC0_BASE_PTR,0)
#define DAC0_DAT0H DAC_DATH_REG(DAC0_BASE_PTR,0)
#define DAC0_DAT1L DAC_DATL_REG(DAC0_BASE_PTR,1)
#define DAC0_DAT1H DAC_DATH_REG(DAC0_BASE_PTR,1)
#define DAC0_DAT2L DAC_DATL_REG(DAC0_BASE_PTR,2)
#define DAC0_DAT2H DAC_DATH_REG(DAC0_BASE_PTR,2)
#define DAC0_DAT3L DAC_DATL_REG(DAC0_BASE_PTR,3)
#define DAC0_DAT3H DAC_DATH_REG(DAC0_BASE_PTR,3)
#define DAC0_DAT4L DAC_DATL_REG(DAC0_BASE_PTR,4)
#define DAC0_DAT4H DAC_DATH_REG(DAC0_BASE_PTR,4)
#define DAC0_DAT5L DAC_DATL_REG(DAC0_BASE_PTR,5)
#define DAC0_DAT5H DAC_DATH_REG(DAC0_BASE_PTR,5)
#define DAC0_DAT6L DAC_DATL_REG(DAC0_BASE_PTR,6)
#define DAC0_DAT6H DAC_DATH_REG(DAC0_BASE_PTR,6)
#define DAC0_DAT7L DAC_DATL_REG(DAC0_BASE_PTR,7)
#define DAC0_DAT7H DAC_DATH_REG(DAC0_BASE_PTR,7)
#define DAC0_DAT8L DAC_DATL_REG(DAC0_BASE_PTR,8)
#define DAC0_DAT8H DAC_DATH_REG(DAC0_BASE_PTR,8)
#define DAC0_DAT9L DAC_DATL_REG(DAC0_BASE_PTR,9)
#define DAC0_DAT9H DAC_DATH_REG(DAC0_BASE_PTR,9)
#define DAC0_DAT10L DAC_DATL_REG(DAC0_BASE_PTR,10)
#define DAC0_DAT10H DAC_DATH_REG(DAC0_BASE_PTR,10)
#define DAC0_DAT11L DAC_DATL_REG(DAC0_BASE_PTR,11)
#define DAC0_DAT11H DAC_DATH_REG(DAC0_BASE_PTR,11)
#define DAC0_DAT12L DAC_DATL_REG(DAC0_BASE_PTR,12)
#define DAC0_DAT12H DAC_DATH_REG(DAC0_BASE_PTR,12)
#define DAC0_DAT13L DAC_DATL_REG(DAC0_BASE_PTR,13)
#define DAC0_DAT13H DAC_DATH_REG(DAC0_BASE_PTR,13)
#define DAC0_DAT14L DAC_DATL_REG(DAC0_BASE_PTR,14)
#define DAC0_DAT14H DAC_DATH_REG(DAC0_BASE_PTR,14)
#define DAC0_DAT15L DAC_DATL_REG(DAC0_BASE_PTR,15)
#define DAC0_DAT15H DAC_DATH_REG(DAC0_BASE_PTR,15)
#define DAC0_SR DAC_SR_REG(DAC0_BASE_PTR)
#define DAC0_C0 DAC_C0_REG(DAC0_BASE_PTR)
#define DAC0_C1 DAC_C1_REG(DAC0_BASE_PTR)
#define DAC0_C2 DAC_C2_REG(DAC0_BASE_PTR)
/* DAC1 */
#define DAC1_DAT0L DAC_DATL_REG(DAC1_BASE_PTR,0)
#define DAC1_DAT0H DAC_DATH_REG(DAC1_BASE_PTR,0)
#define DAC1_DAT1L DAC_DATL_REG(DAC1_BASE_PTR,1)
#define DAC1_DAT1H DAC_DATH_REG(DAC1_BASE_PTR,1)
#define DAC1_DAT2L DAC_DATL_REG(DAC1_BASE_PTR,2)
#define DAC1_DAT2H DAC_DATH_REG(DAC1_BASE_PTR,2)
#define DAC1_DAT3L DAC_DATL_REG(DAC1_BASE_PTR,3)
#define DAC1_DAT3H DAC_DATH_REG(DAC1_BASE_PTR,3)
#define DAC1_DAT4L DAC_DATL_REG(DAC1_BASE_PTR,4)
#define DAC1_DAT4H DAC_DATH_REG(DAC1_BASE_PTR,4)
#define DAC1_DAT5L DAC_DATL_REG(DAC1_BASE_PTR,5)
#define DAC1_DAT5H DAC_DATH_REG(DAC1_BASE_PTR,5)
#define DAC1_DAT6L DAC_DATL_REG(DAC1_BASE_PTR,6)
#define DAC1_DAT6H DAC_DATH_REG(DAC1_BASE_PTR,6)
#define DAC1_DAT7L DAC_DATL_REG(DAC1_BASE_PTR,7)
#define DAC1_DAT7H DAC_DATH_REG(DAC1_BASE_PTR,7)
#define DAC1_DAT8L DAC_DATL_REG(DAC1_BASE_PTR,8)
#define DAC1_DAT8H DAC_DATH_REG(DAC1_BASE_PTR,8)
#define DAC1_DAT9L DAC_DATL_REG(DAC1_BASE_PTR,9)
#define DAC1_DAT9H DAC_DATH_REG(DAC1_BASE_PTR,9)
#define DAC1_DAT10L DAC_DATL_REG(DAC1_BASE_PTR,10)
#define DAC1_DAT10H DAC_DATH_REG(DAC1_BASE_PTR,10)
#define DAC1_DAT11L DAC_DATL_REG(DAC1_BASE_PTR,11)
#define DAC1_DAT11H DAC_DATH_REG(DAC1_BASE_PTR,11)
#define DAC1_DAT12L DAC_DATL_REG(DAC1_BASE_PTR,12)
#define DAC1_DAT12H DAC_DATH_REG(DAC1_BASE_PTR,12)
#define DAC1_DAT13L DAC_DATL_REG(DAC1_BASE_PTR,13)
#define DAC1_DAT13H DAC_DATH_REG(DAC1_BASE_PTR,13)
#define DAC1_DAT14L DAC_DATL_REG(DAC1_BASE_PTR,14)
#define DAC1_DAT14H DAC_DATH_REG(DAC1_BASE_PTR,14)
#define DAC1_DAT15L DAC_DATL_REG(DAC1_BASE_PTR,15)
#define DAC1_DAT15H DAC_DATH_REG(DAC1_BASE_PTR,15)
#define DAC1_SR DAC_SR_REG(DAC1_BASE_PTR)
#define DAC1_C0 DAC_C0_REG(DAC1_BASE_PTR)
#define DAC1_C1 DAC_C1_REG(DAC1_BASE_PTR)
#define DAC1_C2 DAC_C2_REG(DAC1_BASE_PTR)
/* DAC - Register array accessors */
#define DAC0_DATL(index) DAC_DATL_REG(DAC0_BASE_PTR,index)
#define DAC1_DATL(index) DAC_DATL_REG(DAC1_BASE_PTR,index)
#define DAC0_DATH(index) DAC_DATH_REG(DAC0_BASE_PTR,index)
#define DAC1_DATH(index) DAC_DATH_REG(DAC1_BASE_PTR,index)
/**
* @}
*/ /* end of group DAC_Register_Accessor_Macros */
/**
* @}
*/ /* end of group DAC_Peripheral */
/* ----------------------------------------------------------------------------
-- DMA
---------------------------------------------------------------------------- */
/**
* @addtogroup DMA_Peripheral DMA
* @{
*/
/** DMA - Peripheral register structure */
typedef struct DMA_MemMap {
uint32_t CR; /**< Control Register, offset: 0x0 */
uint32_t ES; /**< Error Status Register, offset: 0x4 */
uint8_t RESERVED_0[4];
uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
uint8_t RESERVED_1[4];
uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
uint8_t RESERVED_2[4];
uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
uint8_t RESERVED_3[4];
uint32_t ERR; /**< Error Register, offset: 0x2C */
uint8_t RESERVED_4[4];
uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
uint8_t RESERVED_5[200];
uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
uint8_t RESERVED_6[3824];
struct { /* offset: 0x1000, array step: 0x20 */
uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
union { /* offset: 0x1008, array step: 0x20 */
uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
};
uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
union { /* offset: 0x1016, array step: 0x20 */
uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
};
uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
union { /* offset: 0x101E, array step: 0x20 */
uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
};
} TCD[16];
} volatile *DMA_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DMA - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
* @{
*/
/* DMA - Register accessors */
#define DMA_CR_REG(base) ((base)->CR)
#define DMA_ES_REG(base) ((base)->ES)
#define DMA_ERQ_REG(base) ((base)->ERQ)
#define DMA_EEI_REG(base) ((base)->EEI)
#define DMA_CEEI_REG(base) ((base)->CEEI)
#define DMA_SEEI_REG(base) ((base)->SEEI)
#define DMA_CERQ_REG(base) ((base)->CERQ)
#define DMA_SERQ_REG(base) ((base)->SERQ)
#define DMA_CDNE_REG(base) ((base)->CDNE)
#define DMA_SSRT_REG(base) ((base)->SSRT)
#define DMA_CERR_REG(base) ((base)->CERR)
#define DMA_CINT_REG(base) ((base)->CINT)
#define DMA_INT_REG(base) ((base)->INT)
#define DMA_ERR_REG(base) ((base)->ERR)
#define DMA_HRS_REG(base) ((base)->HRS)
#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
/**
* @}
*/ /* end of group DMA_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DMA Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
/* CR Bit Fields */
#define DMA_CR_EDBG_MASK 0x2u
#define DMA_CR_EDBG_SHIFT 1
#define DMA_CR_ERCA_MASK 0x4u
#define DMA_CR_ERCA_SHIFT 2
#define DMA_CR_HOE_MASK 0x10u
#define DMA_CR_HOE_SHIFT 4
#define DMA_CR_HALT_MASK 0x20u
#define DMA_CR_HALT_SHIFT 5
#define DMA_CR_CLM_MASK 0x40u
#define DMA_CR_CLM_SHIFT 6
#define DMA_CR_EMLM_MASK 0x80u
#define DMA_CR_EMLM_SHIFT 7
#define DMA_CR_ECX_MASK 0x10000u
#define DMA_CR_ECX_SHIFT 16
#define DMA_CR_CX_MASK 0x20000u
#define DMA_CR_CX_SHIFT 17
/* ES Bit Fields */
#define DMA_ES_DBE_MASK 0x1u
#define DMA_ES_DBE_SHIFT 0
#define DMA_ES_SBE_MASK 0x2u
#define DMA_ES_SBE_SHIFT 1
#define DMA_ES_SGE_MASK 0x4u
#define DMA_ES_SGE_SHIFT 2
#define DMA_ES_NCE_MASK 0x8u
#define DMA_ES_NCE_SHIFT 3
#define DMA_ES_DOE_MASK 0x10u
#define DMA_ES_DOE_SHIFT 4
#define DMA_ES_DAE_MASK 0x20u
#define DMA_ES_DAE_SHIFT 5
#define DMA_ES_SOE_MASK 0x40u
#define DMA_ES_SOE_SHIFT 6
#define DMA_ES_SAE_MASK 0x80u
#define DMA_ES_SAE_SHIFT 7
#define DMA_ES_ERRCHN_MASK 0xF00u
#define DMA_ES_ERRCHN_SHIFT 8
#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
#define DMA_ES_CPE_MASK 0x4000u
#define DMA_ES_CPE_SHIFT 14
#define DMA_ES_ECX_MASK 0x10000u
#define DMA_ES_ECX_SHIFT 16
#define DMA_ES_VLD_MASK 0x80000000u
#define DMA_ES_VLD_SHIFT 31
/* ERQ Bit Fields */
#define DMA_ERQ_ERQ0_MASK 0x1u
#define DMA_ERQ_ERQ0_SHIFT 0
#define DMA_ERQ_ERQ1_MASK 0x2u
#define DMA_ERQ_ERQ1_SHIFT 1
#define DMA_ERQ_ERQ2_MASK 0x4u
#define DMA_ERQ_ERQ2_SHIFT 2
#define DMA_ERQ_ERQ3_MASK 0x8u
#define DMA_ERQ_ERQ3_SHIFT 3
#define DMA_ERQ_ERQ4_MASK 0x10u
#define DMA_ERQ_ERQ4_SHIFT 4
#define DMA_ERQ_ERQ5_MASK 0x20u
#define DMA_ERQ_ERQ5_SHIFT 5
#define DMA_ERQ_ERQ6_MASK 0x40u
#define DMA_ERQ_ERQ6_SHIFT 6
#define DMA_ERQ_ERQ7_MASK 0x80u
#define DMA_ERQ_ERQ7_SHIFT 7
#define DMA_ERQ_ERQ8_MASK 0x100u
#define DMA_ERQ_ERQ8_SHIFT 8
#define DMA_ERQ_ERQ9_MASK 0x200u
#define DMA_ERQ_ERQ9_SHIFT 9
#define DMA_ERQ_ERQ10_MASK 0x400u
#define DMA_ERQ_ERQ10_SHIFT 10
#define DMA_ERQ_ERQ11_MASK 0x800u
#define DMA_ERQ_ERQ11_SHIFT 11
#define DMA_ERQ_ERQ12_MASK 0x1000u
#define DMA_ERQ_ERQ12_SHIFT 12
#define DMA_ERQ_ERQ13_MASK 0x2000u
#define DMA_ERQ_ERQ13_SHIFT 13
#define DMA_ERQ_ERQ14_MASK 0x4000u
#define DMA_ERQ_ERQ14_SHIFT 14
#define DMA_ERQ_ERQ15_MASK 0x8000u
#define DMA_ERQ_ERQ15_SHIFT 15
/* EEI Bit Fields */
#define DMA_EEI_EEI0_MASK 0x1u
#define DMA_EEI_EEI0_SHIFT 0
#define DMA_EEI_EEI1_MASK 0x2u
#define DMA_EEI_EEI1_SHIFT 1
#define DMA_EEI_EEI2_MASK 0x4u
#define DMA_EEI_EEI2_SHIFT 2
#define DMA_EEI_EEI3_MASK 0x8u
#define DMA_EEI_EEI3_SHIFT 3
#define DMA_EEI_EEI4_MASK 0x10u
#define DMA_EEI_EEI4_SHIFT 4
#define DMA_EEI_EEI5_MASK 0x20u
#define DMA_EEI_EEI5_SHIFT 5
#define DMA_EEI_EEI6_MASK 0x40u
#define DMA_EEI_EEI6_SHIFT 6
#define DMA_EEI_EEI7_MASK 0x80u
#define DMA_EEI_EEI7_SHIFT 7
#define DMA_EEI_EEI8_MASK 0x100u
#define DMA_EEI_EEI8_SHIFT 8
#define DMA_EEI_EEI9_MASK 0x200u
#define DMA_EEI_EEI9_SHIFT 9
#define DMA_EEI_EEI10_MASK 0x400u
#define DMA_EEI_EEI10_SHIFT 10
#define DMA_EEI_EEI11_MASK 0x800u
#define DMA_EEI_EEI11_SHIFT 11
#define DMA_EEI_EEI12_MASK 0x1000u
#define DMA_EEI_EEI12_SHIFT 12
#define DMA_EEI_EEI13_MASK 0x2000u
#define DMA_EEI_EEI13_SHIFT 13
#define DMA_EEI_EEI14_MASK 0x4000u
#define DMA_EEI_EEI14_SHIFT 14
#define DMA_EEI_EEI15_MASK 0x8000u
#define DMA_EEI_EEI15_SHIFT 15
/* CEEI Bit Fields */
#define DMA_CEEI_CEEI_MASK 0xFu
#define DMA_CEEI_CEEI_SHIFT 0
#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
#define DMA_CEEI_CAEE_MASK 0x40u
#define DMA_CEEI_CAEE_SHIFT 6
#define DMA_CEEI_NOP_MASK 0x80u
#define DMA_CEEI_NOP_SHIFT 7
/* SEEI Bit Fields */
#define DMA_SEEI_SEEI_MASK 0xFu
#define DMA_SEEI_SEEI_SHIFT 0
#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
#define DMA_SEEI_SAEE_MASK 0x40u
#define DMA_SEEI_SAEE_SHIFT 6
#define DMA_SEEI_NOP_MASK 0x80u
#define DMA_SEEI_NOP_SHIFT 7
/* CERQ Bit Fields */
#define DMA_CERQ_CERQ_MASK 0xFu
#define DMA_CERQ_CERQ_SHIFT 0
#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
#define DMA_CERQ_CAER_MASK 0x40u
#define DMA_CERQ_CAER_SHIFT 6
#define DMA_CERQ_NOP_MASK 0x80u
#define DMA_CERQ_NOP_SHIFT 7
/* SERQ Bit Fields */
#define DMA_SERQ_SERQ_MASK 0xFu
#define DMA_SERQ_SERQ_SHIFT 0
#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
#define DMA_SERQ_SAER_MASK 0x40u
#define DMA_SERQ_SAER_SHIFT 6
#define DMA_SERQ_NOP_MASK 0x80u
#define DMA_SERQ_NOP_SHIFT 7
/* CDNE Bit Fields */
#define DMA_CDNE_CDNE_MASK 0xFu
#define DMA_CDNE_CDNE_SHIFT 0
#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
#define DMA_CDNE_CADN_MASK 0x40u
#define DMA_CDNE_CADN_SHIFT 6
#define DMA_CDNE_NOP_MASK 0x80u
#define DMA_CDNE_NOP_SHIFT 7
/* SSRT Bit Fields */
#define DMA_SSRT_SSRT_MASK 0xFu
#define DMA_SSRT_SSRT_SHIFT 0
#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
#define DMA_SSRT_SAST_MASK 0x40u
#define DMA_SSRT_SAST_SHIFT 6
#define DMA_SSRT_NOP_MASK 0x80u
#define DMA_SSRT_NOP_SHIFT 7
/* CERR Bit Fields */
#define DMA_CERR_CERR_MASK 0xFu
#define DMA_CERR_CERR_SHIFT 0
#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
#define DMA_CERR_CAEI_MASK 0x40u
#define DMA_CERR_CAEI_SHIFT 6
#define DMA_CERR_NOP_MASK 0x80u
#define DMA_CERR_NOP_SHIFT 7
/* CINT Bit Fields */
#define DMA_CINT_CINT_MASK 0xFu
#define DMA_CINT_CINT_SHIFT 0
#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
#define DMA_CINT_CAIR_MASK 0x40u
#define DMA_CINT_CAIR_SHIFT 6
#define DMA_CINT_NOP_MASK 0x80u
#define DMA_CINT_NOP_SHIFT 7
/* INT Bit Fields */
#define DMA_INT_INT0_MASK 0x1u
#define DMA_INT_INT0_SHIFT 0
#define DMA_INT_INT1_MASK 0x2u
#define DMA_INT_INT1_SHIFT 1
#define DMA_INT_INT2_MASK 0x4u
#define DMA_INT_INT2_SHIFT 2
#define DMA_INT_INT3_MASK 0x8u
#define DMA_INT_INT3_SHIFT 3
#define DMA_INT_INT4_MASK 0x10u
#define DMA_INT_INT4_SHIFT 4
#define DMA_INT_INT5_MASK 0x20u
#define DMA_INT_INT5_SHIFT 5
#define DMA_INT_INT6_MASK 0x40u
#define DMA_INT_INT6_SHIFT 6
#define DMA_INT_INT7_MASK 0x80u
#define DMA_INT_INT7_SHIFT 7
#define DMA_INT_INT8_MASK 0x100u
#define DMA_INT_INT8_SHIFT 8
#define DMA_INT_INT9_MASK 0x200u
#define DMA_INT_INT9_SHIFT 9
#define DMA_INT_INT10_MASK 0x400u
#define DMA_INT_INT10_SHIFT 10
#define DMA_INT_INT11_MASK 0x800u
#define DMA_INT_INT11_SHIFT 11
#define DMA_INT_INT12_MASK 0x1000u
#define DMA_INT_INT12_SHIFT 12
#define DMA_INT_INT13_MASK 0x2000u
#define DMA_INT_INT13_SHIFT 13
#define DMA_INT_INT14_MASK 0x4000u
#define DMA_INT_INT14_SHIFT 14
#define DMA_INT_INT15_MASK 0x8000u
#define DMA_INT_INT15_SHIFT 15
/* ERR Bit Fields */
#define DMA_ERR_ERR0_MASK 0x1u
#define DMA_ERR_ERR0_SHIFT 0
#define DMA_ERR_ERR1_MASK 0x2u
#define DMA_ERR_ERR1_SHIFT 1
#define DMA_ERR_ERR2_MASK 0x4u
#define DMA_ERR_ERR2_SHIFT 2
#define DMA_ERR_ERR3_MASK 0x8u
#define DMA_ERR_ERR3_SHIFT 3
#define DMA_ERR_ERR4_MASK 0x10u
#define DMA_ERR_ERR4_SHIFT 4
#define DMA_ERR_ERR5_MASK 0x20u
#define DMA_ERR_ERR5_SHIFT 5
#define DMA_ERR_ERR6_MASK 0x40u
#define DMA_ERR_ERR6_SHIFT 6
#define DMA_ERR_ERR7_MASK 0x80u
#define DMA_ERR_ERR7_SHIFT 7
#define DMA_ERR_ERR8_MASK 0x100u
#define DMA_ERR_ERR8_SHIFT 8
#define DMA_ERR_ERR9_MASK 0x200u
#define DMA_ERR_ERR9_SHIFT 9
#define DMA_ERR_ERR10_MASK 0x400u
#define DMA_ERR_ERR10_SHIFT 10
#define DMA_ERR_ERR11_MASK 0x800u
#define DMA_ERR_ERR11_SHIFT 11
#define DMA_ERR_ERR12_MASK 0x1000u
#define DMA_ERR_ERR12_SHIFT 12
#define DMA_ERR_ERR13_MASK 0x2000u
#define DMA_ERR_ERR13_SHIFT 13
#define DMA_ERR_ERR14_MASK 0x4000u
#define DMA_ERR_ERR14_SHIFT 14
#define DMA_ERR_ERR15_MASK 0x8000u
#define DMA_ERR_ERR15_SHIFT 15
/* HRS Bit Fields */
#define DMA_HRS_HRS0_MASK 0x1u
#define DMA_HRS_HRS0_SHIFT 0
#define DMA_HRS_HRS1_MASK 0x2u
#define DMA_HRS_HRS1_SHIFT 1
#define DMA_HRS_HRS2_MASK 0x4u
#define DMA_HRS_HRS2_SHIFT 2
#define DMA_HRS_HRS3_MASK 0x8u
#define DMA_HRS_HRS3_SHIFT 3
#define DMA_HRS_HRS4_MASK 0x10u
#define DMA_HRS_HRS4_SHIFT 4
#define DMA_HRS_HRS5_MASK 0x20u
#define DMA_HRS_HRS5_SHIFT 5
#define DMA_HRS_HRS6_MASK 0x40u
#define DMA_HRS_HRS6_SHIFT 6
#define DMA_HRS_HRS7_MASK 0x80u
#define DMA_HRS_HRS7_SHIFT 7
#define DMA_HRS_HRS8_MASK 0x100u
#define DMA_HRS_HRS8_SHIFT 8
#define DMA_HRS_HRS9_MASK 0x200u
#define DMA_HRS_HRS9_SHIFT 9
#define DMA_HRS_HRS10_MASK 0x400u
#define DMA_HRS_HRS10_SHIFT 10
#define DMA_HRS_HRS11_MASK 0x800u
#define DMA_HRS_HRS11_SHIFT 11
#define DMA_HRS_HRS12_MASK 0x1000u
#define DMA_HRS_HRS12_SHIFT 12
#define DMA_HRS_HRS13_MASK 0x2000u
#define DMA_HRS_HRS13_SHIFT 13
#define DMA_HRS_HRS14_MASK 0x4000u
#define DMA_HRS_HRS14_SHIFT 14
#define DMA_HRS_HRS15_MASK 0x8000u
#define DMA_HRS_HRS15_SHIFT 15
/* DCHPRI3 Bit Fields */
#define DMA_DCHPRI3_CHPRI_MASK 0xFu
#define DMA_DCHPRI3_CHPRI_SHIFT 0
#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
#define DMA_DCHPRI3_DPA_MASK 0x40u
#define DMA_DCHPRI3_DPA_SHIFT 6
#define DMA_DCHPRI3_ECP_MASK 0x80u
#define DMA_DCHPRI3_ECP_SHIFT 7
/* DCHPRI2 Bit Fields */
#define DMA_DCHPRI2_CHPRI_MASK 0xFu
#define DMA_DCHPRI2_CHPRI_SHIFT 0
#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
#define DMA_DCHPRI2_DPA_MASK 0x40u
#define DMA_DCHPRI2_DPA_SHIFT 6
#define DMA_DCHPRI2_ECP_MASK 0x80u
#define DMA_DCHPRI2_ECP_SHIFT 7
/* DCHPRI1 Bit Fields */
#define DMA_DCHPRI1_CHPRI_MASK 0xFu
#define DMA_DCHPRI1_CHPRI_SHIFT 0
#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
#define DMA_DCHPRI1_DPA_MASK 0x40u
#define DMA_DCHPRI1_DPA_SHIFT 6
#define DMA_DCHPRI1_ECP_MASK 0x80u
#define DMA_DCHPRI1_ECP_SHIFT 7
/* DCHPRI0 Bit Fields */
#define DMA_DCHPRI0_CHPRI_MASK 0xFu
#define DMA_DCHPRI0_CHPRI_SHIFT 0
#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
#define DMA_DCHPRI0_DPA_MASK 0x40u
#define DMA_DCHPRI0_DPA_SHIFT 6
#define DMA_DCHPRI0_ECP_MASK 0x80u
#define DMA_DCHPRI0_ECP_SHIFT 7
/* DCHPRI7 Bit Fields */
#define DMA_DCHPRI7_CHPRI_MASK 0xFu
#define DMA_DCHPRI7_CHPRI_SHIFT 0
#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
#define DMA_DCHPRI7_DPA_MASK 0x40u
#define DMA_DCHPRI7_DPA_SHIFT 6
#define DMA_DCHPRI7_ECP_MASK 0x80u
#define DMA_DCHPRI7_ECP_SHIFT 7
/* DCHPRI6 Bit Fields */
#define DMA_DCHPRI6_CHPRI_MASK 0xFu
#define DMA_DCHPRI6_CHPRI_SHIFT 0
#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
#define DMA_DCHPRI6_DPA_MASK 0x40u
#define DMA_DCHPRI6_DPA_SHIFT 6
#define DMA_DCHPRI6_ECP_MASK 0x80u
#define DMA_DCHPRI6_ECP_SHIFT 7
/* DCHPRI5 Bit Fields */
#define DMA_DCHPRI5_CHPRI_MASK 0xFu
#define DMA_DCHPRI5_CHPRI_SHIFT 0
#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
#define DMA_DCHPRI5_DPA_MASK 0x40u
#define DMA_DCHPRI5_DPA_SHIFT 6
#define DMA_DCHPRI5_ECP_MASK 0x80u
#define DMA_DCHPRI5_ECP_SHIFT 7
/* DCHPRI4 Bit Fields */
#define DMA_DCHPRI4_CHPRI_MASK 0xFu
#define DMA_DCHPRI4_CHPRI_SHIFT 0
#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
#define DMA_DCHPRI4_DPA_MASK 0x40u
#define DMA_DCHPRI4_DPA_SHIFT 6
#define DMA_DCHPRI4_ECP_MASK 0x80u
#define DMA_DCHPRI4_ECP_SHIFT 7
/* DCHPRI11 Bit Fields */
#define DMA_DCHPRI11_CHPRI_MASK 0xFu
#define DMA_DCHPRI11_CHPRI_SHIFT 0
#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
#define DMA_DCHPRI11_DPA_MASK 0x40u
#define DMA_DCHPRI11_DPA_SHIFT 6
#define DMA_DCHPRI11_ECP_MASK 0x80u
#define DMA_DCHPRI11_ECP_SHIFT 7
/* DCHPRI10 Bit Fields */
#define DMA_DCHPRI10_CHPRI_MASK 0xFu
#define DMA_DCHPRI10_CHPRI_SHIFT 0
#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
#define DMA_DCHPRI10_DPA_MASK 0x40u
#define DMA_DCHPRI10_DPA_SHIFT 6
#define DMA_DCHPRI10_ECP_MASK 0x80u
#define DMA_DCHPRI10_ECP_SHIFT 7
/* DCHPRI9 Bit Fields */
#define DMA_DCHPRI9_CHPRI_MASK 0xFu
#define DMA_DCHPRI9_CHPRI_SHIFT 0
#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
#define DMA_DCHPRI9_DPA_MASK 0x40u
#define DMA_DCHPRI9_DPA_SHIFT 6
#define DMA_DCHPRI9_ECP_MASK 0x80u
#define DMA_DCHPRI9_ECP_SHIFT 7
/* DCHPRI8 Bit Fields */
#define DMA_DCHPRI8_CHPRI_MASK 0xFu
#define DMA_DCHPRI8_CHPRI_SHIFT 0
#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
#define DMA_DCHPRI8_DPA_MASK 0x40u
#define DMA_DCHPRI8_DPA_SHIFT 6
#define DMA_DCHPRI8_ECP_MASK 0x80u
#define DMA_DCHPRI8_ECP_SHIFT 7
/* DCHPRI15 Bit Fields */
#define DMA_DCHPRI15_CHPRI_MASK 0xFu
#define DMA_DCHPRI15_CHPRI_SHIFT 0
#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
#define DMA_DCHPRI15_DPA_MASK 0x40u
#define DMA_DCHPRI15_DPA_SHIFT 6
#define DMA_DCHPRI15_ECP_MASK 0x80u
#define DMA_DCHPRI15_ECP_SHIFT 7
/* DCHPRI14 Bit Fields */
#define DMA_DCHPRI14_CHPRI_MASK 0xFu
#define DMA_DCHPRI14_CHPRI_SHIFT 0
#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
#define DMA_DCHPRI14_DPA_MASK 0x40u
#define DMA_DCHPRI14_DPA_SHIFT 6
#define DMA_DCHPRI14_ECP_MASK 0x80u
#define DMA_DCHPRI14_ECP_SHIFT 7
/* DCHPRI13 Bit Fields */
#define DMA_DCHPRI13_CHPRI_MASK 0xFu
#define DMA_DCHPRI13_CHPRI_SHIFT 0
#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
#define DMA_DCHPRI13_DPA_MASK 0x40u
#define DMA_DCHPRI13_DPA_SHIFT 6
#define DMA_DCHPRI13_ECP_MASK 0x80u
#define DMA_DCHPRI13_ECP_SHIFT 7
/* DCHPRI12 Bit Fields */
#define DMA_DCHPRI12_CHPRI_MASK 0xFu
#define DMA_DCHPRI12_CHPRI_SHIFT 0
#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
#define DMA_DCHPRI12_DPA_MASK 0x40u
#define DMA_DCHPRI12_DPA_SHIFT 6
#define DMA_DCHPRI12_ECP_MASK 0x80u
#define DMA_DCHPRI12_ECP_SHIFT 7
/* SADDR Bit Fields */
#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
#define DMA_SADDR_SADDR_SHIFT 0
#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
/* SOFF Bit Fields */
#define DMA_SOFF_SOFF_MASK 0xFFFFu
#define DMA_SOFF_SOFF_SHIFT 0
#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
/* ATTR Bit Fields */
#define DMA_ATTR_DSIZE_MASK 0x7u
#define DMA_ATTR_DSIZE_SHIFT 0
#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
#define DMA_ATTR_DMOD_MASK 0xF8u
#define DMA_ATTR_DMOD_SHIFT 3
#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
#define DMA_ATTR_SSIZE_MASK 0x700u
#define DMA_ATTR_SSIZE_SHIFT 8
#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
#define DMA_ATTR_SMOD_MASK 0xF800u
#define DMA_ATTR_SMOD_SHIFT 11
#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
/* NBYTES_MLNO Bit Fields */
#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
/* NBYTES_MLOFFNO Bit Fields */
#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
/* NBYTES_MLOFFYES Bit Fields */
#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
/* SLAST Bit Fields */
#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
#define DMA_SLAST_SLAST_SHIFT 0
#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
/* DADDR Bit Fields */
#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
#define DMA_DADDR_DADDR_SHIFT 0
#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
/* DOFF Bit Fields */
#define DMA_DOFF_DOFF_MASK 0xFFFFu
#define DMA_DOFF_DOFF_SHIFT 0
#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
/* CITER_ELINKYES Bit Fields */
#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
#define DMA_CITER_ELINKYES_CITER_SHIFT 0
#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
/* CITER_ELINKNO Bit Fields */
#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
#define DMA_CITER_ELINKNO_CITER_SHIFT 0
#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
/* DLAST_SGA Bit Fields */
#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
/* CSR Bit Fields */
#define DMA_CSR_START_MASK 0x1u
#define DMA_CSR_START_SHIFT 0
#define DMA_CSR_INTMAJOR_MASK 0x2u
#define DMA_CSR_INTMAJOR_SHIFT 1
#define DMA_CSR_INTHALF_MASK 0x4u
#define DMA_CSR_INTHALF_SHIFT 2
#define DMA_CSR_DREQ_MASK 0x8u
#define DMA_CSR_DREQ_SHIFT 3
#define DMA_CSR_ESG_MASK 0x10u
#define DMA_CSR_ESG_SHIFT 4
#define DMA_CSR_MAJORELINK_MASK 0x20u
#define DMA_CSR_MAJORELINK_SHIFT 5
#define DMA_CSR_ACTIVE_MASK 0x40u
#define DMA_CSR_ACTIVE_SHIFT 6
#define DMA_CSR_DONE_MASK 0x80u
#define DMA_CSR_DONE_SHIFT 7
#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
#define DMA_CSR_MAJORLINKCH_SHIFT 8
#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
#define DMA_CSR_BWC_MASK 0xC000u
#define DMA_CSR_BWC_SHIFT 14
#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
/* BITER_ELINKNO Bit Fields */
#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
#define DMA_BITER_ELINKNO_BITER_SHIFT 0
#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
/* BITER_ELINKYES Bit Fields */
#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
#define DMA_BITER_ELINKYES_BITER_SHIFT 0
#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
/**
* @}
*/ /* end of group DMA_Register_Masks */
/* DMA - Peripheral instance base addresses */
/** Peripheral DMA base pointer */
#define DMA_BASE_PTR ((DMA_MemMapPtr)0x40008000u)
/* ----------------------------------------------------------------------------
-- DMA - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
* @{
*/
/* DMA - Register instance definitions */
/* DMA */
#define DMA_CR DMA_CR_REG(DMA_BASE_PTR)
#define DMA_ES DMA_ES_REG(DMA_BASE_PTR)
#define DMA_ERQ DMA_ERQ_REG(DMA_BASE_PTR)
#define DMA_EEI DMA_EEI_REG(DMA_BASE_PTR)
#define DMA_CEEI DMA_CEEI_REG(DMA_BASE_PTR)
#define DMA_SEEI DMA_SEEI_REG(DMA_BASE_PTR)
#define DMA_CERQ DMA_CERQ_REG(DMA_BASE_PTR)
#define DMA_SERQ DMA_SERQ_REG(DMA_BASE_PTR)
#define DMA_CDNE DMA_CDNE_REG(DMA_BASE_PTR)
#define DMA_SSRT DMA_SSRT_REG(DMA_BASE_PTR)
#define DMA_CERR DMA_CERR_REG(DMA_BASE_PTR)
#define DMA_CINT DMA_CINT_REG(DMA_BASE_PTR)
#define DMA_INT DMA_INT_REG(DMA_BASE_PTR)
#define DMA_ERR DMA_ERR_REG(DMA_BASE_PTR)
#define DMA_HRS DMA_HRS_REG(DMA_BASE_PTR)
#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA_BASE_PTR)
#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA_BASE_PTR)
#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA_BASE_PTR)
#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA_BASE_PTR)
#define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA_BASE_PTR)
#define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA_BASE_PTR)
#define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA_BASE_PTR)
#define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA_BASE_PTR)
#define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA_BASE_PTR)
#define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA_BASE_PTR)
#define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA_BASE_PTR)
#define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA_BASE_PTR)
#define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA_BASE_PTR)
#define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA_BASE_PTR)
#define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA_BASE_PTR)
#define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA_BASE_PTR)
#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_CSR DMA_CSR_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,0)
#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,0)
#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_CSR DMA_CSR_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,1)
#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,1)
#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_CSR DMA_CSR_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,2)
#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,2)
#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_CSR DMA_CSR_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,3)
#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,3)
#define DMA_TCD4_SADDR DMA_SADDR_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_SOFF DMA_SOFF_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_ATTR DMA_ATTR_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_SLAST DMA_SLAST_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_DADDR DMA_DADDR_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_DOFF DMA_DOFF_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_CSR DMA_CSR_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,4)
#define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,4)
#define DMA_TCD5_SADDR DMA_SADDR_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_SOFF DMA_SOFF_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_ATTR DMA_ATTR_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_SLAST DMA_SLAST_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_DADDR DMA_DADDR_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_DOFF DMA_DOFF_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_CSR DMA_CSR_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,5)
#define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,5)
#define DMA_TCD6_SADDR DMA_SADDR_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_SOFF DMA_SOFF_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_ATTR DMA_ATTR_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_SLAST DMA_SLAST_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_DADDR DMA_DADDR_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_DOFF DMA_DOFF_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_CSR DMA_CSR_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,6)
#define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,6)
#define DMA_TCD7_SADDR DMA_SADDR_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_SOFF DMA_SOFF_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_ATTR DMA_ATTR_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_SLAST DMA_SLAST_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_DADDR DMA_DADDR_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_DOFF DMA_DOFF_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_CSR DMA_CSR_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,7)
#define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,7)
#define DMA_TCD8_SADDR DMA_SADDR_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_SOFF DMA_SOFF_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_ATTR DMA_ATTR_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_SLAST DMA_SLAST_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_DADDR DMA_DADDR_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_DOFF DMA_DOFF_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_CSR DMA_CSR_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,8)
#define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,8)
#define DMA_TCD9_SADDR DMA_SADDR_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_SOFF DMA_SOFF_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_ATTR DMA_ATTR_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_SLAST DMA_SLAST_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_DADDR DMA_DADDR_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_DOFF DMA_DOFF_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_CSR DMA_CSR_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,9)
#define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,9)
#define DMA_TCD10_SADDR DMA_SADDR_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_SOFF DMA_SOFF_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_ATTR DMA_ATTR_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_SLAST DMA_SLAST_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_DADDR DMA_DADDR_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_DOFF DMA_DOFF_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_CSR DMA_CSR_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,10)
#define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,10)
#define DMA_TCD11_SADDR DMA_SADDR_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_SOFF DMA_SOFF_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_ATTR DMA_ATTR_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_SLAST DMA_SLAST_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_DADDR DMA_DADDR_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_DOFF DMA_DOFF_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_CSR DMA_CSR_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,11)
#define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,11)
#define DMA_TCD12_SADDR DMA_SADDR_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_SOFF DMA_SOFF_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_ATTR DMA_ATTR_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_SLAST DMA_SLAST_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_DADDR DMA_DADDR_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_DOFF DMA_DOFF_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_CSR DMA_CSR_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,12)
#define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,12)
#define DMA_TCD13_SADDR DMA_SADDR_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_SOFF DMA_SOFF_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_ATTR DMA_ATTR_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_SLAST DMA_SLAST_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_DADDR DMA_DADDR_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_DOFF DMA_DOFF_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_CSR DMA_CSR_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,13)
#define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,13)
#define DMA_TCD14_SADDR DMA_SADDR_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_SOFF DMA_SOFF_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_ATTR DMA_ATTR_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_SLAST DMA_SLAST_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_DADDR DMA_DADDR_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_DOFF DMA_DOFF_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_CSR DMA_CSR_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,14)
#define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,14)
#define DMA_TCD15_SADDR DMA_SADDR_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_SOFF DMA_SOFF_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_ATTR DMA_ATTR_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_SLAST DMA_SLAST_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_DADDR DMA_DADDR_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_DOFF DMA_DOFF_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_CSR DMA_CSR_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,15)
#define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,15)
/* DMA - Register array accessors */
#define DMA_SADDR(index) DMA_SADDR_REG(DMA_BASE_PTR,index)
#define DMA_SOFF(index) DMA_SOFF_REG(DMA_BASE_PTR,index)
#define DMA_ATTR(index) DMA_ATTR_REG(DMA_BASE_PTR,index)
#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,index)
#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,index)
#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,index)
#define DMA_SLAST(index) DMA_SLAST_REG(DMA_BASE_PTR,index)
#define DMA_DADDR(index) DMA_DADDR_REG(DMA_BASE_PTR,index)
#define DMA_DOFF(index) DMA_DOFF_REG(DMA_BASE_PTR,index)
#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,index)
#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,index)
#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA_BASE_PTR,index)
#define DMA_CSR(index) DMA_CSR_REG(DMA_BASE_PTR,index)
#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,index)
#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,index)
/**
* @}
*/ /* end of group DMA_Register_Accessor_Macros */
/**
* @}
*/ /* end of group DMA_Peripheral */
/* ----------------------------------------------------------------------------
-- DMAMUX
---------------------------------------------------------------------------- */
/**
* @addtogroup DMAMUX_Peripheral DMAMUX
* @{
*/
/** DMAMUX - Peripheral register structure */
typedef struct DMAMUX_MemMap {
uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
} volatile *DMAMUX_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DMAMUX - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
* @{
*/
/* DMAMUX - Register accessors */
#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
/**
* @}
*/ /* end of group DMAMUX_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DMAMUX Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
* @{
*/
/* CHCFG Bit Fields */
#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
#define DMAMUX_CHCFG_SOURCE_SHIFT 0
#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
#define DMAMUX_CHCFG_TRIG_MASK 0x40u
#define DMAMUX_CHCFG_TRIG_SHIFT 6
#define DMAMUX_CHCFG_ENBL_MASK 0x80u
#define DMAMUX_CHCFG_ENBL_SHIFT 7
/**
* @}
*/ /* end of group DMAMUX_Register_Masks */
/* DMAMUX - Peripheral instance base addresses */
/** Peripheral DMAMUX base pointer */
#define DMAMUX_BASE_PTR ((DMAMUX_MemMapPtr)0x40021000u)
/* ----------------------------------------------------------------------------
-- DMAMUX - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
* @{
*/
/* DMAMUX - Register instance definitions */
/* DMAMUX */
#define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,0)
#define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,1)
#define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,2)
#define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,3)
#define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,4)
#define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,5)
#define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,6)
#define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,7)
#define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,8)
#define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,9)
#define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,10)
#define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,11)
#define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,12)
#define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,13)
#define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,14)
#define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,15)
/* DMAMUX - Register array accessors */
#define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX_BASE_PTR,index)
/**
* @}
*/ /* end of group DMAMUX_Register_Accessor_Macros */
/**
* @}
*/ /* end of group DMAMUX_Peripheral */
/* ----------------------------------------------------------------------------
-- DWT
---------------------------------------------------------------------------- */
/**
* @addtogroup DWT_Peripheral DWT
* @{
*/
/** DWT - Peripheral register structure */
typedef struct DWT_MemMap {
uint32_t CTRL; /**< Control Register, offset: 0x0 */
uint32_t CYCCNT; /**< Cycle Count Register, offset: 0x4 */
uint32_t CPICNT; /**< CPI Count Register, offset: 0x8 */
uint32_t EXCCNT; /**< Exception Overhead Count Register, offset: 0xC */
uint32_t SLEEPCNT; /**< Sleep Count Register, offset: 0x10 */
uint32_t LSUCNT; /**< LSU Count Register, offset: 0x14 */
uint32_t FOLDCNT; /**< Folded-instruction Count Register, offset: 0x18 */
uint32_t PCSR; /**< Program Counter Sample Register, offset: 0x1C */
struct { /* offset: 0x20, array step: 0x10 */
uint32_t COMP; /**< Comparator Register 0..Comparator Register 3, array offset: 0x20, array step: 0x10 */
uint32_t MASK; /**< Mask Register 0..Mask Register 3, array offset: 0x24, array step: 0x10 */
uint32_t FUNCTION; /**< Function Register 0..Function Register 3, array offset: 0x28, array step: 0x10 */
uint8_t RESERVED_0[4];
} COMPARATOR[4];
uint8_t RESERVED_0[3952];
uint32_t PID4; /**< Peripheral Identification Register 4., offset: 0xFD0 */
uint32_t PID5; /**< Peripheral Identification Register 5., offset: 0xFD4 */
uint32_t PID6; /**< Peripheral Identification Register 6., offset: 0xFD8 */
uint32_t PID7; /**< Peripheral Identification Register 7., offset: 0xFDC */
uint32_t PID0; /**< Peripheral Identification Register 0., offset: 0xFE0 */
uint32_t PID1; /**< Peripheral Identification Register 1., offset: 0xFE4 */
uint32_t PID2; /**< Peripheral Identification Register 2., offset: 0xFE8 */
uint32_t PID3; /**< Peripheral Identification Register 3., offset: 0xFEC */
uint32_t CID0; /**< Component Identification Register 0., offset: 0xFF0 */
uint32_t CID1; /**< Component Identification Register 1., offset: 0xFF4 */
uint32_t CID2; /**< Component Identification Register 2., offset: 0xFF8 */
uint32_t CID3; /**< Component Identification Register 3., offset: 0xFFC */
} volatile *DWT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DWT - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros
* @{
*/
/* DWT - Register accessors */
#define DWT_CTRL_REG(base) ((base)->CTRL)
#define DWT_CYCCNT_REG(base) ((base)->CYCCNT)
#define DWT_CPICNT_REG(base) ((base)->CPICNT)
#define DWT_EXCCNT_REG(base) ((base)->EXCCNT)
#define DWT_SLEEPCNT_REG(base) ((base)->SLEEPCNT)
#define DWT_LSUCNT_REG(base) ((base)->LSUCNT)
#define DWT_FOLDCNT_REG(base) ((base)->FOLDCNT)
#define DWT_PCSR_REG(base) ((base)->PCSR)
#define DWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
#define DWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
#define DWT_FUNCTION_REG(base,index) ((base)->COMPARATOR[index].FUNCTION)
#define DWT_PID4_REG(base) ((base)->PID4)
#define DWT_PID5_REG(base) ((base)->PID5)
#define DWT_PID6_REG(base) ((base)->PID6)
#define DWT_PID7_REG(base) ((base)->PID7)
#define DWT_PID0_REG(base) ((base)->PID0)
#define DWT_PID1_REG(base) ((base)->PID1)
#define DWT_PID2_REG(base) ((base)->PID2)
#define DWT_PID3_REG(base) ((base)->PID3)
#define DWT_CID0_REG(base) ((base)->CID0)
#define DWT_CID1_REG(base) ((base)->CID1)
#define DWT_CID2_REG(base) ((base)->CID2)
#define DWT_CID3_REG(base) ((base)->CID3)
/**
* @}
*/ /* end of group DWT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DWT Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup DWT_Register_Masks DWT Register Masks
* @{
*/
/**
* @}
*/ /* end of group DWT_Register_Masks */
/* DWT - Peripheral instance base addresses */
/** Peripheral DWT base pointer */
#define DWT_BASE_PTR ((DWT_MemMapPtr)0xE0001000u)
/* ----------------------------------------------------------------------------
-- DWT - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros
* @{
*/
/* DWT - Register instance definitions */
/* DWT */
#define DWT_CTRL DWT_CTRL_REG(DWT_BASE_PTR)
#define DWT_CYCCNT DWT_CYCCNT_REG(DWT_BASE_PTR)
#define DWT_CPICNT DWT_CPICNT_REG(DWT_BASE_PTR)
#define DWT_EXCCNT DWT_EXCCNT_REG(DWT_BASE_PTR)
#define DWT_SLEEPCNT DWT_SLEEPCNT_REG(DWT_BASE_PTR)
#define DWT_LSUCNT DWT_LSUCNT_REG(DWT_BASE_PTR)
#define DWT_FOLDCNT DWT_FOLDCNT_REG(DWT_BASE_PTR)
#define DWT_PCSR DWT_PCSR_REG(DWT_BASE_PTR)
#define DWT_COMP0 DWT_COMP_REG(DWT_BASE_PTR,0)
#define DWT_MASK0 DWT_MASK_REG(DWT_BASE_PTR,0)
#define DWT_FUNCTION0 DWT_FUNCTION_REG(DWT_BASE_PTR,0)
#define DWT_COMP1 DWT_COMP_REG(DWT_BASE_PTR,1)
#define DWT_MASK1 DWT_MASK_REG(DWT_BASE_PTR,1)
#define DWT_FUNCTION1 DWT_FUNCTION_REG(DWT_BASE_PTR,1)
#define DWT_COMP2 DWT_COMP_REG(DWT_BASE_PTR,2)
#define DWT_MASK2 DWT_MASK_REG(DWT_BASE_PTR,2)
#define DWT_FUNCTION2 DWT_FUNCTION_REG(DWT_BASE_PTR,2)
#define DWT_COMP3 DWT_COMP_REG(DWT_BASE_PTR,3)
#define DWT_MASK3 DWT_MASK_REG(DWT_BASE_PTR,3)
#define DWT_FUNCTION3 DWT_FUNCTION_REG(DWT_BASE_PTR,3)
#define DWT_PID4 DWT_PID4_REG(DWT_BASE_PTR)
#define DWT_PID5 DWT_PID5_REG(DWT_BASE_PTR)
#define DWT_PID6 DWT_PID6_REG(DWT_BASE_PTR)
#define DWT_PID7 DWT_PID7_REG(DWT_BASE_PTR)
#define DWT_PID0 DWT_PID0_REG(DWT_BASE_PTR)
#define DWT_PID1 DWT_PID1_REG(DWT_BASE_PTR)
#define DWT_PID2 DWT_PID2_REG(DWT_BASE_PTR)
#define DWT_PID3 DWT_PID3_REG(DWT_BASE_PTR)
#define DWT_CID0 DWT_CID0_REG(DWT_BASE_PTR)
#define DWT_CID1 DWT_CID1_REG(DWT_BASE_PTR)
#define DWT_CID2 DWT_CID2_REG(DWT_BASE_PTR)
#define DWT_CID3 DWT_CID3_REG(DWT_BASE_PTR)
/* DWT - Register array accessors */
#define DWT_COMP(index) DWT_COMP_REG(DWT_BASE_PTR,index)
#define DWT_MASK(index) DWT_MASK_REG(DWT_BASE_PTR,index)
#define DWT_FUNCTION(index) DWT_FUNCTION_REG(DWT_BASE_PTR,index)
/**
* @}
*/ /* end of group DWT_Register_Accessor_Macros */
/**
* @}
*/ /* end of group DWT_Peripheral */
/* ----------------------------------------------------------------------------
-- ETB
---------------------------------------------------------------------------- */
/**
* @addtogroup ETB_Peripheral ETB
* @{
*/
/** ETB - Peripheral register structure */
typedef struct ETB_MemMap {
uint8_t RESERVED_0[4];
uint32_t RDP; /**< RAM Depth Register, offset: 0x4 */
uint8_t RESERVED_1[4];
uint32_t STS; /**< Status Register, offset: 0xC */
uint32_t RRD; /**< RAM Read Data Register, offset: 0x10 */
uint32_t RRP; /**< RAM Read Pointer Register, offset: 0x14 */
uint32_t RWP; /**< RAM Write Pointer Register, offset: 0x18 */
uint32_t TRG; /**< Trigger Counter Register, offset: 0x1C */
uint32_t CTL; /**< Control Register, offset: 0x20 */
uint32_t RWD; /**< RAM Write Data Register, offset: 0x24 */
uint8_t RESERVED_2[728];
uint32_t FFSR; /**< Formatter and Flush Status Register, offset: 0x300 */
uint32_t FFCR; /**< Formatter and Flush Control Register, offset: 0x304 */
uint8_t RESERVED_3[3032];
uint32_t ITMISCOP0; /**< Integration Register, ITMISCOP0, offset: 0xEE0 */
uint32_t ITTRFLINACK; /**< Integration Register, ITTRFLINACK, offset: 0xEE4 */
uint32_t ITTRFLIN; /**< Integration Register, ITTRFLIN, offset: 0xEE8 */
uint32_t ITATBDATA0; /**< Integration Register, ITATBDATA0, offset: 0xEEC */
uint32_t ITATBCTR2; /**< Integration Register, ITATBCTR2, offset: 0xEF0 */
uint32_t ITATBCTR1; /**< Integration Register, ITATBCTR1, offset: 0xEF4 */
uint32_t ITATBCTR0; /**< Integration Register, ITATBCTR0, offset: 0xEF8 */
uint8_t RESERVED_4[4];
uint32_t ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */
uint8_t RESERVED_5[156];
uint32_t CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */
uint32_t CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */
uint8_t RESERVED_6[8];
uint32_t LAR; /**< Lock Access Register, offset: 0xFB0 */
uint32_t LSR; /**< Lock Status Register, offset: 0xFB4 */
uint32_t AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */
uint8_t RESERVED_7[12];
uint32_t DEVID; /**< Device ID Register, offset: 0xFC8 */
uint32_t DEVTYPE; /**< Device Type Identifier Register, offset: 0xFCC */
uint32_t PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */
uint32_t PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */
uint32_t PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */
uint32_t PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */
uint32_t PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */
uint32_t PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */
uint32_t PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */
uint32_t PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */
uint32_t CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */
uint32_t CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */
uint32_t CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */
uint32_t CIDR3; /**< Component Identification Register 3, offset: 0xFFC */
} volatile *ETB_MemMapPtr;
/* ----------------------------------------------------------------------------
-- ETB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup ETB_Register_Accessor_Macros ETB - Register accessor macros
* @{
*/
/* ETB - Register accessors */
#define ETB_RDP_REG(base) ((base)->RDP)
#define ETB_STS_REG(base) ((base)->STS)
#define ETB_RRD_REG(base) ((base)->RRD)
#define ETB_RRP_REG(base) ((base)->RRP)
#define ETB_RWP_REG(base) ((base)->RWP)
#define ETB_TRG_REG(base) ((base)->TRG)
#define ETB_CTL_REG(base) ((base)->CTL)
#define ETB_RWD_REG(base) ((base)->RWD)
#define ETB_FFSR_REG(base) ((base)->FFSR)
#define ETB_FFCR_REG(base) ((base)->FFCR)
#define ETB_ITMISCOP0_REG(base) ((base)->ITMISCOP0)
#define ETB_ITTRFLINACK_REG(base) ((base)->ITTRFLINACK)
#define ETB_ITTRFLIN_REG(base) ((base)->ITTRFLIN)
#define ETB_ITATBDATA0_REG(base) ((base)->ITATBDATA0)
#define ETB_ITATBCTR2_REG(base) ((base)->ITATBCTR2)
#define ETB_ITATBCTR1_REG(base) ((base)->ITATBCTR1)
#define ETB_ITATBCTR0_REG(base) ((base)->ITATBCTR0)
#define ETB_ITCTRL_REG(base) ((base)->ITCTRL)
#define ETB_CLAIMSET_REG(base) ((base)->CLAIMSET)
#define ETB_CLAIMCLR_REG(base) ((base)->CLAIMCLR)
#define ETB_LAR_REG(base) ((base)->LAR)
#define ETB_LSR_REG(base) ((base)->LSR)
#define ETB_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS)
#define ETB_DEVID_REG(base) ((base)->DEVID)
#define ETB_DEVTYPE_REG(base) ((base)->DEVTYPE)
#define ETB_PIDR4_REG(base) ((base)->PIDR4)
#define ETB_PIDR5_REG(base) ((base)->PIDR5)
#define ETB_PIDR6_REG(base) ((base)->PIDR6)
#define ETB_PIDR7_REG(base) ((base)->PIDR7)
#define ETB_PIDR0_REG(base) ((base)->PIDR0)
#define ETB_PIDR1_REG(base) ((base)->PIDR1)
#define ETB_PIDR2_REG(base) ((base)->PIDR2)
#define ETB_PIDR3_REG(base) ((base)->PIDR3)
#define ETB_CIDR0_REG(base) ((base)->CIDR0)
#define ETB_CIDR1_REG(base) ((base)->CIDR1)
#define ETB_CIDR2_REG(base) ((base)->CIDR2)
#define ETB_CIDR3_REG(base) ((base)->CIDR3)
/**
* @}
*/ /* end of group ETB_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- ETB Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup ETB_Register_Masks ETB Register Masks
* @{
*/
/**
* @}
*/ /* end of group ETB_Register_Masks */
/* ETB - Peripheral instance base addresses */
/** Peripheral ETB base pointer */
#define ETB_BASE_PTR ((ETB_MemMapPtr)0xE0042000u)
/* ----------------------------------------------------------------------------
-- ETB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup ETB_Register_Accessor_Macros ETB - Register accessor macros
* @{
*/
/* ETB - Register instance definitions */
/* ETB */
#define ETB_RDP ETB_RDP_REG(ETB_BASE_PTR)
#define ETB_STS ETB_STS_REG(ETB_BASE_PTR)
#define ETB_RRD ETB_RRD_REG(ETB_BASE_PTR)
#define ETB_RRP ETB_RRP_REG(ETB_BASE_PTR)
#define ETB_RWP ETB_RWP_REG(ETB_BASE_PTR)
#define ETB_TRG ETB_TRG_REG(ETB_BASE_PTR)
#define ETB_CTL ETB_CTL_REG(ETB_BASE_PTR)
#define ETB_RWD ETB_RWD_REG(ETB_BASE_PTR)
#define ETB_FFSR ETB_FFSR_REG(ETB_BASE_PTR)
#define ETB_FFCR ETB_FFCR_REG(ETB_BASE_PTR)
#define ETB_ITMISCOP0 ETB_ITMISCOP0_REG(ETB_BASE_PTR)
#define ETB_ITTRFLINACK ETB_ITTRFLINACK_REG(ETB_BASE_PTR)
#define ETB_ITTRFLIN ETB_ITTRFLIN_REG(ETB_BASE_PTR)
#define ETB_ITATBDATA0 ETB_ITATBDATA0_REG(ETB_BASE_PTR)
#define ETB_ITATBCTR2 ETB_ITATBCTR2_REG(ETB_BASE_PTR)
#define ETB_ITATBCTR1 ETB_ITATBCTR1_REG(ETB_BASE_PTR)
#define ETB_ITATBCTR0 ETB_ITATBCTR0_REG(ETB_BASE_PTR)
#define ETB_ITCTRL ETB_ITCTRL_REG(ETB_BASE_PTR)
#define ETB_CLAIMSET ETB_CLAIMSET_REG(ETB_BASE_PTR)
#define ETB_CLAIMCLR ETB_CLAIMCLR_REG(ETB_BASE_PTR)
#define ETB_LAR ETB_LAR_REG(ETB_BASE_PTR)
#define ETB_LSR ETB_LSR_REG(ETB_BASE_PTR)
#define ETB_AUTHSTATUS ETB_AUTHSTATUS_REG(ETB_BASE_PTR)
#define ETB_DEVID ETB_DEVID_REG(ETB_BASE_PTR)
#define ETB_DEVTYPE ETB_DEVTYPE_REG(ETB_BASE_PTR)
#define ETB_PIDR4 ETB_PIDR4_REG(ETB_BASE_PTR)
#define ETB_PIDR5 ETB_PIDR5_REG(ETB_BASE_PTR)
#define ETB_PIDR6 ETB_PIDR6_REG(ETB_BASE_PTR)
#define ETB_PIDR7 ETB_PIDR7_REG(ETB_BASE_PTR)
#define ETB_PIDR0 ETB_PIDR0_REG(ETB_BASE_PTR)
#define ETB_PIDR1 ETB_PIDR1_REG(ETB_BASE_PTR)
#define ETB_PIDR2 ETB_PIDR2_REG(ETB_BASE_PTR)
#define ETB_PIDR3 ETB_PIDR3_REG(ETB_BASE_PTR)
#define ETB_CIDR0 ETB_CIDR0_REG(ETB_BASE_PTR)
#define ETB_CIDR1 ETB_CIDR1_REG(ETB_BASE_PTR)
#define ETB_CIDR2 ETB_CIDR2_REG(ETB_BASE_PTR)
#define ETB_CIDR3 ETB_CIDR3_REG(ETB_BASE_PTR)
/**
* @}
*/ /* end of group ETB_Register_Accessor_Macros */
/**
* @}
*/ /* end of group ETB_Peripheral */
/* ----------------------------------------------------------------------------
-- ETF
---------------------------------------------------------------------------- */
/**
* @addtogroup ETF_Peripheral ETF
* @{
*/
/** ETF - Peripheral register structure */
typedef struct ETF_MemMap {
uint32_t FCR; /**< Funnel Control Register, offset: 0x0 */
uint32_t PCR; /**< Priority Control Register, offset: 0x4 */
uint8_t RESERVED_0[3812];
uint32_t ITATBDATA0; /**< Integration Register, ITATBDATA0, offset: 0xEEC */
uint32_t ITATBCTR2; /**< Integration Register, ITATBCTR2, offset: 0xEF0 */
uint32_t ITATBCTR1; /**< Integration Register, ITATBCTR1, offset: 0xEF4 */
uint32_t ITATBCTR0; /**< Integration Register, ITATBCTR0, offset: 0xEF8 */
uint8_t RESERVED_1[4];
uint32_t ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */
uint8_t RESERVED_2[156];
uint32_t CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */
uint32_t CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */
uint8_t RESERVED_3[8];
uint32_t LAR; /**< Lock Access Register, offset: 0xFB0 */
uint32_t LSR; /**< Lock Status Register, offset: 0xFB4 */
uint32_t AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */
uint8_t RESERVED_4[12];
uint32_t DEVID; /**< Device ID Register, offset: 0xFC8 */
uint32_t DEVTYPE; /**< Device Type Identifier Register, offset: 0xFCC */
uint32_t PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */
uint32_t PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */
uint32_t PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */
uint32_t PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */
uint32_t PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */
uint32_t PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */
uint32_t PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */
uint32_t PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */
uint32_t CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */
uint32_t CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */
uint32_t CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */
uint32_t CIDR3; /**< Component Identification Register 3, offset: 0xFFC */
} volatile *ETF_MemMapPtr;
/* ----------------------------------------------------------------------------
-- ETF - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup ETF_Register_Accessor_Macros ETF - Register accessor macros
* @{
*/
/* ETF - Register accessors */
#define ETF_FCR_REG(base) ((base)->FCR)
#define ETF_PCR_REG(base) ((base)->PCR)
#define ETF_ITATBDATA0_REG(base) ((base)->ITATBDATA0)
#define ETF_ITATBCTR2_REG(base) ((base)->ITATBCTR2)
#define ETF_ITATBCTR1_REG(base) ((base)->ITATBCTR1)
#define ETF_ITATBCTR0_REG(base) ((base)->ITATBCTR0)
#define ETF_ITCTRL_REG(base) ((base)->ITCTRL)
#define ETF_CLAIMSET_REG(base) ((base)->CLAIMSET)
#define ETF_CLAIMCLR_REG(base) ((base)->CLAIMCLR)
#define ETF_LAR_REG(base) ((base)->LAR)
#define ETF_LSR_REG(base) ((base)->LSR)
#define ETF_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS)
#define ETF_DEVID_REG(base) ((base)->DEVID)
#define ETF_DEVTYPE_REG(base) ((base)->DEVTYPE)
#define ETF_PIDR4_REG(base) ((base)->PIDR4)
#define ETF_PIDR5_REG(base) ((base)->PIDR5)
#define ETF_PIDR6_REG(base) ((base)->PIDR6)
#define ETF_PIDR7_REG(base) ((base)->PIDR7)
#define ETF_PIDR0_REG(base) ((base)->PIDR0)
#define ETF_PIDR1_REG(base) ((base)->PIDR1)
#define ETF_PIDR2_REG(base) ((base)->PIDR2)
#define ETF_PIDR3_REG(base) ((base)->PIDR3)
#define ETF_CIDR0_REG(base) ((base)->CIDR0)
#define ETF_CIDR1_REG(base) ((base)->CIDR1)
#define ETF_CIDR2_REG(base) ((base)->CIDR2)
#define ETF_CIDR3_REG(base) ((base)->CIDR3)
/**
* @}
*/ /* end of group ETF_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- ETF Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup ETF_Register_Masks ETF Register Masks
* @{
*/
/**
* @}
*/ /* end of group ETF_Register_Masks */
/* ETF - Peripheral instance base addresses */
/** Peripheral ETF base pointer */
#define ETF_BASE_PTR ((ETF_MemMapPtr)0xE0043000u)
/* ----------------------------------------------------------------------------
-- ETF - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup ETF_Register_Accessor_Macros ETF - Register accessor macros
* @{
*/
/* ETF - Register instance definitions */
/* ETF */
#define ETF_FCR ETF_FCR_REG(ETF_BASE_PTR)
#define ETF_PCR ETF_PCR_REG(ETF_BASE_PTR)
#define ETF_ITATBDATA0 ETF_ITATBDATA0_REG(ETF_BASE_PTR)
#define ETF_ITATBCTR2 ETF_ITATBCTR2_REG(ETF_BASE_PTR)
#define ETF_ITATBCTR1 ETF_ITATBCTR1_REG(ETF_BASE_PTR)
#define ETF_ITATBCTR0 ETF_ITATBCTR0_REG(ETF_BASE_PTR)
#define ETF_ITCTRL ETF_ITCTRL_REG(ETF_BASE_PTR)
#define ETF_CLAIMSET ETF_CLAIMSET_REG(ETF_BASE_PTR)
#define ETF_CLAIMCLR ETF_CLAIMCLR_REG(ETF_BASE_PTR)
#define ETF_LAR ETF_LAR_REG(ETF_BASE_PTR)
#define ETF_LSR ETF_LSR_REG(ETF_BASE_PTR)
#define ETF_AUTHSTATUS ETF_AUTHSTATUS_REG(ETF_BASE_PTR)
#define ETF_DEVID ETF_DEVID_REG(ETF_BASE_PTR)
#define ETF_DEVTYPE ETF_DEVTYPE_REG(ETF_BASE_PTR)
#define ETF_PIDR4 ETF_PIDR4_REG(ETF_BASE_PTR)
#define ETF_PIDR5 ETF_PIDR5_REG(ETF_BASE_PTR)
#define ETF_PIDR6 ETF_PIDR6_REG(ETF_BASE_PTR)
#define ETF_PIDR7 ETF_PIDR7_REG(ETF_BASE_PTR)
#define ETF_PIDR0 ETF_PIDR0_REG(ETF_BASE_PTR)
#define ETF_PIDR1 ETF_PIDR1_REG(ETF_BASE_PTR)
#define ETF_PIDR2 ETF_PIDR2_REG(ETF_BASE_PTR)
#define ETF_PIDR3 ETF_PIDR3_REG(ETF_BASE_PTR)
#define ETF_CIDR0 ETF_CIDR0_REG(ETF_BASE_PTR)
#define ETF_CIDR1 ETF_CIDR1_REG(ETF_BASE_PTR)
#define ETF_CIDR2 ETF_CIDR2_REG(ETF_BASE_PTR)
#define ETF_CIDR3 ETF_CIDR3_REG(ETF_BASE_PTR)
/**
* @}
*/ /* end of group ETF_Register_Accessor_Macros */
/**
* @}
*/ /* end of group ETF_Peripheral */
/* ----------------------------------------------------------------------------
-- ETM
---------------------------------------------------------------------------- */
/**
* @addtogroup ETM_Peripheral ETM
* @{
*/
/** ETM - Peripheral register structure */
typedef struct ETM_MemMap {
uint32_t CR; /**< Main Control Register, offset: 0x0 */
uint32_t CCR; /**< Configuration Code Register, offset: 0x4 */
uint32_t TRIGGER; /**< Trigger Event Register, offset: 0x8 */
uint8_t RESERVED_0[4];
uint32_t SR; /**< ETM Status Register, offset: 0x10 */
uint32_t SCR; /**< System Configuration Register, offset: 0x14 */
uint8_t RESERVED_1[8];
uint32_t EEVR; /**< Trace Enable Event Register, offset: 0x20 */
uint32_t TECR1; /**< Trace Enable Control 1 Register, offset: 0x24 */
uint32_t FFLR; /**< FIFOFULL Level Register, offset: 0x28 */
uint8_t RESERVED_2[276];
uint32_t CNTRLDVR1; /**< Free-running counter reload value, offset: 0x140 */
uint8_t RESERVED_3[156];
uint32_t SYNCFR; /**< Synchronization Frequency Register, offset: 0x1E0 */
uint32_t IDR; /**< ID Register, offset: 0x1E4 */
uint32_t CCER; /**< Configuration Code Extension Register, offset: 0x1E8 */
uint8_t RESERVED_4[4];
uint32_t TESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register, offset: 0x1F0 */
uint8_t RESERVED_5[4];
uint32_t TSEVR; /**< Timestamp Event Register, offset: 0x1F8 */
uint8_t RESERVED_6[4];
uint32_t TRACEIDR; /**< CoreSight Trace ID Register, offset: 0x200 */
uint8_t RESERVED_7[4];
uint32_t IDR2; /**< ETM ID Register 2, offset: 0x208 */
uint8_t RESERVED_8[264];
uint32_t PDSR; /**< Device Power-Down Status Register, offset: 0x314 */
uint8_t RESERVED_9[3016];
uint32_t ITMISCIN; /**< Integration Test Miscelaneous Inputs Register, offset: 0xEE0 */
uint8_t RESERVED_10[4];
uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register, offset: 0xEE8 */
uint8_t RESERVED_11[4];
uint32_t ITATBCTR2; /**< ETM Integration Test ATB Control 2 Register, offset: 0xEF0 */
uint8_t RESERVED_12[4];
uint32_t ITATBCTR0; /**< ETM Integration Test ATB Control 0 Register, offset: 0xEF8 */
uint8_t RESERVED_13[4];
uint32_t ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */
uint8_t RESERVED_14[156];
uint32_t CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */
uint32_t CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */
uint8_t RESERVED_15[8];
uint32_t LAR; /**< Lock Access Register, offset: 0xFB0 */
uint32_t LSR; /**< Lock Status Register, offset: 0xFB4 */
uint32_t AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */
uint8_t RESERVED_16[16];
uint32_t DEVTYPE; /**< CoreSight Device Type Register, offset: 0xFCC */
uint32_t PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */
uint32_t PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */
uint32_t PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */
uint32_t PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */
uint32_t PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */
uint32_t PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */
uint32_t PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */
uint32_t PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */
uint32_t CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */
uint32_t CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */
uint32_t CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */
uint32_t CIDR3; /**< Component Identification Register 3, offset: 0xFFC */
} volatile *ETM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- ETM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup ETM_Register_Accessor_Macros ETM - Register accessor macros
* @{
*/
/* ETM - Register accessors */
#define ETM_CR_REG(base) ((base)->CR)
#define ETM_CCR_REG(base) ((base)->CCR)
#define ETM_TRIGGER_REG(base) ((base)->TRIGGER)
#define ETM_SR_REG(base) ((base)->SR)
#define ETM_SCR_REG(base) ((base)->SCR)
#define ETM_EEVR_REG(base) ((base)->EEVR)
#define ETM_TECR1_REG(base) ((base)->TECR1)
#define ETM_FFLR_REG(base) ((base)->FFLR)
#define ETM_CNTRLDVR1_REG(base) ((base)->CNTRLDVR1)
#define ETM_SYNCFR_REG(base) ((base)->SYNCFR)
#define ETM_IDR_REG(base) ((base)->IDR)
#define ETM_CCER_REG(base) ((base)->CCER)
#define ETM_TESSEICR_REG(base) ((base)->TESSEICR)
#define ETM_TSEVR_REG(base) ((base)->TSEVR)
#define ETM_TRACEIDR_REG(base) ((base)->TRACEIDR)
#define ETM_IDR2_REG(base) ((base)->IDR2)
#define ETM_PDSR_REG(base) ((base)->PDSR)
#define ETM_ITMISCIN_REG(base) ((base)->ITMISCIN)
#define ETM_ITTRIGOUT_REG(base) ((base)->ITTRIGOUT)
#define ETM_ITATBCTR2_REG(base) ((base)->ITATBCTR2)
#define ETM_ITATBCTR0_REG(base) ((base)->ITATBCTR0)
#define ETM_ITCTRL_REG(base) ((base)->ITCTRL)
#define ETM_CLAIMSET_REG(base) ((base)->CLAIMSET)
#define ETM_CLAIMCLR_REG(base) ((base)->CLAIMCLR)
#define ETM_LAR_REG(base) ((base)->LAR)
#define ETM_LSR_REG(base) ((base)->LSR)
#define ETM_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS)
#define ETM_DEVTYPE_REG(base) ((base)->DEVTYPE)
#define ETM_PIDR4_REG(base) ((base)->PIDR4)
#define ETM_PIDR5_REG(base) ((base)->PIDR5)
#define ETM_PIDR6_REG(base) ((base)->PIDR6)
#define ETM_PIDR7_REG(base) ((base)->PIDR7)
#define ETM_PIDR0_REG(base) ((base)->PIDR0)
#define ETM_PIDR1_REG(base) ((base)->PIDR1)
#define ETM_PIDR2_REG(base) ((base)->PIDR2)
#define ETM_PIDR3_REG(base) ((base)->PIDR3)
#define ETM_CIDR0_REG(base) ((base)->CIDR0)
#define ETM_CIDR1_REG(base) ((base)->CIDR1)
#define ETM_CIDR2_REG(base) ((base)->CIDR2)
#define ETM_CIDR3_REG(base) ((base)->CIDR3)
/**
* @}
*/ /* end of group ETM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- ETM Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup ETM_Register_Masks ETM Register Masks
* @{
*/
/**
* @}
*/ /* end of group ETM_Register_Masks */
/* ETM - Peripheral instance base addresses */
/** Peripheral ETM base pointer */
#define ETM_BASE_PTR ((ETM_MemMapPtr)0xE0041000u)
/* ----------------------------------------------------------------------------
-- ETM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup ETM_Register_Accessor_Macros ETM - Register accessor macros
* @{
*/
/* ETM - Register instance definitions */
/* ETM */
#define ETMCR ETM_CR_REG(ETM_BASE_PTR)
#define ETMCCR ETM_CCR_REG(ETM_BASE_PTR)
#define ETMTRIGGER ETM_TRIGGER_REG(ETM_BASE_PTR)
#define ETMSR ETM_SR_REG(ETM_BASE_PTR)
#define ETMSCR ETM_SCR_REG(ETM_BASE_PTR)
#define ETMEEVR ETM_EEVR_REG(ETM_BASE_PTR)
#define ETMTECR1 ETM_TECR1_REG(ETM_BASE_PTR)
#define ETMFFLR ETM_FFLR_REG(ETM_BASE_PTR)
#define ETMCNTRLDVR1 ETM_CNTRLDVR1_REG(ETM_BASE_PTR)
#define ETMSYNCFR ETM_SYNCFR_REG(ETM_BASE_PTR)
#define ETMIDR ETM_IDR_REG(ETM_BASE_PTR)
#define ETMCCER ETM_CCER_REG(ETM_BASE_PTR)
#define ETMTESSEICR ETM_TESSEICR_REG(ETM_BASE_PTR)
#define ETMTSEVR ETM_TSEVR_REG(ETM_BASE_PTR)
#define ETMTRACEIDR ETM_TRACEIDR_REG(ETM_BASE_PTR)
#define ETMIDR2 ETM_IDR2_REG(ETM_BASE_PTR)
#define ETMPDSR ETM_PDSR_REG(ETM_BASE_PTR)
#define ETM_ITMISCIN ETM_ITMISCIN_REG(ETM_BASE_PTR)
#define ETM_ITTRIGOUT ETM_ITTRIGOUT_REG(ETM_BASE_PTR)
#define ETM_ITATBCTR2 ETM_ITATBCTR2_REG(ETM_BASE_PTR)
#define ETM_ITATBCTR0 ETM_ITATBCTR0_REG(ETM_BASE_PTR)
#define ETMITCTRL ETM_ITCTRL_REG(ETM_BASE_PTR)
#define ETMCLAIMSET ETM_CLAIMSET_REG(ETM_BASE_PTR)
#define ETMCLAIMCLR ETM_CLAIMCLR_REG(ETM_BASE_PTR)
#define ETMLAR ETM_LAR_REG(ETM_BASE_PTR)
#define ETMLSR ETM_LSR_REG(ETM_BASE_PTR)
#define ETMAUTHSTATUS ETM_AUTHSTATUS_REG(ETM_BASE_PTR)
#define ETMDEVTYPE ETM_DEVTYPE_REG(ETM_BASE_PTR)
#define ETMPIDR4 ETM_PIDR4_REG(ETM_BASE_PTR)
#define ETMPIDR5 ETM_PIDR5_REG(ETM_BASE_PTR)
#define ETMPIDR6 ETM_PIDR6_REG(ETM_BASE_PTR)
#define ETMPIDR7 ETM_PIDR7_REG(ETM_BASE_PTR)
#define ETMPIDR0 ETM_PIDR0_REG(ETM_BASE_PTR)
#define ETMPIDR1 ETM_PIDR1_REG(ETM_BASE_PTR)
#define ETMPIDR2 ETM_PIDR2_REG(ETM_BASE_PTR)
#define ETMPIDR3 ETM_PIDR3_REG(ETM_BASE_PTR)
#define ETMCIDR0 ETM_CIDR0_REG(ETM_BASE_PTR)
#define ETMCIDR1 ETM_CIDR1_REG(ETM_BASE_PTR)
#define ETMCIDR2 ETM_CIDR2_REG(ETM_BASE_PTR)
#define ETMCIDR3 ETM_CIDR3_REG(ETM_BASE_PTR)
/**
* @}
*/ /* end of group ETM_Register_Accessor_Macros */
/**
* @}
*/ /* end of group ETM_Peripheral */
/* ----------------------------------------------------------------------------
-- EWM
---------------------------------------------------------------------------- */
/**
* @addtogroup EWM_Peripheral EWM
* @{
*/
/** EWM - Peripheral register structure */
typedef struct EWM_MemMap {
uint8_t CTRL; /**< Control Register, offset: 0x0 */
uint8_t SERV; /**< Service Register, offset: 0x1 */
uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
} volatile *EWM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- EWM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
* @{
*/
/* EWM - Register accessors */
#define EWM_CTRL_REG(base) ((base)->CTRL)
#define EWM_SERV_REG(base) ((base)->SERV)
#define EWM_CMPL_REG(base) ((base)->CMPL)
#define EWM_CMPH_REG(base) ((base)->CMPH)
/**
* @}
*/ /* end of group EWM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- EWM Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup EWM_Register_Masks EWM Register Masks
* @{
*/
/* CTRL Bit Fields */
#define EWM_CTRL_EWMEN_MASK 0x1u
#define EWM_CTRL_EWMEN_SHIFT 0
#define EWM_CTRL_ASSIN_MASK 0x2u
#define EWM_CTRL_ASSIN_SHIFT 1
#define EWM_CTRL_INEN_MASK 0x4u
#define EWM_CTRL_INEN_SHIFT 2
/* SERV Bit Fields */
#define EWM_SERV_SERVICE_MASK 0xFFu
#define EWM_SERV_SERVICE_SHIFT 0
#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
/* CMPL Bit Fields */
#define EWM_CMPL_COMPAREL_MASK 0xFFu
#define EWM_CMPL_COMPAREL_SHIFT 0
#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
/* CMPH Bit Fields */
#define EWM_CMPH_COMPAREH_MASK 0xFFu
#define EWM_CMPH_COMPAREH_SHIFT 0
#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
/**
* @}
*/ /* end of group EWM_Register_Masks */
/* EWM - Peripheral instance base addresses */
/** Peripheral EWM base pointer */
#define EWM_BASE_PTR ((EWM_MemMapPtr)0x40061000u)
/* ----------------------------------------------------------------------------
-- EWM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
* @{
*/
/* EWM - Register instance definitions */
/* EWM */
#define EWM_CTRL EWM_CTRL_REG(EWM_BASE_PTR)
#define EWM_SERV EWM_SERV_REG(EWM_BASE_PTR)
#define EWM_CMPL EWM_CMPL_REG(EWM_BASE_PTR)
#define EWM_CMPH EWM_CMPH_REG(EWM_BASE_PTR)
/**
* @}
*/ /* end of group EWM_Register_Accessor_Macros */
/**
* @}
*/ /* end of group EWM_Peripheral */
/* ----------------------------------------------------------------------------
-- FB
---------------------------------------------------------------------------- */
/**
* @addtogroup FB_Peripheral FB
* @{
*/
/** FB - Peripheral register structure */
typedef struct FB_MemMap {
struct { /* offset: 0x0, array step: 0xC */
uint32_t CSAR; /**< Chip select address register, array offset: 0x0, array step: 0xC */
uint32_t CSMR; /**< Chip select mask register, array offset: 0x4, array step: 0xC */
uint32_t CSCR; /**< Chip select control register, array offset: 0x8, array step: 0xC */
} CS[6];
uint8_t RESERVED_0[24];
uint32_t CSPMCR; /**< Chip select port multiplexing control register, offset: 0x60 */
} volatile *FB_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
* @{
*/
/* FB - Register accessors */
#define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
#define FB_CSPMCR_REG(base) ((base)->CSPMCR)
/**
* @}
*/ /* end of group FB_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FB Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup FB_Register_Masks FB Register Masks
* @{
*/
/* CSAR Bit Fields */
#define FB_CSAR_BA_MASK 0xFFFF0000u
#define FB_CSAR_BA_SHIFT 16
#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
/* CSMR Bit Fields */
#define FB_CSMR_V_MASK 0x1u
#define FB_CSMR_V_SHIFT 0
#define FB_CSMR_WP_MASK 0x100u
#define FB_CSMR_WP_SHIFT 8
#define FB_CSMR_BAM_MASK 0xFFFF0000u
#define FB_CSMR_BAM_SHIFT 16
#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
/* CSCR Bit Fields */
#define FB_CSCR_BSTW_MASK 0x8u
#define FB_CSCR_BSTW_SHIFT 3
#define FB_CSCR_BSTR_MASK 0x10u
#define FB_CSCR_BSTR_SHIFT 4
#define FB_CSCR_BEM_MASK 0x20u
#define FB_CSCR_BEM_SHIFT 5
#define FB_CSCR_PS_MASK 0xC0u
#define FB_CSCR_PS_SHIFT 6
#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
#define FB_CSCR_AA_MASK 0x100u
#define FB_CSCR_AA_SHIFT 8
#define FB_CSCR_BLS_MASK 0x200u
#define FB_CSCR_BLS_SHIFT 9
#define FB_CSCR_WS_MASK 0xFC00u
#define FB_CSCR_WS_SHIFT 10
#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
#define FB_CSCR_WRAH_MASK 0x30000u
#define FB_CSCR_WRAH_SHIFT 16
#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
#define FB_CSCR_RDAH_MASK 0xC0000u
#define FB_CSCR_RDAH_SHIFT 18
#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
#define FB_CSCR_ASET_MASK 0x300000u
#define FB_CSCR_ASET_SHIFT 20
#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
#define FB_CSCR_EXTS_MASK 0x400000u
#define FB_CSCR_EXTS_SHIFT 22
#define FB_CSCR_SWSEN_MASK 0x800000u
#define FB_CSCR_SWSEN_SHIFT 23
#define FB_CSCR_SWS_MASK 0xFC000000u
#define FB_CSCR_SWS_SHIFT 26
#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
/* CSPMCR Bit Fields */
#define FB_CSPMCR_GROUP5_MASK 0xF000u
#define FB_CSPMCR_GROUP5_SHIFT 12
#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
#define FB_CSPMCR_GROUP4_MASK 0xF0000u
#define FB_CSPMCR_GROUP4_SHIFT 16
#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
#define FB_CSPMCR_GROUP3_MASK 0xF00000u
#define FB_CSPMCR_GROUP3_SHIFT 20
#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
#define FB_CSPMCR_GROUP2_MASK 0xF000000u
#define FB_CSPMCR_GROUP2_SHIFT 24
#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
#define FB_CSPMCR_GROUP1_MASK 0xF0000000u
#define FB_CSPMCR_GROUP1_SHIFT 28
#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
/**
* @}
*/ /* end of group FB_Register_Masks */
/* FB - Peripheral instance base addresses */
/** Peripheral FB base pointer */
#define FB_BASE_PTR ((FB_MemMapPtr)0x4000C000u)
/* ----------------------------------------------------------------------------
-- FB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
* @{
*/
/* FB - Register instance definitions */
/* FB */
#define FB_CSAR0 FB_CSAR_REG(FB_BASE_PTR,0)
#define FB_CSMR0 FB_CSMR_REG(FB_BASE_PTR,0)
#define FB_CSCR0 FB_CSCR_REG(FB_BASE_PTR,0)
#define FB_CSAR1 FB_CSAR_REG(FB_BASE_PTR,1)
#define FB_CSMR1 FB_CSMR_REG(FB_BASE_PTR,1)
#define FB_CSCR1 FB_CSCR_REG(FB_BASE_PTR,1)
#define FB_CSAR2 FB_CSAR_REG(FB_BASE_PTR,2)
#define FB_CSMR2 FB_CSMR_REG(FB_BASE_PTR,2)
#define FB_CSCR2 FB_CSCR_REG(FB_BASE_PTR,2)
#define FB_CSAR3 FB_CSAR_REG(FB_BASE_PTR,3)
#define FB_CSMR3 FB_CSMR_REG(FB_BASE_PTR,3)
#define FB_CSCR3 FB_CSCR_REG(FB_BASE_PTR,3)
#define FB_CSAR4 FB_CSAR_REG(FB_BASE_PTR,4)
#define FB_CSMR4 FB_CSMR_REG(FB_BASE_PTR,4)
#define FB_CSCR4 FB_CSCR_REG(FB_BASE_PTR,4)
#define FB_CSAR5 FB_CSAR_REG(FB_BASE_PTR,5)
#define FB_CSMR5 FB_CSMR_REG(FB_BASE_PTR,5)
#define FB_CSCR5 FB_CSCR_REG(FB_BASE_PTR,5)
#define FB_CSPMCR FB_CSPMCR_REG(FB_BASE_PTR)
/* FB - Register array accessors */
#define FB_CSAR(index) FB_CSAR_REG(FB_BASE_PTR,index)
#define FB_CSMR(index) FB_CSMR_REG(FB_BASE_PTR,index)
#define FB_CSCR(index) FB_CSCR_REG(FB_BASE_PTR,index)
/**
* @}
*/ /* end of group FB_Register_Accessor_Macros */
/**
* @}
*/ /* end of group FB_Peripheral */
/* ----------------------------------------------------------------------------
-- FMC
---------------------------------------------------------------------------- */
/**
* @addtogroup FMC_Peripheral FMC
* @{
*/
/** FMC - Peripheral register structure */
typedef struct FMC_MemMap {
uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
uint8_t RESERVED_0[244];
uint32_t TAGVD[4][8]; /**< Cache Directory Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
uint8_t RESERVED_1[128];
struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
} SET[4][8];
} volatile *FMC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FMC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
* @{
*/
/* FMC - Register accessors */
#define FMC_PFAPR_REG(base) ((base)->PFAPR)
#define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
#define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
#define FMC_TAGVD_REG(base,index,index2) ((base)->TAGVD[index][index2])
#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
/**
* @}
*/ /* end of group FMC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FMC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup FMC_Register_Masks FMC Register Masks
* @{
*/
/* PFAPR Bit Fields */
#define FMC_PFAPR_M0AP_MASK 0x3u
#define FMC_PFAPR_M0AP_SHIFT 0
#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
#define FMC_PFAPR_M1AP_MASK 0xCu
#define FMC_PFAPR_M1AP_SHIFT 2
#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
#define FMC_PFAPR_M2AP_MASK 0x30u
#define FMC_PFAPR_M2AP_SHIFT 4
#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
#define FMC_PFAPR_M3AP_MASK 0xC0u
#define FMC_PFAPR_M3AP_SHIFT 6
#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
#define FMC_PFAPR_M4AP_MASK 0x300u
#define FMC_PFAPR_M4AP_SHIFT 8
#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
#define FMC_PFAPR_M5AP_MASK 0xC00u
#define FMC_PFAPR_M5AP_SHIFT 10
#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
#define FMC_PFAPR_M6AP_MASK 0x3000u
#define FMC_PFAPR_M6AP_SHIFT 12
#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
#define FMC_PFAPR_M7AP_MASK 0xC000u
#define FMC_PFAPR_M7AP_SHIFT 14
#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
#define FMC_PFAPR_M0PFD_MASK 0x10000u
#define FMC_PFAPR_M0PFD_SHIFT 16
#define FMC_PFAPR_M1PFD_MASK 0x20000u
#define FMC_PFAPR_M1PFD_SHIFT 17
#define FMC_PFAPR_M2PFD_MASK 0x40000u
#define FMC_PFAPR_M2PFD_SHIFT 18
#define FMC_PFAPR_M3PFD_MASK 0x80000u
#define FMC_PFAPR_M3PFD_SHIFT 19
#define FMC_PFAPR_M4PFD_MASK 0x100000u
#define FMC_PFAPR_M4PFD_SHIFT 20
#define FMC_PFAPR_M5PFD_MASK 0x200000u
#define FMC_PFAPR_M5PFD_SHIFT 21
#define FMC_PFAPR_M6PFD_MASK 0x400000u
#define FMC_PFAPR_M6PFD_SHIFT 22
#define FMC_PFAPR_M7PFD_MASK 0x800000u
#define FMC_PFAPR_M7PFD_SHIFT 23
/* PFB0CR Bit Fields */
#define FMC_PFB0CR_B0SEBE_MASK 0x1u
#define FMC_PFB0CR_B0SEBE_SHIFT 0
#define FMC_PFB0CR_B0IPE_MASK 0x2u
#define FMC_PFB0CR_B0IPE_SHIFT 1
#define FMC_PFB0CR_B0DPE_MASK 0x4u
#define FMC_PFB0CR_B0DPE_SHIFT 2
#define FMC_PFB0CR_B0ICE_MASK 0x8u
#define FMC_PFB0CR_B0ICE_SHIFT 3
#define FMC_PFB0CR_B0DCE_MASK 0x10u
#define FMC_PFB0CR_B0DCE_SHIFT 4
#define FMC_PFB0CR_CRC_MASK 0xE0u
#define FMC_PFB0CR_CRC_SHIFT 5
#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
#define FMC_PFB0CR_B0MW_MASK 0x60000u
#define FMC_PFB0CR_B0MW_SHIFT 17
#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
#define FMC_PFB0CR_S_B_INV_SHIFT 19
#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
#define FMC_PFB0CR_CINV_WAY_SHIFT 20
#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
#define FMC_PFB0CR_B0RWSC_SHIFT 28
#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
/* PFB1CR Bit Fields */
#define FMC_PFB1CR_B1SEBE_MASK 0x1u
#define FMC_PFB1CR_B1SEBE_SHIFT 0
#define FMC_PFB1CR_B1IPE_MASK 0x2u
#define FMC_PFB1CR_B1IPE_SHIFT 1
#define FMC_PFB1CR_B1DPE_MASK 0x4u
#define FMC_PFB1CR_B1DPE_SHIFT 2
#define FMC_PFB1CR_B1ICE_MASK 0x8u
#define FMC_PFB1CR_B1ICE_SHIFT 3
#define FMC_PFB1CR_B1DCE_MASK 0x10u
#define FMC_PFB1CR_B1DCE_SHIFT 4
#define FMC_PFB1CR_B1MW_MASK 0x60000u
#define FMC_PFB1CR_B1MW_SHIFT 17
#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
#define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
#define FMC_PFB1CR_B1RWSC_SHIFT 28
#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
/* TAGVD Bit Fields */
#define FMC_TAGVD_valid_MASK 0x1u
#define FMC_TAGVD_valid_SHIFT 0
#define FMC_TAGVD_tag_MASK 0x7FFC0u
#define FMC_TAGVD_tag_SHIFT 6
#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
/* DATA_U Bit Fields */
#define FMC_DATA_U_data_MASK 0xFFFFFFFFu
#define FMC_DATA_U_data_SHIFT 0
#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
/* DATA_L Bit Fields */
#define FMC_DATA_L_data_MASK 0xFFFFFFFFu
#define FMC_DATA_L_data_SHIFT 0
#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
/**
* @}
*/ /* end of group FMC_Register_Masks */
/* FMC - Peripheral instance base addresses */
/** Peripheral FMC base pointer */
#define FMC_BASE_PTR ((FMC_MemMapPtr)0x4001F000u)
/* ----------------------------------------------------------------------------
-- FMC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
* @{
*/
/* FMC - Register instance definitions */
/* FMC */
#define FMC_PFAPR FMC_PFAPR_REG(FMC_BASE_PTR)
#define FMC_PFB0CR FMC_PFB0CR_REG(FMC_BASE_PTR)
#define FMC_PFB1CR FMC_PFB1CR_REG(FMC_BASE_PTR)
#define FMC_TAGVDW0S0 FMC_TAGVD_REG(FMC_BASE_PTR,0,0)
#define FMC_TAGVDW0S1 FMC_TAGVD_REG(FMC_BASE_PTR,0,1)
#define FMC_TAGVDW0S2 FMC_TAGVD_REG(FMC_BASE_PTR,0,2)
#define FMC_TAGVDW0S3 FMC_TAGVD_REG(FMC_BASE_PTR,0,3)
#define FMC_TAGVDW0S4 FMC_TAGVD_REG(FMC_BASE_PTR,0,4)
#define FMC_TAGVDW0S5 FMC_TAGVD_REG(FMC_BASE_PTR,0,5)
#define FMC_TAGVDW0S6 FMC_TAGVD_REG(FMC_BASE_PTR,0,6)
#define FMC_TAGVDW0S7 FMC_TAGVD_REG(FMC_BASE_PTR,0,7)
#define FMC_TAGVDW1S0 FMC_TAGVD_REG(FMC_BASE_PTR,1,0)
#define FMC_TAGVDW1S1 FMC_TAGVD_REG(FMC_BASE_PTR,1,1)
#define FMC_TAGVDW1S2 FMC_TAGVD_REG(FMC_BASE_PTR,1,2)
#define FMC_TAGVDW1S3 FMC_TAGVD_REG(FMC_BASE_PTR,1,3)
#define FMC_TAGVDW1S4 FMC_TAGVD_REG(FMC_BASE_PTR,1,4)
#define FMC_TAGVDW1S5 FMC_TAGVD_REG(FMC_BASE_PTR,1,5)
#define FMC_TAGVDW1S6 FMC_TAGVD_REG(FMC_BASE_PTR,1,6)
#define FMC_TAGVDW1S7 FMC_TAGVD_REG(FMC_BASE_PTR,1,7)
#define FMC_TAGVDW2S0 FMC_TAGVD_REG(FMC_BASE_PTR,2,0)
#define FMC_TAGVDW2S1 FMC_TAGVD_REG(FMC_BASE_PTR,2,1)
#define FMC_TAGVDW2S2 FMC_TAGVD_REG(FMC_BASE_PTR,2,2)
#define FMC_TAGVDW2S3 FMC_TAGVD_REG(FMC_BASE_PTR,2,3)
#define FMC_TAGVDW2S4 FMC_TAGVD_REG(FMC_BASE_PTR,2,4)
#define FMC_TAGVDW2S5 FMC_TAGVD_REG(FMC_BASE_PTR,2,5)
#define FMC_TAGVDW2S6 FMC_TAGVD_REG(FMC_BASE_PTR,2,6)
#define FMC_TAGVDW2S7 FMC_TAGVD_REG(FMC_BASE_PTR,2,7)
#define FMC_TAGVDW3S0 FMC_TAGVD_REG(FMC_BASE_PTR,3,0)
#define FMC_TAGVDW3S1 FMC_TAGVD_REG(FMC_BASE_PTR,3,1)
#define FMC_TAGVDW3S2 FMC_TAGVD_REG(FMC_BASE_PTR,3,2)
#define FMC_TAGVDW3S3 FMC_TAGVD_REG(FMC_BASE_PTR,3,3)
#define FMC_TAGVDW3S4 FMC_TAGVD_REG(FMC_BASE_PTR,3,4)
#define FMC_TAGVDW3S5 FMC_TAGVD_REG(FMC_BASE_PTR,3,5)
#define FMC_TAGVDW3S6 FMC_TAGVD_REG(FMC_BASE_PTR,3,6)
#define FMC_TAGVDW3S7 FMC_TAGVD_REG(FMC_BASE_PTR,3,7)
#define FMC_DATAW0S0U FMC_DATA_U_REG(FMC_BASE_PTR,0,0)
#define FMC_DATAW0S0L FMC_DATA_L_REG(FMC_BASE_PTR,0,0)
#define FMC_DATAW0S1U FMC_DATA_U_REG(FMC_BASE_PTR,0,1)
#define FMC_DATAW0S1L FMC_DATA_L_REG(FMC_BASE_PTR,0,1)
#define FMC_DATAW0S2U FMC_DATA_U_REG(FMC_BASE_PTR,0,2)
#define FMC_DATAW0S2L FMC_DATA_L_REG(FMC_BASE_PTR,0,2)
#define FMC_DATAW0S3U FMC_DATA_U_REG(FMC_BASE_PTR,0,3)
#define FMC_DATAW0S3L FMC_DATA_L_REG(FMC_BASE_PTR,0,3)
#define FMC_DATAW0S4U FMC_DATA_U_REG(FMC_BASE_PTR,0,4)
#define FMC_DATAW0S4L FMC_DATA_L_REG(FMC_BASE_PTR,0,4)
#define FMC_DATAW0S5U FMC_DATA_U_REG(FMC_BASE_PTR,0,5)
#define FMC_DATAW0S5L FMC_DATA_L_REG(FMC_BASE_PTR,0,5)
#define FMC_DATAW0S6U FMC_DATA_U_REG(FMC_BASE_PTR,0,6)
#define FMC_DATAW0S6L FMC_DATA_L_REG(FMC_BASE_PTR,0,6)
#define FMC_DATAW0S7U FMC_DATA_U_REG(FMC_BASE_PTR,0,7)
#define FMC_DATAW0S7L FMC_DATA_L_REG(FMC_BASE_PTR,0,7)
#define FMC_DATAW1S0U FMC_DATA_U_REG(FMC_BASE_PTR,1,0)
#define FMC_DATAW1S0L FMC_DATA_L_REG(FMC_BASE_PTR,1,0)
#define FMC_DATAW1S1U FMC_DATA_U_REG(FMC_BASE_PTR,1,1)
#define FMC_DATAW1S1L FMC_DATA_L_REG(FMC_BASE_PTR,1,1)
#define FMC_DATAW1S2U FMC_DATA_U_REG(FMC_BASE_PTR,1,2)
#define FMC_DATAW1S2L FMC_DATA_L_REG(FMC_BASE_PTR,1,2)
#define FMC_DATAW1S3U FMC_DATA_U_REG(FMC_BASE_PTR,1,3)
#define FMC_DATAW1S3L FMC_DATA_L_REG(FMC_BASE_PTR,1,3)
#define FMC_DATAW1S4U FMC_DATA_U_REG(FMC_BASE_PTR,1,4)
#define FMC_DATAW1S4L FMC_DATA_L_REG(FMC_BASE_PTR,1,4)
#define FMC_DATAW1S5U FMC_DATA_U_REG(FMC_BASE_PTR,1,5)
#define FMC_DATAW1S5L FMC_DATA_L_REG(FMC_BASE_PTR,1,5)
#define FMC_DATAW1S6U FMC_DATA_U_REG(FMC_BASE_PTR,1,6)
#define FMC_DATAW1S6L FMC_DATA_L_REG(FMC_BASE_PTR,1,6)
#define FMC_DATAW1S7U FMC_DATA_U_REG(FMC_BASE_PTR,1,7)
#define FMC_DATAW1S7L FMC_DATA_L_REG(FMC_BASE_PTR,1,7)
#define FMC_DATAW2S0U FMC_DATA_U_REG(FMC_BASE_PTR,2,0)
#define FMC_DATAW2S0L FMC_DATA_L_REG(FMC_BASE_PTR,2,0)
#define FMC_DATAW2S1U FMC_DATA_U_REG(FMC_BASE_PTR,2,1)
#define FMC_DATAW2S1L FMC_DATA_L_REG(FMC_BASE_PTR,2,1)
#define FMC_DATAW2S2U FMC_DATA_U_REG(FMC_BASE_PTR,2,2)
#define FMC_DATAW2S2L FMC_DATA_L_REG(FMC_BASE_PTR,2,2)
#define FMC_DATAW2S3U FMC_DATA_U_REG(FMC_BASE_PTR,2,3)
#define FMC_DATAW2S3L FMC_DATA_L_REG(FMC_BASE_PTR,2,3)
#define FMC_DATAW2S4U FMC_DATA_U_REG(FMC_BASE_PTR,2,4)
#define FMC_DATAW2S4L FMC_DATA_L_REG(FMC_BASE_PTR,2,4)
#define FMC_DATAW2S5U FMC_DATA_U_REG(FMC_BASE_PTR,2,5)
#define FMC_DATAW2S5L FMC_DATA_L_REG(FMC_BASE_PTR,2,5)
#define FMC_DATAW2S6U FMC_DATA_U_REG(FMC_BASE_PTR,2,6)
#define FMC_DATAW2S6L FMC_DATA_L_REG(FMC_BASE_PTR,2,6)
#define FMC_DATAW2S7U FMC_DATA_U_REG(FMC_BASE_PTR,2,7)
#define FMC_DATAW2S7L FMC_DATA_L_REG(FMC_BASE_PTR,2,7)
#define FMC_DATAW3S0U FMC_DATA_U_REG(FMC_BASE_PTR,3,0)
#define FMC_DATAW3S0L FMC_DATA_L_REG(FMC_BASE_PTR,3,0)
#define FMC_DATAW3S1U FMC_DATA_U_REG(FMC_BASE_PTR,3,1)
#define FMC_DATAW3S1L FMC_DATA_L_REG(FMC_BASE_PTR,3,1)
#define FMC_DATAW3S2U FMC_DATA_U_REG(FMC_BASE_PTR,3,2)
#define FMC_DATAW3S2L FMC_DATA_L_REG(FMC_BASE_PTR,3,2)
#define FMC_DATAW3S3U FMC_DATA_U_REG(FMC_BASE_PTR,3,3)
#define FMC_DATAW3S3L FMC_DATA_L_REG(FMC_BASE_PTR,3,3)
#define FMC_DATAW3S4U FMC_DATA_U_REG(FMC_BASE_PTR,3,4)
#define FMC_DATAW3S4L FMC_DATA_L_REG(FMC_BASE_PTR,3,4)
#define FMC_DATAW3S5U FMC_DATA_U_REG(FMC_BASE_PTR,3,5)
#define FMC_DATAW3S5L FMC_DATA_L_REG(FMC_BASE_PTR,3,5)
#define FMC_DATAW3S6U FMC_DATA_U_REG(FMC_BASE_PTR,3,6)
#define FMC_DATAW3S6L FMC_DATA_L_REG(FMC_BASE_PTR,3,6)
#define FMC_DATAW3S7U FMC_DATA_U_REG(FMC_BASE_PTR,3,7)
#define FMC_DATAW3S7L FMC_DATA_L_REG(FMC_BASE_PTR,3,7)
/* FMC - Register array accessors */
#define FMC_TAGVD(index,index2) FMC_TAGVD_REG(FMC_BASE_PTR,index,index2)
#define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC_BASE_PTR,index,index2)
#define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC_BASE_PTR,index,index2)
/**
* @}
*/ /* end of group FMC_Register_Accessor_Macros */
/**
* @}
*/ /* end of group FMC_Peripheral */
/* ----------------------------------------------------------------------------
-- FPB
---------------------------------------------------------------------------- */
/**
* @addtogroup FPB_Peripheral FPB
* @{
*/
/** FPB - Peripheral register structure */
typedef struct FPB_MemMap {
uint32_t CTRL; /**< FlashPatch Control Register, offset: 0x0 */
uint32_t REMAP; /**< FlashPatch Remap Register, offset: 0x4 */
uint32_t COMP[8]; /**< FlashPatch Comparator Register 0..FlashPatch Comparator Register 7, array offset: 0x8, array step: 0x4 */
uint8_t RESERVED_0[4008];
uint32_t PID4; /**< Peripheral Identification Register 4., offset: 0xFD0 */
uint32_t PID5; /**< Peripheral Identification Register 5., offset: 0xFD4 */
uint32_t PID6; /**< Peripheral Identification Register 6., offset: 0xFD8 */
uint32_t PID7; /**< Peripheral Identification Register 7., offset: 0xFDC */
uint32_t PID0; /**< Peripheral Identification Register 0., offset: 0xFE0 */
uint32_t PID1; /**< Peripheral Identification Register 1., offset: 0xFE4 */
uint32_t PID2; /**< Peripheral Identification Register 2., offset: 0xFE8 */
uint32_t PID3; /**< Peripheral Identification Register 3., offset: 0xFEC */
uint32_t CID0; /**< Component Identification Register 0., offset: 0xFF0 */
uint32_t CID1; /**< Component Identification Register 1., offset: 0xFF4 */
uint32_t CID2; /**< Component Identification Register 2., offset: 0xFF8 */
uint32_t CID3; /**< Component Identification Register 3., offset: 0xFFC */
} volatile *FPB_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FPB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup FPB_Register_Accessor_Macros FPB - Register accessor macros
* @{
*/
/* FPB - Register accessors */
#define FPB_CTRL_REG(base) ((base)->CTRL)
#define FPB_REMAP_REG(base) ((base)->REMAP)
#define FPB_COMP_REG(base,index) ((base)->COMP[index])
#define FPB_PID4_REG(base) ((base)->PID4)
#define FPB_PID5_REG(base) ((base)->PID5)
#define FPB_PID6_REG(base) ((base)->PID6)
#define FPB_PID7_REG(base) ((base)->PID7)
#define FPB_PID0_REG(base) ((base)->PID0)
#define FPB_PID1_REG(base) ((base)->PID1)
#define FPB_PID2_REG(base) ((base)->PID2)
#define FPB_PID3_REG(base) ((base)->PID3)
#define FPB_CID0_REG(base) ((base)->CID0)
#define FPB_CID1_REG(base) ((base)->CID1)
#define FPB_CID2_REG(base) ((base)->CID2)
#define FPB_CID3_REG(base) ((base)->CID3)
/**
* @}
*/ /* end of group FPB_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FPB Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup FPB_Register_Masks FPB Register Masks
* @{
*/
/**
* @}
*/ /* end of group FPB_Register_Masks */
/* FPB - Peripheral instance base addresses */
/** Peripheral FPB base pointer */
#define FPB_BASE_PTR ((FPB_MemMapPtr)0xE0002000u)
/* ----------------------------------------------------------------------------
-- FPB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup FPB_Register_Accessor_Macros FPB - Register accessor macros
* @{
*/
/* FPB - Register instance definitions */
/* FPB */
#define FP_CTRL FPB_CTRL_REG(FPB_BASE_PTR)
#define FP_REMAP FPB_REMAP_REG(FPB_BASE_PTR)
#define FP_COMP0 FPB_COMP_REG(FPB_BASE_PTR,0)
#define FP_COMP1 FPB_COMP_REG(FPB_BASE_PTR,1)
#define FP_COMP2 FPB_COMP_REG(FPB_BASE_PTR,2)
#define FP_COMP3 FPB_COMP_REG(FPB_BASE_PTR,3)
#define FP_COMP4 FPB_COMP_REG(FPB_BASE_PTR,4)
#define FP_COMP5 FPB_COMP_REG(FPB_BASE_PTR,5)
#define FP_COMP6 FPB_COMP_REG(FPB_BASE_PTR,6)
#define FP_COMP7 FPB_COMP_REG(FPB_BASE_PTR,7)
#define FP_PID4 FPB_PID4_REG(FPB_BASE_PTR)
#define FP_PID5 FPB_PID5_REG(FPB_BASE_PTR)
#define FP_PID6 FPB_PID6_REG(FPB_BASE_PTR)
#define FP_PID7 FPB_PID7_REG(FPB_BASE_PTR)
#define FP_PID0 FPB_PID0_REG(FPB_BASE_PTR)
#define FP_PID1 FPB_PID1_REG(FPB_BASE_PTR)
#define FP_PID2 FPB_PID2_REG(FPB_BASE_PTR)
#define FP_PID3 FPB_PID3_REG(FPB_BASE_PTR)
#define FP_CID0 FPB_CID0_REG(FPB_BASE_PTR)
#define FP_CID1 FPB_CID1_REG(FPB_BASE_PTR)
#define FP_CID2 FPB_CID2_REG(FPB_BASE_PTR)
#define FP_CID3 FPB_CID3_REG(FPB_BASE_PTR)
/* FPB - Register array accessors */
#define FPB_COMP(index) FPB_COMP_REG(FPB_BASE_PTR,index)
/**
* @}
*/ /* end of group FPB_Register_Accessor_Macros */
/**
* @}
*/ /* end of group FPB_Peripheral */
/* ----------------------------------------------------------------------------
-- FTFL
---------------------------------------------------------------------------- */
/**
* @addtogroup FTFL_Peripheral FTFL
* @{
*/
/** FTFL - Peripheral register structure */
typedef struct FTFL_MemMap {
uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
uint8_t RESERVED_0[2];
uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
} volatile *FTFL_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FTFL - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup FTFL_Register_Accessor_Macros FTFL - Register accessor macros
* @{
*/
/* FTFL - Register accessors */
#define FTFL_FSTAT_REG(base) ((base)->FSTAT)
#define FTFL_FCNFG_REG(base) ((base)->FCNFG)
#define FTFL_FSEC_REG(base) ((base)->FSEC)
#define FTFL_FOPT_REG(base) ((base)->FOPT)
#define FTFL_FCCOB3_REG(base) ((base)->FCCOB3)
#define FTFL_FCCOB2_REG(base) ((base)->FCCOB2)
#define FTFL_FCCOB1_REG(base) ((base)->FCCOB1)
#define FTFL_FCCOB0_REG(base) ((base)->FCCOB0)
#define FTFL_FCCOB7_REG(base) ((base)->FCCOB7)
#define FTFL_FCCOB6_REG(base) ((base)->FCCOB6)
#define FTFL_FCCOB5_REG(base) ((base)->FCCOB5)
#define FTFL_FCCOB4_REG(base) ((base)->FCCOB4)
#define FTFL_FCCOBB_REG(base) ((base)->FCCOBB)
#define FTFL_FCCOBA_REG(base) ((base)->FCCOBA)
#define FTFL_FCCOB9_REG(base) ((base)->FCCOB9)
#define FTFL_FCCOB8_REG(base) ((base)->FCCOB8)
#define FTFL_FPROT3_REG(base) ((base)->FPROT3)
#define FTFL_FPROT2_REG(base) ((base)->FPROT2)
#define FTFL_FPROT1_REG(base) ((base)->FPROT1)
#define FTFL_FPROT0_REG(base) ((base)->FPROT0)
#define FTFL_FEPROT_REG(base) ((base)->FEPROT)
#define FTFL_FDPROT_REG(base) ((base)->FDPROT)
/**
* @}
*/ /* end of group FTFL_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FTFL Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup FTFL_Register_Masks FTFL Register Masks
* @{
*/
/* FSTAT Bit Fields */
#define FTFL_FSTAT_MGSTAT0_MASK 0x1u
#define FTFL_FSTAT_MGSTAT0_SHIFT 0
#define FTFL_FSTAT_FPVIOL_MASK 0x10u
#define FTFL_FSTAT_FPVIOL_SHIFT 4
#define FTFL_FSTAT_ACCERR_MASK 0x20u
#define FTFL_FSTAT_ACCERR_SHIFT 5
#define FTFL_FSTAT_RDCOLERR_MASK 0x40u
#define FTFL_FSTAT_RDCOLERR_SHIFT 6
#define FTFL_FSTAT_CCIF_MASK 0x80u
#define FTFL_FSTAT_CCIF_SHIFT 7
/* FCNFG Bit Fields */
#define FTFL_FCNFG_EEERDY_MASK 0x1u
#define FTFL_FCNFG_EEERDY_SHIFT 0
#define FTFL_FCNFG_RAMRDY_MASK 0x2u
#define FTFL_FCNFG_RAMRDY_SHIFT 1
#define FTFL_FCNFG_PFLSH_MASK 0x4u
#define FTFL_FCNFG_PFLSH_SHIFT 2
#define FTFL_FCNFG_SWAP_MASK 0x8u
#define FTFL_FCNFG_SWAP_SHIFT 3
#define FTFL_FCNFG_ERSSUSP_MASK 0x10u
#define FTFL_FCNFG_ERSSUSP_SHIFT 4
#define FTFL_FCNFG_ERSAREQ_MASK 0x20u
#define FTFL_FCNFG_ERSAREQ_SHIFT 5
#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
#define FTFL_FCNFG_RDCOLLIE_SHIFT 6
#define FTFL_FCNFG_CCIE_MASK 0x80u
#define FTFL_FCNFG_CCIE_SHIFT 7
/* FSEC Bit Fields */
#define FTFL_FSEC_SEC_MASK 0x3u
#define FTFL_FSEC_SEC_SHIFT 0
#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
#define FTFL_FSEC_FSLACC_MASK 0xCu
#define FTFL_FSEC_FSLACC_SHIFT 2
#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
#define FTFL_FSEC_MEEN_MASK 0x30u
#define FTFL_FSEC_MEEN_SHIFT 4
#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
#define FTFL_FSEC_KEYEN_MASK 0xC0u
#define FTFL_FSEC_KEYEN_SHIFT 6
#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
/* FOPT Bit Fields */
#define FTFL_FOPT_OPT_MASK 0xFFu
#define FTFL_FOPT_OPT_SHIFT 0
#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
/* FCCOB3 Bit Fields */
#define FTFL_FCCOB3_CCOBn_MASK 0xFFu
#define FTFL_FCCOB3_CCOBn_SHIFT 0
#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
/* FCCOB2 Bit Fields */
#define FTFL_FCCOB2_CCOBn_MASK 0xFFu
#define FTFL_FCCOB2_CCOBn_SHIFT 0
#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
/* FCCOB1 Bit Fields */
#define FTFL_FCCOB1_CCOBn_MASK 0xFFu
#define FTFL_FCCOB1_CCOBn_SHIFT 0
#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
/* FCCOB0 Bit Fields */
#define FTFL_FCCOB0_CCOBn_MASK 0xFFu
#define FTFL_FCCOB0_CCOBn_SHIFT 0
#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
/* FCCOB7 Bit Fields */
#define FTFL_FCCOB7_CCOBn_MASK 0xFFu
#define FTFL_FCCOB7_CCOBn_SHIFT 0
#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
/* FCCOB6 Bit Fields */
#define FTFL_FCCOB6_CCOBn_MASK 0xFFu
#define FTFL_FCCOB6_CCOBn_SHIFT 0
#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
/* FCCOB5 Bit Fields */
#define FTFL_FCCOB5_CCOBn_MASK 0xFFu
#define FTFL_FCCOB5_CCOBn_SHIFT 0
#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
/* FCCOB4 Bit Fields */
#define FTFL_FCCOB4_CCOBn_MASK 0xFFu
#define FTFL_FCCOB4_CCOBn_SHIFT 0
#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
/* FCCOBB Bit Fields */
#define FTFL_FCCOBB_CCOBn_MASK 0xFFu
#define FTFL_FCCOBB_CCOBn_SHIFT 0
#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
/* FCCOBA Bit Fields */
#define FTFL_FCCOBA_CCOBn_MASK 0xFFu
#define FTFL_FCCOBA_CCOBn_SHIFT 0
#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
/* FCCOB9 Bit Fields */
#define FTFL_FCCOB9_CCOBn_MASK 0xFFu
#define FTFL_FCCOB9_CCOBn_SHIFT 0
#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
/* FCCOB8 Bit Fields */
#define FTFL_FCCOB8_CCOBn_MASK 0xFFu
#define FTFL_FCCOB8_CCOBn_SHIFT 0
#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
/* FPROT3 Bit Fields */
#define FTFL_FPROT3_PROT_MASK 0xFFu
#define FTFL_FPROT3_PROT_SHIFT 0
#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
/* FPROT2 Bit Fields */
#define FTFL_FPROT2_PROT_MASK 0xFFu
#define FTFL_FPROT2_PROT_SHIFT 0
#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
/* FPROT1 Bit Fields */
#define FTFL_FPROT1_PROT_MASK 0xFFu
#define FTFL_FPROT1_PROT_SHIFT 0
#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
/* FPROT0 Bit Fields */
#define FTFL_FPROT0_PROT_MASK 0xFFu
#define FTFL_FPROT0_PROT_SHIFT 0
#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
/* FEPROT Bit Fields */
#define FTFL_FEPROT_EPROT_MASK 0xFFu
#define FTFL_FEPROT_EPROT_SHIFT 0
#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
/* FDPROT Bit Fields */
#define FTFL_FDPROT_DPROT_MASK 0xFFu
#define FTFL_FDPROT_DPROT_SHIFT 0
#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
/**
* @}
*/ /* end of group FTFL_Register_Masks */
/* FTFL - Peripheral instance base addresses */
/** Peripheral FTFL base pointer */
#define FTFL_BASE_PTR ((FTFL_MemMapPtr)0x40020000u)
/* ----------------------------------------------------------------------------
-- FTFL - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup FTFL_Register_Accessor_Macros FTFL - Register accessor macros
* @{
*/
/* FTFL - Register instance definitions */
/* FTFL */
#define FTFL_FOPT FTFL_FOPT_REG(FTFL_BASE_PTR)
#define FTFL_FSTAT FTFL_FSTAT_REG(FTFL_BASE_PTR)
#define FTFL_FCNFG FTFL_FCNFG_REG(FTFL_BASE_PTR)
#define FTFL_FSEC FTFL_FSEC_REG(FTFL_BASE_PTR)
#define FTFL_FCCOB0 FTFL_FCCOB0_REG(FTFL_BASE_PTR)
#define FTFL_FCCOB1 FTFL_FCCOB1_REG(FTFL_BASE_PTR)
#define FTFL_FCCOB2 FTFL_FCCOB2_REG(FTFL_BASE_PTR)
#define FTFL_FCCOB3 FTFL_FCCOB3_REG(FTFL_BASE_PTR)
#define FTFL_FCCOB4 FTFL_FCCOB4_REG(FTFL_BASE_PTR)
#define FTFL_FCCOB5 FTFL_FCCOB5_REG(FTFL_BASE_PTR)
#define FTFL_FCCOB6 FTFL_FCCOB6_REG(FTFL_BASE_PTR)
#define FTFL_FCCOB7 FTFL_FCCOB7_REG(FTFL_BASE_PTR)
#define FTFL_FCCOB8 FTFL_FCCOB8_REG(FTFL_BASE_PTR)
#define FTFL_FCCOB9 FTFL_FCCOB9_REG(FTFL_BASE_PTR)
#define FTFL_FCCOBA FTFL_FCCOBA_REG(FTFL_BASE_PTR)
#define FTFL_FCCOBB FTFL_FCCOBB_REG(FTFL_BASE_PTR)
#define FTFL_FPROT0 FTFL_FPROT0_REG(FTFL_BASE_PTR)
#define FTFL_FPROT1 FTFL_FPROT1_REG(FTFL_BASE_PTR)
#define FTFL_FPROT2 FTFL_FPROT2_REG(FTFL_BASE_PTR)
#define FTFL_FPROT3 FTFL_FPROT3_REG(FTFL_BASE_PTR)
#define FTFL_FDPROT FTFL_FDPROT_REG(FTFL_BASE_PTR)
#define FTFL_FEPROT FTFL_FEPROT_REG(FTFL_BASE_PTR)
/**
* @}
*/ /* end of group FTFL_Register_Accessor_Macros */
/**
* @}
*/ /* end of group FTFL_Peripheral */
/* ----------------------------------------------------------------------------
-- NV
---------------------------------------------------------------------------- */
/**
* @addtogroup NV_Peripheral NV
* @{
*/
/** NV - Peripheral register structure */
typedef struct NV_MemMap {
uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
} volatile *NV_MemMapPtr;
/* ----------------------------------------------------------------------------
-- NV - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
* @{
*/
/* NV - Register accessors */
#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
#define NV_FPROT3_REG(base) ((base)->FPROT3)
#define NV_FPROT2_REG(base) ((base)->FPROT2)
#define NV_FPROT1_REG(base) ((base)->FPROT1)
#define NV_FPROT0_REG(base) ((base)->FPROT0)
#define NV_FSEC_REG(base) ((base)->FSEC)
#define NV_FOPT_REG(base) ((base)->FOPT)
#define NV_FEPROT_REG(base) ((base)->FEPROT)
#define NV_FDPROT_REG(base) ((base)->FDPROT)
/**
* @}
*/ /* end of group NV_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- NV Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup NV_Register_Masks NV Register Masks
* @{
*/
/* BACKKEY3 Bit Fields */
#define NV_BACKKEY3_KEY_MASK 0xFFu
#define NV_BACKKEY3_KEY_SHIFT 0
#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
/* BACKKEY2 Bit Fields */
#define NV_BACKKEY2_KEY_MASK 0xFFu
#define NV_BACKKEY2_KEY_SHIFT 0
#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
/* BACKKEY1 Bit Fields */
#define NV_BACKKEY1_KEY_MASK 0xFFu
#define NV_BACKKEY1_KEY_SHIFT 0
#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
/* BACKKEY0 Bit Fields */
#define NV_BACKKEY0_KEY_MASK 0xFFu
#define NV_BACKKEY0_KEY_SHIFT 0
#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
/* BACKKEY7 Bit Fields */
#define NV_BACKKEY7_KEY_MASK 0xFFu
#define NV_BACKKEY7_KEY_SHIFT 0
#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
/* BACKKEY6 Bit Fields */
#define NV_BACKKEY6_KEY_MASK 0xFFu
#define NV_BACKKEY6_KEY_SHIFT 0
#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
/* BACKKEY5 Bit Fields */
#define NV_BACKKEY5_KEY_MASK 0xFFu
#define NV_BACKKEY5_KEY_SHIFT 0
#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
/* BACKKEY4 Bit Fields */
#define NV_BACKKEY4_KEY_MASK 0xFFu
#define NV_BACKKEY4_KEY_SHIFT 0
#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
/* FPROT3 Bit Fields */
#define NV_FPROT3_PROT_MASK 0xFFu
#define NV_FPROT3_PROT_SHIFT 0
#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
/* FPROT2 Bit Fields */
#define NV_FPROT2_PROT_MASK 0xFFu
#define NV_FPROT2_PROT_SHIFT 0
#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
/* FPROT1 Bit Fields */
#define NV_FPROT1_PROT_MASK 0xFFu
#define NV_FPROT1_PROT_SHIFT 0
#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
/* FPROT0 Bit Fields */
#define NV_FPROT0_PROT_MASK 0xFFu
#define NV_FPROT0_PROT_SHIFT 0
#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
/* FSEC Bit Fields */
#define NV_FSEC_SEC_MASK 0x3u
#define NV_FSEC_SEC_SHIFT 0
#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
#define NV_FSEC_FSLACC_MASK 0xCu
#define NV_FSEC_FSLACC_SHIFT 2
#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
#define NV_FSEC_MEEN_MASK 0x30u
#define NV_FSEC_MEEN_SHIFT 4
#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
#define NV_FSEC_KEYEN_MASK 0xC0u
#define NV_FSEC_KEYEN_SHIFT 6
#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
/* FOPT Bit Fields */
#define NV_FOPT_LPBOOT_MASK 0x1u
#define NV_FOPT_LPBOOT_SHIFT 0
#define NV_FOPT_EZPORT_DIS_MASK 0x2u
#define NV_FOPT_EZPORT_DIS_SHIFT 1
/* FEPROT Bit Fields */
#define NV_FEPROT_EPROT_MASK 0xFFu
#define NV_FEPROT_EPROT_SHIFT 0
#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
/* FDPROT Bit Fields */
#define NV_FDPROT_DPROT_MASK 0xFFu
#define NV_FDPROT_DPROT_SHIFT 0
#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
/**
* @}
*/ /* end of group NV_Register_Masks */
/* NV - Peripheral instance base addresses */
/** Peripheral FTFL_FlashConfig base pointer */
#define FTFL_FlashConfig_BASE_PTR ((NV_MemMapPtr)0x400u)
/* ----------------------------------------------------------------------------
-- NV - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
* @{
*/
/* NV - Register instance definitions */
/* FTFL_FlashConfig */
#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_FPROT3 NV_FPROT3_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_FPROT2 NV_FPROT2_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_FPROT1 NV_FPROT1_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_FPROT0 NV_FPROT0_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_FOPT NV_FOPT_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_FSEC NV_FSEC_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_FDPROT NV_FDPROT_REG(FTFL_FlashConfig_BASE_PTR)
#define NV_FEPROT NV_FEPROT_REG(FTFL_FlashConfig_BASE_PTR)
/**
* @}
*/ /* end of group NV_Register_Accessor_Macros */
/**
* @}
*/ /* end of group NV_Peripheral */
/* ----------------------------------------------------------------------------
-- FTM
---------------------------------------------------------------------------- */
/**
* @addtogroup FTM_Peripheral FTM
* @{
*/
/** FTM - Peripheral register structure */
typedef struct FTM_MemMap {
uint32_t SC; /**< Status and Control, offset: 0x0 */
uint32_t CNT; /**< Counter, offset: 0x4 */
uint32_t MOD; /**< Modulo, offset: 0x8 */
struct { /* offset: 0xC, array step: 0x8 */
uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
} CONTROLS[8];
uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
uint32_t SYNC; /**< Synchronization, offset: 0x58 */
uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
uint32_t POL; /**< Channels Polarity, offset: 0x70 */
uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
uint32_t CONF; /**< Configuration, offset: 0x84 */
uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
} volatile *FTM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FTM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
* @{
*/
/* FTM - Register accessors */
#define FTM_SC_REG(base) ((base)->SC)
#define FTM_CNT_REG(base) ((base)->CNT)
#define FTM_MOD_REG(base) ((base)->MOD)
#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
#define FTM_CNTIN_REG(base) ((base)->CNTIN)
#define FTM_STATUS_REG(base) ((base)->STATUS)
#define FTM_MODE_REG(base) ((base)->MODE)
#define FTM_SYNC_REG(base) ((base)->SYNC)
#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
#define FTM_COMBINE_REG(base) ((base)->COMBINE)
#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
#define FTM_POL_REG(base) ((base)->POL)
#define FTM_FMS_REG(base) ((base)->FMS)
#define FTM_FILTER_REG(base) ((base)->FILTER)
#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
#define FTM_CONF_REG(base) ((base)->CONF)
#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
/**
* @}
*/ /* end of group FTM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FTM Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup FTM_Register_Masks FTM Register Masks
* @{
*/
/* SC Bit Fields */
#define FTM_SC_PS_MASK 0x7u
#define FTM_SC_PS_SHIFT 0
#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
#define FTM_SC_CLKS_MASK 0x18u
#define FTM_SC_CLKS_SHIFT 3
#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
#define FTM_SC_CPWMS_MASK 0x20u
#define FTM_SC_CPWMS_SHIFT 5
#define FTM_SC_TOIE_MASK 0x40u
#define FTM_SC_TOIE_SHIFT 6
#define FTM_SC_TOF_MASK 0x80u
#define FTM_SC_TOF_SHIFT 7
/* CNT Bit Fields */
#define FTM_CNT_COUNT_MASK 0xFFFFu
#define FTM_CNT_COUNT_SHIFT 0
#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
/* MOD Bit Fields */
#define FTM_MOD_MOD_MASK 0xFFFFu
#define FTM_MOD_MOD_SHIFT 0
#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
/* CnSC Bit Fields */
#define FTM_CnSC_DMA_MASK 0x1u
#define FTM_CnSC_DMA_SHIFT 0
#define FTM_CnSC_ELSA_MASK 0x4u
#define FTM_CnSC_ELSA_SHIFT 2
#define FTM_CnSC_ELSB_MASK 0x8u
#define FTM_CnSC_ELSB_SHIFT 3
#define FTM_CnSC_MSA_MASK 0x10u
#define FTM_CnSC_MSA_SHIFT 4
#define FTM_CnSC_MSB_MASK 0x20u
#define FTM_CnSC_MSB_SHIFT 5
#define FTM_CnSC_CHIE_MASK 0x40u
#define FTM_CnSC_CHIE_SHIFT 6
#define FTM_CnSC_CHF_MASK 0x80u
#define FTM_CnSC_CHF_SHIFT 7
/* CnV Bit Fields */
#define FTM_CnV_VAL_MASK 0xFFFFu
#define FTM_CnV_VAL_SHIFT 0
#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
/* CNTIN Bit Fields */
#define FTM_CNTIN_INIT_MASK 0xFFFFu
#define FTM_CNTIN_INIT_SHIFT 0
#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
/* STATUS Bit Fields */
#define FTM_STATUS_CH0F_MASK 0x1u
#define FTM_STATUS_CH0F_SHIFT 0
#define FTM_STATUS_CH1F_MASK 0x2u
#define FTM_STATUS_CH1F_SHIFT 1
#define FTM_STATUS_CH2F_MASK 0x4u
#define FTM_STATUS_CH2F_SHIFT 2
#define FTM_STATUS_CH3F_MASK 0x8u
#define FTM_STATUS_CH3F_SHIFT 3
#define FTM_STATUS_CH4F_MASK 0x10u
#define FTM_STATUS_CH4F_SHIFT 4
#define FTM_STATUS_CH5F_MASK 0x20u
#define FTM_STATUS_CH5F_SHIFT 5
#define FTM_STATUS_CH6F_MASK 0x40u
#define FTM_STATUS_CH6F_SHIFT 6
#define FTM_STATUS_CH7F_MASK 0x80u
#define FTM_STATUS_CH7F_SHIFT 7
/* MODE Bit Fields */
#define FTM_MODE_FTMEN_MASK 0x1u
#define FTM_MODE_FTMEN_SHIFT 0
#define FTM_MODE_INIT_MASK 0x2u
#define FTM_MODE_INIT_SHIFT 1
#define FTM_MODE_WPDIS_MASK 0x4u
#define FTM_MODE_WPDIS_SHIFT 2
#define FTM_MODE_PWMSYNC_MASK 0x8u
#define FTM_MODE_PWMSYNC_SHIFT 3
#define FTM_MODE_CAPTEST_MASK 0x10u
#define FTM_MODE_CAPTEST_SHIFT 4
#define FTM_MODE_FAULTM_MASK 0x60u
#define FTM_MODE_FAULTM_SHIFT 5
#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
#define FTM_MODE_FAULTIE_MASK 0x80u
#define FTM_MODE_FAULTIE_SHIFT 7
/* SYNC Bit Fields */
#define FTM_SYNC_CNTMIN_MASK 0x1u
#define FTM_SYNC_CNTMIN_SHIFT 0
#define FTM_SYNC_CNTMAX_MASK 0x2u
#define FTM_SYNC_CNTMAX_SHIFT 1
#define FTM_SYNC_REINIT_MASK 0x4u
#define FTM_SYNC_REINIT_SHIFT 2
#define FTM_SYNC_SYNCHOM_MASK 0x8u
#define FTM_SYNC_SYNCHOM_SHIFT 3
#define FTM_SYNC_TRIG0_MASK 0x10u
#define FTM_SYNC_TRIG0_SHIFT 4
#define FTM_SYNC_TRIG1_MASK 0x20u
#define FTM_SYNC_TRIG1_SHIFT 5
#define FTM_SYNC_TRIG2_MASK 0x40u
#define FTM_SYNC_TRIG2_SHIFT 6
#define FTM_SYNC_SWSYNC_MASK 0x80u
#define FTM_SYNC_SWSYNC_SHIFT 7
/* OUTINIT Bit Fields */
#define FTM_OUTINIT_CH0OI_MASK 0x1u
#define FTM_OUTINIT_CH0OI_SHIFT 0
#define FTM_OUTINIT_CH1OI_MASK 0x2u
#define FTM_OUTINIT_CH1OI_SHIFT 1
#define FTM_OUTINIT_CH2OI_MASK 0x4u
#define FTM_OUTINIT_CH2OI_SHIFT 2
#define FTM_OUTINIT_CH3OI_MASK 0x8u
#define FTM_OUTINIT_CH3OI_SHIFT 3
#define FTM_OUTINIT_CH4OI_MASK 0x10u
#define FTM_OUTINIT_CH4OI_SHIFT 4
#define FTM_OUTINIT_CH5OI_MASK 0x20u
#define FTM_OUTINIT_CH5OI_SHIFT 5
#define FTM_OUTINIT_CH6OI_MASK 0x40u
#define FTM_OUTINIT_CH6OI_SHIFT 6
#define FTM_OUTINIT_CH7OI_MASK 0x80u
#define FTM_OUTINIT_CH7OI_SHIFT 7
/* OUTMASK Bit Fields */
#define FTM_OUTMASK_CH0OM_MASK 0x1u
#define FTM_OUTMASK_CH0OM_SHIFT 0
#define FTM_OUTMASK_CH1OM_MASK 0x2u
#define FTM_OUTMASK_CH1OM_SHIFT 1
#define FTM_OUTMASK_CH2OM_MASK 0x4u
#define FTM_OUTMASK_CH2OM_SHIFT 2
#define FTM_OUTMASK_CH3OM_MASK 0x8u
#define FTM_OUTMASK_CH3OM_SHIFT 3
#define FTM_OUTMASK_CH4OM_MASK 0x10u
#define FTM_OUTMASK_CH4OM_SHIFT 4
#define FTM_OUTMASK_CH5OM_MASK 0x20u
#define FTM_OUTMASK_CH5OM_SHIFT 5
#define FTM_OUTMASK_CH6OM_MASK 0x40u
#define FTM_OUTMASK_CH6OM_SHIFT 6
#define FTM_OUTMASK_CH7OM_MASK 0x80u
#define FTM_OUTMASK_CH7OM_SHIFT 7
/* COMBINE Bit Fields */
#define FTM_COMBINE_COMBINE0_MASK 0x1u
#define FTM_COMBINE_COMBINE0_SHIFT 0
#define FTM_COMBINE_COMP0_MASK 0x2u
#define FTM_COMBINE_COMP0_SHIFT 1
#define FTM_COMBINE_DECAPEN0_MASK 0x4u
#define FTM_COMBINE_DECAPEN0_SHIFT 2
#define FTM_COMBINE_DECAP0_MASK 0x8u
#define FTM_COMBINE_DECAP0_SHIFT 3
#define FTM_COMBINE_DTEN0_MASK 0x10u
#define FTM_COMBINE_DTEN0_SHIFT 4
#define FTM_COMBINE_SYNCEN0_MASK 0x20u
#define FTM_COMBINE_SYNCEN0_SHIFT 5
#define FTM_COMBINE_FAULTEN0_MASK 0x40u
#define FTM_COMBINE_FAULTEN0_SHIFT 6
#define FTM_COMBINE_COMBINE1_MASK 0x100u
#define FTM_COMBINE_COMBINE1_SHIFT 8
#define FTM_COMBINE_COMP1_MASK 0x200u
#define FTM_COMBINE_COMP1_SHIFT 9
#define FTM_COMBINE_DECAPEN1_MASK 0x400u
#define FTM_COMBINE_DECAPEN1_SHIFT 10
#define FTM_COMBINE_DECAP1_MASK 0x800u
#define FTM_COMBINE_DECAP1_SHIFT 11
#define FTM_COMBINE_DTEN1_MASK 0x1000u
#define FTM_COMBINE_DTEN1_SHIFT 12
#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
#define FTM_COMBINE_SYNCEN1_SHIFT 13
#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
#define FTM_COMBINE_FAULTEN1_SHIFT 14
#define FTM_COMBINE_COMBINE2_MASK 0x10000u
#define FTM_COMBINE_COMBINE2_SHIFT 16
#define FTM_COMBINE_COMP2_MASK 0x20000u
#define FTM_COMBINE_COMP2_SHIFT 17
#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
#define FTM_COMBINE_DECAPEN2_SHIFT 18
#define FTM_COMBINE_DECAP2_MASK 0x80000u
#define FTM_COMBINE_DECAP2_SHIFT 19
#define FTM_COMBINE_DTEN2_MASK 0x100000u
#define FTM_COMBINE_DTEN2_SHIFT 20
#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
#define FTM_COMBINE_SYNCEN2_SHIFT 21
#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
#define FTM_COMBINE_FAULTEN2_SHIFT 22
#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
#define FTM_COMBINE_COMBINE3_SHIFT 24
#define FTM_COMBINE_COMP3_MASK 0x2000000u
#define FTM_COMBINE_COMP3_SHIFT 25
#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
#define FTM_COMBINE_DECAPEN3_SHIFT 26
#define FTM_COMBINE_DECAP3_MASK 0x8000000u
#define FTM_COMBINE_DECAP3_SHIFT 27
#define FTM_COMBINE_DTEN3_MASK 0x10000000u
#define FTM_COMBINE_DTEN3_SHIFT 28
#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
#define FTM_COMBINE_SYNCEN3_SHIFT 29
#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
#define FTM_COMBINE_FAULTEN3_SHIFT 30
/* DEADTIME Bit Fields */
#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
#define FTM_DEADTIME_DTVAL_SHIFT 0
#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
#define FTM_DEADTIME_DTPS_MASK 0xC0u
#define FTM_DEADTIME_DTPS_SHIFT 6
#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
/* EXTTRIG Bit Fields */
#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
#define FTM_EXTTRIG_TRIGF_MASK 0x80u
#define FTM_EXTTRIG_TRIGF_SHIFT 7
/* POL Bit Fields */
#define FTM_POL_POL0_MASK 0x1u
#define FTM_POL_POL0_SHIFT 0
#define FTM_POL_POL1_MASK 0x2u
#define FTM_POL_POL1_SHIFT 1
#define FTM_POL_POL2_MASK 0x4u
#define FTM_POL_POL2_SHIFT 2
#define FTM_POL_POL3_MASK 0x8u
#define FTM_POL_POL3_SHIFT 3
#define FTM_POL_POL4_MASK 0x10u
#define FTM_POL_POL4_SHIFT 4
#define FTM_POL_POL5_MASK 0x20u
#define FTM_POL_POL5_SHIFT 5
#define FTM_POL_POL6_MASK 0x40u
#define FTM_POL_POL6_SHIFT 6
#define FTM_POL_POL7_MASK 0x80u
#define FTM_POL_POL7_SHIFT 7
/* FMS Bit Fields */
#define FTM_FMS_FAULTF0_MASK 0x1u
#define FTM_FMS_FAULTF0_SHIFT 0
#define FTM_FMS_FAULTF1_MASK 0x2u
#define FTM_FMS_FAULTF1_SHIFT 1
#define FTM_FMS_FAULTF2_MASK 0x4u
#define FTM_FMS_FAULTF2_SHIFT 2
#define FTM_FMS_FAULTF3_MASK 0x8u
#define FTM_FMS_FAULTF3_SHIFT 3
#define FTM_FMS_FAULTIN_MASK 0x20u
#define FTM_FMS_FAULTIN_SHIFT 5
#define FTM_FMS_WPEN_MASK 0x40u
#define FTM_FMS_WPEN_SHIFT 6
#define FTM_FMS_FAULTF_MASK 0x80u
#define FTM_FMS_FAULTF_SHIFT 7
/* FILTER Bit Fields */
#define FTM_FILTER_CH0FVAL_MASK 0xFu
#define FTM_FILTER_CH0FVAL_SHIFT 0
#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
#define FTM_FILTER_CH1FVAL_MASK 0xF0u
#define FTM_FILTER_CH1FVAL_SHIFT 4
#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
#define FTM_FILTER_CH2FVAL_MASK 0xF00u
#define FTM_FILTER_CH2FVAL_SHIFT 8
#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
#define FTM_FILTER_CH3FVAL_MASK 0xF000u
#define FTM_FILTER_CH3FVAL_SHIFT 12
#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
/* FLTCTRL Bit Fields */
#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
#define FTM_FLTCTRL_FFVAL_SHIFT 8
#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
/* QDCTRL Bit Fields */
#define FTM_QDCTRL_QUADEN_MASK 0x1u
#define FTM_QDCTRL_QUADEN_SHIFT 0
#define FTM_QDCTRL_TOFDIR_MASK 0x2u
#define FTM_QDCTRL_TOFDIR_SHIFT 1
#define FTM_QDCTRL_QUADIR_MASK 0x4u
#define FTM_QDCTRL_QUADIR_SHIFT 2
#define FTM_QDCTRL_QUADMODE_MASK 0x8u
#define FTM_QDCTRL_QUADMODE_SHIFT 3
#define FTM_QDCTRL_PHBPOL_MASK 0x10u
#define FTM_QDCTRL_PHBPOL_SHIFT 4
#define FTM_QDCTRL_PHAPOL_MASK 0x20u
#define FTM_QDCTRL_PHAPOL_SHIFT 5
#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
/* CONF Bit Fields */
#define FTM_CONF_NUMTOF_MASK 0x1Fu
#define FTM_CONF_NUMTOF_SHIFT 0
#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
#define FTM_CONF_BDMMODE_MASK 0xC0u
#define FTM_CONF_BDMMODE_SHIFT 6
#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
#define FTM_CONF_GTBEEN_MASK 0x200u
#define FTM_CONF_GTBEEN_SHIFT 9
#define FTM_CONF_GTBEOUT_MASK 0x400u
#define FTM_CONF_GTBEOUT_SHIFT 10
/* FLTPOL Bit Fields */
#define FTM_FLTPOL_FLT0POL_MASK 0x1u
#define FTM_FLTPOL_FLT0POL_SHIFT 0
#define FTM_FLTPOL_FLT1POL_MASK 0x2u
#define FTM_FLTPOL_FLT1POL_SHIFT 1
#define FTM_FLTPOL_FLT2POL_MASK 0x4u
#define FTM_FLTPOL_FLT2POL_SHIFT 2
#define FTM_FLTPOL_FLT3POL_MASK 0x8u
#define FTM_FLTPOL_FLT3POL_SHIFT 3
/* SYNCONF Bit Fields */
#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
#define FTM_SYNCONF_CNTINC_MASK 0x4u
#define FTM_SYNCONF_CNTINC_SHIFT 2
#define FTM_SYNCONF_INVC_MASK 0x10u
#define FTM_SYNCONF_INVC_SHIFT 4
#define FTM_SYNCONF_SWOC_MASK 0x20u
#define FTM_SYNCONF_SWOC_SHIFT 5
#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
#define FTM_SYNCONF_SYNCMODE_SHIFT 7
#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
#define FTM_SYNCONF_SWWRBUF_SHIFT 9
#define FTM_SYNCONF_SWOM_MASK 0x400u
#define FTM_SYNCONF_SWOM_SHIFT 10
#define FTM_SYNCONF_SWINVC_MASK 0x800u
#define FTM_SYNCONF_SWINVC_SHIFT 11
#define FTM_SYNCONF_SWSOC_MASK 0x1000u
#define FTM_SYNCONF_SWSOC_SHIFT 12
#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
#define FTM_SYNCONF_HWWRBUF_SHIFT 17
#define FTM_SYNCONF_HWOM_MASK 0x40000u
#define FTM_SYNCONF_HWOM_SHIFT 18
#define FTM_SYNCONF_HWINVC_MASK 0x80000u
#define FTM_SYNCONF_HWINVC_SHIFT 19
#define FTM_SYNCONF_HWSOC_MASK 0x100000u
#define FTM_SYNCONF_HWSOC_SHIFT 20
/* INVCTRL Bit Fields */
#define FTM_INVCTRL_INV0EN_MASK 0x1u
#define FTM_INVCTRL_INV0EN_SHIFT 0
#define FTM_INVCTRL_INV1EN_MASK 0x2u
#define FTM_INVCTRL_INV1EN_SHIFT 1
#define FTM_INVCTRL_INV2EN_MASK 0x4u
#define FTM_INVCTRL_INV2EN_SHIFT 2
#define FTM_INVCTRL_INV3EN_MASK 0x8u
#define FTM_INVCTRL_INV3EN_SHIFT 3
/* SWOCTRL Bit Fields */
#define FTM_SWOCTRL_CH0OC_MASK 0x1u
#define FTM_SWOCTRL_CH0OC_SHIFT 0
#define FTM_SWOCTRL_CH1OC_MASK 0x2u
#define FTM_SWOCTRL_CH1OC_SHIFT 1
#define FTM_SWOCTRL_CH2OC_MASK 0x4u
#define FTM_SWOCTRL_CH2OC_SHIFT 2
#define FTM_SWOCTRL_CH3OC_MASK 0x8u
#define FTM_SWOCTRL_CH3OC_SHIFT 3
#define FTM_SWOCTRL_CH4OC_MASK 0x10u
#define FTM_SWOCTRL_CH4OC_SHIFT 4
#define FTM_SWOCTRL_CH5OC_MASK 0x20u
#define FTM_SWOCTRL_CH5OC_SHIFT 5
#define FTM_SWOCTRL_CH6OC_MASK 0x40u
#define FTM_SWOCTRL_CH6OC_SHIFT 6
#define FTM_SWOCTRL_CH7OC_MASK 0x80u
#define FTM_SWOCTRL_CH7OC_SHIFT 7
#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
#define FTM_SWOCTRL_CH0OCV_SHIFT 8
#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
#define FTM_SWOCTRL_CH1OCV_SHIFT 9
#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
#define FTM_SWOCTRL_CH2OCV_SHIFT 10
#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
#define FTM_SWOCTRL_CH3OCV_SHIFT 11
#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
#define FTM_SWOCTRL_CH4OCV_SHIFT 12
#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
#define FTM_SWOCTRL_CH5OCV_SHIFT 13
#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
#define FTM_SWOCTRL_CH6OCV_SHIFT 14
#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
#define FTM_SWOCTRL_CH7OCV_SHIFT 15
/* PWMLOAD Bit Fields */
#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
#define FTM_PWMLOAD_CH0SEL_SHIFT 0
#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
#define FTM_PWMLOAD_CH1SEL_SHIFT 1
#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
#define FTM_PWMLOAD_CH2SEL_SHIFT 2
#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
#define FTM_PWMLOAD_CH3SEL_SHIFT 3
#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
#define FTM_PWMLOAD_CH4SEL_SHIFT 4
#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
#define FTM_PWMLOAD_CH5SEL_SHIFT 5
#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
#define FTM_PWMLOAD_CH6SEL_SHIFT 6
#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
#define FTM_PWMLOAD_CH7SEL_SHIFT 7
#define FTM_PWMLOAD_LDOK_MASK 0x200u
#define FTM_PWMLOAD_LDOK_SHIFT 9
/**
* @}
*/ /* end of group FTM_Register_Masks */
/* FTM - Peripheral instance base addresses */
/** Peripheral FTM0 base pointer */
#define FTM0_BASE_PTR ((FTM_MemMapPtr)0x40038000u)
/** Peripheral FTM1 base pointer */
#define FTM1_BASE_PTR ((FTM_MemMapPtr)0x40039000u)
/** Peripheral FTM2 base pointer */
#define FTM2_BASE_PTR ((FTM_MemMapPtr)0x400B8000u)
/* ----------------------------------------------------------------------------
-- FTM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
* @{
*/
/* FTM - Register instance definitions */
/* FTM0 */
#define FTM0_SC FTM_SC_REG(FTM0_BASE_PTR)
#define FTM0_CNT FTM_CNT_REG(FTM0_BASE_PTR)
#define FTM0_MOD FTM_MOD_REG(FTM0_BASE_PTR)
#define FTM0_C0SC FTM_CnSC_REG(FTM0_BASE_PTR,0)
#define FTM0_C0V FTM_CnV_REG(FTM0_BASE_PTR,0)
#define FTM0_C1SC FTM_CnSC_REG(FTM0_BASE_PTR,1)
#define FTM0_C1V FTM_CnV_REG(FTM0_BASE_PTR,1)
#define FTM0_C2SC FTM_CnSC_REG(FTM0_BASE_PTR,2)
#define FTM0_C2V FTM_CnV_REG(FTM0_BASE_PTR,2)
#define FTM0_C3SC FTM_CnSC_REG(FTM0_BASE_PTR,3)
#define FTM0_C3V FTM_CnV_REG(FTM0_BASE_PTR,3)
#define FTM0_C4SC FTM_CnSC_REG(FTM0_BASE_PTR,4)
#define FTM0_C4V FTM_CnV_REG(FTM0_BASE_PTR,4)
#define FTM0_C5SC FTM_CnSC_REG(FTM0_BASE_PTR,5)
#define FTM0_C5V FTM_CnV_REG(FTM0_BASE_PTR,5)
#define FTM0_C6SC FTM_CnSC_REG(FTM0_BASE_PTR,6)
#define FTM0_C6V FTM_CnV_REG(FTM0_BASE_PTR,6)
#define FTM0_C7SC FTM_CnSC_REG(FTM0_BASE_PTR,7)
#define FTM0_C7V FTM_CnV_REG(FTM0_BASE_PTR,7)
#define FTM0_CNTIN FTM_CNTIN_REG(FTM0_BASE_PTR)
#define FTM0_STATUS FTM_STATUS_REG(FTM0_BASE_PTR)
#define FTM0_MODE FTM_MODE_REG(FTM0_BASE_PTR)
#define FTM0_SYNC FTM_SYNC_REG(FTM0_BASE_PTR)
#define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0_BASE_PTR)
#define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0_BASE_PTR)
#define FTM0_COMBINE FTM_COMBINE_REG(FTM0_BASE_PTR)
#define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0_BASE_PTR)
#define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0_BASE_PTR)
#define FTM0_POL FTM_POL_REG(FTM0_BASE_PTR)
#define FTM0_FMS FTM_FMS_REG(FTM0_BASE_PTR)
#define FTM0_FILTER FTM_FILTER_REG(FTM0_BASE_PTR)
#define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0_BASE_PTR)
#define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0_BASE_PTR)
#define FTM0_CONF FTM_CONF_REG(FTM0_BASE_PTR)
#define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0_BASE_PTR)
#define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0_BASE_PTR)
#define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0_BASE_PTR)
#define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0_BASE_PTR)
#define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0_BASE_PTR)
/* FTM1 */
#define FTM1_SC FTM_SC_REG(FTM1_BASE_PTR)
#define FTM1_CNT FTM_CNT_REG(FTM1_BASE_PTR)
#define FTM1_MOD FTM_MOD_REG(FTM1_BASE_PTR)
#define FTM1_C0SC FTM_CnSC_REG(FTM1_BASE_PTR,0)
#define FTM1_C0V FTM_CnV_REG(FTM1_BASE_PTR,0)
#define FTM1_C1SC FTM_CnSC_REG(FTM1_BASE_PTR,1)
#define FTM1_C1V FTM_CnV_REG(FTM1_BASE_PTR,1)
#define FTM1_CNTIN FTM_CNTIN_REG(FTM1_BASE_PTR)
#define FTM1_STATUS FTM_STATUS_REG(FTM1_BASE_PTR)
#define FTM1_MODE FTM_MODE_REG(FTM1_BASE_PTR)
#define FTM1_SYNC FTM_SYNC_REG(FTM1_BASE_PTR)
#define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1_BASE_PTR)
#define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1_BASE_PTR)
#define FTM1_COMBINE FTM_COMBINE_REG(FTM1_BASE_PTR)
#define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1_BASE_PTR)
#define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1_BASE_PTR)
#define FTM1_POL FTM_POL_REG(FTM1_BASE_PTR)
#define FTM1_FMS FTM_FMS_REG(FTM1_BASE_PTR)
#define FTM1_FILTER FTM_FILTER_REG(FTM1_BASE_PTR)
#define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1_BASE_PTR)
#define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1_BASE_PTR)
#define FTM1_CONF FTM_CONF_REG(FTM1_BASE_PTR)
#define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1_BASE_PTR)
#define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1_BASE_PTR)
#define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1_BASE_PTR)
#define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1_BASE_PTR)
#define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1_BASE_PTR)
/* FTM2 */
#define FTM2_SC FTM_SC_REG(FTM2_BASE_PTR)
#define FTM2_CNT FTM_CNT_REG(FTM2_BASE_PTR)
#define FTM2_MOD FTM_MOD_REG(FTM2_BASE_PTR)
#define FTM2_C0SC FTM_CnSC_REG(FTM2_BASE_PTR,0)
#define FTM2_C0V FTM_CnV_REG(FTM2_BASE_PTR,0)
#define FTM2_C1SC FTM_CnSC_REG(FTM2_BASE_PTR,1)
#define FTM2_C1V FTM_CnV_REG(FTM2_BASE_PTR,1)
#define FTM2_CNTIN FTM_CNTIN_REG(FTM2_BASE_PTR)
#define FTM2_STATUS FTM_STATUS_REG(FTM2_BASE_PTR)
#define FTM2_MODE FTM_MODE_REG(FTM2_BASE_PTR)
#define FTM2_SYNC FTM_SYNC_REG(FTM2_BASE_PTR)
#define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2_BASE_PTR)
#define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2_BASE_PTR)
#define FTM2_COMBINE FTM_COMBINE_REG(FTM2_BASE_PTR)
#define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2_BASE_PTR)
#define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2_BASE_PTR)
#define FTM2_POL FTM_POL_REG(FTM2_BASE_PTR)
#define FTM2_FMS FTM_FMS_REG(FTM2_BASE_PTR)
#define FTM2_FILTER FTM_FILTER_REG(FTM2_BASE_PTR)
#define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2_BASE_PTR)
#define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2_BASE_PTR)
#define FTM2_CONF FTM_CONF_REG(FTM2_BASE_PTR)
#define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2_BASE_PTR)
#define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2_BASE_PTR)
#define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2_BASE_PTR)
#define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2_BASE_PTR)
#define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2_BASE_PTR)
/* FTM - Register array accessors */
#define FTM0_CnSC(index) FTM_CnSC_REG(FTM0_BASE_PTR,index)
#define FTM1_CnSC(index) FTM_CnSC_REG(FTM1_BASE_PTR,index)
#define FTM2_CnSC(index) FTM_CnSC_REG(FTM2_BASE_PTR,index)
#define FTM0_CnV(index) FTM_CnV_REG(FTM0_BASE_PTR,index)
#define FTM1_CnV(index) FTM_CnV_REG(FTM1_BASE_PTR,index)
#define FTM2_CnV(index) FTM_CnV_REG(FTM2_BASE_PTR,index)
/**
* @}
*/ /* end of group FTM_Register_Accessor_Macros */
/**
* @}
*/ /* end of group FTM_Peripheral */
/* ----------------------------------------------------------------------------
-- I2C
---------------------------------------------------------------------------- */
/**
* @addtogroup I2C_Peripheral I2C
* @{
*/
/** I2C - Peripheral register structure */
typedef struct I2C_MemMap {
uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
uint8_t S; /**< I2C Status Register, offset: 0x3 */
uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
} volatile *I2C_MemMapPtr;
/* ----------------------------------------------------------------------------
-- I2C - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
* @{
*/
/* I2C - Register accessors */
#define I2C_A1_REG(base) ((base)->A1)
#define I2C_F_REG(base) ((base)->F)
#define I2C_C1_REG(base) ((base)->C1)
#define I2C_S_REG(base) ((base)->S)
#define I2C_D_REG(base) ((base)->D)
#define I2C_C2_REG(base) ((base)->C2)
#define I2C_FLT_REG(base) ((base)->FLT)
#define I2C_RA_REG(base) ((base)->RA)
#define I2C_SMB_REG(base) ((base)->SMB)
#define I2C_A2_REG(base) ((base)->A2)
#define I2C_SLTH_REG(base) ((base)->SLTH)
#define I2C_SLTL_REG(base) ((base)->SLTL)
/**
* @}
*/ /* end of group I2C_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- I2C Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup I2C_Register_Masks I2C Register Masks
* @{
*/
/* A1 Bit Fields */
#define I2C_A1_AD_MASK 0xFEu
#define I2C_A1_AD_SHIFT 1
#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
/* F Bit Fields */
#define I2C_F_ICR_MASK 0x3Fu
#define I2C_F_ICR_SHIFT 0
#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
#define I2C_F_MULT_MASK 0xC0u
#define I2C_F_MULT_SHIFT 6
#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
/* C1 Bit Fields */
#define I2C_C1_DMAEN_MASK 0x1u
#define I2C_C1_DMAEN_SHIFT 0
#define I2C_C1_WUEN_MASK 0x2u
#define I2C_C1_WUEN_SHIFT 1
#define I2C_C1_RSTA_MASK 0x4u
#define I2C_C1_RSTA_SHIFT 2
#define I2C_C1_TXAK_MASK 0x8u
#define I2C_C1_TXAK_SHIFT 3
#define I2C_C1_TX_MASK 0x10u
#define I2C_C1_TX_SHIFT 4
#define I2C_C1_MST_MASK 0x20u
#define I2C_C1_MST_SHIFT 5
#define I2C_C1_IICIE_MASK 0x40u
#define I2C_C1_IICIE_SHIFT 6
#define I2C_C1_IICEN_MASK 0x80u
#define I2C_C1_IICEN_SHIFT 7
/* S Bit Fields */
#define I2C_S_RXAK_MASK 0x1u
#define I2C_S_RXAK_SHIFT 0
#define I2C_S_IICIF_MASK 0x2u
#define I2C_S_IICIF_SHIFT 1
#define I2C_S_SRW_MASK 0x4u
#define I2C_S_SRW_SHIFT 2
#define I2C_S_RAM_MASK 0x8u
#define I2C_S_RAM_SHIFT 3
#define I2C_S_ARBL_MASK 0x10u
#define I2C_S_ARBL_SHIFT 4
#define I2C_S_BUSY_MASK 0x20u
#define I2C_S_BUSY_SHIFT 5
#define I2C_S_IAAS_MASK 0x40u
#define I2C_S_IAAS_SHIFT 6
#define I2C_S_TCF_MASK 0x80u
#define I2C_S_TCF_SHIFT 7
/* D Bit Fields */
#define I2C_D_DATA_MASK 0xFFu
#define I2C_D_DATA_SHIFT 0
#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
/* C2 Bit Fields */
#define I2C_C2_AD_MASK 0x7u
#define I2C_C2_AD_SHIFT 0
#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
#define I2C_C2_RMEN_MASK 0x8u
#define I2C_C2_RMEN_SHIFT 3
#define I2C_C2_SBRC_MASK 0x10u
#define I2C_C2_SBRC_SHIFT 4
#define I2C_C2_HDRS_MASK 0x20u
#define I2C_C2_HDRS_SHIFT 5
#define I2C_C2_ADEXT_MASK 0x40u
#define I2C_C2_ADEXT_SHIFT 6
#define I2C_C2_GCAEN_MASK 0x80u
#define I2C_C2_GCAEN_SHIFT 7
/* FLT Bit Fields */
#define I2C_FLT_FLT_MASK 0x1Fu
#define I2C_FLT_FLT_SHIFT 0
#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
/* RA Bit Fields */
#define I2C_RA_RAD_MASK 0xFEu
#define I2C_RA_RAD_SHIFT 1
#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
/* SMB Bit Fields */
#define I2C_SMB_SHTF2IE_MASK 0x1u
#define I2C_SMB_SHTF2IE_SHIFT 0
#define I2C_SMB_SHTF2_MASK 0x2u
#define I2C_SMB_SHTF2_SHIFT 1
#define I2C_SMB_SHTF1_MASK 0x4u
#define I2C_SMB_SHTF1_SHIFT 2
#define I2C_SMB_SLTF_MASK 0x8u
#define I2C_SMB_SLTF_SHIFT 3
#define I2C_SMB_TCKSEL_MASK 0x10u
#define I2C_SMB_TCKSEL_SHIFT 4
#define I2C_SMB_SIICAEN_MASK 0x20u
#define I2C_SMB_SIICAEN_SHIFT 5
#define I2C_SMB_ALERTEN_MASK 0x40u
#define I2C_SMB_ALERTEN_SHIFT 6
#define I2C_SMB_FACK_MASK 0x80u
#define I2C_SMB_FACK_SHIFT 7
/* A2 Bit Fields */
#define I2C_A2_SAD_MASK 0xFEu
#define I2C_A2_SAD_SHIFT 1
#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
/* SLTH Bit Fields */
#define I2C_SLTH_SSLT_MASK 0xFFu
#define I2C_SLTH_SSLT_SHIFT 0
#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
/* SLTL Bit Fields */
#define I2C_SLTL_SSLT_MASK 0xFFu
#define I2C_SLTL_SSLT_SHIFT 0
#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
/**
* @}
*/ /* end of group I2C_Register_Masks */
/* I2C - Peripheral instance base addresses */
/** Peripheral I2C0 base pointer */
#define I2C0_BASE_PTR ((I2C_MemMapPtr)0x40066000u)
/** Peripheral I2C1 base pointer */
#define I2C1_BASE_PTR ((I2C_MemMapPtr)0x40067000u)
/* ----------------------------------------------------------------------------
-- I2C - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
* @{
*/
/* I2C - Register instance definitions */
/* I2C0 */
#define I2C0_A1 I2C_A1_REG(I2C0_BASE_PTR)
#define I2C0_F I2C_F_REG(I2C0_BASE_PTR)
#define I2C0_C1 I2C_C1_REG(I2C0_BASE_PTR)
#define I2C0_S I2C_S_REG(I2C0_BASE_PTR)
#define I2C0_D I2C_D_REG(I2C0_BASE_PTR)
#define I2C0_C2 I2C_C2_REG(I2C0_BASE_PTR)
#define I2C0_FLT I2C_FLT_REG(I2C0_BASE_PTR)
#define I2C0_RA I2C_RA_REG(I2C0_BASE_PTR)
#define I2C0_SMB I2C_SMB_REG(I2C0_BASE_PTR)
#define I2C0_A2 I2C_A2_REG(I2C0_BASE_PTR)
#define I2C0_SLTH I2C_SLTH_REG(I2C0_BASE_PTR)
#define I2C0_SLTL I2C_SLTL_REG(I2C0_BASE_PTR)
/* I2C1 */
#define I2C1_A1 I2C_A1_REG(I2C1_BASE_PTR)
#define I2C1_F I2C_F_REG(I2C1_BASE_PTR)
#define I2C1_C1 I2C_C1_REG(I2C1_BASE_PTR)
#define I2C1_S I2C_S_REG(I2C1_BASE_PTR)
#define I2C1_D I2C_D_REG(I2C1_BASE_PTR)
#define I2C1_C2 I2C_C2_REG(I2C1_BASE_PTR)
#define I2C1_FLT I2C_FLT_REG(I2C1_BASE_PTR)
#define I2C1_RA I2C_RA_REG(I2C1_BASE_PTR)
#define I2C1_SMB I2C_SMB_REG(I2C1_BASE_PTR)
#define I2C1_A2 I2C_A2_REG(I2C1_BASE_PTR)
#define I2C1_SLTH I2C_SLTH_REG(I2C1_BASE_PTR)
#define I2C1_SLTL I2C_SLTL_REG(I2C1_BASE_PTR)
/**
* @}
*/ /* end of group I2C_Register_Accessor_Macros */
/**
* @}
*/ /* end of group I2C_Peripheral */
/* ----------------------------------------------------------------------------
-- I2S
---------------------------------------------------------------------------- */
/**
* @addtogroup I2S_Peripheral I2S
* @{
*/
/** I2S - Peripheral register structure */
typedef struct I2S_MemMap {
uint32_t TX0; /**< I2S Transmit Data Registers 0, offset: 0x0 */
uint32_t TX1; /**< I2S Transmit Data Registers 1, offset: 0x4 */
uint32_t RX0; /**< I2S Receive Data Registers 0, offset: 0x8 */
uint32_t RX1; /**< I2S Receive Data Registers 1, offset: 0xC */
uint32_t CR; /**< I2S Control Register, offset: 0x10 */
uint32_t ISR; /**< I2S Interrupt Status Register, offset: 0x14 */
uint32_t IER; /**< I2S Interrupt Enable Register, offset: 0x18 */
uint32_t TCR; /**< I2S Transmit Configuration Register, offset: 0x1C */
uint32_t RCR; /**< I2S Receive Configuration Register, offset: 0x20 */
uint32_t TCCR; /**< I2S Transmit Clock Control Registers, offset: 0x24 */
uint32_t RCCR; /**< I2S Receive Clock Control Registers, offset: 0x28 */
uint32_t FCSR; /**< I2S FIFO Control/Status Register, offset: 0x2C */
uint8_t RESERVED_0[8];
uint32_t ACNT; /**< I2S AC97 Control Register, offset: 0x38 */
uint32_t ACADD; /**< I2S AC97 Command Address Register, offset: 0x3C */
uint32_t ACDAT; /**< I2S AC97 Command Data Register, offset: 0x40 */
uint32_t ATAG; /**< I2S AC97 Tag Register, offset: 0x44 */
uint32_t TMSK; /**< I2S Transmit Time Slot Mask Register, offset: 0x48 */
uint32_t RMSK; /**< I2S Receive Time Slot Mask Register, offset: 0x4C */
uint32_t ACCST; /**< I2S AC97 Channel Status Register, offset: 0x50 */
uint32_t ACCEN; /**< I2S AC97 Channel Enable Register, offset: 0x54 */
uint32_t ACCDIS; /**< I2S AC97 Channel Disable Register, offset: 0x58 */
} volatile *I2S_MemMapPtr;
/* ----------------------------------------------------------------------------
-- I2S - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
* @{
*/
/* I2S - Register accessors */
#define I2S_TX0_REG(base) ((base)->TX0)
#define I2S_TX1_REG(base) ((base)->TX1)
#define I2S_RX0_REG(base) ((base)->RX0)
#define I2S_RX1_REG(base) ((base)->RX1)
#define I2S_CR_REG(base) ((base)->CR)
#define I2S_ISR_REG(base) ((base)->ISR)
#define I2S_IER_REG(base) ((base)->IER)
#define I2S_TCR_REG(base) ((base)->TCR)
#define I2S_RCR_REG(base) ((base)->RCR)
#define I2S_TCCR_REG(base) ((base)->TCCR)
#define I2S_RCCR_REG(base) ((base)->RCCR)
#define I2S_FCSR_REG(base) ((base)->FCSR)
#define I2S_ACNT_REG(base) ((base)->ACNT)
#define I2S_ACADD_REG(base) ((base)->ACADD)
#define I2S_ACDAT_REG(base) ((base)->ACDAT)
#define I2S_ATAG_REG(base) ((base)->ATAG)
#define I2S_TMSK_REG(base) ((base)->TMSK)
#define I2S_RMSK_REG(base) ((base)->RMSK)
#define I2S_ACCST_REG(base) ((base)->ACCST)
#define I2S_ACCEN_REG(base) ((base)->ACCEN)
#define I2S_ACCDIS_REG(base) ((base)->ACCDIS)
/**
* @}
*/ /* end of group I2S_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- I2S Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup I2S_Register_Masks I2S Register Masks
* @{
*/
/* TX0 Bit Fields */
#define I2S_TX0_TX0_MASK 0xFFFFFFFFu
#define I2S_TX0_TX0_SHIFT 0
#define I2S_TX0_TX0(x) (((uint32_t)(((uint32_t)(x))<<I2S_TX0_TX0_SHIFT))&I2S_TX0_TX0_MASK)
/* TX1 Bit Fields */
#define I2S_TX1_TX1_MASK 0xFFFFFFFFu
#define I2S_TX1_TX1_SHIFT 0
#define I2S_TX1_TX1(x) (((uint32_t)(((uint32_t)(x))<<I2S_TX1_TX1_SHIFT))&I2S_TX1_TX1_MASK)
/* RX0 Bit Fields */
#define I2S_RX0_RX0_MASK 0xFFFFFFFFu
#define I2S_RX0_RX0_SHIFT 0
#define I2S_RX0_RX0(x) (((uint32_t)(((uint32_t)(x))<<I2S_RX0_RX0_SHIFT))&I2S_RX0_RX0_MASK)
/* RX1 Bit Fields */
#define I2S_RX1_RX1_MASK 0xFFFFFFFFu
#define I2S_RX1_RX1_SHIFT 0
#define I2S_RX1_RX1(x) (((uint32_t)(((uint32_t)(x))<<I2S_RX1_RX1_SHIFT))&I2S_RX1_RX1_MASK)
/* CR Bit Fields */
#define I2S_CR_I2SEN_MASK 0x1u
#define I2S_CR_I2SEN_SHIFT 0
#define I2S_CR_TE_MASK 0x2u
#define I2S_CR_TE_SHIFT 1
#define I2S_CR_RE_MASK 0x4u
#define I2S_CR_RE_SHIFT 2
#define I2S_CR_NET_MASK 0x8u
#define I2S_CR_NET_SHIFT 3
#define I2S_CR_SYN_MASK 0x10u
#define I2S_CR_SYN_SHIFT 4
#define I2S_CR_I2SMODE_MASK 0x60u
#define I2S_CR_I2SMODE_SHIFT 5
#define I2S_CR_I2SMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_CR_I2SMODE_SHIFT))&I2S_CR_I2SMODE_MASK)
#define I2S_CR_SYSCLKEN_MASK 0x80u
#define I2S_CR_SYSCLKEN_SHIFT 7
#define I2S_CR_TCHEN_MASK 0x100u
#define I2S_CR_TCHEN_SHIFT 8
#define I2S_CR_CLKIST_MASK 0x200u
#define I2S_CR_CLKIST_SHIFT 9
#define I2S_CR_TFRCLKDIS_MASK 0x400u
#define I2S_CR_TFRCLKDIS_SHIFT 10
#define I2S_CR_RFRCLKDIS_MASK 0x800u
#define I2S_CR_RFRCLKDIS_SHIFT 11
#define I2S_CR_SYNCTXFS_MASK 0x1000u
#define I2S_CR_SYNCTXFS_SHIFT 12
/* ISR Bit Fields */
#define I2S_ISR_TFE0_MASK 0x1u
#define I2S_ISR_TFE0_SHIFT 0
#define I2S_ISR_TFE1_MASK 0x2u
#define I2S_ISR_TFE1_SHIFT 1
#define I2S_ISR_RFF0_MASK 0x4u
#define I2S_ISR_RFF0_SHIFT 2
#define I2S_ISR_RFF1_MASK 0x8u
#define I2S_ISR_RFF1_SHIFT 3
#define I2S_ISR_RLS_MASK 0x10u
#define I2S_ISR_RLS_SHIFT 4
#define I2S_ISR_TLS_MASK 0x20u
#define I2S_ISR_TLS_SHIFT 5
#define I2S_ISR_RFS_MASK 0x40u
#define I2S_ISR_RFS_SHIFT 6
#define I2S_ISR_TFS_MASK 0x80u
#define I2S_ISR_TFS_SHIFT 7
#define I2S_ISR_TUE0_MASK 0x100u
#define I2S_ISR_TUE0_SHIFT 8
#define I2S_ISR_TUE1_MASK 0x200u
#define I2S_ISR_TUE1_SHIFT 9
#define I2S_ISR_ROE0_MASK 0x400u
#define I2S_ISR_ROE0_SHIFT 10
#define I2S_ISR_ROE1_MASK 0x800u
#define I2S_ISR_ROE1_SHIFT 11
#define I2S_ISR_TDE0_MASK 0x1000u
#define I2S_ISR_TDE0_SHIFT 12
#define I2S_ISR_TDE1_MASK 0x2000u
#define I2S_ISR_TDE1_SHIFT 13
#define I2S_ISR_RDR0_MASK 0x4000u
#define I2S_ISR_RDR0_SHIFT 14
#define I2S_ISR_RDR1_MASK 0x8000u
#define I2S_ISR_RDR1_SHIFT 15
#define I2S_ISR_RXT_MASK 0x10000u
#define I2S_ISR_RXT_SHIFT 16
#define I2S_ISR_CMDDU_MASK 0x20000u
#define I2S_ISR_CMDDU_SHIFT 17
#define I2S_ISR_CMDAU_MASK 0x40000u
#define I2S_ISR_CMDAU_SHIFT 18
#define I2S_ISR_TRFC_MASK 0x800000u
#define I2S_ISR_TRFC_SHIFT 23
#define I2S_ISR_RFRC_MASK 0x1000000u
#define I2S_ISR_RFRC_SHIFT 24
/* IER Bit Fields */
#define I2S_IER_TFE0EN_MASK 0x1u
#define I2S_IER_TFE0EN_SHIFT 0
#define I2S_IER_TFE1EN_MASK 0x2u
#define I2S_IER_TFE1EN_SHIFT 1
#define I2S_IER_RFF0EN_MASK 0x4u
#define I2S_IER_RFF0EN_SHIFT 2
#define I2S_IER_RFF1EN_MASK 0x8u
#define I2S_IER_RFF1EN_SHIFT 3
#define I2S_IER_RLSEN_MASK 0x10u
#define I2S_IER_RLSEN_SHIFT 4
#define I2S_IER_TLSEN_MASK 0x20u
#define I2S_IER_TLSEN_SHIFT 5
#define I2S_IER_RFSEN_MASK 0x40u
#define I2S_IER_RFSEN_SHIFT 6
#define I2S_IER_TFSEN_MASK 0x80u
#define I2S_IER_TFSEN_SHIFT 7
#define I2S_IER_TUE0EN_MASK 0x100u
#define I2S_IER_TUE0EN_SHIFT 8
#define I2S_IER_TUE1EN_MASK 0x200u
#define I2S_IER_TUE1EN_SHIFT 9
#define I2S_IER_ROE0EN_MASK 0x400u
#define I2S_IER_ROE0EN_SHIFT 10
#define I2S_IER_ROE1EN_MASK 0x800u
#define I2S_IER_ROE1EN_SHIFT 11
#define I2S_IER_TDE0EN_MASK 0x1000u
#define I2S_IER_TDE0EN_SHIFT 12
#define I2S_IER_TDE1EN_MASK 0x2000u
#define I2S_IER_TDE1EN_SHIFT 13
#define I2S_IER_RDR0EN_MASK 0x4000u
#define I2S_IER_RDR0EN_SHIFT 14
#define I2S_IER_RDR1EN_MASK 0x8000u
#define I2S_IER_RDR1EN_SHIFT 15
#define I2S_IER_RXTEN_MASK 0x10000u
#define I2S_IER_RXTEN_SHIFT 16
#define I2S_IER_CMDDUEN_MASK 0x20000u
#define I2S_IER_CMDDUEN_SHIFT 17
#define I2S_IER_CMDAUEN_MASK 0x40000u
#define I2S_IER_CMDAUEN_SHIFT 18
#define I2S_IER_TIE_MASK 0x80000u
#define I2S_IER_TIE_SHIFT 19
#define I2S_IER_TDMAE_MASK 0x100000u
#define I2S_IER_TDMAE_SHIFT 20
#define I2S_IER_RIE_MASK 0x200000u
#define I2S_IER_RIE_SHIFT 21
#define I2S_IER_RDMAE_MASK 0x400000u
#define I2S_IER_RDMAE_SHIFT 22
#define I2S_IER_TFRC_EN_MASK 0x800000u
#define I2S_IER_TFRC_EN_SHIFT 23
#define I2S_IER_RFRC_EN_MASK 0x1000000u
#define I2S_IER_RFRC_EN_SHIFT 24
/* TCR Bit Fields */
#define I2S_TCR_TEFS_MASK 0x1u
#define I2S_TCR_TEFS_SHIFT 0
#define I2S_TCR_TFSL_MASK 0x2u
#define I2S_TCR_TFSL_SHIFT 1
#define I2S_TCR_TFSI_MASK 0x4u
#define I2S_TCR_TFSI_SHIFT 2
#define I2S_TCR_TSCKP_MASK 0x8u
#define I2S_TCR_TSCKP_SHIFT 3
#define I2S_TCR_TSHFD_MASK 0x10u
#define I2S_TCR_TSHFD_SHIFT 4
#define I2S_TCR_TXDIR_MASK 0x20u
#define I2S_TCR_TXDIR_SHIFT 5
#define I2S_TCR_TFDIR_MASK 0x40u
#define I2S_TCR_TFDIR_SHIFT 6
#define I2S_TCR_TFEN0_MASK 0x80u
#define I2S_TCR_TFEN0_SHIFT 7
#define I2S_TCR_TFEN1_MASK 0x100u
#define I2S_TCR_TFEN1_SHIFT 8
#define I2S_TCR_TXBIT0_MASK 0x200u
#define I2S_TCR_TXBIT0_SHIFT 9
/* RCR Bit Fields */
#define I2S_RCR_REFS_MASK 0x1u
#define I2S_RCR_REFS_SHIFT 0
#define I2S_RCR_RFSL_MASK 0x2u
#define I2S_RCR_RFSL_SHIFT 1
#define I2S_RCR_RFSI_MASK 0x4u
#define I2S_RCR_RFSI_SHIFT 2
#define I2S_RCR_RSCKP_MASK 0x8u
#define I2S_RCR_RSCKP_SHIFT 3
#define I2S_RCR_RSHFD_MASK 0x10u
#define I2S_RCR_RSHFD_SHIFT 4
#define I2S_RCR_RXDIR_MASK 0x20u
#define I2S_RCR_RXDIR_SHIFT 5
#define I2S_RCR_RFDIR_MASK 0x40u
#define I2S_RCR_RFDIR_SHIFT 6
#define I2S_RCR_RFEN0_MASK 0x80u
#define I2S_RCR_RFEN0_SHIFT 7
#define I2S_RCR_RFEN1_MASK 0x100u
#define I2S_RCR_RFEN1_SHIFT 8
#define I2S_RCR_RXBIT0_MASK 0x200u
#define I2S_RCR_RXBIT0_SHIFT 9
#define I2S_RCR_RXEXT_MASK 0x400u
#define I2S_RCR_RXEXT_SHIFT 10
/* TCCR Bit Fields */
#define I2S_TCCR_PM_MASK 0xFFu
#define I2S_TCCR_PM_SHIFT 0
#define I2S_TCCR_PM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_PM_SHIFT))&I2S_TCCR_PM_MASK)
#define I2S_TCCR_DC_MASK 0x1F00u
#define I2S_TCCR_DC_SHIFT 8
#define I2S_TCCR_DC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_DC_SHIFT))&I2S_TCCR_DC_MASK)
#define I2S_TCCR_WL_MASK 0x1E000u
#define I2S_TCCR_WL_SHIFT 13
#define I2S_TCCR_WL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_WL_SHIFT))&I2S_TCCR_WL_MASK)
#define I2S_TCCR_PSR_MASK 0x20000u
#define I2S_TCCR_PSR_SHIFT 17
#define I2S_TCCR_DIV2_MASK 0x40000u
#define I2S_TCCR_DIV2_SHIFT 18
/* RCCR Bit Fields */
#define I2S_RCCR_PM_MASK 0xFFu
#define I2S_RCCR_PM_SHIFT 0
#define I2S_RCCR_PM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_PM_SHIFT))&I2S_RCCR_PM_MASK)
#define I2S_RCCR_DC_MASK 0x1F00u
#define I2S_RCCR_DC_SHIFT 8
#define I2S_RCCR_DC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_DC_SHIFT))&I2S_RCCR_DC_MASK)
#define I2S_RCCR_WL_MASK 0x1E000u
#define I2S_RCCR_WL_SHIFT 13
#define I2S_RCCR_WL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_WL_SHIFT))&I2S_RCCR_WL_MASK)
#define I2S_RCCR_PSR_MASK 0x20000u
#define I2S_RCCR_PSR_SHIFT 17
#define I2S_RCCR_DIV2_MASK 0x40000u
#define I2S_RCCR_DIV2_SHIFT 18
/* FCSR Bit Fields */
#define I2S_FCSR_TFWM0_MASK 0xFu
#define I2S_FCSR_TFWM0_SHIFT 0
#define I2S_FCSR_TFWM0(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFWM0_SHIFT))&I2S_FCSR_TFWM0_MASK)
#define I2S_FCSR_RFWM0_MASK 0xF0u
#define I2S_FCSR_RFWM0_SHIFT 4
#define I2S_FCSR_RFWM0(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFWM0_SHIFT))&I2S_FCSR_RFWM0_MASK)
#define I2S_FCSR_TFCNT0_MASK 0xF00u
#define I2S_FCSR_TFCNT0_SHIFT 8
#define I2S_FCSR_TFCNT0(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFCNT0_SHIFT))&I2S_FCSR_TFCNT0_MASK)
#define I2S_FCSR_RFCNT0_MASK 0xF000u
#define I2S_FCSR_RFCNT0_SHIFT 12
#define I2S_FCSR_RFCNT0(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFCNT0_SHIFT))&I2S_FCSR_RFCNT0_MASK)
#define I2S_FCSR_TFWM1_MASK 0xF0000u
#define I2S_FCSR_TFWM1_SHIFT 16
#define I2S_FCSR_TFWM1(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFWM1_SHIFT))&I2S_FCSR_TFWM1_MASK)
#define I2S_FCSR_RFWM1_MASK 0xF00000u
#define I2S_FCSR_RFWM1_SHIFT 20
#define I2S_FCSR_RFWM1(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFWM1_SHIFT))&I2S_FCSR_RFWM1_MASK)
#define I2S_FCSR_TFCNT1_MASK 0xF000000u
#define I2S_FCSR_TFCNT1_SHIFT 24
#define I2S_FCSR_TFCNT1(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFCNT1_SHIFT))&I2S_FCSR_TFCNT1_MASK)
#define I2S_FCSR_RFCNT1_MASK 0xF0000000u
#define I2S_FCSR_RFCNT1_SHIFT 28
#define I2S_FCSR_RFCNT1(x) (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFCNT1_SHIFT))&I2S_FCSR_RFCNT1_MASK)
/* ACNT Bit Fields */
#define I2S_ACNT_AC97EN_MASK 0x1u
#define I2S_ACNT_AC97EN_SHIFT 0
#define I2S_ACNT_FV_MASK 0x2u
#define I2S_ACNT_FV_SHIFT 1
#define I2S_ACNT_TIF_MASK 0x4u
#define I2S_ACNT_TIF_SHIFT 2
#define I2S_ACNT_RD_MASK 0x8u
#define I2S_ACNT_RD_SHIFT 3
#define I2S_ACNT_WR_MASK 0x10u
#define I2S_ACNT_WR_SHIFT 4
#define I2S_ACNT_FRDIV_MASK 0x7E0u
#define I2S_ACNT_FRDIV_SHIFT 5
#define I2S_ACNT_FRDIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACNT_FRDIV_SHIFT))&I2S_ACNT_FRDIV_MASK)
/* ACADD Bit Fields */
#define I2S_ACADD_ACADD_MASK 0x7FFFFu
#define I2S_ACADD_ACADD_SHIFT 0
#define I2S_ACADD_ACADD(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACADD_ACADD_SHIFT))&I2S_ACADD_ACADD_MASK)
/* ACDAT Bit Fields */
#define I2S_ACDAT_ACDAT_MASK 0xFFFFFu
#define I2S_ACDAT_ACDAT_SHIFT 0
#define I2S_ACDAT_ACDAT(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACDAT_ACDAT_SHIFT))&I2S_ACDAT_ACDAT_MASK)
/* ATAG Bit Fields */
#define I2S_ATAG_ATAG_MASK 0xFFFFu
#define I2S_ATAG_ATAG_SHIFT 0
#define I2S_ATAG_ATAG(x) (((uint32_t)(((uint32_t)(x))<<I2S_ATAG_ATAG_SHIFT))&I2S_ATAG_ATAG_MASK)
/* TMSK Bit Fields */
#define I2S_TMSK_TMSK_MASK 0xFFFFFFFFu
#define I2S_TMSK_TMSK_SHIFT 0
#define I2S_TMSK_TMSK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMSK_TMSK_SHIFT))&I2S_TMSK_TMSK_MASK)
/* RMSK Bit Fields */
#define I2S_RMSK_RMSK_MASK 0xFFFFFFFFu
#define I2S_RMSK_RMSK_SHIFT 0
#define I2S_RMSK_RMSK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMSK_RMSK_SHIFT))&I2S_RMSK_RMSK_MASK)
/* ACCST Bit Fields */
#define I2S_ACCST_ACCST_MASK 0x3FFu
#define I2S_ACCST_ACCST_SHIFT 0
#define I2S_ACCST_ACCST(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACCST_ACCST_SHIFT))&I2S_ACCST_ACCST_MASK)
/* ACCEN Bit Fields */
#define I2S_ACCEN_ACCEN_MASK 0x3FFu
#define I2S_ACCEN_ACCEN_SHIFT 0
#define I2S_ACCEN_ACCEN(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACCEN_ACCEN_SHIFT))&I2S_ACCEN_ACCEN_MASK)
/* ACCDIS Bit Fields */
#define I2S_ACCDIS_ACCDIS_MASK 0x3FFu
#define I2S_ACCDIS_ACCDIS_SHIFT 0
#define I2S_ACCDIS_ACCDIS(x) (((uint32_t)(((uint32_t)(x))<<I2S_ACCDIS_ACCDIS_SHIFT))&I2S_ACCDIS_ACCDIS_MASK)
/**
* @}
*/ /* end of group I2S_Register_Masks */
/* I2S - Peripheral instance base addresses */
/** Peripheral I2S0 base pointer */
#define I2S0_BASE_PTR ((I2S_MemMapPtr)0x4002F000u)
/* ----------------------------------------------------------------------------
-- I2S - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
* @{
*/
/* I2S - Register instance definitions */
/* I2S0 */
#define I2S0_TX0 I2S_TX0_REG(I2S0_BASE_PTR)
#define I2S0_TX1 I2S_TX1_REG(I2S0_BASE_PTR)
#define I2S0_RX0 I2S_RX0_REG(I2S0_BASE_PTR)
#define I2S0_RX1 I2S_RX1_REG(I2S0_BASE_PTR)
#define I2S0_CR I2S_CR_REG(I2S0_BASE_PTR)
#define I2S0_ISR I2S_ISR_REG(I2S0_BASE_PTR)
#define I2S0_IER I2S_IER_REG(I2S0_BASE_PTR)
#define I2S0_TCR I2S_TCR_REG(I2S0_BASE_PTR)
#define I2S0_RCR I2S_RCR_REG(I2S0_BASE_PTR)
#define I2S0_TCCR I2S_TCCR_REG(I2S0_BASE_PTR)
#define I2S0_RCCR I2S_RCCR_REG(I2S0_BASE_PTR)
#define I2S0_FCSR I2S_FCSR_REG(I2S0_BASE_PTR)
#define I2S0_ACNT I2S_ACNT_REG(I2S0_BASE_PTR)
#define I2S0_ACADD I2S_ACADD_REG(I2S0_BASE_PTR)
#define I2S0_ACDAT I2S_ACDAT_REG(I2S0_BASE_PTR)
#define I2S0_ATAG I2S_ATAG_REG(I2S0_BASE_PTR)
#define I2S0_TMSK I2S_TMSK_REG(I2S0_BASE_PTR)
#define I2S0_RMSK I2S_RMSK_REG(I2S0_BASE_PTR)
#define I2S0_ACCST I2S_ACCST_REG(I2S0_BASE_PTR)
#define I2S0_ACCEN I2S_ACCEN_REG(I2S0_BASE_PTR)
#define I2S0_ACCDIS I2S_ACCDIS_REG(I2S0_BASE_PTR)
/**
* @}
*/ /* end of group I2S_Register_Accessor_Macros */
/**
* @}
*/ /* end of group I2S_Peripheral */
/* ----------------------------------------------------------------------------
-- ITM
---------------------------------------------------------------------------- */
/**
* @addtogroup ITM_Peripheral ITM
* @{
*/
/** ITM - Peripheral register structure */
typedef struct ITM_MemMap {
union { /* offset: 0x0 */
uint32_t STIM_READ[32]; /**< Stimulus Port Register 0 (for reading)..Stimulus Port Register 31 (for reading), array offset: 0x0, array step: 0x4 */
uint32_t STIM_WRITE[32]; /**< Stimulus Port Register 0 (for writing)..Stimulus Port Register 31 (for writing), array offset: 0x0, array step: 0x4 */
};
uint8_t RESERVED_0[3456];
uint32_t TER; /**< Trace Enable Register, offset: 0xE00 */
uint8_t RESERVED_1[60];
uint32_t TPR; /**< Trace Privilege Register, offset: 0xE40 */
uint8_t RESERVED_2[60];
uint32_t TCR; /**< Trace Control Register, offset: 0xE80 */
uint8_t RESERVED_3[300];
uint32_t LAR; /**< Lock Access Register, offset: 0xFB0 */
uint32_t LSR; /**< Lock Status Register, offset: 0xFB4 */
uint8_t RESERVED_4[24];
uint32_t PID4; /**< Peripheral Identification Register 4., offset: 0xFD0 */
uint32_t PID5; /**< Peripheral Identification Register 5., offset: 0xFD4 */
uint32_t PID6; /**< Peripheral Identification Register 6., offset: 0xFD8 */
uint32_t PID7; /**< Peripheral Identification Register 7., offset: 0xFDC */
uint32_t PID0; /**< Peripheral Identification Register 0., offset: 0xFE0 */
uint32_t PID1; /**< Peripheral Identification Register 1., offset: 0xFE4 */
uint32_t PID2; /**< Peripheral Identification Register 2., offset: 0xFE8 */
uint32_t PID3; /**< Peripheral Identification Register 3., offset: 0xFEC */
uint32_t CID0; /**< Component Identification Register 0., offset: 0xFF0 */
uint32_t CID1; /**< Component Identification Register 1., offset: 0xFF4 */
uint32_t CID2; /**< Component Identification Register 2., offset: 0xFF8 */
uint32_t CID3; /**< Component Identification Register 3., offset: 0xFFC */
} volatile *ITM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- ITM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup ITM_Register_Accessor_Macros ITM - Register accessor macros
* @{
*/
/* ITM - Register accessors */
#define ITM_STIM_READ_REG(base,index2) ((base)->STIM_READ[index2])
#define ITM_STIM_WRITE_REG(base,index2) ((base)->STIM_WRITE[index2])
#define ITM_TER_REG(base) ((base)->TER)
#define ITM_TPR_REG(base) ((base)->TPR)
#define ITM_TCR_REG(base) ((base)->TCR)
#define ITM_LAR_REG(base) ((base)->LAR)
#define ITM_LSR_REG(base) ((base)->LSR)
#define ITM_PID4_REG(base) ((base)->PID4)
#define ITM_PID5_REG(base) ((base)->PID5)
#define ITM_PID6_REG(base) ((base)->PID6)
#define ITM_PID7_REG(base) ((base)->PID7)
#define ITM_PID0_REG(base) ((base)->PID0)
#define ITM_PID1_REG(base) ((base)->PID1)
#define ITM_PID2_REG(base) ((base)->PID2)
#define ITM_PID3_REG(base) ((base)->PID3)
#define ITM_CID0_REG(base) ((base)->CID0)
#define ITM_CID1_REG(base) ((base)->CID1)
#define ITM_CID2_REG(base) ((base)->CID2)
#define ITM_CID3_REG(base) ((base)->CID3)
/**
* @}
*/ /* end of group ITM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- ITM Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup ITM_Register_Masks ITM Register Masks
* @{
*/
/**
* @}
*/ /* end of group ITM_Register_Masks */
/* ITM - Peripheral instance base addresses */
/** Peripheral ITM base pointer */
#define ITM_BASE_PTR ((ITM_MemMapPtr)0xE0000000u)
/* ----------------------------------------------------------------------------
-- ITM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup ITM_Register_Accessor_Macros ITM - Register accessor macros
* @{
*/
/* ITM - Register instance definitions */
/* ITM */
#define ITM_STIM0_READ ITM_STIM_READ_REG(ITM_BASE_PTR,0)
#define ITM_STIM0_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,0)
#define ITM_STIM1_READ ITM_STIM_READ_REG(ITM_BASE_PTR,1)
#define ITM_STIM1_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,1)
#define ITM_STIM2_READ ITM_STIM_READ_REG(ITM_BASE_PTR,2)
#define ITM_STIM2_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,2)
#define ITM_STIM3_READ ITM_STIM_READ_REG(ITM_BASE_PTR,3)
#define ITM_STIM3_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,3)
#define ITM_STIM4_READ ITM_STIM_READ_REG(ITM_BASE_PTR,4)
#define ITM_STIM4_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,4)
#define ITM_STIM5_READ ITM_STIM_READ_REG(ITM_BASE_PTR,5)
#define ITM_STIM5_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,5)
#define ITM_STIM6_READ ITM_STIM_READ_REG(ITM_BASE_PTR,6)
#define ITM_STIM6_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,6)
#define ITM_STIM7_READ ITM_STIM_READ_REG(ITM_BASE_PTR,7)
#define ITM_STIM7_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,7)
#define ITM_STIM8_READ ITM_STIM_READ_REG(ITM_BASE_PTR,8)
#define ITM_STIM8_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,8)
#define ITM_STIM9_READ ITM_STIM_READ_REG(ITM_BASE_PTR,9)
#define ITM_STIM9_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,9)
#define ITM_STIM10_READ ITM_STIM_READ_REG(ITM_BASE_PTR,10)
#define ITM_STIM10_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,10)
#define ITM_STIM11_READ ITM_STIM_READ_REG(ITM_BASE_PTR,11)
#define ITM_STIM11_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,11)
#define ITM_STIM12_READ ITM_STIM_READ_REG(ITM_BASE_PTR,12)
#define ITM_STIM12_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,12)
#define ITM_STIM13_READ ITM_STIM_READ_REG(ITM_BASE_PTR,13)
#define ITM_STIM13_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,13)
#define ITM_STIM14_READ ITM_STIM_READ_REG(ITM_BASE_PTR,14)
#define ITM_STIM14_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,14)
#define ITM_STIM15_READ ITM_STIM_READ_REG(ITM_BASE_PTR,15)
#define ITM_STIM15_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,15)
#define ITM_STIM16_READ ITM_STIM_READ_REG(ITM_BASE_PTR,16)
#define ITM_STIM16_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,16)
#define ITM_STIM17_READ ITM_STIM_READ_REG(ITM_BASE_PTR,17)
#define ITM_STIM17_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,17)
#define ITM_STIM18_READ ITM_STIM_READ_REG(ITM_BASE_PTR,18)
#define ITM_STIM18_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,18)
#define ITM_STIM19_READ ITM_STIM_READ_REG(ITM_BASE_PTR,19)
#define ITM_STIM19_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,19)
#define ITM_STIM20_READ ITM_STIM_READ_REG(ITM_BASE_PTR,20)
#define ITM_STIM20_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,20)
#define ITM_STIM21_READ ITM_STIM_READ_REG(ITM_BASE_PTR,21)
#define ITM_STIM21_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,21)
#define ITM_STIM22_READ ITM_STIM_READ_REG(ITM_BASE_PTR,22)
#define ITM_STIM22_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,22)
#define ITM_STIM23_READ ITM_STIM_READ_REG(ITM_BASE_PTR,23)
#define ITM_STIM23_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,23)
#define ITM_STIM24_READ ITM_STIM_READ_REG(ITM_BASE_PTR,24)
#define ITM_STIM24_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,24)
#define ITM_STIM25_READ ITM_STIM_READ_REG(ITM_BASE_PTR,25)
#define ITM_STIM25_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,25)
#define ITM_STIM26_READ ITM_STIM_READ_REG(ITM_BASE_PTR,26)
#define ITM_STIM26_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,26)
#define ITM_STIM27_READ ITM_STIM_READ_REG(ITM_BASE_PTR,27)
#define ITM_STIM27_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,27)
#define ITM_STIM28_READ ITM_STIM_READ_REG(ITM_BASE_PTR,28)
#define ITM_STIM28_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,28)
#define ITM_STIM29_READ ITM_STIM_READ_REG(ITM_BASE_PTR,29)
#define ITM_STIM29_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,29)
#define ITM_STIM30_READ ITM_STIM_READ_REG(ITM_BASE_PTR,30)
#define ITM_STIM30_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,30)
#define ITM_STIM31_READ ITM_STIM_READ_REG(ITM_BASE_PTR,31)
#define ITM_STIM31_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,31)
#define ITM_TER ITM_TER_REG(ITM_BASE_PTR)
#define ITM_TPR ITM_TPR_REG(ITM_BASE_PTR)
#define ITM_TCR ITM_TCR_REG(ITM_BASE_PTR)
#define ITM_LAR ITM_LAR_REG(ITM_BASE_PTR)
#define ITM_LSR ITM_LSR_REG(ITM_BASE_PTR)
#define ITM_PID4 ITM_PID4_REG(ITM_BASE_PTR)
#define ITM_PID5 ITM_PID5_REG(ITM_BASE_PTR)
#define ITM_PID6 ITM_PID6_REG(ITM_BASE_PTR)
#define ITM_PID7 ITM_PID7_REG(ITM_BASE_PTR)
#define ITM_PID0 ITM_PID0_REG(ITM_BASE_PTR)
#define ITM_PID1 ITM_PID1_REG(ITM_BASE_PTR)
#define ITM_PID2 ITM_PID2_REG(ITM_BASE_PTR)
#define ITM_PID3 ITM_PID3_REG(ITM_BASE_PTR)
#define ITM_CID0 ITM_CID0_REG(ITM_BASE_PTR)
#define ITM_CID1 ITM_CID1_REG(ITM_BASE_PTR)
#define ITM_CID2 ITM_CID2_REG(ITM_BASE_PTR)
#define ITM_CID3 ITM_CID3_REG(ITM_BASE_PTR)
/* ITM - Register array accessors */
#define ITM_STIM_READ(index2) ITM_STIM_READ_REG(ITM_BASE_PTR,index2)
#define ITM_STIM_WRITE(index2) ITM_STIM_WRITE_REG(ITM_BASE_PTR,index2)
/**
* @}
*/ /* end of group ITM_Register_Accessor_Macros */
/**
* @}
*/ /* end of group ITM_Peripheral */
/* ----------------------------------------------------------------------------
-- LLWU
---------------------------------------------------------------------------- */
/**
* @addtogroup LLWU_Peripheral LLWU
* @{
*/
/** LLWU - Peripheral register structure */
typedef struct LLWU_MemMap {
uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
uint8_t CS; /**< LLWU Control and Status Register, offset: 0x8 */
} volatile *LLWU_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LLWU - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
* @{
*/
/* LLWU - Register accessors */
#define LLWU_PE1_REG(base) ((base)->PE1)
#define LLWU_PE2_REG(base) ((base)->PE2)
#define LLWU_PE3_REG(base) ((base)->PE3)
#define LLWU_PE4_REG(base) ((base)->PE4)
#define LLWU_ME_REG(base) ((base)->ME)
#define LLWU_F1_REG(base) ((base)->F1)
#define LLWU_F2_REG(base) ((base)->F2)
#define LLWU_F3_REG(base) ((base)->F3)
#define LLWU_CS_REG(base) ((base)->CS)
/**
* @}
*/ /* end of group LLWU_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LLWU Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup LLWU_Register_Masks LLWU Register Masks
* @{
*/
/* PE1 Bit Fields */
#define LLWU_PE1_WUPE0_MASK 0x3u
#define LLWU_PE1_WUPE0_SHIFT 0
#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
#define LLWU_PE1_WUPE1_MASK 0xCu
#define LLWU_PE1_WUPE1_SHIFT 2
#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
#define LLWU_PE1_WUPE2_MASK 0x30u
#define LLWU_PE1_WUPE2_SHIFT 4
#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
#define LLWU_PE1_WUPE3_MASK 0xC0u
#define LLWU_PE1_WUPE3_SHIFT 6
#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
/* PE2 Bit Fields */
#define LLWU_PE2_WUPE4_MASK 0x3u
#define LLWU_PE2_WUPE4_SHIFT 0
#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
#define LLWU_PE2_WUPE5_MASK 0xCu
#define LLWU_PE2_WUPE5_SHIFT 2
#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
#define LLWU_PE2_WUPE6_MASK 0x30u
#define LLWU_PE2_WUPE6_SHIFT 4
#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
#define LLWU_PE2_WUPE7_MASK 0xC0u
#define LLWU_PE2_WUPE7_SHIFT 6
#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
/* PE3 Bit Fields */
#define LLWU_PE3_WUPE8_MASK 0x3u
#define LLWU_PE3_WUPE8_SHIFT 0
#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
#define LLWU_PE3_WUPE9_MASK 0xCu
#define LLWU_PE3_WUPE9_SHIFT 2
#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
#define LLWU_PE3_WUPE10_MASK 0x30u
#define LLWU_PE3_WUPE10_SHIFT 4
#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
#define LLWU_PE3_WUPE11_MASK 0xC0u
#define LLWU_PE3_WUPE11_SHIFT 6
#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
/* PE4 Bit Fields */
#define LLWU_PE4_WUPE12_MASK 0x3u
#define LLWU_PE4_WUPE12_SHIFT 0
#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
#define LLWU_PE4_WUPE13_MASK 0xCu
#define LLWU_PE4_WUPE13_SHIFT 2
#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
#define LLWU_PE4_WUPE14_MASK 0x30u
#define LLWU_PE4_WUPE14_SHIFT 4
#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
#define LLWU_PE4_WUPE15_MASK 0xC0u
#define LLWU_PE4_WUPE15_SHIFT 6
#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
/* ME Bit Fields */
#define LLWU_ME_WUME0_MASK 0x1u
#define LLWU_ME_WUME0_SHIFT 0
#define LLWU_ME_WUME1_MASK 0x2u
#define LLWU_ME_WUME1_SHIFT 1
#define LLWU_ME_WUME2_MASK 0x4u
#define LLWU_ME_WUME2_SHIFT 2
#define LLWU_ME_WUME3_MASK 0x8u
#define LLWU_ME_WUME3_SHIFT 3
#define LLWU_ME_WUME4_MASK 0x10u
#define LLWU_ME_WUME4_SHIFT 4
#define LLWU_ME_WUME5_MASK 0x20u
#define LLWU_ME_WUME5_SHIFT 5
#define LLWU_ME_WUME6_MASK 0x40u
#define LLWU_ME_WUME6_SHIFT 6
#define LLWU_ME_WUME7_MASK 0x80u
#define LLWU_ME_WUME7_SHIFT 7
/* F1 Bit Fields */
#define LLWU_F1_WUF0_MASK 0x1u
#define LLWU_F1_WUF0_SHIFT 0
#define LLWU_F1_WUF1_MASK 0x2u
#define LLWU_F1_WUF1_SHIFT 1
#define LLWU_F1_WUF2_MASK 0x4u
#define LLWU_F1_WUF2_SHIFT 2
#define LLWU_F1_WUF3_MASK 0x8u
#define LLWU_F1_WUF3_SHIFT 3
#define LLWU_F1_WUF4_MASK 0x10u
#define LLWU_F1_WUF4_SHIFT 4
#define LLWU_F1_WUF5_MASK 0x20u
#define LLWU_F1_WUF5_SHIFT 5
#define LLWU_F1_WUF6_MASK 0x40u
#define LLWU_F1_WUF6_SHIFT 6
#define LLWU_F1_WUF7_MASK 0x80u
#define LLWU_F1_WUF7_SHIFT 7
/* F2 Bit Fields */
#define LLWU_F2_WUF8_MASK 0x1u
#define LLWU_F2_WUF8_SHIFT 0
#define LLWU_F2_WUF9_MASK 0x2u
#define LLWU_F2_WUF9_SHIFT 1
#define LLWU_F2_WUF10_MASK 0x4u
#define LLWU_F2_WUF10_SHIFT 2
#define LLWU_F2_WUF11_MASK 0x8u
#define LLWU_F2_WUF11_SHIFT 3
#define LLWU_F2_WUF12_MASK 0x10u
#define LLWU_F2_WUF12_SHIFT 4
#define LLWU_F2_WUF13_MASK 0x20u
#define LLWU_F2_WUF13_SHIFT 5
#define LLWU_F2_WUF14_MASK 0x40u
#define LLWU_F2_WUF14_SHIFT 6
#define LLWU_F2_WUF15_MASK 0x80u
#define LLWU_F2_WUF15_SHIFT 7
/* F3 Bit Fields */
#define LLWU_F3_MWUF0_MASK 0x1u
#define LLWU_F3_MWUF0_SHIFT 0
#define LLWU_F3_MWUF1_MASK 0x2u
#define LLWU_F3_MWUF1_SHIFT 1
#define LLWU_F3_MWUF2_MASK 0x4u
#define LLWU_F3_MWUF2_SHIFT 2
#define LLWU_F3_MWUF3_MASK 0x8u
#define LLWU_F3_MWUF3_SHIFT 3
#define LLWU_F3_MWUF4_MASK 0x10u
#define LLWU_F3_MWUF4_SHIFT 4
#define LLWU_F3_MWUF5_MASK 0x20u
#define LLWU_F3_MWUF5_SHIFT 5
#define LLWU_F3_MWUF6_MASK 0x40u
#define LLWU_F3_MWUF6_SHIFT 6
#define LLWU_F3_MWUF7_MASK 0x80u
#define LLWU_F3_MWUF7_SHIFT 7
/* CS Bit Fields */
#define LLWU_CS_FLTR_MASK 0x1u
#define LLWU_CS_FLTR_SHIFT 0
#define LLWU_CS_FLTEP_MASK 0x2u
#define LLWU_CS_FLTEP_SHIFT 1
#define LLWU_CS_ACKISO_MASK 0x80u
#define LLWU_CS_ACKISO_SHIFT 7
/**
* @}
*/ /* end of group LLWU_Register_Masks */
/* LLWU - Peripheral instance base addresses */
/** Peripheral LLWU base pointer */
#define LLWU_BASE_PTR ((LLWU_MemMapPtr)0x4007C000u)
/* ----------------------------------------------------------------------------
-- LLWU - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
* @{
*/
/* LLWU - Register instance definitions */
/* LLWU */
#define LLWU_PE1 LLWU_PE1_REG(LLWU_BASE_PTR)
#define LLWU_PE2 LLWU_PE2_REG(LLWU_BASE_PTR)
#define LLWU_PE3 LLWU_PE3_REG(LLWU_BASE_PTR)
#define LLWU_PE4 LLWU_PE4_REG(LLWU_BASE_PTR)
#define LLWU_ME LLWU_ME_REG(LLWU_BASE_PTR)
#define LLWU_F1 LLWU_F1_REG(LLWU_BASE_PTR)
#define LLWU_F2 LLWU_F2_REG(LLWU_BASE_PTR)
#define LLWU_F3 LLWU_F3_REG(LLWU_BASE_PTR)
#define LLWU_CS LLWU_CS_REG(LLWU_BASE_PTR)
/**
* @}
*/ /* end of group LLWU_Register_Accessor_Macros */
/**
* @}
*/ /* end of group LLWU_Peripheral */
/* ----------------------------------------------------------------------------
-- LPTMR
---------------------------------------------------------------------------- */
/**
* @addtogroup LPTMR_Peripheral LPTMR
* @{
*/
/** LPTMR - Peripheral register structure */
typedef struct LPTMR_MemMap {
uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
} volatile *LPTMR_MemMapPtr;
/* ----------------------------------------------------------------------------
-- LPTMR - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
* @{
*/
/* LPTMR - Register accessors */
#define LPTMR_CSR_REG(base) ((base)->CSR)
#define LPTMR_PSR_REG(base) ((base)->PSR)
#define LPTMR_CMR_REG(base) ((base)->CMR)
#define LPTMR_CNR_REG(base) ((base)->CNR)
/**
* @}
*/ /* end of group LPTMR_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- LPTMR Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
* @{
*/
/* CSR Bit Fields */
#define LPTMR_CSR_TEN_MASK 0x1u
#define LPTMR_CSR_TEN_SHIFT 0
#define LPTMR_CSR_TMS_MASK 0x2u
#define LPTMR_CSR_TMS_SHIFT 1
#define LPTMR_CSR_TFC_MASK 0x4u
#define LPTMR_CSR_TFC_SHIFT 2
#define LPTMR_CSR_TPP_MASK 0x8u
#define LPTMR_CSR_TPP_SHIFT 3
#define LPTMR_CSR_TPS_MASK 0x30u
#define LPTMR_CSR_TPS_SHIFT 4
#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
#define LPTMR_CSR_TIE_MASK 0x40u
#define LPTMR_CSR_TIE_SHIFT 6
#define LPTMR_CSR_TCF_MASK 0x80u
#define LPTMR_CSR_TCF_SHIFT 7
/* PSR Bit Fields */
#define LPTMR_PSR_PCS_MASK 0x3u
#define LPTMR_PSR_PCS_SHIFT 0
#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
#define LPTMR_PSR_PBYP_MASK 0x4u
#define LPTMR_PSR_PBYP_SHIFT 2
#define LPTMR_PSR_PRESCALE_MASK 0x78u
#define LPTMR_PSR_PRESCALE_SHIFT 3
#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
/* CMR Bit Fields */
#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
#define LPTMR_CMR_COMPARE_SHIFT 0
#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
/* CNR Bit Fields */
#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
#define LPTMR_CNR_COUNTER_SHIFT 0
#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
/**
* @}
*/ /* end of group LPTMR_Register_Masks */
/* LPTMR - Peripheral instance base addresses */
/** Peripheral LPTMR0 base pointer */
#define LPTMR0_BASE_PTR ((LPTMR_MemMapPtr)0x40040000u)
/* ----------------------------------------------------------------------------
-- LPTMR - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
* @{
*/
/* LPTMR - Register instance definitions */
/* LPTMR0 */
#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0_BASE_PTR)
#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0_BASE_PTR)
#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0_BASE_PTR)
#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0_BASE_PTR)
/**
* @}
*/ /* end of group LPTMR_Register_Accessor_Macros */
/**
* @}
*/ /* end of group LPTMR_Peripheral */
/* ----------------------------------------------------------------------------
-- MC
---------------------------------------------------------------------------- */
/**
* @addtogroup MC_Peripheral MC
* @{
*/
/** MC - Peripheral register structure */
typedef struct MC_MemMap {
uint8_t SRSH; /**< System Reset Status Register High, offset: 0x0 */
uint8_t SRSL; /**< System Reset Status Register Low, offset: 0x1 */
uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x2 */
uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x3 */
} volatile *MC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- MC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup MC_Register_Accessor_Macros MC - Register accessor macros
* @{
*/
/* MC - Register accessors */
#define MC_SRSH_REG(base) ((base)->SRSH)
#define MC_SRSL_REG(base) ((base)->SRSL)
#define MC_PMPROT_REG(base) ((base)->PMPROT)
#define MC_PMCTRL_REG(base) ((base)->PMCTRL)
/**
* @}
*/ /* end of group MC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- MC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup MC_Register_Masks MC Register Masks
* @{
*/
/* SRSH Bit Fields */
#define MC_SRSH_JTAG_MASK 0x1u
#define MC_SRSH_JTAG_SHIFT 0
#define MC_SRSH_LOCKUP_MASK 0x2u
#define MC_SRSH_LOCKUP_SHIFT 1
#define MC_SRSH_SW_MASK 0x4u
#define MC_SRSH_SW_SHIFT 2
/* SRSL Bit Fields */
#define MC_SRSL_WAKEUP_MASK 0x1u
#define MC_SRSL_WAKEUP_SHIFT 0
#define MC_SRSL_LVD_MASK 0x2u
#define MC_SRSL_LVD_SHIFT 1
#define MC_SRSL_LOC_MASK 0x4u
#define MC_SRSL_LOC_SHIFT 2
#define MC_SRSL_COP_MASK 0x20u
#define MC_SRSL_COP_SHIFT 5
#define MC_SRSL_PIN_MASK 0x40u
#define MC_SRSL_PIN_SHIFT 6
#define MC_SRSL_POR_MASK 0x80u
#define MC_SRSL_POR_SHIFT 7
/* PMPROT Bit Fields */
#define MC_PMPROT_AVLLS1_MASK 0x1u
#define MC_PMPROT_AVLLS1_SHIFT 0
#define MC_PMPROT_AVLLS2_MASK 0x2u
#define MC_PMPROT_AVLLS2_SHIFT 1
#define MC_PMPROT_AVLLS3_MASK 0x4u
#define MC_PMPROT_AVLLS3_SHIFT 2
#define MC_PMPROT_ALLS_MASK 0x10u
#define MC_PMPROT_ALLS_SHIFT 4
#define MC_PMPROT_AVLP_MASK 0x20u
#define MC_PMPROT_AVLP_SHIFT 5
/* PMCTRL Bit Fields */
#define MC_PMCTRL_LPLLSM_MASK 0x7u
#define MC_PMCTRL_LPLLSM_SHIFT 0
#define MC_PMCTRL_LPLLSM(x) (((uint8_t)(((uint8_t)(x))<<MC_PMCTRL_LPLLSM_SHIFT))&MC_PMCTRL_LPLLSM_MASK)
#define MC_PMCTRL_RUNM_MASK 0x60u
#define MC_PMCTRL_RUNM_SHIFT 5
#define MC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<MC_PMCTRL_RUNM_SHIFT))&MC_PMCTRL_RUNM_MASK)
#define MC_PMCTRL_LPWUI_MASK 0x80u
#define MC_PMCTRL_LPWUI_SHIFT 7
/**
* @}
*/ /* end of group MC_Register_Masks */
/* MC - Peripheral instance base addresses */
/** Peripheral MC base pointer */
#define MC_BASE_PTR ((MC_MemMapPtr)0x4007E000u)
/* ----------------------------------------------------------------------------
-- MC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup MC_Register_Accessor_Macros MC - Register accessor macros
* @{
*/
/* MC - Register instance definitions */
/* MC */
#define MC_SRSH MC_SRSH_REG(MC_BASE_PTR)
#define MC_SRSL MC_SRSL_REG(MC_BASE_PTR)
#define MC_PMPROT MC_PMPROT_REG(MC_BASE_PTR)
#define MC_PMCTRL MC_PMCTRL_REG(MC_BASE_PTR)
/**
* @}
*/ /* end of group MC_Register_Accessor_Macros */
/**
* @}
*/ /* end of group MC_Peripheral */
/* ----------------------------------------------------------------------------
-- MCG
---------------------------------------------------------------------------- */
/**
* @addtogroup MCG_Peripheral MCG
* @{
*/
/** MCG - Peripheral register structure */
typedef struct MCG_MemMap {
uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
uint8_t S; /**< MCG Status Register, offset: 0x6 */
uint8_t RESERVED_0[1];
uint8_t ATC; /**< MCG Auto Trim Control Register, offset: 0x8 */
uint8_t RESERVED_1[1];
uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
} volatile *MCG_MemMapPtr;
/* ----------------------------------------------------------------------------
-- MCG - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
* @{
*/
/* MCG - Register accessors */
#define MCG_C1_REG(base) ((base)->C1)
#define MCG_C2_REG(base) ((base)->C2)
#define MCG_C3_REG(base) ((base)->C3)
#define MCG_C4_REG(base) ((base)->C4)
#define MCG_C5_REG(base) ((base)->C5)
#define MCG_C6_REG(base) ((base)->C6)
#define MCG_S_REG(base) ((base)->S)
#define MCG_ATC_REG(base) ((base)->ATC)
#define MCG_ATCVH_REG(base) ((base)->ATCVH)
#define MCG_ATCVL_REG(base) ((base)->ATCVL)
/**
* @}
*/ /* end of group MCG_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- MCG Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup MCG_Register_Masks MCG Register Masks
* @{
*/
/* C1 Bit Fields */
#define MCG_C1_IREFSTEN_MASK 0x1u
#define MCG_C1_IREFSTEN_SHIFT 0
#define MCG_C1_IRCLKEN_MASK 0x2u
#define MCG_C1_IRCLKEN_SHIFT 1
#define MCG_C1_IREFS_MASK 0x4u
#define MCG_C1_IREFS_SHIFT 2
#define MCG_C1_FRDIV_MASK 0x38u
#define MCG_C1_FRDIV_SHIFT 3
#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
#define MCG_C1_CLKS_MASK 0xC0u
#define MCG_C1_CLKS_SHIFT 6
#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
/* C2 Bit Fields */
#define MCG_C2_IRCS_MASK 0x1u
#define MCG_C2_IRCS_SHIFT 0
#define MCG_C2_LP_MASK 0x2u
#define MCG_C2_LP_SHIFT 1
#define MCG_C2_EREFS_MASK 0x4u
#define MCG_C2_EREFS_SHIFT 2
#define MCG_C2_HGO_MASK 0x8u
#define MCG_C2_HGO_SHIFT 3
#define MCG_C2_RANGE_MASK 0x30u
#define MCG_C2_RANGE_SHIFT 4
#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
/* C3 Bit Fields */
#define MCG_C3_SCTRIM_MASK 0xFFu
#define MCG_C3_SCTRIM_SHIFT 0
#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
/* C4 Bit Fields */
#define MCG_C4_SCFTRIM_MASK 0x1u
#define MCG_C4_SCFTRIM_SHIFT 0
#define MCG_C4_FCTRIM_MASK 0x1Eu
#define MCG_C4_FCTRIM_SHIFT 1
#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
#define MCG_C4_DRST_DRS_MASK 0x60u
#define MCG_C4_DRST_DRS_SHIFT 5
#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
#define MCG_C4_DMX32_MASK 0x80u
#define MCG_C4_DMX32_SHIFT 7
/* C5 Bit Fields */
#define MCG_C5_PRDIV_MASK 0x1Fu
#define MCG_C5_PRDIV_SHIFT 0
#define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV_SHIFT))&MCG_C5_PRDIV_MASK)
#define MCG_C5_PLLSTEN_MASK 0x20u
#define MCG_C5_PLLSTEN_SHIFT 5
#define MCG_C5_PLLCLKEN_MASK 0x40u
#define MCG_C5_PLLCLKEN_SHIFT 6
/* C6 Bit Fields */
#define MCG_C6_VDIV_MASK 0x1Fu
#define MCG_C6_VDIV_SHIFT 0
#define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV_SHIFT))&MCG_C6_VDIV_MASK)
#define MCG_C6_CME_MASK 0x20u
#define MCG_C6_CME_SHIFT 5
#define MCG_C6_PLLS_MASK 0x40u
#define MCG_C6_PLLS_SHIFT 6
#define MCG_C6_LOLIE_MASK 0x80u
#define MCG_C6_LOLIE_SHIFT 7
/* S Bit Fields */
#define MCG_S_IRCST_MASK 0x1u
#define MCG_S_IRCST_SHIFT 0
#define MCG_S_OSCINIT_MASK 0x2u
#define MCG_S_OSCINIT_SHIFT 1
#define MCG_S_CLKST_MASK 0xCu
#define MCG_S_CLKST_SHIFT 2
#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
#define MCG_S_IREFST_MASK 0x10u
#define MCG_S_IREFST_SHIFT 4
#define MCG_S_PLLST_MASK 0x20u
#define MCG_S_PLLST_SHIFT 5
#define MCG_S_LOCK_MASK 0x40u
#define MCG_S_LOCK_SHIFT 6
#define MCG_S_LOLS_MASK 0x80u
#define MCG_S_LOLS_SHIFT 7
/* ATC Bit Fields */
#define MCG_ATC_ATMF_MASK 0x20u
#define MCG_ATC_ATMF_SHIFT 5
#define MCG_ATC_ATMS_MASK 0x40u
#define MCG_ATC_ATMS_SHIFT 6
#define MCG_ATC_ATME_MASK 0x80u
#define MCG_ATC_ATME_SHIFT 7
/* ATCVH Bit Fields */
#define MCG_ATCVH_ATCVH_MASK 0xFFu
#define MCG_ATCVH_ATCVH_SHIFT 0
#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
/* ATCVL Bit Fields */
#define MCG_ATCVL_ATCVL_MASK 0xFFu
#define MCG_ATCVL_ATCVL_SHIFT 0
#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
/**
* @}
*/ /* end of group MCG_Register_Masks */
/* MCG - Peripheral instance base addresses */
/** Peripheral MCG base pointer */
#define MCG_BASE_PTR ((MCG_MemMapPtr)0x40064000u)
/* ----------------------------------------------------------------------------
-- MCG - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
* @{
*/
/* MCG - Register instance definitions */
/* MCG */
#define MCG_C1 MCG_C1_REG(MCG_BASE_PTR)
#define MCG_C2 MCG_C2_REG(MCG_BASE_PTR)
#define MCG_C3 MCG_C3_REG(MCG_BASE_PTR)
#define MCG_C4 MCG_C4_REG(MCG_BASE_PTR)
#define MCG_C5 MCG_C5_REG(MCG_BASE_PTR)
#define MCG_C6 MCG_C6_REG(MCG_BASE_PTR)
#define MCG_S MCG_S_REG(MCG_BASE_PTR)
#define MCG_ATC MCG_ATC_REG(MCG_BASE_PTR)
#define MCG_ATCVH MCG_ATCVH_REG(MCG_BASE_PTR)
#define MCG_ATCVL MCG_ATCVL_REG(MCG_BASE_PTR)
/**
* @}
*/ /* end of group MCG_Register_Accessor_Macros */
/**
* @}
*/ /* end of group MCG_Peripheral */
/* ----------------------------------------------------------------------------
-- MCM
---------------------------------------------------------------------------- */
/**
* @addtogroup MCM_Peripheral MCM
* @{
*/
/** MCM - Peripheral register structure */
typedef struct MCM_MemMap {
uint8_t RESERVED_0[8];
uint16_t PLASC; /**< Crossbar switch (AXBS) slave configuration, offset: 0x8 */
uint16_t PLAMC; /**< Crossbar switch (AXBS) master configuration, offset: 0xA */
uint32_t SRAMAP; /**< SRAM arbitration and protection, offset: 0xC */
uint32_t ISR; /**< Interrupt status register, offset: 0x10 */
uint32_t ETBCC; /**< ETB counter control register, offset: 0x14 */
uint32_t ETBRL; /**< ETB reload register, offset: 0x18 */
uint32_t ETBCNT; /**< ETB counter value register, offset: 0x1C */
} volatile *MCM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- MCM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
* @{
*/
/* MCM - Register accessors */
#define MCM_PLASC_REG(base) ((base)->PLASC)
#define MCM_PLAMC_REG(base) ((base)->PLAMC)
#define MCM_SRAMAP_REG(base) ((base)->SRAMAP)
#define MCM_ISR_REG(base) ((base)->ISR)
#define MCM_ETBCC_REG(base) ((base)->ETBCC)
#define MCM_ETBRL_REG(base) ((base)->ETBRL)
#define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
/**
* @}
*/ /* end of group MCM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- MCM Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup MCM_Register_Masks MCM Register Masks
* @{
*/
/* PLASC Bit Fields */
#define MCM_PLASC_ASC_MASK 0xFFu
#define MCM_PLASC_ASC_SHIFT 0
#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
/* PLAMC Bit Fields */
#define MCM_PLAMC_AMC_MASK 0xFFu
#define MCM_PLAMC_AMC_SHIFT 0
#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
/* SRAMAP Bit Fields */
#define MCM_SRAMAP_SRAMUAP_MASK 0x3000000u
#define MCM_SRAMAP_SRAMUAP_SHIFT 24
#define MCM_SRAMAP_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_SRAMAP_SRAMUAP_SHIFT))&MCM_SRAMAP_SRAMUAP_MASK)
#define MCM_SRAMAP_SRAMUWP_MASK 0x4000000u
#define MCM_SRAMAP_SRAMUWP_SHIFT 26
#define MCM_SRAMAP_SRAMLAP_MASK 0x30000000u
#define MCM_SRAMAP_SRAMLAP_SHIFT 28
#define MCM_SRAMAP_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_SRAMAP_SRAMLAP_SHIFT))&MCM_SRAMAP_SRAMLAP_MASK)
#define MCM_SRAMAP_SRAMLWP_MASK 0x40000000u
#define MCM_SRAMAP_SRAMLWP_SHIFT 30
/* ISR Bit Fields */
#define MCM_ISR_IRQ_MASK 0x2u
#define MCM_ISR_IRQ_SHIFT 1
#define MCM_ISR_NMI_MASK 0x4u
#define MCM_ISR_NMI_SHIFT 2
/* ETBCC Bit Fields */
#define MCM_ETBCC_CNTEN_MASK 0x1u
#define MCM_ETBCC_CNTEN_SHIFT 0
#define MCM_ETBCC_RSPT_MASK 0x6u
#define MCM_ETBCC_RSPT_SHIFT 1
#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
#define MCM_ETBCC_RLRQ_MASK 0x8u
#define MCM_ETBCC_RLRQ_SHIFT 3
#define MCM_ETBCC_ETDIS_MASK 0x10u
#define MCM_ETBCC_ETDIS_SHIFT 4
#define MCM_ETBCC_ITDIS_MASK 0x20u
#define MCM_ETBCC_ITDIS_SHIFT 5
/* ETBRL Bit Fields */
#define MCM_ETBRL_RELOAD_MASK 0x7FFu
#define MCM_ETBRL_RELOAD_SHIFT 0
#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
/* ETBCNT Bit Fields */
#define MCM_ETBCNT_COUNTER_MASK 0x7FFu
#define MCM_ETBCNT_COUNTER_SHIFT 0
#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
/**
* @}
*/ /* end of group MCM_Register_Masks */
/* MCM - Peripheral instance base addresses */
/** Peripheral MCM base pointer */
#define MCM_BASE_PTR ((MCM_MemMapPtr)0xE0080000u)
/* ----------------------------------------------------------------------------
-- MCM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
* @{
*/
/* MCM - Register instance definitions */
/* MCM */
#define MCM_PLASC MCM_PLASC_REG(MCM_BASE_PTR)
#define MCM_PLAMC MCM_PLAMC_REG(MCM_BASE_PTR)
#define MCM_SRAMAP MCM_SRAMAP_REG(MCM_BASE_PTR)
#define MCM_ISR MCM_ISR_REG(MCM_BASE_PTR)
#define MCM_ETBCC MCM_ETBCC_REG(MCM_BASE_PTR)
#define MCM_ETBRL MCM_ETBRL_REG(MCM_BASE_PTR)
#define MCM_ETBCNT MCM_ETBCNT_REG(MCM_BASE_PTR)
/**
* @}
*/ /* end of group MCM_Register_Accessor_Macros */
/**
* @}
*/ /* end of group MCM_Peripheral */
/* ----------------------------------------------------------------------------
-- MPU
---------------------------------------------------------------------------- */
/**
* @addtogroup MPU_Peripheral MPU
* @{
*/
/** MPU - Peripheral register structure */
typedef struct MPU_MemMap {
uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
uint8_t RESERVED_0[12];
struct { /* offset: 0x10, array step: 0x8 */
uint32_t EAR; /**< Error Address Register, Slave Port n, array offset: 0x10, array step: 0x8 */
uint32_t EDR; /**< Error Detail Register, Slave Port n, array offset: 0x14, array step: 0x8 */
} SP[5];
uint8_t RESERVED_1[968];
uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
uint8_t RESERVED_2[832];
uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
} volatile *MPU_MemMapPtr;
/* ----------------------------------------------------------------------------
-- MPU - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
* @{
*/
/* MPU - Register accessors */
#define MPU_CESR_REG(base) ((base)->CESR)
#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
/**
* @}
*/ /* end of group MPU_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- MPU Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup MPU_Register_Masks MPU Register Masks
* @{
*/
/* CESR Bit Fields */
#define MPU_CESR_VLD_MASK 0x1u
#define MPU_CESR_VLD_SHIFT 0
#define MPU_CESR_NRGD_MASK 0xF00u
#define MPU_CESR_NRGD_SHIFT 8
#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
#define MPU_CESR_NSP_MASK 0xF000u
#define MPU_CESR_NSP_SHIFT 12
#define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
#define MPU_CESR_HRL_MASK 0xF0000u
#define MPU_CESR_HRL_SHIFT 16
#define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
#define MPU_CESR_SPERR_MASK 0xF8000000u
#define MPU_CESR_SPERR_SHIFT 27
#define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
/* EAR Bit Fields */
#define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
#define MPU_EAR_EADDR_SHIFT 0
#define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
/* EDR Bit Fields */
#define MPU_EDR_ERW_MASK 0x1u
#define MPU_EDR_ERW_SHIFT 0
#define MPU_EDR_EATTR_MASK 0xEu
#define MPU_EDR_EATTR_SHIFT 1
#define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
#define MPU_EDR_EMN_MASK 0xF0u
#define MPU_EDR_EMN_SHIFT 4
#define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
#define MPU_EDR_EACD_MASK 0xFFFF0000u
#define MPU_EDR_EACD_SHIFT 16
#define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
/* WORD Bit Fields */
#define MPU_WORD_M0UM_MASK 0x7u
#define MPU_WORD_M0UM_SHIFT 0
#define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
#define MPU_WORD_VLD_MASK 0x1u
#define MPU_WORD_VLD_SHIFT 0
#define MPU_WORD_M0SM_MASK 0x18u
#define MPU_WORD_M0SM_SHIFT 3
#define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
#define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
#define MPU_WORD_ENDADDR_SHIFT 5
#define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
#define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
#define MPU_WORD_SRTADDR_SHIFT 5
#define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
#define MPU_WORD_M1UM_MASK 0x1C0u
#define MPU_WORD_M1UM_SHIFT 6
#define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
#define MPU_WORD_M1SM_MASK 0x600u
#define MPU_WORD_M1SM_SHIFT 9
#define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
#define MPU_WORD_M2UM_MASK 0x7000u
#define MPU_WORD_M2UM_SHIFT 12
#define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
#define MPU_WORD_M2SM_MASK 0x18000u
#define MPU_WORD_M2SM_SHIFT 15
#define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
#define MPU_WORD_M3UM_MASK 0x1C0000u
#define MPU_WORD_M3UM_SHIFT 18
#define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
#define MPU_WORD_M3SM_MASK 0x600000u
#define MPU_WORD_M3SM_SHIFT 21
#define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
#define MPU_WORD_M4WE_MASK 0x1000000u
#define MPU_WORD_M4WE_SHIFT 24
#define MPU_WORD_M4RE_MASK 0x2000000u
#define MPU_WORD_M4RE_SHIFT 25
#define MPU_WORD_M5WE_MASK 0x4000000u
#define MPU_WORD_M5WE_SHIFT 26
#define MPU_WORD_M5RE_MASK 0x8000000u
#define MPU_WORD_M5RE_SHIFT 27
#define MPU_WORD_M6WE_MASK 0x10000000u
#define MPU_WORD_M6WE_SHIFT 28
#define MPU_WORD_M6RE_MASK 0x20000000u
#define MPU_WORD_M6RE_SHIFT 29
#define MPU_WORD_M7WE_MASK 0x40000000u
#define MPU_WORD_M7WE_SHIFT 30
#define MPU_WORD_M7RE_MASK 0x80000000u
#define MPU_WORD_M7RE_SHIFT 31
/* RGDAAC Bit Fields */
#define MPU_RGDAAC_M0UM_MASK 0x7u
#define MPU_RGDAAC_M0UM_SHIFT 0
#define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
#define MPU_RGDAAC_M0SM_MASK 0x18u
#define MPU_RGDAAC_M0SM_SHIFT 3
#define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
#define MPU_RGDAAC_M1UM_MASK 0x1C0u
#define MPU_RGDAAC_M1UM_SHIFT 6
#define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
#define MPU_RGDAAC_M1SM_MASK 0x600u
#define MPU_RGDAAC_M1SM_SHIFT 9
#define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
#define MPU_RGDAAC_M2UM_MASK 0x7000u
#define MPU_RGDAAC_M2UM_SHIFT 12
#define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
#define MPU_RGDAAC_M2SM_MASK 0x18000u
#define MPU_RGDAAC_M2SM_SHIFT 15
#define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
#define MPU_RGDAAC_M3UM_MASK 0x1C0000u
#define MPU_RGDAAC_M3UM_SHIFT 18
#define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
#define MPU_RGDAAC_M3SM_MASK 0x600000u
#define MPU_RGDAAC_M3SM_SHIFT 21
#define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
#define MPU_RGDAAC_M4WE_MASK 0x1000000u
#define MPU_RGDAAC_M4WE_SHIFT 24
#define MPU_RGDAAC_M4RE_MASK 0x2000000u
#define MPU_RGDAAC_M4RE_SHIFT 25
#define MPU_RGDAAC_M5WE_MASK 0x4000000u
#define MPU_RGDAAC_M5WE_SHIFT 26
#define MPU_RGDAAC_M5RE_MASK 0x8000000u
#define MPU_RGDAAC_M5RE_SHIFT 27
#define MPU_RGDAAC_M6WE_MASK 0x10000000u
#define MPU_RGDAAC_M6WE_SHIFT 28
#define MPU_RGDAAC_M6RE_MASK 0x20000000u
#define MPU_RGDAAC_M6RE_SHIFT 29
#define MPU_RGDAAC_M7WE_MASK 0x40000000u
#define MPU_RGDAAC_M7WE_SHIFT 30
#define MPU_RGDAAC_M7RE_MASK 0x80000000u
#define MPU_RGDAAC_M7RE_SHIFT 31
/**
* @}
*/ /* end of group MPU_Register_Masks */
/* MPU - Peripheral instance base addresses */
/** Peripheral MPU base pointer */
#define MPU_BASE_PTR ((MPU_MemMapPtr)0x4000D000u)
/* ----------------------------------------------------------------------------
-- MPU - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
* @{
*/
/* MPU - Register instance definitions */
/* MPU */
#define MPU_CESR MPU_CESR_REG(MPU_BASE_PTR)
#define MPU_EAR0 MPU_EAR_REG(MPU_BASE_PTR,0)
#define MPU_EDR0 MPU_EDR_REG(MPU_BASE_PTR,0)
#define MPU_EAR1 MPU_EAR_REG(MPU_BASE_PTR,1)
#define MPU_EDR1 MPU_EDR_REG(MPU_BASE_PTR,1)
#define MPU_EAR2 MPU_EAR_REG(MPU_BASE_PTR,2)
#define MPU_EDR2 MPU_EDR_REG(MPU_BASE_PTR,2)
#define MPU_EAR3 MPU_EAR_REG(MPU_BASE_PTR,3)
#define MPU_EDR3 MPU_EDR_REG(MPU_BASE_PTR,3)
#define MPU_EAR4 MPU_EAR_REG(MPU_BASE_PTR,4)
#define MPU_EDR4 MPU_EDR_REG(MPU_BASE_PTR,4)
#define MPU_RGD0_WORD0 MPU_WORD_REG(MPU_BASE_PTR,0,0)
#define MPU_RGD0_WORD1 MPU_WORD_REG(MPU_BASE_PTR,0,1)
#define MPU_RGD0_WORD2 MPU_WORD_REG(MPU_BASE_PTR,0,2)
#define MPU_RGD0_WORD3 MPU_WORD_REG(MPU_BASE_PTR,0,3)
#define MPU_RGD1_WORD0 MPU_WORD_REG(MPU_BASE_PTR,1,0)
#define MPU_RGD1_WORD1 MPU_WORD_REG(MPU_BASE_PTR,1,1)
#define MPU_RGD1_WORD2 MPU_WORD_REG(MPU_BASE_PTR,1,2)
#define MPU_RGD1_WORD3 MPU_WORD_REG(MPU_BASE_PTR,1,3)
#define MPU_RGD2_WORD0 MPU_WORD_REG(MPU_BASE_PTR,2,0)
#define MPU_RGD2_WORD1 MPU_WORD_REG(MPU_BASE_PTR,2,1)
#define MPU_RGD2_WORD2 MPU_WORD_REG(MPU_BASE_PTR,2,2)
#define MPU_RGD2_WORD3 MPU_WORD_REG(MPU_BASE_PTR,2,3)
#define MPU_RGD3_WORD0 MPU_WORD_REG(MPU_BASE_PTR,3,0)
#define MPU_RGD3_WORD1 MPU_WORD_REG(MPU_BASE_PTR,3,1)
#define MPU_RGD3_WORD2 MPU_WORD_REG(MPU_BASE_PTR,3,2)
#define MPU_RGD3_WORD3 MPU_WORD_REG(MPU_BASE_PTR,3,3)
#define MPU_RGD4_WORD0 MPU_WORD_REG(MPU_BASE_PTR,4,0)
#define MPU_RGD4_WORD1 MPU_WORD_REG(MPU_BASE_PTR,4,1)
#define MPU_RGD4_WORD2 MPU_WORD_REG(MPU_BASE_PTR,4,2)
#define MPU_RGD4_WORD3 MPU_WORD_REG(MPU_BASE_PTR,4,3)
#define MPU_RGD5_WORD0 MPU_WORD_REG(MPU_BASE_PTR,5,0)
#define MPU_RGD5_WORD1 MPU_WORD_REG(MPU_BASE_PTR,5,1)
#define MPU_RGD5_WORD2 MPU_WORD_REG(MPU_BASE_PTR,5,2)
#define MPU_RGD5_WORD3 MPU_WORD_REG(MPU_BASE_PTR,5,3)
#define MPU_RGD6_WORD0 MPU_WORD_REG(MPU_BASE_PTR,6,0)
#define MPU_RGD6_WORD1 MPU_WORD_REG(MPU_BASE_PTR,6,1)
#define MPU_RGD6_WORD2 MPU_WORD_REG(MPU_BASE_PTR,6,2)
#define MPU_RGD6_WORD3 MPU_WORD_REG(MPU_BASE_PTR,6,3)
#define MPU_RGD7_WORD0 MPU_WORD_REG(MPU_BASE_PTR,7,0)
#define MPU_RGD7_WORD1 MPU_WORD_REG(MPU_BASE_PTR,7,1)
#define MPU_RGD7_WORD2 MPU_WORD_REG(MPU_BASE_PTR,7,2)
#define MPU_RGD7_WORD3 MPU_WORD_REG(MPU_BASE_PTR,7,3)
#define MPU_RGD8_WORD0 MPU_WORD_REG(MPU_BASE_PTR,8,0)
#define MPU_RGD8_WORD1 MPU_WORD_REG(MPU_BASE_PTR,8,1)
#define MPU_RGD8_WORD2 MPU_WORD_REG(MPU_BASE_PTR,8,2)
#define MPU_RGD8_WORD3 MPU_WORD_REG(MPU_BASE_PTR,8,3)
#define MPU_RGD9_WORD0 MPU_WORD_REG(MPU_BASE_PTR,9,0)
#define MPU_RGD9_WORD1 MPU_WORD_REG(MPU_BASE_PTR,9,1)
#define MPU_RGD9_WORD2 MPU_WORD_REG(MPU_BASE_PTR,9,2)
#define MPU_RGD9_WORD3 MPU_WORD_REG(MPU_BASE_PTR,9,3)
#define MPU_RGD10_WORD0 MPU_WORD_REG(MPU_BASE_PTR,10,0)
#define MPU_RGD10_WORD1 MPU_WORD_REG(MPU_BASE_PTR,10,1)
#define MPU_RGD10_WORD2 MPU_WORD_REG(MPU_BASE_PTR,10,2)
#define MPU_RGD10_WORD3 MPU_WORD_REG(MPU_BASE_PTR,10,3)
#define MPU_RGD11_WORD0 MPU_WORD_REG(MPU_BASE_PTR,11,0)
#define MPU_RGD11_WORD1 MPU_WORD_REG(MPU_BASE_PTR,11,1)
#define MPU_RGD11_WORD2 MPU_WORD_REG(MPU_BASE_PTR,11,2)
#define MPU_RGD11_WORD3 MPU_WORD_REG(MPU_BASE_PTR,11,3)
#define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU_BASE_PTR,0)
#define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU_BASE_PTR,1)
#define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU_BASE_PTR,2)
#define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU_BASE_PTR,3)
#define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU_BASE_PTR,4)
#define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU_BASE_PTR,5)
#define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU_BASE_PTR,6)
#define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU_BASE_PTR,7)
#define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU_BASE_PTR,8)
#define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU_BASE_PTR,9)
#define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU_BASE_PTR,10)
#define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU_BASE_PTR,11)
/* MPU - Register array accessors */
#define MPU_EAR(index) MPU_EAR_REG(MPU_BASE_PTR,index)
#define MPU_EDR(index) MPU_EDR_REG(MPU_BASE_PTR,index)
#define MPU_WORD(index,index2) MPU_WORD_REG(MPU_BASE_PTR,index,index2)
#define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU_BASE_PTR,index)
/**
* @}
*/ /* end of group MPU_Register_Accessor_Macros */
/**
* @}
*/ /* end of group MPU_Peripheral */
/* ----------------------------------------------------------------------------
-- NVIC
---------------------------------------------------------------------------- */
/**
* @addtogroup NVIC_Peripheral NVIC
* @{
*/
/** NVIC - Peripheral register structure */
typedef struct NVIC_MemMap {
uint32_t ISER[4]; /**< Interrupt Set Enable Register n, array offset: 0x0, array step: 0x4 */
uint8_t RESERVED_0[112];
uint32_t ICER[4]; /**< Interrupt Clear Enable Register n, array offset: 0x80, array step: 0x4 */
uint8_t RESERVED_1[112];
uint32_t ISPR[4]; /**< Interrupt Set Pending Register n, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_2[112];
uint32_t ICPR[4]; /**< Interrupt Clear Pending Register n, array offset: 0x180, array step: 0x4 */
uint8_t RESERVED_3[112];
uint32_t IABR[4]; /**< Interrupt Active bit Register n, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_4[240];
uint8_t IP[104]; /**< Interrupt Priority Register n, array offset: 0x300, array step: 0x1 */
uint8_t RESERVED_5[2712];
uint32_t STIR[1]; /**< Software Trigger Interrupt Register, array offset: 0xE00, array step: 0x4 */
} volatile *NVIC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- NVIC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup NVIC_Register_Accessor_Macros NVIC - Register accessor macros
* @{
*/
/* NVIC - Register accessors */
#define NVIC_ISER_REG(base,index) ((base)->ISER[index])
#define NVIC_ICER_REG(base,index) ((base)->ICER[index])
#define NVIC_ISPR_REG(base,index) ((base)->ISPR[index])
#define NVIC_ICPR_REG(base,index) ((base)->ICPR[index])
#define NVIC_IABR_REG(base,index) ((base)->IABR[index])
#define NVIC_IP_REG(base,index) ((base)->IP[index])
#define NVIC_STIR_REG(base,index) ((base)->STIR[index])
/**
* @}
*/ /* end of group NVIC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- NVIC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup NVIC_Register_Masks NVIC Register Masks
* @{
*/
/* ISER Bit Fields */
#define NVIC_ISER_SETENA_MASK 0xFFFFFFFFu
#define NVIC_ISER_SETENA_SHIFT 0
#define NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISER_SETENA_SHIFT))&NVIC_ISER_SETENA_MASK)
/* ICER Bit Fields */
#define NVIC_ICER_CLRENA_MASK 0xFFFFFFFFu
#define NVIC_ICER_CLRENA_SHIFT 0
#define NVIC_ICER_CLRENA(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ICER_CLRENA_SHIFT))&NVIC_ICER_CLRENA_MASK)
/* ISPR Bit Fields */
#define NVIC_ISPR_SETPEND_MASK 0xFFFFFFFFu
#define NVIC_ISPR_SETPEND_SHIFT 0
#define NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISPR_SETPEND_SHIFT))&NVIC_ISPR_SETPEND_MASK)
/* ICPR Bit Fields */
#define NVIC_ICPR_CLRPEND_MASK 0xFFFFFFFFu
#define NVIC_ICPR_CLRPEND_SHIFT 0
#define NVIC_ICPR_CLRPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ICPR_CLRPEND_SHIFT))&NVIC_ICPR_CLRPEND_MASK)
/* IABR Bit Fields */
#define NVIC_IABR_ACTIVE_MASK 0xFFFFFFFFu
#define NVIC_IABR_ACTIVE_SHIFT 0
#define NVIC_IABR_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IABR_ACTIVE_SHIFT))&NVIC_IABR_ACTIVE_MASK)
/* IP Bit Fields */
#define NVIC_IP_PRI0_MASK 0xFFu
#define NVIC_IP_PRI0_SHIFT 0
#define NVIC_IP_PRI0(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI0_SHIFT))&NVIC_IP_PRI0_MASK)
#define NVIC_IP_PRI1_MASK 0xFFu
#define NVIC_IP_PRI1_SHIFT 0
#define NVIC_IP_PRI1(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI1_SHIFT))&NVIC_IP_PRI1_MASK)
#define NVIC_IP_PRI2_MASK 0xFFu
#define NVIC_IP_PRI2_SHIFT 0
#define NVIC_IP_PRI2(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI2_SHIFT))&NVIC_IP_PRI2_MASK)
#define NVIC_IP_PRI3_MASK 0xFFu
#define NVIC_IP_PRI3_SHIFT 0
#define NVIC_IP_PRI3(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI3_SHIFT))&NVIC_IP_PRI3_MASK)
#define NVIC_IP_PRI4_MASK 0xFFu
#define NVIC_IP_PRI4_SHIFT 0
#define NVIC_IP_PRI4(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI4_SHIFT))&NVIC_IP_PRI4_MASK)
#define NVIC_IP_PRI5_MASK 0xFFu
#define NVIC_IP_PRI5_SHIFT 0
#define NVIC_IP_PRI5(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI5_SHIFT))&NVIC_IP_PRI5_MASK)
#define NVIC_IP_PRI6_MASK 0xFFu
#define NVIC_IP_PRI6_SHIFT 0
#define NVIC_IP_PRI6(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI6_SHIFT))&NVIC_IP_PRI6_MASK)
#define NVIC_IP_PRI7_MASK 0xFFu
#define NVIC_IP_PRI7_SHIFT 0
#define NVIC_IP_PRI7(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI7_SHIFT))&NVIC_IP_PRI7_MASK)
#define NVIC_IP_PRI8_MASK 0xFFu
#define NVIC_IP_PRI8_SHIFT 0
#define NVIC_IP_PRI8(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI8_SHIFT))&NVIC_IP_PRI8_MASK)
#define NVIC_IP_PRI9_MASK 0xFFu
#define NVIC_IP_PRI9_SHIFT 0
#define NVIC_IP_PRI9(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI9_SHIFT))&NVIC_IP_PRI9_MASK)
#define NVIC_IP_PRI10_MASK 0xFFu
#define NVIC_IP_PRI10_SHIFT 0
#define NVIC_IP_PRI10(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI10_SHIFT))&NVIC_IP_PRI10_MASK)
#define NVIC_IP_PRI11_MASK 0xFFu
#define NVIC_IP_PRI11_SHIFT 0
#define NVIC_IP_PRI11(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI11_SHIFT))&NVIC_IP_PRI11_MASK)
#define NVIC_IP_PRI12_MASK 0xFFu
#define NVIC_IP_PRI12_SHIFT 0
#define NVIC_IP_PRI12(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI12_SHIFT))&NVIC_IP_PRI12_MASK)
#define NVIC_IP_PRI13_MASK 0xFFu
#define NVIC_IP_PRI13_SHIFT 0
#define NVIC_IP_PRI13(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI13_SHIFT))&NVIC_IP_PRI13_MASK)
#define NVIC_IP_PRI14_MASK 0xFFu
#define NVIC_IP_PRI14_SHIFT 0
#define NVIC_IP_PRI14(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI14_SHIFT))&NVIC_IP_PRI14_MASK)
#define NVIC_IP_PRI15_MASK 0xFFu
#define NVIC_IP_PRI15_SHIFT 0
#define NVIC_IP_PRI15(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI15_SHIFT))&NVIC_IP_PRI15_MASK)
#define NVIC_IP_PRI16_MASK 0xFFu
#define NVIC_IP_PRI16_SHIFT 0
#define NVIC_IP_PRI16(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI16_SHIFT))&NVIC_IP_PRI16_MASK)
#define NVIC_IP_PRI17_MASK 0xFFu
#define NVIC_IP_PRI17_SHIFT 0
#define NVIC_IP_PRI17(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI17_SHIFT))&NVIC_IP_PRI17_MASK)
#define NVIC_IP_PRI18_MASK 0xFFu
#define NVIC_IP_PRI18_SHIFT 0
#define NVIC_IP_PRI18(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI18_SHIFT))&NVIC_IP_PRI18_MASK)
#define NVIC_IP_PRI19_MASK 0xFFu
#define NVIC_IP_PRI19_SHIFT 0
#define NVIC_IP_PRI19(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI19_SHIFT))&NVIC_IP_PRI19_MASK)
#define NVIC_IP_PRI20_MASK 0xFFu
#define NVIC_IP_PRI20_SHIFT 0
#define NVIC_IP_PRI20(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI20_SHIFT))&NVIC_IP_PRI20_MASK)
#define NVIC_IP_PRI21_MASK 0xFFu
#define NVIC_IP_PRI21_SHIFT 0
#define NVIC_IP_PRI21(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI21_SHIFT))&NVIC_IP_PRI21_MASK)
#define NVIC_IP_PRI22_MASK 0xFFu
#define NVIC_IP_PRI22_SHIFT 0
#define NVIC_IP_PRI22(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI22_SHIFT))&NVIC_IP_PRI22_MASK)
#define NVIC_IP_PRI23_MASK 0xFFu
#define NVIC_IP_PRI23_SHIFT 0
#define NVIC_IP_PRI23(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI23_SHIFT))&NVIC_IP_PRI23_MASK)
#define NVIC_IP_PRI24_MASK 0xFFu
#define NVIC_IP_PRI24_SHIFT 0
#define NVIC_IP_PRI24(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI24_SHIFT))&NVIC_IP_PRI24_MASK)
#define NVIC_IP_PRI25_MASK 0xFFu
#define NVIC_IP_PRI25_SHIFT 0
#define NVIC_IP_PRI25(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI25_SHIFT))&NVIC_IP_PRI25_MASK)
#define NVIC_IP_PRI26_MASK 0xFFu
#define NVIC_IP_PRI26_SHIFT 0
#define NVIC_IP_PRI26(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI26_SHIFT))&NVIC_IP_PRI26_MASK)
#define NVIC_IP_PRI27_MASK 0xFFu
#define NVIC_IP_PRI27_SHIFT 0
#define NVIC_IP_PRI27(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI27_SHIFT))&NVIC_IP_PRI27_MASK)
#define NVIC_IP_PRI28_MASK 0xFFu
#define NVIC_IP_PRI28_SHIFT 0
#define NVIC_IP_PRI28(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI28_SHIFT))&NVIC_IP_PRI28_MASK)
#define NVIC_IP_PRI29_MASK 0xFFu
#define NVIC_IP_PRI29_SHIFT 0
#define NVIC_IP_PRI29(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI29_SHIFT))&NVIC_IP_PRI29_MASK)
#define NVIC_IP_PRI30_MASK 0xFFu
#define NVIC_IP_PRI30_SHIFT 0
#define NVIC_IP_PRI30(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI30_SHIFT))&NVIC_IP_PRI30_MASK)
#define NVIC_IP_PRI31_MASK 0xFFu
#define NVIC_IP_PRI31_SHIFT 0
#define NVIC_IP_PRI31(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI31_SHIFT))&NVIC_IP_PRI31_MASK)
#define NVIC_IP_PRI32_MASK 0xFFu
#define NVIC_IP_PRI32_SHIFT 0
#define NVIC_IP_PRI32(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI32_SHIFT))&NVIC_IP_PRI32_MASK)
#define NVIC_IP_PRI33_MASK 0xFFu
#define NVIC_IP_PRI33_SHIFT 0
#define NVIC_IP_PRI33(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI33_SHIFT))&NVIC_IP_PRI33_MASK)
#define NVIC_IP_PRI34_MASK 0xFFu
#define NVIC_IP_PRI34_SHIFT 0
#define NVIC_IP_PRI34(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI34_SHIFT))&NVIC_IP_PRI34_MASK)
#define NVIC_IP_PRI35_MASK 0xFFu
#define NVIC_IP_PRI35_SHIFT 0
#define NVIC_IP_PRI35(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI35_SHIFT))&NVIC_IP_PRI35_MASK)
#define NVIC_IP_PRI36_MASK 0xFFu
#define NVIC_IP_PRI36_SHIFT 0
#define NVIC_IP_PRI36(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI36_SHIFT))&NVIC_IP_PRI36_MASK)
#define NVIC_IP_PRI37_MASK 0xFFu
#define NVIC_IP_PRI37_SHIFT 0
#define NVIC_IP_PRI37(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI37_SHIFT))&NVIC_IP_PRI37_MASK)
#define NVIC_IP_PRI38_MASK 0xFFu
#define NVIC_IP_PRI38_SHIFT 0
#define NVIC_IP_PRI38(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI38_SHIFT))&NVIC_IP_PRI38_MASK)
#define NVIC_IP_PRI39_MASK 0xFFu
#define NVIC_IP_PRI39_SHIFT 0
#define NVIC_IP_PRI39(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI39_SHIFT))&NVIC_IP_PRI39_MASK)
#define NVIC_IP_PRI40_MASK 0xFFu
#define NVIC_IP_PRI40_SHIFT 0
#define NVIC_IP_PRI40(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI40_SHIFT))&NVIC_IP_PRI40_MASK)
#define NVIC_IP_PRI41_MASK 0xFFu
#define NVIC_IP_PRI41_SHIFT 0
#define NVIC_IP_PRI41(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI41_SHIFT))&NVIC_IP_PRI41_MASK)
#define NVIC_IP_PRI42_MASK 0xFFu
#define NVIC_IP_PRI42_SHIFT 0
#define NVIC_IP_PRI42(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI42_SHIFT))&NVIC_IP_PRI42_MASK)
#define NVIC_IP_PRI43_MASK 0xFFu
#define NVIC_IP_PRI43_SHIFT 0
#define NVIC_IP_PRI43(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI43_SHIFT))&NVIC_IP_PRI43_MASK)
#define NVIC_IP_PRI44_MASK 0xFFu
#define NVIC_IP_PRI44_SHIFT 0
#define NVIC_IP_PRI44(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI44_SHIFT))&NVIC_IP_PRI44_MASK)
#define NVIC_IP_PRI45_MASK 0xFFu
#define NVIC_IP_PRI45_SHIFT 0
#define NVIC_IP_PRI45(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI45_SHIFT))&NVIC_IP_PRI45_MASK)
#define NVIC_IP_PRI46_MASK 0xFFu
#define NVIC_IP_PRI46_SHIFT 0
#define NVIC_IP_PRI46(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI46_SHIFT))&NVIC_IP_PRI46_MASK)
#define NVIC_IP_PRI47_MASK 0xFFu
#define NVIC_IP_PRI47_SHIFT 0
#define NVIC_IP_PRI47(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI47_SHIFT))&NVIC_IP_PRI47_MASK)
#define NVIC_IP_PRI48_MASK 0xFFu
#define NVIC_IP_PRI48_SHIFT 0
#define NVIC_IP_PRI48(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI48_SHIFT))&NVIC_IP_PRI48_MASK)
#define NVIC_IP_PRI49_MASK 0xFFu
#define NVIC_IP_PRI49_SHIFT 0
#define NVIC_IP_PRI49(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI49_SHIFT))&NVIC_IP_PRI49_MASK)
#define NVIC_IP_PRI50_MASK 0xFFu
#define NVIC_IP_PRI50_SHIFT 0
#define NVIC_IP_PRI50(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI50_SHIFT))&NVIC_IP_PRI50_MASK)
#define NVIC_IP_PRI51_MASK 0xFFu
#define NVIC_IP_PRI51_SHIFT 0
#define NVIC_IP_PRI51(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI51_SHIFT))&NVIC_IP_PRI51_MASK)
#define NVIC_IP_PRI52_MASK 0xFFu
#define NVIC_IP_PRI52_SHIFT 0
#define NVIC_IP_PRI52(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI52_SHIFT))&NVIC_IP_PRI52_MASK)
#define NVIC_IP_PRI53_MASK 0xFFu
#define NVIC_IP_PRI53_SHIFT 0
#define NVIC_IP_PRI53(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI53_SHIFT))&NVIC_IP_PRI53_MASK)
#define NVIC_IP_PRI54_MASK 0xFFu
#define NVIC_IP_PRI54_SHIFT 0
#define NVIC_IP_PRI54(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI54_SHIFT))&NVIC_IP_PRI54_MASK)
#define NVIC_IP_PRI55_MASK 0xFFu
#define NVIC_IP_PRI55_SHIFT 0
#define NVIC_IP_PRI55(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI55_SHIFT))&NVIC_IP_PRI55_MASK)
#define NVIC_IP_PRI56_MASK 0xFFu
#define NVIC_IP_PRI56_SHIFT 0
#define NVIC_IP_PRI56(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI56_SHIFT))&NVIC_IP_PRI56_MASK)
#define NVIC_IP_PRI57_MASK 0xFFu
#define NVIC_IP_PRI57_SHIFT 0
#define NVIC_IP_PRI57(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI57_SHIFT))&NVIC_IP_PRI57_MASK)
#define NVIC_IP_PRI58_MASK 0xFFu
#define NVIC_IP_PRI58_SHIFT 0
#define NVIC_IP_PRI58(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI58_SHIFT))&NVIC_IP_PRI58_MASK)
#define NVIC_IP_PRI59_MASK 0xFFu
#define NVIC_IP_PRI59_SHIFT 0
#define NVIC_IP_PRI59(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI59_SHIFT))&NVIC_IP_PRI59_MASK)
#define NVIC_IP_PRI60_MASK 0xFFu
#define NVIC_IP_PRI60_SHIFT 0
#define NVIC_IP_PRI60(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI60_SHIFT))&NVIC_IP_PRI60_MASK)
#define NVIC_IP_PRI61_MASK 0xFFu
#define NVIC_IP_PRI61_SHIFT 0
#define NVIC_IP_PRI61(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI61_SHIFT))&NVIC_IP_PRI61_MASK)
#define NVIC_IP_PRI62_MASK 0xFFu
#define NVIC_IP_PRI62_SHIFT 0
#define NVIC_IP_PRI62(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI62_SHIFT))&NVIC_IP_PRI62_MASK)
#define NVIC_IP_PRI63_MASK 0xFFu
#define NVIC_IP_PRI63_SHIFT 0
#define NVIC_IP_PRI63(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI63_SHIFT))&NVIC_IP_PRI63_MASK)
#define NVIC_IP_PRI64_MASK 0xFFu
#define NVIC_IP_PRI64_SHIFT 0
#define NVIC_IP_PRI64(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI64_SHIFT))&NVIC_IP_PRI64_MASK)
#define NVIC_IP_PRI65_MASK 0xFFu
#define NVIC_IP_PRI65_SHIFT 0
#define NVIC_IP_PRI65(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI65_SHIFT))&NVIC_IP_PRI65_MASK)
#define NVIC_IP_PRI66_MASK 0xFFu
#define NVIC_IP_PRI66_SHIFT 0
#define NVIC_IP_PRI66(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI66_SHIFT))&NVIC_IP_PRI66_MASK)
#define NVIC_IP_PRI67_MASK 0xFFu
#define NVIC_IP_PRI67_SHIFT 0
#define NVIC_IP_PRI67(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI67_SHIFT))&NVIC_IP_PRI67_MASK)
#define NVIC_IP_PRI68_MASK 0xFFu
#define NVIC_IP_PRI68_SHIFT 0
#define NVIC_IP_PRI68(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI68_SHIFT))&NVIC_IP_PRI68_MASK)
#define NVIC_IP_PRI69_MASK 0xFFu
#define NVIC_IP_PRI69_SHIFT 0
#define NVIC_IP_PRI69(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI69_SHIFT))&NVIC_IP_PRI69_MASK)
#define NVIC_IP_PRI70_MASK 0xFFu
#define NVIC_IP_PRI70_SHIFT 0
#define NVIC_IP_PRI70(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI70_SHIFT))&NVIC_IP_PRI70_MASK)
#define NVIC_IP_PRI71_MASK 0xFFu
#define NVIC_IP_PRI71_SHIFT 0
#define NVIC_IP_PRI71(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI71_SHIFT))&NVIC_IP_PRI71_MASK)
#define NVIC_IP_PRI72_MASK 0xFFu
#define NVIC_IP_PRI72_SHIFT 0
#define NVIC_IP_PRI72(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI72_SHIFT))&NVIC_IP_PRI72_MASK)
#define NVIC_IP_PRI73_MASK 0xFFu
#define NVIC_IP_PRI73_SHIFT 0
#define NVIC_IP_PRI73(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI73_SHIFT))&NVIC_IP_PRI73_MASK)
#define NVIC_IP_PRI74_MASK 0xFFu
#define NVIC_IP_PRI74_SHIFT 0
#define NVIC_IP_PRI74(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI74_SHIFT))&NVIC_IP_PRI74_MASK)
#define NVIC_IP_PRI75_MASK 0xFFu
#define NVIC_IP_PRI75_SHIFT 0
#define NVIC_IP_PRI75(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI75_SHIFT))&NVIC_IP_PRI75_MASK)
#define NVIC_IP_PRI76_MASK 0xFFu
#define NVIC_IP_PRI76_SHIFT 0
#define NVIC_IP_PRI76(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI76_SHIFT))&NVIC_IP_PRI76_MASK)
#define NVIC_IP_PRI77_MASK 0xFFu
#define NVIC_IP_PRI77_SHIFT 0
#define NVIC_IP_PRI77(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI77_SHIFT))&NVIC_IP_PRI77_MASK)
#define NVIC_IP_PRI78_MASK 0xFFu
#define NVIC_IP_PRI78_SHIFT 0
#define NVIC_IP_PRI78(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI78_SHIFT))&NVIC_IP_PRI78_MASK)
#define NVIC_IP_PRI79_MASK 0xFFu
#define NVIC_IP_PRI79_SHIFT 0
#define NVIC_IP_PRI79(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI79_SHIFT))&NVIC_IP_PRI79_MASK)
#define NVIC_IP_PRI80_MASK 0xFFu
#define NVIC_IP_PRI80_SHIFT 0
#define NVIC_IP_PRI80(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI80_SHIFT))&NVIC_IP_PRI80_MASK)
#define NVIC_IP_PRI81_MASK 0xFFu
#define NVIC_IP_PRI81_SHIFT 0
#define NVIC_IP_PRI81(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI81_SHIFT))&NVIC_IP_PRI81_MASK)
#define NVIC_IP_PRI82_MASK 0xFFu
#define NVIC_IP_PRI82_SHIFT 0
#define NVIC_IP_PRI82(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI82_SHIFT))&NVIC_IP_PRI82_MASK)
#define NVIC_IP_PRI83_MASK 0xFFu
#define NVIC_IP_PRI83_SHIFT 0
#define NVIC_IP_PRI83(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI83_SHIFT))&NVIC_IP_PRI83_MASK)
#define NVIC_IP_PRI84_MASK 0xFFu
#define NVIC_IP_PRI84_SHIFT 0
#define NVIC_IP_PRI84(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI84_SHIFT))&NVIC_IP_PRI84_MASK)
#define NVIC_IP_PRI85_MASK 0xFFu
#define NVIC_IP_PRI85_SHIFT 0
#define NVIC_IP_PRI85(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI85_SHIFT))&NVIC_IP_PRI85_MASK)
#define NVIC_IP_PRI86_MASK 0xFFu
#define NVIC_IP_PRI86_SHIFT 0
#define NVIC_IP_PRI86(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI86_SHIFT))&NVIC_IP_PRI86_MASK)
#define NVIC_IP_PRI87_MASK 0xFFu
#define NVIC_IP_PRI87_SHIFT 0
#define NVIC_IP_PRI87(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI87_SHIFT))&NVIC_IP_PRI87_MASK)
#define NVIC_IP_PRI88_MASK 0xFFu
#define NVIC_IP_PRI88_SHIFT 0
#define NVIC_IP_PRI88(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI88_SHIFT))&NVIC_IP_PRI88_MASK)
#define NVIC_IP_PRI89_MASK 0xFFu
#define NVIC_IP_PRI89_SHIFT 0
#define NVIC_IP_PRI89(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI89_SHIFT))&NVIC_IP_PRI89_MASK)
#define NVIC_IP_PRI90_MASK 0xFFu
#define NVIC_IP_PRI90_SHIFT 0
#define NVIC_IP_PRI90(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI90_SHIFT))&NVIC_IP_PRI90_MASK)
#define NVIC_IP_PRI91_MASK 0xFFu
#define NVIC_IP_PRI91_SHIFT 0
#define NVIC_IP_PRI91(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI91_SHIFT))&NVIC_IP_PRI91_MASK)
#define NVIC_IP_PRI92_MASK 0xFFu
#define NVIC_IP_PRI92_SHIFT 0
#define NVIC_IP_PRI92(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI92_SHIFT))&NVIC_IP_PRI92_MASK)
#define NVIC_IP_PRI93_MASK 0xFFu
#define NVIC_IP_PRI93_SHIFT 0
#define NVIC_IP_PRI93(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI93_SHIFT))&NVIC_IP_PRI93_MASK)
#define NVIC_IP_PRI94_MASK 0xFFu
#define NVIC_IP_PRI94_SHIFT 0
#define NVIC_IP_PRI94(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI94_SHIFT))&NVIC_IP_PRI94_MASK)
#define NVIC_IP_PRI95_MASK 0xFFu
#define NVIC_IP_PRI95_SHIFT 0
#define NVIC_IP_PRI95(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI95_SHIFT))&NVIC_IP_PRI95_MASK)
#define NVIC_IP_PRI96_MASK 0xFFu
#define NVIC_IP_PRI96_SHIFT 0
#define NVIC_IP_PRI96(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI96_SHIFT))&NVIC_IP_PRI96_MASK)
#define NVIC_IP_PRI97_MASK 0xFFu
#define NVIC_IP_PRI97_SHIFT 0
#define NVIC_IP_PRI97(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI97_SHIFT))&NVIC_IP_PRI97_MASK)
#define NVIC_IP_PRI98_MASK 0xFFu
#define NVIC_IP_PRI98_SHIFT 0
#define NVIC_IP_PRI98(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI98_SHIFT))&NVIC_IP_PRI98_MASK)
#define NVIC_IP_PRI99_MASK 0xFFu
#define NVIC_IP_PRI99_SHIFT 0
#define NVIC_IP_PRI99(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI99_SHIFT))&NVIC_IP_PRI99_MASK)
#define NVIC_IP_PRI100_MASK 0xFFu
#define NVIC_IP_PRI100_SHIFT 0
#define NVIC_IP_PRI100(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI100_SHIFT))&NVIC_IP_PRI100_MASK)
#define NVIC_IP_PRI101_MASK 0xFFu
#define NVIC_IP_PRI101_SHIFT 0
#define NVIC_IP_PRI101(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI101_SHIFT))&NVIC_IP_PRI101_MASK)
#define NVIC_IP_PRI102_MASK 0xFFu
#define NVIC_IP_PRI102_SHIFT 0
#define NVIC_IP_PRI102(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI102_SHIFT))&NVIC_IP_PRI102_MASK)
#define NVIC_IP_PRI103_MASK 0xFFu
#define NVIC_IP_PRI103_SHIFT 0
#define NVIC_IP_PRI103(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI103_SHIFT))&NVIC_IP_PRI103_MASK)
/* STIR Bit Fields */
#define NVIC_STIR_INTID_MASK 0x1FFu
#define NVIC_STIR_INTID_SHIFT 0
#define NVIC_STIR_INTID(x) (((uint32_t)(((uint32_t)(x))<<NVIC_STIR_INTID_SHIFT))&NVIC_STIR_INTID_MASK)
/**
* @}
*/ /* end of group NVIC_Register_Masks */
/* NVIC - Peripheral instance base addresses */
/** Peripheral NVIC base pointer */
#define NVIC_BASE_PTR ((NVIC_MemMapPtr)0xE000E100u)
/* ----------------------------------------------------------------------------
-- NVIC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup NVIC_Register_Accessor_Macros NVIC - Register accessor macros
* @{
*/
/* NVIC - Register instance definitions */
/* NVIC */
#define NVICISER0 NVIC_ISER_REG(NVIC_BASE_PTR,0)
#define NVICISER1 NVIC_ISER_REG(NVIC_BASE_PTR,1)
#define NVICISER2 NVIC_ISER_REG(NVIC_BASE_PTR,2)
#define NVICISER3 NVIC_ISER_REG(NVIC_BASE_PTR,3)
#define NVICICER0 NVIC_ICER_REG(NVIC_BASE_PTR,0)
#define NVICICER1 NVIC_ICER_REG(NVIC_BASE_PTR,1)
#define NVICICER2 NVIC_ICER_REG(NVIC_BASE_PTR,2)
#define NVICICER3 NVIC_ICER_REG(NVIC_BASE_PTR,3)
#define NVICISPR0 NVIC_ISPR_REG(NVIC_BASE_PTR,0)
#define NVICISPR1 NVIC_ISPR_REG(NVIC_BASE_PTR,1)
#define NVICISPR2 NVIC_ISPR_REG(NVIC_BASE_PTR,2)
#define NVICISPR3 NVIC_ISPR_REG(NVIC_BASE_PTR,3)
#define NVICICPR0 NVIC_ICPR_REG(NVIC_BASE_PTR,0)
#define NVICICPR1 NVIC_ICPR_REG(NVIC_BASE_PTR,1)
#define NVICICPR2 NVIC_ICPR_REG(NVIC_BASE_PTR,2)
#define NVICICPR3 NVIC_ICPR_REG(NVIC_BASE_PTR,3)
#define NVICIABR0 NVIC_IABR_REG(NVIC_BASE_PTR,0)
#define NVICIABR1 NVIC_IABR_REG(NVIC_BASE_PTR,1)
#define NVICIABR2 NVIC_IABR_REG(NVIC_BASE_PTR,2)
#define NVICIABR3 NVIC_IABR_REG(NVIC_BASE_PTR,3)
#define NVICIP0 NVIC_IP_REG(NVIC_BASE_PTR,0)
#define NVICIP1 NVIC_IP_REG(NVIC_BASE_PTR,1)
#define NVICIP2 NVIC_IP_REG(NVIC_BASE_PTR,2)
#define NVICIP3 NVIC_IP_REG(NVIC_BASE_PTR,3)
#define NVICIP4 NVIC_IP_REG(NVIC_BASE_PTR,4)
#define NVICIP5 NVIC_IP_REG(NVIC_BASE_PTR,5)
#define NVICIP6 NVIC_IP_REG(NVIC_BASE_PTR,6)
#define NVICIP7 NVIC_IP_REG(NVIC_BASE_PTR,7)
#define NVICIP8 NVIC_IP_REG(NVIC_BASE_PTR,8)
#define NVICIP9 NVIC_IP_REG(NVIC_BASE_PTR,9)
#define NVICIP10 NVIC_IP_REG(NVIC_BASE_PTR,10)
#define NVICIP11 NVIC_IP_REG(NVIC_BASE_PTR,11)
#define NVICIP12 NVIC_IP_REG(NVIC_BASE_PTR,12)
#define NVICIP13 NVIC_IP_REG(NVIC_BASE_PTR,13)
#define NVICIP14 NVIC_IP_REG(NVIC_BASE_PTR,14)
#define NVICIP15 NVIC_IP_REG(NVIC_BASE_PTR,15)
#define NVICIP16 NVIC_IP_REG(NVIC_BASE_PTR,16)
#define NVICIP17 NVIC_IP_REG(NVIC_BASE_PTR,17)
#define NVICIP18 NVIC_IP_REG(NVIC_BASE_PTR,18)
#define NVICIP19 NVIC_IP_REG(NVIC_BASE_PTR,19)
#define NVICIP20 NVIC_IP_REG(NVIC_BASE_PTR,20)
#define NVICIP21 NVIC_IP_REG(NVIC_BASE_PTR,21)
#define NVICIP22 NVIC_IP_REG(NVIC_BASE_PTR,22)
#define NVICIP23 NVIC_IP_REG(NVIC_BASE_PTR,23)
#define NVICIP24 NVIC_IP_REG(NVIC_BASE_PTR,24)
#define NVICIP25 NVIC_IP_REG(NVIC_BASE_PTR,25)
#define NVICIP26 NVIC_IP_REG(NVIC_BASE_PTR,26)
#define NVICIP27 NVIC_IP_REG(NVIC_BASE_PTR,27)
#define NVICIP28 NVIC_IP_REG(NVIC_BASE_PTR,28)
#define NVICIP29 NVIC_IP_REG(NVIC_BASE_PTR,29)
#define NVICIP30 NVIC_IP_REG(NVIC_BASE_PTR,30)
#define NVICIP31 NVIC_IP_REG(NVIC_BASE_PTR,31)
#define NVICIP32 NVIC_IP_REG(NVIC_BASE_PTR,32)
#define NVICIP33 NVIC_IP_REG(NVIC_BASE_PTR,33)
#define NVICIP34 NVIC_IP_REG(NVIC_BASE_PTR,34)
#define NVICIP35 NVIC_IP_REG(NVIC_BASE_PTR,35)
#define NVICIP36 NVIC_IP_REG(NVIC_BASE_PTR,36)
#define NVICIP37 NVIC_IP_REG(NVIC_BASE_PTR,37)
#define NVICIP38 NVIC_IP_REG(NVIC_BASE_PTR,38)
#define NVICIP39 NVIC_IP_REG(NVIC_BASE_PTR,39)
#define NVICIP40 NVIC_IP_REG(NVIC_BASE_PTR,40)
#define NVICIP41 NVIC_IP_REG(NVIC_BASE_PTR,41)
#define NVICIP42 NVIC_IP_REG(NVIC_BASE_PTR,42)
#define NVICIP43 NVIC_IP_REG(NVIC_BASE_PTR,43)
#define NVICIP44 NVIC_IP_REG(NVIC_BASE_PTR,44)
#define NVICIP45 NVIC_IP_REG(NVIC_BASE_PTR,45)
#define NVICIP46 NVIC_IP_REG(NVIC_BASE_PTR,46)
#define NVICIP47 NVIC_IP_REG(NVIC_BASE_PTR,47)
#define NVICIP48 NVIC_IP_REG(NVIC_BASE_PTR,48)
#define NVICIP49 NVIC_IP_REG(NVIC_BASE_PTR,49)
#define NVICIP50 NVIC_IP_REG(NVIC_BASE_PTR,50)
#define NVICIP51 NVIC_IP_REG(NVIC_BASE_PTR,51)
#define NVICIP52 NVIC_IP_REG(NVIC_BASE_PTR,52)
#define NVICIP53 NVIC_IP_REG(NVIC_BASE_PTR,53)
#define NVICIP54 NVIC_IP_REG(NVIC_BASE_PTR,54)
#define NVICIP55 NVIC_IP_REG(NVIC_BASE_PTR,55)
#define NVICIP56 NVIC_IP_REG(NVIC_BASE_PTR,56)
#define NVICIP57 NVIC_IP_REG(NVIC_BASE_PTR,57)
#define NVICIP58 NVIC_IP_REG(NVIC_BASE_PTR,58)
#define NVICIP59 NVIC_IP_REG(NVIC_BASE_PTR,59)
#define NVICIP60 NVIC_IP_REG(NVIC_BASE_PTR,60)
#define NVICIP61 NVIC_IP_REG(NVIC_BASE_PTR,61)
#define NVICIP62 NVIC_IP_REG(NVIC_BASE_PTR,62)
#define NVICIP63 NVIC_IP_REG(NVIC_BASE_PTR,63)
#define NVICIP64 NVIC_IP_REG(NVIC_BASE_PTR,64)
#define NVICIP65 NVIC_IP_REG(NVIC_BASE_PTR,65)
#define NVICIP66 NVIC_IP_REG(NVIC_BASE_PTR,66)
#define NVICIP67 NVIC_IP_REG(NVIC_BASE_PTR,67)
#define NVICIP68 NVIC_IP_REG(NVIC_BASE_PTR,68)
#define NVICIP69 NVIC_IP_REG(NVIC_BASE_PTR,69)
#define NVICIP70 NVIC_IP_REG(NVIC_BASE_PTR,70)
#define NVICIP71 NVIC_IP_REG(NVIC_BASE_PTR,71)
#define NVICIP72 NVIC_IP_REG(NVIC_BASE_PTR,72)
#define NVICIP73 NVIC_IP_REG(NVIC_BASE_PTR,73)
#define NVICIP74 NVIC_IP_REG(NVIC_BASE_PTR,74)
#define NVICIP75 NVIC_IP_REG(NVIC_BASE_PTR,75)
#define NVICIP76 NVIC_IP_REG(NVIC_BASE_PTR,76)
#define NVICIP77 NVIC_IP_REG(NVIC_BASE_PTR,77)
#define NVICIP78 NVIC_IP_REG(NVIC_BASE_PTR,78)
#define NVICIP79 NVIC_IP_REG(NVIC_BASE_PTR,79)
#define NVICIP80 NVIC_IP_REG(NVIC_BASE_PTR,80)
#define NVICIP81 NVIC_IP_REG(NVIC_BASE_PTR,81)
#define NVICIP82 NVIC_IP_REG(NVIC_BASE_PTR,82)
#define NVICIP83 NVIC_IP_REG(NVIC_BASE_PTR,83)
#define NVICIP84 NVIC_IP_REG(NVIC_BASE_PTR,84)
#define NVICIP85 NVIC_IP_REG(NVIC_BASE_PTR,85)
#define NVICIP86 NVIC_IP_REG(NVIC_BASE_PTR,86)
#define NVICIP87 NVIC_IP_REG(NVIC_BASE_PTR,87)
#define NVICIP88 NVIC_IP_REG(NVIC_BASE_PTR,88)
#define NVICIP89 NVIC_IP_REG(NVIC_BASE_PTR,89)
#define NVICIP90 NVIC_IP_REG(NVIC_BASE_PTR,90)
#define NVICIP91 NVIC_IP_REG(NVIC_BASE_PTR,91)
#define NVICIP92 NVIC_IP_REG(NVIC_BASE_PTR,92)
#define NVICIP93 NVIC_IP_REG(NVIC_BASE_PTR,93)
#define NVICIP94 NVIC_IP_REG(NVIC_BASE_PTR,94)
#define NVICIP95 NVIC_IP_REG(NVIC_BASE_PTR,95)
#define NVICIP96 NVIC_IP_REG(NVIC_BASE_PTR,96)
#define NVICIP97 NVIC_IP_REG(NVIC_BASE_PTR,97)
#define NVICIP98 NVIC_IP_REG(NVIC_BASE_PTR,98)
#define NVICIP99 NVIC_IP_REG(NVIC_BASE_PTR,99)
#define NVICIP100 NVIC_IP_REG(NVIC_BASE_PTR,100)
#define NVICIP101 NVIC_IP_REG(NVIC_BASE_PTR,101)
#define NVICIP102 NVIC_IP_REG(NVIC_BASE_PTR,102)
#define NVICIP103 NVIC_IP_REG(NVIC_BASE_PTR,103)
#define NVICSTIR NVIC_STIR_REG(NVIC_BASE_PTR,0)
/* NVIC - Register array accessors */
#define NVIC_ISER(index) NVIC_ISER_REG(NVIC_BASE_PTR,index)
#define NVIC_ICER(index) NVIC_ICER_REG(NVIC_BASE_PTR,index)
#define NVIC_ISPR(index) NVIC_ISPR_REG(NVIC_BASE_PTR,index)
#define NVIC_ICPR(index) NVIC_ICPR_REG(NVIC_BASE_PTR,index)
#define NVIC_IABR(index) NVIC_IABR_REG(NVIC_BASE_PTR,index)
#define NVIC_IP(index) NVIC_IP_REG(NVIC_BASE_PTR,index)
#define NVIC_STIR(index) NVIC_STIR_REG(NVIC_BASE_PTR,index)
/**
* @}
*/ /* end of group NVIC_Register_Accessor_Macros */
/**
* @}
*/ /* end of group NVIC_Peripheral */
/* ----------------------------------------------------------------------------
-- OSC
---------------------------------------------------------------------------- */
/**
* @addtogroup OSC_Peripheral OSC
* @{
*/
/** OSC - Peripheral register structure */
typedef struct OSC_MemMap {
uint8_t CR; /**< OSC Control Register, offset: 0x0 */
} volatile *OSC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- OSC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
* @{
*/
/* OSC - Register accessors */
#define OSC_CR_REG(base) ((base)->CR)
/**
* @}
*/ /* end of group OSC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- OSC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup OSC_Register_Masks OSC Register Masks
* @{
*/
/* CR Bit Fields */
#define OSC_CR_SC16P_MASK 0x1u
#define OSC_CR_SC16P_SHIFT 0
#define OSC_CR_SC8P_MASK 0x2u
#define OSC_CR_SC8P_SHIFT 1
#define OSC_CR_SC4P_MASK 0x4u
#define OSC_CR_SC4P_SHIFT 2
#define OSC_CR_SC2P_MASK 0x8u
#define OSC_CR_SC2P_SHIFT 3
#define OSC_CR_EREFSTEN_MASK 0x20u
#define OSC_CR_EREFSTEN_SHIFT 5
#define OSC_CR_ERCLKEN_MASK 0x80u
#define OSC_CR_ERCLKEN_SHIFT 7
/**
* @}
*/ /* end of group OSC_Register_Masks */
/* OSC - Peripheral instance base addresses */
/** Peripheral OSC base pointer */
#define OSC_BASE_PTR ((OSC_MemMapPtr)0x40065000u)
/* ----------------------------------------------------------------------------
-- OSC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
* @{
*/
/* OSC - Register instance definitions */
/* OSC */
#define OSC_CR OSC_CR_REG(OSC_BASE_PTR)
/**
* @}
*/ /* end of group OSC_Register_Accessor_Macros */
/**
* @}
*/ /* end of group OSC_Peripheral */
/* ----------------------------------------------------------------------------
-- PDB
---------------------------------------------------------------------------- */
/**
* @addtogroup PDB_Peripheral PDB
* @{
*/
/** PDB - Peripheral register structure */
typedef struct PDB_MemMap {
uint32_t SC; /**< Status and Control Register, offset: 0x0 */
uint32_t MOD; /**< Modulus Register, offset: 0x4 */
uint32_t CNT; /**< Counter Register, offset: 0x8 */
uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
struct { /* offset: 0x10, array step: 0x28 */
uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */
uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x28 */
uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */
uint8_t RESERVED_0[24];
} CH[2];
uint8_t RESERVED_0[240];
struct { /* offset: 0x150, array step: 0x8 */
uint32_t INTC; /**< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 */
uint32_t INT; /**< DAC Interval n Register, array offset: 0x154, array step: 0x8 */
} DAC[2];
uint8_t RESERVED_1[48];
uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
uint32_t PODLY; /**< Pulse-Out n Delay Register, offset: 0x194 */
} volatile *PDB_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PDB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
* @{
*/
/* PDB - Register accessors */
#define PDB_SC_REG(base) ((base)->SC)
#define PDB_MOD_REG(base) ((base)->MOD)
#define PDB_CNT_REG(base) ((base)->CNT)
#define PDB_IDLY_REG(base) ((base)->IDLY)
#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
#define PDB_S_REG(base,index) ((base)->CH[index].S)
#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
#define PDB_POEN_REG(base) ((base)->POEN)
#define PDB_PODLY_REG(base) ((base)->PODLY)
/**
* @}
*/ /* end of group PDB_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PDB Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup PDB_Register_Masks PDB Register Masks
* @{
*/
/* SC Bit Fields */
#define PDB_SC_LDOK_MASK 0x1u
#define PDB_SC_LDOK_SHIFT 0
#define PDB_SC_CONT_MASK 0x2u
#define PDB_SC_CONT_SHIFT 1
#define PDB_SC_MULT_MASK 0xCu
#define PDB_SC_MULT_SHIFT 2
#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
#define PDB_SC_PDBIE_MASK 0x20u
#define PDB_SC_PDBIE_SHIFT 5
#define PDB_SC_PDBIF_MASK 0x40u
#define PDB_SC_PDBIF_SHIFT 6
#define PDB_SC_PDBEN_MASK 0x80u
#define PDB_SC_PDBEN_SHIFT 7
#define PDB_SC_TRGSEL_MASK 0xF00u
#define PDB_SC_TRGSEL_SHIFT 8
#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
#define PDB_SC_PRESCALER_MASK 0x7000u
#define PDB_SC_PRESCALER_SHIFT 12
#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
#define PDB_SC_DMAEN_MASK 0x8000u
#define PDB_SC_DMAEN_SHIFT 15
#define PDB_SC_SWTRIG_MASK 0x10000u
#define PDB_SC_SWTRIG_SHIFT 16
#define PDB_SC_PDBEIE_MASK 0x20000u
#define PDB_SC_PDBEIE_SHIFT 17
#define PDB_SC_LDMOD_MASK 0xC0000u
#define PDB_SC_LDMOD_SHIFT 18
#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
/* MOD Bit Fields */
#define PDB_MOD_MOD_MASK 0xFFFFu
#define PDB_MOD_MOD_SHIFT 0
#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
/* CNT Bit Fields */
#define PDB_CNT_CNT_MASK 0xFFFFu
#define PDB_CNT_CNT_SHIFT 0
#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
/* IDLY Bit Fields */
#define PDB_IDLY_IDLY_MASK 0xFFFFu
#define PDB_IDLY_IDLY_SHIFT 0
#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
/* C1 Bit Fields */
#define PDB_C1_EN_MASK 0xFFu
#define PDB_C1_EN_SHIFT 0
#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
#define PDB_C1_TOS_MASK 0xFF00u
#define PDB_C1_TOS_SHIFT 8
#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
#define PDB_C1_BB_MASK 0xFF0000u
#define PDB_C1_BB_SHIFT 16
#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
/* S Bit Fields */
#define PDB_S_ERR_MASK 0xFFu
#define PDB_S_ERR_SHIFT 0
#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
#define PDB_S_CF_MASK 0xFF0000u
#define PDB_S_CF_SHIFT 16
#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
/* DLY Bit Fields */
#define PDB_DLY_DLY_MASK 0xFFFFu
#define PDB_DLY_DLY_SHIFT 0
#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
/* INTC Bit Fields */
#define PDB_INTC_TOE_MASK 0x1u
#define PDB_INTC_TOE_SHIFT 0
#define PDB_INTC_EXT_MASK 0x2u
#define PDB_INTC_EXT_SHIFT 1
/* INT Bit Fields */
#define PDB_INT_INT_MASK 0xFFFFu
#define PDB_INT_INT_SHIFT 0
#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
/* POEN Bit Fields */
#define PDB_POEN_POEN_MASK 0xFFu
#define PDB_POEN_POEN_SHIFT 0
#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
/* PODLY Bit Fields */
#define PDB_PODLY_DLY2_MASK 0xFFFFu
#define PDB_PODLY_DLY2_SHIFT 0
#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
#define PDB_PODLY_DLY1_SHIFT 16
#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
/**
* @}
*/ /* end of group PDB_Register_Masks */
/* PDB - Peripheral instance base addresses */
/** Peripheral PDB0 base pointer */
#define PDB0_BASE_PTR ((PDB_MemMapPtr)0x40036000u)
/* ----------------------------------------------------------------------------
-- PDB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
* @{
*/
/* PDB - Register instance definitions */
/* PDB0 */
#define PDB0_SC PDB_SC_REG(PDB0_BASE_PTR)
#define PDB0_MOD PDB_MOD_REG(PDB0_BASE_PTR)
#define PDB0_CNT PDB_CNT_REG(PDB0_BASE_PTR)
#define PDB0_IDLY PDB_IDLY_REG(PDB0_BASE_PTR)
#define PDB0_CH0C1 PDB_C1_REG(PDB0_BASE_PTR,0)
#define PDB0_CH0S PDB_S_REG(PDB0_BASE_PTR,0)
#define PDB0_CH0DLY0 PDB_DLY_REG(PDB0_BASE_PTR,0,0)
#define PDB0_CH0DLY1 PDB_DLY_REG(PDB0_BASE_PTR,0,1)
#define PDB0_CH1C1 PDB_C1_REG(PDB0_BASE_PTR,1)
#define PDB0_CH1S PDB_S_REG(PDB0_BASE_PTR,1)
#define PDB0_CH1DLY0 PDB_DLY_REG(PDB0_BASE_PTR,1,0)
#define PDB0_CH1DLY1 PDB_DLY_REG(PDB0_BASE_PTR,1,1)
#define PDB0_DACINTC0 PDB_INTC_REG(PDB0_BASE_PTR,0)
#define PDB0_DACINT0 PDB_INT_REG(PDB0_BASE_PTR,0)
#define PDB0_DACINTC1 PDB_INTC_REG(PDB0_BASE_PTR,1)
#define PDB0_DACINT1 PDB_INT_REG(PDB0_BASE_PTR,1)
#define PDB0_PO0EN PDB_POEN_REG(PDB0_BASE_PTR)
#define PDB0_PO0DLY PDB_PODLY_REG(PDB0_BASE_PTR)
/* PDB - Register array accessors */
#define PDB0_C1(index) PDB_C1_REG(PDB0_BASE_PTR,index)
#define PDB0_S(index) PDB_S_REG(PDB0_BASE_PTR,index)
#define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0_BASE_PTR,index,index2)
#define PDB0_INTC(index) PDB_INTC_REG(PDB0_BASE_PTR,index)
#define PDB0_INT(index) PDB_INT_REG(PDB0_BASE_PTR,index)
/**
* @}
*/ /* end of group PDB_Register_Accessor_Macros */
/**
* @}
*/ /* end of group PDB_Peripheral */
/* ----------------------------------------------------------------------------
-- PIT
---------------------------------------------------------------------------- */
/**
* @addtogroup PIT_Peripheral PIT
* @{
*/
/** PIT - Peripheral register structure */
typedef struct PIT_MemMap {
uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
uint8_t RESERVED_0[252];
struct { /* offset: 0x100, array step: 0x10 */
uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
} CHANNEL[4];
} volatile *PIT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PIT - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
* @{
*/
/* PIT - Register accessors */
#define PIT_MCR_REG(base) ((base)->MCR)
#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
/**
* @}
*/ /* end of group PIT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PIT Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup PIT_Register_Masks PIT Register Masks
* @{
*/
/* MCR Bit Fields */
#define PIT_MCR_FRZ_MASK 0x1u
#define PIT_MCR_FRZ_SHIFT 0
#define PIT_MCR_MDIS_MASK 0x2u
#define PIT_MCR_MDIS_SHIFT 1
/* LDVAL Bit Fields */
#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
#define PIT_LDVAL_TSV_SHIFT 0
#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
/* CVAL Bit Fields */
#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
#define PIT_CVAL_TVL_SHIFT 0
#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
/* TCTRL Bit Fields */
#define PIT_TCTRL_TEN_MASK 0x1u
#define PIT_TCTRL_TEN_SHIFT 0
#define PIT_TCTRL_TIE_MASK 0x2u
#define PIT_TCTRL_TIE_SHIFT 1
/* TFLG Bit Fields */
#define PIT_TFLG_TIF_MASK 0x1u
#define PIT_TFLG_TIF_SHIFT 0
/**
* @}
*/ /* end of group PIT_Register_Masks */
/* PIT - Peripheral instance base addresses */
/** Peripheral PIT base pointer */
#define PIT_BASE_PTR ((PIT_MemMapPtr)0x40037000u)
/* ----------------------------------------------------------------------------
-- PIT - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
* @{
*/
/* PIT - Register instance definitions */
/* PIT */
#define PIT_MCR PIT_MCR_REG(PIT_BASE_PTR)
#define PIT_LDVAL0 PIT_LDVAL_REG(PIT_BASE_PTR,0)
#define PIT_CVAL0 PIT_CVAL_REG(PIT_BASE_PTR,0)
#define PIT_TCTRL0 PIT_TCTRL_REG(PIT_BASE_PTR,0)
#define PIT_TFLG0 PIT_TFLG_REG(PIT_BASE_PTR,0)
#define PIT_LDVAL1 PIT_LDVAL_REG(PIT_BASE_PTR,1)
#define PIT_CVAL1 PIT_CVAL_REG(PIT_BASE_PTR,1)
#define PIT_TCTRL1 PIT_TCTRL_REG(PIT_BASE_PTR,1)
#define PIT_TFLG1 PIT_TFLG_REG(PIT_BASE_PTR,1)
#define PIT_LDVAL2 PIT_LDVAL_REG(PIT_BASE_PTR,2)
#define PIT_CVAL2 PIT_CVAL_REG(PIT_BASE_PTR,2)
#define PIT_TCTRL2 PIT_TCTRL_REG(PIT_BASE_PTR,2)
#define PIT_TFLG2 PIT_TFLG_REG(PIT_BASE_PTR,2)
#define PIT_LDVAL3 PIT_LDVAL_REG(PIT_BASE_PTR,3)
#define PIT_CVAL3 PIT_CVAL_REG(PIT_BASE_PTR,3)
#define PIT_TCTRL3 PIT_TCTRL_REG(PIT_BASE_PTR,3)
#define PIT_TFLG3 PIT_TFLG_REG(PIT_BASE_PTR,3)
/* PIT - Register array accessors */
#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT_BASE_PTR,index)
#define PIT_CVAL(index) PIT_CVAL_REG(PIT_BASE_PTR,index)
#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT_BASE_PTR,index)
#define PIT_TFLG(index) PIT_TFLG_REG(PIT_BASE_PTR,index)
/**
* @}
*/ /* end of group PIT_Register_Accessor_Macros */
/**
* @}
*/ /* end of group PIT_Peripheral */
/* ----------------------------------------------------------------------------
-- PMC
---------------------------------------------------------------------------- */
/**
* @addtogroup PMC_Peripheral PMC
* @{
*/
/** PMC - Peripheral register structure */
typedef struct PMC_MemMap {
uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
} volatile *PMC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PMC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
* @{
*/
/* PMC - Register accessors */
#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
#define PMC_REGSC_REG(base) ((base)->REGSC)
/**
* @}
*/ /* end of group PMC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PMC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup PMC_Register_Masks PMC Register Masks
* @{
*/
/* LVDSC1 Bit Fields */
#define PMC_LVDSC1_LVDV_MASK 0x3u
#define PMC_LVDSC1_LVDV_SHIFT 0
#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
#define PMC_LVDSC1_LVDRE_MASK 0x10u
#define PMC_LVDSC1_LVDRE_SHIFT 4
#define PMC_LVDSC1_LVDIE_MASK 0x20u
#define PMC_LVDSC1_LVDIE_SHIFT 5
#define PMC_LVDSC1_LVDACK_MASK 0x40u
#define PMC_LVDSC1_LVDACK_SHIFT 6
#define PMC_LVDSC1_LVDF_MASK 0x80u
#define PMC_LVDSC1_LVDF_SHIFT 7
/* LVDSC2 Bit Fields */
#define PMC_LVDSC2_LVWV_MASK 0x3u
#define PMC_LVDSC2_LVWV_SHIFT 0
#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
#define PMC_LVDSC2_LVWIE_MASK 0x20u
#define PMC_LVDSC2_LVWIE_SHIFT 5
#define PMC_LVDSC2_LVWACK_MASK 0x40u
#define PMC_LVDSC2_LVWACK_SHIFT 6
#define PMC_LVDSC2_LVWF_MASK 0x80u
#define PMC_LVDSC2_LVWF_SHIFT 7
/* REGSC Bit Fields */
#define PMC_REGSC_BGBE_MASK 0x1u
#define PMC_REGSC_BGBE_SHIFT 0
#define PMC_REGSC_REGONS_MASK 0x4u
#define PMC_REGSC_REGONS_SHIFT 2
#define PMC_REGSC_VLPRS_MASK 0x8u
#define PMC_REGSC_VLPRS_SHIFT 3
#define PMC_REGSC_TRAMPO_MASK 0x10u
#define PMC_REGSC_TRAMPO_SHIFT 4
/**
* @}
*/ /* end of group PMC_Register_Masks */
/* PMC - Peripheral instance base addresses */
/** Peripheral PMC base pointer */
#define PMC_BASE_PTR ((PMC_MemMapPtr)0x4007D000u)
/* ----------------------------------------------------------------------------
-- PMC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
* @{
*/
/* PMC - Register instance definitions */
/* PMC */
#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC_BASE_PTR)
#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC_BASE_PTR)
#define PMC_REGSC PMC_REGSC_REG(PMC_BASE_PTR)
/**
* @}
*/ /* end of group PMC_Register_Accessor_Macros */
/**
* @}
*/ /* end of group PMC_Peripheral */
/* ----------------------------------------------------------------------------
-- PORT
---------------------------------------------------------------------------- */
/**
* @addtogroup PORT_Peripheral PORT
* @{
*/
/** PORT - Peripheral register structure */
typedef struct PORT_MemMap {
uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
uint8_t RESERVED_0[24];
uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
uint8_t RESERVED_1[28];
uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
} volatile *PORT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- PORT - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
* @{
*/
/* PORT - Register accessors */
#define PORT_PCR_REG(base,index) ((base)->PCR[index])
#define PORT_GPCLR_REG(base) ((base)->GPCLR)
#define PORT_GPCHR_REG(base) ((base)->GPCHR)
#define PORT_ISFR_REG(base) ((base)->ISFR)
#define PORT_DFER_REG(base) ((base)->DFER)
#define PORT_DFCR_REG(base) ((base)->DFCR)
#define PORT_DFWR_REG(base) ((base)->DFWR)
/**
* @}
*/ /* end of group PORT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- PORT Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup PORT_Register_Masks PORT Register Masks
* @{
*/
/* PCR Bit Fields */
#define PORT_PCR_PS_MASK 0x1u
#define PORT_PCR_PS_SHIFT 0
#define PORT_PCR_PE_MASK 0x2u
#define PORT_PCR_PE_SHIFT 1
#define PORT_PCR_SRE_MASK 0x4u
#define PORT_PCR_SRE_SHIFT 2
#define PORT_PCR_PFE_MASK 0x10u
#define PORT_PCR_PFE_SHIFT 4
#define PORT_PCR_ODE_MASK 0x20u
#define PORT_PCR_ODE_SHIFT 5
#define PORT_PCR_DSE_MASK 0x40u
#define PORT_PCR_DSE_SHIFT 6
#define PORT_PCR_MUX_MASK 0x700u
#define PORT_PCR_MUX_SHIFT 8
#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
#define PORT_PCR_LK_MASK 0x8000u
#define PORT_PCR_LK_SHIFT 15
#define PORT_PCR_IRQC_MASK 0xF0000u
#define PORT_PCR_IRQC_SHIFT 16
#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
#define PORT_PCR_ISF_MASK 0x1000000u
#define PORT_PCR_ISF_SHIFT 24
/* GPCLR Bit Fields */
#define PORT_GPCLR_GPWD_MASK 0xFFFFu
#define PORT_GPCLR_GPWD_SHIFT 0
#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
#define PORT_GPCLR_GPWE_SHIFT 16
#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
/* GPCHR Bit Fields */
#define PORT_GPCHR_GPWD_MASK 0xFFFFu
#define PORT_GPCHR_GPWD_SHIFT 0
#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
#define PORT_GPCHR_GPWE_SHIFT 16
#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
/* ISFR Bit Fields */
#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
#define PORT_ISFR_ISF_SHIFT 0
#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
/* DFER Bit Fields */
#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
#define PORT_DFER_DFE_SHIFT 0
#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
/* DFCR Bit Fields */
#define PORT_DFCR_CS_MASK 0x1u
#define PORT_DFCR_CS_SHIFT 0
/* DFWR Bit Fields */
#define PORT_DFWR_FILT_MASK 0x1Fu
#define PORT_DFWR_FILT_SHIFT 0
#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
/**
* @}
*/ /* end of group PORT_Register_Masks */
/* PORT - Peripheral instance base addresses */
/** Peripheral PORTA base pointer */
#define PORTA_BASE_PTR ((PORT_MemMapPtr)0x40049000u)
/** Peripheral PORTB base pointer */
#define PORTB_BASE_PTR ((PORT_MemMapPtr)0x4004A000u)
/** Peripheral PORTC base pointer */
#define PORTC_BASE_PTR ((PORT_MemMapPtr)0x4004B000u)
/** Peripheral PORTD base pointer */
#define PORTD_BASE_PTR ((PORT_MemMapPtr)0x4004C000u)
/** Peripheral PORTE base pointer */
#define PORTE_BASE_PTR ((PORT_MemMapPtr)0x4004D000u)
/* ----------------------------------------------------------------------------
-- PORT - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
* @{
*/
/* PORT - Register instance definitions */
/* PORTA */
#define PORTA_PCR0 PORT_PCR_REG(PORTA_BASE_PTR,0)
#define PORTA_PCR1 PORT_PCR_REG(PORTA_BASE_PTR,1)
#define PORTA_PCR2 PORT_PCR_REG(PORTA_BASE_PTR,2)
#define PORTA_PCR3 PORT_PCR_REG(PORTA_BASE_PTR,3)
#define PORTA_PCR4 PORT_PCR_REG(PORTA_BASE_PTR,4)
#define PORTA_PCR5 PORT_PCR_REG(PORTA_BASE_PTR,5)
#define PORTA_PCR6 PORT_PCR_REG(PORTA_BASE_PTR,6)
#define PORTA_PCR7 PORT_PCR_REG(PORTA_BASE_PTR,7)
#define PORTA_PCR8 PORT_PCR_REG(PORTA_BASE_PTR,8)
#define PORTA_PCR9 PORT_PCR_REG(PORTA_BASE_PTR,9)
#define PORTA_PCR10 PORT_PCR_REG(PORTA_BASE_PTR,10)
#define PORTA_PCR11 PORT_PCR_REG(PORTA_BASE_PTR,11)
#define PORTA_PCR12 PORT_PCR_REG(PORTA_BASE_PTR,12)
#define PORTA_PCR13 PORT_PCR_REG(PORTA_BASE_PTR,13)
#define PORTA_PCR14 PORT_PCR_REG(PORTA_BASE_PTR,14)
#define PORTA_PCR15 PORT_PCR_REG(PORTA_BASE_PTR,15)
#define PORTA_PCR16 PORT_PCR_REG(PORTA_BASE_PTR,16)
#define PORTA_PCR17 PORT_PCR_REG(PORTA_BASE_PTR,17)
#define PORTA_PCR18 PORT_PCR_REG(PORTA_BASE_PTR,18)
#define PORTA_PCR19 PORT_PCR_REG(PORTA_BASE_PTR,19)
#define PORTA_PCR20 PORT_PCR_REG(PORTA_BASE_PTR,20)
#define PORTA_PCR21 PORT_PCR_REG(PORTA_BASE_PTR,21)
#define PORTA_PCR22 PORT_PCR_REG(PORTA_BASE_PTR,22)
#define PORTA_PCR23 PORT_PCR_REG(PORTA_BASE_PTR,23)
#define PORTA_PCR24 PORT_PCR_REG(PORTA_BASE_PTR,24)
#define PORTA_PCR25 PORT_PCR_REG(PORTA_BASE_PTR,25)
#define PORTA_PCR26 PORT_PCR_REG(PORTA_BASE_PTR,26)
#define PORTA_PCR27 PORT_PCR_REG(PORTA_BASE_PTR,27)
#define PORTA_PCR28 PORT_PCR_REG(PORTA_BASE_PTR,28)
#define PORTA_PCR29 PORT_PCR_REG(PORTA_BASE_PTR,29)
#define PORTA_PCR30 PORT_PCR_REG(PORTA_BASE_PTR,30)
#define PORTA_PCR31 PORT_PCR_REG(PORTA_BASE_PTR,31)
#define PORTA_GPCLR PORT_GPCLR_REG(PORTA_BASE_PTR)
#define PORTA_GPCHR PORT_GPCHR_REG(PORTA_BASE_PTR)
#define PORTA_ISFR PORT_ISFR_REG(PORTA_BASE_PTR)
#define PORTA_DFER PORT_DFER_REG(PORTA_BASE_PTR)
#define PORTA_DFCR PORT_DFCR_REG(PORTA_BASE_PTR)
#define PORTA_DFWR PORT_DFWR_REG(PORTA_BASE_PTR)
/* PORTB */
#define PORTB_PCR0 PORT_PCR_REG(PORTB_BASE_PTR,0)
#define PORTB_PCR1 PORT_PCR_REG(PORTB_BASE_PTR,1)
#define PORTB_PCR2 PORT_PCR_REG(PORTB_BASE_PTR,2)
#define PORTB_PCR3 PORT_PCR_REG(PORTB_BASE_PTR,3)
#define PORTB_PCR4 PORT_PCR_REG(PORTB_BASE_PTR,4)
#define PORTB_PCR5 PORT_PCR_REG(PORTB_BASE_PTR,5)
#define PORTB_PCR6 PORT_PCR_REG(PORTB_BASE_PTR,6)
#define PORTB_PCR7 PORT_PCR_REG(PORTB_BASE_PTR,7)
#define PORTB_PCR8 PORT_PCR_REG(PORTB_BASE_PTR,8)
#define PORTB_PCR9 PORT_PCR_REG(PORTB_BASE_PTR,9)
#define PORTB_PCR10 PORT_PCR_REG(PORTB_BASE_PTR,10)
#define PORTB_PCR11 PORT_PCR_REG(PORTB_BASE_PTR,11)
#define PORTB_PCR12 PORT_PCR_REG(PORTB_BASE_PTR,12)
#define PORTB_PCR13 PORT_PCR_REG(PORTB_BASE_PTR,13)
#define PORTB_PCR14 PORT_PCR_REG(PORTB_BASE_PTR,14)
#define PORTB_PCR15 PORT_PCR_REG(PORTB_BASE_PTR,15)
#define PORTB_PCR16 PORT_PCR_REG(PORTB_BASE_PTR,16)
#define PORTB_PCR17 PORT_PCR_REG(PORTB_BASE_PTR,17)
#define PORTB_PCR18 PORT_PCR_REG(PORTB_BASE_PTR,18)
#define PORTB_PCR19 PORT_PCR_REG(PORTB_BASE_PTR,19)
#define PORTB_PCR20 PORT_PCR_REG(PORTB_BASE_PTR,20)
#define PORTB_PCR21 PORT_PCR_REG(PORTB_BASE_PTR,21)
#define PORTB_PCR22 PORT_PCR_REG(PORTB_BASE_PTR,22)
#define PORTB_PCR23 PORT_PCR_REG(PORTB_BASE_PTR,23)
#define PORTB_PCR24 PORT_PCR_REG(PORTB_BASE_PTR,24)
#define PORTB_PCR25 PORT_PCR_REG(PORTB_BASE_PTR,25)
#define PORTB_PCR26 PORT_PCR_REG(PORTB_BASE_PTR,26)
#define PORTB_PCR27 PORT_PCR_REG(PORTB_BASE_PTR,27)
#define PORTB_PCR28 PORT_PCR_REG(PORTB_BASE_PTR,28)
#define PORTB_PCR29 PORT_PCR_REG(PORTB_BASE_PTR,29)
#define PORTB_PCR30 PORT_PCR_REG(PORTB_BASE_PTR,30)
#define PORTB_PCR31 PORT_PCR_REG(PORTB_BASE_PTR,31)
#define PORTB_GPCLR PORT_GPCLR_REG(PORTB_BASE_PTR)
#define PORTB_GPCHR PORT_GPCHR_REG(PORTB_BASE_PTR)
#define PORTB_ISFR PORT_ISFR_REG(PORTB_BASE_PTR)
#define PORTB_DFER PORT_DFER_REG(PORTB_BASE_PTR)
#define PORTB_DFCR PORT_DFCR_REG(PORTB_BASE_PTR)
#define PORTB_DFWR PORT_DFWR_REG(PORTB_BASE_PTR)
/* PORTC */
#define PORTC_PCR0 PORT_PCR_REG(PORTC_BASE_PTR,0)
#define PORTC_PCR1 PORT_PCR_REG(PORTC_BASE_PTR,1)
#define PORTC_PCR2 PORT_PCR_REG(PORTC_BASE_PTR,2)
#define PORTC_PCR3 PORT_PCR_REG(PORTC_BASE_PTR,3)
#define PORTC_PCR4 PORT_PCR_REG(PORTC_BASE_PTR,4)
#define PORTC_PCR5 PORT_PCR_REG(PORTC_BASE_PTR,5)
#define PORTC_PCR6 PORT_PCR_REG(PORTC_BASE_PTR,6)
#define PORTC_PCR7 PORT_PCR_REG(PORTC_BASE_PTR,7)
#define PORTC_PCR8 PORT_PCR_REG(PORTC_BASE_PTR,8)
#define PORTC_PCR9 PORT_PCR_REG(PORTC_BASE_PTR,9)
#define PORTC_PCR10 PORT_PCR_REG(PORTC_BASE_PTR,10)
#define PORTC_PCR11 PORT_PCR_REG(PORTC_BASE_PTR,11)
#define PORTC_PCR12 PORT_PCR_REG(PORTC_BASE_PTR,12)
#define PORTC_PCR13 PORT_PCR_REG(PORTC_BASE_PTR,13)
#define PORTC_PCR14 PORT_PCR_REG(PORTC_BASE_PTR,14)
#define PORTC_PCR15 PORT_PCR_REG(PORTC_BASE_PTR,15)
#define PORTC_PCR16 PORT_PCR_REG(PORTC_BASE_PTR,16)
#define PORTC_PCR17 PORT_PCR_REG(PORTC_BASE_PTR,17)
#define PORTC_PCR18 PORT_PCR_REG(PORTC_BASE_PTR,18)
#define PORTC_PCR19 PORT_PCR_REG(PORTC_BASE_PTR,19)
#define PORTC_PCR20 PORT_PCR_REG(PORTC_BASE_PTR,20)
#define PORTC_PCR21 PORT_PCR_REG(PORTC_BASE_PTR,21)
#define PORTC_PCR22 PORT_PCR_REG(PORTC_BASE_PTR,22)
#define PORTC_PCR23 PORT_PCR_REG(PORTC_BASE_PTR,23)
#define PORTC_PCR24 PORT_PCR_REG(PORTC_BASE_PTR,24)
#define PORTC_PCR25 PORT_PCR_REG(PORTC_BASE_PTR,25)
#define PORTC_PCR26 PORT_PCR_REG(PORTC_BASE_PTR,26)
#define PORTC_PCR27 PORT_PCR_REG(PORTC_BASE_PTR,27)
#define PORTC_PCR28 PORT_PCR_REG(PORTC_BASE_PTR,28)
#define PORTC_PCR29 PORT_PCR_REG(PORTC_BASE_PTR,29)
#define PORTC_PCR30 PORT_PCR_REG(PORTC_BASE_PTR,30)
#define PORTC_PCR31 PORT_PCR_REG(PORTC_BASE_PTR,31)
#define PORTC_GPCLR PORT_GPCLR_REG(PORTC_BASE_PTR)
#define PORTC_GPCHR PORT_GPCHR_REG(PORTC_BASE_PTR)
#define PORTC_ISFR PORT_ISFR_REG(PORTC_BASE_PTR)
#define PORTC_DFER PORT_DFER_REG(PORTC_BASE_PTR)
#define PORTC_DFCR PORT_DFCR_REG(PORTC_BASE_PTR)
#define PORTC_DFWR PORT_DFWR_REG(PORTC_BASE_PTR)
/* PORTD */
#define PORTD_PCR0 PORT_PCR_REG(PORTD_BASE_PTR,0)
#define PORTD_PCR1 PORT_PCR_REG(PORTD_BASE_PTR,1)
#define PORTD_PCR2 PORT_PCR_REG(PORTD_BASE_PTR,2)
#define PORTD_PCR3 PORT_PCR_REG(PORTD_BASE_PTR,3)
#define PORTD_PCR4 PORT_PCR_REG(PORTD_BASE_PTR,4)
#define PORTD_PCR5 PORT_PCR_REG(PORTD_BASE_PTR,5)
#define PORTD_PCR6 PORT_PCR_REG(PORTD_BASE_PTR,6)
#define PORTD_PCR7 PORT_PCR_REG(PORTD_BASE_PTR,7)
#define PORTD_PCR8 PORT_PCR_REG(PORTD_BASE_PTR,8)
#define PORTD_PCR9 PORT_PCR_REG(PORTD_BASE_PTR,9)
#define PORTD_PCR10 PORT_PCR_REG(PORTD_BASE_PTR,10)
#define PORTD_PCR11 PORT_PCR_REG(PORTD_BASE_PTR,11)
#define PORTD_PCR12 PORT_PCR_REG(PORTD_BASE_PTR,12)
#define PORTD_PCR13 PORT_PCR_REG(PORTD_BASE_PTR,13)
#define PORTD_PCR14 PORT_PCR_REG(PORTD_BASE_PTR,14)
#define PORTD_PCR15 PORT_PCR_REG(PORTD_BASE_PTR,15)
#define PORTD_PCR16 PORT_PCR_REG(PORTD_BASE_PTR,16)
#define PORTD_PCR17 PORT_PCR_REG(PORTD_BASE_PTR,17)
#define PORTD_PCR18 PORT_PCR_REG(PORTD_BASE_PTR,18)
#define PORTD_PCR19 PORT_PCR_REG(PORTD_BASE_PTR,19)
#define PORTD_PCR20 PORT_PCR_REG(PORTD_BASE_PTR,20)
#define PORTD_PCR21 PORT_PCR_REG(PORTD_BASE_PTR,21)
#define PORTD_PCR22 PORT_PCR_REG(PORTD_BASE_PTR,22)
#define PORTD_PCR23 PORT_PCR_REG(PORTD_BASE_PTR,23)
#define PORTD_PCR24 PORT_PCR_REG(PORTD_BASE_PTR,24)
#define PORTD_PCR25 PORT_PCR_REG(PORTD_BASE_PTR,25)
#define PORTD_PCR26 PORT_PCR_REG(PORTD_BASE_PTR,26)
#define PORTD_PCR27 PORT_PCR_REG(PORTD_BASE_PTR,27)
#define PORTD_PCR28 PORT_PCR_REG(PORTD_BASE_PTR,28)
#define PORTD_PCR29 PORT_PCR_REG(PORTD_BASE_PTR,29)
#define PORTD_PCR30 PORT_PCR_REG(PORTD_BASE_PTR,30)
#define PORTD_PCR31 PORT_PCR_REG(PORTD_BASE_PTR,31)
#define PORTD_GPCLR PORT_GPCLR_REG(PORTD_BASE_PTR)
#define PORTD_GPCHR PORT_GPCHR_REG(PORTD_BASE_PTR)
#define PORTD_ISFR PORT_ISFR_REG(PORTD_BASE_PTR)
#define PORTD_DFER PORT_DFER_REG(PORTD_BASE_PTR)
#define PORTD_DFCR PORT_DFCR_REG(PORTD_BASE_PTR)
#define PORTD_DFWR PORT_DFWR_REG(PORTD_BASE_PTR)
/* PORTE */
#define PORTE_PCR0 PORT_PCR_REG(PORTE_BASE_PTR,0)
#define PORTE_PCR1 PORT_PCR_REG(PORTE_BASE_PTR,1)
#define PORTE_PCR2 PORT_PCR_REG(PORTE_BASE_PTR,2)
#define PORTE_PCR3 PORT_PCR_REG(PORTE_BASE_PTR,3)
#define PORTE_PCR4 PORT_PCR_REG(PORTE_BASE_PTR,4)
#define PORTE_PCR5 PORT_PCR_REG(PORTE_BASE_PTR,5)
#define PORTE_PCR6 PORT_PCR_REG(PORTE_BASE_PTR,6)
#define PORTE_PCR7 PORT_PCR_REG(PORTE_BASE_PTR,7)
#define PORTE_PCR8 PORT_PCR_REG(PORTE_BASE_PTR,8)
#define PORTE_PCR9 PORT_PCR_REG(PORTE_BASE_PTR,9)
#define PORTE_PCR10 PORT_PCR_REG(PORTE_BASE_PTR,10)
#define PORTE_PCR11 PORT_PCR_REG(PORTE_BASE_PTR,11)
#define PORTE_PCR12 PORT_PCR_REG(PORTE_BASE_PTR,12)
#define PORTE_PCR13 PORT_PCR_REG(PORTE_BASE_PTR,13)
#define PORTE_PCR14 PORT_PCR_REG(PORTE_BASE_PTR,14)
#define PORTE_PCR15 PORT_PCR_REG(PORTE_BASE_PTR,15)
#define PORTE_PCR16 PORT_PCR_REG(PORTE_BASE_PTR,16)
#define PORTE_PCR17 PORT_PCR_REG(PORTE_BASE_PTR,17)
#define PORTE_PCR18 PORT_PCR_REG(PORTE_BASE_PTR,18)
#define PORTE_PCR19 PORT_PCR_REG(PORTE_BASE_PTR,19)
#define PORTE_PCR20 PORT_PCR_REG(PORTE_BASE_PTR,20)
#define PORTE_PCR21 PORT_PCR_REG(PORTE_BASE_PTR,21)
#define PORTE_PCR22 PORT_PCR_REG(PORTE_BASE_PTR,22)
#define PORTE_PCR23 PORT_PCR_REG(PORTE_BASE_PTR,23)
#define PORTE_PCR24 PORT_PCR_REG(PORTE_BASE_PTR,24)
#define PORTE_PCR25 PORT_PCR_REG(PORTE_BASE_PTR,25)
#define PORTE_PCR26 PORT_PCR_REG(PORTE_BASE_PTR,26)
#define PORTE_PCR27 PORT_PCR_REG(PORTE_BASE_PTR,27)
#define PORTE_PCR28 PORT_PCR_REG(PORTE_BASE_PTR,28)
#define PORTE_PCR29 PORT_PCR_REG(PORTE_BASE_PTR,29)
#define PORTE_PCR30 PORT_PCR_REG(PORTE_BASE_PTR,30)
#define PORTE_PCR31 PORT_PCR_REG(PORTE_BASE_PTR,31)
#define PORTE_GPCLR PORT_GPCLR_REG(PORTE_BASE_PTR)
#define PORTE_GPCHR PORT_GPCHR_REG(PORTE_BASE_PTR)
#define PORTE_ISFR PORT_ISFR_REG(PORTE_BASE_PTR)
#define PORTE_DFER PORT_DFER_REG(PORTE_BASE_PTR)
#define PORTE_DFCR PORT_DFCR_REG(PORTE_BASE_PTR)
#define PORTE_DFWR PORT_DFWR_REG(PORTE_BASE_PTR)
/* PORT - Register array accessors */
#define PORTA_PCR(index) PORT_PCR_REG(PORTA_BASE_PTR,index)
#define PORTB_PCR(index) PORT_PCR_REG(PORTB_BASE_PTR,index)
#define PORTC_PCR(index) PORT_PCR_REG(PORTC_BASE_PTR,index)
#define PORTD_PCR(index) PORT_PCR_REG(PORTD_BASE_PTR,index)
#define PORTE_PCR(index) PORT_PCR_REG(PORTE_BASE_PTR,index)
/**
* @}
*/ /* end of group PORT_Register_Accessor_Macros */
/**
* @}
*/ /* end of group PORT_Peripheral */
/* ----------------------------------------------------------------------------
-- GPIO
---------------------------------------------------------------------------- */
/**
* @addtogroup GPIO_Peripheral GPIO
* @{
*/
/** GPIO - Peripheral register structure */
typedef struct GPIO_MemMap {
uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} volatile *GPIO_MemMapPtr;
/* ----------------------------------------------------------------------------
-- GPIO - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
* @{
*/
/* GPIO - Register accessors */
#define GPIO_PDOR_REG(base) ((base)->PDOR)
#define GPIO_PSOR_REG(base) ((base)->PSOR)
#define GPIO_PCOR_REG(base) ((base)->PCOR)
#define GPIO_PTOR_REG(base) ((base)->PTOR)
#define GPIO_PDIR_REG(base) ((base)->PDIR)
#define GPIO_PDDR_REG(base) ((base)->PDDR)
/**
* @}
*/ /* end of group GPIO_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- GPIO Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
/* PDOR Bit Fields */
#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
#define GPIO_PDOR_PDO_SHIFT 0
#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
/* PSOR Bit Fields */
#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
#define GPIO_PSOR_PTSO_SHIFT 0
#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
/* PCOR Bit Fields */
#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
#define GPIO_PCOR_PTCO_SHIFT 0
#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
/* PTOR Bit Fields */
#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
#define GPIO_PTOR_PTTO_SHIFT 0
#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
/* PDIR Bit Fields */
#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
#define GPIO_PDIR_PDI_SHIFT 0
#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
/* PDDR Bit Fields */
#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
#define GPIO_PDDR_PDD_SHIFT 0
#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
/**
* @}
*/ /* end of group GPIO_Register_Masks */
/* GPIO - Peripheral instance base addresses */
/** Peripheral PTA base pointer */
#define PTA_BASE_PTR ((GPIO_MemMapPtr)0x400FF000u)
/** Peripheral PTB base pointer */
#define PTB_BASE_PTR ((GPIO_MemMapPtr)0x400FF040u)
/** Peripheral PTC base pointer */
#define PTC_BASE_PTR ((GPIO_MemMapPtr)0x400FF080u)
/** Peripheral PTD base pointer */
#define PTD_BASE_PTR ((GPIO_MemMapPtr)0x400FF0C0u)
/** Peripheral PTE base pointer */
#define PTE_BASE_PTR ((GPIO_MemMapPtr)0x400FF100u)
/* ----------------------------------------------------------------------------
-- GPIO - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
* @{
*/
/* GPIO - Register instance definitions */
/* PTA */
#define GPIOA_PDOR GPIO_PDOR_REG(PTA_BASE_PTR)
#define GPIOA_PSOR GPIO_PSOR_REG(PTA_BASE_PTR)
#define GPIOA_PCOR GPIO_PCOR_REG(PTA_BASE_PTR)
#define GPIOA_PTOR GPIO_PTOR_REG(PTA_BASE_PTR)
#define GPIOA_PDIR GPIO_PDIR_REG(PTA_BASE_PTR)
#define GPIOA_PDDR GPIO_PDDR_REG(PTA_BASE_PTR)
/* PTB */
#define GPIOB_PDOR GPIO_PDOR_REG(PTB_BASE_PTR)
#define GPIOB_PSOR GPIO_PSOR_REG(PTB_BASE_PTR)
#define GPIOB_PCOR GPIO_PCOR_REG(PTB_BASE_PTR)
#define GPIOB_PTOR GPIO_PTOR_REG(PTB_BASE_PTR)
#define GPIOB_PDIR GPIO_PDIR_REG(PTB_BASE_PTR)
#define GPIOB_PDDR GPIO_PDDR_REG(PTB_BASE_PTR)
/* PTC */
#define GPIOC_PDOR GPIO_PDOR_REG(PTC_BASE_PTR)
#define GPIOC_PSOR GPIO_PSOR_REG(PTC_BASE_PTR)
#define GPIOC_PCOR GPIO_PCOR_REG(PTC_BASE_PTR)
#define GPIOC_PTOR GPIO_PTOR_REG(PTC_BASE_PTR)
#define GPIOC_PDIR GPIO_PDIR_REG(PTC_BASE_PTR)
#define GPIOC_PDDR GPIO_PDDR_REG(PTC_BASE_PTR)
/* PTD */
#define GPIOD_PDOR GPIO_PDOR_REG(PTD_BASE_PTR)
#define GPIOD_PSOR GPIO_PSOR_REG(PTD_BASE_PTR)
#define GPIOD_PCOR GPIO_PCOR_REG(PTD_BASE_PTR)
#define GPIOD_PTOR GPIO_PTOR_REG(PTD_BASE_PTR)
#define GPIOD_PDIR GPIO_PDIR_REG(PTD_BASE_PTR)
#define GPIOD_PDDR GPIO_PDDR_REG(PTD_BASE_PTR)
/* PTE */
#define GPIOE_PDOR GPIO_PDOR_REG(PTE_BASE_PTR)
#define GPIOE_PSOR GPIO_PSOR_REG(PTE_BASE_PTR)
#define GPIOE_PCOR GPIO_PCOR_REG(PTE_BASE_PTR)
#define GPIOE_PTOR GPIO_PTOR_REG(PTE_BASE_PTR)
#define GPIOE_PDIR GPIO_PDIR_REG(PTE_BASE_PTR)
#define GPIOE_PDDR GPIO_PDDR_REG(PTE_BASE_PTR)
/**
* @}
*/ /* end of group GPIO_Register_Accessor_Macros */
/**
* @}
*/ /* end of group GPIO_Peripheral */
/* ----------------------------------------------------------------------------
-- RFSYS
---------------------------------------------------------------------------- */
/**
* @addtogroup RFSYS_Peripheral RFSYS
* @{
*/
/** RFSYS - Peripheral register structure */
typedef struct RFSYS_MemMap {
uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
} volatile *RFSYS_MemMapPtr;
/* ----------------------------------------------------------------------------
-- RFSYS - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
* @{
*/
/* RFSYS - Register accessors */
#define RFSYS_REG_REG(base,index) ((base)->REG[index])
/**
* @}
*/ /* end of group RFSYS_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- RFSYS Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup RFSYS_Register_Masks RFSYS Register Masks
* @{
*/
/* REG Bit Fields */
#define RFSYS_REG_LL_MASK 0xFFu
#define RFSYS_REG_LL_SHIFT 0
#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
#define RFSYS_REG_LH_MASK 0xFF00u
#define RFSYS_REG_LH_SHIFT 8
#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
#define RFSYS_REG_HL_MASK 0xFF0000u
#define RFSYS_REG_HL_SHIFT 16
#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
#define RFSYS_REG_HH_MASK 0xFF000000u
#define RFSYS_REG_HH_SHIFT 24
#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
/**
* @}
*/ /* end of group RFSYS_Register_Masks */
/* RFSYS - Peripheral instance base addresses */
/** Peripheral RFSYS base pointer */
#define RFSYS_BASE_PTR ((RFSYS_MemMapPtr)0x40041000u)
/* ----------------------------------------------------------------------------
-- RFSYS - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
* @{
*/
/* RFSYS - Register instance definitions */
/* RFSYS */
#define RFSYS_REG0 RFSYS_REG_REG(RFSYS_BASE_PTR,0)
#define RFSYS_REG1 RFSYS_REG_REG(RFSYS_BASE_PTR,1)
#define RFSYS_REG2 RFSYS_REG_REG(RFSYS_BASE_PTR,2)
#define RFSYS_REG3 RFSYS_REG_REG(RFSYS_BASE_PTR,3)
#define RFSYS_REG4 RFSYS_REG_REG(RFSYS_BASE_PTR,4)
#define RFSYS_REG5 RFSYS_REG_REG(RFSYS_BASE_PTR,5)
#define RFSYS_REG6 RFSYS_REG_REG(RFSYS_BASE_PTR,6)
#define RFSYS_REG7 RFSYS_REG_REG(RFSYS_BASE_PTR,7)
/* RFSYS - Register array accessors */
#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS_BASE_PTR,index)
/**
* @}
*/ /* end of group RFSYS_Register_Accessor_Macros */
/**
* @}
*/ /* end of group RFSYS_Peripheral */
/* ----------------------------------------------------------------------------
-- RFVBAT
---------------------------------------------------------------------------- */
/**
* @addtogroup RFVBAT_Peripheral RFVBAT
* @{
*/
/** RFVBAT - Peripheral register structure */
typedef struct RFVBAT_MemMap {
uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
} volatile *RFVBAT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- RFVBAT - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
* @{
*/
/* RFVBAT - Register accessors */
#define RFVBAT_REG_REG(base,index) ((base)->REG[index])
/**
* @}
*/ /* end of group RFVBAT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- RFVBAT Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
* @{
*/
/* REG Bit Fields */
#define RFVBAT_REG_LL_MASK 0xFFu
#define RFVBAT_REG_LL_SHIFT 0
#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
#define RFVBAT_REG_LH_MASK 0xFF00u
#define RFVBAT_REG_LH_SHIFT 8
#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
#define RFVBAT_REG_HL_MASK 0xFF0000u
#define RFVBAT_REG_HL_SHIFT 16
#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
#define RFVBAT_REG_HH_MASK 0xFF000000u
#define RFVBAT_REG_HH_SHIFT 24
#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
/**
* @}
*/ /* end of group RFVBAT_Register_Masks */
/* RFVBAT - Peripheral instance base addresses */
/** Peripheral RFVBAT base pointer */
#define RFVBAT_BASE_PTR ((RFVBAT_MemMapPtr)0x4003E000u)
/* ----------------------------------------------------------------------------
-- RFVBAT - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
* @{
*/
/* RFVBAT - Register instance definitions */
/* RFVBAT */
#define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT_BASE_PTR,0)
#define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT_BASE_PTR,1)
#define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT_BASE_PTR,2)
#define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT_BASE_PTR,3)
#define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT_BASE_PTR,4)
#define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT_BASE_PTR,5)
#define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT_BASE_PTR,6)
#define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT_BASE_PTR,7)
/* RFVBAT - Register array accessors */
#define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT_BASE_PTR,index)
/**
* @}
*/ /* end of group RFVBAT_Register_Accessor_Macros */
/**
* @}
*/ /* end of group RFVBAT_Peripheral */
/* ----------------------------------------------------------------------------
-- RTC
---------------------------------------------------------------------------- */
/**
* @addtogroup RTC_Peripheral RTC
* @{
*/
/** RTC - Peripheral register structure */
typedef struct RTC_MemMap {
uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
uint32_t CR; /**< RTC Control Register, offset: 0x10 */
uint32_t SR; /**< RTC Status Register, offset: 0x14 */
uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
uint8_t RESERVED_0[2016];
uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
} volatile *RTC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- RTC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
* @{
*/
/* RTC - Register accessors */
#define RTC_TSR_REG(base) ((base)->TSR)
#define RTC_TPR_REG(base) ((base)->TPR)
#define RTC_TAR_REG(base) ((base)->TAR)
#define RTC_TCR_REG(base) ((base)->TCR)
#define RTC_CR_REG(base) ((base)->CR)
#define RTC_SR_REG(base) ((base)->SR)
#define RTC_LR_REG(base) ((base)->LR)
#define RTC_IER_REG(base) ((base)->IER)
#define RTC_WAR_REG(base) ((base)->WAR)
#define RTC_RAR_REG(base) ((base)->RAR)
/**
* @}
*/ /* end of group RTC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- RTC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup RTC_Register_Masks RTC Register Masks
* @{
*/
/* TSR Bit Fields */
#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
#define RTC_TSR_TSR_SHIFT 0
#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
/* TPR Bit Fields */
#define RTC_TPR_TPR_MASK 0xFFFFu
#define RTC_TPR_TPR_SHIFT 0
#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
/* TAR Bit Fields */
#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
#define RTC_TAR_TAR_SHIFT 0
#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
/* TCR Bit Fields */
#define RTC_TCR_TCR_MASK 0xFFu
#define RTC_TCR_TCR_SHIFT 0
#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
#define RTC_TCR_CIR_MASK 0xFF00u
#define RTC_TCR_CIR_SHIFT 8
#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
#define RTC_TCR_TCV_MASK 0xFF0000u
#define RTC_TCR_TCV_SHIFT 16
#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
#define RTC_TCR_CIC_MASK 0xFF000000u
#define RTC_TCR_CIC_SHIFT 24
#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
/* CR Bit Fields */
#define RTC_CR_SWR_MASK 0x1u
#define RTC_CR_SWR_SHIFT 0
#define RTC_CR_WPE_MASK 0x2u
#define RTC_CR_WPE_SHIFT 1
#define RTC_CR_SUP_MASK 0x4u
#define RTC_CR_SUP_SHIFT 2
#define RTC_CR_UM_MASK 0x8u
#define RTC_CR_UM_SHIFT 3
#define RTC_CR_OSCE_MASK 0x100u
#define RTC_CR_OSCE_SHIFT 8
#define RTC_CR_CLKO_MASK 0x200u
#define RTC_CR_CLKO_SHIFT 9
#define RTC_CR_SC16P_MASK 0x400u
#define RTC_CR_SC16P_SHIFT 10
#define RTC_CR_SC8P_MASK 0x800u
#define RTC_CR_SC8P_SHIFT 11
#define RTC_CR_SC4P_MASK 0x1000u
#define RTC_CR_SC4P_SHIFT 12
#define RTC_CR_SC2P_MASK 0x2000u
#define RTC_CR_SC2P_SHIFT 13
/* SR Bit Fields */
#define RTC_SR_TIF_MASK 0x1u
#define RTC_SR_TIF_SHIFT 0
#define RTC_SR_TOF_MASK 0x2u
#define RTC_SR_TOF_SHIFT 1
#define RTC_SR_TAF_MASK 0x4u
#define RTC_SR_TAF_SHIFT 2
#define RTC_SR_TCE_MASK 0x10u
#define RTC_SR_TCE_SHIFT 4
/* LR Bit Fields */
#define RTC_LR_TCL_MASK 0x8u
#define RTC_LR_TCL_SHIFT 3
#define RTC_LR_CRL_MASK 0x10u
#define RTC_LR_CRL_SHIFT 4
#define RTC_LR_SRL_MASK 0x20u
#define RTC_LR_SRL_SHIFT 5
#define RTC_LR_LRL_MASK 0x40u
#define RTC_LR_LRL_SHIFT 6
/* IER Bit Fields */
#define RTC_IER_TIIE_MASK 0x1u
#define RTC_IER_TIIE_SHIFT 0
#define RTC_IER_TOIE_MASK 0x2u
#define RTC_IER_TOIE_SHIFT 1
#define RTC_IER_TAIE_MASK 0x4u
#define RTC_IER_TAIE_SHIFT 2
/* WAR Bit Fields */
#define RTC_WAR_TSRW_MASK 0x1u
#define RTC_WAR_TSRW_SHIFT 0
#define RTC_WAR_TPRW_MASK 0x2u
#define RTC_WAR_TPRW_SHIFT 1
#define RTC_WAR_TARW_MASK 0x4u
#define RTC_WAR_TARW_SHIFT 2
#define RTC_WAR_TCRW_MASK 0x8u
#define RTC_WAR_TCRW_SHIFT 3
#define RTC_WAR_CRW_MASK 0x10u
#define RTC_WAR_CRW_SHIFT 4
#define RTC_WAR_SRW_MASK 0x20u
#define RTC_WAR_SRW_SHIFT 5
#define RTC_WAR_LRW_MASK 0x40u
#define RTC_WAR_LRW_SHIFT 6
#define RTC_WAR_IERW_MASK 0x80u
#define RTC_WAR_IERW_SHIFT 7
/* RAR Bit Fields */
#define RTC_RAR_TSRR_MASK 0x1u
#define RTC_RAR_TSRR_SHIFT 0
#define RTC_RAR_TPRR_MASK 0x2u
#define RTC_RAR_TPRR_SHIFT 1
#define RTC_RAR_TARR_MASK 0x4u
#define RTC_RAR_TARR_SHIFT 2
#define RTC_RAR_TCRR_MASK 0x8u
#define RTC_RAR_TCRR_SHIFT 3
#define RTC_RAR_CRR_MASK 0x10u
#define RTC_RAR_CRR_SHIFT 4
#define RTC_RAR_SRR_MASK 0x20u
#define RTC_RAR_SRR_SHIFT 5
#define RTC_RAR_LRR_MASK 0x40u
#define RTC_RAR_LRR_SHIFT 6
#define RTC_RAR_IERR_MASK 0x80u
#define RTC_RAR_IERR_SHIFT 7
/**
* @}
*/ /* end of group RTC_Register_Masks */
/* RTC - Peripheral instance base addresses */
/** Peripheral RTC base pointer */
#define RTC_BASE_PTR ((RTC_MemMapPtr)0x4003D000u)
/* ----------------------------------------------------------------------------
-- RTC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
* @{
*/
/* RTC - Register instance definitions */
/* RTC */
#define RTC_TSR RTC_TSR_REG(RTC_BASE_PTR)
#define RTC_TPR RTC_TPR_REG(RTC_BASE_PTR)
#define RTC_TAR RTC_TAR_REG(RTC_BASE_PTR)
#define RTC_TCR RTC_TCR_REG(RTC_BASE_PTR)
#define RTC_CR RTC_CR_REG(RTC_BASE_PTR)
#define RTC_SR RTC_SR_REG(RTC_BASE_PTR)
#define RTC_LR RTC_LR_REG(RTC_BASE_PTR)
#define RTC_IER RTC_IER_REG(RTC_BASE_PTR)
#define RTC_WAR RTC_WAR_REG(RTC_BASE_PTR)
#define RTC_RAR RTC_RAR_REG(RTC_BASE_PTR)
/**
* @}
*/ /* end of group RTC_Register_Accessor_Macros */
/**
* @}
*/ /* end of group RTC_Peripheral */
/* ----------------------------------------------------------------------------
-- SDHC
---------------------------------------------------------------------------- */
/**
* @addtogroup SDHC_Peripheral SDHC
* @{
*/
/** SDHC - Peripheral register structure */
typedef struct SDHC_MemMap {
uint32_t DSADDR; /**< DMA System Address Register, offset: 0x0 */
uint32_t BLKATTR; /**< Block Attributes Register, offset: 0x4 */
uint32_t CMDARG; /**< Command Argument Register, offset: 0x8 */
uint32_t XFERTYP; /**< Transfer Type Register, offset: 0xC */
uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
uint32_t DATPORT; /**< Buffer Data Port Register, offset: 0x20 */
uint32_t PRSSTAT; /**< Present State Register, offset: 0x24 */
uint32_t PROCTL; /**< Protocol Control Register, offset: 0x28 */
uint32_t SYSCTL; /**< System Control Register, offset: 0x2C */
uint32_t IRQSTAT; /**< Interrupt Status Register, offset: 0x30 */
uint32_t IRQSTATEN; /**< Interrupt Status Enable Register, offset: 0x34 */
uint32_t IRQSIGEN; /**< Interrupt Signal Enable Register, offset: 0x38 */
uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
uint8_t RESERVED_0[8];
uint32_t FEVT; /**< Force Event Register, offset: 0x50 */
uint32_t ADMAES; /**< ADMA Error Status Register, offset: 0x54 */
uint32_t ADSADDR; /**< ADMA System Address Register, offset: 0x58 */
uint8_t RESERVED_1[100];
uint32_t VENDOR; /**< Vendor Specific Register, offset: 0xC0 */
uint32_t MMCBOOT; /**< MMC Boot Register, offset: 0xC4 */
uint8_t RESERVED_2[52];
uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
} volatile *SDHC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- SDHC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
* @{
*/
/* SDHC - Register accessors */
#define SDHC_DSADDR_REG(base) ((base)->DSADDR)
#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
#define SDHC_CMDARG_REG(base) ((base)->CMDARG)
#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
#define SDHC_DATPORT_REG(base) ((base)->DATPORT)
#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
#define SDHC_PROCTL_REG(base) ((base)->PROCTL)
#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
#define SDHC_WML_REG(base) ((base)->WML)
#define SDHC_FEVT_REG(base) ((base)->FEVT)
#define SDHC_ADMAES_REG(base) ((base)->ADMAES)
#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
#define SDHC_VENDOR_REG(base) ((base)->VENDOR)
#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
/**
* @}
*/ /* end of group SDHC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- SDHC Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup SDHC_Register_Masks SDHC Register Masks
* @{
*/
/* DSADDR Bit Fields */
#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
#define SDHC_DSADDR_DSADDR_SHIFT 2
#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
/* BLKATTR Bit Fields */
#define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
#define SDHC_BLKATTR_BLKSIZE_SHIFT 0
#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
#define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
#define SDHC_BLKATTR_BLKCNT_SHIFT 16
#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
/* CMDARG Bit Fields */
#define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
#define SDHC_CMDARG_CMDARG_SHIFT 0
#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
/* XFERTYP Bit Fields */
#define SDHC_XFERTYP_DMAEN_MASK 0x1u
#define SDHC_XFERTYP_DMAEN_SHIFT 0
#define SDHC_XFERTYP_BCEN_MASK 0x2u
#define SDHC_XFERTYP_BCEN_SHIFT 1
#define SDHC_XFERTYP_AC12EN_MASK 0x4u
#define SDHC_XFERTYP_AC12EN_SHIFT 2
#define SDHC_XFERTYP_DTDSEL_MASK 0x10u
#define SDHC_XFERTYP_DTDSEL_SHIFT 4
#define SDHC_XFERTYP_MSBSEL_MASK 0x20u
#define SDHC_XFERTYP_MSBSEL_SHIFT 5
#define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
#define SDHC_XFERTYP_RSPTYP_SHIFT 16
#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
#define SDHC_XFERTYP_CCCEN_MASK 0x80000u
#define SDHC_XFERTYP_CCCEN_SHIFT 19
#define SDHC_XFERTYP_CICEN_MASK 0x100000u
#define SDHC_XFERTYP_CICEN_SHIFT 20
#define SDHC_XFERTYP_DPSEL_MASK 0x200000u
#define SDHC_XFERTYP_DPSEL_SHIFT 21
#define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
#define SDHC_XFERTYP_CMDTYP_SHIFT 22
#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
#define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
#define SDHC_XFERTYP_CMDINX_SHIFT 24
#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
/* CMDRSP Bit Fields */
#define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
#define SDHC_CMDRSP_CMDRSP0_SHIFT 0
#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
#define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
#define SDHC_CMDRSP_CMDRSP1_SHIFT 0
#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
#define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
#define SDHC_CMDRSP_CMDRSP2_SHIFT 0
#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
#define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
#define SDHC_CMDRSP_CMDRSP3_SHIFT 0
#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
/* DATPORT Bit Fields */
#define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
#define SDHC_DATPORT_DATCONT_SHIFT 0
#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
/* PRSSTAT Bit Fields */
#define SDHC_PRSSTAT_CIHB_MASK 0x1u
#define SDHC_PRSSTAT_CIHB_SHIFT 0
#define SDHC_PRSSTAT_CDIHB_MASK 0x2u
#define SDHC_PRSSTAT_CDIHB_SHIFT 1
#define SDHC_PRSSTAT_DLA_MASK 0x4u
#define SDHC_PRSSTAT_DLA_SHIFT 2
#define SDHC_PRSSTAT_SDSTB_MASK 0x8u
#define SDHC_PRSSTAT_SDSTB_SHIFT 3
#define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
#define SDHC_PRSSTAT_IPGOFF_SHIFT 4
#define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
#define SDHC_PRSSTAT_HCKOFF_SHIFT 5
#define SDHC_PRSSTAT_PEROFF_MASK 0x40u
#define SDHC_PRSSTAT_PEROFF_SHIFT 6
#define SDHC_PRSSTAT_SDOFF_MASK 0x80u
#define SDHC_PRSSTAT_SDOFF_SHIFT 7
#define SDHC_PRSSTAT_WTA_MASK 0x100u
#define SDHC_PRSSTAT_WTA_SHIFT 8
#define SDHC_PRSSTAT_RTA_MASK 0x200u
#define SDHC_PRSSTAT_RTA_SHIFT 9
#define SDHC_PRSSTAT_BWEN_MASK 0x400u
#define SDHC_PRSSTAT_BWEN_SHIFT 10
#define SDHC_PRSSTAT_BREN_MASK 0x800u
#define SDHC_PRSSTAT_BREN_SHIFT 11
#define SDHC_PRSSTAT_CINS_MASK 0x10000u
#define SDHC_PRSSTAT_CINS_SHIFT 16
#define SDHC_PRSSTAT_CLSL_MASK 0x800000u
#define SDHC_PRSSTAT_CLSL_SHIFT 23
#define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
#define SDHC_PRSSTAT_DLSL_SHIFT 24
#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
/* PROCTL Bit Fields */
#define SDHC_PROCTL_LCTL_MASK 0x1u
#define SDHC_PROCTL_LCTL_SHIFT 0
#define SDHC_PROCTL_DTW_MASK 0x6u
#define SDHC_PROCTL_DTW_SHIFT 1
#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
#define SDHC_PROCTL_D3CD_MASK 0x8u
#define SDHC_PROCTL_D3CD_SHIFT 3
#define SDHC_PROCTL_EMODE_MASK 0x30u
#define SDHC_PROCTL_EMODE_SHIFT 4
#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
#define SDHC_PROCTL_CDTL_MASK 0x40u
#define SDHC_PROCTL_CDTL_SHIFT 6
#define SDHC_PROCTL_CDSS_MASK 0x80u
#define SDHC_PROCTL_CDSS_SHIFT 7
#define SDHC_PROCTL_DMAS_MASK 0x300u
#define SDHC_PROCTL_DMAS_SHIFT 8
#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
#define SDHC_PROCTL_SABGREQ_MASK 0x10000u
#define SDHC_PROCTL_SABGREQ_SHIFT 16
#define SDHC_PROCTL_CREQ_MASK 0x20000u
#define SDHC_PROCTL_CREQ_SHIFT 17
#define SDHC_PROCTL_RWCTL_MASK 0x40000u
#define SDHC_PROCTL_RWCTL_SHIFT 18
#define SDHC_PROCTL_IABG_MASK 0x80000u
#define SDHC_PROCTL_IABG_SHIFT 19
#define SDHC_PROCTL_WECINT_MASK 0x1000000u
#define SDHC_PROCTL_WECINT_SHIFT 24
#define SDHC_PROCTL_WECINS_MASK 0x2000000u
#define SDHC_PROCTL_WECINS_SHIFT 25
#define SDHC_PROCTL_WECRM_MASK 0x4000000u
#define SDHC_PROCTL_WECRM_SHIFT 26
/* SYSCTL Bit Fields */
#define SDHC_SYSCTL_IPGEN_MASK 0x1u
#define SDHC_SYSCTL_IPGEN_SHIFT 0
#define SDHC_SYSCTL_HCKEN_MASK 0x2u
#define SDHC_SYSCTL_HCKEN_SHIFT 1
#define SDHC_SYSCTL_PEREN_MASK 0x4u
#define SDHC_SYSCTL_PEREN_SHIFT 2
#define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
#define SDHC_SYSCTL_SDCLKEN_SHIFT 3
#define SDHC_SYSCTL_DVS_MASK 0xF0u
#define SDHC_SYSCTL_DVS_SHIFT 4
#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
#define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
#define SDHC_SYSCTL_SDCLKFS_SHIFT 8
#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
#define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
#define SDHC_SYSCTL_DTOCV_SHIFT 16
#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
#define SDHC_SYSCTL_RSTA_MASK 0x1000000u
#define SDHC_SYSCTL_RSTA_SHIFT 24
#define SDHC_SYSCTL_RSTC_MASK 0x2000000u
#define SDHC_SYSCTL_RSTC_SHIFT 25
#define SDHC_SYSCTL_RSTD_MASK 0x4000000u
#define SDHC_SYSCTL_RSTD_SHIFT 26
#define SDHC_SYSCTL_INITA_MASK 0x8000000u
#define SDHC_SYSCTL_INITA_SHIFT 27
/* IRQSTAT Bit Fields */
#define SDHC_IRQSTAT_CC_MASK 0x1u
#define SDHC_IRQSTAT_CC_SHIFT 0
#define SDHC_IRQSTAT_TC_MASK 0x2u
#define SDHC_IRQSTAT_TC_SHIFT 1
#define SDHC_IRQSTAT_BGE_MASK 0x4u
#define SDHC_IRQSTAT_BGE_SHIFT 2
#define SDHC_IRQSTAT_DINT_MASK 0x8u
#define SDHC_IRQSTAT_DINT_SHIFT 3
#define SDHC_IRQSTAT_BWR_MASK 0x10u
#define SDHC_IRQSTAT_BWR_SHIFT 4
#define SDHC_IRQSTAT_BRR_MASK 0x20u
#define SDHC_IRQSTAT_BRR_SHIFT 5
#define SDHC_IRQSTAT_CINS_MASK 0x40u
#define SDHC_IRQSTAT_CINS_SHIFT 6
#define SDHC_IRQSTAT_CRM_MASK 0x80u
#define SDHC_IRQSTAT_CRM_SHIFT 7
#define SDHC_IRQSTAT_CINT_MASK 0x100u
#define SDHC_IRQSTAT_CINT_SHIFT 8
#define SDHC_IRQSTAT_CTOE_MASK 0x10000u
#define SDHC_IRQSTAT_CTOE_SHIFT 16
#define SDHC_IRQSTAT_CCE_MASK 0x20000u
#define SDHC_IRQSTAT_CCE_SHIFT 17
#define SDHC_IRQSTAT_CEBE_MASK 0x40000u
#define SDHC_IRQSTAT_CEBE_SHIFT 18
#define SDHC_IRQSTAT_CIE_MASK 0x80000u
#define SDHC_IRQSTAT_CIE_SHIFT 19
#define SDHC_IRQSTAT_DTOE_MASK 0x100000u
#define SDHC_IRQSTAT_DTOE_SHIFT 20
#define SDHC_IRQSTAT_DCE_MASK 0x200000u
#define SDHC_IRQSTAT_DCE_SHIFT 21
#define SDHC_IRQSTAT_DEBE_MASK 0x400000u
#define SDHC_IRQSTAT_DEBE_SHIFT 22
#define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
#define SDHC_IRQSTAT_AC12E_SHIFT 24
#define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
#define SDHC_IRQSTAT_DMAE_SHIFT 28
/* IRQSTATEN Bit Fields */
#define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
#define SDHC_IRQSTATEN_CCSEN_SHIFT 0
#define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
#define SDHC_IRQSTATEN_TCSEN_SHIFT 1
#define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
#define SDHC_IRQSTATEN_BGESEN_SHIFT 2
#define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
#define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
#define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
#define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
#define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
#define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
#define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
#define SDHC_IRQSTATEN_CINSEN_SHIFT 6
#define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
#define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
#define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
#define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
#define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
#define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
#define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
#define SDHC_IRQSTATEN_CCESEN_SHIFT 17
#define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
#define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
#define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
#define SDHC_IRQSTATEN_CIESEN_SHIFT 19
#define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
#define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
#define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
#define SDHC_IRQSTATEN_DCESEN_SHIFT 21
#define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
#define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
#define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
#define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
#define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
#define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
/* IRQSIGEN Bit Fields */
#define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
#define SDHC_IRQSIGEN_CCIEN_SHIFT 0
#define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
#define SDHC_IRQSIGEN_TCIEN_SHIFT 1
#define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
#define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
#define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
#define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
#define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
#define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
#define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
#define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
#define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
#define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
#define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
#define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
#define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
#define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
#define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
#define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
#define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
#define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
#define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
#define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
#define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
#define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
#define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
#define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
#define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
#define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
#define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
#define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
#define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
#define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
#define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
#define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
/* AC12ERR Bit Fields */
#define SDHC_AC12ERR_AC12NE_MASK 0x1u
#define SDHC_AC12ERR_AC12NE_SHIFT 0
#define SDHC_AC12ERR_AC12TOE_MASK 0x2u
#define SDHC_AC12ERR_AC12TOE_SHIFT 1
#define SDHC_AC12ERR_AC12EBE_MASK 0x4u
#define SDHC_AC12ERR_AC12EBE_SHIFT 2
#define SDHC_AC12ERR_AC12CE_MASK 0x8u
#define SDHC_AC12ERR_AC12CE_SHIFT 3
#define SDHC_AC12ERR_AC12IE_MASK 0x10u
#define SDHC_AC12ERR_AC12IE_SHIFT 4
#define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
#define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
/* HTCAPBLT Bit Fields */
#define SDHC_HTCAPBLT_MBL_MASK 0x70000u
#define SDHC_HTCAPBLT_MBL_SHIFT 16
#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
#define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
#define SDHC_HTCAPBLT_ADMAS_SHIFT 20
#define SDHC_HTCAPBLT_HSS_MASK 0x200000u
#define SDHC_HTCAPBLT_HSS_SHIFT 21
#define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
#define SDHC_HTCAPBLT_DMAS_SHIFT 22
#define SDHC_HTCAPBLT_SRS_MASK 0x800000u
#define SDHC_HTCAPBLT_SRS_SHIFT 23
#define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
#define SDHC_HTCAPBLT_VS33_SHIFT 24
#define SDHC_HTCAPBLT_VS30_MASK 0x2000000u
#define SDHC_HTCAPBLT_VS30_SHIFT 25
#define SDHC_HTCAPBLT_VS18_MASK 0x4000000u
#define SDHC_HTCAPBLT_VS18_SHIFT 26
/* WML Bit Fields */
#define SDHC_WML_RDWML_MASK 0xFFu
#define SDHC_WML_RDWML_SHIFT 0
#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
#define SDHC_WML_WRWML_MASK 0xFF0000u
#define SDHC_WML_WRWML_SHIFT 16
#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
#define SDHC_WML_WRBRSTLEN_MASK 0x1F000000u
#define SDHC_WML_WRBRSTLEN_SHIFT 24
#define SDHC_WML_WRBRSTLEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRBRSTLEN_SHIFT))&SDHC_WML_WRBRSTLEN_MASK)
/* FEVT Bit Fields */
#define SDHC_FEVT_AC12NE_MASK 0x1u
#define SDHC_FEVT_AC12NE_SHIFT 0
#define SDHC_FEVT_AC12TOE_MASK 0x2u
#define SDHC_FEVT_AC12TOE_SHIFT 1
#define SDHC_FEVT_AC12CE_MASK 0x4u
#define SDHC_FEVT_AC12CE_SHIFT 2
#define SDHC_FEVT_AC12EBE_MASK 0x8u
#define SDHC_FEVT_AC12EBE_SHIFT 3
#define SDHC_FEVT_AC12IE_MASK 0x10u
#define SDHC_FEVT_AC12IE_SHIFT 4
#define SDHC_FEVT_CNIBAC12E_MASK 0x80u
#define SDHC_FEVT_CNIBAC12E_SHIFT 7
#define SDHC_FEVT_CTOE_MASK 0x10000u
#define SDHC_FEVT_CTOE_SHIFT 16
#define SDHC_FEVT_CCE_MASK 0x20000u
#define SDHC_FEVT_CCE_SHIFT 17
#define SDHC_FEVT_CEBE_MASK 0x40000u
#define SDHC_FEVT_CEBE_SHIFT 18
#define SDHC_FEVT_CIE_MASK 0x80000u
#define SDHC_FEVT_CIE_SHIFT 19
#define SDHC_FEVT_DTOE_MASK 0x100000u
#define SDHC_FEVT_DTOE_SHIFT 20
#define SDHC_FEVT_DCE_MASK 0x200000u
#define SDHC_FEVT_DCE_SHIFT 21
#define SDHC_FEVT_DEBE_MASK 0x400000u
#define SDHC_FEVT_DEBE_SHIFT 22
#define SDHC_FEVT_AC12E_MASK 0x1000000u
#define SDHC_FEVT_AC12E_SHIFT 24
#define SDHC_FEVT_DMAE_MASK 0x10000000u
#define SDHC_FEVT_DMAE_SHIFT 28
#define SDHC_FEVT_CINT_MASK 0x80000000u
#define SDHC_FEVT_CINT_SHIFT 31
/* ADMAES Bit Fields */
#define SDHC_ADMAES_ADMAES_MASK 0x3u
#define SDHC_ADMAES_ADMAES_SHIFT 0
#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
#define SDHC_ADMAES_ADMALME_MASK 0x4u
#define SDHC_ADMAES_ADMALME_SHIFT 2
#define SDHC_ADMAES_ADMADCE_MASK 0x8u
#define SDHC_ADMAES_ADMADCE_SHIFT 3
/* ADSADDR Bit Fields */
#define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
#define SDHC_ADSADDR_ADSADDR_SHIFT 2
#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
/* VENDOR Bit Fields */
#define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
#define SDHC_VENDOR_EXTDMAEN_SHIFT 0
#define SDHC_VENDOR_EXBLKNU_MASK 0x2u
#define SDHC_VENDOR_EXBLKNU_SHIFT 1
#define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
#define SDHC_VENDOR_INTSTVAL_SHIFT 16
#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
/* MMCBOOT Bit Fields */
#define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
#define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
#define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
#define SDHC_MMCBOOT_BOOTACK_SHIFT 4
#define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
#define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
#define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
#define SDHC_MMCBOOT_BOOTEN_SHIFT 6
#define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
#define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
/* HOSTVER Bit Fields */
#define SDHC_HOSTVER_SVN_MASK 0xFFu
#define SDHC_HOSTVER_SVN_SHIFT 0
#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
#define SDHC_HOSTVER_VVN_MASK 0xFF00u
#define SDHC_HOSTVER_VVN_SHIFT 8
#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
/**
* @}
*/ /* end of group SDHC_Register_Masks */
/* SDHC - Peripheral instance base addresses */
/** Peripheral SDHC base pointer */
#define SDHC_BASE_PTR ((SDHC_MemMapPtr)0x400B1000u)
/* ----------------------------------------------------------------------------
-- SDHC - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
* @{
*/
/* SDHC - Register instance definitions */
/* SDHC */
#define SDHC_DSADDR SDHC_DSADDR_REG(SDHC_BASE_PTR)
#define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC_BASE_PTR)
#define SDHC_CMDARG SDHC_CMDARG_REG(SDHC_BASE_PTR)
#define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC_BASE_PTR)
#define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC_BASE_PTR,0)
#define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC_BASE_PTR,1)
#define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC_BASE_PTR,2)
#define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC_BASE_PTR,3)
#define SDHC_DATPORT SDHC_DATPORT_REG(SDHC_BASE_PTR)
#define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC_BASE_PTR)
#define SDHC_PROCTL SDHC_PROCTL_REG(SDHC_BASE_PTR)
#define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC_BASE_PTR)
#define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC_BASE_PTR)
#define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC_BASE_PTR)
#define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC_BASE_PTR)
#define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC_BASE_PTR)
#define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC_BASE_PTR)
#define SDHC_WML SDHC_WML_REG(SDHC_BASE_PTR)
#define SDHC_FEVT SDHC_FEVT_REG(SDHC_BASE_PTR)
#define SDHC_ADMAES SDHC_ADMAES_REG(SDHC_BASE_PTR)
#define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC_BASE_PTR)
#define SDHC_VENDOR SDHC_VENDOR_REG(SDHC_BASE_PTR)
#define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC_BASE_PTR)
#define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC_BASE_PTR)
/* SDHC - Register array accessors */
#define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC_BASE_PTR,index)
/**
* @}
*/ /* end of group SDHC_Register_Accessor_Macros */
/**
* @}
*/ /* end of group SDHC_Peripheral */
/* ----------------------------------------------------------------------------
-- SIM
---------------------------------------------------------------------------- */
/**
* @addtogroup SIM_Peripheral SIM
* @{
*/
/** SIM - Peripheral register structure */
typedef struct SIM_MemMap {
uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
uint8_t RESERVED_0[4096];
uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
uint8_t RESERVED_1[4];
uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
uint32_t SOPT6; /**< System Options Register 6, offset: 0x1014 */
uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
uint8_t RESERVED_2[8];
uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
} volatile *SIM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- SIM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
* @{
*/
/* SIM - Register accessors */
#define SIM_SOPT1_REG(base) ((base)->SOPT1)
#define SIM_SOPT2_REG(base) ((base)->SOPT2)
#define SIM_SOPT4_REG(base) ((base)->SOPT4)
#define SIM_SOPT5_REG(base) ((base)->SOPT5)
#define SIM_SOPT6_REG(base) ((base)->SOPT6)
#define SIM_SOPT7_REG(base) ((base)->SOPT7)
#define SIM_SDID_REG(base) ((base)->SDID)
#define SIM_SCGC1_REG(base) ((base)->SCGC1)
#define SIM_SCGC2_REG(base) ((base)->SCGC2)
#define SIM_SCGC3_REG(base) ((base)->SCGC3)
#define SIM_SCGC4_REG(base) ((base)->SCGC4)
#define SIM_SCGC5_REG(base) ((base)->SCGC5)
#define SIM_SCGC6_REG(base) ((base)->SCGC6)
#define SIM_SCGC7_REG(base) ((base)->SCGC7)
#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
#define SIM_FCFG1_REG(base) ((base)->FCFG1)
#define SIM_FCFG2_REG(base) ((base)->FCFG2)
#define SIM_UIDH_REG(base) ((base)->UIDH)
#define SIM_UIDMH_REG(base) ((base)->UIDMH)
#define SIM_UIDML_REG(base) ((base)->UIDML)
#define SIM_UIDL_REG(base) ((base)->UIDL)
/**
* @}
*/ /* end of group SIM_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- SIM Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup SIM_Register_Masks SIM Register Masks
* @{
*/
/* SOPT1 Bit Fields */
#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
#define SIM_SOPT1_RAMSIZE_SHIFT 12
#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
#define SIM_SOPT1_OSC32KSEL_MASK 0x80000u
#define SIM_SOPT1_OSC32KSEL_SHIFT 19
#define SIM_SOPT1_MS_MASK 0x800000u
#define SIM_SOPT1_MS_SHIFT 23
#define SIM_SOPT1_USBSTBY_MASK 0x40000000u
#define SIM_SOPT1_USBSTBY_SHIFT 30
#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
#define SIM_SOPT1_USBREGEN_SHIFT 31
/* SOPT2 Bit Fields */
#define SIM_SOPT2_MCGCLKSEL_MASK 0x1u
#define SIM_SOPT2_MCGCLKSEL_SHIFT 0
#define SIM_SOPT2_FBSL_MASK 0x300u
#define SIM_SOPT2_FBSL_SHIFT 8
#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
#define SIM_SOPT2_CMTUARTPAD_MASK 0x800u
#define SIM_SOPT2_CMTUARTPAD_SHIFT 11
#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
#define SIM_SOPT2_USBSRC_MASK 0x40000u
#define SIM_SOPT2_USBSRC_SHIFT 18
#define SIM_SOPT2_I2SSRC_MASK 0x3000000u
#define SIM_SOPT2_I2SSRC_SHIFT 24
#define SIM_SOPT2_I2SSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_I2SSRC_SHIFT))&SIM_SOPT2_I2SSRC_MASK)
#define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
#define SIM_SOPT2_SDHCSRC_SHIFT 28
#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
/* SOPT4 Bit Fields */
#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
#define SIM_SOPT4_FTM0FLT0_SHIFT 0
#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
#define SIM_SOPT4_FTM0FLT1_SHIFT 1
#define SIM_SOPT4_FTM0FLT2_MASK 0x4u
#define SIM_SOPT4_FTM0FLT2_SHIFT 2
#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
#define SIM_SOPT4_FTM1FLT0_SHIFT 4
#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
#define SIM_SOPT4_FTM2FLT0_SHIFT 8
#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
/* SOPT5 Bit Fields */
#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
#define SIM_SOPT5_UART0TXSRC_SHIFT 0
#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
#define SIM_SOPT5_UART0RXSRC_SHIFT 2
#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
#define SIM_SOPT5_UARTTXSRC_MASK 0x30u
#define SIM_SOPT5_UARTTXSRC_SHIFT 4
#define SIM_SOPT5_UARTTXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UARTTXSRC_SHIFT))&SIM_SOPT5_UARTTXSRC_MASK)
#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
#define SIM_SOPT5_UART1RXSRC_SHIFT 6
#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
/* SOPT6 Bit Fields */
#define SIM_SOPT6_RSTFLTSEL_MASK 0x1F000000u
#define SIM_SOPT6_RSTFLTSEL_SHIFT 24
#define SIM_SOPT6_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT6_RSTFLTSEL_SHIFT))&SIM_SOPT6_RSTFLTSEL_MASK)
#define SIM_SOPT6_RSTFLTEN_MASK 0xE0000000u
#define SIM_SOPT6_RSTFLTEN_SHIFT 29
#define SIM_SOPT6_RSTFLTEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT6_RSTFLTEN_SHIFT))&SIM_SOPT6_RSTFLTEN_MASK)
/* SOPT7 Bit Fields */
#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
/* SDID Bit Fields */
#define SIM_SDID_PINID_MASK 0xFu
#define SIM_SDID_PINID_SHIFT 0
#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
#define SIM_SDID_FAMID_MASK 0x70u
#define SIM_SDID_FAMID_SHIFT 4
#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
#define SIM_SDID_REVID_MASK 0xF000u
#define SIM_SDID_REVID_SHIFT 12
#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
/* SCGC1 Bit Fields */
#define SIM_SCGC1_UART4_MASK 0x400u
#define SIM_SCGC1_UART4_SHIFT 10
#define SIM_SCGC1_UART5_MASK 0x800u
#define SIM_SCGC1_UART5_SHIFT 11
/* SCGC2 Bit Fields */
#define SIM_SCGC2_DAC0_MASK 0x1000u
#define SIM_SCGC2_DAC0_SHIFT 12
#define SIM_SCGC2_DAC1_MASK 0x2000u
#define SIM_SCGC2_DAC1_SHIFT 13
/* SCGC3 Bit Fields */
#define SIM_SCGC3_FLEXCAN1_MASK 0x10u
#define SIM_SCGC3_FLEXCAN1_SHIFT 4
#define SIM_SCGC3_SPI2_MASK 0x1000u
#define SIM_SCGC3_SPI2_SHIFT 12
#define SIM_SCGC3_SDHC_MASK 0x20000u
#define SIM_SCGC3_SDHC_SHIFT 17
#define SIM_SCGC3_FTM2_MASK 0x1000000u
#define SIM_SCGC3_FTM2_SHIFT 24
#define SIM_SCGC3_ADC1_MASK 0x8000000u
#define SIM_SCGC3_ADC1_SHIFT 27
/* SCGC4 Bit Fields */
#define SIM_SCGC4_EWM_MASK 0x2u
#define SIM_SCGC4_EWM_SHIFT 1
#define SIM_SCGC4_CMT_MASK 0x4u
#define SIM_SCGC4_CMT_SHIFT 2
#define SIM_SCGC4_I2C0_MASK 0x40u
#define SIM_SCGC4_I2C0_SHIFT 6
#define SIM_SCGC4_I2C1_MASK 0x80u
#define SIM_SCGC4_I2C1_SHIFT 7
#define SIM_SCGC4_UART0_MASK 0x400u
#define SIM_SCGC4_UART0_SHIFT 10
#define SIM_SCGC4_UART1_MASK 0x800u
#define SIM_SCGC4_UART1_SHIFT 11
#define SIM_SCGC4_UART2_MASK 0x1000u
#define SIM_SCGC4_UART2_SHIFT 12
#define SIM_SCGC4_UART3_MASK 0x2000u
#define SIM_SCGC4_UART3_SHIFT 13
#define SIM_SCGC4_USBOTG_MASK 0x40000u
#define SIM_SCGC4_USBOTG_SHIFT 18
#define SIM_SCGC4_CMP_MASK 0x80000u
#define SIM_SCGC4_CMP_SHIFT 19
#define SIM_SCGC4_VREF_MASK 0x100000u
#define SIM_SCGC4_VREF_SHIFT 20
#define SIM_SCGC4_LLWU_MASK 0x10000000u
#define SIM_SCGC4_LLWU_SHIFT 28
/* SCGC5 Bit Fields */
#define SIM_SCGC5_LPTIMER_MASK 0x1u
#define SIM_SCGC5_LPTIMER_SHIFT 0
#define SIM_SCGC5_REGFILE_MASK 0x2u
#define SIM_SCGC5_REGFILE_SHIFT 1
#define SIM_SCGC5_TSI_MASK 0x20u
#define SIM_SCGC5_TSI_SHIFT 5
#define SIM_SCGC5_PORTA_MASK 0x200u
#define SIM_SCGC5_PORTA_SHIFT 9
#define SIM_SCGC5_PORTB_MASK 0x400u
#define SIM_SCGC5_PORTB_SHIFT 10
#define SIM_SCGC5_PORTC_MASK 0x800u
#define SIM_SCGC5_PORTC_SHIFT 11
#define SIM_SCGC5_PORTD_MASK 0x1000u
#define SIM_SCGC5_PORTD_SHIFT 12
#define SIM_SCGC5_PORTE_MASK 0x2000u
#define SIM_SCGC5_PORTE_SHIFT 13
/* SCGC6 Bit Fields */
#define SIM_SCGC6_FTFL_MASK 0x1u
#define SIM_SCGC6_FTFL_SHIFT 0
#define SIM_SCGC6_DMAMUX_MASK 0x2u
#define SIM_SCGC6_DMAMUX_SHIFT 1
#define SIM_SCGC6_FLEXCAN0_MASK 0x10u
#define SIM_SCGC6_FLEXCAN0_SHIFT 4
#define SIM_SCGC6_DSPI0_MASK 0x1000u
#define SIM_SCGC6_DSPI0_SHIFT 12
#define SIM_SCGC6_SPI1_MASK 0x2000u
#define SIM_SCGC6_SPI1_SHIFT 13
#define SIM_SCGC6_I2S_MASK 0x8000u
#define SIM_SCGC6_I2S_SHIFT 15
#define SIM_SCGC6_CRC_MASK 0x40000u
#define SIM_SCGC6_CRC_SHIFT 18
#define SIM_SCGC6_USBDCD_MASK 0x200000u
#define SIM_SCGC6_USBDCD_SHIFT 21
#define SIM_SCGC6_PDB_MASK 0x400000u
#define SIM_SCGC6_PDB_SHIFT 22
#define SIM_SCGC6_PIT_MASK 0x800000u
#define SIM_SCGC6_PIT_SHIFT 23
#define SIM_SCGC6_FTM0_MASK 0x1000000u
#define SIM_SCGC6_FTM0_SHIFT 24
#define SIM_SCGC6_FTM1_MASK 0x2000000u
#define SIM_SCGC6_FTM1_SHIFT 25
#define SIM_SCGC6_ADC0_MASK 0x8000000u
#define SIM_SCGC6_ADC0_SHIFT 27
#define SIM_SCGC6_RTC_MASK 0x20000000u
#define SIM_SCGC6_RTC_SHIFT 29
/* SCGC7 Bit Fields */
#define SIM_SCGC7_FLEXBUS_MASK 0x1u
#define SIM_SCGC7_FLEXBUS_SHIFT 0
#define SIM_SCGC7_DMA_MASK 0x2u
#define SIM_SCGC7_DMA_SHIFT 1
#define SIM_SCGC7_MPU_MASK 0x4u
#define SIM_SCGC7_MPU_SHIFT 2
/* CLKDIV1 Bit Fields */
#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
#define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
#define SIM_CLKDIV1_OUTDIV3_SHIFT 20
#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
/* CLKDIV2 Bit Fields */
#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
#define SIM_CLKDIV2_USBFRAC_SHIFT 0
#define SIM_CLKDIV2_USBDIV_MASK 0xEu
#define SIM_CLKDIV2_USBDIV_SHIFT 1
#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
#define SIM_CLKDIV2_I2SFRAC_MASK 0xFF00u
#define SIM_CLKDIV2_I2SFRAC_SHIFT 8
#define SIM_CLKDIV2_I2SFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_I2SFRAC_SHIFT))&SIM_CLKDIV2_I2SFRAC_MASK)
#define SIM_CLKDIV2_I2SDIV_MASK 0xFFF00000u
#define SIM_CLKDIV2_I2SDIV_SHIFT 20
#define SIM_CLKDIV2_I2SDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_I2SDIV_SHIFT))&SIM_CLKDIV2_I2SDIV_MASK)
/* FCFG1 Bit Fields */
#define SIM_FCFG1_DEPART_MASK 0xF00u
#define SIM_FCFG1_DEPART_SHIFT 8
#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
#define SIM_FCFG1_EESIZE_MASK 0xF0000u
#define SIM_FCFG1_EESIZE_SHIFT 16
#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
#define SIM_FCFG1_PFSIZE_SHIFT 24
#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
#define SIM_FCFG1_NVMSIZE_SHIFT 28
#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
/* FCFG2 Bit Fields */
#define SIM_FCFG2_MAXADDR1_MASK 0x3F0000u
#define SIM_FCFG2_MAXADDR1_SHIFT 16
#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
#define SIM_FCFG2_PFLSH_MASK 0x800000u
#define SIM_FCFG2_PFLSH_SHIFT 23
#define SIM_FCFG2_MAXADDR0_MASK 0x3F000000u
#define SIM_FCFG2_MAXADDR0_SHIFT 24
#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
#define SIM_FCFG2_SWAPPFLSH_MASK 0x80000000u
#define SIM_FCFG2_SWAPPFLSH_SHIFT 31
/* UIDH Bit Fields */
#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
#define SIM_UIDH_UID_SHIFT 0
#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
/* UIDMH Bit Fields */
#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
#define SIM_UIDMH_UID_SHIFT 0
#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
/* UIDML Bit Fields */
#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
#define SIM_UIDML_UID_SHIFT 0
#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
/* UIDL Bit Fields */
#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
#define SIM_UIDL_UID_SHIFT 0
#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
/**
* @}
*/ /* end of group SIM_Register_Masks */
/* SIM - Peripheral instance base addresses */
/** Peripheral SIM base pointer */
#define SIM_BASE_PTR ((SIM_MemMapPtr)0x40047000u)
/* ----------------------------------------------------------------------------
-- SIM - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
* @{
*/
/* SIM - Register instance definitions */
/* SIM */
#define SIM_SOPT1 SIM_SOPT1_REG(SIM_BASE_PTR)
#define SIM_SOPT2 SIM_SOPT2_REG(SIM_BASE_PTR)
#define SIM_SOPT4 SIM_SOPT4_REG(SIM_BASE_PTR)
#define SIM_SOPT5 SIM_SOPT5_REG(SIM_BASE_PTR)
#define SIM_SOPT6 SIM_SOPT6_REG(SIM_BASE_PTR)
#define SIM_SOPT7 SIM_SOPT7_REG(SIM_BASE_PTR)
#define SIM_SDID SIM_SDID_REG(SIM_BASE_PTR)
#define SIM_SCGC1 SIM_SCGC1_REG(SIM_BASE_PTR)
#define SIM_SCGC2 SIM_SCGC2_REG(SIM_BASE_PTR)
#define SIM_SCGC3 SIM_SCGC3_REG(SIM_BASE_PTR)
#define SIM_SCGC4 SIM_SCGC4_REG(SIM_BASE_PTR)
#define SIM_SCGC5 SIM_SCGC5_REG(SIM_BASE_PTR)
#define SIM_SCGC6 SIM_SCGC6_REG(SIM_BASE_PTR)
#define SIM_SCGC7 SIM_SCGC7_REG(SIM_BASE_PTR)
#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM_BASE_PTR)
#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM_BASE_PTR)
#define SIM_FCFG1 SIM_FCFG1_REG(SIM_BASE_PTR)
#define SIM_FCFG2 SIM_FCFG2_REG(SIM_BASE_PTR)
#define SIM_UIDH SIM_UIDH_REG(SIM_BASE_PTR)
#define SIM_UIDMH SIM_UIDMH_REG(SIM_BASE_PTR)
#define SIM_UIDML SIM_UIDML_REG(SIM_BASE_PTR)
#define SIM_UIDL SIM_UIDL_REG(SIM_BASE_PTR)
/**
* @}
*/ /* end of group SIM_Register_Accessor_Macros */
/**
* @}
*/ /* end of group SIM_Peripheral */
/* ----------------------------------------------------------------------------
-- SPI
---------------------------------------------------------------------------- */
/**
* @addtogroup SPI_Peripheral SPI
* @{
*/
/** SPI - Peripheral register structure */
typedef struct SPI_MemMap {
uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
uint8_t RESERVED_0[4];
uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
union { /* offset: 0xC */
uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
};
uint8_t RESERVED_1[24];
uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
union { /* offset: 0x34 */
uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
};
uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
uint8_t RESERVED_2[48];
uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
} volatile *SPI_MemMapPtr;
/* ----------------------------------------------------------------------------
-- SPI - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
* @{
*/
/* SPI - Register accessors */
#define SPI_MCR_REG(base) ((base)->MCR)
#define SPI_TCR_REG(base) ((base)->TCR)
#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
#define SPI_SR_REG(base) ((base)->SR)
#define SPI_RSER_REG(base) ((base)->RSER)
#define SPI_PUSHR_REG(base) ((base)->PUSHR)
#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
#define SPI_POPR_REG(base) ((base)->POPR)
#define SPI_TXFR0_REG(base) ((base)->TXFR0)
#define SPI_TXFR1_REG(base) ((base)->TXFR1)
#define SPI_TXFR2_REG(base) ((base)->TXFR2)
#define SPI_TXFR3_REG(base) ((base)->TXFR3)
#define SPI_RXFR0_REG(base) ((base)->RXFR0)
#define SPI_RXFR1_REG(base) ((base)->RXFR1)
#define SPI_RXFR2_REG(base) ((base)->RXFR2)
#define SPI_RXFR3_REG(base) ((base)->RXFR3)
/**
* @}
*/ /* end of group SPI_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- SPI Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup SPI_Register_Masks SPI Register Masks
* @{
*/
/* MCR Bit Fields */
#define SPI_MCR_HALT_MASK 0x1u
#define SPI_MCR_HALT_SHIFT 0
#define SPI_MCR_SMPL_PT_MASK 0x300u
#define SPI_MCR_SMPL_PT_SHIFT 8
#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
#define SPI_MCR_CLR_RXF_MASK 0x400u
#define SPI_MCR_CLR_RXF_SHIFT 10
#define SPI_MCR_CLR_TXF_MASK 0x800u
#define SPI_MCR_CLR_TXF_SHIFT 11
#define SPI_MCR_DIS_RXF_MASK 0x1000u
#define SPI_MCR_DIS_RXF_SHIFT 12
#define SPI_MCR_DIS_TXF_MASK 0x2000u
#define SPI_MCR_DIS_TXF_SHIFT 13
#define SPI_MCR_MDIS_MASK 0x4000u
#define SPI_MCR_MDIS_SHIFT 14
#define SPI_MCR_DOZE_MASK 0x8000u
#define SPI_MCR_DOZE_SHIFT 15
#define SPI_MCR_PCSIS_MASK 0x3F0000u
#define SPI_MCR_PCSIS_SHIFT 16
#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
#define SPI_MCR_ROOE_MASK 0x1000000u
#define SPI_MCR_ROOE_SHIFT 24
#define SPI_MCR_PCSSE_MASK 0x2000000u
#define SPI_MCR_PCSSE_SHIFT 25
#define SPI_MCR_MTFE_MASK 0x4000000u
#define SPI_MCR_MTFE_SHIFT 26
#define SPI_MCR_FRZ_MASK 0x8000000u
#define SPI_MCR_FRZ_SHIFT 27
#define SPI_MCR_DCONF_MASK 0x30000000u
#define SPI_MCR_DCONF_SHIFT 28
#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
#define SPI_MCR_CONT_SCKE_SHIFT 30
#define SPI_MCR_MSTR_MASK 0x80000000u
#define SPI_MCR_MSTR_SHIFT 31
/* TCR Bit Fields */
#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
#define SPI_TCR_SPI_TCNT_SHIFT 16
#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
/* CTAR Bit Fields */
#define SPI_CTAR_BR_MASK 0xFu
#define SPI_CTAR_BR_SHIFT 0
#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
#define SPI_CTAR_DT_MASK 0xF0u
#define SPI_CTAR_DT_SHIFT 4
#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
#define SPI_CTAR_ASC_MASK 0xF00u
#define SPI_CTAR_ASC_SHIFT 8
#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
#define SPI_CTAR_CSSCK_MASK 0xF000u
#define SPI_CTAR_CSSCK_SHIFT 12
#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
#define SPI_CTAR_PBR_MASK 0x30000u
#define SPI_CTAR_PBR_SHIFT 16
#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
#define SPI_CTAR_PDT_MASK 0xC0000u
#define SPI_CTAR_PDT_SHIFT 18
#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
#define SPI_CTAR_PASC_MASK 0x300000u
#define SPI_CTAR_PASC_SHIFT 20
#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
#define SPI_CTAR_PCSSCK_MASK 0xC00000u
#define SPI_CTAR_PCSSCK_SHIFT 22
#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
#define SPI_CTAR_LSBFE_MASK 0x1000000u
#define SPI_CTAR_LSBFE_SHIFT 24
#define SPI_CTAR_CPHA_MASK 0x2000000u
#define SPI_CTAR_CPHA_SHIFT 25
#define SPI_CTAR_CPOL_MASK 0x4000000u
#define SPI_CTAR_CPOL_SHIFT 26
#define SPI_CTAR_FMSZ_MASK 0x78000000u
#define SPI_CTAR_FMSZ_SHIFT 27
#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
#define SPI_CTAR_DBR_MASK 0x80000000u
#define SPI_CTAR_DBR_SHIFT 31
/* CTAR_SLAVE Bit Fields */
#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
/* SR Bit Fields */
#define SPI_SR_POPNXTPTR_MASK 0xFu
#define SPI_SR_POPNXTPTR_SHIFT 0
#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
#define SPI_SR_RXCTR_MASK 0xF0u
#define SPI_SR_RXCTR_SHIFT 4
#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
#define SPI_SR_TXNXTPTR_MASK 0xF00u
#define SPI_SR_TXNXTPTR_SHIFT 8
#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
#define SPI_SR_TXCTR_MASK 0xF000u
#define SPI_SR_TXCTR_SHIFT 12
#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
#define SPI_SR_RFDF_MASK 0x20000u
#define SPI_SR_RFDF_SHIFT 17
#define SPI_SR_RFOF_MASK 0x80000u
#define SPI_SR_RFOF_SHIFT 19
#define SPI_SR_TFFF_MASK 0x2000000u
#define SPI_SR_TFFF_SHIFT 25
#define SPI_SR_TFUF_MASK 0x8000000u
#define SPI_SR_TFUF_SHIFT 27
#define SPI_SR_EOQF_MASK 0x10000000u
#define SPI_SR_EOQF_SHIFT 28
#define SPI_SR_TXRXS_MASK 0x40000000u
#define SPI_SR_TXRXS_SHIFT 30
#define SPI_SR_TCF_MASK 0x80000000u
#define SPI_SR_TCF_SHIFT 31
/* RSER Bit Fields */
#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
#define SPI_RSER_RFDF_DIRS_SHIFT 16
#define SPI_RSER_RFDF_RE_MASK 0x20000u
#define SPI_RSER_RFDF_RE_SHIFT 17
#define SPI_RSER_RFOF_RE_MASK 0x80000u
#define SPI_RSER_RFOF_RE_SHIFT 19
#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
#define SPI_RSER_TFFF_DIRS_SHIFT 24
#define SPI_RSER_TFFF_RE_MASK 0x2000000u
#define SPI_RSER_TFFF_RE_SHIFT 25
#define SPI_RSER_TFUF_RE_MASK 0x8000000u
#define SPI_RSER_TFUF_RE_SHIFT 27
#define SPI_RSER_EOQF_RE_MASK 0x10000000u
#define SPI_RSER_EOQF_RE_SHIFT 28
#define SPI_RSER_TCF_RE_MASK 0x80000000u
#define SPI_RSER_TCF_RE_SHIFT 31
/* PUSHR Bit Fields */
#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
#define SPI_PUSHR_TXDATA_SHIFT 0
#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
#define SPI_PUSHR_PCS_MASK 0x3F0000u
#define SPI_PUSHR_PCS_SHIFT 16
#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
#define SPI_PUSHR_CTCNT_MASK 0x4000000u
#define SPI_PUSHR_CTCNT_SHIFT 26
#define SPI_PUSHR_EOQ_MASK 0x8000000u
#define SPI_PUSHR_EOQ_SHIFT 27
#define SPI_PUSHR_CTAS_MASK 0x70000000u
#define SPI_PUSHR_CTAS_SHIFT 28
#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
#define SPI_PUSHR_CONT_MASK 0x80000000u
#define SPI_PUSHR_CONT_SHIFT 31
/* PUSHR_SLAVE Bit Fields */
#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
/* POPR Bit Fields */
#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
#define SPI_POPR_RXDATA_SHIFT 0
#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
/* TXFR0 Bit Fields */
#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
#define SPI_TXFR0_TXDATA_SHIFT 0
#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
/* TXFR1 Bit Fields */
#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
#define SPI_TXFR1_TXDATA_SHIFT 0
#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
/* TXFR2 Bit Fields */
#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
#define SPI_TXFR2_TXDATA_SHIFT 0
#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
/* TXFR3 Bit Fields */
#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
#define SPI_TXFR3_TXDATA_SHIFT 0
#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
/* RXFR0 Bit Fields */
#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR0_RXDATA_SHIFT 0
#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
/* RXFR1 Bit Fields */
#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR1_RXDATA_SHIFT 0
#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
/* RXFR2 Bit Fields */
#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR2_RXDATA_SHIFT 0
#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
/* RXFR3 Bit Fields */
#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
#define SPI_RXFR3_RXDATA_SHIFT 0
#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
/**
* @}
*/ /* end of group SPI_Register_Masks */
/* SPI - Peripheral instance base addresses */
/** Peripheral SPI0 base pointer */
#define SPI0_BASE_PTR ((SPI_MemMapPtr)0x4002C000u)
/** Peripheral SPI1 base pointer */
#define SPI1_BASE_PTR ((SPI_MemMapPtr)0x4002D000u)
/** Peripheral SPI2 base pointer */
#define SPI2_BASE_PTR ((SPI_MemMapPtr)0x400AC000u)
/* ----------------------------------------------------------------------------
-- SPI - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
* @{
*/
/* SPI - Register instance definitions */
/* SPI0 */
#define SPI0_MCR SPI_MCR_REG(SPI0_BASE_PTR)
#define SPI0_TCR SPI_TCR_REG(SPI0_BASE_PTR)
#define SPI0_CTAR0 SPI_CTAR_REG(SPI0_BASE_PTR,0)
#define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0_BASE_PTR,0)
#define SPI0_CTAR1 SPI_CTAR_REG(SPI0_BASE_PTR,1)
#define SPI0_SR SPI_SR_REG(SPI0_BASE_PTR)
#define SPI0_RSER SPI_RSER_REG(SPI0_BASE_PTR)
#define SPI0_PUSHR SPI_PUSHR_REG(SPI0_BASE_PTR)
#define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0_BASE_PTR)
#define SPI0_POPR SPI_POPR_REG(SPI0_BASE_PTR)
#define SPI0_TXFR0 SPI_TXFR0_REG(SPI0_BASE_PTR)
#define SPI0_TXFR1 SPI_TXFR1_REG(SPI0_BASE_PTR)
#define SPI0_TXFR2 SPI_TXFR2_REG(SPI0_BASE_PTR)
#define SPI0_TXFR3 SPI_TXFR3_REG(SPI0_BASE_PTR)
#define SPI0_RXFR0 SPI_RXFR0_REG(SPI0_BASE_PTR)
#define SPI0_RXFR1 SPI_RXFR1_REG(SPI0_BASE_PTR)
#define SPI0_RXFR2 SPI_RXFR2_REG(SPI0_BASE_PTR)
#define SPI0_RXFR3 SPI_RXFR3_REG(SPI0_BASE_PTR)
/* SPI1 */
#define SPI1_MCR SPI_MCR_REG(SPI1_BASE_PTR)
#define SPI1_TCR SPI_TCR_REG(SPI1_BASE_PTR)
#define SPI1_CTAR0 SPI_CTAR_REG(SPI1_BASE_PTR,0)
#define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1_BASE_PTR,0)
#define SPI1_CTAR1 SPI_CTAR_REG(SPI1_BASE_PTR,1)
#define SPI1_SR SPI_SR_REG(SPI1_BASE_PTR)
#define SPI1_RSER SPI_RSER_REG(SPI1_BASE_PTR)
#define SPI1_PUSHR SPI_PUSHR_REG(SPI1_BASE_PTR)
#define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1_BASE_PTR)
#define SPI1_POPR SPI_POPR_REG(SPI1_BASE_PTR)
#define SPI1_TXFR0 SPI_TXFR0_REG(SPI1_BASE_PTR)
#define SPI1_TXFR1 SPI_TXFR1_REG(SPI1_BASE_PTR)
#define SPI1_TXFR2 SPI_TXFR2_REG(SPI1_BASE_PTR)
#define SPI1_TXFR3 SPI_TXFR3_REG(SPI1_BASE_PTR)
#define SPI1_RXFR0 SPI_RXFR0_REG(SPI1_BASE_PTR)
#define SPI1_RXFR1 SPI_RXFR1_REG(SPI1_BASE_PTR)
#define SPI1_RXFR2 SPI_RXFR2_REG(SPI1_BASE_PTR)
#define SPI1_RXFR3 SPI_RXFR3_REG(SPI1_BASE_PTR)
/* SPI2 */
#define SPI2_MCR SPI_MCR_REG(SPI2_BASE_PTR)
#define SPI2_TCR SPI_TCR_REG(SPI2_BASE_PTR)
#define SPI2_CTAR0 SPI_CTAR_REG(SPI2_BASE_PTR,0)
#define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2_BASE_PTR,0)
#define SPI2_CTAR1 SPI_CTAR_REG(SPI2_BASE_PTR,1)
#define SPI2_SR SPI_SR_REG(SPI2_BASE_PTR)
#define SPI2_RSER SPI_RSER_REG(SPI2_BASE_PTR)
#define SPI2_PUSHR SPI_PUSHR_REG(SPI2_BASE_PTR)
#define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2_BASE_PTR)
#define SPI2_POPR SPI_POPR_REG(SPI2_BASE_PTR)
#define SPI2_TXFR0 SPI_TXFR0_REG(SPI2_BASE_PTR)
#define SPI2_TXFR1 SPI_TXFR1_REG(SPI2_BASE_PTR)
#define SPI2_TXFR2 SPI_TXFR2_REG(SPI2_BASE_PTR)
#define SPI2_TXFR3 SPI_TXFR3_REG(SPI2_BASE_PTR)
#define SPI2_RXFR0 SPI_RXFR0_REG(SPI2_BASE_PTR)
#define SPI2_RXFR1 SPI_RXFR1_REG(SPI2_BASE_PTR)
#define SPI2_RXFR2 SPI_RXFR2_REG(SPI2_BASE_PTR)
#define SPI2_RXFR3 SPI_RXFR3_REG(SPI2_BASE_PTR)
/* SPI - Register array accessors */
#define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0_BASE_PTR,index2)
#define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1_BASE_PTR,index2)
#define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2_BASE_PTR,index2)
#define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0_BASE_PTR,index2)
#define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1_BASE_PTR,index2)
#define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2_BASE_PTR,index2)
/**
* @}
*/ /* end of group SPI_Register_Accessor_Macros */
/**
* @}
*/ /* end of group SPI_Peripheral */
/* ----------------------------------------------------------------------------
-- SysTick
---------------------------------------------------------------------------- */
/**
* @addtogroup SysTick_Peripheral SysTick
* @{
*/
/** SysTick - Peripheral register structure */
typedef struct SysTick_MemMap {
uint32_t CSR; /**< SysTick Control and Status Register, offset: 0x0 */
uint32_t RVR; /**< SysTick Reload Value Register, offset: 0x4 */
uint32_t CVR; /**< SysTick Current Value Register, offset: 0x8 */
uint32_t CALIB; /**< SysTick Calibration Value Register, offset: 0xC */
} volatile *SysTick_MemMapPtr;
/* ----------------------------------------------------------------------------
-- SysTick - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup SysTick_Register_Accessor_Macros SysTick - Register accessor macros
* @{
*/
/* SysTick - Register accessors */
#define SysTick_CSR_REG(base) ((base)->CSR)
#define SysTick_RVR_REG(base) ((base)->RVR)
#define SysTick_CVR_REG(base) ((base)->CVR)
#define SysTick_CALIB_REG(base) ((base)->CALIB)
/**
* @}
*/ /* end of group SysTick_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- SysTick Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup SysTick_Register_Masks SysTick Register Masks
* @{
*/
/* CSR Bit Fields */
#define SysTick_CSR_ENABLE_MASK 0x1u
#define SysTick_CSR_ENABLE_SHIFT 0
#define SysTick_CSR_TICKINT_MASK 0x2u
#define SysTick_CSR_TICKINT_SHIFT 1
#define SysTick_CSR_CLKSOURCE_MASK 0x4u
#define SysTick_CSR_CLKSOURCE_SHIFT 2
#define SysTick_CSR_COUNTFLAG_MASK 0x10000u
#define SysTick_CSR_COUNTFLAG_SHIFT 16
/* RVR Bit Fields */
#define SysTick_RVR_RELOAD_MASK 0xFFFFFFu
#define SysTick_RVR_RELOAD_SHIFT 0
#define SysTick_RVR_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<SysTick_RVR_RELOAD_SHIFT))&SysTick_RVR_RELOAD_MASK)
/* CVR Bit Fields */
#define SysTick_CVR_CURRENT_MASK 0xFFFFFFu
#define SysTick_CVR_CURRENT_SHIFT 0
#define SysTick_CVR_CURRENT(x) (((uint32_t)(((uint32_t)(x))<<SysTick_CVR_CURRENT_SHIFT))&SysTick_CVR_CURRENT_MASK)
/* CALIB Bit Fields */
#define SysTick_CALIB_TENMS_MASK 0xFFFFFFu
#define SysTick_CALIB_TENMS_SHIFT 0
#define SysTick_CALIB_TENMS(x) (((uint32_t)(((uint32_t)(x))<<SysTick_CALIB_TENMS_SHIFT))&SysTick_CALIB_TENMS_MASK)
#define SysTick_CALIB_SKEW_MASK 0x40000000u
#define SysTick_CALIB_SKEW_SHIFT 30
#define SysTick_CALIB_NOREF_MASK 0x80000000u
#define SysTick_CALIB_NOREF_SHIFT 31
/**
* @}
*/ /* end of group SysTick_Register_Masks */
/* SysTick - Peripheral instance base addresses */
/** Peripheral SysTick base pointer */
#define SysTick_BASE_PTR ((SysTick_MemMapPtr)0xE000E010u)
/* ----------------------------------------------------------------------------
-- SysTick - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup SysTick_Register_Accessor_Macros SysTick - Register accessor macros
* @{
*/
/* SysTick - Register instance definitions */
/* SysTick */
#define SYST_CSR SysTick_CSR_REG(SysTick_BASE_PTR)
#define SYST_RVR SysTick_RVR_REG(SysTick_BASE_PTR)
#define SYST_CVR SysTick_CVR_REG(SysTick_BASE_PTR)
#define SYST_CALIB SysTick_CALIB_REG(SysTick_BASE_PTR)
/**
* @}
*/ /* end of group SysTick_Register_Accessor_Macros */
/**
* @}
*/ /* end of group SysTick_Peripheral */
/* ----------------------------------------------------------------------------
-- SCB
---------------------------------------------------------------------------- */
/**
* @addtogroup SCB_Peripheral SCB
* @{
*/
/** SCB - Peripheral register structure */
typedef struct SCB_MemMap {
uint8_t RESERVED_0[8];
uint32_t ACTLR; /**< Auxiliary Control Register,, offset: 0x8 */
uint8_t RESERVED_1[3316];
uint32_t CPUID; /**< CPUID Base Register, offset: 0xD00 */
uint32_t ICSR; /**< Interrupt Control and State Register, offset: 0xD04 */
uint32_t VTOR; /**< Vector Table Offset Register, offset: 0xD08 */
uint32_t AIRCR; /**< Application Interrupt and Reset Control Register, offset: 0xD0C */
uint32_t SCR; /**< System Control Register, offset: 0xD10 */
uint32_t CCR; /**< Configuration and Control Register, offset: 0xD14 */
uint32_t SHPR1; /**< System Handler Priority Register 1, offset: 0xD18 */
uint32_t SHPR2; /**< System Handler Priority Register 2, offset: 0xD1C */
uint32_t SHPR3; /**< System Handler Priority Register 3, offset: 0xD20 */
uint32_t SHCSR; /**< System Handler Control and State Register, offset: 0xD24 */
uint32_t CFSR; /**< Configurable Fault Status Registers, offset: 0xD28 */
uint32_t HFSR; /**< HardFault Status register, offset: 0xD2C */
uint32_t DFSR; /**< Debug Fault Status Register, offset: 0xD30 */
uint32_t MMFAR; /**< MemManage Address Register, offset: 0xD34 */
uint32_t BFAR; /**< BusFault Address Register, offset: 0xD38 */
uint32_t AFSR; /**< Auxiliary Fault Status Register, offset: 0xD3C */
} volatile *SCB_MemMapPtr;
/* ----------------------------------------------------------------------------
-- SCB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup SCB_Register_Accessor_Macros SCB - Register accessor macros
* @{
*/
/* SCB - Register accessors */
#define SCB_ACTLR_REG(base) ((base)->ACTLR)
#define SCB_CPUID_REG(base) ((base)->CPUID)
#define SCB_ICSR_REG(base) ((base)->ICSR)
#define SCB_VTOR_REG(base) ((base)->VTOR)
#define SCB_AIRCR_REG(base) ((base)->AIRCR)
#define SCB_SCR_REG(base) ((base)->SCR)
#define SCB_CCR_REG(base) ((base)->CCR)
#define SCB_SHPR1_REG(base) ((base)->SHPR1)
#define SCB_SHPR2_REG(base) ((base)->SHPR2)
#define SCB_SHPR3_REG(base) ((base)->SHPR3)
#define SCB_SHCSR_REG(base) ((base)->SHCSR)
#define SCB_CFSR_REG(base) ((base)->CFSR)
#define SCB_HFSR_REG(base) ((base)->HFSR)
#define SCB_DFSR_REG(base) ((base)->DFSR)
#define SCB_MMFAR_REG(base) ((base)->MMFAR)
#define SCB_BFAR_REG(base) ((base)->BFAR)
#define SCB_AFSR_REG(base) ((base)->AFSR)
/**
* @}
*/ /* end of group SCB_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- SCB Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup SCB_Register_Masks SCB Register Masks
* @{
*/
/* ACTLR Bit Fields */
#define SCB_ACTLR_DISMCYCINT_MASK 0x1u
#define SCB_ACTLR_DISMCYCINT_SHIFT 0
#define SCB_ACTLR_DISDEFWBUF_MASK 0x2u
#define SCB_ACTLR_DISDEFWBUF_SHIFT 1
#define SCB_ACTLR_DISFOLD_MASK 0x4u
#define SCB_ACTLR_DISFOLD_SHIFT 2
/* CPUID Bit Fields */
#define SCB_CPUID_REVISION_MASK 0xFu
#define SCB_CPUID_REVISION_SHIFT 0
#define SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_REVISION_SHIFT))&SCB_CPUID_REVISION_MASK)
#define SCB_CPUID_PARTNO_MASK 0xFFF0u
#define SCB_CPUID_PARTNO_SHIFT 4
#define SCB_CPUID_PARTNO(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_PARTNO_SHIFT))&SCB_CPUID_PARTNO_MASK)
#define SCB_CPUID_VARIANT_MASK 0xF00000u
#define SCB_CPUID_VARIANT_SHIFT 20
#define SCB_CPUID_VARIANT(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_VARIANT_SHIFT))&SCB_CPUID_VARIANT_MASK)
#define SCB_CPUID_IMPLEMENTER_MASK 0xFF000000u
#define SCB_CPUID_IMPLEMENTER_SHIFT 24
#define SCB_CPUID_IMPLEMENTER(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_IMPLEMENTER_SHIFT))&SCB_CPUID_IMPLEMENTER_MASK)
/* ICSR Bit Fields */
#define SCB_ICSR_VECTACTIVE_MASK 0x1FFu
#define SCB_ICSR_VECTACTIVE_SHIFT 0
#define SCB_ICSR_VECTACTIVE(x) (((uint32_t)(((uint32_t)(x))<<SCB_ICSR_VECTACTIVE_SHIFT))&SCB_ICSR_VECTACTIVE_MASK)
#define SCB_ICSR_RETTOBASE_MASK 0x800u
#define SCB_ICSR_RETTOBASE_SHIFT 11
#define SCB_ICSR_VECTPENDING_MASK 0x3F000u
#define SCB_ICSR_VECTPENDING_SHIFT 12
#define SCB_ICSR_VECTPENDING(x) (((uint32_t)(((uint32_t)(x))<<SCB_ICSR_VECTPENDING_SHIFT))&SCB_ICSR_VECTPENDING_MASK)
#define SCB_ICSR_ISRPENDING_MASK 0x400000u
#define SCB_ICSR_ISRPENDING_SHIFT 22
#define SCB_ICSR_ISRPREEMPT_MASK 0x800000u
#define SCB_ICSR_ISRPREEMPT_SHIFT 23
#define SCB_ICSR_PENDSTCLR_MASK 0x2000000u
#define SCB_ICSR_PENDSTCLR_SHIFT 25
#define SCB_ICSR_PENDSTSET_MASK 0x4000000u
#define SCB_ICSR_PENDSTSET_SHIFT 26
#define SCB_ICSR_PENDSVCLR_MASK 0x8000000u
#define SCB_ICSR_PENDSVCLR_SHIFT 27
#define SCB_ICSR_PENDSVSET_MASK 0x10000000u
#define SCB_ICSR_PENDSVSET_SHIFT 28
#define SCB_ICSR_NMIPENDSET_MASK 0x80000000u
#define SCB_ICSR_NMIPENDSET_SHIFT 31
/* VTOR Bit Fields */
#define SCB_VTOR_TBLOFF_MASK 0xFFFFFF80u
#define SCB_VTOR_TBLOFF_SHIFT 7
#define SCB_VTOR_TBLOFF(x) (((uint32_t)(((uint32_t)(x))<<SCB_VTOR_TBLOFF_SHIFT))&SCB_VTOR_TBLOFF_MASK)
/* AIRCR Bit Fields */
#define SCB_AIRCR_VECTRESET_MASK 0x1u
#define SCB_AIRCR_VECTRESET_SHIFT 0
#define SCB_AIRCR_VECTCLRACTIVE_MASK 0x2u
#define SCB_AIRCR_VECTCLRACTIVE_SHIFT 1
#define SCB_AIRCR_SYSRESETREQ_MASK 0x4u
#define SCB_AIRCR_SYSRESETREQ_SHIFT 2
#define SCB_AIRCR_PRIGROUP_MASK 0x700u
#define SCB_AIRCR_PRIGROUP_SHIFT 8
#define SCB_AIRCR_PRIGROUP(x) (((uint32_t)(((uint32_t)(x))<<SCB_AIRCR_PRIGROUP_SHIFT))&SCB_AIRCR_PRIGROUP_MASK)
#define SCB_AIRCR_ENDIANNESS_MASK 0x8000u
#define SCB_AIRCR_ENDIANNESS_SHIFT 15
#define SCB_AIRCR_VECTKEY_MASK 0xFFFF0000u
#define SCB_AIRCR_VECTKEY_SHIFT 16
#define SCB_AIRCR_VECTKEY(x) (((uint32_t)(((uint32_t)(x))<<SCB_AIRCR_VECTKEY_SHIFT))&SCB_AIRCR_VECTKEY_MASK)
/* SCR Bit Fields */
#define SCB_SCR_SLEEPONEXIT_MASK 0x2u
#define SCB_SCR_SLEEPONEXIT_SHIFT 1
#define SCB_SCR_SLEEPDEEP_MASK 0x4u
#define SCB_SCR_SLEEPDEEP_SHIFT 2
#define SCB_SCR_SEVONPEND_MASK 0x10u
#define SCB_SCR_SEVONPEND_SHIFT 4
/* CCR Bit Fields */
#define SCB_CCR_NONBASETHRDENA_MASK 0x1u
#define SCB_CCR_NONBASETHRDENA_SHIFT 0
#define SCB_CCR_USERSETMPEND_MASK 0x2u
#define SCB_CCR_USERSETMPEND_SHIFT 1
#define SCB_CCR_UNALIGN_TRP_MASK 0x8u
#define SCB_CCR_UNALIGN_TRP_SHIFT 3
#define SCB_CCR_DIV_0_TRP_MASK 0x10u
#define SCB_CCR_DIV_0_TRP_SHIFT 4
#define SCB_CCR_BFHFNMIGN_MASK 0x100u
#define SCB_CCR_BFHFNMIGN_SHIFT 8
#define SCB_CCR_STKALIGN_MASK 0x200u
#define SCB_CCR_STKALIGN_SHIFT 9
/* SHPR1 Bit Fields */
#define SCB_SHPR1_PRI_4_MASK 0xFFu
#define SCB_SHPR1_PRI_4_SHIFT 0
#define SCB_SHPR1_PRI_4(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR1_PRI_4_SHIFT))&SCB_SHPR1_PRI_4_MASK)
#define SCB_SHPR1_PRI_5_MASK 0xFF00u
#define SCB_SHPR1_PRI_5_SHIFT 8
#define SCB_SHPR1_PRI_5(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR1_PRI_5_SHIFT))&SCB_SHPR1_PRI_5_MASK)
#define SCB_SHPR1_PRI_6_MASK 0xFF0000u
#define SCB_SHPR1_PRI_6_SHIFT 16
#define SCB_SHPR1_PRI_6(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR1_PRI_6_SHIFT))&SCB_SHPR1_PRI_6_MASK)
/* SHPR2 Bit Fields */
#define SCB_SHPR2_PRI_11_MASK 0xFF000000u
#define SCB_SHPR2_PRI_11_SHIFT 24
#define SCB_SHPR2_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR2_PRI_11_SHIFT))&SCB_SHPR2_PRI_11_MASK)
/* SHPR3 Bit Fields */
#define SCB_SHPR3_PRI_14_MASK 0xFF0000u
#define SCB_SHPR3_PRI_14_SHIFT 16
#define SCB_SHPR3_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR3_PRI_14_SHIFT))&SCB_SHPR3_PRI_14_MASK)
#define SCB_SHPR3_PRI_15_MASK 0xFF000000u
#define SCB_SHPR3_PRI_15_SHIFT 24
#define SCB_SHPR3_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR3_PRI_15_SHIFT))&SCB_SHPR3_PRI_15_MASK)
/* SHCSR Bit Fields */
#define SCB_SHCSR_MEMFAULTACT_MASK 0x1u
#define SCB_SHCSR_MEMFAULTACT_SHIFT 0
#define SCB_SHCSR_BUSFAULTACT_MASK 0x2u
#define SCB_SHCSR_BUSFAULTACT_SHIFT 1
#define SCB_SHCSR_USGFAULTACT_MASK 0x8u
#define SCB_SHCSR_USGFAULTACT_SHIFT 3
#define SCB_SHCSR_SVCALLACT_MASK 0x80u
#define SCB_SHCSR_SVCALLACT_SHIFT 7
#define SCB_SHCSR_MONITORACT_MASK 0x100u
#define SCB_SHCSR_MONITORACT_SHIFT 8
#define SCB_SHCSR_PENDSVACT_MASK 0x400u
#define SCB_SHCSR_PENDSVACT_SHIFT 10
#define SCB_SHCSR_SYSTICKACT_MASK 0x800u
#define SCB_SHCSR_SYSTICKACT_SHIFT 11
#define SCB_SHCSR_USGFAULTPENDED_MASK 0x1000u
#define SCB_SHCSR_USGFAULTPENDED_SHIFT 12
#define SCB_SHCSR_MEMFAULTPENDED_MASK 0x2000u
#define SCB_SHCSR_MEMFAULTPENDED_SHIFT 13
#define SCB_SHCSR_BUSFAULTPENDED_MASK 0x4000u
#define SCB_SHCSR_BUSFAULTPENDED_SHIFT 14
#define SCB_SHCSR_SVCALLPENDED_MASK 0x8000u
#define SCB_SHCSR_SVCALLPENDED_SHIFT 15
#define SCB_SHCSR_MEMFAULTENA_MASK 0x10000u
#define SCB_SHCSR_MEMFAULTENA_SHIFT 16
#define SCB_SHCSR_BUSFAULTENA_MASK 0x20000u
#define SCB_SHCSR_BUSFAULTENA_SHIFT 17
#define SCB_SHCSR_USGFAULTENA_MASK 0x40000u
#define SCB_SHCSR_USGFAULTENA_SHIFT 18
/* CFSR Bit Fields */
#define SCB_CFSR_IACCVIOL_MASK 0x1u
#define SCB_CFSR_IACCVIOL_SHIFT 0
#define SCB_CFSR_DACCVIOL_MASK 0x2u
#define SCB_CFSR_DACCVIOL_SHIFT 1
#define SCB_CFSR_MUNSTKERR_MASK 0x8u
#define SCB_CFSR_MUNSTKERR_SHIFT 3
#define SCB_CFSR_MSTKERR_MASK 0x10u
#define SCB_CFSR_MSTKERR_SHIFT 4
#define SCB_CFSR_MLSPERR_MASK 0x20u
#define SCB_CFSR_MLSPERR_SHIFT 5
#define SCB_CFSR_MMARVALID_MASK 0x80u
#define SCB_CFSR_MMARVALID_SHIFT 7
#define SCB_CFSR_IBUSERR_MASK 0x100u
#define SCB_CFSR_IBUSERR_SHIFT 8
#define SCB_CFSR_PRECISERR_MASK 0x200u
#define SCB_CFSR_PRECISERR_SHIFT 9
#define SCB_CFSR_IMPRECISERR_MASK 0x400u
#define SCB_CFSR_IMPRECISERR_SHIFT 10
#define SCB_CFSR_UNSTKERR_MASK 0x800u
#define SCB_CFSR_UNSTKERR_SHIFT 11
#define SCB_CFSR_STKERR_MASK 0x1000u
#define SCB_CFSR_STKERR_SHIFT 12
#define SCB_CFSR_LSPERR_MASK 0x2000u
#define SCB_CFSR_LSPERR_SHIFT 13
#define SCB_CFSR_BFARVALID_MASK 0x8000u
#define SCB_CFSR_BFARVALID_SHIFT 15
#define SCB_CFSR_UNDEFINSTR_MASK 0x10000u
#define SCB_CFSR_UNDEFINSTR_SHIFT 16
#define SCB_CFSR_INVSTATE_MASK 0x20000u
#define SCB_CFSR_INVSTATE_SHIFT 17
#define SCB_CFSR_INVPC_MASK 0x40000u
#define SCB_CFSR_INVPC_SHIFT 18
#define SCB_CFSR_NOCP_MASK 0x80000u
#define SCB_CFSR_NOCP_SHIFT 19
#define SCB_CFSR_UNALIGNED_MASK 0x1000000u
#define SCB_CFSR_UNALIGNED_SHIFT 24
#define SCB_CFSR_DIVBYZERO_MASK 0x2000000u
#define SCB_CFSR_DIVBYZERO_SHIFT 25
/* HFSR Bit Fields */
#define SCB_HFSR_VECTTBL_MASK 0x2u
#define SCB_HFSR_VECTTBL_SHIFT 1
#define SCB_HFSR_FORCED_MASK 0x40000000u
#define SCB_HFSR_FORCED_SHIFT 30
#define SCB_HFSR_DEBUGEVT_MASK 0x80000000u
#define SCB_HFSR_DEBUGEVT_SHIFT 31
/* DFSR Bit Fields */
#define SCB_DFSR_HALTED_MASK 0x1u
#define SCB_DFSR_HALTED_SHIFT 0
#define SCB_DFSR_BKPT_MASK 0x2u
#define SCB_DFSR_BKPT_SHIFT 1
#define SCB_DFSR_DWTTRAP_MASK 0x4u
#define SCB_DFSR_DWTTRAP_SHIFT 2
#define SCB_DFSR_VCATCH_MASK 0x8u
#define SCB_DFSR_VCATCH_SHIFT 3
#define SCB_DFSR_EXTERNAL_MASK 0x10u
#define SCB_DFSR_EXTERNAL_SHIFT 4
/* MMFAR Bit Fields */
#define SCB_MMFAR_ADDRESS_MASK 0xFFFFFFFFu
#define SCB_MMFAR_ADDRESS_SHIFT 0
#define SCB_MMFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<SCB_MMFAR_ADDRESS_SHIFT))&SCB_MMFAR_ADDRESS_MASK)
/* BFAR Bit Fields */
#define SCB_BFAR_ADDRESS_MASK 0xFFFFFFFFu
#define SCB_BFAR_ADDRESS_SHIFT 0
#define SCB_BFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<SCB_BFAR_ADDRESS_SHIFT))&SCB_BFAR_ADDRESS_MASK)
/* AFSR Bit Fields */
#define SCB_AFSR_AUXFAULT_MASK 0xFFFFFFFFu
#define SCB_AFSR_AUXFAULT_SHIFT 0
#define SCB_AFSR_AUXFAULT(x) (((uint32_t)(((uint32_t)(x))<<SCB_AFSR_AUXFAULT_SHIFT))&SCB_AFSR_AUXFAULT_MASK)
/**
* @}
*/ /* end of group SCB_Register_Masks */
/* SCB - Peripheral instance base addresses */
/** Peripheral SystemControl base pointer */
#define SystemControl_BASE_PTR ((SCB_MemMapPtr)0xE000E000u)
/* ----------------------------------------------------------------------------
-- SCB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup SCB_Register_Accessor_Macros SCB - Register accessor macros
* @{
*/
/* SCB - Register instance definitions */
/* SystemControl */
#define SCB_ACTLR SCB_ACTLR_REG(SystemControl_BASE_PTR)
#define SCB_CPUID SCB_CPUID_REG(SystemControl_BASE_PTR)
#define SCB_ICSR SCB_ICSR_REG(SystemControl_BASE_PTR)
#define SCB_AIRCR SCB_AIRCR_REG(SystemControl_BASE_PTR)
#define SCB_VTOR SCB_VTOR_REG(SystemControl_BASE_PTR)
#define SCB_SCR SCB_SCR_REG(SystemControl_BASE_PTR)
#define SCB_CCR SCB_CCR_REG(SystemControl_BASE_PTR)
#define SCB_SHPR1 SCB_SHPR1_REG(SystemControl_BASE_PTR)
#define SCB_SHPR2 SCB_SHPR2_REG(SystemControl_BASE_PTR)
#define SCB_SHPR3 SCB_SHPR3_REG(SystemControl_BASE_PTR)
#define SCB_SHCSR SCB_SHCSR_REG(SystemControl_BASE_PTR)
#define SCB_CFSR SCB_CFSR_REG(SystemControl_BASE_PTR)
#define SCB_HFSR SCB_HFSR_REG(SystemControl_BASE_PTR)
#define SCB_DFSR SCB_DFSR_REG(SystemControl_BASE_PTR)
#define SCB_MMFAR SCB_MMFAR_REG(SystemControl_BASE_PTR)
#define SCB_BFAR SCB_BFAR_REG(SystemControl_BASE_PTR)
#define SCB_AFSR SCB_AFSR_REG(SystemControl_BASE_PTR)
/**
* @}
*/ /* end of group SCB_Register_Accessor_Macros */
/**
* @}
*/ /* end of group SCB_Peripheral */
/* ----------------------------------------------------------------------------
-- TPIU
---------------------------------------------------------------------------- */
/**
* @addtogroup TPIU_Peripheral TPIU
* @{
*/
/** TPIU - Peripheral register structure */
typedef struct TPIU_MemMap {
uint32_t SSPSR; /**< Supported Parallel Port Size Register, offset: 0x0 */
uint32_t CSPSR; /**< Current Parallel Port Size Register, offset: 0x4 */
uint8_t RESERVED_0[8];
uint32_t ACPR; /**< Asynchronous Clock Prescaler Register, offset: 0x10 */
uint8_t RESERVED_1[220];
uint32_t SPPR; /**< Selected Pin Protocol Register, offset: 0xF0 */
uint8_t RESERVED_2[524];
uint32_t FFSR; /**< Formatter and Flush Status Register, offset: 0x300 */
uint32_t FFCR; /**< Formatter and Flush Control Register, offset: 0x304 */
uint32_t FSCR; /**< Formatter Synchronization Counter Register, offset: 0x308 */
uint8_t RESERVED_3[3036];
uint32_t TRIGGER; /**< Trigger Register, offset: 0xEE8 */
uint32_t FIFODATA0; /**< FIFODATA0 Register, offset: 0xEEC */
uint32_t ITATBCTR2; /**< Integration Test ATB Control 2 Register, offset: 0xEF0 */
uint8_t RESERVED_4[4];
uint32_t ITATBCTR0; /**< Integration Test ATB Control 0 Register, offset: 0xEF8 */
uint32_t FIFODATA1; /**< FIFODATA1 Register, offset: 0xEFC */
uint32_t ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */
uint8_t RESERVED_5[156];
uint32_t CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */
uint32_t CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */
uint8_t RESERVED_6[32];
uint32_t DEVID; /**< TPIU_DEVID Register, offset: 0xFC8 */
uint8_t RESERVED_7[4];
uint32_t PID4; /**< Peripheral Identification Register 4., offset: 0xFD0 */
uint32_t PID5; /**< Peripheral Identification Register 5., offset: 0xFD4 */
uint32_t PID6; /**< Peripheral Identification Register 6., offset: 0xFD8 */
uint32_t PID7; /**< Peripheral Identification Register 7., offset: 0xFDC */
uint32_t PID0; /**< Peripheral Identification Register 0., offset: 0xFE0 */
uint32_t PID1; /**< Peripheral Identification Register 1., offset: 0xFE4 */
uint32_t PID2; /**< Peripheral Identification Register 2., offset: 0xFE8 */
uint32_t PID3; /**< Peripheral Identification Register 3., offset: 0xFEC */
uint32_t CID0; /**< Component Identification Register 0., offset: 0xFF0 */
uint32_t CID1; /**< Component Identification Register 1., offset: 0xFF4 */
uint32_t CID2; /**< Component Identification Register 2., offset: 0xFF8 */
uint32_t CID4; /**< Component Identification Register 3., offset: 0xFFC */
} volatile *TPIU_MemMapPtr;
/* ----------------------------------------------------------------------------
-- TPIU - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup TPIU_Register_Accessor_Macros TPIU - Register accessor macros
* @{
*/
/* TPIU - Register accessors */
#define TPIU_SSPSR_REG(base) ((base)->SSPSR)
#define TPIU_CSPSR_REG(base) ((base)->CSPSR)
#define TPIU_ACPR_REG(base) ((base)->ACPR)
#define TPIU_SPPR_REG(base) ((base)->SPPR)
#define TPIU_FFSR_REG(base) ((base)->FFSR)
#define TPIU_FFCR_REG(base) ((base)->FFCR)
#define TPIU_FSCR_REG(base) ((base)->FSCR)
#define TPIU_TRIGGER_REG(base) ((base)->TRIGGER)
#define TPIU_FIFODATA0_REG(base) ((base)->FIFODATA0)
#define TPIU_ITATBCTR2_REG(base) ((base)->ITATBCTR2)
#define TPIU_ITATBCTR0_REG(base) ((base)->ITATBCTR0)
#define TPIU_FIFODATA1_REG(base) ((base)->FIFODATA1)
#define TPIU_ITCTRL_REG(base) ((base)->ITCTRL)
#define TPIU_CLAIMSET_REG(base) ((base)->CLAIMSET)
#define TPIU_CLAIMCLR_REG(base) ((base)->CLAIMCLR)
#define TPIU_DEVID_REG(base) ((base)->DEVID)
#define TPIU_PID4_REG(base) ((base)->PID4)
#define TPIU_PID5_REG(base) ((base)->PID5)
#define TPIU_PID6_REG(base) ((base)->PID6)
#define TPIU_PID7_REG(base) ((base)->PID7)
#define TPIU_PID0_REG(base) ((base)->PID0)
#define TPIU_PID1_REG(base) ((base)->PID1)
#define TPIU_PID2_REG(base) ((base)->PID2)
#define TPIU_PID3_REG(base) ((base)->PID3)
#define TPIU_CID0_REG(base) ((base)->CID0)
#define TPIU_CID1_REG(base) ((base)->CID1)
#define TPIU_CID2_REG(base) ((base)->CID2)
#define TPIU_CID4_REG(base) ((base)->CID4)
/**
* @}
*/ /* end of group TPIU_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- TPIU Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup TPIU_Register_Masks TPIU Register Masks
* @{
*/
/**
* @}
*/ /* end of group TPIU_Register_Masks */
/* TPIU - Peripheral instance base addresses */
/** Peripheral TPIU base pointer */
#define TPIU_BASE_PTR ((TPIU_MemMapPtr)0xE0040000u)
/* ----------------------------------------------------------------------------
-- TPIU - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup TPIU_Register_Accessor_Macros TPIU - Register accessor macros
* @{
*/
/* TPIU - Register instance definitions */
/* TPIU */
#define TPIU_SSPSR TPIU_SSPSR_REG(TPIU_BASE_PTR)
#define TPIU_CSPSR TPIU_CSPSR_REG(TPIU_BASE_PTR)
#define TPIU_ACPR TPIU_ACPR_REG(TPIU_BASE_PTR)
#define TPIU_SPPR TPIU_SPPR_REG(TPIU_BASE_PTR)
#define TPIU_FFSR TPIU_FFSR_REG(TPIU_BASE_PTR)
#define TPIU_FFCR TPIU_FFCR_REG(TPIU_BASE_PTR)
#define TPIU_FSCR TPIU_FSCR_REG(TPIU_BASE_PTR)
#define TPIU_TRIGGER TPIU_TRIGGER_REG(TPIU_BASE_PTR)
#define TPIU_FIFODATA0 TPIU_FIFODATA0_REG(TPIU_BASE_PTR)
#define TPIU_ITATBCTR2 TPIU_ITATBCTR2_REG(TPIU_BASE_PTR)
#define TPIU_FIFODATA1 TPIU_FIFODATA1_REG(TPIU_BASE_PTR)
#define TPIU_ITATBCTR0 TPIU_ITATBCTR0_REG(TPIU_BASE_PTR)
#define TPIU_ITCTRL TPIU_ITCTRL_REG(TPIU_BASE_PTR)
#define TPIU_CLAIMSET TPIU_CLAIMSET_REG(TPIU_BASE_PTR)
#define TPIU_CLAIMCLR TPIU_CLAIMCLR_REG(TPIU_BASE_PTR)
#define TPIU_DEVID TPIU_DEVID_REG(TPIU_BASE_PTR)
#define TPIU_PID4 TPIU_PID4_REG(TPIU_BASE_PTR)
#define TPIU_PID5 TPIU_PID5_REG(TPIU_BASE_PTR)
#define TPIU_PID6 TPIU_PID6_REG(TPIU_BASE_PTR)
#define TPIU_PID7 TPIU_PID7_REG(TPIU_BASE_PTR)
#define TPIU_PID0 TPIU_PID0_REG(TPIU_BASE_PTR)
#define TPIU_PID1 TPIU_PID1_REG(TPIU_BASE_PTR)
#define TPIU_PID2 TPIU_PID2_REG(TPIU_BASE_PTR)
#define TPIU_PID3 TPIU_PID3_REG(TPIU_BASE_PTR)
#define TPIU_CID0 TPIU_CID0_REG(TPIU_BASE_PTR)
#define TPIU_CID1 TPIU_CID1_REG(TPIU_BASE_PTR)
#define TPIU_CID2 TPIU_CID2_REG(TPIU_BASE_PTR)
#define TPIU_CID3 TPIU_CID4_REG(TPIU_BASE_PTR)
/**
* @}
*/ /* end of group TPIU_Register_Accessor_Macros */
/**
* @}
*/ /* end of group TPIU_Peripheral */
/* ----------------------------------------------------------------------------
-- TSI
---------------------------------------------------------------------------- */
/**
* @addtogroup TSI_Peripheral TSI
* @{
*/
/** TSI - Peripheral register structure */
typedef struct TSI_MemMap {
uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
uint32_t SCANC; /**< SCAN control register, offset: 0x4 */
uint32_t PEN; /**< Pin enable register, offset: 0x8 */
uint32_t STATUS; /**< Status Register, offset: 0xC */
uint8_t RESERVED_0[240];
uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
uint32_t THRESHLD[16]; /**< Channel n threshold register, array offset: 0x120, array step: 0x4 */
} volatile *TSI_MemMapPtr;
/* ----------------------------------------------------------------------------
-- TSI - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
* @{
*/
/* TSI - Register accessors */
#define TSI_GENCS_REG(base) ((base)->GENCS)
#define TSI_SCANC_REG(base) ((base)->SCANC)
#define TSI_PEN_REG(base) ((base)->PEN)
#define TSI_STATUS_REG(base) ((base)->STATUS)
#define TSI_CNTR1_REG(base) ((base)->CNTR1)
#define TSI_CNTR3_REG(base) ((base)->CNTR3)
#define TSI_CNTR5_REG(base) ((base)->CNTR5)
#define TSI_CNTR7_REG(base) ((base)->CNTR7)
#define TSI_CNTR9_REG(base) ((base)->CNTR9)
#define TSI_CNTR11_REG(base) ((base)->CNTR11)
#define TSI_CNTR13_REG(base) ((base)->CNTR13)
#define TSI_CNTR15_REG(base) ((base)->CNTR15)
#define TSI_THRESHLD_REG(base,index) ((base)->THRESHLD[index])
/**
* @}
*/ /* end of group TSI_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- TSI Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup TSI_Register_Masks TSI Register Masks
* @{
*/
/* GENCS Bit Fields */
#define TSI_GENCS_STPE_MASK 0x1u
#define TSI_GENCS_STPE_SHIFT 0
#define TSI_GENCS_STM_MASK 0x2u
#define TSI_GENCS_STM_SHIFT 1
#define TSI_GENCS_ESOR_MASK 0x10u
#define TSI_GENCS_ESOR_SHIFT 4
#define TSI_GENCS_ERIE_MASK 0x20u
#define TSI_GENCS_ERIE_SHIFT 5
#define TSI_GENCS_TSIIE_MASK 0x40u
#define TSI_GENCS_TSIIE_SHIFT 6
#define TSI_GENCS_TSIEN_MASK 0x80u
#define TSI_GENCS_TSIEN_SHIFT 7
#define TSI_GENCS_SWTS_MASK 0x100u
#define TSI_GENCS_SWTS_SHIFT 8
#define TSI_GENCS_SCNIP_MASK 0x200u
#define TSI_GENCS_SCNIP_SHIFT 9
#define TSI_GENCS_OVRF_MASK 0x1000u
#define TSI_GENCS_OVRF_SHIFT 12
#define TSI_GENCS_EXTERF_MASK 0x2000u
#define TSI_GENCS_EXTERF_SHIFT 13
#define TSI_GENCS_OUTRGF_MASK 0x4000u
#define TSI_GENCS_OUTRGF_SHIFT 14
#define TSI_GENCS_EOSF_MASK 0x8000u
#define TSI_GENCS_EOSF_SHIFT 15
#define TSI_GENCS_PS_MASK 0x70000u
#define TSI_GENCS_PS_SHIFT 16
#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
#define TSI_GENCS_NSCN_MASK 0xF80000u
#define TSI_GENCS_NSCN_SHIFT 19
#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
#define TSI_GENCS_LPSCNITV_MASK 0xF000000u
#define TSI_GENCS_LPSCNITV_SHIFT 24
#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
#define TSI_GENCS_LPCLKS_MASK 0x10000000u
#define TSI_GENCS_LPCLKS_SHIFT 28
/* SCANC Bit Fields */
#define TSI_SCANC_AMPSC_MASK 0x7u
#define TSI_SCANC_AMPSC_SHIFT 0
#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
#define TSI_SCANC_AMCLKS_MASK 0x18u
#define TSI_SCANC_AMCLKS_SHIFT 3
#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
#define TSI_SCANC_AMCLKDIV_MASK 0x20u
#define TSI_SCANC_AMCLKDIV_SHIFT 5
#define TSI_SCANC_SMOD_MASK 0xFF00u
#define TSI_SCANC_SMOD_SHIFT 8
#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
#define TSI_SCANC_DELVOL_MASK 0x70000u
#define TSI_SCANC_DELVOL_SHIFT 16
#define TSI_SCANC_DELVOL(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_DELVOL_SHIFT))&TSI_SCANC_DELVOL_MASK)
#define TSI_SCANC_EXTCHRG_MASK 0xF80000u
#define TSI_SCANC_EXTCHRG_SHIFT 19
#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
#define TSI_SCANC_CAPTRM_MASK 0x7000000u
#define TSI_SCANC_CAPTRM_SHIFT 24
#define TSI_SCANC_CAPTRM(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_CAPTRM_SHIFT))&TSI_SCANC_CAPTRM_MASK)
#define TSI_SCANC_REFCHRG_MASK 0xF8000000u
#define TSI_SCANC_REFCHRG_SHIFT 27
#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
/* PEN Bit Fields */
#define TSI_PEN_PEN0_MASK 0x1u
#define TSI_PEN_PEN0_SHIFT 0
#define TSI_PEN_PEN1_MASK 0x2u
#define TSI_PEN_PEN1_SHIFT 1
#define TSI_PEN_PEN2_MASK 0x4u
#define TSI_PEN_PEN2_SHIFT 2
#define TSI_PEN_PEN3_MASK 0x8u
#define TSI_PEN_PEN3_SHIFT 3
#define TSI_PEN_PEN4_MASK 0x10u
#define TSI_PEN_PEN4_SHIFT 4
#define TSI_PEN_PEN5_MASK 0x20u
#define TSI_PEN_PEN5_SHIFT 5
#define TSI_PEN_PEN6_MASK 0x40u
#define TSI_PEN_PEN6_SHIFT 6
#define TSI_PEN_PEN7_MASK 0x80u
#define TSI_PEN_PEN7_SHIFT 7
#define TSI_PEN_PEN8_MASK 0x100u
#define TSI_PEN_PEN8_SHIFT 8
#define TSI_PEN_PEN9_MASK 0x200u
#define TSI_PEN_PEN9_SHIFT 9
#define TSI_PEN_PEN10_MASK 0x400u
#define TSI_PEN_PEN10_SHIFT 10
#define TSI_PEN_PEN11_MASK 0x800u
#define TSI_PEN_PEN11_SHIFT 11
#define TSI_PEN_PEN12_MASK 0x1000u
#define TSI_PEN_PEN12_SHIFT 12
#define TSI_PEN_PEN13_MASK 0x2000u
#define TSI_PEN_PEN13_SHIFT 13
#define TSI_PEN_PEN14_MASK 0x4000u
#define TSI_PEN_PEN14_SHIFT 14
#define TSI_PEN_PEN15_MASK 0x8000u
#define TSI_PEN_PEN15_SHIFT 15
#define TSI_PEN_LPSP_MASK 0xF0000u
#define TSI_PEN_LPSP_SHIFT 16
#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
/* STATUS Bit Fields */
#define TSI_STATUS_ORNGF0_MASK 0x1u
#define TSI_STATUS_ORNGF0_SHIFT 0
#define TSI_STATUS_ORNGF1_MASK 0x2u
#define TSI_STATUS_ORNGF1_SHIFT 1
#define TSI_STATUS_ORNGF2_MASK 0x4u
#define TSI_STATUS_ORNGF2_SHIFT 2
#define TSI_STATUS_ORNGF3_MASK 0x8u
#define TSI_STATUS_ORNGF3_SHIFT 3
#define TSI_STATUS_ORNGF4_MASK 0x10u
#define TSI_STATUS_ORNGF4_SHIFT 4
#define TSI_STATUS_ORNGF5_MASK 0x20u
#define TSI_STATUS_ORNGF5_SHIFT 5
#define TSI_STATUS_ORNGF6_MASK 0x40u
#define TSI_STATUS_ORNGF6_SHIFT 6
#define TSI_STATUS_ORNGF7_MASK 0x80u
#define TSI_STATUS_ORNGF7_SHIFT 7
#define TSI_STATUS_ORNGF8_MASK 0x100u
#define TSI_STATUS_ORNGF8_SHIFT 8
#define TSI_STATUS_ORNGF9_MASK 0x200u
#define TSI_STATUS_ORNGF9_SHIFT 9
#define TSI_STATUS_ORNGF10_MASK 0x400u
#define TSI_STATUS_ORNGF10_SHIFT 10
#define TSI_STATUS_ORNGF11_MASK 0x800u
#define TSI_STATUS_ORNGF11_SHIFT 11
#define TSI_STATUS_ORNGF12_MASK 0x1000u
#define TSI_STATUS_ORNGF12_SHIFT 12
#define TSI_STATUS_ORNGF13_MASK 0x2000u
#define TSI_STATUS_ORNGF13_SHIFT 13
#define TSI_STATUS_ORNGF14_MASK 0x4000u
#define TSI_STATUS_ORNGF14_SHIFT 14
#define TSI_STATUS_ORNGF15_MASK 0x8000u
#define TSI_STATUS_ORNGF15_SHIFT 15
#define TSI_STATUS_ERROF0_MASK 0x10000u
#define TSI_STATUS_ERROF0_SHIFT 16
#define TSI_STATUS_ERROF1_MASK 0x20000u
#define TSI_STATUS_ERROF1_SHIFT 17
#define TSI_STATUS_ERROF2_MASK 0x40000u
#define TSI_STATUS_ERROF2_SHIFT 18
#define TSI_STATUS_ERROF3_MASK 0x80000u
#define TSI_STATUS_ERROF3_SHIFT 19
#define TSI_STATUS_ERROF4_MASK 0x100000u
#define TSI_STATUS_ERROF4_SHIFT 20
#define TSI_STATUS_ERROF5_MASK 0x200000u
#define TSI_STATUS_ERROF5_SHIFT 21
#define TSI_STATUS_ERROF6_MASK 0x400000u
#define TSI_STATUS_ERROF6_SHIFT 22
#define TSI_STATUS_ERROF7_MASK 0x800000u
#define TSI_STATUS_ERROF7_SHIFT 23
#define TSI_STATUS_ERROF8_MASK 0x1000000u
#define TSI_STATUS_ERROF8_SHIFT 24
#define TSI_STATUS_ERROF9_MASK 0x2000000u
#define TSI_STATUS_ERROF9_SHIFT 25
#define TSI_STATUS_ERROF10_MASK 0x4000000u
#define TSI_STATUS_ERROF10_SHIFT 26
#define TSI_STATUS_ERROF11_MASK 0x8000000u
#define TSI_STATUS_ERROF11_SHIFT 27
#define TSI_STATUS_ERROF12_MASK 0x10000000u
#define TSI_STATUS_ERROF12_SHIFT 28
#define TSI_STATUS_ERROF13_MASK 0x20000000u
#define TSI_STATUS_ERROF13_SHIFT 29
#define TSI_STATUS_ERROF14_MASK 0x40000000u
#define TSI_STATUS_ERROF14_SHIFT 30
#define TSI_STATUS_ERROF15_MASK 0x80000000u
#define TSI_STATUS_ERROF15_SHIFT 31
/* CNTR1 Bit Fields */
#define TSI_CNTR1_CTN1_MASK 0xFFFFu
#define TSI_CNTR1_CTN1_SHIFT 0
#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
#define TSI_CNTR1_CTN_MASK 0xFFFF0000u
#define TSI_CNTR1_CTN_SHIFT 16
#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
/* CNTR3 Bit Fields */
#define TSI_CNTR3_CTN1_MASK 0xFFFFu
#define TSI_CNTR3_CTN1_SHIFT 0
#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
#define TSI_CNTR3_CTN_MASK 0xFFFF0000u
#define TSI_CNTR3_CTN_SHIFT 16
#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
/* CNTR5 Bit Fields */
#define TSI_CNTR5_CTN1_MASK 0xFFFFu
#define TSI_CNTR5_CTN1_SHIFT 0
#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
#define TSI_CNTR5_CTN_MASK 0xFFFF0000u
#define TSI_CNTR5_CTN_SHIFT 16
#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
/* CNTR7 Bit Fields */
#define TSI_CNTR7_CTN1_MASK 0xFFFFu
#define TSI_CNTR7_CTN1_SHIFT 0
#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
#define TSI_CNTR7_CTN_MASK 0xFFFF0000u
#define TSI_CNTR7_CTN_SHIFT 16
#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
/* CNTR9 Bit Fields */
#define TSI_CNTR9_CTN1_MASK 0xFFFFu
#define TSI_CNTR9_CTN1_SHIFT 0
#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
#define TSI_CNTR9_CTN_MASK 0xFFFF0000u
#define TSI_CNTR9_CTN_SHIFT 16
#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
/* CNTR11 Bit Fields */
#define TSI_CNTR11_CTN1_MASK 0xFFFFu
#define TSI_CNTR11_CTN1_SHIFT 0
#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
#define TSI_CNTR11_CTN_MASK 0xFFFF0000u
#define TSI_CNTR11_CTN_SHIFT 16
#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
/* CNTR13 Bit Fields */
#define TSI_CNTR13_CTN1_MASK 0xFFFFu
#define TSI_CNTR13_CTN1_SHIFT 0
#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
#define TSI_CNTR13_CTN_MASK 0xFFFF0000u
#define TSI_CNTR13_CTN_SHIFT 16
#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
/* CNTR15 Bit Fields */
#define TSI_CNTR15_CTN1_MASK 0xFFFFu
#define TSI_CNTR15_CTN1_SHIFT 0
#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
#define TSI_CNTR15_CTN_MASK 0xFFFF0000u
#define TSI_CNTR15_CTN_SHIFT 16
#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
/* THRESHLD Bit Fields */
#define TSI_THRESHLD_HTHH_MASK 0xFFFFu
#define TSI_THRESHLD_HTHH_SHIFT 0
#define TSI_THRESHLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHLD_HTHH_SHIFT))&TSI_THRESHLD_HTHH_MASK)
#define TSI_THRESHLD_LTHH_MASK 0xFFFF0000u
#define TSI_THRESHLD_LTHH_SHIFT 16
#define TSI_THRESHLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHLD_LTHH_SHIFT))&TSI_THRESHLD_LTHH_MASK)
/**
* @}
*/ /* end of group TSI_Register_Masks */
/* TSI - Peripheral instance base addresses */
/** Peripheral TSI0 base pointer */
#define TSI0_BASE_PTR ((TSI_MemMapPtr)0x40045000u)
/* ----------------------------------------------------------------------------
-- TSI - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
* @{
*/
/* TSI - Register instance definitions */
/* TSI0 */
#define TSI0_GENCS TSI_GENCS_REG(TSI0_BASE_PTR)
#define TSI0_SCANC TSI_SCANC_REG(TSI0_BASE_PTR)
#define TSI0_PEN TSI_PEN_REG(TSI0_BASE_PTR)
#define TSI0_STATUS TSI_STATUS_REG(TSI0_BASE_PTR)
#define TSI0_CNTR1 TSI_CNTR1_REG(TSI0_BASE_PTR)
#define TSI0_CNTR3 TSI_CNTR3_REG(TSI0_BASE_PTR)
#define TSI0_CNTR5 TSI_CNTR5_REG(TSI0_BASE_PTR)
#define TSI0_CNTR7 TSI_CNTR7_REG(TSI0_BASE_PTR)
#define TSI0_CNTR9 TSI_CNTR9_REG(TSI0_BASE_PTR)
#define TSI0_CNTR11 TSI_CNTR11_REG(TSI0_BASE_PTR)
#define TSI0_CNTR13 TSI_CNTR13_REG(TSI0_BASE_PTR)
#define TSI0_CNTR15 TSI_CNTR15_REG(TSI0_BASE_PTR)
#define TSI0_THRESHLD0 TSI_THRESHLD_REG(TSI0_BASE_PTR,0)
#define TSI0_THRESHLD1 TSI_THRESHLD_REG(TSI0_BASE_PTR,1)
#define TSI0_THRESHLD2 TSI_THRESHLD_REG(TSI0_BASE_PTR,2)
#define TSI0_THRESHLD3 TSI_THRESHLD_REG(TSI0_BASE_PTR,3)
#define TSI0_THRESHLD4 TSI_THRESHLD_REG(TSI0_BASE_PTR,4)
#define TSI0_THRESHLD5 TSI_THRESHLD_REG(TSI0_BASE_PTR,5)
#define TSI0_THRESHLD6 TSI_THRESHLD_REG(TSI0_BASE_PTR,6)
#define TSI0_THRESHLD7 TSI_THRESHLD_REG(TSI0_BASE_PTR,7)
#define TSI0_THRESHLD8 TSI_THRESHLD_REG(TSI0_BASE_PTR,8)
#define TSI0_THRESHLD9 TSI_THRESHLD_REG(TSI0_BASE_PTR,9)
#define TSI0_THRESHLD10 TSI_THRESHLD_REG(TSI0_BASE_PTR,10)
#define TSI0_THRESHLD11 TSI_THRESHLD_REG(TSI0_BASE_PTR,11)
#define TSI0_THRESHLD12 TSI_THRESHLD_REG(TSI0_BASE_PTR,12)
#define TSI0_THRESHLD13 TSI_THRESHLD_REG(TSI0_BASE_PTR,13)
#define TSI0_THRESHLD14 TSI_THRESHLD_REG(TSI0_BASE_PTR,14)
#define TSI0_THRESHLD15 TSI_THRESHLD_REG(TSI0_BASE_PTR,15)
/* TSI - Register array accessors */
#define TSI0_THRESHLD(index) TSI_THRESHLD_REG(TSI0_BASE_PTR,index)
/**
* @}
*/ /* end of group TSI_Register_Accessor_Macros */
/**
* @}
*/ /* end of group TSI_Peripheral */
/* ----------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------- */
/**
* @addtogroup UART_Peripheral UART
* @{
*/
/** UART - Peripheral register structure */
typedef struct UART_MemMap {
uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
uint8_t D; /**< UART Data Register, offset: 0x7 */
uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
uint8_t C4; /**< UART Control Register 4, offset: 0xA */
uint8_t C5; /**< UART Control Register 5, offset: 0xB */
uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
uint8_t IR; /**< UART Infrared Register, offset: 0xE */
uint8_t RESERVED_0[1];
uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
uint8_t RESERVED_1[1];
uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
union { /* offset: 0x1B */
uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
};
uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
} volatile *UART_MemMapPtr;
/* ----------------------------------------------------------------------------
-- UART - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
* @{
*/
/* UART - Register accessors */
#define UART_BDH_REG(base) ((base)->BDH)
#define UART_BDL_REG(base) ((base)->BDL)
#define UART_C1_REG(base) ((base)->C1)
#define UART_C2_REG(base) ((base)->C2)
#define UART_S1_REG(base) ((base)->S1)
#define UART_S2_REG(base) ((base)->S2)
#define UART_C3_REG(base) ((base)->C3)
#define UART_D_REG(base) ((base)->D)
#define UART_MA1_REG(base) ((base)->MA1)
#define UART_MA2_REG(base) ((base)->MA2)
#define UART_C4_REG(base) ((base)->C4)
#define UART_C5_REG(base) ((base)->C5)
#define UART_ED_REG(base) ((base)->ED)
#define UART_MODEM_REG(base) ((base)->MODEM)
#define UART_IR_REG(base) ((base)->IR)
#define UART_PFIFO_REG(base) ((base)->PFIFO)
#define UART_CFIFO_REG(base) ((base)->CFIFO)
#define UART_SFIFO_REG(base) ((base)->SFIFO)
#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
#define UART_C7816_REG(base) ((base)->C7816)
#define UART_IE7816_REG(base) ((base)->IE7816)
#define UART_IS7816_REG(base) ((base)->IS7816)
#define UART_WP7816_T_TYPE0_REG(base) ((base)->WP7816_T_TYPE0)
#define UART_WP7816_T_TYPE1_REG(base) ((base)->WP7816_T_TYPE1)
#define UART_WN7816_REG(base) ((base)->WN7816)
#define UART_WF7816_REG(base) ((base)->WF7816)
#define UART_ET7816_REG(base) ((base)->ET7816)
#define UART_TL7816_REG(base) ((base)->TL7816)
/**
* @}
*/ /* end of group UART_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- UART Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup UART_Register_Masks UART Register Masks
* @{
*/
/* BDH Bit Fields */
#define UART_BDH_SBR_MASK 0x1Fu
#define UART_BDH_SBR_SHIFT 0
#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
#define UART_BDH_RXEDGIE_MASK 0x40u
#define UART_BDH_RXEDGIE_SHIFT 6
#define UART_BDH_LBKDIE_MASK 0x80u
#define UART_BDH_LBKDIE_SHIFT 7
/* BDL Bit Fields */
#define UART_BDL_SBR_MASK 0xFFu
#define UART_BDL_SBR_SHIFT 0
#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
/* C1 Bit Fields */
#define UART_C1_PT_MASK 0x1u
#define UART_C1_PT_SHIFT 0
#define UART_C1_PE_MASK 0x2u
#define UART_C1_PE_SHIFT 1
#define UART_C1_ILT_MASK 0x4u
#define UART_C1_ILT_SHIFT 2
#define UART_C1_WAKE_MASK 0x8u
#define UART_C1_WAKE_SHIFT 3
#define UART_C1_M_MASK 0x10u
#define UART_C1_M_SHIFT 4
#define UART_C1_RSRC_MASK 0x20u
#define UART_C1_RSRC_SHIFT 5
#define UART_C1_UARTSWAI_MASK 0x40u
#define UART_C1_UARTSWAI_SHIFT 6
#define UART_C1_LOOPS_MASK 0x80u
#define UART_C1_LOOPS_SHIFT 7
/* C2 Bit Fields */
#define UART_C2_SBK_MASK 0x1u
#define UART_C2_SBK_SHIFT 0
#define UART_C2_RWU_MASK 0x2u
#define UART_C2_RWU_SHIFT 1
#define UART_C2_RE_MASK 0x4u
#define UART_C2_RE_SHIFT 2
#define UART_C2_TE_MASK 0x8u
#define UART_C2_TE_SHIFT 3
#define UART_C2_ILIE_MASK 0x10u
#define UART_C2_ILIE_SHIFT 4
#define UART_C2_RIE_MASK 0x20u
#define UART_C2_RIE_SHIFT 5
#define UART_C2_TCIE_MASK 0x40u
#define UART_C2_TCIE_SHIFT 6
#define UART_C2_TIE_MASK 0x80u
#define UART_C2_TIE_SHIFT 7
/* S1 Bit Fields */
#define UART_S1_PF_MASK 0x1u
#define UART_S1_PF_SHIFT 0
#define UART_S1_FE_MASK 0x2u
#define UART_S1_FE_SHIFT 1
#define UART_S1_NF_MASK 0x4u
#define UART_S1_NF_SHIFT 2
#define UART_S1_OR_MASK 0x8u
#define UART_S1_OR_SHIFT 3
#define UART_S1_IDLE_MASK 0x10u
#define UART_S1_IDLE_SHIFT 4
#define UART_S1_RDRF_MASK 0x20u
#define UART_S1_RDRF_SHIFT 5
#define UART_S1_TC_MASK 0x40u
#define UART_S1_TC_SHIFT 6
#define UART_S1_TDRE_MASK 0x80u
#define UART_S1_TDRE_SHIFT 7
/* S2 Bit Fields */
#define UART_S2_RAF_MASK 0x1u
#define UART_S2_RAF_SHIFT 0
#define UART_S2_LBKDE_MASK 0x2u
#define UART_S2_LBKDE_SHIFT 1
#define UART_S2_BRK13_MASK 0x4u
#define UART_S2_BRK13_SHIFT 2
#define UART_S2_RWUID_MASK 0x8u
#define UART_S2_RWUID_SHIFT 3
#define UART_S2_RXINV_MASK 0x10u
#define UART_S2_RXINV_SHIFT 4
#define UART_S2_MSBF_MASK 0x20u
#define UART_S2_MSBF_SHIFT 5
#define UART_S2_RXEDGIF_MASK 0x40u
#define UART_S2_RXEDGIF_SHIFT 6
#define UART_S2_LBKDIF_MASK 0x80u
#define UART_S2_LBKDIF_SHIFT 7
/* C3 Bit Fields */
#define UART_C3_PEIE_MASK 0x1u
#define UART_C3_PEIE_SHIFT 0
#define UART_C3_FEIE_MASK 0x2u
#define UART_C3_FEIE_SHIFT 1
#define UART_C3_NEIE_MASK 0x4u
#define UART_C3_NEIE_SHIFT 2
#define UART_C3_ORIE_MASK 0x8u
#define UART_C3_ORIE_SHIFT 3
#define UART_C3_TXINV_MASK 0x10u
#define UART_C3_TXINV_SHIFT 4
#define UART_C3_TXDIR_MASK 0x20u
#define UART_C3_TXDIR_SHIFT 5
#define UART_C3_T8_MASK 0x40u
#define UART_C3_T8_SHIFT 6
#define UART_C3_R8_MASK 0x80u
#define UART_C3_R8_SHIFT 7
/* D Bit Fields */
#define UART_D_RT_MASK 0xFFu
#define UART_D_RT_SHIFT 0
#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
/* MA1 Bit Fields */
#define UART_MA1_MA_MASK 0xFFu
#define UART_MA1_MA_SHIFT 0
#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
/* MA2 Bit Fields */
#define UART_MA2_MA_MASK 0xFFu
#define UART_MA2_MA_SHIFT 0
#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
/* C4 Bit Fields */
#define UART_C4_BRFA_MASK 0x1Fu
#define UART_C4_BRFA_SHIFT 0
#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
#define UART_C4_M10_MASK 0x20u
#define UART_C4_M10_SHIFT 5
#define UART_C4_MAEN2_MASK 0x40u
#define UART_C4_MAEN2_SHIFT 6
#define UART_C4_MAEN1_MASK 0x80u
#define UART_C4_MAEN1_SHIFT 7
/* C5 Bit Fields */
#define UART_C5_RDMAS_MASK 0x20u
#define UART_C5_RDMAS_SHIFT 5
#define UART_C5_TDMAS_MASK 0x80u
#define UART_C5_TDMAS_SHIFT 7
/* ED Bit Fields */
#define UART_ED_PARITYE_MASK 0x40u
#define UART_ED_PARITYE_SHIFT 6
#define UART_ED_NOISY_MASK 0x80u
#define UART_ED_NOISY_SHIFT 7
/* MODEM Bit Fields */
#define UART_MODEM_TXCTSE_MASK 0x1u
#define UART_MODEM_TXCTSE_SHIFT 0
#define UART_MODEM_TXRTSE_MASK 0x2u
#define UART_MODEM_TXRTSE_SHIFT 1
#define UART_MODEM_TXRTSPOL_MASK 0x4u
#define UART_MODEM_TXRTSPOL_SHIFT 2
#define UART_MODEM_RXRTSE_MASK 0x8u
#define UART_MODEM_RXRTSE_SHIFT 3
/* IR Bit Fields */
#define UART_IR_TNP_MASK 0x3u
#define UART_IR_TNP_SHIFT 0
#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
#define UART_IR_IREN_MASK 0x4u
#define UART_IR_IREN_SHIFT 2
/* PFIFO Bit Fields */
#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
#define UART_PFIFO_RXFE_MASK 0x8u
#define UART_PFIFO_RXFE_SHIFT 3
#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
#define UART_PFIFO_TXFE_MASK 0x80u
#define UART_PFIFO_TXFE_SHIFT 7
/* CFIFO Bit Fields */
#define UART_CFIFO_RXUFE_MASK 0x1u
#define UART_CFIFO_RXUFE_SHIFT 0
#define UART_CFIFO_TXOFE_MASK 0x2u
#define UART_CFIFO_TXOFE_SHIFT 1
#define UART_CFIFO_RXFLUSH_MASK 0x40u
#define UART_CFIFO_RXFLUSH_SHIFT 6
#define UART_CFIFO_TXFLUSH_MASK 0x80u
#define UART_CFIFO_TXFLUSH_SHIFT 7
/* SFIFO Bit Fields */
#define UART_SFIFO_RXUF_MASK 0x1u
#define UART_SFIFO_RXUF_SHIFT 0
#define UART_SFIFO_TXOF_MASK 0x2u
#define UART_SFIFO_TXOF_SHIFT 1
#define UART_SFIFO_RXEMPT_MASK 0x40u
#define UART_SFIFO_RXEMPT_SHIFT 6
#define UART_SFIFO_TXEMPT_MASK 0x80u
#define UART_SFIFO_TXEMPT_SHIFT 7
/* TWFIFO Bit Fields */
#define UART_TWFIFO_TXWATER_MASK 0xFFu
#define UART_TWFIFO_TXWATER_SHIFT 0
#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
/* TCFIFO Bit Fields */
#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
#define UART_TCFIFO_TXCOUNT_SHIFT 0
#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
/* RWFIFO Bit Fields */
#define UART_RWFIFO_RXWATER_MASK 0xFFu
#define UART_RWFIFO_RXWATER_SHIFT 0
#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
/* RCFIFO Bit Fields */
#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
#define UART_RCFIFO_RXCOUNT_SHIFT 0
#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
/* C7816 Bit Fields */
#define UART_C7816_ISO_7816E_MASK 0x1u
#define UART_C7816_ISO_7816E_SHIFT 0
#define UART_C7816_TTYPE_MASK 0x2u
#define UART_C7816_TTYPE_SHIFT 1
#define UART_C7816_INIT_MASK 0x4u
#define UART_C7816_INIT_SHIFT 2
#define UART_C7816_ANACK_MASK 0x8u
#define UART_C7816_ANACK_SHIFT 3
#define UART_C7816_ONACK_MASK 0x10u
#define UART_C7816_ONACK_SHIFT 4
/* IE7816 Bit Fields */
#define UART_IE7816_RXTE_MASK 0x1u
#define UART_IE7816_RXTE_SHIFT 0
#define UART_IE7816_TXTE_MASK 0x2u
#define UART_IE7816_TXTE_SHIFT 1
#define UART_IE7816_GTVE_MASK 0x4u
#define UART_IE7816_GTVE_SHIFT 2
#define UART_IE7816_INITDE_MASK 0x10u
#define UART_IE7816_INITDE_SHIFT 4
#define UART_IE7816_BWTE_MASK 0x20u
#define UART_IE7816_BWTE_SHIFT 5
#define UART_IE7816_CWTE_MASK 0x40u
#define UART_IE7816_CWTE_SHIFT 6
#define UART_IE7816_WTE_MASK 0x80u
#define UART_IE7816_WTE_SHIFT 7
/* IS7816 Bit Fields */
#define UART_IS7816_RXT_MASK 0x1u
#define UART_IS7816_RXT_SHIFT 0
#define UART_IS7816_TXT_MASK 0x2u
#define UART_IS7816_TXT_SHIFT 1
#define UART_IS7816_GTV_MASK 0x4u
#define UART_IS7816_GTV_SHIFT 2
#define UART_IS7816_INITD_MASK 0x10u
#define UART_IS7816_INITD_SHIFT 4
#define UART_IS7816_BWT_MASK 0x20u
#define UART_IS7816_BWT_SHIFT 5
#define UART_IS7816_CWT_MASK 0x40u
#define UART_IS7816_CWT_SHIFT 6
#define UART_IS7816_WT_MASK 0x80u
#define UART_IS7816_WT_SHIFT 7
/* WP7816_T_TYPE0 Bit Fields */
#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
#define UART_WP7816_T_TYPE0_WI_SHIFT 0
#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
/* WP7816_T_TYPE1 Bit Fields */
#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
#define UART_WP7816_T_TYPE1_BWI_SHIFT 0
#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
#define UART_WP7816_T_TYPE1_CWI_SHIFT 4
#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
/* WN7816 Bit Fields */
#define UART_WN7816_GTN_MASK 0xFFu
#define UART_WN7816_GTN_SHIFT 0
#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
/* WF7816 Bit Fields */
#define UART_WF7816_GTFD_MASK 0xFFu
#define UART_WF7816_GTFD_SHIFT 0
#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
/* ET7816 Bit Fields */
#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
#define UART_ET7816_RXTHRESHOLD_SHIFT 0
#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
#define UART_ET7816_TXTHRESHOLD_SHIFT 4
#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
/* TL7816 Bit Fields */
#define UART_TL7816_TLEN_MASK 0xFFu
#define UART_TL7816_TLEN_SHIFT 0
#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
/**
* @}
*/ /* end of group UART_Register_Masks */
/* UART - Peripheral instance base addresses */
/** Peripheral UART0 base pointer */
#define UART0_BASE_PTR ((UART_MemMapPtr)0x4006A000u)
/** Peripheral UART1 base pointer */
#define UART1_BASE_PTR ((UART_MemMapPtr)0x4006B000u)
/** Peripheral UART2 base pointer */
#define UART2_BASE_PTR ((UART_MemMapPtr)0x4006C000u)
/** Peripheral UART3 base pointer */
#define UART3_BASE_PTR ((UART_MemMapPtr)0x4006D000u)
/** Peripheral UART4 base pointer */
#define UART4_BASE_PTR ((UART_MemMapPtr)0x400EA000u)
/** Peripheral UART5 base pointer */
#define UART5_BASE_PTR ((UART_MemMapPtr)0x400EB000u)
/* ----------------------------------------------------------------------------
-- UART - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
* @{
*/
/* UART - Register instance definitions */
/* UART0 */
#define UART0_BDH UART_BDH_REG(UART0_BASE_PTR)
#define UART0_BDL UART_BDL_REG(UART0_BASE_PTR)
#define UART0_C1 UART_C1_REG(UART0_BASE_PTR)
#define UART0_C2 UART_C2_REG(UART0_BASE_PTR)
#define UART0_S1 UART_S1_REG(UART0_BASE_PTR)
#define UART0_S2 UART_S2_REG(UART0_BASE_PTR)
#define UART0_C3 UART_C3_REG(UART0_BASE_PTR)
#define UART0_D UART_D_REG(UART0_BASE_PTR)
#define UART0_MA1 UART_MA1_REG(UART0_BASE_PTR)
#define UART0_MA2 UART_MA2_REG(UART0_BASE_PTR)
#define UART0_C4 UART_C4_REG(UART0_BASE_PTR)
#define UART0_C5 UART_C5_REG(UART0_BASE_PTR)
#define UART0_ED UART_ED_REG(UART0_BASE_PTR)
#define UART0_MODEM UART_MODEM_REG(UART0_BASE_PTR)
#define UART0_IR UART_IR_REG(UART0_BASE_PTR)
#define UART0_PFIFO UART_PFIFO_REG(UART0_BASE_PTR)
#define UART0_CFIFO UART_CFIFO_REG(UART0_BASE_PTR)
#define UART0_SFIFO UART_SFIFO_REG(UART0_BASE_PTR)
#define UART0_TWFIFO UART_TWFIFO_REG(UART0_BASE_PTR)
#define UART0_TCFIFO UART_TCFIFO_REG(UART0_BASE_PTR)
#define UART0_RWFIFO UART_RWFIFO_REG(UART0_BASE_PTR)
#define UART0_RCFIFO UART_RCFIFO_REG(UART0_BASE_PTR)
#define UART0_C7816 UART_C7816_REG(UART0_BASE_PTR)
#define UART0_IE7816 UART_IE7816_REG(UART0_BASE_PTR)
#define UART0_IS7816 UART_IS7816_REG(UART0_BASE_PTR)
#define UART0_WP7816T0 UART_WP7816_T_TYPE0_REG(UART0_BASE_PTR)
#define UART0_WP7816T1 UART_WP7816_T_TYPE1_REG(UART0_BASE_PTR)
#define UART0_WN7816 UART_WN7816_REG(UART0_BASE_PTR)
#define UART0_WF7816 UART_WF7816_REG(UART0_BASE_PTR)
#define UART0_ET7816 UART_ET7816_REG(UART0_BASE_PTR)
#define UART0_TL7816 UART_TL7816_REG(UART0_BASE_PTR)
/* UART1 */
#define UART1_BDH UART_BDH_REG(UART1_BASE_PTR)
#define UART1_BDL UART_BDL_REG(UART1_BASE_PTR)
#define UART1_C1 UART_C1_REG(UART1_BASE_PTR)
#define UART1_C2 UART_C2_REG(UART1_BASE_PTR)
#define UART1_S1 UART_S1_REG(UART1_BASE_PTR)
#define UART1_S2 UART_S2_REG(UART1_BASE_PTR)
#define UART1_C3 UART_C3_REG(UART1_BASE_PTR)
#define UART1_D UART_D_REG(UART1_BASE_PTR)
#define UART1_MA1 UART_MA1_REG(UART1_BASE_PTR)
#define UART1_MA2 UART_MA2_REG(UART1_BASE_PTR)
#define UART1_C4 UART_C4_REG(UART1_BASE_PTR)
#define UART1_C5 UART_C5_REG(UART1_BASE_PTR)
#define UART1_ED UART_ED_REG(UART1_BASE_PTR)
#define UART1_MODEM UART_MODEM_REG(UART1_BASE_PTR)
#define UART1_IR UART_IR_REG(UART1_BASE_PTR)
#define UART1_PFIFO UART_PFIFO_REG(UART1_BASE_PTR)
#define UART1_CFIFO UART_CFIFO_REG(UART1_BASE_PTR)
#define UART1_SFIFO UART_SFIFO_REG(UART1_BASE_PTR)
#define UART1_TWFIFO UART_TWFIFO_REG(UART1_BASE_PTR)
#define UART1_TCFIFO UART_TCFIFO_REG(UART1_BASE_PTR)
#define UART1_RWFIFO UART_RWFIFO_REG(UART1_BASE_PTR)
#define UART1_RCFIFO UART_RCFIFO_REG(UART1_BASE_PTR)
/* UART2 */
#define UART2_BDH UART_BDH_REG(UART2_BASE_PTR)
#define UART2_BDL UART_BDL_REG(UART2_BASE_PTR)
#define UART2_C1 UART_C1_REG(UART2_BASE_PTR)
#define UART2_C2 UART_C2_REG(UART2_BASE_PTR)
#define UART2_S1 UART_S1_REG(UART2_BASE_PTR)
#define UART2_S2 UART_S2_REG(UART2_BASE_PTR)
#define UART2_C3 UART_C3_REG(UART2_BASE_PTR)
#define UART2_D UART_D_REG(UART2_BASE_PTR)
#define UART2_MA1 UART_MA1_REG(UART2_BASE_PTR)
#define UART2_MA2 UART_MA2_REG(UART2_BASE_PTR)
#define UART2_C4 UART_C4_REG(UART2_BASE_PTR)
#define UART2_C5 UART_C5_REG(UART2_BASE_PTR)
#define UART2_ED UART_ED_REG(UART2_BASE_PTR)
#define UART2_MODEM UART_MODEM_REG(UART2_BASE_PTR)
#define UART2_IR UART_IR_REG(UART2_BASE_PTR)
#define UART2_PFIFO UART_PFIFO_REG(UART2_BASE_PTR)
#define UART2_CFIFO UART_CFIFO_REG(UART2_BASE_PTR)
#define UART2_SFIFO UART_SFIFO_REG(UART2_BASE_PTR)
#define UART2_TWFIFO UART_TWFIFO_REG(UART2_BASE_PTR)
#define UART2_TCFIFO UART_TCFIFO_REG(UART2_BASE_PTR)
#define UART2_RWFIFO UART_RWFIFO_REG(UART2_BASE_PTR)
#define UART2_RCFIFO UART_RCFIFO_REG(UART2_BASE_PTR)
/* UART3 */
#define UART3_BDH UART_BDH_REG(UART3_BASE_PTR)
#define UART3_BDL UART_BDL_REG(UART3_BASE_PTR)
#define UART3_C1 UART_C1_REG(UART3_BASE_PTR)
#define UART3_C2 UART_C2_REG(UART3_BASE_PTR)
#define UART3_S1 UART_S1_REG(UART3_BASE_PTR)
#define UART3_S2 UART_S2_REG(UART3_BASE_PTR)
#define UART3_C3 UART_C3_REG(UART3_BASE_PTR)
#define UART3_D UART_D_REG(UART3_BASE_PTR)
#define UART3_MA1 UART_MA1_REG(UART3_BASE_PTR)
#define UART3_MA2 UART_MA2_REG(UART3_BASE_PTR)
#define UART3_C4 UART_C4_REG(UART3_BASE_PTR)
#define UART3_C5 UART_C5_REG(UART3_BASE_PTR)
#define UART3_ED UART_ED_REG(UART3_BASE_PTR)
#define UART3_MODEM UART_MODEM_REG(UART3_BASE_PTR)
#define UART3_IR UART_IR_REG(UART3_BASE_PTR)
#define UART3_PFIFO UART_PFIFO_REG(UART3_BASE_PTR)
#define UART3_CFIFO UART_CFIFO_REG(UART3_BASE_PTR)
#define UART3_SFIFO UART_SFIFO_REG(UART3_BASE_PTR)
#define UART3_TWFIFO UART_TWFIFO_REG(UART3_BASE_PTR)
#define UART3_TCFIFO UART_TCFIFO_REG(UART3_BASE_PTR)
#define UART3_RWFIFO UART_RWFIFO_REG(UART3_BASE_PTR)
#define UART3_RCFIFO UART_RCFIFO_REG(UART3_BASE_PTR)
/* UART4 */
#define UART4_BDH UART_BDH_REG(UART4_BASE_PTR)
#define UART4_BDL UART_BDL_REG(UART4_BASE_PTR)
#define UART4_C1 UART_C1_REG(UART4_BASE_PTR)
#define UART4_C2 UART_C2_REG(UART4_BASE_PTR)
#define UART4_S1 UART_S1_REG(UART4_BASE_PTR)
#define UART4_S2 UART_S2_REG(UART4_BASE_PTR)
#define UART4_C3 UART_C3_REG(UART4_BASE_PTR)
#define UART4_D UART_D_REG(UART4_BASE_PTR)
#define UART4_MA1 UART_MA1_REG(UART4_BASE_PTR)
#define UART4_MA2 UART_MA2_REG(UART4_BASE_PTR)
#define UART4_C4 UART_C4_REG(UART4_BASE_PTR)
#define UART4_C5 UART_C5_REG(UART4_BASE_PTR)
#define UART4_ED UART_ED_REG(UART4_BASE_PTR)
#define UART4_MODEM UART_MODEM_REG(UART4_BASE_PTR)
#define UART4_IR UART_IR_REG(UART4_BASE_PTR)
#define UART4_PFIFO UART_PFIFO_REG(UART4_BASE_PTR)
#define UART4_CFIFO UART_CFIFO_REG(UART4_BASE_PTR)
#define UART4_SFIFO UART_SFIFO_REG(UART4_BASE_PTR)
#define UART4_TWFIFO UART_TWFIFO_REG(UART4_BASE_PTR)
#define UART4_TCFIFO UART_TCFIFO_REG(UART4_BASE_PTR)
#define UART4_RWFIFO UART_RWFIFO_REG(UART4_BASE_PTR)
#define UART4_RCFIFO UART_RCFIFO_REG(UART4_BASE_PTR)
/* UART5 */
#define UART5_BDH UART_BDH_REG(UART5_BASE_PTR)
#define UART5_BDL UART_BDL_REG(UART5_BASE_PTR)
#define UART5_C1 UART_C1_REG(UART5_BASE_PTR)
#define UART5_C2 UART_C2_REG(UART5_BASE_PTR)
#define UART5_S1 UART_S1_REG(UART5_BASE_PTR)
#define UART5_S2 UART_S2_REG(UART5_BASE_PTR)
#define UART5_C3 UART_C3_REG(UART5_BASE_PTR)
#define UART5_D UART_D_REG(UART5_BASE_PTR)
#define UART5_MA1 UART_MA1_REG(UART5_BASE_PTR)
#define UART5_MA2 UART_MA2_REG(UART5_BASE_PTR)
#define UART5_C4 UART_C4_REG(UART5_BASE_PTR)
#define UART5_C5 UART_C5_REG(UART5_BASE_PTR)
#define UART5_ED UART_ED_REG(UART5_BASE_PTR)
#define UART5_MODEM UART_MODEM_REG(UART5_BASE_PTR)
#define UART5_IR UART_IR_REG(UART5_BASE_PTR)
#define UART5_PFIFO UART_PFIFO_REG(UART5_BASE_PTR)
#define UART5_CFIFO UART_CFIFO_REG(UART5_BASE_PTR)
#define UART5_SFIFO UART_SFIFO_REG(UART5_BASE_PTR)
#define UART5_TWFIFO UART_TWFIFO_REG(UART5_BASE_PTR)
#define UART5_TCFIFO UART_TCFIFO_REG(UART5_BASE_PTR)
#define UART5_RWFIFO UART_RWFIFO_REG(UART5_BASE_PTR)
#define UART5_RCFIFO UART_RCFIFO_REG(UART5_BASE_PTR)
/**
* @}
*/ /* end of group UART_Register_Accessor_Macros */
/**
* @}
*/ /* end of group UART_Peripheral */
/* ----------------------------------------------------------------------------
-- USB
---------------------------------------------------------------------------- */
/**
* @addtogroup USB_Peripheral USB
* @{
*/
/** USB - Peripheral register structure */
typedef struct USB_MemMap {
uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
uint8_t RESERVED_0[3];
uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
uint8_t RESERVED_1[3];
uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
uint8_t RESERVED_2[3];
uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
uint8_t RESERVED_3[3];
uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
uint8_t RESERVED_4[3];
uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
uint8_t RESERVED_5[3];
uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
uint8_t RESERVED_6[3];
uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
uint8_t RESERVED_7[99];
uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
uint8_t RESERVED_8[3];
uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
uint8_t RESERVED_9[3];
uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
uint8_t RESERVED_10[3];
uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
uint8_t RESERVED_11[3];
uint8_t STAT; /**< Status Register, offset: 0x90 */
uint8_t RESERVED_12[3];
uint8_t CTL; /**< Control Register, offset: 0x94 */
uint8_t RESERVED_13[3];
uint8_t ADDR; /**< Address Register, offset: 0x98 */
uint8_t RESERVED_14[3];
uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
uint8_t RESERVED_15[3];
uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
uint8_t RESERVED_16[3];
uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
uint8_t RESERVED_17[3];
uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
uint8_t RESERVED_18[3];
uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
uint8_t RESERVED_19[3];
uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
uint8_t RESERVED_20[3];
uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
uint8_t RESERVED_21[11];
struct { /* offset: 0xC0, array step: 0x4 */
uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_0[3];
} ENDPOINT[16];
uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
uint8_t RESERVED_22[3];
uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
uint8_t RESERVED_23[3];
uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
uint8_t RESERVED_24[3];
uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
} volatile *USB_MemMapPtr;
/* ----------------------------------------------------------------------------
-- USB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
* @{
*/
/* USB - Register accessors */
#define USB_PERID_REG(base) ((base)->PERID)
#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
#define USB_REV_REG(base) ((base)->REV)
#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
#define USB_OTGICR_REG(base) ((base)->OTGICR)
#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
#define USB_ISTAT_REG(base) ((base)->ISTAT)
#define USB_INTEN_REG(base) ((base)->INTEN)
#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
#define USB_ERREN_REG(base) ((base)->ERREN)
#define USB_STAT_REG(base) ((base)->STAT)
#define USB_CTL_REG(base) ((base)->CTL)
#define USB_ADDR_REG(base) ((base)->ADDR)
#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
#define USB_TOKEN_REG(base) ((base)->TOKEN)
#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
#define USB_CONTROL_REG(base) ((base)->CONTROL)
#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
/**
* @}
*/ /* end of group USB_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- USB Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup USB_Register_Masks USB Register Masks
* @{
*/
/* PERID Bit Fields */
#define USB_PERID_ID_MASK 0x3Fu
#define USB_PERID_ID_SHIFT 0
#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
/* IDCOMP Bit Fields */
#define USB_IDCOMP_NID_MASK 0x3Fu
#define USB_IDCOMP_NID_SHIFT 0
#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
/* REV Bit Fields */
#define USB_REV_REV_MASK 0xFFu
#define USB_REV_REV_SHIFT 0
#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
/* ADDINFO Bit Fields */
#define USB_ADDINFO_IEHOST_MASK 0x1u
#define USB_ADDINFO_IEHOST_SHIFT 0
#define USB_ADDINFO_IRQNUM_MASK 0xF8u
#define USB_ADDINFO_IRQNUM_SHIFT 3
#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
/* OTGISTAT Bit Fields */
#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
#define USB_OTGISTAT_ONEMSEC_SHIFT 6
#define USB_OTGISTAT_IDCHG_MASK 0x80u
#define USB_OTGISTAT_IDCHG_SHIFT 7
/* OTGICR Bit Fields */
#define USB_OTGICR_AVBUSEN_MASK 0x1u
#define USB_OTGICR_AVBUSEN_SHIFT 0
#define USB_OTGICR_BSESSEN_MASK 0x4u
#define USB_OTGICR_BSESSEN_SHIFT 2
#define USB_OTGICR_SESSVLDEN_MASK 0x8u
#define USB_OTGICR_SESSVLDEN_SHIFT 3
#define USB_OTGICR_LINESTATEEN_MASK 0x20u
#define USB_OTGICR_LINESTATEEN_SHIFT 5
#define USB_OTGICR_ONEMSECEN_MASK 0x40u
#define USB_OTGICR_ONEMSECEN_SHIFT 6
#define USB_OTGICR_IDEN_MASK 0x80u
#define USB_OTGICR_IDEN_SHIFT 7
/* OTGSTAT Bit Fields */
#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
#define USB_OTGSTAT_BSESSEND_MASK 0x4u
#define USB_OTGSTAT_BSESSEND_SHIFT 2
#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
#define USB_OTGSTAT_SESS_VLD_SHIFT 3
#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
#define USB_OTGSTAT_ID_MASK 0x80u
#define USB_OTGSTAT_ID_SHIFT 7
/* OTGCTL Bit Fields */
#define USB_OTGCTL_OTGEN_MASK 0x4u
#define USB_OTGCTL_OTGEN_SHIFT 2
#define USB_OTGCTL_DMLOW_MASK 0x10u
#define USB_OTGCTL_DMLOW_SHIFT 4
#define USB_OTGCTL_DPLOW_MASK 0x20u
#define USB_OTGCTL_DPLOW_SHIFT 5
#define USB_OTGCTL_DPHIGH_MASK 0x80u
#define USB_OTGCTL_DPHIGH_SHIFT 7
/* ISTAT Bit Fields */
#define USB_ISTAT_USBRST_MASK 0x1u
#define USB_ISTAT_USBRST_SHIFT 0
#define USB_ISTAT_ERROR_MASK 0x2u
#define USB_ISTAT_ERROR_SHIFT 1
#define USB_ISTAT_SOFTOK_MASK 0x4u
#define USB_ISTAT_SOFTOK_SHIFT 2
#define USB_ISTAT_TOKDNE_MASK 0x8u
#define USB_ISTAT_TOKDNE_SHIFT 3
#define USB_ISTAT_SLEEP_MASK 0x10u
#define USB_ISTAT_SLEEP_SHIFT 4
#define USB_ISTAT_RESUME_MASK 0x20u
#define USB_ISTAT_RESUME_SHIFT 5
#define USB_ISTAT_ATTACH_MASK 0x40u
#define USB_ISTAT_ATTACH_SHIFT 6
#define USB_ISTAT_STALL_MASK 0x80u
#define USB_ISTAT_STALL_SHIFT 7
/* INTEN Bit Fields */
#define USB_INTEN_USBRSTEN_MASK 0x1u
#define USB_INTEN_USBRSTEN_SHIFT 0
#define USB_INTEN_ERROREN_MASK 0x2u
#define USB_INTEN_ERROREN_SHIFT 1
#define USB_INTEN_SOFTOKEN_MASK 0x4u
#define USB_INTEN_SOFTOKEN_SHIFT 2
#define USB_INTEN_TOKDNEEN_MASK 0x8u
#define USB_INTEN_TOKDNEEN_SHIFT 3
#define USB_INTEN_SLEEPEN_MASK 0x10u
#define USB_INTEN_SLEEPEN_SHIFT 4
#define USB_INTEN_RESUMEEN_MASK 0x20u
#define USB_INTEN_RESUMEEN_SHIFT 5
#define USB_INTEN_ATTACHEN_MASK 0x40u
#define USB_INTEN_ATTACHEN_SHIFT 6
#define USB_INTEN_STALLEN_MASK 0x80u
#define USB_INTEN_STALLEN_SHIFT 7
/* ERRSTAT Bit Fields */
#define USB_ERRSTAT_PIDERR_MASK 0x1u
#define USB_ERRSTAT_PIDERR_SHIFT 0
#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
#define USB_ERRSTAT_CRC5EOF_SHIFT 1
#define USB_ERRSTAT_CRC16_MASK 0x4u
#define USB_ERRSTAT_CRC16_SHIFT 2
#define USB_ERRSTAT_DFN8_MASK 0x8u
#define USB_ERRSTAT_DFN8_SHIFT 3
#define USB_ERRSTAT_BTOERR_MASK 0x10u
#define USB_ERRSTAT_BTOERR_SHIFT 4
#define USB_ERRSTAT_DMAERR_MASK 0x20u
#define USB_ERRSTAT_DMAERR_SHIFT 5
#define USB_ERRSTAT_BTSERR_MASK 0x80u
#define USB_ERRSTAT_BTSERR_SHIFT 7
/* ERREN Bit Fields */
#define USB_ERREN_PIDERREN_MASK 0x1u
#define USB_ERREN_PIDERREN_SHIFT 0
#define USB_ERREN_CRC5EOFEN_MASK 0x2u
#define USB_ERREN_CRC5EOFEN_SHIFT 1
#define USB_ERREN_CRC16EN_MASK 0x4u
#define USB_ERREN_CRC16EN_SHIFT 2
#define USB_ERREN_DFN8EN_MASK 0x8u
#define USB_ERREN_DFN8EN_SHIFT 3
#define USB_ERREN_BTOERREN_MASK 0x10u
#define USB_ERREN_BTOERREN_SHIFT 4
#define USB_ERREN_DMAERREN_MASK 0x20u
#define USB_ERREN_DMAERREN_SHIFT 5
#define USB_ERREN_BTSERREN_MASK 0x80u
#define USB_ERREN_BTSERREN_SHIFT 7
/* STAT Bit Fields */
#define USB_STAT_ODD_MASK 0x4u
#define USB_STAT_ODD_SHIFT 2
#define USB_STAT_TX_MASK 0x8u
#define USB_STAT_TX_SHIFT 3
#define USB_STAT_ENDP_MASK 0xF0u
#define USB_STAT_ENDP_SHIFT 4
#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
/* CTL Bit Fields */
#define USB_CTL_USBENSOFEN_MASK 0x1u
#define USB_CTL_USBENSOFEN_SHIFT 0
#define USB_CTL_ODDRST_MASK 0x2u
#define USB_CTL_ODDRST_SHIFT 1
#define USB_CTL_RESUME_MASK 0x4u
#define USB_CTL_RESUME_SHIFT 2
#define USB_CTL_HOSTMODEEN_MASK 0x8u
#define USB_CTL_HOSTMODEEN_SHIFT 3
#define USB_CTL_RESET_MASK 0x10u
#define USB_CTL_RESET_SHIFT 4
#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
#define USB_CTL_SE0_MASK 0x40u
#define USB_CTL_SE0_SHIFT 6
#define USB_CTL_JSTATE_MASK 0x80u
#define USB_CTL_JSTATE_SHIFT 7
/* ADDR Bit Fields */
#define USB_ADDR_ADDR_MASK 0x7Fu
#define USB_ADDR_ADDR_SHIFT 0
#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
#define USB_ADDR_LSEN_MASK 0x80u
#define USB_ADDR_LSEN_SHIFT 7
/* BDTPAGE1 Bit Fields */
#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
#define USB_BDTPAGE1_BDTBA_SHIFT 1
#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
/* FRMNUML Bit Fields */
#define USB_FRMNUML_FRM_MASK 0xFFu
#define USB_FRMNUML_FRM_SHIFT 0
#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
/* FRMNUMH Bit Fields */
#define USB_FRMNUMH_FRM_MASK 0x7u
#define USB_FRMNUMH_FRM_SHIFT 0
#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
/* TOKEN Bit Fields */
#define USB_TOKEN_TOKENENDPT_MASK 0xFu
#define USB_TOKEN_TOKENENDPT_SHIFT 0
#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
#define USB_TOKEN_TOKENPID_MASK 0xF0u
#define USB_TOKEN_TOKENPID_SHIFT 4
#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
/* SOFTHLD Bit Fields */
#define USB_SOFTHLD_CNT_MASK 0xFFu
#define USB_SOFTHLD_CNT_SHIFT 0
#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
/* BDTPAGE2 Bit Fields */
#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
#define USB_BDTPAGE2_BDTBA_SHIFT 0
#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
/* BDTPAGE3 Bit Fields */
#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
#define USB_BDTPAGE3_BDTBA_SHIFT 0
#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
/* ENDPT Bit Fields */
#define USB_ENDPT_EPHSHK_MASK 0x1u
#define USB_ENDPT_EPHSHK_SHIFT 0
#define USB_ENDPT_EPSTALL_MASK 0x2u
#define USB_ENDPT_EPSTALL_SHIFT 1
#define USB_ENDPT_EPTXEN_MASK 0x4u
#define USB_ENDPT_EPTXEN_SHIFT 2
#define USB_ENDPT_EPRXEN_MASK 0x8u
#define USB_ENDPT_EPRXEN_SHIFT 3
#define USB_ENDPT_EPCTLDIS_MASK 0x10u
#define USB_ENDPT_EPCTLDIS_SHIFT 4
#define USB_ENDPT_RETRYDIS_MASK 0x40u
#define USB_ENDPT_RETRYDIS_SHIFT 6
#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
#define USB_ENDPT_HOSTWOHUB_SHIFT 7
/* USBCTRL Bit Fields */
#define USB_USBCTRL_PDE_MASK 0x40u
#define USB_USBCTRL_PDE_SHIFT 6
#define USB_USBCTRL_SUSP_MASK 0x80u
#define USB_USBCTRL_SUSP_SHIFT 7
/* OBSERVE Bit Fields */
#define USB_OBSERVE_DMPD_MASK 0x10u
#define USB_OBSERVE_DMPD_SHIFT 4
#define USB_OBSERVE_DPPD_MASK 0x40u
#define USB_OBSERVE_DPPD_SHIFT 6
#define USB_OBSERVE_DPPU_MASK 0x80u
#define USB_OBSERVE_DPPU_SHIFT 7
/* CONTROL Bit Fields */
#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
/* USBTRC0 Bit Fields */
#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
#define USB_USBTRC0_SYNC_DET_MASK 0x2u
#define USB_USBTRC0_SYNC_DET_SHIFT 1
#define USB_USBTRC0_USBRESMEN_MASK 0x20u
#define USB_USBTRC0_USBRESMEN_SHIFT 5
#define USB_USBTRC0_USBRESET_MASK 0x80u
#define USB_USBTRC0_USBRESET_SHIFT 7
/**
* @}
*/ /* end of group USB_Register_Masks */
/* USB - Peripheral instance base addresses */
/** Peripheral USB0 base pointer */
#define USB0_BASE_PTR ((USB_MemMapPtr)0x40072000u)
/* ----------------------------------------------------------------------------
-- USB - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
* @{
*/
/* USB - Register instance definitions */
/* USB0 */
#define USB0_PERID USB_PERID_REG(USB0_BASE_PTR)
#define USB0_IDCOMP USB_IDCOMP_REG(USB0_BASE_PTR)
#define USB0_REV USB_REV_REG(USB0_BASE_PTR)
#define USB0_ADDINFO USB_ADDINFO_REG(USB0_BASE_PTR)
#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0_BASE_PTR)
#define USB0_OTGICR USB_OTGICR_REG(USB0_BASE_PTR)
#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0_BASE_PTR)
#define USB0_OTGCTL USB_OTGCTL_REG(USB0_BASE_PTR)
#define USB0_ISTAT USB_ISTAT_REG(USB0_BASE_PTR)
#define USB0_INTEN USB_INTEN_REG(USB0_BASE_PTR)
#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0_BASE_PTR)
#define USB0_ERREN USB_ERREN_REG(USB0_BASE_PTR)
#define USB0_STAT USB_STAT_REG(USB0_BASE_PTR)
#define USB0_CTL USB_CTL_REG(USB0_BASE_PTR)
#define USB0_ADDR USB_ADDR_REG(USB0_BASE_PTR)
#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0_BASE_PTR)
#define USB0_FRMNUML USB_FRMNUML_REG(USB0_BASE_PTR)
#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0_BASE_PTR)
#define USB0_TOKEN USB_TOKEN_REG(USB0_BASE_PTR)
#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0_BASE_PTR)
#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0_BASE_PTR)
#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0_BASE_PTR)
#define USB0_ENDPT0 USB_ENDPT_REG(USB0_BASE_PTR,0)
#define USB0_ENDPT1 USB_ENDPT_REG(USB0_BASE_PTR,1)
#define USB0_ENDPT2 USB_ENDPT_REG(USB0_BASE_PTR,2)
#define USB0_ENDPT3 USB_ENDPT_REG(USB0_BASE_PTR,3)
#define USB0_ENDPT4 USB_ENDPT_REG(USB0_BASE_PTR,4)
#define USB0_ENDPT5 USB_ENDPT_REG(USB0_BASE_PTR,5)
#define USB0_ENDPT6 USB_ENDPT_REG(USB0_BASE_PTR,6)
#define USB0_ENDPT7 USB_ENDPT_REG(USB0_BASE_PTR,7)
#define USB0_ENDPT8 USB_ENDPT_REG(USB0_BASE_PTR,8)
#define USB0_ENDPT9 USB_ENDPT_REG(USB0_BASE_PTR,9)
#define USB0_ENDPT10 USB_ENDPT_REG(USB0_BASE_PTR,10)
#define USB0_ENDPT11 USB_ENDPT_REG(USB0_BASE_PTR,11)
#define USB0_ENDPT12 USB_ENDPT_REG(USB0_BASE_PTR,12)
#define USB0_ENDPT13 USB_ENDPT_REG(USB0_BASE_PTR,13)
#define USB0_ENDPT14 USB_ENDPT_REG(USB0_BASE_PTR,14)
#define USB0_ENDPT15 USB_ENDPT_REG(USB0_BASE_PTR,15)
#define USB0_USBCTRL USB_USBCTRL_REG(USB0_BASE_PTR)
#define USB0_OBSERVE USB_OBSERVE_REG(USB0_BASE_PTR)
#define USB0_CONTROL USB_CONTROL_REG(USB0_BASE_PTR)
#define USB0_USBTRC0 USB_USBTRC0_REG(USB0_BASE_PTR)
/* USB - Register array accessors */
#define USB0_ENDPT(index) USB_ENDPT_REG(USB0_BASE_PTR,index)
/**
* @}
*/ /* end of group USB_Register_Accessor_Macros */
/**
* @}
*/ /* end of group USB_Peripheral */
/* ----------------------------------------------------------------------------
-- USBDCD
---------------------------------------------------------------------------- */
/**
* @addtogroup USBDCD_Peripheral USBDCD
* @{
*/
/** USBDCD - Peripheral register structure */
typedef struct USBDCD_MemMap {
uint32_t CONTROL; /**< Control Register, offset: 0x0 */
uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
uint32_t STATUS; /**< Status Register, offset: 0x8 */
uint8_t RESERVED_0[4];
uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
uint32_t TIMER1; /**< , offset: 0x14 */
uint32_t TIMER2; /**< , offset: 0x18 */
} volatile *USBDCD_MemMapPtr;
/* ----------------------------------------------------------------------------
-- USBDCD - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
* @{
*/
/* USBDCD - Register accessors */
#define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
#define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
#define USBDCD_STATUS_REG(base) ((base)->STATUS)
#define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
#define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
#define USBDCD_TIMER2_REG(base) ((base)->TIMER2)
/**
* @}
*/ /* end of group USBDCD_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- USBDCD Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup USBDCD_Register_Masks USBDCD Register Masks
* @{
*/
/* CONTROL Bit Fields */
#define USBDCD_CONTROL_IACK_MASK 0x1u
#define USBDCD_CONTROL_IACK_SHIFT 0
#define USBDCD_CONTROL_IF_MASK 0x100u
#define USBDCD_CONTROL_IF_SHIFT 8
#define USBDCD_CONTROL_IE_MASK 0x10000u
#define USBDCD_CONTROL_IE_SHIFT 16
#define USBDCD_CONTROL_START_MASK 0x1000000u
#define USBDCD_CONTROL_START_SHIFT 24
#define USBDCD_CONTROL_SR_MASK 0x2000000u
#define USBDCD_CONTROL_SR_SHIFT 25
/* CLOCK Bit Fields */
#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
/* STATUS Bit Fields */
#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
#define USBDCD_STATUS_SEQ_RES_SHIFT 16
#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
#define USBDCD_STATUS_ERR_MASK 0x100000u
#define USBDCD_STATUS_ERR_SHIFT 20
#define USBDCD_STATUS_TO_MASK 0x200000u
#define USBDCD_STATUS_TO_SHIFT 21
#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
#define USBDCD_STATUS_ACTIVE_SHIFT 22
/* TIMER0 Bit Fields */
#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
#define USBDCD_TIMER0_TUNITCON_SHIFT 0
#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
/* TIMER1 Bit Fields */
#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
/* TIMER2 Bit Fields */
#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
#define USBDCD_TIMER2_CHECK_DM_SHIFT 0
#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
/**
* @}
*/ /* end of group USBDCD_Register_Masks */
/* USBDCD - Peripheral instance base addresses */
/** Peripheral USBDCD base pointer */
#define USBDCD_BASE_PTR ((USBDCD_MemMapPtr)0x40035000u)
/* ----------------------------------------------------------------------------
-- USBDCD - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
* @{
*/
/* USBDCD - Register instance definitions */
/* USBDCD */
#define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD_BASE_PTR)
#define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD_BASE_PTR)
#define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD_BASE_PTR)
#define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD_BASE_PTR)
#define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD_BASE_PTR)
#define USBDCD_TIMER2 USBDCD_TIMER2_REG(USBDCD_BASE_PTR)
/**
* @}
*/ /* end of group USBDCD_Register_Accessor_Macros */
/**
* @}
*/ /* end of group USBDCD_Peripheral */
/* ----------------------------------------------------------------------------
-- VREF
---------------------------------------------------------------------------- */
/**
* @addtogroup VREF_Peripheral VREF
* @{
*/
/** VREF - Peripheral register structure */
typedef struct VREF_MemMap {
uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
} volatile *VREF_MemMapPtr;
/* ----------------------------------------------------------------------------
-- VREF - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
* @{
*/
/* VREF - Register accessors */
#define VREF_TRM_REG(base) ((base)->TRM)
#define VREF_SC_REG(base) ((base)->SC)
/**
* @}
*/ /* end of group VREF_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- VREF Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup VREF_Register_Masks VREF Register Masks
* @{
*/
/* TRM Bit Fields */
#define VREF_TRM_TRIM_MASK 0x3Fu
#define VREF_TRM_TRIM_SHIFT 0
#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
/* SC Bit Fields */
#define VREF_SC_MODE_LV_MASK 0x3u
#define VREF_SC_MODE_LV_SHIFT 0
#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
#define VREF_SC_VREFST_MASK 0x4u
#define VREF_SC_VREFST_SHIFT 2
#define VREF_SC_REGEN_MASK 0x40u
#define VREF_SC_REGEN_SHIFT 6
#define VREF_SC_VREFEN_MASK 0x80u
#define VREF_SC_VREFEN_SHIFT 7
/**
* @}
*/ /* end of group VREF_Register_Masks */
/* VREF - Peripheral instance base addresses */
/** Peripheral VREF base pointer */
#define VREF_BASE_PTR ((VREF_MemMapPtr)0x40074000u)
/* ----------------------------------------------------------------------------
-- VREF - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
* @{
*/
/* VREF - Register instance definitions */
/* VREF */
#define VREF_TRM VREF_TRM_REG(VREF_BASE_PTR)
#define VREF_SC VREF_SC_REG(VREF_BASE_PTR)
/**
* @}
*/ /* end of group VREF_Register_Accessor_Macros */
/**
* @}
*/ /* end of group VREF_Peripheral */
/* ----------------------------------------------------------------------------
-- WDOG
---------------------------------------------------------------------------- */
/**
* @addtogroup WDOG_Peripheral WDOG
* @{
*/
/** WDOG - Peripheral register structure */
typedef struct WDOG_MemMap {
uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
} volatile *WDOG_MemMapPtr;
/* ----------------------------------------------------------------------------
-- WDOG - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
* @{
*/
/* WDOG - Register accessors */
#define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
#define WDOG_WINH_REG(base) ((base)->WINH)
#define WDOG_WINL_REG(base) ((base)->WINL)
#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
#define WDOG_PRESC_REG(base) ((base)->PRESC)
/**
* @}
*/ /* end of group WDOG_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
---------------------------------------------------------------------------- */
/**
* @addtogroup WDOG_Register_Masks WDOG Register Masks
* @{
*/
/* STCTRLH Bit Fields */
#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
#define WDOG_STCTRLH_WDOGEN_SHIFT 0
#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
#define WDOG_STCTRLH_CLKSRC_SHIFT 1
#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
#define WDOG_STCTRLH_WINEN_MASK 0x8u
#define WDOG_STCTRLH_WINEN_SHIFT 3
#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
#define WDOG_STCTRLH_DBGEN_MASK 0x20u
#define WDOG_STCTRLH_DBGEN_SHIFT 5
#define WDOG_STCTRLH_STOPEN_MASK 0x40u
#define WDOG_STCTRLH_STOPEN_SHIFT 6
#define WDOG_STCTRLH_WAITEN_MASK 0x80u
#define WDOG_STCTRLH_WAITEN_SHIFT 7
#define WDOG_STCTRLH_STNDBYEN_MASK 0x100u
#define WDOG_STCTRLH_STNDBYEN_SHIFT 8
#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
#define WDOG_STCTRLH_TESTSEL_SHIFT 11
#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
#define WDOG_STCTRLH_BYTESEL_SHIFT 12
#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
/* STCTRLL Bit Fields */
#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
#define WDOG_STCTRLL_INTFLG_SHIFT 15
/* TOVALH Bit Fields */
#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
/* TOVALL Bit Fields */
#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
#define WDOG_TOVALL_TOVALLOW_SHIFT 0
#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
/* WINH Bit Fields */
#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
#define WDOG_WINH_WINHIGH_SHIFT 0
#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
/* WINL Bit Fields */
#define WDOG_WINL_WINLOW_MASK 0xFFFFu
#define WDOG_WINL_WINLOW_SHIFT 0
#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
/* REFRESH Bit Fields */
#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
/* UNLOCK Bit Fields */
#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
/* TMROUTH Bit Fields */
#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
/* TMROUTL Bit Fields */
#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
/* RSTCNT Bit Fields */
#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
#define WDOG_RSTCNT_RSTCNT_SHIFT 0
#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
/* PRESC Bit Fields */
#define WDOG_PRESC_PRESCVAL_MASK 0x700u
#define WDOG_PRESC_PRESCVAL_SHIFT 8
#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
/**
* @}
*/ /* end of group WDOG_Register_Masks */
/* WDOG - Peripheral instance base addresses */
/** Peripheral WDOG base pointer */
#define WDOG_BASE_PTR ((WDOG_MemMapPtr)0x40052000u)
/* ----------------------------------------------------------------------------
-- WDOG - Register accessor macros
---------------------------------------------------------------------------- */
/**
* @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
* @{
*/
/* WDOG - Register instance definitions */
/* WDOG */
#define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG_BASE_PTR)
#define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG_BASE_PTR)
#define WDOG_TOVALH WDOG_TOVALH_REG(WDOG_BASE_PTR)
#define WDOG_TOVALL WDOG_TOVALL_REG(WDOG_BASE_PTR)
#define WDOG_WINH WDOG_WINH_REG(WDOG_BASE_PTR)
#define WDOG_WINL WDOG_WINL_REG(WDOG_BASE_PTR)
#define WDOG_REFRESH WDOG_REFRESH_REG(WDOG_BASE_PTR)
#define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG_BASE_PTR)
#define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG_BASE_PTR)
#define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG_BASE_PTR)
#define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG_BASE_PTR)
#define WDOG_PRESC WDOG_PRESC_REG(WDOG_BASE_PTR)
/**
* @}
*/ /* end of group WDOG_Register_Accessor_Macros */
/**
* @}
*/ /* end of group WDOG_Peripheral */
/*
** End of section using anonymous unions
*/
#if defined(__CWCC__)
#pragma pop
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=default
#else
#error Not supported compiler type
#endif
/**
* @}
*/ /* end of group Peripheral_defines */
/* ----------------------------------------------------------------------------
-- Backward Compatibility
---------------------------------------------------------------------------- */
/**
* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
* @{
*/
#define FB_CSCR_EXALE_MASK FB_CSCR_EXTS_MASK
#define FB_CSCR_EXALE_SHIFT FB_CSCR_EXTS_SHIFT
#define RTC_CCR_REG This_symb_has_been_deprecated
#define RTC_CCR_CONFIG_MASK This_symb_has_been_deprecated
#define RTC_CCR_CONFIG_SHIFT This_symb_has_been_deprecated
#define RTC_CCR_CONFIG This_symb_has_been_deprecated
#define RTC_WAR_CCRW_MASK This_symb_has_been_deprecated
#define RTC_WAR_CCRW_SHIFT This_symb_has_been_deprecated
#define RTC_RAR_CCRR_MASK This_symb_has_been_deprecated
#define RTC_RAR_CCRR_SHIFT This_symb_has_been_deprecated
#define RTC_CCR This_symb_has_been_deprecated
#define SIM_FCFG1_FSIZE_MASK This_symb_has_been_deprecated
#define SIM_FCFG1_FSIZE_SHIFT This_symb_has_been_deprecated
#define SIM_FCFG1_FSIZE This_symb_has_been_deprecated
#define I2S_CR_SSIEN_MASK I2S_CR_I2SEN_MASK
#define I2S_CR_SSIEN_SHIFT I2S_CR_I2SEN_SHIFT
#define SDHC_VENDOR_VOLTSEL_MASK This_symb_has_been_deprecated
#define SDHC_VENDOR_VOLTSEL_SHIFT This_symb_has_been_deprecated
#define INT_Reserved4 INT_Mem_Manage_Fault
#define TSI_CNTR1_CNTN_MASK TSI_CNTR1_CTN1_MASK
#define TSI_CNTR1_CNTN_SHIFT TSI_CNTR1_CTN1_SHIFT
#define TSI_CNTR1_CNTN(x) TSI_CNTR1_CTN1(x)
#define TSI_CNTR1_CNTN1_MASK TSI_CNTR1_CTN_MASK
#define TSI_CNTR1_CNTN1_SHIFT TSI_CNTR1_CTN_SHIFT
#define TSI_CNTR1_CNTN1(x) TSI_CNTR1_CTN(x)
#define TSI_CNTR3_CNTN_MASK TSI_CNTR3_CTN1_MASK
#define TSI_CNTR3_CNTN_SHIFT TSI_CNTR3_CTN1_SHIFT
#define TSI_CNTR3_CNTN(x) TSI_CNTR3_CTN1(x)
#define TSI_CNTR3_CNTN1_MASK TSI_CNTR3_CTN_MASK
#define TSI_CNTR3_CNTN1_SHIFT TSI_CNTR3_CTN_SHIFT
#define TSI_CNTR3_CNTN1(x) TSI_CNTR3_CTN(x)
#define TSI_CNTR5_CNTN_MASK TSI_CNTR5_CTN1_MASK
#define TSI_CNTR5_CNTN_SHIFT TSI_CNTR5_CTN1_SHIFT
#define TSI_CNTR5_CNTN(x) TSI_CNTR5_CTN1(x)
#define TSI_CNTR5_CNTN1_MASK TSI_CNTR5_CTN_MASK
#define TSI_CNTR5_CNTN1_SHIFT TSI_CNTR5_CTN_SHIFT
#define TSI_CNTR5_CNTN1(x) TSI_CNTR5_CTN(x)
#define TSI_CNTR7_CNTN_MASK TSI_CNTR7_CTN1_MASK
#define TSI_CNTR7_CNTN_SHIFT TSI_CNTR7_CTN1_SHIFT
#define TSI_CNTR7_CNTN(x) TSI_CNTR7_CTN1(x)
#define TSI_CNTR7_CNTN1_MASK TSI_CNTR7_CTN_MASK
#define TSI_CNTR7_CNTN1_SHIFT TSI_CNTR7_CTN_SHIFT
#define TSI_CNTR7_CNTN1(x) TSI_CNTR7_CTN(x)
#define TSI_CNTR9_CNTN_MASK TSI_CNTR9_CTN1_MASK
#define TSI_CNTR9_CNTN_SHIFT TSI_CNTR9_CTN1_SHIFT
#define TSI_CNTR9_CNTN(x) TSI_CNTR9_CTN1(x)
#define TSI_CNTR9_CNTN1_MASK TSI_CNTR9_CTN_MASK
#define TSI_CNTR9_CNTN1_SHIFT TSI_CNTR9_CTN_SHIFT
#define TSI_CNTR9_CNTN1(x) TSI_CNTR9_CTN(x)
#define TSI_CNTR11_CNTN_MASK TSI_CNTR11_CTN1_MASK
#define TSI_CNTR11_CNTN_SHIFT TSI_CNTR11_CTN1_SHIFT
#define TSI_CNTR11_CNTN(x) TSI_CNTR11_CTN1(x)
#define TSI_CNTR11_CNTN1_MASK TSI_CNTR11_CTN_MASK
#define TSI_CNTR11_CNTN1_SHIFT TSI_CNTR11_CTN_SHIFT
#define TSI_CNTR11_CNTN1(x) TSI_CNTR11_CTN(x)
#define TSI_CNTR13_CNTN_MASK TSI_CNTR13_CTN1_MASK
#define TSI_CNTR13_CNTN_SHIFT TSI_CNTR13_CTN1_SHIFT
#define TSI_CNTR13_CNTN(x) TSI_CNTR13_CTN1(x)
#define TSI_CNTR13_CNTN1_MASK TSI_CNTR13_CTN_MASK
#define TSI_CNTR13_CNTN1_SHIFT TSI_CNTR13_CTN_SHIFT
#define TSI_CNTR13_CNTN1(x) TSI_CNTR13_CTN(x)
#define TSI_CNTR15_CNTN_MASK TSI_CNTR15_CTN1_MASK
#define TSI_CNTR15_CNTN_SHIFT TSI_CNTR15_CTN1_SHIFT
#define TSI_CNTR15_CNTN(x) TSI_CNTR15_CTN1(x)
#define TSI_CNTR15_CNTN1_MASK TSI_CNTR15_CTN_MASK
#define TSI_CNTR15_CNTN1_SHIFT TSI_CNTR15_CTN_SHIFT
#define TSI_CNTR15_CNTN1(x) TSI_CNTR15_CTN(x)
/**
* @}
*/ /* end of group Backward_Compatibility_Symbols */
#else /* #if !defined(MCU_MK20DZ10) */
/* There is already included the same memory map. Check if it is the same version */
#if (MCU_MEM_MAP_VERSION != 0x0101u)
#if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
#warning There are included two different versions of memory maps. Please check possible differences.
#endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
#endif /* (MCU_MEM_MAP_VERSION != 0x0101u) */
#endif /* #if !defined(MCU_MK20DZ10) */
/* MK20DZ10.h, eof. */
| 56.043126 | 178 | 0.527487 |
310bd1bbc2e8255cada7e6434d6c3d34c10f66a3 | 4,081 | h | C | RemoteJobManager.h | fmckenna/EE-UQ | a1fe96fd000aec933430bda5829c82b5743338c3 | [
"BSD-2-Clause"
] | 1 | 2019-04-30T19:38:17.000Z | 2019-04-30T19:38:17.000Z | RemoteJobManager.h | s-m-amin-ghasemi/EE-UQ | 7eb42d09b59b42fd1256c6d8693cfe46e0b8034b | [
"BSD-2-Clause"
] | 2 | 2018-09-11T01:32:27.000Z | 2018-09-11T23:08:06.000Z | RemoteJobManager.h | s-m-amin-ghasemi/EE-UQ | 7eb42d09b59b42fd1256c6d8693cfe46e0b8034b | [
"BSD-2-Clause"
] | 6 | 2018-05-14T21:45:24.000Z | 2018-10-04T18:13:42.000Z | #ifndef REMOTEJOBMANAGER_H
#define REMOTEJOBMANAGER_H
/* *****************************************************************************
Copyright (c) 2016-2017, The Regents of the University of California (Regents).
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of the FreeBSD Project.
REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED HEREUNDER IS
PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT,
UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*************************************************************************** */
// Written: fmckenna
// Purpose: a widget for managing submiited jobs by uqFEM tool
// - allow for refresh of status, deletion of submitted jobs, and download of results from finished job
#include <QWidget>
#include <QString>
#include <QJsonObject>
#include <QStringList>
#include <QString>
class MainWindow;
//#include <AgaveCurl.h>
class MainWindow;
class QTableWidget;
class QPushButton;
class RemoteService;
class RemoteJobManager : public QWidget
{
Q_OBJECT
public:
explicit RemoteJobManager(RemoteService *theInterface, QWidget *parent = nullptr);
bool addJob(QString &jobID);
void clearTable(void);
signals:
void statusMessage(QString);
void errorMessage(QString);
void getJobsList(QString);
void getJobStatus(QString);
void getJobDetails(QString);
void deleteJob(QString, QStringList);
void downloadFiles(QStringList, QStringList);
void processResults(QString, QString, QString);
void loadFile(QString);
// void deleteDirectory(QString);
// void downloadFile(QString);
public slots:
void updateJobTable(QString);
void jobsListReturn(QJsonObject);
void jobStatusReturn(QString);
void deleteJobReturn(bool);
void getJobDetailsReturn(QJsonObject);
// void deleteDirectoryReturn(bool);
// void jobDetailsReturn(QJsonObject);
void downloadFilesReturn(bool);
public slots:
void bringUpJobActionMenu(int row, int col);
void updateJobStatus(void);
void deleteJob(void);
void deleteJobAndData(void);
void getJobData(void);
private:
QString inputDirectory;
// AgaveCurl *theInterface;
QJsonObject jobs;
QTableWidget *jobsTable;
QStringList headers;
int triggeredRow;
QString htmlInputDirectory;
QPushButton *pushButton;
QString jobIDRequest;
int getJobDetailsRequest;
QString name1;
QString name2;
QString name3;
MainWindow *theMainWindow;
};
#endif // REMOTEJOBMANAGER_H
| 32.648 | 104 | 0.7432 |
640cb45afd56c41e0f089707786cb91543c5730b | 586 | h | C | JCommon/JRender/JSDL/JTextSDL.h | jimmythepage/JEngine | aec32fd2a3be9910f7f75511ba90f0d92fbd82c6 | [
"MIT"
] | null | null | null | JCommon/JRender/JSDL/JTextSDL.h | jimmythepage/JEngine | aec32fd2a3be9910f7f75511ba90f0d92fbd82c6 | [
"MIT"
] | 5 | 2020-05-08T13:41:03.000Z | 2020-05-10T11:06:23.000Z | JCommon/JRender/JSDL/JTextSDL.h | jimmythepage/JTPE | b86f5bbd4bbe3a5d543f1707c9b49cecc4484b05 | [
"MIT"
] | null | null | null | #ifndef JTEXTSDL
#define JTEXTSDL
struct FC_Font;
namespace J
{
namespace RENDER
{
class JTextSDL : public ::J::RENDER::JRenderable
{
public:
JTextSDL();
~JTextSDL();
virtual void Init(const std::string fontpath, const std::string name, JRenderableProperties properties);
virtual void Init(const std::string name);
virtual void Clear();
virtual void Update();
virtual void Activate();
virtual void Deactivate();
void SetText(std::string text);
protected:
std::string mText;
FC_Font * mFont;
SDL_Renderer* mRenderer;
};
}
}
#endif
| 17.757576 | 107 | 0.686007 |
9689c9584d73a79f6a80800feaded8549a28eee5 | 4,566 | h | C | MSCL/source/mscl/MicroStrain/ResponseCollector.h | vibhoraggarwal/MSCL | 9965f2b6309b5f497e765c8adb3ff317e517ea6c | [
"BSL-1.0",
"OpenSSL",
"MIT"
] | null | null | null | MSCL/source/mscl/MicroStrain/ResponseCollector.h | vibhoraggarwal/MSCL | 9965f2b6309b5f497e765c8adb3ff317e517ea6c | [
"BSL-1.0",
"OpenSSL",
"MIT"
] | 1 | 2019-09-18T07:55:46.000Z | 2021-06-22T07:55:14.000Z | MSCL/source/mscl/MicroStrain/ResponseCollector.h | vibhoraggarwal/MSCL | 9965f2b6309b5f497e765c8adb3ff317e517ea6c | [
"BSL-1.0",
"OpenSSL",
"MIT"
] | null | null | null | /*******************************************************************************
Copyright(c) 2015-2019 LORD Corporation. All rights reserved.
MIT Licensed. See the included LICENSE.txt for a copy of the full MIT License.
*******************************************************************************/
#pragma once
#include <memory>
#include <mutex>
#include <vector>
namespace mscl
{
class Connection;
class DataBuffer;
class WirelessPacket;
class MipDataField;
class ResponsePattern;
struct ResponseInfo
{
ResponsePattern* pattern;
std::size_t minBytePosition;
ResponseInfo(ResponsePattern* responsePattern, std::size_t minBytePos):
pattern(responsePattern),
minBytePosition(minBytePos)
{ }
};
//Class: ResponseCollector
// Stores all the expected command responses
class ResponseCollector
{
public:
//Default Constructor: ResponseCollector
// Creates a ResponseCollector object
ResponseCollector();
private:
ResponseCollector(const ResponseCollector&); //copy constructor disabled
ResponseCollector& operator=(const ResponseCollector&); //disable assignment operator
//std::shared_ptr<ResponseCollector> operator=(const ResponseCollector&); //assignement operator disabled
private:
//Variable: m_expectedResponses
// Holds the response patterns that, if matched, belong to this collector
std::vector<ResponseInfo> m_expectedResponses;
//Variable: m_responseMutex
// A mutex used for thread safety when accessing/modifying the m_expectedResponses vector
std::mutex m_responseMutex;
//Variable: m_connection
// The <Connection> pointer to use for retrieving byte information.
Connection* m_connection;
public:
//Function: setConnection
// Sets the connection points to use for retrieving byte information.
//
//Parameters:
// connection - The <Connection> pointer to use for retrieving byte info.
void setConnection(Connection* connection);
//Function: registerResponse
// Registers a <ResponsePattern> with this collector
//
//Parameters:
// response - The <ResponsePattern> to register
void registerResponse(ResponsePattern* response);
//Function: unregisterResponse
// Unregisters a <ResponsePattern> that is within this collector
//
//Parameters:
// response - A pointer to the <ResponsePattern> to unregister
void unregisterResponse(ResponsePattern* response);
//Function: waitingForResponse
// Gets whether or not this response collector currently has any response patterns to match
//
//Returns:
// true if the response collector has any response patterns to match, false otherwise
bool waitingForResponse();
void adjustResponsesMinBytePos(std::size_t bytesToSubtract);
//Function: matchExpected
// Checks to see if the byte(s) passed in match any of the expected responses
//
//Parameters:
// data - The <DataBuffer> containing the bytes to be read and compared against the
// expected responses, starting at the current read position.
//
//Returns:
// true if the byte(s) matched an expected response, false otherwise
bool matchExpected(DataBuffer& data);
//Function: matchExpected
// Checks to see if the wireless packet passed in matches any of the expected responses
//
//Parameters:
// packet - The <WirelessPacket> to be compared against the expected responses
// lastReadPos - The last read position where the packet was parsed from.
//
//Returns:
// true if the packet matched an expected response, false otherwise
bool matchExpected(const WirelessPacket& packet, std::size_t lastReadPos);
//Function: matchExpected
// Checks to see if the <MipDataField> passed in matches any of the expected responses
//
//Parameters:
// field - The <MipDataField> to be compared against the expected responses
//
//Returns:
// true if the packet matched an expected response, false otherwise
bool matchExpected(MipDataField& field);
};
} | 37.735537 | 117 | 0.621989 |
1b2ed49738b061bcc77e8cb862c45882b17f244d | 5,917 | h | C | tsMuxer/vc1Parser.h | Zero-Maple/tsMuxer | 664dc78c32ce08b120aa237013924b3b53ccc45f | [
"Apache-2.0"
] | null | null | null | tsMuxer/vc1Parser.h | Zero-Maple/tsMuxer | 664dc78c32ce08b120aa237013924b3b53ccc45f | [
"Apache-2.0"
] | null | null | null | tsMuxer/vc1Parser.h | Zero-Maple/tsMuxer | 664dc78c32ce08b120aa237013924b3b53ccc45f | [
"Apache-2.0"
] | null | null | null | #ifndef VC1_PARSER_H
#define VC1_PARSER_H
#include <types/types.h>
#include <string>
#include "bitStream.h"
#include "memory.h"
#include "vod_common.h"
enum class VC1Code
{
ENDOFSEQ = 0x0A,
SLICE,
FIELD,
FRAME,
ENTRYPOINT,
SEQHDR,
USER_SLICE = 0x1B, // user-defined slice
USER_FIELD,
USER_FRAME,
USER_ENTRYPOINT,
USER_SEQHDR
};
enum class Profile
{
SIMPLE,
MAIN,
COMPLEX, ///< TODO: WMV9 specific
ADVANCED
};
const int ff_vc1_fps_nr[7] = {24, 25, 30, 50, 60, 48, 72};
const int ff_vc1_fps_dr[2] = {1000, 1001};
/*
struct AVRational {
int w, h;
AVRational() {w = h =0;}
AVRational(int _w, int _h) {w = _w; h = _h;}
};
*/
const AVRational ff_vc1_pixel_aspect[16] = {
AVRational(0, 1), AVRational(1, 1), AVRational(12, 11), AVRational(10, 11),
AVRational(16, 11), AVRational(40, 33), AVRational(24, 11), AVRational(20, 11),
AVRational(32, 11), AVRational(80, 33), AVRational(18, 11), AVRational(15, 11),
AVRational(64, 33), AVRational(160, 99), AVRational(0, 1), AVRational(0, 1)};
enum class VC1PictType
{
I_TYPE,
P_TYPE,
B_TYPE,
BI_TYPE
};
extern const char* pict_type_str[4];
class VC1Unit
{
public:
VC1Unit() : bitReader(), m_nalBuffer(0), m_nalBufferLen(0) {}
~VC1Unit() { delete[] m_nalBuffer; }
inline static bool isMarker(uint8_t* ptr) { return ptr[0] == ptr[1] == 0 && ptr[2] == 1; }
inline static uint8_t* findNextMarker(uint8_t* buffer, uint8_t* end)
{
for (buffer += 2; buffer < end;)
{
if (*buffer > 1)
buffer += 3;
else if (*buffer == 0)
buffer++;
else if (buffer[-2] == 0 && buffer[-1] == 0)
{
return buffer - 2;
}
else
buffer += 3;
}
return end;
}
inline int64_t vc1_unescape_buffer(uint8_t* src, int64_t size)
{
delete[] m_nalBuffer;
m_nalBuffer = new uint8_t[size];
if (size < 4)
{
std::copy(src, src + size, m_nalBuffer);
m_nalBufferLen = size;
return size;
}
int64_t dsize = 0;
for (int64_t i = 0; i < size; i++, src++)
{
if (src[0] == 3 && i >= 2 && !src[-1] && !src[-2] && i < size - 1 && src[1] < 4)
{
m_nalBuffer[dsize++] = src[1];
src++;
i++;
}
else
m_nalBuffer[dsize++] = *src;
}
m_nalBufferLen = dsize;
return dsize;
}
inline int64_t vc1_escape_buffer(uint8_t* dst)
{
uint8_t* srcStart = m_nalBuffer;
uint8_t* initDstBuffer = dst;
uint8_t* srcBuffer = m_nalBuffer;
uint8_t* srcEnd = m_nalBuffer + m_nalBufferLen;
for (srcBuffer += 2; srcBuffer < srcEnd;)
{
if (*srcBuffer > 3)
srcBuffer += 3;
else if (srcBuffer[-2] == 0 && srcBuffer[-1] == 0)
{
memcpy(dst, srcStart, srcBuffer - srcStart);
dst += srcBuffer - srcStart;
*dst++ = 3;
*dst++ = *srcBuffer++;
for (int k = 0; k < 1; k++)
if (srcBuffer < srcEnd)
{
*dst++ = *srcBuffer++;
}
srcStart = srcBuffer;
}
else
srcBuffer++;
}
memcpy(dst, srcStart, srcEnd - srcStart);
dst += srcEnd - srcStart;
return dst - initDstBuffer;
}
const BitStreamReader& getBitReader() { return bitReader; }
protected:
void updateBits(int bitOffset, int bitLen, int value);
BitStreamReader bitReader;
uint8_t* m_nalBuffer;
size_t m_nalBufferLen;
};
class VC1SequenceHeader : public VC1Unit
{
public:
VC1SequenceHeader()
: VC1Unit(),
profile(Profile::SIMPLE),
rangered(0),
max_b_frames(0),
finterpflag(false),
level(0),
coded_width(0),
coded_height(0),
display_width(0),
display_height(0),
pulldown(0),
interlace(0),
tfcntrflag(false),
psf(0),
time_base_num(0),
time_base_den(0),
hrd_param_flag(false),
hrd_num_leaky_buckets(0),
sample_aspect_ratio(1, 1),
m_fpsFieldBitVal(0)
{
}
Profile profile;
int rangered;
int max_b_frames;
int finterpflag; ///< INTERPFRM present
int level;
int coded_width;
int coded_height;
int display_width;
int display_height;
int pulldown; ///< TFF/RFF present
bool interlace; ///< Progressive/interlaced (RPTFTM syntax element)
bool tfcntrflag; ///< TFCNTR present
int psf; ///< Progressive Segmented Frame
int time_base_num;
int time_base_den;
int hrd_param_flag;
int hrd_num_leaky_buckets;
/* for decoding entry point */
int decode_entry_point();
/* ------------------------*/
AVRational sample_aspect_ratio; // w, h
int decode_sequence_header();
int decode_sequence_header_adv();
std::string getStreamDescr();
double getFPS();
void setFPS(double value);
private:
int m_fpsFieldBitVal;
};
class VC1Frame : public VC1Unit
{
public:
VC1Frame() : VC1Unit(), fcm(0), pict_type(VC1PictType::I_TYPE), rptfrm(0), tff(0), rff(0), rptfrmBitPos(0) {}
int fcm;
VC1PictType pict_type;
int rptfrm;
int tff;
int rff;
int rptfrmBitPos;
int decode_frame_direct(const VC1SequenceHeader& sequenceHdr, uint8_t* buffer, uint8_t* end);
private:
int vc1_parse_frame_header(const VC1SequenceHeader& sequenceHdr);
int vc1_parse_frame_header_adv(const VC1SequenceHeader& sequenceHdr);
};
#endif
| 26.066079 | 113 | 0.545378 |
0048045229de77c8916d071b779400b24678e1ac | 1,359 | h | C | Core/Source/DTScripting/DTScriptExpression.h | hekkihek/DTFoundation | c06f7e12a17b09042dab496fcc50bda6f03c2e9c | [
"BSD-2-Clause"
] | 394 | 2015-01-04T15:59:12.000Z | 2022-02-06T11:26:39.000Z | Core/Source/DTScripting/DTScriptExpression.h | hekkihek/DTFoundation | c06f7e12a17b09042dab496fcc50bda6f03c2e9c | [
"BSD-2-Clause"
] | 40 | 2015-01-08T18:42:31.000Z | 2021-08-18T13:51:15.000Z | Core/Source/DTScripting/DTScriptExpression.h | hekkihek/DTFoundation | c06f7e12a17b09042dab496fcc50bda6f03c2e9c | [
"BSD-2-Clause"
] | 163 | 2015-01-15T19:21:40.000Z | 2022-02-02T15:53:38.000Z | //
// DTScriptExpression.h
// DTFoundation
//
// Created by Oliver Drobnik on 10/17/12.
// Copyright (c) 2012 Cocoanetics. All rights reserved.
//
#import <Foundation/Foundation.h>
#import "DTScriptVariable.h"
typedef void (^DTScriptExpressionParameterEnumerationBlock) (NSString *paramName, DTScriptVariable *variable, BOOL *stop);
/**
Instances of this class represent a single Objective-C script expression
*/
@interface DTScriptExpression : NSObject
/**
Creates a script expression from an `NSString`
@param string A string representing an Object-C command including square brackets.
*/
+ (DTScriptExpression *)scriptExpressionWithString:(NSString *)string;
/**
Creates a script expression from an `NSString`
@param string A string representing an Object-C command including square brackets.
*/
- (id)initWithString:(NSString *)string;
/**
The parameters of the script expression
*/
@property (nonatomic, readonly) NSArray *parameters;
/**
Enumerates the script parameters and executes the block for each parameter.
@param block The block to be executed for each parameter
*/
- (void)enumerateParametersWithBlock:(DTScriptExpressionParameterEnumerationBlock)block;
/**
Accesses the receiver of the expression
*/
@property (nonatomic, readonly) DTScriptVariable *receiver;
/**
The method selector
*/
- (SEL)selector;
@end
| 24.267857 | 122 | 0.761589 |
63ce036ff912c4489f6782a5e1d0e7e04b836946 | 601 | c | C | Exercism/c/binary-search/src/binary_search.c | CajetanP/programming-exercises | aee01ff3208ab14e7d0e0a7077798342123bc3e6 | [
"MIT"
] | 1 | 2017-06-23T16:39:17.000Z | 2017-06-23T16:39:17.000Z | Exercism/c/binary-search/src/binary_search.c | CajetanP/coding-exercises | aee01ff3208ab14e7d0e0a7077798342123bc3e6 | [
"MIT"
] | 10 | 2021-05-09T00:06:22.000Z | 2021-09-02T12:07:41.000Z | Exercism/c/binary-search/src/binary_search.c | mrkajetanp/programming-exercises | aee01ff3208ab14e7d0e0a7077798342123bc3e6 | [
"MIT"
] | null | null | null | #include <stdio.h>
#include "binary_search.h"
int binary_search_idx_rec(int* arr, int key, int low, int high) {
if (low > high)
return -1;
int mid = (low+high) / 2;
if (arr[mid] == key)
return mid;
if (arr[mid] > key)
return binary_search_idx_rec(arr, key, low, mid-1);
else
return binary_search_idx_rec(arr, key, mid+1, high);
}
int* binary_search(int x, int* arr, int len) {
if (!arr || len == 0)
return NULL;
int idx = binary_search_idx_rec(arr, x, 0, len);
if (idx == -1)
return NULL;
return &arr[idx];
}
| 20.033333 | 65 | 0.570715 |
bbbeb693c0123ed2c5694fab62613e8aafee48ca | 10,989 | h | C | external/eclib/vector.h | RobbeDGreef/OS | 121709618164906ab030502861c487b0dc1cdefa | [
"MIT"
] | 87 | 2019-08-24T16:10:35.000Z | 2022-03-24T15:28:47.000Z | external/eclib/vector.h | RobbeDGreef/OS | 121709618164906ab030502861c487b0dc1cdefa | [
"MIT"
] | null | null | null | external/eclib/vector.h | RobbeDGreef/OS | 121709618164906ab030502861c487b0dc1cdefa | [
"MIT"
] | 5 | 2019-10-31T17:43:36.000Z | 2021-01-17T18:58:57.000Z | #ifndef __ECLIB_VECTOR_H
#define __ECLIB_VECTOR_H
#include "core.h"
#define VECTOR_STARTCAP 8
#define CHECK_INDEX(vec, ind) (ind < vec->size && !vec->destroyed)
#define VECTOR_GET(vec, ind, type) ((char *) vec->buffer + ind * sizeof(type))
#define define_vector_functionprototypes(type, name) \
name name##_create(); \
type name##_get(name vec, unsigned int index); \
int name##_destroy(name vec); \
int name##_wipe(name vec, unsigned int index); \
name name##_copy(name srcvec); \
int name##_reserve(name vec, size_t amount); \
int name##_push(name vec, type object); \
type name##_pop(name vec); \
int name##_set(name vec, unsigned int index, type object); \
int name##_iter(name vec);
/**
* @brief Defines a vector
*
* @param name The suffix for the vector name. For example if the name
* would be foo the vector name would be vec_foo
*
*
* This macro first defines a basic vector structure with prefix name
* "vec_s_" (and then after that your chosen suffix). After that it will
* create an alias for a pointer to the structure called "vec_". You should
* always use the "vec_" structure pointer and not the raw structure.
*
*/
#define define_vector_type(name) \
struct vec_s_##name \
{ \
void * buffer; \
size_t size; \
size_t capacity; \
int destroyed; \
int error; \
int iter; \
}; \
typedef struct vec_s_##name *name;
/**
* @brief Defines all the vector functions
*
* @param type The type of the vector
* @param name The name of the vector
*
*/
#define define_vector_functions(type, name) \
_define_vector_create(type, name); \
_define_vector_get(type, name); \
_define_vector_destroy(type, name); \
_define_vector_wipe(type, name); \
_define_vector_copy(type, name); \
_define_vector_reserve(type, name); \
_define_vector_push(type, name); \
_define_vector_set(type, name); \
_define_vector_pop(type, name); \
_define_vector_iter(type, name); \
_define_vector_find_int(type, name);
#define _ret_error(err, vec, type) \
vec->error = err; \
type x; \
memset(&x, 0, sizeof(type)); \
return x;
/**
* @brief Defines the vector create function.
*
* @param type The type of the vector
* @param name The name of the vector
*
*/
#define _define_vector_create(type, name) \
name name##_create() \
{ \
name vec = eclib_malloc(sizeof(struct vec_s_##name)); \
vec->buffer = eclib_malloc(sizeof(type) * VECTOR_STARTCAP); \
vec->capacity = VECTOR_STARTCAP; \
vec->size = 0; \
vec->destroyed = 0; \
vec->iter = 0; \
vec->error = 0; \
return vec; \
}
#define _define_vector_get(type, name) \
type name##_get(name vec, unsigned int index) \
{ \
vec->error = 0; \
if (!CHECK_INDEX(vec, index)) \
{ \
_ret_error(ECLIB_EIND, vec, type); \
} \
if (vec->destroyed) \
{ \
_ret_error(ECLIB_EDESTR, vec, type); \
} \
\
return *(type *) VECTOR_GET(vec, index, type); \
}
#define _define_vector_destroy(type, name) \
int name##_destroy(name vec) \
{ \
if (vec->destroyed) \
return -1; \
\
vec->destroyed = 1; \
eclib_free(vec->buffer); \
eclib_free(vec); \
return 0; \
}
#define _define_vector_wipe(type, name) \
int name##_wipe(name vec, unsigned int index) \
{ \
if (!CHECK_INDEX(vec, index)) \
return -1; \
\
eclib_memset(VECTOR_GET(vec, index, type), 0, sizeof(type)); \
return 0; \
}
#define _define_vector_copy(type, name) \
name name##_copy(name srcvec) \
{ \
name newvec = eclib_malloc(sizeof(struct vec_s_##name)); \
newvec->capacity = srcvec->capacity; \
newvec->size = srcvec->size; \
newvec->destroyed = srcvec->destroyed; \
\
newvec->buffer = eclib_malloc(sizeof(type) * srcvec->capacity); \
eclib_memcpy(newvec->buffer, srcvec->buffer, \
sizeof(type) * srcvec->capacity); \
\
return newvec; \
}
#define _define_vector_reserve(type, name) \
int name##_reserve(name vec, size_t amount) \
{ \
if (amount < vec->capacity) \
return -1; \
\
int prevcap = vec->capacity; \
vec->capacity = amount; \
\
void *buf = eclib_malloc(sizeof(type) * vec->capacity); \
eclib_memcpy(buf, vec->buffer, prevcap * sizeof(type)); \
eclib_free(vec->buffer); \
\
vec->buffer = buf; \
return 0; \
}
#define _define_vector_push(type, name) \
int name##_push(name vec, type object) \
{ \
if (vec->destroyed) \
return -1; \
\
if (vec->size == vec->capacity) \
name##_reserve(vec, vec->capacity * 2); \
\
eclib_memcpy(VECTOR_GET(vec, vec->size, type), &object, sizeof(type)); \
\
return ++vec->size; \
}
#define _define_vector_set(type, name) \
int name##_set(name vec, unsigned int index, type object) \
{ \
if (vec->destroyed) \
return -1; \
\
if (!CHECK_INDEX(vec, index)) \
return -1; \
\
eclib_memcpy(VECTOR_GET(vec, index, type), &object, sizeof(type)); \
return 0; \
}
#define _define_vector_pop(type, name) \
type name##_pop(name vec) \
{ \
vec->error = 0; \
if (vec->destroyed) \
{ \
_ret_error(ECLIB_EDESTR, vec, type); \
} \
\
if (vec->size == 0) \
{ \
_ret_error(ECLIB_EIND, vec, type); \
} \
\
return *(type *) VECTOR_GET(vec, vec->size - 1, type); \
}
/**
* example:
*
* int iter;
* vec_int vec;
*
* while ((iter = vec_int_iter(vec)) != -1)
* {
* printf("data %i\n", vec_int_get(vec, iter));
* }
*/
#define _define_vector_iter(type, name) \
int name##_iter(name vec) \
{ \
if (vec->iter == (int) vec->size) \
{ \
vec->iter = 0; \
return -1; \
} \
\
return vec->iter++; \
}
#define _define_vector_find_int(type, name) \
int name##_find_int(name vec, int offset, int value) \
{ \
for (unsigned int i = 0; i < vec->size; i++) \
{ \
type x = name##_get(vec, i); \
if ((int) *(((char *) &x) + offset) == value) \
return i; \
} \
\
return -1; \
}
#define define_vector(type, name) \
define_vector_type(name); \
define_vector_functions(type, name);
#endif /* __ECLIB_VECTOR_H */ | 44.670732 | 80 | 0.342706 |
49c102c90f7f863cb890b201444be2a994b4d1af | 91,605 | c | C | src/add_simd_armv7.c | m1griffin/arrayfunc | df57097699c25d3e949e1ade307ed61eaa5728c2 | [
"Apache-2.0"
] | 2 | 2017-08-28T08:41:16.000Z | 2018-05-29T03:49:36.000Z | src/add_simd_armv7.c | m1griffin/arrayfunc | df57097699c25d3e949e1ade307ed61eaa5728c2 | [
"Apache-2.0"
] | null | null | null | src/add_simd_armv7.c | m1griffin/arrayfunc | df57097699c25d3e949e1ade307ed61eaa5728c2 | [
"Apache-2.0"
] | null | null | null | //------------------------------------------------------------------------------
// Project: arrayfunc
// Module: add_simd_armv7.c
// Purpose: Calculate the add of values in an array.
// This file provides an SIMD version of the functions.
// Language: C
// Date: 8-Oct-2019
// Ver: 31-Oct-2021.
//
//------------------------------------------------------------------------------
//
// Copyright 2014 - 2021 Michael Griffin <m12.griffin@gmail.com>
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
/*--------------------------------------------------------------------------- */
// This must be defined before "Python.h" in order for the pointers in the
// argument parsing functions to work properly.
#define PY_SSIZE_T_CLEAN
#include "Python.h"
#include "simddefs.h"
#ifdef AF_HASSIMD_ARMv7_32BIT
#include "arm_neon.h"
#endif
#include "arrayerrs.h"
/*--------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------- */
// Auto generated code goes below.
// Function specific macros and other definitions.
#include "add_defs.h"
// Function specific macros and other definitions.
#include "add_defs.h"
/*--------------------------------------------------------------------------- */
/* Initialise an SIMD vector with a specifired value.
initval = The value to initialise the vector to.
Returns the initalised SIMD vector.
*/
#if defined(AF_HASSIMD_ARMv7_32BIT)
int8x8_t initvec_signed_char(signed char initval) {
unsigned int y;
signed char initvals[CHARSIMDSIZE];
int8x8_t simdvec;
for (y = 0; y < CHARSIMDSIZE; y++) {
initvals[y] = initval;
}
simdvec = vld1_s8((initvals));
return simdvec;
}
#endif
/*--------------------------------------------------------------------------- */
/* The following series of functions reflect the different parameter options possible.
This version is without overflow checking.
arraylen = The length of the data arrays.
data1 = The first data array.
data2 = The second data array.
data3 = The third data array.
param = The parameter to be applied to each array element.
*/
// param_arr_num_none
#if defined(AF_HASSIMD_ARMv7_32BIT)
void add_signed_char_1_simd(Py_ssize_t arraylen, signed char *data1, signed char param) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int8x8_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceright = initvec_signed_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data1[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + param;
}
}
// param_arr_num_arr
void add_signed_char_2_simd(Py_ssize_t arraylen, signed char *data1, signed char param, signed char *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int8x8_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceright = initvec_signed_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + param;
}
}
// param_num_arr_none
void add_signed_char_3_simd(Py_ssize_t arraylen, signed char param, signed char *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int8x8_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceleft = initvec_signed_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_s8( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data2[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data2[x] = param + data2[x];
}
}
// param_num_arr_arr
void add_signed_char_4_simd(Py_ssize_t arraylen, signed char param, signed char *data2, signed char *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int8x8_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceleft = initvec_signed_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_s8( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = param + data2[x];
}
}
// param_arr_arr_none
void add_signed_char_5_simd(Py_ssize_t arraylen, signed char *data1, signed char *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int8x8_t datasliceleft, datasliceright, resultslice;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data1[x]);
datasliceright = vld1_s8( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data1[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + data2[x];
}
}
// param_arr_arr_arr
void add_signed_char_6_simd(Py_ssize_t arraylen, signed char *data1, signed char *data2, signed char *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int8x8_t datasliceleft, datasliceright, resultslice;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data1[x]);
datasliceright = vld1_s8( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + data2[x];
}
}
#endif
/*--------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------- */
/* The following series of functions reflect the different parameter options possible.
This version supports overflow checking.
arraylen = The length of the data arrays.
data1 = The first data array.
data2 = The second data array.
data3 = The third data array.
param = The parameter to be applied to each array element.
Returns 1 if overflow occurred, else returns 0.
*/
// param_arr_num_none
#if defined(AF_HASSIMD_ARMv7_32BIT)
char add_signed_char_1_simd_ovfl(Py_ssize_t arraylen, signed char *data1, signed char param) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
signed char ovlimit;
int8x8_t datasliceleft, datasliceright, resultslice, ovflvec;
uint8x8_t ovcheck;
// We don't need to do anything if param is zero.
if (param == 0) {
return 0;
}
// Initialise the param values.
datasliceright = initvec_signed_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// param is positive.
if (param > 0) {
// Used to calculate overflow.
ovlimit = pos_ovlimit_signed_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_char(ovlimit);
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data1[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_s8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data1[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data1[x], ovlimit) ) {return 1;}
data1[x] = data1[x] + param;
}
}
// param is negative.
if (param < 0) {
// Used to calculate overflow.
ovlimit = neg_ovlimit_signed_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_char(ovlimit);
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data1[x]);
// Check for overflow.
// Do a less than compare operation.
ovcheck = vclt_s8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data1[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( neg_willoverflow(data1[x], ovlimit) ) {return 1;}
data1[x] = data1[x] + param;
}
}
return 0;
}
// param_arr_num_arr
char add_signed_char_2_simd_ovfl(Py_ssize_t arraylen, signed char *data1, signed char param, signed char *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
signed char ovlimit;
int8x8_t datasliceleft, datasliceright, resultslice, ovflvec;
uint8x8_t ovcheck;
// We don't need to do anything if param is zero, just copy the data.
if (param == 0) {
for (x = 0; x < arraylen; x++) {
data3[x] = data1[x];
}
return 0;
}
// Initialise the param values.
datasliceright = initvec_signed_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// param is positive.
if (param > 0) {
// Used to calculate overflow.
ovlimit = pos_ovlimit_signed_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_char(ovlimit);
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data1[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_s8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data1[x], ovlimit) ) {return 1;}
data3[x] = data1[x] + param;
}
}
// param is negative.
if (param < 0) {
// Used to calculate overflow.
ovlimit = neg_ovlimit_signed_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_char(ovlimit);
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data1[x]);
// Check for overflow.
// Do a less than compare operation.
ovcheck = vclt_s8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( neg_willoverflow(data1[x], ovlimit) ) {return 1;}
data3[x] = data1[x] + param;
}
}
return 0;
}
// param_num_arr_none
char add_signed_char_3_simd_ovfl(Py_ssize_t arraylen, signed char param, signed char *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
signed char ovlimit;
int8x8_t datasliceleft, datasliceright, resultslice, ovflvec;
uint8x8_t ovcheck;
// We don't need to do anything if param is zero.
if (param == 0) {
return 0;
}
// Initialise the param values.
datasliceright = initvec_signed_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// param is positive.
if (param > 0) {
ovlimit = pos_ovlimit_signed_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_char(ovlimit);
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data2[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_s8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data2[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data2[x], ovlimit) ) {return 1;}
data2[x] = data2[x] + param;
}
}
// param is negative.
if (param < 0) {
// Used to calculate overflow.
ovlimit = neg_ovlimit_signed_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_char(ovlimit);
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data2[x]);
// Check for overflow.
// Do a less than compare operation.
ovcheck = vclt_s8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data2[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( neg_willoverflow(data2[x], ovlimit) ) {return 1;}
data2[x] = data2[x] + param;
}
}
return 0;
}
// param_num_arr_arr
char add_signed_char_4_simd_ovfl(Py_ssize_t arraylen, signed char param, signed char *data2, signed char *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
signed char ovlimit;
int8x8_t datasliceleft, datasliceright, resultslice, ovflvec;
uint8x8_t ovcheck;
// We don't need to do anything if param is zero, just copy the data.
if (param == 0) {
for (x = 0; x < arraylen; x++) {
data3[x] = data2[x];
}
return 0;
}
// Initialise the param values.
datasliceright = initvec_signed_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// param is positive.
if (param > 0) {
// Used to calculate overflow.
ovlimit = pos_ovlimit_signed_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_char(ovlimit);
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data2[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_s8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data2[x], ovlimit) ) {return 1;}
data3[x] = data2[x] + param;
}
}
// param is negative.
if (param < 0) {
// Used to calculate overflow.
ovlimit = neg_ovlimit_signed_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_char(ovlimit);
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s8( &data2[x]);
// Check for overflow.
// Do a less than compare operation.
ovcheck = vclt_s8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s8(datasliceleft, datasliceright);
// Store the result.
vst1_s8( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( neg_willoverflow(data2[x], ovlimit) ) {return 1;}
data3[x] = data2[x] + param;
}
}
return 0;
}
#endif
/*--------------------------------------------------------------------------- */
/* Initialise an SIMD vector with a specifired value.
initval = The value to initialise the vector to.
Returns the initalised SIMD vector.
*/
#if defined(AF_HASSIMD_ARMv7_32BIT)
uint8x8_t initvec_unsigned_char(unsigned char initval) {
unsigned int y;
unsigned char initvals[CHARSIMDSIZE];
uint8x8_t simdvec;
for (y = 0; y < CHARSIMDSIZE; y++) {
initvals[y] = initval;
}
simdvec = vld1_u8((initvals));
return simdvec;
}
#endif
/*--------------------------------------------------------------------------- */
/* The following series of functions reflect the different parameter options possible.
This version is without overflow checking.
arraylen = The length of the data arrays.
data1 = The first data array.
data2 = The second data array.
data3 = The third data array.
param = The parameter to be applied to each array element.
*/
// param_arr_num_none
#if defined(AF_HASSIMD_ARMv7_32BIT)
void add_unsigned_char_1_simd(Py_ssize_t arraylen, unsigned char *data1, unsigned char param) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint8x8_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceright = initvec_unsigned_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u8( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data1[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + param;
}
}
// param_arr_num_arr
void add_unsigned_char_2_simd(Py_ssize_t arraylen, unsigned char *data1, unsigned char param, unsigned char *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint8x8_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceright = initvec_unsigned_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u8( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + param;
}
}
// param_num_arr_none
void add_unsigned_char_3_simd(Py_ssize_t arraylen, unsigned char param, unsigned char *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint8x8_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceleft = initvec_unsigned_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_u8( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data2[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data2[x] = param + data2[x];
}
}
// param_num_arr_arr
void add_unsigned_char_4_simd(Py_ssize_t arraylen, unsigned char param, unsigned char *data2, unsigned char *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint8x8_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceleft = initvec_unsigned_char(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_u8( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = param + data2[x];
}
}
// param_arr_arr_none
void add_unsigned_char_5_simd(Py_ssize_t arraylen, unsigned char *data1, unsigned char *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint8x8_t datasliceleft, datasliceright, resultslice;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u8( &data1[x]);
datasliceright = vld1_u8( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data1[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + data2[x];
}
}
// param_arr_arr_arr
void add_unsigned_char_6_simd(Py_ssize_t arraylen, unsigned char *data1, unsigned char *data2, unsigned char *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint8x8_t datasliceleft, datasliceright, resultslice;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u8( &data1[x]);
datasliceright = vld1_u8( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + data2[x];
}
}
#endif
/*--------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------- */
/* The following series of functions reflect the different parameter options possible.
This version is with overflow checking.
arraylen = The length of the data arrays.
data1 = The first data array.
data2 = The second data array.
data3 = The third data array.
param = The parameter to be applied to each array element.
*/
// param_arr_num_none
#if defined(AF_HASSIMD_ARMv7_32BIT)
char add_unsigned_char_1_simd_ovfl(Py_ssize_t arraylen, unsigned char *data1, unsigned char param) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
unsigned char ovlimit;
uint8x8_t datasliceleft, datasliceright, resultslice, ovflvec;
uint8x8_t ovcheck;
// Initialise the comparison values.
datasliceright = initvec_unsigned_char(param);
// Used to calculate overflow.
ovlimit = ovlimit_unsigned_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_unsigned_char(ovlimit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u8( &data1[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data1[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data1[x], ovlimit) ) {return 1;}
data1[x] = data1[x] + param;
}
return 0;
}
// param_arr_num_arr
char add_unsigned_char_2_simd_ovfl(Py_ssize_t arraylen, unsigned char *data1, unsigned char param, unsigned char *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
unsigned char ovlimit;
uint8x8_t datasliceleft, datasliceright, resultslice, ovflvec;
uint8x8_t ovcheck;
// Initialise the comparison values.
datasliceright = initvec_unsigned_char(param);
// Used to calculate overflow.
ovlimit = ovlimit_unsigned_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_unsigned_char(ovlimit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u8( &data1[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data1[x], ovlimit) ) {return 1;}
data3[x] = data1[x] + param;
}
return 0;
}
// param_num_arr_none
char add_unsigned_char_3_simd_ovfl(Py_ssize_t arraylen, unsigned char param, unsigned char *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
unsigned char ovlimit;
uint8x8_t datasliceleft, datasliceright, resultslice, ovflvec;
uint8x8_t ovcheck;
// Initialise the comparison values.
datasliceright = initvec_unsigned_char(param);
// Used to calculate overflow.
ovlimit = ovlimit_unsigned_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_unsigned_char(ovlimit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u8( &data2[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data2[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data2[x], ovlimit) ) {return 1;}
data2[x] = param + data2[x];
}
return 0;
}
// param_num_arr_arr
char add_unsigned_char_4_simd_ovfl(Py_ssize_t arraylen, unsigned char param, unsigned char *data2, unsigned char *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
unsigned char ovlimit;
uint8x8_t datasliceleft, datasliceright, resultslice, ovflvec;
uint8x8_t ovcheck;
// Initialise the comparison values.
datasliceright = initvec_unsigned_char(param);
// Used to calculate overflow.
ovlimit = ovlimit_unsigned_char(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_unsigned_char(ovlimit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u8( &data2[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data2[x], ovlimit) ) {return 1;}
data3[x] = param + data2[x];
}
return 0;
}
// param_arr_arr_none
char add_unsigned_char_5_simd_ovfl(Py_ssize_t arraylen, unsigned char *data1, unsigned char *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
static unsigned char ovcompvals[CHARSIMDSIZE] = {UCHAR_MAX, UCHAR_MAX, UCHAR_MAX, UCHAR_MAX, UCHAR_MAX, UCHAR_MAX, UCHAR_MAX, UCHAR_MAX};
uint8x8_t datasliceleft, datasliceright, resultslice, ovcompslice, ovflvec;
uint8x8_t ovcheck;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Used to check for overflows.
ovcompslice = vld1_u8( ovcompvals);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u8( &data1[x]);
datasliceright = vld1_u8( &data2[x]);
// Subtract the right hand value.
ovflvec = vsub_u8(ovcompslice, datasliceright);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data1[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( loop_willoverflow_unsigned_char(data1[x], data2[x]) ) {return 1;}
data1[x] = data1[x] + data2[x];
}
return 0;
}
// param_arr_arr_arr
char add_unsigned_char_6_simd_ovfl(Py_ssize_t arraylen, unsigned char *data1, unsigned char *data2, unsigned char *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
static unsigned char ovcompvals[CHARSIMDSIZE] = {UCHAR_MAX, UCHAR_MAX, UCHAR_MAX, UCHAR_MAX, UCHAR_MAX, UCHAR_MAX, UCHAR_MAX, UCHAR_MAX};
uint8x8_t datasliceleft, datasliceright, resultslice, ovcompslice, ovflvec;
uint8x8_t ovcheck;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, CHARSIMDSIZE);
// Used to check for overflows.
ovcompslice = vld1_u8( ovcompvals);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += CHARSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u8( &data1[x]);
datasliceright = vld1_u8( &data2[x]);
// Subtract the right hand value.
ovflvec = vsub_u8(ovcompslice, datasliceright);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u8 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u8(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u8(datasliceleft, datasliceright);
// Store the result.
vst1_u8( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( loop_willoverflow_unsigned_char(data1[x], data2[x]) ) {return 1;}
data3[x] = data1[x] + data2[x];
}
return 0;
}
#endif
/*--------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------- */
/* Initialise an SIMD vector with a specifired value.
initval = The value to initialise the vector to.
Returns the initalised SIMD vector.
*/
#if defined(AF_HASSIMD_ARMv7_32BIT)
int16x4_t initvec_signed_short(signed short initval) {
unsigned int y;
signed short initvals[SHORTSIMDSIZE];
int16x4_t simdvec;
for (y = 0; y < SHORTSIMDSIZE; y++) {
initvals[y] = initval;
}
simdvec = vld1_s16((initvals));
return simdvec;
}
#endif
/*--------------------------------------------------------------------------- */
/* The following series of functions reflect the different parameter options possible.
This version is without overflow checking.
arraylen = The length of the data arrays.
data1 = The first data array.
data2 = The second data array.
data3 = The third data array.
param = The parameter to be applied to each array element.
*/
// param_arr_num_none
#if defined(AF_HASSIMD_ARMv7_32BIT)
void add_signed_short_1_simd(Py_ssize_t arraylen, signed short *data1, signed short param) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int16x4_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceright = initvec_signed_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data1[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + param;
}
}
// param_arr_num_arr
void add_signed_short_2_simd(Py_ssize_t arraylen, signed short *data1, signed short param, signed short *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int16x4_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceright = initvec_signed_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + param;
}
}
// param_num_arr_none
void add_signed_short_3_simd(Py_ssize_t arraylen, signed short param, signed short *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int16x4_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceleft = initvec_signed_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_s16( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data2[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data2[x] = param + data2[x];
}
}
// param_num_arr_arr
void add_signed_short_4_simd(Py_ssize_t arraylen, signed short param, signed short *data2, signed short *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int16x4_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceleft = initvec_signed_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_s16( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = param + data2[x];
}
}
// param_arr_arr_none
void add_signed_short_5_simd(Py_ssize_t arraylen, signed short *data1, signed short *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int16x4_t datasliceleft, datasliceright, resultslice;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data1[x]);
datasliceright = vld1_s16( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data1[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + data2[x];
}
}
// param_arr_arr_arr
void add_signed_short_6_simd(Py_ssize_t arraylen, signed short *data1, signed short *data2, signed short *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
int16x4_t datasliceleft, datasliceright, resultslice;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data1[x]);
datasliceright = vld1_s16( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + data2[x];
}
}
#endif
/*--------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------- */
/* The following series of functions reflect the different parameter options possible.
This version supports overflow checking.
arraylen = The length of the data arrays.
data1 = The first data array.
data2 = The second data array.
data3 = The third data array.
param = The parameter to be applied to each array element.
Returns 1 if overflow occurred, else returns 0.
*/
// param_arr_num_none
#if defined(AF_HASSIMD_ARMv7_32BIT)
char add_signed_short_1_simd_ovfl(Py_ssize_t arraylen, signed short *data1, signed short param) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
signed short ovlimit;
int16x4_t datasliceleft, datasliceright, resultslice, ovflvec;
uint16x4_t ovcheck;
// We don't need to do anything if param is zero.
if (param == 0) {
return 0;
}
// Initialise the param values.
datasliceright = initvec_signed_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// param is positive.
if (param > 0) {
// Used to calculate overflow.
ovlimit = pos_ovlimit_signed_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_short(ovlimit);
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data1[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_s16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data1[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data1[x], ovlimit) ) {return 1;}
data1[x] = data1[x] + param;
}
}
// param is negative.
if (param < 0) {
// Used to calculate overflow.
ovlimit = neg_ovlimit_signed_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_short(ovlimit);
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data1[x]);
// Check for overflow.
// Do a less than compare operation.
ovcheck = vclt_s16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data1[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( neg_willoverflow(data1[x], ovlimit) ) {return 1;}
data1[x] = data1[x] + param;
}
}
return 0;
}
// param_arr_num_arr
char add_signed_short_2_simd_ovfl(Py_ssize_t arraylen, signed short *data1, signed short param, signed short *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
signed short ovlimit;
int16x4_t datasliceleft, datasliceright, resultslice, ovflvec;
uint16x4_t ovcheck;
// We don't need to do anything if param is zero, just copy the data.
if (param == 0) {
for (x = 0; x < arraylen; x++) {
data3[x] = data1[x];
}
return 0;
}
// Initialise the param values.
datasliceright = initvec_signed_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// param is positive.
if (param > 0) {
// Used to calculate overflow.
ovlimit = pos_ovlimit_signed_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_short(ovlimit);
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data1[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_s16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data1[x], ovlimit) ) {return 1;}
data3[x] = data1[x] + param;
}
}
// param is negative.
if (param < 0) {
// Used to calculate overflow.
ovlimit = neg_ovlimit_signed_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_short(ovlimit);
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data1[x]);
// Check for overflow.
// Do a less than compare operation.
ovcheck = vclt_s16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( neg_willoverflow(data1[x], ovlimit) ) {return 1;}
data3[x] = data1[x] + param;
}
}
return 0;
}
// param_num_arr_none
char add_signed_short_3_simd_ovfl(Py_ssize_t arraylen, signed short param, signed short *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
signed short ovlimit;
int16x4_t datasliceleft, datasliceright, resultslice, ovflvec;
uint16x4_t ovcheck;
// We don't need to do anything if param is zero.
if (param == 0) {
return 0;
}
// Initialise the param values.
datasliceright = initvec_signed_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// param is positive.
if (param > 0) {
ovlimit = pos_ovlimit_signed_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_short(ovlimit);
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data2[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_s16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data2[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data2[x], ovlimit) ) {return 1;}
data2[x] = data2[x] + param;
}
}
// param is negative.
if (param < 0) {
// Used to calculate overflow.
ovlimit = neg_ovlimit_signed_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_short(ovlimit);
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data2[x]);
// Check for overflow.
// Do a less than compare operation.
ovcheck = vclt_s16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data2[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( neg_willoverflow(data2[x], ovlimit) ) {return 1;}
data2[x] = data2[x] + param;
}
}
return 0;
}
// param_num_arr_arr
char add_signed_short_4_simd_ovfl(Py_ssize_t arraylen, signed short param, signed short *data2, signed short *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
signed short ovlimit;
int16x4_t datasliceleft, datasliceright, resultslice, ovflvec;
uint16x4_t ovcheck;
// We don't need to do anything if param is zero, just copy the data.
if (param == 0) {
for (x = 0; x < arraylen; x++) {
data3[x] = data2[x];
}
return 0;
}
// Initialise the param values.
datasliceright = initvec_signed_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// param is positive.
if (param > 0) {
// Used to calculate overflow.
ovlimit = pos_ovlimit_signed_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_short(ovlimit);
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data2[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_s16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data2[x], ovlimit) ) {return 1;}
data3[x] = data2[x] + param;
}
}
// param is negative.
if (param < 0) {
// Used to calculate overflow.
ovlimit = neg_ovlimit_signed_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_signed_short(ovlimit);
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_s16( &data2[x]);
// Check for overflow.
// Do a less than compare operation.
ovcheck = vclt_s16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_s16(datasliceleft, datasliceright);
// Store the result.
vst1_s16( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( neg_willoverflow(data2[x], ovlimit) ) {return 1;}
data3[x] = data2[x] + param;
}
}
return 0;
}
#endif
/*--------------------------------------------------------------------------- */
/* Initialise an SIMD vector with a specifired value.
initval = The value to initialise the vector to.
Returns the initalised SIMD vector.
*/
#if defined(AF_HASSIMD_ARMv7_32BIT)
uint16x4_t initvec_unsigned_short(unsigned short initval) {
unsigned int y;
unsigned short initvals[SHORTSIMDSIZE];
uint16x4_t simdvec;
for (y = 0; y < SHORTSIMDSIZE; y++) {
initvals[y] = initval;
}
simdvec = vld1_u16((initvals));
return simdvec;
}
#endif
/*--------------------------------------------------------------------------- */
/* The following series of functions reflect the different parameter options possible.
This version is without overflow checking.
arraylen = The length of the data arrays.
data1 = The first data array.
data2 = The second data array.
data3 = The third data array.
param = The parameter to be applied to each array element.
*/
// param_arr_num_none
#if defined(AF_HASSIMD_ARMv7_32BIT)
void add_unsigned_short_1_simd(Py_ssize_t arraylen, unsigned short *data1, unsigned short param) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint16x4_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceright = initvec_unsigned_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u16( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data1[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + param;
}
}
// param_arr_num_arr
void add_unsigned_short_2_simd(Py_ssize_t arraylen, unsigned short *data1, unsigned short param, unsigned short *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint16x4_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceright = initvec_unsigned_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u16( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + param;
}
}
// param_num_arr_none
void add_unsigned_short_3_simd(Py_ssize_t arraylen, unsigned short param, unsigned short *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint16x4_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceleft = initvec_unsigned_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_u16( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data2[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data2[x] = param + data2[x];
}
}
// param_num_arr_arr
void add_unsigned_short_4_simd(Py_ssize_t arraylen, unsigned short param, unsigned short *data2, unsigned short *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint16x4_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceleft = initvec_unsigned_short(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_u16( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = param + data2[x];
}
}
// param_arr_arr_none
void add_unsigned_short_5_simd(Py_ssize_t arraylen, unsigned short *data1, unsigned short *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint16x4_t datasliceleft, datasliceright, resultslice;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u16( &data1[x]);
datasliceright = vld1_u16( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data1[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + data2[x];
}
}
// param_arr_arr_arr
void add_unsigned_short_6_simd(Py_ssize_t arraylen, unsigned short *data1, unsigned short *data2, unsigned short *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
uint16x4_t datasliceleft, datasliceright, resultslice;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u16( &data1[x]);
datasliceright = vld1_u16( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + data2[x];
}
}
#endif
/*--------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------- */
/* The following series of functions reflect the different parameter options possible.
This version is with overflow checking.
arraylen = The length of the data arrays.
data1 = The first data array.
data2 = The second data array.
data3 = The third data array.
param = The parameter to be applied to each array element.
*/
// param_arr_num_none
#if defined(AF_HASSIMD_ARMv7_32BIT)
char add_unsigned_short_1_simd_ovfl(Py_ssize_t arraylen, unsigned short *data1, unsigned short param) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
unsigned short ovlimit;
uint16x4_t datasliceleft, datasliceright, resultslice, ovflvec;
uint16x4_t ovcheck;
// Initialise the comparison values.
datasliceright = initvec_unsigned_short(param);
// Used to calculate overflow.
ovlimit = ovlimit_unsigned_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_unsigned_short(ovlimit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u16( &data1[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data1[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data1[x], ovlimit) ) {return 1;}
data1[x] = data1[x] + param;
}
return 0;
}
// param_arr_num_arr
char add_unsigned_short_2_simd_ovfl(Py_ssize_t arraylen, unsigned short *data1, unsigned short param, unsigned short *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
unsigned short ovlimit;
uint16x4_t datasliceleft, datasliceright, resultslice, ovflvec;
uint16x4_t ovcheck;
// Initialise the comparison values.
datasliceright = initvec_unsigned_short(param);
// Used to calculate overflow.
ovlimit = ovlimit_unsigned_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_unsigned_short(ovlimit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u16( &data1[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data1[x], ovlimit) ) {return 1;}
data3[x] = data1[x] + param;
}
return 0;
}
// param_num_arr_none
char add_unsigned_short_3_simd_ovfl(Py_ssize_t arraylen, unsigned short param, unsigned short *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
unsigned short ovlimit;
uint16x4_t datasliceleft, datasliceright, resultslice, ovflvec;
uint16x4_t ovcheck;
// Initialise the comparison values.
datasliceright = initvec_unsigned_short(param);
// Used to calculate overflow.
ovlimit = ovlimit_unsigned_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_unsigned_short(ovlimit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u16( &data2[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data2[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data2[x], ovlimit) ) {return 1;}
data2[x] = param + data2[x];
}
return 0;
}
// param_num_arr_arr
char add_unsigned_short_4_simd_ovfl(Py_ssize_t arraylen, unsigned short param, unsigned short *data2, unsigned short *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
unsigned short ovlimit;
uint16x4_t datasliceleft, datasliceright, resultslice, ovflvec;
uint16x4_t ovcheck;
// Initialise the comparison values.
datasliceright = initvec_unsigned_short(param);
// Used to calculate overflow.
ovlimit = ovlimit_unsigned_short(param);
// This is used for detecting a potential overflow condition.
ovflvec = initvec_unsigned_short(ovlimit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u16( &data2[x]);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( pos_willoverflow(data2[x], ovlimit) ) {return 1;}
data3[x] = param + data2[x];
}
return 0;
}
// param_arr_arr_none
char add_unsigned_short_5_simd_ovfl(Py_ssize_t arraylen, unsigned short *data1, unsigned short *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
static unsigned short ovcompvals[SHORTSIMDSIZE] = {USHRT_MAX, USHRT_MAX, USHRT_MAX, USHRT_MAX};
uint16x4_t datasliceleft, datasliceright, resultslice, ovcompslice, ovflvec;
uint16x4_t ovcheck;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Used to check for overflows.
ovcompslice = vld1_u16( ovcompvals);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u16( &data1[x]);
datasliceright = vld1_u16( &data2[x]);
// Subtract the right hand value.
ovflvec = vsub_u16(ovcompslice, datasliceright);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data1[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( loop_willoverflow_unsigned_short(data1[x], data2[x]) ) {return 1;}
data1[x] = data1[x] + data2[x];
}
return 0;
}
// param_arr_arr_arr
char add_unsigned_short_6_simd_ovfl(Py_ssize_t arraylen, unsigned short *data1, unsigned short *data2, unsigned short *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
static unsigned short ovcompvals[SHORTSIMDSIZE] = {USHRT_MAX, USHRT_MAX, USHRT_MAX, USHRT_MAX};
uint16x4_t datasliceleft, datasliceright, resultslice, ovcompslice, ovflvec;
uint16x4_t ovcheck;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, SHORTSIMDSIZE);
// Used to check for overflows.
ovcompslice = vld1_u16( ovcompvals);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += SHORTSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_u16( &data1[x]);
datasliceright = vld1_u16( &data2[x]);
// Subtract the right hand value.
ovflvec = vsub_u16(ovcompslice, datasliceright);
// Check for overflow.
// Do a greater than compare operation.
ovcheck = vcgt_u16 (datasliceleft, ovflvec);
// Check for overflow.
if (!(vreinterpret_u64_u16(ovcheck) == 0x0000000000000000)) {
return 1;
}
// The actual SIMD operation.
resultslice = vadd_u16(datasliceleft, datasliceright);
// Store the result.
vst1_u16( &data3[x], resultslice);
}
// Handle the values left over at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
if ( loop_willoverflow_unsigned_short(data1[x], data2[x]) ) {return 1;}
data3[x] = data1[x] + data2[x];
}
return 0;
}
#endif
/*--------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------- */
/* Initialise an SIMD vector with a specifired value.
initval = The value to initialise the vector to.
Returns the initalised SIMD vector.
*/
#if defined(AF_HASSIMD_ARMv7_32BIT)
float32x2_t initvec_float(float initval) {
unsigned int y;
float initvals[FLOATSIMDSIZE];
float32x2_t simdvec;
for (y = 0; y < FLOATSIMDSIZE; y++) {
initvals[y] = initval;
}
simdvec = vld1_f32((initvals));
return simdvec;
}
#endif
/*--------------------------------------------------------------------------- */
/* The following series of functions reflect the different parameter options possible.
This version is without overflow checking.
arraylen = The length of the data arrays.
data1 = The first data array.
data2 = The second data array.
data3 = The third data array.
param = The parameter to be applied to each array element.
*/
// param_arr_num_none
#if defined(AF_HASSIMD_ARMv7_32BIT)
void add_float_1_simd(Py_ssize_t arraylen, float *data1, float param) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceright = initvec_float(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_f32( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data1[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + param;
}
}
// param_arr_num_arr
void add_float_2_simd(Py_ssize_t arraylen, float *data1, float param, float *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceright = initvec_float(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_f32( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + param;
}
}
// param_num_arr_none
void add_float_3_simd(Py_ssize_t arraylen, float param, float *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceleft = initvec_float(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_f32( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data2[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data2[x] = param + data2[x];
}
}
// param_num_arr_arr
void add_float_4_simd(Py_ssize_t arraylen, float param, float *data2, float *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice;
// Initialise the comparison values.
datasliceleft = initvec_float(param);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_f32( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = param + data2[x];
}
}
// param_arr_arr_none
void add_float_5_simd(Py_ssize_t arraylen, float *data1, float *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_f32( &data1[x]);
datasliceright = vld1_f32( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data1[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + data2[x];
}
}
// param_arr_arr_arr
void add_float_6_simd(Py_ssize_t arraylen, float *data1, float *data2, float *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice;
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_f32( &data1[x]);
datasliceright = vld1_f32( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data3[x], resultslice);
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + data2[x];
}
}
#endif
/*--------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------- */
/* The following series of functions reflect the different parameter options possible.
This version is without overflow checking.
arraylen = The length of the data arrays.
data1 = The first data array.
data2 = The second data array.
data3 = The third data array.
param = The parameter to be applied to each array element.
Returns 1 if overflow occurred, else returns 0.
*/
// param_arr_num_none
#if defined(AF_HASSIMD_ARMv7_32BIT)
char add_float_1_simd_ovfl(Py_ssize_t arraylen, float *data1, float param) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice, checkslice;
float checkvecresults[FLOATSIMDSIZE];
float checksliceinit[FLOATSIMDSIZE] = {0.0};
// Initialise the comparison values.
datasliceright = initvec_float(param);
// This is used to check for errors by accumulating non-finite values.
checkslice = vld1_f32( checksliceinit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_f32( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data1[x], resultslice);
// Check the result. None-finite errors should accumulate.
checkslice = vmul_f32(checkslice, resultslice);
}
// Check the results of the SIMD operations. If all is OK then the
// results should be all zeros. Any none-finite numbers however will
// propagate through and accumulate.
vst1_f32( checkvecresults, checkslice);
for (x = 0; x < FLOATSIMDSIZE; x++) {
if (!isfinite(checkvecresults[x])) {return 1;}
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + param;
if (!isfinite(data1[x])) {return 1;}
}
return 0;
}
// param_arr_num_arr
char add_float_2_simd_ovfl(Py_ssize_t arraylen, float *data1, float param, float *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice, checkslice;
float checkvecresults[FLOATSIMDSIZE];
float checksliceinit[FLOATSIMDSIZE] = {0.0};
// Initialise the comparison values.
datasliceright = initvec_float(param);
// This is used to check for errors by accumulating non-finite values.
checkslice = vld1_f32( checksliceinit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_f32( &data1[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data3[x], resultslice);
// Check the result. None-finite errors should accumulate.
checkslice = vmul_f32(checkslice, resultslice);
}
// Check the results of the SIMD operations. If all is OK then the
// results should be all zeros. Any none-finite numbers however will
// propagate through and accumulate.
vst1_f32( checkvecresults, checkslice);
for (x = 0; x < FLOATSIMDSIZE; x++) {
if (!isfinite(checkvecresults[x])) {return 1;}
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + param;
if (!isfinite(data3[x])) {return 1;}
}
return 0;
}
// param_num_arr_none
char add_float_3_simd_ovfl(Py_ssize_t arraylen, float param, float *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice, checkslice;
float checkvecresults[FLOATSIMDSIZE];
float checksliceinit[FLOATSIMDSIZE] = {0.0};
// Initialise the comparison values.
datasliceleft = initvec_float(param);
// This is used to check for errors by accumulating non-finite values.
checkslice = vld1_f32( checksliceinit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_f32( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data2[x], resultslice);
// Check the result. None-finite errors should accumulate.
checkslice = vmul_f32(checkslice, resultslice);
}
// Check the results of the SIMD operations. If all is OK then the
// results should be all zeros. Any none-finite numbers however will
// propagate through and accumulate.
vst1_f32( checkvecresults, checkslice);
for (x = 0; x < FLOATSIMDSIZE; x++) {
if (!isfinite(checkvecresults[x])) {return 1;}
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data2[x] = param + data2[x];
if (!isfinite(data2[x])) {return 1;}
}
return 0;
}
// param_num_arr_arr
char add_float_4_simd_ovfl(Py_ssize_t arraylen, float param, float *data2, float *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice, checkslice;
float checkvecresults[FLOATSIMDSIZE];
float checksliceinit[FLOATSIMDSIZE] = {0.0};
// Initialise the comparison values.
datasliceleft = initvec_float(param);
// This is used to check for errors by accumulating non-finite values.
checkslice = vld1_f32( checksliceinit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceright = vld1_f32( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data3[x], resultslice);
// Check the result. None-finite errors should accumulate.
checkslice = vmul_f32(checkslice, resultslice);
}
// Check the results of the SIMD operations. If all is OK then the
// results should be all zeros. Any none-finite numbers however will
// propagate through and accumulate.
vst1_f32( checkvecresults, checkslice);
for (x = 0; x < FLOATSIMDSIZE; x++) {
if (!isfinite(checkvecresults[x])) {return 1;}
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = param + data2[x];
if (!isfinite(data3[x])) {return 1;}
}
return 0;
}
// param_arr_arr_none
char add_float_5_simd_ovfl(Py_ssize_t arraylen, float *data1, float *data2) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice, checkslice;
float checkvecresults[FLOATSIMDSIZE];
float checksliceinit[FLOATSIMDSIZE] = {0.0};
// This is used to check for errors by accumulating non-finite values.
checkslice = vld1_f32( checksliceinit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_f32( &data1[x]);
datasliceright = vld1_f32( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data1[x], resultslice);
// Check the result. None-finite errors should accumulate.
checkslice = vmul_f32(checkslice, resultslice);
}
// Check the results of the SIMD operations. If all is OK then the
// results should be all zeros. Any none-finite numbers however will
// propagate through and accumulate.
vst1_f32( checkvecresults, checkslice);
for (x = 0; x < FLOATSIMDSIZE; x++) {
if (!isfinite(checkvecresults[x])) {return 1;}
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data1[x] = data1[x] + data2[x];
if (!isfinite(data1[x])) {return 1;}
}
return 0;
}
// param_arr_arr_arr
char add_float_6_simd_ovfl(Py_ssize_t arraylen, float *data1, float *data2, float *data3) {
// array index counter.
Py_ssize_t x;
// SIMD related variables.
Py_ssize_t alignedlength;
float32x2_t datasliceleft, datasliceright, resultslice, checkslice;
float checkvecresults[FLOATSIMDSIZE];
float checksliceinit[FLOATSIMDSIZE] = {0.0};
// This is used to check for errors by accumulating non-finite values.
checkslice = vld1_f32( checksliceinit);
// Calculate array lengths for arrays whose lengths which are not even
// multipes of the SIMD slice length.
alignedlength = calcalignedlength(arraylen, FLOATSIMDSIZE);
// Perform the main operation using SIMD instructions.
for (x = 0; x < alignedlength; x += FLOATSIMDSIZE) {
// Load the data into the vector register.
datasliceleft = vld1_f32( &data1[x]);
datasliceright = vld1_f32( &data2[x]);
// The actual SIMD operation.
resultslice = vadd_f32(datasliceleft, datasliceright);
// Store the result.
vst1_f32( &data3[x], resultslice);
// Check the result. None-finite errors should accumulate.
checkslice = vmul_f32(checkslice, resultslice);
}
// Check the results of the SIMD operations. If all is OK then the
// results should be all zeros. Any none-finite numbers however will
// propagate through and accumulate.
vst1_f32( checkvecresults, checkslice);
for (x = 0; x < FLOATSIMDSIZE; x++) {
if (!isfinite(checkvecresults[x])) {return 1;}
}
// Get the max value within the left over elements at the end of the array.
for (x = alignedlength; x < arraylen; x++) {
data3[x] = data1[x] + data2[x];
if (!isfinite(data3[x])) {return 1;}
}
return 0;
}
#endif
/*--------------------------------------------------------------------------- */
| 26.998232 | 138 | 0.695497 |
177dfc17e52a51ce7b9225cc7966b26258d49582 | 3,463 | h | C | exercises/lesson03/2/szediwy/include/peripherals/mini_uart.h | djmaster458/raspberry-pi-os | 31fc1481f529ba1a72a8a6bc62dc488b84fc2cdb | [
"MIT"
] | 11,864 | 2018-04-10T01:44:12.000Z | 2022-03-31T23:52:33.000Z | exercises/lesson03/2/szediwy/include/peripherals/mini_uart.h | aosi87/raspberry-pi-os | 31fc1481f529ba1a72a8a6bc62dc488b84fc2cdb | [
"MIT"
] | 130 | 2018-06-06T08:21:23.000Z | 2022-03-23T10:12:37.000Z | exercises/lesson03/2/szediwy/include/peripherals/mini_uart.h | aosi87/raspberry-pi-os | 31fc1481f529ba1a72a8a6bc62dc488b84fc2cdb | [
"MIT"
] | 1,273 | 2018-04-10T06:36:42.000Z | 2022-03-27T04:59:50.000Z | #ifndef _P_MINI_UART_H
#define _P_MINI_UART_H
#include "peripherals/base.h"
#define AUX_ENABLES (PBASE + 0x00215004)
#define AUX_MU_IO_REG (PBASE + 0x00215040)
#define AUX_MU_IER_REG (PBASE + 0x00215044)
#define AUX_MU_IIR_REG (PBASE + 0x00215048)
#define AUX_MU_LCR_REG (PBASE + 0x0021504C)
#define AUX_MU_MCR_REG (PBASE + 0x00215050)
#define AUX_MU_LSR_REG (PBASE + 0x00215054)
#define AUX_MU_MSR_REG (PBASE + 0x00215058)
#define AUX_MU_SCRATCH (PBASE + 0x0021505C)
#define AUX_MU_CNTL_REG (PBASE + 0x00215060)
#define AUX_MU_STAT_REG (PBASE + 0x00215064)
#define AUX_MU_BAUD_REG (PBASE + 0x00215068)
#define PACTL_CS_REG (PBASE + 0x00204E00)
#define UART0_BASE (PBASE + 0x00201000)
#define UART2_BASE (PBASE + 0x00201400)
#define UART3_BASE (PBASE + 0x00201600)
#define UART4_BASE (PBASE + 0x00201800)
#define UART5_BASE (PBASE + 0x00201a00)
#define UART_DR_OFFSET 0x0
#define UART_FR_OFFSET 0x18
#define UART_IBRD_OFFSET 0x24
#define UART_FBRD_OFFSET 0x28
#define UART_LCRH_OFFSET 0x2C
#define UART_CR_OFFSET 0x30
// The UART_IFLS Register is the interrupt FIFO level select register.
// You can use this register to define the FIFO level that triggers the
// assertion of the combined interrupt signal.
//
// The interrupts are generated based on a transition through a level rather
// than being based on the level. That is, the interrupts are generated when
// the fill level progresses through the trigger level. The bits are reset
// so that the trigger level is when the FIFOs are at the half-way mark.
#define UART_IFLS_OFFSET 0x34
// Setting the appropriate mask bit HIGH enables the interrupt.
#define UART_IMSC_OFFSET 0x38
// Masked Interrupt Status Register
// The UARTMIS Register is the masked interrupt status register. It is a read-only register.
// This register returns the current masked status value of the corresponding interrupt. A
// write has no effect.
// All the bits except for the modem status interrupt bits (bits 3 to 0) are cleared to 0 when
// reset. The modem status interrupt bits are undefined after reset. Table 3-16 lists the
// register bit assignments.
#define UART_MIS_OFFSET 0x40
// The UART_ICR Register is the interrupt clear register.
#define UART_ICR_OFFSET 0x44
// The receive interrupt changes state when one of the following events occurs:
// • If the FIFOs are enabled and the receive FIFO reaches the programmed trigger
// level. When this happens, the receive interrupt is asserted HIGH. The receive
// interrupt is cleared by reading data from the receive FIFO until it becomes less
// than the trigger level, or by clearing the interrupt.
// • If the FIFOs are disabled (have a depth of one location) and data is received
// thereby filling the location, the receive interrupt is asserted HIGH. The receive
// interrupt is cleared by performing a single read of the receive FIFO, or by clearing
// the interrupt.
#define UART_IRQ_RXIM_MASK (1 << 4)
// The receive timeout interrupt is asserted when the receive FIFO is not empty, and no
// more data is received during a 32-bit period. The receive timeout interrupt is cleared
// either when the FIFO becomes empty through reading all the data (or by reading the
// holding register), or when a 1 is written to the corresponding bit of the Interrupt Clear
// Register, UARTICR on page 3-21.
// TODO: 32-bit period - 32 cycles of UART clock?
#define UART_IRQ_RTIM_MASK (1 << 6)
#define UART_RX_MASK (1 << 4)
#endif /*_P_MINI_UART_H */
| 42.753086 | 94 | 0.778516 |
9d73575b9fe5b62dddf1d92f3056df8805a4124c | 8,056 | h | C | toolbox-dssynth/dssynth-tool/benchmark-runner/AACegar/include/SphericalPoints4D.h | SSV-Group/dsverifier | 1daca4704216edf9a360b4a39e00663d94646ad1 | [
"Apache-2.0"
] | 10 | 2016-08-29T19:23:25.000Z | 2020-10-18T22:27:21.000Z | toolbox-dssynth/dssynth-tool/benchmark-runner/AACegar/include/SphericalPoints4D.h | SSV-Group/dsverifier | 1daca4704216edf9a360b4a39e00663d94646ad1 | [
"Apache-2.0"
] | 64 | 2016-09-10T16:29:44.000Z | 2019-01-15T14:31:06.000Z | toolbox-dssynth/dssynth-tool/benchmark-runner/AACegar/include/SphericalPoints4D.h | SSV-Group/dsverifier | 1daca4704216edf9a360b4a39e00663d94646ad1 | [
"Apache-2.0"
] | 5 | 2016-10-09T21:38:41.000Z | 2017-07-05T10:05:32.000Z | -0.055301923610
0.528810740090
-0.753507978839
-0.386686726222
-0.060097404447
0.755693890764
0.133435662689
-0.638365075300
0.799134904595
-0.417881737394
0.431582262314
0.022248790238
0.166627174637
-0.856406408470
0.069230032631
0.483746473668
0.641631174710
-0.580940350431
0.207158753802
-0.455963809534
-0.834037335041
-0.111736093930
-0.447327492215
0.302976705012
-0.677685985271
-0.467134734266
-0.149930807639
-0.547766006913
0.035477969402
0.915610718754
0.399984199418
-0.020272286633
-0.210755101574
-0.291111928652
-0.296019049027
-0.884990878354
0.148760463247
-0.895915119858
0.143494985435
-0.393211917088
-0.069857456757
-0.975804496457
-0.207177978011
-0.001675069223
0.132943788781
0.157872965307
-0.848368432604
0.487517259603
-0.039966103715
0.546881972512
0.835974969796
0.021648754476
0.308386195410
-0.044902135448
-0.306848158808
-0.899291921541
0.453805140184
0.011010287766
-0.479095609209
0.751270301251
0.784335262132
0.436875676050
-0.181444335430
0.401292653051
-0.092585657184
0.256597108151
-0.467557504423
0.840818529904
0.553712423806
-0.700479908361
-0.380252116927
0.241119840074
0.973862952083
0.013822585627
0.102118898523
0.202414468977
0.819463318532
-0.210949153459
-0.370663528963
0.382869262977
-0.075774986287
0.058663084759
-0.695862816394
-0.711752579693
0.103596316734
0.872631082026
-0.322494966222
-0.351823527643
-0.952588033105
-0.016690200583
0.133504458242
-0.272899314802
-0.034156467155
-0.244150197798
-0.938379569383
-0.242214368756
0.378346777386
0.761510452095
0.036881410465
0.524971722052
-0.857354572168
-0.088246777917
-0.428859999317
-0.270619187706
0.130868351654
-0.232062538252
0.788174516300
0.554798508226
-0.597801589771
-0.051343465784
0.158850526387
-0.784068630959
-0.172056445730
0.236675201621
0.847003491608
-0.443809095923
0.913281274621
-0.063272928542
0.183436470756
-0.358140909611
-0.669913702799
0.447758463088
-0.521676482678
0.280324164058
0.284302325743
0.339926862914
-0.045076254908
0.895315612893
-0.118571126656
0.311063631013
-0.163391791140
-0.928699858928
-0.139631793761
-0.389284221371
-0.860221172753
0.298295643802
-0.587710737961
0.358920681883
-0.669075895050
-0.279480731474
0.655757440078
-0.155374059027
0.543769150860
0.500156167748
0.240150748464
0.108594562464
0.614288218604
-0.743763956843
0.706448886814
0.007885346434
0.035332080312
0.706837630388
0.289750375205
0.164846392956
0.494539538093
0.802683643823
0.186422412139
0.722787093928
-0.659573307393
0.088252780572
0.481980799484
-0.757866470591
-0.298696332743
-0.322666116114
0.605710705484
0.475566072603
-0.594254210201
-0.231977122814
0.542068545691
0.810280798621
-0.219196307083
0.039493013554
0.386242301017
-0.646309804480
0.543854702509
0.370570619582
0.787432613921
0.131037466109
0.601873120413
0.022974070907
-0.046212171836
0.000258802539
0.993490364915
0.104121385972
0.918695051819
0.064141696925
-0.373277001781
-0.112024659880
-0.453425568788
-0.249683035171
0.837546360546
-0.174870607746
-0.380709884244
-0.701330116161
-0.596707766605
-0.084474217827
0.243780392985
-0.558015297563
-0.081389365849
-0.789028401775
-0.838099214162
-0.132014686692
0.514056368867
0.126126441901
-0.569743479105
-0.157166725308
-0.239913755747
0.770150880203
-0.065386109590
-0.552833509308
0.821816408252
0.121315946138
0.465154533047
0.015489768631
-0.714086084072
-0.522945878641
-0.248985809458
0.325570905215
0.415627581884
-0.811950346723
-0.170479175435
-0.778434602682
-0.301137802182
-0.523729361587
-0.514933557940
-0.568840117727
-0.464457490472
0.442203110478
0.638787540194
0.225613320664
-0.680923672150
0.278194285956
0.652332988183
-0.370139961745
-0.645045020387
-0.146201925164
-0.650984540555
0.708598224235
-0.009832193652
0.272049650868
-0.186076554730
0.765697306513
0.109823275272
0.605823405612
-0.566949219278
0.120964615451
-0.384728448091
-0.718275828494
-0.462580449625
-0.834330478921
0.122511315432
-0.273684046227
-0.803743368746
0.463202921755
0.370330637943
-0.047904791769
0.603059791864
-0.205601417562
0.640591729482
-0.428589757989
-0.945054138936
0.150525628817
0.051710804774
0.285553326401
-0.414331716678
0.699677291601
0.513964850985
0.273168534288
0.352459907274
0.405463779467
0.137197410345
-0.832194693506
0.210737300033
-0.482286965324
0.480694574962
-0.701371370285
0.381272861494
0.244683610601
0.821668755415
0.345863256456
-0.212125406118
0.705663530219
-0.451917920366
0.502804124338
-0.374805449811
0.646487839088
-0.330917399905
-0.576253436558
-0.084244693712
-0.917844269740
0.380520621392
0.075291332712
-0.566741173889
-0.636670703926
0.516774877309
0.079991141784
-0.868971934200
0.432385067998
-0.191507381279
-0.145793873195
-0.182089457070
-0.651667839652
0.469111886588
0.567544266334
0.338752803169
-0.691900645794
0.606371730336
-0.197061816050
0.710418858243
-0.512975292292
0.097768060211
0.471808013660
0.143289103577
0.675705865586
0.551260377821
0.467976294115
-0.689362978915
-0.418231233863
0.409743324779
-0.426581441371
0.846412383878
0.507503290950
0.150280968794
-0.058669553520
0.028167745244
-0.756698624050
-0.478325238506
0.444768183099
-0.450763123037
-0.325118217045
-0.657173246877
-0.509150346601
0.659303632011
0.352660969000
0.465683042491
-0.473379621127
-0.344125083794
0.793374241238
-0.499861815508
-0.047680241612
0.551416105611
-0.129509167456
0.197519779985
-0.800095988324
0.176321362140
0.629864310865
0.606648364078
-0.451840114988
0.879048821740
-0.453015066353
-0.128234626594
-0.074875891967
0.419835921306
-0.317647215911
-0.769315798356
0.361927130518
0.443785084330
-0.264071226056
0.852781681942
0.078003778364
0.014613987701
0.974863663130
-0.136976717850
0.175113244614
-0.284796953000
-0.203582823174
0.612058934438
-0.709104075891
0.332785088154
0.548812280648
-0.491387285876
0.588725488655
-0.542365142553
-0.119819121926
-0.831499064157
-0.009629977699
-0.246980370408
-0.600114182222
-0.066940642302
0.757880343681
-0.241662079866
0.405874869847
-0.871810961164
0.129655995528
-0.800951445808
-0.551806266292
-0.232347312047
0.001162979986
0.523645292742
-0.839674513540
0.138668059183
0.038903573915
-0.669843885156
0.130181476061
0.579956483196
-0.444985876639
-0.527448085820
0.252330415638
0.805860840879
0.093360501531
-0.062772258815
-0.108214053863
-0.050471768220
0.990859204268
-0.230110827756
0.298034134458
0.301914980815
0.875826470259
0.501752775733
0.637512068903
0.584263054709
0.021428881189
0.341204651818
-0.494532410173
-0.230112543920
0.765549017370
-0.170487706071
0.257259932725
0.774356721367
0.552379341727
0.677805688228
0.411544569339
0.377620755673
0.478135003255
-0.806774329914
-0.384030772213
0.102685421725
0.437139852622
-0.212858839922
-0.670749328844
0.603071195562
-0.375621598428
0.198441629117
-0.480849304261
-0.620130634749
-0.587233226470
0.183031654528
-0.683997100246
-0.703965396114
-0.055498660969
0.243349523089
-0.380265935531
0.320621249554
0.832694927462
0.259786653399
0.218546315226
-0.938066828155
-0.069130519543
0.358019123401
0.216182003934
0.880080626189
-0.224823797364
-0.658629241369
0.219215016883
0.473328482413
0.542321349869
-0.656453819628
0.486859365022
0.143749610202
-0.558007518724
-0.266609829411
-0.579281933067
0.179203500730
-0.749158024858
-0.380177530117
0.667668238985
0.552002114062
-0.324002830722
-0.451352791513
-0.227213406388
0.317293986494
0.802483178444
-0.419877712983
0.045523228630
-0.742644310186
0.519720858099
0.730113517097
-0.252043972079
-0.282173863381
-0.569021967164
-0.429598718649
-0.241100991012
0.755694994715
0.431555706752
0.088459403641
-0.269491938401
0.883500455721
-0.372794814590
-0.479191222549
-0.827095639277
0.025547634003
0.292636112122
-0.532770888758
0.407725599349
-0.150215535221
0.726188893268
0.465536023141
0.774749572067
0.133626625898
-0.406427406299
0.003391341234
-0.115161800916
0.199844447712
-0.973030552004
0.758900754913
0.354829404942
-0.138452311708
-0.528201377284
0.307098093147
0.477259736765
-0.437508904797
-0.697495421542
-0.381032381638
0.902979627845
0.043976538531
-0.193670286566
-0.104852743503
-0.309424862208
-0.541782158601
0.774425109000 | 15.492308 | 15 | 0.839126 |
a048f9ba65d7ff0f34a1e848b92009bfc1e4983c | 1,769 | c | C | error/error.c | Arden97/ifj2018 | 21928448cc833ef6842fd6986cc7d4e8099a8f27 | [
"MIT"
] | null | null | null | error/error.c | Arden97/ifj2018 | 21928448cc833ef6842fd6986cc7d4e8099a8f27 | [
"MIT"
] | null | null | null | error/error.c | Arden97/ifj2018 | 21928448cc833ef6842fd6986cc7d4e8099a8f27 | [
"MIT"
] | null | null | null | ///////////////////////////////////////////////////////////////////////////////////
// School: Brno University of Technology, Faculty of Information Technology //
// Course: Formal Languages and Compilers //
// Project: IFJ18 //
// Module: Error states //
// Authors: Artem Denisov (xdenis00) //
// Volodymyr Piskun (xpisku03) //
///////////////////////////////////////////////////////////////////////////////////
#include "error.h"
char *error_msg(int error_code){
char *err_msg;
switch(error_code){
case LEXICAL_ERROR:
err_msg = "Lexical error";
break;
case SYNTAX_ERROR:
err_msg = "Syntax error";
break;
case DEFINITION_ERROR:
err_msg = "Undefined/redefined function/variable";
break;
case TYPE_ERROR:
err_msg = "";
break;
case ARGS_ERROR:
err_msg = "ArgumentsError";
break;
case SEMANTIC_ERROR:
err_msg = "SemanticError";
break;
case DIVBYZERO_ERROR:
err_msg = "DivisionByZeroError";
break;
case INTERNAL_ERROR:
err_msg = "InternalError";
break;
default:
err_msg = "UnknownError";
break;
}
return err_msg;
}
void error(int error_code, const char *format, ...){
fprintf(stderr,RESET);
printf(RESET);
fprintf(stderr, "%s%s. ", KRED, error_msg(error_code));
va_list ap;
va_start (ap, format);
vfprintf(stderr, format, ap);
va_end (ap);
fprintf(stderr, "%s\n", RESET);
// gc_dispose();
exit(error_code);
}
| 26.014706 | 83 | 0.472018 |
ae2274dbd305120b29f4ae8a86bd638cb1ce053d | 1,820 | h | C | release/src/linux/linux/arch/i386/math-emu/control_w.h | enfoTek/tomato.linksys.e2000.nvram-mod | 2ce3a5217def49d6df7348522e2bfda702b56029 | [
"FSFAP"
] | 278 | 2015-11-03T03:01:20.000Z | 2022-01-20T18:21:05.000Z | release/src/linux/linux/arch/i386/math-emu/control_w.h | unforgiven512/tomato | 96f09fab4929c6ddde5c9113f1b2476ad37133c4 | [
"FSFAP"
] | 374 | 2015-11-03T12:37:22.000Z | 2021-12-17T14:18:08.000Z | arch/x86/math-emu/control_w.h | KylinskyChen/linuxCore_2.6.24 | 11e90b14386491cc80477d4015e0c8f673f6d020 | [
"MIT"
] | 96 | 2015-11-22T07:47:26.000Z | 2022-01-20T19:52:19.000Z | /*---------------------------------------------------------------------------+
| control_w.h |
| |
| Copyright (C) 1992,1993 |
| W. Metzenthen, 22 Parker St, Ormond, Vic 3163, |
| Australia. E-mail billm@vaxc.cc.monash.edu.au |
| |
+---------------------------------------------------------------------------*/
#ifndef _CONTROLW_H_
#define _CONTROLW_H_
#ifdef __ASSEMBLY__
#define _Const_(x) $##x
#else
#define _Const_(x) x
#endif
#define CW_RC _Const_(0x0C00) /* rounding control */
#define CW_PC _Const_(0x0300) /* precision control */
#define CW_Precision Const_(0x0020) /* loss of precision mask */
#define CW_Underflow Const_(0x0010) /* underflow mask */
#define CW_Overflow Const_(0x0008) /* overflow mask */
#define CW_ZeroDiv Const_(0x0004) /* divide by zero mask */
#define CW_Denormal Const_(0x0002) /* denormalized operand mask */
#define CW_Invalid Const_(0x0001) /* invalid operation mask */
#define CW_Exceptions _Const_(0x003f) /* all masks */
#define RC_RND _Const_(0x0000)
#define RC_DOWN _Const_(0x0400)
#define RC_UP _Const_(0x0800)
#define RC_CHOP _Const_(0x0C00)
/* p 15-5: Precision control bits affect only the following:
ADD, SUB(R), MUL, DIV(R), and SQRT */
#define PR_24_BITS _Const_(0x000)
#define PR_53_BITS _Const_(0x200)
#define PR_64_BITS _Const_(0x300)
#define PR_RESERVED_BITS _Const_(0x100)
/* FULL_PRECISION simulates all exceptions masked */
#define FULL_PRECISION (PR_64_BITS | RC_RND | 0x3f)
#endif /* _CONTROLW_H_ */
| 39.565217 | 79 | 0.533516 |
1604cd6e7fc7ce1d1ec639a67771ce47f7d8bb88 | 5,662 | h | C | RMF01.h | bartlomiej-zdrojewski/RMF01 | 598d02de415e153a5e066de2445ddb944b4fd405 | [
"MIT"
] | null | null | null | RMF01.h | bartlomiej-zdrojewski/RMF01 | 598d02de415e153a5e066de2445ddb944b4fd405 | [
"MIT"
] | null | null | null | RMF01.h | bartlomiej-zdrojewski/RMF01 | 598d02de415e153a5e066de2445ddb944b4fd405 | [
"MIT"
] | null | null | null | #ifndef RMF01_MODULE
#define RMF01_MODULE
#include <avr/io.h>
#include <stdint.h>
#include <math.h>
/*
#define RMF01_SCK_DDR DDRB
#define RMF01_SDI_DDR DDRB
#define RMF01_SDO_DDR DDRB
#define RMF01_SEL_DDR DDRB
#define RMF01_INT_DDR DDRB
#define RMF01_SCK_PORT PORTB
#define RMF01_SDI_PORT PORTB
#define RMF01_SDO_PORT PORTB
#define RMF01_SEL_PORT PORTB
#define RMF01_INT_PORT PORTB
#define RMF01_SCK_PIN 0
#define RMF01_SDI_PIN 0
#define RMF01_SDO_PIN 0
#define RMF01_SEL_PIN 0
#define RMF01_INT_PIN 0
*/
#define RMF01_SCK_DDR DDRB
#define RMF01_SDI_DDR DDRB
#define RMF01_SDO_DDR DDRB
#define RMF01_SEL_DDR DDRB
#define RMF01_INT_DDR DDRB
#define RMF01_SCK_PORT PORTB
#define RMF01_SDI_PORT PORTB
#define RMF01_SDO_PORT PORTB
#define RMF01_SEL_PORT PORTB
#define RMF01_INT_PORT PORTB
#define RMF01_SCK_PIN 0
#define RMF01_SDI_PIN 0
#define RMF01_SDO_PIN 0
#define RMF01_SEL_PIN 0
#define RMF01_INT_PIN 0
namespace RMF01 {
enum BAND {
BAND_315_MHZ,
BAND_433_MHZ,
BAND_868_MHZ,
BAND_915_MHZ
};
enum BANDWIDTH {
BANDWIDTH_67_KHZ,
BANDWIDTH_134_KHZ,
BANDWIDTH_200_KHZ,
BANDWIDTH_270_KHZ,
BANDWIDTH_340_KHZ,
BANDWIDTH_400_KHZ
};
enum LNA_GAIN {
LNA_GAIN_0_DBM,
LNA_GAIN_MINUS_6_DBM,
LNA_GAIN_MINUS_14_DBM,
LNA_GAIN_MINUS_20_DBM
};
enum SIGNAL_THRESHOLD { // To obtain the actual signal threshold, you have to add the LNA gain value.
SIGNAL_THRESHOLD_MINUS_73_DBM, // Equal to 5.01 * 10^(-8) mW
SIGNAL_THRESHOLD_MINUS_79_DBM, // Equal to 1.26 * 10^(-8) mW
SIGNAL_THRESHOLD_MINUS_85_DBM, // Equal to 3.16 * 10^(-9) mW
SIGNAL_THRESHOLD_MINUS_91_DBM, // Equal to 7.94 * 10^(-10) mW
SIGNAL_THRESHOLD_MINUS_97_DBM, // Equal to 2.00 * 10^(-10) mW
SIGNAL_THRESHOLD_MINUS_103_DBM // Equal to 5.01 * 10^(-11) mW
};
enum SIGNAL_DEVATION {
SIGNAL_DEVATION_7_STEPS,
SIGNAL_DEVATION_15_STEPS,
SIGNAL_DEVATION_31_STEPS,
SIGNAL_DEVATION_UNLIMITED
};
enum AFC {
AFC_POWERUP,
AFC_LOW_SIGNAL,
AFC_STEADY
};
enum VDI {
VDI_DIGITAL_RSSI,
VDI_DATA_QUALITY_DETECTOR,
VDI_DIGITAL_RSSI_AND_DATA_QUALITY_DETECTOR
};
enum DQF {
DQF_0,
DQF_1,
DQF_2,
DQF_3,
DQF_4, // Default data quality factor
DQF_5,
DQF_6,
DQF_7
};
enum INTERRUPT {
INTERRUPT_NONE = 0x00,
INTERRUPT_WAKE_UP = 0x01,
INTERRUPT_LOW_VOLTAGE = 0x02
};
enum PROFILE {
PROFILE_AVERANGE, // Parameters are medium bandwidth, medium gain, medium signal threshold, medium signal devation, frequency control on low signal, digital rssi and data quality detector as data indicators, high accuracy mode.
PROFILE_LOW_POWER, // Parameters are medium bandwidth, medium gain, medium signal threshold, low signal devation, steady frequency control, digital rssi as data indicator, low accuracy mode, low power mode.
PROFILE_LOW_NOISE, // Parameters are narrow bandwidth, low gain, high signal threshold, low signal devation, frequency control on power up, digital rssi and data quality detector as data indicators, and high accuracy mode.
PROFILE_LONG_RANGE, // Parameters are narrow bandwidth, high gain, low signal threshold, high signal devation, frequency control on low signal, digital rssi and data quality detector as data indicators, high accuracy mode. Baud (bitrate) value should be as low as possible.
PROFILE_MULTIPLE_TRANSMITTERS // Parameters are wide bandwidth, medium gain, medium threshold, high signal devation, frequency control on low signal, digital rssi and data quality detector as data indicators, low accuracy mode.
};
struct DataStruct {
bool Valid;
uint8_t Data;
};
struct StatusStruct {
bool Interrupt; // Preprogrammed interrupt occurred
bool WakeUp; // Wake-up interrupt occurred
bool LowVoltage; // Low voltage interrupt occurred
bool BufferOverflow; // Buffer overflow interrupt occurred
bool BufferEmpty; // Data buffer is empty
bool StrongSignal; // Digital RSSI detected a strong signal
bool GoodQualitySignal; // Data Quality Detector detected a good quality signal
bool FrequencyToggling; // Frequency controller is in toggling cycle
bool FrequencyStable; // Frequency is stable
uint8_t SignalDevation; // Signal frecuency devation in steps
};
void Init ( BAND Band, BANDWIDTH Bandwidth, uint16_t Frequency, uint8_t Baud, LNA_GAIN Gain, SIGNAL_THRESHOLD Threshold, SIGNAL_DEVATION Devation, AFC FrequencyControl, VDI DataIndicator, DQF DataQualityFactor, bool HighAccuracyMode, bool LowPowerMode, uint16_t WakeUpTime, uint8_t DutyCycle, uint8_t LowVoltage, uint8_t Interrupt, bool InitSPI );
void Init ( PROFILE Profile, BAND Band, uint16_t Frequency, uint8_t Baud, uint16_t WakeUpTime = 0x0001, uint8_t DutyCycle = 0x00, uint8_t LowVoltage = 0xE0, uint8_t Interrupt = INTERRUPT_NONE, bool InitSPI = true );
uint8_t Command ( uint8_t Data );
bool IsReady ( );
void Update ( );
void Reset ( );
DataStruct GetData ( );
StatusStruct GetStatus ( );
uint16_t GetFrequency ( BAND Band, uint32_t Hertz );
uint8_t GetBaud ( uint32_t Bitrate );
uint32_t GetBitrate ( uint8_t Baud );
uint16_t GetWakeUpTime ( uint32_t Milliseconds );
uint8_t GetDutyCycle ( uint32_t Milliseconds, uint8_t Percent );
uint8_t GetLowVoltage ( uint16_t Millivolts );
extern uint8_t Data;
extern uint16_t Status;
}
#endif
| 29.336788 | 349 | 0.717238 |
8bdfd85e4cf055ec3475039d00e1e67af2b0c91e | 1,290 | h | C | main.h | mal-tee/rayzor | f730d2654e58acb3f327553c4748aa8c137dba4a | [
"MIT"
] | null | null | null | main.h | mal-tee/rayzor | f730d2654e58acb3f327553c4748aa8c137dba4a | [
"MIT"
] | null | null | null | main.h | mal-tee/rayzor | f730d2654e58acb3f327553c4748aa8c137dba4a | [
"MIT"
] | null | null | null | #ifndef RAYZOR_MAIN_H
#define RAYZOR_MAIN_H
#define _USE_MATH_DEFINES
#include <cmath>
#include <iostream>
#include <iomanip>
#include <TGUI/TGUI.hpp>
#include "enemy.h"
#include "Level.h"
#include <cfloat>
#include <sstream>
#include <fstream>
#include "Wall.h"
#include "helper.h"
#include "entitiy.h"
#include "TileMap.h"
#define RAYCOUNT 1500
static const int MAX_JUMPS = 5;
using namespace sf;
using namespace std;
void generate_walls(const vector<Wall> &walls, VertexArray &draw_lines);
void raycast(Vector2f origin, std::vector<Wall> &walls, VertexArray &draw_lines, float window = M_2PI, float angle = 0,
int raycount = RAYCOUNT, bool shot = false, float ray_length = 1500);
void update_player(const std::vector<Wall> &walls, Player &player);
std::vector<TileMap> load_map(const std::string &name);
float delta_speed = 17;
void draw_coins(RenderWindow &window, const vector<Coin> &coins);
void prepareGameGUI(tgui::Gui &gui);
void prepareClearedGUI(tgui::Gui &gui);
void preparePauseGUI(tgui::Gui &gui);
void prepareMainMenuGUI(tgui::Gui &gui);
void prepareWonGUI(tgui::Gui &gui);
void startGame(tgui::Gui &gui, bool restart = false);
bool isKeyPressed(Keyboard::Key key);
enum gamestate {
running, paused, mainmenu, won
};
#endif //RAYZOR_MAIN_H
| 22.631579 | 119 | 0.739535 |
276393bb64bb90782ef94dcd4c24b86c12187495 | 1,271 | h | C | third_party/blink/renderer/modules/webaudio/audio_worklet_object_proxy.h | zealoussnow/chromium | fd8a8914ca0183f0add65ae55f04e287543c7d4a | [
"BSD-3-Clause-No-Nuclear-License-2014",
"BSD-3-Clause"
] | 14,668 | 2015-01-01T01:57:10.000Z | 2022-03-31T23:33:32.000Z | third_party/blink/renderer/modules/webaudio/audio_worklet_object_proxy.h | zealoussnow/chromium | fd8a8914ca0183f0add65ae55f04e287543c7d4a | [
"BSD-3-Clause-No-Nuclear-License-2014",
"BSD-3-Clause"
] | 86 | 2015-10-21T13:02:42.000Z | 2022-03-14T07:50:50.000Z | third_party/blink/renderer/modules/webaudio/audio_worklet_object_proxy.h | zealoussnow/chromium | fd8a8914ca0183f0add65ae55f04e287543c7d4a | [
"BSD-3-Clause-No-Nuclear-License-2014",
"BSD-3-Clause"
] | 5,941 | 2015-01-02T11:32:21.000Z | 2022-03-31T16:35:46.000Z | // Copyright 2017 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef THIRD_PARTY_BLINK_RENDERER_MODULES_WEBAUDIO_AUDIO_WORKLET_OBJECT_PROXY_H_
#define THIRD_PARTY_BLINK_RENDERER_MODULES_WEBAUDIO_AUDIO_WORKLET_OBJECT_PROXY_H_
#include "third_party/blink/renderer/core/workers/threaded_worklet_object_proxy.h"
namespace blink {
class AudioWorkletGlobalScope;
class AudioWorkletMessagingProxy;
class AudioWorkletObjectProxy final : public ThreadedWorkletObjectProxy {
public:
AudioWorkletObjectProxy(AudioWorkletMessagingProxy*,
ParentExecutionContextTaskRunners*,
float context_sample_rate);
// Implements WorkerReportingProxy.
void DidCreateWorkerGlobalScope(WorkerOrWorkletGlobalScope*) override;
void WillDestroyWorkerGlobalScope() override;
void SynchronizeProcessorInfoList();
private:
CrossThreadWeakPersistent<AudioWorkletMessagingProxy>
GetAudioWorkletMessagingProxyWeakPtr();
CrossThreadPersistent<AudioWorkletGlobalScope> global_scope_;
float context_sample_rate_;
};
} // namespace blink
#endif // THIRD_PARTY_BLINK_RENDERER_MODULES_WEBAUDIO_AUDIO_WORKLET_OBJECT_PROXY_H_
| 32.589744 | 84 | 0.817467 |
e9c44ab2a7f724780e36d60f744a9d9830032ad0 | 532 | h | C | MdeModulePkg/Core/Dxe/Image/Image.h | nicklela/edk2 | dfafa8e45382939fb5dc78e9d37b97b500a43613 | [
"Python-2.0",
"Zlib",
"BSD-2-Clause",
"MIT",
"BSD-2-Clause-Patent",
"BSD-3-Clause"
] | 3,861 | 2019-09-04T10:10:11.000Z | 2022-03-31T15:46:28.000Z | MdeModulePkg/Core/Dxe/Image/Image.h | nicklela/edk2 | dfafa8e45382939fb5dc78e9d37b97b500a43613 | [
"Python-2.0",
"Zlib",
"BSD-2-Clause",
"MIT",
"BSD-2-Clause-Patent",
"BSD-3-Clause"
] | 461 | 2019-09-24T10:26:56.000Z | 2022-03-26T13:22:32.000Z | MdeModulePkg/Core/Dxe/Image/Image.h | nicklela/edk2 | dfafa8e45382939fb5dc78e9d37b97b500a43613 | [
"Python-2.0",
"Zlib",
"BSD-2-Clause",
"MIT",
"BSD-2-Clause-Patent",
"BSD-3-Clause"
] | 654 | 2019-09-05T11:42:37.000Z | 2022-03-30T02:42:32.000Z | /** @file
Data structure and functions to load and unload PeImage.
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IMAGE_H_
#define _IMAGE_H_
//
// Private Data Types
//
#define IMAGE_FILE_HANDLE_SIGNATURE SIGNATURE_32('i','m','g','f')
typedef struct {
UINTN Signature;
BOOLEAN FreeBuffer;
VOID *Source;
UINTN SourceSize;
} IMAGE_FILE_HANDLE;
#endif
| 21.28 | 72 | 0.614662 |
eb3f1d8ee8dad9cd1da666f3a1f31ebb31a03365 | 553 | h | C | tasmota/Sonoff-Tasmota-6.2.1/lib/IRremoteESP8266-2.2.1.02/src/IRutils.h | zorcec/SARAH | c7936ce9467fb11594b6ae4a937d6766060bec05 | [
"MIT"
] | null | null | null | tasmota/Sonoff-Tasmota-6.2.1/lib/IRremoteESP8266-2.2.1.02/src/IRutils.h | zorcec/SARAH | c7936ce9467fb11594b6ae4a937d6766060bec05 | [
"MIT"
] | null | null | null | tasmota/Sonoff-Tasmota-6.2.1/lib/IRremoteESP8266-2.2.1.02/src/IRutils.h | zorcec/SARAH | c7936ce9467fb11594b6ae4a937d6766060bec05 | [
"MIT"
] | null | null | null | #ifndef IRUTILS_H_
#define IRUTILS_H_
// Copyright 2017 David Conran
#ifndef UNIT_TEST
#include <Arduino.h>
#endif
#define __STDC_LIMIT_MACROS
#include <stdint.h>
#ifndef ARDUINO
#include <string>
#endif
uint64_t reverseBits(uint64_t input, uint16_t nbits);
#ifdef ARDUINO // Arduino's & C++'s string implementations can't co-exist.
String uint64ToString(uint64_t input, uint8_t base = 10);
#else
std::string uint64ToString(uint64_t input, uint8_t base = 10);
#endif
void serialPrintUint64(uint64_t input, uint8_t base = 10);
#endif // IRUTILS_H_
| 23.041667 | 75 | 0.770344 |
8f122be3bc4b50483033dc0748cd6b63293e0011 | 1,572 | h | C | hardware/cores/mididuino/midi_link_desc.h | anupam19/mididuino | 27c30f586a8d61381309434ed05b4958c7727402 | [
"BSD-3-Clause"
] | null | null | null | hardware/cores/mididuino/midi_link_desc.h | anupam19/mididuino | 27c30f586a8d61381309434ed05b4958c7727402 | [
"BSD-3-Clause"
] | null | null | null | hardware/cores/mididuino/midi_link_desc.h | anupam19/mididuino | 27c30f586a8d61381309434ed05b4958c7727402 | [
"BSD-3-Clause"
] | null | null | null | #ifndef MIDI_LINK_DESC_H__
#define MIDI_LINK_DESC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "usb.h"
#include "usb_midi.h"
#define USB_ENABLE_HID 1
#define USB_VERSION 0x0200 // XXX ??
/* XXXX replace */
#define USB_ID_VENDOR 0x1ACC
#define USB_ID_PRODUCT 0x0010 // mididuino
#define USB_ID_RELEASE 0x1000
#define USB_APP_CONFIG_NUM 1
#define MIDI_EP_IN 2
#define MIDI_EP_OUT 2
#define D12_MIDI_EP_IN 5
#define D12_MIDI_EP_OUT 4
#define USB_STR_MANUFACTURER 1
#define USB_STR_PRODUCT 1
/* application specific configuration setup */
typedef struct {
/* standard things */
usb_configuration_descriptor_t config;
usb_interface_descriptor_t ac_interface;
usb_audiocontrol_descriptor_t ac_specific_interface;
usb_interface_descriptor_t ms_interface;
usb_midistreaming_descriptor_t ms_specific_interface;
usb_midistreaming_injack_descriptor_t ms_injack_emb_descriptor;
usb_midistreaming_injack_descriptor_t ms_injack_ext_descriptor;
usb_midistreaming_outjack_descriptor_t ms_outjack_emb_descriptor;
usb_midistreaming_outjack_descriptor_t ms_outjack_ext_descriptor;
/* device specific endpoints */
usb_endpoint_descriptor_t out_ep;
usb_midistreaming_ep_descriptor_t ms_out_ep;
usb_endpoint_descriptor_t int_ep;
usb_midistreaming_ep_descriptor_t ms_int_ep;
} PACKED usb_app_config_t;
extern const PROGMEM usb_app_config_t usb_configuration_descriptor;
#ifdef __cplusplus
}
#endif
#endif /* MIDI_LINK_DESC_H__ */
| 26.644068 | 68 | 0.776718 |
6a32382bbb64490f1d84f9286aa4868ebc826e18 | 450 | c | C | W8/300791_maksymilian_polarczyk/zad2/zad2.c | T3sT3ro/ASK | 34ff7ee4752e0d904acbe33249d367e69c7fe6a7 | [
"MIT"
] | null | null | null | W8/300791_maksymilian_polarczyk/zad2/zad2.c | T3sT3ro/ASK | 34ff7ee4752e0d904acbe33249d367e69c7fe6a7 | [
"MIT"
] | null | null | null | W8/300791_maksymilian_polarczyk/zad2/zad2.c | T3sT3ro/ASK | 34ff7ee4752e0d904acbe33249d367e69c7fe6a7 | [
"MIT"
] | null | null | null | #include <stdio.h>
#include <stdlib.h>
typedef struct {
unsigned long lcm, gcd;
} result_t;
result_t lcm_gcd(unsigned long , unsigned long);
int main(int argc, char **argv){
if(argc < 3)
return EXIT_FAILURE;
unsigned long a = strtoul(argv[1], NULL, 10);
unsigned long b = strtoul(argv[2], NULL, 10);
result_t x = lcm_gcd(a,b);
printf("a=%lu b=%lu gcd=%lu lcm=%lu\n", a, b, x.gcd, x.lcm);
return EXIT_SUCCESS;
}
| 18.75 | 63 | 0.628889 |
3a729126992eddf4d9585a22b42a4347c63324cd | 1,212 | c | C | sdcard_gpio_spi/helper.c | paulwratt/RPi_Baremetal | fb71effc3643ba418b804d9f7d4c33d4858d1230 | [
"Unlicense"
] | 3 | 2018-07-29T22:46:11.000Z | 2020-04-03T20:36:25.000Z | sdcard_gpio_spi/helper.c | paulwratt/RPi_Baremetal | fb71effc3643ba418b804d9f7d4c33d4858d1230 | [
"Unlicense"
] | null | null | null | sdcard_gpio_spi/helper.c | paulwratt/RPi_Baremetal | fb71effc3643ba418b804d9f7d4c33d4858d1230 | [
"Unlicense"
] | 1 | 2018-08-13T05:37:59.000Z | 2018-08-13T05:37:59.000Z | #include "helper.h"
#include "mylib.h"
uint32_t cut_bits(uint8_t *csd, int32_t start, int32_t end)
{
uint32_t ret = 0;
int32_t shift = 0;
int32_t bits = 0;
for(int32_t i = 0; i < 16 && 0 <= end; i++) {
uint8_t mask;
if (start < 8) {
if (8 <= end) {
mask = 0xff;
bits = 8 - start;
} else {
mask = ((0xFF << (7 - end)) & 0xFF) >> (7 - end);
bits = end - start + 1;
}
ret |= ((csd[15 - i] >> start) & mask) << shift;
shift += bits;
start = 0;
end -= 8;
} else {
start -= 8;
end -= 8;
}
/* printf("Ret: %4x, mask: %x, start: %d, end: %d, shift: %d\n", ret, mask, start, end, shift); */
}
return ret;
}
void cut_bit_test()
{
uint8_t csd[16];
csd[3] = csd[4] = 0xff;
int32_t result = cut_bits(csd, 22, 37);
if ( result == 0xFFFC ) {
printf("Cut bits test pass\n");
} else {
printf("Cut bits test fail. Expected %d, actual %d\n", 0xFFFC, result);
}
result = cut_bits(csd, 22, 35);
if ( result == 0x3FFC ) {
printf("Cut bits test pass\n");
} else {
printf("Cut bits test fail. Expected %d, actual %d\n", 0x3FFC, result);
}
}
| 23.307692 | 102 | 0.494224 |
16a907d0a5738ce9d81285b90994fe2e0d003c8f | 1,156 | c | C | d/deku/open/castle/castle2.c | Dbevan/SunderingShadows | 6c15ec56cef43c36361899bae6dc08d0ee907304 | [
"MIT"
] | 13 | 2019-07-19T05:24:44.000Z | 2021-11-18T04:08:19.000Z | d/deku/open/castle/castle2.c | Dbevan/SunderingShadows | 6c15ec56cef43c36361899bae6dc08d0ee907304 | [
"MIT"
] | 4 | 2021-03-15T18:56:39.000Z | 2021-08-17T17:08:22.000Z | d/deku/open/castle/castle2.c | Dbevan/SunderingShadows | 6c15ec56cef43c36361899bae6dc08d0ee907304 | [
"MIT"
] | 13 | 2019-09-12T06:22:38.000Z | 2022-01-31T01:15:12.000Z | // castle2.c
// Pator@ShadowGate
// Tue Apr 11 05:25:17 1995
#include <castle.h>
inherit ROOM;
void create() {
::create();
set_terrain(VILLAGE);
set_travel(DIRT_ROAD);
set_indoors(0);
set_author("pator");
set_light(2);
set_short("Between the castle gates");
set("day long",
@DAY
You are standing between the gates. You see the guardhouse at your left. To the west there are some guardquarters and to the east there are the stables.
DAY
);
set("night long",
@NIGHT
You are standing between the gates. Some torches light this area and so you can see all there is to see : The stables to the east and the guardquarters to your west.
NIGHT
);
set_smell("default","You smell the stables here and a scent of beans");
set_listen("default","Nothing much except some birds singing.");
set_listen("quarters","You hear distinct sleeping noises coming from the quarters !");
set_exits(([
"south" : CASTLE+"castle1",
"north" : CASTLE+"castle3",
"east" : CASTLE+"castleE1",
"west" : CASTLE+"castleW1"
] ));
}
reset(){
::reset();
if (!present("guard")) {
new(CASTLE+MONSTERS+"cas_guard1")->move(this_object());
}
}
| 26.272727 | 165 | 0.687716 |
362eb779dc0cc9c0beb2e02e137ee4e0f4ad2a56 | 2,993 | h | C | ShapeLab/MainWindow.h | YingGwan/collisionAwareSOROSimulator | ab9399b19f1c734974cf46429138c653f1a5ac26 | [
"MIT"
] | 2 | 2022-03-10T05:19:46.000Z | 2022-03-14T08:19:54.000Z | ShapeLab/MainWindow.h | YingGwan/collisionAwareSOROSimulator | ab9399b19f1c734974cf46429138c653f1a5ac26 | [
"MIT"
] | null | null | null | ShapeLab/MainWindow.h | YingGwan/collisionAwareSOROSimulator | ab9399b19f1c734974cf46429138c653f1a5ac26 | [
"MIT"
] | null | null | null | #ifndef MAINWINDOW_H
#define MAINWINDOW_H
#include <QMainWindow>
#include <QSignalMapper>
#include <QStandardItemModel>
#include <QTimer>
#include "../GLKLib/GLKLib.h"
#include "../QMeshLib/PolygenMesh.h"
#include "meshOperation.h"
#include <iostream>
#include <fstream> // std::ifstream
#include <cstring>
#include "ui_MainWindow.h"
#include "AABB.h"
#include "DeformTet.h"
#include "soroPneumaticKinematics.h"
#include "MannequinMacro.h"
namespace Ui {
class MainWindow;
}
class MainWindow : public QMainWindow
{
Q_OBJECT
public:
explicit MainWindow(QWidget *parent = 0);
~MainWindow();
private:
Ui::MainWindow *ui;
GLKLib *pGLK;
GLKObList polygenMeshList;
private:
void createActions();
void createTreeView();
void createActions_SoftRobotFunction();
PolygenMesh *getSelectedPolygenMesh();
QSignalMapper *signalMapper;
QStandardItemModel *treeModel;
protected:
void dragEnterEvent(QDragEnterEvent *event);
void dropEvent(QDropEvent *event);
private slots:
void open();
void save();
void signalNavigation(int flag);
void shiftToOrigin();
void updateTree();
void on_pushButton_clearAll_clicked();
void on_treeView_clicked(const QModelIndex &index);
void generateTetraMeshbyTetgen();
PolygenMesh* _buildPolygenMesh(std::string name);
void split_Show_TET_Mesh();
public slots:
void soroGenerateTetraMesh_withChamber();
void soroSimulation_highExpandingModel();
void soroSimulation_dataGeneration();
void collisionCheckingByAABBTree();
private:
void MainWindow::inputSoftRobotModel(
QMeshPatch* body_init, QMeshPatch* chamber_init, QMeshPatch* tetMesh,
meshOperation* meshOperator, std::string modelName);
void MainWindow::inputSoftRobotModelWithShifting(
QMeshPatch* body_init, QMeshPatch* chamber_init, QMeshPatch* tetMesh,
meshOperation* meshOperator, std::string modelName, std::string modelIdx, Eigen::Vector3d shift);
double actuatorPara_twisting = 2.5; //.2.5 for twisting, 5.0 for expanding, 3.0 for finger
int iterationTimeSOROSimulation = 1;
public:
void InputEnvironmentObstacle(void);
//QMeshPatch
QMeshPatch* body_init;
QMeshPatch* chamber_init;
QMeshPatch* tetMesh;
/*Free-form Membrane Simulation*/
public:
void SignalSlotConnection(void);
//size is MAN_CHAMBER_SIZE
QVector<QMeshPatch*> ChamberArray_body; //body element
QVector<QMeshPatch*> ChamberArray_chamber; //actuation element: chamber
QVector<QMeshPatch*> ChamberArray_tet; //
QMeshPatch* _freeformMem; //ball obstacle
public slots:
void InputFreeFormMembrane(void);
void GenerateChamberTetMesh(void);
void ChamberDeformation(void);
void InputMem(void);
void CollisionChecking(void);
void CollisionResponse(void);
void MoveBall(void);
void TrajGeneration(void);
void ApplyRotation(void);
};
#endif // MAINWINDOW_H
| 24.333333 | 105 | 0.724023 |
d9d97f6f10c67b2855f26c161bb0d9375589063b | 1,014 | h | C | Classes/NSMutableArray+ZYExtension.h | Eyshen/ios-zy-common | eea7631797b7898b5c4948bf2d8ed14d91697057 | [
"MIT"
] | null | null | null | Classes/NSMutableArray+ZYExtension.h | Eyshen/ios-zy-common | eea7631797b7898b5c4948bf2d8ed14d91697057 | [
"MIT"
] | null | null | null | Classes/NSMutableArray+ZYExtension.h | Eyshen/ios-zy-common | eea7631797b7898b5c4948bf2d8ed14d91697057 | [
"MIT"
] | null | null | null | //
// NSMutableArray+ZYExtension.h
//
// _______________ __
// /\______ / \ \ / /
// \/___ / / \ \ / /
// / / / \ \/ /
// / / / \/ /
// / / /______ / /
// / /__________\ / /
// /_____________/ \/
//
// Created by Eason.zhangyi on 15/12/16.
// Copyright © 2016年 ZY. All rights reserved.
//
#import <Foundation/Foundation.h>
@interface NSMutableArray (ZYExtension)
/**
* 添加一个元素
*/
- (void) zy_push:(id)object;
/**
* 取出最后一个数据并移除
*/
- (id) zy_pop;
/**
* 取出指定数量的元素并移除
*/
- (NSArray *) zy_pop:(NSUInteger)numberOfElements;
/**
* 添加数组
*/
- (void) zy_concat:(NSArray *)array;
/**
* 取出第一个元素，并在数据中移除这个元素
*
* @return 移除元素
*/
- (id) zy_shift;
/**
* 取出前 numberOfElements 个对象并从数组中移除
*
* @param numberOfElements 元素数量
*
* @return 移除元素列表
*/
- (NSArray *) zy_shift:(NSUInteger)numberOfElements;
/**
* 根据条件移除元素
*
* @param block 筛选block
*
* @return 移除后的结果
*/
- (NSArray *) zy_keepIf:(BOOL (^)(id object))block;
@end
| 15.134328 | 52 | 0.538462 |
0e2eb9fe427eff3fe1b47b2dd7c11c18a6e44dbb | 3,126 | h | C | C5515_Support_Files/C5515_Lib/dsplib_2.40.00/EXAMPLES/Cfir/t7.h | HeroSizy/Sizy | 89bc29940dc7666591259730b5112efd0a626043 | [
"Unlicense"
] | null | null | null | C5515_Support_Files/C5515_Lib/dsplib_2.40.00/EXAMPLES/Cfir/t7.h | HeroSizy/Sizy | 89bc29940dc7666591259730b5112efd0a626043 | [
"Unlicense"
] | null | null | null | C5515_Support_Files/C5515_Lib/dsplib_2.40.00/EXAMPLES/Cfir/t7.h | HeroSizy/Sizy | 89bc29940dc7666591259730b5112efd0a626043 | [
"Unlicense"
] | null | null | null | #define NX 64
#define NH 64
#define FNAME "t7"
#define MAXERROR 15
DATA x[2*NX] ={
-20501, -14779,
-4223, -17175,
-8764, -9007,
-16656, -1353,
-23928, -24432,
-15841, -4508,
-6295, -7597,
-17237, -468,
-20123, -22863,
-14373, -23472,
-3261, -6391,
-9218, -4446,
-23220, -18166,
-14645, -7275,
-17156, -17290,
-20833, -22554,
-16978, -3063,
-24496, -22673,
-13827, -6366,
-7953, -21503,
-4353, -13672,
-6001, -10016,
-20579, -8938,
-11009, -11484,
-11672, -19447,
-1982, -8019,
-13716, -18631,
-23475, -6869,
-871, -14747,
-24246, -14893,
-11010, -14463,
-1615, -20896,
-2492, -2993,
-9389, -24042,
-7375, -1872,
-1497, -9029,
-13466, -22932,
-20235, -9028,
-9419, -6052,
-11837, -5661,
-15619, -4718,
-5572, -11224,
-4221, -12655,
-16752, -13733,
-9930, -9180,
-5363, -22665,
-23751, -11206,
-3515, -19438,
-7801, -17941,
-4870, -17408,
-2023, -4370,
-15038, -14464,
-12977, -11626,
-22412, -1961,
-1841, -15259,
-7902, -8875,
-8822, -20307,
-101, -5265,
-12300, -15591,
-14008, -5482,
-4199, -16168,
-21709, -5550,
-9863, -20943,
-19140, -20933,
};
#pragma DATA_SECTION(h,".coeffs")
DATA h[2*NH] ={ /* b0 b1 b2 ... b(NH-1) */
-340, -434,
-854, -73,
-68, -531,
-485, -434,
-789, -285,
-682, -940,
-819, -154,
-920, -105,
-724, -924,
-146, -850,
-258, -590,
-288, -31,
-582, -359,
-490, -311,
-32, -513,
-204, -153,
-556, -167,
-41, -432,
-757, -855,
-444, -664,
-467, -375,
-487, -770,
-587, -252,
-453, -425,
-174, -795,
-746, -71,
-576, -752,
-899, -934,
-655, -293,
-176, -565,
-300, -585,
-111, -92,
-865, -54,
-476, -496,
-537, -926,
-617, -170,
-82, -888,
-791, -857,
-577, -286,
-31, -804,
-879, -888,
-644, -883,
-823, -262,
-833, -911,
-788, -287,
-854, -734,
-441, -353,
-224, -459,
-549, -400,
-155, -672,
-184, -102,
-934, -855,
-335, -667,
-837, -168,
-739, -6,
-86, -878,
-806, -26,
-747, -73,
-141, -39,
-271, -412,
-867, -47,
-171, -643,
-614, -692,
-789, -885,
};
#pragma DATA_SECTION(db,".dbuffer")
DATA db[2*NH + 2] ;
DATA rtest[2*NX] ={
17, 425,
318, 664,
-153, 1028,
202, 1081,
429, 1645,
652, 2812,
421, 2228,
1177, 2932,
1368, 3914,
417, 4477,
833, 4075,
1071, 3801,
1229, 5380,
942, 5595,
190, 5357,
1701, 5542,
1743, 6627,
133, 6970,
917, 6962,
1001, 7020,
1267, 8326,
1222, 8737,
434, 9327,
1138, 8633,
641, 9514,
949, 9684,
349, 10517,
407, 11608,
355, 9982,
284, 11062,
1619, 11786,
118, 12442,
681, 12469,
111, 12079,
937, 13414,
398, 13279,
-665, 14337,
1010, 14443,
-1575, 14093,
-2, 14532,
1085, 14598,
-599, 16567,
666, 16629,
83, 16350,
894, 17083,
217, 17646,
358, 18453,
543, 17601,
62, 18983,
238, 19961,
-91, 18001,
-973, 20664,
13, 20812,
-1198, 20588,
40, 20668,
-631, 21785,
314, 21698,
-91, 21399,
887, 21097,
1110, 20589,
-569, 21822,
873, 22505,
640, 21113,
-1393, 25083,
};
| 14.815166 | 43 | 0.507678 |
07e7c9da335dad1729254fb94d4b615dbe775645 | 1,237 | h | C | Workout/Workout.h | KinveyApps/Workout-iOS | cccdc769d18fd0d63a09954ded884558e1de9c9a | [
"Apache-2.0"
] | 1 | 2016-02-01T14:25:52.000Z | 2016-02-01T14:25:52.000Z | Workout/Workout.h | KinveyApps/Workout-iOS | cccdc769d18fd0d63a09954ded884558e1de9c9a | [
"Apache-2.0"
] | null | null | null | Workout/Workout.h | KinveyApps/Workout-iOS | cccdc769d18fd0d63a09954ded884558e1de9c9a | [
"Apache-2.0"
] | null | null | null | //
// Workout.h
// Workout
//
// Copyright 2013 Kinvey, Inc
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// Created by Michael Katz on 5/20/13.
//
#import <Foundation/Foundation.h>
#import <KinveyKit/KinveyKit.h>
#define kZoneArm @"arm"
#define kZoneChest @"chest"
#define kZoneCore @"core"
#define kZoneLeg @"leg"
#define kZoneBack @"back"
@interface Workout : NSObject <KCSPersistable>
@property (nonatomic, strong) NSString* workoutId;
@property (nonatomic, strong) NSString* zone;
@property (nonatomic, strong) NSString* workoutName;
@property (nonatomic, strong) NSMutableArray* repCount;
@property (nonatomic, strong) NSMutableArray* repWeight;
@property (nonatomic, strong) NSDate* workoutTime;
@end
| 30.170732 | 76 | 0.738884 |
6d7f519a138065d231a030af8e1e9ef094a2cc08 | 7,203 | c | C | src/mcu_zephyr.c | nandojve/lib_sigfox | 7baed6424547b1120238fc1cdfb323cf377062dc | [
"Apache-2.0"
] | null | null | null | src/mcu_zephyr.c | nandojve/lib_sigfox | 7baed6424547b1120238fc1cdfb323cf377062dc | [
"Apache-2.0"
] | null | null | null | src/mcu_zephyr.c | nandojve/lib_sigfox | 7baed6424547b1120238fc1cdfb323cf377062dc | [
"Apache-2.0"
] | null | null | null | /*
* Copyright (c) 2020 Gerson Fernando Budke
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr.h>
#include <drivers/sigfox.h>
#include <sigfox_types.h>
#include <sigfox_api.h>
#include <mcu_api.h>
#include <retriever_api.h>
#include <string.h>
#include <stdlib.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(sigfox_mcu, CONFIG_SIGFOX_LOG_LEVEL);
#define SIGFOX_MCU_API_VERSION "v2.3.7"
static uint8_t sfx_int_data[SFX_NVMEM_BLOCK_SIZE] = { 0 };
#if defined(CONFIG_SIGFOX_ST_RETRIEVER)
static uint32_t _id;
static uint8_t _pac[8];
static uint8_t _rcz;
#endif
/**
* SIGFOX MCU ZEPHYR API
*/
sfx_u8 MCU_API_malloc(sfx_u16 size, sfx_u8 **returned_pointer)
{
/* Must be 4 bytes align */
uint32_t *ptr = malloc(size / sizeof(uint32_t));
LOG_DBG("Size: %d, Address: %08X", size, (uint32_t) ptr);
if (ptr) {
(*returned_pointer) = (sfx_u8 *) ptr;
return SIGFOX_ERR_NONE;
}
return SIGFOX_ERR_MCU_MALLOC;
}
sfx_u8 MCU_API_free(sfx_u8 *ptr)
{
LOG_DBG("Address: %08X", (uint32_t) ptr);
free((uint32_t *) ptr);
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_get_voltage_temperature(sfx_u16 *voltage_idle,
sfx_u16 *voltage_tx,
sfx_s16 *temperature)
{
(*voltage_idle) = 0;
(*voltage_tx) = 0;
(*temperature) = 0;
LOG_DBG("MCU_API_get_voltage_temperature");
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_delay(sfx_delay_t delay_type)
{
LOG_DBG("Type: %d", delay_type);
switch (delay_type) {
case SFX_DLY_INTER_FRAME_TRX:
case SFX_DLY_INTER_FRAME_TX:
case SFX_DLY_CS_SLEEP:
/**
* Since ramp consists of 72 samples (18ms for each ramp, it
* needs to be compensate 36 ms). Moreover, 6ms of silence
* (2 before and 4 after packet).
*/
/*(500 - 2 * ST_RF_API_get_ramp_duration());*/
k_busy_wait(500000);
break;
case SFX_DLY_OOB_ACK:
/*(2000-2*ST_RF_API_get_ramp_duration());*/
k_busy_wait(2000000);
break;
}
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_timer_start_carrier_sense(sfx_u16 time_duration_in_ms)
{
LOG_DBG("Duration: %dms", time_duration_in_ms);
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_timer_stop_carrier_sense(void)
{
LOG_DBG("");
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_timer_start(sfx_u32 time_duration_in_s)
{
LOG_DBG("Duration: %lus", time_duration_in_s);
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_timer_stop(void)
{
LOG_DBG("");
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_timer_wait_for_end(void)
{
LOG_DBG("");
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_report_test_result(sfx_bool status, sfx_s16 rssi)
{
LOG_DBG("Status: %d, RSSI: %d", status, rssi);
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_get_version(sfx_u8 **version, sfx_u8 *size)
{
(*version) = (sfx_u8 *) SIGFOX_MCU_API_VERSION;
(*size) = sizeof(SIGFOX_MCU_API_VERSION);
LOG_DBG("Version: %s, Size: %d", *version, *size);
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_get_nv_mem(sfx_u8 read_data[SFX_NVMEM_BLOCK_SIZE])
{
memcpy((uint8_t *) read_data,
(uint8_t *) sfx_int_data,
SFX_NVMEM_BLOCK_SIZE);
LOG_HEXDUMP_DBG(read_data, SFX_NVMEM_BLOCK_SIZE, "get NV mem");
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_set_nv_mem(sfx_u8 data_to_write[SFX_NVMEM_BLOCK_SIZE])
{
memcpy((uint8_t *) sfx_int_data,
(uint8_t *) data_to_write,
SFX_NVMEM_BLOCK_SIZE);
LOG_HEXDUMP_DBG(data_to_write, SFX_NVMEM_BLOCK_SIZE, "set NV mem");
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_aes_128_cbc_encrypt(sfx_u8 *encrypted_data,
sfx_u8 *data_to_encrypt,
sfx_u8 aes_block_len,
sfx_u8 key[16],
sfx_credentials_use_key_t use_key)
{
/*
#if !defined(CONFIG_SIGFOX_ST_RETRIEVER)
struct tc_aes_key_sched_struct aes;
uint8_t iv[TC_AES_BLOCK_SIZE];
uint8_t enc[TC_AES_BLOCK_SIZE + aes_block_len];
const uint8_t *key_ptr;
sfx_s8 ret;
key_ptr = (use_key == CREDENTIALS_PRIVATE_KEY) ? private_key : key;
LOG_HEXDUMP_DBG(data_to_encrypt, aes_block_len, "aes in");
LOG_HEXDUMP_DBG(key_ptr, TC_AES_BLOCK_SIZE, "PK");
LOG_HEXDUMP_DBG(key, TC_AES_BLOCK_SIZE, "Public Key");
(void)tc_aes128_set_encrypt_key(&aes, key_ptr);
(void)memset(iv, 0, TC_AES_BLOCK_SIZE);
if (tc_cbc_mode_encrypt(enc,
aes_block_len + TC_AES_BLOCK_SIZE,
data_to_encrypt, aes_block_len,
iv, &aes) == 0) {
LOG_ERR("encrypting");
ret = SIGFOX_ERR_MCU_AES;
} else {
memcpy(encrypted_data, enc + TC_AES_BLOCK_SIZE, aes_block_len);
LOG_HEXDUMP_DBG(enc + TC_AES_BLOCK_SIZE,
aes_block_len, "aes out");
ret = SIGFOX_ERR_NONE;
}
(void)memset(iv, 0, TC_AES_BLOCK_SIZE);
(void)memset(&aes, 0, sizeof(struct tc_aes_key_sched_struct));
return ret;
#else
LOG_HEXDUMP_DBG(data_to_encrypt, aes_block_len, "aes in");
enc_utils_encrypt(encrypted_data, data_to_encrypt,
aes_block_len, key, use_key);
LOG_HEXDUMP_DBG(encrypted_data, aes_block_len, "aes out");
return SIGFOX_ERR_NONE;
#endif
*/
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_get_device_id_and_payload_encryption_flag(
sfx_u8 dev_id[ID_LENGTH],
sfx_bool *payload_encryption_enabled)
{
#if defined(CONFIG_SIGFOX_ST_RETRIEVER)
enc_utils_retrieve_data(&_id, _pac, &_rcz);
LOG_DBG("ID: %08x", _id);
memcpy(dev_id, &_id, ID_LENGTH);
#else
dev_id[0] = 0xFE;
dev_id[1] = 0xDC;
dev_id[2] = 0xBA;
dev_id[3] = 0x98;
#endif
(*payload_encryption_enabled) = 0;
LOG_DBG("ID: %02x-%02x-%02x-%02x, Encrypt: %s",
dev_id[0], dev_id[1], dev_id[2], dev_id[3],
*payload_encryption_enabled ? "True" : "False");
return SIGFOX_ERR_NONE;
}
sfx_u8 MCU_API_get_initial_pac(sfx_u8 initial_pac[PAC_LENGTH])
{
#if defined(CONFIG_SIGFOX_ST_RETRIEVER)
memcpy(initial_pac, _pac, PAC_LENGTH);
#else
initial_pac[0] = 0x11;
initial_pac[1] = 0x22;
initial_pac[2] = 0x33;
initial_pac[3] = 0x44;
initial_pac[4] = 0x55;
initial_pac[5] = 0x66;
initial_pac[6] = 0x77;
initial_pac[7] = 0x88;
#endif
LOG_DBG("ID: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
initial_pac[3], initial_pac[2],
initial_pac[1], initial_pac[0],
initial_pac[7], initial_pac[6],
initial_pac[5], initial_pac[4]);
return SIGFOX_ERR_NONE;
}
/**
* Sigfox dependency
*/
void __aeabi_memcpy(void *dest, const void *src, size_t n)
{
memcpy(dest, src, n);
}
void __aeabi_memcpy4(void *dest, const void *src, size_t n)
{
memcpy(dest, src, n);
}
void __aeabi_memclr(void *dest, size_t n)
{
memset(dest, 0, n);
}
void __aeabi_memclr4(void *dest, size_t n)
{
memset(dest, 0, n);
}
void __aeabi_memset(void *dest, char c, size_t n)
{
memset(dest, c, n);
}
/**
* ST, deve ser removido
*/
#if defined(CONFIG_SIGFOX_ST_RETRIEVER)
uint32_t GetNVMBoardDataAddress(void)
{
uint32_t address = 0x600;
LOG_DBG("Address: 0x%08x", address);
return address;
}
NVM_RW_RESULTS NVM_Read(uint32_t nAddress, uint8_t cNbBytes, uint8_t *pcBuffer)
{
LOG_DBG("Address: 0x%08x, len: %d", nAddress, cNbBytes);
return 0;
}
uint8_t EepromRead(uint16_t nAddress, uint8_t cNbBytes, uint8_t *pcBuffer)
{
LOG_DBG("Address: 0x%08x, len: %d", nAddress, cNbBytes);
switch (nAddress) {
case 0x1f0:
memcpy(pcBuffer, sfx_data_vector, cNbBytes);
break;
case 0x200:
memcpy(pcBuffer, sfx_data_vector + 16, cNbBytes);
break;
case 0x6:
memcpy(pcBuffer, sfx_data_vector + 6, cNbBytes);
break;
}
LOG_HEXDUMP_DBG(pcBuffer, cNbBytes, "dump");
return 0;
}
#endif
| 21 | 79 | 0.726919 |
ed45e34b932f2f3fada39b276500a4804b3a4dda | 7,609 | h | C | graphy/external/SurpriseMeCPM/src/Base/greedy_louvain.h | artemyk/graphy | 3e87efad4f743b8802b603d264eb5df64754548f | [
"BSD-2-Clause"
] | 1 | 2015-05-21T18:12:59.000Z | 2015-05-21T18:12:59.000Z | graphy/external/SurpriseMeCPM/src/Base/greedy_louvain.h | artemyk/graphy | 3e87efad4f743b8802b603d264eb5df64754548f | [
"BSD-2-Clause"
] | 2 | 2015-02-20T17:27:00.000Z | 2018-08-31T20:36:41.000Z | graphy/external/SurpriseMeCPM/src/Base/greedy_louvain.h | artemyk/graphy | 3e87efad4f743b8802b603d264eb5df64754548f | [
"BSD-2-Clause"
] | 5 | 2015-02-10T15:34:53.000Z | 2018-08-31T19:42:37.000Z | /* greedy_louvain.h
* Copyright (C) (2011) V.A. Traag, P. Van Dooren, Y. Nesterov
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* In case of any problems or bugs, please contact Vincent Traag at
* vincent (dot) traag (at) uclouvain (dot) be
*
* This software is based on the article
*
* V.A. Traag, P. Van Dooren, Y. Nesterov, "Narrow scope for resolution-free
* community detection" (2011) arXiv:1104.3083v1.
*
*/
// Originally based on:
//-----------------------------------------------------------------------------
// Community detection
// Based on the article "Fast unfolding of community hierarchies in large networks"
// Copyright (C) 2008 V. Blondel, J.-L. Guillaume, R. Lambiotte, E. Lefebvre
//
// This program must not be distributed without agreement of the above mentionned authors.
//-----------------------------------------------------------------------------
// Author : E. Lefebvre, adapted by J.-L. Guillaume
// Email : jean-loup.guillaume@lip6.fr
// Location : Paris, France
// Time : February 2008
//-----------------------------------------------------------------------------
#ifndef GREEDY_LOUVAIN_H
#define GREEDY_LOUVAIN_H
//#define THREAD_SUPPORT
#define NODES_PER_THREAD 10000
#include "community.h"
#include <set>
#include <queue>
#include <algorithm>
#ifdef THREAD_SUPPORT
#include <pthread.h>
#include <errno.h>
#endif
#include "../MTRand/MersenneTwister.h"
class GreedyLouvain
{
public:
static void detect_communities(Community* c); // Detect communities and return community vector
// number of pass for one level computation
// if -1, compute as many pass as needed to increase modularity
static int nb_pass;
// a new pass is computed if the last one has generated an increase
// greater than min_modularity
// if 0. even a minor increase is enough to go for one more pass
static double min_modularity;
// Minimum proportion of changes (below this percentage of changes)
// we will not make another pass
static double min_prop_changes;
// Use random iteration over the nodes?
static int iterate_randomly;
// Move individual nodes in between levels?
static int move_individual;
// Maximum number of threads to use
static int max_nb_threads;
// Random seed
static int random_seed;
private:
//////////////////////////////////////////////////////////////////////////////
// Syncing variables
//////////////////////////////////////////////////////////////////////////////
// These variables allow the threads to synchronize at the end of a pass
// and to hence determine whether another general pass should be made. Since
// each thread will only examine a smaller portion of it's nodes, it is not
// necessarily the case that if that part is optimized, it won't be affected by
// optimizations in another part of the network. Hence, the decision to do
// another pass, must be made in synchrony.
class ThreadSync
{
public:
// Variables required for threading
// If these variables would be static, it would interfere when doing
// multiple communities at the same time.
// Keep track of the number of improvements in each pass
int nb_improvements;
// Keep track of the increase in modularity
double diff;
#ifdef THREAD_SUPPORT
// Keep track of the number of threads that have finished their part of the pass
int nb_threads_finished_pass;
// This is the total number of threads. If this contains *ANY* error, there will either
// be some deadlock situation, or there will be unsynchronized threads.
int nb_threads;
// This is the shared condition upon which all threads base themselves in order to
// determine whether they should stop or not.
int stop;
//////////////////////////////////////////////////////////////////////////////
// Locking variables
//////////////////////////////////////////////////////////////////////////////
// These variables are used to enable multi threaded community detection
//
// General lock, used for the node locking section. This is to
// prevent deadlock situations in which two different nodes have
// shared neighbours and are hence weighting for each other to unlock
// that neighbour.
pthread_mutex_t lock;
// Bookkeeping lock, for if any changes are being made to the bookkeeping of
// the algorithm. That is, changes to community assignments, et cetera.
pthread_mutex_t bookkeeping_lock;
// Node lock, per node. Each node can be locked, so that other thread can't
// simultaneously examine it and make changes. Also the neighbours are locked
// so as to minimize the affects of interfering changes from other threads. These
// effects are still present in the expected values, but should be relatively
// minor in terms of optimization. The locking of the neighbours however does ensure
// that the bookkeeping remains correct. That is, the total weight from and to a
// community *cannot* change when examining a node, ensuring correct bookkeeping.
pthread_mutex_t* node_locks; // Need to dynamically allocate this one
// Comm lock, per community. This way, changes can be made for different communities
// at the same time, without affecting each other. As is the case with the node lock
// it is best to have as much of the nodes of the same community in the same thread
// so that they interfere as little as possible.
pthread_mutex_t* comm_locks; // Need to dynamically allocate this one
// The lock to enable synchronization signals
pthread_mutex_t sync_lock;
// The synchronization signals. All threads wait at the end of the pass, to let the
// last thread decide whether they should stop or not. After deciding whether to stop
// or not, it broadcasts to all other thread, signaling it may continue.
pthread_cond_t sync_signal;
pthread_mutexattr_t lock_t; // Lock type for the recursive locks
int* thread_id_per_node;
set<int>unclaimed_nodes;
#endif
// Functions
void reset_sync();
ThreadSync(int nb_nodes, int nb_threads); // Constructor
~ThreadSync(); // Destructuror
};
// compute communities of the graph for one level
// returns the modularity
static double one_level(Community* c);
#ifdef THREAD_SUPPORT
static void* one_level_thread(void* cc); //Do threaded community detection (one level)
#endif
static double one_level_single(Community* cc, ThreadSync* ts); // Run a single level (without multiple threads)
static void random_shuffle(deque<int> &v, MTRand* r);
// Use this PRNG to initialize the seed (to avoid multhread problems when detecting communities
// repeatedly, i.e. when probing resolution parameters)
//static MTRand& mt_rand();
#ifdef THREAD_SUPPORT
static pthread_mutex_t rand_lock;
struct level_thread_data
{
Community* c;
ThreadSync* ts;
int thread_id;
};
#endif
};
#endif
| 37.117073 | 113 | 0.672362 |
355010d7e6f0e782c5b821c70571a230cf1d53ef | 281 | h | C | lib/ios/RNNSetRootAnimator.h | sharekey/react-native-navigation | 7347ed6fa71781c7646b6aec45122a50f9b5aaac | [
"MIT"
] | 13,709 | 2016-03-13T10:18:49.000Z | 2022-03-31T03:56:24.000Z | lib/ios/RNNSetRootAnimator.h | sharekey/react-native-navigation | 7347ed6fa71781c7646b6aec45122a50f9b5aaac | [
"MIT"
] | 5,880 | 2016-03-17T11:57:36.000Z | 2022-03-31T20:25:50.000Z | lib/ios/RNNSetRootAnimator.h | sharekey/react-native-navigation | 7347ed6fa71781c7646b6aec45122a50f9b5aaac | [
"MIT"
] | 3,514 | 2016-03-23T20:24:43.000Z | 2022-03-30T11:06:46.000Z | #import "TransitionOptions.h"
#import <Foundation/Foundation.h>
typedef void (^RNNAnimationEndedBlock)(void);
@interface RNNSetRootAnimator : NSObject
- (void)animate:(UIWindow *)window
duration:(CGFloat)duration
completion:(RNNAnimationEndedBlock)completion;
@end
| 21.615385 | 51 | 0.768683 |
899ff72d229eda7bc4334cda1a3ecc6b240f991f | 4,367 | c | C | mwc/romana/relic/d/bin/prep.c | gspu/Coherent | 299bea1bb52a4dcc42a06eabd5b476fce77013ef | [
"BSD-3-Clause"
] | 20 | 2019-10-10T14:14:56.000Z | 2022-02-24T02:54:38.000Z | mwc/romana/relic/d/bin/prep.c | gspu/Coherent | 299bea1bb52a4dcc42a06eabd5b476fce77013ef | [
"BSD-3-Clause"
] | null | null | null | mwc/romana/relic/d/bin/prep.c | gspu/Coherent | 299bea1bb52a4dcc42a06eabd5b476fce77013ef | [
"BSD-3-Clause"
] | 1 | 2022-03-25T18:38:37.000Z | 2022-03-25T18:38:37.000Z | /*
* Prepare text for statistical processing
* by breaking it into words (and possibly
* also punctuation marks) and discarding
* certain words if this is desired.
*/
#include <stdio.h>
#include <ctype.h>
#define NHASH 64 /* Hash buckets for ignore and only */
#define NWORD 400 /* Longest word */
typedef struct WORDS {
struct WORDS *w_next;
char w_name[];
} WORDS;
WORDS *words[NHASH];
int pflag; /* Print punctuation as well */
int dflag; /* Print (input) word numbers */
int fflag; /* Fold upper into lower case */
int iflag; /* Ignore case for '-i' */
int nignore; /* Number of ignored words */
int nonly; /* Number of only words */
long wordno; /* Input word number */
char wordbuf[NWORD];
char missing[] = "Missing `%s' file argument";
char onlyone[] = "Only one of `-i' or `-o' may be given";
main(argc, argv)
int argc;
char *argv[];
{
register char *ap;
register int i;
register int estat = 0;
register FILE *fp;
while (argc>1 && *argv[1]=='-') {
for (ap = &argv[1][1]; *ap != '\0'; ap++)
switch (*ap) {
case 'd':
dflag = 1;
break;
case 'f':
fflag = 1;
break;
case 'p':
pflag = 1;
break;
case 'i':
if (nonly)
preperr(onlyone);
if (argc < 3)
preperr(missing, "ignore");
argv++;
argc--;
nignore += enter(argv[1]);
iflag = 1;
break;
case 'o':
if (nignore)
preperr(onlyone);
if (argc < 3)
preperr(missing, "only");
argv++;
argc--;
nonly += enter(argv[1]);
break;
default:
usage();
}
argv++;
argc--;
}
if (argc > 1)
for (i=1; i<argc; i++) {
if ((fp = fopen(argv[i], "r")) == NULL)
preperr("Cannot open `%s'", argv[i]);
estat |= prep(fp);
fclose(fp);
}
else
estat = prep(stdin);
exit(estat);
}
/*
* Run prep on each input file.
*/
prep(fp)
FILE *fp;
{
register char *cp;
register int c;
register int inword = 0;
while ((c = getc(fp)) != EOF) {
if (!isascii(c))
c = '\0';
if (fflag && isupper(c))
c = tolower(c);
if (inword) {
if (isalpha(c) || c=='\'') {
*cp++ = c;
continue;
}
if (c == '-') {
if ((c = getc(fp)) == '\n')
continue;
ungetc(c, fp);
c = '-';
}
*cp = '\0';
inword = 0;
wordno++;
print(wordbuf);
}
if (isalpha(c) || c=='\'') {
inword++;
cp = wordbuf;
*cp++ = c;
} else if (pflag && ispunct(c)) {
putchar(c);
putchar('\n');
}
}
}
/*
* Print out a word.
*/
print(word)
char *word;
{
if ((nignore && lookup(word)) || (nonly && !lookup(word)))
return;
if (dflag)
printf("%ld\t", wordno);
printf("%s\n", wordbuf);
}
/*
* Enter words from the given file
* into the hash table.
*/
enter(fn)
char *fn;
{
register char *cp;
register WORDS *wp;
register int c;
register unsigned hash;
register int nword = 0;
register FILE *fp;
if ((fp = fopen(fn, "r")) == NULL)
preperr("Cannot open `%s'", fn);
while (fgets(wordbuf, NWORD, fp) != NULL) {
hash = 0;
cp = wordbuf;
while ((c = *cp++) != '\0') {
if (c == '\n') {
cp[-1] = '\0';
break;
}
if (isupper(c))
cp[-1] = c = tolower(c);
hash += c;
}
if ((wp = (WORDS *)malloc(sizeof(WORDS) + cp-wordbuf)) == NULL)
preperr("Out of memory for words from `%s'", fn);
strcpy(wp->w_name, wordbuf);
wp->w_next = words[hash %= NHASH];
words[hash] = wp;
nword++;
}
fclose(fp);
return (nword);
}
/*
* Lookup a word in either the only
* or exception list.
*/
lookup(word)
char *word;
{
register WORDS *wp;
register char *cp;
register unsigned hash = 0;
char wordbuf[256]; /* Keep a temporary copy of a world */
int i;
cp = word;
while (*cp != '\0')
if (isupper(*cp))
hash += tolower(*cp++); else
hash += *cp++;
for (wp = words[hash%NHASH]; wp != NULL; wp = wp->w_next) {
if (iflag && !fflag) {
if (strlen(word) > 256)
preperr("word too long %s", word);
for (cp = word, i = 0; *cp != '\0'; cp++)
if (isupper(*cp))
wordbuf[i++] = tolower(*cp);
else
wordbuf[i++] = *cp;
wordbuf[i] = '\0';
cp = wordbuf;
if (strcmp(wp->w_name, cp) == 0)
return (1);
} else {
if (strcmp(wp->w_name, word) == 0)
return (1);
}
}
return (0);
}
/* VARARGS */
preperr(x)
{
fprintf(stderr, "prep: %r\n", &x);
exit(1);
}
usage()
{
fprintf(stderr, "Usage: prep [-dfp] [-i file] [-o file] [file ...]\n");
exit(1);
}
| 18.045455 | 72 | 0.538585 |
60c1ab2c924460dec81cae184ff022fe498b4e94 | 971 | h | C | source/Wfs/EnmWfsFactory.h | Borrk/Enzyme-labeled-instrument | a7c8f4459511c774f7e0c4fee1fe05baf1ae2a5f | [
"MIT"
] | null | null | null | source/Wfs/EnmWfsFactory.h | Borrk/Enzyme-labeled-instrument | a7c8f4459511c774f7e0c4fee1fe05baf1ae2a5f | [
"MIT"
] | null | null | null | source/Wfs/EnmWfsFactory.h | Borrk/Enzyme-labeled-instrument | a7c8f4459511c774f7e0c4fee1fe05baf1ae2a5f | [
"MIT"
] | null | null | null | // EnmWfsFactory.h: interface for the CEnmWfsFactory class.
//
//////////////////////////////////////////////////////////////////////
#if !defined(AFX_ENMWFSFACTORY_H__7D307864_CA4F_4FF8_A6AF_021C121B1B06__INCLUDED_)
#define AFX_ENMWFSFACTORY_H__7D307864_CA4F_4FF8_A6AF_021C121B1B06__INCLUDED_
#if _MSC_VER > 1000
#pragma once
#endif // _MSC_VER > 1000
#include "EnmWfo.h"
#include "EnmWfoSelecter.h"
class CEnmWfsFactory
{
public:
CEnmWfoSelector* CreateWfs();
private:
BOOLEAN CreateProgramModeTree( CEnmWfoSelector& root );
BOOLEAN CreateFastModeTree( CEnmWfoSelector& root );
BOOLEAN CreateProgrammingTree( CEnmWfoSelector& root );
BOOLEAN CreateProgramListTree( CEnmWfoSelector& root );
BOOLEAN CreateDataListTree( CEnmWfoSelector& root );
BOOLEAN CreateSysConfigTree( CEnmWfoSelector& root );
BOOLEAN CreateHostConsoleTree( CEnmWfoSelector& root );
};
#endif // !defined(AFX_ENMWFSFACTORY_H__7D307864_CA4F_4FF8_A6AF_021C121B1B06__INCLUDED_)
| 30.34375 | 88 | 0.754892 |
e4b8ff19b708482bd693051323125d3b76356e04 | 7,384 | h | C | copasi/model/CModelParameterGroup.h | tobiaselsaesser/COPASI | 7e61c1b1667b0f4acf8f3865fe557603f221c472 | [
"Artistic-2.0"
] | null | null | null | copasi/model/CModelParameterGroup.h | tobiaselsaesser/COPASI | 7e61c1b1667b0f4acf8f3865fe557603f221c472 | [
"Artistic-2.0"
] | null | null | null | copasi/model/CModelParameterGroup.h | tobiaselsaesser/COPASI | 7e61c1b1667b0f4acf8f3865fe557603f221c472 | [
"Artistic-2.0"
] | null | null | null | // Copyright (C) 2017 - 2018 by Pedro Mendes, Virginia Tech Intellectual
// Properties, Inc., University of Heidelberg, and University of
// of Connecticut School of Medicine.
// All rights reserved.
// Copyright (C) 2011 - 2016 by Pedro Mendes, Virginia Tech Intellectual
// Properties, Inc., University of Heidelberg, and The University
// of Manchester.
// All rights reserved.
#ifndef COPASI_CModelParameterGroup
#define COPASI_CModelParameterGroup
#include <vector>
#include "copasi.h"
#include "copasi/model/CModelParameter.h"
class CModel;
class CValidatedUnit;
class CModelParameterGroup: public CModelParameter
{
public:
typedef std::vector< CModelParameter * >::iterator iterator;
typedef std::vector< CModelParameter * >::const_iterator const_iterator;
public:
/**
* Create and insert an undo object based on the given data.
* This method needs to be re-implemented in container which support INSERT and REMOVE
* @param const CData & data
* @return CUndoObjectInterface * pUndoObject
*/
virtual CUndoObjectInterface * insert(const CData & data);
/**
* Update the index of a contained object
* This method needs to be re-implemented in container which care about the order of contained objects
* @param const size_t & index
* @param const CUndoObjectInterface * pUndoObject
*/
virtual void updateIndex(const size_t & index, const CUndoObjectInterface * pUndoObject);
/**
* Retrieve the data describing the object
* @return CData data
*/
virtual CData toData() const;
/**
* Apply the provided data to the object
* @param const CData & data
* @return bool success
*/
virtual bool applyData(const CData & data, CUndoData::ChangeSet & changes);
/**
* Create the undo data which represents the changes recording the
* differences between the provided oldData and the current data.
* @param CUndoData & undoData
* @param const CUndoData::Type & type
* @param const CData & oldData (default: empty data)
* @param const CCore::Framework & framework (default: CCore::Framework::ParticleNumbers)
* @return CUndoData undoData
*/
virtual void createUndoData(CUndoData & undoData,
const CUndoData::Type & type,
const CData & oldData = CData(),
const CCore::Framework & framework = CCore::Framework::ParticleNumbers) const;
/**
* Constructor
* @param CModelParameterGroup * pParent
* @param const CModelParameter::Type & type (default: CModelParameter::Group)
*/
CModelParameterGroup(CModelParameterGroup * pParent, const CModelParameter::Type & type = CModelParameter::Type::Group);
/**
* Copy constructor
* @param const CModelParameterGroup & src
* @param CModelParameterGroup * pParent
* @param const bool & createMissing
*/
CModelParameterGroup(const CModelParameterGroup & src,
CModelParameterGroup * pParent,
const bool & createMissing);
/**
* Destructor
*/
virtual ~CModelParameterGroup();
/**
* Add parameter of the given type to the group and return a pointer to it
* @param const CModelParameter::Type & type
* @return CModelParameter * pParameter
*/
CModelParameter * add(const CModelParameter::Type & type);
/**
* Add the given parameter to the group.
* Note, the parent of the parameter is not updated
* @param CModelParameter * pModelParameter
*/
void add(CModelParameter * pModelParameter);
/**
* Remove the given parameter from the group.
* Note, the parameter is not deleted.
* @param CModelParameter * pModelParameter
*/
void remove(CModelParameter * pModelParameter);
/**
* Remove the indexed parameter from the group and delete it
* @param const size_t & index
*/
void remove(const size_t & index);
/**
* Retrieve the size of the group
* @return size_t size
*/
size_t size() const;
/**
* Retrieve the iterator pointing to the first contained parameter.
* @return iterator begin
*/
iterator begin();
/**
* Retrieve the iterator pointing past the last contained parameter.
* @return iterator end
*/
iterator end();
/**
* Retrieve the const_iterator pointing to the first contained parameter.
* @return const_iterator begin
*/
const_iterator begin() const;
/**
* Retrieve the const_iterator pointing past the last contained parameter.
* @return const_iterator end
*/
const_iterator end() const;
/**
* Compile the parameter
*/
virtual void compile();
/**
* Clear the contained parameters and delete them.
*/
void clear();
#ifndef SWIG
/**
* Compare the parameter to an other
* @param const CModelParameter & other
* @param const CCore::Framework & framework
* @param const bool & createMissing = false
*/
const virtual CompareResult & diff(const CModelParameter& other,
const CCore::Framework & framework,
const bool & createMissing = false);
#endif //SWIG
/**
* Update the corresponding model object with the current parameter settings
*/
virtual bool updateModel();
/**
* Refresh the parameter from the corresponding model object
* @param const bool & modifyExistence
*/
virtual bool refreshFromModel(const bool & modifyExistence);
/**
* Retrieve a pointer to the parameter with the given CN
* @param const std::string & cn
* @return CModelParameter * pModelParameter
*/
CModelParameter * getModelParameter(const std::string & cn) const;
/**
* Retrieve a pointer to the parameter with the given name and type
* @param const std::string & name
* @param const CModelParameter::Type & type
* @return CModelParameter * pModelParameter
*/
CModelParameter * getModelParameter(const std::string & name,
const CModelParameter::Type & type) const;
// These methods are only here so that we can use CNodeIterator to traverse the tree.
virtual size_t getNumChildren() const;
virtual const CModelParameter * getChild(const size_t & index) const;
/**
* Retrieve the validated unit of the object units
* @param const CModelParameter * pModelParameter
* @return const CValidatedUnit & objectUnit
*/
const CValidatedUnit & getObjectUnit(const CModelParameter * pModelParameter) const;
/**
* Assign the content of the source group to this, i.e., copy all
* contained parameters.
* @param const CModelParameterGroup & src
* @param const bool & createMissing
*/
void assignGroupContent(const CModelParameterGroup & src,
const bool & createMissing);
protected:
/**
* Copy the existing parameter and add it to the group
* @param const CModelParameter & src
* @param const bool & createMissing
* @return CModelParameter * pCopy
*/
CModelParameter * copy(const CModelParameter & src,
const bool & createMissing);
private:
/**
* A vector of pointer to the contained parameters.
*/
std::vector< CModelParameter * > mModelParameters;
/**
* A map of model objects and their validated units
*/
mutable std::map< CObjectInterface *, CValidatedUnit > mValidatedUnits;
};
#endif // COPASI_CModelParameterGroup
| 30.01626 | 122 | 0.680525 |
b097763853a36c460d198c014ef8ea7946700d3d | 1,985 | h | C | applications/acsdkAudioInputStream/include/acsdkAudioInputStream/AudioInputStreamFactory.h | immortalkrazy/avs-device-sdk | 703b06188eae146af396f58be4e47442d7ce5b1e | [
"Apache-2.0"
] | 1,272 | 2017-08-17T04:58:05.000Z | 2022-03-27T03:28:29.000Z | applications/acsdkAudioInputStream/include/acsdkAudioInputStream/AudioInputStreamFactory.h | immortalkrazy/avs-device-sdk | 703b06188eae146af396f58be4e47442d7ce5b1e | [
"Apache-2.0"
] | 1,948 | 2017-08-17T03:39:24.000Z | 2022-03-30T15:52:41.000Z | applications/acsdkAudioInputStream/include/acsdkAudioInputStream/AudioInputStreamFactory.h | immortalkrazy/avs-device-sdk | 703b06188eae146af396f58be4e47442d7ce5b1e | [
"Apache-2.0"
] | 630 | 2017-08-17T06:35:59.000Z | 2022-03-29T04:04:44.000Z | /*
* Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License").
* You may not use this file except in compliance with the License.
* A copy of the License is located at
*
* http://aws.amazon.com/apache2.0/
*
* or in the "license" file accompanying this file. This file is distributed
* on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either
* express or implied. See the License for the specific language governing
* permissions and limitations under the License.
*/
#ifndef ACSDKAUDIOINPUTSTREAM_AUDIOINPUTSTREAMFACTORY_H_
#define ACSDKAUDIOINPUTSTREAM_AUDIOINPUTSTREAMFACTORY_H_
#include <memory>
#include <chrono>
#include <AVSCommon/AVS/AudioInputStream.h>
#include <AVSCommon/Utils/AudioFormat.h>
#include <AVSCommon/Utils/Configuration/ConfigurationNode.h>
namespace alexaClientSDK {
namespace acsdkAudioInputStream {
/**
* This class produces an @c AudioInputStream.
*/
class AudioInputStreamFactory {
public:
/**
* Method to create a factory method for an @c AudioInputStream.
*
* @param audioFormat The shared ptr to the @c AudioFormat of the stream
* @param wordSize The size of each word within the stream.
* @param maxReaders The maximum number of readers of the stream.
* @param amountOfAudioDataInBuffer The amount of audio data to keep in the ring buffer.
*
* @return A @c std::function that returns a @cstd::shared_ptr to a new instance of @c AudioInputStream.
*/
static std::shared_ptr<alexaClientSDK::avsCommon::avs::AudioInputStream> createAudioInputStream(
const std::shared_ptr<avsCommon::utils::AudioFormat>& audioFormat,
const size_t wordSize,
const size_t maxReaders,
const std::chrono::seconds amountOfAudioDataInBuffer);
};
} // namespace acsdkAudioInputStream
} // namespace alexaClientSDK
#endif // ACSDKAUDIOINPUTSTREAM_AUDIOINPUTSTREAMFACTORY_H_
| 36.090909 | 108 | 0.745088 |
69237d07d50c17a9a862a520086446775c53f318 | 1,387 | h | C | asn1c_defs/all-defs/TDD-InfoServedNRCell-Information.h | o-ran-sc/ric-app-kpimon | b402550220ed60118aea67031516f4164b82a8ac | [
"Apache-2.0"
] | null | null | null | asn1c_defs/all-defs/TDD-InfoServedNRCell-Information.h | o-ran-sc/ric-app-kpimon | b402550220ed60118aea67031516f4164b82a8ac | [
"Apache-2.0"
] | null | null | null | asn1c_defs/all-defs/TDD-InfoServedNRCell-Information.h | o-ran-sc/ric-app-kpimon | b402550220ed60118aea67031516f4164b82a8ac | [
"Apache-2.0"
] | null | null | null | /*
* Generated by asn1c-0.9.29 (http://lionet.info/asn1c)
* From ASN.1 module "X2AP-PDU-Contents"
* found in "../../asn_defs/asn1/x2ap-modified-15-05.asn"
* `asn1c -fcompound-names -fno-include-deps -findirect-choice -gen-PER -no-gen-OER`
*/
#ifndef _TDD_InfoServedNRCell_Information_H_
#define _TDD_InfoServedNRCell_Information_H_
#include <asn_application.h>
/* Including external dependencies */
#include "NRFreqInfo.h"
#include "NR-TxBW.h"
#include <constr_SEQUENCE.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Forward declarations */
struct ProtocolExtensionContainer;
/* TDD-InfoServedNRCell-Information */
typedef struct TDD_InfoServedNRCell_Information {
NRFreqInfo_t nRFreqInfo;
NR_TxBW_t nR_TxBW;
struct ProtocolExtensionContainer *iE_Extensions; /* OPTIONAL */
/*
* This type is extensible,
* possible extensions are below.
*/
/* Context for parsing across buffer boundaries */
asn_struct_ctx_t _asn_ctx;
} TDD_InfoServedNRCell_Information_t;
/* Implementation */
extern asn_TYPE_descriptor_t asn_DEF_TDD_InfoServedNRCell_Information;
extern asn_SEQUENCE_specifics_t asn_SPC_TDD_InfoServedNRCell_Information_specs_1;
extern asn_TYPE_member_t asn_MBR_TDD_InfoServedNRCell_Information_1[3];
#ifdef __cplusplus
}
#endif
#endif /* _TDD_InfoServedNRCell_Information_H_ */
#include <asn_internal.h>
| 27.196078 | 86 | 0.759913 |
0a60252995b056b6afad6602846b7b6e505eb914 | 385 | h | C | include/commands/Delay.h | 1138programming/1138G-VEX-Code-2018-2019 | f9b40d56b39dcca6823d4d81c7a9041274b348a2 | [
"MIT"
] | null | null | null | include/commands/Delay.h | 1138programming/1138G-VEX-Code-2018-2019 | f9b40d56b39dcca6823d4d81c7a9041274b348a2 | [
"MIT"
] | null | null | null | include/commands/Delay.h | 1138programming/1138G-VEX-Code-2018-2019 | f9b40d56b39dcca6823d4d81c7a9041274b348a2 | [
"MIT"
] | null | null | null | #ifndef _COMMANDS_DELAY_H_
#define _COMMANDS_DELAY_H_
#include "commands/Command.h"
class Delay : public Command {
private:
unsigned int startTime;
unsigned int duration;
public:
bool canRun();
void initialize();
void execute();
bool isFinished();
void end();
void interrupted();
Delay(unsigned int duration);
};
#endif // _COMMANDS_DELAY_H_
| 18.333333 | 33 | 0.685714 |
52691f3f2dc9c9fc117ca955ac680d9a8122c4c5 | 869 | h | C | src/backends/common/configuration.h | aliefhooghe/Gammou | 1b29bf6667279fb9edc69dd998409f881eed6cab | [
"BSD-3-Clause"
] | 27 | 2017-12-12T19:31:04.000Z | 2022-03-30T02:11:54.000Z | src/backends/common/configuration.h | aliefhooghe/Gammou | 1b29bf6667279fb9edc69dd998409f881eed6cab | [
"BSD-3-Clause"
] | null | null | null | src/backends/common/configuration.h | aliefhooghe/Gammou | 1b29bf6667279fb9edc69dd998409f881eed6cab | [
"BSD-3-Clause"
] | 1 | 2019-02-20T20:30:56.000Z | 2019-02-20T20:30:56.000Z | #ifndef GAMMOU_CONFIGURATION_H_
#define GAMMOU_CONFIGURATION_H_
#include <filesystem>
#define GAMMOU_PACKAGE_PATH_ENV "GAMMOU_PACKAGE_PATH"
#define GAMMOU_PATCH_PATH_ENV "GAMMOU_PATCH_PATH"
#define GAMMOU_SAMPLE_PATH_ENV "GAMMOU_SAMPLE_PATH"
namespace Gammou {
class configuration {
public:
/**
* @brief Retrieve the packages directory from an environment variable or a default value
*/
static std::filesystem::path get_packages_directory_path();
/**
* @brief Retrieve the patch directory from an environment variable or a default value
*/
static std::filesystem::path get_patch_path();
/**
* @brief Retrieve the sample directory from an environment variable or a default value
*/
static std::filesystem::path get_samples_path();
};
}
#endif | 24.828571 | 98 | 0.686997 |
f84740873aa2897576bf476cc5ce46bccadc3105 | 485 | h | C | src/add-ons/translators/wonderbrush/support/bitmap_compression.h | Kirishikesan/haiku | 835565c55830f2dab01e6e332cc7e2d9c015b51e | [
"MIT"
] | 1,338 | 2015-01-03T20:06:56.000Z | 2022-03-26T13:49:54.000Z | src/add-ons/translators/wonderbrush/support/bitmap_compression.h | Kirishikesan/haiku | 835565c55830f2dab01e6e332cc7e2d9c015b51e | [
"MIT"
] | 15 | 2015-01-17T22:19:32.000Z | 2021-12-20T12:35:00.000Z | src/add-ons/translators/wonderbrush/support/bitmap_compression.h | Kirishikesan/haiku | 835565c55830f2dab01e6e332cc7e2d9c015b51e | [
"MIT"
] | 350 | 2015-01-08T14:15:27.000Z | 2022-03-21T18:14:35.000Z | /*
* Copyright 2006, Haiku. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Authors:
* Stephan Aßmus <superstippi@gmx.de>
*/
#ifndef BITMAP_COMPRESSION_H
#define BITMAP_COMPRESSION_H
#include <SupportDefs.h>
class BBitmap;
class BMessage;
status_t
archive_bitmap(const BBitmap* bitmap, BMessage* into, const char* fieldName);
status_t
extract_bitmap(BBitmap** bitmap, const BMessage* from, const char* fieldName);
#endif // BITMAP_COMPRESSION_H
| 20.208333 | 78 | 0.762887 |
1cab6d45c5d64263caca697abd476c54154ca5be | 2,487 | h | C | src/lib/lists/includes/cl_list.h | vndmtrx/libadt | 648b5b3004d1188c654e367cd677d52b742081d1 | [
"MIT"
] | 10 | 2015-06-09T21:04:45.000Z | 2018-11-21T14:50:50.000Z | src/lib/lists/includes/cl_list.h | vndmtrx/libadt | 648b5b3004d1188c654e367cd677d52b742081d1 | [
"MIT"
] | 23 | 2015-06-15T23:54:57.000Z | 2018-03-26T18:13:29.000Z | src/lib/lists/includes/cl_list.h | vndmtrx/libadt | 648b5b3004d1188c654e367cd677d52b742081d1 | [
"MIT"
] | 2 | 2018-01-25T01:38:13.000Z | 2018-08-23T17:49:16.000Z | #ifndef _LIBADT_CL_LIST_H
#define _LIBADT_CL_LIST_H
#include <list_commons.h>
typedef list_root cl_list_root;
/*
* Get the next element of the list based on current element.
* If the current is NULL, return NULL instead.
* Complexity: O(1).
*/
list_node * cl_list_next(list_node *current);
/*
* Get the previous element of the list based on current element.
* If the current is NULL, return NULL instead.
* Complexity: O(1).
*/
list_node * cl_list_prev(list_node *current);
/*
* Get the data from the current element.
* If the current is NULL, return NULL instead.
* Complexity: O(1).
*/
void * cl_list_get_data(list_node *current);
/*
* Create a empty list structure and set a destroy function for its elements.
* The destroy argument gives a way to free the entire structure when we
* call cl_list_destroy. For malloc/calloc data, free must be used. If data
* is a struct with other members, a function designed to free its memory
* must be provided. If the data is static or have another way to free its
* memory, NULL must be set.
* Complexity: O(1).
*/
cl_list_root * cl_list_create(t_destroyfunc destroyfunc, enum list_insert_el_mode mode);
/*
* Insert an element in the list after the current element indicated.
* If *current is NULL, the new element is set as head.
* Complexity: O(1).
*/
int cl_list_insert_el_next(cl_list_root *list, list_node *current, void *data);
/*
* Insert an element in the list before the current element indicated.
* If *current is NULL, the new element is set as head.
* Complexity: O(1).
*/
int cl_list_insert_el_prev(cl_list_root *list, list_node *current, void *data);
/*
* Move an element after the newpos element indicated.
* Complexity: O(1).
*/
int cl_list_move_el_next(cl_list_root *list, list_node *current, list_node *newpos);
/*
* Move an element before the newpos element indicated.
* Complexity: O(1).
*/
int cl_list_move_el_prev(cl_list_root *list, list_node *current, list_node *newpos);
/*
* Change positions of the two elements on the list.
* Complexity: O(1).
*/
int cl_list_swap_el(cl_list_root *list, list_node *el1, list_node *el2);
/*
* Remove the element in the head and save the respective data in **data.
* Compĺexity: O(1).
*/
void * cl_list_rem_el(cl_list_root *list, list_node *current);
/*
* Destroy the list and its elements, if have any. If destroy function is provided,
* it will be used.
* Complexity: O(n).
*/
void cl_list_destroy(cl_list_root *list);
#endif
| 28.918605 | 88 | 0.731805 |
975afaefc7f1f3fe625fac44418e68c970f6e69b | 232 | h | C | NetEaseMusic/NetEaseMusic/Classes/Config/CAppConst/SXAppConst.h | SunXu231/NetEaseMusic---Object-C | 23b62eb4ae89dc8ea4114cf3e1973804e360133e | [
"MIT"
] | 2 | 2019-07-05T07:14:31.000Z | 2019-07-08T07:09:55.000Z | NetEaseMusic/NetEaseMusic/Classes/Config/CAppConst/SXAppConst.h | SunXu231/NetEaseMusic---Object-C | 23b62eb4ae89dc8ea4114cf3e1973804e360133e | [
"MIT"
] | null | null | null | NetEaseMusic/NetEaseMusic/Classes/Config/CAppConst/SXAppConst.h | SunXu231/NetEaseMusic---Object-C | 23b62eb4ae89dc8ea4114cf3e1973804e360133e | [
"MIT"
] | null | null | null | //
// SXAppConst.h
// MVVM Without Binding With DataController
//
// Created by sunxu on 2017/3/17.
// Copyright © 2017年 Sun Xu. All rights reserved.
//
#import <Foundation/Foundation.h>
@interface SXAppConst : NSObject
@end
| 16.571429 | 50 | 0.702586 |
9779f2342a519bf9dc84c19cc0e535af0b8d6775 | 1,060 | h | C | BENDijkstra/BENPoint.h | bmichotte/BENDijkstra | 63df8b208c92289bf7be843a94b3e81d39234939 | [
"MIT"
] | 1 | 2015-07-27T16:18:12.000Z | 2015-07-27T16:18:12.000Z | BENDijkstra/BENPoint.h | bmichotte/BENDijkstra | 63df8b208c92289bf7be843a94b3e81d39234939 | [
"MIT"
] | null | null | null | BENDijkstra/BENPoint.h | bmichotte/BENDijkstra | 63df8b208c92289bf7be843a94b3e81d39234939 | [
"MIT"
] | 1 | 2019-04-16T08:08:58.000Z | 2019-04-16T08:08:58.000Z | //
// BENPoint.h
// BENDijkstra
//
// Created by Benjamin Michotte on 18/07/13.
// Copyright (c) 2013 Benjamin Michotte. All rights reserved.
//
#import <Foundation/Foundation.h>
/**
* This class represent a point with x and y coordinates.
* It also contains links to other points.
*/
@interface BENPoint : NSObject
/**
Convenient initializer
*/
+ (BENPoint *)pointWithX:(NSInteger)x y:(NSInteger)y;
/** The X coordinate of the point */
@property (nonatomic, assign) NSInteger x;
/** The Y coordinate of the point */
@property (nonatomic, assign) NSInteger y;
/** The BMPoints linked to this point */
@property (nonatomic, readonly) NSArray *linkedPoints;
/** Identify the point by the concatenation of x and y */
@property (nonatomic, readonly) NSString *ref;
/**
* Add a link between two points
* @param point The BMPoint to link with
*/
- (void)addLinkedPoint:(BENPoint *)point;
/**
* Find the distance between two BMPoint
* @param point The other point
* @return double The distance
*/
- (double)distance:(BENPoint *)point;
@end
| 22.083333 | 62 | 0.701887 |
1c07dbadf639690f03ed40b749bad07b0a76c00f | 2,224 | c | C | hello-openshift.c | sixtyeight/s2i-hello-openshift-nes-example | 683afcf611ceb11a916a6438a4ef0fc2cf2e130c | [
"MIT"
] | null | null | null | hello-openshift.c | sixtyeight/s2i-hello-openshift-nes-example | 683afcf611ceb11a916a6438a4ef0fc2cf2e130c | [
"MIT"
] | null | null | null | hello-openshift.c | sixtyeight/s2i-hello-openshift-nes-example | 683afcf611ceb11a916a6438a4ef0fc2cf2e130c | [
"MIT"
] | null | null | null | /* simple Hello World for OpenShift nes-s2i builder for cc65, for NES
* Based on example code by Doug Fraker
* using neslib
*/
#include "neslib.h"
#include "MoreLib.c"
#define PPU_CTRL *((unsigned char*)0x2000)
#define PPU_MASK *((unsigned char*)0x2001)
#define PPU_STATUS *((unsigned char*)0x2002)
#define SCROLL *((unsigned char*)0x2005)
#define PPU_ADDRESS *((unsigned char*)0x2006)
#define PPU_DATA *((unsigned char*)0x2007)
#define FP_BITS 4
const unsigned char palette[16]={ 0x0f,0x00,0x16,0x30,0x0f,0x01,0x21,0x31,0x0f,0x06,0x16,0x26,0x0f,0x09,0x19,0x29 };
int index;
void write_str(unsigned char x, unsigned char y, unsigned char *str) {
while( *str != 0) {
vram_adr(NTADR_A(x, y));
PPU_DATA = *str;
++str;
++x;
}
}
void render_logo(unsigned int x, unsigned int y) {
unsigned char *tile = (unsigned char *) 0x80; // start of logo in charset A
unsigned int left = 16; // width of logo
vram_adr(NTADR_A(x, y));
while(tile <= (unsigned char *) 0xFF) { // end of logo in charset A
PPU_DATA = tile;
++tile;
--left;
if(left == 0) {
y++;
vram_adr(NTADR_A(x, y));
left = 16;
}
}
}
unsigned char buf[256]={};
void type_str(unsigned char x, unsigned char y, unsigned char *str, unsigned char _delay) {
while( *str != 0) {
buf[0] = MSB(NTADR_A(x,y))|NT_UPD_HORZ;
buf[1] = LSB(NTADR_A(x,y));
buf[2] = 1; // 1 write
buf[3] = *str; // tile #
buf[4] = NT_UPD_EOF;
set_vram_update(buf);
++str;
++x;
if(_delay > 0) {
delay(_delay);
} else {
delay(1);
}
}
set_vram_update(NULL);
}
void clear_line(unsigned char row) {
type_str(1, row, " ", 0);
}
unsigned int s;
void main (void) {
pal_bg(palette);
render_logo(1, 1);
ppu_on_all();
scroll(0, 0);
while (1) {
delay(40);
type_str(1, 10, (unsigned char *) "Red Hat [ OpenShift", 3); // square bracket is actually defined as dash symbol in tileset
type_str(1, 12, (unsigned char *) "s2i NES builder example", 3);
delay(40);
clear_line(10);
clear_line(12);
s=0;
while(s<256) {
delay(1);
scroll(s, 0);
++s;
}
}
};
| 21.803922 | 127 | 0.593525 |
5a1bd7765b24c941582a2e040aac5bc3982e4b24 | 3,178 | h | C | src/highScore.h | nholthaus/minesweeper | 27a2bb3a434b2e89545de95b29aa255ae483e124 | [
"MIT"
] | 9 | 2017-10-08T15:20:08.000Z | 2022-03-11T03:27:38.000Z | src/highScore.h | tatokis/minesweeper | 65cd025364ea72fe7e333a7524d803e6139cfed2 | [
"MIT"
] | 3 | 2019-10-25T19:04:10.000Z | 2019-10-25T19:04:35.000Z | src/highScore.h | tatokis/minesweeper | 65cd025364ea72fe7e333a7524d803e6139cfed2 | [
"MIT"
] | 3 | 2019-01-16T12:38:52.000Z | 2021-02-09T15:40:22.000Z | //--------------------------------------------------------------------------------------------------
//
// The MIT License (MIT)
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software
// and associated documentation files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or
// substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
// BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
// DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//--------------------------------------------------------------------------------------------------
//
// Copyright (c) 2017 Nic Holthaus
//
//--------------------------------------------------------------------------------------------------
//
// ATTRIBUTION:
//
//
//--------------------------------------------------------------------------------------------------
//
/// @file highScore.h
/// @brief Class to contain a minesweeper high score
//
//--------------------------------------------------------------------------------------------------
#pragma once
//-------------------------
// INCLUDES
//-------------------------
#include <QString>
#include <QDataStream>
#include <QDateTime>
//-------------------------
// FORWARD DECLARATIONS
//-------------------------
class HighScoreModel;
//--------------------------------------------------------------------------------------------------
// CLASS HIGHSCORE
//--------------------------------------------------------------------------------------------------
class HighScore : public QObject
{
Q_OBJECT
public:
enum Difficulty
{
beginner,
intermediate,
expert,
custom,
};
Q_ENUM(Difficulty);
public:
HighScore() = default;
HighScore(QString name, Difficulty difficulty, quint32 score, QDateTime date);
HighScore(const HighScore& other);
HighScore& operator=(const HighScore& other);
QString name() const;
Difficulty difficulty() const;
quint32 score() const;
QDateTime date() const;
void setName(QString name);
void setDifficultty(Difficulty difficulty);
void setScore(quint32 score);
void setDate(QDateTime date);
bool operator<(const HighScore& rhs) const;
bool operator==(const HighScore& rhs) const;
friend HighScoreModel;
private:
QString m_name;
Difficulty m_difficulty;
quint32 m_score;
QDateTime m_date;
};
Q_DECLARE_METATYPE(HighScore);
QDataStream &operator<<(QDataStream &out, const HighScore&);
QDataStream &operator>>(QDataStream &in, HighScore&); | 30.854369 | 100 | 0.554437 |
f6af6aebbbe7fc00935cc4735e9e4e3631178b0a | 2,761 | h | C | Other/UltraPanBase/Source/SpeakerSet.h | jdsierral/UltraPan-FinalProject | 760888e81647786eebbabd4bff8a45b87d8bd339 | [
"Unlicense"
] | null | null | null | Other/UltraPanBase/Source/SpeakerSet.h | jdsierral/UltraPan-FinalProject | 760888e81647786eebbabd4bff8a45b87d8bd339 | [
"Unlicense"
] | null | null | null | Other/UltraPanBase/Source/SpeakerSet.h | jdsierral/UltraPan-FinalProject | 760888e81647786eebbabd4bff8a45b87d8bd339 | [
"Unlicense"
] | null | null | null | /*
==============================================================================
SpeakerSet.h
Created: 26 Nov 2016 3:15:12pm
Author: Juan David Sierra
==============================================================================
*/
#ifndef SPEAKERSET_H_INCLUDED
#define SPEAKERSET_H_INCLUDED
#include "Dsp.h"
#include "../JuceLibraryCode/JuceHeader.h"
struct Speaker{
void init(int SR) {
dsp.buildUserInterface(¶ms);
dsp.init(SR);
}
void compute() {
int bufSize = buffer.getNumSamples();
float** data = buffer.getArrayOfWritePointers();
dsp.compute(bufSize, data, data);
}
Dsp dsp;
MapUI params;
Vector3D<float> pos;
AudioSampleBuffer buffer;
String name;
/*
Params
/Sp/delay
/Sp/gain
*/
};
class SpeakerSet{
public:
SpeakerSet();
~SpeakerSet();
//=================================================================
void init(int sampleRate);
//=================================================================
void setNumSpeakers(int newNumSpeakers);
void setBufferSize(int bufSize);
//=================================================================
void setSourcePos(Vector3D<float> newSourcePos);
void setSourcePosX(float newPosX);
void setSourcePosY(float newPosY);
void setSourcePosZ(float newPosZ);
void setSpeakerPos(int sp, Vector3D<float> newPos);
void setSpeakerPosX(int sp, float newPosX);
void setSpeakerPosY(int sp, float newPosY);
void setSpeakerPosZ(int sp, float newPosZ);
void setBase (float newBase);
void setScale (float newScale);
//=================================================================
Vector3D<float> getSourcePosition();
Vector3D<float> getSpeakerPos(int numSpeaker);
float getSpeakerGain(int numSpeaker);
float getSpeakerDelay(int numSpeaker);
String getSpeakerName(int numSpeaker);
float getBase();
float getScale();
//=================================================================
void compute(AudioSampleBuffer& inBuffer, AudioSampleBuffer& outBuffer);
//=================================================================
private:
void updateAllSpeakers();
void updateSpeaker(int numSpeaker);
void checkMinDistance();
void printParam(int sp);
//=================================================================
int totalNumSpeakers;
Vector3D<float> sourcePos;
OwnedArray<Speaker> speakers;
float base;
float scale; // maybe it wont be needed;
float SR;
float minDist;
const float c = 340.f;//m/s
// fmOsc.init(sampleRate);
// fmOsc.buildUserInterface(&oscParams);
// fmOsc.compute(bufSize, NULL, audioBuf);
};
#endif // SPEAKERSET_H_INCLUDED
| 23.201681 | 81 | 0.524448 |
0c542bead9de229bba271dd453bec5c75f68a961 | 25,890 | h | C | Vulkan/jni/bor.vulkan.structs.VkWriteDescriptorSet.h | AlessandroBorges/Bor_Vulkan | 3847e6f44ce7f14dfc1e671a6cc51eb4788e4e4b | [
"MIT"
] | 14 | 2016-02-29T12:30:05.000Z | 2020-09-17T11:30:50.000Z | Vulkan/jni/bor.vulkan.structs.VkWriteDescriptorSet.h | AlessandroBorges/Bor_Vulkan | 3847e6f44ce7f14dfc1e671a6cc51eb4788e4e4b | [
"MIT"
] | 2 | 2016-09-13T18:02:55.000Z | 2019-11-03T01:54:20.000Z | Vulkan/jni/bor.vulkan.structs.VkWriteDescriptorSet.h | AlessandroBorges/Bor_Vulkan | 3847e6f44ce7f14dfc1e671a6cc51eb4788e4e4b | [
"MIT"
] | 5 | 2017-09-19T03:09:06.000Z | 2021-11-23T20:20:52.000Z | /* DO NOT EDIT THIS FILE - it is machine generated */
#include <jni.h>
/* Header for class bor_vulkan_structs_VkWriteDescriptorSet */
#ifndef _Included_bor_vulkan_structs_VkWriteDescriptorSet
#define _Included_bor_vulkan_structs_VkWriteDescriptorSet
#ifdef __cplusplus
extern "C" {
#endif
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKAPPLICATIONINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKAPPLICATIONINFO_ID 1L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKINSTANCECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKINSTANCECREATEINFO_ID 2L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKALLOCATIONCALLBACKS_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKALLOCATIONCALLBACKS_ID 3L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPHYSICALDEVICEFEATURES_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPHYSICALDEVICEFEATURES_ID 4L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKFORMATPROPERTIES_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKFORMATPROPERTIES_ID 5L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKEXTENT3D_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKEXTENT3D_ID 6L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGEFORMATPROPERTIES_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGEFORMATPROPERTIES_ID 7L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPHYSICALDEVICELIMITS_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPHYSICALDEVICELIMITS_ID 8L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPHYSICALDEVICESPARSEPROPERTIES_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPHYSICALDEVICESPARSEPROPERTIES_ID 9L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPHYSICALDEVICEPROPERTIES_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPHYSICALDEVICEPROPERTIES_ID 10L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKQUEUEFAMILYPROPERTIES_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKQUEUEFAMILYPROPERTIES_ID 11L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKMEMORYTYPE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKMEMORYTYPE_ID 12L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKMEMORYHEAP_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKMEMORYHEAP_ID 13L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPHYSICALDEVICEMEMORYPROPERTIES_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPHYSICALDEVICEMEMORYPROPERTIES_ID 14L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDEVICEQUEUECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDEVICEQUEUECREATEINFO_ID 15L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDEVICECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDEVICECREATEINFO_ID 16L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKEXTENSIONPROPERTIES_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKEXTENSIONPROPERTIES_ID 17L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKLAYERPROPERTIES_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKLAYERPROPERTIES_ID 18L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSUBMITINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSUBMITINFO_ID 19L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKMEMORYALLOCATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKMEMORYALLOCATEINFO_ID 20L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKMAPPEDMEMORYRANGE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKMAPPEDMEMORYRANGE_ID 21L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKMEMORYREQUIREMENTS_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKMEMORYREQUIREMENTS_ID 22L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEIMAGEFORMATPROPERTIES_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEIMAGEFORMATPROPERTIES_ID 23L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEIMAGEMEMORYREQUIREMENTS_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEIMAGEMEMORYREQUIREMENTS_ID 24L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEMEMORYBIND_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEMEMORYBIND_ID 25L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEBUFFERMEMORYBINDINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEBUFFERMEMORYBINDINFO_ID 26L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEIMAGEOPAQUEMEMORYBINDINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEIMAGEOPAQUEMEMORYBINDINFO_ID 27L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGESUBRESOURCE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGESUBRESOURCE_ID 28L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKOFFSET3D_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKOFFSET3D_ID 29L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEIMAGEMEMORYBIND_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEIMAGEMEMORYBIND_ID 30L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEIMAGEMEMORYBINDINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSPARSEIMAGEMEMORYBINDINFO_ID 31L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKBINDSPARSEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKBINDSPARSEINFO_ID 32L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKFENCECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKFENCECREATEINFO_ID 33L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSEMAPHORECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSEMAPHORECREATEINFO_ID 34L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKEVENTCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKEVENTCREATEINFO_ID 35L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKQUERYPOOLCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKQUERYPOOLCREATEINFO_ID 36L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKBUFFERCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKBUFFERCREATEINFO_ID 37L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKBUFFERVIEWCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKBUFFERVIEWCREATEINFO_ID 38L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGECREATEINFO_ID 39L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSUBRESOURCELAYOUT_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSUBRESOURCELAYOUT_ID 40L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCOMPONENTMAPPING_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCOMPONENTMAPPING_ID 41L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGESUBRESOURCERANGE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGESUBRESOURCERANGE_ID 42L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGEVIEWCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGEVIEWCREATEINFO_ID 43L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSHADERMODULECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSHADERMODULECREATEINFO_ID 44L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINECACHECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINECACHECREATEINFO_ID 45L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSPECIALIZATIONMAPENTRY_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSPECIALIZATIONMAPENTRY_ID 46L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSPECIALIZATIONINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSPECIALIZATIONINFO_ID 47L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINESHADERSTAGECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINESHADERSTAGECREATEINFO_ID 48L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKVERTEXINPUTBINDINGDESCRIPTION_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKVERTEXINPUTBINDINGDESCRIPTION_ID 49L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKVERTEXINPUTATTRIBUTEDESCRIPTION_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKVERTEXINPUTATTRIBUTEDESCRIPTION_ID 50L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEVERTEXINPUTSTATECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEVERTEXINPUTSTATECREATEINFO_ID 51L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEINPUTASSEMBLYSTATECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEINPUTASSEMBLYSTATECREATEINFO_ID 52L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINETESSELLATIONSTATECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINETESSELLATIONSTATECREATEINFO_ID 53L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKVIEWPORT_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKVIEWPORT_ID 54L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKOFFSET2D_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKOFFSET2D_ID 55L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKEXTENT2D_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKEXTENT2D_ID 56L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKRECT2D_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKRECT2D_ID 57L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEVIEWPORTSTATECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEVIEWPORTSTATECREATEINFO_ID 58L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINERASTERIZATIONSTATECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINERASTERIZATIONSTATECREATEINFO_ID 59L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEMULTISAMPLESTATECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEMULTISAMPLESTATECREATEINFO_ID 60L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSTENCILOPSTATE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSTENCILOPSTATE_ID 61L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEDEPTHSTENCILSTATECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEDEPTHSTENCILSTATECREATEINFO_ID 62L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINECOLORBLENDATTACHMENTSTATE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINECOLORBLENDATTACHMENTSTATE_ID 63L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINECOLORBLENDSTATECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINECOLORBLENDSTATECREATEINFO_ID 64L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEDYNAMICSTATECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINEDYNAMICSTATECREATEINFO_ID 65L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKGRAPHICSPIPELINECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKGRAPHICSPIPELINECREATEINFO_ID 66L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCOMPUTEPIPELINECREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCOMPUTEPIPELINECREATEINFO_ID 67L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPUSHCONSTANTRANGE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPUSHCONSTANTRANGE_ID 68L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINELAYOUTCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINELAYOUTCREATEINFO_ID 69L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSAMPLERCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSAMPLERCREATEINFO_ID 70L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORSETLAYOUTBINDING_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORSETLAYOUTBINDING_ID 71L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORSETLAYOUTCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORSETLAYOUTCREATEINFO_ID 72L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORPOOLSIZE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORPOOLSIZE_ID 73L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORPOOLCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORPOOLCREATEINFO_ID 74L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORSETALLOCATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORSETALLOCATEINFO_ID 75L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORIMAGEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORIMAGEINFO_ID 76L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORBUFFERINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDESCRIPTORBUFFERINFO_ID 77L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKWRITEDESCRIPTORSET_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKWRITEDESCRIPTORSET_ID 78L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCOPYDESCRIPTORSET_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCOPYDESCRIPTORSET_ID 79L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKFRAMEBUFFERCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKFRAMEBUFFERCREATEINFO_ID 80L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKATTACHMENTDESCRIPTION_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKATTACHMENTDESCRIPTION_ID 81L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKATTACHMENTREFERENCE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKATTACHMENTREFERENCE_ID 82L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSUBPASSDESCRIPTION_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSUBPASSDESCRIPTION_ID 83L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSUBPASSDEPENDENCY_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSUBPASSDEPENDENCY_ID 84L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKRENDERPASSCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKRENDERPASSCREATEINFO_ID 85L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCOMMANDPOOLCREATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCOMMANDPOOLCREATEINFO_ID 86L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCOMMANDBUFFERALLOCATEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCOMMANDBUFFERALLOCATEINFO_ID 87L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCOMMANDBUFFERINHERITANCEINFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCOMMANDBUFFERINHERITANCEINFO_ID 88L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCOMMANDBUFFERBEGININFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCOMMANDBUFFERBEGININFO_ID 89L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKBUFFERCOPY_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKBUFFERCOPY_ID 90L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGESUBRESOURCELAYERS_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGESUBRESOURCELAYERS_ID 91L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGECOPY_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGECOPY_ID 92L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGEBLIT_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGEBLIT_ID 93L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKBUFFERIMAGECOPY_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKBUFFERIMAGECOPY_ID 94L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCLEARDEPTHSTENCILVALUE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCLEARDEPTHSTENCILVALUE_ID 95L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCLEARATTACHMENT_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCLEARATTACHMENT_ID 96L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCLEARRECT_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCLEARRECT_ID 97L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGERESOLVE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGERESOLVE_ID 98L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKMEMORYBARRIER_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKMEMORYBARRIER_ID 99L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKBUFFERMEMORYBARRIER_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKBUFFERMEMORYBARRIER_ID 100L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGEMEMORYBARRIER_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKIMAGEMEMORYBARRIER_ID 101L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKRENDERPASSBEGININFO_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKRENDERPASSBEGININFO_ID 102L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDISPATCHINDIRECTCOMMAND_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDISPATCHINDIRECTCOMMAND_ID 103L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDRAWINDEXEDINDIRECTCOMMAND_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDRAWINDEXEDINDIRECTCOMMAND_ID 104L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDRAWINDIRECTCOMMAND_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDRAWINDIRECTCOMMAND_ID 105L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSURFACECAPABILITIESKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSURFACECAPABILITIESKHR_ID 106L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSURFACEFORMATKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSURFACEFORMATKHR_ID 107L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKSWAPCHAINCREATEINFOKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKSWAPCHAINCREATEINFOKHR_ID 108L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPRESENTINFOKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPRESENTINFOKHR_ID 109L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYPROPERTIESKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYPROPERTIESKHR_ID 110L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYMODEPARAMETERSKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYMODEPARAMETERSKHR_ID 111L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYMODEPROPERTIESKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYMODEPROPERTIESKHR_ID 112L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYMODECREATEINFOKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYMODECREATEINFOKHR_ID 113L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYPLANECAPABILITIESKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYPLANECAPABILITIESKHR_ID 114L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYPLANEPROPERTIESKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYPLANEPROPERTIESKHR_ID 115L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYSURFACECREATEINFOKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYSURFACECREATEINFOKHR_ID 116L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYPRESENTINFOKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDISPLAYPRESENTINFOKHR_ID 117L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKXLIBSURFACECREATEINFOKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKXLIBSURFACECREATEINFOKHR_ID 118L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKXCBSURFACECREATEINFOKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKXCBSURFACECREATEINFOKHR_ID 119L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKWAYLANDSURFACECREATEINFOKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKWAYLANDSURFACECREATEINFOKHR_ID 120L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKMIRSURFACECREATEINFOKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKMIRSURFACECREATEINFOKHR_ID 121L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKANDROIDSURFACECREATEINFOKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKANDROIDSURFACECREATEINFOKHR_ID 122L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKWIN32SURFACECREATEINFOKHR_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKWIN32SURFACECREATEINFOKHR_ID 123L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDEBUGREPORTCALLBACKCREATEINFOEXT_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDEBUGREPORTCALLBACKCREATEINFOEXT_ID 124L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINERASTERIZATIONSTATERASTERIZATIONORDERAMD_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKPIPELINERASTERIZATIONSTATERASTERIZATIONORDERAMD_ID 125L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDEBUGMARKEROBJECTNAMEINFOEXT_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDEBUGMARKEROBJECTNAMEINFOEXT_ID 126L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDEBUGMARKEROBJECTTAGINFOEXT_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDEBUGMARKEROBJECTTAGINFOEXT_ID 127L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDEBUGMARKERMARKERINFOEXT_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDEBUGMARKERMARKERINFOEXT_ID 128L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDEDICATEDALLOCATIONIMAGECREATEINFONV_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDEDICATEDALLOCATIONIMAGECREATEINFONV_ID 129L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDEDICATEDALLOCATIONBUFFERCREATEINFONV_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDEDICATEDALLOCATIONBUFFERCREATEINFONV_ID 130L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKDEDICATEDALLOCATIONMEMORYALLOCATEINFONV_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKDEDICATEDALLOCATIONMEMORYALLOCATEINFONV_ID 131L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCLEARVALUE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCLEARVALUE_ID 200L
#undef bor_vulkan_structs_VkWriteDescriptorSet_VKCLEARCOLORVALUE_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_VKCLEARCOLORVALUE_ID 201L
#undef bor_vulkan_structs_VkWriteDescriptorSet_TAG_ID
#define bor_vulkan_structs_VkWriteDescriptorSet_TAG_ID 78L
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: setSType0
* Signature: (Ljava/nio/Buffer;I)V
*/
JNIEXPORT void JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_setSType0
(JNIEnv *, jclass, jobject, jint);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: getSType0
* Signature: (Ljava/nio/Buffer;)I
*/
JNIEXPORT jint JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_getSType0
(JNIEnv *, jclass, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: setPNext0
* Signature: (Ljava/nio/Buffer;Ljava/nio/ByteBuffer;)V
*/
JNIEXPORT void JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_setPNext0
(JNIEnv *, jclass, jobject, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: getPNext0
* Signature: (Ljava/nio/Buffer;)J
*/
JNIEXPORT jlong JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_getPNext0
(JNIEnv *, jclass, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: setDstSet0
* Signature: (Ljava/nio/Buffer;J)V
*/
JNIEXPORT void JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_setDstSet0
(JNIEnv *, jclass, jobject, jlong);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: getDstSet0
* Signature: (Ljava/nio/Buffer;)J
*/
JNIEXPORT jlong JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_getDstSet0
(JNIEnv *, jclass, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: setDstBinding0
* Signature: (Ljava/nio/Buffer;I)V
*/
JNIEXPORT void JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_setDstBinding0
(JNIEnv *, jclass, jobject, jint);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: getDstBinding0
* Signature: (Ljava/nio/Buffer;)I
*/
JNIEXPORT jint JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_getDstBinding0
(JNIEnv *, jclass, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: setDstArrayElement0
* Signature: (Ljava/nio/Buffer;I)V
*/
JNIEXPORT void JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_setDstArrayElement0
(JNIEnv *, jclass, jobject, jint);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: getDstArrayElement0
* Signature: (Ljava/nio/Buffer;)I
*/
JNIEXPORT jint JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_getDstArrayElement0
(JNIEnv *, jclass, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: setDescriptorCount0
* Signature: (Ljava/nio/Buffer;I)V
*/
JNIEXPORT void JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_setDescriptorCount0
(JNIEnv *, jclass, jobject, jint);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: getDescriptorCount0
* Signature: (Ljava/nio/Buffer;)I
*/
JNIEXPORT jint JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_getDescriptorCount0
(JNIEnv *, jclass, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: setDescriptorType0
* Signature: (Ljava/nio/Buffer;I)V
*/
JNIEXPORT void JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_setDescriptorType0
(JNIEnv *, jclass, jobject, jint);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: getDescriptorType0
* Signature: (Ljava/nio/Buffer;)I
*/
JNIEXPORT jint JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_getDescriptorType0
(JNIEnv *, jclass, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: setPImageInfo0
* Signature: (Ljava/nio/Buffer;Ljava/nio/ByteBuffer;)V
*/
JNIEXPORT void JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_setPImageInfo0
(JNIEnv *, jclass, jobject, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: getPImageInfo0
* Signature: (Ljava/nio/Buffer;)J
*/
JNIEXPORT jlong JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_getPImageInfo0
(JNIEnv *, jclass, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: setPBufferInfo0
* Signature: (Ljava/nio/Buffer;Ljava/nio/ByteBuffer;)V
*/
JNIEXPORT void JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_setPBufferInfo0
(JNIEnv *, jclass, jobject, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: getPBufferInfo0
* Signature: (Ljava/nio/Buffer;)J
*/
JNIEXPORT jlong JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_getPBufferInfo0
(JNIEnv *, jclass, jobject);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: setPTexelBufferView0
* Signature: (Ljava/nio/Buffer;J)V
*/
JNIEXPORT void JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_setPTexelBufferView0
(JNIEnv *, jclass, jobject, jlong);
/*
* Class: bor_vulkan_structs_VkWriteDescriptorSet
* Method: getPTexelBufferView0
* Signature: (Ljava/nio/Buffer;)J
*/
JNIEXPORT jlong JNICALL Java_bor_vulkan_structs_VkWriteDescriptorSet_getPTexelBufferView0
(JNIEnv *, jclass, jobject);
#ifdef __cplusplus
}
#endif
#endif
| 58.574661 | 105 | 0.918617 |
8c89bbd2ea404450378241dac44e3b128480e874 | 260 | c | C | gcc-gcc-7_3_0-release/gcc/testsuite/gcc.dg/torture/pr68906.c | best08618/asylo | 5a520a9f5c461ede0f32acc284017b737a43898c | [
"Apache-2.0"
] | 7 | 2020-05-02T17:34:05.000Z | 2021-10-17T10:15:18.000Z | gcc-gcc-7_3_0-release/gcc/testsuite/gcc.dg/torture/pr68906.c | best08618/asylo | 5a520a9f5c461ede0f32acc284017b737a43898c | [
"Apache-2.0"
] | null | null | null | gcc-gcc-7_3_0-release/gcc/testsuite/gcc.dg/torture/pr68906.c | best08618/asylo | 5a520a9f5c461ede0f32acc284017b737a43898c | [
"Apache-2.0"
] | 2 | 2020-07-27T00:22:36.000Z | 2021-04-01T09:41:02.000Z | /* { dg-do compile } */
/* { dg-options "-O3" } */
int a;
volatile int b;
short c, d;
int
fn1 ()
{
int e;
for (;;)
{
a = 3;
if (c)
continue;
e = 0;
for (; e > -30; e--)
if (b)
{
int f = e;
return d;
}
}
}
| 10.4 | 26 | 0.365385 |
86e8facb1e73d76491a5b432447330b1325a55b6 | 342 | h | C | include/unirender/DepthRange.h | xzrunner/unirender | 2b26554eaf71230e1553409c3a1bff20898d970d | [
"MIT"
] | null | null | null | include/unirender/DepthRange.h | xzrunner/unirender | 2b26554eaf71230e1553409c3a1bff20898d970d | [
"MIT"
] | null | null | null | include/unirender/DepthRange.h | xzrunner/unirender | 2b26554eaf71230e1553409c3a1bff20898d970d | [
"MIT"
] | null | null | null | #pragma once
namespace ur
{
struct DepthRange
{
double d_near = 0.0;
double d_far = 1.0;
bool operator == (const DepthRange& dr) const {
return d_near == dr.d_near
&& d_far == dr.d_far;
}
bool operator != (const DepthRange& dr) const {
return !operator == (dr);
}
}; // DepthRange
}
| 14.869565 | 51 | 0.555556 |
81128c7c956f09c02a7e93fc12a1f4bf91db1d0e | 618 | h | C | Sample Code/ObjcSampleCode/DJISdkDemo/Demo/Accessory/speaker/record/RecordingHandler.h | Matheus193dn/Mobile-SDK-iOS | 9403dbfddd7c32cf95cf007beebcc8878f65b96a | [
"MIT"
] | 575 | 2015-09-28T13:23:47.000Z | 2022-03-21T15:54:56.000Z | Sample Code/ObjcSampleCode/DJISdkDemo/Demo/Accessory/speaker/record/RecordingHandler.h | Matheus193dn/Mobile-SDK-iOS | 9403dbfddd7c32cf95cf007beebcc8878f65b96a | [
"MIT"
] | 483 | 2015-09-29T07:52:04.000Z | 2022-03-31T05:19:14.000Z | Sample Code/ObjcSampleCode/DJISdkDemo/Demo/Accessory/speaker/record/RecordingHandler.h | Matheus193dn/Mobile-SDK-iOS | 9403dbfddd7c32cf95cf007beebcc8878f65b96a | [
"MIT"
] | 292 | 2015-09-30T09:14:10.000Z | 2022-03-25T20:02:35.000Z | //
// RecordingHandler.h
// DJISdkDemo
//
// Copyright © 2018 DJI. All rights reserved.
//
#import <Foundation/Foundation.h>
NS_ASSUME_NONNULL_BEGIN
@class RecordingHandler;
@protocol RecordingHandlerDelegate <NSObject>
- (void)recordingHandler:(RecordingHandler *)handler output:(NSData *)pcmData;
@end
@interface RecordingHandler : NSObject
@property (nonatomic, weak) id<RecordingHandlerDelegate> delegate;
@property (nonatomic) BOOL isRecording;
- (instancetype)initWithSampleRate:(Float64)sampleRate channelsPerFrame:(UInt32)channelPerFrame;
- (void)start;
- (void)stop;
@end
NS_ASSUME_NONNULL_END
| 18.727273 | 96 | 0.778317 |
7bc5604b4ca8aa98aad6a947ef1f79eb2b5b1406 | 4,307 | h | C | src/common/config-file.h | somaen/Wintermute-git | edd11774a2662c55f1ebd6386206a41da37bcd18 | [
"MIT"
] | 1 | 2015-08-15T21:51:37.000Z | 2015-08-15T21:51:37.000Z | src/common/config-file.h | somaen/Wintermute-git | edd11774a2662c55f1ebd6386206a41da37bcd18 | [
"MIT"
] | null | null | null | src/common/config-file.h | somaen/Wintermute-git | edd11774a2662c55f1ebd6386206a41da37bcd18 | [
"MIT"
] | null | null | null | /* ScummVM - Graphic Adventure Engine
*
* ScummVM is the legal property of its developers, whose names
* are too numerous to list here. Please refer to the COPYRIGHT
* file distributed with this source distribution.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
*/
#ifndef COMMON_CONFIG_FILE_H
#define COMMON_CONFIG_FILE_H
#include "common/hash-str.h"
#include "common/list.h"
#include "common/str.h"
namespace Common {
class SeekableReadStream;
class WriteStream;
/**
* This class allows reading/writing INI style config files.
* It is used by the ConfigManager for storage, but can also
* be used by other code if it needs to read/write custom INI
* files.
*
* Lines starting with a '#' are ignored (i.e. treated as comments).
* Some effort is made to preserve comments, though.
*
* This class makes no attempts to provide fast access to key/value pairs.
* In particular, it stores all sections and k/v pairs in lists, not
* in dictionaries/maps. This makes it very easy to read/write the data
* from/to files, but of course is not appropriate for fast access.
* The main reason is that this class is indeed geared toward doing precisely
* that!
* If you need fast access to the game config, use higher level APIs, like the
* one provided by ConfigManager.
*/
class ConfigFile {
public:
struct KeyValue {
String key;
String value;
String comment;
};
typedef List<KeyValue> SectionKeyList;
/** A section in a config file. I.e. corresponds to something like this:
* [mySection]
* key=value
*
* Comments are also stored, to keep users happy who like editing their
* config files manually.
*/
struct Section {
String name;
List<KeyValue> keys;
String comment;
bool hasKey(const String &key) const;
const KeyValue* getKey(const String &key) const;
void setKey(const String &key, const String &value);
void removeKey(const String &key);
const SectionKeyList getKeys() const { return keys; }
};
typedef List<Section> SectionList;
public:
ConfigFile();
~ConfigFile();
// TODO: Maybe add a copy constructor etc.?
/**
* Check whether the given string is a valid section or key name.
* For that, it must only consist of letters, numbers, dashes and
* underscores. In particular, white space and "#", "=", "[", "]"
* are not valid!
*/
static bool isValidName(const String &name);
/** Reset everything stored in this config file. */
void clear();
bool loadFromFile(const String &filename);
bool loadFromSaveFile(const char *filename);
bool loadFromStream(SeekableReadStream &stream);
bool saveToFile(const String &filename);
bool saveToSaveFile(const char *filename);
bool saveToStream(WriteStream &stream);
bool hasSection(const String §ion) const;
void removeSection(const String §ion);
void renameSection(const String &oldName, const String &newName);
bool hasKey(const String &key, const String §ion) const;
bool getKey(const String &key, const String §ion, String &value) const;
void setKey(const String &key, const String §ion, const String &value);
void removeKey(const String &key, const String §ion);
const SectionList getSections() const { return _sections; }
const SectionKeyList getKeys(const String §ion) const;
void listKeyValues(StringMap &kv);
private:
SectionList _sections;
Section *getSection(const String §ion);
const Section *getSection(const String §ion) const;
};
/*
- ConfigMan owns a config file
- allow direct access to that config file (for the launcher)
- simplify and unify the regular ConfigMan API in exchange
*/
} // End of namespace Common
#endif
| 30.764286 | 81 | 0.738797 |
eff133de069c158005318b88b6f8a1428fc3e296 | 297 | h | C | include/il2cpp/NexPlugin/Detail/SmartDeviceVoiceChat/SmartDeviceVoiceChatLeaveRoomParamInt.h | martmists-gh/BDSP | d6326c5d3ad9697ea65269ed47aa0b63abac2a0a | [
"MIT"
] | 1 | 2022-01-15T20:20:27.000Z | 2022-01-15T20:20:27.000Z | include/il2cpp/NexPlugin/Detail/SmartDeviceVoiceChat/SmartDeviceVoiceChatLeaveRoomParamInt.h | martmists-gh/BDSP | d6326c5d3ad9697ea65269ed47aa0b63abac2a0a | [
"MIT"
] | null | null | null | include/il2cpp/NexPlugin/Detail/SmartDeviceVoiceChat/SmartDeviceVoiceChatLeaveRoomParamInt.h | martmists-gh/BDSP | d6326c5d3ad9697ea65269ed47aa0b63abac2a0a | [
"MIT"
] | null | null | null | #pragma once
#include "il2cpp.h"
void NexPlugin_Detail_SmartDeviceVoiceChat_SmartDeviceVoiceChatLeaveRoomParamInt___ctor (NexPlugin_Detail_SmartDeviceVoiceChat_SmartDeviceVoiceChatLeaveRoomParamInt_o __this, NexPlugin_SmartDeviceVoiceChatLeaveRoomParam_o* param, const MethodInfo* method_info);
| 49.5 | 261 | 0.909091 |
4c685edab8eb94e671b1b5538c8b488f12548d53 | 18,190 | h | C | experimental/include/altruct/structure/math/double_int.h | plamenko/altruct | e16fc162043933fbe282fe01a44e0c908df4f612 | [
"MIT"
] | 66 | 2016-10-18T20:37:09.000Z | 2021-11-28T09:56:41.000Z | experimental/include/altruct/structure/math/double_int.h | plamenko/altruct | e16fc162043933fbe282fe01a44e0c908df4f612 | [
"MIT"
] | null | null | null | experimental/include/altruct/structure/math/double_int.h | plamenko/altruct | e16fc162043933fbe282fe01a44e0c908df4f612 | [
"MIT"
] | 4 | 2018-02-11T17:56:03.000Z | 2019-01-18T15:41:15.000Z | #pragma once
#include "altruct/algorithm/math/base.h"
#include "altruct/algorithm/math/bits.h"
#include <stdint.h>
#include <algorithm>
#include <string>
#include <typeinfo>
#include <type_traits>
namespace altruct {
namespace math {
/** TODO **
mul
mulw; long multiplication by a single machine word
div
half machine-word size step; (O(n) m-w divisions, O(n^2) m-w multiplications)
div_full
to string
add buffer length to be safe
use proper format specifier for printf: <inttypes.h>
use divide-and-conquer to achieve O(n log^2 n) instead O(n^2) time
*/
template<typename T>
class double_int {
public:
typedef T half_type;
static const int type_bits = half_type::type_bits * 2;
static inline int sign(bool is_negative) { return is_negative ? -1 : 0; }
// DATA
T hi, lo;
// CONSTRUCTORS
double_int(int val = 0) : hi(sign(val < 0)), lo(val) {}
double_int(const T& val) : hi(sign(val.is_negative())), lo(val) {}
double_int(const T& rhs_hi, const T& rhs_lo) : hi(rhs_hi), lo(rhs_lo) {}
double_int(const double_int& rhs) : hi(rhs.hi), lo(rhs.lo) {}
//double_int(const char *buff) : double_int(from_string10(buff)) {}
// GETTERS
bool is_negative() const { return hi.is_negative(); }
// EQUALITY COMPARISON
bool operator == (const double_int& rhs) const { return (hi == rhs.hi && lo == rhs.lo); }
bool operator != (const double_int& rhs) const { return (hi != rhs.hi || lo != rhs.lo); }
// SIGNED COMPARISON
bool operator < (const double_int& rhs) const { return hi < rhs.hi || (hi == rhs.hi && lo.unsigned_lt(rhs.lo)); }
bool operator > (const double_int& rhs) const { return hi > rhs.hi || (hi == rhs.hi && lo.unsigned_gt(rhs.lo)); }
bool operator <= (const double_int& rhs) const { return hi < rhs.hi || (hi == rhs.hi && lo.unsigned_lte(rhs.lo)); }
bool operator >= (const double_int& rhs) const { return hi > rhs.hi || (hi == rhs.hi && lo.unsigned_gte(rhs.lo)); }
// UNSIGNED COMPARISON
bool unsigned_lt(const double_int& rhs) const { return hi.unsigned_lt(rhs.hi) || (hi == rhs.hi && lo.unsigned_lt(rhs.lo)); }
bool unsigned_gt(const double_int& rhs) const { return hi.unsigned_gt(rhs.hi) || (hi == rhs.hi && lo.unsigned_gt(rhs.lo)); }
bool unsigned_lte(const double_int& rhs) const { return hi.unsigned_lt(rhs.hi) || (hi == rhs.hi && lo.unsigned_lte(rhs.lo)); }
bool unsigned_gte(const double_int& rhs) const { return hi.unsigned_gt(rhs.hi) || (hi == rhs.hi && lo.unsigned_gte(rhs.lo)); }
// ADDITION / SUBTRACTION WITH CARRY
double_int& assign_adc(const double_int& rhs, int& carry) {
lo.assign_adc(rhs.lo, carry);
hi.assign_adc(rhs.hi, carry);
return *this;
}
double_int& assign_sbb(const double_int& rhs, int& borrow) {
lo.assign_sbb(rhs.lo, borrow);
hi.assign_sbb(rhs.hi, borrow);
return *this;
}
// INCREMENT / DECREMENT
double_int& operator ++ () { int carry = 1; return assign_adc(0, carry); }
double_int& operator -- () { int borrow = 1;return assign_sbb(0, borrow); }
double_int operator ++ (int) { double_int r(*this); return ++r; }
double_int operator -- (int) { double_int r(*this); return --r; }
// ADDITION / SUBTRACTION
double_int& operator += (const double_int& rhs) { int carry = 0; return assign_adc(rhs, carry); }
double_int& operator -= (const double_int& rhs) { int borrow = 0; return assign_sbb(rhs, borrow); }
double_int operator + (const double_int& rhs) const { double_int r(*this); return r += rhs; }
double_int operator - (const double_int& rhs) const { double_int r(*this); return r -= rhs; }
double_int operator + () const { return *this; }
double_int operator - () const { return double_int(0) -= *this; }
double_int& negate() { return *this = -*this; }
// MULTIPLICATION
static double_int<double_int> unsigned_mul_full(const double_int& lhs, const double_int& rhs) {
int lhs_cy = 0; auto lhs_su = lhs.lo; lhs_su.assign_adc(lhs.hi, lhs_cy);
int rhs_cy = 0; auto rhs_su = rhs.lo; rhs_su.assign_adc(rhs.hi, rhs_cy);
auto m0 = T::unsigned_mul_full(lhs.lo, rhs.lo);
auto m2 = T::unsigned_mul_full(lhs.hi, rhs.hi);
auto m1 = T::unsigned_mul_full(lhs_su, rhs_su);
int borrow0 = 0; m1.assign_sbb(m0, borrow0);
int borrow2 = 0; m1.assign_sbb(m2, borrow2);
double_int<double_int> r(m2, m0);
int carry = 0;
r.lo.hi.assign_adc(m1.lo, carry);
r.hi.lo.assign_adc(m1.hi, carry);
int carry1 = 0; if (rhs_cy) r.hi.lo.assign_adc(lhs_su, carry1);
int carry2 = 0; if (lhs_cy) r.hi.lo.assign_adc(rhs_su, carry2);
r.hi.hi += (lhs_cy & rhs_cy) - borrow0 - borrow2 + carry + carry1 + carry2;
return r;
}
static double_int unsigned_mul(const double_int& lhs, const double_int& rhs) {
auto r = T::unsigned_mul_full(lhs.lo, rhs.lo);
r.hi += T::unsigned_mul(lhs.lo, rhs.hi);
r.hi += T::unsigned_mul(lhs.hi, rhs.lo);
return r;
}
double_int operator * (const double_int& rhs) const { return unsigned_mul(*this, rhs); }
double_int& operator *= (const double_int& rhs) { return *this = *this * rhs; }
// DIVISION
static double_int unsigned_div(const double_int& a0, const double_int& b0, double_int *r = 0) {
if (a0.unsigned_lt(b0)) return 0;
double_int q = 0, a = a0, b = b0;
// TODO: do half machine-word divisions, not half double-int divisions !!
//int r_shift = 0;
//while (a.unsigned_gte(b)) {
// // shifting both a and b by the same amount doesn't affect the quotient
// int a_lzc = a.leading_zeros_count(); a <<= a_lzc;
// int b_lzc = b.leading_zeros_count(); b <<= a_lzc;
// r_shift += a_lzc;
// if (b_lzc == a_lzc) { a -= b; q += 1; continue; }
// // shifting b left so that (b << k).hi >= 2^(T::type_bits/2-1)
// int k = max(0, b_lzc - a_lzc - T::type_bits / 2);
// double_int c = b << k;
// double_int t = T::unsigned_div(a.get_hi(), c.get_hi() + 1);
// t <<= k; // correcting the quotient because shifting b left shifted the quotient right
// a -= b * t;
// q += t;
//}
//if (r) *r = a >> r_shift;
return q;
}
static double_int signed_div(const double_int& a0, const double_int& b0, double_int *r = 0) {
double_int a = a0; if (a0.is_negative()) a.negate();
double_int b = b0; if (b0.is_negative()) b.negate();
double_int q = unsigned_div(a, b, r);
if (r && a0.is_negative()) r->negate();
return (a0.is_negative() != b0.is_negative()) ? -q : q;
}
double_int operator / (const double_int& rhs) const { return signed_div(*this, rhs); }
double_int operator % (const double_int& rhs) const { double_int r; signed_div(*this, rhs, &r); return r; }
double_int& operator /= (const double_int& rhs) { return *this = *this / rhs; }
double_int& operator %= (const double_int& rhs) { return *this = *this % rhs; }
// BITWISE
double_int& operator &= (const double_int& rhs) { hi &= rhs.hi; lo &= rhs.lo; return *this; }
double_int& operator |= (const double_int& rhs) { hi |= rhs.hi; lo |= rhs.lo; return *this; }
double_int& operator ^= (const double_int& rhs) { hi ^= rhs.hi; lo ^= rhs.lo; return *this; }
double_int operator & (const double_int& rhs) const { double_int r(*this); return r &= rhs; }
double_int operator | (const double_int& rhs) const { double_int r(*this); return r |= rhs; }
double_int operator ^ (const double_int& rhs) const { double_int r(*this); return r ^= rhs; }
double_int operator ~ () const { return double_int(~hi, ~lo); }
// SHIFTS
double_int& operator <<= (int cnt) {
if (cnt >= 2 * T::type_bits) {
hi = 0;
lo = 0;
} else if (cnt > T::type_bits) {
hi = lo;
hi <<= cnt - T::type_bits;
lo = 0;
} else if (cnt == T::type_bits) {
hi = lo;
lo = 0;
} else if (cnt > 0) {
hi <<= cnt;
hi |= double_int(lo).assign_unsigned_shr(T::type_bits - cnt);
lo <<= cnt;
}
return *this;
}
double_int& operator >>= (int cnt) {
return assign_extended_shr(cnt, sign(is_negative()));
}
double_int& assign_unsigned_shr(int cnt) {
return assign_extended_shr(cnt, 0);
}
double_int& assign_extended_shr(int cnt, int ext) {
if (cnt >= 2 * T::type_bits) {
lo = ext;
hi = ext;
} else if (cnt > T::type_bits) {
lo = hi;
lo.assign_extended_shr(cnt - T::type_bits, ext);
hi = ext;
} else if (cnt == T::type_bits) {
lo = hi;
hi = ext;
} else if (cnt > 0) {
lo.assign_unsigned_shr(cnt);
lo |= hi << (T::type_bits - cnt);
hi.assign_extended_shr(cnt, ext);
}
return *this;
}
double_int operator << (int cnt) const { double_int r(*this); return r <<= cnt; }
double_int operator >> (int cnt) const { double_int r(*this); return r >>= cnt; }
int leading_zeros_count() const {
int hi_lzc = hi.leading_zeros_count();
return (hi_lzc < T::type_bits) ? hi_lzc : T::type_bits + lo.leading_zeros_count();
}
// INPUT / OUTPUT
uint64_t to_uint64() const {
if (T::type_bits >= 64) return lo.to_uint64();
return (hi.to_uint64() << T::type_bits) | lo.to_uint64();
}
//static double_int pow10(int e) {
// double_int r = 1;
// while (e-- > 0) {
// r += r; if (r.is_negative()) return r;
// double_int r2 = r;
// r += r; if (r.is_negative()) return r;
// r += r; if (r.is_negative()) return r;
// r += r2; if (r.is_negative()) return r;
// }
// return r;
//}
//// WARNING: does not check for buffer overflow!
//// LIMITATION: outputs "-OF" for minimum value
//char *to_string10(char *buff) const {
// char *wr = buff;
// double_int t = *this;
// if (t == 0) {
// *(wr++) = '0';
// *(wr++) = 0;
// return buff;
// }
// if (t.is_negative()) {
// *(wr++) = '-';
// t = -t;
// }
// if (t.is_negative()) {
// *(wr++) = 'O';
// *(wr++) = 'F';
// *(wr++) = 0;
// return buff;
// }
// int digits = 0;
// double_int p10;
// do {
// digits++;
// p10 = pow10(digits);
// } while (!p10.is_negative() && p10 <= t);
// while (digits-- > 0) {
// p10 = pow10(digits);
// int d = 0;
// while (t >= p10) {
// t -= p10;
// d++;
// }
// *(wr++) = '0' + d;
// }
// *(wr++) = 0;
// return buff;
//}
//static double_int from_string10(const char *buff) {
// double_int r = 0;
// bool is_neg = false;
// if (*buff == '-') {
// buff++;
// is_neg = true;
// }
// while (*buff) {
// int d = *(buff++) -'0';
// r += r;
// double_int r2 = r;
// r += r;
// r += r;
// r += r2;
// r += d;
// }
// return is_neg ? -r : r;
//}
std::string to_string16() const {
return hi.to_string16() + lo.to_string16();
}
};
/**
* A wrapper around a signed primitive integral type
* that adds some unsigned facilities.
*
* Accepts:
* int8_t, uint8_t, uint16_t
* int16_t, uint16_t, uint32_t
* int32_t, uint32_t, uint64_t
* int64_t, uint64_t, <uint128_t>
*
* @param sT - signed variant of the wrapped type
* @param uT - unsigned variant of the wrapped type
* @param INTR - intrinsics for `adc`, `sbb` and `umul`.
*/
template<typename sT, typename uT, typename INTR>
class prim_int {
public:
static const int type_bits = sizeof(sT) * 8;
// DATA
sT v;
// CONSTRUCTORS
prim_int() : v(0) {}
prim_int(const sT& val) : v(val) {}
prim_int(const uT& val) : v(sT(val)) {}
// construct from int, but only if sT is not int itself to avoid constructor clashing
template <typename sI = sT, typename = std::enable_if_t<!std::is_same<sI, int>::value>>
prim_int(int val) : v(sT(val)) {}
// GETTERS
bool is_negative() const { return v < 0; }
// FORWARDING
bool operator == (const prim_int& rhs) const { return (v == rhs.v); }
bool operator != (const prim_int& rhs) const { return (v != rhs.v); }
bool operator < (const prim_int& rhs) const { return (v < rhs.v); }
bool operator > (const prim_int& rhs) const { return (v > rhs.v); }
bool operator <= (const prim_int& rhs) const { return (v <= rhs.v); }
bool operator >= (const prim_int& rhs) const { return (v >= rhs.v); }
prim_int operator ++ (int) { return prim_int(v++); } // prim_int++
prim_int operator -- (int) { return prim_int(v--); } // prim_int--
prim_int operator - () const { return prim_int(-v); }
prim_int operator + () const { return prim_int(+v); }
prim_int operator + (const prim_int& rhs) const { return prim_int(v + rhs.v); }
prim_int operator - (const prim_int& rhs) const { return prim_int(v - rhs.v); }
prim_int operator * (const prim_int& rhs) const { return prim_int(v * rhs.v); }
prim_int operator / (const prim_int& rhs) const { return prim_int(v / rhs.v); }
prim_int operator % (const prim_int& rhs) const { return prim_int(v % rhs.v); }
prim_int operator ~ () const { return prim_int(~v); }
prim_int operator & (const prim_int& rhs) const { return prim_int(v & rhs.v); }
prim_int operator | (const prim_int& rhs) const { return prim_int(v | rhs.v); }
prim_int operator ^ (const prim_int& rhs) const { return prim_int(v ^ rhs.v); }
prim_int operator << (int cnt) const { return prim_int(v << cnt); }
prim_int operator >> (int cnt) const { return prim_int(v >> cnt); }
prim_int& operator ++ () { ++v; return *this; } // ++prim_int
prim_int& operator -- () { --v; return *this; } // --prim_int
prim_int& operator += (const prim_int& rhs) { v += rhs.v; return *this; }
prim_int& operator -= (const prim_int& rhs) { v -= rhs.v; return *this; }
prim_int& operator *= (const prim_int& rhs) { v *= rhs.v; return *this; }
prim_int& operator /= (const prim_int& rhs) { v /= rhs.v; return *this; }
prim_int& operator %= (const prim_int& rhs) { v %= rhs.v; return *this; }
prim_int& negate() { return prim_int(-v); }
prim_int& operator &= (const prim_int& rhs) { v &= rhs.v; return *this; }
prim_int& operator |= (const prim_int& rhs) { v |= rhs.v; return *this; }
prim_int& operator ^= (const prim_int& rhs) { v ^= rhs.v; return *this; }
prim_int& operator <<= (int cnt) { v <<= cnt; return *this; }
prim_int& operator >>= (int cnt) { v >>= cnt; return *this; }
// UNSIGNED COMPARISON
bool unsigned_lt(const prim_int& rhs) const { return (uT(v) < uT(rhs.v)); }
bool unsigned_gt(const prim_int& rhs) const { return (uT(v) > uT(rhs.v)); }
bool unsigned_lte(const prim_int& rhs) const { return (uT(v) <= uT(rhs.v)); }
bool unsigned_gte(const prim_int& rhs) const { return (uT(v) >= uT(rhs.v)); }
// UNSIGNED SHIFT RIGHT
prim_int& assign_unsigned_shr(int cnt) { v = uT(v) >> cnt; return *this; }
prim_int& assign_extended_shr(int cnt, int ext) { v = (uT(v) >> cnt) | (uT(ext) << (type_bits - cnt)); return *this; } // undefined for cnt = 0
int leading_zeros_count() const { return lzc(uT(v)); }
// ADDITION / SUBTRACTION WITH CARRY
prim_int& assign_adc(const prim_int& rhs, int& carry) {
v = INTR().adc(uT(v), uT(rhs.v), carry);
return *this;
}
prim_int& assign_sbb(const prim_int& rhs, int& borrow) {
v = INTR().sbb(uT(v), uT(rhs.v), borrow);
return *this;
}
// UNSIGNED MULTIPLICATION
static double_int<prim_int> unsigned_mul_full(const prim_int& lhs, const prim_int& rhs) {
double_int<prim_int> r;
r.lo = INTR().umul(uT(lhs.v), uT(rhs.v), (uT*)&(r.hi.v));
return r;
}
static prim_int unsigned_mul(const prim_int& lhs, const prim_int& rhs) {
return uT(lhs.v) * uT(rhs.v);
}
// UNSIGNED DIVISION
static prim_int unsigned_div_full(const prim_int& lhs_hi, const prim_int& lhs_lo, const prim_int& rhs, prim_int *r = 0) {
// TODO
}
static prim_int unsigned_div(const prim_int& lhs, const prim_int& rhs, prim_int *r = 0) {
if (r) *r = uT(lhs.v) % uT(rhs.v);
return uT(lhs.v) / uT(rhs.v);
}
// OUTPUT
uint64_t to_uint64() const { return uT(v); }
std::string to_string16() const {
static const char hex_digits[16] = {
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', 'a', 'b', 'c', 'd', 'e', 'f' };
int num_digits = type_bits / 4;
std::string s(num_digits, '0');
auto u = to_uint64();
for (int i = num_digits - 1; i >= 0; i--) {
s[i] = hex_digits[u & 0xF];
u >>= 4;
}
return s;
}
};
template<typename T>
struct identityT<double_int<T>> {
static double_int<T> of(const double_int<T>& x) {
return double_int<T>(1);
}
};
template<typename T>
struct zeroT<double_int<T>> {
static double_int<T> of(const double_int<T>& x) {
return double_int<T>(0);
}
};
} // math
} // altruct
| 39.287257 | 148 | 0.552446 |
bc2a9035bba7c184e0575eb3fa0604098d687728 | 791 | h | C | AdNetworkSupport/FlurryAdapterForMoPubiOS-master 6/FlurryAdsCustomRouter.h | gje4/ads | 762d8d27a9b1d0b5dcad8416e2cfe357578680d5 | [
"MIT"
] | 1 | 2018-07-27T21:46:03.000Z | 2018-07-27T21:46:03.000Z | FlurryAdapterForMoPubiOS-master 3/FlurryAdsCustomRouter.h | gje4/ads | 762d8d27a9b1d0b5dcad8416e2cfe357578680d5 | [
"MIT"
] | null | null | null | FlurryAdapterForMoPubiOS-master 3/FlurryAdsCustomRouter.h | gje4/ads | 762d8d27a9b1d0b5dcad8416e2cfe357578680d5 | [
"MIT"
] | null | null | null | //
// FlurryAdsCustomRouter.h
// MoPub Mediates Flurry
//
// Copyright (c) 2013 MoPub. All rights reserved.
//
#import "FlurryAdDelegate.h"
#import "MPInstanceProvider.h"
@interface FlurryAdsCustomRouter : NSObject <FlurryAdDelegate>
// Map of the ad spaces that holds click status
@property (nonatomic,strong) NSMutableDictionary *adSpaceClickMap;
+ (FlurryAdsCustomRouter *)sharedRouter;
- (void)setRouter:(id<FlurryAdDelegate>)router forSpace:(NSString *)space;
- (void)setClickStatus:(BOOL)status forSpace:(NSString*)space;
@end
////////////////////////////////////////////////////////////////////////////////////////////////////
@interface MPInstanceProvider (FlurryAdsRouterBridge)
- (FlurryAdsCustomRouter *)sharedFlurryAdsCustomRouter;
- (void) delegateFlurry: id;
@end | 25.516129 | 100 | 0.675095 |
294ff95c8db2ec299cc73a0b0e332934df888d47 | 680 | h | C | StRoot/Sti/Base/Named.h | xiaohaijin/RHIC-STAR | a305cb0a6ac15c8165bd8f0d074d7075d5e58752 | [
"MIT"
] | 2 | 2018-12-24T19:37:00.000Z | 2022-02-28T06:57:20.000Z | StRoot/Sti/Base/Named.h | xiaohaijin/RHIC-STAR | a305cb0a6ac15c8165bd8f0d074d7075d5e58752 | [
"MIT"
] | null | null | null | StRoot/Sti/Base/Named.h | xiaohaijin/RHIC-STAR | a305cb0a6ac15c8165bd8f0d074d7075d5e58752 | [
"MIT"
] | null | null | null | #ifndef NAMED_H
#define NAMED_H
#include <string>
using std::string;
/*!
\class Named
This class encapsulates the notion of "name". It should be used as
base class to provide a "named" property to objects.#include <string>
use STD;
\author Claude A Pruneau
*/
class Named
{
public:
virtual ~Named();
/// Set the name of the object
void setName(const string & newName);
/// Get the name of the object
const string &getName() const;
/// Determine whether name equals given name
bool isName(const string & aName) const;
protected:
/// Only derived class are Named
Named(const string & aName=" ");
protected:
string _name;
};
#endif //
| 15.813953 | 69 | 0.679412 |
ad7bf4ade81addbf6b26b293b6e1ed79ccda1b22 | 947 | c | C | homework_2/hw2.4/main.c | Degiv/spbu_2020_c_homeworks | 05f22059fff76f344cd805ab7a8b690888ec9127 | [
"Apache-2.0"
] | null | null | null | homework_2/hw2.4/main.c | Degiv/spbu_2020_c_homeworks | 05f22059fff76f344cd805ab7a8b690888ec9127 | [
"Apache-2.0"
] | 7 | 2020-09-29T07:49:03.000Z | 2020-11-26T17:06:38.000Z | homework_2/hw2.4/main.c | Degiv/spbu_2020_c_homeworks | 05f22059fff76f344cd805ab7a8b690888ec9127 | [
"Apache-2.0"
] | null | null | null | #include "../../library/commonUtils/mysorts.h"
#include "../../library/commonUtils/numericOperations.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
void showNumerals(int* numerals, int n)
{
int i = 0;
while (numerals[i] == 0) {
++i;
}
swap(&numerals[i], &numerals[0]);
i = 0;
while (i < n) {
printf("%d", numerals[i]);
++i;
}
}
void inputNumerals(int* numerals, int n)
{
char* number = (char*)calloc(n + 1, sizeof(char));
scanf("%s", number);
for (int i = n - 1; i >= 0; --i) {
numerals[i] = (int)(number[i] - '0');
}
free(number);
}
int main()
{
int n = 0;
printf("Enter the length of number :\n");
scanf("%d", &n);
printf("Enter the number :\n");
int* numerals = calloc(n, sizeof(int));
inputNumerals(numerals, n);
countingSort(numerals, n, 0, 9);
showNumerals(numerals, n);
free(numerals);
return 0;
}
| 19.729167 | 56 | 0.544879 |
addc18de629d2b41702be92fccb901810f05f198 | 1,061 | c | C | CPE_n4s_2017/tests/unit_test_get_nbr_value.c | ltabis/epitech-projects | e38b3f00a4ac44c969d5e4880cd65084dc2c870a | [
"MIT"
] | null | null | null | CPE_n4s_2017/tests/unit_test_get_nbr_value.c | ltabis/epitech-projects | e38b3f00a4ac44c969d5e4880cd65084dc2c870a | [
"MIT"
] | null | null | null | CPE_n4s_2017/tests/unit_test_get_nbr_value.c | ltabis/epitech-projects | e38b3f00a4ac44c969d5e4880cd65084dc2c870a | [
"MIT"
] | 1 | 2021-01-07T17:41:14.000Z | 2021-01-07T17:41:14.000Z | /*
** EPITECH PROJECT, 2018
** unit_test_get_nbr_value.c
** File description:
** unti test for function get_nbr_value in parser.c
*/
#include "test.h"
#include "proto.h"
Test(parser, check_get_nbr_value)
{
char *command = "1:OK:No errors so far:600.0:625.0:675.0:700.0:750.0:8"\
"00.0:850.0:900.0:975.0:1050.0:1125.0:1375.0:1500.0:2500.0:275"\
"0.0:2750.0:2750.0:2750.0:2750.0:2500.0:1500.0:1375.0:1225.0:1"\
"125.0:1050.0:975.0:900.0:850.0:800.0:750.0:700.0:675.0:No fur"\
"ther info";
int value = set_point(command);
cr_assert_eq(value, 22);
}
Test(parser, check_line_parsing)
{
value_t values = {0.0, 0.0, 0.0, 0.0, 0.0};
char *command = "1:OK:No errors so far:100.0:105.0:675.0:700.0:750.0:8"\
"00.0:850.0:900.0:975.0:1050.0:1125.0:1375.0:1500.0:2500.0:275"\
"0.0:200.0:200.0:200.0:200.0:2500.0:1500.0:1375.0:1225.0:1"\
"125.0:1050.0:975.0:900.0:850.0:700.0:750.0:700.0:600.0:No fur"\
"ther info";
line_parser(command, &values);
cr_assert_neq(values.middle, 0);
cr_assert_neq(values.left, 0);
cr_assert_neq(values.right, 0);
}
| 28.675676 | 73 | 0.668238 |
21544a31bff8f8e37586fbfc4e8bc8c28680b328 | 18,299 | h | C | Moco/Moco/MocoProblemRep.h | zhengsizehrb/opensim-moco | 9844abc640a34d818a4bb21ef4fea3c3cb0f34ed | [
"Apache-2.0"
] | 41 | 2019-11-13T10:29:20.000Z | 2022-03-10T17:42:30.000Z | Moco/Moco/MocoProblemRep.h | zhengsizehrb/opensim-moco | 9844abc640a34d818a4bb21ef4fea3c3cb0f34ed | [
"Apache-2.0"
] | 165 | 2019-11-13T00:55:57.000Z | 2022-03-04T19:02:26.000Z | Moco/Moco/MocoProblemRep.h | zhengsizehrb/opensim-moco | 9844abc640a34d818a4bb21ef4fea3c3cb0f34ed | [
"Apache-2.0"
] | 15 | 2020-01-24T23:57:57.000Z | 2021-12-10T21:59:46.000Z | #ifndef MOCO_MOCOPROBLEMREP_H
#define MOCO_MOCOPROBLEMREP_H
/* -------------------------------------------------------------------------- *
* OpenSim Moco: MocoProblemRep.h *
* -------------------------------------------------------------------------- *
* Copyright (c) 2017 Stanford University and the Authors *
* *
* Author(s): Christopher Dembia, Nicholas Bianco *
* *
* Licensed under the Apache License, Version 2.0 (the "License"); you may *
* not use this file except in compliance with the License. You may obtain a *
* copy of the License at http://www.apache.org/licenses/LICENSE-2.0 *
* *
* Unless required by applicable law or agreed to in writing, software *
* distributed under the License is distributed on an "AS IS" BASIS, *
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
* See the License for the specific language governing permissions and *
* limitations under the License. *
* -------------------------------------------------------------------------- */
#include "MocoConstraint.h"
#include "MocoGoal/MocoGoal.h"
#include "MocoParameter.h"
#include "MocoVariableInfo.h"
#include "osimMocoDLL.h"
#include <OpenSim/Simulation/Model/Model.h>
#include "Components/DeGrooteFregly2016Muscle.h"
namespace OpenSim {
class MocoProblem;
class DiscreteController;
class DiscreteForces;
class PositionMotion;
class AccelerationMotion;
/// The primary intent of this class is for use by MocoSolver%s, but users
/// can also use this class to apply parameter values to the model
/// and evaluate cost terms.
/// This class also checks the MocoProblem for various errors.
/// To get an instance of this class, use MocoProblem::createRep().
/// This interface currently supports only single-phase problems.
/// This class stores a reference (not a copy) to the original MocoProblem
/// from which it was created.
class OSIMMOCO_API MocoProblemRep {
public:
MocoProblemRep() = default;
MocoProblemRep(const MocoProblemRep&) = delete;
MocoProblemRep& operator=(const MocoProblemRep&) = delete;
MocoProblemRep(MocoProblemRep&& source)
: m_problem(std::move(source.m_problem)) {
if (m_problem) initialize();
}
MocoProblemRep& operator=(MocoProblemRep&& source) {
m_problem = std::move(source.m_problem);
if (m_problem) initialize();
return *this;
}
const std::string& getName() const;
/// Get a reference to the copy of the model being used by this
/// MocoProblemRep. This model is *not* the model given to MocoGoal or
/// MocoPathConstraint, but can be used within solvers to compute constraint
/// forces and constraint errors (see getModelDisabledConstraints() for more
/// details). Any parameter updates via a MocoParameter added to the problem
/// will be applied to this model.
const Model& getModelBase() const { return m_model_base; }
/// This is a state object that solvers can use along with ModelBase.
SimTK::State& updStateBase() const { return m_state_base; }
/// This is a component inside ModelBase that you can use to
/// set the value of control signals.
const DiscreteController& getDiscreteControllerBase() const {
return m_discrete_controller_base.getRef();
}
/// Get a reference to a copy of the model being used by this
/// MocoProblemRep, but with all constraints disabled and an additional
/// DiscreteForces component. This new component can be used to apply
/// constraint forces computed from the base model to this model, which
/// updates the discrete variables in the state associated with these
/// forces. You should use this model to compute accelerations via
/// getModelDisabledConstraints().realizeAccleration(state), making sure to
/// add any constraint forces to the model preceeding the realization. This
/// model is the same instance as that given to MocoGoal and
/// MocoPathConstraint, ensuring that realizing to Stage::Acceleration
/// in these classes produces the same accelerations computed by the solver.
/// Any parameter updates via a MocoParameter added to the problem
/// will be applied to this model.
const Model& getModelDisabledConstraints() const {
return m_model_disabled_constraints;
}
/// This is a state object that solvers can use with
/// ModelDisabledConstraints. Some solvers may need to use 2 state objects
/// at once; you can supply an index of 1 to get a second state object.
SimTK::State& updStateDisabledConstraints(int index = 0) const {
assert(index <= 1);
return m_state_disabled_constraints[index];
}
/// This is a component inside ModelDisabledConstraints that you can use to
/// set the value of control signals.
const DiscreteController& getDiscreteControllerDisabledConstraints() const {
return m_discrete_controller_disabled_constraints.getRef();
}
/// This is a component inside ModelDisabledConstraints that you can use
/// to set the value of discrete forces, intended to hold the constraint
/// forces obtained from ModelBase.
const DiscreteForces& getConstraintForces() const {
return m_constraint_forces.getRef();
}
/// This is a component inside ModelDisabledConstraints that you can use
/// to set the value of generalized accelerations UDot, for use in
/// implicit dynamics formulations. The motion is not necessarily enabled.
const AccelerationMotion& getAccelerationMotion() const {
return m_acceleration_motion.getRef();
}
int getNumStates() const { return (int)m_state_infos.size(); }
int getNumControls() const { return (int)m_control_infos.size(); }
int getNumParameters() const { return (int)m_parameters.size(); }
/// Get the number of goals in cost mode.
int getNumCosts() const { return (int)m_costs.size(); }
/// Get the number of goals in endpoint constraint mode.
int getNumEndpointConstraints() const {
return (int)m_endpoint_constraints.size();
}
int getNumKinematicConstraints() const {
return (int)m_kinematic_constraints.size();
}
/// Does the model contain a PositionMotion to prescribe all generalized
/// coordinates, speeds, and accelerations?
bool isPrescribedKinematics() const { return m_prescribedKinematics; }
int getNumImplicitAuxiliaryResiduals() const {
return (int)m_implicit_residual_refs.size();
}
/// This excludes generalized coordinate and speed states if
/// isPrescribedKinematics() is true.
std::vector<std::string> createStateVariableNamesInSystemOrder(
std::unordered_map<int, int>& yIndexMap) const;
/// Get the state names of all the state infos.
std::vector<std::string> createStateInfoNames() const;
/// Get the control names of all the control infos.
std::vector<std::string> createControlInfoNames() const;
/// Get the names of all the parameters.
std::vector<std::string> createParameterNames() const;
/// Get the names of all the goals in cost mode.
std::vector<std::string> createCostNames() const;
/// Get the names of all the goals in endpoint constraint mode.
std::vector<std::string> createEndpointConstraintNames() const;
/// Get the names of all the MocoPathConstraint%s.
std::vector<std::string> createPathConstraintNames() const;
/// Get the names of all the Lagrange multiplier infos.
std::vector<std::string> createMultiplierInfoNames() const;
/// Get the constraint names of all the kinematic constraints. Note: this
/// should only be called after initialize().
std::vector<std::string> createKinematicConstraintNames() const;
/// Get a vector of names for all kinematic constraint equations.
/// Kinematic constraint equations are ordered as so:
/// - position-level constraints
/// - velocity-level constraints
/// - acceleration-level constraints
/// If includeDerivatives is true, the ordering is:
/// - position-level constraints
/// - first derivative of position-level constraints (denoted by suffix "d")
/// - velocity-level constraints
/// - second derivative of position-level constraints (suffix "dd")
/// - first derivative of velocity-level constraints (suffix "d")
/// - acceleration-level constraints
std::vector<std::string> getKinematicConstraintEquationNames(
bool includeDerivatives) const;
/// @details Note: the return value is constructed fresh on every call from
/// the internal property. Avoid repeated calls to this function.
MocoInitialBounds getTimeInitialBounds() const;
/// @copydoc getTimeInitialBounds()
MocoFinalBounds getTimeFinalBounds() const;
/// Get information for state variables. See MocoPhase::setStateInfo().
const MocoVariableInfo& getStateInfo(const std::string& name) const;
/// Get information for actuator controls.
/// If the control is associated with a non-scalar actuator (i.e. uses
/// multiple control variables), then the control name will be the actuator
/// path appended by the control index (e.g. "/actuator_0");
/// See MocoPhase::setControlInfo().
const MocoVariableInfo& getControlInfo(const std::string& name) const;
const MocoParameter& getParameter(const std::string& name) const;
/// Get a cost by name. This returns a MocoGoal in cost mode.
const MocoGoal& getCost(const std::string& name) const;
/// Get a cost by index. The order is the same as in getCostNames().
/// Note: this does not perform a bounds check.
const MocoGoal& getCostByIndex(int index) const;
/// Get an endpoint constraint by name. This returns a MocoGoal in endpoint
/// constraint mode.
const MocoGoal& getEndpointConstraint(const std::string& name) const;
/// Get an endpoint constraint by index.
/// The order is the same as in getEndpointConstraintNames().
/// Note: this does not perform a bounds check.
const MocoGoal& getEndpointConstraintByIndex(int index) const;
/// Get a MocoPathConstraint. Note: this does not
/// include MocoKinematicConstraints, use getKinematicConstraint() instead.
const MocoPathConstraint& getPathConstraint(const std::string& name) const;
/// Get a path constraint by index. The order is the same as
/// in getPathConstraintNames(). Note: this does not perform a bounds check.
const MocoPathConstraint& getPathConstraintByIndex(int index) const;
/// Get the number of scalar path constraints in the MocoProblem. This does
/// not include kinematic constraints equations.
int getNumPathConstraintEquations() const {
OPENSIM_THROW_IF(m_num_path_constraint_equations == -1, Exception,
"The number of scalar path constraint equations is not "
"available until after initialization.");
return m_num_path_constraint_equations;
}
/// Given a kinematic constraint name, get a vector of MocoVariableInfos
/// corresponding to the Lagrange multipliers for that kinematic constraint.
/// Note: Since these are created directly from model constraint
/// information, this should only be called after initialization. TODO
const std::vector<MocoVariableInfo>& getMultiplierInfos(
const std::string& kinematicConstraintInfoName) const;
/// Get a MocoKinematicConstraint from this MocoPhase. Note: this does not
/// include MocoPathConstraints, use getPathConstraint() instead. Since
/// these are created directly from model information, this should only be
/// called after initialization. TODO
const MocoKinematicConstraint& getKinematicConstraint(
const std::string& name) const;
/// Get the number of scalar kinematic constraints in the MocoProblem. This
/// does not include path constraints equations.
int getNumKinematicConstraintEquations() const {
OPENSIM_THROW_IF(m_num_kinematic_constraint_equations == -1, Exception,
"The number of scalar kinematic constraint equations is not "
"available until after initialization.");
return m_num_kinematic_constraint_equations;
}
/// Print a description of this problem, including costs and variable
/// bounds. Printing is done using OpenSim::log_cout().
void printDescription() const;
/// @name Interface for solvers
/// These functions are for use by MocoSolver%s, but can also be called
/// by users for debugging.
/// @{
/// Calculate the errors in all the scalar path constraint equations in this
/// phase.
void calcPathConstraintErrors(
const SimTK::State& state, SimTK::Vector& errors) const {
OPENSIM_THROW_IF(errors.size() != getNumPathConstraintEquations(),
Exception,
"The size of the errors vector passed is not consistent with "
"the "
"number of scalar path constraint equations in this "
"MocoProblem.");
for (const auto& pc : m_path_constraints) {
pc->calcPathConstraintErrors(state, errors);
}
}
/// Calculate the errors in all the scalar kinematic constraint equations in
/// this phase. This may not be the most efficient solution for solvers, but
/// is rather intended as a convenience method for a quick implementation or
/// for debugging model constraints causing issues in an optimal control
/// problem.
SimTK::Vector calcKinematicConstraintErrors(
const SimTK::State& state) const {
SimTK::Vector errors(getNumKinematicConstraintEquations(), 0.0);
int index = 0;
int thisConstraintNumEquations;
for (int i = 0; i < (int)m_kinematic_constraints.size(); ++i) {
thisConstraintNumEquations = m_kinematic_constraints[i]
.getConstraintInfo()
.getNumEquations();
SimTK::Vector theseErrors(thisConstraintNumEquations,
errors.getContiguousScalarData() + index, true);
m_kinematic_constraints[i].calcKinematicConstraintErrors(
getModelBase(), state, theseErrors);
index += thisConstraintNumEquations;
}
return errors;
}
/// Apply paramater values to the models created from the model passed to
/// initialize() within the current MocoProblem. Values must be consistent
/// with the order of parameters returned from createParameterNames().
///
/// Note: initSystem() must be called on each model after calls to this
/// method in order for provided parameter values to be applied to the
/// model. You can pass `true` to have initSystem() called for you, and to
/// also re-disable any constraints re-enabled by the initSystem() call
/// (see getModelDisabledConstraints()).
void applyParametersToModelProperties(const SimTK::Vector& parameterValues,
bool initSystemAndDisableConstraints = false) const;
/// Get a vector of reference pointers to model outputs that return residual
/// values for any components with dynamics in implicit forms. The
/// references returned are from the model returned by
/// getModelDisabledConstraints().
const std::vector<SimTK::ReferencePtr<const Output<double>>>&
getImplicitResidualReferencePtrs() const {
return m_implicit_residual_refs;
}
/// Get reference pointers to components that enforce dynamics in implicit
/// form. This returns a vector of pairs including the name of the discrete
/// derivative variable and the component reference pointer.
const
std::vector<std::pair<std::string, SimTK::ReferencePtr<const Component>>>&
getImplicitComponentReferencePtrs() const {
return m_implicit_component_refs;
}
/// @}
private:
explicit MocoProblemRep(const MocoProblem& problem);
friend MocoProblem;
void initialize();
const MocoProblem* m_problem;
Model m_model_base;
mutable SimTK::State m_state_base;
SimTK::ReferencePtr<const DiscreteController> m_discrete_controller_base;
SimTK::ReferencePtr<const PositionMotion> m_position_motion_base;
Model m_model_disabled_constraints;
mutable std::array<SimTK::State, 2> m_state_disabled_constraints;
SimTK::ReferencePtr<const DiscreteController>
m_discrete_controller_disabled_constraints;
SimTK::ReferencePtr<const PositionMotion>
m_position_motion_disabled_constraints;
SimTK::ReferencePtr<DiscreteForces> m_constraint_forces;
SimTK::ReferencePtr<AccelerationMotion> m_acceleration_motion;
bool m_prescribedKinematics = false;
std::unordered_map<std::string, MocoVariableInfo> m_state_infos;
std::unordered_map<std::string, MocoVariableInfo> m_control_infos;
std::vector<std::unique_ptr<MocoParameter>> m_parameters;
std::vector<std::unique_ptr<MocoGoal>> m_costs;
std::vector<std::unique_ptr<MocoGoal>> m_endpoint_constraints;
std::vector<std::unique_ptr<MocoPathConstraint>> m_path_constraints;
int m_num_path_constraint_equations = -1;
int m_num_kinematic_constraint_equations = -1;
std::vector<MocoKinematicConstraint> m_kinematic_constraints;
std::map<std::string, std::vector<MocoVariableInfo>> m_multiplier_infos_map;
std::vector<std::string> m_kinematic_constraint_eq_names_with_derivatives;
std::vector<std::string>
m_kinematic_constraint_eq_names_without_derivatives;
std::vector<SimTK::ReferencePtr<const Output<double>>>
m_implicit_residual_refs;
std::vector<std::pair<std::string, SimTK::ReferencePtr<const Component>>>
m_implicit_component_refs;
};
} // namespace OpenSim
#endif // MOCO_MOCOPROBLEMREP_H
| 50.830556 | 80 | 0.687469 |
09a4d9e05f8d0eef6e95d5f4bb1bef891855c23e | 573 | h | C | instagram-mock/Views/PostCell.h | melo2902/instagram-mock | 31804f3c0e76d599d9390e05a1cd8b638f933749 | [
"Apache-2.0"
] | null | null | null | instagram-mock/Views/PostCell.h | melo2902/instagram-mock | 31804f3c0e76d599d9390e05a1cd8b638f933749 | [
"Apache-2.0"
] | 1 | 2021-07-10T09:46:32.000Z | 2021-07-10T09:46:32.000Z | instagram-mock/Views/PostCell.h | melo2902/instagram-mock | 31804f3c0e76d599d9390e05a1cd8b638f933749 | [
"Apache-2.0"
] | null | null | null | //
// PostCell.h
// instagram-mock
//
// Created by mwen on 7/6/21.
//
#import <UIKit/UIKit.h>
#import "Parse/Parse.h"
#import "Post.h"
NS_ASSUME_NONNULL_BEGIN
@interface PostCell : UITableViewCell
@property (weak, nonatomic) IBOutlet UILabel *username;
@property (weak, nonatomic) IBOutlet UILabel *captionField;
@property (weak, nonatomic) IBOutlet UILabel *creationField;
@property (weak, nonatomic) IBOutlet UIImageView *postPicture;
@property (weak, nonatomic) IBOutlet UIImageView *pfpView;
@property (strong, nonatomic) Post *post;
@end
NS_ASSUME_NONNULL_END
| 23.875 | 62 | 0.759162 |
b6f21fc8775ff45d9d1a6ca5700ea8d5a11119d8 | 2,717 | h | C | tensorflow/compiler/jit/xla_compile_on_demand_op.h | uve/tensorflow | e08079463bf43e5963acc41da1f57e95603f8080 | [
"Apache-2.0"
] | null | null | null | tensorflow/compiler/jit/xla_compile_on_demand_op.h | uve/tensorflow | e08079463bf43e5963acc41da1f57e95603f8080 | [
"Apache-2.0"
] | null | null | null | tensorflow/compiler/jit/xla_compile_on_demand_op.h | uve/tensorflow | e08079463bf43e5963acc41da1f57e95603f8080 | [
"Apache-2.0"
] | null | null | null | /* Copyright 2018 The TensorFlow Authors. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
==============================================================================*/
// The XlaCompileOnDemandOp is an OpKernel that, when its Compute method is
// called, will generate an xla::Computation and run it asynchronously.
#ifndef TENSORFLOW_COMPILER_JIT_XLA_COMPILE_ON_DEMAND_OP_H_
#define TENSORFLOW_COMPILER_JIT_XLA_COMPILE_ON_DEMAND_OP_H_
#include "tensorflow/compiler/jit/xla_device.h"
#include "tensorflow/compiler/tf2xla/xla_compiler.h"
#include "tensorflow/compiler/xla/client/local_client.h"
#include "tensorflow/core/framework/function.h"
#include "tensorflow/core/framework/tensor.h"
#include "tensorflow/core/framework/types.h"
#include "tensorflow/core/lib/core/status.h"
namespace tensorflow {
// An OpKernel that compiles an op to an XLA computation and runs it. Unlike
// XlaLaunch this doesn't rely on any rewrites of the graphdef - it will run a
// vanilla TensorFlow op as long as the bridge supports it.
class XlaCompileOnDemandOp : public OpKernel {
public:
explicit XlaCompileOnDemandOp(OpKernelConstruction* ctx) : OpKernel(ctx) {}
void Compute(OpKernelContext* ctx) override;
private:
XlaCompiler::Argument CreateCompilerArgument(OpKernelContext* ctx, int64 i);
Status ShouldArgumentBeConstant(const OpKernel* op_kernel, int64 argument_idx,
FunctionLibraryRuntime* flib_runtime,
bool* result);
Status MustArgumentBeConstant(const OpKernel* op_kernel, int64 argument_idx,
FunctionLibraryRuntime* flib_runtime,
bool* result);
Status Compile(OpKernelContext* ctx, const XlaDevice::Metadata& metadata,
const XlaCompiler::CompilationResult** result,
xla::LocalExecutable** executable);
Status Run(OpKernelContext* ctx, const XlaDevice::Metadata& metadata,
const XlaCompiler::CompilationResult* result,
xla::LocalExecutable* executable);
};
} // namespace tensorflow
#endif // TENSORFLOW_COMPILER_JIT_XLA_COMPILE_ON_DEMAND_OP_H_
| 46.050847 | 81 | 0.708134 |
e51681bbdc4f1b0607bb186ebc40771020219d2e | 4,403 | c | C | Library/src/HTMuxTx.c | bldcm/Libwww | ba230049bbf6246f9c055ddf9c1526fe98ae9a4f | [
"W3C-19980720"
] | null | null | null | Library/src/HTMuxTx.c | bldcm/Libwww | ba230049bbf6246f9c055ddf9c1526fe98ae9a4f | [
"W3C-19980720"
] | null | null | null | Library/src/HTMuxTx.c | bldcm/Libwww | ba230049bbf6246f9c055ddf9c1526fe98ae9a4f | [
"W3C-19980720"
] | null | null | null | /*
** BUFFERED MUX OUTPUT STREAM
**
** (c) COPYRIGHT MIT 1995.
** Please first read the full copyright statement in the file COPYRIGH.
** @(#) $Id: HTMuxTx.c,v 2.3 1999/02/22 22:10:11 frystyk Exp $
**
** A buffered output MUX stream.
**
** Authors
** HFN Henrik Frystyk Nielsen <frystyk@w3.org>
**
** History:
** Oct 96 Written
*/
/* Library include files */
#include "wwwsys.h"
#include "WWWUtil.h"
#include "WWWCore.h"
#include "WWWTrans.h"
#include "HTMuxHeader.h"
#include "HTMuxCh.h"
#include "HTMuxTx.h" /* Implemented here */
struct _HTOutputStream {
const HTOutputStreamClass * isa;
HTOutputStream * target; /* Target for outgoing data */
HTChannel * ch;
int size; /* Buffer size */
int bb;
char * block;
char * read; /* Position in 'data' */
char * data; /* buffer */
};
#define PUTBLOCK(b,l) (*me->target->isa->put_block)(me->target,(b),(l))
/* ------------------------------------------------------------------------- */
PRIVATE int HTMuxBuffer_write (HTOutputStream *me, const char *buf, int len)
{
int status;
if (me->bb > 0) {
len -= (me->block - buf);
if ((status = PUTBLOCK(me->block, me->bb)) != HT_OK) return status;
me->block += me->bb;
len -= me->bb;
me->bb = 0;
} else {
int available = me->data + me->size - me->read;
/* Still room in buffer */
if (len <= available) {
memcpy(me->read, buf, len);
me->read += len;
return HT_OK;
}
/* If already data in buffer then fill it and flush */
if (me->read > me->data) {
memcpy(me->read, buf, available);
me->block = (char *) buf+available;
if ((status = PUTBLOCK(me->data, me->size))!=HT_OK) return status;
}
/* If more data then write n times buffer size */
if (!me->block)
me->block = (char *) buf;
else {
len -= (me->block - buf);
}
me->bb = len - len%me->size;
if ((status = PUTBLOCK(me->block, me->bb)) != HT_OK) return status;
me->block += me->bb;
len -= me->bb;
me->bb = 0;
}
/* If data is not aligned then save the rest in our buffer */
if (len > 0) {
memcpy(me->data, me->block, len);
me->read = me->data + len;
} else
me->read = me->data;
me->block = NULL;
return HT_OK;
}
PRIVATE int HTMuxBuffer_put_character (HTOutputStream * me, char c)
{
return HTMuxBuffer_write(me, &c, 1);
}
PRIVATE int HTMuxBuffer_put_string (HTOutputStream * me, const char * s)
{
return HTMuxBuffer_write(me, s, (int) strlen(s));
}
PRIVATE int HTMuxBuffer_flush (HTOutputStream * me)
{
int status = HT_OK;
if (me->read > me->data) {
if ((status = PUTBLOCK(me->data, me->read - me->data))==HT_WOULD_BLOCK)
return HT_WOULD_BLOCK;
me->read = me->data;
me->block = NULL;
}
return status;
}
PRIVATE int HTMuxBuffer_free (HTOutputStream * me)
{
#if 0
return HTMuxBuffer_flush(me);
#else
return HT_OK;
#endif
}
PRIVATE int HTMuxBuffer_abort (HTOutputStream * me, HTList * e)
{
if (me->target) (*me->target->isa->abort)(me->target, e);
HTTRACE(PROT_TRACE, "MUX Tx...... ABORTING...\n");
return HT_ERROR;
}
/*
** The difference between the close and the free method is that we don't
** close the connection in the free method - we only call the free method
** of the target stream. That way, we can keep the output stream as long
** as the channel itself.
*/
PRIVATE int HTMuxBuffer_close (HTOutputStream * me)
{
if (me) {
HTMuxBuffer_flush(me);
if (me->target) (*me->target->isa->close)(me->target);
HT_FREE(me->data);
HT_FREE(me);
}
return HT_OK;
}
PRIVATE const HTOutputStreamClass HTMuxBuffer =
{
"MuxBuffer",
HTMuxBuffer_flush,
HTMuxBuffer_free,
HTMuxBuffer_abort,
HTMuxBuffer_put_character,
HTMuxBuffer_put_string,
HTMuxBuffer_write,
HTMuxBuffer_close
};
PUBLIC HTOutputStream * HTMuxBuffer_new (HTHost * host, HTChannel * ch,
void * param, int bufsize)
{
if (host && ch) {
HTOutputStream * me = HTChannel_output(ch);
if (me == NULL) {
if (bufsize <= 0) bufsize = MUX_BUFFER_SIZE;
if ((me = (HTOutputStream *) HT_CALLOC(1, sizeof(HTOutputStream))) == NULL ||
(me->data = (char *) HT_MALLOC(bufsize)) == NULL)
HT_OUTOFMEM("HTMuxBuffer_new");
me->isa = &HTMuxBuffer;
me->target = HTWriter_new(host, ch, param, 0);
me->ch = ch;
me->size = bufsize;
me->read = me->data;
}
return me;
}
return NULL;
}
| 24.735955 | 82 | 0.612083 |
9f973726c52bf990e3224e75a12743a5bf0253b4 | 978 | h | C | System/Library/PrivateFrameworks/PhotosUICore.framework/PXNavigationListGroupItem.h | zhangkn/iOS14Header | 4323e9459ed6f6f5504ecbea2710bfd6c3d7c946 | [
"MIT"
] | 1 | 2020-11-04T15:43:01.000Z | 2020-11-04T15:43:01.000Z | System/Library/PrivateFrameworks/PhotosUICore.framework/PXNavigationListGroupItem.h | zhangkn/iOS14Header | 4323e9459ed6f6f5504ecbea2710bfd6c3d7c946 | [
"MIT"
] | null | null | null | System/Library/PrivateFrameworks/PhotosUICore.framework/PXNavigationListGroupItem.h | zhangkn/iOS14Header | 4323e9459ed6f6f5504ecbea2710bfd6c3d7c946 | [
"MIT"
] | null | null | null | /*
* This header is generated by classdump-dyld 1.0
* on Monday, September 28, 2020 at 5:55:01 PM Mountain Standard Time
* Operating System: Version 14.0 (Build 18A373)
* Image Source: /System/Library/PrivateFrameworks/PhotosUICore.framework/PhotosUICore
* classdump-dyld is licensed under GPLv3, Copyright © 2013-2016 by Elias Limneos.
*/
#import <PhotosUICore/PhotosUICore-Structs.h>
#import <PhotosUICore/PXNavigationListItem.h>
@class PHCollection;
@interface PXNavigationListGroupItem : PXNavigationListItem {
BOOL _group;
BOOL _draggable;
BOOL _expandable;
PHCollection* _collection;
}
+(id)titleForIdentifier:(id)arg1 ;
-(BOOL)isExpandable;
-(id)initWithIdentifier:(id)arg1 ;
-(id)copyWithZone:(NSZone*)arg1 ;
-(BOOL)isDraggable;
-(id)collection;
-(BOOL)isGroup;
-(id)initWithIdentifier:(id)arg1 collection:(id)arg2 ;
@end
| 30.5625 | 108 | 0.663599 |
f90163cffb7650333bb11ee4a32214a6a42ab5c1 | 1,019 | c | C | 379-a1/test7.c | lllor/Cmput379-OS- | 3e36dfba7fc0c53fb7b10fc5dbea7981b79e6bf9 | [
"MIT"
] | null | null | null | 379-a1/test7.c | lllor/Cmput379-OS- | 3e36dfba7fc0c53fb7b10fc5dbea7981b79e6bf9 | [
"MIT"
] | null | null | null | 379-a1/test7.c | lllor/Cmput379-OS- | 3e36dfba7fc0c53fb7b10fc5dbea7981b79e6bf9 | [
"MIT"
] | null | null | null | #include<stdio.h>
#include<signal.h>
#include<stdlib.h>
#include <unistd.h>
#ifdef SINGLE//second
void OnlineCheckReciever();
void main(){
printf("Own PID:%d\n",getpid());
if(signal(SIGUSR2,OnlineCheckReciever)==SIG_ERR){
printf("usr2 error");
}
while(1);
}
#else//first
int getPID();
void OnlineCheckRequest(int PID);
void main(){
printf("Own PID1:%d\n",getpid());
int other= -1;
//printf("Own PID:%d\n",getpid());
while (other == -1)
{
printf("1");
scanf("%d",&other);
}
//int target_pid = getPID();
printf("%d",other);
//OnlineCheckRequest(target_pid);
while(1);
}
#endif
void OnlineCheckRequest(int PID)//send a signal to other process to allow it get user input
{
printf("1");
kill(PID,SIGUSR2);
}
void OnlineCheckReciever()
{
printf("now enter");
//int id = getPID();
}
int getPID()//promote user enter target PID
{
int other= -1;
//printf("Own PID:%d\n",getpid());
while (other == -1)
{
printf("1");
scanf("%d",&other);
}
return other;
}
| 13.77027 | 91 | 0.622179 |
7f2172c3d32f53205092ee9acbd83fbcfe95f5b4 | 1,484 | h | C | PrivateFrameworks/PassKitCore/PKPeerPaymentWebServiceContext.h | phatblat/macOSPrivateFrameworks | 9047371eb80f925642c8a7c4f1e00095aec66044 | [
"MIT"
] | 17 | 2018-11-13T04:02:58.000Z | 2022-01-20T09:27:13.000Z | PrivateFrameworks/PassKitCore/PKPeerPaymentWebServiceContext.h | phatblat/macOSPrivateFrameworks | 9047371eb80f925642c8a7c4f1e00095aec66044 | [
"MIT"
] | 3 | 2018-04-06T02:02:27.000Z | 2018-10-02T01:12:10.000Z | PrivateFrameworks/PassKitCore/PKPeerPaymentWebServiceContext.h | phatblat/macOSPrivateFrameworks | 9047371eb80f925642c8a7c4f1e00095aec66044 | [
"MIT"
] | 1 | 2018-09-28T13:54:23.000Z | 2018-09-28T13:54:23.000Z | //
// Generated by class-dump 3.5 (64 bit).
//
// class-dump is Copyright (C) 1997-1998, 2000-2001, 2004-2013 by Steve Nygard.
//
#import <PassKitCore/PKWebServiceContext.h>
@class NSData, NSString, NSURL;
@interface PKPeerPaymentWebServiceContext : PKWebServiceContext
{
BOOL _devSigned;
NSURL *_serviceURL;
NSString *_deviceIdentifier;
NSString *_pushTopic;
NSString *_pushToken;
NSString *_companionSerialNumber;
NSData *_signedEnrollmentDataSignature;
}
+ (id)contextWithArchive:(id)arg1;
+ (BOOL)supportsSecureCoding;
@property(copy, nonatomic) NSData *signedEnrollmentDataSignature; // @synthesize signedEnrollmentDataSignature=_signedEnrollmentDataSignature;
@property(readonly, copy, nonatomic) NSString *companionSerialNumber; // @synthesize companionSerialNumber=_companionSerialNumber;
@property(nonatomic) BOOL devSigned; // @synthesize devSigned=_devSigned;
@property(copy, nonatomic) NSString *pushToken; // @synthesize pushToken=_pushToken;
@property(readonly, copy, nonatomic) NSString *pushTopic; // @synthesize pushTopic=_pushTopic;
@property(readonly, copy, nonatomic) NSString *deviceIdentifier; // @synthesize deviceIdentifier=_deviceIdentifier;
@property(readonly, copy, nonatomic) NSURL *serviceURL; // @synthesize serviceURL=_serviceURL;
- (void).cxx_destruct;
- (void)updateContextWithDeviceRegistrationData:(id)arg1 registrationResponse:(id)arg2;
- (void)encodeWithCoder:(id)arg1;
- (id)initWithCoder:(id)arg1;
@end
| 39.052632 | 142 | 0.780997 |
bf659ca9a72bc3b5c63a944426a4cf629e7709cd | 2,926 | h | C | release/src-rt-6.x.4708/router/mysql/storage/innobase/include/mem0pool.h | afeng11/tomato-arm | 1ca18a88480b34fd495e683d849f46c2d47bb572 | [
"FSFAP"
] | 278 | 2015-11-03T03:01:20.000Z | 2022-01-20T18:21:05.000Z | apps/mysql-5.1.65/storage/innobase/include/mem0pool.h | vusec/firestarter | 2048c1f731b8f3c5570a920757f9d7730d5f716a | [
"Apache-2.0"
] | 374 | 2015-11-03T12:37:22.000Z | 2021-12-17T14:18:08.000Z | apps/mysql-5.1.65/storage/innobase/include/mem0pool.h | vusec/firestarter | 2048c1f731b8f3c5570a920757f9d7730d5f716a | [
"Apache-2.0"
] | 96 | 2015-11-22T07:47:26.000Z | 2022-01-20T19:52:19.000Z | /******************************************************
The lowest-level memory management
(c) 1994, 1995 Innobase Oy
Created 6/9/1994 Heikki Tuuri
*******************************************************/
#ifndef mem0pool_h
#define mem0pool_h
#include "univ.i"
#include "os0file.h"
#include "ut0lst.h"
typedef struct mem_area_struct mem_area_t;
typedef struct mem_pool_struct mem_pool_t;
/* The common memory pool */
extern mem_pool_t* mem_comm_pool;
/* Memory area header */
struct mem_area_struct{
ulint size_and_free; /* memory area size is obtained by
anding with ~MEM_AREA_FREE; area in
a free list if ANDing with
MEM_AREA_FREE results in nonzero */
UT_LIST_NODE_T(mem_area_t)
free_list; /* free list node */
};
/* Each memory area takes this many extra bytes for control information */
#define MEM_AREA_EXTRA_SIZE (ut_calc_align(sizeof(struct mem_area_struct),\
UNIV_MEM_ALIGNMENT))
/************************************************************************
Creates a memory pool. */
mem_pool_t*
mem_pool_create(
/*============*/
/* out: memory pool */
ulint size); /* in: pool size in bytes */
/************************************************************************
Allocates memory from a pool. NOTE: This low-level function should only be
used in mem0mem.*! */
void*
mem_area_alloc(
/*===========*/
/* out, own: allocated memory buffer */
ulint size, /* in: allocated size in bytes; for optimum
space usage, the size should be a power of 2
minus MEM_AREA_EXTRA_SIZE */
mem_pool_t* pool); /* in: memory pool */
/************************************************************************
Frees memory to a pool. */
void
mem_area_free(
/*==========*/
void* ptr, /* in, own: pointer to allocated memory
buffer */
mem_pool_t* pool); /* in: memory pool */
/************************************************************************
Returns the amount of reserved memory. */
ulint
mem_pool_get_reserved(
/*==================*/
/* out: reserved mmeory in bytes */
mem_pool_t* pool); /* in: memory pool */
/************************************************************************
Reserves the mem pool mutex. */
void
mem_pool_mutex_enter(void);
/*======================*/
/************************************************************************
Releases the mem pool mutex. */
void
mem_pool_mutex_exit(void);
/*=====================*/
/************************************************************************
Validates a memory pool. */
ibool
mem_pool_validate(
/*==============*/
/* out: TRUE if ok */
mem_pool_t* pool); /* in: memory pool */
/************************************************************************
Prints info of a memory pool. */
void
mem_pool_print_info(
/*================*/
FILE* outfile,/* in: output file to write to */
mem_pool_t* pool); /* in: memory pool */
#ifndef UNIV_NONINL
#include "mem0pool.ic"
#endif
#endif
| 26.844037 | 75 | 0.50581 |
6876a5e5b07601613749c27fe0c399b05eec28b7 | 1,339 | h | C | CallTraceForWeChat/CallTraceForWeChat/WeChat_Headers/FBSDKWebDialogView.h | ceekay1991/CallTraceForWeChat | 5767cb6f781821b6bf9facc8c87e58e15fa88541 | [
"MIT"
] | 30 | 2020-03-22T12:30:21.000Z | 2022-02-09T08:49:13.000Z | CallTraceForWeChat/CallTraceForWeChat/WeChat_Headers/FBSDKWebDialogView.h | ceekay1991/CallTraceForWeChat | 5767cb6f781821b6bf9facc8c87e58e15fa88541 | [
"MIT"
] | null | null | null | CallTraceForWeChat/CallTraceForWeChat/WeChat_Headers/FBSDKWebDialogView.h | ceekay1991/CallTraceForWeChat | 5767cb6f781821b6bf9facc8c87e58e15fa88541 | [
"MIT"
] | 8 | 2020-03-22T12:30:23.000Z | 2020-09-22T04:01:47.000Z | //
// Generated by class-dump 3.5 (64 bit) (Debug version compiled Sep 17 2017 16:24:48).
//
// class-dump is Copyright (C) 1997-1998, 2000-2001, 2004-2015 by Steve Nygard.
//
#import <UIKit/UIView.h>
#import "WKNavigationDelegate-Protocol.h"
@class NSString, UIActivityIndicatorView, UIButton, WKWebView;
@protocol FBSDKWebDialogViewDelegate;
@interface FBSDKWebDialogView : UIView <WKNavigationDelegate>
{
UIButton *_closeButton;
UIActivityIndicatorView *_loadingView;
WKWebView *_webView;
id <FBSDKWebDialogViewDelegate> _delegate;
}
@property(nonatomic) __weak id <FBSDKWebDialogViewDelegate> delegate; // @synthesize delegate=_delegate;
- (void).cxx_destruct;
- (void)webView:(id)arg1 didFinishNavigation:(id)arg2;
- (void)webView:(id)arg1 decidePolicyForNavigationAction:(id)arg2 decisionHandler:(CDUnknownBlockType)arg3;
- (void)webView:(id)arg1 didFailNavigation:(id)arg2 withError:(id)arg3;
- (void)_close:(id)arg1;
- (void)layoutSubviews;
- (void)drawRect:(struct CGRect)arg1;
- (void)stopLoading;
- (void)loadURL:(id)arg1;
- (void)dealloc;
- (id)initWithFrame:(struct CGRect)arg1;
// Remaining properties
@property(readonly, copy) NSString *debugDescription;
@property(readonly, copy) NSString *description;
@property(readonly) unsigned long long hash;
@property(readonly) Class superclass;
@end
| 31.139535 | 107 | 0.761763 |
68bae57921a60868e18b6e2b7b251fdc09abb669 | 17,510 | c | C | slant-collectd-openbsd.c | timkuijsten/slant | 172950aa1d38566f22f8383b6553f9d534befa8f | [
"ISC"
] | null | null | null | slant-collectd-openbsd.c | timkuijsten/slant | 172950aa1d38566f22f8383b6553f9d534befa8f | [
"ISC"
] | null | null | null | slant-collectd-openbsd.c | timkuijsten/slant | 172950aa1d38566f22f8383b6553f9d534befa8f | [
"ISC"
] | null | null | null | /* $Id$ */
/*
* A lot of this file is a restatement of OpenBSD's top(1) machine.c.
* Its copyright and license file is retained below.
*/
/*-
* Copyright (c) 1994 Thorsten Lockert <tholo@sigmasoft.com>
* Copyright (c) 2018 Thorsten Lockert <tholo@sigmasoft.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Other parts are from OpenBSD's systat(1) if.c.
* Its copyright and license file is retained below.
*/
/*
* Copyright (c) 2004 Markus Friedl <markus@openbsd.org>
* Copyright (c) 2018 Kristaps Dzonsons <kristaps@bsd.lv>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <sys/param.h>
#include <sys/sched.h>
#include <sys/socket.h>
#include <sys/sysctl.h>
#include <net/if.h>
#include <net/route.h>
#include <sys/ioctl.h>
#include <sys/disk.h>
#include <assert.h>
#include <err.h>
#include <errno.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "slant-collectd.h"
struct ifcount {
u_int64_t ifc_ib; /* input bytes */
u_int64_t ifc_ip; /* input packets */
u_int64_t ifc_ie; /* input errors */
u_int64_t ifc_ob; /* output bytes */
u_int64_t ifc_op; /* output packets */
u_int64_t ifc_oe; /* output errors */
u_int64_t ifc_co; /* collisions */
int ifc_flags; /* up / down */
int ifc_state; /* link state */
};
struct ifstat {
struct ifcount ifs_cur;
struct ifcount ifs_old;
struct ifcount ifs_now;
char ifs_flag;
};
/*
* Define pagetok in terms of pageshift.
*/
#define PAGETOK(size, pageshift) ((size) << (pageshift))
struct sysinfo {
size_t sample; /* sample number */
int pageshift; /* used for memory pages */
double mem_avg; /* average memory */
double nproc_pct; /* nprocs percent */
double nfile_pct; /* nfiles percent */
int64_t *cpu_states; /* used for cpu compute */
double cpu_avg; /* average cpu */
int64_t **cp_time; /* used for cpu compute */
int64_t **cp_old; /* used for cpu compute */
int64_t **cp_diff; /* used for cpu compute */
size_t ncpu; /* number cpus */
double rproc_pct; /* pct command (by name) found */
struct ifstat *ifstats; /* used for inet compute */
size_t ifstatsz; /* used for inet compute */
struct ifcount ifsum; /* average inet */
u_int64_t disc_rbytes; /* last disc total read */
u_int64_t disc_wbytes; /* last disc total write */
int64_t disc_ravg; /* average reads/sec */
int64_t disc_wavg; /* average reads/sec */
time_t boottime; /* time booted */
};
/*
* Get the number of online (working) CPUs---that is, those that will
* return non-zero working time.
* Return zero on failure, non-zero on success.
* Fills in "p" on success.
*/
static int
getonlinecpu(size_t *p)
{
int mib[] = { CTL_HW, HW_NCPUONLINE };
int numcpu;
size_t size = sizeof(numcpu);
if (sysctl(mib, sizeof(mib) / sizeof(mib[0]),
&numcpu, &size, NULL, 0) == -1) {
warn("sysctl: CTL_HW, HW_NCPUONLINE");
return 0;
}
*p = numcpu;
return 1;
}
/*
* Get the number of configured CPUs.
* This might be less than the number of working CPUs.
* Return zero on failure, non-zero on success.
* Fills in "p" on success.
*/
static int
getncpu(size_t *p)
{
int mib[] = { CTL_HW, HW_NCPU };
int numcpu;
size_t size = sizeof(numcpu);
if (sysctl(mib, sizeof(mib) / sizeof(mib[0]),
&numcpu, &size, NULL, 0) == -1) {
warn("sysctl: CTL_HW, HW_NCPU");
return 0;
}
*p = numcpu;
return 1;
}
static void
percentages(int cnt, int64_t *out,
int64_t *new, int64_t *old, int64_t *diffs)
{
int64_t change, tot, *dp, half_total;
int i;
/* initialization */
tot = 0;
dp = diffs;
/* calculate changes for each state and the overall change */
for (i = 0; i < cnt; i++) {
if ((change = *new - *old) < 0) {
/* this only happens when the counter wraps */
change = INT64_MAX - *old + *new;
}
tot += (*dp++ = change);
*old++ = *new++;
}
/* avoid divide by zero potential */
if (tot == 0)
tot = 1;
/* calculate percentages based on overall change, rounding up */
half_total = tot / 2l;
for (i = 0; i < cnt; i++)
*out++ = ((*diffs++ * 1000 + half_total) / tot);
}
void
sysinfo_free(struct sysinfo *p)
{
size_t i;
if (NULL == p)
return;
for (i = 0; i < p->ncpu; i++) {
free(p->cp_time[i]);
free(p->cp_old[i]);
free(p->cp_diff[i]);
}
free(p->cp_time);
free(p->cp_old);
free(p->cp_diff);
free(p->cpu_states);
free(p->ifstats);
free(p);
}
static int
sysinfo_init_boottime(struct sysinfo *p)
{
int bt_mib[] = { CTL_KERN, KERN_BOOTTIME };
struct timeval tv;
size_t size;
size = sizeof(struct timeval);
if (sysctl(bt_mib, 2, &tv, &size, NULL, 0) < 0) {
warn("sysctl: CTL_KERN, KERN_BOOTTIME");
return 0;
}
p->boottime = tv.tv_sec;
return 1;
}
struct sysinfo *
sysinfo_alloc(void)
{
struct sysinfo *p;
size_t i;
int pagesize;
p = calloc(1, sizeof(struct sysinfo));
if (NULL == p) {
warn(NULL);
return NULL;
}
if ( ! getncpu(&p->ncpu)) {
warn(NULL);
sysinfo_free(p);
return NULL;
}
assert(p->ncpu > 0);
p->cpu_states = calloc
(p->ncpu, CPUSTATES * sizeof(int64_t));
p->cp_time = calloc(p->ncpu, sizeof(int64_t *));
p->cp_old = calloc(p->ncpu, sizeof(int64_t *));
p->cp_diff = calloc(p->ncpu, sizeof(int64_t *));
if (NULL == p->cpu_states ||
NULL == p->cp_time ||
NULL == p->cp_old ||
NULL == p->cp_diff) {
warn(NULL);
sysinfo_free(p);
return NULL;
}
for (i = 0; i < p->ncpu; i++) {
p->cp_time[i] = calloc(CPUSTATES, sizeof(int64_t));
p->cp_old[i] = calloc(CPUSTATES, sizeof(int64_t));
p->cp_diff[i] = calloc(CPUSTATES, sizeof(int64_t));
if (NULL == p->cp_time[i] ||
NULL == p->cp_old[i] ||
NULL == p->cp_diff[i]) {
warn(NULL);
sysinfo_free(p);
return NULL;
}
}
/*
* get the page size with "getpagesize" and calculate pageshift
* from it
*/
pagesize = getpagesize();
p->pageshift = 0;
while (pagesize > 1) {
p->pageshift++;
pagesize >>= 1;
}
/* we only need the amount of log(2)1024 for our conversion */
p->pageshift -= 10;
if ( ! sysinfo_init_boottime(p)) {
sysinfo_free(p);
return NULL;
}
return p;
}
static int
sysinfo_update_mem(struct sysinfo *p)
{
int uvmexp_mib[] = { CTL_VM, VM_UVMEXP };
struct uvmexp uvmexp;
size_t size;
size = sizeof(uvmexp);
if (sysctl(uvmexp_mib, 2, &uvmexp, &size, NULL, 0) < 0) {
warn("sysctl: CTL_VM, VM_UVMEXP");
return 0;
}
p->mem_avg = 100.0 *
PAGETOK(uvmexp.active, p->pageshift) /
(double)PAGETOK(uvmexp.npages, p->pageshift);
return 1;
}
static int
sysinfo_update_nfiles(const struct syscfg *cfg, struct sysinfo *p)
{
size_t size;
int maxfile, nfiles;
int cp_nfile_mib[] = { CTL_KERN, KERN_NFILES },
cp_maxfile_mib[] = { CTL_KERN, KERN_MAXFILES };
size = sizeof(int);
if (sysctl(cp_maxfile_mib, 2, &maxfile, &size, NULL, 0) < 0) {
warn("sysctl: CTL_KERN, KERN_MAXFILES");
return 0;
} else if (0 == maxfile) {
warnx("sysctl: CTL_KERN, KERN_MAXFILES returns 0");
return 0;
}
size = sizeof(int);
if (sysctl(cp_nfile_mib, 2,
&nfiles, &size, NULL, 0) < 0) {
warn("sysctl: CTL_KERN, KERN_NFILES");
return 0;
}
p->nfile_pct = 100.0 * nfiles / (double)maxfile;
return 1;
}
static int
sysinfo_update_nprocs(const struct syscfg *cfg, struct sysinfo *p)
{
size_t i, j, size, len, rprocs = 0;
int maxproc, nprocs;
int cp_nproc_mib[] = { CTL_KERN, KERN_NPROCS },
cp_maxproc_mib[] = { CTL_KERN, KERN_MAXPROC },
cp_procs_mib[] = { CTL_KERN, KERN_PROC,
0, 0, sizeof(struct kinfo_proc), 0};
struct kinfo_proc *pb = NULL;
size = sizeof(int);
if (sysctl(cp_maxproc_mib, 2, &maxproc, &size, NULL, 0) < 0) {
warn("sysctl: CTL_KERN, KERN_MAXPROC");
return 0;
} else if (0 == maxproc) {
warnx("sysctl: CTL_KERN, KERN_MAXPROC returns 0");
return 0;
}
/*
* If we're only going to look at the number of processes, then
* there's no need for us to look at the kinfo_proc: we always
* have 100% running (of... none).
* So short-circuit here.
*/
if (0 == cfg->cmdsz) {
size = sizeof(int);
if (sysctl(cp_nproc_mib, 2,
&nprocs, &size, NULL, 0) < 0) {
warn("sysctl: CTL_KERN, KERN_NPROCS");
return 0;
}
p->nproc_pct = 100.0 * nprocs / (double)maxproc;
p->rproc_pct = 100.0;
return 1;
}
retry:
free(pb);
size = sizeof(int);
if (sysctl(cp_procs_mib, 6, NULL, &size, NULL, 0) < 0) {
warn("sysctl: CTL_KERN, KERN_PROC");
return 0;
}
/* Add extra slop for new interim processes. */
size = 5 * size / 4;
if (NULL == (pb = malloc(size))) {
warn(NULL);
return 0;
}
cp_procs_mib[5] = (int)(size / sizeof(struct kinfo_proc));
if (sysctl(cp_procs_mib, 6, pb, &size, NULL, 0) < 0) {
if (errno == ENOMEM)
goto retry;
warn("sysctl: CTL_KERN, KERN_PROC");
free(pb);
return 0;
}
len = size / sizeof(struct kinfo_proc);
for (j = 0; j < cfg->cmdsz; j++) {
for (i = 0; i < len; i++) {
if (0 == strcmp(pb[i].p_comm, cfg->cmds[j]))
break;
}
if (i < len)
rprocs++;
}
free(pb);
p->nproc_pct = 100.0 * len / (double)maxproc;
p->rproc_pct = 100.0 * rprocs / (double)cfg->cmdsz;
return 1;
}
static int
sysinfo_update_cpu(struct sysinfo *p)
{
size_t i, pos, size, online = 0;
long cp_time_tmp[CPUSTATES];
int64_t val;
double sum = 0.0;
int64_t *tmpstate;
if ( ! getonlinecpu(&online))
return 0;
assert(online > 0);
/*
* If the CPU is offline (like with disabled hyperthreads), the
* CPU will return zero percent usage.
* We use getonlinecpu() to make sure that when we divide our
* accumulated percentage, it works out.
* We can also use KERN_CPUSTATS.
*/
if (p->ncpu > 1) {
int cp_time_mib[] =
{ CTL_KERN, KERN_CPTIME2, /*fillme*/0 };
size = CPUSTATES * sizeof(int64_t);
for (i = 0; i < p->ncpu; i++) {
cp_time_mib[2] = i;
tmpstate = p->cpu_states + (CPUSTATES * i);
if (sysctl(cp_time_mib, 3,
p->cp_time[i], &size, NULL, 0) < 0) {
warn("sysctl: CTL_KERN, KERN_CPTIME2");
return 0;
}
percentages(CPUSTATES, tmpstate,
p->cp_time[i], p->cp_old[i],
p->cp_diff[i]);
}
} else {
int cp_time_mib[] = { CTL_KERN, KERN_CPTIME };
size = sizeof(cp_time_tmp);
if (sysctl(cp_time_mib, 2,
cp_time_tmp, &size, NULL, 0) < 0) {
warn("sysctl: CTL_KERN, KERN_CPTIME");
return 0;
}
for (i = 0; i < CPUSTATES; i++)
p->cp_time[0][i] = cp_time_tmp[i];
percentages(CPUSTATES, p->cpu_states, p->cp_time[0],
p->cp_old[0], p->cp_diff[0]);
}
/* Update our averages. */
for (i = 0; i < p->ncpu; i++) {
pos = i * CPUSTATES + CP_IDLE;
val = 1000 - p->cpu_states[pos];
if (val > 1000) {
warnx("CPU state out of bound: %" PRId64, val);
val = 1000;
} else if (val < 0) {
warnx("CPU state out of bound: %" PRId64, val);
val = 0;
}
sum += val / 10.;
}
p->cpu_avg = sum / online;
return 1;
}
#define UPDATE(x, y, up) \
do { \
ifs->ifs_now.x = ifm.y; \
ifs->ifs_cur.x = ifs->ifs_now.x - ifs->ifs_old.x; \
ifs->ifs_old.x = ifs->ifs_now.x; \
ifs->ifs_cur.x /= 15; \
if ((up)) \
p->ifsum.x += ifs->ifs_cur.x; \
} while(0)
static int
sysinfo_update_if(struct sysinfo *p)
{
struct ifstat *newstats, *ifs;
struct if_msghdr ifm;
char *buf, *next, *lim;
int mib[6];
size_t need, up;
mib[0] = CTL_NET;
mib[1] = PF_ROUTE;
mib[2] = 0;
mib[3] = 0;
mib[4] = NET_RT_IFLIST;
mib[5] = 0;
if (-1 == sysctl(mib, 6, NULL, &need, NULL, 0)) {
warn("sysctl: CTL_NET, PF_ROUTE, NET_RT_IFLIST");
return 0;
} else if (NULL == (buf = malloc(need))) {
warn(NULL);
return 0;
} else if (-1 == sysctl(mib, 6, buf, &need, NULL, 0)) {
warn("sysctl: CTL_NET, PF_ROUTE, NET_RT_IFLIST");
free(buf);
return 0;
}
memset(&p->ifsum, 0, sizeof(p->ifsum));
lim = buf + need;
for (next = buf; next < lim; next += ifm.ifm_msglen) {
memcpy(&ifm, next, sizeof(ifm));
if (ifm.ifm_version != RTM_VERSION ||
ifm.ifm_type != RTM_IFINFO ||
! (ifm.ifm_addrs & RTA_IFP))
continue;
if (ifm.ifm_index >= p->ifstatsz) {
newstats = reallocarray
(p->ifstats, ifm.ifm_index + 4,
sizeof(struct ifstat));
if (NULL == newstats) {
warn(NULL);
free(buf);
return 0;
}
p->ifstats = newstats;
while (p->ifstatsz < ifm.ifm_index + 4) {
memset(&p->ifstats[p->ifstatsz],
0, sizeof(*p->ifstats));
p->ifstatsz++;
}
}
ifs = &p->ifstats[ifm.ifm_index];
/* Only consider non-loopback up addresses. */
up = (ifs->ifs_cur.ifc_flags & IFF_UP) &&
! (ifs->ifs_cur.ifc_flags & IFF_LOOPBACK);
UPDATE(ifc_ip, ifm_data.ifi_ipackets, up);
UPDATE(ifc_ib, ifm_data.ifi_ibytes, up);
UPDATE(ifc_ie, ifm_data.ifi_ierrors, up);
UPDATE(ifc_op, ifm_data.ifi_opackets, up);
UPDATE(ifc_ob, ifm_data.ifi_obytes, up);
UPDATE(ifc_oe, ifm_data.ifi_oerrors, up);
UPDATE(ifc_co, ifm_data.ifi_collisions, up);
ifs->ifs_cur.ifc_flags = ifm.ifm_flags;
ifs->ifs_cur.ifc_state = ifm.ifm_data.ifi_link_state;
ifs->ifs_flag++;
}
free(buf);
return 1;
}
static int
sysinfo_update_disc(const struct syscfg *cfg, struct sysinfo *p)
{
struct diskstats q;
size_t i, need;
int mib[2];
char *buf, *lim, *next;
u_int64_t rb = 0, wb = 0;
mib[0] = CTL_HW;
mib[1] = HW_DISKSTATS;
if (sysctl(mib, 2, NULL, &need, NULL, 0) < 0) {
warn("sysctl: CTL_HW, HW_DISKSTATS");
return 0;
} else if (NULL == (buf = malloc(need))) {
warn(NULL);
return 0;
} else if (-1 == sysctl(mib, 2, buf, &need, NULL, 0)) {
warn("sysctl: CTL_HW, HW_DISKSTATS");
free(buf);
return 0;
}
lim = buf + need;
for (next = buf; next < lim; next += sizeof(q)) {
memcpy(&q, next, sizeof(q));
for (i = 0; i < cfg->discsz; i++)
if (0 == strcmp(cfg->discs[i], q.ds_name))
break;
if (cfg->discsz && i == cfg->discsz)
continue;
rb += q.ds_rbytes;
wb += q.ds_wbytes;
}
if (rb > p->disc_rbytes) {
p->disc_ravg = (rb - p->disc_rbytes) / 15;
p->disc_rbytes = rb;
} else {
p->disc_ravg = 0;
p->disc_rbytes = rb;
}
if (wb > p->disc_wbytes) {
p->disc_wavg = (wb - p->disc_wbytes) / 15;
p->disc_wbytes = wb;
} else {
p->disc_wavg = 0;
p->disc_wbytes = wb;
}
free(buf);
return 1;
}
int
sysinfo_update(const struct syscfg *cfg, struct sysinfo *p)
{
if ( ! sysinfo_update_nprocs(cfg, p))
return 0;
if ( ! sysinfo_update_nfiles(cfg, p))
return 0;
if ( ! sysinfo_update_cpu(p))
return 0;
if ( ! sysinfo_update_mem(p))
return 0;
if ( ! sysinfo_update_if(p))
return 0;
if ( ! sysinfo_update_disc(cfg, p))
return 0;
p->sample++;
return 1;
}
double
sysinfo_get_cpu_avg(const struct sysinfo *p)
{
return p->cpu_avg;
}
double
sysinfo_get_mem_avg(const struct sysinfo *p)
{
return p->mem_avg;
}
int64_t
sysinfo_get_nettx_avg(const struct sysinfo *p)
{
if (1 == p->sample)
return 0;
return p->ifsum.ifc_ob;
}
int64_t
sysinfo_get_netrx_avg(const struct sysinfo *p)
{
if (1 == p->sample)
return 0;
return p->ifsum.ifc_ib;
}
int64_t
sysinfo_get_discread_avg(const struct sysinfo *p)
{
if (1 == p->sample)
return 0;
return p->disc_ravg;
}
int64_t
sysinfo_get_discwrite_avg(const struct sysinfo *p)
{
if (1 == p->sample)
return 0;
return p->disc_wavg;
}
double
sysinfo_get_rprocs(const struct sysinfo *p)
{
return p->rproc_pct;
}
double
sysinfo_get_nfiles(const struct sysinfo *p)
{
return p->nfile_pct;
}
double
sysinfo_get_nprocs(const struct sysinfo *p)
{
return p->nproc_pct;
}
time_t
sysinfo_get_boottime(const struct sysinfo *p)
{
return p->boottime;
}
| 23.192053 | 78 | 0.642547 |
70f501377b4d78d84f1bf00bb5d74e1a8a4f0163 | 6,832 | h | C | ugene/src/corelibs/U2View/src/ov_sequence/GSequenceLineView.h | iganna/lspec | c75cba3e4fa9a46abeecbf31b5d467827cf4fec0 | [
"MIT"
] | null | null | null | ugene/src/corelibs/U2View/src/ov_sequence/GSequenceLineView.h | iganna/lspec | c75cba3e4fa9a46abeecbf31b5d467827cf4fec0 | [
"MIT"
] | null | null | null | ugene/src/corelibs/U2View/src/ov_sequence/GSequenceLineView.h | iganna/lspec | c75cba3e4fa9a46abeecbf31b5d467827cf4fec0 | [
"MIT"
] | null | null | null | /**
* UGENE - Integrated Bioinformatics Tools.
* Copyright (C) 2008-2012 UniPro <ugene@unipro.ru>
* http://ugene.unipro.ru
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef _U2_GSEQUENCE_LINE_VIEW_H_
#define _U2_GSEQUENCE_LINE_VIEW_H_
#include <U2Core/U2Region.h>
#include <QtCore/QFlag>
#include <QtGui/QWidget>
#include <QtGui/QMouseEvent>
#include <QtGui/QWheelEvent>
#include <QtGui/QFocusEvent>
#include <QtGui/QPainter>
#include <QtGui/QMenu>
namespace U2 {
class GSequenceLineViewRenderArea;
class DNASequenceSelection;
class LRegionsSelection;
class GScrollBar;
class ADVSequenceObjectContext;
class GObjectViewOpConstraints;
class GObject;
class U2SequenceObject;
enum GSLV_UpdateFlag {
GSLV_UF_NeedCompleteRedraw = 1<<0,
GSLV_UF_ViewResized = 1<<1,
GSLV_UF_VisibleRangeChanged = 1<<2,
GSLV_UF_SelectionChanged = 1<<3,
GSLV_UF_FocusChanged = 1<<4,
GSLV_UF_FrameChanged = 1<<5,
GSLV_UF_AnnotationsChanged = 1<<6
};
enum GSLV_FeatureFlag {
GSLV_FF_SupportsCustomRange = 0x1
};
typedef QFlags<GSLV_UpdateFlag> GSLV_UpdateFlags;
typedef QFlags<GSLV_FeatureFlag> GSLV_FeatureFlags;
//single-line sequence view
class U2VIEW_EXPORT GSequenceLineView : public QWidget {
Q_OBJECT
public:
GSequenceLineView(QWidget* p, ADVSequenceObjectContext* ctx);
const U2Region& getVisibleRange() const {return visibleRange;}
ADVSequenceObjectContext* getSequenceContext() const {return ctx;}
virtual void setStartPos(qint64 pos);
virtual void setCenterPos(qint64 pos);
qint64 getSequenceLength() const {return seqLen;}
virtual void addUpdateFlags(GSLV_UpdateFlags newFlags) {lastUpdateFlags|=newFlags;}
virtual void clearUpdateFlags() {lastUpdateFlags = 0;}
GSLV_UpdateFlags getUpdateFlags() const {return lastUpdateFlags;}
virtual void setFrameView(GSequenceLineView* frameView);
virtual GSequenceLineView* getFrameView() const {return frameView;}
virtual void setCoherentRangeView(GSequenceLineView* rangeView);
virtual GSequenceLineView* getConherentRangeView() const {return coherentRangeView;}
// [0..seqLen)
virtual void setVisibleRange(const U2Region& reg, bool signal = true);
virtual QAction* getZoomInAction() const {return coherentRangeView == NULL ? NULL : coherentRangeView->getZoomInAction();}
virtual QAction* getZoomOutAction() const {return coherentRangeView == NULL ? NULL : coherentRangeView->getZoomOutAction();}
virtual QAction* getZoomToSelectionAction() const {return coherentRangeView == NULL ? NULL : coherentRangeView->getZoomToSelectionAction();}
virtual QAction* getZoomToSequenceAction() const {return coherentRangeView == NULL ? NULL : coherentRangeView->getZoomToSequenceAction();}
virtual U2SequenceObject* getSequenceObject() const;
virtual void buildPopupMenu(QMenu& m){ Q_UNUSED(m); }
virtual bool isWidgetOnlyObject(GObject* o) const { Q_UNUSED(o); return false;}
virtual bool eventFilter (QObject * watched, QEvent * event);
signals:
void si_visibleRangeChanged();
void si_centerPosition(qint64 pos);
protected:
void resizeEvent(QResizeEvent* e);
void mouseDoubleClickEvent(QMouseEvent* me);
void mousePressEvent(QMouseEvent* me);
void mouseReleaseEvent(QMouseEvent* me);
void mouseMoveEvent(QMouseEvent* me);
void wheelEvent(QWheelEvent* we);
void focusInEvent(QFocusEvent* fe);
void focusOutEvent(QFocusEvent* fe);
void keyPressEvent(QKeyEvent *e);
virtual void onVisibleRangeChanged(bool signal = true);
public slots:
void sl_centerPosition(int pos) {setCenterPos(pos);}
protected slots:
virtual void sl_onScrollBarMoved(int pos);
virtual void sl_onDNASelectionChanged(LRegionsSelection* thiz, const QVector<U2Region>& added, const QVector<U2Region>& removed);
virtual void sl_sequenceChanged();
void sl_onFrameRangeChanged();
void sl_onCoherentRangeViewRangeChanged();
void completeUpdate();
protected:
QPoint toRenderAreaPoint(const QPoint& p);
void updateScrollBar();
void setSelection(const U2Region& r);
void addSelection(const U2Region& r);
void removeSelection(const U2Region& r);
virtual void pack();
virtual int getSingleStep() const;
virtual int getPageStep() const;
ADVSequenceObjectContext* ctx;
GSequenceLineViewRenderArea* renderArea;
U2Region visibleRange;
GScrollBar* scrollBar;
qint64 lastPressPos;
qint64 seqLen;
GSLV_UpdateFlags lastUpdateFlags;
GSLV_FeatureFlags featureFlags;
GSequenceLineView* frameView;
GSequenceLineView* coherentRangeView;
double coefScrollBarMapping;
// special flag setup by child classes that tells to this class do or skip
// any changes to selection on mouse ops
bool ignoreMouseSelectionEvents;
};
class U2VIEW_EXPORT GSequenceLineViewRenderArea : public QWidget {
public:
GSequenceLineViewRenderArea(GSequenceLineView* p);
~GSequenceLineViewRenderArea();
virtual qint64 coordToPos(int x) const;
virtual int posToCoord(qint64 p, bool useVirtualSpace = false) const;
virtual float posToCoordF(qint64 p, bool useVirtualSpace = false) const;
//number of pixels per base
virtual double getCurrentScale() const;
//char width, derived from current 'font'
int getCharWidth() const {return charWidth;}
protected:
virtual void paintEvent(QPaintEvent *e);
virtual void drawAll(QPaintDevice* pd) = 0;
void drawFrame(QPainter& p);
virtual void drawFocus(QPainter& p);
void updateFontMetrics();
GSequenceLineView* view;
QPixmap* cachedView;
QPixmap* tmpView;
//per char and per line metrics
QFont sequenceFont;
QFont smallSequenceFont;
QFont rulerFont;
int charWidth;
int smallCharWidth;
int lineHeight;
int yCharOffset;
int xCharOffset;
};
} //namespace
#endif
| 32.226415 | 144 | 0.721019 |
3b132414388c84fd395a8348349da6453f26f420 | 393 | c | C | tutorialspoint/4-c_constants/constants.c | tarekbadrshalaan/C | a98d0f4e77a44dbdf4a82ba665cb282af5ef97d8 | [
"MIT"
] | null | null | null | tutorialspoint/4-c_constants/constants.c | tarekbadrshalaan/C | a98d0f4e77a44dbdf4a82ba665cb282af5ef97d8 | [
"MIT"
] | null | null | null | tutorialspoint/4-c_constants/constants.c | tarekbadrshalaan/C | a98d0f4e77a44dbdf4a82ba665cb282af5ef97d8 | [
"MIT"
] | null | null | null | #include <stdio.h>
#define LENGTH1 10
#define WIDTH1 5
#define NEWLINE '\n'
int main(){
int area1 ;
area1 = LENGTH1 * WIDTH1;
printf("value of area1 : %d",area1);
printf("%c",NEWLINE);
const int LENGTH2 = 10;
const int WIDTH2 = 10;
int area2 ;
area2 = LENGTH2 * WIDTH2;
printf("value of area2 : %d",area2);
printf("%c",NEWLINE);
return 0 ;
}
| 15.72 | 40 | 0.585242 |
3b14522d9216b9f421484f436b2e90760e4ce422 | 654 | h | C | Window Controllers/RegistrationSplashController.h | echristopherson/Creatures | 290709536161781fcaf4a999b4bc3a407cfee2e8 | [
"BSD-3-Clause"
] | 1 | 2021-11-16T03:24:49.000Z | 2021-11-16T03:24:49.000Z | Window Controllers/RegistrationSplashController.h | echristopherson/Creatures | 290709536161781fcaf4a999b4bc3a407cfee2e8 | [
"BSD-3-Clause"
] | null | null | null | Window Controllers/RegistrationSplashController.h | echristopherson/Creatures | 290709536161781fcaf4a999b4bc3a407cfee2e8 | [
"BSD-3-Clause"
] | null | null | null | //
// RegistrationSplashController.h
// Creatures
//
// Created by Michael Ash on Thu Oct 16 2003.
// Copyright (c) 2003 __MyCompanyName__. All rights reserved.
//
#import <AppKit/AppKit.h>
@interface RegistrationSplashController : NSWindowController {
IBOutlet NSButton *notYetButton;
IBOutlet NSTextField *messageField;
}
+ (int)runRegistrationSplashWithMessage:(NSString *)message notYetDelay:(NSTimeInterval)delay;
// returns 1 for 'purchase', 2 for 'enter serial number', 3 for 'not yet'
- (void)setMessage:(NSString *)message delay:(NSTimeInterval)delay;
- (void)purchase:sender;
- (void)doRegister:sender;
- (void)notYet:sender;
@end
| 25.153846 | 94 | 0.752294 |
7d8b1e328c8fa4adfce567c1b6ad536997ed9b27 | 319 | c | C | validation_tests/llvm/f18/gfortran.dg/c_ptr_tests_7_driver.c | brugger1/testsuite | 9b504db668cdeaf7c561f15b76c95d05bfdd1517 | [
"MIT"
] | 488 | 2015-01-09T08:54:48.000Z | 2022-03-30T07:15:46.000Z | tests/CompileTests/Fortran_tests/gfortranTestSuite/gfortran.dg/c_ptr_tests_7_driver.c | sujankh/rose-matlab | 7435d4fa1941826c784ba97296c0ec55fa7d7c7e | [
"BSD-3-Clause"
] | 174 | 2015-01-28T18:41:32.000Z | 2022-03-31T16:51:05.000Z | tests/CompileTests/Fortran_tests/gfortranTestSuite/gfortran.dg/c_ptr_tests_7_driver.c | sujankh/rose-matlab | 7435d4fa1941826c784ba97296c0ec55fa7d7c7e | [
"BSD-3-Clause"
] | 146 | 2015-04-27T02:48:34.000Z | 2022-03-04T07:32:53.000Z | /* This is the driver for c_ptr_test_7. */
extern void abort(void);
void *func0();
int main(int argc, char **argv)
{
/* The Fortran module c_ptr_tests_7 contains function func0, which has
return type of c_ptr, and should set the return value to c_null_ptr. */
if (func0() != 0)
abort();
return 0;
}
| 21.266667 | 77 | 0.667712 |
dfca18e6e9bb958fcc4303e0ec6b6375ece9b43d | 234 | h | C | WSD/WSD/ViewController/Me/Setting/UserInfoViewController.h | wyao1612/WSD_IOS | 258a4e7917f4f854a856f020f37e61fed2a812d0 | [
"MIT"
] | null | null | null | WSD/WSD/ViewController/Me/Setting/UserInfoViewController.h | wyao1612/WSD_IOS | 258a4e7917f4f854a856f020f37e61fed2a812d0 | [
"MIT"
] | null | null | null | WSD/WSD/ViewController/Me/Setting/UserInfoViewController.h | wyao1612/WSD_IOS | 258a4e7917f4f854a856f020f37e61fed2a812d0 | [
"MIT"
] | null | null | null | //
// UserInfoViewController.h
// GolfIOS
//
// Created by 李明星 on 2016/12/5.
// Copyright © 2016年 TSou. All rights reserved.
//
#import "STL_BaseViewController.h"
@interface UserInfoViewController : STL_BaseViewController
@end
| 16.714286 | 58 | 0.730769 |
cc0863506474561d687400c21be05260c6953530 | 5,507 | h | C | emulator/src/devices/video/huc6202.h | rjw57/tiw-computer | 5ef1c79893165b8622d1114d81cd0cded58910f0 | [
"MIT"
] | 1 | 2022-01-15T21:38:38.000Z | 2022-01-15T21:38:38.000Z | emulator/src/devices/video/huc6202.h | rjw57/tiw-computer | 5ef1c79893165b8622d1114d81cd0cded58910f0 | [
"MIT"
] | null | null | null | emulator/src/devices/video/huc6202.h | rjw57/tiw-computer | 5ef1c79893165b8622d1114d81cd0cded58910f0 | [
"MIT"
] | null | null | null | // license:BSD-3-Clause
// copyright-holders:Wilbert Pol
/**********************************************************************
Hudson/NEC HuC6202 interface
**********************************************************************/
#ifndef MAME_VIDEO_HUC6202_H
#define MAME_VIDEO_HUC6202_H
#pragma once
#define MCFG_HUC6202_NEXT_PIXEL_0_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_next_pixel_0_callback(DEVCB_##_devcb);
#define MCFG_HUC6202_TIME_TIL_NEXT_EVENT_0_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_time_til_next_event_0_callback(DEVCB_##_devcb);
#define MCFG_HUC6202_VSYNC_CHANGED_0_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_vsync_changed_0_callback(DEVCB_##_devcb);
#define MCFG_HUC6202_HSYNC_CHANGED_0_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_hsync_changed_0_callback(DEVCB_##_devcb);
#define MCFG_HUC6202_READ_0_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_read_0_callback(DEVCB_##_devcb);
#define MCFG_HUC6202_WRITE_0_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_write_0_callback(DEVCB_##_devcb);
#define MCFG_HUC6202_NEXT_PIXEL_1_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_next_pixel_1_callback(DEVCB_##_devcb);
#define MCFG_HUC6202_TIME_TIL_NEXT_EVENT_1_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_time_til_next_event_1_callback(DEVCB_##_devcb);
#define MCFG_HUC6202_VSYNC_CHANGED_1_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_vsync_changed_1_callback(DEVCB_##_devcb);
#define MCFG_HUC6202_HSYNC_CHANGED_1_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_hsync_changed_1_callback(DEVCB_##_devcb);
#define MCFG_HUC6202_READ_1_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_read_1_callback(DEVCB_##_devcb);
#define MCFG_HUC6202_WRITE_1_CB(_devcb) \
devcb = &downcast<huc6202_device &>(*device).set_write_1_callback(DEVCB_##_devcb);
class huc6202_device : public device_t
{
public:
// construction/destruction
huc6202_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
template <class Object> devcb_base &set_next_pixel_0_callback(Object &&cb) { return m_next_pixel_0_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_time_til_next_event_0_callback(Object &&cb) { return m_time_til_next_event_0_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_vsync_changed_0_callback(Object &&cb) { return m_vsync_changed_0_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_hsync_changed_0_callback(Object &&cb) { return m_hsync_changed_0_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_read_0_callback(Object &&cb) { return m_read_0_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_write_0_callback(Object &&cb) { return m_write_0_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_next_pixel_1_callback(Object &&cb) { return m_next_pixel_1_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_time_til_next_event_1_callback(Object &&cb) { return m_time_til_next_event_1_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_vsync_changed_1_callback(Object &&cb) { return m_vsync_changed_1_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_hsync_changed_1_callback(Object &&cb) { return m_hsync_changed_1_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_read_1_callback(Object &&cb) { return m_read_1_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_write_1_callback(Object &&cb) { return m_write_1_cb.set_callback(std::forward<Object>(cb)); }
DECLARE_READ8_MEMBER( read );
DECLARE_WRITE8_MEMBER( write );
DECLARE_READ8_MEMBER( io_read );
DECLARE_WRITE8_MEMBER( io_write );
DECLARE_READ16_MEMBER( next_pixel );
DECLARE_READ16_MEMBER( time_until_next_event );
DECLARE_WRITE_LINE_MEMBER( vsync_changed );
DECLARE_WRITE_LINE_MEMBER( hsync_changed );
protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
private:
/* callbacks */
/* First gfx input device */
devcb_read16 m_next_pixel_0_cb;
/* TODO: Choose proper types */
/* Callback function to get time until next event */
devcb_read16 m_time_til_next_event_0_cb;
devcb_write_line m_vsync_changed_0_cb;
devcb_write_line m_hsync_changed_0_cb;
devcb_read8 m_read_0_cb;
devcb_write8 m_write_0_cb;
/* Second gfx input device */
devcb_read16 m_next_pixel_1_cb;
/* TODO: Choose proper types */
/* Callback function to get time until next event */
devcb_read16 m_time_til_next_event_1_cb;
devcb_write_line m_vsync_changed_1_cb;
devcb_write_line m_hsync_changed_1_cb;
devcb_read8 m_read_1_cb;
devcb_write8 m_write_1_cb;
struct {
uint8_t prio_type;
uint8_t dev0_enabled;
uint8_t dev1_enabled;
} m_prio[4];
uint16_t m_window1;
uint16_t m_window2;
int m_io_device;
int m_map_index;
int m_map_dirty;
uint8_t m_prio_map[512];
};
DECLARE_DEVICE_TYPE(HUC6202, huc6202_device)
#endif // MAME_VIDEO_HUC6202_H
| 42.361538 | 162 | 0.74832 |
624e3bbc684289435a2d8ec389e3421fbc52959b | 584 | h | C | Demo-ObjC/BackgroundVideoDemo/BackgroundVideoObjC.h | Guzlan/BackgroundVideo-iOS | e9c99d331dac23969c77fe50be2cec36421a69fa | [
"MIT"
] | 613 | 2016-06-26T11:14:33.000Z | 2021-12-24T10:44:34.000Z | Demo-ObjC/BackgroundVideoDemo/BackgroundVideoObjC.h | Guzlan/BackgroundVideo-iOS | e9c99d331dac23969c77fe50be2cec36421a69fa | [
"MIT"
] | 5 | 2016-06-30T02:10:55.000Z | 2019-05-09T05:44:23.000Z | Demo-ObjC/BackgroundVideoDemo/BackgroundVideoObjC.h | Guzlan/BackgroundVideo-iOS | e9c99d331dac23969c77fe50be2cec36421a69fa | [
"MIT"
] | 65 | 2016-06-27T06:00:17.000Z | 2020-07-03T13:39:54.000Z | //
// BackgroundVideoObjC.h
// BackgroundVideoDemo
//
// Created by Adam Albarghouthi on 2016-06-26.
// Copyright © 2016 backgroundVideo. All rights reserved.
//
#import <Foundation/Foundation.h>
#import <AVKit/AVKit.h>
#import <AVFoundation/AVFoundation.h>
@interface BackgroundVideoObjC : NSObject {
NSURL *videoURL;
UIViewController *viewController;
}
@property (strong, nonatomic) AVPlayer *backgroundPlayer;
- (id)initOnViewController:(UIViewController *)onViewController withVideoURL:(NSString *)url;
- (void)setUpBackground;
- (void)pause;
- (void)play;
@end
| 21.62963 | 93 | 0.746575 |
d1444cbcbdbf3c7ee3e81c2f9607d83f3ab042a6 | 2,225 | h | C | AMS/PubSub/PubSub.h | aozturk/AMS | f2625244725695d7e1606fb536b1c7ee5520bb88 | [
"Apache-2.0"
] | 6 | 2015-01-11T23:03:11.000Z | 2021-09-06T08:00:48.000Z | AMS/PubSub/PubSub.h | aozturk/AMS | f2625244725695d7e1606fb536b1c7ee5520bb88 | [
"Apache-2.0"
] | null | null | null | AMS/PubSub/PubSub.h | aozturk/AMS | f2625244725695d7e1606fb536b1c7ee5520bb88 | [
"Apache-2.0"
] | 1 | 2020-07-15T08:22:54.000Z | 2020-07-15T08:22:54.000Z | #pragma once
#include "AMS/Net/Socket.h"
#include "AMS/Types.h"
#include "AMS/IService.h"
#include "AMS/Config/Configurator.h"
#include "AMS/Reactor/IHandler.h"
#include "AMS/PubSub/IPubSub.h"
namespace AMS {
template<typename T>
class PubSub : public IPubSub
{
public:
PubSub(Socket& socket)
: m_socket(socket) {
}
~PubSub(void) {
}
Socket& getSocket() {
return m_socket;
}
void subscribe();
void unsubscribe();
IMsgObj* receive_message(SingleMessage& message);
void send_message(IMsgObj& msg_obj);
private:
Socket& m_socket;
socket_type m_socktype;
};
template<typename T>
void PubSub<T>::subscribe() {
T obj;
int id = obj.getMessageObjectId();
std::ostringstream filter;
filter << id << "-";
m_socket.subscribeTopic(filter.str());
}
template<typename T>
void PubSub<T>::unsubscribe() {
T obj;
int id = obj.getMessageObjectId();
std::ostringstream filter;
filter << id << "-";
m_socket.unsubscribeTopic(filter.str());
}
template<typename T>
IMsgObj* PubSub<T>::receive_message(SingleMessage& message) {
msgpack::unpacked msg;
msgpack::unpack(&msg, ((char*)message.raw_data())+MSG_NAME_SIZE, message.size()-MSG_NAME_SIZE);
msgpack::object obj = msg.get();
// you can convert msg_obj to myclass directly
T* msg_obj = new T;
obj.convert(msg_obj);
return msg_obj;
}
template<typename T>
void PubSub<T>::send_message(IMsgObj& msg_obj) {
msgpack::sbuffer sbuf;
msgpack::pack(sbuf, dynamic_cast<T&>(msg_obj));
char msg_name [MSG_NAME_SIZE] = {0};
sprintf (msg_name, "%d-", msg_obj.getMessageObjectId());
int totsize = sbuf.size() + MSG_NAME_SIZE;
SingleMessage message(totsize);
memcpy((char*) message.raw_data(), msg_name, MSG_NAME_SIZE);
memcpy((char*) message.raw_data()+MSG_NAME_SIZE, sbuf.data(), sbuf.size());
// Send message to all subscribers
m_socket.send(message);
}
}
| 25.872093 | 103 | 0.589213 |
2fbc830497463c71eb6ea35d12cae168eb67a432 | 2,317 | h | C | src/phrase.h | danieldeutsch/thrax2 | 68c60bab9f12788e16750b15eba6be5ac9e7df36 | [
"MIT"
] | 3 | 2018-09-06T18:11:12.000Z | 2020-10-29T02:15:26.000Z | src/phrase.h | danieldeutsch/thrax2 | 68c60bab9f12788e16750b15eba6be5ac9e7df36 | [
"MIT"
] | 4 | 2018-06-21T15:31:12.000Z | 2018-06-21T17:38:56.000Z | src/phrase.h | danieldeutsch/thrax2 | 68c60bab9f12788e16750b15eba6be5ac9e7df36 | [
"MIT"
] | 5 | 2018-06-21T15:46:32.000Z | 2020-11-13T01:38:11.000Z | #pragma once
#include <algorithm>
#include <iostream>
#include <numeric>
#include <optional>
#include <vector>
#include "alignment.h"
namespace jhu::thrax {
using IndexType = int16_t;
using Indices = std::vector<IndexType>;
struct Span {
IndexType start = 0;
IndexType end = 0;
auto size() const {
return std::max(end - start, 0);
}
auto empty() const {
return start >= end;
}
auto indices() const {
Indices result(size());
std::iota(result.begin(), result.end(), start);
return result;
}
bool operator==(Span s) const {
return start == s.start && end == s.end;
}
bool operator!=(Span s) const {
return !(*this == s);
}
bool contains(Span s) const {
return s.start >= start && s.end <= end;
}
};
inline void removeIndices(Indices& from, Span s) {
auto b = std::lower_bound(from.begin(), from.end(), s.start);
auto e = std::lower_bound(from.begin(), from.end(), s.end);
if (b != from.end() && *b < s.start) {
b++;
}
from.erase(b, e);
}
constexpr bool disjoint(Span a, Span b) {
if (b.start < a.start) {
std::swap(a, b);
}
return b.start >= a.end;
}
struct SpanPair {
Span src, tgt;
auto empty() const {
return src.empty() || tgt.empty();
}
template<bool SourceSide> Span get() const {
if constexpr (SourceSide) {
return src;
} else {
return tgt;
}
}
bool operator==(SpanPair sp) const {
return src == sp.src && tgt == sp.tgt;
}
bool operator!=(SpanPair sp) const {
return !(*this == sp);
}
bool contains(SpanPair sp) const {
return src.contains(sp.src) && tgt.contains(sp.tgt);
}
};
constexpr bool disjoint(SpanPair a, SpanPair b) {
return disjoint(a.src, b.src) && disjoint(a.tgt, b.tgt);
}
inline std::ostream& operator<<(std::ostream& out, Span s) {
return out << '[' << s.start << ',' << s.end << ')';
}
inline std::ostream& operator<<(std::ostream& out, SpanPair sp) {
return out << sp.src << '+' << sp.tgt;
}
std::optional<Span> minimalTargetSpan(const Alignment& a, Span src);
bool isConsistent(const Alignment& a, SpanPair sp);
std::vector<SpanPair> minimalConsistentPairs(const Alignment& a, int maxSize);
struct AlignedSentencePair;
std::vector<SpanPair> allConsistentPairs(
const AlignedSentencePair& sentence, int maxSize);
}
| 20.873874 | 78 | 0.622788 |
f397a175a0a2acd28ff9584f916223c1df312d8c | 2,106 | h | C | src/util.h | jfajkowski/tableware-recognition | acfd5e0d85b52b0f807c6e209f20f2b1ede6cd77 | [
"MIT"
] | null | null | null | src/util.h | jfajkowski/tableware-recognition | acfd5e0d85b52b0f807c6e209f20f2b1ede6cd77 | [
"MIT"
] | null | null | null | src/util.h | jfajkowski/tableware-recognition | acfd5e0d85b52b0f807c6e209f20f2b1ede6cd77 | [
"MIT"
] | null | null | null | //
// Created by jfajkowski on 01.12.18.
//
#ifndef TABLEWARE_RECOGNITION_UTIL_H
#define TABLEWARE_RECOGNITION_UTIL_H
#include <opencv4/opencv2/opencv.hpp>
#include <vector>
#include <ostream>
using namespace cv;
double truncate(double value);
void bimshow(const String &winname, Mat &I);
void hishow(const String &winname, Mat &I, int hist_size = 256, float lo = 0, float hi = 256, bool uniform = true,
bool accumulate = false);
std::vector<Point> generatePoints(Mat &I, size_t size, bool grid);
class Vector {
private:
size_t _size;
std::vector<double> _data;
public:
Vector(const std::vector<double> &vector);
Vector(size_t size);
static double distance(const Vector &a, const Vector &b) {
double result = 0;
for (size_t i = 0; i < a._size; ++i) {
result += pow(a[i] - b[i], 2);
}
return sqrt(result);
}
std::vector<double> unwrap() const;
Vector normalize(double mean, double variance) const;
double mean() const;
double variance() const;
size_t argmax() const;
Vector operator+(const Vector &b) const;
Vector &operator+=(const Vector &b);
Vector operator/(const double &b) const;
Vector &operator/=(const double &b);
double &operator[](size_t i);
double operator[](size_t i) const;
bool operator==(const Vector &rhs) const;
friend std::ostream &operator<<(std::ostream &os, const Vector &row);
size_t size() const;
};
class Matrix {
private:
size_t _rows;
size_t _cols;
std::vector<double> _data;
public:
Matrix();
Matrix(size_t rows, size_t cols);
Matrix(const Matrix &matrix);
double &operator()(size_t i, size_t j);
double operator()(size_t i, size_t j) const;
Vector getRow(size_t n) const;
void addRow(Vector row);
int rowPosition(Vector row);
Vector getCol(size_t n) const;
void addCol(Vector col);
friend std::ostream &operator<<(std::ostream &os, const Matrix &matrix);
size_t rows() const;
size_t cols() const;
};
#endif //TABLEWARE_RECOGNITION_UTIL_H
| 20.057143 | 114 | 0.650047 |
faceeb63185634fa197e8a232aaa3b6eb5ff150d | 296 | h | C | Example/KKCocoaCommon_Example/KKGuideViewController.h | LeungKinKeung/KKCocoaCommon | 57a9d0e8b36cff204f6934fb35b1f72a1d5b75a9 | [
"MIT"
] | null | null | null | Example/KKCocoaCommon_Example/KKGuideViewController.h | LeungKinKeung/KKCocoaCommon | 57a9d0e8b36cff204f6934fb35b1f72a1d5b75a9 | [
"MIT"
] | null | null | null | Example/KKCocoaCommon_Example/KKGuideViewController.h | LeungKinKeung/KKCocoaCommon | 57a9d0e8b36cff204f6934fb35b1f72a1d5b75a9 | [
"MIT"
] | null | null | null | //
// KKGuideViewController.h
// KKCocoaCommon_Example
//
// Created by LeungKinKeung on 2020/12/15.
// Copyright © 2020 LeungKinKeung. All rights reserved.
//
#import <Cocoa/Cocoa.h>
NS_ASSUME_NONNULL_BEGIN
@interface KKGuideViewController : NSViewController
@end
NS_ASSUME_NONNULL_END
| 16.444444 | 56 | 0.77027 |
7aae4c5e4348045bd880e9ba058a7d2abcc358d7 | 1,033 | h | C | open-vm-tools/common-agent/Cpp/Framework/Framework/include/Doc/DocXml/CafCoreTypesXml/RequestInstanceParameterXml.h | mrehman29/open-vm-tools | 03f35e3209b3a73cf8e43a74ac764f22526723a0 | [
"X11"
] | 2 | 2020-07-23T06:01:37.000Z | 2021-02-25T06:48:42.000Z | open-vm-tools/common-agent/Cpp/Framework/Framework/include/Doc/DocXml/CafCoreTypesXml/RequestInstanceParameterXml.h | mrehman29/open-vm-tools | 03f35e3209b3a73cf8e43a74ac764f22526723a0 | [
"X11"
] | null | null | null | open-vm-tools/common-agent/Cpp/Framework/Framework/include/Doc/DocXml/CafCoreTypesXml/RequestInstanceParameterXml.h | mrehman29/open-vm-tools | 03f35e3209b3a73cf8e43a74ac764f22526723a0 | [
"X11"
] | 1 | 2020-11-11T12:54:06.000Z | 2020-11-11T12:54:06.000Z | /*
* Author: bwilliams
* Created: April 6, 2012
*
* Copyright (C) 2012-2016 VMware, Inc. All rights reserved. -- VMware Confidential
*
* This code was generated by the script "build/dev/codeGen/genCppXml". Please
* speak to Brian W. before modifying it by hand.
*
*/
#ifndef RequestInstanceParameterXml_h_
#define RequestInstanceParameterXml_h_
#include "Doc/CafCoreTypesDoc/CRequestInstanceParameterDoc.h"
#include "Doc/DocXml/CafCoreTypesXml/CafCoreTypesXmlLink.h"
#include "Xml/XmlUtils/CXmlElement.h"
namespace Caf {
/// Streams the RequestInstanceParameter class to/from XML
namespace RequestInstanceParameterXml {
/// Adds the RequestInstanceParameterDoc into the XML.
void CAFCORETYPESXML_LINKAGE add(
const SmartPtrCRequestInstanceParameterDoc requestInstanceParameterDoc,
const SmartPtrCXmlElement thisXml);
/// Parses the RequestInstanceParameterDoc from the XML.
SmartPtrCRequestInstanceParameterDoc CAFCORETYPESXML_LINKAGE parse(
const SmartPtrCXmlElement thisXml);
}
}
#endif
| 27.184211 | 85 | 0.787028 |
d8cadb58cd228d1681a02e2cd72db9084ba72fd0 | 199 | c | C | test_wcupa.c | tommyb603/xv6-public | 2a36725847eaa686990500a52cbc098c913867e0 | [
"MIT-0"
] | null | null | null | test_wcupa.c | tommyb603/xv6-public | 2a36725847eaa686990500a52cbc098c913867e0 | [
"MIT-0"
] | null | null | null | test_wcupa.c | tommyb603/xv6-public | 2a36725847eaa686990500a52cbc098c913867e0 | [
"MIT-0"
] | null | null | null | #include "types.h"
#include "stat.h"
#include "user.h"
int main(void) {
printf(1, "System calls: ", readc());
printf(1, "West Chester University as founded in %d\n", wcupa());
exit();
}
| 19.9 | 69 | 0.60804 |
4d7ee4848525b49fb7e8a2d77e0f7604206550a2 | 2,093 | h | C | projects/savefile/src/pse-savefile/expanded/player/playerpokedex.h | junebug12851/pokered-save-editor-2 | af883fd4c12097d408e1756c7181709cf2b797d8 | [
"Apache-2.0"
] | null | null | null | projects/savefile/src/pse-savefile/expanded/player/playerpokedex.h | junebug12851/pokered-save-editor-2 | af883fd4c12097d408e1756c7181709cf2b797d8 | [
"Apache-2.0"
] | null | null | null | projects/savefile/src/pse-savefile/expanded/player/playerpokedex.h | junebug12851/pokered-save-editor-2 | af883fd4c12097d408e1756c7181709cf2b797d8 | [
"Apache-2.0"
] | null | null | null | /*
* Copyright 2020 June Hanabi
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef PLAYERPOKEDEX_H
#define PLAYERPOKEDEX_H
#include <QObject>
#include <QVector>
#include <pse-common/types.h>
#include "../../savefile_autoport.h"
class SaveFile;
constexpr var8 maxPokedex = 151;
class SAVEFILE_AUTOPORT PlayerPokedex : public QObject
{
Q_OBJECT
Q_PROPERTY(int ownedCount READ ownedCount NOTIFY dexChanged STORED false)
Q_PROPERTY(int seenCount READ seenCount NOTIFY dexChanged STORED false)
public:
enum DexEntryState {
DexNone = 0,
DexSeen = 1,
DexOwned = 2
};
PlayerPokedex(SaveFile* saveFile = nullptr);
virtual ~PlayerPokedex();
void load(SaveFile* saveFile = nullptr);
void save(SaveFile* saveFile);
void loadPokedex(SaveFile* saveFile, QVector<bool>* toArr, var16 fromOffset);
void savePokedex(SaveFile* saveFile, QVector<bool>* fromArr, var16 toOffset);
int ownedCount();
int seenCount();
Q_INVOKABLE int ownedMax();
Q_INVOKABLE bool ownedAt(int ind);
Q_INVOKABLE void ownedSet(int ind, bool val);
Q_INVOKABLE int seenMax();
Q_INVOKABLE bool seenAt(int ind);
Q_INVOKABLE void seenSet(int ind, bool val);
Q_INVOKABLE int getState(int ind);
signals:
void dexChanged();
void dexItemChanged(int ind);
public slots:
void reset();
void randomize();
void toggleAll();
void toggleOne(int val);
void markAll(int val);
public:
bool owned[maxPokedex];
bool seen[maxPokedex];
};
#endif // PLAYERPOKEDEX_H
| 26.1625 | 80 | 0.703297 |
b11e023dc78f57049aece2e1a1008d248133cf18 | 352 | h | C | VierticalScrollView/VierticalScrollView/VierticalScrollView.h | Aaron0619/VierticalScrollView | 9c133f5e4b4dc7b6a1dead715a0f162fdf774d6a | [
"MIT"
] | 2 | 2018-02-24T07:58:27.000Z | 2018-04-19T05:25:36.000Z | VierticalScrollView/VierticalScrollView/VierticalScrollView.h | Aaron0619/VierticalScrollView | 9c133f5e4b4dc7b6a1dead715a0f162fdf774d6a | [
"MIT"
] | 1 | 2018-03-25T04:08:23.000Z | 2018-03-26T01:18:42.000Z | VierticalScrollView/VierticalScrollView/VierticalScrollView.h | Aaron0619/VierticalScrollView | 9c133f5e4b4dc7b6a1dead715a0f162fdf774d6a | [
"MIT"
] | null | null | null | //
// VierticalScrollView.h
// CommunityApp
//
// Created by AaronLee on 2017/10/12.
// Copyright © 2017年 com.ebeitech. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface VierticalScrollView : UIScrollView
-(instancetype)initWithFrame:(CGRect)frame;
-(void)setDataWithArray:(NSArray *)typeArray AndTitleArray:(NSArray *)titleArray;
@end
| 22 | 81 | 0.747159 |
7f56f84be745f9c11551183ce0b0627c443343fb | 1,762 | h | C | src/hash/sha512-224.h | lambdaconcept/libecc | 873837325b065ea55e45ed4fa70c31965d860e6e | [
"BSD-2-Clause"
] | 2 | 2022-03-08T07:56:28.000Z | 2022-03-08T08:16:06.000Z | src/hash/sha512-224.h | lambdaconcept/libecc | 873837325b065ea55e45ed4fa70c31965d860e6e | [
"BSD-2-Clause"
] | 7 | 2021-07-23T15:21:39.000Z | 2021-08-11T22:27:17.000Z | src/hash/sha512-224.h | lambdaconcept/libecc | 873837325b065ea55e45ed4fa70c31965d860e6e | [
"BSD-2-Clause"
] | 3 | 2021-03-15T14:44:18.000Z | 2022-03-09T02:56:14.000Z | /*
* Copyright (C) 2017 - This file is part of libecc project
*
* Authors:
* Ryad BENADJILA <ryadbenadjila@gmail.com>
* Arnaud EBALARD <arnaud.ebalard@ssi.gouv.fr>
* Jean-Pierre FLORI <jean-pierre.flori@ssi.gouv.fr>
*
* Contributors:
* Nicolas VIVET <nicolas.vivet@ssi.gouv.fr>
* Karim KHALFALLAH <karim.khalfallah@ssi.gouv.fr>
*
* This software is licensed under a dual BSD and GPL v2 license.
* See LICENSE file at the root folder of the project.
*/
#include "../lib_ecc_config.h"
#ifdef WITH_HASH_SHA512_224
#ifndef __SHA512_224_H__
#define __SHA512_224_H__
#include "../words/words.h"
#include "../utils/utils.h"
#include "sha2.h"
#include "sha512_core.h"
#define SHA512_224_STATE_SIZE SHA512_CORE_STATE_SIZE
#define SHA512_224_BLOCK_SIZE SHA512_CORE_BLOCK_SIZE
#define SHA512_224_DIGEST_SIZE 28
/* Compute max hash digest and block sizes */
#ifndef MAX_DIGEST_SIZE
#define MAX_DIGEST_SIZE 0
#endif
#if (MAX_DIGEST_SIZE < SHA512_224_DIGEST_SIZE)
#undef MAX_DIGEST_SIZE
#define MAX_DIGEST_SIZE SHA512_224_DIGEST_SIZE
#endif
#ifndef MAX_BLOCK_SIZE
#define MAX_BLOCK_SIZE 0
#endif
#if (MAX_BLOCK_SIZE < SHA512_224_BLOCK_SIZE)
#undef MAX_BLOCK_SIZE
#define MAX_BLOCK_SIZE SHA512_224_BLOCK_SIZE
#endif
typedef sha512_core_context sha512_224_context;
void sha512_224_init(sha512_224_context *ctx);
void sha512_224_update(sha512_224_context *ctx, const u8 *input, u32 ilen);
void sha512_224_final(sha512_224_context *ctx, u8 output[SHA512_224_DIGEST_SIZE]);
void sha512_224_scattered(const u8 **inputs, const u32 *ilens,
u8 output[SHA512_224_DIGEST_SIZE]);
void sha512_224(const u8 *input, u32 ilen, u8 output[SHA512_224_DIGEST_SIZE]);
#endif /* __SHA512_224_H__ */
#endif /* WITH_HASH_SHA512_224 */
| 29.864407 | 82 | 0.77185 |
366c1c7ef9ef539a9ac27469c910cea0ef1c37fe | 875 | h | C | UI/Enemy/HpSystem/SC_WidgetEnemyHp.h | Bornsoul/Revenger_JoyContinue | 599716970ca87a493bf3a959b36de0b330b318f1 | [
"MIT"
] | null | null | null | UI/Enemy/HpSystem/SC_WidgetEnemyHp.h | Bornsoul/Revenger_JoyContinue | 599716970ca87a493bf3a959b36de0b330b318f1 | [
"MIT"
] | null | null | null | UI/Enemy/HpSystem/SC_WidgetEnemyHp.h | Bornsoul/Revenger_JoyContinue | 599716970ca87a493bf3a959b36de0b330b318f1 | [
"MIT"
] | null | null | null | // Fill out your copyright notice in the Description page of Project Settings.
#pragma once
#include "Revenger.h"
#include "Components/SceneComponent.h"
#include "SC_WidgetEnemyHp.generated.h"
UCLASS(ClassGroup = (Custom), meta = (BlueprintSpawnableComponent))
class REVENGER_API USC_WidgetEnemyHp : public USceneComponent
{
GENERATED_BODY()
private:
UPROPERTY(EditAnywhere)
class UBoxComponent* m_pBox;
UPROPERTY(EditAnywhere)
TArray<class UWidgetComp_EnemyHp*> m_pEnemyHp;
UPROPERTY()
class UWidgetComp_EnemyHp* m_pEnemy;
UPROPERTY(EditAnywhere, Category = HpBar)
FVector2D m_vHpPos = FVector2D(30.0f, 250.0f);
bool m_bActive = false;
int nCnt = 0;
public:
USC_WidgetEnemyHp();
public:
virtual void BeginPlay() override;
void SetInit(int nCnt);
void Tick_Transform(FVector vLocation, float fDeltaTime);
void SetHit();
void SetDestroy();
};
| 20.833333 | 78 | 0.769143 |
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