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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
9ef50888c0420fa5033844a78bd3bbbdfcbb2444 | 418 | c | C | miscCode/NumWords.c | jcode94/CS1-study | c063b706aa1972b5af3460250e9b5ae29251608d | [
"MIT"
] | null | null | null | miscCode/NumWords.c | jcode94/CS1-study | c063b706aa1972b5af3460250e9b5ae29251608d | [
"MIT"
] | null | null | null | miscCode/NumWords.c | jcode94/CS1-study | c063b706aa1972b5af3460250e9b5ae29251608d | [
"MIT"
] | null | null | null | // Justice Smith 1/2021
// Basic word counter implementation
#include <stdio.h>
void NumOfWords(char *s, int *);
int main() {
char str[] = "Hello how are you";
int res = 1;
NumOfWords(str, &res);
printf("Result is: %d\n", res);
return 0;
}
void NumOfWords(char *s, int *r) {
int i = 0;
while (s[i] != '\0') {
if(s[i] == ' ') {
*r += 1;
}
i++;
}
} | 17.416667 | 37 | 0.483254 |
fa192dd501d368d74fa5e3d0e0af5d15632301cf | 5,061 | h | C | NativePatcher_cef_binary_3.3163.1671.win32/BridgeBuilder/dev_snap/tests/cefclient/browser/root_window_win.h | prepare/kn_patches | f6566c8f06c92d965a453d1f8de23d6d003cd71f | [
"MIT"
] | 4 | 2017-08-29T02:24:04.000Z | 2019-02-26T09:44:36.000Z | NativePatcher_cef_binary_3.3163.1671.win32/BridgeBuilder/dev_snap/tests/cefclient/browser/root_window_win.h | prepare/kn_patches | f6566c8f06c92d965a453d1f8de23d6d003cd71f | [
"MIT"
] | 15 | 2017-08-31T22:07:48.000Z | 2019-03-22T05:09:28.000Z | NativePatcher_cef_binary_3.3163.1671.win32/BridgeBuilder/dev_snap/tests/cefclient/browser/root_window_win.h | prepare/kn_patches | f6566c8f06c92d965a453d1f8de23d6d003cd71f | [
"MIT"
] | 3 | 2017-10-10T03:42:10.000Z | 2019-02-26T09:44:38.000Z | //###_ORIGINAL D:\projects\cef_binary_3.3163.1671.win32\tests\cefclient\browser//root_window_win.h
// Copyright (c) 2015 The Chromium Embedded Framework Authors. All rights
// reserved. Use of this source code is governed by a BSD-style license that
// can be found in the LICENSE file.
#ifndef CEF_TESTS_CEFCLIENT_BROWSER_ROOT_WINDOW_WIN_H_
#define CEF_TESTS_CEFCLIENT_BROWSER_ROOT_WINDOW_WIN_H_
#pragma once
#include <windows.h>
#include <commdlg.h>
#include <string>
#include "include/base/cef_scoped_ptr.h"
#include "tests/cefclient/browser/browser_window.h"
#include "tests/cefclient/browser/root_window.h"
namespace client {
//###_BEGIN
#include "tests/cefclient/myext/mycef_buildconfig.h"
#if BUILD_TEST_ROOT_WINDOW
//###_END
// Windows implementation of a top-level native window in the browser process.
// The methods of this class must be called on the main thread unless otherwise
// indicated.
class RootWindowWin : public RootWindow, public BrowserWindow::Delegate {
public:
// Constructor may be called on any thread.
RootWindowWin();
~RootWindowWin();
// RootWindow methods.
void Init(RootWindow::Delegate* delegate,
bool with_controls,
bool with_osr,
const CefRect& rect,
const CefBrowserSettings& settings,
const std::string& url) OVERRIDE;
void InitAsPopup(RootWindow::Delegate* delegate,
bool with_controls,
bool with_osr,
const CefPopupFeatures& popupFeatures,
CefWindowInfo& windowInfo,
CefRefPtr<CefClient>& client,
CefBrowserSettings& settings) OVERRIDE;
void Show(ShowMode mode) OVERRIDE;
void Hide() OVERRIDE;
void SetBounds(int x, int y, size_t width, size_t height) OVERRIDE;
void Close(bool force) OVERRIDE;
void SetDeviceScaleFactor(float device_scale_factor) OVERRIDE;
float GetDeviceScaleFactor() const OVERRIDE;
CefRefPtr<CefBrowser> GetBrowser() const OVERRIDE;
ClientWindowHandle GetWindowHandle() const OVERRIDE;
private:
void CreateBrowserWindow(const std::string& startup_url);
void CreateRootWindow(const CefBrowserSettings& settings);
// Register the root window class.
static void RegisterRootClass(HINSTANCE hInstance,
const std::wstring& window_class,
HBRUSH background_brush);
// Window procedure for the edit field.
static LRESULT CALLBACK EditWndProc(HWND hWnd,
UINT message,
WPARAM wParam,
LPARAM lParam);
// Window procedure for the find dialog.
static LRESULT CALLBACK FindWndProc(HWND hWnd,
UINT message,
WPARAM wParam,
LPARAM lParam);
// Window procedure for the root window.
static LRESULT CALLBACK RootWndProc(HWND hWnd,
UINT message,
WPARAM wParam,
LPARAM lParam);
// Event handlers.
void OnPaint();
void OnFocus();
void OnSize(bool minimized);
void OnMove();
bool OnEraseBkgnd();
bool OnCommand(UINT id);
void OnFind();
void OnFindEvent();
void OnAbout();
bool OnClose();
void OnDestroyed();
// BrowserWindow::Delegate methods.
void OnBrowserCreated(CefRefPtr<CefBrowser> browser) OVERRIDE;
void OnBrowserWindowDestroyed() OVERRIDE;
void OnSetAddress(const std::string& url) OVERRIDE;
void OnSetTitle(const std::string& title) OVERRIDE;
void OnSetFullscreen(bool fullscreen) OVERRIDE;
void OnSetLoadingState(bool isLoading,
bool canGoBack,
bool canGoForward) OVERRIDE;
void OnSetDraggableRegions(
const std::vector<CefDraggableRegion>& regions) OVERRIDE;
void NotifyDestroyedIfDone();
// After initialization all members are only accessed on the main thread.
// Members set during initialization.
RootWindow::Delegate* delegate_;
bool with_controls_;
bool with_osr_;
bool is_popup_;
RECT start_rect_;
scoped_ptr<BrowserWindow> browser_window_;
bool initialized_;
// Main window.
HWND hwnd_;
// Draggable region.
HRGN draggable_region_;
// Font for buttons and text fields.
HFONT font_;
// Buttons.
HWND back_hwnd_;
HWND forward_hwnd_;
HWND reload_hwnd_;
HWND stop_hwnd_;
// URL text field.
HWND edit_hwnd_;
WNDPROC edit_wndproc_old_;
// Find dialog.
HWND find_hwnd_;
UINT find_message_id_;
WNDPROC find_wndproc_old_;
// Find dialog state.
FINDREPLACE find_state_;
WCHAR find_buff_[80];
std::wstring find_what_last_;
bool find_next_;
bool find_match_case_last_;
bool window_destroyed_;
bool browser_destroyed_;
DISALLOW_COPY_AND_ASSIGN(RootWindowWin);
};
//###_BEGIN
#endif //BUILD_TEST
//###_END
} // namespace client
#endif // CEF_TESTS_CEFCLIENT_BROWSER_ROOT_WINDOW_WIN_H_
| 30.305389 | 98 | 0.672594 |
d0ee3831a8cd9d01e422ccdd74e2ddc65e826194 | 1,052 | h | C | DS3231/DS3231/DS3231.h | dataronio/STM32-Libraries | af7c01bdb55b5b7ec0043886f2e1299259d09fdf | [
"MIT"
] | 26 | 2019-11-13T20:28:32.000Z | 2022-03-24T01:35:22.000Z | DS3231/DS3231/DS3231.h | dataronio/STM32-Libraries | af7c01bdb55b5b7ec0043886f2e1299259d09fdf | [
"MIT"
] | null | null | null | DS3231/DS3231/DS3231.h | dataronio/STM32-Libraries | af7c01bdb55b5b7ec0043886f2e1299259d09fdf | [
"MIT"
] | 7 | 2020-03-21T10:27:10.000Z | 2022-03-13T11:30:51.000Z | /*
* DS3231.h
*
* Created on: 6 mars 2020
* Author: Daniel Mårtensson
*/
#ifndef SRC_DS3231_DS3231_H_
#define SRC_DS3231_DS3231_H_
#include "main.h"
#include "stdbool.h"
typedef struct {
uint8_t addr; /* Address of the RTC */
I2C_HandleTypeDef *hi2c; /* Handler for the I2C */
uint8_t second;
uint8_t minute;
uint8_t hour;
uint8_t day;
uint8_t date;
uint8_t month;
uint8_t year;
}DS3231_I2C;
void DS3231_init(DS3231_I2C* i2c, I2C_HandleTypeDef* hi2c, uint8_t addr,uint8_t enableWeekAlarm, uint8_t enableDateAlarm);
void DS3231_setClock(DS3231_I2C* i2c, uint8_t seconds, uint8_t minutes, uint8_t hours, uint8_t days, uint8_t dates, uint8_t months, uint8_t years);
void DS3231_getClock(DS3231_I2C* i2c);
void DS3231_setDateAlarm(DS3231_I2C* i2c, uint8_t seconds, uint8_t minutes, uint8_t hours, uint8_t dates);
void DS3231_setWeekAlarm(DS3231_I2C* i2c, uint8_t minutes, uint8_t hours, uint8_t days);
void DS3231_offTriggAlarm(DS3231_I2C* i2c);
uint8_t DS3231_readALarmStatus(DS3231_I2C* i2c);
#endif /* SRC_DS3231_DS3231_H_ */
| 30.057143 | 147 | 0.773764 |
4a423a405a876f403b33f34721f4f996b7db29ae | 25 | h | C | src/tictactoe/logic.h | lonely-code-cube/tic-tac-toe-os | a4827f69dbc707ba863a0ae42aca4dd630457ec2 | [
"BSD-3-Clause"
] | 1 | 2022-02-28T16:15:51.000Z | 2022-02-28T16:15:51.000Z | src/tictactoe/logic.h | lonely-code-cube/tic-tac-toe-os | a4827f69dbc707ba863a0ae42aca4dd630457ec2 | [
"BSD-3-Clause"
] | null | null | null | src/tictactoe/logic.h | lonely-code-cube/tic-tac-toe-os | a4827f69dbc707ba863a0ae42aca4dd630457ec2 | [
"BSD-3-Clause"
] | null | null | null | int verify(int filled[]); | 25 | 25 | 0.72 |
0bbfcb7f3f50b4f2df83bbd6ed30d61b2727255e | 460 | h | C | example/GsQueryTest/CMap.h | yulei880831/gskernel | 955385165a79f3be2d0ec06bf2d9099071fa8c74 | [
"Apache-2.0"
] | null | null | null | example/GsQueryTest/CMap.h | yulei880831/gskernel | 955385165a79f3be2d0ec06bf2d9099071fa8c74 | [
"Apache-2.0"
] | null | null | null | example/GsQueryTest/CMap.h | yulei880831/gskernel | 955385165a79f3be2d0ec06bf2d9099071fa8c74 | [
"Apache-2.0"
] | null | null | null | #ifndef MAPVIEW_H
#define MAPVIEW_H
#include <QDockWidget>
#include "geospace2d.h"
#include "queryresult.h"
using namespace GeoStar::Kernel::QT;
using namespace GeoStar::Kernel;
class MapView: public QDockWidget
{
Q_OBJECT
public:
MapView(const QString &config, const QString &title, QWidget *parent = 0);
~MapView();
GsGeoSpace2D* m_GeoSpace2D;
QueryResult m_QueryResult;
private slots:
void QueryByGeometry(GsGeometry* geo);
};
#endif // MAPVIEW_H
| 19.166667 | 75 | 0.767391 |
2e0b6816d353e7cf6d840ed9627f474da17ceccd | 1,587 | c | C | flecs-components-physics/src/physics.c | tang1024/vflecs | 7d438aa18d207193eb4ad2aefabe2c95cb3d3a4d | [
"MIT"
] | null | null | null | flecs-components-physics/src/physics.c | tang1024/vflecs | 7d438aa18d207193eb4ad2aefabe2c95cb3d3a4d | [
"MIT"
] | null | null | null | flecs-components-physics/src/physics.c | tang1024/vflecs | 7d438aa18d207193eb4ad2aefabe2c95cb3d3a4d | [
"MIT"
] | null | null | null | #include <flecs_components_physics.h>
#include <string.h>
void FlecsComponentsPhysicsImport(
ecs_world_t *world,
int flags)
{
bool do_2d = !flags || flags & ECS_2D;
bool do_3d = !flags || flags & ECS_3D;
ECS_MODULE(world, FlecsComponentsPhysics);
if (do_2d) {
ECS_TAG(world, EcsCollider);
ECS_TAG(world, EcsRigidBody);
ECS_COMPONENT(world, EcsPolygon8Collider);
ECS_COMPONENT(world, EcsCircleCollider);
ECS_COMPONENT(world, EcsCollision2D);
ECS_COMPONENT(world, EcsPolygon8ColliderWorld);
ECS_COMPONENT(world, EcsCircleColliderWorld);
ECS_COMPONENT(world, EcsVelocity2D);
ECS_COMPONENT(world, EcsSpeed);
ECS_COMPONENT(world, EcsAngularSpeed);
ECS_COMPONENT(world, EcsBounciness);
ECS_COMPONENT(world, EcsFriction);
ECS_SET_ENTITY(EcsCollider);
ECS_SET_ENTITY(EcsRigidBody);
ECS_SET_COMPONENT(EcsCollision2D);
ECS_SET_COMPONENT(EcsPolygon8Collider);
ECS_SET_COMPONENT(EcsCircleCollider);
ECS_SET_COMPONENT(EcsPolygon8ColliderWorld);
ECS_SET_COMPONENT(EcsCircleColliderWorld);
ECS_SET_COMPONENT(EcsVelocity2D);
ECS_SET_COMPONENT(EcsSpeed);
ECS_SET_COMPONENT(EcsAngularSpeed);
ECS_SET_COMPONENT(EcsBounciness);
ECS_SET_COMPONENT(EcsFriction);
}
if (do_3d) {
ECS_COMPONENT(world, EcsVelocity3D);
ECS_COMPONENT(world, EcsAngularVelocity);
ECS_SET_COMPONENT(EcsVelocity3D);
ECS_SET_COMPONENT(EcsAngularVelocity);
}
}
| 31.74 | 55 | 0.689981 |
6d2c3bc76ba86e178505c51390c09898986a589f | 7,664 | h | C | Tools/ExpressionEvaluator/Src/EEFloatX.h | L-Spiro/MhsX | 9cc71fbbac93ba54a01839db129cd9b47a68f29e | [
"BSD-2-Clause"
] | 19 | 2016-09-07T18:22:09.000Z | 2022-03-25T23:05:39.000Z | Tools/ExpressionEvaluator/Src/EEFloatX.h | L-Spiro/MhsX | 9cc71fbbac93ba54a01839db129cd9b47a68f29e | [
"BSD-2-Clause"
] | 1 | 2021-09-30T14:24:54.000Z | 2021-11-13T14:58:02.000Z | Tools/ExpressionEvaluator/Src/EEFloatX.h | L-Spiro/MhsX | 9cc71fbbac93ba54a01839db129cd9b47a68f29e | [
"BSD-2-Clause"
] | 5 | 2018-04-10T16:52:25.000Z | 2021-05-11T02:40:17.000Z | #pragma once
#include <cfloat>
#include <cmath>
#include <cstdint>
#define EE_FLOATX_DBL_EXP_BITS 11
#define EE_FLOATX_DBL_MAN_BITS DBL_MANT_DIG
#define EE_FLOATX_FLT_EXP_BITS 8
#define EE_FLOATX_FLT_MAN_BITS FLT_MANT_DIG
#define EE_FLOAT16_EPSILON 0.0009765625f
namespace ee {
// A floating-point value with any number of bits, separated into a sign bit, X exponent bits, and Y mantissa bits.
class CFloatX {
public :
CFloatX() :
uiExponent( 0 ),
uiMantissa( 0 ),
uiManBits( 0 ),
uiExpBits( 0 ),
bSign( false ),
bImplicitManBit( true ) {
}
uint64_t uiExponent;
uint64_t uiMantissa;
uint16_t uiExpBits;
uint16_t uiManBits;
bool bSign;
bool bImplicitManBit;
bool bHasSign;
// == Functions.
// Creates a +InF value.
CFloatX & CreateInfP( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit, bool _bHasSign );
// Creates a -InF value.
CFloatX & CreateInfN( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit, bool _bHasSign );
// Creates a NaN value.
CFloatX & CreateNaN( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit, bool _bHasSign );
// Creates a max value.
CFloatX & CreateMax( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit, bool _bHasSign );
// Creates the smallest normalized value.
CFloatX & CreateMinNormalized( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit, bool _bHasSign );
// Creates the smallest non-0 value.
CFloatX & CreateMin( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit, bool _bHasSign );
// Creates epsilon, the smallest value such that 1.0+X does not equal 1.
CFloatX & CreateEpsilon( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit, bool _bHasSign );
// Creates the next-after value going up from the given number.
CFloatX & CreateNextAfterUp( double _dVal, uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit, bool _bHasSign );
// Creates the next-after value going down from the given number.
CFloatX & CreateNextAfterDown( double _dVal, uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit, bool _bHasSign );
// Is this a NaN?
bool IsNaN() const;
// Is this +InF?
bool IsInfP() const;
// Is this -InF?
bool IsInfN() const;
// Create from a double.
CFloatX & CreateFromDouble( double _dVal, uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit = true, bool _bHasSign = true );
// Create from bits in a uint64_t value.
CFloatX & CreateFromBits( uint64_t _uiVal, uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit = true, bool _bHasSign = true );
// Create from separate values.
CFloatX & CreateFromParts( uint64_t _uiSign, uint64_t _uiExp, uint64_t _uiMan,
uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit = true, bool _bHasSign = true );
// Cast to double.
double AsDouble() const;
// Put all the bits together into a uint64_t value.
uint64_t AsUint64() const;
// Gets the exponent with all bits set.
uint64_t AllExpBitsSet() const { return AllExpBitsSet( uiExpBits ); }
// Put all the bits together into a uint64_t value except for the sign value.
uint64_t AsUint64SansSign() const;
// Gets the exponent bias.
double ExpBias() const { return ExpBias( uiExpBits ); }
// Gets the denormalized exponent bias.
double DenormalExpBias() const { return ExpBias() - 1; }
// Determines if the type is denormalized or not.
bool IsDenormalized() const { return uiExponent == 0; }
// Gets a sign multiplier.
double Sign() const { return ((bHasSign && bSign) ? -1.0 : 1.0); }
// Gets the sign bit shifted.
uint64_t SignBit() const { return ((bHasSign && bSign) ? 1 : 0); }
// Gets the exponent bits shifted.
uint64_t ExpBits() const { return uiExponent & ((1ULL << uiExpBits) - 1ULL); }
// Gets the mantissa bits shifted.
uint64_t ManBits() const { return uiMantissa & ((1ULL << RealMantissaBits( uiManBits, bImplicitManBit )) - 1ULL); }
// Sets the sign bit, if applicable.
CFloatX & SetSign( bool _bEnabled );
// Sets or unsets a bit in the exponent.
CFloatX & SetExpBit( bool _bEnabled, uint16_t _uiBit );
// Sets or unsets a bit in the mantissa.
CFloatX & SetManBit( bool _bEnabled, uint16_t _uiBit );
// Gets the maximum possible value for a float type with the given bits.
static double GetMaxForBits( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit );
// Gets the smallest possible non-0 value for a float type with the given bits.
static double GetMinForBits( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit );
// Gets the smallest normalized non-0 value for a float type with the given bits.
static double GetNormalizedMinForBits( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit );
// Gets the maximum denormalized value for a float type with the given bits.
static double GetDenormalizedMaxForBits( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit );
// Gets an exponent with all bits set.
static uint64_t AllExpBitsSet( uint16_t _uiExpBits ) { return (1 << _uiExpBits) - 1; }
// Gets the exponent bias.
static const double ExpBias( uint16_t _uiExpBits ) { return (1 << (_uiExpBits - 1)) - 1; }
// Gets the maximum normalized exponent bias for a given number of bits.
static const double MaxExpBias( uint16_t _uiExpBits ) { return (1 << (_uiExpBits - 1)) - 1; }
// Gets the minimum normalized exponent bias for a given number of bits.
static const double MinExpBias( uint16_t _uiExpBits ) { return (1 << (_uiExpBits - 1)) - 1; }
// Gets the maximum number of bits in a sign.
static const uint32_t MaxSignBits() { return 1; }
// Gets the maximum number of bits in an exponent.
static const uint32_t MaxExpBits() { return 11; }
// Gets the maximum number of bits in a mantissa.
static const uint32_t MaxManBits() { return EE_FLOATX_DBL_MAN_BITS; }
// Gets the real number of mantissa bits based on whether or not there is an implicit bit.
static const uint64_t RealMantissaBits( uint16_t _uiManBits, bool _bImplicitMantissaBit ) { return _bImplicitMantissaBit ? _uiManBits - 1 : _uiManBits; }
// Gets the sign bit from a double (not shifted).
static uint64_t SignBit( double _dVal ) { return (*reinterpret_cast<uint64_t *>(&_dVal)) & (1ULL << 63ULL); }
// Gets the exponent from a double (not shifted).
static uint64_t ExpBits( double _dVal ) { return (*reinterpret_cast<uint64_t *>(&_dVal)) & (((1ULL << 11ULL) - 1ULL) << (EE_FLOATX_DBL_MAN_BITS - 1ULL)); }
// Gets the mantissa from a double (not shifted).
static uint64_t ManBits( double _dVal ) { return (*reinterpret_cast<uint64_t *>(&_dVal)) & (((1ULL << (EE_FLOATX_DBL_MAN_BITS - 2ULL)) - 1ULL)); }
// Gets the number of bits in a given representation.
static uint64_t TotalBits( uint16_t _uiExpBits, uint16_t _uiManBits, bool _bImplicitMantissaBit, bool _bHasSign ) {
return (_uiExpBits + _uiManBits) + (_bHasSign ? 1 : 0) - (_bImplicitMantissaBit ? 1 : 0);
}
// Gets the precision given the number of mantissa bits for numbers greater than 1.
static double Precision( uint16_t _uiManBits ) {
return _uiManBits > 1 ? std::log10( std::pow( 2.0, _uiManBits ) ) :
(std::log10( _uiManBits ) + 1.0);
}
};
} // namespace ee | 42.342541 | 161 | 0.704854 |
28974f84dff496fcc55a284b5b19bbe881eaf3bc | 2,098 | c | C | src/region3/region3vpsa.c | mgorny/libh2o | 016786307cc3735ff08b3e9333244b2d9ca448bd | [
"BSD-2-Clause"
] | 3 | 2019-07-10T09:56:10.000Z | 2020-09-28T04:53:12.000Z | src/region3/region3vpsa.c | mgorny/libh2o | 016786307cc3735ff08b3e9333244b2d9ca448bd | [
"BSD-2-Clause"
] | null | null | null | src/region3/region3vpsa.c | mgorny/libh2o | 016786307cc3735ff08b3e9333244b2d9ca448bd | [
"BSD-2-Clause"
] | null | null | null | /* libh2o -- steam & water properties
* (c) 2012 Michał Górny
* Released under the terms of the 2-clause BSD license
*/
#ifdef HAVE_CONFIG_H
# include "config.h"
#endif
#include "region3.h"
#include "xmath.h"
/* Revised Supplementary Release on Backward Equations for the Functions
* T(p,h), v(p,h) and T(p,s), v(p,s) for Region 3 of the IAPWS Industrial
* Formulation 1997 for the Thermodynamic Properties of Water and Steam
* s. 3.4: Backward Equations T(p,s) and v(p,s) for Subregions 3a and 3b */
/* coefficient table; n[0] added for convenience */
static const double n[] = {
+0.000000000000000E+00,
+0.795544074093975E+02, -0.238261242984590E+04,
+0.176813100617787E+05, -0.110524727080379E-02,
-0.153213833655326E+02, +0.297544599376982E+03,
-0.350315206871242E+08, +0.277513761062119E+00,
-0.523964271036888E+00, -0.148011182995403E+06,
+0.160014899374266E+07, +0.170802322663427E+13,
+0.246866996006494E-03, +0.165326084797980E+01,
-0.118008384666987E+00, +0.253798642355900E+01,
+0.965127704669424E+00, -0.282172420532826E+02,
+0.203224612353823E+00, +0.110648186063513E+01,
+0.526127948451280E+00, +0.277000018736321E+00,
+0.108153340501132E+01, -0.744127885357893E-01,
+0.164094443541384E-01, -0.680468275301065E-01,
+0.257988576101640E-01, -0.145749861944416E-03
};
static const double Ipows[] = {
-12, -10, -8, -6, -5, -4, -3, -2, -1, 0, 1, 2, 4, 5, 6
};
static const int I[] = {
0,
0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2,
3, 4, 5, 6, 6, 7, 7, 8, 8,
9, 9, 9, 10, 11, 12, 13, 14
};
static const double Jpows[] = {
0, 1, 2, 3, 4, 5, 6, 8, 10, 12, 14, 16, 20, 28
};
static const int J[] = {
0,
8, 9, 10, 4, 7, 8, 12, 5, 6, 10, 11,
13, 1, 5, 2, 4, 3, 7, 1, 2,
0, 1, 3, 0, 0, 2, 2, 0
};
static const double vstar = 0.0028; /* [m³/kg] */
static const double pstar = 100; /* [MPa] */
static const double sstar = 4.4; /* [kJ/kgK] */
double h2o_region3a_v_ps(double p, double s)
{
double pi = p / pstar;
double sigma = s / sstar;
return twoarg_poly_value(pi + 0.187, sigma - 0.755,
I, Ipows, 9, 15, 0,
J, Jpows, 0, 14, 0,
n, 28) * vstar;
}
| 26.556962 | 75 | 0.65348 |
2f19b29bcefbfad0fc480713c079106e026f6a29 | 31,284 | h | C | src/drivers/rf/nfc/pn532/helpers/pn532_ndef.h | bitsoftwang/LPC11U_LPC13U_CodeBase | a0e1a75bfb9865225b0d9f66c9eb7e4945ebea9f | [
"BSD-3-Clause"
] | 30 | 2015-01-11T04:18:50.000Z | 2019-09-22T17:26:51.000Z | src/drivers/rf/nfc/pn532/helpers/pn532_ndef.h | ADTL/LPC11U_LPC13U_CodeBase | 1e366fb390f1af3e087495b88f574b69b62e86c4 | [
"BSD-3-Clause"
] | null | null | null | src/drivers/rf/nfc/pn532/helpers/pn532_ndef.h | ADTL/LPC11U_LPC13U_CodeBase | 1e366fb390f1af3e087495b88f574b69b62e86c4 | [
"BSD-3-Clause"
] | 25 | 2015-01-11T04:17:41.000Z | 2021-04-03T14:29:10.000Z | /**************************************************************************/
/*!
@file pn532_ndef.h
@section LICENSE
Software License Agreement (BSD License)
Copyright (c) 2013 Adafruit Industries (www.adafruit.com)
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holders nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************/
#ifndef __PN532_NDEF_H__
#define __PN532_NDEF_H__
#include "projectconfig.h"
#include "../pn532.h"
/**************************************************************************/
/*!
Indicates no type, id, or payload is associated with this NDEF Record.
Type, id and payload fields must all be empty to be a valid
NDEF_TNF_EMPTY record.
*/
/**************************************************************************/
#define NDEF_TNF_EMPTY (0x00)
/**************************************************************************/
/*!
Indicates the type field uses the RTD type name format.
Use this TNF with RTD types such as NDEF_RTD_TEXT, NDEF_RTD_URI.
*/
/**************************************************************************/
#define NDEF_TNF_WELL_KNOWN (0x01)
/**************************************************************************/
/*!
Indicates the type field contains a value that follows the media-type
BNF construct defined by RFC 2046.
*/
/**************************************************************************/
#define NDEF_TNF_MIME_MEDIA (0x02)
/**************************************************************************/
/*!
Indicates the type field contains a value that follows the absolute-URI
BNF construct defined by RFC 3986.
*/
/**************************************************************************/
#define NDEF_TNF_ABSOLUTE_URI (0x03)
/**************************************************************************/
/*!
Indicates the type field contains a value that follows the RTD external
name specification.
Note this TNF should not be used with NDEF_RTD_TEXT or NDEF_RTD_URI
constants. Those are well known RTD constants, not external RTD
constants.
*/
/**************************************************************************/
#define NDEF_TNF_EXTERNAL_TYPE (0x04)
/**************************************************************************/
/*!
Indicates the payload type is unknown.
This is similar to the "application/octet-stream" MIME type. The
payload type is not explicitly encoded within the NDEF Message.
The type field must be empty to be a valid NDEF_TNF_UNKNOWN record.
*/
/**************************************************************************/
#define NDEF_TNF_UNKNOWN (0x05)
/**************************************************************************/
/*!
Indicates the payload is an intermediate or final chunk of a chunked
NDEF Record.
The payload type is specified in the first chunk, and subsequent chunks
must use NDEF_TNF_UNCHANGED with an empty type field.
NDEF_TNF_UNCHANGED must not be used in any other situation.
*/
/**************************************************************************/
#define NDEF_TNF_UNCHANGED (0x06)
/**************************************************************************/
/*!
Reserved TNF type.
The NFC Forum NDEF Specification v1.0 suggests for NDEF parsers to
treat this value like NDEF_TNF_UNKNOWN.
@hide
*/
/**************************************************************************/
#define NDEF_TNF_RESERVED (0x07)
/**************************************************************************/
/*!
RTD Text type. For use with NDEF_TNF_WELL_KNOWN.
*/
/**************************************************************************/
#define NDEF_RTD_TEXT ("T")
/**************************************************************************/
/*!
RTD URI type. For use with NDEF_TNF_WELL_KNOWN.
*/
/**************************************************************************/
#define NDEF_RTD_URI ("U")
/**************************************************************************/
/*!
RTD Smart Poster type. For use with NDEF_TNF_WELL_KNOWN.
*/
/**************************************************************************/
#define NDEF_RTD_SMART_POSTER ("Sp")
/**************************************************************************/
/*!
RTD Alternative Carrier type. For use with NDEF_TNF_WELL_KNOWN.
*/
/**************************************************************************/
#define NDEF_RTD_ALTERNATIVE_CARRIER ("ac")
/**************************************************************************/
/*!
RTD Handover Carrier type. For use with NDEF_TNF_WELL_KNOWN.
*/
/**************************************************************************/
#define NDEF_RTD_HANDOVER_CARRIER ("Hc")
/**************************************************************************/
/*!
RTD Handover Request type. For use with NDEF_TNF_WELL_KNOWN.
*/
/**************************************************************************/
#define NDEF_RTD_HANDOVER_REQUEST ("Hr")
/**************************************************************************/
/*!
RTD Handover Select type. For use with NDEF_TNF_WELL_KNOWN.
*/
/**************************************************************************/
#define NDEF_RTD_HANDOVER_SELECT ("Hs")
/**************************************************************************/
/*!
RTD Android app type. For use with TNF_EXTERNAL.
The payload of a record with type NDEF_RTD_ANDROID_APP should be the
package name identifying an application. Multiple NDEF_RTD_ANDROID_APP
records may be included in a single {@link NdefMessage}.
Use {@link #createApplicationRecord(String)} to create
NDEF_RTD_ANDROID_APP records.
*/
/**************************************************************************/
#define NDEF_RTD_ANDROID_APP ("android.com:pkg")
/**************************************************************************/
/*!
URI Idenfifier Codes used by URI Records with Well-Known Records (TNF
Record type 0x01). These code are inserted before the URI payload to
help keep the records as short as possible.
*/
/**************************************************************************/
typedef enum
{
NDEF_WNR_URIPREFIX_NONE = 0x00,
NDEF_WNR_URIPREFIX_HTTP_WWWDOT = 0x01,
NDEF_WNR_URIPREFIX_HTTPS_WWWDOT = 0x02,
NDEF_WNR_URIPREFIX_HTTP = 0x03,
NDEF_WNR_URIPREFIX_HTTPS = 0x04,
NDEF_WNR_URIPREFIX_TEL = 0x05,
NDEF_WNR_URIPREFIX_MAILTO = 0x06,
NDEF_WNR_URIPREFIX_FTP_ANONAT = 0x07,
NDEF_WNR_URIPREFIX_FTP_FTPDOT = 0x08,
NDEF_WNR_URIPREFIX_FTPS = 0x09,
NDEF_WNR_URIPREFIX_SFTP = 0x0A,
NDEF_WNR_URIPREFIX_SMB = 0x0B,
NDEF_WNR_URIPREFIX_NFS = 0x0C,
NDEF_WNR_URIPREFIX_FTP = 0x0D,
NDEF_WNR_URIPREFIX_DAV = 0x0E,
NDEF_WNR_URIPREFIX_NEWS = 0x0F,
NDEF_WNR_URIPREFIX_TELNET = 0x10,
NDEF_WNR_URIPREFIX_IMAP = 0x11,
NDEF_WNR_URIPREFIX_RTSP = 0x12,
NDEF_WNR_URIPREFIX_URN = 0x13,
NDEF_WNR_URIPREFIX_POP = 0x14,
NDEF_WNR_URIPREFIX_SIP = 0x15,
NDEF_WNR_URIPREFIX_SIPS = 0x16,
NDEF_WNR_URIPREFIX_TFTP = 0x17,
NDEF_WNR_URIPREFIX_BTSPP = 0x18,
NDEF_WNR_URIPREFIX_BTL2CAP = 0x19,
NDEF_WNR_URIPREFIX_BTGOEP = 0x1A,
NDEF_WNR_URIPREFIX_TCPOBEX = 0x1B,
NDEF_WNR_URIPREFIX_IRDAOBEX = 0x1C,
NDEF_WNR_URIPREFIX_FILE = 0x1D,
NDEF_WNR_URIPREFIX_URN_EPC_ID = 0x1E,
NDEF_WNR_URIPREFIX_URN_EPC_TAG = 0x1F,
NDEF_WNR_URIPREFIX_URN_EPC_PAT = 0x20,
NDEF_WNR_URIPREFIX_URN_EPC_RAW = 0x21,
NDEF_WNR_URIPREFIX_URN_EPC = 0x22,
NDEF_WNR_URIPREFIX_URN_NFC = 0x23
} pn532_ndef_wnr_urirec_ident_t;
/**************************************************************************/
/*!
PN532 buffer modes (controls the way dynamic memory is managed)
*/
/**************************************************************************/
typedef enum pn532_ndef_create_buffer_mode_en
{
/** pn532_ndef_create allocate new buffer to store NDEF record and manage
* it, after calling pn532_ndef_create function, upper layer can change
* buffer content and free it after using.
* This is the safest mode, but require more memory*/
NDEF_CREATE_BUFFER_MODE_DUPLICATE = 0,
/** pn532_ndef_create refer to input buffer, upper layer should not modify
* buffer content and has to free it after using buffer */
NDEF_CREATE_BUFFER_MODE_REFERENCE,
/** pn532_ndef_create refer and manage input buffer */
NDEF_CREATE_BUFFER_MODE_DELEGATE
} pn532_ndef_create_buffer_mode_t;
/**************************************************************************/
/*!
NDEF Structures use to parse NDEF message reading from media
*/
/**************************************************************************/
typedef void* pn532_ndef_record_t;
typedef pn532_ndef_record_t pn532_ndef_message_t;
/**************************************************************************/
/*!
@brief Call back to fetch data for NDEF parsing
@see pn532_ndef_parser_stream
*/
/**************************************************************************/
typedef pn532_error_t (*pn532_ndef_fetch_data_fn)(void* pUserData,
uint8_t *out_buff, uint32_t length);
/**************************************************************************/
/*!
@brief Creates an empty NDEF record
@param[out] pNdefRecord pointer to the new record
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
PN532_ERROR_MEM_INSUFFICIENT
*/
/**************************************************************************/
pn532_error_t pn532_ndef_create_empty(pn532_ndef_record_t *pNdefRecord);
/**************************************************************************/
/*!
@brief Create an NDEF record from supplied details
@param[out] pNdefRecord pointer to the new record
@param[in] tnf TNF ID
@param[in] pType record type
@param[in] typeLength length of pType
@param[in,opt] pId record ID
@param[in] idLength length of pId
@param[in] pPayload record payload
@param[in] payloadLength length of pPayload
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
PN532_ERROR_MEM_INSUFFICIENT
*/
/**************************************************************************/
pn532_error_t pn532_ndef_createFromValue(pn532_ndef_record_t *pNdefRecord,
uint8_t tnf, uint8_t *pType, uint8_t typeLength, uint8_t *pId,
uint8_t idLength, uint8_t *pPayload, uint32_t payloadLength);
/**************************************************************************/
/*!
@brief Creates an NDEF record from raw buffer data
@param[out] pNdefRecord pointer to the new record
@param[in] pBuffer buffer containing the raw record data
@param[in] length length of the raw NDEF record data
@param[in] bufferMode buffer management mode
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
PN532_ERROR_MEM_INSUFFICIENT
@see pn532_ndef_create_buffer_mode_t
*/
/**************************************************************************/
pn532_error_t pn532_ndef_createFromRawEx(pn532_ndef_record_t *pNdefRecord,
uint8_t *pBuffer, uint32_t length,
pn532_ndef_create_buffer_mode_t bufferMode);
/**************************************************************************/
/*!
@brief Creates an NDEF record from raw buffer data using the default
buffer management mode (NDEF_CREATE_BUFFER_MODE_DUPLICATE)
@param[out] pNdefRecord pointer to the new record
@param[in] pBuffer buffer containing the raw record data
@param[in] length length of raw NDEF record data
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
PN532_ERROR_MEM_INSUFFICIENT
@see pn532_ndef_create_buffer_mode_t
*/
/**************************************************************************/
pn532_error_t pn532_ndef_createFromRaw(pn532_ndef_record_t *pNdefRecord,
uint8_t *pBuffer, uint32_t length);
/**************************************************************************/
/*!
@brief Creates an NDEF record from a stream (NDEF_CREATE_BUFFER_MODE_REFERENCE)
@param[out] pNdefRecord pointer to the new record
@param[in] fnFetch function to fetch data
@param[in] pUserData User data which will be passed to
the fnFetch callback
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
PN532_ERROR_MEM_INSUFFICIENT
@see pn532_ndef_create_buffer_mode_t
*/
/**************************************************************************/
pn532_error_t pn532_ndef_createFromStream(pn532_ndef_record_t *pNdefRecord,
pn532_ndef_fetch_data_fn fnFetch, void *pUserData);
/**************************************************************************/
/*!
@brief Destroys the record, freeing the memory
@param ndefRec NDEF record to destroy
*/
/**************************************************************************/
void pn532_ndef_destroy(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Updates an NDEF record with new data/values
@note Please note that this function frees allocated resources
before updating any values. If the function fails to allocate
memory for new record, previous values are discarded
and the record becomes empty.
@param[in,out] ndefRecord Ndef record to update
@param[in] tnf TNF ID
@param[in] pType record type
@param[in] typeLength length of pType
@param[in,opt] pId record Id
@param[in] idLength length of pId
@param[in] pPayload record payload
@param[in] payloadLength length of pPayload
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
PN532_ERROR_MEM_INSUFFICIENT
*/
/**************************************************************************/
pn532_error_t pn532_ndef_update(pn532_ndef_record_t ndefRecord, uint8_t tnf,
uint8_t *pType, uint8_t typeLength, uint8_t *pId, uint8_t idLength,
uint8_t *pPayload, uint32_t payloadLength);
/**************************************************************************/
/*!
@brief Updates an NDEF record from a raw buffer
@note Please note that this function frees allocated resources
before updating any values. If the function fails to allocate
memory for new record, previous values are discarded
and the record becomes empty.
@param[in,out] ndefRecord Ndef record to update
@param[in] pBuffer Buffer containing raw record data
@param[in] length length of data in buffer
@param[in] bufferMode buffer management mode
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
PN532_ERROR_MEM_INSUFFICIENT
*/
/**************************************************************************/
pn532_error_t pn532_ndef_updateFromRawEx(pn532_ndef_record_t ndefRecord,
uint8_t *pBuffer, uint32_t length,
pn532_ndef_create_buffer_mode_t bufferMode);
/**************************************************************************/
/*!
@brief Parse an NDEF record from a buffer using the default buffer
management mode (NDEF_CREATE_BUFFER_MODE_DUPLICATE)
@note Please note that this function frees allocated resources
before updating any values. If the function fails to allocate
memory for new record, previous values are discarded
and the record becomes empty.
@param[in,out] ndefRecord Ndef record to update
@param[in] pBuffer Buffer containing raw record data
@param[in] length length of data in buffer
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
PN532_ERROR_MEM_INSUFFICIENT
*/
/**************************************************************************/
pn532_error_t pn532_ndef_updateFromRaw(pn532_ndef_record_t ndefRecord,
uint8_t *pBuffer, uint32_t length);
/**************************************************************************/
/*!
@brief Updates an Ndef record from a runtime stream
@note Please note that this function frees allocated resources
before updating any values. If the function fails to allocate
memory for new record, previous values are discarded
and the record becomes empty.
@param[in,out] ndefRecord Ndef record to store data
@param[in] fnFetch Function to get data on demand during the
parsing process
@param[in] pUserData User data which will passed to fnFetch
callback
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
PN532_ERROR_MEM_INSUFFICIENT
*/
/**************************************************************************/
pn532_error_t pn532_ndef_updateFromStream(pn532_ndef_record_t ndefRecord,
pn532_ndef_fetch_data_fn fnFetch, void* pUserData);
/**************************************************************************/
/* Getter and Setter functions */
/**************************************************************************/
/**************************************************************************/
/*!
@brief Get MB (Message Begin) flag
@param[in] ndefRecord NDEF record to get MB from
@return MB state (1 or 0)
@see pn532_ndef_setMB, pn532_ndef_clearMB
*/
/**************************************************************************/
uint8_t pn532_ndef_getMB(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Set MB (Message Begin) flag
@param[in] ndefRecord Ndef record to set MB flag in
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
@see pn532_ndef_getMB, pn532_ndef_clearMB
*/
/**************************************************************************/
pn532_error_t pn532_ndef_setMB(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Clear MB (Message Begin) flag
@param[in] ndefRecord Ndef record to clear MB flag in
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
@see pn532_ndef_getMB, pn532_ndef_setMB
*/
/**************************************************************************/
pn532_error_t pn532_ndef_clearMB(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Gets the ME (Message End) flag
@param[in] ndefRecord NDEF record to get MB from
@return ME flag
@see pn532_ndef_setME, pn532_ndef_clearME
*/
/**************************************************************************/
uint8_t pn532_ndef_getME(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Sets the ME (Message End) flag
@param[in] ndefRecord Ndef record to set ME flag in
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
@see pn532_ndef_getME, pn532_ndef_clearME
*/
/**************************************************************************/
pn532_error_t pn532_ndef_setME(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Clears the ME (Message End) flag
@param[in] ndefRecord Ndef record to clear ME flag in
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
@see pn532_ndef_getME, pn532_ndef_setME
*/
/**************************************************************************/
pn532_error_t pn532_ndef_clearME(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Gets the TNF (Type Name Format)
@param[in] ndefRecord NDEF record to get TNF from
@return The TNF value
*/
/**************************************************************************/
uint8_t pn532_ndef_getTNF(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Gets the record type
@param[in] ndefRecord NDEF record to get Type from
@return A constant pointer to Type or NULL if no valid Type
value was found
@see pn532_ndef_getTypeLength
*/
/**************************************************************************/
const uint8_t* pn532_ndef_getType(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Gets the type length
@param[in] ndefRecord NDEF record to get Type length from
@return type length or 0 if no valid type value
@see pn532_ndef_getType
*/
/**************************************************************************/
uint32_t pn532_ndef_getTypeLength(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Gets the record's ID
@param[in] ndefRecord NDEF record to get ID from
@return A constant pointer to ID or NULL if the input record
has no ID
@see pn532_ndef_getIdLength
*/
/**************************************************************************/
const uint8_t* pn532_ndef_getId(pn532_ndef_record_t ndefRecord);
/**
*/
/**************************************************************************/
/*!
@brief Get the ID length
@param[in] ndefRecord NDEF record to get Id length from
@return ID length or 0 if the input record has no ID
@see pn532_ndef_getId
*/
/**************************************************************************/
uint32_t pn532_ndef_getIdLength(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Get the record payload
@param[in] ndefRecord NDEF record to get payload from
@return A constant pointer to payload or NULL if the input
record has no valid payload.
@see pn532_ndef_getPayloadLength
*/
/**************************************************************************/
const uint8_t* pn532_ndef_getPayload(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Get the payload length
@param[in] ndefRecord NDEF record to get Payload length
@return Payload length or 0 if the input record has no
valid payload
@see pn532_ndef_getPayload
*/
/**************************************************************************/
uint32_t pn532_ndef_getPayloadLength(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Get the entire NDEF record
@param[in] ndefRecord NDEF record
@return constant pointer to the record data
*/
/**************************************************************************/
const uint8_t* pn532_ndef_getAll(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Get length of entire NDEF record
@param[in] ndefRecord NDEF record to get length
@return length of entire NDEF record
*/
/**************************************************************************/
uint32_t pn532_ndef_getLength(pn532_ndef_record_t ndefRecord);
/************************************************************************/
/* NDEF Message functions */
/************************************************************************/
/**************************************************************************/
/*!
@brief Gets the next NDEF record in the NDEF message
@param[in] ndefRecord Current NDEF record
@return The next NDEF record, or NULL if no record is present
@see pn532_ndef_linkNextRecord
*/
/**************************************************************************/
pn532_ndef_record_t pn532_ndef_getNextRecord(pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Appends an NDEF record after current NDEF record.<br/>
The current record should be the last record of the NDEF
message.
@param[in] ndefRecord Current NDEF record
@param[in] nextRecord Next NDEF record
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
@see pn532_ndef_linkNextRecord
*/
/**************************************************************************/
pn532_error_t pn532_ndef_linkNextRecord(pn532_ndef_record_t ndefRecord,
pn532_ndef_record_t nextRecord);
/**************************************************************************/
/*!
@brief Appends a new NDEF record to NDEF message.
@param[in] ndefMesg NDEF message
@param[in] ndefRecord new NDEF record, which will be appended
to ndefMesg
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
*/
/**************************************************************************/
pn532_error_t pn532_ndef_appendRecord(pn532_ndef_message_t ndefMesg,
pn532_ndef_record_t ndefRecord);
/**************************************************************************/
/*!
@brief Gest the first record of the NDEF message
@param[in] ndefMesg NDEF message
@return The first NDEF record or NULL if NDEF message is empty
*/
/**************************************************************************/
pn532_ndef_record_t pn532_ndef_getFirstRecord(pn532_ndef_message_t ndefMesg);
/**************************************************************************/
/*!
@brief Gets the record identified by index
@param[in] ndefMesg NDEF message
@param[in] index index of requested record (start by 0)
@return NDEF record at index or NULL if NDEF message has less
than (index+1) record
@see pn532_ndef_getNumberOfRecord
*/
/**************************************************************************/
pn532_ndef_record_t pn532_ndef_getRecord(pn532_ndef_message_t ndefMesg,
uint32_t index);
/**************************************************************************/
/*!
@brief Gets the number of records in the NDEF message
@param[in] ndefMesg NDEF message
@return Number of NDEF record
*/
/**************************************************************************/
uint32_t pn532_ndef_getNumberOfRecords(pn532_ndef_message_t ndefMesg);
/**************************************************************************/
/*!
@brief Creates a payload for a Text 'Well-Known Record Type'
BYTE Description
---- -------------------------------------------------
0 Status byte
Bit 7 - 0 - UTF-8 encoding
1 - UTF-16 encoding
Bit 6 - RFU (must be 0)
BIT 5..0 - ISO/IANA code length
1 ISO/IANA language code (ex. 'en' or 'en-GB').
Encoding is always in US-ASCII.
n+1 Actual text encoded in either UTF-8 or UTF-16
@param[in] isoCode char array containing the ISO/IANA code
@param[in] text char array containg the text payload
@param[in] payloadBuffer buffer to hold the text payload
@param[out] bufferLen length of the payloadBuffer
@return pn532_error_t, possible error messages are:
PN532_ERROR_INVALID_PARAM
*/
/**************************************************************************/
pn532_error_t pn532_ndef_createTextPayload(char *isoCode, char *text,
char *payloadBuffer, int32_t *bufferLen);
#endif
| 38.765799 | 83 | 0.489579 |
7802f0a2df2d1108d4503aaf20de84099dbcf6e2 | 29,652 | c | C | engine/src/font.c | OldCoder/BEWorld | dc189ab712930152e177fe3699b003d56562c349 | [
"MIT"
] | 3 | 2015-08-27T05:15:18.000Z | 2021-01-24T22:23:34.000Z | engine/src/font.c | OldCoder/BEWorld | dc189ab712930152e177fe3699b003d56562c349 | [
"MIT"
] | null | null | null | engine/src/font.c | OldCoder/BEWorld | dc189ab712930152e177fe3699b003d56562c349 | [
"MIT"
] | null | null | null | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "common.h"
#include "font.h"
/* all fonts loaded into the system */
static list *fonts;
/*
* let's start our font list with our "default" font
*/
void init_fonts()
{
int i;
unsigned char *buf;
/* a simple default 8x8 font definition */
unsigned char font[] =
{
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1,
1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1,
1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 0,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1,
1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 0, 1, 1,
1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0,
1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1,
1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1,
1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1,
1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,
1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1,
1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1,
1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1,
1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 0,
1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 1, 1,
1, 1, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 0, 1, 1, 0, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1,
1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0,
1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1,
1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1,
1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1,
1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 0, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1,
1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1,
1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1,
1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0,
1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1,
1, 0, 1, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1,
1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 1, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1,
1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1,
1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 1,
1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1,
1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1 };
/* initialize font list */
DEBUG("Initializing font list...");
fonts = list_create();
DEBUGF;
/* expand the char-encoded font into rgba data */
buf = ck_malloc(8 * 8 * FONT_CT * RGBA_BYTES);
for( i=0; i < 8192; i++ )
*(int32_t *)(buf + i * RGBA_BYTES) = font[i] ? 0xffffffff : 0xff000000;
/* add the default 8x8 font to the fontlist */
DEBUG("Adding default font...");
font_add("default", 8, 8, buf, NULL);
DEBUGF;
/* and done */
free(buf);
}
/*
* delete the fonts in the font list and free the list itself
*/
void quit_fonts()
{
iterator iter;
font *f;
int i;
DEBUG("Freeing font list...");
/* start off with the font list .. */
iterator_start(iter, fonts);
while( (f = iterator_data(iter)) )
{
/* free the font characters */
for( i=0; i < FONT_CT; i++ )
frame_delete(f->chars[i]);
/* and the font itself */
free(f);
iterator_next(iter);
}
/* and now, free the list itself */
list_delete(fonts);
fonts = NULL;
DEBUGF;
}
/*
* add a font to the master list
*/
void font_add(const char *name, int w, int h, const unsigned char *data, int *widths)
{
/* the font data, the new font .. */
frame *fr;
font *f;
/* failsafe */
if( !name || !data )
return;
/* copy the characters into the font definition */
fr = frame_create(FRAME_RGBA, w * FONT_CT, h, data, NULL);
f = prepare_font(fr, widths);
/* now add this new font to the font list */
strncpy(f->name, name, 49);
list_add(fonts, f);
/* and free the scratchpad frame */
frame_delete(fr);
}
/*
* load a font from disk
*/
void font_from_disk(const char *name, const char *file, int *widths)
{
/* the new font */
font *f;
frame *fr;
/* failsafe */
if( !name || !file )
return;
/* copy the characters into the font definition */
fr = frame_from_disk(file);
if( !fr )
return;
f = prepare_font(fr, widths);
/* now add this new font to the font list */
strncpy(f->name, name, 49);
list_add(fonts, f);
/* and free the scratchpad frame */
frame_delete(fr);
}
/*
* load a font from a memory buffer
*/
void font_from_buffer(const char *name, int len, const unsigned char *data, int *widths)
{
/* the new font */
font *f;
frame *fr;
/* failsafe */
if( !name )
return;
/* copy the characters into the font definition */
fr = frame_from_buffer(len, data);
if( !fr )
return;
f = prepare_font(fr, widths);
/* now add this new font to the font list */
strncpy(f->name, name, 49);
list_add(fonts, f);
/* and free the scratchpad frame */
frame_delete(fr);
}
/*
* retrieve a font by its name
*/
font *get_font_by_name(const char *name)
{
/* to scan the fonts */
iterator iter;
font *f;
/* failsafe */
if( !name )
return NULL;
/* first, retrieve the font list .. */
iterator_start(iter, fonts);
while( (f = iterator_data(iter)) )
{
if( !strcmp(f->name, name) )
return f;
iterator_next(iter);
}
/* nothing found? */
return NULL;
}
/*
* the internal processing of a font
*/
static font *prepare_font(frame *fr, int *widths)
{
/* the new font */
int i, w, xofs;
font *f;
/* allocate the new font definition */
f = ck_malloc(sizeof(font));
/* copy the characters into the font definition */
if( widths )
{
/* if we've got a set of widths, use those to slice out chars of the desired widths */
for( i=0, xofs = 0; i < FONT_CT; i++ )
{
f->chars[i] = frame_slice(fr, xofs, 0, *(widths+i), fr->h);
xofs += *(widths+i);
}
}
else
{
/* otherwise, assume a fixed width */
w = fr->w / FONT_CT;
for( i=0; i < FONT_CT; i++ )
f->chars[i] = frame_slice(fr, w*i, 0, w, fr->h);
}
/* and done */
return f;
}
| 47.825806 | 89 | 0.359436 |
931fc8feec49a7a215dcfed8c5f887c678582a76 | 476 | h | C | VisAnalyticsKit/Log/Filesystem/Writer/VAKFileWriterConstants.h | HPC-Group/VisAnalyticsKit | 12bc297bdd989afbd4cf4d9bc20c56e9e4a59ae1 | [
"Apache-2.0",
"MIT"
] | null | null | null | VisAnalyticsKit/Log/Filesystem/Writer/VAKFileWriterConstants.h | HPC-Group/VisAnalyticsKit | 12bc297bdd989afbd4cf4d9bc20c56e9e4a59ae1 | [
"Apache-2.0",
"MIT"
] | null | null | null | VisAnalyticsKit/Log/Filesystem/Writer/VAKFileWriterConstants.h | HPC-Group/VisAnalyticsKit | 12bc297bdd989afbd4cf4d9bc20c56e9e4a59ae1 | [
"Apache-2.0",
"MIT"
] | null | null | null | //
// VAKFileWriterConstants.h
// VisAnalyticsKit
//
// Created by VisAnalyticsKit on 11.02.16.
// Copyright © 2016 VisAnalyticsKit. MIT
//
/** For internal use only. Sets keys for the file writer in a reusable and maintainable way. */
static NSString *const VAKFileWriterDataKey = @"data";
static NSString *const VAKFileWriterFileKey = @"file";
static NSString *const VAKFileWriterFolderKey = @"folder";
static NSString *const VAKFileWriterExtensionKey = @"extension";
| 31.733333 | 95 | 0.752101 |
2b6050977503578c5098d4cc838bb97a05ef4e3e | 275 | h | C | SimCore/model/Power/Power.h | kino-6/BuiltInSystemSimulator | 63d447f89c0c9166b93a96844d2d103f9d00a4b2 | [
"Apache-2.0"
] | null | null | null | SimCore/model/Power/Power.h | kino-6/BuiltInSystemSimulator | 63d447f89c0c9166b93a96844d2d103f9d00a4b2 | [
"Apache-2.0"
] | null | null | null | SimCore/model/Power/Power.h | kino-6/BuiltInSystemSimulator | 63d447f89c0c9166b93a96844d2d103f9d00a4b2 | [
"Apache-2.0"
] | null | null | null | #pragma once
#include "BaseModel.h"
class Power :
public BaseModel
{
public:
long double input_v;
long double output_v;
Power();
~Power();
void input(long double input_v);
long double output(void);
void Main(void);
void Reset(void);
};
| 14.473684 | 36 | 0.632727 |
1a54c6a1f0851a63ffc9eb145691aef510249452 | 1,473 | h | C | vm_tools/sommelier/sommelier-timing.h | Toromino/chromiumos-platform2 | 97e6ba18f0e5ab6723f3448a66f82c1a07538d87 | [
"BSD-3-Clause"
] | null | null | null | vm_tools/sommelier/sommelier-timing.h | Toromino/chromiumos-platform2 | 97e6ba18f0e5ab6723f3448a66f82c1a07538d87 | [
"BSD-3-Clause"
] | null | null | null | vm_tools/sommelier/sommelier-timing.h | Toromino/chromiumos-platform2 | 97e6ba18f0e5ab6723f3448a66f82c1a07538d87 | [
"BSD-3-Clause"
] | null | null | null | // Copyright 2021 The Chromium OS Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef VM_TOOLS_SOMMELIER_SOMMELIER_TIMING_H_
#define VM_TOOLS_SOMMELIER_SOMMELIER_TIMING_H_
#include <time.h>
const int kUnknownBufferId = -1;
const int kUnknownSurfaceId = -1;
class Timing {
public:
explicit Timing(const char* fname) : filename(fname) {}
void UpdateLastAttach(int surface_id, int buffer_id);
void UpdateLastCommit(int surface_id);
void UpdateLastRelease(int buffer_id);
void OutputLog();
private:
// 10 min * 60 sec/min * 60 frames/sec * 3 actions/frame = 108000 actions
static const int kMaxNumActions = 10 * 60 * 60 * 3;
struct BufferAction {
enum Type { UNKNOWN, ATTACH, COMMIT, RELEASE };
timespec time;
int surface_id;
int buffer_id;
Type action_type;
BufferAction()
: surface_id(kUnknownSurfaceId),
buffer_id(kUnknownBufferId),
action_type(UNKNOWN) {}
explicit BufferAction(timespec t,
int sid = kUnknownSurfaceId,
int bid = kUnknownBufferId,
Type type = UNKNOWN)
: time(t), surface_id(sid), buffer_id(bid), action_type(type) {}
};
BufferAction actions[kMaxNumActions];
int actions_idx = 0;
int saves = 0;
const char* filename;
}; // class Timing
#endif // VM_TOOLS_SOMMELIER_SOMMELIER_TIMING_H_
| 30.6875 | 75 | 0.678887 |
1a85bc168f377da3e73deb319cbfc0baeb7d8139 | 146 | h | C | src/mods/gromacs/rpcxdr.h | JonnyWideFoot/pd.arcus | a6197a5a2a18c0e3f752e15aa982d1e44d052730 | [
"BSD-4-Clause-UC"
] | null | null | null | src/mods/gromacs/rpcxdr.h | JonnyWideFoot/pd.arcus | a6197a5a2a18c0e3f752e15aa982d1e44d052730 | [
"BSD-4-Clause-UC"
] | null | null | null | src/mods/gromacs/rpcxdr.h | JonnyWideFoot/pd.arcus | a6197a5a2a18c0e3f752e15aa982d1e44d052730 | [
"BSD-4-Clause-UC"
] | null | null | null |
//#include <rpc/rpc.h>
//#include <rpc/xdr.h>
#ifdef __cplusplus
extern "C" {
#endif
#include "gmx_system_xdr.h"
#ifdef __cplusplus
}
#endif
| 9.733333 | 27 | 0.678082 |
ff01187bb2b51dbe89ff80a26c4201e85b9bc9a2 | 10,081 | c | C | ocempgui/access/papi/papi_atkhyperlink.c | djkool/OcempGUI3 | 43a68033cb0dbad10654231299cb762cd18b7c25 | [
"BSD-2-Clause"
] | null | null | null | ocempgui/access/papi/papi_atkhyperlink.c | djkool/OcempGUI3 | 43a68033cb0dbad10654231299cb762cd18b7c25 | [
"BSD-2-Clause"
] | null | null | null | ocempgui/access/papi/papi_atkhyperlink.c | djkool/OcempGUI3 | 43a68033cb0dbad10654231299cb762cd18b7c25 | [
"BSD-2-Clause"
] | null | null | null | /* $Id: papi_atkhyperlink.c,v 1.5.2.5 2007/09/23 07:37:48 marcusva Exp $
*
* Copyright (c) 2006-2007, Marcus von Appen
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "papi.h"
#include "papi_private.h"
/* Forward declarations. */
static PyObject* _atkhyperlink_new (PyTypeObject *type, PyObject *args,
PyObject *kwds);
static int _atkhyperlink_init (PyAtkHyperlink *self, PyObject *args,
PyObject *kwds);
static void _atkhyperlink_dealloc (PyAtkHyperlink *self);
static PyObject *_atkhyperlink_get_uri (PyAtkHyperlink *self, PyObject *args);
static PyObject *_atkhyperlink_get_object (PyAtkHyperlink *self,
PyObject *args);
static PyObject *_atkhyperlink_get_end_index (PyAtkHyperlink *self);
static PyObject *_atkhyperlink_get_start_index (PyAtkHyperlink *self);
static PyObject *_atkhyperlink_get_n_anchors (PyAtkHyperlink *self);
static PyObject *_atkhyperlink_is_valid (PyAtkHyperlink *self, void *closure);
static PyObject *_atkhyperlink_is_inline (PyAtkHyperlink *self, void *closure);
static PyObject *_atkhyperlink_is_selected_link (PyAtkHyperlink *self,
void *closure);
/**
* Methods, which are bound to the PyAtkHyperlink type.
*/
static PyMethodDef _atkhyperlink_methods[] =
{
{ "get_uri", (PyCFunction) _atkhyperlink_get_uri, METH_VARARGS,
"H.get_uri (index) -> string\n\n"
"Get the URI associated with the anchor specified by index of link.\n\n"
"Multiple anchors are primarily used by client-side image maps.\n\n"
"This method has to be implemented by inherited classes." },
{ "get_object", (PyCFunction) _atkhyperlink_get_object, METH_VARARGS,
"H.get_object (index) -> AtkObject\n\n"
"Returns the item associated with this hyperlinks nth anchor.\n\n"
"For instance, the returned AtkObject will implement AtkText if link\n"
"is a text hyperlink, AtkImage if link_ is an image hyperlink etc.\n"
"Multiple anchors are primarily used by client-side image maps.\n\n"
"This method has to be implemented by inherited classes." },
{ "get_end_index", (PyCFunction) _atkhyperlink_get_end_index, METH_NOARGS,
"H.get_end_index () -> int\n\n"
"Gets the index with the hypertext document at which this link ends.\n\n"
"This method has to be implemented by inherited classes." },
{ "get_start_index", (PyCFunction) _atkhyperlink_get_start_index,
METH_NOARGS,
"H.get_start_index () -> int\n\n"
"Gets the index with the hypertext document at which this link "
"begins.\n\n"
"This method has to be implemented by inherited classes." },
{ "get_n_anchors", (PyCFunction) _atkhyperlink_get_n_anchors, METH_NOARGS,
"H.get_n_anchors () -> int\n\n"
"Gets the number of anchors associated with this hyperlink.\n\n"
"This method has to be implemented by inherited classes." },
{ NULL, NULL, 0, NULL }
};
/**
* Getters and setters for the AtkHyperlink.
*/
static PyGetSetDef _atkhyperlink_getsets[] =
{
{ "is_valid", (getter) _atkhyperlink_is_valid, NULL,
"H.is_valid () -> bool\n\n"
"Checks, whether the link is still valid.\n\n"
"Since the document that a link is associated with may have changed\n"
"this method returns True if the link is still valid (with respect\n"
"to the document it references) and False otherwise.", NULL },
{ "is_inline", (getter) _atkhyperlink_is_inline, NULL,
"H.is_inline () -> bool\n\n"
"Indicates whether the link displays its content inline.\n\n"
"Indicates whether the link currently displays some or all of its\n"
"content inline. Ordinary HTML links will usually return False, but\n"
"an inline <src> HTML element will return True.", NULL },
{ "is_selected_link", (getter) _atkhyperlink_is_selected_link, NULL,
"H.is_selected_link ()\n\n"
"Determines whether this AtkHyperlink is selected.\n\n"
"THIS METHOD IS DEPRECATED", NULL },
{ NULL, NULL, NULL, NULL, NULL }
};
/**
* PyAtkHyperlink wrapper type, that encapsulates the AtkHyperlink.
*/
PyTypeObject PyAtkHyperlink_Type =
{
PyObject_HEAD_INIT(NULL)
0,
"papi.AtkHyperlink", /* tp_name */
sizeof (PyAtkHyperlink), /* tp_basicsize */
0, /* tp_itemsize */
(destructor) _atkhyperlink_dealloc, /* tp_dealloc */
0, /* tp_print */
0, /* tp_getattr */
0, /* tp_setattr */
0, /* tp_compare */
0, /* tp_repr */
0, /* tp_as_number */
0, /* tp_as_sequence */
0, /* tp_as_mapping */
0, /* tp_hash */
0, /* tp_call */
0, /* tp_str */
0, /* tp_getattro */
0, /* tp_setattro */
0, /* tp_as_buffer */
Py_TPFLAGS_DEFAULT | Py_TPFLAGS_BASETYPE, /* tp_flags */
"AtkHyperlink () -> AtkHyperlink\n\n"
"ATK accessibility hyperlink.\n\n"
"An ATK object which encapsulates a link or set of links in a hypertext\n"
"document.",
0, /* tp_traverse */
0, /* tp_clear */
0, /* tp_richcompare */
0, /* tp_weaklistoffset */
0, /* tp_iter */
0, /* tp_iternext */
_atkhyperlink_methods, /* tp_methods */
0, /* tp_members */
_atkhyperlink_getsets, /* tp_getset */
0, /* tp_base */
0, /* tp_dict */
0, /* tp_descr_get */
0, /* tp_descr_set */
0, /* tp_dictoffset */
(initproc) _atkhyperlink_init, /* tp_init */
0, /* tp_alloc */
_atkhyperlink_new, /* tp_new */
0, /* tp_free */
0, /* tp_is_gc */
0, /* tp_bases */
0, /* tp_mro */
0, /* tp_cache */
0, /* tp_subclasses */
0, /* tp_weaklist */
0 /* tp_del */
};
/**
* Creates a new PyAtkHyperlink.
*/
static PyObject*
_atkhyperlink_new (PyTypeObject *type, PyObject *args, PyObject *kwds)
{
PyAtkHyperlink *self;
debug ("_atkhyperlink_new\n");
self = (PyAtkHyperlink *) type->tp_alloc (type, 0);
return (PyObject *) self;
}
/**
* Initializes the PyAtkHyperlink members, such as the AtkHyperlink.
*/
static int
_atkhyperlink_init (PyAtkHyperlink *self, PyObject *args, PyObject *kwds)
{
debug ("_atkhyperlink_init\n");
if (!self->obj)
self->obj = g_object_new (ATK_TYPE_HYPERLINK, NULL);
return 0;
}
/**
* Deallocates the PyAtkHyperlink and its members.
*/
static void
_atkhyperlink_dealloc (PyAtkHyperlink *self)
{
debug ("_atkhyperlink_dealloc\n");
if (self->obj)
g_object_unref (self->obj);
self->ob_type->tp_free ((PyObject *) self);
}
/**
* Wrapper for atk_hyperlink_get_uri().
*/
static PyObject*
_atkhyperlink_get_uri (PyAtkHyperlink *self, PyObject *args)
{
/* TODO */
Py_RETURN_NONE;
}
/**
* Wrapper for atk_hyperlink_get_object().
*/
static PyObject*
_atkhyperlink_get_object (PyAtkHyperlink *self, PyObject *args)
{
/* TODO */
Py_RETURN_NONE;
}
/**
* Wrapper for atk_hyperlink_get_end_index().
*/
static PyObject*
_atkhyperlink_get_end_index (PyAtkHyperlink *self)
{
/* TODO */
Py_RETURN_NONE;
}
/**
* Wrapper for atk_hyperlink_get_start_index().
*/
static PyObject*
_atkhyperlink_get_start_index (PyAtkHyperlink *self)
{
/* TODO */
Py_RETURN_NONE;
}
/**
* Wrapper for atk_hyperlink_is_valid().
*/
static PyObject*
_atkhyperlink_is_valid (PyAtkHyperlink *self, void *closure)
{
/* TODO */
Py_RETURN_NONE;
}
/**
* Wrapper for atk_hyperlink_is_inline().
*/
static PyObject*
_atkhyperlink_is_inline (PyAtkHyperlink *self, void *closure)
{
/* TODO */
Py_RETURN_NONE;
}
/**
* Wrapper for atk_hyperlink_get_n_anchors().
*/
static PyObject*
_atkhyperlink_get_n_anchors (PyAtkHyperlink *self)
{
/* TODO */
Py_RETURN_NONE;
}
/**
* Wrapper for atk_hyperlink_is_selected_link().
*/
static PyObject*
_atkhyperlink_is_selected_link (PyAtkHyperlink *self, void *closure)
{
/* TODO */
Py_RETURN_NONE;
}
| 35.748227 | 80 | 0.617201 |
ff8346ddb0bcb8f3c08a8962c8fcb513ee5b7554 | 556 | h | C | forks/a_little_smalltalk/src/env.h | zenwerk/littlesmalltalk | 4c9d58891b09bfce8d333b3cf718bbbd349ed246 | [
"BSD-3-Clause"
] | null | null | null | forks/a_little_smalltalk/src/env.h | zenwerk/littlesmalltalk | 4c9d58891b09bfce8d333b3cf718bbbd349ed246 | [
"BSD-3-Clause"
] | null | null | null | forks/a_little_smalltalk/src/env.h | zenwerk/littlesmalltalk | 4c9d58891b09bfce8d333b3cf718bbbd349ed246 | [
"BSD-3-Clause"
] | null | null | null | /*
Little Smalltalk, version two
Written by Tim Budd, Oregon State University, July 1987
=============== rules for various systems ====================
*/
#ifndef ENV_H
#define ENV_H
#include <stdlib.h>
#include <string.h>
typedef unsigned char byte;
/* this is a bit sloppy - but it works */
#define longCanBeInt(l) ((l >= -16383) && (l <= 16383))
#define STRINGS
#define SIGNAL
/* ======== various defines that should work on all systems ==== */
# define true 1
# define false 0
/* define the datatype boolean */
typedef char boolean;
#endif | 18.533333 | 67 | 0.642086 |
a241c60aecfdcc583db6464a83dfab5ec81e0db2 | 8,625 | c | C | Modules/mathmodule.c | 1byte2bytes/cpython | 7fbaeb819ca7b20dca048217ff585ec195e999ec | [
"Unlicense",
"TCL",
"DOC",
"AAL",
"X11"
] | 1 | 2019-10-25T21:41:07.000Z | 2019-10-25T21:41:07.000Z | Modules/mathmodule.c | 1byte2bytes/cpython | 7fbaeb819ca7b20dca048217ff585ec195e999ec | [
"Unlicense",
"TCL",
"DOC",
"AAL",
"X11"
] | null | null | null | Modules/mathmodule.c | 1byte2bytes/cpython | 7fbaeb819ca7b20dca048217ff585ec195e999ec | [
"Unlicense",
"TCL",
"DOC",
"AAL",
"X11"
] | null | null | null | /***********************************************************
Copyright 1991-1995 by Stichting Mathematisch Centrum, Amsterdam,
The Netherlands.
All Rights Reserved
Permission to use, copy, modify, and distribute this software and its
documentation for any purpose and without fee is hereby granted,
provided that the above copyright notice appear in all copies and that
both that copyright notice and this permission notice appear in
supporting documentation, and that the names of Stichting Mathematisch
Centrum or CWI or Corporation for National Research Initiatives or
CNRI not be used in advertising or publicity pertaining to
distribution of the software without specific, written prior
permission.
While CWI is the initial source for this software, a modified version
is made available by the Corporation for National Research Initiatives
(CNRI) at the Internet address ftp://ftp.python.org.
STICHTING MATHEMATISCH CENTRUM AND CNRI DISCLAIM ALL WARRANTIES WITH
REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL STICHTING MATHEMATISCH
CENTRUM OR CNRI BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL
DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
PERFORMANCE OF THIS SOFTWARE.
******************************************************************/
/* Math module -- standard C math library functions, pi and e */
#include "Python.h"
#include "mymath.h"
#ifndef _MSC_VER
#ifndef __STDC__
extern double fmod Py_PROTO((double, double));
extern double frexp Py_PROTO((double, int *));
extern double ldexp Py_PROTO((double, int));
extern double modf Py_PROTO((double, double *));
#endif /* __STDC__ */
#endif /* _MSC_VER */
#ifdef i860
/* Cray APP has bogus definition of HUGE_VAL in <math.h> */
#undef HUGE_VAL
#endif
#ifdef HUGE_VAL
#define CHECK(x) if (errno != 0) ; \
else if (-HUGE_VAL <= (x) && (x) <= HUGE_VAL) ; \
else errno = ERANGE
#else
#define CHECK(x) /* Don't know how to check */
#endif
static PyObject *
math_error()
{
if (errno == EDOM)
PyErr_SetString(PyExc_ValueError, "math domain error");
else if (errno == ERANGE)
PyErr_SetString(PyExc_OverflowError, "math range error");
else
/* Unexpected math error */
PyErr_SetFromErrno(PyExc_ValueError);
return NULL;
}
static PyObject *
math_1(args, func)
PyObject *args;
double (*func) Py_FPROTO((double));
{
double x;
if (! PyArg_Parse(args, "d", &x))
return NULL;
errno = 0;
PyFPE_START_PROTECT("in math_1", return 0)
x = (*func)(x);
PyFPE_END_PROTECT(x)
CHECK(x);
if (errno != 0)
return math_error();
else
return PyFloat_FromDouble(x);
}
static PyObject *
math_2(args, func)
PyObject *args;
double (*func) Py_FPROTO((double, double));
{
double x, y;
if (! PyArg_Parse(args, "(dd)", &x, &y))
return NULL;
errno = 0;
PyFPE_START_PROTECT("in math_2", return 0)
x = (*func)(x, y);
PyFPE_END_PROTECT(x)
CHECK(x);
if (errno != 0)
return math_error();
else
return PyFloat_FromDouble(x);
}
#define FUNC1(stubname, func, docstring_name, docstring) \
static PyObject * stubname(self, args) PyObject *self, *args; { \
return math_1(args, func); \
}\
static char docstring_name [] = docstring;
#define FUNC2(stubname, func, docstring_name, docstring) \
static PyObject * stubname(self, args) PyObject *self, *args; { \
return math_2(args, func); \
}\
static char docstring_name [] = docstring;
FUNC1(math_acos, acos, math_acos_doc,
"acos(x)\n\nReturn the arc cosine of x.")
FUNC1(math_asin, asin, math_asin_doc,
"asin(x)\n\nReturn the arc sine of x.")
FUNC1(math_atan, atan, math_atan_doc,
"atan(x)\n\nReturn the arc tangent of x.")
FUNC2(math_atan2, atan2, math_atan2_doc,
"atan2(y, x)\n\nReturn atan(y/x).")
FUNC1(math_ceil, ceil, math_ceil_doc,
"ceil(x)\n\nReturn the ceiling of x as a real.")
FUNC1(math_cos, cos, math_cos_doc,
"cos(x)\n\nReturn the cosine of x.")
FUNC1(math_cosh, cosh, math_cosh_doc,
"cosh(x)\n\nReturn the hyperbolic cosine of x.")
FUNC1(math_exp, exp, math_exp_doc,
"exp(x)\n\nReturn e raised to the power of x.")
FUNC1(math_fabs, fabs, math_fabs_doc,
"fabs(x)\n\nReturn the absolute value of the real x.")
FUNC1(math_floor, floor, math_floor_doc,
"floor(x)\n\nReturn the floor of x as a real.")
FUNC2(math_fmod, fmod, math_fmod_doc,
"fmod(x,y)\n\nReturn x % y.")
FUNC2(math_hypot, hypot, math_hypot_doc,
"hypot(x,y)\n\nReturn the Euclidean distance, sqrt(x*x + y*y).")
FUNC1(math_log, log, math_log_doc,
"log(x)\n\nReturn the natural logarithm of x.")
FUNC1(math_log10, log10, math_log10_doc,
"log10(x)\n\nReturn the base-10 logarithm of x.")
#ifdef MPW_3_1 /* This hack is needed for MPW 3.1 but not for 3.2 ... */
FUNC2(math_pow, power, math_pow_doc,
"power(x,y)\n\nReturn x**y.")
#else
FUNC2(math_pow, pow, math_pow_doc,
"pow(x,y)\n\nReturn x**y.")
#endif
FUNC1(math_sin, sin, math_sin_doc,
"sin(x)\n\nReturn the sine of x.")
FUNC1(math_sinh, sinh, math_sinh_doc,
"sinh(x)\n\nReturn the hyperbolic sine of x.")
FUNC1(math_sqrt, sqrt, math_sqrt_doc,
"sqrt(x)\n\nReturn the square root of x.")
FUNC1(math_tan, tan, math_tan_doc,
"tan(x)\n\nReturn the tangent of x.")
FUNC1(math_tanh, tanh, math_tanh_doc,
"tanh(x)\n\nReturn the hyperbolic tangent of x.")
static PyObject *
math_frexp(self, args)
PyObject *self;
PyObject *args;
{
double x;
int i;
if (! PyArg_Parse(args, "d", &x))
return NULL;
errno = 0;
x = frexp(x, &i);
CHECK(x);
if (errno != 0)
return math_error();
return Py_BuildValue("(di)", x, i);
}
static char math_frexp_doc [] =
"frexp(x)\n\
\n\
Return the matissa and exponent for x. The mantissa is positive.";
static PyObject *
math_ldexp(self, args)
PyObject *self;
PyObject *args;
{
double x, y;
/* Cheat -- allow float as second argument */
if (! PyArg_Parse(args, "(dd)", &x, &y))
return NULL;
errno = 0;
PyFPE_START_PROTECT("ldexp", return 0)
x = ldexp(x, (int)y);
PyFPE_END_PROTECT(x)
CHECK(x);
if (errno != 0)
return math_error();
else
return PyFloat_FromDouble(x);
}
static char math_ldexp_doc [] =
"ldexp_doc(x, i)\n\
\n\
Return x * (2**i).";
static PyObject *
math_modf(self, args)
PyObject *self;
PyObject *args;
{
double x, y;
if (! PyArg_Parse(args, "d", &x))
return NULL;
errno = 0;
#ifdef MPW /* MPW C modf expects pointer to extended as second argument */
{
extended e;
x = modf(x, &e);
y = e;
}
#else
x = modf(x, &y);
#endif
CHECK(x);
if (errno != 0)
return math_error();
return Py_BuildValue("(dd)", x, y);
}
static char math_modf_doc [] =
"modf(x)\n\
\n\
Return the fractional and integer parts of x. Both results carry the sign\n\
of x. The integer part is returned as a real.";
static PyMethodDef math_methods[] = {
{"acos", math_acos, 0, math_acos_doc},
{"asin", math_asin, 0, math_asin_doc},
{"atan", math_atan, 0, math_atan_doc},
{"atan2", math_atan2, 0, math_atan2_doc},
{"ceil", math_ceil, 0, math_ceil_doc},
{"cos", math_cos, 0, math_cos_doc},
{"cosh", math_cosh, 0, math_cosh_doc},
{"exp", math_exp, 0, math_exp_doc},
{"fabs", math_fabs, 0, math_fabs_doc},
{"floor", math_floor, 0, math_floor_doc},
{"fmod", math_fmod, 0, math_fmod_doc},
{"frexp", math_frexp, 0, math_frexp_doc},
{"hypot", math_hypot, 0, math_hypot_doc},
{"ldexp", math_ldexp, 0, math_ldexp_doc},
{"log", math_log, 0, math_log_doc},
{"log10", math_log10, 0, math_log10_doc},
{"modf", math_modf, 0, math_modf_doc},
{"pow", math_pow, 0, math_pow_doc},
{"sin", math_sin, 0, math_sin_doc},
{"sinh", math_sinh, 0, math_sinh_doc},
{"sqrt", math_sqrt, 0, math_sqrt_doc},
{"tan", math_tan, 0, math_tan_doc},
{"tanh", math_tanh, 0, math_tanh_doc},
{NULL, NULL} /* sentinel */
};
static char module_doc [] =
"This module is always available. It provides access to the\n\
mathematical functions defined by the C standard.";
DL_EXPORT(void)
initmath()
{
PyObject *m, *d, *v;
m = Py_InitModule3("math", math_methods, module_doc);
d = PyModule_GetDict(m);
if (!(v = PyFloat_FromDouble(atan(1.0) * 4.0)))
goto finally;
if (PyDict_SetItemString(d, "pi", v) < 0)
goto finally;
Py_DECREF(v);
if (!(v = PyFloat_FromDouble(exp(1.0))))
goto finally;
if (PyDict_SetItemString(d, "e", v) < 0)
goto finally;
Py_DECREF(v);
return;
finally:
Py_FatalError("can't initialize math module");
}
| 28.094463 | 76 | 0.674899 |
9ea139805f525b794a5b92f8e8f27cd252942ab6 | 187 | h | C | src/log.h | ShajTester/prod-db | 028f571c06aecfa6588f80db1a7f65b2f10c99f2 | [
"MIT"
] | null | null | null | src/log.h | ShajTester/prod-db | 028f571c06aecfa6588f80db1a7f65b2f10c99f2 | [
"MIT"
] | null | null | null | src/log.h | ShajTester/prod-db | 028f571c06aecfa6588f80db1a7f65b2f10c99f2 | [
"MIT"
] | null | null | null | #pragma once
#include <memory>
#include "spdlog/spdlog.h"
#include "spdlog/fmt/ostr.h"
extern std::shared_ptr<spdlog::logger> my_logger;
bool is_file_exists(const std::string &name);
| 17 | 49 | 0.748663 |
7f88ccf67fdde8f31411f61503dd0975f2a994fb | 1,422 | h | C | drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.h | jainsakshi2395/linux | 7ccb860232bb83fb60cd6bcf5aaf0c008d903acb | [
"Linux-OpenIB"
] | 44 | 2022-03-16T08:32:31.000Z | 2022-03-31T16:02:35.000Z | drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.h | jainsakshi2395/linux | 7ccb860232bb83fb60cd6bcf5aaf0c008d903acb | [
"Linux-OpenIB"
] | 13 | 2021-07-10T04:36:17.000Z | 2022-03-03T10:50:05.000Z | drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.h | jainsakshi2395/linux | 7ccb860232bb83fb60cd6bcf5aaf0c008d903acb | [
"Linux-OpenIB"
] | 18 | 2022-03-19T04:41:04.000Z | 2022-03-31T03:32:12.000Z | /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/* Copyright (c) 2019 Mellanox Technologies. */
#ifndef __MLX5_EN_XSK_RX_H__
#define __MLX5_EN_XSK_RX_H__
#include "en.h"
#include <net/xdp_sock_drv.h>
/* RX data path */
struct sk_buff *mlx5e_xsk_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq,
struct mlx5e_mpw_info *wi,
u16 cqe_bcnt,
u32 head_offset,
u32 page_idx);
struct sk_buff *mlx5e_xsk_skb_from_cqe_linear(struct mlx5e_rq *rq,
struct mlx5_cqe64 *cqe,
struct mlx5e_wqe_frag_info *wi,
u32 cqe_bcnt);
static inline int mlx5e_xsk_page_alloc_pool(struct mlx5e_rq *rq,
struct mlx5e_dma_info *dma_info)
{
dma_info->xsk = xsk_buff_alloc(rq->xsk_pool);
if (!dma_info->xsk)
return -ENOMEM;
/* Store the DMA address without headroom. In striding RQ case, we just
* provide pages for UMR, and headroom is counted at the setup stage
* when creating a WQE. In non-striding RQ case, headroom is accounted
* in mlx5e_alloc_rx_wqe.
*/
dma_info->addr = xsk_buff_xdp_get_frame_dma(dma_info->xsk);
return 0;
}
static inline bool mlx5e_xsk_update_rx_wakeup(struct mlx5e_rq *rq, bool alloc_err)
{
if (!xsk_uses_need_wakeup(rq->xsk_pool))
return alloc_err;
if (unlikely(alloc_err))
xsk_set_rx_need_wakeup(rq->xsk_pool);
else
xsk_clear_rx_need_wakeup(rq->xsk_pool);
return false;
}
#endif /* __MLX5_EN_XSK_RX_H__ */
| 26.830189 | 82 | 0.724332 |
7f8a9c140f9c797266ecd9e91e67039c0db1b87f | 750 | h | C | UnrealDITests/Source/UnrealDITests/Public/MockClasses_EmptyDependencies.h | druhasu/UnrealDI | 6e4da5d4ddbc48e138e383b3896c8fb6c5c08467 | [
"MIT"
] | 2 | 2021-11-28T17:09:17.000Z | 2021-12-09T11:02:34.000Z | UnrealDITests/Source/UnrealDITests/Public/MockClasses_EmptyDependencies.h | druhasu/UnrealDI | 6e4da5d4ddbc48e138e383b3896c8fb6c5c08467 | [
"MIT"
] | null | null | null | UnrealDITests/Source/UnrealDITests/Public/MockClasses_EmptyDependencies.h | druhasu/UnrealDI | 6e4da5d4ddbc48e138e383b3896c8fb6c5c08467 | [
"MIT"
] | 1 | 2021-12-23T14:11:06.000Z | 2021-12-23T14:11:06.000Z | // Copyright Andrei Sudarikov. All Rights Reserved.
#pragma once
#include "TestClasses.h"
#include "GameFramework/Actor.h"
#include "Blueprint/UserWidget.h"
#include "MockClasses_EmptyDependencies.generated.h"
UCLASS()
class UObjectNoDeps : public UObject
{
GENERATED_BODY()
public:
void InitDependencies()
{
bWasCalled = true;
}
bool bWasCalled = false;
};
UCLASS()
class AActorNoDeps : public AActor
{
GENERATED_BODY()
public:
void InitDependencies()
{
bWasCalled = true;
}
bool bWasCalled = false;
};
UCLASS()
class UWidgetNoDeps : public UUserWidget
{
GENERATED_BODY()
public:
void InitDependencies()
{
bWasCalled = true;
}
bool bWasCalled = false;
}; | 15 | 52 | 0.668 |
9ac865375b8d2731a9b88be54327cf8d0127d799 | 3,982 | c | C | main.c | Dananga/Voting-System-for-PIC-micro-Controller | 8aac0968184f69c7ab9eb322c7b7fecf7cc027b5 | [
"MIT"
] | 1 | 2019-07-18T05:22:15.000Z | 2019-07-18T05:22:15.000Z | main.c | Dananga/Voting-System-for-PIC-micro-Controller | 8aac0968184f69c7ab9eb322c7b7fecf7cc027b5 | [
"MIT"
] | null | null | null | main.c | Dananga/Voting-System-for-PIC-micro-Controller | 8aac0968184f69c7ab9eb322c7b7fecf7cc027b5 | [
"MIT"
] | null | null | null | /*
* File: main.c
* Author: Navindu Dananga
*
* Created on June 9, 2019, 7:51 PM
*/
#define _XTAL_FREQ 4000000
// PIC16F877 Configuration Bit Settings
// 'C' source line config statements
// CONFIG
#pragma config FOSC = XT // Oscillator Selection bits (XT oscillator)
#pragma config WDTE = OFF // Watchdog Timer Enable bit (WDT enabled)
#pragma config PWRTE = OFF // Power-up Timer Enable bit (PWRT disabled)
#pragma config CP = OFF // FLASH Program Memory Code Protection bits (Code protection off)
#pragma config BOREN = OFF // Brown-out Reset Enable bit (BOR disabled)
#pragma config LVP = OFF // Low Voltage In-Circuit Serial Programming Enable bit (RB3 is digital I/O, HV on MCLR must be used for programming)
#pragma config CPD = OFF // Data EE Memory Code Protection (Code Protection off)
#pragma config WRT = OFF // FLASH Program Memory Write Enable (Unprotected program memory may not be written to by EECON control)
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
#define RS RD2
#define EN RD3
#define D4 RD4
#define D5 RD5
#define D6 RD6
#define D7 RD7
#include <xc.h>
#include "lcd.h"
#include <stdio.h>
#include <string.h>
char votes[16];
void main(void) {
TRISB = 0xFF;
TRISD = 0x00;
TRISC = 0x00;
PORTB = 0x00;
PORTC = 0x00;
PORTCbits.RC0 = 1; //power indicator
PORTDbits.RD0 = 0;
int accessToVote = 0; //rb0
int ttlVotesOf_A = 0; //rb1
int ttlVotesOf_B = 0; //rb2
int ttlVotesOf_C = 0; //rb3
Lcd_Init();
Lcd_Set_Cursor(1,1);
Lcd_Write_String(" Voting System ");
__delay_ms(1000);
Lcd_Clear();
sprintf(votes, " A:%d B:%d C:%d", ttlVotesOf_A, ttlVotesOf_B, ttlVotesOf_C);
Lcd_Set_Cursor(1,1);
Lcd_Write_String(votes);
while(1){
if(PORTBbits.RB0 == 1) {
accessToVote = 1;
}
int pressBtnOf_A = (PORTBbits.RB1 == 1) && (PORTBbits.RB2 == 0) && (PORTBbits.RB3 == 0);
int pressBtnOf_B = (PORTBbits.RB1 == 0) && (PORTBbits.RB2 == 1) && (PORTBbits.RB3 == 0);
int pressBtnOf_C = (PORTBbits.RB1 == 0) && (PORTBbits.RB2 == 0) && (PORTBbits.RB3 == 1);
if(accessToVote){
PORTDbits.RD1 = 1;
Lcd_Set_Cursor(2,1);
Lcd_Write_String("You Can Vote Now");
if(pressBtnOf_A){
PORTDbits.RD0 = 1;
PORTCbits.RC1 = 1;
ttlVotesOf_A += 1;
accessToVote = 0;
Lcd_Set_Cursor(2,1);
Lcd_Write_String("Thanks for Vote ");
__delay_ms(500);
PORTCbits.RC1 = 0;
}
if(pressBtnOf_B){
PORTDbits.RD0 = 1;
PORTCbits.RC2 = 1;
ttlVotesOf_B += 1;
accessToVote = 0;
Lcd_Set_Cursor(2,1);
Lcd_Write_String("Thanks for Vote ");
__delay_ms(500);
PORTCbits.RC2 = 0;
}
if(pressBtnOf_C){
PORTDbits.RD0 = 1;
PORTCbits.RC3 = 1;
ttlVotesOf_C += 1;
accessToVote = 0;
Lcd_Set_Cursor(2,1);
Lcd_Write_String("Thanks for Vote ");
__delay_ms(500);
PORTCbits.RC3 = 0;
}
sprintf(votes, "A:%d B:%d C:%d", ttlVotesOf_A, ttlVotesOf_B, ttlVotesOf_C);
int a = strlen(votes);
int y = (16 - a > 0)? (16 - a)/2 + 1 : 1;
Lcd_Set_Cursor(1,y);
Lcd_Write_String(votes);
}else{
PORTDbits.RD0 = 0;
PORTDbits.RD1 = 0;
Lcd_Set_Cursor(2,1);
Lcd_Write_String(" Access denied ");
}
}
}
| 32.909091 | 150 | 0.533651 |
3c01059ccfc60d0b3b70033b220fab940291cd4a | 9,335 | c | C | bin/varnishd/mgt/mgt_vcc.c | slimhazard/Varnish-Cache | 2aeb1d36ddd0ca3cec70ff859ddca0ab6e37760f | [
"BSD-2-Clause"
] | null | null | null | bin/varnishd/mgt/mgt_vcc.c | slimhazard/Varnish-Cache | 2aeb1d36ddd0ca3cec70ff859ddca0ab6e37760f | [
"BSD-2-Clause"
] | null | null | null | bin/varnishd/mgt/mgt_vcc.c | slimhazard/Varnish-Cache | 2aeb1d36ddd0ca3cec70ff859ddca0ab6e37760f | [
"BSD-2-Clause"
] | null | null | null | /*-
* Copyright (c) 2006 Verdens Gang AS
* Copyright (c) 2006-2015 Varnish Software AS
* All rights reserved.
*
* Author: Poul-Henning Kamp <phk@phk.freebsd.dk>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* VCL compiler stuff
*/
#include "config.h"
#include <errno.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <sys/stat.h>
#include "mgt/mgt.h"
#include "common/heritage.h"
#include "storage/storage.h"
#include "libvcc.h"
#include "vcli_serve.h"
#include "vfil.h"
#include "vsub.h"
#include "vav.h"
#include "vtim.h"
struct vcc_priv {
unsigned magic;
#define VCC_PRIV_MAGIC 0x70080cb8
char *dir;
const char *vclsrc;
const char *vclsrcfile;
char *csrcfile;
char *libfile;
};
char *mgt_cc_cmd;
const char *mgt_vcl_path;
const char *mgt_vmod_path;
unsigned mgt_vcc_err_unref;
unsigned mgt_vcc_allow_inline_c;
unsigned mgt_vcc_unsafe_path;
#define VGC_SRC "vgc.c"
#define VGC_LIB "vgc.so"
/*--------------------------------------------------------------------*/
void
mgt_DumpBuiltin(void)
{
printf("%s\n", builtin_vcl);
}
/*--------------------------------------------------------------------
* Invoke system VCC compiler in a sub-process
*/
static void v_matchproto_(vsub_func_f)
run_vcc(void *priv)
{
struct vsb *csrc;
struct vsb *sb = NULL;
struct vcc_priv *vp;
int fd, i, l;
struct vcc *vcc;
struct stevedore *stv;
VJ_subproc(JAIL_SUBPROC_VCC);
CAST_OBJ_NOTNULL(vp, priv, VCC_PRIV_MAGIC);
AZ(chdir(vp->dir));
vcc = VCC_New();
AN(vcc);
VCC_Builtin_VCL(vcc, builtin_vcl);
VCC_VCL_path(vcc, mgt_vcl_path);
VCC_VMOD_path(vcc, mgt_vmod_path);
VCC_Err_Unref(vcc, mgt_vcc_err_unref);
VCC_Allow_InlineC(vcc, mgt_vcc_allow_inline_c);
VCC_Unsafe_Path(vcc, mgt_vcc_unsafe_path);
STV_Foreach(stv)
VCC_Predef(vcc, "VCL_STEVEDORE", stv->ident);
mgt_vcl_export_labels(vcc);
csrc = VCC_Compile(vcc, &sb, vp->vclsrc, vp->vclsrcfile);
AZ(VSB_finish(sb));
if (VSB_len(sb))
printf("%s", VSB_data(sb));
VSB_destroy(&sb);
if (csrc == NULL)
exit(2);
fd = open(VGC_SRC, O_WRONLY|O_TRUNC|O_CREAT, 0600);
if (fd < 0) {
fprintf(stderr, "VCC cannot open %s", vp->csrcfile);
exit(2);
}
l = VSB_len(csrc);
i = write(fd, VSB_data(csrc), l);
if (i != l) {
fprintf(stderr, "VCC cannot write %s", vp->csrcfile);
exit(2);
}
closefd(&fd);
VSB_destroy(&csrc);
exit(0);
}
/*--------------------------------------------------------------------
* Invoke system C compiler in a sub-process
*/
static void v_matchproto_(vsub_func_f)
run_cc(void *priv)
{
struct vcc_priv *vp;
struct vsb *sb;
int pct;
char *p;
VJ_subproc(JAIL_SUBPROC_CC);
CAST_OBJ_NOTNULL(vp, priv, VCC_PRIV_MAGIC);
AZ(chdir(vp->dir));
sb = VSB_new_auto();
AN(sb);
for (p = mgt_cc_cmd, pct = 0; *p; ++p) {
if (pct) {
switch (*p) {
case 's':
VSB_cat(sb, VGC_SRC);
break;
case 'o':
VSB_cat(sb, VGC_LIB);
break;
case '%':
VSB_putc(sb, '%');
break;
default:
VSB_putc(sb, '%');
VSB_putc(sb, *p);
break;
}
pct = 0;
} else if (*p == '%') {
pct = 1;
} else {
VSB_putc(sb, *p);
}
}
if (pct)
VSB_putc(sb, '%');
AZ(VSB_finish(sb));
(void)umask(027);
(void)execl("/bin/sh", "/bin/sh", "-c", VSB_data(sb), (char*)0);
VSB_destroy(&sb); // For flexelint
}
/*--------------------------------------------------------------------
* Attempt to open compiled VCL in a sub-process
*/
static void v_matchproto_(vsub_func_f)
run_dlopen(void *priv)
{
struct vcc_priv *vp;
VJ_subproc(JAIL_SUBPROC_VCLLOAD);
CAST_OBJ_NOTNULL(vp, priv, VCC_PRIV_MAGIC);
if (VCL_TestLoad(vp->libfile))
exit(1);
exit(0);
}
/*--------------------------------------------------------------------
* Touch a filename and make it available to privsep-privs
*/
static int
mgt_vcc_touchfile(const char *fn, struct vsb *sb)
{
int i;
i = open(fn, O_WRONLY|O_CREAT|O_TRUNC, 0640);
if (i < 0) {
VSB_printf(sb, "Failed to create %s: %s", fn, strerror(errno));
return (2);
}
if (fchown(i, mgt_param.uid, mgt_param.gid) != 0)
if (geteuid() == 0)
VSB_printf(sb, "Failed to change owner on %s: %s\n",
fn, strerror(errno));
closefd(&i);
return (0);
}
/*--------------------------------------------------------------------
* Compile a VCL program, return shared object, errors in sb.
*/
static unsigned
mgt_vcc_compile(struct vcc_priv *vp, struct vsb *sb, int C_flag)
{
char *csrc;
unsigned subs;
if (mgt_vcc_touchfile(vp->csrcfile, sb))
return (2);
if (mgt_vcc_touchfile(vp->libfile, sb))
return (2);
subs = VSUB_run(sb, run_vcc, vp, "VCC-compiler", -1);
if (subs)
return (subs);
if (C_flag) {
csrc = VFIL_readfile(NULL, vp->csrcfile, NULL);
AN(csrc);
VSB_cat(sb, csrc);
free(csrc);
}
subs = VSUB_run(sb, run_cc, vp, "C-compiler", 10);
if (subs)
return (subs);
subs = VSUB_run(sb, run_dlopen, vp, "dlopen", 10);
return (subs);
}
/*--------------------------------------------------------------------*/
char *
mgt_VccCompile(struct cli *cli, struct vclprog *vcl, const char *vclname,
const char *vclsrc, const char *vclsrcfile, int C_flag)
{
struct vcc_priv vp;
struct vsb *sb;
unsigned status;
char buf[1024];
FILE *fcs;
char **av;
int ac;
AN(cli);
sb = VSB_new_auto();
XXXAN(sb);
INIT_OBJ(&vp, VCC_PRIV_MAGIC);
vp.vclsrc = vclsrc;
vp.vclsrcfile = vclsrcfile;
/*
* The subdirectory must have a unique name to 100% certain evade
* the refcounting semantics of dlopen(3).
*
* Bad implementations of dlopen(3) think the shlib you are opening
* is the same, if the filename is the same as one already opened.
*
* Sensible implementations do a stat(2) and requires st_ino and
* st_dev to also match.
*
* A correct implementation would run on filesystems which tickle
* st_gen, and also insist that be the identical, before declaring
* a match.
*
* Since no correct implementations are known to exist, we are subject
* to really interesting races if you do something like:
*
* (running on 'boot' vcl)
* vcl.load foo /foo.vcl
* vcl.use foo
* few/slow requests
* vcl.use boot
* vcl.discard foo
* vcl.load foo /foo.vcl // dlopen(3) says "same-same"
* vcl.use foo
*
* Because discard of the first 'foo' lingers on non-zero reference
* count, and when it finally runs, it trashes the second 'foo' because
* dlopen(3) decided they were really the same thing.
*
* The Best way to reproduce this is to have regexps in the VCL.
*/
VSB_printf(sb, "vcl_%s.%.9f", vclname, VTIM_real());
AZ(VSB_finish(sb));
vp.dir = strdup(VSB_data(sb));
AN(vp.dir);
if (VJ_make_vcldir(vp.dir)) {
free(vp.dir);
VSB_destroy(&sb);
VCLI_Out(cli, "VCL compilation failed");
VCLI_SetResult(cli, CLIS_PARAM);
return (NULL);
}
VSB_clear(sb);
VSB_printf(sb, "%s/%s", vp.dir, VGC_SRC);
AZ(VSB_finish(sb));
vp.csrcfile = strdup(VSB_data(sb));
AN(vp.csrcfile);
VSB_clear(sb);
VSB_printf(sb, "%s/%s", vp.dir, VGC_LIB);
AZ(VSB_finish(sb));
vp.libfile = strdup(VSB_data(sb));
AN(vp.csrcfile);
VSB_clear(sb);
status = mgt_vcc_compile(&vp, sb, C_flag);
AZ(VSB_finish(sb));
if (VSB_len(sb) > 0)
VCLI_Out(cli, "%s", VSB_data(sb));
VSB_destroy(&sb);
if (status || C_flag) {
(void)unlink(vp.csrcfile);
free(vp.csrcfile);
(void)unlink(vp.libfile);
free(vp.libfile);
(void)rmdir(vp.dir);
free(vp.dir);
if (status) {
VCLI_Out(cli, "VCL compilation failed");
VCLI_SetResult(cli, CLIS_PARAM);
}
return (NULL);
}
fcs = fopen(vp.csrcfile, "r");
AN(fcs);
while (1) {
AN(fgets(buf, sizeof buf, fcs));
if (memcmp(buf, VCC_INFO_PREFIX, strlen(VCC_INFO_PREFIX)))
break;
av = VAV_Parse(buf, &ac, 0);
AN(av);
AZ(av[0]);
AZ(strcmp(av[1], "/*"));
AZ(strcmp(av[ac-1], "*/"));
if (!strcmp(av[3], "VCL"))
mgt_vcl_depends(vcl, av[4]);
else if (!strcmp(av[3], "VMOD"))
mgt_vcl_vmod(vcl, av[4], av[5]);
else
WRONG("Wrong VCCINFO");
VAV_Free(av);
}
AZ(fclose(fcs));
(void)unlink(vp.csrcfile);
free(vp.csrcfile);
free(vp.dir);
VCLI_Out(cli, "VCL compiled.\n");
return (vp.libfile);
}
| 23.813776 | 77 | 0.639743 |
d2dee90560ebf69a464cba89c08bc7368c732613 | 20,002 | c | C | demo/demo.c | monolifed/iqm-demo-c | 33521f8c7eb294c7d6b6413e4dba639993c1a0cd | [
"Info-ZIP"
] | 7 | 2020-03-29T10:58:01.000Z | 2020-10-15T23:58:26.000Z | demo/demo.c | monolifed/iqm-demo-c | 33521f8c7eb294c7d6b6413e4dba639993c1a0cd | [
"Info-ZIP"
] | null | null | null | demo/demo.c | monolifed/iqm-demo-c | 33521f8c7eb294c7d6b6413e4dba639993c1a0cd | [
"Info-ZIP"
] | null | null | null | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <stdarg.h>
#include <math.h>
#include <stdbool.h>
//#include <glad/gl.h>
//#define GLFW_INCLUDE_GLEXT
#include <GLFW/glfw3.h>
#include "iqm.h"
#include "common.h"
#include "stb_easy_font.h"
#define VSYNC 0
#define WINDOW_TITLE "IQM Demo"
extern GLuint loadtexture(const char *name, int clamp);
int FPS = 0;
const char *modelname = "mrfixit.iqm";
char keyinfo[50000];
int keyinfo_numquads = 0;
static void print_keyinfo(float x, float y)
{
char textbuf[256];
snprintf(textbuf, sizeof textbuf,
"MODEL: %s\n"
"---------------\n"
"[A] TURN LEFT\n"
"[D] TURN RIGHT\n"
"[S] MOVE AWAY\n"
"[W] MOVE CLOSER\n"
"[Q] MOVE DOWN\n"
"[E] MOVE UP\n",
modelname);
keyinfo_numquads = stb_easy_font_print(x, y, textbuf, NULL, keyinfo, sizeof keyinfo);
}
static void glprintf(float x, float y, char *format, ...)
{
char textbuf[256];
va_list args;
va_start(args, format);
vsnprintf(textbuf, sizeof textbuf, format, args);
va_end(args);
static char buffer[99999]; // ~500 chars
int num_quads;
num_quads = stb_easy_font_print(x, y, textbuf, NULL, buffer, sizeof buffer);
glVertexPointer(2, GL_FLOAT, 16, buffer);
glDrawArrays(GL_QUADS, 0, num_quads*4);
}
// Note that while this demo stores pointer directly into mesh data in a buffer
// of the entire IQM file's data, it is recommended that you copy the data and
// convert it into a more suitable internal representation for whichever 3D
// engine you use.
uint8_t *meshdata = NULL, *animdata = NULL;
int nummeshes = 0, numtris = 0, numverts = 0, numjoints = 0, numframes = 0, numanims = 0;
iqmtriangle *tris = NULL, *adjacency = NULL;
iqmmesh *meshes = NULL;
GLuint *textures = NULL;
iqmjoint *joints = NULL;
iqmpose *poses = NULL;
iqmanim *anims = NULL;
iqmbounds *bounds = NULL;
mat3x4 *baseframe = NULL, *inversebaseframe = NULL, *outframe = NULL, *frames = NULL;
GLuint notexture = 0;
uint8_t *incolor = NULL;
float *inposition = NULL, *innormal = NULL, *intangent = NULL, *intexcoord = NULL;
uint8_t *inblendindex = NULL, *inblendweight = NULL;
float *outposition = NULL, *outnormal = NULL, *outtangent = NULL, *outbitangent = NULL;
void cleanupiqm()
{
if (textures)
{
glDeleteTextures(nummeshes, textures);
free(textures);
}
if (notexture)
glDeleteTextures(1, ¬exture);
free(baseframe);
free(inversebaseframe);
free(outframe);
free(frames);
free(outposition);
free(outnormal);
free(outtangent);
free(outbitangent);
}
bool loadiqmmeshes(const char *filename, const iqmheader *hdr, uint8_t *buf)
{
if (meshdata)
return false;
leswap32(buf + hdr->ofs_vertexarrays, hdr->num_vertexarrays * sizeof(iqmvertexarray));
leswap32(buf + hdr->ofs_triangles, hdr->num_triangles * sizeof(iqmtriangle));
leswap32(buf + hdr->ofs_meshes, hdr->num_meshes * sizeof(iqmmesh));
leswap32(buf + hdr->ofs_joints, hdr->num_joints * sizeof(iqmjoint));
if (hdr->ofs_adjacency)
leswap32(buf + hdr->ofs_adjacency, hdr->num_triangles * sizeof(iqmtriangle));
meshdata = buf;
nummeshes = hdr->num_meshes;
numtris = hdr->num_triangles;
numverts = hdr->num_vertexes;
numjoints = hdr->num_joints;
outframe = malloc(sizeof(mat3x4) * hdr->num_joints);
textures = malloc(sizeof(GLuint) * nummeshes);
memset(textures, 0, nummeshes * sizeof(GLuint));
outposition = malloc(sizeof(float) * 3 * numverts);
outnormal = malloc(sizeof(float) * 3 * numverts);
outtangent = malloc(sizeof(float) * 3 * numverts);
outbitangent = malloc(sizeof(float) * 3 * numverts);
const char *str = hdr->ofs_text ? (char *) &buf[hdr->ofs_text] : "";
iqmvertexarray *vas = (iqmvertexarray *) &buf[hdr->ofs_vertexarrays];
for (int i = 0; i < (int) hdr->num_vertexarrays; i++)
{
iqmvertexarray *va = vas + i;
switch (va->type)
{
case IQM_POSITION:
if (va->format != IQM_FLOAT || va->size != 3)
return false;
leswap32(buf + va->offset, 3 * hdr->num_vertexes * sizeof(float));
inposition = (float *) &buf[va->offset]; break;
case IQM_NORMAL:
if (va->format != IQM_FLOAT || va->size != 3)
return false;
leswap32(buf + va->offset, 3 * hdr->num_vertexes * sizeof(float));
innormal = (float *) &buf[va->offset]; break;
case IQM_TANGENT:
if (va->format != IQM_FLOAT || va->size != 4)
return false;
leswap32(buf + va->offset, 4 * hdr->num_vertexes * sizeof(float));
intangent = (float *) &buf[va->offset]; break;
case IQM_TEXCOORD:
if (va->format != IQM_FLOAT || va->size != 2)
return false;
leswap32(buf + va->offset, 2 * hdr->num_vertexes * sizeof(float));
intexcoord = (float *) &buf[va->offset]; break;
case IQM_BLENDINDEXES:
if (va->format != IQM_UBYTE || va->size != 4)
return false;
inblendindex = (uint8_t *) &buf[va->offset]; break;
case IQM_BLENDWEIGHTS:
if (va->format != IQM_UBYTE || va->size != 4)
return false;
inblendweight = (uint8_t *) &buf[va->offset]; break;
case IQM_COLOR:
if (va->format != IQM_UBYTE || va->size != 4)
return false;
incolor = (uint8_t *) &buf[va->offset]; break;
}
}
tris = (iqmtriangle *) &buf[hdr->ofs_triangles];
meshes = (iqmmesh *) &buf[hdr->ofs_meshes];
joints = (iqmjoint *) &buf[hdr->ofs_joints];
if (hdr->ofs_adjacency)
adjacency = (iqmtriangle *) &buf[hdr->ofs_adjacency];
baseframe = malloc(sizeof(mat3x4) * hdr->num_joints);
inversebaseframe = malloc(sizeof(mat3x4) * hdr->num_joints);
for (int i = 0; i < (int) hdr->num_joints; i++)
{
iqmjoint *j = joints + i;
mat3x4_from_rst(baseframe[i], j->rotate, j->translate, j->scale);
mat3x4_invert(inversebaseframe[i], baseframe[i]);
if (j->parent >= 0)
{
//tempmat = baseframe[i];
mat3x4_mul(baseframe[i], baseframe[j->parent], baseframe[i]);
mat3x4_mul(inversebaseframe[i], inversebaseframe[i], inversebaseframe[j->parent]);
}
}
for (int i = 0; i < (int) hdr->num_meshes; i++)
{
iqmmesh *m = meshes + i;
printf("%s: loaded mesh: %s\n", filename, &str[m->name]);
textures[i] = loadtexture(&str[m->material], 0);
if (textures[i])
printf("%s: loaded material: %s\n", filename, &str[m->material]);
}
return true;
}
bool loadiqmanims(const char *filename, const iqmheader *hdr, uint8_t *buf)
{
if ((int) hdr->num_poses != numjoints)
return false;
if (animdata)
{
if (animdata != meshdata)
free(animdata);
free(frames);
animdata = NULL;
anims = NULL;
frames = 0;
numframes = 0;
numanims = 0;
}
leswap32(buf + hdr->ofs_poses, hdr->num_poses * sizeof(iqmpose));
leswap32(buf + hdr->ofs_anims, hdr->num_anims * sizeof(iqmanim));
leswap16(buf + hdr->ofs_frames, hdr->num_frames * hdr->num_framechannels * sizeof(uint16_t));
if (hdr->ofs_bounds)
leswap32(buf + hdr->ofs_bounds, hdr->num_frames * sizeof(iqmbounds));
animdata = buf;
numanims = hdr->num_anims;
numframes = hdr->num_frames;
const char *str = hdr->ofs_text ? (char *) &buf[hdr->ofs_text] : "";
anims = (iqmanim *) &buf[hdr->ofs_anims];
poses = (iqmpose *) &buf[hdr->ofs_poses];
frames = malloc(sizeof(mat3x4) * hdr->num_frames * hdr->num_poses);
uint16_t *framedata = (uint16_t *) &buf[hdr->ofs_frames];
if (hdr->ofs_bounds)
bounds = (iqmbounds *) &buf[hdr->ofs_bounds];
mat3x4 mat;
float rotate[4], translate[3], scale[3];
for (int i = 0; i < (int) hdr->num_frames; i++)
{
for (int j = 0; j < (int) hdr->num_poses; j++)
{
iqmpose *p = poses + j;
translate[0] = p->channeloffset[0]; if (p->mask & 0x01) translate[0] += *framedata++ * p->channelscale[0];
translate[1] = p->channeloffset[1]; if (p->mask & 0x02) translate[1] += *framedata++ * p->channelscale[1];
translate[2] = p->channeloffset[2]; if (p->mask & 0x04) translate[2] += *framedata++ * p->channelscale[2];
rotate[0] = p->channeloffset[3]; if (p->mask & 0x08) rotate[0] += *framedata++ * p->channelscale[3];
rotate[1] = p->channeloffset[4]; if (p->mask & 0x10) rotate[1] += *framedata++ * p->channelscale[4];
rotate[2] = p->channeloffset[5]; if (p->mask & 0x20) rotate[2] += *framedata++ * p->channelscale[5];
rotate[3] = p->channeloffset[6]; if (p->mask & 0x40) rotate[3] += *framedata++ * p->channelscale[6];
scale[0] = p->channeloffset[7]; if (p->mask & 0x80) scale[0] += *framedata++ * p->channelscale[7];
scale[1] = p->channeloffset[8]; if (p->mask & 0x100) scale[1] += *framedata++ * p->channelscale[8];
scale[2] = p->channeloffset[9]; if (p->mask & 0x200) scale[2] += *framedata++ * p->channelscale[9];
// Concatenate each pose with the inverse base pose to avoid doing this at animation time.
// If the joint has a parent, then it needs to be pre-concatenated with its parent's base pose.
// Thus it all negates at animation time like so:
// (parentPose * parentInverseBasePose) * (parentBasePose * childPose * childInverseBasePose) =>
// parentPose * (parentInverseBasePose * parentBasePose) * childPose * childInverseBasePose =>
// parentPose * childPose * childInverseBasePose
mat3x4_from_rst(mat, rotate, translate, scale);
if (p->parent >= 0)
{
mat3x4_mul(mat, mat, inversebaseframe[j]);
mat3x4_mul(frames[i * hdr->num_poses + j], baseframe[p->parent], mat);
}
else
{
mat3x4_mul(frames[i * hdr->num_poses + j], mat, inversebaseframe[j]);
}
}
}
for (int i = 0; i < (int) hdr->num_anims; i++)
{
//iqmanim *a = anims + i;
printf("%s: loaded anim: %s\n", filename, &str[anims[i].name]);
}
return true;
}
bool loadiqm(const char *filename)
{
FILE *f = fopen(filename, "rb");
if (!f)
return false;
uint8_t *buf = NULL;
iqmheader hdr;
if (fread(&hdr, 1, sizeof(hdr), f) != sizeof(hdr) || memcmp(hdr.magic, IQM_MAGIC, sizeof(hdr.magic)))
goto error;
leswap32((uint8_t *) &hdr.version, sizeof(hdr) - sizeof(hdr.magic));
if (hdr.version != IQM_VERSION)
goto error;
if (hdr.filesize > (16 << 20))
goto error; // sanity check... don't load files bigger than 16 MB
buf = malloc(sizeof(uint8_t) * hdr.filesize);
if (fread(buf + sizeof(hdr), 1, hdr.filesize - sizeof(hdr), f) != hdr.filesize - sizeof(hdr))
goto error;
if (hdr.num_meshes > 0 && !loadiqmmeshes(filename, &hdr, buf))
goto error;
if (hdr.num_anims > 0 && !loadiqmanims(filename, &hdr, buf))
goto error;
fclose(f);
return true;
error:
printf("%s: error while loading\n", filename);
if (buf != meshdata && buf != animdata)
free(buf);
fclose(f);
return false;
}
// Note that this animates all attributes (position, normal, tangent, bitangent)
// for expository purposes, even though this demo does not use all of them for rendering.
void animateiqm(float curframe)
{
if (numframes <= 0)
return;
int frame1 = (int) floor(curframe),
frame2 = frame1 + 1;
float frameoffset = curframe - frame1;
frame1 %= numframes;
frame2 %= numframes;
mat3x4 *mat1 = &frames[frame1 * numjoints],
*mat2 = &frames[frame2 * numjoints];
// Interpolate matrixes between the two closest frames and concatenate with parent matrix if necessary.
// Concatenate the result with the inverse of the base pose.
// You would normally do animation blending and inter-frame blending here in a 3D engine.
mat3x4 mat;
for (int i = 0; i < numjoints; i++)
{
for (int k = 0; k < 3; k++)
for (int l = 0; l < 4; l++)
mat[k][l] = mat1[i][k][l] * (1 - frameoffset) + mat2[i][k][l] * frameoffset;
if (joints[i].parent >= 0)
mat3x4_mul(outframe[i], outframe[joints[i].parent], mat);
else
memcpy(outframe[i], mat, sizeof(mat3x4));
}
// The actual vertex generation based on the matrixes follows...
const vec3 *srcpos = (const vec3 *) inposition, *srcnorm = (const vec3 *) innormal;
const vec4 *srctan = (const vec4 *) intangent;
vec3 *dstpos = (vec3 *) outposition, *dstnorm = (vec3 *) outnormal, *dsttan = (vec3 *) outtangent, *dstbitan = (vec3 *) outbitangent;
const uint8_t *index = inblendindex, *weight = inblendweight;
mat3x4 matnorm = {0}; // with 0 translation
for (int i = 0; i < numverts; i++)
{
// Blend matrixes for this vertex according to its blend weights.
// the first index/weight is always present, and the weights are
// guaranteed to add up to 255. So if only the first weight is
// presented, you could optimize this case by skipping any weight
// multiplies and intermediate storage of a blended matrix.
// There are only at most 4 weights per vertex, and they are in
// sorted order from highest weight to lowest weight. Weights with
// 0 values, which are always at the end, are unused.
mat3x4_scale(mat, weight[0] / 255.0f, outframe[index[0]]);
for (int j = 1; j < 4 && weight[j]; j++)
mat3x4_scaleadd(mat, weight[j] / 255.0f, outframe[index[j]], mat);
// Transform attributes by the blended matrix.
// Position uses the full 3x4 transformation matrix.
// Normals and tangents only use the 3x3 rotation part
// of the transformation matrix.
vec3_matmul(*dstpos, mat, *srcpos);
// Note that if the matrix includes non-uniform scaling, normal vectors
// must be transformed by the inverse-transpose of the matrix to have the
// correct relative scale. Note that invert(mat) = adjoint(mat)/determinant(mat),
// and since the absolute scale is not important for a vector that will later
// be renormalized, the adjoint-transpose matrix will work fine, which can be
// cheaply generated by 3 cross-products.
//
// If you don't need to use joint scaling in your models, you can simply use the
// upper 3x3 part of the position matrix instead of the adjoint-transpose shown
// here.
vec3_cross(matnorm[0], mat[1], mat[2]);
vec3_cross(matnorm[1], mat[2], mat[0]);
vec3_cross(matnorm[2], mat[0], mat[1]);
vec3_matmul(*dstnorm, matnorm, *srcnorm);
// Note that input tangent data has 4 coordinates,
// so only transform the first 3 as the tangent vector.
//*dsttan = matnorm.transform(Vec3(*srctan));
vec3_matmul(*dsttan, matnorm, *srctan);
// Note that bitangent = cross(normal, tangent) * sign,
// where the sign is stored in the 4th coordinate of the input tangent data.
vec3_cross(*dstbitan, *dstnorm, *dsttan);
vec3_scale(*dstbitan, (*srctan)[3], *dstbitan);
srcpos++;
srcnorm++;
srctan++;
dstpos++;
dstnorm++;
dsttan++;
dstbitan++;
index += 4;
weight += 4;
}
}
float scale = 1, rotate = 0;
vec3 translate = {0, 0, 0};
void renderiqm()
{
static const GLfloat zero[4] = {0, 0, 0, 0};
static const GLfloat one[4] = {1, 1, 1, 1};
static const GLfloat ambientcol[4] = {0.5f, 0.5f, 0.5f, 1};
static const GLfloat diffusecol[4] = {0.5f, 0.5f, 0.5f, 1};
const GLfloat lightdir[4] = {cosf(-M_PI / 3), 0, sinf(-M_PI / 3), 0};
glPushMatrix();
glTranslatef(translate[0] * scale, translate[1] * scale, translate[2] * scale);
glRotatef(rotate, 0, 0, -1);
glScalef(scale, scale, scale);
glLightModelfv(GL_LIGHT_MODEL_AMBIENT, zero);
glMaterialfv(GL_FRONT, GL_SPECULAR, zero);
glMaterialfv(GL_FRONT, GL_EMISSION, zero);
glMaterialfv(GL_FRONT, GL_AMBIENT_AND_DIFFUSE, one);
glLightfv(GL_LIGHT0, GL_SPECULAR, zero);
glLightfv(GL_LIGHT0, GL_AMBIENT, ambientcol);
glLightfv(GL_LIGHT0, GL_DIFFUSE, diffusecol);
glLightfv(GL_LIGHT0, GL_POSITION, lightdir);
glEnable(GL_LIGHTING);
glEnable(GL_LIGHT0);
glEnable(GL_NORMALIZE);
glColor3f(1, 1, 1);
glVertexPointer(3, GL_FLOAT, 0, numframes > 0 ? outposition : inposition);
glNormalPointer(GL_FLOAT, 0, numframes > 0 ? outnormal : innormal);
glTexCoordPointer(2, GL_FLOAT, 0, intexcoord);
glEnableClientState(GL_VERTEX_ARRAY);
glEnableClientState(GL_NORMAL_ARRAY);
glEnableClientState(GL_TEXTURE_COORD_ARRAY);
if (incolor)
{
glColorPointer(4, GL_UNSIGNED_BYTE, 0, incolor);
glEnableClientState(GL_COLOR_ARRAY);
}
glEnable(GL_TEXTURE_2D);
for (int i = 0; i < nummeshes; i++)
{
iqmmesh *m = meshes + i;
glBindTexture(GL_TEXTURE_2D, textures[i] ? textures[i] : notexture);
glDrawElements(GL_TRIANGLES, 3 * m->num_triangles, GL_UNSIGNED_INT, &tris[m->first_triangle]);
}
glDisable(GL_TEXTURE_2D);
glDisableClientState(GL_VERTEX_ARRAY);
glDisableClientState(GL_NORMAL_ARRAY);
glDisableClientState(GL_TEXTURE_COORD_ARRAY);
if (incolor)
glDisableClientState(GL_COLOR_ARRAY);
glDisable(GL_NORMALIZE);
glDisable(GL_LIGHT0);
glDisable(GL_LIGHTING);
glPopMatrix();
}
void initgl()
{
glClearColor(0.2, 0.2, 0.2, 0);
glClearDepth(1);
glDisable(GL_FOG);
glEnable(GL_DEPTH_TEST);
glDepthFunc(GL_LESS);
glEnable(GL_CULL_FACE);
glCullFace(GL_BACK);
notexture = loadtexture("notexture.tga", 0);
}
int scrw = 0, scrh = 0;
void reshapefunc(int w, int h)
{
scrw = w;
scrh = h;
glViewport(0, 0, w, h);
}
float camyaw = -90, campitch = 0, camroll = 0;
vec3 campos = {10, 0, 5};
void setupcamera()
{
glMatrixMode(GL_PROJECTION);
glLoadIdentity();
GLdouble aspect = ((double) scrw) / scrh,
fov = M_PI / 2,
fovy = 2 * atan2(tan(fov / 2), aspect),
nearplane = 1e-2f, farplane = 1000,
ydist = nearplane * tan(fovy / 2), xdist = ydist * aspect;
glFrustum(-xdist, xdist, -ydist, ydist, nearplane, farplane);
glMatrixMode(GL_MODELVIEW);
glLoadIdentity();
glRotatef(camroll, 0, 0, 1);
glRotatef(campitch, -1, 0, 0);
glRotatef(camyaw, 0, 1, 0);
glRotatef(-90, 1, 0, 0);
glScalef(1, -1, 1);
glTranslatef(-campos[0], -campos[1], -campos[2]);
}
float animate = 0;
void timerfunc(float dt)
{
animate += dt;
}
void drawui()
{
glMatrixMode(GL_PROJECTION);
glLoadIdentity();
glOrtho(0, scrw, scrh, 0, -100, 100);
glMatrixMode(GL_MODELVIEW);
glLoadIdentity();
glEnableClientState(GL_VERTEX_ARRAY);
glColor4f(1, 1, 1, 1);
glprintf(5, 5, "FPS: %i", FPS);
glVertexPointer(2, GL_FLOAT, 16, keyinfo);
glDrawArrays(GL_QUADS, 0, keyinfo_numquads * 4);
glDisableClientState(GL_VERTEX_ARRAY);
}
void displayfunc(GLFWwindow *window)
{
glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT);
setupcamera();
animateiqm(animate);
renderiqm();
drawui();
#if VSYNC == 0
(void) window;
glFlush();
#else
glfwSwapBuffers(window);
#endif
}
static void keycallback(GLFWwindow *window, int key, int scancode, int action, int mods)
{
(void) scancode; (void) mods;
if (key == GLFW_KEY_ESCAPE && action == GLFW_PRESS)
{
glfwSetWindowShouldClose(window, GLFW_TRUE);
return;
}
if (action == GLFW_REPEAT)
{
switch(key)
{
case GLFW_KEY_A: rotate -= 5; break;
case GLFW_KEY_D: rotate += 5; break;
case GLFW_KEY_S: translate[0] -= .1; break;
case GLFW_KEY_W: translate[0] += .1; break;
case GLFW_KEY_Q: translate[2] -= .1; break;
case GLFW_KEY_E: translate[2] += .1; break;
}
}
}
static void errcallback(int errid, const char *errtext)
{
(void) errid;
fprintf(stderr, "Error: %s\n", errtext);
}
int main(int argc, char **argv)
{
(void) argc; (void) argv;
if (!glfwInit())
return EXIT_FAILURE;
glfwSetErrorCallback(errcallback);
#if VSYNC == 0
glfwWindowHint(GLFW_DOUBLEBUFFER, GLFW_FALSE);
#else
glfwWindowHint(GLFW_DOUBLEBUFFER, GLFW_TRUE);
#endif
//glfwWindowHint(GLFW_DEPTH_BITS, 24);
glfwWindowHint(GLFW_CONTEXT_VERSION_MAJOR, 2);
glfwWindowHint(GLFW_CONTEXT_VERSION_MINOR, 1);
GLFWwindow *window = glfwCreateWindow(640, 480, WINDOW_TITLE, NULL, NULL);
if (!window)
{
glfwTerminate();
return EXIT_FAILURE;
}
glfwSetKeyCallback(window, keycallback);
glfwMakeContextCurrent(window);
//gladLoadGL(glfwGetProcAddress);
glfwSwapInterval(1);
//loadexts();
atexit(cleanupiqm);
if (!meshdata && !loadiqm(modelname))
return EXIT_FAILURE;
print_keyinfo(5, 25);
initgl();
int framecount = 0;
double curtime = 0, prevtime = 0, dt = 0;
while (!glfwWindowShouldClose(window))
{
dt = curtime;
curtime = glfwGetTime();
dt = curtime - dt;
framecount++;
if (curtime - prevtime >= 1.0)
{
FPS = framecount;
framecount = 0;
prevtime = curtime;
}
int width, height;
glfwGetFramebufferSize(window, &width, &height);
timerfunc(dt * 24);
reshapefunc(width, height);
displayfunc(window);
glfwPollEvents();
}
glfwDestroyWindow(window);
glfwTerminate();
return EXIT_SUCCESS;
}
| 30.398176 | 134 | 0.674083 |
cf546672b01914301397773042c3d30c04a58871 | 794 | h | C | System/Library/PrivateFrameworks/C2.framework/C2SessionCallbackMetrics.h | lechium/tvOS142Headers | c7696f6d760e4822f61b9f2c2adcd18749700fda | [
"MIT"
] | 1 | 2020-11-11T06:05:23.000Z | 2020-11-11T06:05:23.000Z | System/Library/PrivateFrameworks/C2.framework/C2SessionCallbackMetrics.h | lechium/tvOS142Headers | c7696f6d760e4822f61b9f2c2adcd18749700fda | [
"MIT"
] | null | null | null | System/Library/PrivateFrameworks/C2.framework/C2SessionCallbackMetrics.h | lechium/tvOS142Headers | c7696f6d760e4822f61b9f2c2adcd18749700fda | [
"MIT"
] | null | null | null | /*
* This header is generated by classdump-dyld 1.5
* on Tuesday, November 10, 2020 at 10:20:00 PM Mountain Standard Time
* Operating System: Version 14.2 (Build 18K57)
* Image Source: /System/Library/PrivateFrameworks/C2.framework/C2
* classdump-dyld is licensed under GPLv3, Copyright © 2013-2016 by Elias Limneos. Updated by Kevin Bradley.
*/
@interface C2SessionCallbackMetrics : NSObject {
unsigned long long _startTime;
}
@property (assign,nonatomic) unsigned long long startTime; //@synthesize startTime=_startTime - In the implementation block
-(unsigned long long)startTime;
-(void)setStartTime:(unsigned long long)arg1 ;
@end
| 37.809524 | 136 | 0.625945 |
cf1b8b68734bd53231e9aa4c5d074f039d6856e7 | 457 | h | C | cpp/include/TreeLinkNode.h | qianbinbin/leetcode | 915cecab0c940cd13847683ec55b17b77eb0f39b | [
"MIT"
] | 4 | 2018-03-05T02:27:16.000Z | 2021-03-15T14:19:44.000Z | cpp/include/TreeLinkNode.h | qianbinbin/leetcode | 915cecab0c940cd13847683ec55b17b77eb0f39b | [
"MIT"
] | null | null | null | cpp/include/TreeLinkNode.h | qianbinbin/leetcode | 915cecab0c940cd13847683ec55b17b77eb0f39b | [
"MIT"
] | 2 | 2018-07-22T10:32:10.000Z | 2018-10-20T03:14:28.000Z | #ifndef LEETCODECPP_NODE_H
#define LEETCODECPP_NODE_H
namespace lcpp {
class TreeLinkNode {
public:
int val;
TreeLinkNode *left;
TreeLinkNode *right;
TreeLinkNode *next;
TreeLinkNode() = default;
TreeLinkNode(int _val,
TreeLinkNode *_left,
TreeLinkNode *_right,
TreeLinkNode *_next) {
val = _val;
left = _left;
right = _right;
next = _next;
}
};
}
#endif //LEETCODECPP_NODE_H
| 15.758621 | 37 | 0.630197 |
65bb80a3e98321836778fadb8b49cceb54126870 | 6,027 | c | C | MyApps/ShowRNG/ShowRNG.c | Albert-JF-Lee/UEFI-Utilities-2016 | 71ce611753c2960e5e7ceb5cc23a5faaa95fbf9f | [
"BSD-2-Clause"
] | 39 | 2016-06-20T17:23:48.000Z | 2022-02-15T02:57:45.000Z | MyApps/ShowRNG/ShowRNG.c | Albert-JF-Lee/UEFI-Utilities-2016 | 71ce611753c2960e5e7ceb5cc23a5faaa95fbf9f | [
"BSD-2-Clause"
] | null | null | null | MyApps/ShowRNG/ShowRNG.c | Albert-JF-Lee/UEFI-Utilities-2016 | 71ce611753c2960e5e7ceb5cc23a5faaa95fbf9f | [
"BSD-2-Clause"
] | 19 | 2016-03-31T07:21:01.000Z | 2021-08-24T22:19:49.000Z | //
// Copyright (c) 2016 Finnbarr P. Murphy. All rights reserved.
//
// Display UEFI RNG (Random Number Generator) algorithm information
//
// License: BSD License
//
#include <Uefi.h>
#include <Uefi/UefiSpec.h>
#include <Guid/GlobalVariable.h>
#include <Library/UefiLib.h>
#include <Library/ShellCEntryLib.h>
#include <Library/ShellLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Protocol/EfiShell.h>
#include <Protocol/LoadedImage.h>
#include <Protocol/Rng.h>
#define UTILITY_VERSION L"0.1"
#undef DEBUG
// from Microsoft document - not part of EDK2 at present!
#define EFI_RNG_SERVICE_BINDING_PROTOCOL_GUID \
{0xe417a4a2, 0x0843, 0x4619, {0xbf, 0x11, 0x5c, 0xe8, 0x2a, 0xfc, 0xfc, 0x59}}
#define EFI_RNG_ALGORITHM_RAW_GUID \
{0xe43176d7, 0xb6e8, 0x4827, {0xb7, 0x84, 0x7f, 0xfd, 0xc4, 0xb6, 0x85, 0x61 }}
EFI_GUID gEfiRngAlgorithmRawGuid = EFI_RNG_ALGORITHM_RAW_GUID;
EFI_GUID gEfiRngAlgorithmSp80090Ctr256Guid = EFI_RNG_ALGORITHM_SP800_90_CTR_256_GUID;
VOID
PrintAlg(EFI_RNG_ALGORITHM *RngAlg)
{
Print (L"%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x ", RngAlg->Data1,
RngAlg->Data2, RngAlg->Data3, RngAlg->Data4[0], RngAlg->Data4[1],
RngAlg->Data4[2], RngAlg->Data4[3], RngAlg->Data4[4],
RngAlg->Data4[5], RngAlg->Data4[6], RngAlg->Data4[7]);
if (CompareGuid(RngAlg, &gEfiRngAlgorithmRawGuid)) {
Print(L"Raw");
}
if (CompareGuid(RngAlg, &gEfiRngAlgorithmSp80090Ctr256Guid)) {
Print(L"NIST SP800-90 AES-CTR-256");
}
// Add other algorithm here when implemented in EDK2
}
EFI_STATUS
PrintDeviceRng( UINTN Index,
EFI_RNG_PROTOCOL *Rng)
{
EFI_STATUS Status = EFI_SUCCESS;
EFI_RNG_ALGORITHM RngAlgList[10];
EFI_RNG_ALGORITHM *RngAlg;
UINTN RngAlgCount = 0;
UINTN RngAlgListSize = 0;
UINT8 *Rand;
UINTN RandSize = 32;
Status = Rng->GetInfo( Rng,
&RngAlgListSize,
RngAlgList);
if (Status != EFI_BUFFER_TOO_SMALL) {
Print (L"ERROR: Rng->GetInfo [%n]\n", Status);
return Status;
}
#ifdef DEBUG
Print(L"Rng->GetInfo Size: %d %d\n", RngAlgListSize, sizeof(EFI_RNG_ALGORITHM));
#endif
RngAlgCount = RngAlgListSize / sizeof(EFI_RNG_ALGORITHM);
if (RngAlgCount == 0) {
//
// This is a hack for poor IBV firmware on Lenovo T450
//
Rand = AllocatePool(RandSize);
if (Rand == NULL) {
Print (L"ERROR: AllocatePool\n");
return Status;
}
Status = Rng->GetRNG(Rng, NULL, RandSize, Rand);
FreePool(Rand);
if (EFI_ERROR (Status)) {
Print (L"ERROR: GetRNG default failed [%d]", Status);
return Status;
}
Print (L"Device: %d Number of supported algorithms: %d\n", Index, 1);
Print (L"\n %d) ", 1);
PrintAlg((EFI_RNG_ALGORITHM *)&gEfiRngAlgorithmRawGuid);
} else {
Print (L"Device: %d Number of supported algorithms: %d\n", Index, RngAlgCount);
Status = Rng->GetInfo (Rng, &RngAlgListSize, RngAlgList);
if (EFI_ERROR (Status)) {
Print (L"ERROR: GetInfo failed [%d]", Status);
return Status;
}
for (int index = 0; index < RngAlgCount; index++) {
RngAlg = (EFI_RNG_ALGORITHM *)(&RngAlgList[index]);
Print (L"\n %d) ", index);
PrintAlg(RngAlg);
}
}
Print (L"\n\n");
return Status;
}
VOID
Usage(CHAR16 *Str)
{
Print(L"Usage: %s [-V|--version]\n", Str);
}
INTN
EFIAPI
ShellAppMain(UINTN Argc, CHAR16 **Argv)
{
EFI_GUID gEfiRngProtocolGuid = EFI_RNG_PROTOCOL_GUID;
EFI_GUID gEfiRngServiceProtocolGuid = EFI_RNG_SERVICE_BINDING_PROTOCOL_GUID;
EFI_STATUS Status = EFI_SUCCESS;
EFI_RNG_PROTOCOL *Rng;
EFI_HANDLE *HandleBuffer;
UINTN HandleCount = 0;
if (Argc == 2) {
if (!StrCmp(Argv[1], L"--version") ||
!StrCmp(Argv[1], L"-V")) {
Print(L"Version: %s\n", UTILITY_VERSION);
return Status;
}
if (!StrCmp(Argv[1], L"--help") ||
!StrCmp(Argv[1], L"-h") ||
!StrCmp(Argv[1], L"-?")) {
Usage(Argv[0]);
return Status;
}
}
// catchall for all other cases
if (Argc > 1) {
Usage(Argv[0]);
return Status;
}
// Try locating EFI_RNG_SERVICE_BINDING handles
Status = gBS->LocateHandleBuffer( ByProtocol,
&gEfiRngServiceProtocolGuid,
NULL,
&HandleCount,
&HandleBuffer);
if (EFI_ERROR (Status)) {
Print(L"No EFI_RNG_SERVICE_BINDING_PROTOCOL handles found");
} else {
Print(L"RNG service binding protocol handles found [%d]", HandleCount);
}
Print(L"\n\n");
// Try locating EFI_RNG_PROTOCOL handles
Status = gBS->LocateHandleBuffer( ByProtocol,
&gEfiRngProtocolGuid,
NULL,
&HandleCount,
&HandleBuffer);
if (EFI_ERROR (Status) || HandleCount == 0 ) {
Print(L"ERROR: No EFI_RNG_PROTOCOL handles found\n");
return Status;
}
#ifdef DEBUG
Print(L"RNG protocol found [%d]\n", HandleCount);
#endif
for (int Index = 0; Index < HandleCount; Index++) {
Status = gBS->HandleProtocol( HandleBuffer[Index],
&gEfiRngProtocolGuid,
(VOID*) &Rng);
if (!EFI_ERROR (Status)) {
PrintDeviceRng(Index, Rng);
} else {
Print(L"ERROR: HandleProtocol [%d]\n", Status);
}
}
FreePool(HandleBuffer);
return EFI_SUCCESS;
}
| 28.7 | 88 | 0.574415 |
6807186566a0788634aef63b8a719a28539b7baa | 12,508 | h | C | 3rd/include/gstreamer-1.0/gst/gstplugin.h | dieqms/imx6q_qplayer | 41ddd37f4d64aff8acbeb170f13129ab7cfd7aee | [
"MIT"
] | 4 | 2018-07-01T15:08:14.000Z | 2021-08-13T05:00:05.000Z | 3rd/include/gstreamer-1.0/gst/gstplugin.h | dieqms/imx6q_qplayer | 41ddd37f4d64aff8acbeb170f13129ab7cfd7aee | [
"MIT"
] | null | null | null | 3rd/include/gstreamer-1.0/gst/gstplugin.h | dieqms/imx6q_qplayer | 41ddd37f4d64aff8acbeb170f13129ab7cfd7aee | [
"MIT"
] | 2 | 2018-07-13T04:06:10.000Z | 2021-08-13T05:00:07.000Z | /* GStreamer
* Copyright (C) 1999,2000 Erik Walthinsen <omega@cse.ogi.edu>
* 2000 Wim Taymans <wtay@chello.be>
*
* gstplugin.h: Header for plugin subsystem
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Library General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Library General Public License for more details.
*
* You should have received a copy of the GNU Library General Public
* License along with this library; if not, write to the
* Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 02111-1307, USA.
*/
#ifndef __GST_PLUGIN_H__
#define __GST_PLUGIN_H__
#include <gst/gstconfig.h>
#include <gst/gstobject.h>
#include <gst/gstmacros.h>
#include <gst/gststructure.h>
G_BEGIN_DECLS
/**
* GstPlugin:
*
* The opaque plugin object
*/
typedef struct _GstPlugin GstPlugin;
typedef struct _GstPluginClass GstPluginClass;
typedef struct _GstPluginDesc GstPluginDesc;
/**
* gst_plugin_error_quark:
*
* Get the error quark.
*
* Returns: The error quark used in GError messages
*/
GQuark gst_plugin_error_quark (void);
/**
* GST_PLUGIN_ERROR:
*
* The error message category quark
*/
#define GST_PLUGIN_ERROR gst_plugin_error_quark ()
/**
* GstPluginError:
* @GST_PLUGIN_ERROR_MODULE: The plugin could not be loaded
* @GST_PLUGIN_ERROR_DEPENDENCIES: The plugin has unresolved dependencies
* @GST_PLUGIN_ERROR_NAME_MISMATCH: The plugin has already be loaded from a different file
*
* The plugin loading errors
*/
typedef enum
{
GST_PLUGIN_ERROR_MODULE,
GST_PLUGIN_ERROR_DEPENDENCIES,
GST_PLUGIN_ERROR_NAME_MISMATCH
} GstPluginError;
/**
* GstPluginFlags:
* @GST_PLUGIN_FLAG_CACHED: Temporarily loaded plugins
* @GST_PLUGIN_FLAG_BLACKLISTED: The plugin won't be scanned (again)
*
* The plugin loading state
*/
typedef enum
{
GST_PLUGIN_FLAG_CACHED = (GST_OBJECT_FLAG_LAST << 0),
GST_PLUGIN_FLAG_BLACKLISTED = (GST_OBJECT_FLAG_LAST << 1)
} GstPluginFlags;
/**
* GstPluginDependencyFlags:
* @GST_PLUGIN_DEPENDENCY_FLAG_NONE : no special flags
* @GST_PLUGIN_DEPENDENCY_FLAG_RECURSE : recurse into subdirectories
* @GST_PLUGIN_DEPENDENCY_FLAG_PATHS_ARE_DEFAULT_ONLY : use paths
* argument only if none of the environment variables is set
* @GST_PLUGIN_DEPENDENCY_FLAG_FILE_NAME_IS_SUFFIX : interpret
* filename argument as filter suffix and check all matching files in
* the directory
*
* Flags used in connection with gst_plugin_add_dependency().
*/
typedef enum {
GST_PLUGIN_DEPENDENCY_FLAG_NONE = 0,
GST_PLUGIN_DEPENDENCY_FLAG_RECURSE = (1 << 0),
GST_PLUGIN_DEPENDENCY_FLAG_PATHS_ARE_DEFAULT_ONLY = (1 << 1),
GST_PLUGIN_DEPENDENCY_FLAG_FILE_NAME_IS_SUFFIX = (1 << 2)
} GstPluginDependencyFlags;
/**
* GstPluginInitFunc:
* @plugin: The plugin object
*
* A plugin should provide a pointer to a function of this type in the
* plugin_desc struct.
* This function will be called by the loader at startup. One would then
* register each #GstPluginFeature.
*
* Returns: %TRUE if plugin initialised successfully
*/
/* FIXME 0.11: Make return void */
typedef gboolean (*GstPluginInitFunc) (GstPlugin *plugin);
/**
* GstPluginInitFullFunc:
* @plugin: The plugin object
* @user_data: extra data
*
* A plugin should provide a pointer to a function of either #GstPluginInitFunc
* or this type in the plugin_desc struct.
* The function will be called by the loader at startup. One would then
* register each #GstPluginFeature. This version allows
* user data to be passed to init function (useful for bindings).
*
* Returns: %TRUE if plugin initialised successfully
*/
/* FIXME 0.11: Merge with GstPluginInitFunc */
typedef gboolean (*GstPluginInitFullFunc) (GstPlugin *plugin, gpointer user_data);
/**
* GstPluginDesc:
* @major_version: the major version number of core that plugin was compiled for
* @minor_version: the minor version number of core that plugin was compiled for
* @name: a unique name of the plugin
* @description: description of plugin
* @plugin_init: pointer to the init function of this plugin.
* @version: version of the plugin
* @license: effective license of plugin
* @source: source module plugin belongs to
* @package: shipped package plugin belongs to
* @origin: URL to provider of plugin
* @release_datetime: date time string in ISO 8601 format (or rather, a
* subset thereof), or NULL. Allowed are the following formats:
* "YYYY-MM-DD" and "YYY-MM-DDTHH:MMZ" (with 'T' a separator and 'Z'
* indicating UTC/Zulu time). This field should be set via the
* GST_PACKAGE_RELEASE_DATETIME preprocessor macro.
*
* A plugin should export a variable of this type called plugin_desc. The plugin
* loader will use the data provided there to initialize the plugin.
*
* The @licence parameter must be one of: LGPL, GPL, QPL, GPL/QPL, MPL,
* BSD, MIT/X11, Proprietary, unknown.
*/
struct _GstPluginDesc {
gint major_version;
gint minor_version;
const gchar *name;
const gchar *description;
GstPluginInitFunc plugin_init;
const gchar *version;
const gchar *license;
const gchar *source;
const gchar *package;
const gchar *origin;
const gchar *release_datetime;
/*< private >*/
gpointer _gst_reserved[GST_PADDING];
};
#define GST_TYPE_PLUGIN (gst_plugin_get_type())
#define GST_IS_PLUGIN(obj) (G_TYPE_CHECK_INSTANCE_TYPE ((obj), GST_TYPE_PLUGIN))
#define GST_IS_PLUGIN_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE ((klass), GST_TYPE_PLUGIN))
#define GST_PLUGIN_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS ((obj), GST_TYPE_PLUGIN, GstPluginClass))
#define GST_PLUGIN(obj) (G_TYPE_CHECK_INSTANCE_CAST ((obj), GST_TYPE_PLUGIN, GstPlugin))
#define GST_PLUGIN_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST ((klass), GST_TYPE_PLUGIN, GstPluginClass))
#define GST_PLUGIN_CAST(obj) ((GstPlugin*)(obj))
#ifdef GST_PACKAGE_RELEASE_DATETIME
#define __GST_PACKAGE_RELEASE_DATETIME GST_PACKAGE_RELEASE_DATETIME
#else
#define __GST_PACKAGE_RELEASE_DATETIME NULL
#endif
/**
* GST_PLUGIN_DEFINE:
* @major: major version number of the gstreamer-core that plugin was compiled for
* @minor: minor version number of the gstreamer-core that plugin was compiled for
* @name: short, but unique name of the plugin
* @description: information about the purpose of the plugin
* @init: function pointer to the plugin_init method with the signature of <code>static gboolean plugin_init (GstPlugin * plugin)</code>.
* @version: full version string (e.g. VERSION from config.h)
* @license: under which licence the package has been released, e.g. GPL, LGPL.
* @package: the package-name (e.g. PACKAGE_NAME from config.h)
* @origin: a description from where the package comes from (e.g. the homepage URL)
*
* This macro needs to be used to define the entry point and meta data of a
* plugin. One would use this macro to export a plugin, so that it can be used
* by other applications.
*
* The macro uses a define named PACKAGE for the #GstPluginDesc,source field.
* When using autoconf, this is usually set automatically via the AC_INIT
* macro, and set in config.h. If you are not using autoconf, you will need to
* define PACKAGE yourself and set it to a short mnemonic string identifying
* your application/package, e.g. 'someapp' or 'my-plugins-foo.
*
* If defined, the GST_PACKAGE_RELEASE_DATETIME will also be used for the
* #GstPluginDesc,release_datetime field.
*/
#define GST_PLUGIN_DEFINE(major,minor,name,description,init,version,license,package,origin) \
G_BEGIN_DECLS \
GST_PLUGIN_EXPORT GstPluginDesc gst_plugin_desc = { \
major, \
minor, \
#name, \
(gchar *) description, \
init, \
version, \
license, \
PACKAGE, \
package, \
origin, \
__GST_PACKAGE_RELEASE_DATETIME, \
GST_PADDING_INIT \
}; \
G_END_DECLS
/**
* GST_LICENSE_UNKNOWN:
*
* To be used in GST_PLUGIN_DEFINE if usure about the licence.
*/
#define GST_LICENSE_UNKNOWN "unknown"
/* function for filters */
/**
* GstPluginFilter:
* @plugin: the plugin to check
* @user_data: the user_data that has been passed on e.g. gst_registry_plugin_filter()
*
* A function that can be used with e.g. gst_registry_plugin_filter()
* to get a list of plugins that match certain criteria.
*
* Returns: TRUE for a positive match, FALSE otherwise
*/
typedef gboolean (*GstPluginFilter) (GstPlugin *plugin,
gpointer user_data);
GType gst_plugin_get_type (void);
gboolean gst_plugin_register_static (gint major_version,
gint minor_version,
const gchar *name,
const gchar *description,
GstPluginInitFunc init_func,
const gchar *version,
const gchar *license,
const gchar *source,
const gchar *package,
const gchar *origin);
gboolean gst_plugin_register_static_full (gint major_version,
gint minor_version,
const gchar *name,
const gchar *description,
GstPluginInitFullFunc init_full_func,
const gchar *version,
const gchar *license,
const gchar *source,
const gchar *package,
const gchar *origin,
gpointer user_data);
const gchar* gst_plugin_get_name (GstPlugin *plugin);
const gchar* gst_plugin_get_description (GstPlugin *plugin);
const gchar* gst_plugin_get_filename (GstPlugin *plugin);
const gchar* gst_plugin_get_version (GstPlugin *plugin);
const gchar* gst_plugin_get_license (GstPlugin *plugin);
const gchar* gst_plugin_get_source (GstPlugin *plugin);
const gchar* gst_plugin_get_package (GstPlugin *plugin);
const gchar* gst_plugin_get_origin (GstPlugin *plugin);
const gchar* gst_plugin_get_release_date_string (GstPlugin *plugin);
const GstStructure* gst_plugin_get_cache_data (GstPlugin * plugin);
void gst_plugin_set_cache_data (GstPlugin * plugin, GstStructure *cache_data);
gboolean gst_plugin_is_loaded (GstPlugin *plugin);
GstPlugin * gst_plugin_load_file (const gchar *filename, GError** error);
GstPlugin * gst_plugin_load (GstPlugin *plugin);
GstPlugin * gst_plugin_load_by_name (const gchar *name);
void gst_plugin_add_dependency (GstPlugin * plugin,
const gchar ** env_vars,
const gchar ** paths,
const gchar ** names,
GstPluginDependencyFlags flags);
void gst_plugin_add_dependency_simple (GstPlugin * plugin,
const gchar * env_vars,
const gchar * paths,
const gchar * names,
GstPluginDependencyFlags flags);
void gst_plugin_list_free (GList *list);
G_END_DECLS
#endif /* __GST_PLUGIN_H__ */
| 39.582278 | 137 | 0.645667 |
65651d9a9c604417921c0798532ea62c5aad1985 | 1,909 | h | C | Firestore/core/test/unit/testutil/view_testing.h | kentanakae/firebase-ios-sdk | 9f39fdccc309c8e3207a2e6ae4422c5930ff7084 | [
"Apache-2.0"
] | 3,807 | 2017-05-17T20:07:20.000Z | 2022-03-31T12:41:24.000Z | Firestore/core/test/unit/testutil/view_testing.h | kentanakae/firebase-ios-sdk | 9f39fdccc309c8e3207a2e6ae4422c5930ff7084 | [
"Apache-2.0"
] | 6,256 | 2017-05-17T20:14:21.000Z | 2022-03-31T21:41:51.000Z | Firestore/core/test/unit/testutil/view_testing.h | kentanakae/firebase-ios-sdk | 9f39fdccc309c8e3207a2e6ae4422c5930ff7084 | [
"Apache-2.0"
] | 1,246 | 2017-05-18T00:30:26.000Z | 2022-03-31T17:47:09.000Z | /*
* Copyright 2019 Google
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef FIRESTORE_CORE_TEST_UNIT_TESTUTIL_VIEW_TESTING_H_
#define FIRESTORE_CORE_TEST_UNIT_TESTUTIL_VIEW_TESTING_H_
#include <initializer_list>
#include <vector>
#include "Firestore/core/src/core/core_fwd.h"
#include "Firestore/core/src/model/model_fwd.h"
#include "absl/types/optional.h"
namespace firebase {
namespace firestore {
namespace remote {
class TargetChange;
} // namespace remote
namespace testutil {
/** Converts a list of documents to a sorted map. */
model::DocumentMap DocUpdates(const std::vector<model::Document>& docs);
/**
* Computes changes to the view with the docs and then applies them and returns
* the snapshot.
*/
absl::optional<core::ViewSnapshot> ApplyChanges(
core::View* view,
const std::vector<model::Document>& docs,
const absl::optional<remote::TargetChange>& target_change);
/**
* Creates a test target change that acks all 'docs' and marks the target as
* CURRENT.
*/
remote::TargetChange AckTarget(model::DocumentKeySet docs);
remote::TargetChange AckTarget(std::initializer_list<model::Document> docs);
/** Creates a test target change that marks the target as CURRENT */
remote::TargetChange MarkCurrent();
} // namespace testutil
} // namespace firestore
} // namespace firebase
#endif // FIRESTORE_CORE_TEST_UNIT_TESTUTIL_VIEW_TESTING_H_
| 29.828125 | 79 | 0.754845 |
a26a98c1f2f645a5d64fc1479dca78d11d052315 | 322 | h | C | projects/PointerPlay/PointerPlay/Student.h | baykamsay/cs-201 | e8e2083748643a2bd4eed313ebb73c652d525a50 | [
"MIT"
] | null | null | null | projects/PointerPlay/PointerPlay/Student.h | baykamsay/cs-201 | e8e2083748643a2bd4eed313ebb73c652d525a50 | [
"MIT"
] | null | null | null | projects/PointerPlay/PointerPlay/Student.h | baykamsay/cs-201 | e8e2083748643a2bd4eed313ebb73c652d525a50 | [
"MIT"
] | null | null | null | #ifndef __STUDENT_H
#define __STUDENT_H
#include <iostream>
using namespace std;
class Student {
int id;
string name;
string dep;
void setName(string s);
public:
Student(int id, string name);
int getId();
string getName();
string getDep();
void setDep(string s);
void setId(int i);
};
#endif // !__STUDENT_H
| 14 | 30 | 0.704969 |
a2bdedb79d801b46a33966d69ab5ac250f449eaa | 8,162 | h | C | src/prod/src/Transport/SecurityContextSsl.h | vishnuk007/service-fabric | d0afdea185ae932cc3c9eacf179692e6fddbc630 | [
"MIT"
] | 2,542 | 2018-03-14T21:56:12.000Z | 2019-05-06T01:18:20.000Z | src/prod/src/Transport/SecurityContextSsl.h | vishnuk007/service-fabric | d0afdea185ae932cc3c9eacf179692e6fddbc630 | [
"MIT"
] | 994 | 2019-05-07T02:39:30.000Z | 2022-03-31T13:23:04.000Z | src/prod/src/Transport/SecurityContextSsl.h | vishnuk007/service-fabric | d0afdea185ae932cc3c9eacf179692e6fddbc630 | [
"MIT"
] | 300 | 2018-03-14T21:57:17.000Z | 2019-05-06T20:07:00.000Z | // ------------------------------------------------------------
// Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License (MIT). See License.txt in the repo root for license information.
// ------------------------------------------------------------
#pragma once
namespace Transport
{
class SecurityContextSsl : public SecurityContext
{
public:
SecurityContextSsl(
IConnectionSPtr const & connection,
TransportSecuritySPtr const & transportSecurity,
std::wstring const & targetName,
ListenInstance localListenInstance);
static bool Supports(SecurityProvider::Enum provider);
SECURITY_STATUS AuthorizeRemoteEnd() override;
SECURITY_STATUS EncodeMessage(_Inout_ MessageUPtr & message) override;
SECURITY_STATUS EncodeMessage(
TcpFrameHeader const & frameHeader,
Message & message,
Common::ByteBuffer2 & encrypted) override;
SECURITY_STATUS DecodeMessage(_Inout_ MessageUPtr & message) override;
SECURITY_STATUS DecodeMessage(Common::bique<byte> & receiveQueue, Common::bique<byte> & decrypted) override;
bool AuthenticateRemoteByClaims() const override;
bool ShouldPerformClaimsRetrieval() const override;
void CompleteClaimsRetrieval(Common::ErrorCode const &, std::wstring const & claimsToken) override;
void CompleteClientAuth(Common::ErrorCode const &, SecuritySettings::RoleClaims const & clientClaims, Common::TimeSpan expiration) override;
virtual bool AccessCheck(AccessControl::FabricAcl const & acl, DWORD desiredAccess) const override;
static void TraceCertificate(
std::wstring const & traceId,
PCCERT_CONTEXT certContext,
Common::Thumbprint const & issuerCertThumbprint);
static SECURITY_STATUS VerifyCertificate(
std::wstring const & traceId,
PCCERT_CONTEXT certContext,
DWORD certChainFlags,
bool shouldIgnoreCrlOffline,
bool remoteAuthenticatedAsPeer,
Common::ThumbprintSet const & certThumbprintsToMatch,
Common::SecurityConfig::X509NameMap const & x509NamesToMatch,
bool traceCert,
_Out_opt_ std::wstring * commonNameMatched = nullptr);
static SECURITY_STATUS Test_VerifyCertificate(_In_ PCCERT_CONTEXT certContext, std::wstring const & commonNameToMatch);
#ifdef PLATFORM_UNIX
Common::ErrorCode Encrypt(void const* buffer, size_t len);
Common::ByteBuffer2 EncryptFinal();
#endif
SECURITY_STATUS ProcessClaimsMessage(MessageUPtr & message) override;
private:
void OnInitialize() override;
SECURITY_STATUS OnNegotiateSecurityContext(
_In_ MessageUPtr const & inputMessage,
_Inout_opt_ PSecBufferDesc pOutput,
_Out_ MessageUPtr & outputMessage) override;
SECURITY_STATUS OnNegotiationSucceeded(SecPkgContext_NegotiationInfo const & negotiationInfo) override;
SECURITY_STATUS CheckClientAuthHeader(_In_ MessageUPtr const & inputMessage);
SECURITY_STATUS SspiDecrypt(_Inout_ byte* input, ULONG inputLength, _Inout_ SecBuffer buffers[4]);
SECURITY_STATUS DecryptMessageHeaders(_Inout_ std::vector<byte> & input, _Out_ ByteBique & output);
SECURITY_STATUS DecryptMessageBody(_Inout_ MessageUPtr & message);
HRESULT GetSslOutputLimit(ULONG inputBytes, _Out_ ULONG & outputLimit);
SECURITY_STATUS WriteSslRecord(
ULONG dataLength,
_Inout_ byte * sslRecord,
_Out_ ULONG & sslRecordSize);
static SECURITY_STATUS TryMatchCertThumbprint(
std::wstring const & traceId,
PCCERT_CONTEXT certContext,
Common::Thumbprint const & incoming,
SECURITY_STATUS certChainErrorStatus,
uint certChainFlags,
bool onlyCrlOfflineEncountered,
Common::ThumbprintSet const & thumbprintSet);
static SECURITY_STATUS GetCertChainContext(
std::wstring const & traceId,
_In_ PCCERT_CONTEXT certContext,
_In_ LPSTR usage,
DWORD certChainFlags,
_Out_ Common::CertChainContextUPtr & certChainContext,
_Out_opt_ Common::X509Identity::SPtr* issuerPubKey,
_Out_opt_ Common::X509Identity::SPtr* issuerCertThumbprint);
static SECURITY_STATUS VerifySslCertChain(
std::wstring const & traceId,
PCCERT_CHAIN_CONTEXT certChainContext,
DWORD authType,
DWORD certChainFlags,
bool shouldIgnoreCrlOffline,
bool & onlyCrlOfflineEncountered);
static bool IsClientAuthenticationCertificate(std::wstring const & traceId, _In_ PCCERT_CONTEXT certContext);
static bool IsServerAuthenticationCertificate(std::wstring const & traceId, _In_ PCCERT_CONTEXT certContext);
static bool CertCheckEnhancedKeyUsage(
std::wstring const & traceId,
_In_ PCCERT_CONTEXT certContext,
LPCSTR usageIdentifier);
static SECURITY_STATUS VerifyAsServerAuthCert(
std::wstring const & traceId,
PCCERT_CONTEXT certContext,
PCCERT_CHAIN_CONTEXT certChainContext,
Common::Thumbprint const & certThumbprint,
Common::X509Identity::SPtr const & issuerPubKey,
Common::X509Identity::SPtr const & issuerCertThumbprint,
Common::SecurityConfig::X509NameMap const & x509NamesToMatch,
DWORD certChainFlags,
bool shouldIgnoreCrlOffline,
bool onlyCrlOfflineEncountered,
_Out_opt_ std::wstring * nameMatched = nullptr);
static MessageUPtr CreateClaimsTokenErrorMessage(Common::ErrorCode const &);
void TryAuthenticateRemoteAsPeer();
private:
#ifdef PLATFORM_UNIX
static void SslInfoCallbackStatic(const SSL* ssl, int where, int ret);
void SslInfoCallback(int where, int ret);
static int CertVerifyCallbackStatic(int, X509_STORE_CTX*);
int CertVerifyCallback(int, X509_STORE_CTX*);
void AddDataToDecrypt(void const* buffer, size_t len);
SECURITY_STATUS Decrypt(void* buffer, _Inout_ int64& len);
static constexpr size_t DecryptedPendingMax();
Common::LinuxCryptUtil cryptUtil_;
BIO* inBio_ = nullptr;
BIO* outBio_ = nullptr;
SslUPtr ssl_;
Common::LinuxCryptUtil::CertChainErrors certChainErrors_;
#else
///
/// Verifies whether the chain's trust status contains only allowed/non-fatal errors.
///
static inline bool IsExpectedCertChainTrustError(
PCCERT_CHAIN_CONTEXT certChainContext,
SECURITY_STATUS certChainValidationStatus,
HRESULT expectedChainValidationStatus,
DWORD nonFatalCertChainErrorMask)
{
return (certChainValidationStatus == expectedChainValidationStatus) // act on specific validation errors
&& nonFatalCertChainErrorMask // must be a trust error
&& ((certChainContext->TrustStatus.dwErrorStatus & nonFatalCertChainErrorMask) == nonFatalCertChainErrorMask); // must be an expected trust error
}
std::vector<SecurityCredentialsSPtr> svrCredentials_;
SecPkgContext_StreamSizes streamSizes_;
class TemplateHelper;
// SSPI SSL decryption dictates a single input buffer. When and only when input span across multiple
// buffers, e.g. bique chunk boundary, such buffers are merged into a continuous one before decryption.
Common::ByteBuffer2 decryptionInputMergeBuffer_;
#endif
Common::CertContextUPtr remoteCertContext_;
std::wstring remoteCommonName_;
bool remoteAuthenticatedAsPeer_ = false;
bool claimsMessageReceived_ = false;
SecuritySettings::RoleClaims clientClaims_;
};
}
| 43.414894 | 164 | 0.668464 |
c8588f2c0057810e5d679341d41102aeb4663191 | 251 | c | C | Ch04/Exercises/e06.c | xixixixixiao/cpamase | 9404b4015fb8e2d03dde996ce269e3278a78ac84 | [
"MIT"
] | null | null | null | Ch04/Exercises/e06.c | xixixixixiao/cpamase | 9404b4015fb8e2d03dde996ce269e3278a78ac84 | [
"MIT"
] | null | null | null | Ch04/Exercises/e06.c | xixixixixiao/cpamase | 9404b4015fb8e2d03dde996ce269e3278a78ac84 | [
"MIT"
] | null | null | null | /**
* 6. 对C99重复上题。
*/
#include <stdio.h>
int main(void)
{
printf("%d\n", 8 % 5);
printf("%d\n", -8 % 5);
printf("%d\n", 8 % -5);
printf("%d\n", -8 % -5);
return 0;
}
/**
* gcc -std=c99 .\e06.c -o e06
*/
| 12.55 | 31 | 0.386454 |
c8e32eefa7cfb7279dbc4882865f8d934467a1be | 689 | h | C | mazerunner/source/Way.h | 1pkg/dump | 0ee579cb6a97ae64d5367cc624b2407d7d4b1c7b | [
"MIT"
] | null | null | null | mazerunner/source/Way.h | 1pkg/dump | 0ee579cb6a97ae64d5367cc624b2407d7d4b1c7b | [
"MIT"
] | 3 | 2020-12-11T10:01:27.000Z | 2022-02-13T22:12:05.000Z | mazerunner/source/Way.h | 1pkg/dump | 0ee579cb6a97ae64d5367cc624b2407d7d4b1c7b | [
"MIT"
] | null | null | null | #ifndef H_WAY
#define H_WAY
#include "List.h"
class Way : public List {
private:
int len, width;
public:
Way(int width, int len);
bool gate_Checker(int wall, int position);
void do_Gate();
bool check_Way(int route, int size);
void do_step(int route, int size);
void regen_it();
bool fin();
void do_Way();
void coppy_lab(bool **lab);
void position(int &start_width, int &start_len, int &end_width, int &end_len);
void main(bool **labint, int &start_width, int &start_len, int &end_width,
int &end_len);
bool check_sWay(int route, int size);
void do_sWay();
friend int seed(int distance, int seed);
};
#endif | 20.878788 | 81 | 0.642961 |
b7fa55c157e2d71390a53e6cc18caa0d547db37a | 1,425 | h | C | cmake_targets/basic_simulator/enb/CMakeFiles/RRC_Rel14/MeasObjectId-v1310.h | kikikos/openairinterface5g | 54d541c22cdfcb774774089291c93e4e79294a1d | [
"Apache-2.0"
] | null | null | null | cmake_targets/basic_simulator/enb/CMakeFiles/RRC_Rel14/MeasObjectId-v1310.h | kikikos/openairinterface5g | 54d541c22cdfcb774774089291c93e4e79294a1d | [
"Apache-2.0"
] | null | null | null | cmake_targets/basic_simulator/enb/CMakeFiles/RRC_Rel14/MeasObjectId-v1310.h | kikikos/openairinterface5g | 54d541c22cdfcb774774089291c93e4e79294a1d | [
"Apache-2.0"
] | 1 | 2020-02-10T14:17:39.000Z | 2020-02-10T14:17:39.000Z | /*
* Generated by asn1c-0.9.29 (http://lionet.info/asn1c)
* From ASN.1 module "EUTRA-RRC-Definitions"
* found in "/home/user/openairinterface5g/openair2/RRC/LTE/MESSAGES/asn1c/ASN1_files/lte-rrc-14.7.0.asn1"
* `asn1c -pdu=all -fcompound-names -gen-PER -no-gen-OER -no-gen-example -D /home/user/openairinterface5g/cmake_targets/basic_simulator/enb/CMakeFiles/RRC_Rel14`
*/
#ifndef _MeasObjectId_v1310_H_
#define _MeasObjectId_v1310_H_
#include <asn_application.h>
/* Including external dependencies */
#include <NativeInteger.h>
#ifdef __cplusplus
extern "C" {
#endif
/* MeasObjectId-v1310 */
typedef long MeasObjectId_v1310_t;
/* Implementation */
extern asn_per_constraints_t asn_PER_type_MeasObjectId_v1310_constr_1;
extern asn_TYPE_descriptor_t asn_DEF_MeasObjectId_v1310;
asn_struct_free_f MeasObjectId_v1310_free;
asn_struct_print_f MeasObjectId_v1310_print;
asn_constr_check_f MeasObjectId_v1310_constraint;
ber_type_decoder_f MeasObjectId_v1310_decode_ber;
der_type_encoder_f MeasObjectId_v1310_encode_der;
xer_type_decoder_f MeasObjectId_v1310_decode_xer;
xer_type_encoder_f MeasObjectId_v1310_encode_xer;
per_type_decoder_f MeasObjectId_v1310_decode_uper;
per_type_encoder_f MeasObjectId_v1310_encode_uper;
per_type_decoder_f MeasObjectId_v1310_decode_aper;
per_type_encoder_f MeasObjectId_v1310_encode_aper;
#ifdef __cplusplus
}
#endif
#endif /* _MeasObjectId_v1310_H_ */
#include <asn_internal.h>
| 31.666667 | 162 | 0.842105 |
d913a79c580909953ece855f5b7e17bb75e0af43 | 396 | c | C | Test/200-map-to-callee-variable-3/main.c | flix-/environment-variable-tracing | 85a1ad880b47acad28f5b1a418f1ee2259f77fad | [
"MIT"
] | null | null | null | Test/200-map-to-callee-variable-3/main.c | flix-/environment-variable-tracing | 85a1ad880b47acad28f5b1a418f1ee2259f77fad | [
"MIT"
] | null | null | null | Test/200-map-to-callee-variable-3/main.c | flix-/environment-variable-tracing | 85a1ad880b47acad28f5b1a418f1ee2259f77fad | [
"MIT"
] | null | null | null | extern char *getenv(const char *name);
void
bar(char *tainted_bar, char *not_tainted)
{
char *tainted2 = tainted_bar;
char *not_tainted2 = not_tainted;
}
void
foo(char *tainted_foo)
{
char *also_tainted = tainted_foo;
char *not_tainted = "noe";
bar(tainted_foo, not_tainted);
}
int
main()
{
char *tainted_main = getenv("gude");
foo(tainted_main);
return 0;
}
| 14.666667 | 41 | 0.664141 |
03081e5cf209e8a0a834b59867ee636d4cb079b6 | 3,031 | c | C | client/fhistory.c | dcrossleyau/yaz | af3a02922bd2d0a7c080942cbe7f55a7710dd27e | [
"BSD-3-Clause"
] | 35 | 2016-01-12T00:21:19.000Z | 2022-02-21T12:12:11.000Z | client/fhistory.c | dcrossleyau/yaz | af3a02922bd2d0a7c080942cbe7f55a7710dd27e | [
"BSD-3-Clause"
] | 33 | 2016-01-27T16:44:32.000Z | 2022-01-17T16:14:11.000Z | client/fhistory.c | dcrossleyau/yaz | af3a02922bd2d0a7c080942cbe7f55a7710dd27e | [
"BSD-3-Clause"
] | 18 | 2016-01-27T15:48:13.000Z | 2021-05-17T20:29:22.000Z | /* This file is part of the YAZ toolkit.
* Copyright (C) Index Data
* See the file LICENSE for details.
*/
/** \file fhistory.c
* \brief file history implementation
*/
#if HAVE_CONFIG_H
#include <config.h>
#endif
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#if HAVE_SYS_TYPES_H
#include <sys/types.h>
#endif
#include "fhistory.h"
struct file_history {
WRBUF wr;
};
file_history_t file_history_new()
{
file_history_t fh = (file_history_t) xmalloc(sizeof(*fh));
fh->wr = wrbuf_alloc();
return fh;
}
void file_history_destroy(file_history_t *fhp)
{
if (*fhp)
{
wrbuf_destroy((*fhp)->wr);
xfree(*fhp);
*fhp = 0;
}
}
void file_history_add_line(file_history_t fh, const char *line)
{
wrbuf_puts(fh->wr, line);
wrbuf_puts(fh->wr, "\n");
}
int file_history_load(file_history_t fh)
{
FILE *f;
char* homedir = getenv("HOME");
char fname[1024];
int ret = 0;
wrbuf_rewind(fh->wr);
sprintf(fname, "%.500s%s%s", homedir ? homedir : "",
homedir ? "/" : "", ".yazclient.history");
f = fopen(fname, "r");
if (f)
{
int c;
while ((c = fgetc(f)) != EOF)
wrbuf_putc(fh->wr, c);
fclose(f);
}
return ret;
}
#define FILE_SAVE_HISTORY_MAX 16384
int file_history_save(file_history_t fh)
{
FILE *f;
char* homedir = getenv("HOME");
char fname[1024];
int ret = 0;
size_t sz = wrbuf_len(fh->wr);
if (!sz)
return 0;
sprintf(fname, "%.500s%s%s", homedir ? homedir : "",
homedir ? "/" : "", ".yazclient.history");
f = fopen(fname, "w");
if (!f)
{
ret = -1;
}
else
{
size_t w;
const char *start = wrbuf_buf(fh->wr);
if (sz > FILE_SAVE_HISTORY_MAX)
{
const char *nl = strchr(
wrbuf_buf(fh->wr) + sz - FILE_SAVE_HISTORY_MAX,
'\n');
if (nl)
{
nl++;
sz = sz - (nl - start);
start = nl;
}
}
w = fwrite(start, 1, sz, f);
if (w != sz)
ret = -1;
if (fclose(f))
ret = -1;
}
return ret;
}
int file_history_trav(file_history_t fh, void *client_data,
void (*callback)(void *client_data, const char *line))
{
size_t off = 0;
while (off < wrbuf_len(fh->wr))
{
size_t i;
for (i = off; i < wrbuf_len(fh->wr); i++)
{
if (wrbuf_buf(fh->wr)[i] == '\n')
{
wrbuf_buf(fh->wr)[i] = '\0';
callback(client_data, wrbuf_cstr(fh->wr) + off);
wrbuf_buf(fh->wr)[i] = '\n';
i++;
break;
}
}
off = i;
}
return 0;
}
/*
* Local variables:
* c-basic-offset: 4
* c-file-style: "Stroustrup"
* indent-tabs-mode: nil
* End:
* vim: shiftwidth=4 tabstop=8 expandtab
*/
| 20.072848 | 76 | 0.506434 |
6c36b17a32f8e861009b44056fbbd5ccdbeb0dd0 | 2,146 | h | C | src/GameStateWinGame.h | MaxSavenkov/drdestructo2 | a8c0d506ea7280e60d4b6bb3045ea9b471c3e314 | [
"MIT"
] | 33 | 2015-04-15T16:58:00.000Z | 2021-06-06T13:58:14.000Z | src/GameStateWinGame.h | MaxSavenkov/drdestructo2 | a8c0d506ea7280e60d4b6bb3045ea9b471c3e314 | [
"MIT"
] | 3 | 2015-04-15T17:11:01.000Z | 2021-01-08T14:08:52.000Z | src/GameStateWinGame.h | MaxSavenkov/drdestructo2 | a8c0d506ea7280e60d4b6bb3045ea9b471c3e314 | [
"MIT"
] | 6 | 2015-05-07T14:41:53.000Z | 2022-01-27T12:19:58.000Z | #pragma once
#include "BaseGameState.h"
#include "IRender.h"
/*
This class describes what happens after the game is won
*/
class GameStateWinGame : public BaseGameState
{
// Ending sequence stages
enum EStage
{
STAGE_INVALID,
STAGE_SPACE,
STAGE_EARTH,
STAGE_TEXT,
STAGE_LAST,
};
// Current stage
EStage m_stage;
// Stage timer
float m_timer;
// Y-coordinate of sky rectangle
float m_y;
// Y-coordinate of falling object
float m_yShip;
// Fade parameters
bool m_fadeOut;
bool m_fadeIn;
float m_fadeTimer;
float m_fadeMax;
Color m_fadeColor;
// Image of Dr. Destructo for text stage
ImageHandle m_question;
// Image of stars
ImageHandle m_space;
// Image of island
ImageHandle m_island;
// Image of falling fortress
ImageHandle m_ship;
// Explosion in space stage
static const int MAX_EXPLOSIONS = 20;
struct SExplosion
{
SExplosion()
: m_lifeTimer( 0.25f )
{}
GameObjectID m_objID;
float m_lifeTimer;
};
SExplosion m_explosions[ MAX_EXPLOSIONS ];
RequestID m_explosionRequestID[ MAX_EXPLOSIONS ];
void NextStage();
bool Skip( const InputEvent & e );
public:
GameStateWinGame()
: BaseGameState( GAMESTATE_WIN )
, m_stage( STAGE_INVALID )
, m_timer( 0 )
, m_fadeIn( false )
, m_fadeOut( false )
, m_fadeTimer( 0.0f )
{
AddKeyboardHandler( this, &GameStateWinGame::Skip, KeyboardEvent::KBD_KEY_DOWN, ALLEGRO_KEY_ESCAPE );
AddTouchHandler( this, &GameStateWinGame::Skip, TouchEvent::TOUCH_BEGIN );
AddGamepadHandlerFromConfig( "Pad_Bomb", this, &GameStateWinGame::Skip );
}
void RenderBefore( IRender & render, const IGameContext & context );
void RenderAfter( IRender & render, const IGameContext & context );
void Update( float dt, IGameContext & context );
bool AllowPhysicsUpdate() const { return false; }
bool AllowGraphicsUpdate() const { return true; }
bool AllowGraphicsRender() const { return true; }
bool AllowAIUpdate() const { return false; }
void OnPush( IGameContext & context );
void OnRemove( IGameContext & context ) {}
};
| 24.11236 | 105 | 0.691519 |
96aacd18b534e517b9fd0da563619f7de89d222a | 325 | h | C | installed/keyring/keyring/backends/keyring_util.h | jscherer26/Icarra | 5bc8b298ae21dcde7e8e2253b9ed9db95fd0d164 | [
"BSD-3-Clause"
] | 1 | 2021-11-09T04:36:57.000Z | 2021-11-09T04:36:57.000Z | installed/keyring/keyring/backends/keyring_util.h | jscherer26/Icarra | 5bc8b298ae21dcde7e8e2253b9ed9db95fd0d164 | [
"BSD-3-Clause"
] | null | null | null | installed/keyring/keyring/backends/keyring_util.h | jscherer26/Icarra | 5bc8b298ae21dcde7e8e2253b9ed9db95fd0d164 | [
"BSD-3-Clause"
] | 2 | 2020-03-28T02:55:19.000Z | 2021-11-09T04:37:08.000Z | /*
* keyring_util.h
*
* Some useful functions for keyring lib
*/
#ifndef KEYRING_UTIL_H
#define KEYRING_UTIL_H
char *
string_dump(const char *s,int n)
{
char *res;
if (s == NULL)
return NULL;
res = (char*) malloc(n+1);
memcpy(res,s,n);
res[n] = '\0';
return res;
}
#endif //KEYRING_UTIL_H
| 16.25 | 40 | 0.606154 |
182ec8ef2d1a3fba45e0c2abc39dfe3fb7c64280 | 103 | c | C | boards/arm/colibri_imx7d_m4/pinmux.c | dmgerman/zephyrd3 | b6a23cc9c5d534c352e33fd18fff7799ac3c2886 | [
"Apache-2.0"
] | null | null | null | boards/arm/colibri_imx7d_m4/pinmux.c | dmgerman/zephyrd3 | b6a23cc9c5d534c352e33fd18fff7799ac3c2886 | [
"Apache-2.0"
] | null | null | null | boards/arm/colibri_imx7d_m4/pinmux.c | dmgerman/zephyrd3 | b6a23cc9c5d534c352e33fd18fff7799ac3c2886 | [
"Apache-2.0"
] | null | null | null | DECL|colibri_imx7d_m4_pinmux_init|function|static int colibri_imx7d_m4_pinmux_init(struct device *dev)
| 51.5 | 102 | 0.893204 |
495b0afda93c2d4d959caaddbcb1003cbbe91416 | 5,228 | h | C | modules/XL/Standard/array.h | xenginez/XE | 7f536c906460c7062cad5b8e09a644812cabf6d3 | [
"MIT"
] | 2 | 2019-06-10T06:51:27.000Z | 2021-11-20T19:57:46.000Z | modules/XL/Standard/array.h | xenginez/XE | 7f536c906460c7062cad5b8e09a644812cabf6d3 | [
"MIT"
] | 1 | 2019-07-12T03:05:02.000Z | 2019-08-12T12:01:06.000Z | modules/XL/Standard/array.h | xenginez/XE | 7f536c906460c7062cad5b8e09a644812cabf6d3 | [
"MIT"
] | null | null | null | /*!
* \file array.h
*
* \author ZhengYuanQing
* \date 2021/12/31
* \email zhengyuanqing.95@gmail.com
*
*/
#ifndef ARRAY_H__574088A1_05B3_40E5_8024_B7CB3F0676FB
#define ARRAY_H__574088A1_05B3_40E5_8024_B7CB3F0676FB
BEG_XL_NAMESPACE
static constexpr const char * std_array = R"(
module std
{
public template array< T >
{
public typedef T value_type;
public typedef const T const_value_type;
public delegate bool foreach_type( value_type value );
public delegate bool const_foreach_type( const_value_type value );
public delegate bool foreach_index_type( uint64 index, value_type value );
public delegate bool const_foreach_index_type( uint64 index, const_value_type value );
public construct( uint64 size )
{
_data.allocate( size );
}
public construct( array< T > & other )
{
_data.allocate( other.size() * sizeof( T ) );
_data.memcpy( 0, other, other.size() * sizeof( T ) );
}
public value_type front()
{
return _data.address( 0 ) as value_type;
}
public const_value_type front() const
{
return _data.address( 0 ) as const_value_type;
}
public void push_front( value_type value )
{
_data.reallocate( _size * sizeof( T ) * 2, sizeof( T ) );
_data.memcpy( 0, value, sizeof( T ) );
--_size;
}
public void pop_front()
{
assert( _size == 0, "element of zero" );
_data.memmove( sizeof( T ), sizeof( T ) );
--_size;
}
public value_type back()
{
return _data.address( _size * sizeof( T ) - sizeof( T ) ) as value_type;
}
public const_value_type back() const
{
return _data.address( _size * sizeof( T ) - sizeof( T ) ) as const_value_type;
}
public void push_back( value_type value )
{
if( _size * sizeof( T ) == _data.size() )
{
_data.reallocate( _size * sizeof( T ) * 2, sizeof( T ) );
}
_data.memcpy( _size * sizeof( T ), value, sizeof( T ) );
++_size;
}
public void pop_back()
{
assert( _size == 0, "element of zero" );
--_size;
}
public void insert( uint64 index, value_type value )
{
if( _size * sizeof( T ) == _data.size() )
{
_data.reallocate( _size * sizeof( T ) * 2, sizeof( T ) );
}
_data.memmove( index * sizeof( T ), sizeof( T ) );
_data.memcpy( index * sizeof( T ), value, sizeof( T ) );
++_size;
}
public uint64 remove( uint64 index )
{
assert( index >= _size, "out of range" );
_data.memmove( index * sizeof( T ), sizeof( T ) );
--_size;
}
public value_type at( uint64 index )
{
assert( index >= _size, "out of range" );
return _data.address( index * sizeof( T ) ) as value_type;
}
public const_value_type at( uint64 index ) const
{
assert( index >= _size, "out of range" );
return _data.address( index * sizeof( T ) ) as const_value_type;
}
public value_type operator[]( uint64 index )
{
assert( index >= _size, "out of range" );
return _data.address( index * sizeof( T ) ) as value_type;
}
public const_value_type operator[]( uint64 index ) const
{
assert( index >= _size, "out of range" );
return _data.address( index * sizeof( T ) ) as const_value_type;
}
public void clear()
{
_size = 0;
}
public void resize( uint64 size )
{
if( size > _size && size * sizeof( T ) > _data.size() )
{
_data.reallocate( size * sizeof( T ) );
}
_size = size;
}
public bool empty() const
{
return _size == 0;
}
public uint64 size() const
{
return _size;
}
public void foreach( foreach_type callback )
{
for( uint64 i = 0; i < _size; ++i )
{
callback( _data.address( i * sizeof( T ) ) as value_type );
}
}
public void foreach( const_foreach_type callback ) const
{
for( uint64 i = 0; i < _size; ++i )
{
callback( _data.address( i * sizeof( T ) ) as const_value_type );
}
}
public void foreach( foreach_index_type callback )
{
for( uint64 i = 0; i < _size; ++i )
{
callback( i, _data.address( i * sizeof( T ) ) as value_type );
}
}
public void foreach( const_foreach_index_type callback ) const
{
for( uint64 i = 0; i < _size; ++i )
{
callback( i, _data.address( i * sizeof( T ) ) as const_value_type );
}
}
public void reverse_foreach( foreach_type callback )
{
for( uint64 i = _size - 1; i >= 0; ++i )
{
callback( _data.address( i * sizeof( T ) ) as value_type );
}
}
public void reverse_foreach( const_foreach_type callback ) const
{
for( uint64 i = _size - 1; i >= 0; ++i )
{
callback( _data.address( i * sizeof( T ) ) as const_value_type );
}
}
public void reverse_foreach( foreach_index_type callback )
{
for( uint64 i = _size - 1; i >= 0; ++i )
{
callback( i, _data.address( i * sizeof( T ) ) as value_type );
}
}
public void reverse_foreach( const_foreach_index_type callback ) const
{
for( uint64 i = _size - 1; i >= 0; ++i )
{
callback( i, _data.address( i * sizeof( T ) ) as const_value_type );
}
}
public void bytes data()
{
return _data;
}
public void const bytes data() const
{
return _data;
}
private int64 _size = 0;
private bytes _data = new bytes;
}
}
)";
END_XL_NAMESPACE
#endif//ARRAY_H__574088A1_05B3_40E5_8024_B7CB3F0676FB | 23.339286 | 88 | 0.621844 |
5baba298f009c79e83d1dea5895f23fe50f356e5 | 3,683 | h | C | source/graphics/2d/Sprites/Animation/AnimationController.h | VUEngine/VUEngine-Core | 4737e0efd2c8e6ba7f69e689bf9e79dcdd627050 | [
"MIT"
] | 9 | 2021-01-09T19:24:27.000Z | 2022-03-27T11:57:20.000Z | source/graphics/2d/Sprites/Animation/AnimationController.h | VUEngine/VUEngine-Core | 4737e0efd2c8e6ba7f69e689bf9e79dcdd627050 | [
"MIT"
] | null | null | null | source/graphics/2d/Sprites/Animation/AnimationController.h | VUEngine/VUEngine-Core | 4737e0efd2c8e6ba7f69e689bf9e79dcdd627050 | [
"MIT"
] | null | null | null | /* VUEngine - Virtual Utopia Engine <https://www.vuengine.dev>
* A universal game engine for the Nintendo Virtual Boy
*
* © Jorge Eremiev <jorgech3@gmail.com> and Christian Radke <c.radke@posteo.de>, 2007-2020
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software and
* associated documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
* LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
* NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef ANIMATION_CONTROLLER_H_
#define ANIMATION_CONTROLLER_H_
//---------------------------------------------------------------------------------------------------------
// INCLUDES
//---------------------------------------------------------------------------------------------------------
#include <Object.h>
#include <Clock.h>
#include <CharSet.h>
#include <Sprite.h>
//---------------------------------------------------------------------------------------------------------
// CLASS'S DECLARATION
//---------------------------------------------------------------------------------------------------------
// Forward declaration
class AnimationCoordinator;
/// @ingroup graphics-2d-sprites-animation
class AnimationController : Object
{
// who owns the animated sprite
AnimationCoordinator animationCoordinator;
// a pointer to the animation function being played
const AnimationFunction* animationFunction;
// actual animation's frame to show
int16 actualFrame;
// previous animation's frame shown
uint8 previousFrameValue;
// the number of game cycles that an animation frame is shown
uint8 frameDuration;
// frame delay decrement update cycle
uint8 frameCycleDecrement;
// flag to know if playing an animation
uint8 playing;
// frame changed flag
uint8 animationFrameChanged;
/// @publicsection
void constructor();
AnimationCoordinator getAnimationCoordinator();
void setAnimationCoordinator(AnimationCoordinator animationCoordinator);
int16 getActualFrame();
int16 getActualFrameIndex();
uint8 getCols();
uint8 getFrameCycleDecrement();
uint8 getFrameDuration();
int32 getMapType();
int32 getNumberOfFrames();
const AnimationFunction* getPlayingAnimationFunction();
uint8 getRows();
bool isPlaying();
bool isPlayingFunction(const char* functionName);
void pause(bool pause);
bool play(const AnimationDescription* animationDescription, const char* functionName, Object scope);
bool replay(const AnimationDescription* animationDescription);
void playAnimationFunction(const AnimationFunction* animationFunction, Object scope);
void nextFrame();
void previousFrame();
bool setActualFrame(int16 actualFrame);
void setFrameCycleDecrement(uint8 frameCycleDecrement);
void setFrameDuration(uint8 frameDuration);
void stop();
bool update(Clock clock);
bool updateAnimation();
void write();
void writeAnimation();
}
#endif
| 38.364583 | 107 | 0.686397 |
8b00f5c8d224d4e668920ea95485859306987f35 | 380 | h | C | carport/carport/MeTableViewCell.h | wgziOS/TestCarPort | d4b12646354799b9e0a110e8900d753346af99a4 | [
"MIT"
] | null | null | null | carport/carport/MeTableViewCell.h | wgziOS/TestCarPort | d4b12646354799b9e0a110e8900d753346af99a4 | [
"MIT"
] | null | null | null | carport/carport/MeTableViewCell.h | wgziOS/TestCarPort | d4b12646354799b9e0a110e8900d753346af99a4 | [
"MIT"
] | null | null | null | //
// MeTableViewCell.h
// carport
//
// Created by 吴桂钊 on 2016/12/2.
// Copyright © 2016年 86gg.cn. All rights reserved.
//
#import <UIKit/UIKit.h>
static NSString * const kMeTableViewCell = @"MeTableViewCell";
@interface MeTableViewCell : UITableViewCell
@property (weak, nonatomic) IBOutlet UILabel *label;
@property (weak, nonatomic) IBOutlet UIImageView *imgView;
@end
| 22.352941 | 62 | 0.731579 |
3ee341dc2644709a46ed257e0f8315b7020f86bf | 1,067 | h | C | libraries/SdFat/src/SystemInclude.h | icobani/ArduinoIOT | 47423a921b7bf571e7d4550c74c2a82df19397f6 | [
"Apache-2.0"
] | 5 | 2017-01-09T21:24:36.000Z | 2021-10-03T07:00:49.000Z | libraries/SdFat/src/SystemInclude.h | icobani/ArduinoIOT | 47423a921b7bf571e7d4550c74c2a82df19397f6 | [
"Apache-2.0"
] | 39 | 2019-02-12T17:11:54.000Z | 2019-03-25T18:08:58.000Z | libraries/SdFat/src/SystemInclude.h | icobani/ArduinoIOT | 47423a921b7bf571e7d4550c74c2a82df19397f6 | [
"Apache-2.0"
] | 3 | 2019-03-01T16:51:57.000Z | 2022-03-31T13:34:06.000Z | /* Arduino SdFat Library
* Copyright (C) 2016 by William Greiman
*
* This file is part of the Arduino SdFat Library
*
* This Library is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This Library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with the Arduino SdFat Library. If not, see
* <http://www.gnu.org/licenses/>.
*/
#ifndef SystemInclude_h
#define SystemInclude_h
#if defined(ARDUINO)
#include "FatLib/SysCall.h"
#elif defined(PLATFORM_ID) // Only defined if a Particle device
#include "SysCall.h"
#else // System type
#error Unknown System.
#endif // System type
#endif // SystemInclude_h
| 35.566667 | 71 | 0.74508 |
994150dd4e8f4445dcd0d541b5127c053796bd9d | 2,665 | h | C | src/drivers/devices/cpu/flowunit/java/java_flowunit.h | yamal-shang/modelbox | b2785568f4acd56d4922a793aa25516f883edc26 | [
"Apache-2.0"
] | 51 | 2021-09-24T08:57:44.000Z | 2022-03-31T09:12:46.000Z | src/drivers/devices/cpu/flowunit/java/java_flowunit.h | yamal-shang/modelbox | b2785568f4acd56d4922a793aa25516f883edc26 | [
"Apache-2.0"
] | 3 | 2022-02-22T07:13:02.000Z | 2022-03-30T02:03:40.000Z | src/drivers/devices/cpu/flowunit/java/java_flowunit.h | yamal-shang/modelbox | b2785568f4acd56d4922a793aa25516f883edc26 | [
"Apache-2.0"
] | 31 | 2021-11-29T02:22:39.000Z | 2022-03-15T03:05:24.000Z | /*
* Copyright 2021 The Modelbox Project Authors. All Rights Reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MODELBOX_FLOWUNIT_JAVA_H_
#define MODELBOX_FLOWUNIT_JAVA_H_
#include <modelbox/base/device.h>
#include <modelbox/base/status.h>
#include <modelbox/flow.h>
#include <modelbox/flowunit.h>
#include "virtualdriver_java.h"
constexpr const char *FLOWUNIT_TYPE = "cpu";
class JavaFlowUnitDesc : public modelbox::FlowUnitDesc {
public:
JavaFlowUnitDesc() = default;
virtual ~JavaFlowUnitDesc() = default;
void SetJavaEntry(const std::string java_entry);
const std::string GetJavaEntry();
std::string java_entry_;
};
class JavaFlowUnit : public modelbox::FlowUnit {
public:
JavaFlowUnit();
virtual ~JavaFlowUnit();
modelbox::Status Open(const std::shared_ptr<modelbox::Configuration> &opts);
modelbox::Status Close();
modelbox::Status Process(std::shared_ptr<modelbox::DataContext> data_ctx);
modelbox::Status DataPre(std::shared_ptr<modelbox::DataContext> data_ctx);
modelbox::Status DataPost(std::shared_ptr<modelbox::DataContext> data_ctx);
modelbox::Status DataGroupPre(
std::shared_ptr<modelbox::DataContext> data_ctx);
modelbox::Status DataGroupPost(
std::shared_ptr<modelbox::DataContext> data_ctx);
virtual void SetFlowUnitDesc(std::shared_ptr<modelbox::FlowUnitDesc> desc);
virtual std::shared_ptr<modelbox::FlowUnitDesc> GetFlowUnitDesc();
private:
std::shared_ptr<VirtualJavaFlowUnitDesc> java_desc_;
};
class JavaFlowUnitFactory : public modelbox::FlowUnitFactory {
public:
JavaFlowUnitFactory() = default;
virtual ~JavaFlowUnitFactory() = default;
virtual std::shared_ptr<modelbox::FlowUnit> CreateFlowUnit(
const std::string &unit_name, const std::string &unit_type) {
auto java_flowunit = std::make_shared<JavaFlowUnit>();
return java_flowunit;
};
const std::string GetFlowUnitFactoryType() { return FLOWUNIT_TYPE; };
std::map<std::string, std::shared_ptr<modelbox::FlowUnitDesc>>
FlowUnitProbe() {
return std::map<std::string, std::shared_ptr<modelbox::FlowUnitDesc>>();
};
};
#endif // MODELBOX_FLOWUNIT_JAVA_H_
| 30.284091 | 78 | 0.750844 |
5b20efb32bd491aca23b5f2e5c7b0eff8c331924 | 5,362 | h | C | src/asn1/c/OBJECT_IDENTIFIER.h | player999/cryptonite | d6ad2a0c79d9914bf1ac535f47425eaad56f5be2 | [
"BSD-2-Clause"
] | 33 | 2019-05-04T19:22:25.000Z | 2022-02-21T14:01:29.000Z | src/asn1/c/OBJECT_IDENTIFIER.h | player999/cryptonite | d6ad2a0c79d9914bf1ac535f47425eaad56f5be2 | [
"BSD-2-Clause"
] | 10 | 2019-05-14T08:33:28.000Z | 2022-01-23T16:31:54.000Z | src/asn1/c/OBJECT_IDENTIFIER.h | player999/cryptonite | d6ad2a0c79d9914bf1ac535f47425eaad56f5be2 | [
"BSD-2-Clause"
] | 17 | 2019-05-04T20:11:36.000Z | 2022-01-23T14:59:56.000Z | /*
* Copyright (c) 2016 PrivatBank IT <acsk@privatbank.ua>. All rights reserved.
* Redistribution and modifications are permitted subject to BSD license.
*/
#ifndef _OBJECT_IDENTIFIER_H_
#define _OBJECT_IDENTIFIER_H_
#include "asn_application.h"
#include "asn_codecs_prim.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef ASN__PRIMITIVE_TYPE_t OBJECT_IDENTIFIER_t;
extern asn_TYPE_descriptor_t OBJECT_IDENTIFIER_desc;
CRYPTONITE_EXPORT asn_TYPE_descriptor_t *get_OBJECT_IDENTIFIER_desc(void);
asn_struct_print_f OBJECT_IDENTIFIER_print;
asn_constr_check_f OBJECT_IDENTIFIER_constraint;
der_type_encoder_f OBJECT_IDENTIFIER_encode_der;
xer_type_decoder_f OBJECT_IDENTIFIER_decode_xer;
xer_type_encoder_f OBJECT_IDENTIFIER_encode_xer;
/**********************************
* Some handy conversion routines *
**********************************/
/*
* This function fills an (_arcs) array with OBJECT IDENTIFIER arcs
* up to specified (_arc_slots) elements.
*
* EXAMPLE:
* void print_arcs(OBJECT_IDENTIFIER_t *oid) {
* unsigned long fixed_arcs[10]; // Try with fixed space first
* unsigned long *arcs = fixed_arcs;
* int arc_type_size = sizeof(fixed_arcs[0]); // sizeof(long)
* int arc_slots = sizeof(fixed_arcs)/sizeof(fixed_arcs[0]); // 10
* int count; // Real number of arcs.
* int i;
*
* count = OBJECT_IDENTIFIER_get_arcs(oid, arcs,
* arc_type_size, arc_slots);
* // If necessary, reallocate arcs array and try again.
* if(count > arc_slots) {
* arc_slots = count;
* arcs = malloc(arc_type_size * arc_slots);
* if(!arcs) return;
* count = OBJECT_IDENTIFIER_get_arcs(oid, arcs,
* arc_type_size, arc_slots);
* ASSERT(count == arc_slots);
* }
*
* // Print the contents of the arcs array.
* for(i = 0; i < count; i++)
* printf("%d\n", arcs[i]);
*
* // Avoid memory leak.
* if(arcs != fixed_arcs) free(arcs);
* }
*
* RETURN VALUES:
* -1/EINVAL: Invalid arguments (oid is missing)
* -1/ERANGE: One or more arcs have value out of array cell type range.
* >=0: Number of arcs contained in the OBJECT IDENTIFIER
*
* WARNING: The function always returns the real number of arcs,
* even if there is no sufficient (_arc_slots) provided.
*/
CRYPTONITE_EXPORT int OBJECT_IDENTIFIER_get_arcs(const OBJECT_IDENTIFIER_t *_oid,
void *_arcs, /* e.g., unsigned int arcs[N] */
unsigned int _arc_type_size, /* e.g., sizeof(arcs[0]) */
unsigned int _arc_slots /* e.g., N */);
/*
* This functions initializes the OBJECT IDENTIFIER object with
* the given set of arcs.
* The minimum of two arcs must be present; some restrictions apply.
* RETURN VALUES:
* -1/EINVAL: Invalid arguments
* -1/ERANGE: The first two arcs do not conform to ASN.1 restrictions.
* -1/ENOMEM: Memory allocation failed
* 0: The object was initialized with new arcs.
*/
CRYPTONITE_EXPORT int OBJECT_IDENTIFIER_set_arcs(OBJECT_IDENTIFIER_t *_oid,
const void *_arcs, /* e.g., unsigned int arcs[N] */
unsigned int _arc_type_size, /* e.g., sizeof(arcs[0]) */
unsigned int _arc_slots /* e.g., N */);
/*
* Print the specified OBJECT IDENTIFIER arc.
*/
CRYPTONITE_EXPORT int OBJECT_IDENTIFIER_print_arc(const uint8_t *arcbuf, int arclen,
int add, /* Arbitrary offset, required to process the first two arcs */
asn_app_consume_bytes_f *cb, void *app_key);
/* Same as above, but returns the number of written digits, instead of 0 */
CRYPTONITE_EXPORT ssize_t OBJECT_IDENTIFIER__dump_arc(const uint8_t *arcbuf, int arclen, int add,
asn_app_consume_bytes_f *cb, void *app_key);
/*
* Parse the OBJECT IDENTIFIER textual representation ("1.3.6.1.4.1.9363").
* No arc can exceed the (0..signed_long_max) range (typically, 0..2G if L32).
* This function is not specific to OBJECT IDENTIFIER, it may be used to parse
* the RELATIVE-OID data, or any other data consisting of dot-separated
* series of numeric values.
*
* If (oid_txt_length == -1), the strlen() will be invoked to determine the
* size of the (oid_text) string.
*
* After return, the optional (opt_oid_text_end) is set to the character after
* the last parsed one. (opt_oid_text_end) is never less than (oid_text).
*
* RETURN VALUES:
* -1: Parse error.
* >= 0: Number of arcs contained in the OBJECT IDENTIFIER.
*
* WARNING: The function always returns the real number of arcs,
* even if there is no sufficient (_arc_slots) provided.
* This is useful for (_arc_slots) value estimation.
*/
CRYPTONITE_EXPORT int OBJECT_IDENTIFIER_parse_arcs(const char *oid_text, ssize_t oid_txt_length,
long arcs[], unsigned int arcs_slots, const char **opt_oid_text_end);
/*
* Internal functions.
* Used by RELATIVE-OID implementation in particular.
*/
CRYPTONITE_EXPORT int OBJECT_IDENTIFIER_get_single_arc(const uint8_t *arcbuf, unsigned int arclen,
signed int add, void *value, unsigned int value_size);
CRYPTONITE_EXPORT int OBJECT_IDENTIFIER_set_single_arc(uint8_t *arcbuf,
const void *arcval, unsigned int arcval_size, int _prepared_order);
#ifdef __cplusplus
}
#endif
#endif
| 38.028369 | 99 | 0.681462 |
160b828d326f06c01579b8088f7982d817404e43 | 754 | h | C | src/tensors/backend.h | delong-coder/marian-dev | 2ef018e829e08a688eb02d3a56f29d23b284b901 | [
"MIT"
] | 829 | 2017-06-05T12:14:34.000Z | 2022-03-29T17:24:03.000Z | src/tensors/backend.h | delong-coder/marian-dev | 2ef018e829e08a688eb02d3a56f29d23b284b901 | [
"MIT"
] | 318 | 2017-06-03T13:31:44.000Z | 2022-03-22T14:57:24.000Z | src/tensors/backend.h | delong-coder/marian-dev | 2ef018e829e08a688eb02d3a56f29d23b284b901 | [
"MIT"
] | 192 | 2017-06-27T10:17:26.000Z | 2022-03-28T05:33:11.000Z | #pragma once
#include "common/definitions.h"
#include "tensors/rand.h"
namespace marian {
class Backend {
protected:
DeviceId deviceId_;
size_t seed_;
Ptr<RandomGenerator> randomGenerator_;
public:
Backend(DeviceId deviceId, size_t seed)
: deviceId_(deviceId), seed_(seed), randomGenerator_(createRandomGenerator(seed, deviceId)) {}
virtual ~Backend() {};
virtual DeviceId getDeviceId() { return deviceId_; };
virtual Ptr<RandomGenerator> getRandomGenerator() { return randomGenerator_; }
// for GPU only, calls cudaSetDevice, does nothing on CPU. Maybe change name.
virtual void setDevice() = 0;
virtual void synchronize() = 0;
};
Ptr<Backend> BackendByDeviceId(DeviceId deviceId, size_t seed);
} // namespace marian
| 26 | 100 | 0.738727 |
8fbab6383a351cc8894c1f59202dc36a06531b2e | 3,035 | h | C | include/Log.h | logikoisto/kangaroo | 27b9326aa558023244e7d9df330f931935bbeb3b | [
"MIT"
] | null | null | null | include/Log.h | logikoisto/kangaroo | 27b9326aa558023244e7d9df330f931935bbeb3b | [
"MIT"
] | null | null | null | include/Log.h | logikoisto/kangaroo | 27b9326aa558023244e7d9df330f931935bbeb3b | [
"MIT"
] | null | null | null | #ifndef _ZOO_KANGAROO_LOG_H__
#define _ZOO_KANGAROO_LOG_H__
#include <stdarg.h> /* ANSI C header file */
#include <map>
#include "../src/LogLevel.h"
#include "LogAppender.h"
#include "Singleton.h"
/*
Logger::setGlobalLogLevel(LogLevel::INFO);
Logger::getInstance()->addAppender("console", LogAppender::ptr(new ConsoleAppender()));
*/
namespace zoo
{
namespace kangaroo
{
class Logger
{
public:
static Logger *getLogger()
{
return Singleton<Logger>::getInstance();
}
static void setGlobalLogLevel(LogLevel level);
static LogLevel getGlobalLogLevel();
void info(const char *format, ...);
void debug(const char *format, ...);
void warn(const char *format, ...);
void error(const char *format, ...);
void fatal(const char *format, ...);
/*需要加锁的*/
void addAppender(const std::string name, LogAppender::Ptr appender);
void delAppender(const std::string name);
void clearAppender();
private:
Logger();
~Logger(){};
void log(LogLevel logLevel,const char *fmt, va_list ap)
{
//
if (logLevel < gLogLevel)
{
return;
}
//格式化固有前缀+data
//固定前缀：日期+时间(精确到微妙)+线程ID+日志级别+日志内容+源文件+行号
MutexGuard guard(m_mutex);
for (const auto &pair : m_appenders)
{
pair.second->append(res.data(), res.length());
}
}
private:
string formatMsg(const char *fmt, va_list ap)
{
string res;
#ifdef HAVE_VSNPRINTF
vsnprintf(res.data(), res.length(), fmt, ap); /* safe */
#else
vsprintf((char *)res.data(), fmt, ap); /* not safe */
#endif
return res;
}
private:
Mutex m_mutex;
map<std::string, LogAppender::Ptr> m_appenders;
};
} // namespace kangaroo
} // namespace zoo
#define log_out(lvl, fmt, args...) \
if(zoo::kangaroo::gLogLevel<zoo::kangaroo::Logger::getLogger()->getGlobalLogLevel()) \
log_center_write(lvl, __FILE__, __FUNCTION__, __LINE__ , fmt, ##args)
#define log_fatal(fmt, args...) log_out(zoo::kangaroo::LogLevel::FATAL, fmt, ##args)
#define log_error(fmt, args...) log_out(zoo::kangaroo::LogLevel::ERROR, fmt, ##args)
#define log_warn(fmt, args...) log_out(zoo::kangaroo::LogLevel::WARN, fmt, ##args)
#define log_debug(fmt, args...) log_out(zoo::kangaroo::LogLevel::DEBUG, fmt, ##args)
#define log_info(fmt, args...) log_out(zoo::kangaroo::LogLevel::INFO, fmt, ##args)
#endif | 33.351648 | 95 | 0.507414 |
6bd0e9c5cc029483ce6a20499446838a74049f3f | 306 | h | C | src/nursery.h | quietfanatic/Sequoia | 03beb7dbdc1b83a60e799b43548f8b1dadf34295 | [
"MIT"
] | null | null | null | src/nursery.h | quietfanatic/Sequoia | 03beb7dbdc1b83a60e799b43548f8b1dadf34295 | [
"MIT"
] | null | null | null | src/nursery.h | quietfanatic/Sequoia | 03beb7dbdc1b83a60e799b43548f8b1dadf34295 | [
"MIT"
] | null | null | null | #pragma once
#include <functional>
#include <string>
#include <windows.h>
#include "util/types.h"
// If the nursery already exists in another process, returns it
HWND existing_nursery ();
void init_nursery ();
void new_webview (const std::function<void(WebViewController*, WebView*, HWND)>& then);
| 18 | 87 | 0.735294 |
ac510c4a628cefe004a79531423bacef94fef7f8 | 20 | c | C | lib/discord.c | timmypidashev/discord.c | 56c7ee1f85c1149a4c5a1a0d10aea5f83d9fa041 | [
"MIT"
] | null | null | null | lib/discord.c | timmypidashev/discord.c | 56c7ee1f85c1149a4c5a1a0d10aea5f83d9fa041 | [
"MIT"
] | null | null | null | lib/discord.c | timmypidashev/discord.c | 56c7ee1f85c1149a4c5a1a0d10aea5f83d9fa041 | [
"MIT"
] | null | null | null | #include "discord.h" | 20 | 20 | 0.75 |
6b2a4d8e77c415e877fe0bf3eb5fc4879a21929e | 415 | c | C | nemu/src/cpu/exec/data-mov/mov.c | ryanhe312/nemu-lab | a939001d77eea61ab7926af94e501ec03c9c45ff | [
"Apache-2.0"
] | 29 | 2017-07-30T07:46:11.000Z | 2021-11-21T15:51:04.000Z | nemu/src/cpu/exec/data-mov/mov.c | jasha64/ics2015 | b6073effe3a7f4f73e60163b060274350a243d10 | [
"MIT"
] | 2 | 2018-03-22T10:09:35.000Z | 2021-09-12T16:08:35.000Z | nemu/src/cpu/exec/data-mov/mov.c | jasha64/ics2015 | b6073effe3a7f4f73e60163b060274350a243d10 | [
"MIT"
] | 9 | 2018-09-03T13:14:08.000Z | 2021-06-25T17:00:46.000Z | #include "cpu/exec/helper.h"
#define DATA_BYTE 1
#include "mov-template.h"
#undef DATA_BYTE
#define DATA_BYTE 2
#include "mov-template.h"
#undef DATA_BYTE
#define DATA_BYTE 4
#include "mov-template.h"
#undef DATA_BYTE
/* for instruction encoding overloading */
make_helper_v(mov_i2r)
make_helper_v(mov_i2rm)
make_helper_v(mov_r2rm)
make_helper_v(mov_rm2r)
make_helper_v(mov_a2moffs)
make_helper_v(mov_moffs2a)
| 18.043478 | 42 | 0.8 |
5c3adbbf6805a38e502780563843bc3167ee11c5 | 471 | h | C | Project/zoolib/Dataspace/Tests.h | ElectricMagic/zoolib_cxx | cb3ccfde931b3989cd420fa093153204a7899805 | [
"MIT"
] | 13 | 2015-01-28T21:05:09.000Z | 2021-11-03T22:21:11.000Z | Project/zoolib/Dataspace/Tests.h | ElectricMagic/zoolib_cxx | cb3ccfde931b3989cd420fa093153204a7899805 | [
"MIT"
] | null | null | null | Project/zoolib/Dataspace/Tests.h | ElectricMagic/zoolib_cxx | cb3ccfde931b3989cd420fa093153204a7899805 | [
"MIT"
] | 4 | 2018-11-16T08:33:33.000Z | 2021-12-11T19:40:46.000Z | // Copyright (c) 2019 Andrew Green. MIT License. http://www.zoolib.org
#ifndef __ZooLib_Dataspace_Tests_h__
#define __ZooLib_Dataspace_Tests_h__
#include "zconfig.h"
namespace ZooLib {
namespace Dataspace {
namespace Tests {
// =================================================================================================
#pragma mark -
void RunTests();
} // namespace Tests
} // namespace Dataspace
} // namespace ZooLib
#endif // __ZooLib_Dataspace_Tests_h__
| 22.428571 | 100 | 0.600849 |
1d0f86dbb6ed24a995e775c484d88d82f21b7a1d | 238 | h | C | Engine/src/core/Entity.h | ilkp/IlkanPelimoottori2 | a4c4e203fc39113e47a1c825547c606392e93429 | [
"MIT"
] | null | null | null | Engine/src/core/Entity.h | ilkp/IlkanPelimoottori2 | a4c4e203fc39113e47a1c825547c606392e93429 | [
"MIT"
] | null | null | null | Engine/src/core/Entity.h | ilkp/IlkanPelimoottori2 | a4c4e203fc39113e47a1c825547c606392e93429 | [
"MIT"
] | null | null | null | #pragma once
#include <cstdint>
namespace idop
{
class Entity
{
public:
const uint32_t _entityId;
Entity(uint32_t entityId) : _entityId(entityId) {}
};
class EntityBlock
{
public:
uint32_t _idBegin;
uint32_t _size;
};
} | 11.9 | 52 | 0.697479 |
5925d11e2466dfdadc04076ca4b85e4de96158f2 | 14,661 | c | C | linux-4.4-zynq/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | beehive-lab/FastPath_MP | 2fb19330caca92f9821b38da759530ef5419fdee | [
"Apache-2.0"
] | 16 | 2021-04-20T04:25:45.000Z | 2022-02-07T15:58:16.000Z | linux-4.4-zynq/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | beehive-lab/FastPath_MP | 2fb19330caca92f9821b38da759530ef5419fdee | [
"Apache-2.0"
] | null | null | null | linux-4.4-zynq/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | beehive-lab/FastPath_MP | 2fb19330caca92f9821b38da759530ef5419fdee | [
"Apache-2.0"
] | 2 | 2021-08-02T21:41:09.000Z | 2021-09-29T13:33:24.000Z | /*
* Xilinx DRM crtc driver for Xilinx
*
* Copyright (C) 2013 Xilinx, Inc.
*
* Author: Hyun Woo Kwon <hyunk@xilinx.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <video/videomode.h>
#include "xilinx_drm_crtc.h"
#include "xilinx_drm_dp_sub.h"
#include "xilinx_drm_drv.h"
#include "xilinx_drm_plane.h"
#include "xilinx_cresample.h"
#include "xilinx_rgb2yuv.h"
#include "xilinx_vtc.h"
struct xilinx_drm_crtc {
struct drm_crtc base;
struct xilinx_cresample *cresample;
struct xilinx_rgb2yuv *rgb2yuv;
struct clk *pixel_clock;
struct xilinx_vtc *vtc;
struct xilinx_drm_plane_manager *plane_manager;
int dpms;
unsigned int alpha;
struct drm_pending_vblank_event *event;
struct xilinx_drm_dp_sub *dp_sub;
};
#define to_xilinx_crtc(x) container_of(x, struct xilinx_drm_crtc, base)
/* set crtc dpms */
static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
DRM_DEBUG_KMS("dpms: %d -> %d\n", crtc->dpms, dpms);
if (crtc->dpms == dpms)
return;
crtc->dpms = dpms;
switch (dpms) {
case DRM_MODE_DPMS_ON:
xilinx_drm_plane_manager_dpms(crtc->plane_manager, dpms);
xilinx_drm_plane_dpms(base_crtc->primary, dpms);
if (crtc->rgb2yuv)
xilinx_rgb2yuv_enable(crtc->rgb2yuv);
if (crtc->cresample)
xilinx_cresample_enable(crtc->cresample);
if (crtc->vtc)
xilinx_vtc_enable(crtc->vtc);
break;
default:
if (crtc->vtc) {
xilinx_vtc_disable(crtc->vtc);
xilinx_vtc_reset(crtc->vtc);
}
if (crtc->cresample) {
xilinx_cresample_disable(crtc->cresample);
xilinx_cresample_reset(crtc->cresample);
}
if (crtc->rgb2yuv) {
xilinx_rgb2yuv_disable(crtc->rgb2yuv);
xilinx_rgb2yuv_reset(crtc->rgb2yuv);
}
xilinx_drm_plane_dpms(base_crtc->primary, dpms);
xilinx_drm_plane_manager_dpms(crtc->plane_manager, dpms);
break;
}
}
/* prepare crtc */
static void xilinx_drm_crtc_prepare(struct drm_crtc *base_crtc)
{
xilinx_drm_crtc_dpms(base_crtc, DRM_MODE_DPMS_OFF);
}
/* apply mode to crtc pipe */
static void xilinx_drm_crtc_commit(struct drm_crtc *base_crtc)
{
xilinx_drm_crtc_dpms(base_crtc, DRM_MODE_DPMS_ON);
xilinx_drm_plane_commit(base_crtc->primary);
}
/* fix mode */
static bool xilinx_drm_crtc_mode_fixup(struct drm_crtc *base_crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
/* no op */
return true;
}
/* set new mode in crtc pipe */
static int xilinx_drm_crtc_mode_set(struct drm_crtc *base_crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
int x, int y,
struct drm_framebuffer *old_fb)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
struct videomode vm;
long diff;
int ret;
/* set pixel clock */
ret = clk_set_rate(crtc->pixel_clock, adjusted_mode->clock * 1000);
if (ret) {
DRM_ERROR("failed to set a pixel clock\n");
return ret;
}
diff = clk_get_rate(crtc->pixel_clock) - adjusted_mode->clock * 1000;
if (abs(diff) > (adjusted_mode->clock * 1000) / 20)
DRM_INFO("actual pixel clock rate(%d) is off by %ld\n",
adjusted_mode->clock, diff);
if (crtc->vtc) {
/* set video timing */
vm.hactive = adjusted_mode->hdisplay;
vm.hfront_porch = adjusted_mode->hsync_start -
adjusted_mode->hdisplay;
vm.hback_porch = adjusted_mode->htotal -
adjusted_mode->hsync_end;
vm.hsync_len = adjusted_mode->hsync_end -
adjusted_mode->hsync_start;
vm.vactive = adjusted_mode->vdisplay;
vm.vfront_porch = adjusted_mode->vsync_start -
adjusted_mode->vdisplay;
vm.vback_porch = adjusted_mode->vtotal -
adjusted_mode->vsync_end;
vm.vsync_len = adjusted_mode->vsync_end -
adjusted_mode->vsync_start;
xilinx_vtc_config_sig(crtc->vtc, &vm);
}
/* configure cresample and rgb2yuv */
if (crtc->cresample)
xilinx_cresample_configure(crtc->cresample,
adjusted_mode->hdisplay,
adjusted_mode->vdisplay);
if (crtc->rgb2yuv)
xilinx_rgb2yuv_configure(crtc->rgb2yuv,
adjusted_mode->hdisplay,
adjusted_mode->vdisplay);
/* configure a plane: vdma and osd layer */
xilinx_drm_plane_manager_mode_set(crtc->plane_manager,
adjusted_mode->hdisplay,
adjusted_mode->vdisplay);
ret = xilinx_drm_plane_mode_set(base_crtc->primary,
base_crtc->primary->fb, 0, 0,
adjusted_mode->hdisplay,
adjusted_mode->vdisplay,
x, y,
adjusted_mode->hdisplay,
adjusted_mode->vdisplay);
if (ret) {
DRM_ERROR("failed to mode set a plane\n");
return ret;
}
return 0;
}
static int _xilinx_drm_crtc_mode_set_base(struct drm_crtc *base_crtc,
struct drm_framebuffer *fb,
int x, int y)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
int ret;
/* configure a plane */
xilinx_drm_plane_manager_mode_set(crtc->plane_manager,
base_crtc->hwmode.hdisplay,
base_crtc->hwmode.vdisplay);
ret = xilinx_drm_plane_mode_set(base_crtc->primary,
fb, 0, 0,
base_crtc->hwmode.hdisplay,
base_crtc->hwmode.vdisplay,
x, y,
base_crtc->hwmode.hdisplay,
base_crtc->hwmode.vdisplay);
if (ret) {
DRM_ERROR("failed to mode set a plane\n");
return ret;
}
/* apply the new fb addr */
xilinx_drm_crtc_commit(base_crtc);
return 0;
}
/* update address and information from fb */
static int xilinx_drm_crtc_mode_set_base(struct drm_crtc *base_crtc,
int x, int y,
struct drm_framebuffer *old_fb)
{
/* configure a plane */
return _xilinx_drm_crtc_mode_set_base(base_crtc, base_crtc->primary->fb,
x, y);
}
/* load rgb LUT for crtc */
static void xilinx_drm_crtc_load_lut(struct drm_crtc *base_crtc)
{
/* no op */
}
static struct drm_crtc_helper_funcs xilinx_drm_crtc_helper_funcs = {
.dpms = xilinx_drm_crtc_dpms,
.prepare = xilinx_drm_crtc_prepare,
.commit = xilinx_drm_crtc_commit,
.mode_fixup = xilinx_drm_crtc_mode_fixup,
.mode_set = xilinx_drm_crtc_mode_set,
.mode_set_base = xilinx_drm_crtc_mode_set_base,
.load_lut = xilinx_drm_crtc_load_lut,
};
/* destroy crtc */
void xilinx_drm_crtc_destroy(struct drm_crtc *base_crtc)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
/* make sure crtc is off */
xilinx_drm_crtc_dpms(base_crtc, DRM_MODE_DPMS_OFF);
drm_crtc_cleanup(base_crtc);
if (crtc->dp_sub)
xilinx_drm_dp_sub_put(crtc->dp_sub);
clk_disable_unprepare(crtc->pixel_clock);
xilinx_drm_plane_remove_manager(crtc->plane_manager);
}
/* crtc set config helper */
int xilinx_drm_crtc_helper_set_config(struct drm_mode_set *set)
{
struct drm_device *drm = set->crtc->dev;
xilinx_drm_set_config(drm, set);
return drm_crtc_helper_set_config(set);
}
/* cancel page flip functions */
void xilinx_drm_crtc_cancel_page_flip(struct drm_crtc *base_crtc,
struct drm_file *file)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
struct drm_device *drm = base_crtc->dev;
struct drm_pending_vblank_event *event;
unsigned long flags;
spin_lock_irqsave(&drm->event_lock, flags);
event = crtc->event;
if (event && (event->base.file_priv == file)) {
crtc->event = NULL;
event->base.destroy(&event->base);
drm_vblank_put(drm, 0);
}
spin_unlock_irqrestore(&drm->event_lock, flags);
}
/* finish page flip functions */
static void xilinx_drm_crtc_finish_page_flip(struct drm_crtc *base_crtc)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
struct drm_device *drm = base_crtc->dev;
struct drm_pending_vblank_event *event;
unsigned long flags;
spin_lock_irqsave(&drm->event_lock, flags);
event = crtc->event;
crtc->event = NULL;
if (event) {
drm_send_vblank_event(drm, 0, event);
drm_vblank_put(drm, 0);
}
spin_unlock_irqrestore(&drm->event_lock, flags);
}
/* page flip functions */
static int xilinx_drm_crtc_page_flip(struct drm_crtc *base_crtc,
struct drm_framebuffer *fb,
struct drm_pending_vblank_event *event,
uint32_t page_flip_flags)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
struct drm_device *drm = base_crtc->dev;
unsigned long flags;
int ret;
spin_lock_irqsave(&drm->event_lock, flags);
if (crtc->event != NULL) {
spin_unlock_irqrestore(&drm->event_lock, flags);
return -EBUSY;
}
spin_unlock_irqrestore(&drm->event_lock, flags);
/* configure a plane */
ret = _xilinx_drm_crtc_mode_set_base(base_crtc, fb,
base_crtc->x, base_crtc->y);
if (ret) {
DRM_ERROR("failed to mode set a plane\n");
return ret;
}
base_crtc->primary->fb = fb;
if (event) {
event->pipe = 0;
drm_vblank_get(drm, 0);
spin_lock_irqsave(&drm->event_lock, flags);
crtc->event = event;
spin_unlock_irqrestore(&drm->event_lock, flags);
}
return 0;
}
/* vblank interrupt handler */
static void xilinx_drm_crtc_vblank_handler(void *data)
{
struct drm_crtc *base_crtc = data;
struct drm_device *drm;
if (!base_crtc)
return;
drm = base_crtc->dev;
drm_handle_vblank(drm, 0);
xilinx_drm_crtc_finish_page_flip(base_crtc);
}
/* enable vblank interrupt */
void xilinx_drm_crtc_enable_vblank(struct drm_crtc *base_crtc)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
if (crtc->vtc)
xilinx_vtc_enable_vblank_intr(crtc->vtc,
xilinx_drm_crtc_vblank_handler,
base_crtc);
if (crtc->dp_sub)
xilinx_drm_dp_sub_enable_vblank(crtc->dp_sub,
xilinx_drm_crtc_vblank_handler,
base_crtc);
}
/* disable vblank interrupt */
void xilinx_drm_crtc_disable_vblank(struct drm_crtc *base_crtc)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
if (crtc->dp_sub)
xilinx_drm_dp_sub_disable_vblank(crtc->dp_sub);
if (crtc->vtc)
xilinx_vtc_disable_vblank_intr(crtc->vtc);
}
/**
* xilinx_drm_crtc_restore - Restore the crtc states
* @base_crtc: base crtc object
*
* Restore the crtc states to the default ones. The request is propagated
* to the plane driver.
*/
void xilinx_drm_crtc_restore(struct drm_crtc *base_crtc)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
xilinx_drm_plane_restore(crtc->plane_manager);
}
/* check max width */
unsigned int xilinx_drm_crtc_get_max_width(struct drm_crtc *base_crtc)
{
return xilinx_drm_plane_get_max_width(base_crtc->primary);
}
/* check format */
bool xilinx_drm_crtc_check_format(struct drm_crtc *base_crtc, uint32_t fourcc)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
return xilinx_drm_plane_check_format(crtc->plane_manager, fourcc);
}
/* get format */
uint32_t xilinx_drm_crtc_get_format(struct drm_crtc *base_crtc)
{
return xilinx_drm_plane_get_format(base_crtc->primary);
}
/**
* xilinx_drm_crtc_get_align - Get the alignment value for pitch
* @base_crtc: Base crtc object
*
* Get the alignment value for pitch from the plane
*
* Return: The alignment value if successful, or the error code.
*/
unsigned int xilinx_drm_crtc_get_align(struct drm_crtc *base_crtc)
{
return xilinx_drm_plane_get_align(base_crtc->primary);
}
static struct drm_crtc_funcs xilinx_drm_crtc_funcs = {
.destroy = xilinx_drm_crtc_destroy,
.set_config = xilinx_drm_crtc_helper_set_config,
.page_flip = xilinx_drm_crtc_page_flip,
};
/* create crtc */
struct drm_crtc *xilinx_drm_crtc_create(struct drm_device *drm)
{
struct xilinx_drm_crtc *crtc;
struct drm_plane *primary_plane;
struct device_node *sub_node;
int possible_crtcs = 1;
int ret;
crtc = devm_kzalloc(drm->dev, sizeof(*crtc), GFP_KERNEL);
if (!crtc)
return ERR_PTR(-ENOMEM);
/* probe chroma resampler and enable */
sub_node = of_parse_phandle(drm->dev->of_node, "xlnx,cresample", 0);
if (sub_node) {
crtc->cresample = xilinx_cresample_probe(drm->dev, sub_node);
of_node_put(sub_node);
if (IS_ERR(crtc->cresample)) {
DRM_ERROR("failed to probe a cresample\n");
return ERR_CAST(crtc->cresample);
}
}
/* probe color space converter and enable */
sub_node = of_parse_phandle(drm->dev->of_node, "xlnx,rgb2yuv", 0);
if (sub_node) {
crtc->rgb2yuv = xilinx_rgb2yuv_probe(drm->dev, sub_node);
of_node_put(sub_node);
if (IS_ERR(crtc->rgb2yuv)) {
DRM_ERROR("failed to probe a rgb2yuv\n");
return ERR_CAST(crtc->rgb2yuv);
}
}
/* probe a plane manager */
crtc->plane_manager = xilinx_drm_plane_probe_manager(drm);
if (IS_ERR(crtc->plane_manager)) {
if ((int)crtc->plane_manager != -EPROBE_DEFER)
DRM_ERROR("failed to probe a plane manager\n");
return ERR_CAST(crtc->plane_manager);
}
/* create a primary plane. there's only one crtc now */
primary_plane = xilinx_drm_plane_create_primary(crtc->plane_manager,
possible_crtcs);
if (IS_ERR(primary_plane)) {
DRM_ERROR("failed to create a primary plane for crtc\n");
ret = PTR_ERR(primary_plane);
goto err_plane;
}
/* create extra planes */
xilinx_drm_plane_create_planes(crtc->plane_manager, possible_crtcs);
crtc->pixel_clock = devm_clk_get(drm->dev, NULL);
if (IS_ERR(crtc->pixel_clock)) {
DRM_DEBUG_KMS("failed to get pixel clock\n");
ret = -EPROBE_DEFER;
goto err_plane;
}
ret = clk_prepare_enable(crtc->pixel_clock);
if (ret) {
DRM_DEBUG_KMS("failed to prepare/enable clock\n");
goto err_plane;
}
sub_node = of_parse_phandle(drm->dev->of_node, "xlnx,vtc", 0);
if (sub_node) {
crtc->vtc = xilinx_vtc_probe(drm->dev, sub_node);
of_node_put(sub_node);
if (IS_ERR(crtc->vtc)) {
DRM_ERROR("failed to probe video timing controller\n");
ret = PTR_ERR(crtc->vtc);
goto err_plane;
}
}
crtc->dp_sub = xilinx_drm_dp_sub_of_get(drm->dev->of_node);
if (IS_ERR(crtc->dp_sub)) {
ret = PTR_ERR(crtc->dp_sub);
if (ret != -EPROBE_DEFER)
DRM_ERROR("failed to get a dp_sub\n");
goto err_plane;
}
crtc->dpms = DRM_MODE_DPMS_OFF;
/* initialize drm crtc */
ret = drm_crtc_init_with_planes(drm, &crtc->base, primary_plane,
NULL, &xilinx_drm_crtc_funcs);
if (ret) {
DRM_ERROR("failed to initialize crtc\n");
goto err_plane;
}
drm_crtc_helper_add(&crtc->base, &xilinx_drm_crtc_helper_funcs);
return &crtc->base;
err_plane:
xilinx_drm_plane_remove_manager(crtc->plane_manager);
return ERR_PTR(ret);
}
| 26.656364 | 78 | 0.733511 |
d9c013ba02fbe2c778797ba2a2c7dac7a41eb798 | 3,764 | c | C | topspek_functions/plotter.c | e-j-w/TopSpek | 6fd0332c3095fa12ba6fc0f8b72decd3df292033 | [
"MIT"
] | null | null | null | topspek_functions/plotter.c | e-j-w/TopSpek | 6fd0332c3095fa12ba6fc0f8b72decd3df292033 | [
"MIT"
] | null | null | null | topspek_functions/plotter.c | e-j-w/TopSpek | 6fd0332c3095fa12ba6fc0f8b72decd3df292033 | [
"MIT"
] | 1 | 2016-02-23T19:23:19.000Z | 2016-02-23T19:23:19.000Z | //handles the gnuplot prompt
void plotPrompt(int cont)
{
int c;
char inp[256];
if(cont==0)
printf("Enter 'g' for a gnuplot prompt or press [ENTER] to exit. ");
else
printf("Enter 'g' for a gnuplot prompt or press [ENTER] to continue. ");
c=getc(stdin);
if(c=='g')
{
printf("Enter 'exit' to return from the gnuplot prompt.\n");
fgets(inp,256,stdin);
while(strcmp(inp,"exit\n")!=0)
{
gnuplot_cmd(handle,inp);
printf("gnuplot > ");
fgets(inp,256,stdin);
}
}
return;
}
//function handles plotting of data, using the gnuplot_i library
void plotSpectra(const par * p, const data * d, const fitdata * fd)
{
char str[256];
int i,j,k;
//allocate arrays to hold plot data
double** x=allocateArrayD2(p->numSpectra,p->maxNumCh);
double** yexp=allocateArrayD2(p->numSpectra,p->maxNumCh);
double*** ysim=allocateArrayD3(NSIMDATA,p->numSpectra,p->maxNumCh);
double** ybackground=allocateArrayD2(p->numSpectra,p->maxNumCh);
double** ysimsum=allocateArrayD2(p->numSpectra,p->maxNumCh);
for (i=0;i<p->numSpectra;i++)
for (j=p->startCh[i];j<=p->endCh[i];j++)
{
x[i][j-p->startCh[i]]=(double)j;
yexp[i][j-p->startCh[i]]=(double)d->expHist[p->spectrum[i]][j];
if(abs(p->addBackground)>=1)
ybackground[i][j-p->startCh[i]]=fd->bgHist[i][j];
ysimsum[i][j-p->startCh[i]]=ybackground[i][j-p->startCh[i]];
for (k=0;k<p->numSimData;k++)
{
ysim[k][i][j-p->startCh[i]]=fd->scaledSimHist[k][i][j];
ysimsum[i][j-p->startCh[i]]+=fd->scaledSimHist[k][i][j];
}
}
plotOpen=1;
handle=gnuplot_init();
printf("\nDATA PLOTS\n----------\n");
//printf("Use 'l' in the plotting window to switch between linear and logarithmic scale.\n");
for(i=0;i<p->numSpectra;i++)
{
gnuplot_setstyle(handle,"steps");
gnuplot_cmd(handle,"set xlabel 'Channel'");
gnuplot_cmd(handle,"set ylabel 'Counts'");
gnuplot_plot_xy(handle, x[i], yexp[i], p->endCh[i]-p->startCh[i]+1, "Experiment");
if(p->plotOutput>1)//detailed plot
{
if(abs(p->addBackground)>=1)//plot background
{
gnuplot_setstyle(handle,"lines"); //plot background as a line
gnuplot_plot_xy(handle, x[i], ybackground[i], p->endCh[i]-p->startCh[i]+1, "Background");
gnuplot_setstyle(handle,"steps"); //set the plot style back
}
for (j=0;j<p->numSimData;j++)//plot individual sim data
{
sprintf(str,"Simulation (%s)",p->simDataName[j]);
gnuplot_plot_xy(handle, x[i], ysim[j][i], p->endCh[i]-p->startCh[i]+1, str);
}
if((p->numSimData>1)||(abs(p->addBackground)>=1))//plot sum
{
gnuplot_setcolor(handle, "black");
gnuplot_plot_xy(handle, x[i], ysimsum[i], p->endCh[i]-p->startCh[i]+1, "Simulation and Background(sum)");
gnuplot_unsetcolor(handle);
}
}
else //simple plot
gnuplot_plot_xy(handle, x[i], ysimsum[i], p->endCh[i]-p->startCh[i]+1, "Simulation and Background(sum)");
printf("Showing plot for spectrum %i, channel %i to %i.\n", p->spectrum[i],p->startCh[i],p->endCh[i]);
if(i!=p->numSpectra-1)//check whether we're showing the last plot
plotPrompt(1);
else
plotPrompt(0);
gnuplot_resetplot(handle);
}
gnuplot_close(handle);
plotOpen=0;
free(x);
free(yexp);
free(ysim);
free(ybackground);
free(ysimsum);
}
//function run after CTRL-C, used to clean up temporary files generated
//by the plotting library
void sigint_cleanup()
{
if(plotOpen==1)
gnuplot_close(handle); //cleans up temporary files
exit(1);
}
| 33.90991 | 119 | 0.595643 |
69ea275e60e9bd04f9af06fdeff4b858f0cbd120 | 1,067 | h | C | MailHeaders/Mavericks_GM/MailFW/MFIMAPOperation.h | w-i-n-s/SimplePlugin | b834309d470de50b2eac29d5c4488a1942bab925 | [
"MIT"
] | 10 | 2015-02-19T21:47:05.000Z | 2021-04-23T10:40:12.000Z | MailHeaders/Mavericks_GM/MailFW/MFIMAPOperation.h | w-i-n-s/SimplePlugin | b834309d470de50b2eac29d5c4488a1942bab925 | [
"MIT"
] | null | null | null | MailHeaders/Mavericks_GM/MailFW/MFIMAPOperation.h | w-i-n-s/SimplePlugin | b834309d470de50b2eac29d5c4488a1942bab925 | [
"MIT"
] | 2 | 2018-03-04T02:29:41.000Z | 2021-02-09T20:42:21.000Z | /*
* Generated by class-dump 3.4 (64 bit).
*
* class-dump is Copyright (C) 1997-1998, 2000-2001, 2004-2012 by Steve Nygard.
*/
#import "NSObject.h"
@class NSString;
@interface MFIMAPOperation : NSObject
{
BOOL _usesRealUids;
NSString *_mailboxName;
}
+ (id)newOperationWithSerializedData:(id)arg1 cursor:(unsigned long long *)arg2;
@property(nonatomic) BOOL usesRealUids; // @synthesize usesRealUids=_usesRealUids;
@property(copy, nonatomic) NSString *mailboxName; // @synthesize mailboxName=_mailboxName;
- (unsigned int)lastTemporaryUid;
- (unsigned int)firstTemporaryUid;
- (void)expungeTemporaryUid:(unsigned int)arg1;
- (BOOL)actsOnTemporaryUid:(unsigned int)arg1;
- (BOOL)isSourceOfTemporaryUid:(unsigned int)arg1;
- (unsigned long long)approximateSize;
@property(readonly, nonatomic) unsigned char operationType;
- (void)dealloc;
- (id)init;
- (id)_initWithMailboxName:(id)arg1;
- (void)serializeIntoData:(id)arg1;
- (void)_deserializeOpSpecificValuesFromData:(id)arg1 cursor:(unsigned long long *)arg2;
- (unsigned char)_magic;
@end
| 29.638889 | 90 | 0.753515 |
cde087d2bdf41c224333dcf0c5b26e6bd6f5b6c7 | 966 | h | C | QSimZombie/QSimZombie/QSimZombie.h | ADozois/ZombieSim | 58672fc5b8dcbd4d0647651b2ed33320951841cb | [
"MIT"
] | null | null | null | QSimZombie/QSimZombie/QSimZombie.h | ADozois/ZombieSim | 58672fc5b8dcbd4d0647651b2ed33320951841cb | [
"MIT"
] | null | null | null | QSimZombie/QSimZombie/QSimZombie.h | ADozois/ZombieSim | 58672fc5b8dcbd4d0647651b2ed33320951841cb | [
"MIT"
] | null | null | null | #ifndef Q_SIM_ZOMBIE_H
#define Q_SIM_ZOMBIE_H
#include "QSimulationTab.h"//Tabs: Simulation, Statistics, Parameters.
#include "QStatisticsTab.h"
#include "QParametersTab.h"
#include <QtWidgets/QMainWindow>
#include "ui_QSimZombie.h"
#include <QMenuBar>//QWidgets
#include <QLayout>
#include <QLabel>
#include <QTabWidget>
#include <QSplitter>
class QSimZombie : public QMainWindow
{
Q_OBJECT
public:
QSimZombie(QWidget *parent = Q_NULLPTR);
public slots:
void setupSim();
void activateParametersTab();
void disableParametersTab();
void activateStatTab();
void disableStatTab();
private:
Ui::QSimZombieClass ui;
QMenuBar *mMenuBar;
QLayout *mMainLayout;
QLabel *mLabel;
QTabWidget *mTabWidget;
QSplitter *mSplitter;
QSimulationTab *mSimTab;
QStatisticsTab *mStatTab;
QParametersTab *mParamTab;
TimeLord * mLord;
int mSimTabIndex{ 0 };
int mStatTabIndex{ 1 };
int mParamTabIndex{ 2 };
void setupSimTab();
};
#endif //Q_SIM_ZOMBIE_H | 17.563636 | 70 | 0.757764 |
079bf4c864f1ea3e8d91ee9e70322f5566c20bee | 10,908 | c | C | boards/arm/stm32/px_hero/apps/cli_explorer/src/px_cli_cmds_uart.c | piconomix/piconomix-fwlib | 83ad1a9973cd53240408ab45d129e733f1505d9a | [
"MIT"
] | 225 | 2018-09-07T12:26:13.000Z | 2021-08-06T06:53:40.000Z | boards/arm/stm32/px_hero/apps/cli_explorer/src/px_cli_cmds_uart.c | piconomix/piconomix-fwlib | 83ad1a9973cd53240408ab45d129e733f1505d9a | [
"MIT"
] | 8 | 2019-10-18T15:26:14.000Z | 2021-05-11T14:10:57.000Z | boards/arm/stm32/px_hero/apps/cli_explorer/src/px_cli_cmds_uart.c | piconomix/px-fwlib | 862b7b7995bad3935585b41047a823bdbe8bceba | [
"MIT"
] | 25 | 2018-11-11T05:56:08.000Z | 2021-07-20T14:38:09.000Z | /* =============================================================================
____ ___ ____ ___ _ _ ___ __ __ ___ __ __ TM
| _ \ |_ _| / ___| / _ \ | \ | | / _ \ | \/ | |_ _| \ \/ /
| |_) | | | | | | | | | | \| | | | | | | |\/| | | | \ /
| __/ | | | |___ | |_| | | |\ | | |_| | | | | | | | / \
|_| |___| \____| \___/ |_| \_| \___/ |_| |_| |___| /_/\_\
Copyright (c) 2014 Pieter Conradie <https://piconomix.com>
License: MIT
https://github.com/piconomix/px-fwlib/blob/master/LICENSE.md
Title: px_cli_cmds_uart.h : CLI commands for UART
Author(s): Pieter Conradie
Creation Date: 2014-05-31
============================================================================= */
/* _____STANDARD INCLUDES____________________________________________________ */
/* _____PROJECT INCLUDES_____________________________________________________ */
#include "px_board.h"
#include "main.h"
#include "px_uart.h"
#include "px_cli.h"
#include "px_pgm_P.h"
#include "px_systmr.h"
#include "px_usb_cdc_stdio.h"
#include "px_log.h"
/* _____LOCAL DEFINITIONS____________________________________________________ */
PX_LOG_NAME("cli_cmds_uart");
/* _____MACROS_______________________________________________________________ */
/* _____GLOBAL VARIABLES_____________________________________________________ */
/* _____LOCAL VARIABLES______________________________________________________ */
static px_uart_handle_t px_uart_handle;
static bool px_uart_handle_open;
/* _____LOCAL FUNCTION DECLARATIONS__________________________________________ */
/* _____LOCAL FUNCTIONS______________________________________________________ */
static const char * px_cli_cmd_fn_uart_cfg(uint8_t argc, char * argv[])
{
px_uart_nr_t per;
uint32_t baud_rate_hz;
px_uart_data_bits_t data_bits = PX_UART_DATA_BITS_8;
px_uart_parity_t parity = PX_UART_PARITY_NONE;
px_uart_stop_bits_t stop_bits = PX_UART_STOP_BITS_1;
// <per>
switch(argv[0][0])
{
case '2': per = PX_UART_NR_2; break;
case '4': per = PX_UART_NR_4; break;
default:
return "Error. <per> must be 2 or 4";
}
// <baud>
if(!px_cli_util_argv_to_u32(1, 300, PX_BOARD_PER_CLK_HZ/16))
{
printf("Error. <baud> must be 300 to %lu\n", PX_BOARD_PER_CLK_HZ/16);
return NULL;
}
baud_rate_hz = px_cli_argv_val.u32;
// [data]>
if(argc >= 3)
{
switch(argv[2][0])
{
case '7': data_bits = PX_UART_DATA_BITS_7; break;
case '8': data_bits = PX_UART_DATA_BITS_8; break;
case '9': data_bits = PX_UART_DATA_BITS_9; break;
default: return "Error. [data] must be 7, 8 or 9";
}
}
// [parity]
if(argc >= 4)
{
switch(argv[3][0])
{
case 'n': parity = PX_UART_PARITY_NONE; break;
case 'o': parity = PX_UART_PARITY_ODD; break;
case 'e': parity = PX_UART_PARITY_EVEN; break;
default: return "Error. [parity] must be n (none), o (odd) or e (even)";
}
}
// [stop]
if(argc >= 5)
{
switch(argv[4][0])
{
case '1': stop_bits = PX_UART_STOP_BITS_1; break;
case '2': stop_bits = PX_UART_STOP_BITS_2; break;
default: return "Error. [stop] must be 1 or 2";
}
}
// Handle already open?
if(px_uart_handle_open)
{
// Close handle first
px_uart_close(&px_uart_handle);
}
// Open UART device handle
if(!px_uart_open2(&px_uart_handle,
per,
baud_rate_hz,
data_bits,
parity,
stop_bits))
{
return "Error. Incorrect parameters; unable to initialise UART";
}
// Set flag
px_uart_handle_open = true;
return NULL;
}
static const char * px_cli_cmd_fn_uart_bridge(uint8_t argc, char * argv[])
{
uint8_t data;
// Button is pressed?
while(!PX_USR_PB_IS_PRESSED())
{
// Any byte received from console?
if(px_usb_cdc_stdio_rd_u8(&data))
{
// Send byte to UART
px_uart_putchar(&px_uart_handle, data);
}
// Any byte received from UART?
if(px_uart_rd_u8(&px_uart_handle, &data))
{
// Send byte to console
while(!px_usb_cdc_stdio_wr_u8(data)) {;}
}
}
// Wait until button is released
while(PX_USR_PB_IS_PRESSED()) {;}
putchar('\n');
return NULL;
}
static const char * px_cli_cmd_fn_uart_write(uint8_t argc, char * argv[])
{
uint8_t i;
// <data>
for(i = 0; i < argc; i++)
{
if(!px_cli_util_argv_to_u8(i, 0, 255))
{
printf("Error. <data> at index %d invalid\n", i);
return NULL;
}
px_uart_putchar(&px_uart_handle, (char)px_cli_argv_val.u8);
}
return NULL;
}
static const char * px_cli_cmd_fn_uart_receive(uint8_t argc, char * argv[])
{
uint8_t i;
uint8_t nr_of_bytes;
uint16_t timeout_ms;
uint8_t data[16];
px_systmr_t tmr;
// <nr of bytes>
if(!px_cli_util_argv_to_u8(0, 0, 16))
{
return "Error. <nr of bytes> must be 0 to 16";
}
nr_of_bytes = px_cli_argv_val.u8;
// <timeout ms>
if(!px_cli_util_argv_to_u16(1, 0, 65535))
{
return "Error. <timeout ms> must be 0 to 65535";
}
timeout_ms = px_cli_argv_val.u16;
// Start timeout
px_systmr_start(&tmr, PX_SYSTMR_MS_TO_TICKS(timeout_ms));
// Try to receive specified number of bytes
i = 0;
while(!px_systmr_has_expired(&tmr))
{
if(px_uart_rd_u8(&px_uart_handle, &data[i]))
{
if(++i >= nr_of_bytes)
{
break;
}
}
}
nr_of_bytes = i;
// Report received bytes
for(i = 0; i < nr_of_bytes; i++)
{
printf("0x%02x ", data[i]);
}
putchar('\n');
return NULL;
}
static const char * px_cli_cmd_fn_uart_exchange(uint8_t argc, char * argv[])
{
uint8_t i;
uint8_t nr_of_bytes;
uint16_t timeout_ms;
uint8_t data[16];
px_systmr_t tmr;
// <nr of bytes>
if(!px_cli_util_argv_to_u8(0, 0, 16))
{
return "Error. <r nr of bytes> must be 0 to 16";
}
nr_of_bytes = px_cli_argv_val.u8;
// <timeout ms>
if(!px_cli_util_argv_to_u16(1, 0, 65535))
{
return "Error. <r timeout ms> must be 0 to 65535";
}
timeout_ms = px_cli_argv_val.u16;
// <data>
for(i = 2; i < argc; i++)
{
if(!px_cli_util_argv_to_u8(i, 0, 255))
{
printf("Error. <data> at index %d invalid\n", i);
return NULL;
}
px_uart_putchar(&px_uart_handle, (char)px_cli_argv_val.u8);
}
// Start timeout
px_systmr_start(&tmr, PX_SYSTMR_MS_TO_TICKS(timeout_ms));
// Try to receive specified number of bytes
i = 0;
while(!px_systmr_has_expired(&tmr))
{
if(px_uart_rd_u8(&px_uart_handle, &data[i]))
{
if(++i >= nr_of_bytes)
{
break;
}
}
}
nr_of_bytes = i;
// Report received bytes
for(i = 0; i < nr_of_bytes; i++)
{
printf("0x%02x ", data[i]);
}
putchar('\n');
return NULL;
}
static const char * px_cli_cmd_fn_uart_str(uint8_t argc, char * argv[])
{
uint16_t timeout_ms;
char * tx_char;
char rx_char;
px_systmr_t tmr;
// <timeout ms>
if(!px_cli_util_argv_to_u16(0, 0, 65535))
{
return "Error. <r timeout ms> must be 0 to 65535";
}
timeout_ms = px_cli_argv_val.u16;
// <"w str">
tx_char = argv[1];
while(*tx_char != '\0')
{
px_uart_putchar(&px_uart_handle, *tx_char++);
}
// [cr|lf|crlf]
if(argc == 3)
{
switch(px_cli_util_argv_to_option(2, "cr\0lf\0crlf\0"))
{
case 0:
px_uart_putchar(&px_uart_handle, '\r');
break;
case 1:
px_uart_putchar(&px_uart_handle, '\n');
break;
case 2:
px_uart_putchar(&px_uart_handle, '\r');
px_uart_putchar(&px_uart_handle, '\n');
break;
default:
return "Error: [cr|lf|crlf] must be cr (Carriage Return) or lf (Line Feed) or crlf (CR+LF)";
}
}
// Start timeout
px_systmr_start(&tmr, PX_SYSTMR_MS_TO_TICKS(timeout_ms));
// Receive characters until timeout or NULL, CR of LF is received
while(!px_systmr_has_expired(&tmr))
{
if(px_uart_rd_u8(&px_uart_handle, (uint8_t *)&rx_char))
{
// End of string?
if( (rx_char == '\r') || (rx_char == '\n') || (rx_char == '\0') )
{
break;
}
// Report received byte
putchar(rx_char);
}
}
// Terminate string
putchar('\n');
return NULL;
}
// Create CLI command structures
PX_CLI_CMD_CREATE(px_cli_cmd_uart_cfg, "cfg", 2, 5, "<per> <baud> [data] [parity] [stop]", "Configure UART")
PX_CLI_CMD_CREATE(px_cli_cmd_uart_bridge, "b", 0, 0, "", "Bridge Console<->UART until button is pressed")
PX_CLI_CMD_CREATE(px_cli_cmd_uart_write, "w", 1, 16, "<d0> .. [d15]", "Write 1 to 16 bytes of data")
PX_CLI_CMD_CREATE(px_cli_cmd_uart_receive, "r", 2, 2, "<nr of bytes> <timeout ms>", "Receive up to 16 bytes of data or until timeout")
PX_CLI_CMD_CREATE(px_cli_cmd_uart_exchange, "x", 3, 18, "<nr of bytes> <timeout ms> <d0> .. [d15]", "Write 1 to 16 bytes of data and receive up to 16 bytes of data")
PX_CLI_CMD_CREATE(px_cli_cmd_uart_str, "s", 2, 3, "<timeout ms> <\"w str\"> [cr|lf|crlf]", "Write str and receive str. Use quotes if str has spaces")
PX_CLI_GROUP_CREATE(px_cli_group_uart, "uart")
PX_CLI_CMD_ADD(px_cli_cmd_uart_cfg, px_cli_cmd_fn_uart_cfg)
PX_CLI_CMD_ADD(px_cli_cmd_uart_bridge, px_cli_cmd_fn_uart_bridge)
PX_CLI_CMD_ADD(px_cli_cmd_uart_write, px_cli_cmd_fn_uart_write)
PX_CLI_CMD_ADD(px_cli_cmd_uart_receive, px_cli_cmd_fn_uart_receive)
PX_CLI_CMD_ADD(px_cli_cmd_uart_exchange, px_cli_cmd_fn_uart_exchange)
PX_CLI_CMD_ADD(px_cli_cmd_uart_str, px_cli_cmd_fn_uart_str)
PX_CLI_GROUP_END()
| 30.049587 | 172 | 0.550972 |
81d97ebdcdaf94868d02e73178199c3639a9170e | 13,746 | h | C | src/video/yuv2rgb/yuv_rgb.h | GaryOderNichts/SDL | d516577d4feb348fb01900811eb9de6cbb014b94 | [
"Zlib"
] | 13,885 | 2018-08-03T17:46:24.000Z | 2022-03-31T14:26:19.000Z | src/video/yuv2rgb/yuv_rgb.h | GaryOderNichts/SDL | d516577d4feb348fb01900811eb9de6cbb014b94 | [
"Zlib"
] | 5,122 | 2021-02-10T21:56:28.000Z | 2022-03-31T23:05:15.000Z | src/video/yuv2rgb/yuv_rgb.h | GaryOderNichts/SDL | d516577d4feb348fb01900811eb9de6cbb014b94 | [
"Zlib"
] | 1,860 | 2017-10-20T05:22:35.000Z | 2022-03-27T10:54:14.000Z | // Copyright 2016 Adrien Descamps
// Distributed under BSD 3-Clause License
// Provide optimized functions to convert images from 8bits yuv420 to rgb24 format
// There are a few slightly different variations of the YCbCr color space with different parameters that
// change the conversion matrix.
// The three most common YCbCr color space, defined by BT.601, BT.709 and JPEG standard are implemented here.
// See the respective standards for details
// The matrix values used are derived from http://www.equasys.de/colorconversion.html
// YUV420 is stored as three separate channels, with U and V (Cb and Cr) subsampled by a 2 factor
// For conversion from yuv to rgb, no interpolation is done, and the same UV value are used for 4 rgb pixels. This
// is suboptimal for image quality, but by far the fastest method.
// For all methods, width and height should be even, if not, the last row/column of the result image won't be affected.
// For sse methods, if the width if not divisable by 32, the last (width%32) pixels of each line won't be affected.
#include "SDL_stdinc.h"
/*#include <stdint.h>*/
typedef enum
{
YCBCR_JPEG,
YCBCR_601,
YCBCR_709
} YCbCrType;
// yuv to rgb, standard c implementation
void yuv420_rgb565_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_rgb24_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_rgba_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_bgra_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_argb_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_abgr_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_rgb565_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_rgb24_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_rgba_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_bgra_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_argb_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_abgr_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_rgb565_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_rgb24_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_rgba_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_bgra_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_argb_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_abgr_std(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
// yuv to rgb, sse implementation
// pointers must be 16 byte aligned, and strides must be divisable by 16
void yuv420_rgb565_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_rgb24_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_rgba_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_bgra_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_argb_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_abgr_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_rgb565_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_rgb24_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_rgba_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_bgra_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_argb_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_abgr_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_rgb565_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_rgb24_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_rgba_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_bgra_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_argb_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_abgr_sse(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
// yuv to rgb, sse implementation
// pointers do not need to be 16 byte aligned
void yuv420_rgb565_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_rgb24_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_rgba_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_bgra_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_argb_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv420_abgr_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_rgb565_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_rgb24_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_rgba_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_bgra_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_argb_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuv422_abgr_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_rgb565_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_rgb24_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_rgba_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_bgra_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_argb_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
void yuvnv12_abgr_sseu(
uint32_t width, uint32_t height,
const uint8_t *y, const uint8_t *u, const uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
uint8_t *rgb, uint32_t rgb_stride,
YCbCrType yuv_type);
// rgb to yuv, standard c implementation
void rgb24_yuv420_std(
uint32_t width, uint32_t height,
const uint8_t *rgb, uint32_t rgb_stride,
uint8_t *y, uint8_t *u, uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
YCbCrType yuv_type);
// rgb to yuv, sse implementation
// pointers must be 16 byte aligned, and strides must be divisible by 16
void rgb24_yuv420_sse(
uint32_t width, uint32_t height,
const uint8_t *rgb, uint32_t rgb_stride,
uint8_t *y, uint8_t *u, uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
YCbCrType yuv_type);
// rgb to yuv, sse implementation
// pointers do not need to be 16 byte aligned
void rgb24_yuv420_sseu(
uint32_t width, uint32_t height,
const uint8_t *rgb, uint32_t rgb_stride,
uint8_t *y, uint8_t *u, uint8_t *v, uint32_t y_stride, uint32_t uv_stride,
YCbCrType yuv_type);
| 35.984293 | 119 | 0.768442 |
9893030d3e4271dd98a87b90cba31eb8eba466c2 | 18,082 | c | C | stack/framework/hal/platforms/EZR32LG_WSTK6200A/kits/common/drivers/caplesense.c | rickiewars/dash7-ap-open-source-stack | 34cd88c581bc975b0c747e383a7dd07ccb5b44df | [
"Apache-2.0"
] | 86 | 2015-10-29T01:13:00.000Z | 2021-08-15T18:16:58.000Z | stack/framework/hal/platforms/EZR32LG_WSTK6200A/kits/common/drivers/caplesense.c | rickiewars/dash7-ap-open-source-stack | 34cd88c581bc975b0c747e383a7dd07ccb5b44df | [
"Apache-2.0"
] | 66 | 2015-11-18T20:34:37.000Z | 2021-05-26T07:53:52.000Z | stack/framework/hal/platforms/EZR32LG_WSTK6200A/kits/common/drivers/caplesense.c | rickiewars/dash7-ap-open-source-stack | 34cd88c581bc975b0c747e383a7dd07ccb5b44df | [
"Apache-2.0"
] | 68 | 2015-09-24T11:26:59.000Z | 2021-04-06T10:55:30.000Z | /**************************************************************************//**
* @file
* @brief Capacitive sense driver
* @version 4.1.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* This file is licensed under the Silabs License Agreement. See the file
* "Silabs_License_Agreement.txt" for details. Before using this software for
* any purpose, you must agree to the terms of that agreement.
*
******************************************************************************/
/* EM header files */
#include "em_device.h"
/* Drivers */
#include "caplesense.h"
#include "em_emu.h"
#include "em_acmp.h"
#include "em_assert.h"
#include "em_cmu.h"
#include "em_emu.h"
#include "em_gpio.h"
#include "em_int.h"
#include "em_lesense.h"
/* Capacitive sense configuration */
#include "caplesenseconfig.h"
/**************************************************************************//**
* @brief This vector stores the latest read values from LESENSE
* @param LESENSE_CHANNELS Vector of channels.
*****************************************************************************/
static volatile uint32_t channelValues[LESENSE_CHANNELS] =
{
/* Ch0, Ch1, Ch2, Ch3, Ch4, Ch5, Ch6, Ch7 */
0, 0, 0, 0, 0, 0, 0, 0,
/* Ch8, Ch9, Ch10, Ch11, Ch12, Ch13, Ch14, Ch15 */
0, 0, 0, 0, 0, 0, 0, 0
};
/**************************************************************************//**
* @brief This stores the maximum values seen by a channel
* @param LESENSE_CHANNELS Vector of channels.
*****************************************************************************/
static volatile uint32_t channelMaxValues[LESENSE_CHANNELS] =
{
/* Ch0, Ch1, Ch2, Ch3, Ch4, Ch5, Ch6, Ch7 */
1, 1, 1, 1, 1, 1, 1, 1,
/* Ch8, Ch9, Ch11, Ch11, Ch12, Ch13, Ch14, Ch15 */
1, 1, 1, 1, 1, 1, 1, 1
};
/**************************************************************************//**
* @brief A bit vector which represents the channels to iterate through
* @param LESENSE_CHANNELS Vector of channels.
*****************************************************************************/
static const bool channelsInUse[LESENSE_CHANNELS] = LESENSE_CAPSENSE_CH_IN_USE;
/**************************************************************************//**
* Prototypes
*****************************************************************************/
void CAPLESENSE_setupCMU(void);
void CAPLESENSE_setupGPIO(void);
void CAPLESENSE_setupACMP(void);
/**************************************************************************//**
* Local variables
*****************************************************************************/
/** Callback function for LESENSE interrupts. */
static void (*lesenseScanCb)(void);
/** Callback function for LESENSE interrupts. */
static void (*lesenseChCb)(void);
/** The current channel we are sensing */
static volatile uint8_t currentChannel;
/**************************************************************************//**
* @brief Setup the CMU
*****************************************************************************/
void CAPLESENSE_setupCMU(void)
{
/* Ensure core frequency has been updated */
SystemCoreClockUpdate();
/* Select clock source for HF clock. */
CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO);
/* Select clock source for LFA clock. */
CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFRCO);
/* Select clock source for LFB clock. */
CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_Disabled);
/* Enable HF peripheral clock. */
CMU_ClockEnable(cmuClock_HFPER, 1);
/* Enable clock for GPIO. */
CMU_ClockEnable(cmuClock_GPIO, 1);
/* Enable clock for ACMP0. */
CMU_ClockEnable(cmuClock_ACMP0, 1);
/* Enable clock for ACMP1. */
CMU_ClockEnable(cmuClock_ACMP1, 1);
/* Enable CORELE clock. */
CMU_ClockEnable(cmuClock_CORELE, 1);
/* Enable clock for LESENSE. */
CMU_ClockEnable(cmuClock_LESENSE, 1);
/* Enable clock divider for LESENSE. */
CMU_ClockDivSet(cmuClock_LESENSE, cmuClkDiv_1);
}
/**************************************************************************//**
* @brief Setup the GPIO
*****************************************************************************/
void CAPLESENSE_setupGPIO(void)
{
/* Configure the drive strength of the ports for the light sensor. */
GPIO_DriveModeSet(CAPLESENSE_SLIDER_PORT0, gpioDriveModeStandard);
/* Initialize the 4 GPIO pins of the touch slider for using them as LESENSE
* scan channels for capacitive sensing. */
GPIO_PinModeSet(CAPLESENSE_SLIDER_PORT0, CAPLESENSE_SLIDER0_PIN, gpioModeDisabled, 0);
GPIO_PinModeSet(CAPLESENSE_SLIDER_PORT0, CAPLESENSE_SLIDER1_PIN, gpioModeDisabled, 0);
GPIO_PinModeSet(CAPLESENSE_SLIDER_PORT0, CAPLESENSE_SLIDER2_PIN, gpioModeDisabled, 0);
GPIO_PinModeSet(CAPLESENSE_SLIDER_PORT0, CAPLESENSE_SLIDER3_PIN, gpioModeDisabled, 0);
}
/**************************************************************************//**
* @brief Setup the ACMP
*****************************************************************************/
void CAPLESENSE_setupACMP(void)
{
/* ACMP capsense configuration constant table. */
static const ACMP_CapsenseInit_TypeDef initACMP =
{
.fullBias = false,
.halfBias = false,
.biasProg = 0x7,
.warmTime = acmpWarmTime512,
.hysteresisLevel = acmpHysteresisLevel7,
.resistor = acmpResistor0,
.lowPowerReferenceEnabled = false,
.vddLevel = 0x3D,
.enable = false
};
/* Configure ACMP locations, ACMP output to pin disabled. */
ACMP_GPIOSetup(ACMP0, 0, false, false);
ACMP_GPIOSetup(ACMP1, 0, false, false);
/* Initialize ACMPs in capacitive sense mode. */
ACMP_CapsenseInit(ACMP0, &initACMP);
ACMP_CapsenseInit(ACMP1, &initACMP);
/* Don't enable ACMP, LESENSE controls it! */
}
/**************************************************************************//**
* @brief Setup the LESENSE for capavitive sensing
* @param sleep If true, go into sleep mode.
*****************************************************************************/
void CAPLESENSE_setupLESENSE(bool sleep)
{
uint8_t i;
static bool init = true;
/* Array for storing the calibration values. */
static uint16_t capsenseCalibrateVals[4];
/* LESENSE channel configuration constant table in sense mode. */
static const LESENSE_ChAll_TypeDef initChsSense = LESENSE_CAPSENSE_SCAN_CONF_SENSE;
/* LESENSE channel configuration constant table in sleep mode. */
static const LESENSE_ChAll_TypeDef initChsSleep = LESENSE_CAPSENSE_SCAN_CONF_SLEEP;
/* LESENSE central configuration constant table. */
static const LESENSE_Init_TypeDef initLESENSE =
{
.coreCtrl =
{
.scanStart = lesenseScanStartPeriodic,
.prsSel = lesensePRSCh0,
.scanConfSel = lesenseScanConfDirMap,
.invACMP0 = false,
.invACMP1 = false,
.dualSample = false,
.storeScanRes = false,
.bufOverWr = true,
.bufTrigLevel = lesenseBufTrigHalf,
.wakeupOnDMA = lesenseDMAWakeUpDisable,
.biasMode = lesenseBiasModeDutyCycle,
.debugRun = false
},
.timeCtrl =
{
.startDelay = 0U
},
.perCtrl =
{
.dacCh0Data = lesenseDACIfData,
.dacCh0ConvMode = lesenseDACConvModeDisable,
.dacCh0OutMode = lesenseDACOutModeDisable,
.dacCh1Data = lesenseDACIfData,
.dacCh1ConvMode = lesenseDACConvModeDisable,
.dacCh1OutMode = lesenseDACOutModeDisable,
.dacPresc = 0U,
.dacRef = lesenseDACRefBandGap,
.acmp0Mode = lesenseACMPModeMuxThres,
.acmp1Mode = lesenseACMPModeMuxThres,
.warmupMode = lesenseWarmupModeNormal
},
.decCtrl =
{
.decInput = lesenseDecInputSensorSt,
.chkState = false,
.intMap = true,
.hystPRS0 = false,
.hystPRS1 = false,
.hystPRS2 = false,
.hystIRQ = false,
.prsCount = true,
.prsChSel0 = lesensePRSCh0,
.prsChSel1 = lesensePRSCh1,
.prsChSel2 = lesensePRSCh2,
.prsChSel3 = lesensePRSCh3
}
};
/* Only initialize main LESENSE parameters once. */
if (init)
{
/* Initialize LESENSE interface with RESET. */
LESENSE_Init(&initLESENSE, true);
}
/* Different configuration for "sleep" and "sense" modes. */
if (sleep)
{
/* Stop LESENSE before configuration. */
LESENSE_ScanStop();
/* Wait until the currently active scan is finished. */
while (LESENSE_STATUS_SCANACTIVE & LESENSE_StatusGet()) ;
/* Clear result buffer. */
LESENSE_ResultBufferClear();
/* Set scan frequency (in Hz). */
(void) LESENSE_ScanFreqSet(0U, 4U);
/* Set clock divisor for LF clock. */
LESENSE_ClkDivSet(lesenseClkLF, lesenseClkDiv_1);
/* Configure scan channels. */
LESENSE_ChannelAllConfig(&initChsSleep);
/* Restore calibration values. */
LESENSE_ChannelThresSet(CAPLESENSE_SLIDER0_PIN, CAPLESENSE_ACMP_VDD_SCALE, capsenseCalibrateVals[0]);
LESENSE_ChannelThresSet(CAPLESENSE_SLIDER1_PIN, CAPLESENSE_ACMP_VDD_SCALE, capsenseCalibrateVals[1]);
LESENSE_ChannelThresSet(CAPLESENSE_SLIDER2_PIN, CAPLESENSE_ACMP_VDD_SCALE, capsenseCalibrateVals[2]);
LESENSE_ChannelThresSet(CAPLESENSE_SLIDER3_PIN, CAPLESENSE_ACMP_VDD_SCALE, capsenseCalibrateVals[3]);
/* Disable scan complete interrupt. */
LESENSE_IntDisable(LESENSE_IEN_SCANCOMPLETE);
}
else
{
/* Stop LESENSE before configuration. */
LESENSE_ScanStop();
/* Wait until the currently active scan is finished. */
while (LESENSE_STATUS_SCANACTIVE & LESENSE_StatusGet()) ;
/* Clean scan complete interrupt flag. */
LESENSE_IntClear(LESENSE_IEN_SCANCOMPLETE);
/* Clear result buffer. */
LESENSE_ResultBufferClear();
/* Set scan frequency (in Hz). */
(void) LESENSE_ScanFreqSet(0U, 64U);
/* Set clock divisor for LF clock. */
LESENSE_ClkDivSet(lesenseClkLF, lesenseClkDiv_8);
/* Configure scan channels. */
LESENSE_ChannelAllConfig(&initChsSense);
/* Enable scan complete interrupt. */
LESENSE_IntEnable(LESENSE_IEN_SCANCOMPLETE);
}
/* Enable LESENSE interrupt in NVIC. */
NVIC_EnableIRQ(LESENSE_IRQn);
/* Start scanning LESENSE channels. */
LESENSE_ScanStart();
/* Run it only once. */
if (init)
{
/* Assuming that the pads are not touched at first, we can use the result as
* the threshold value to calibrate the capacitive sensing in LESENSE. */
init = false;
/* Waiting for buffer to be full. */
while (!(LESENSE->STATUS & LESENSE_STATUS_BUFHALFFULL)) ;
/* Read out steady state values from LESENSE for calibration. */
for (i = 0U; i < CAPLESENSE_NUMOF_SLIDERS; i++)
{
capsenseCalibrateVals[i] = LESENSE_ScanResultDataBufferGet(i) - CAPLESENSE_SENSITIVITY_OFFS;
}
/* Set calibration values. */
LESENSE_ChannelThresSet(CAPLESENSE_SLIDER0_PIN, CAPLESENSE_ACMP_VDD_SCALE, capsenseCalibrateVals[0]);
LESENSE_ChannelThresSet(CAPLESENSE_SLIDER1_PIN, CAPLESENSE_ACMP_VDD_SCALE, capsenseCalibrateVals[1]);
LESENSE_ChannelThresSet(CAPLESENSE_SLIDER2_PIN, CAPLESENSE_ACMP_VDD_SCALE, capsenseCalibrateVals[2]);
LESENSE_ChannelThresSet(CAPLESENSE_SLIDER3_PIN, CAPLESENSE_ACMP_VDD_SCALE, capsenseCalibrateVals[3]);
}
}
/**************************************************************************//**
* @brief LESENSE callback setup
* @param scanCb Scan callback
* @param chCb Channel callback
*****************************************************************************/
void CAPLESENSE_setupCallbacks(void (*scanCb)(void), void (*chCb)(void))
{
lesenseScanCb = scanCb;
lesenseChCb = chCb;
}
/**************************************************************************//**
* @brief LESENSE interrupt handler
*****************************************************************************/
void LESENSE_IRQHandler(void)
{
uint32_t count;
/* LESENSE scan complete interrupt. */
if (LESENSE_IF_SCANCOMPLETE & LESENSE_IntGetEnabled())
{
LESENSE_IntClear(LESENSE_IF_SCANCOMPLETE);
/* Iterate trough all channels */
for (currentChannel = 0; currentChannel < LESENSE_CHANNELS; currentChannel++)
{
/* If this channel is not in use, skip to the next one */
if (!channelsInUse[currentChannel])
{
continue;
}
/* Read out value from LESENSE buffer */
count = LESENSE_ScanResultDataGet();
/* Store value in channelValues */
channelValues[currentChannel] = count;
/* Update channelMaxValues */
if (count > channelMaxValues[currentChannel])
{
channelMaxValues[currentChannel] = count;
}
}
/* Call callback function. */
if (lesenseScanCb != 0x00000000)
{
lesenseScanCb();
}
}
/* LESENSE channel interrupt. */
if (CAPLESENSE_CHANNEL_INT & LESENSE_IntGetEnabled())
{
/* Clear flags. */
LESENSE_IntClear(CAPLESENSE_CHANNEL_INT);
/* Call callback function. */
if (lesenseChCb != 0x00000000)
{
lesenseChCb();
}
}
}
/**************************************************************************//**
* @brief Get the channelValue for a sensor segment
* @param capSegment
* @return channel
*****************************************************************************/
uint8_t CAPLESENSE_getSegmentChannel(uint8_t capSegment)
{
uint8_t channel;
switch (capSegment)
{
case(0):
channel = SLIDER_PART0_CHANNEL;
break;
case(1):
channel = SLIDER_PART1_CHANNEL;
break;
case(2):
channel = SLIDER_PART2_CHANNEL;
break;
default:
channel = SLIDER_PART3_CHANNEL;
break;
}
return channel;
}
/**************************************************************************//**
* @brief Get the current channelValue for a channel
* @param channel The channel.
* @return The channelValue.
*****************************************************************************/
uint32_t CAPLESENSE_getVal(uint8_t channel)
{
return channelValues[channel];
}
/**************************************************************************//**
* @brief Get the current normalized channelValue for a channel
* @param channel The channel.
* @return The channel value in range (0-256).
*****************************************************************************/
uint32_t CAPLESENSE_getNormalizedVal(uint8_t channel)
{
uint32_t max = channelMaxValues[channel];
return (channelValues[channel] << 8) / max;
}
/**************************************************************************//**
* @brief Get the position of the slider
* @return The position of the slider if it can be determined,
* -1 otherwise.
*****************************************************************************/
int32_t CAPLESENSE_getSliderPosition(void)
{
int i;
int minPos = -1;
uint32_t minVal = 236; /* adjust it */
/* Values used for interpolation. There is two more which represents the edges.
* This makes the interpolation code a bit cleaner as we do not have to make special
* cases for handling them */
uint32_t interpol[6] = { 255, 255, 255, 255, 255, 255 };
uint32_t channelPattern[] = { 0, SLIDER_PART0_CHANNEL + 1,
SLIDER_PART1_CHANNEL + 1,
SLIDER_PART2_CHANNEL + 1,
SLIDER_PART3_CHANNEL + 1 };
/* The calculated slider position. */
int position;
/* Iterate through the 4 slider bars and calculate the current value divided by
* the maximum value multiplied by 256.
* Note that there is an offset of 1 between channelValues and interpol.
* This is done to make interpolation easier.
*/
for (i = 1; i < CAPLESENSE_NUMOF_SLIDERS + 1; i++)
{
/* interpol[i] will be in the range 0-256 depending on channelMax */
interpol[i] = channelValues[channelPattern[i] - 1] << 8;
interpol[i] /= channelMaxValues[channelPattern[i] - 1];
/* Find the minimum value and position */
if (interpol[i] < minVal)
{
minVal = interpol[i];
minPos = i;
}
}
/* Check if the slider has not been touched */
if (minPos == -1)
return -1;
/* Start position. Shift by 4 to get additional resolution. */
/* Because of the interpol trick earlier we have to substract one to offset that effect */
position = (minPos - 1) << 4;
/* Interpolate with pad to the left */
position -= ((256 - interpol[minPos - 1]) << 3)
/ (256 - interpol[minPos]);
/* Interpolate with pad to the right */
position += ((256 - interpol[minPos + 1]) << 3)
/ (256 - interpol[minPos]);
return position;
}
/**************************************************************************//**
* @brief Send the capacative sense system to sleep mode.
*****************************************************************************/
void CAPLESENSE_Sleep(void)
{
/* Go to EM2 and wait for the measurement to complete. */
EMU_EnterEM2(true);
}
/**************************************************************************//**
* @brief Initializes the capacative sense system without LESENSE.
* @param sleep If true, go into sleep mode.
*****************************************************************************/
void CAPLESENSE_Init(bool sleep)
{
/* Disable interrupts */
INT_Disable();
/* Setup CMU. */
CAPLESENSE_setupCMU();
/* Setup GPIO. */
CAPLESENSE_setupGPIO();
/* Setup ACMP. */
CAPLESENSE_setupACMP();
/* Setup LESENSE. */
CAPLESENSE_setupLESENSE(sleep);
/* Initialization done, enable interrupts globally. */
INT_Enable();
}
| 32.876364 | 105 | 0.561774 |
b0ecacdea243e900664899298fd1c548db312a54 | 357 | h | C | Happy/server/gate/include/module/server/Message.h | zivhoo/children | 5e6bcc1ec9e2fa9c4f6d84564d566b36b65a80ec | [
"Apache-2.0"
] | null | null | null | Happy/server/gate/include/module/server/Message.h | zivhoo/children | 5e6bcc1ec9e2fa9c4f6d84564d566b36b65a80ec | [
"Apache-2.0"
] | null | null | null | Happy/server/gate/include/module/server/Message.h | zivhoo/children | 5e6bcc1ec9e2fa9c4f6d84564d566b36b65a80ec | [
"Apache-2.0"
] | null | null | null | //
// Created by Ziv on 2018/4/21.
//
#ifndef GATESERVER_MESSAGE_H
#define GATESERVER_MESSAGE_H
#include <string>
namespace uvw{
class TcpHandle;
}
class Message {
public:
Message(uvw::TcpHandle& handle,std::string msg);
virtual ~Message();
protected:
std::string _msg;
uvw::TcpHandle& _client;
};
#endif //GATESERVER_MESSAGE_H
| 12.75 | 52 | 0.691877 |
8e641463d0bb8b6738d778b080323c42fb335440 | 524 | h | C | NewsApp/NewsApp/DAT/BaseDAT.h | FMYang/NewsApp | 55bfe4e3824cfd09b22162231bbe2f9769ee39d3 | [
"MIT"
] | 1 | 2017-07-05T10:10:05.000Z | 2017-07-05T10:10:05.000Z | NewsApp/NewsApp/DAT/BaseDAT.h | FMYang/NewsApp | 55bfe4e3824cfd09b22162231bbe2f9769ee39d3 | [
"MIT"
] | null | null | null | NewsApp/NewsApp/DAT/BaseDAT.h | FMYang/NewsApp | 55bfe4e3824cfd09b22162231bbe2f9769ee39d3 | [
"MIT"
] | null | null | null | //
// BaseDAT.h
// Urundc_IOS
//
// Created by 杨方明 on 15/1/7.
// Copyright (c) 2015年 urun. All rights reserved.
//
#import <Foundation/Foundation.h>
#import "FMDB.h"
#import "DBConfig.h"
@interface BaseDAT : NSObject
@property (nonatomic, strong) FMDatabase *urunDB;
@property (nonatomic, strong) FMDatabaseQueue *dbQueue;
+ (instancetype)sharedBaseDAT;
/*创建数据库*/
- (void)createDataBase;
/*获取数据库本地路径*/
+ (NSString *)GetDataBasePath;
/*打开数据库*/
- (FMDatabase *)openDataBase;
/*关闭数据库*/
- (void)closeDataBase;
@end
| 15.878788 | 55 | 0.696565 |
fc1c74a944d1be247a28340f812ef09203d7e3d8 | 765 | h | C | src/Providers/UNIXProviders/ComputerSystemDMA/UNIX_ComputerSystemDMADeps.h | brunolauze/openpegasus-providers-old | b00f1aad575bae144b8538bf57ba5fd5582a4ec7 | [
"MIT"
] | 1 | 2020-10-12T09:00:09.000Z | 2020-10-12T09:00:09.000Z | src/Providers/UNIXProviders/ComputerSystemDMA/UNIX_ComputerSystemDMADeps.h | brunolauze/openpegasus-providers-old | b00f1aad575bae144b8538bf57ba5fd5582a4ec7 | [
"MIT"
] | null | null | null | src/Providers/UNIXProviders/ComputerSystemDMA/UNIX_ComputerSystemDMADeps.h | brunolauze/openpegasus-providers-old | b00f1aad575bae144b8538bf57ba5fd5582a4ec7 | [
"MIT"
] | null | null | null |
#if defined(PEGASUS_OS_HPUX)
# include "UNIX_ComputerSystemDMADeps_HPUX.h"
#elif defined(PEGASUS_OS_LINUX)
# include "UNIX_ComputerSystemDMADeps_LINUX.h"
#elif defined(PEGASUS_OS_DARWIN)
# include "UNIX_ComputerSystemDMADeps_DARWIN.h"
#elif defined(PEGASUS_OS_AIX)
# include "UNIX_ComputerSystemDMADeps_AIX.h"
#elif defined(PEGASUS_OS_FREEBSD)
# include "UNIX_ComputerSystemDMADeps_FREEBSD.h"
#elif defined(PEGASUS_OS_SOLARIS)
# include "UNIX_ComputerSystemDMADeps_SOLARIS.h"
#elif defined(PEGASUS_OS_ZOS)
# include "UNIX_ComputerSystemDMADeps_ZOS.h"
#elif defined(PEGASUS_OS_VMS)
# include "UNIX_ComputerSystemDMADeps_VMS.h"
#elif defined(PEGASUS_OS_TRU64)
# include "UNIX_ComputerSystemDMADeps_TRU64.h"
#else
# include "UNIX_ComputerSystemDMADeps_STUB.h"
#endif
| 33.26087 | 48 | 0.843137 |
5acb5e0ea540b854e55342233116e6b4f9b6df66 | 90 | h | C | ios/Classes/SecondsplashPlugin.h | fuadarradhi/secondsplash | 04f8642d78ea12a63683a828ed78898f5e64728a | [
"MIT"
] | null | null | null | ios/Classes/SecondsplashPlugin.h | fuadarradhi/secondsplash | 04f8642d78ea12a63683a828ed78898f5e64728a | [
"MIT"
] | null | null | null | ios/Classes/SecondsplashPlugin.h | fuadarradhi/secondsplash | 04f8642d78ea12a63683a828ed78898f5e64728a | [
"MIT"
] | null | null | null | #import <Flutter/Flutter.h>
@interface SecondsplashPlugin : NSObject<FlutterPlugin>
@end
| 18 | 55 | 0.8 |
5415b28384966ab1d6940d31c4457394167de7c1 | 2,475 | h | C | src/alock.h | mrozekma/alock | 09d2ad2cf560e77a7d022c5cb8b68ede4275983c | [
"MIT"
] | null | null | null | src/alock.h | mrozekma/alock | 09d2ad2cf560e77a7d022c5cb8b68ede4275983c | [
"MIT"
] | null | null | null | src/alock.h | mrozekma/alock | 09d2ad2cf560e77a7d022c5cb8b68ede4275983c | [
"MIT"
] | null | null | null |
#ifndef _ALOCK_H_
#define _ALOCK_H_
/* ---------------------------------------------------------------- *\
file : alock.h
author : m. gumz <akira at fluxbox dot org>
copyr : copyright (c) 2005 - 2007 by m. gumz
license : see LICENSE
start : Sa 30 Apr 2005 11:51:52 CEST
\* ---------------------------------------------------------------- */
/* ---------------------------------------------------------------- *\
about :
\* ---------------------------------------------------------------- */
#include <X11/Xlib.h>
#include <stdio.h>
/* ---------------------------------------------------------------- *\
\* ---------------------------------------------------------------- */
#ifdef DEBUG
# define DBGMSG fprintf(stderr, "%s : %d\n", __FUNCTION__, __LINE__); fflush(stderr)
#else
# define DBGMSG
#endif /* DEBUG */
/*------------------------------------------------------------------*\
\*------------------------------------------------------------------*/
struct aXInfo {
Display* display;
Atom pid_atom;
int nr_screens;
int* width_of_root;
int* height_of_root;
Window* root;
Colormap* colormap;
Window* window;
Cursor* cursor;
};
struct aAuth {
const char* name;
int (*init)(const char* args);
int (*auth)(const char* pass);
int (*deinit)();
};
struct aCursor {
const char* name;
int (*init)(const char* args, struct aXInfo* xinfo);
int (*deinit)(struct aXInfo* xinfo);
};
struct aBackground {
const char* name;
int (*init)(const char* args, struct aXInfo* xinfo);
int (*deinit)(struct aXInfo* xinfo);
};
struct aOpts {
struct aAuth* auth;
struct aCursor* cursor;
struct aBackground* background;
};
/*------------------------------------------------------------------*\
\*------------------------------------------------------------------*/
void alock_string2lower(char* string);
int alock_native_byte_order(void);
int alock_alloc_color(const struct aXInfo* xinfo, int scr,
const char* color_name,
const char* fallback_name,
XColor* result);
int alock_check_xrender(const struct aXInfo* xinfo);
int alock_shade_pixmap(const struct aXInfo* xinfo,
int scr,
const Pixmap src_pm,
Pixmap dst_pm,
unsigned char shade,
int src_x, int src_y,
int dst_x, int dst_y,
unsigned int width,
unsigned int height);
#endif /* _ALOCK_H_ */
| 25 | 87 | 0.450505 |
542d698bf40025efa2f519293dca87c5cd59963f | 6,568 | h | C | Labyrint/Temp/il2cppOutput/il2cppOutput/mscorlib_System_Runtime_Remoting_Messaging_MethodCa524563129MethodDeclarations.h | mimietti/Labyball | c4b03f5b5d5ec1a1cae5831d22391bc2a171230f | [
"MIT"
] | null | null | null | Labyrint/Temp/il2cppOutput/il2cppOutput/mscorlib_System_Runtime_Remoting_Messaging_MethodCa524563129MethodDeclarations.h | mimietti/Labyball | c4b03f5b5d5ec1a1cae5831d22391bc2a171230f | [
"MIT"
] | 23 | 2016-07-21T13:03:02.000Z | 2016-10-03T12:43:01.000Z | Labyrint/labyrinti1/Classes/Native/mscorlib_System_Runtime_Remoting_Messaging_MethodCa524563129MethodDeclarations.h | mimietti/Labyball | c4b03f5b5d5ec1a1cae5831d22391bc2a171230f | [
"MIT"
] | 1 | 2019-09-08T17:32:17.000Z | 2019-09-08T17:32:17.000Z | #pragma once
#include "il2cpp-config.h"
#ifndef _MSC_VER
# include <alloca.h>
#else
# include <malloc.h>
#endif
#include <stdint.h>
#include <assert.h>
#include <exception>
// System.Runtime.Remoting.Messaging.MethodCall
struct MethodCall_t524563129;
// System.Runtime.Remoting.Messaging.Header[]
struct HeaderU5BU5D_t3833532446;
// System.Runtime.Serialization.SerializationInfo
struct SerializationInfo_t2995724695;
// System.String
struct String_t;
// System.Object
struct Il2CppObject;
// System.Object[]
struct ObjectU5BU5D_t11523773;
// System.Runtime.Remoting.Messaging.LogicalCallContext
struct LogicalCallContext_t1074763138;
// System.Reflection.MethodBase
struct MethodBase_t3461000640;
// System.Collections.IDictionary
struct IDictionary_t1654916945;
// System.Type
struct Type_t;
// System.Type[]
struct TypeU5BU5D_t3431720054;
#include "codegen/il2cpp-codegen.h"
#include "mscorlib_System_Runtime_Serialization_Serializatio2995724695.h"
#include "mscorlib_System_Runtime_Serialization_StreamingCont986364934.h"
#include "mscorlib_System_String968488902.h"
#include "mscorlib_System_Object837106420.h"
#include "mscorlib_System_Type2779229935.h"
// System.Void System.Runtime.Remoting.Messaging.MethodCall::.ctor(System.Runtime.Remoting.Messaging.Header[])
extern "C" void MethodCall__ctor_m2280547300 (MethodCall_t524563129 * __this, HeaderU5BU5D_t3833532446* ___h10, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Void System.Runtime.Remoting.Messaging.MethodCall::.ctor(System.Runtime.Serialization.SerializationInfo,System.Runtime.Serialization.StreamingContext)
extern "C" void MethodCall__ctor_m3232041652 (MethodCall_t524563129 * __this, SerializationInfo_t2995724695 * ___info0, StreamingContext_t986364934 ___context1, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Void System.Runtime.Remoting.Messaging.MethodCall::.ctor()
extern "C" void MethodCall__ctor_m4232248307 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Void System.Runtime.Remoting.Messaging.MethodCall::System.Runtime.Remoting.Messaging.IInternalMessage.set_Uri(System.String)
extern "C" void MethodCall_System_Runtime_Remoting_Messaging_IInternalMessage_set_Uri_m75118319 (MethodCall_t524563129 * __this, String_t* ___value0, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Void System.Runtime.Remoting.Messaging.MethodCall::InitMethodProperty(System.String,System.Object)
extern "C" void MethodCall_InitMethodProperty_m2379029369 (MethodCall_t524563129 * __this, String_t* ___key0, Il2CppObject * ___value1, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Void System.Runtime.Remoting.Messaging.MethodCall::GetObjectData(System.Runtime.Serialization.SerializationInfo,System.Runtime.Serialization.StreamingContext)
extern "C" void MethodCall_GetObjectData_m3092930065 (MethodCall_t524563129 * __this, SerializationInfo_t2995724695 * ___info0, StreamingContext_t986364934 ___context1, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Object[] System.Runtime.Remoting.Messaging.MethodCall::get_Args()
extern "C" ObjectU5BU5D_t11523773* MethodCall_get_Args_m2777349738 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Runtime.Remoting.Messaging.LogicalCallContext System.Runtime.Remoting.Messaging.MethodCall::get_LogicalCallContext()
extern "C" LogicalCallContext_t1074763138 * MethodCall_get_LogicalCallContext_m3758703237 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Reflection.MethodBase System.Runtime.Remoting.Messaging.MethodCall::get_MethodBase()
extern "C" MethodBase_t3461000640 * MethodCall_get_MethodBase_m1563575745 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.String System.Runtime.Remoting.Messaging.MethodCall::get_MethodName()
extern "C" String_t* MethodCall_get_MethodName_m703141353 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Object System.Runtime.Remoting.Messaging.MethodCall::get_MethodSignature()
extern "C" Il2CppObject * MethodCall_get_MethodSignature_m3505289450 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Collections.IDictionary System.Runtime.Remoting.Messaging.MethodCall::get_Properties()
extern "C" Il2CppObject * MethodCall_get_Properties_m3494690993 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Void System.Runtime.Remoting.Messaging.MethodCall::InitDictionary()
extern "C" void MethodCall_InitDictionary_m1823571767 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.String System.Runtime.Remoting.Messaging.MethodCall::get_TypeName()
extern "C" String_t* MethodCall_get_TypeName_m2818536578 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.String System.Runtime.Remoting.Messaging.MethodCall::get_Uri()
extern "C" String_t* MethodCall_get_Uri_m110584337 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Void System.Runtime.Remoting.Messaging.MethodCall::set_Uri(System.String)
extern "C" void MethodCall_set_Uri_m3629049250 (MethodCall_t524563129 * __this, String_t* ___value0, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Void System.Runtime.Remoting.Messaging.MethodCall::Init()
extern "C" void MethodCall_Init_m1334986753 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Void System.Runtime.Remoting.Messaging.MethodCall::ResolveMethod()
extern "C" void MethodCall_ResolveMethod_m2191435710 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Type System.Runtime.Remoting.Messaging.MethodCall::CastTo(System.String,System.Type)
extern "C" Type_t * MethodCall_CastTo_m2140135600 (MethodCall_t524563129 * __this, String_t* ___clientType0, Type_t * ___serverType1, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.String System.Runtime.Remoting.Messaging.MethodCall::GetTypeNameFromAssemblyQualifiedName(System.String)
extern "C" String_t* MethodCall_GetTypeNameFromAssemblyQualifiedName_m148372306 (Il2CppObject * __this /* static, unused */, String_t* ___aqname0, const MethodInfo* method) IL2CPP_METHOD_ATTR;
// System.Type[] System.Runtime.Remoting.Messaging.MethodCall::get_GenericArguments()
extern "C" TypeU5BU5D_t3431720054* MethodCall_get_GenericArguments_m3093552433 (MethodCall_t524563129 * __this, const MethodInfo* method) IL2CPP_METHOD_ATTR;
| 75.494253 | 216 | 0.842113 |
2de4b730a3247e28b8c174cc041dcd951c5cfec3 | 1,004 | c | C | myMore.c | ismetkizgin/C-Language-File-Read-Pipeline | dcd35c049be8390257bb7a30bb06831dd180ece5 | [
"MIT"
] | 4 | 2020-07-20T11:08:45.000Z | 2021-02-07T17:18:00.000Z | myMore.c | ismetkizgin/C-Language-File-Read-Pipeline | dcd35c049be8390257bb7a30bb06831dd180ece5 | [
"MIT"
] | null | null | null | myMore.c | ismetkizgin/C-Language-File-Read-Pipeline | dcd35c049be8390257bb7a30bb06831dd180ece5 | [
"MIT"
] | 3 | 2020-06-03T17:59:25.000Z | 2020-06-16T21:38:48.000Z | #include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <string.h>
#define BufferSize 500
#define MaxLineSize 250
#define PrintLineCount 24
int main(int argc, char *argv[])
{
char pidIndex[10];
int pidValue = getpid();
sprintf(pidIndex, "%d", pidValue);
char ppidIndex[10];
int ppidValue = getppid();
sprintf(ppidIndex, "%d", ppidValue);
char *pidIndexParent = argv[2]; // Parent üzerinden parametre olarak gönderilen pid id'ler alınır.
char *ppidIndexParent = argv[3]; // Process çalışan process id alınır.
if (strcmp(pidIndex, pidIndexParent) != 0 && strcmp(ppidIndex, ppidIndexParent) != 0) // Parent ve child process id'ler kontrol edilir.
{
printf("myMore dosyasi parenti olmadan calisamaz...\n");
}
else
{
int readEnd = atoi(argv[1]);
char readMessage[MaxLineSize][BufferSize];
read(readEnd, &readMessage, PrintLineCount * BufferSize);
for (int i = 0; i < PrintLineCount; ++i)
{
printf("%s", readMessage[i]);
}
close(readEnd);
return 0;
}
}
| 23.348837 | 137 | 0.690239 |
0cb6fb8db4c396bbd6879c7439106eedfb308759 | 17,687 | c | C | Tests/9/kwonlyargs.c | jwilk/Pyrex | 83dfbae1261788933472e3f9c501ad74c61a37c5 | [
"Apache-2.0"
] | 5 | 2019-05-26T20:48:36.000Z | 2021-07-09T01:38:38.000Z | Tests/9/kwonlyargs.c | jwilk/Pyrex | 83dfbae1261788933472e3f9c501ad74c61a37c5 | [
"Apache-2.0"
] | null | null | null | Tests/9/kwonlyargs.c | jwilk/Pyrex | 83dfbae1261788933472e3f9c501ad74c61a37c5 | [
"Apache-2.0"
] | 1 | 2022-02-10T07:14:58.000Z | 2022-02-10T07:14:58.000Z | /* Generated by Pyrex */
#define PY_SSIZE_T_CLEAN
#include "Python.h"
#include "structmember.h"
#ifndef PY_LONG_LONG
#define PY_LONG_LONG LONG_LONG
#endif
#if PY_VERSION_HEX < 0x02050000
typedef int Py_ssize_t;
#define PY_SSIZE_T_MAX INT_MAX
#define PY_SSIZE_T_MIN INT_MIN
#define PyInt_FromSsize_t(z) PyInt_FromLong(z)
#define PyInt_AsSsize_t(o) PyInt_AsLong(o)
#endif
#if !defined(WIN32) && !defined(MS_WINDOWS)
#ifndef __stdcall
#define __stdcall
#endif
#ifndef __cdecl
#define __cdecl
#endif
#endif
#ifdef __cplusplus
#define __PYX_EXTERN_C extern "C"
#else
#define __PYX_EXTERN_C extern
#endif
#include <math.h>
typedef struct {PyObject **p; int i; char *s; long n;} __Pyx_StringTabEntry; /*proto*/
static PyObject *__pyx_m;
static PyObject *__pyx_b;
static int __pyx_lineno;
static char *__pyx_filename;
static char **__pyx_f;
static int __Pyx_GetStarArgs(PyObject **args, PyObject **kwds, char *kwd_list[], Py_ssize_t nargs, PyObject **args2, PyObject **kwds2, char rqd_kwds[]); /*proto*/
static int __Pyx_InitStrings(__Pyx_StringTabEntry *t); /*proto*/
static void __Pyx_AddTraceback(char *funcname); /*proto*/
/* Declarations from kwonlyargs */
/* Declarations from implementation of kwonlyargs */
static __Pyx_StringTabEntry __pyx_string_tab[] = {
{0, 0, 0, 0}
};
static PyObject *__pyx_d1;
static PyObject *__pyx_d2;
static PyObject *__pyx_d3;
static PyObject *__pyx_d4;
static PyObject *__pyx_d5;
static PyObject *__pyx_d6;
static PyObject *__pyx_d7;
/* Implementation of kwonlyargs */
static PyObject *__pyx_f_10kwonlyargs_c(PyObject *__pyx_self, PyObject *__pyx_args, PyObject *__pyx_kwds); /*proto*/
static PyObject *__pyx_f_10kwonlyargs_c(PyObject *__pyx_self, PyObject *__pyx_args, PyObject *__pyx_kwds) {
PyObject *__pyx_v_a = 0;
PyObject *__pyx_v_b = 0;
PyObject *__pyx_v_c = 0;
PyObject *__pyx_v_z;
PyObject *__pyx_r;
PyObject *__pyx_1 = 0;
static char *__pyx_argnames[] = {"a","b","c",0};
if (!PyArg_ParseTupleAndKeywords(__pyx_args, __pyx_kwds, "OOO", __pyx_argnames, &__pyx_v_a, &__pyx_v_b, &__pyx_v_c)) return 0;
Py_INCREF(__pyx_v_a);
Py_INCREF(__pyx_v_b);
Py_INCREF(__pyx_v_c);
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PyObject *__pyx_v_b = 0;
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PyObject *__pyx_v_z;
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Py_DECREF(__pyx_v_z);
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Py_XDECREF(__pyx_args);
Py_XDECREF(__pyx_kwds);
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static PyObject *__pyx_f_10kwonlyargs_h(PyObject *__pyx_self, PyObject *__pyx_args, PyObject *__pyx_kwds) {
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PyObject *__pyx_v_b = 0;
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PyObject *__pyx_v_args = 0;
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PyObject *__pyx_v_z;
PyObject *__pyx_r;
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static char *__pyx_argnames[] = {"a","b","c","d","e","f",0};
static char __pyx_reqd_kwds[] = {0,0,1,0,0,1};
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if (__Pyx_GetStarArgs(&__pyx_args, &__pyx_kwds, __pyx_argnames, 2, &__pyx_v_args, &__pyx_v_kwds, __pyx_reqd_kwds) < 0) return 0;
if (!PyArg_ParseTupleAndKeywords(__pyx_args, __pyx_kwds, "OOO|OOO", __pyx_argnames, &__pyx_v_a, &__pyx_v_b, &__pyx_v_c, &__pyx_v_d, &__pyx_v_e, &__pyx_v_f)) {
Py_XDECREF(__pyx_args);
Py_XDECREF(__pyx_kwds);
Py_XDECREF(__pyx_v_args);
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Py_DECREF(__pyx_v_z);
__pyx_v_z = __pyx_1;
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goto __pyx_L0;
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Py_XDECREF(__pyx_1);
__Pyx_AddTraceback("kwonlyargs.h");
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Py_XDECREF(__pyx_v_args);
Py_XDECREF(__pyx_v_kwds);
Py_DECREF(__pyx_v_z);
Py_DECREF(__pyx_v_a);
Py_DECREF(__pyx_v_b);
Py_DECREF(__pyx_v_c);
Py_DECREF(__pyx_v_d);
Py_DECREF(__pyx_v_e);
Py_DECREF(__pyx_v_f);
Py_XDECREF(__pyx_args);
Py_XDECREF(__pyx_kwds);
return __pyx_r;
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static struct PyMethodDef __pyx_methods[] = {
{"c", (PyCFunction)__pyx_f_10kwonlyargs_c, METH_VARARGS|METH_KEYWORDS, 0},
{"d", (PyCFunction)__pyx_f_10kwonlyargs_d, METH_VARARGS|METH_KEYWORDS, 0},
{"e", (PyCFunction)__pyx_f_10kwonlyargs_e, METH_VARARGS|METH_KEYWORDS, 0},
{"f", (PyCFunction)__pyx_f_10kwonlyargs_f, METH_VARARGS|METH_KEYWORDS, 0},
{"g", (PyCFunction)__pyx_f_10kwonlyargs_g, METH_VARARGS|METH_KEYWORDS, 0},
{"h", (PyCFunction)__pyx_f_10kwonlyargs_h, METH_VARARGS|METH_KEYWORDS, 0},
{0, 0, 0, 0}
};
static void __pyx_init_filenames(void); /*proto*/
PyMODINIT_FUNC initkwonlyargs(void); /*proto*/
PyMODINIT_FUNC initkwonlyargs(void) {
PyObject *__pyx_1 = 0;
PyObject *__pyx_2 = 0;
PyObject *__pyx_3 = 0;
PyObject *__pyx_4 = 0;
PyObject *__pyx_5 = 0;
PyObject *__pyx_6 = 0;
PyObject *__pyx_7 = 0;
__pyx_init_filenames();
__pyx_m = Py_InitModule4("kwonlyargs", __pyx_methods, 0, 0, PYTHON_API_VERSION);
if (!__pyx_m) {__pyx_filename = __pyx_f[0]; __pyx_lineno = 1; goto __pyx_L1;};
Py_INCREF(__pyx_m);
__pyx_b = PyImport_AddModule("__builtin__");
if (!__pyx_b) {__pyx_filename = __pyx_f[0]; __pyx_lineno = 1; goto __pyx_L1;};
if (PyObject_SetAttrString(__pyx_m, "__builtins__", __pyx_b) < 0) {__pyx_filename = __pyx_f[0]; __pyx_lineno = 1; goto __pyx_L1;};
if (__Pyx_InitStrings(__pyx_string_tab) < 0) {__pyx_filename = __pyx_f[0]; __pyx_lineno = 1; goto __pyx_L1;};
/* "/Local/Projects/D/Pyrex/Source/Tests/9/kwonlyargs.pyx":4 */
__pyx_1 = PyInt_FromLong(88); if (!__pyx_1) {__pyx_filename = __pyx_f[0]; __pyx_lineno = 4; goto __pyx_L1;}
__pyx_d1 = __pyx_1;
__pyx_1 = 0;
/* "/Local/Projects/D/Pyrex/Source/Tests/9/kwonlyargs.pyx":7 */
__pyx_2 = PyInt_FromLong(88); if (!__pyx_2) {__pyx_filename = __pyx_f[0]; __pyx_lineno = 7; goto __pyx_L1;}
__pyx_d2 = __pyx_2;
__pyx_2 = 0;
/* "/Local/Projects/D/Pyrex/Source/Tests/9/kwonlyargs.pyx":10 */
__pyx_3 = PyInt_FromLong(42); if (!__pyx_3) {__pyx_filename = __pyx_f[0]; __pyx_lineno = 10; goto __pyx_L1;}
__pyx_d3 = __pyx_3;
__pyx_3 = 0;
/* "/Local/Projects/D/Pyrex/Source/Tests/9/kwonlyargs.pyx":13 */
__pyx_4 = PyInt_FromLong(42); if (!__pyx_4) {__pyx_filename = __pyx_f[0]; __pyx_lineno = 13; goto __pyx_L1;}
__pyx_d4 = __pyx_4;
__pyx_4 = 0;
__pyx_5 = PyInt_FromLong(17); if (!__pyx_5) {__pyx_filename = __pyx_f[0]; __pyx_lineno = 13; goto __pyx_L1;}
__pyx_d5 = __pyx_5;
__pyx_5 = 0;
/* "/Local/Projects/D/Pyrex/Source/Tests/9/kwonlyargs.pyx":16 */
__pyx_6 = PyInt_FromLong(42); if (!__pyx_6) {__pyx_filename = __pyx_f[0]; __pyx_lineno = 16; goto __pyx_L1;}
__pyx_d6 = __pyx_6;
__pyx_6 = 0;
__pyx_7 = PyInt_FromLong(17); if (!__pyx_7) {__pyx_filename = __pyx_f[0]; __pyx_lineno = 16; goto __pyx_L1;}
__pyx_d7 = __pyx_7;
__pyx_7 = 0;
return;
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Py_XDECREF(__pyx_1);
Py_XDECREF(__pyx_2);
Py_XDECREF(__pyx_3);
Py_XDECREF(__pyx_4);
Py_XDECREF(__pyx_5);
Py_XDECREF(__pyx_6);
Py_XDECREF(__pyx_7);
__Pyx_AddTraceback("kwonlyargs");
}
static char *__pyx_filenames[] = {
"kwonlyargs.pyx",
};
/* Runtime support code */
static void __pyx_init_filenames(void) {
__pyx_f = __pyx_filenames;
}
static int __Pyx_GetStarArgs(
PyObject **args,
PyObject **kwds,
char *kwd_list[],
Py_ssize_t nargs,
PyObject **args2,
PyObject **kwds2,
char rqd_kwds[])
{
PyObject *x = 0, *args1 = 0, *kwds1 = 0;
int i;
char **p;
if (args2)
*args2 = 0;
if (kwds2)
*kwds2 = 0;
if (args2) {
args1 = PyTuple_GetSlice(*args, 0, nargs);
if (!args1)
goto bad;
*args2 = PyTuple_GetSlice(*args, nargs, PyTuple_GET_SIZE(*args));
if (!*args2)
goto bad;
}
else if (PyTuple_GET_SIZE(*args) > nargs) {
int m = nargs;
int n = PyTuple_GET_SIZE(*args);
PyErr_Format(PyExc_TypeError,
"function takes at most %d positional arguments (%d given)",
m, n);
goto bad;
}
else {
args1 = *args;
Py_INCREF(args1);
}
if (rqd_kwds && !*kwds)
for (i = 0, p = kwd_list; *p; i++, p++)
if (rqd_kwds[i])
goto missing_kwarg;
if (kwds2) {
if (*kwds) {
kwds1 = PyDict_New();
if (!kwds1)
goto bad;
*kwds2 = PyDict_Copy(*kwds);
if (!*kwds2)
goto bad;
for (i = 0, p = kwd_list; *p; i++, p++) {
x = PyDict_GetItemString(*kwds, *p);
if (x) {
if (PyDict_SetItemString(kwds1, *p, x) < 0)
goto bad;
if (PyDict_DelItemString(*kwds2, *p) < 0)
goto bad;
}
else if (rqd_kwds && rqd_kwds[i])
goto missing_kwarg;
}
}
else {
*kwds2 = PyDict_New();
if (!*kwds2)
goto bad;
}
}
else {
kwds1 = *kwds;
Py_XINCREF(kwds1);
if (rqd_kwds && *kwds)
for (i = 0, p = kwd_list; *p; i++, p++)
if (rqd_kwds[i] && !PyDict_GetItemString(*kwds, *p))
goto missing_kwarg;
}
*args = args1;
*kwds = kwds1;
return 0;
missing_kwarg:
PyErr_Format(PyExc_TypeError,
"required keyword argument '%s' is missing", *p);
bad:
Py_XDECREF(args1);
Py_XDECREF(kwds1);
if (args2) {
Py_XDECREF(*args2);
}
if (kwds2) {
Py_XDECREF(*kwds2);
}
return -1;
}
static int __Pyx_InitStrings(__Pyx_StringTabEntry *t) {
while (t->p) {
*t->p = PyString_FromStringAndSize(t->s, t->n - 1);
if (!*t->p)
return -1;
if (t->i)
PyString_InternInPlace(t->p);
++t;
}
return 0;
}
#include "compile.h"
#include "frameobject.h"
#include "traceback.h"
static void __Pyx_AddTraceback(char *funcname) {
PyObject *py_srcfile = 0;
PyObject *py_funcname = 0;
PyObject *py_globals = 0;
PyObject *empty_tuple = 0;
PyObject *empty_string = 0;
PyCodeObject *py_code = 0;
PyFrameObject *py_frame = 0;
py_srcfile = PyString_FromString(__pyx_filename);
if (!py_srcfile) goto bad;
py_funcname = PyString_FromString(funcname);
if (!py_funcname) goto bad;
py_globals = PyModule_GetDict(__pyx_m);
if (!py_globals) goto bad;
empty_tuple = PyTuple_New(0);
if (!empty_tuple) goto bad;
empty_string = PyString_FromString("");
if (!empty_string) goto bad;
py_code = PyCode_New(
0, /*int argcount,*/
0, /*int nlocals,*/
0, /*int stacksize,*/
0, /*int flags,*/
empty_string, /*PyObject *code,*/
empty_tuple, /*PyObject *consts,*/
empty_tuple, /*PyObject *names,*/
empty_tuple, /*PyObject *varnames,*/
empty_tuple, /*PyObject *freevars,*/
empty_tuple, /*PyObject *cellvars,*/
py_srcfile, /*PyObject *filename,*/
py_funcname, /*PyObject *name,*/
__pyx_lineno, /*int firstlineno,*/
empty_string /*PyObject *lnotab*/
);
if (!py_code) goto bad;
py_frame = PyFrame_New(
PyThreadState_Get(), /*PyThreadState *tstate,*/
py_code, /*PyCodeObject *code,*/
py_globals, /*PyObject *globals,*/
0 /*PyObject *locals*/
);
if (!py_frame) goto bad;
py_frame->f_lineno = __pyx_lineno;
PyTraceBack_Here(py_frame);
bad:
Py_XDECREF(py_srcfile);
Py_XDECREF(py_funcname);
Py_XDECREF(empty_tuple);
Py_XDECREF(empty_string);
Py_XDECREF(py_code);
Py_XDECREF(py_frame);
}
| 29.776094 | 163 | 0.703794 |
7ce0e4e8f70dd6ea7f5e62358936f9f9cc595dde | 695 | h | C | aws-cpp-sdk-chime/include/aws/chime/model/OriginationRouteProtocol.h | Neusoft-Technology-Solutions/aws-sdk-cpp | 88c041828b0dbee18a297c3cfe98c5ecd0706d0b | [
"Apache-2.0"
] | 1 | 2022-02-10T08:06:54.000Z | 2022-02-10T08:06:54.000Z | aws-cpp-sdk-chime/include/aws/chime/model/OriginationRouteProtocol.h | Neusoft-Technology-Solutions/aws-sdk-cpp | 88c041828b0dbee18a297c3cfe98c5ecd0706d0b | [
"Apache-2.0"
] | 1 | 2022-01-03T23:59:37.000Z | 2022-01-03T23:59:37.000Z | aws-cpp-sdk-chime/include/aws/chime/model/OriginationRouteProtocol.h | ravindra-wagh/aws-sdk-cpp | 7d5ff01b3c3b872f31ca98fb4ce868cd01e97696 | [
"Apache-2.0"
] | 1 | 2021-11-09T11:58:03.000Z | 2021-11-09T11:58:03.000Z | /**
* Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0.
*/
#pragma once
#include <aws/chime/Chime_EXPORTS.h>
#include <aws/core/utils/memory/stl/AWSString.h>
namespace Aws
{
namespace Chime
{
namespace Model
{
enum class OriginationRouteProtocol
{
NOT_SET,
TCP,
UDP
};
namespace OriginationRouteProtocolMapper
{
AWS_CHIME_API OriginationRouteProtocol GetOriginationRouteProtocolForName(const Aws::String& name);
AWS_CHIME_API Aws::String GetNameForOriginationRouteProtocol(OriginationRouteProtocol value);
} // namespace OriginationRouteProtocolMapper
} // namespace Model
} // namespace Chime
} // namespace Aws
| 21.71875 | 99 | 0.772662 |
4c636a0e8e001ec63ae63fbbcb5987b734f83246 | 585 | h | C | Ravine/RvTexture.h | gabriellanzer/Ravine | d0dc08eb7980d2023e305a019166d5d359687e46 | [
"MIT"
] | 8 | 2018-10-17T15:49:48.000Z | 2021-09-01T06:31:53.000Z | Ravine/RvTexture.h | gabriellanzer/Ravine | d0dc08eb7980d2023e305a019166d5d359687e46 | [
"MIT"
] | 15 | 2019-02-21T22:29:13.000Z | 2019-05-31T21:44:18.000Z | Ravine/RvTexture.h | gabriellanzer/Ravine | d0dc08eb7980d2023e305a019166d5d359687e46 | [
"MIT"
] | null | null | null | #ifndef RV_TEXTURE_H
#define RV_TEXTURE_H
//Vulkan Includes
#include "volk.h"
struct RvTexture
{
RvTexture() = default;
~RvTexture() = default;
//The texture size extent
VkExtent2D extent;
//Buffer size in bytes
size_t dataSize;
//Amount of mipLevels for this texture
uint32_t mipLevels;
//The GPU device that holds this image
VkDevice device;
//The VkImage handle
VkImage handle;
//The VkImageView handle
VkImageView view;
//The memory handle on a GPU device
VkDeviceMemory memory;
void free();
operator VkImage() const
{
return handle;
}
};
#endif | 13.928571 | 39 | 0.724786 |
718485acfd1304f31f4deab2c00d5b71973911e6 | 1,221 | h | C | arrows/matlab/matlab_detection_output.h | willdunklin/kwiver | 7642af7cc9c8727f85b322331164569665bae224 | [
"BSD-3-Clause"
] | null | null | null | arrows/matlab/matlab_detection_output.h | willdunklin/kwiver | 7642af7cc9c8727f85b322331164569665bae224 | [
"BSD-3-Clause"
] | null | null | null | arrows/matlab/matlab_detection_output.h | willdunklin/kwiver | 7642af7cc9c8727f85b322331164569665bae224 | [
"BSD-3-Clause"
] | null | null | null | // This file is part of KWIVER, and is distributed under the
// OSI-approved BSD 3-Clause License. See top-level LICENSE file or
// https://github.com/Kitware/kwiver/blob/master/LICENSE for details.
/// \file
/// \brief Header defining matlab image object set writer
#ifndef KWIVER_VITAL_BINDINGS_MATLAB_DETECTION_OUTPUT_H_
#define KWIVER_VITAL_BINDINGS_MATLAB_DETECTION_OUTPUT_H_
#include <vital/algo/detected_object_set_output.h>
#include <arrows/matlab/kwiver_algo_matlab_export.h>
namespace kwiver {
namespace arrows {
namespace matlab {
class KWIVER_ALGO_MATLAB_EXPORT matlab_detection_output
: public vital::algo::detected_object_set_output
{
public:
matlab_detection_output();
virtual ~matlab_detection_output();
PLUGIN_INFO( "matlab",
"Bridge to matlab detection output writer.")
virtual vital::config_block_sptr get_configuration() const;
virtual void set_configuration(vital::config_block_sptr config);
virtual bool check_configuration(vital::config_block_sptr config) const;
virtual void write_set( const kwiver::vital::detected_object_set_sptr set, std::string const& image_name );
private:
class priv;
std::unique_ptr< priv > d;
};
} } } // end namespace
#endif
| 29.071429 | 109 | 0.782146 |
bc97ba584261b859dcfd25ca5e163e24d84c697b | 3,237 | c | C | examples/micro_ros_kobuki_control.c | cndabai/micro_ros | 56676e56ceed07af4dedf1f92b8a4f4768691921 | [
"Apache-2.0"
] | 4 | 2021-07-29T03:01:04.000Z | 2021-12-21T09:12:39.000Z | examples/micro_ros_kobuki_control.c | cndabai/micro_ros | 56676e56ceed07af4dedf1f92b8a4f4768691921 | [
"Apache-2.0"
] | null | null | null | examples/micro_ros_kobuki_control.c | cndabai/micro_ros | 56676e56ceed07af4dedf1f92b8a4f4768691921 | [
"Apache-2.0"
] | 6 | 2021-06-14T15:55:19.000Z | 2021-11-19T01:18:10.000Z | /*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-06-12 hw630 the first version
*/
#include <micro_ros_rtt.h>
#include <kobuki.h>
#include <stdio.h>
#include <rcl/rcl.h>
#include <rcl/error_handling.h>
#include <rclc/rclc.h>
#include <rclc/executor.h>
#include <geometry_msgs/msg/twist.h>
rcl_subscription_t subscriber;
geometry_msgs__msg__Twist msg;
rclc_executor_t executor;
rcl_allocator_t allocator;
rclc_support_t support;
rcl_node_t node;
static struct kobuki robot;
static double linear_x = 0;
static double angular_z = 0;
static void kobuki_entry(void *parameter)
{
kobuki_init(&robot);
while(1)
{
rt_thread_mdelay(100);
kobuki_set_speed(linear_x, angular_z);
}
kobuki_close(&robot);
}
static void microros_kobuki_entry(void *parameter)
{
while(1)
{
rt_thread_mdelay(100);
rclc_executor_spin_some(&executor, RCL_MS_TO_NS(100));
}
}
//twist message cb
static void kobuki_callback(const void *msgin) {
// Please remember to enable -u_printf_float in compiler settings
const geometry_msgs__msg__Twist * msg = (const geometry_msgs__msg__Twist *)msgin;
printf("linear \n");
printf(" x: %f \n", msg->linear.x);
printf("angular \n");
printf(" z: %f \n", msg->angular.z);
linear_x = msg->linear.x;
angular_z = msg->angular.z;
}
void microros_kobuki_control(int argc, char* argv[])
{
#if defined MICRO_ROS_USE_SERIAL
// Serial setup
set_microros_transports();
#endif
#if defined MICRO_ROS_USE_UDP
// UDP setup
set_microros_udp_transports("192.168.199.100", 9999);
#endif
allocator = rcl_get_default_allocator();
// create init_options
if (rclc_support_init(&support, 0, NULL, &allocator) != RCL_RET_OK)
{
rt_kprintf("[micro_ros] failed to initialize\n");
return;
};
// create node
if (rclc_node_init_default(&node, "micro_ros_rtt_sub_twist", "", &support) != RCL_RET_OK)
{
rt_kprintf("[micro_ros] failed to create node\n");
return;
}
// create subscriber
rclc_subscription_init_default(
&subscriber,
&node,
ROSIDL_GET_MSG_TYPE_SUPPORT(geometry_msgs, msg, Twist),
"cmd_vel");
// create executor
rclc_executor_init(&executor, &support.context, 1, &allocator);
rclc_executor_add_subscription(&executor, &subscriber, &msg, &kobuki_callback, ON_NEW_DATA);
rt_thread_t thread = rt_thread_create("mr_kobuki", microros_kobuki_entry, RT_NULL, 2048, 15, 10);
if(thread != RT_NULL)
{
rt_thread_startup(thread);
rt_kprintf("[micro_ros] New thread mr_kobuki\n");
}
else
{
rt_kprintf("[micro_ros] Failed to create thread mr_kobuki\n");
}
rt_thread_t threadk = rt_thread_create("kobuki", kobuki_entry, RT_NULL, 2048, 10, 10);
if(threadk != RT_NULL)
{
rt_thread_startup(threadk);
rt_kprintf("[micro_ros] New thread kobuki\n");
}
else
{
rt_kprintf("[micro_ros] Failed to create thread kobuki\n");
}
}
MSH_CMD_EXPORT(microros_kobuki_control, micro ros control kobuki robot example)
| 25.488189 | 101 | 0.674699 |
9512dcc01ead63660f9c7a0eceb4137815d62115 | 69 | c | C | tests/errors/_questions/generated_errors/decl_after_strmt/decl_in_main_4.c | Ri7ay/RuC | 949487f4a336befb0e8b8760303c5c93ceabed83 | [
"Apache-2.0"
] | null | null | null | tests/errors/_questions/generated_errors/decl_after_strmt/decl_in_main_4.c | Ri7ay/RuC | 949487f4a336befb0e8b8760303c5c93ceabed83 | [
"Apache-2.0"
] | 1 | 2020-11-02T09:10:18.000Z | 2020-11-02T09:10:18.000Z | tests/errors/_questions/generated_errors/decl_after_strmt/decl_in_main_4.c | Ri7ay/RuC | 949487f4a336befb0e8b8760303c5c93ceabed83 | [
"Apache-2.0"
] | null | null | null | void main()
{
int А = 100;
printid(А);
int b = 10;
printid(b);
} | 8.625 | 13 | 0.536232 |
395c5a98aa29d685affd15abf3d83b6d75ec8051 | 668 | h | C | source/InputDisplay/hook.h | EPonyA/DisplayKeystroke | 3084736ce232a60216c39dc9f53f262da3456cd9 | [
"MIT"
] | 50 | 2017-01-21T11:45:11.000Z | 2022-02-09T22:17:02.000Z | source/InputDisplay/hook.h | EPonyA/DisplayKeystroke | 3084736ce232a60216c39dc9f53f262da3456cd9 | [
"MIT"
] | 2 | 2019-01-20T18:56:57.000Z | 2021-02-28T05:18:10.000Z | source/InputDisplay/hook.h | EPonyA/DisplayKeystroke | 3084736ce232a60216c39dc9f53f262da3456cd9 | [
"MIT"
] | 11 | 2017-12-04T17:26:27.000Z | 2021-12-08T09:03:18.000Z | #pragma once
#include <windows.h>
class Hook
{
public:
Hook();
~Hook();
typedef void(*ONKEY)(DWORD vkCode, bool toggle, void* pass_obj);
typedef void(*ONMOUSEMOVE)(POINT point, void* pass_obj);
void init(HINSTANCE hinstance, ONKEY onKeyFunc, ONMOUSEMOVE onMouseMoveFunc, void* pass_obj);
void start();
void stop();
static LRESULT CALLBACK LowLevelKeyboardProc(int nCode, WPARAM wParam, LPARAM lParam);
static LRESULT CALLBACK LowLevelMouseProc(int nCode, WPARAM wParam, LPARAM lParam);
protected:
HHOOK hh_keyboard;
HHOOK hh_mouse;
HINSTANCE hinst;
void* pass_object;
bool keymap[512];
ONKEY onKey;
ONMOUSEMOVE onMouseMove;
};
extern Hook hook; | 20.875 | 94 | 0.755988 |
e8388d6117c1ba9021791277a38342d7cf6c795e | 1,635 | h | C | System/Library/PrivateFrameworks/HelpKit.framework/HLPHelpSearchIndexController.h | lechium/iPhoneOS_12.1.1_Headers | aac688b174273dfcbade13bab104461f463db772 | [
"MIT"
] | 12 | 2019-06-02T02:42:41.000Z | 2021-04-13T07:22:20.000Z | System/Library/PrivateFrameworks/HelpKit.framework/HLPHelpSearchIndexController.h | lechium/iPhoneOS_12.1.1_Headers | aac688b174273dfcbade13bab104461f463db772 | [
"MIT"
] | null | null | null | System/Library/PrivateFrameworks/HelpKit.framework/HLPHelpSearchIndexController.h | lechium/iPhoneOS_12.1.1_Headers | aac688b174273dfcbade13bab104461f463db772 | [
"MIT"
] | 3 | 2019-06-11T02:46:10.000Z | 2019-12-21T14:58:16.000Z | /*
* This header is generated by classdump-dyld 1.0
* on Saturday, June 1, 2019 at 6:51:02 PM Mountain Standard Time
* Operating System: Version 12.1.1 (Build 16C5050a)
* Image Source: /System/Library/PrivateFrameworks/HelpKit.framework/HelpKit
* classdump-dyld is licensed under GPLv3, Copyright © 2013-2016 by Elias Limneos.
*/
#import <HelpKit/HLPRemoteDataController.h>
@class HLPHelpBookController, NSDictionary;
@interface HLPHelpSearchIndexController : HLPRemoteDataController {
HLPHelpBookController* _helpBookController;
NSDictionary* _searchIndex;
}
@property (nonatomic,retain) HLPHelpBookController * helpBookController; //@synthesize helpBookController=_helpBookController - In the implementation block
@property (nonatomic,retain) NSDictionary * searchIndex; //@synthesize searchIndex=_searchIndex - In the implementation block
-(NSDictionary *)searchIndex;
-(void)setSearchIndex:(NSDictionary *)arg1 ;
-(void)setHelpBookController:(HLPHelpBookController *)arg1 ;
-(void)fetchDataWithDataType:(long long)arg1 identifier:(id)arg2 completionHandler:(/*^block*/id)arg3 ;
-(id)resultsWithSearchText:(id)arg1 localeCode:(id)arg2 searchTerms:(id*)arg3 ;
-(HLPHelpBookController *)helpBookController;
-(void)processFileURLWithCompletionHandler:(/*^block*/id)arg1 ;
-(void)processData:(id)arg1 formattedData:(id)arg2 ;
-(id)searchTermsForSearchText:(id)arg1 localeCode:(id)arg2 ;
-(id)searchTree:(id)arg1 forQueryWord:(id)arg2 withMaxDepth:(int)arg3 ;
-(id)mergeDictionary:(id)arg1 withDictionary:(id)arg2 ;
-(id)getAllIdentifiersFromTree:(id)arg1 withMaxDepth:(int)arg2 ;
@end
| 45.416667 | 168 | 0.775535 |
b2057ee3b91428b9c5a33565cde08ba0e5ba8ba7 | 1,044 | h | C | src/visitor/interpreter.h | moray95/mbfc | e5a1c94d90b34aebb1147162934bc4aba847e545 | [
"MIT"
] | null | null | null | src/visitor/interpreter.h | moray95/mbfc | e5a1c94d90b34aebb1147162934bc4aba847e545 | [
"MIT"
] | null | null | null | src/visitor/interpreter.h | moray95/mbfc | e5a1c94d90b34aebb1147162934bc4aba847e545 | [
"MIT"
] | null | null | null | #pragma once
#include "visitor.h"
#include <mbfc-exception.h>
namespace visitor
{
class InterpreterException : public exception::MBFCException
{
public:
InterpreterException(const std::string& message) : MBFCException(message)
{
}
};
class Interpreter : public Visitor
{
public:
using super_type = Visitor;
using super_type::visit;
Interpreter();
virtual void visit(instruction::DecByteInstruction& instruction) override;
virtual void visit(instruction::DecPtrInstruction& instruction) override;
virtual void visit(instruction::InByteInstruction& instruction) override;
virtual void visit(instruction::IncByteInstruction& instruction) override;
virtual void visit(instruction::IncPtrInstruction& instruction) override;
virtual void visit(instruction::LoopInstruction& instruction) override;
virtual void visit(instruction::OutByteInstruction& instruction) override;
virtual ~Interpreter() = default;
private:
std::vector<char> data_;
size_t index_ = 0;
};
}
| 29 | 78 | 0.742337 |
ba8c86f5cd542995385f6fcc1d8c8b5952fac852 | 241 | h | C | FFScrollView/Class/ViewController/InfosHomeViewController.h | michaelMaoMao/FFScrollView | de7f52c3d7c1c14c0e5fc9e80f913c4cf5da3ac7 | [
"MIT"
] | 6 | 2017-11-17T03:55:43.000Z | 2018-06-13T17:04:38.000Z | FFScrollView/Class/ViewController/InfosHomeViewController.h | michaelMaoMao/FFScrollView | de7f52c3d7c1c14c0e5fc9e80f913c4cf5da3ac7 | [
"MIT"
] | null | null | null | FFScrollView/Class/ViewController/InfosHomeViewController.h | michaelMaoMao/FFScrollView | de7f52c3d7c1c14c0e5fc9e80f913c4cf5da3ac7 | [
"MIT"
] | 1 | 2019-03-05T05:54:51.000Z | 2019-03-05T05:54:51.000Z | //
// InfosHomeViewController.h
// FFScrollView
//
// Created by MichaelMao on 2017/11/11.
// Copyright © 2017年 GlobalScanner. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface InfosHomeViewController : UIViewController
@end
| 17.214286 | 57 | 0.73444 |
bafddc5f9e06f0c9033d8af47241eb62122b61ed | 3,669 | c | C | baseboard/intelrvp/ite_ec.c | coreboot/chrome-ec | 61044db105bc854167efe83815acb3fcb55deb85 | [
"BSD-3-Clause"
] | 46 | 2017-02-12T20:48:45.000Z | 2022-03-01T15:53:39.000Z | baseboard/intelrvp/ite_ec.c | coreboot/chrome-ec | 61044db105bc854167efe83815acb3fcb55deb85 | [
"BSD-3-Clause"
] | 1 | 2022-01-08T23:28:01.000Z | 2022-01-09T00:43:16.000Z | baseboard/intelrvp/ite_ec.c | coreboot/chrome-ec | 61044db105bc854167efe83815acb3fcb55deb85 | [
"BSD-3-Clause"
] | 46 | 2016-02-07T18:43:27.000Z | 2022-01-03T02:30:51.000Z | /* Copyright 2019 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Intel BASEBOARD-RVP ITE EC specific configuration */
#include "adc_chip.h"
#include "common.h"
#include "it83xx_pd.h"
#include "keyboard_scan.h"
#include "pwm.h"
#include "pwm_chip.h"
#include "timer.h"
#include "usb_pd_tcpm.h"
/* Keyboard scan setting */
__override struct keyboard_scan_config keyscan_config = {
.output_settle_us = 35,
.debounce_down_us = 5 * MSEC,
.debounce_up_us = 40 * MSEC,
.scan_period_us = 3 * MSEC,
.min_post_scan_delay_us = 1000,
.poll_timeout_us = 100 * MSEC,
.actual_key_mask = {
0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */
},
};
/* ADC channels */
const struct adc_t adc_channels[] = {
[ADC_TEMP_SNS_AMBIENT] = {
.name = "ADC_TEMP_SNS_AMBIENT",
.factor_mul = ADC_MAX_MVOLT,
.factor_div = ADC_READ_MAX + 1,
.shift = 0,
.channel = ADC_TEMP_SNS_AMBIENT_CHANNEL,
},
[ADC_TEMP_SNS_DDR] = {
.name = "ADC_TEMP_SNS_DDR",
.factor_mul = ADC_MAX_MVOLT,
.factor_div = ADC_READ_MAX + 1,
.shift = 0,
.channel = ADC_TEMP_SNS_DDR_CHANNEL,
},
[ADC_TEMP_SNS_SKIN] = {
.name = "ADC_TEMP_SNS_SKIN",
.factor_mul = ADC_MAX_MVOLT,
.factor_div = ADC_READ_MAX + 1,
.shift = 0,
.channel = ADC_TEMP_SNS_SKIN_CHANNEL,
},
[ADC_TEMP_SNS_VR] = {
.name = "ADC_TEMP_SNS_VR",
.factor_mul = ADC_MAX_MVOLT,
.factor_div = ADC_READ_MAX + 1,
.shift = 0,
.channel = ADC_TEMP_SNS_VR_CHANNEL,
},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/*
* PWM HW channelx binding tachometer channelx for fan control.
* Four tachometer input pins but two tachometer modules only,
* so always binding [TACH_CH_TACH0A | TACH_CH_TACH0B] and/or
* [TACH_CH_TACH1A | TACH_CH_TACH1B]
*/
const struct fan_tach_t fan_tach[] = {
[PWM_HW_CH_DCR0] = {
.ch_tach = TACH_CH_NULL,
.fan_p = -1,
.rpm_re = -1,
.s_duty = -1,
},
[PWM_HW_CH_DCR1] = {
.ch_tach = TACH_CH_NULL,
.fan_p = -1,
.rpm_re = -1,
.s_duty = -1,
},
[PWM_HW_CH_DCR2] = {
.ch_tach = TACH_CH_TACH1A,
.fan_p = 2,
.rpm_re = 1,
.s_duty = 1,
},
[PWM_HW_CH_DCR3] = {
.ch_tach = TACH_CH_NULL,
.fan_p = -1,
.rpm_re = -1,
.s_duty = -1,
},
[PWM_HW_CH_DCR4] = {
.ch_tach = TACH_CH_NULL,
.fan_p = -1,
.rpm_re = -1,
.s_duty = -1,
},
[PWM_HW_CH_DCR5] = {
.ch_tach = TACH_CH_NULL,
.fan_p = -1,
.rpm_re = -1,
.s_duty = -1,
},
[PWM_HW_CH_DCR6] = {
.ch_tach = TACH_CH_NULL,
.fan_p = -1,
.rpm_re = -1,
.s_duty = -1,
},
[PWM_HW_CH_DCR7] = {
.ch_tach = TACH_CH_NULL,
.fan_p = -1,
.rpm_re = -1,
.s_duty = -1,
},
};
BUILD_ASSERT(ARRAY_SIZE(fan_tach) == PWM_HW_CH_TOTAL);
/* PWM channels */
const struct pwm_t pwm_channels[] = {
[PWM_CH_FAN] = {
.channel = PWM_HW_CH_DCR2,
.flags = PWM_CONFIG_HAS_RPM_MODE,
.freq_hz = 30000,
.pcfsr_sel = PWM_PRESCALER_C7,
},
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
#if defined(CONFIG_USBC_VCONN) && defined(CONFIG_USB_PD_TCPM_ITE_ON_CHIP)
void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
{
#ifndef CONFIG_USBC_PPC_VCONN
/*
* Setting VCONN low by disabling the power switch before
* enabling the VCONN on respective CC line
*/
gpio_set_level(tcpc_gpios[port].vconn.cc1_pin,
!tcpc_gpios[port].vconn.pin_pol);
gpio_set_level(tcpc_gpios[port].vconn.cc2_pin,
!tcpc_gpios[port].vconn.pin_pol);
if (enabled)
gpio_set_level((cc_pin != USBPD_CC_PIN_1) ?
tcpc_gpios[port].vconn.cc2_pin :
tcpc_gpios[port].vconn.cc1_pin,
tcpc_gpios[port].vconn.pin_pol);
#endif
}
#endif
| 23.824675 | 73 | 0.679204 |
9c0803bbf3d3c82762732d5b760f772a65a0f0e3 | 3,192 | c | C | util/file.c | aaaaaa123456789/bspbuild | 7563c218cc2eaaa271f9962f89e1d6d87d485622 | [
"Unlicense"
] | 4 | 2017-11-18T02:10:35.000Z | 2018-10-30T04:04:07.000Z | util/file.c | aaaaaa123456789/xorbsp | 7563c218cc2eaaa271f9962f89e1d6d87d485622 | [
"Unlicense"
] | 4 | 2018-02-17T19:10:47.000Z | 2018-07-18T10:48:47.000Z | util/file.c | aaaaaa123456789/bspbuild | 7563c218cc2eaaa271f9962f89e1d6d87d485622 | [
"Unlicense"
] | null | null | null | #include "proto.h"
FILE * open_text_file (const char * file, char ** error) {
return open_file(file, "r", "reading", error);
}
FILE * open_binary_file (const char * file, char ** error) {
return open_file(file, "rb", "reading", error);
}
FILE * open_binary_file_for_writing (const char * file, char ** error) {
return open_file(file, "wb", "writing", error);
}
FILE * open_file (const char * file, const char * mode, const char * mode_description, char ** error) {
FILE * fp = fopen(file, mode);
if (!fp)
*error = generate_string("could not open file %s for %s", file, mode_description);
else
*error = NULL;
return fp;
}
char * read_line (FILE * fp) {
char * line = NULL;
unsigned length = 0;
int c;
while (1) {
c = getc(fp);
if ((c == EOF) || (c == '\n')) break;
if (c == '\r') continue;
line = realloc(line, length + 1);
line[length ++] = c;
}
line = realloc(line, length + 1);
line[length] = 0;
return line;
}
char ** read_file_as_lines (FILE * fp, unsigned * line_count) {
char ** lines = NULL;
unsigned count = 0;
char * line;
while (!feof(fp)) {
line = read_line(fp);
lines = realloc(lines, sizeof(char *) * (count + 1));
lines[count ++] = line;
}
lines = realloc(lines, sizeof(char *) * (count + 1));
lines[count] = NULL;
if (line_count) *line_count = count;
return lines;
}
int write_data_to_file (FILE * fp, const void * data, unsigned length) {
unsigned rv;
const char * current = data;
while (length) {
rv = fwrite(current, 1, (length > 65536) ? 65536 : length, fp);
if (!rv) return 0;
current += rv;
length -= rv;
}
return 1;
}
long get_file_length (FILE * fp) {
fpos_t saved_pos;
if (fgetpos(fp, &saved_pos) < 0) return -1;
long result = -1;
if (fseek(fp, 0, 2) >= 0) result = ftell(fp);
fsetpos(fp, &saved_pos);
return result;
}
Buffer read_file_into_buffer (const char * filename, char ** error) {
*error = NULL;
FILE * fp = open_binary_file(filename, error);
if (*error) return NULL;
unsigned long length = get_file_length(fp);
if (length > (UINT_MAX - sizeof(struct buffer))) {
fclose(fp);
*error = generate_string("invalid file size for file %s", filename);
return NULL;
}
Buffer result = malloc(sizeof(struct buffer) + length);
if (!result) {
fclose(fp);
*error = duplicate_string("out of memory");
return NULL;
}
result -> length = length;
char * wp = result -> data;
int current, rv;
while (length) {
current = (length > FILE_BUFFER_SIZE) ? FILE_BUFFER_SIZE : length;
rv = fread(wp, 1, current, fp);
if (rv <= 0) {
fclose(fp);
free(result);
*error = generate_string("could not read data from %s", filename);
return NULL;
}
length -= rv;
wp += rv;
}
fclose(fp);
return result;
}
char * write_buffer_to_new_file (const char * filename, Buffer buffer) {
char * error;
FILE * fp = open_binary_file_for_writing(filename, &error);
if (error) return error;
int rv = write_data_to_file(fp, buffer -> data, buffer -> length);
fclose(fp);
if (!rv) return generate_string("could not write data to %s", filename);
return NULL;
}
| 26.6 | 103 | 0.618421 |
414277bf4ece7132959e1c3d5a9faac8504e3e5c | 911 | c | C | _Books_/C - KNK/06 LOOPS/Projects/{proj02}gcd_greatest_common_divisor.c | JUD210/Study-Note | 2add9db3f11d99370f49878f0c19e9caa60d2d02 | [
"MIT"
] | null | null | null | _Books_/C - KNK/06 LOOPS/Projects/{proj02}gcd_greatest_common_divisor.c | JUD210/Study-Note | 2add9db3f11d99370f49878f0c19e9caa60d2d02 | [
"MIT"
] | null | null | null | _Books_/C - KNK/06 LOOPS/Projects/{proj02}gcd_greatest_common_divisor.c | JUD210/Study-Note | 2add9db3f11d99370f49878f0c19e9caa60d2d02 | [
"MIT"
] | null | null | null | /* Write a program that asks the user to enter two integers, then calculates and displays their greatest common divisor (GCD):
Enter two integers: 12 28 (input)
Greatest common divisor: 4
Hint: The classic algorithm for computing the GCD, known as Euclid's algorithm, goes as follows:
- Let m and n be variables containing the two numbers.
- if n is 0, then stop: in contains the GCD.
- Otherwise, compute the remainder when m is divided by n.
- Copy n into m and copy the remainder into n.
- Then repeat the process, starting with testing whether n is O.
*/
#include <stdio.h>
int main() {
int m, n, remainder;
printf("Enter two integers: ");
scanf("%d%d", &m, &n);
// Enter two integers: 12 28
while (n != 0) {
remainder = m % n;
m = n;
n = remainder;
}
printf("Greatest common divisor: %d\n", m);
// Greatest common divisor: 4
return 0;
} | 26.794118 | 126 | 0.657519 |
418b3c03f1484a41498baf73d02f5d01af4af760 | 931 | h | C | src/rpc_sub.h | opset/openset | 201ee4a6247b6cce369885e05794e7dd3e8b8508 | [
"MIT"
] | 18 | 2017-09-28T16:46:27.000Z | 2022-03-13T19:32:04.000Z | src/rpc_sub.h | perple-io/openset | 201ee4a6247b6cce369885e05794e7dd3e8b8508 | [
"MIT"
] | 14 | 2017-10-05T13:40:48.000Z | 2019-10-18T15:44:44.000Z | src/rpc_sub.h | perple-io/openset | 201ee4a6247b6cce369885e05794e7dd3e8b8508 | [
"MIT"
] | 4 | 2017-12-07T22:34:10.000Z | 2021-07-17T00:19:43.000Z | #pragma once
#include "rpc_global.h"
#include "shuttle.h"
#include "database.h"
#include "http_serve.h"
using namespace openset::async;
using namespace openset::db;
namespace openset::comms
{
class RpcSub
{
public:
// POST /v1/revent/{table}/trigger/{revent_name}
//static void revent_create(const openset::web::MessagePtr message, const RpcMapping& matches);
// GET /v1/revent/{table}/trigger/{revent_name}
//static void revent_describe(const openset::web::MessagePtr message, const RpcMapping& matches);
//
// DELETE /v1/subscription/{table}/{segment_name}/{sub_name}
static void sub_delete(const openset::web::MessagePtr message, const RpcMapping& matches);
// POST /v1/subscription/{table}/{segment_name}/{sub_name}
static void sub_create(const openset::web::MessagePtr message, const RpcMapping& matches);
};
} | 35.807692 | 106 | 0.671321 |
5775ab8f127dc8d08b6c1f4576bc2e019b457a89 | 9,705 | h | C | src/generic.h | paladin-t/bitty | a09d45ba5b0f038d19d80ef7b98d8342d328bccc | [
"BSD-3-Clause"
] | 63 | 2020-10-22T10:31:00.000Z | 2022-03-25T15:54:14.000Z | src/generic.h | paladin-t/bitty | a09d45ba5b0f038d19d80ef7b98d8342d328bccc | [
"BSD-3-Clause"
] | 1 | 2021-05-08T18:14:06.000Z | 2021-05-08T18:14:06.000Z | src/generic.h | paladin-t/bitty | a09d45ba5b0f038d19d80ef7b98d8342d328bccc | [
"BSD-3-Clause"
] | 6 | 2021-03-09T07:20:53.000Z | 2022-02-13T05:23:52.000Z | /*
** Bitty
**
** An itty bitty game engine.
**
** Copyright (C) 2020 - 2021 Tony Wang, all rights reserved
**
** For the latest info, see https://github.com/paladin-t/bitty/
*/
#ifndef __GENERIC_H__
#define __GENERIC_H__
#include "bitty.h"
#include <algorithm>
#include <deque>
#include <functional>
/*
** {===========================================================================
** Generic
**
** @note The principle of these templates is to help writing code in a handier
** way, for workspaces, editors, etc.
*/
/**
* @brief Comparison utilities.
*/
namespace Compare {
/**
* @brief Compares two iterables lexicographically.
*/
template<typename Left, typename Right, typename Cmp> int lex(Left left0, Left left1, Right right0, Right right1, Cmp cmp) {
while (left0 != left1 && right0 != right1) {
const int ret = cmp(*left0, *right0);
if (ret < 0)
return -1;
else if (ret > 0)
return 1;
++left0;
++right0;
}
if (left0 == left1 && right0 != right1)
return -1;
else if (left0 != left1 && right0 == right1)
return 1;
return 0;
}
/**
* @brief Compares two iterables documentally.
*/
template<typename Left, typename Right, typename Cmp> int doc(Left left0, Left left1, Right right0, Right right1, Cmp cmp) {
while (left0 != left1 && right0 != right1) {
if (left0 + 1 != left1 && right0 + 1 == right1)
return -1;
else if (left0 + 1 == left1 && right0 + 1 != right1)
return 1;
const int ret = cmp(*left0, *right0);
if (ret < 0)
return -1;
else if (ret > 0)
return 1;
++left0;
++right0;
}
if (left0 == left1 && right0 != right1)
return -1;
else if (left0 != left1 && right0 == right1)
return 1;
return 0;
}
/**
* @brief Compares two iterables differentially, noncommutative.
*
* @param[out] outdec
* @param[out] outinc
*/
template<typename Left, typename Right, typename Coll> std::pair<int, Coll> diff(Left left0, Left left1, Right right0, Right right1, int* outdec = nullptr, Coll* outinc = nullptr) {
int dec = 0;
Coll inc;
if (outdec)
*outdec = 0;
if (outinc)
outinc->clear();
while (left0 != left1 && right0 != right1) {
if (*left0 != *right0) {
while (right0 != right1) {
++dec;
++right0;
}
while (left0 != left1) {
inc.push_back(*left0);
++left0;
}
if (outdec)
*outdec = dec;
if (outinc)
*outinc = inc;
return std::make_pair(dec, inc);
}
++left0;
++right0;
}
if (left0 == left1 && right0 != right1) {
while (right0 != right1) {
++dec;
++right0;
}
} else if (left0 != left1 && right0 == right1) {
while (left0 != left1) {
inc.push_back(*left0);
++left0;
}
}
if (outdec)
*outdec = dec;
if (outinc)
*outinc = inc;
return std::make_pair(dec, inc);
}
}
/**
* @brief Dual collection.
*/
template<typename Val, typename Coll1 = std::deque<Val>, typename Coll2 = std::deque<Val> > class Dual {
public:
typedef Val ValueType;
typedef Coll1 FirstCollection;
typedef Coll2 SecondCollection;
typedef FirstCollection Collection;
typedef typename Collection::const_iterator ConstIterator;
typedef std::function<int(const ValueType &, const ValueType &)> Comparer;
struct Index {
private:
int _index = 0;
bool _second = false;
public:
Index() {
}
Index(int index) : _index(index) {
}
Index(int index, bool second) : _index(index), _second(second) {
}
Index(const Index &other) {
_index = other._index;
_second = other._second;
}
bool operator == (const Index &other) const {
return _index == other._index && _second == other._second;
}
bool operator == (int other) const {
return _index == other;
}
bool operator != (const Index &other) const {
return _index != other._index || _second != other._second;
}
bool operator != (int other) const {
return _index != other;
}
Index &operator = (const Index &other) {
_index = other._index;
_second = other._second;
return *this;
}
Index &operator ++ (void) {
++_index;
return *this;
}
Index operator ++ (int _) {
(void)_;
return Index(_index++, _second);
}
operator int (void) const {
return _index;
}
bool second(void) const {
return _second;
}
};
typedef std::function<void(const ValueType &, Index)> ConstEnumerator;
typedef std::function<void(ValueType &, Index)> Enumerator;
public:
FirstCollection first;
SecondCollection second;
private:
Comparer _firstComparer = nullptr;
Comparer _secondComparer = nullptr;
public:
Dual() {
}
Dual(Comparer fstCmp, Comparer sndCmp) : _firstComparer(fstCmp), _secondComparer(sndCmp) {
}
const Collection &all(void) const {
return first;
}
const ValueType &front(void) const {
return first.front();
}
ValueType &front(void) {
return first.front();
}
int count(void) const {
return (int)first.size();
}
bool empty(void) const {
return first.empty();
}
template<typename T> ConstIterator get(const T &val, std::function<int(const ValueType &, const T &)> cmp) const {
if (_firstComparer) {
ConstIterator it = std::lower_bound(
first.begin(), first.end(),
val,
[&] (const ValueType &left, const T &right) -> bool {
return cmp(left, right) < 0;
}
);
if (it == first.end())
return first.end();
if (cmp(*it, val) != 0)
return first.end();
return it;
}
return std::find_if(
first.begin(), first.end(),
[&] (const ValueType &val_) -> bool {
return cmp(val_, val) == 0;
}
);
}
bool add(const ValueType &val) {
if (_firstComparer) {
first.insert(
std::upper_bound(
first.begin(), first.end(),
val,
[&] (const ValueType &left, const ValueType &right) -> bool {
return _firstComparer(left, right) < 0;
}
),
val
);
} else {
first.push_back(val);
}
if (_secondComparer) {
second.insert(
std::upper_bound(
second.begin(), second.end(),
val,
[&] (const ValueType &left, const ValueType &right) -> bool {
return _secondComparer(left, right) < 0;
}
),
val
);
} else {
second.push_back(val);
}
return true;
}
int remove(const ValueType &val) {
typename Collection::iterator fit = std::find_if(
first.begin(), first.end(),
[&] (const ValueType &val_) -> bool {
return val_ == val;
}
);
if (fit == first.end())
return 0;
first.erase(fit);
typename SecondCollection::iterator sit = std::find_if(
second.begin(), second.end(),
[&] (const ValueType &val_) -> bool {
return val_ == val;
}
);
assert(sit != second.end());
second.erase(sit);
return 1;
}
void clear(void) {
first.clear();
second.clear();
}
Index indexOf(const ValueType &val, bool second_) const {
if (!second_) {
if (_firstComparer) {
typename FirstCollection::const_iterator it = std::upper_bound(
first.begin(), first.end(),
val,
[&] (const ValueType &left, const ValueType &right) -> bool {
return _firstComparer(left, right) < 0;
}
);
if (it != first.end())
return Index((int)(it - first.begin()), second_);
} else {
typename FirstCollection::const_iterator it = std::find_if(
first.begin(), first.end(),
[&] (const ValueType &val_) -> bool {
return val_ == val;
}
);
if (it != first.end())
return Index((int)(it - first.begin()), second_);
}
return Index(-1, second_);
}
if (_secondComparer) {
typename SecondCollection::const_iterator it = std::upper_bound(
second.begin(), second.end(),
val,
[&] (const ValueType &left, const ValueType &right) -> bool {
return _secondComparer(left, right) < 0;
}
);
if (it != first.end())
return Index((int)(it - second.begin()), second_);
} else {
typename SecondCollection::const_iterator it = std::find_if(
second.begin(), second.end(),
[&] (const ValueType &val_) -> bool {
return val_ == val;
}
);
if (it != second.end())
return Index((int)(it - second.begin()), second_);
}
return Index(-1, second_);
}
ConstIterator begin(void) const {
return first.begin();
}
ConstIterator end(void) const {
return first.end();
}
int foreach(ConstEnumerator enumerator) const {
int result = 0;
Index i = 0;
for (ConstIterator fit = first.begin(); fit != first.end(); ++fit) {
enumerator(*fit, i++);
++result;
}
return result;
}
/**
* @note This function gives you both read and write right, but you should
* never modify the relevant data if it's ordered.
*/
int foreach(Enumerator enumerator) {
int result = 0;
Index i = 0;
for (typename Collection::iterator fit = first.begin(); fit != first.end(); ++fit) {
enumerator(*fit, i++);
++result;
}
return result;
}
void sort(void) {
if (_firstComparer) {
std::sort(
first.begin(), first.end(),
[&] (const ValueType &left, const ValueType &right) -> bool {
return _firstComparer(left, right) < 0;
}
);
}
if (_secondComparer) {
std::sort(
second.begin(), second.end(),
[&] (const ValueType &left, const ValueType &right) -> bool {
return _secondComparer(left, right) < 0;
}
);
}
}
};
/* ===========================================================================} */
#endif /* __GENERIC_H__ */
| 22.157534 | 182 | 0.575992 |
3b84f38d51eeade85ef330e27743ee2957c048e8 | 891 | h | C | mapEditor/src/panel/sounds/SoundTableView.h | petitg1987/urchinEngine | a14a57ac49a19237d748d2eafc7c2a38a45b95d6 | [
"BSL-1.0"
] | 18 | 2020-06-12T00:04:46.000Z | 2022-01-11T14:56:19.000Z | mapEditor/src/panel/sounds/SoundTableView.h | petitg1987/urchinEngine | a14a57ac49a19237d748d2eafc7c2a38a45b95d6 | [
"BSL-1.0"
] | null | null | null | mapEditor/src/panel/sounds/SoundTableView.h | petitg1987/urchinEngine | a14a57ac49a19237d748d2eafc7c2a38a45b95d6 | [
"BSL-1.0"
] | 6 | 2020-08-16T15:58:41.000Z | 2022-03-05T13:17:50.000Z | #pragma once
#include <QtWidgets/QTableView>
#include <QStandardItemModel>
#include <UrchinCommon.h>
#include <UrchinMapHandler.h>
#include <controller/SceneController.h>
Q_DECLARE_METATYPE(const urchin::SceneSound*)
namespace urchin {
class SoundTableView : public QTableView, public Observable {
Q_OBJECT
public:
explicit SoundTableView(QWidget* = nullptr);
enum NotificationType {
SOUND_SELECTION_CHANGED
};
bool hasSceneSoundSelected() const;
const SceneSound* getSelectedSceneSound() const;
void addSound(const SceneSound&);
bool removeSelectedSound();
void removeAllSounds();
private:
QStandardItemModel* soundsListModel;
void selectionChanged(const QItemSelection&, const QItemSelection&) override;
};
}
| 23.447368 | 89 | 0.653199 |
f32af376577c883aa9578c4869b24d3e56ad382a | 788 | h | C | cc3200-sdk/ti_rtos/ti_rtos_config/ewarm/iar/tirtos/ti/catalog/peripherals/hdvicp2/hdvicp2.h | rchtsang/cc3200-sdk-linux-gcc | 92d11e088a19cdea9374ef0ead2c3dd55995dcff | [
"MIT"
] | 2 | 2017-04-27T09:24:42.000Z | 2020-04-01T17:52:28.000Z | cc3200-sdk/ti_rtos/ti_rtos_config/ewarm/iar/tirtos/ti/catalog/peripherals/hdvicp2/hdvicp2.h | rchtsang/cc3200-sdk-linux-gcc | 92d11e088a19cdea9374ef0ead2c3dd55995dcff | [
"MIT"
] | null | null | null | cc3200-sdk/ti_rtos/ti_rtos_config/ewarm/iar/tirtos/ti/catalog/peripherals/hdvicp2/hdvicp2.h | rchtsang/cc3200-sdk-linux-gcc | 92d11e088a19cdea9374ef0ead2c3dd55995dcff | [
"MIT"
] | 3 | 2018-01-30T16:38:52.000Z | 2022-03-30T00:56:46.000Z | /*
* Copyright (c) 2015 by Texas Instruments and others.
* All rights reserved. This program and the accompanying materials
* are made available under the terms of the Eclipse Public License v1.0
* which accompanies this distribution, and is available at
* http://www.eclipse.org/legal/epl-v10.html
*
* Contributors:
* Texas Instruments - initial implementation
*
* */
#ifndef ti_catalog_peripherals_hdvicp2_hdvicp2_h
#define ti_catalog_peripherals_hdvicp2_hdvicp2_h
#include <xdc/std.h>
typedef volatile struct ti_catalog_peripherals_hdvicp2_Hdvicp2Regs {
} ti_catalog_peripherals_hdvicp2_Hdvicp2Regs;
#endif
/*
* @(#) ti.catalog.peripherals.hdvicp2; 1,0,0,; 12-4-2015 21:40:23; /db/ztree/library/trees/platform/platform-q16/src/
*/
| 30.307692 | 120 | 0.738579 |
b393b42b9db000f213188b2d6b141244785652e8 | 2,716 | c | C | jni/sdk/v2_0_1/ARDroneLib/VP_SDK/VP_Api/vp_api_error.c | hatpick/DroneMyoGlass | d1a7a0d9ebd71a62f54f4356a47a0eb6b98474ee | [
"Apache-2.0"
] | 46 | 2015-02-11T13:56:53.000Z | 2021-03-25T20:46:14.000Z | jni/sdk/v2_0_1/ARDroneLib/VP_SDK/VP_Api/vp_api_error.c | hatpick/DroneMyoGlass | d1a7a0d9ebd71a62f54f4356a47a0eb6b98474ee | [
"Apache-2.0"
] | 2 | 2018-02-23T02:22:51.000Z | 2020-07-17T03:57:09.000Z | jni/sdk/v2_0_1/ARDroneLib/VP_SDK/VP_Api/vp_api_error.c | hatpick/DroneMyoGlass | d1a7a0d9ebd71a62f54f4356a47a0eb6b98474ee | [
"Apache-2.0"
] | 20 | 2015-03-03T16:03:07.000Z | 2020-01-23T14:48:49.000Z | /**
* \brief VP Api. Error management
* \author Thomas Landais <thomas.landais@parrot.fr>
* \version 2.0
* \date first release 16/12/2006
* \date modification 19/03/2007
*/
///////////////////////////////////////////////
// INCLUDES
#include <VP_Api/vp_api_error.h>
/**
* \struct private definition of structure message
* \brief This structure is used to create the list of error message
* \brief the Parrot Video Software Development Kit
*/
typedef struct _vp_api_msg_
{
uint32_t index;
const char *msg;
} vp_api_msg_t;
static const vp_api_msg_t vp_api_errorMsg[] =
{
{VP_API_OK, "OK" },
{VP_API_UNKNOW_ERROR, "Unknown error" },
{VP_API_INPUT_ERROR, "Input error" },
{VP_API_INPUT_CAMIF_SELECTION, "Input CAMIF" },
{VP_API_INPUT_CAMIF_ERROR , "Input CAMIF error" },
{VP_API_INPUT_FILE_SELECTION, "Input FILE" },
{VP_API_INPUT_FILE_ERROR, "Input FILE error" },
{VP_API_INPUT_SOCKET_BLUETOOTH_BNEP, "Input Socket Bluetooth BNEP" },
{VP_API_INPUT_SOCKET_BLUETOOTH_BNEP_ERROR, "Input Socket Bluetooth BNEP Error" },
{VP_API_INPUT_SOCKET_BLUETOOTH_RFCOMM, "Input Socket Bluetooth RFComm" },
{VP_API_INPUT_SOCKET_BLUETOOTH_RFCOMM_ERROR, "Input Socket Bluetooth RFComm Error" },
{VP_API_INPUT_SOCKET_BLUETOOTH_FTP, "Input Socket Bluetooth FTP" },
{VP_API_INPUT_SOCKET_BLUETOOTH_FTP_ERROR, "Input Socket Bluetooth FTP Error" },
{VP_API_INPUT_SOCKET_BLUETOOTH_BIP, "Input Socket Bluetooth BIP" },
{VP_API_INPUT_SOCKET_BLUETOOTH_BIP_ERROR, "Input Socket Bluetooth BIP Error" },
{VP_API_OUTPUT_FILE_SELECTION, "Output file selection" },
{VP_API_OUTPUT_SOCKET_SELECTION, "Output socket selection" },
{VP_API_OUTPUT_BUFFER_SELECTION, "Output buffer selection" },
{VP_API_OUTPUT_ERROR, "Output error" },
};
const char* vp_api_format_message(uint32_t error_code)
{
if(error_code >= VP_API_MAX_NUM_ERROR)
error_code = VP_API_UNKNOW_ERROR;
return vp_api_errorMsg[error_code & 0xFFFF].msg;
}
| 46.827586 | 99 | 0.532769 |
b3a0eae8031a64ea9eb5fc324c530e1d11f4de38 | 10,814 | c | C | lib/queue_service/service.c | lambdaxymox/barrelfish | 06a9f54721a8d96874a8939d8973178a562c342f | [
"MIT"
] | 111 | 2015-02-03T02:57:27.000Z | 2022-03-01T23:57:09.000Z | lib/queue_service/service.c | lambdaxymox/barrelfish | 06a9f54721a8d96874a8939d8973178a562c342f | [
"MIT"
] | 12 | 2016-03-22T14:44:32.000Z | 2020-03-18T13:30:29.000Z | lib/queue_service/service.c | lambdaxymox/barrelfish | 06a9f54721a8d96874a8939d8973178a562c342f | [
"MIT"
] | 55 | 2015-02-03T05:28:12.000Z | 2022-03-31T05:00:03.000Z | /**
* \file
* \brief This code shall be intantiated as a service within kaluga.
* It's main purpose is to have a service where the applications network
* stack can requests endpoints of NIC drivers. From the NIC drivers the applicatons
* network stack can request to initalized a queue and in turn receives the
* resources to manage this queue.
*
*/
/*
* Copyright (c) 2018, ETH Zurich.
* All rights reserved.
*
* This file is distributed under the terms in the attached LICENSE file.
* If you do not find this file, copies can be found by writing to:
* ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
*/
#include <barrelfish/barrelfish.h>
#include <barrelfish/nameservice_client.h>
#include <collections/list.h>
#include <driverkit/driverkit.h>
#include <driverkit/control.h>
#include <queue_service/queue_service.h>
#include <if/queue_service_defs.h>
#include "debug.h"
#include "qs_internal.h"
struct queue_service_state {
char* name;
bool is_done;
errval_t err;
collections_listnode* ep_factory_list;
struct slab_allocator alloc;
};
struct ep_factory_state {
char name[256];
coreid_t core;
struct driver_instance* factory_ep;
};
// the full name has to be correct
static int32_t check_name_full(void *data, void *arg)
{
char* name1 = (char*) data;
char* name2 = (char*) arg;
return !strncmp(name1, name2, strlen(name1));
}
// checks also if first part is isimilar i.e. e10k and e10k:8086....
static int32_t check_name_part(void *data, void *arg)
{
char* name1 = (char*) data;
char* name2 = (char*) arg;
QUEUE_SERVICE_DEBUG("%s:%s:%d: Comparing %s %zu %s %zu results %d \n",
__FILE__, __FUNCTION__, __LINE__, name1, strlen(name1),
name2, strlen(name2), strncmp(name2, name1, strlen(name2) -1));
return strncmp(name2, name1, strlen(name2)-1) ? 0: 1;
}
static errval_t request_queue_rpc(struct queue_service_binding *b, coreid_t coreid,
struct capref* ep, errval_t* err)
{
*err = SYS_ERR_OK;
*ep = NULL_CAP;
QUEUE_SERVICE_DEBUG("%s:%s:%d: Request queue rpc \n", __FILE__, __FUNCTION__, __LINE__);
return SYS_ERR_OK;
}
static void request_queue(struct queue_service_binding *b, coreid_t coreid)
{
errval_t err;
struct capref ep;
QUEUE_SERVICE_DEBUG("%s:%s:%d: Request queue\n", __FILE__, __FUNCTION__, __LINE__);
err = request_queue_rpc(b, coreid, &ep, &err);
err = b->tx_vtbl.request_queue_with_constraints_response(b, NOP_CONT, ep, err);
assert(err_is_ok(err));
}
static errval_t request_queue_with_constraints_rpc(struct queue_service_binding *b, coreid_t coreid,
struct capref* ep, errval_t* err)
{
*err = SYS_ERR_OK;
*ep = NULL_CAP;
QUEUE_SERVICE_DEBUG("%s:%s:%d: Request queue with constraints rpc \n", __FILE__, __FUNCTION__, __LINE__);
return SYS_ERR_OK;
}
static void request_queue_with_constraints(struct queue_service_binding *b, coreid_t coreid)
{
errval_t err;
struct capref ep;
QUEUE_SERVICE_DEBUG("%s:%s:%d: Request queue with constraints \n", __FILE__, __FUNCTION__, __LINE__);
err = request_queue_with_constraints_rpc(b, coreid, &ep, &err);
err = b->tx_vtbl.request_queue_with_constraints_response(b, NOP_CONT, ep, err);
assert(err_is_ok(err));
}
static errval_t request_queue_by_name_rpc(struct queue_service_binding *b,
const char* name, coreid_t coreid,
struct capref* ep, errval_t* err)
{
*err = SYS_ERR_OK;
QUEUE_SERVICE_DEBUG("%s:%s:%d: Request queue by name rpc %s \n", __FILE__, __FUNCTION__, __LINE__, name);
struct queue_service_state* st = (struct queue_service_state*) b->st;
struct ep_factory_state* factory_ep = (struct ep_factory_state*)
collections_list_find_if(st->ep_factory_list,
check_name_part, (char*) name);
if (factory_ep == NULL) {
*err = QSERVICE_ERR_NOT_FOUND;
return *err;
}
*err = driverkit_get_driver_ep_cap(factory_ep->factory_ep, ep,
(coreid == factory_ep->core));
if (err_is_fail(*err)) {
return *err;
}
QUEUE_SERVICE_DEBUG("%s:%s:%d: Request queue by name rpc done \n", __FILE__, __FUNCTION__, __LINE__);
return SYS_ERR_OK;
}
static void request_queue_by_name(struct queue_service_binding *b, const char* name, coreid_t core)
{
errval_t err;
struct capref ep = NULL_CAP;
QUEUE_SERVICE_DEBUG("%s:%s:%d: Request queue by name \n", __FILE__, __FUNCTION__, __LINE__);
err = request_queue_by_name_rpc(b, name, core, &ep, &err);
err = b->tx_vtbl.request_queue_by_name_response(b, NOP_CONT, ep, err);
assert(err_is_ok(err));
QUEUE_SERVICE_DEBUG("%s:%s:%d: Request queue by name done \n", __FILE__, __FUNCTION__, __LINE__);
}
static struct queue_service_rx_vtbl rx_vtbl = {
.request_queue_call = request_queue,
.request_queue_with_constraints_call = request_queue_with_constraints,
.request_queue_by_name_call = request_queue_by_name
};
static struct queue_service_rpc_rx_vtbl rpc_rx_vtbl = {
.request_queue_call = request_queue_rpc,
.request_queue_with_constraints_call = request_queue_with_constraints_rpc,
.request_queue_by_name_call = request_queue_by_name_rpc
};
static void export_cb(void *st, errval_t err, iref_t iref)
{
struct queue_service_state* state = (struct queue_service_state*) st;
state->err = err;
if (err_is_ok(err)) {
if (state->name == NULL) {
err = nameservice_register(DEFAULT_SERVICE_NAME, iref);
} else {
err = nameservice_register(state->name, iref);
}
state->err = err;
}
state->is_done = true;
}
static errval_t connect_cb(void *st, struct queue_service_binding *b)
{
b->rx_vtbl = rx_vtbl;
b->rpc_rx_vtbl = rpc_rx_vtbl;
queue_service_rpc_client_init(b);
// Set up continuation queue
b->st = st;
QUEUE_SERVICE_DEBUG("%s:%s:%d: New connection\n", __FILE__, __FUNCTION__, __LINE__);
return SYS_ERR_OK;
}
/**
* @brief initializes the queue service with a provided name
*
* @param st returned queue service state handle
*
* @return SYS_ERR_OK on sucess, errval on failure
*/
errval_t queue_service_init(struct queue_service_state** state, char* name)
{
struct queue_service_state* st = calloc(sizeof(struct queue_service_state), 1);
if (st == NULL) {
return LIB_ERR_MALLOC_FAIL;
}
collections_list_create(&st->ep_factory_list, NULL);
st->err = SYS_ERR_OK;
st->is_done = false;
if (name != NULL) {
st->name = malloc(strlen(name));
strncpy(st->name, name, strlen(name));
} else {
st->name = NULL;
}
slab_init(&st->alloc, sizeof(struct ep_factory_state), slab_default_refill);
errval_t err = queue_service_export(st, export_cb, connect_cb,
get_default_waitset(),
IDC_EXPORT_FLAGS_DEFAULT);
if (err_is_fail(err)) {
free(st);
return err;
}
QUEUE_SERVICE_DEBUG("%s:%s:%d: Trying to export queue service interface\n", __FILE__, __FUNCTION__, __LINE__);
while (!st->is_done) {
messages_wait_and_handle_next();
}
*state = st;
return st->err;
}
/**
* @brief initializes the queue service with a default name
*
* @param st returned queue service state handle
*
* @return SYS_ERR_OK on sucess, errval on failure
*/
errval_t queue_service_init_default(struct queue_service_state** st)
{
QUEUE_SERVICE_DEBUG("%s:%s:%d: calling init default \n", __FILE__, __FUNCTION__, __LINE__);
return queue_service_init(st, NULL);
}
/**
* @brief Adds an endpoint factory to the queue service. The queu service can
* request endpoints form these factories which represent connectons
* to drivers on which a single queue can be requested.
*
* @param st service state handle
* @param name factory name
* @param core core id on which the factory is running
* @param factory driver_instance struct of a endpoint factory
* (normally only available in kaluga)
*
* @return SYS_ERR_OK on sucess, errval on failure
*/
errval_t queue_service_add_ep_factory(struct queue_service_state* st,
char* factory_name,
coreid_t core,
struct driver_instance* factory)
{
if (strlen(factory_name) > MAX_NAME_LEN) {
return QSERVICE_ERR_NAME;
}
struct ep_factory_state* epf_state = slab_alloc(&st->alloc);
// check if aleady in list
void* item = collections_list_find_if(st->ep_factory_list, check_name_full,
factory_name);
if (item == NULL) {
QUEUE_SERVICE_DEBUG("%s:%s:%d: Add factory ep %s\n", __FILE__, __FUNCTION__, __LINE__, factory_name);
strncpy(epf_state->name, factory_name, strlen(factory_name));
epf_state->factory_ep = factory;
epf_state->core = core;
collections_list_insert_tail(st->ep_factory_list, epf_state);
} else {
QUEUE_SERVICE_DEBUG("%s:%s:%d: Already have an ep: %s\n", __FILE__, __FUNCTION__, __LINE__, factory_name);
return QSERVICE_ERR_ALREADY_ADDED;
}
return SYS_ERR_OK;
};
/**
* @brief Create an endpoint to the queue service itself
*
* @param st service state handle
* @param core core on which the program requesting the ep runs
* @param ep returend endpoint of this queue service
*
* @return SYS_ERR_OK on sucess, errval on failure
*/
errval_t queue_service_create_self_ep(struct queue_service_state* st,
coreid_t core,
struct capref* ep)
{
if (st == NULL) {
return QSERVICE_ERR_INVALID_SERVICE;
}
errval_t err;
struct queue_service_binding* b;
QUEUE_SERVICE_DEBUG("%s:%s:%d: Create self ep\n", __FILE__, __FUNCTION__, __LINE__);
err = queue_service_create_endpoint(core == disp_get_core_id()?
IDC_ENDPOINT_LMP: IDC_ENDPOINT_UMP,
&rx_vtbl, st,
get_default_waitset(),
IDC_ENDPOINT_FLAGS_DUMMY,
&b, *ep);
return err;
};
| 32.572289 | 114 | 0.638062 |
7b22e788a23300a6526f520ac834dd412428e508 | 1,761 | c | C | nfp-sdk-6.0.1/p4/components/flowcache/me/lib/standardlibrary/_c/mem_atomic_indirect.c | earthcomputing/Netronome | 9f5132ecea3c134322305c9524da7189374881ec | [
"MIT"
] | null | null | null | nfp-sdk-6.0.1/p4/components/flowcache/me/lib/standardlibrary/_c/mem_atomic_indirect.c | earthcomputing/Netronome | 9f5132ecea3c134322305c9524da7189374881ec | [
"MIT"
] | null | null | null | nfp-sdk-6.0.1/p4/components/flowcache/me/lib/standardlibrary/_c/mem_atomic_indirect.c | earthcomputing/Netronome | 9f5132ecea3c134322305c9524da7189374881ec | [
"MIT"
] | null | null | null | /*
* Copyright (C) 2014-2016, Netronome Systems, Inc. All rights reserved.
*
* @file mem_atomic_indirect.c
* @brief MEM atomic indirect function.
*/
#include <assert.h>
#include <nfp.h>
#include <stdint.h>
#include <nfp6000/nfp_me.h>
#include <mem_atomic_indirect_c.h>
__intrinsic void mem_write_atomic_with_bytemask (__xwrite void *data, __mem void *addr,
size_t size, const size_t max_size, sync_t sync, SIGNAL *sig, unsigned int byte_mask)
{
__gpr uint32_t addr_hi;
__gpr uint32_t addr_lo;
struct nfp_mecsr_prev_alu prev_alu;
struct nfp_mecsr_cmd_indirect_ref_0 ind_csr;
unsigned int count = (size >> 2);
unsigned int max_count = (max_size >> 2);
ctassert(__is_write_reg(data));
try_ctassert(__is_aligned(size, 4));
try_ctassert(size <= 128);
prev_alu.__raw = 0;
prev_alu.ov_bm_csr = 1;
ind_csr.__raw = 0;
ind_csr.byte_mask = byte_mask;
addr_hi = ((unsigned long long int)addr >> 8) & 0xff000000;
addr_lo = (unsigned long long int)addr & 0xffffffff;
if (sync == sig_done) {
__asm
{
local_csr_wr[CMD_INDIRECT_REF_0, ind_csr.__raw]
alu[--, --, B, prev_alu.__raw]
mem[write_atomic, *data, addr_hi, << 8, addr_lo, __ct_const_val(count)], sig_done[*sig], indirect_ref
}
} else {
__asm
{
local_csr_wr[CMD_INDIRECT_REF_0, ind_csr.__raw]
alu[--, --, B, prev_alu.__raw]
mem[write_atomic, *data, addr_hi, << 8, addr_lo, __ct_const_val(count)], ctx_swap[*sig], indirect_ref
}
}
}
| 31.446429 | 115 | 0.582056 |
701fe1f6e899f572f0565a453b3df1976fe7aaf7 | 1,349 | h | C | macOS/10.13/CoreData.framework/_PFChangeInfo.h | onmyway133/Runtime-Headers | e9b80e7ab9103f37ad421ad6b8b58ee06369d21f | [
"MIT"
] | 30 | 2016-10-09T20:13:00.000Z | 2022-01-24T04:14:57.000Z | macOS/10.13/CoreData.framework/_PFChangeInfo.h | onmyway133/Runtime-Headers | e9b80e7ab9103f37ad421ad6b8b58ee06369d21f | [
"MIT"
] | null | null | null | macOS/10.13/CoreData.framework/_PFChangeInfo.h | onmyway133/Runtime-Headers | e9b80e7ab9103f37ad421ad6b8b58ee06369d21f | [
"MIT"
] | 7 | 2017-08-29T14:41:25.000Z | 2022-01-19T17:14:54.000Z | /* Generated by RuntimeBrowser
Image: /System/Library/Frameworks/CoreData.framework/Versions/A/CoreData
*/
@interface _PFChangeInfo : NSObject {
unsigned long long _changeType;
NSIndexPath * _finalIndexPath;
_NSDefaultSectionInfo * _finalSectionInfo;
NSManagedObject * _object;
NSIndexPath * _startIndexPath;
_NSDefaultSectionInfo * _startSectionInfo;
}
@property (nonatomic, readwrite) unsigned long long changeType;
@property (nonatomic, readwrite, retain) NSIndexPath *finalIndexPath;
@property (nonatomic, readwrite, retain) _NSDefaultSectionInfo *finalSectionInfo;
@property (nonatomic, readonly, retain) NSManagedObject *object;
@property (nonatomic, readwrite, retain) NSIndexPath *startIndexPath;
@property (nonatomic, readwrite, retain) _NSDefaultSectionInfo *startSectionInfo;
- (unsigned long long)changeType;
- (void)dealloc;
- (id)description;
- (id)finalIndexPath;
- (id)finalSectionInfo;
- (unsigned long long)hash;
- (id)initWithObject:(id)arg1;
- (id)initWithObject:(id)arg1 changeType:(unsigned long long)arg2;
- (BOOL)isEqual:(id)arg1;
- (id)object;
- (void)setChangeType:(unsigned long long)arg1;
- (void)setFinalIndexPath:(id)arg1;
- (void)setFinalSectionInfo:(id)arg1;
- (void)setStartIndexPath:(id)arg1;
- (void)setStartSectionInfo:(id)arg1;
- (id)startIndexPath;
- (id)startSectionInfo;
@end
| 33.725 | 81 | 0.7702 |
f25463e4053251a2fa80b4def760ed5f80b1ea2d | 241 | c | C | musl-1.1.18/src/dirent/rewinddir.c | h7ga40/azure_iot_hub | e255088c4b2afe5e86cae820e8e3fb747f28b35b | [
"curl",
"Apache-2.0",
"MIT"
] | null | null | null | musl-1.1.18/src/dirent/rewinddir.c | h7ga40/azure_iot_hub | e255088c4b2afe5e86cae820e8e3fb747f28b35b | [
"curl",
"Apache-2.0",
"MIT"
] | null | null | null | musl-1.1.18/src/dirent/rewinddir.c | h7ga40/azure_iot_hub | e255088c4b2afe5e86cae820e8e3fb747f28b35b | [
"curl",
"Apache-2.0",
"MIT"
] | 1 | 2019-09-27T10:22:23.000Z | 2019-09-27T10:22:23.000Z | #include <dirent.h>
#include <unistd.h>
#include "__dirent.h"
#include "libc.h"
void rewinddir(DIR *dir)
{
LOCK(dir->lock);
lseek(dir->fd, 0, SEEK_SET);
dir->buf_pos = dir->buf_end = 0;
dir->tell = 0;
UNLOCK(dir->lock);
}
| 17.214286 | 34 | 0.609959 |
cc1a30022547ca2cb6fb9b6b37793d2c187d8c2a | 891,318 | h | C | include/plat/marvell/octeontx/csr/cavm-csrs-rst.h | Gateworks/atf-newport | 67f418ebe7ee6630f77c3ef7a10b7bf6c15c5ce3 | [
"BSD-3-Clause"
] | null | null | null | include/plat/marvell/octeontx/csr/cavm-csrs-rst.h | Gateworks/atf-newport | 67f418ebe7ee6630f77c3ef7a10b7bf6c15c5ce3 | [
"BSD-3-Clause"
] | null | null | null | include/plat/marvell/octeontx/csr/cavm-csrs-rst.h | Gateworks/atf-newport | 67f418ebe7ee6630f77c3ef7a10b7bf6c15c5ce3 | [
"BSD-3-Clause"
] | 1 | 2021-06-12T11:06:26.000Z | 2021-06-12T11:06:26.000Z | #ifndef __CAVM_CSRS_RST_H__
#define __CAVM_CSRS_RST_H__
/* This file is auto-generated. Do not edit */
/***********************license start***********************************
* Copyright (C) 2019 Marvell International Ltd.
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
***********************license end**************************************/
/**
* @file
*
* Configuration and status register (CSR) address and type definitions for
* OcteonTX RST.
*
* This file is auto generated. Do not edit.
*
*/
/**
* Enumeration rst_bar_e
*
* RST Base Address Register Enumeration
* Enumerates the base address registers.
*/
#define CAVM_RST_BAR_E_RST_PF_BAR0_CN8 (0x87e006000000ll)
#define CAVM_RST_BAR_E_RST_PF_BAR0_CN8_SIZE 0x800000ull
#define CAVM_RST_BAR_E_RST_PF_BAR0_CN9 (0x87e006000000ll)
#define CAVM_RST_BAR_E_RST_PF_BAR0_CN9_SIZE 0x10000ull
#define CAVM_RST_BAR_E_RST_PF_BAR2 (0x87e00a000000ll)
#define CAVM_RST_BAR_E_RST_PF_BAR2_SIZE 0x10000ull
#define CAVM_RST_BAR_E_RST_PF_BAR4 (0x87e006f00000ll)
#define CAVM_RST_BAR_E_RST_PF_BAR4_SIZE 0x100000ull
/**
* Enumeration rst_boot_fail_e
*
* RST Boot Failure Code Enumeration
* Enumerates the reasons for boot failure, returned to post-boot code
* in argument register 0 and blinked on GPIO\<11\>.
*/
#define CAVM_RST_BOOT_FAIL_E_AUTH (6)
#define CAVM_RST_BOOT_FAIL_E_BUS_ERROR (0xb)
#define CAVM_RST_BOOT_FAIL_E_DEVICE (3)
#define CAVM_RST_BOOT_FAIL_E_GOOD_CN8 (0)
#define CAVM_RST_BOOT_FAIL_E_GOOD_CN9 (1)
#define CAVM_RST_BOOT_FAIL_E_HASH (8)
#define CAVM_RST_BOOT_FAIL_E_KEY (7)
#define CAVM_RST_BOOT_FAIL_E_MAGIC (4)
#define CAVM_RST_BOOT_FAIL_E_MCORE (5)
#define CAVM_RST_BOOT_FAIL_E_METH (2)
#define CAVM_RST_BOOT_FAIL_E_SCRIPT_ACC_ERROR (0xa)
#define CAVM_RST_BOOT_FAIL_E_SCRIPT_INVALID (9)
#define CAVM_RST_BOOT_FAIL_E_UNINIT (0)
/**
* Enumeration rst_boot_method_e
*
* RST Primary Boot-strap Method Enumeration
* Enumerates the primary (first choice) and secondary (second choice) boot
* device. Primary boot method is selected with the straps
* GPIO_STRAP_PIN_E::BOOT_METHOD2..0, and secondary is selected with the straps
* GPIO_STRAP_PIN_E::BOOT_METHOD5..3.
*
* To disable the secondary method, use ::REMOTE.
*/
#define CAVM_RST_BOOT_METHOD_E_CCPI0 (9)
#define CAVM_RST_BOOT_METHOD_E_CCPI1 (0xa)
#define CAVM_RST_BOOT_METHOD_E_CCPI2 (0xb)
#define CAVM_RST_BOOT_METHOD_E_EMMC_CS0 (0)
#define CAVM_RST_BOOT_METHOD_E_EMMC_CS1 (1)
#define CAVM_RST_BOOT_METHOD_E_EMMC_LS (3)
#define CAVM_RST_BOOT_METHOD_E_EMMC_SS (2)
#define CAVM_RST_BOOT_METHOD_E_PCIE0 (0xc)
#define CAVM_RST_BOOT_METHOD_E_PCIE2 (0xd)
#define CAVM_RST_BOOT_METHOD_E_REMOTE_CN8 (8)
#define CAVM_RST_BOOT_METHOD_E_REMOTE_CN9 (7)
#define CAVM_RST_BOOT_METHOD_E_SPI0_CS0 (2)
#define CAVM_RST_BOOT_METHOD_E_SPI0_CS1 (3)
#define CAVM_RST_BOOT_METHOD_E_SPI1_CS0 (4)
#define CAVM_RST_BOOT_METHOD_E_SPI1_CS1 (5)
#define CAVM_RST_BOOT_METHOD_E_SPI24 (5)
#define CAVM_RST_BOOT_METHOD_E_SPI32 (6)
/**
* Enumeration rst_dev_e
*
* Programmable Reset Device Enumeration
* Enumerates devices that have programmable reset domains, and index {a} of RST_DEV_MAP().
*/
#define CAVM_RST_DEV_E_AVS (1)
#define CAVM_RST_DEV_E_CGXX(a) (0x12 + (a))
#define CAVM_RST_DEV_E_EMMC (0x19)
#define CAVM_RST_DEV_E_GSERX(a) (0x1a + (a))
#define CAVM_RST_DEV_E_GSERRX(a) (0x20 + (a))
#define CAVM_RST_DEV_E_MPIX(a) (2 + (a))
#define CAVM_RST_DEV_E_NCSI (0)
#define CAVM_RST_DEV_E_PEMX(a) (0x28 + (a))
#define CAVM_RST_DEV_E_RFIFX_CNF95XX(a) (0x26 + (a))
#define CAVM_RST_DEV_E_RFIFX_LOKI(a) (0x21 + (a))
#define CAVM_RST_DEV_E_ROC_OCLA (0x18)
#define CAVM_RST_DEV_E_SGPIO (0x17)
#define CAVM_RST_DEV_E_SMI_CN96XX (0x16)
#define CAVM_RST_DEV_E_SMI_CN98XX (0x1a)
#define CAVM_RST_DEV_E_SMI_CNF95XX (0x16)
#define CAVM_RST_DEV_E_SMI_LOKI (0x16)
#define CAVM_RST_DEV_E_TWSX(a) (4 + (a))
#define CAVM_RST_DEV_E_UAAX(a) (0xa + (a))
/**
* Enumeration rst_domain_e
*
* RST Domain Enumeration
* This enumerates the values of RST_DEV_MAP()[DMN].
*/
#define CAVM_RST_DOMAIN_E_BPHY (5)
#define CAVM_RST_DOMAIN_E_CHIP (0)
#define CAVM_RST_DOMAIN_E_CORE (1)
#define CAVM_RST_DOMAIN_E_MCP (2)
#define CAVM_RST_DOMAIN_E_OFF (4)
#define CAVM_RST_DOMAIN_E_SCP (3)
/**
* Enumeration rst_int_vec_e
*
* RST MSI-X Vector Enumeration
* Enumerates the MSI-X interrupt vectors.
*/
#define CAVM_RST_INT_VEC_E_INTS (0)
/**
* Enumeration rst_source_e
*
* RST Cause Enumeration
* Enumerates the reset sources for both reset domain mapping and cause of last reset,
* corresponding to the bit numbers of RST_LBOOT.
*/
#define CAVM_RST_SOURCE_E_BPHY_RESET_PIN (0x30)
#define CAVM_RST_SOURCE_E_BPHY_SOFT (0x31)
#define CAVM_RST_SOURCE_E_CHIPKILL (4)
#define CAVM_RST_SOURCE_E_CHIP_RESET_PIN (2)
#define CAVM_RST_SOURCE_E_CHIP_SOFT (3)
#define CAVM_RST_SOURCE_E_COLD_SOFT (1)
#define CAVM_RST_SOURCE_E_CORE_RESET_PIN (0xb)
#define CAVM_RST_SOURCE_E_CORE_SOFT (0xc)
#define CAVM_RST_SOURCE_E_CORE_WDOG (0xd)
#define CAVM_RST_SOURCE_E_DCOK_PIN (0)
#define CAVM_RST_SOURCE_E_MCP_RESET_PIN (8)
#define CAVM_RST_SOURCE_E_MCP_SOFT (9)
#define CAVM_RST_SOURCE_E_MCP_WDOG (0xa)
#define CAVM_RST_SOURCE_E_OCX (0xe)
#define CAVM_RST_SOURCE_E_PEM_CHIPX(a) (0x11 + 2 * (a))
#define CAVM_RST_SOURCE_E_PEM_COREX(a) (0x10 + 2 * (a))
#define CAVM_RST_SOURCE_E_PEM_LINKDOWNX(a) (0x11 + 4 * (a))
#define CAVM_RST_SOURCE_E_PEM_PFFLRX(a) (0x13 + 4 * (a))
#define CAVM_RST_SOURCE_E_PEM_PWRDOWNX(a) (0x12 + 4 * (a))
#define CAVM_RST_SOURCE_E_PERST_PINX(a) (0x10 + 4 * (a))
#define CAVM_RST_SOURCE_E_RSVD_F (0xf)
#define CAVM_RST_SOURCE_E_SCP_RESET_PIN (5)
#define CAVM_RST_SOURCE_E_SCP_SOFT (6)
#define CAVM_RST_SOURCE_E_SCP_WDOG (7)
/**
* Structure rst_boot_stat_s
*
* BOOT_STATUS field Structure
* The ROM boot code stores this data in the RST_BOOT_STATUS register, once per each boot attempt.
*/
union cavm_rst_boot_stat_s
{
uint32_t u;
struct cavm_rst_boot_stat_s_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint32_t reserved_16_31 : 16;
uint32_t trusted : 1; /**< [ 15: 15] This was a trusted-mode boot. */
uint32_t primary : 1; /**< [ 14: 14] This was a boot from the primary device. */
uint32_t scr_done : 1; /**< [ 13: 13] The ROM script ran to completion on this boot. */
uint32_t reserved_7_12 : 6;
uint32_t boot_method : 3; /**< [ 6: 4] The boot method for this boot attempt RST_BOOT_METHOD_E. */
uint32_t fail : 4; /**< [ 3: 0] The failure code for this boot attempt RST_BOOT_FAIL_E. */
#else /* Word 0 - Little Endian */
uint32_t fail : 4; /**< [ 3: 0] The failure code for this boot attempt RST_BOOT_FAIL_E. */
uint32_t boot_method : 3; /**< [ 6: 4] The boot method for this boot attempt RST_BOOT_METHOD_E. */
uint32_t reserved_7_12 : 6;
uint32_t scr_done : 1; /**< [ 13: 13] The ROM script ran to completion on this boot. */
uint32_t primary : 1; /**< [ 14: 14] This was a boot from the primary device. */
uint32_t trusted : 1; /**< [ 15: 15] This was a trusted-mode boot. */
uint32_t reserved_16_31 : 16;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_boot_stat_s_s cn; */
};
/**
* Structure rst_pp_pwr_s
*
* INTERNAL: Core Reset Power Delivery Structure
*
* This structure specifies the layout of RTL reset and power delivery. It is not visible to software.
*/
union cavm_rst_pp_pwr_s
{
uint32_t u;
struct cavm_rst_pp_pwr_s_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint32_t reserved_10_31 : 22;
uint32_t valid : 1; /**< [ 9: 9] Data transmitted on interface is valid.. */
uint32_t ppvid : 6; /**< [ 8: 3] Virtual core number. */
uint32_t dbg_rst : 1; /**< [ 2: 2] Reset control for the core specified by PPVID. */
uint32_t pwrdwn : 1; /**< [ 1: 1] Core does not require power. */
uint32_t rst : 1; /**< [ 0: 0] Reset control for the core specified by PPVID. */
#else /* Word 0 - Little Endian */
uint32_t rst : 1; /**< [ 0: 0] Reset control for the core specified by PPVID. */
uint32_t pwrdwn : 1; /**< [ 1: 1] Core does not require power. */
uint32_t dbg_rst : 1; /**< [ 2: 2] Reset control for the core specified by PPVID. */
uint32_t ppvid : 6; /**< [ 8: 3] Virtual core number. */
uint32_t valid : 1; /**< [ 9: 9] Data transmitted on interface is valid.. */
uint32_t reserved_10_31 : 22;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_pp_pwr_s_s cn8; */
struct cavm_rst_pp_pwr_s_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint32_t reserved_10_31 : 22;
uint32_t valid : 1; /**< [ 9: 9] Data transmitted on interface is valid. */
uint32_t ppvid : 6; /**< [ 8: 3] Virtual core number. */
uint32_t dbg_rst : 1; /**< [ 2: 2] Reset control for the core specified by PPVID. */
uint32_t pwrdwn : 1; /**< [ 1: 1] Core does not require power. */
uint32_t rst : 1; /**< [ 0: 0] Reset control for the core specified by PPVID. */
#else /* Word 0 - Little Endian */
uint32_t rst : 1; /**< [ 0: 0] Reset control for the core specified by PPVID. */
uint32_t pwrdwn : 1; /**< [ 1: 1] Core does not require power. */
uint32_t dbg_rst : 1; /**< [ 2: 2] Reset control for the core specified by PPVID. */
uint32_t ppvid : 6; /**< [ 8: 3] Virtual core number. */
uint32_t valid : 1; /**< [ 9: 9] Data transmitted on interface is valid. */
uint32_t reserved_10_31 : 22;
#endif /* Word 0 - End */
} cn9;
};
/**
* Register (RSL) rst_ap#_affinity_const
*
* RST Virtual AP Affinity Map Register
* This register indicates the processor affinity identification and logical core
* number mapping to physical core numbers. This is indexed by logical core number.
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_apx_affinity_const
{
uint64_t u;
struct cavm_rst_apx_affinity_const_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_56_63 : 8;
uint64_t core : 8; /**< [ 55: 48](RO) Physical core number. */
uint64_t reserved_44_47 : 4;
uint64_t phy_clu : 4; /**< [ 43: 40](RO) Physical cluster number. */
uint64_t reserved_36_39 : 4;
uint64_t phy_core : 4; /**< [ 35: 32](RO) Physical core-within-cluster number. */
uint64_t fov : 1; /**< [ 31: 31](RO) Set to indicate if the fields are valid. */
uint64_t u : 1; /**< [ 30: 30](RO) Set to indicate processors are part of a multprocessor system. */
uint64_t reserved_25_29 : 5;
uint64_t mt : 1; /**< [ 24: 24](RO) Set to indicate multithreaded and [AFF0] is thread number in core. */
uint64_t aff2 : 8; /**< [ 23: 16](RO/H) Affinity 2 for this logical core number. In CNXXXX, the node id. */
uint64_t aff1 : 8; /**< [ 15: 8](RO/H) Affinity 1 for this logical core number. In CNXXXX, the logical cluster id. */
uint64_t aff0 : 8; /**< [ 7: 0](RO/H) Affinity 0 for this logical core number. In CNXXXX, the logical core number within a cluster. */
#else /* Word 0 - Little Endian */
uint64_t aff0 : 8; /**< [ 7: 0](RO/H) Affinity 0 for this logical core number. In CNXXXX, the logical core number within a cluster. */
uint64_t aff1 : 8; /**< [ 15: 8](RO/H) Affinity 1 for this logical core number. In CNXXXX, the logical cluster id. */
uint64_t aff2 : 8; /**< [ 23: 16](RO/H) Affinity 2 for this logical core number. In CNXXXX, the node id. */
uint64_t mt : 1; /**< [ 24: 24](RO) Set to indicate multithreaded and [AFF0] is thread number in core. */
uint64_t reserved_25_29 : 5;
uint64_t u : 1; /**< [ 30: 30](RO) Set to indicate processors are part of a multprocessor system. */
uint64_t fov : 1; /**< [ 31: 31](RO) Set to indicate if the fields are valid. */
uint64_t phy_core : 4; /**< [ 35: 32](RO) Physical core-within-cluster number. */
uint64_t reserved_36_39 : 4;
uint64_t phy_clu : 4; /**< [ 43: 40](RO) Physical cluster number. */
uint64_t reserved_44_47 : 4;
uint64_t core : 8; /**< [ 55: 48](RO) Physical core number. */
uint64_t reserved_56_63 : 8;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_apx_affinity_const_s cn; */
};
typedef union cavm_rst_apx_affinity_const cavm_rst_apx_affinity_const_t;
static inline uint64_t CAVM_RST_APX_AFFINITY_CONST(unsigned long a) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_APX_AFFINITY_CONST(unsigned long a)
{
if (cavm_is_model(OCTEONTX_CN96XX) && (a<=23))
return 0x87e006001000ll + 8ll * ((a) & 0x1f);
if (cavm_is_model(OCTEONTX_CN98XX) && (a<=35))
return 0x87e006001000ll + 8ll * ((a) & 0x3f);
if (cavm_is_model(OCTEONTX_CNF95XX) && (a<=5))
return 0x87e006001000ll + 8ll * ((a) & 0x7);
if (cavm_is_model(OCTEONTX_LOKI) && (a<=5))
return 0x87e006001000ll + 8ll * ((a) & 0x7);
__cavm_csr_fatal("RST_APX_AFFINITY_CONST", 1, a, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_APX_AFFINITY_CONST(a) cavm_rst_apx_affinity_const_t
#define bustype_CAVM_RST_APX_AFFINITY_CONST(a) CSR_TYPE_RSL
#define basename_CAVM_RST_APX_AFFINITY_CONST(a) "RST_APX_AFFINITY_CONST"
#define device_bar_CAVM_RST_APX_AFFINITY_CONST(a) 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_APX_AFFINITY_CONST(a) (a)
#define arguments_CAVM_RST_APX_AFFINITY_CONST(a) (a),-1,-1,-1
/**
* Register (RSL) rst_bcn_pll
*
* RST GSERR Clock PLL Control Register
* This register should only be programmed while all RFIF logic is in reset.
* It is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_bcn_pll
{
uint64_t u;
struct cavm_rst_bcn_pll_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_16_63 : 48;
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Programs the active PLL using [NXT_MUL]. Hardware automatically
clears bit when PLL has been updated. Software should wait at least 20uS
for clock frequency to be reached before releasing GSERRs from reset.
This field is always reinitialized on a chip domain reset.
Changing BCN Clock frequency is for diagnostic use only; changes can only be made
while all RFIF logic is in reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) BCN PLL frequency to be program in 61.44 MHz increments. The
actual value must be in the range between 295 MHz and 1228.8 MHz.
Value will be 307.2 MHz immediately after a cold domain reset. */
uint64_t reserved_7 : 1;
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) BCN clock frequency. Actual frequency is [CUR_MUL] * 61.44 MHz.
Value will reflect [NXT_MUL] after [NXT_PGM] has been set or 307.2 MHz
immediately after a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) BCN clock frequency. Actual frequency is [CUR_MUL] * 61.44 MHz.
Value will reflect [NXT_MUL] after [NXT_PGM] has been set or 307.2 MHz
immediately after a cold domain reset. */
uint64_t reserved_7 : 1;
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) BCN PLL frequency to be program in 61.44 MHz increments. The
actual value must be in the range between 295 MHz and 1228.8 MHz.
Value will be 307.2 MHz immediately after a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Programs the active PLL using [NXT_MUL]. Hardware automatically
clears bit when PLL has been updated. Software should wait at least 20uS
for clock frequency to be reached before releasing GSERRs from reset.
This field is always reinitialized on a chip domain reset.
Changing BCN Clock frequency is for diagnostic use only; changes can only be made
while all RFIF logic is in reset. */
uint64_t reserved_16_63 : 48;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_bcn_pll_s cn; */
};
typedef union cavm_rst_bcn_pll cavm_rst_bcn_pll_t;
#define CAVM_RST_BCN_PLL CAVM_RST_BCN_PLL_FUNC()
static inline uint64_t CAVM_RST_BCN_PLL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_BCN_PLL_FUNC(void)
{
if (cavm_is_model(OCTEONTX_LOKI))
return 0x87e00a001800ll;
__cavm_csr_fatal("RST_BCN_PLL", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_BCN_PLL cavm_rst_bcn_pll_t
#define bustype_CAVM_RST_BCN_PLL CSR_TYPE_RSL
#define basename_CAVM_RST_BCN_PLL "RST_BCN_PLL"
#define device_bar_CAVM_RST_BCN_PLL 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_BCN_PLL 0
#define arguments_CAVM_RST_BCN_PLL -1,-1,-1,-1
/**
* Register (RSL) rst_bist_active
*
* RST BIST Active Status Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_bist_active
{
uint64_t u;
struct cavm_rst_bist_active_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_7_63 : 57;
uint64_t bphy : 1; /**< [ 6: 6](RO/H) BPHY domain BIST in progress. When set, memories accociated with
the BPHY domain are being tested. */
uint64_t ap : 1; /**< [ 5: 5](RO/H) BIST in progress due to AP cores being put into reset. When set, memories
associated with this group are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t csr : 1; /**< [ 4: 4](RO/H) BIST in progress due to access to RST_DEV_MAP(). When set, memories
associated with this access are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain BIST in progress. When set, memories associated with
the SCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain BIST in progress. When set, memories associated with
the MCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain BIST in progress. When set, memories associated with
the core domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t chip : 1; /**< [ 0: 0](RO/H) Chip BIST in progress. Always reads 0. */
#else /* Word 0 - Little Endian */
uint64_t chip : 1; /**< [ 0: 0](RO/H) Chip BIST in progress. Always reads 0. */
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain BIST in progress. When set, memories associated with
the core domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain BIST in progress. When set, memories associated with
the MCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain BIST in progress. When set, memories associated with
the SCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t csr : 1; /**< [ 4: 4](RO/H) BIST in progress due to access to RST_DEV_MAP(). When set, memories
associated with this access are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t ap : 1; /**< [ 5: 5](RO/H) BIST in progress due to AP cores being put into reset. When set, memories
associated with this group are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t bphy : 1; /**< [ 6: 6](RO/H) BPHY domain BIST in progress. When set, memories accociated with
the BPHY domain are being tested. */
uint64_t reserved_7_63 : 57;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_bist_active_s cn9; */
struct cavm_rst_bist_active_cn96xxp1
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_6_63 : 58;
uint64_t ap : 1; /**< [ 5: 5](RO/H) BIST in progress due to AP cores being put into reset. When set, memories
associated with this group are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t csr : 1; /**< [ 4: 4](RO/H) BIST in progress due to access to RST_DEV_MAP(). When set, memories
associated with this access are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain BIST in progress. When set, memories associated with
the SCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain BIST in progress. When set, memories associated with
the MCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain BIST in progress. When set, memories associated with
the core domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t reserved_0 : 1;
#else /* Word 0 - Little Endian */
uint64_t reserved_0 : 1;
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain BIST in progress. When set, memories associated with
the core domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain BIST in progress. When set, memories associated with
the MCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain BIST in progress. When set, memories associated with
the SCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t csr : 1; /**< [ 4: 4](RO/H) BIST in progress due to access to RST_DEV_MAP(). When set, memories
associated with this access are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t ap : 1; /**< [ 5: 5](RO/H) BIST in progress due to AP cores being put into reset. When set, memories
associated with this group are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t reserved_6_63 : 58;
#endif /* Word 0 - End */
} cn96xxp1;
struct cavm_rst_bist_active_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_6_63 : 58;
uint64_t ap : 1; /**< [ 5: 5](RO/H) BIST in progress due to AP cores being put into reset. When set, memories
associated with this group are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t csr : 1; /**< [ 4: 4](RO/H) BIST in progress due to access to RST_DEV_MAP(). When set, memories
associated with this access are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain BIST in progress. When set, memories associated with
the SCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain BIST in progress. When set, memories associated with
the MCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain BIST in progress. When set, memories associated with
the core domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t chip : 1; /**< [ 0: 0](RO/H) Chip BIST in progress. Always reads 0. */
#else /* Word 0 - Little Endian */
uint64_t chip : 1; /**< [ 0: 0](RO/H) Chip BIST in progress. Always reads 0. */
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain BIST in progress. When set, memories associated with
the core domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain BIST in progress. When set, memories associated with
the MCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain BIST in progress. When set, memories associated with
the SCP domain are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t csr : 1; /**< [ 4: 4](RO/H) BIST in progress due to access to RST_DEV_MAP(). When set, memories
associated with this access are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t ap : 1; /**< [ 5: 5](RO/H) BIST in progress due to AP cores being put into reset. When set, memories
associated with this group are being tested.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t reserved_6_63 : 58;
#endif /* Word 0 - End */
} cn96xxp3;
/* struct cavm_rst_bist_active_cn96xxp3 cn98xx; */
/* struct cavm_rst_bist_active_s cnf95xx; */
/* struct cavm_rst_bist_active_s loki; */
};
typedef union cavm_rst_bist_active cavm_rst_bist_active_t;
#define CAVM_RST_BIST_ACTIVE CAVM_RST_BIST_ACTIVE_FUNC()
static inline uint64_t CAVM_RST_BIST_ACTIVE_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_BIST_ACTIVE_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001890ll;
__cavm_csr_fatal("RST_BIST_ACTIVE", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_BIST_ACTIVE cavm_rst_bist_active_t
#define bustype_CAVM_RST_BIST_ACTIVE CSR_TYPE_RSL
#define basename_CAVM_RST_BIST_ACTIVE "RST_BIST_ACTIVE"
#define device_bar_CAVM_RST_BIST_ACTIVE 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_BIST_ACTIVE 0
#define arguments_CAVM_RST_BIST_ACTIVE -1,-1,-1,-1
/**
* Register (RSL) rst_bist_timer
*
* INTERNAL: RST BIST Timer Register
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_bist_timer
{
uint64_t u;
struct cavm_rst_bist_timer_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_29_63 : 35;
uint64_t count : 29; /**< [ 28: 0](RO) Number of 50 MHz reference clocks that have elapsed during BIST and repair during the last
reset.
If MSB is set the BIST chain did not complete as expected. */
#else /* Word 0 - Little Endian */
uint64_t count : 29; /**< [ 28: 0](RO) Number of 50 MHz reference clocks that have elapsed during BIST and repair during the last
reset.
If MSB is set the BIST chain did not complete as expected. */
uint64_t reserved_29_63 : 35;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_bist_timer_s cn8; */
struct cavm_rst_bist_timer_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_29_63 : 35;
uint64_t count : 29; /**< [ 28: 0](RO/H) Number of 100 MHz reference clocks that have elapsed during the
last BIST operation. If MSB is set the BIST did not
complete as expected. This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dll_stable. */
#else /* Word 0 - Little Endian */
uint64_t count : 29; /**< [ 28: 0](RO/H) Number of 100 MHz reference clocks that have elapsed during the
last BIST operation. If MSB is set the BIST did not
complete as expected. This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dll_stable. */
uint64_t reserved_29_63 : 35;
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_bist_timer cavm_rst_bist_timer_t;
#define CAVM_RST_BIST_TIMER CAVM_RST_BIST_TIMER_FUNC()
static inline uint64_t CAVM_RST_BIST_TIMER_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_BIST_TIMER_FUNC(void)
{
return 0x87e006001760ll;
}
#define typedef_CAVM_RST_BIST_TIMER cavm_rst_bist_timer_t
#define bustype_CAVM_RST_BIST_TIMER CSR_TYPE_RSL
#define basename_CAVM_RST_BIST_TIMER "RST_BIST_TIMER"
#define device_bar_CAVM_RST_BIST_TIMER 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_BIST_TIMER 0
#define arguments_CAVM_RST_BIST_TIMER -1,-1,-1,-1
/**
* Register (RSL) rst_boot
*
* RST Boot Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_boot
{
uint64_t u;
struct cavm_rst_boot_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
uint64_t reserved_61_62 : 2;
uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
strap GPIO_STRAP\<10\> are set. */
uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
RST_BOOT[CHIPKILL]=1. */
uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
uint64_t vrm_err : 1; /**< [ 57: 57](RO) Reserved. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
Software must write a one to this bit when the chain of trust is broken. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
allowed in the part.
This state persists across soft and warm resets.
Internal:
This state will persist across a simulation */
uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the SCP EJTAG interface (See EJTAGDIS).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
of MCP and SCP devices is routed directly to GPIO pins. When
cleared these devices are included in the standard JTAG chain.
The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
This field is reinitialized with a cold domain reset.
Reset value is determined by GPIO strap pin number
GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
uint64_t reserved_47_52 : 6;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
ref-clock speed should always be 50 MHz.
Internal:
[C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
pins and the smaller value is used. */
uint64_t reserved_39 : 1;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
The value ref-clock speed should always be 50 MHz.
Internal:
[PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
pins and the smaller value is used. */
uint64_t reserved_2_32 : 31;
uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
for the cold reset. */
#else /* Word 0 - Little Endian */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
for the cold reset. */
uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
uint64_t reserved_2_32 : 31;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
The value ref-clock speed should always be 50 MHz.
Internal:
[PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
pins and the smaller value is used. */
uint64_t reserved_39 : 1;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
ref-clock speed should always be 50 MHz.
Internal:
[C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
pins and the smaller value is used. */
uint64_t reserved_47_52 : 6;
uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
of MCP and SCP devices is routed directly to GPIO pins. When
cleared these devices are included in the standard JTAG chain.
The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
This field is reinitialized with a cold domain reset.
Reset value is determined by GPIO strap pin number
GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the SCP EJTAG interface (See EJTAGDIS).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
allowed in the part.
This state persists across soft and warm resets.
Internal:
This state will persist across a simulation */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
Software must write a one to this bit when the chain of trust is broken. */
uint64_t vrm_err : 1; /**< [ 57: 57](RO) Reserved. */
uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
RST_BOOT[CHIPKILL]=1. */
uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
strap GPIO_STRAP\<10\> are set. */
uint64_t reserved_61_62 : 2;
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
#endif /* Word 0 - End */
} s;
struct cavm_rst_boot_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
in trusted-mode, else 0. */
uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
strap GPIO_STRAP\<10\> are set. */
uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
RST_BOOT[CHIPKILL]=1. */
uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
uint64_t vrm_err : 1; /**< [ 57: 57](RO) Reserved. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
Software must write a one to this bit when the chain of trust is broken. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
allowed in the part.
This state persists across soft and warm resets.
Internal:
This state will persist across a simulation */
uint64_t reserved_47_54 : 8;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
ref-clock speed should always be 50 MHz.
Internal:
[C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
pins and the smaller value is used. */
uint64_t reserved_39 : 1;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
The value ref-clock speed should always be 50 MHz.
Internal:
[PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
pins and the smaller value is used. */
uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Reserved.
Internal:
Last boot cause mask for CCPI; resets only with PLL_DC_OK.
\<32\> = Warm reset due to CCPI link 2 going down.
\<31\> = Warm reset due to CCPI link 1 going down.
\<30\> = Warm reset due to CCPI link 0 going down. */
uint64_t lboot_pf_flr : 4; /**< [ 29: 26](R/W1C/H) Last boot cause was caused by a PF Function Level Reset event.
\<29\> = Warm reset due to PF FLR on PEM3.
\<28\> = Warm reset due to PF FLR on PEM2.
\<27\> = Warm reset due to PF FLR on PEM1.
\<26\> = Warm reset due to PF FLR on PEM0. */
uint64_t lboot_ckill : 1; /**< [ 25: 25](R/W1C/H) Last boot cause was chip kill timer expiring. See RST_BOOT[CHIPKILL]. */
uint64_t lboot_jtg : 1; /**< [ 24: 24](R/W1C/H) Last boot cause was write to JTG reset. */
uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Reserved. */
uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM2; resets only with PLL_DC_OK.
\<17\> = Reserved
\<16\> = Warm reset due to Cntl2 link-down or hot-reset.
\<15\> = Reserved
\<14\> = Cntl2 reset due to PERST2_L pin.
\<13\> = Reserved
\<12\> = Warm reset due to PERST2_L pin. */
uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
\<11\> = Soft reset due to watchdog.
\<10\> = Soft reset due to RST_SOFT_RST write.
\<9\> = Warm reset due to Cntl1 link-down or hot-reset.
\<8\> = Warm reset due to Cntl0 link-down or hot-reset.
\<7\> = Cntl1 reset due to PERST1_L pin.
\<6\> = Cntl0 reset due to PERST0_L pin.
\<5\> = Warm reset due to PERST1_L pin.
\<4\> = Warm reset due to PERST0_L pin.
\<3\> = Warm reset due to CHIP_RESET_L pin.
\<2\> = Cold reset due to PLL_DC_OK pin. */
uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
for the cold reset. */
#else /* Word 0 - Little Endian */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
for the cold reset. */
uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
\<11\> = Soft reset due to watchdog.
\<10\> = Soft reset due to RST_SOFT_RST write.
\<9\> = Warm reset due to Cntl1 link-down or hot-reset.
\<8\> = Warm reset due to Cntl0 link-down or hot-reset.
\<7\> = Cntl1 reset due to PERST1_L pin.
\<6\> = Cntl0 reset due to PERST0_L pin.
\<5\> = Warm reset due to PERST1_L pin.
\<4\> = Warm reset due to PERST0_L pin.
\<3\> = Warm reset due to CHIP_RESET_L pin.
\<2\> = Cold reset due to PLL_DC_OK pin. */
uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM2; resets only with PLL_DC_OK.
\<17\> = Reserved
\<16\> = Warm reset due to Cntl2 link-down or hot-reset.
\<15\> = Reserved
\<14\> = Cntl2 reset due to PERST2_L pin.
\<13\> = Reserved
\<12\> = Warm reset due to PERST2_L pin. */
uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Reserved. */
uint64_t lboot_jtg : 1; /**< [ 24: 24](R/W1C/H) Last boot cause was write to JTG reset. */
uint64_t lboot_ckill : 1; /**< [ 25: 25](R/W1C/H) Last boot cause was chip kill timer expiring. See RST_BOOT[CHIPKILL]. */
uint64_t lboot_pf_flr : 4; /**< [ 29: 26](R/W1C/H) Last boot cause was caused by a PF Function Level Reset event.
\<29\> = Warm reset due to PF FLR on PEM3.
\<28\> = Warm reset due to PF FLR on PEM2.
\<27\> = Warm reset due to PF FLR on PEM1.
\<26\> = Warm reset due to PF FLR on PEM0. */
uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Reserved.
Internal:
Last boot cause mask for CCPI; resets only with PLL_DC_OK.
\<32\> = Warm reset due to CCPI link 2 going down.
\<31\> = Warm reset due to CCPI link 1 going down.
\<30\> = Warm reset due to CCPI link 0 going down. */
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
The value ref-clock speed should always be 50 MHz.
Internal:
[PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
pins and the smaller value is used. */
uint64_t reserved_39 : 1;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
ref-clock speed should always be 50 MHz.
Internal:
[C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
pins and the smaller value is used. */
uint64_t reserved_47_54 : 8;
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
allowed in the part.
This state persists across soft and warm resets.
Internal:
This state will persist across a simulation */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
Software must write a one to this bit when the chain of trust is broken. */
uint64_t vrm_err : 1; /**< [ 57: 57](RO) Reserved. */
uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
RST_BOOT[CHIPKILL]=1. */
uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
strap GPIO_STRAP\<10\> are set. */
uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
in trusted-mode, else 0. */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_boot_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
in trusted-mode, else 0. */
uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
strap GPIO_STRAP\<10\> are set. */
uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
RST_BOOT[CHIPKILL]=1. */
uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
uint64_t vrm_err : 1; /**< [ 57: 57](RO) Reserved. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
Software must write a one to this bit when the chain of trust is broken. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
allowed in the part.
This state persists across soft and warm resets.
Internal:
This state will persist across a simulation */
uint64_t reserved_47_54 : 8;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
ref-clock speed should always be 50 MHz.
Internal:
[C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
pins and the smaller value is used. */
uint64_t reserved_39 : 1;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
The value ref-clock speed should always be 50 MHz.
Internal:
[PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
pins and the smaller value is used. */
uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Reserved.
Internal:
Last boot cause mask for CCPI; resets only with PLL_DC_OK.
\<32\> = Warm reset due to CCPI link 2 going down.
\<31\> = Warm reset due to CCPI link 1 going down.
\<30\> = Warm reset due to CCPI link 0 going down. */
uint64_t reserved_26_29 : 4;
uint64_t lboot_ckill : 1; /**< [ 25: 25](R/W1C/H) Last boot cause was chip kill timer expiring. See RST_BOOT[CHIPKILL]. */
uint64_t lboot_jtg : 1; /**< [ 24: 24](R/W1C/H) Last boot cause was write to JTG reset. */
uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Reserved. */
uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM2; resets only with PLL_DC_OK.
\<17\> = Reserved
\<16\> = Warm reset due to Cntl2 link-down or hot-reset.
\<15\> = Reserved
\<14\> = Cntl2 reset due to PERST2_L pin.
\<13\> = Reserved
\<12\> = Warm reset due to PERST2_L pin. */
uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
\<11\> = Soft reset due to watchdog.
\<10\> = Soft reset due to RST_SOFT_RST write.
\<9\> = Warm reset due to Cntl1 link-down or hot-reset.
\<8\> = Warm reset due to Cntl0 link-down or hot-reset.
\<7\> = Cntl1 reset due to PERST1_L pin.
\<6\> = Cntl0 reset due to PERST0_L pin.
\<5\> = Warm reset due to PERST1_L pin.
\<4\> = Warm reset due to PERST0_L pin.
\<3\> = Warm reset due to CHIP_RESET_L pin.
\<2\> = Cold reset due to PLL_DC_OK pin. */
uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
for the cold reset. */
#else /* Word 0 - Little Endian */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
for the cold reset. */
uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
\<11\> = Soft reset due to watchdog.
\<10\> = Soft reset due to RST_SOFT_RST write.
\<9\> = Warm reset due to Cntl1 link-down or hot-reset.
\<8\> = Warm reset due to Cntl0 link-down or hot-reset.
\<7\> = Cntl1 reset due to PERST1_L pin.
\<6\> = Cntl0 reset due to PERST0_L pin.
\<5\> = Warm reset due to PERST1_L pin.
\<4\> = Warm reset due to PERST0_L pin.
\<3\> = Warm reset due to CHIP_RESET_L pin.
\<2\> = Cold reset due to PLL_DC_OK pin. */
uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM2; resets only with PLL_DC_OK.
\<17\> = Reserved
\<16\> = Warm reset due to Cntl2 link-down or hot-reset.
\<15\> = Reserved
\<14\> = Cntl2 reset due to PERST2_L pin.
\<13\> = Reserved
\<12\> = Warm reset due to PERST2_L pin. */
uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Reserved. */
uint64_t lboot_jtg : 1; /**< [ 24: 24](R/W1C/H) Last boot cause was write to JTG reset. */
uint64_t lboot_ckill : 1; /**< [ 25: 25](R/W1C/H) Last boot cause was chip kill timer expiring. See RST_BOOT[CHIPKILL]. */
uint64_t reserved_26_29 : 4;
uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Reserved.
Internal:
Last boot cause mask for CCPI; resets only with PLL_DC_OK.
\<32\> = Warm reset due to CCPI link 2 going down.
\<31\> = Warm reset due to CCPI link 1 going down.
\<30\> = Warm reset due to CCPI link 0 going down. */
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
The value ref-clock speed should always be 50 MHz.
Internal:
[PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
pins and the smaller value is used. */
uint64_t reserved_39 : 1;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
ref-clock speed should always be 50 MHz.
Internal:
[C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
pins and the smaller value is used. */
uint64_t reserved_47_54 : 8;
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
allowed in the part.
This state persists across soft and warm resets.
Internal:
This state will persist across a simulation */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
Software must write a one to this bit when the chain of trust is broken. */
uint64_t vrm_err : 1; /**< [ 57: 57](RO) Reserved. */
uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
RST_BOOT[CHIPKILL]=1. */
uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
strap GPIO_STRAP\<10\> are set. */
uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
in trusted-mode, else 0. */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
#endif /* Word 0 - End */
} cn81xx;
struct cavm_rst_boot_cn83xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
in trusted-mode, else 0. */
uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
strap GPIO_STRAP\<10\> are set. */
uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
RST_BOOT[CHIPKILL]=1. */
uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
uint64_t vrm_err : 1; /**< [ 57: 57](RO) VRM error. VRM did not complete operations within 5.25ms of PLL_DC_OK being
asserted. PLLs were released automatically. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
Software must write a one to this bit when the chain of trust is broken. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
allowed in the part.
This state persists across soft and warm resets.
Internal:
This state will persist across a simulation */
uint64_t reserved_47_54 : 8;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
ref-clock speed should always be 50 MHz.
Internal:
[C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
pins and the smaller value is used. */
uint64_t reserved_39 : 1;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
The value ref-clock speed should always be 50 MHz.
Internal:
[PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
pins and the smaller value is used. */
uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Reserved.
Internal:
Last boot cause mask for CCPI; resets only with PLL_DC_OK.
\<32\> = Warm reset due to CCPI link 2 going down.
\<31\> = Warm reset due to CCPI link 1 going down.
\<30\> = Warm reset due to CCPI link 0 going down. */
uint64_t lboot_pf_flr : 4; /**< [ 29: 26](R/W1C/H) Last boot cause was caused by a PF Function Level Reset event.
\<29\> = Warm reset due to PF FLR on PEM3.
\<28\> = Warm reset due to PF FLR on PEM2.
\<27\> = Warm reset due to PF FLR on PEM1.
\<26\> = Warm reset due to PF FLR on PEM0. */
uint64_t lboot_ckill : 1; /**< [ 25: 25](R/W1C/H) Last boot cause was chip kill timer expiring. See RST_BOOT[CHIPKILL]. */
uint64_t lboot_jtg : 1; /**< [ 24: 24](R/W1C/H) Last boot cause was write to JTG reset. */
uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Reserved. */
uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM3 and PEM2; resets only with PLL_DC_OK.
\<17\> = Warm reset due to Cntl3 link-down or hot-reset.
\<16\> = Warm reset due to Cntl2 link-down or hot-reset.
\<15\> = Cntl3 reset due to PERST3_L pin.
\<14\> = Cntl2 reset due to PERST2_L pin.
\<13\> = Warm reset due to PERST3_L pin.
\<12\> = Warm reset due to PERST2_L pin. */
uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
\<11\> = Soft reset due to watchdog.
\<10\> = Soft reset due to RST_SOFT_RST write.
\<9\> = Warm reset due to Cntl1 link-down or hot-reset.
\<8\> = Warm reset due to Cntl0 link-down or hot-reset.
\<7\> = Cntl1 reset due to PERST1_L pin.
\<6\> = Cntl0 reset due to PERST0_L pin.
\<5\> = Warm reset due to PERST1_L pin.
\<4\> = Warm reset due to PERST0_L pin.
\<3\> = Warm reset due to CHIP_RESET_L pin.
\<2\> = Cold reset due to PLL_DC_OK pin. */
uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
for the cold reset. */
#else /* Word 0 - Little Endian */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
for the cold reset. */
uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
\<11\> = Soft reset due to watchdog.
\<10\> = Soft reset due to RST_SOFT_RST write.
\<9\> = Warm reset due to Cntl1 link-down or hot-reset.
\<8\> = Warm reset due to Cntl0 link-down or hot-reset.
\<7\> = Cntl1 reset due to PERST1_L pin.
\<6\> = Cntl0 reset due to PERST0_L pin.
\<5\> = Warm reset due to PERST1_L pin.
\<4\> = Warm reset due to PERST0_L pin.
\<3\> = Warm reset due to CHIP_RESET_L pin.
\<2\> = Cold reset due to PLL_DC_OK pin. */
uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM3 and PEM2; resets only with PLL_DC_OK.
\<17\> = Warm reset due to Cntl3 link-down or hot-reset.
\<16\> = Warm reset due to Cntl2 link-down or hot-reset.
\<15\> = Cntl3 reset due to PERST3_L pin.
\<14\> = Cntl2 reset due to PERST2_L pin.
\<13\> = Warm reset due to PERST3_L pin.
\<12\> = Warm reset due to PERST2_L pin. */
uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Reserved. */
uint64_t lboot_jtg : 1; /**< [ 24: 24](R/W1C/H) Last boot cause was write to JTG reset. */
uint64_t lboot_ckill : 1; /**< [ 25: 25](R/W1C/H) Last boot cause was chip kill timer expiring. See RST_BOOT[CHIPKILL]. */
uint64_t lboot_pf_flr : 4; /**< [ 29: 26](R/W1C/H) Last boot cause was caused by a PF Function Level Reset event.
\<29\> = Warm reset due to PF FLR on PEM3.
\<28\> = Warm reset due to PF FLR on PEM2.
\<27\> = Warm reset due to PF FLR on PEM1.
\<26\> = Warm reset due to PF FLR on PEM0. */
uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Reserved.
Internal:
Last boot cause mask for CCPI; resets only with PLL_DC_OK.
\<32\> = Warm reset due to CCPI link 2 going down.
\<31\> = Warm reset due to CCPI link 1 going down.
\<30\> = Warm reset due to CCPI link 0 going down. */
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
The value ref-clock speed should always be 50 MHz.
Internal:
[PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
pins and the smaller value is used. */
uint64_t reserved_39 : 1;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
ref-clock speed should always be 50 MHz.
Internal:
[C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
pins and the smaller value is used. */
uint64_t reserved_47_54 : 8;
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
allowed in the part.
This state persists across soft and warm resets.
Internal:
This state will persist across a simulation */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
Software must write a one to this bit when the chain of trust is broken. */
uint64_t vrm_err : 1; /**< [ 57: 57](RO) VRM error. VRM did not complete operations within 5.25ms of PLL_DC_OK being
asserted. PLLs were released automatically. */
uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
RST_BOOT[CHIPKILL]=1. */
uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
strap GPIO_STRAP\<10\> are set. */
uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
in trusted-mode, else 0. */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
#endif /* Word 0 - End */
} cn83xx;
struct cavm_rst_boot_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A zero-to-one transition of CHIPKILL starts the CHIPKILL timer. When set and the timer
expires, chip domain reset is asserted.
The length of the CHIPKILL timer is specified by RST_CKILL[TIMER].
This feature is effectively a delayed reset.
This field is reinitialized with a chip domain reset. */
uint64_t jtagdis : 1; /**< [ 62: 62](R/W/H) JTAG access disable. When set, the debug access port of the
JTAG TAP controller will be disabled, i.e. DAP_IMP_DAR will be zero.
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t scp_jtagdis : 1; /**< [ 61: 61](R/W/H) SCP JTAG debugger disable. When set, the SCP debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the MCP EJTAG interface (See [MCP_JTAGDIS]).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t trusted_mode : 1; /**< [ 60: 60](RO/H) When set, chip is operating as a trusted device. This bit is asserted when
either FUSF_CTL[TZ_FORCE2], or the trusted mode strap on GPIO number
GPIO_STRAP_PIN_E::TRUSTED_MODE is set. */
uint64_t reserved_58_59 : 2;
uint64_t vrm_err : 1; /**< [ 57: 57](R/W1) Reserved. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set, FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to one if FUSF_CTL[FJ_DIS_HUK] is set and not in trusted mode.
It is also set anytime scan mode is activated while FUSF_CTL[FJ_DIS_HUK] is set.
Software must set this bit when the chain of trust is broken.
This field is reinitialized with either a cold or chip domain reset. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S/H) Disable scan. When set and FUSF_CTL[ROT_LCK] = 1, scan is not
allowed in the part. Read requests return current disable scan status.
Internal:
The field is actually reset only after DCOK has been left
deasserted for an extended period of time. */
uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the SCP EJTAG interface (See EJTAGDIS).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
of MCP and SCP devices is routed directly to GPIO pins. When
cleared these devices are included in the standard JTAG chain.
The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
This field is reinitialized with a cold domain reset.
Reset value is determined by GPIO strap pin number
GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
uint64_t reserved_47_52 : 6;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Current core-clock multiplier. Clock frequency = [C_MUL] * 50 MHz.
See RST_CORE_PLL for details on programming and initial values.
Internal:
[C_MUL] is a copy of RST_CORE_PLL[CUR_MUL]. */
uint64_t reserved_39 : 1;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Current coprocessor-clock multiplier. Clock frequency = [PNR_MUL] * 50 MHz.
See RST_PNR_PLL for details on programming and initial values.
Internal:
[PNR_MUL] is a copy of RST_PNR_PLL[CUR_MUL]. */
uint64_t reserved_31_32 : 2;
uint64_t cpt_mul : 7; /**< [ 30: 24](RO/H) Current crypto-clock multiplier. Clock frequency = [CPT_MUL] * 50 MHz.
See RST_CPT_PLL for details on programming and initial values.
Internal:
[CPT_MUL] is a copy of RST_CPT_PLL[CUR_MUL]. */
uint64_t reserved_2_23 : 22;
uint64_t rboot : 1; /**< [ 1: 1](R/W/H) Remote boot. If set, indicates that SCP will require a write to
RST_SCP_DOMAIN_W1C to bring it out of reset. Otherwise it
will automatically come out of reset once the reset source has
been deasserted.
The initial value is set when [RBOOT_PIN] is true and
trustzone has not been enabled.
This field is reinitialized with a cold domain reset.
Internal:
This field is cleared when jtg__rst_disable_remote is active. */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO) Remote boot strap. The value is set when primary boot method is RST_BOOT_METHOD_E::REMOTE
when the GPIO pins are sampled on the rising edge of PLL_DCOK. */
#else /* Word 0 - Little Endian */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO) Remote boot strap. The value is set when primary boot method is RST_BOOT_METHOD_E::REMOTE
when the GPIO pins are sampled on the rising edge of PLL_DCOK. */
uint64_t rboot : 1; /**< [ 1: 1](R/W/H) Remote boot. If set, indicates that SCP will require a write to
RST_SCP_DOMAIN_W1C to bring it out of reset. Otherwise it
will automatically come out of reset once the reset source has
been deasserted.
The initial value is set when [RBOOT_PIN] is true and
trustzone has not been enabled.
This field is reinitialized with a cold domain reset.
Internal:
This field is cleared when jtg__rst_disable_remote is active. */
uint64_t reserved_2_23 : 22;
uint64_t cpt_mul : 7; /**< [ 30: 24](RO/H) Current crypto-clock multiplier. Clock frequency = [CPT_MUL] * 50 MHz.
See RST_CPT_PLL for details on programming and initial values.
Internal:
[CPT_MUL] is a copy of RST_CPT_PLL[CUR_MUL]. */
uint64_t reserved_31_32 : 2;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Current coprocessor-clock multiplier. Clock frequency = [PNR_MUL] * 50 MHz.
See RST_PNR_PLL for details on programming and initial values.
Internal:
[PNR_MUL] is a copy of RST_PNR_PLL[CUR_MUL]. */
uint64_t reserved_39 : 1;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Current core-clock multiplier. Clock frequency = [C_MUL] * 50 MHz.
See RST_CORE_PLL for details on programming and initial values.
Internal:
[C_MUL] is a copy of RST_CORE_PLL[CUR_MUL]. */
uint64_t reserved_47_52 : 6;
uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
of MCP and SCP devices is routed directly to GPIO pins. When
cleared these devices are included in the standard JTAG chain.
The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
This field is reinitialized with a cold domain reset.
Reset value is determined by GPIO strap pin number
GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the SCP EJTAG interface (See EJTAGDIS).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S/H) Disable scan. When set and FUSF_CTL[ROT_LCK] = 1, scan is not
allowed in the part. Read requests return current disable scan status.
Internal:
The field is actually reset only after DCOK has been left
deasserted for an extended period of time. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set, FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to one if FUSF_CTL[FJ_DIS_HUK] is set and not in trusted mode.
It is also set anytime scan mode is activated while FUSF_CTL[FJ_DIS_HUK] is set.
Software must set this bit when the chain of trust is broken.
This field is reinitialized with either a cold or chip domain reset. */
uint64_t vrm_err : 1; /**< [ 57: 57](R/W1) Reserved. */
uint64_t reserved_58_59 : 2;
uint64_t trusted_mode : 1; /**< [ 60: 60](RO/H) When set, chip is operating as a trusted device. This bit is asserted when
either FUSF_CTL[TZ_FORCE2], or the trusted mode strap on GPIO number
GPIO_STRAP_PIN_E::TRUSTED_MODE is set. */
uint64_t scp_jtagdis : 1; /**< [ 61: 61](R/W/H) SCP JTAG debugger disable. When set, the SCP debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the MCP EJTAG interface (See [MCP_JTAGDIS]).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t jtagdis : 1; /**< [ 62: 62](R/W/H) JTAG access disable. When set, the debug access port of the
JTAG TAP controller will be disabled, i.e. DAP_IMP_DAR will be zero.
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A zero-to-one transition of CHIPKILL starts the CHIPKILL timer. When set and the timer
expires, chip domain reset is asserted.
The length of the CHIPKILL timer is specified by RST_CKILL[TIMER].
This feature is effectively a delayed reset.
This field is reinitialized with a chip domain reset. */
#endif /* Word 0 - End */
} cn9;
/* struct cavm_rst_boot_cn9 cn96xx; */
struct cavm_rst_boot_cn98xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A zero-to-one transition of CHIPKILL starts the CHIPKILL timer. When set and the timer
expires, chip domain reset is asserted.
The length of the CHIPKILL timer is specified by RST_CKILL[TIMER].
This feature is effectively a delayed reset.
This field is reinitialized with a chip domain reset. */
uint64_t jtagdis : 1; /**< [ 62: 62](R/W/H) JTAG access disable. When set, the debug access port of the
JTAG TAP controller will be disabled, i.e. DAP_IMP_DAR will be zero.
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t scp_jtagdis : 1; /**< [ 61: 61](R/W/H) SCP JTAG debugger disable. When set, the SCP debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the MCP EJTAG interface (See [MCP_JTAGDIS]).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t trusted_mode : 1; /**< [ 60: 60](RO/H) When set, chip is operating as a trusted device. This bit is asserted when
either FUSF_CTL[TZ_FORCE2], or the trusted mode strap on GPIO number
GPIO_STRAP_PIN_E::TRUSTED_MODE is set. */
uint64_t reserved_58_59 : 2;
uint64_t vrm_err : 1; /**< [ 57: 57](R/W1) Reserved. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set, FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to one if FUSF_CTL[FJ_DIS_HUK] is set and not in trusted mode.
It is also set anytime scan mode is activated while FUSF_CTL[FJ_DIS_HUK] is set.
Software must set this bit when the chain of trust is broken.
This field is reinitialized with either a cold or chip domain reset. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S/H) Disable scan. When set and FUSF_CTL[ROT_LCK] = 1, scan is not
allowed in the part. Read requests return current disable scan status.
Internal:
The field is actually reset only after DCOK has been left
deasserted for an extended period of time. */
uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the SCP EJTAG interface (See EJTAGDIS).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
of MCP and SCP devices is routed directly to GPIO pins. When
cleared these devices are included in the standard JTAG chain.
The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
This field is reinitialized with a cold domain reset.
Reset value is determined by GPIO strap pin number
GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
uint64_t reserved_47_52 : 6;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Current core-clock multiplier. Clock frequency = [C_MUL] * 50 MHz.
See RST_CORE_PLL for details on programming and initial values.
Internal:
[C_MUL] is a copy of RST_CORE_PLL[CUR_MUL]. */
uint64_t reserved_39 : 1;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Current coprocessor-clock multiplier. Clock frequency = [PNR_MUL] * 50 MHz.
See RST_PNR_PLL for details on programming and initial values.
Internal:
[PNR_MUL] is a copy of RST_PNR_PLL[CUR_MUL]. */
uint64_t reserved_31_32 : 2;
uint64_t cpt_mul : 7; /**< [ 30: 24](RO/H) Current crypto-clock multiplier for CPT0. Clock frequency = [CPT_MUL] * 50 MHz.
See RST_CPT_PLL for details on programming and initial values.
Internal:
[CPT_MUL] is a copy of RST_CPT_PLL[CUR_MUL]. */
uint64_t reserved_23 : 1;
uint64_t cpt1_mul : 7; /**< [ 22: 16](RO/H) Current crypto-clock multiplier for CPT1. Clock frequency = [CPT1_MUL] * 50 MHz.
See RST_CPT1_PLL for details on programming and initial values.
Internal:
[CPT1_MUL] is a copy of RST_CPT1_PLL[CUR_MUL]. */
uint64_t reserved_15 : 1;
uint64_t rxp_mul : 7; /**< [ 14: 8](RO/H) Current RXP clock multiplier. Clock frequency = [RXP_MUL] * 50 MHz.
See RST_RXP_PLL for details on programming and initial values.
Internal:
[RXP_MUL] is a copy of RST_RXP_PLL[CUR_MUL]. */
uint64_t reserved_2_7 : 6;
uint64_t rboot : 1; /**< [ 1: 1](R/W/H) Remote boot. If set, indicates that SCP will require a write to
RST_SCP_DOMAIN_W1C to bring it out of reset. Otherwise it
will automatically come out of reset once the reset source has
been deasserted.
The initial value is set when [RBOOT_PIN] is true and
trustzone has not been enabled.
This field is reinitialized with a cold domain reset.
Internal:
This field is cleared when jtg__rst_disable_remote is active. */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO) Remote boot strap. The value is set when primary boot method is RST_BOOT_METHOD_E::REMOTE
when the GPIO pins are sampled on the rising edge of PLL_DCOK. */
#else /* Word 0 - Little Endian */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO) Remote boot strap. The value is set when primary boot method is RST_BOOT_METHOD_E::REMOTE
when the GPIO pins are sampled on the rising edge of PLL_DCOK. */
uint64_t rboot : 1; /**< [ 1: 1](R/W/H) Remote boot. If set, indicates that SCP will require a write to
RST_SCP_DOMAIN_W1C to bring it out of reset. Otherwise it
will automatically come out of reset once the reset source has
been deasserted.
The initial value is set when [RBOOT_PIN] is true and
trustzone has not been enabled.
This field is reinitialized with a cold domain reset.
Internal:
This field is cleared when jtg__rst_disable_remote is active. */
uint64_t reserved_2_7 : 6;
uint64_t rxp_mul : 7; /**< [ 14: 8](RO/H) Current RXP clock multiplier. Clock frequency = [RXP_MUL] * 50 MHz.
See RST_RXP_PLL for details on programming and initial values.
Internal:
[RXP_MUL] is a copy of RST_RXP_PLL[CUR_MUL]. */
uint64_t reserved_15 : 1;
uint64_t cpt1_mul : 7; /**< [ 22: 16](RO/H) Current crypto-clock multiplier for CPT1. Clock frequency = [CPT1_MUL] * 50 MHz.
See RST_CPT1_PLL for details on programming and initial values.
Internal:
[CPT1_MUL] is a copy of RST_CPT1_PLL[CUR_MUL]. */
uint64_t reserved_23 : 1;
uint64_t cpt_mul : 7; /**< [ 30: 24](RO/H) Current crypto-clock multiplier for CPT0. Clock frequency = [CPT_MUL] * 50 MHz.
See RST_CPT_PLL for details on programming and initial values.
Internal:
[CPT_MUL] is a copy of RST_CPT_PLL[CUR_MUL]. */
uint64_t reserved_31_32 : 2;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Current coprocessor-clock multiplier. Clock frequency = [PNR_MUL] * 50 MHz.
See RST_PNR_PLL for details on programming and initial values.
Internal:
[PNR_MUL] is a copy of RST_PNR_PLL[CUR_MUL]. */
uint64_t reserved_39 : 1;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Current core-clock multiplier. Clock frequency = [C_MUL] * 50 MHz.
See RST_CORE_PLL for details on programming and initial values.
Internal:
[C_MUL] is a copy of RST_CORE_PLL[CUR_MUL]. */
uint64_t reserved_47_52 : 6;
uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
of MCP and SCP devices is routed directly to GPIO pins. When
cleared these devices are included in the standard JTAG chain.
The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
This field is reinitialized with a cold domain reset.
Reset value is determined by GPIO strap pin number
GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the SCP EJTAG interface (See EJTAGDIS).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S/H) Disable scan. When set and FUSF_CTL[ROT_LCK] = 1, scan is not
allowed in the part. Read requests return current disable scan status.
Internal:
The field is actually reset only after DCOK has been left
deasserted for an extended period of time. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set, FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to one if FUSF_CTL[FJ_DIS_HUK] is set and not in trusted mode.
It is also set anytime scan mode is activated while FUSF_CTL[FJ_DIS_HUK] is set.
Software must set this bit when the chain of trust is broken.
This field is reinitialized with either a cold or chip domain reset. */
uint64_t vrm_err : 1; /**< [ 57: 57](R/W1) Reserved. */
uint64_t reserved_58_59 : 2;
uint64_t trusted_mode : 1; /**< [ 60: 60](RO/H) When set, chip is operating as a trusted device. This bit is asserted when
either FUSF_CTL[TZ_FORCE2], or the trusted mode strap on GPIO number
GPIO_STRAP_PIN_E::TRUSTED_MODE is set. */
uint64_t scp_jtagdis : 1; /**< [ 61: 61](R/W/H) SCP JTAG debugger disable. When set, the SCP debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the MCP EJTAG interface (See [MCP_JTAGDIS]).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t jtagdis : 1; /**< [ 62: 62](R/W/H) JTAG access disable. When set, the debug access port of the
JTAG TAP controller will be disabled, i.e. DAP_IMP_DAR will be zero.
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A zero-to-one transition of CHIPKILL starts the CHIPKILL timer. When set and the timer
expires, chip domain reset is asserted.
The length of the CHIPKILL timer is specified by RST_CKILL[TIMER].
This feature is effectively a delayed reset.
This field is reinitialized with a chip domain reset. */
#endif /* Word 0 - End */
} cn98xx;
struct cavm_rst_boot_cnf95xxp1
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A zero-to-one transition of CHIPKILL starts the CHIPKILL timer. When set and the timer
expires, chip domain reset is asserted.
The length of the CHIPKILL timer is specified by RST_CKILL[TIMER].
This feature is effectively a delayed reset.
This field is reinitialized with a chip domain reset. */
uint64_t jtagdis : 1; /**< [ 62: 62](R/W/H) JTAG access disable. When set, the debug access port of the
JTAG TAP controller will be disabled, i.e. DAP_IMP_DAR will be zero.
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t scp_jtagdis : 1; /**< [ 61: 61](R/W/H) SCP JTAG debugger disable. When set, the SCP debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the MCP EJTAG interface (See [MCP_JTAGDIS]).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t trusted_mode : 1; /**< [ 60: 60](RO/H) When set, chip is operating as a trusted device. This bit is asserted when
either FUSF_CTL[TZ_FORCE2], or the trusted mode strap on GPIO number
GPIO_STRAP_PIN_E::TRUSTED_MODE is set. */
uint64_t reserved_58_59 : 2;
uint64_t vrm_err : 1; /**< [ 57: 57](R/W1) Reserved. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set, FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to one if FUSF_CTL[FJ_DIS_HUK] is set and not in trusted mode.
It is also set anytime scan mode is activated while FUSF_CTL[FJ_DIS_HUK] is set.
Software must set this bit when the chain of trust is broken.
This field is reinitialized with either a cold or chip domain reset. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S/H) Disable scan. When set and FUSF_CTL[ROT_LCK] = 1, scan is not
allowed in the part. Read requests return current disable scan status.
Internal:
The field is actually reset only after DCOK has been left
deasserted for an extended period of time. */
uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the SCP EJTAG interface (See EJTAGDIS).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
of MCP and SCP devices is routed directly to GPIO pins. When
cleared these devices are included in the standard JTAG chain.
The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
This field is reinitialized with a cold domain reset.
Reset value is determined by GPIO strap pin number
GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
uint64_t reserved_47_52 : 6;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Current core-clock multiplier. Clock frequency = [C_MUL] * 50 MHz.
See RST_CORE_PLL for details on programming and initial values.
Internal:
[C_MUL] is a copy of RST_CORE_PLL[CUR_MUL]. */
uint64_t reserved_39 : 1;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Current coprocessor-clock multiplier. Clock frequency = [PNR_MUL] * 50 MHz.
See RST_PNR_PLL for details on programming and initial values.
Internal:
[PNR_MUL] is a copy of RST_PNR_PLL[CUR_MUL]. */
uint64_t reserved_31_32 : 2;
uint64_t cpt_mul : 7; /**< [ 30: 24](RO/H) Reserved.
Internal:
Unused on 95xx. */
uint64_t reserved_23 : 1;
uint64_t dsp_mul : 7; /**< [ 22: 16](RO/H) Current dsp-clock multiplier. Clock frequency = [DSP_MUL] * 50 MHz.
See RST_DSP_PLL for details on programming and initial values.
Internal:
[DSP_MUL] is a copy of RST_DSP_PLL[CUR_MUL]. */
uint64_t reserved_15 : 1;
uint64_t bphy_mul : 7; /**< [ 14: 8](RO/H) Current bphy-clock multiplier. Clock frequency = [BPHY_MUL] * 50 MHz.
See RST_BPHY_PLL for details on programming and initial values.
Internal:
[BPHY_MUL] is a copy of RST_BPHY_PLL[CUR_MUL]. */
uint64_t reserved_2_7 : 6;
uint64_t rboot : 1; /**< [ 1: 1](R/W/H) Remote boot. If set, indicates that SCP will require a write to
RST_SCP_DOMAIN_W1C to bring it out of reset. Otherwise it
will automatically come out of reset once the reset source has
been deasserted.
The initial value is set when [RBOOT_PIN] is true and
trustzone has not been enabled.
This field is reinitialized with a cold domain reset.
Internal:
This field is cleared when jtg__rst_disable_remote is active. */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO) Remote boot strap. The value is set when primary boot method is RST_BOOT_METHOD_E::REMOTE
when the GPIO pins are sampled on the rising edge of PLL_DCOK. */
#else /* Word 0 - Little Endian */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO) Remote boot strap. The value is set when primary boot method is RST_BOOT_METHOD_E::REMOTE
when the GPIO pins are sampled on the rising edge of PLL_DCOK. */
uint64_t rboot : 1; /**< [ 1: 1](R/W/H) Remote boot. If set, indicates that SCP will require a write to
RST_SCP_DOMAIN_W1C to bring it out of reset. Otherwise it
will automatically come out of reset once the reset source has
been deasserted.
The initial value is set when [RBOOT_PIN] is true and
trustzone has not been enabled.
This field is reinitialized with a cold domain reset.
Internal:
This field is cleared when jtg__rst_disable_remote is active. */
uint64_t reserved_2_7 : 6;
uint64_t bphy_mul : 7; /**< [ 14: 8](RO/H) Current bphy-clock multiplier. Clock frequency = [BPHY_MUL] * 50 MHz.
See RST_BPHY_PLL for details on programming and initial values.
Internal:
[BPHY_MUL] is a copy of RST_BPHY_PLL[CUR_MUL]. */
uint64_t reserved_15 : 1;
uint64_t dsp_mul : 7; /**< [ 22: 16](RO/H) Current dsp-clock multiplier. Clock frequency = [DSP_MUL] * 50 MHz.
See RST_DSP_PLL for details on programming and initial values.
Internal:
[DSP_MUL] is a copy of RST_DSP_PLL[CUR_MUL]. */
uint64_t reserved_23 : 1;
uint64_t cpt_mul : 7; /**< [ 30: 24](RO/H) Reserved.
Internal:
Unused on 95xx. */
uint64_t reserved_31_32 : 2;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Current coprocessor-clock multiplier. Clock frequency = [PNR_MUL] * 50 MHz.
See RST_PNR_PLL for details on programming and initial values.
Internal:
[PNR_MUL] is a copy of RST_PNR_PLL[CUR_MUL]. */
uint64_t reserved_39 : 1;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Current core-clock multiplier. Clock frequency = [C_MUL] * 50 MHz.
See RST_CORE_PLL for details on programming and initial values.
Internal:
[C_MUL] is a copy of RST_CORE_PLL[CUR_MUL]. */
uint64_t reserved_47_52 : 6;
uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
of MCP and SCP devices is routed directly to GPIO pins. When
cleared these devices are included in the standard JTAG chain.
The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
This field is reinitialized with a cold domain reset.
Reset value is determined by GPIO strap pin number
GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the SCP EJTAG interface (See EJTAGDIS).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S/H) Disable scan. When set and FUSF_CTL[ROT_LCK] = 1, scan is not
allowed in the part. Read requests return current disable scan status.
Internal:
The field is actually reset only after DCOK has been left
deasserted for an extended period of time. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set, FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to one if FUSF_CTL[FJ_DIS_HUK] is set and not in trusted mode.
It is also set anytime scan mode is activated while FUSF_CTL[FJ_DIS_HUK] is set.
Software must set this bit when the chain of trust is broken.
This field is reinitialized with either a cold or chip domain reset. */
uint64_t vrm_err : 1; /**< [ 57: 57](R/W1) Reserved. */
uint64_t reserved_58_59 : 2;
uint64_t trusted_mode : 1; /**< [ 60: 60](RO/H) When set, chip is operating as a trusted device. This bit is asserted when
either FUSF_CTL[TZ_FORCE2], or the trusted mode strap on GPIO number
GPIO_STRAP_PIN_E::TRUSTED_MODE is set. */
uint64_t scp_jtagdis : 1; /**< [ 61: 61](R/W/H) SCP JTAG debugger disable. When set, the SCP debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the MCP EJTAG interface (See [MCP_JTAGDIS]).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t jtagdis : 1; /**< [ 62: 62](R/W/H) JTAG access disable. When set, the debug access port of the
JTAG TAP controller will be disabled, i.e. DAP_IMP_DAR will be zero.
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A zero-to-one transition of CHIPKILL starts the CHIPKILL timer. When set and the timer
expires, chip domain reset is asserted.
The length of the CHIPKILL timer is specified by RST_CKILL[TIMER].
This feature is effectively a delayed reset.
This field is reinitialized with a chip domain reset. */
#endif /* Word 0 - End */
} cnf95xxp1;
struct cavm_rst_boot_cnf95xxp2
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A zero-to-one transition of CHIPKILL starts the CHIPKILL timer. When set and the timer
expires, chip domain reset is asserted.
The length of the CHIPKILL timer is specified by RST_CKILL[TIMER].
This feature is effectively a delayed reset.
This field is reinitialized with a chip domain reset. */
uint64_t jtagdis : 1; /**< [ 62: 62](R/W/H) JTAG access disable. When set, the debug access port of the
JTAG TAP controller will be disabled, i.e. DAP_IMP_DAR will be zero.
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t scp_jtagdis : 1; /**< [ 61: 61](R/W/H) SCP JTAG debugger disable. When set, the SCP debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the MCP EJTAG interface (See [MCP_JTAGDIS]).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t trusted_mode : 1; /**< [ 60: 60](RO/H) When set, chip is operating as a trusted device. This bit is asserted when
either FUSF_CTL[TZ_FORCE2], or the trusted mode strap on GPIO number
GPIO_STRAP_PIN_E::TRUSTED_MODE is set. */
uint64_t reserved_58_59 : 2;
uint64_t vrm_err : 1; /**< [ 57: 57](R/W1) Reserved. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set, FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to one if FUSF_CTL[FJ_DIS_HUK] is set and not in trusted mode.
It is also set anytime scan mode is activated while FUSF_CTL[FJ_DIS_HUK] is set.
Software must set this bit when the chain of trust is broken.
This field is reinitialized with either a cold or chip domain reset. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S/H) Disable scan. When set and FUSF_CTL[ROT_LCK] = 1, scan is not
allowed in the part. Read requests return current disable scan status.
Internal:
The field is actually reset only after DCOK has been left
deasserted for an extended period of time. */
uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the SCP EJTAG interface (See EJTAGDIS).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
of MCP and SCP devices is routed directly to GPIO pins. When
cleared these devices are included in the standard JTAG chain.
The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
This field is reinitialized with a cold domain reset.
Reset value is determined by GPIO strap pin number
GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
uint64_t reserved_47_52 : 6;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Current core-clock multiplier. Clock frequency = [C_MUL] * 50 MHz.
See RST_CORE_PLL for details on programming and initial values.
Internal:
[C_MUL] is a copy of RST_CORE_PLL[CUR_MUL]. */
uint64_t reserved_39 : 1;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Current coprocessor-clock multiplier. Clock frequency = [PNR_MUL] * 50 MHz.
See RST_PNR_PLL for details on programming and initial values.
Internal:
[PNR_MUL] is a copy of RST_PNR_PLL[CUR_MUL]. */
uint64_t reserved_31_32 : 2;
uint64_t cpt_mul : 7; /**< [ 30: 24](RO/H) Reserved.
Internal:
Unused on 95xx. */
uint64_t reserved_23 : 1;
uint64_t dsp_mul : 7; /**< [ 22: 16](RO/H) Current DSP-clock multiplier. Clock frequency = [DSP_MUL] * 50 MHz.
See RST_DSP_PLL for details on programming and initial values.
Internal:
[DSP_MUL] is a copy of RST_DSP_PLL[CUR_MUL]. */
uint64_t reserved_15 : 1;
uint64_t bphy_mul : 7; /**< [ 14: 8](RO/H) Current BPHY-clock multiplier. Clock frequency = [BPHY_MUL] * 50 MHz.
See RST_BPHY_PLL for details on programming and initial values.
Internal:
[BPHY_MUL] is a copy of RST_BPHY_PLL[CUR_MUL]. */
uint64_t reserved_2_7 : 6;
uint64_t rboot : 1; /**< [ 1: 1](R/W/H) Remote boot. If set, indicates that SCP will require a write to
RST_SCP_DOMAIN_W1C to bring it out of reset. Otherwise it
will automatically come out of reset once the reset source has
been deasserted.
The initial value is set when [RBOOT_PIN] is true and
trustzone has not been enabled.
This field is reinitialized with a cold domain reset.
Internal:
This field is cleared when jtg__rst_disable_remote is active. */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO) Remote boot strap. The value is set when primary boot method is RST_BOOT_METHOD_E::REMOTE
when the GPIO pins are sampled on the rising edge of PLL_DCOK. */
#else /* Word 0 - Little Endian */
uint64_t rboot_pin : 1; /**< [ 0: 0](RO) Remote boot strap. The value is set when primary boot method is RST_BOOT_METHOD_E::REMOTE
when the GPIO pins are sampled on the rising edge of PLL_DCOK. */
uint64_t rboot : 1; /**< [ 1: 1](R/W/H) Remote boot. If set, indicates that SCP will require a write to
RST_SCP_DOMAIN_W1C to bring it out of reset. Otherwise it
will automatically come out of reset once the reset source has
been deasserted.
The initial value is set when [RBOOT_PIN] is true and
trustzone has not been enabled.
This field is reinitialized with a cold domain reset.
Internal:
This field is cleared when jtg__rst_disable_remote is active. */
uint64_t reserved_2_7 : 6;
uint64_t bphy_mul : 7; /**< [ 14: 8](RO/H) Current BPHY-clock multiplier. Clock frequency = [BPHY_MUL] * 50 MHz.
See RST_BPHY_PLL for details on programming and initial values.
Internal:
[BPHY_MUL] is a copy of RST_BPHY_PLL[CUR_MUL]. */
uint64_t reserved_15 : 1;
uint64_t dsp_mul : 7; /**< [ 22: 16](RO/H) Current DSP-clock multiplier. Clock frequency = [DSP_MUL] * 50 MHz.
See RST_DSP_PLL for details on programming and initial values.
Internal:
[DSP_MUL] is a copy of RST_DSP_PLL[CUR_MUL]. */
uint64_t reserved_23 : 1;
uint64_t cpt_mul : 7; /**< [ 30: 24](RO/H) Reserved.
Internal:
Unused on 95xx. */
uint64_t reserved_31_32 : 2;
uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Current coprocessor-clock multiplier. Clock frequency = [PNR_MUL] * 50 MHz.
See RST_PNR_PLL for details on programming and initial values.
Internal:
[PNR_MUL] is a copy of RST_PNR_PLL[CUR_MUL]. */
uint64_t reserved_39 : 1;
uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Current core-clock multiplier. Clock frequency = [C_MUL] * 50 MHz.
See RST_CORE_PLL for details on programming and initial values.
Internal:
[C_MUL] is a copy of RST_CORE_PLL[CUR_MUL]. */
uint64_t reserved_47_52 : 6;
uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
of MCP and SCP devices is routed directly to GPIO pins. When
cleared these devices are included in the standard JTAG chain.
The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
This field is reinitialized with a cold domain reset.
Reset value is determined by GPIO strap pin number
GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the SCP EJTAG interface (See EJTAGDIS).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S/H) Disable scan. When set and FUSF_CTL[ROT_LCK] = 1, scan is not
allowed in the part. Read requests return current disable scan status.
Internal:
The field is actually reset only after DCOK has been left
deasserted for an extended period of time. */
uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set, FUSF_SSK(),
FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
Resets to one if FUSF_CTL[FJ_DIS_HUK] is set and not in trusted mode.
It is also set anytime scan mode is activated while FUSF_CTL[FJ_DIS_HUK] is set.
Software must set this bit when the chain of trust is broken.
This field is reinitialized with either a cold or chip domain reset. */
uint64_t vrm_err : 1; /**< [ 57: 57](R/W1) Reserved. */
uint64_t reserved_58_59 : 2;
uint64_t trusted_mode : 1; /**< [ 60: 60](RO/H) When set, chip is operating as a trusted device. This bit is asserted when
either FUSF_CTL[TZ_FORCE2], or the trusted mode strap on GPIO number
GPIO_STRAP_PIN_E::TRUSTED_MODE is set. */
uint64_t scp_jtagdis : 1; /**< [ 61: 61](R/W/H) SCP JTAG debugger disable. When set, the SCP debug interface of
the EJTAG TAP controller will be disabled. This field does not
control the MCP EJTAG interface (See [MCP_JTAGDIS]).
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t jtagdis : 1; /**< [ 62: 62](R/W/H) JTAG access disable. When set, the debug access port of the
JTAG TAP controller will be disabled, i.e. DAP_IMP_DAR will be zero.
This field resets to one in trusted mode otherwise it is cleared.
This field is reinitialized with a cold domain reset. */
uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A zero-to-one transition of CHIPKILL starts the CHIPKILL timer. When set and the timer
expires, chip domain reset is asserted.
The length of the CHIPKILL timer is specified by RST_CKILL[TIMER].
This feature is effectively a delayed reset.
This field is reinitialized with a chip domain reset. */
#endif /* Word 0 - End */
} cnf95xxp2;
/* struct cavm_rst_boot_cnf95xxp2 loki; */
};
typedef union cavm_rst_boot cavm_rst_boot_t;
#define CAVM_RST_BOOT CAVM_RST_BOOT_FUNC()
static inline uint64_t CAVM_RST_BOOT_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_BOOT_FUNC(void)
{
return 0x87e006001600ll;
}
#define typedef_CAVM_RST_BOOT cavm_rst_boot_t
#define bustype_CAVM_RST_BOOT CSR_TYPE_RSL
#define basename_CAVM_RST_BOOT "RST_BOOT"
#define device_bar_CAVM_RST_BOOT 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_BOOT 0
#define arguments_CAVM_RST_BOOT -1,-1,-1,-1
/**
* Register (RSL) rst_boot_status
*
* RST Boot Status Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_boot_status
{
uint64_t u;
struct cavm_rst_boot_status_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t stat3 : 16; /**< [ 63: 48](R/W) JTAG-accessible boot status word three. Used by software to indicate progress of
boot. Accessible via JTG/DTX with offset 17.
This field is always reinitialized on a chip domain reset. */
uint64_t stat2 : 16; /**< [ 47: 32](R/W) JTAG-accessible boot status word two. Used by software to indicate progress of
boot. Accessible via JTG/DTX with offset 16.
This field is always reinitialized on a chip domain reset. */
uint64_t stat1 : 16; /**< [ 31: 16](R/W) JTAG-accessible boot status word one. Used by software to indicate progress of
boot. Accessible via JTG/DTX with offset 13.
This field is always reinitialized on a chip domain reset. */
uint64_t stat0 : 16; /**< [ 15: 0](R/W) JTAG-accessible boot status word zero. Used by software to indicate progress of
boot. Accessible via JTG/DTX with offset 12.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t stat0 : 16; /**< [ 15: 0](R/W) JTAG-accessible boot status word zero. Used by software to indicate progress of
boot. Accessible via JTG/DTX with offset 12.
This field is always reinitialized on a chip domain reset. */
uint64_t stat1 : 16; /**< [ 31: 16](R/W) JTAG-accessible boot status word one. Used by software to indicate progress of
boot. Accessible via JTG/DTX with offset 13.
This field is always reinitialized on a chip domain reset. */
uint64_t stat2 : 16; /**< [ 47: 32](R/W) JTAG-accessible boot status word two. Used by software to indicate progress of
boot. Accessible via JTG/DTX with offset 16.
This field is always reinitialized on a chip domain reset. */
uint64_t stat3 : 16; /**< [ 63: 48](R/W) JTAG-accessible boot status word three. Used by software to indicate progress of
boot. Accessible via JTG/DTX with offset 17.
This field is always reinitialized on a chip domain reset. */
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_boot_status_s cn; */
};
typedef union cavm_rst_boot_status cavm_rst_boot_status_t;
#define CAVM_RST_BOOT_STATUS CAVM_RST_BOOT_STATUS_FUNC()
static inline uint64_t CAVM_RST_BOOT_STATUS_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_BOOT_STATUS_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001800ll;
__cavm_csr_fatal("RST_BOOT_STATUS", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_BOOT_STATUS cavm_rst_boot_status_t
#define bustype_CAVM_RST_BOOT_STATUS CSR_TYPE_RSL
#define basename_CAVM_RST_BOOT_STATUS "RST_BOOT_STATUS"
#define device_bar_CAVM_RST_BOOT_STATUS 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_BOOT_STATUS 0
#define arguments_CAVM_RST_BOOT_STATUS -1,-1,-1,-1
/**
* Register (RSL) rst_bphy_domain_w1c
*
* RST BPHY Domain Soft Reset Clear Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_bphy_domain_w1c
{
uint64_t u;
struct cavm_rst_bphy_domain_w1c_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear softare-initiated reset of the BPHY processor and associated logic.
When set to one, the soft reset of the bphy is removed.
Reads of this register show the soft reset state. Not the actual bphy domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[BPHY] shows
the actual reset state. To compensate for delays in reset, this field should only
be set if RST_RESET_ACTIVE[BPHY] is set.
This field is always reinitialized on a core domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear softare-initiated reset of the BPHY processor and associated logic.
When set to one, the soft reset of the bphy is removed.
Reads of this register show the soft reset state. Not the actual bphy domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[BPHY] shows
the actual reset state. To compensate for delays in reset, this field should only
be set if RST_RESET_ACTIVE[BPHY] is set.
This field is always reinitialized on a core domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_bphy_domain_w1c_s cn9; */
/* struct cavm_rst_bphy_domain_w1c_s cnf95xxp1; */
struct cavm_rst_bphy_domain_w1c_cnf95xxp2
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear software-initiated reset of the BPHY processor and associated logic.
When set to one, the soft reset of the BPHY is removed.
Reads of this register show the soft reset state. Not the actual BPHY domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[BPHY] shows
the actual reset state. To compensate for delays in reset, this field should only
be set if RST_RESET_ACTIVE[BPHY] is set.
This field is always reinitialized on a core domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear software-initiated reset of the BPHY processor and associated logic.
When set to one, the soft reset of the BPHY is removed.
Reads of this register show the soft reset state. Not the actual BPHY domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[BPHY] shows
the actual reset state. To compensate for delays in reset, this field should only
be set if RST_RESET_ACTIVE[BPHY] is set.
This field is always reinitialized on a core domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} cnf95xxp2;
/* struct cavm_rst_bphy_domain_w1c_cnf95xxp2 loki; */
};
typedef union cavm_rst_bphy_domain_w1c cavm_rst_bphy_domain_w1c_t;
#define CAVM_RST_BPHY_DOMAIN_W1C CAVM_RST_BPHY_DOMAIN_W1C_FUNC()
static inline uint64_t CAVM_RST_BPHY_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_BPHY_DOMAIN_W1C_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CNF95XX))
return 0x87e006001858ll;
if (cavm_is_model(OCTEONTX_LOKI))
return 0x87e006001858ll;
__cavm_csr_fatal("RST_BPHY_DOMAIN_W1C", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_BPHY_DOMAIN_W1C cavm_rst_bphy_domain_w1c_t
#define bustype_CAVM_RST_BPHY_DOMAIN_W1C CSR_TYPE_RSL
#define basename_CAVM_RST_BPHY_DOMAIN_W1C "RST_BPHY_DOMAIN_W1C"
#define device_bar_CAVM_RST_BPHY_DOMAIN_W1C 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_BPHY_DOMAIN_W1C 0
#define arguments_CAVM_RST_BPHY_DOMAIN_W1C -1,-1,-1,-1
/**
* Register (RSL) rst_bphy_domain_w1s
*
* RST BPHY Domain Soft Reset Set Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_bphy_domain_w1s
{
uint64_t u;
struct cavm_rst_bphy_domain_w1s_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set software-initiated reset of BPHY associated logic.
When set to one, all logic associated with the bphy domain is placed in reset.
Reads of this register show the soft reset state. Not the actual bphy domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[BPHY] shows
the actual reset state.
This field is always reinitialized on a core domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set software-initiated reset of BPHY associated logic.
When set to one, all logic associated with the bphy domain is placed in reset.
Reads of this register show the soft reset state. Not the actual bphy domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[BPHY] shows
the actual reset state.
This field is always reinitialized on a core domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_bphy_domain_w1s_s cn9; */
/* struct cavm_rst_bphy_domain_w1s_s cnf95xxp1; */
struct cavm_rst_bphy_domain_w1s_cnf95xxp2
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set software-initiated reset of BPHY associated logic.
When set to one, all logic associated with the BPHY domain is placed in reset.
Reads of this register show the soft reset state. Not the actual BPHY domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[BPHY] shows
the actual reset state.
This field is always reinitialized on a core domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set software-initiated reset of BPHY associated logic.
When set to one, all logic associated with the BPHY domain is placed in reset.
Reads of this register show the soft reset state. Not the actual BPHY domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[BPHY] shows
the actual reset state.
This field is always reinitialized on a core domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} cnf95xxp2;
/* struct cavm_rst_bphy_domain_w1s_cnf95xxp2 loki; */
};
typedef union cavm_rst_bphy_domain_w1s cavm_rst_bphy_domain_w1s_t;
#define CAVM_RST_BPHY_DOMAIN_W1S CAVM_RST_BPHY_DOMAIN_W1S_FUNC()
static inline uint64_t CAVM_RST_BPHY_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_BPHY_DOMAIN_W1S_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CNF95XX))
return 0x87e006001850ll;
if (cavm_is_model(OCTEONTX_LOKI))
return 0x87e006001850ll;
__cavm_csr_fatal("RST_BPHY_DOMAIN_W1S", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_BPHY_DOMAIN_W1S cavm_rst_bphy_domain_w1s_t
#define bustype_CAVM_RST_BPHY_DOMAIN_W1S CSR_TYPE_RSL
#define basename_CAVM_RST_BPHY_DOMAIN_W1S "RST_BPHY_DOMAIN_W1S"
#define device_bar_CAVM_RST_BPHY_DOMAIN_W1S 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_BPHY_DOMAIN_W1S 0
#define arguments_CAVM_RST_BPHY_DOMAIN_W1S -1,-1,-1,-1
/**
* Register (RSL) rst_bphy_pll
*
* RST BPHY Clock PLL Control Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_bphy_pll
{
uint64_t u;
struct cavm_rst_bphy_pll_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) BPHY clockout select.
0x0 = BPHY clock divided by 32.
0x1 = BPHY clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) BPHY clockout reset. The bphy clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 bclk/dsp_clk/sclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) BPHY PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) BPHY PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) BPHY clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[BPHY_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both pll is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) BPHY PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[BPHY_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) BPHY clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[BPHY_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) BPHY clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[BPHY_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) BPHY PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[BPHY_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both pll is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) BPHY clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[BPHY_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) BPHY PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) BPHY PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 bclk/dsp_clk/sclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) BPHY clockout reset. The bphy clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) BPHY clockout select.
0x0 = BPHY clock divided by 32.
0x1 = BPHY clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_bphy_pll_s cn9; */
/* struct cavm_rst_bphy_pll_s cnf95xxp1; */
struct cavm_rst_bphy_pll_cnf95xxp2
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) BPHY clockout select.
0x0 = BPHY clock divided by 32.
0x1 = BPHY clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) BPHY clockout reset. The BPHY clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 bclk/dsp_clk/sclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) BPHY PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) BPHY PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) BPHY clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[BPHY_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) BPHY PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[BPHY_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) BPHY clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[BPHY_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) BPHY clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[BPHY_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) BPHY PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[BPHY_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) BPHY clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[BPHY_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) BPHY PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) BPHY PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 bclk/dsp_clk/sclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) BPHY clockout reset. The BPHY clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) BPHY clockout select.
0x0 = BPHY clock divided by 32.
0x1 = BPHY clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cnf95xxp2;
/* struct cavm_rst_bphy_pll_cnf95xxp2 loki; */
};
typedef union cavm_rst_bphy_pll cavm_rst_bphy_pll_t;
#define CAVM_RST_BPHY_PLL CAVM_RST_BPHY_PLL_FUNC()
static inline uint64_t CAVM_RST_BPHY_PLL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_BPHY_PLL_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CNF95XX))
return 0x87e00a001768ll;
if (cavm_is_model(OCTEONTX_LOKI))
return 0x87e00a001768ll;
__cavm_csr_fatal("RST_BPHY_PLL", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_BPHY_PLL cavm_rst_bphy_pll_t
#define bustype_CAVM_RST_BPHY_PLL CSR_TYPE_RSL
#define basename_CAVM_RST_BPHY_PLL "RST_BPHY_PLL"
#define device_bar_CAVM_RST_BPHY_PLL 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_BPHY_PLL 0
#define arguments_CAVM_RST_BPHY_PLL -1,-1,-1,-1
/**
* Register (RSL) rst_cfg
*
* RST Configuration Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_cfg
{
uint64_t u;
struct cavm_rst_cfg_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t bist_delay : 58; /**< [ 63: 6](RO/H) Reserved. */
uint64_t reserved_3_5 : 3;
uint64_t cntl_clr_bist : 1; /**< [ 2: 2](R/W) Perform clear BIST during control-only reset, instead of a full BIST. A warm/soft reset
does not change this field. */
uint64_t warm_clr_bist : 1; /**< [ 1: 1](R/W) Perform clear BIST during warm reset, instead of a full BIST. A warm/soft reset does not
change this field. Note that a cold reset always performs a full BIST. */
uint64_t reserved_0 : 1;
#else /* Word 0 - Little Endian */
uint64_t reserved_0 : 1;
uint64_t warm_clr_bist : 1; /**< [ 1: 1](R/W) Perform clear BIST during warm reset, instead of a full BIST. A warm/soft reset does not
change this field. Note that a cold reset always performs a full BIST. */
uint64_t cntl_clr_bist : 1; /**< [ 2: 2](R/W) Perform clear BIST during control-only reset, instead of a full BIST. A warm/soft reset
does not change this field. */
uint64_t reserved_3_5 : 3;
uint64_t bist_delay : 58; /**< [ 63: 6](RO/H) Reserved. */
#endif /* Word 0 - End */
} s;
struct cavm_rst_cfg_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t bist_delay : 58; /**< [ 63: 6](RO/H) Reserved. */
uint64_t reserved_3_5 : 3;
uint64_t cntl_clr_bist : 1; /**< [ 2: 2](R/W) Perform clear BIST during control-only reset, instead of a full BIST. A warm/soft reset
does not change this field. */
uint64_t warm_clr_bist : 1; /**< [ 1: 1](R/W) Perform clear BIST during warm reset, instead of a full BIST. A warm/soft reset does not
change this field. Note that a cold reset always performs a full BIST. */
uint64_t soft_clr_bist : 1; /**< [ 0: 0](R/W) Perform clear BIST during soft reset, instead of a full BIST. A warm/soft reset does not
change this field. Note that a cold reset always performs a full BIST. */
#else /* Word 0 - Little Endian */
uint64_t soft_clr_bist : 1; /**< [ 0: 0](R/W) Perform clear BIST during soft reset, instead of a full BIST. A warm/soft reset does not
change this field. Note that a cold reset always performs a full BIST. */
uint64_t warm_clr_bist : 1; /**< [ 1: 1](R/W) Perform clear BIST during warm reset, instead of a full BIST. A warm/soft reset does not
change this field. Note that a cold reset always performs a full BIST. */
uint64_t cntl_clr_bist : 1; /**< [ 2: 2](R/W) Perform clear BIST during control-only reset, instead of a full BIST. A warm/soft reset
does not change this field. */
uint64_t reserved_3_5 : 3;
uint64_t bist_delay : 58; /**< [ 63: 6](RO/H) Reserved. */
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_cfg_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t clr_bist : 1; /**< [ 0: 0](R/W) Perform clear BIST on each chip domain reset, instead of a full BIST.
Note that the first BIST during a cold domain reset is always a full BIST.
This field is reinitialized with a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t clr_bist : 1; /**< [ 0: 0](R/W) Perform clear BIST on each chip domain reset, instead of a full BIST.
Note that the first BIST during a cold domain reset is always a full BIST.
This field is reinitialized with a cold domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_cfg cavm_rst_cfg_t;
#define CAVM_RST_CFG CAVM_RST_CFG_FUNC()
static inline uint64_t CAVM_RST_CFG_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_CFG_FUNC(void)
{
return 0x87e006001610ll;
}
#define typedef_CAVM_RST_CFG cavm_rst_cfg_t
#define bustype_CAVM_RST_CFG CSR_TYPE_RSL
#define basename_CAVM_RST_CFG "RST_CFG"
#define device_bar_CAVM_RST_CFG 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_CFG 0
#define arguments_CAVM_RST_CFG -1,-1,-1,-1
/**
* Register (RSL) rst_chip_domain_w1s
*
* RST Chip Domain Soft Pulse Reset Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_chip_domain_w1s
{
uint64_t u;
struct cavm_rst_chip_domain_w1s_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Software-initiated reset of entire chip domain.
When set to one, places the entire chip into reset. At the completion
of the reset the field is cleared. This is similar to asserting and
deasserting the CHIP_RESET_L pin.
When performing a reset, set this bit and then read any register to
confirm that chip is out of reset.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Software-initiated reset of entire chip domain.
When set to one, places the entire chip into reset. At the completion
of the reset the field is cleared. This is similar to asserting and
deasserting the CHIP_RESET_L pin.
When performing a reset, set this bit and then read any register to
confirm that chip is out of reset.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_chip_domain_w1s_s cn; */
};
typedef union cavm_rst_chip_domain_w1s cavm_rst_chip_domain_w1s_t;
#define CAVM_RST_CHIP_DOMAIN_W1S CAVM_RST_CHIP_DOMAIN_W1S_FUNC()
static inline uint64_t CAVM_RST_CHIP_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_CHIP_DOMAIN_W1S_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001810ll;
__cavm_csr_fatal("RST_CHIP_DOMAIN_W1S", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_CHIP_DOMAIN_W1S cavm_rst_chip_domain_w1s_t
#define bustype_CAVM_RST_CHIP_DOMAIN_W1S CSR_TYPE_RSL
#define basename_CAVM_RST_CHIP_DOMAIN_W1S "RST_CHIP_DOMAIN_W1S"
#define device_bar_CAVM_RST_CHIP_DOMAIN_W1S 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_CHIP_DOMAIN_W1S 0
#define arguments_CAVM_RST_CHIP_DOMAIN_W1S -1,-1,-1,-1
/**
* Register (RSL) rst_ckill
*
* RST Chipkill Timer Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_ckill
{
uint64_t u;
struct cavm_rst_ckill_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_47_63 : 17;
uint64_t timer : 47; /**< [ 46: 0](R/W/H) Chipkill timer measured in coprocessor-clock cycles. Read requests return
current chipkill timer. Write operations have no effect when RST_BOOT[CHIPKILL]
= 1. */
#else /* Word 0 - Little Endian */
uint64_t timer : 47; /**< [ 46: 0](R/W/H) Chipkill timer measured in coprocessor-clock cycles. Read requests return
current chipkill timer. Write operations have no effect when RST_BOOT[CHIPKILL]
= 1. */
uint64_t reserved_47_63 : 17;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_ckill_s cn8; */
struct cavm_rst_ckill_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_47_63 : 17;
uint64_t timer : 47; /**< [ 46: 0](R/W/H) Chipkill timer measured in 100 MHz PLL reference clocks. Read
requests return current chip kill timer. Write operations have
no effect when RST_BOOT[CHIPKILL] is set.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t timer : 47; /**< [ 46: 0](R/W/H) Chipkill timer measured in 100 MHz PLL reference clocks. Read
requests return current chip kill timer. Write operations have
no effect when RST_BOOT[CHIPKILL] is set.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_47_63 : 17;
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_ckill cavm_rst_ckill_t;
#define CAVM_RST_CKILL CAVM_RST_CKILL_FUNC()
static inline uint64_t CAVM_RST_CKILL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_CKILL_FUNC(void)
{
return 0x87e006001638ll;
}
#define typedef_CAVM_RST_CKILL cavm_rst_ckill_t
#define bustype_CAVM_RST_CKILL CSR_TYPE_RSL
#define basename_CAVM_RST_CKILL "RST_CKILL"
#define device_bar_CAVM_RST_CKILL 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_CKILL 0
#define arguments_CAVM_RST_CKILL -1,-1,-1,-1
/**
* Register (RSL) rst_cold_data#
*
* RST Cold Reset Data Registers
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_cold_datax
{
uint64_t u;
struct cavm_rst_cold_datax_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t data : 64; /**< [ 63: 0](R/W) Scratch data registers preserved through warm reset. */
#else /* Word 0 - Little Endian */
uint64_t data : 64; /**< [ 63: 0](R/W) Scratch data registers preserved through warm reset. */
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_cold_datax_s cn8; */
struct cavm_rst_cold_datax_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t data : 64; /**< [ 63: 0](R/W) Scratch data registers preserved through chip, core,
MCP and SCP domain resets.
This field is always reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t data : 64; /**< [ 63: 0](R/W) Scratch data registers preserved through chip, core,
MCP and SCP domain resets.
This field is always reinitialized on a cold domain reset. */
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_cold_datax cavm_rst_cold_datax_t;
static inline uint64_t CAVM_RST_COLD_DATAX(unsigned long a) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_COLD_DATAX(unsigned long a)
{
if (a<=5)
return 0x87e0060017c0ll + 8ll * ((a) & 0x7);
__cavm_csr_fatal("RST_COLD_DATAX", 1, a, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_COLD_DATAX(a) cavm_rst_cold_datax_t
#define bustype_CAVM_RST_COLD_DATAX(a) CSR_TYPE_RSL
#define basename_CAVM_RST_COLD_DATAX(a) "RST_COLD_DATAX"
#define device_bar_CAVM_RST_COLD_DATAX(a) 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_COLD_DATAX(a) (a)
#define arguments_CAVM_RST_COLD_DATAX(a) (a),-1,-1,-1
/**
* Register (RSL) rst_cold_domain_w1s
*
* RST Cold Domain Pulse Reset Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_cold_domain_w1s
{
uint64_t u;
struct cavm_rst_cold_domain_w1s_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Software-initiated reset of entire chip emulating a cold domain reset.
When set to one, places the entire chip into reset. At the completion
of the reset the field is cleared.
This action is similar to deasserting and asserting PLL_DCOK with the
exception that external pins are not sampled again.
When performing a reset, set this bit and
then read any register to confirm that chip is out of reset.
This field is always reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Software-initiated reset of entire chip emulating a cold domain reset.
When set to one, places the entire chip into reset. At the completion
of the reset the field is cleared.
This action is similar to deasserting and asserting PLL_DCOK with the
exception that external pins are not sampled again.
When performing a reset, set this bit and
then read any register to confirm that chip is out of reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_cold_domain_w1s_s cn; */
};
typedef union cavm_rst_cold_domain_w1s cavm_rst_cold_domain_w1s_t;
#define CAVM_RST_COLD_DOMAIN_W1S CAVM_RST_COLD_DOMAIN_W1S_FUNC()
static inline uint64_t CAVM_RST_COLD_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_COLD_DOMAIN_W1S_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001808ll;
__cavm_csr_fatal("RST_COLD_DOMAIN_W1S", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_COLD_DOMAIN_W1S cavm_rst_cold_domain_w1s_t
#define bustype_CAVM_RST_COLD_DOMAIN_W1S CSR_TYPE_RSL
#define basename_CAVM_RST_COLD_DOMAIN_W1S "RST_COLD_DOMAIN_W1S"
#define device_bar_CAVM_RST_COLD_DOMAIN_W1S 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_COLD_DOMAIN_W1S 0
#define arguments_CAVM_RST_COLD_DOMAIN_W1S -1,-1,-1,-1
/**
* Register (RSL) rst_const
*
* RST Constant Register
* This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_const
{
uint64_t u;
struct cavm_rst_const_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_16_63 : 48;
uint64_t rst_devs : 8; /**< [ 15: 8](RO) Number of RST_DEV_E enumeration values supported, and size of RST_DEV_MAP(). */
uint64_t pems : 8; /**< [ 7: 0](RO) Number of PEMs supported by RST, and size of RST_CTL(), RST_SOFT_PRST(). */
#else /* Word 0 - Little Endian */
uint64_t pems : 8; /**< [ 7: 0](RO) Number of PEMs supported by RST, and size of RST_CTL(), RST_SOFT_PRST(). */
uint64_t rst_devs : 8; /**< [ 15: 8](RO) Number of RST_DEV_E enumeration values supported, and size of RST_DEV_MAP(). */
uint64_t reserved_16_63 : 48;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_const_s cn9; */
/* struct cavm_rst_const_s cn96xxp1; */
struct cavm_rst_const_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_16_63 : 48;
uint64_t rst_devs : 8; /**< [ 15: 8](RO) Number of RST_DEV_E enumeration values supported, and size of RST_DEV_MAP(). */
uint64_t pems : 8; /**< [ 7: 0](RO) Number of PEMs supported by RST. */
#else /* Word 0 - Little Endian */
uint64_t pems : 8; /**< [ 7: 0](RO) Number of PEMs supported by RST. */
uint64_t rst_devs : 8; /**< [ 15: 8](RO) Number of RST_DEV_E enumeration values supported, and size of RST_DEV_MAP(). */
uint64_t reserved_16_63 : 48;
#endif /* Word 0 - End */
} cn96xxp3;
/* struct cavm_rst_const_cn96xxp3 cn98xx; */
/* struct cavm_rst_const_s cnf95xx; */
struct cavm_rst_const_loki
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_16_63 : 48;
uint64_t rst_devs : 8; /**< [ 15: 8](RO) Number of RST_DEV_E enumeration values supported, and size of RST_DEV_MAP(). */
uint64_t pems : 8; /**< [ 7: 0](RO) Number of PEMs supported by RST */
#else /* Word 0 - Little Endian */
uint64_t pems : 8; /**< [ 7: 0](RO) Number of PEMs supported by RST */
uint64_t rst_devs : 8; /**< [ 15: 8](RO) Number of RST_DEV_E enumeration values supported, and size of RST_DEV_MAP(). */
uint64_t reserved_16_63 : 48;
#endif /* Word 0 - End */
} loki;
};
typedef union cavm_rst_const cavm_rst_const_t;
#define CAVM_RST_CONST CAVM_RST_CONST_FUNC()
static inline uint64_t CAVM_RST_CONST_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_CONST_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e0060018f8ll;
__cavm_csr_fatal("RST_CONST", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_CONST cavm_rst_const_t
#define bustype_CAVM_RST_CONST CSR_TYPE_RSL
#define basename_CAVM_RST_CONST "RST_CONST"
#define device_bar_CAVM_RST_CONST 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_CONST 0
#define arguments_CAVM_RST_CONST -1,-1,-1,-1
/**
* Register (RSL) rst_core_domain_w1c
*
* RST Core Domain Soft Reset Clear Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_core_domain_w1c
{
uint64_t u;
struct cavm_rst_core_domain_w1c_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear software-initiated reset of AP cores, cache, NCB and associated logic.
When set to one, the soft reset of the core is removed.
Reads of this register show the soft reset state. Not the actual core domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[CORE] shows
the actual reset state. To compensate for delays in reset, this field should only
be set if RST_RESET_ACTIVE[CORE] is set.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear software-initiated reset of AP cores, cache, NCB and associated logic.
When set to one, the soft reset of the core is removed.
Reads of this register show the soft reset state. Not the actual core domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[CORE] shows
the actual reset state. To compensate for delays in reset, this field should only
be set if RST_RESET_ACTIVE[CORE] is set.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_core_domain_w1c_s cn; */
};
typedef union cavm_rst_core_domain_w1c cavm_rst_core_domain_w1c_t;
#define CAVM_RST_CORE_DOMAIN_W1C CAVM_RST_CORE_DOMAIN_W1C_FUNC()
static inline uint64_t CAVM_RST_CORE_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_CORE_DOMAIN_W1C_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001828ll;
__cavm_csr_fatal("RST_CORE_DOMAIN_W1C", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_CORE_DOMAIN_W1C cavm_rst_core_domain_w1c_t
#define bustype_CAVM_RST_CORE_DOMAIN_W1C CSR_TYPE_RSL
#define basename_CAVM_RST_CORE_DOMAIN_W1C "RST_CORE_DOMAIN_W1C"
#define device_bar_CAVM_RST_CORE_DOMAIN_W1C 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_CORE_DOMAIN_W1C 0
#define arguments_CAVM_RST_CORE_DOMAIN_W1C -1,-1,-1,-1
/**
* Register (RSL) rst_core_domain_w1s
*
* RST Core Domain Soft Reset Set Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_core_domain_w1s
{
uint64_t u;
struct cavm_rst_core_domain_w1s_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Software-initiated reset of AP cores, cache, NCB and associated logic.
When set to one, all logic associated with the core domain is placed in reset.
Reads of this register show the soft reset state. Not the actual core domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[CORE] shows
the actual reset state.
It is typically cleared by writing to RST_CORE_DOMAIN_W1C.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Software-initiated reset of AP cores, cache, NCB and associated logic.
When set to one, all logic associated with the core domain is placed in reset.
Reads of this register show the soft reset state. Not the actual core domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[CORE] shows
the actual reset state.
It is typically cleared by writing to RST_CORE_DOMAIN_W1C.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_core_domain_w1s_s cn; */
};
typedef union cavm_rst_core_domain_w1s cavm_rst_core_domain_w1s_t;
#define CAVM_RST_CORE_DOMAIN_W1S CAVM_RST_CORE_DOMAIN_W1S_FUNC()
static inline uint64_t CAVM_RST_CORE_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_CORE_DOMAIN_W1S_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001820ll;
__cavm_csr_fatal("RST_CORE_DOMAIN_W1S", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_CORE_DOMAIN_W1S cavm_rst_core_domain_w1s_t
#define bustype_CAVM_RST_CORE_DOMAIN_W1S CSR_TYPE_RSL
#define basename_CAVM_RST_CORE_DOMAIN_W1S "RST_CORE_DOMAIN_W1S"
#define device_bar_CAVM_RST_CORE_DOMAIN_W1S 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_CORE_DOMAIN_W1S 0
#define arguments_CAVM_RST_CORE_DOMAIN_W1S -1,-1,-1,-1
/**
* Register (RSL) rst_core_pll
*
* RST Core Clock PLL Control Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_core_pll
{
uint64_t u;
struct cavm_rst_core_pll_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Core clockout select.
0x0 = Core clock divided by 32.
0x1 = Core clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Core clockout reset. The core clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) Core PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) Core PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Core clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CORE_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Core PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CORE_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Core clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CORE_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Core clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CORE_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Core PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CORE_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Core clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CORE_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) Core PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) Core PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Core clockout reset. The core clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Core clockout select.
0x0 = Core clock divided by 32.
0x1 = Core clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_core_pll_s cn9; */
/* struct cavm_rst_core_pll_s cn96xx; */
struct cavm_rst_core_pll_cn98xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Core clockout select.
0x0 = Core clock divided by 32.
0x1 = Core clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Core clockout reset. The core clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 rxp_clk/cpt_clk/sclk/rclk notification to
hardware. Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) Core PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) Core PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Core clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CORE_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Core PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CORE_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Core clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CORE_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Core clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CORE_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Core PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CORE_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Core clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CORE_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) Core PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) Core PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 rxp_clk/cpt_clk/sclk/rclk notification to
hardware. Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Core clockout reset. The core clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Core clockout select.
0x0 = Core clock divided by 32.
0x1 = Core clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cn98xx;
struct cavm_rst_core_pll_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Core clockout select.
0x0 = Core clock divided by 32.
0x1 = Core clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Core clockout reset. The core clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 sclk/rclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) Core PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) Core PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Core clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CORE_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Core PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CORE_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Core clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CORE_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Core clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CORE_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Core PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CORE_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Core clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CORE_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) Core PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) Core PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 sclk/rclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Core clockout reset. The core clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Core clockout select.
0x0 = Core clock divided by 32.
0x1 = Core clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cnf95xx;
/* struct cavm_rst_core_pll_cnf95xx loki; */
};
typedef union cavm_rst_core_pll cavm_rst_core_pll_t;
#define CAVM_RST_CORE_PLL CAVM_RST_CORE_PLL_FUNC()
static inline uint64_t CAVM_RST_CORE_PLL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_CORE_PLL_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e00a001780ll;
__cavm_csr_fatal("RST_CORE_PLL", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_CORE_PLL cavm_rst_core_pll_t
#define bustype_CAVM_RST_CORE_PLL CSR_TYPE_RSL
#define basename_CAVM_RST_CORE_PLL "RST_CORE_PLL"
#define device_bar_CAVM_RST_CORE_PLL 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_CORE_PLL 0
#define arguments_CAVM_RST_CORE_PLL -1,-1,-1,-1
/**
* Register (RSL) rst_cpt1_pll
*
* RST Crypto Clock1 PLL Control Register
*/
union cavm_rst_cpt1_pll
{
uint64_t u;
struct cavm_rst_cpt1_pll_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Crypto clockout select.
0x0 = Crypto clock divided by 32.
0x1 = Crypto clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Crypto clockout reset. The crypto clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
The bit is typically used in conjunction with [NXT_PGM].
When [DLY_SWITCH] is zero, [NXT_PGM] can be used to program the inactive
PLL and that PLL will remain inactive. When set to a nonzero value, the
hardware will wait for any PLL programming to complete ([NXT_PGM]) and then
switch to the inactive PLL after the specified number of PLL reference clocks.
Hardware will add additional clocks if required.
This field is always reinitialized to 0x0 on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 rxp_clk/cpt_clk/sclk/rclk notification to
hardware. Additional delay will also be added to wakeup powered down AP cores during
a chip reset but that time is not reflected in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) CPT PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) CPT PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Crypto clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CPT_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Crypto PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CPT_MAX_MUL] and
a minimum setting of 200 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Crypto clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CPT_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Crypto clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CPT_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Crypto PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CPT_MAX_MUL] and
a minimum setting of 200 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Crypto clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CPT_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) CPT PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) CPT PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
The bit is typically used in conjunction with [NXT_PGM].
When [DLY_SWITCH] is zero, [NXT_PGM] can be used to program the inactive
PLL and that PLL will remain inactive. When set to a nonzero value, the
hardware will wait for any PLL programming to complete ([NXT_PGM]) and then
switch to the inactive PLL after the specified number of PLL reference clocks.
Hardware will add additional clocks if required.
This field is always reinitialized to 0x0 on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 rxp_clk/cpt_clk/sclk/rclk notification to
hardware. Additional delay will also be added to wakeup powered down AP cores during
a chip reset but that time is not reflected in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Crypto clockout reset. The crypto clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Crypto clockout select.
0x0 = Crypto clock divided by 32.
0x1 = Crypto clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_cpt1_pll_s cn; */
};
typedef union cavm_rst_cpt1_pll cavm_rst_cpt1_pll_t;
#define CAVM_RST_CPT1_PLL CAVM_RST_CPT1_PLL_FUNC()
static inline uint64_t CAVM_RST_CPT1_PLL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_CPT1_PLL_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN98XX))
return 0x87e00a0017a0ll;
__cavm_csr_fatal("RST_CPT1_PLL", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_CPT1_PLL cavm_rst_cpt1_pll_t
#define bustype_CAVM_RST_CPT1_PLL CSR_TYPE_RSL
#define basename_CAVM_RST_CPT1_PLL "RST_CPT1_PLL"
#define device_bar_CAVM_RST_CPT1_PLL 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_CPT1_PLL 0
#define arguments_CAVM_RST_CPT1_PLL -1,-1,-1,-1
/**
* Register (RSL) rst_cpt_pll
*
* RST Crypto Clock PLL Control Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_cpt_pll
{
uint64_t u;
struct cavm_rst_cpt_pll_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Crypto clockout select.
0x0 = Crypto clock divided by 32.
0x1 = Crypto clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Crypto clockout reset. The crypto clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
The bit is typically used in conjunction with [NXT_PGM].
When [DLY_SWITCH] is zero, [NXT_PGM] can be used to program the inactive
PLL and that PLL will remain inactive. When set to a nonzero value, the
hardware will wait for any PLL programming to complete ([NXT_PGM]) and then
switch to the inactive PLL after the specified number of PLL reference clocks.
Hardware will add additional clocks if required.
This field is always reinitialized to 0x0 on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
Additional delay will also be added to wakeup powered down AP cores during a
chip reset but that time is not reflected in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) CPT PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) CPT PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Crypto clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CPT_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Crypto PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CPT_MAX_MUL] and
a minimum setting of 200 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Crypto clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CPT_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Crypto clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CPT_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Crypto PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CPT_MAX_MUL] and
a minimum setting of 200 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Crypto clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CPT_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) CPT PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) CPT PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
The bit is typically used in conjunction with [NXT_PGM].
When [DLY_SWITCH] is zero, [NXT_PGM] can be used to program the inactive
PLL and that PLL will remain inactive. When set to a nonzero value, the
hardware will wait for any PLL programming to complete ([NXT_PGM]) and then
switch to the inactive PLL after the specified number of PLL reference clocks.
Hardware will add additional clocks if required.
This field is always reinitialized to 0x0 on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
Additional delay will also be added to wakeup powered down AP cores during a
chip reset but that time is not reflected in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Crypto clockout reset. The crypto clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Crypto clockout select.
0x0 = Crypto clock divided by 32.
0x1 = Crypto clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_cpt_pll_s cn9; */
/* struct cavm_rst_cpt_pll_s cn96xx; */
struct cavm_rst_cpt_pll_cn98xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Crypto clockout select.
0x0 = Crypto clock divided by 32.
0x1 = Crypto clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Crypto clockout reset. The crypto clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
The bit is typically used in conjunction with [NXT_PGM].
When [DLY_SWITCH] is zero, [NXT_PGM] can be used to program the inactive
PLL and that PLL will remain inactive. When set to a nonzero value, the
hardware will wait for any PLL programming to complete ([NXT_PGM]) and then
switch to the inactive PLL after the specified number of PLL reference clocks.
Hardware will add additional clocks if required.
This field is always reinitialized to 0x0 on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 rxp_clk/cpt_clk/sclk/rclk notification to
hardware. Additional delay will also be added to wakeup powered down AP cores during
a chip reset but that time is not reflected in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) CPT PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) CPT PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Crypto clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CPT_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Crypto PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CPT_MAX_MUL] and
a minimum setting of 200 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Crypto clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CPT_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Crypto clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[CPT_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Crypto PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[CPT_MAX_MUL] and
a minimum setting of 200 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Crypto clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[CPT_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) CPT PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) CPT PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
The bit is typically used in conjunction with [NXT_PGM].
When [DLY_SWITCH] is zero, [NXT_PGM] can be used to program the inactive
PLL and that PLL will remain inactive. When set to a nonzero value, the
hardware will wait for any PLL programming to complete ([NXT_PGM]) and then
switch to the inactive PLL after the specified number of PLL reference clocks.
Hardware will add additional clocks if required.
This field is always reinitialized to 0x0 on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 rxp_clk/cpt_clk/sclk/rclk notification to
hardware. Additional delay will also be added to wakeup powered down AP cores during
a chip reset but that time is not reflected in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Crypto clockout reset. The crypto clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Crypto clockout select.
0x0 = Crypto clock divided by 32.
0x1 = Crypto clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cn98xx;
};
typedef union cavm_rst_cpt_pll cavm_rst_cpt_pll_t;
#define CAVM_RST_CPT_PLL CAVM_RST_CPT_PLL_FUNC()
static inline uint64_t CAVM_RST_CPT_PLL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_CPT_PLL_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN96XX))
return 0x87e00a001778ll;
if (cavm_is_model(OCTEONTX_CN98XX))
return 0x87e00a001778ll;
__cavm_csr_fatal("RST_CPT_PLL", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_CPT_PLL cavm_rst_cpt_pll_t
#define bustype_CAVM_RST_CPT_PLL CSR_TYPE_RSL
#define basename_CAVM_RST_CPT_PLL "RST_CPT_PLL"
#define device_bar_CAVM_RST_CPT_PLL 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_CPT_PLL 0
#define arguments_CAVM_RST_CPT_PLL -1,-1,-1,-1
/**
* Register (RSL) rst_ctl#
*
* RST Controllers Registers
* This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_ctlx
{
uint64_t u;
struct cavm_rst_ctlx_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_14_63 : 50;
uint64_t reset_type : 1; /**< [ 13: 13](R/W) Type of reset generated internally by PCI MAC PF FLR, link down/hot reset, Powerdown or
PERST events. See [PF_FLR_CHIP], [RST_LINK], [RST_PWRDWN] and [RST_CHIP].
0 = Chip and core domain reset. (A chip domain reset always also causes a core
domain reset.)
1 = Core domain reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1. */
uint64_t rst_pwrdwn : 1; /**< [ 12: 12](R/W) Powerdown event internal reset enable.
0 = PEM going into powerdown (L2) does not cause an internal reset.
1 = PEM going into powerdown (L2) causes the internal reset
specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a powerdown event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t prst_pwrdwn : 1; /**< [ 11: 11](R/W) PEM reset on power down.
0 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for the
corresponding controller, and (provided properly configured) the link should
come back up automatically.
1 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for
the corresponding controller and set RST_SOFT_PRST()[SOFT_PRST]. This will
hold the link in reset until software clears RST_SOFT_PRST()[SOFT_PRST].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Controls whether corresponding controller PF Function Level Reset causes a chip warm
reset like CHIP_RESET_L. A warm/soft reset does not change this field.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
until software clears RST_SOFT_PRST()[SOFT_PRST].
A warm/soft reset does not change this field. On cold reset, this field is initialized to
0. */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
reset causes a warm chip reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
Note that a link-down or hot-reset event can never cause a warm chip reset when the
controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
uint64_t host_mode : 1; /**< [ 6: 6](RO) For all controllers this field is set as host. */
uint64_t reserved_4_5 : 2;
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1.
When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
the corresponding PERST*_L pin. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
not change this field. On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) warm reset the chip.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
does not change this field. On cold reset, this field is initialized to 0.
When [RST_RCV] = 0, [RST_CHIP] is ignored.
When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
#else /* Word 0 - Little Endian */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
does not change this field. On cold reset, this field is initialized to 0.
When [RST_RCV] = 0, [RST_CHIP] is ignored.
When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
not change this field. On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) warm reset the chip.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1.
When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
the corresponding PERST*_L pin. */
uint64_t reserved_4_5 : 2;
uint64_t host_mode : 1; /**< [ 6: 6](RO) For all controllers this field is set as host. */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
reset causes a warm chip reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
Note that a link-down or hot-reset event can never cause a warm chip reset when the
controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
until software clears RST_SOFT_PRST()[SOFT_PRST].
A warm/soft reset does not change this field. On cold reset, this field is initialized to
0. */
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Controls whether corresponding controller PF Function Level Reset causes a chip warm
reset like CHIP_RESET_L. A warm/soft reset does not change this field.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t prst_pwrdwn : 1; /**< [ 11: 11](R/W) PEM reset on power down.
0 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for the
corresponding controller, and (provided properly configured) the link should
come back up automatically.
1 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for
the corresponding controller and set RST_SOFT_PRST()[SOFT_PRST]. This will
hold the link in reset until software clears RST_SOFT_PRST()[SOFT_PRST].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t rst_pwrdwn : 1; /**< [ 12: 12](R/W) Powerdown event internal reset enable.
0 = PEM going into powerdown (L2) does not cause an internal reset.
1 = PEM going into powerdown (L2) causes the internal reset
specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a powerdown event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t reset_type : 1; /**< [ 13: 13](R/W) Type of reset generated internally by PCI MAC PF FLR, link down/hot reset, Powerdown or
PERST events. See [PF_FLR_CHIP], [RST_LINK], [RST_PWRDWN] and [RST_CHIP].
0 = Chip and core domain reset. (A chip domain reset always also causes a core
domain reset.)
1 = Core domain reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1. */
uint64_t reserved_14_63 : 50;
#endif /* Word 0 - End */
} s;
struct cavm_rst_ctlx_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_11_63 : 53;
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Controls whether corresponding controller PF Function Level Reset causes a chip warm
reset like CHIP_RESET_L. A warm/soft reset does not change this field.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
until software clears RST_SOFT_PRST()[SOFT_PRST].
A warm/soft reset does not change this field. On cold reset, this field is initialized to
0. */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
reset causes a warm chip reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
Note that a link-down or hot-reset event can never cause a warm chip reset when the
controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
uint64_t host_mode : 1; /**< [ 6: 6](RO) For all controllers this field is set as host. */
uint64_t reserved_4_5 : 2;
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1.
When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
the corresponding PERST*_L pin. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
not change this field. On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) warm reset the chip.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
does not change this field. On cold reset, this field is initialized to 0.
When [RST_RCV] = 0, [RST_CHIP] is ignored.
When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
#else /* Word 0 - Little Endian */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
does not change this field. On cold reset, this field is initialized to 0.
When [RST_RCV] = 0, [RST_CHIP] is ignored.
When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
not change this field. On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) warm reset the chip.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1.
When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
the corresponding PERST*_L pin. */
uint64_t reserved_4_5 : 2;
uint64_t host_mode : 1; /**< [ 6: 6](RO) For all controllers this field is set as host. */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
reset causes a warm chip reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
Note that a link-down or hot-reset event can never cause a warm chip reset when the
controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
until software clears RST_SOFT_PRST()[SOFT_PRST].
A warm/soft reset does not change this field. On cold reset, this field is initialized to
0. */
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Controls whether corresponding controller PF Function Level Reset causes a chip warm
reset like CHIP_RESET_L. A warm/soft reset does not change this field.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t reserved_11_63 : 53;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_ctlx_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_10_63 : 54;
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
until software clears RST_SOFT_PRST()[SOFT_PRST].
A warm/soft reset does not change this field. On cold reset, this field is initialized to
0. */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
reset causes a warm chip reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
Note that a link-down or hot-reset event can never cause a warm chip reset when the
controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
uint64_t host_mode : 1; /**< [ 6: 6](RO) For all controllers this field is set as host. */
uint64_t reserved_4_5 : 2;
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1.
When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
the corresponding PERST*_L pin. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
not change this field. On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) warm reset the chip.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
does not change this field. On cold reset, this field is initialized to 0.
When [RST_RCV] = 0, [RST_CHIP] is ignored.
When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
#else /* Word 0 - Little Endian */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
does not change this field. On cold reset, this field is initialized to 0.
When [RST_RCV] = 0, [RST_CHIP] is ignored.
When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
not change this field. On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) warm reset the chip.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1.
When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
the corresponding PERST*_L pin. */
uint64_t reserved_4_5 : 2;
uint64_t host_mode : 1; /**< [ 6: 6](RO) For all controllers this field is set as host. */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
reset causes a warm chip reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
Note that a link-down or hot-reset event can never cause a warm chip reset when the
controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
until software clears RST_SOFT_PRST()[SOFT_PRST].
A warm/soft reset does not change this field. On cold reset, this field is initialized to
0. */
uint64_t reserved_10_63 : 54;
#endif /* Word 0 - End */
} cn81xx;
struct cavm_rst_ctlx_cn83xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_11_63 : 53;
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Controls whether corresponding controller PF Function Level Reset causes a chip warm
reset like CHIP_RESET_L. A warm/soft reset does not change this field.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
until software clears RST_SOFT_PRST()[SOFT_PRST].
A warm/soft reset does not change this field. On cold reset, this field is initialized to
0. */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
reset causes a warm chip reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
Note that a link-down or hot-reset event can never cause a warm chip reset when the
controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
uint64_t host_mode : 1; /**< [ 6: 6](RO) Read-only access to the corresponding PEM()_CFG[HOSTMD] field indicating PEMn is root
complex (host). For controllers 0 and 2 the initial value is determined by straps. For
controllers 1 and 3 this field is initially set as host. */
uint64_t reserved_4_5 : 2;
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1.
When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
the corresponding PERST*_L pin. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
not change this field. On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) warm reset the chip.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
does not change this field. On cold reset, this field is initialized to 0.
When [RST_RCV] = 0, [RST_CHIP] is ignored.
When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
#else /* Word 0 - Little Endian */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
does not change this field. On cold reset, this field is initialized to 0.
When [RST_RCV] = 0, [RST_CHIP] is ignored.
When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
not change this field. On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) warm reset the chip.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1.
When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
the corresponding PERST*_L pin. */
uint64_t reserved_4_5 : 2;
uint64_t host_mode : 1; /**< [ 6: 6](RO) Read-only access to the corresponding PEM()_CFG[HOSTMD] field indicating PEMn is root
complex (host). For controllers 0 and 2 the initial value is determined by straps. For
controllers 1 and 3 this field is initially set as host. */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
reset causes a warm chip reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0.
Note that a link-down or hot-reset event can never cause a warm chip reset when the
controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
until software clears RST_SOFT_PRST()[SOFT_PRST].
A warm/soft reset does not change this field. On cold reset, this field is initialized to
0. */
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Controls whether corresponding controller PF Function Level Reset causes a chip warm
reset like CHIP_RESET_L. A warm/soft reset does not change this field.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t reserved_11_63 : 53;
#endif /* Word 0 - End */
} cn83xx;
struct cavm_rst_ctlx_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_14_63 : 50;
uint64_t reset_type : 1; /**< [ 13: 13](R/W) Type of reset generated internally by PCI MAC PF FLR, link down/hot reset, Powerdown or
PERST events. See [PF_FLR_CHIP], [RST_LINK], [RST_PWRDWN] and [RST_CHIP].
0 = Chip and core domain reset. (A chip domain reset always also causes a core
domain reset.)
1 = Core domain reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1. */
uint64_t rst_pwrdwn : 1; /**< [ 12: 12](R/W) Powerdown event internal reset enable.
0 = PEM going into powerdown (L2) does not cause an internal reset.
1 = PEM going into powerdown (L2) causes the internal reset
specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a powerdown event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t prst_pwrdwn : 1; /**< [ 11: 11](R/W) PEM reset on power down.
0 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for the
corresponding controller, and (provided properly configured) the link should
come back up automatically.
1 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for
the corresponding controller and set RST_SOFT_PRST()[SOFT_PRST]. This will
hold the link in reset until software clears RST_SOFT_PRST()[SOFT_PRST].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) PF FLR internal reset enable.
0 = PF FLR events will not cause an internal reset.
1 = A PF FLR event received by the PCIe logic causes the internal reset
specified by [RESET_TYPE].
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
until software clears RST_SOFT_PRST()[SOFT_PRST].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Link down / hot reset event internal reset enable.
0 = Link down or hot reset do not cause an internal reset.
1 = A link-down or hot-reset event on the PCIe interface causes the internal
reset specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a link-down or hot reset event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t host_mode : 1; /**< [ 6: 6](RO/H) Read-only access to the corresponding PEM()_CFG[HOSTMD] field
indicating PEMn is root complex (host). */
uint64_t reserved_4_5 : 2;
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is cleared.
_ 1 when RST_CTL()[HOST_MODE] is set.
This bit must not be changed in the same write that sets [RST_RCV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) cause a domain reset.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored.
This bit must not be changed in the same write that sets [RST_DRV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other.
If this bit is written while PERSTx_L pin is de-asserted then the MAC can come
out of reset unexpectedly. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) PERST internal reset enable. When set along with [RST_RCV],
logic will generate an internal reset specified by [RESET_TYPE]
when the corresponding PERST*_L pin is asserted. When cleared or
when [RST_RCV] is cleared, the PERST*_L does not cause an internal reset.
If this bit is written while PERSTx_L pin is asserted and [RST_RCV]=1 then an
internal reset can occur unexpectedly.
During a cold domain reset this field is initialized to zero. */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
#else /* Word 0 - Little Endian */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) PERST internal reset enable. When set along with [RST_RCV],
logic will generate an internal reset specified by [RESET_TYPE]
when the corresponding PERST*_L pin is asserted. When cleared or
when [RST_RCV] is cleared, the PERST*_L does not cause an internal reset.
If this bit is written while PERSTx_L pin is asserted and [RST_RCV]=1 then an
internal reset can occur unexpectedly.
During a cold domain reset this field is initialized to zero. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) cause a domain reset.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored.
This bit must not be changed in the same write that sets [RST_DRV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other.
If this bit is written while PERSTx_L pin is de-asserted then the MAC can come
out of reset unexpectedly. */
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is cleared.
_ 1 when RST_CTL()[HOST_MODE] is set.
This bit must not be changed in the same write that sets [RST_RCV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other. */
uint64_t reserved_4_5 : 2;
uint64_t host_mode : 1; /**< [ 6: 6](RO/H) Read-only access to the corresponding PEM()_CFG[HOSTMD] field
indicating PEMn is root complex (host). */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Link down / hot reset event internal reset enable.
0 = Link down or hot reset do not cause an internal reset.
1 = A link-down or hot-reset event on the PCIe interface causes the internal
reset specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a link-down or hot reset event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
until software clears RST_SOFT_PRST()[SOFT_PRST].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) PF FLR internal reset enable.
0 = PF FLR events will not cause an internal reset.
1 = A PF FLR event received by the PCIe logic causes the internal reset
specified by [RESET_TYPE].
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t prst_pwrdwn : 1; /**< [ 11: 11](R/W) PEM reset on power down.
0 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for the
corresponding controller, and (provided properly configured) the link should
come back up automatically.
1 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for
the corresponding controller and set RST_SOFT_PRST()[SOFT_PRST]. This will
hold the link in reset until software clears RST_SOFT_PRST()[SOFT_PRST].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t rst_pwrdwn : 1; /**< [ 12: 12](R/W) Powerdown event internal reset enable.
0 = PEM going into powerdown (L2) does not cause an internal reset.
1 = PEM going into powerdown (L2) causes the internal reset
specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a powerdown event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t reset_type : 1; /**< [ 13: 13](R/W) Type of reset generated internally by PCI MAC PF FLR, link down/hot reset, Powerdown or
PERST events. See [PF_FLR_CHIP], [RST_LINK], [RST_PWRDWN] and [RST_CHIP].
0 = Chip and core domain reset. (A chip domain reset always also causes a core
domain reset.)
1 = Core domain reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1. */
uint64_t reserved_14_63 : 50;
#endif /* Word 0 - End */
} cn9;
/* struct cavm_rst_ctlx_cn9 cn96xx; */
struct cavm_rst_ctlx_cnf95xxp1
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_14_63 : 50;
uint64_t reset_type : 1; /**< [ 13: 13](R/W) Type of reset generated internally by PCI MAC PF FLR, link down/hot reset, Powerdown or
PERST events. See [PF_FLR_CHIP], [RST_LINK], [RST_PWRDWN] and [RST_CHIP].
0 = Chip and core domain reset. (A chip domain reset always also causes a core
domain reset.)
1 = Core domain reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1. */
uint64_t rst_pwrdwn : 1; /**< [ 12: 12](R/W) Powerdown event internal reset enable.
0 = PEM going into powerdown (L2) does not cause an internal reset.
1 = PEM going into powerdown (L2) causes the internal reset
specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a powerdown event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t prst_pwrdwn : 1; /**< [ 11: 11](R/W) PEM reset on power down.
0 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for the
corresponding controller, and (provided properly configured) the link should
come back up automatically.
1 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for
the corresponding controller and set RST_SOFT_PRST()[SOFT_PRST]. This will
hold the link in reset until software clears RST_SOFT_PRST()[SOFT_PRST].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) PF FLR internal reset enable.
0 = PF FLR events will not cause an internal reset.
1 = A PF FLR event received by the PCIe logic causes the internal reset
specified by [RESET_TYPE].
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down event will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down event detected by the PCIe logic causes the internal reset
specified by [RESET_TYPE].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Link down / hot reset event internal reset enable.
0 = Link down or hot reset do not cause an internal reset.
1 = A link-down or hot-reset event on the PCIe interface causes the internal
reset specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a link-down or hot reset event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t host_mode : 1; /**< [ 6: 6](RO/H) Read-only access to the corresponding PEM()_CFG[HOSTMD] field
indicating PEMn is root complex (host). */
uint64_t reserved_4_5 : 2;
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is cleared.
_ 1 when RST_CTL()[HOST_MODE] is set.
This bit must not be changed in the same write that sets [RST_RCV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) cause a domain reset.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored.
This bit must not be changed in the same write that sets [RST_DRV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other.
If this bit is written while PERSTx_L pin is de-asserted then the MAC can come
out of reset unexpectedly. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) PERST internal reset enable. When set along with [RST_RCV],
logic will generate an internal reset specified by [RESET_TYPE]
when the corresponding PERST*_L pin is asserted. When cleared or
when [RST_RCV] is cleared, the PERST*_L does not cause an internal reset.
If this bit is written while PERSTx_L pin is asserted and [RST_RCV]=1 then an
internal reset can occur unexpectedly.
During a cold domain reset this field is initialized to zero. */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
#else /* Word 0 - Little Endian */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) PERST internal reset enable. When set along with [RST_RCV],
logic will generate an internal reset specified by [RESET_TYPE]
when the corresponding PERST*_L pin is asserted. When cleared or
when [RST_RCV] is cleared, the PERST*_L does not cause an internal reset.
If this bit is written while PERSTx_L pin is asserted and [RST_RCV]=1 then an
internal reset can occur unexpectedly.
During a cold domain reset this field is initialized to zero. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) cause a domain reset.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored.
This bit must not be changed in the same write that sets [RST_DRV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other.
If this bit is written while PERSTx_L pin is de-asserted then the MAC can come
out of reset unexpectedly. */
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is cleared.
_ 1 when RST_CTL()[HOST_MODE] is set.
This bit must not be changed in the same write that sets [RST_RCV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other. */
uint64_t reserved_4_5 : 2;
uint64_t host_mode : 1; /**< [ 6: 6](RO/H) Read-only access to the corresponding PEM()_CFG[HOSTMD] field
indicating PEMn is root complex (host). */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Link down / hot reset event internal reset enable.
0 = Link down or hot reset do not cause an internal reset.
1 = A link-down or hot-reset event on the PCIe interface causes the internal
reset specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a link-down or hot reset event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
0 = Link-down event will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down event detected by the PCIe logic causes the internal reset
specified by [RESET_TYPE].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) PF FLR internal reset enable.
0 = PF FLR events will not cause an internal reset.
1 = A PF FLR event received by the PCIe logic causes the internal reset
specified by [RESET_TYPE].
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t prst_pwrdwn : 1; /**< [ 11: 11](R/W) PEM reset on power down.
0 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for the
corresponding controller, and (provided properly configured) the link should
come back up automatically.
1 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for
the corresponding controller and set RST_SOFT_PRST()[SOFT_PRST]. This will
hold the link in reset until software clears RST_SOFT_PRST()[SOFT_PRST].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t rst_pwrdwn : 1; /**< [ 12: 12](R/W) Powerdown event internal reset enable.
0 = PEM going into powerdown (L2) does not cause an internal reset.
1 = PEM going into powerdown (L2) causes the internal reset
specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a powerdown event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t reset_type : 1; /**< [ 13: 13](R/W) Type of reset generated internally by PCI MAC PF FLR, link down/hot reset, Powerdown or
PERST events. See [PF_FLR_CHIP], [RST_LINK], [RST_PWRDWN] and [RST_CHIP].
0 = Chip and core domain reset. (A chip domain reset always also causes a core
domain reset.)
1 = Core domain reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1. */
uint64_t reserved_14_63 : 50;
#endif /* Word 0 - End */
} cnf95xxp1;
struct cavm_rst_ctlx_cnf95xxp2
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_14_63 : 50;
uint64_t reset_type : 1; /**< [ 13: 13](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Type of reset generated internally by PCI MAC PF FLR, link down/hot reset, Powerdown or
PERST events. See [PF_FLR_CHIP], [RST_LINK], [RST_PWRDWN] and [RST_CHIP].
0 = Chip and core domain reset. (A chip domain reset always also causes a core
domain reset.)
1 = Core domain reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1. */
uint64_t rst_pwrdwn : 1; /**< [ 12: 12](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Powerdown event internal reset enable.
0 = PEM going into powerdown (L2) does not cause an internal reset.
1 = PEM going into powerdown (L2) causes the internal reset
specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a powerdown event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t prst_pwrdwn : 1; /**< [ 11: 11](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
PEM reset on power down.
0 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for the
corresponding controller, and (provided properly configured) the link should
come back up automatically.
1 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for
the corresponding controller and set RST_SOFT_PRST()[SOFT_PRST]. This will
hold the link in reset until software clears RST_SOFT_PRST()[SOFT_PRST].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
PF FLR internal reset enable.
0 = PF FLR events will not cause an internal reset.
1 = A PF FLR event received by the PCIe logic causes the internal reset
specified by [RESET_TYPE].
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
PEM reset on link down.
0 = Link-down event will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down event detected by the PCIe logic causes the internal reset
specified by [RESET_TYPE].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Link down / hot reset event internal reset enable.
0 = Link down or hot reset do not cause an internal reset.
1 = A link-down or hot-reset event on the PCIe interface causes the internal
reset specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a link-down or hot reset event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t host_mode : 1; /**< [ 6: 6](RO/H) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Read-only access to the corresponding PEM()_CFG[HOSTMD] field
indicating PEMn is root complex (host). */
uint64_t reserved_4_5 : 2;
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Controls whether PERST*_L is driven.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is cleared.
_ 1 when RST_CTL()[HOST_MODE] is set.
This bit must not be changed in the same write that sets [RST_RCV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Reset received. Controls whether PERST*_L is received.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) cause a domain reset.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored.
This bit must not be changed in the same write that sets [RST_DRV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other.
If this bit is written while PERSTx_L pin is de-asserted then the MAC can come
out of reset unexpectedly. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
PERST internal reset enable. When set along with [RST_RCV],
logic will generate an internal reset specified by [RESET_TYPE]
when the corresponding PERST*_L pin is asserted. When cleared or
when [RST_RCV] is cleared, the PERST*_L does not cause an internal reset.
If this bit is written while PERSTx_L pin is asserted and [RST_RCV]=1 then an
internal reset can occur unexpectedly.
During a cold domain reset this field is initialized to zero. */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
#else /* Word 0 - Little Endian */
uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
PERST internal reset enable. When set along with [RST_RCV],
logic will generate an internal reset specified by [RESET_TYPE]
when the corresponding PERST*_L pin is asserted. When cleared or
when [RST_RCV] is cleared, the PERST*_L does not cause an internal reset.
If this bit is written while PERSTx_L pin is asserted and [RST_RCV]=1 then an
internal reset can occur unexpectedly.
During a cold domain reset this field is initialized to zero. */
uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Reset received. Controls whether PERST*_L is received.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
controller and (optionally, based on [RST_CHIP]) cause a domain reset.
When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
pin asserts. (This interrupt can alert software whenever the external reset pin initiates
a controller reset sequence.)
[RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
When [RST_RCV] = 0, the PERST*_L pin value is ignored.
This bit must not be changed in the same write that sets [RST_DRV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other.
If this bit is written while PERSTx_L pin is de-asserted then the MAC can come
out of reset unexpectedly. */
uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Controls whether PERST*_L is driven.
This field is always reinitialized on a cold domain reset.
The field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is cleared.
_ 1 when RST_CTL()[HOST_MODE] is set.
This bit must not be changed in the same write that sets [RST_RCV]=1; separate
writes to RST_CTL() are required to clear one bit and then set the other. */
uint64_t reserved_4_5 : 2;
uint64_t host_mode : 1; /**< [ 6: 6](RO/H) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Read-only access to the corresponding PEM()_CFG[HOSTMD] field
indicating PEMn is root complex (host). */
uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Link down / hot reset event internal reset enable.
0 = Link down or hot reset do not cause an internal reset.
1 = A link-down or hot-reset event on the PCIe interface causes the internal
reset specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a link-down or hot reset event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Reset done. Indicates the controller reset status. [RST_DONE] is always 0
(i.e. the controller is held in reset) when
* RST_SOFT_PRST()[SOFT_PRST] = 1, or
* [RST_RCV] = 1 and PERST*_L pin is asserted. */
uint64_t prst_link : 1; /**< [ 9: 9](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
PEM reset on link down.
0 = Link-down event will set RST_INT[RST_LINK] for the corresponding
controller, and (provided properly configured) the link should come back up
automatically.
1 = Link-down event detected by the PCIe logic causes the internal reset
specified by [RESET_TYPE].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
PF FLR internal reset enable.
0 = PF FLR events will not cause an internal reset.
1 = A PF FLR event received by the PCIe logic causes the internal reset
specified by [RESET_TYPE].
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 1.
_ 1 when RST_CTL()[HOST_MODE] = 0. */
uint64_t prst_pwrdwn : 1; /**< [ 11: 11](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
PEM reset on power down.
0 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for the
corresponding controller, and (provided properly configured) the link should
come back up automatically.
1 = PEM entering L2/P2 power state will set RST_INT[RST_PWRDWN] for
the corresponding controller and set RST_SOFT_PRST()[SOFT_PRST]. This will
hold the link in reset until software clears RST_SOFT_PRST()[SOFT_PRST].
A core/chip reset does not change this field. On cold reset, this field is
initialized to 0. */
uint64_t rst_pwrdwn : 1; /**< [ 12: 12](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Powerdown event internal reset enable.
0 = PEM going into powerdown (L2) does not cause an internal reset.
1 = PEM going into powerdown (L2) causes the internal reset
specified by [RESET_TYPE].
On a cold reset, the field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] is set.
_ 1 when RST_CTL()[HOST_MODE] is cleared.
Note that a powerdown event can never cause a domain reset when the
controller is already in reset (i.e. when [RST_DONE] = 0). */
uint64_t reset_type : 1; /**< [ 13: 13](R/W) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Type of reset generated internally by PCI MAC PF FLR, link down/hot reset, Powerdown or
PERST events. See [PF_FLR_CHIP], [RST_LINK], [RST_PWRDWN] and [RST_CHIP].
0 = Chip and core domain reset. (A chip domain reset always also causes a core
domain reset.)
1 = Core domain reset.
On cold reset, this field is initialized as follows:
_ 0 when RST_CTL()[HOST_MODE] = 0.
_ 1 when RST_CTL()[HOST_MODE] = 1. */
uint64_t reserved_14_63 : 50;
#endif /* Word 0 - End */
} cnf95xxp2;
};
typedef union cavm_rst_ctlx cavm_rst_ctlx_t;
static inline uint64_t CAVM_RST_CTLX(unsigned long a) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_CTLX(unsigned long a)
{
if (cavm_is_model(OCTEONTX_CN81XX) && (a<=2))
return 0x87e006001640ll + 8ll * ((a) & 0x3);
if (cavm_is_model(OCTEONTX_CN83XX) && (a<=3))
return 0x87e006001640ll + 8ll * ((a) & 0x3);
if (cavm_is_model(OCTEONTX_CN96XX_PASS1_X) && (a<=3))
return 0x87e006001640ll + 8ll * ((a) & 0x3);
if (cavm_is_model(OCTEONTX_CNF95XX) && (a==0))
return 0x87e006001640ll + 8ll * ((a) & 0x0);
__cavm_csr_fatal("RST_CTLX", 1, a, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_CTLX(a) cavm_rst_ctlx_t
#define bustype_CAVM_RST_CTLX(a) CSR_TYPE_RSL
#define basename_CAVM_RST_CTLX(a) "RST_CTLX"
#define device_bar_CAVM_RST_CTLX(a) 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_CTLX(a) (a)
#define arguments_CAVM_RST_CTLX(a) (a),-1,-1,-1
/**
* Register (RSL) rst_dbg_reset
*
* INTERNAL: RST Debug Logic Reset Register
*
* This register contains the reset control for each core's debug logic.
* Debug reset is not supported.
*/
union cavm_rst_dbg_reset
{
uint64_t u;
struct cavm_rst_dbg_reset_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_24_63 : 40;
uint64_t rst : 24; /**< [ 23: 0](R/W) Reserved. */
#else /* Word 0 - Little Endian */
uint64_t rst : 24; /**< [ 23: 0](R/W) Reserved. */
uint64_t reserved_24_63 : 40;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_dbg_reset_s cn8; */
struct cavm_rst_dbg_reset_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_4_63 : 60;
uint64_t rst : 4; /**< [ 3: 0](R/W) Reserved. */
#else /* Word 0 - Little Endian */
uint64_t rst : 4; /**< [ 3: 0](R/W) Reserved. */
uint64_t reserved_4_63 : 60;
#endif /* Word 0 - End */
} cn81xx;
/* struct cavm_rst_dbg_reset_s cn83xx; */
};
typedef union cavm_rst_dbg_reset cavm_rst_dbg_reset_t;
#define CAVM_RST_DBG_RESET CAVM_RST_DBG_RESET_FUNC()
static inline uint64_t CAVM_RST_DBG_RESET_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_DBG_RESET_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN8XXX))
return 0x87e006001750ll;
__cavm_csr_fatal("RST_DBG_RESET", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_DBG_RESET cavm_rst_dbg_reset_t
#define bustype_CAVM_RST_DBG_RESET CSR_TYPE_RSL
#define basename_CAVM_RST_DBG_RESET "RST_DBG_RESET"
#define device_bar_CAVM_RST_DBG_RESET 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_DBG_RESET 0
#define arguments_CAVM_RST_DBG_RESET -1,-1,-1,-1
/**
* Register (RSL) rst_debug
*
* RST Debug Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_debug
{
uint64_t u;
struct cavm_rst_debug_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_6_63 : 58;
uint64_t suspend_rstpwr : 1; /**< [ 5: 5](R/W) Stop RSTPWR bus.
Setting this field will stop AP resets from getting to the cores.
Clearing this field will restart communication starting with AP0.
This allows test sequences to predict AP resets with much greater accuracy.
For diagnostic and test use only.
This field is always reinitialized on a cold domain reset. */
uint64_t div_clk_rst : 1; /**< [ 4: 4](R/W) Forces Clock Divider Reset.
Setting this field will force fixed clock dividers into reset.
Clearing this field will enable clock dividers.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Currently only used in BPHY on f95n */
uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
Setting this field will force all DLLs to track clock changes.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
Setting this field will force all clocks on while they are in reset and
will dramatically increase power consumption.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Forces store-n-forward across clock domains. */
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on. For diagnostic use only. */
#else /* Word 0 - Little Endian */
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on. For diagnostic use only. */
uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Forces store-n-forward across clock domains. */
uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
Setting this field will force all clocks on while they are in reset and
will dramatically increase power consumption.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
Setting this field will force all DLLs to track clock changes.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t div_clk_rst : 1; /**< [ 4: 4](R/W) Forces Clock Divider Reset.
Setting this field will force fixed clock dividers into reset.
Clearing this field will enable clock dividers.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Currently only used in BPHY on f95n */
uint64_t suspend_rstpwr : 1; /**< [ 5: 5](R/W) Stop RSTPWR bus.
Setting this field will stop AP resets from getting to the cores.
Clearing this field will restart communication starting with AP0.
This allows test sequences to predict AP resets with much greater accuracy.
For diagnostic and test use only.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_6_63 : 58;
#endif /* Word 0 - End */
} s;
struct cavm_rst_debug_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on. For diagnostic use only. */
#else /* Word 0 - Little Endian */
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on. For diagnostic use only. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_debug_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_6_63 : 58;
uint64_t suspend_rstpwr : 1; /**< [ 5: 5](R/W) Stop RSTPWR bus.
Setting this field will stop AP resets from getting to the cores.
Clearing this field will restart communication starting with AP0.
This allows test sequences to predict AP resets with much greater accuracy.
For diagnostic and test use only.
This field is always reinitialized on a cold domain reset. */
uint64_t div_clk_rst : 1; /**< [ 4: 4](R/W) Forces Clock Divider Reset.
Setting this field will force fixed clock dividers into reset.
Clearing this field will enable clock dividers.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Currently only used in BPHY on f95n */
uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
Setting this field will force all DLLs to track clock changes.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
Setting this field will force all clocks on while they are in reset and
will dramatically increase power consumption.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Forces store-n-forward across clock domains. */
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Forces store-n-forward across clock domains. */
uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
Setting this field will force all clocks on while they are in reset and
will dramatically increase power consumption.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
Setting this field will force all DLLs to track clock changes.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t div_clk_rst : 1; /**< [ 4: 4](R/W) Forces Clock Divider Reset.
Setting this field will force fixed clock dividers into reset.
Clearing this field will enable clock dividers.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Currently only used in BPHY on f95n */
uint64_t suspend_rstpwr : 1; /**< [ 5: 5](R/W) Stop RSTPWR bus.
Setting this field will stop AP resets from getting to the cores.
Clearing this field will restart communication starting with AP0.
This allows test sequences to predict AP resets with much greater accuracy.
For diagnostic and test use only.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_6_63 : 58;
#endif /* Word 0 - End */
} cn9;
struct cavm_rst_debug_cn96xxp1
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_4_63 : 60;
uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
Setting this field will force all DLLs to track clock changes.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
Setting this field will force all clocks on while they are in reset and
will dramatically increase power consumption.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Forces store-n-forward across clock domains. */
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Forces store-n-forward across clock domains. */
uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
Setting this field will force all clocks on while they are in reset and
will dramatically increase power consumption.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
Setting this field will force all DLLs to track clock changes.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_4_63 : 60;
#endif /* Word 0 - End */
} cn96xxp1;
struct cavm_rst_debug_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_6_63 : 58;
uint64_t suspend_rstpwr : 1; /**< [ 5: 5](R/W) Stop RSTPWR bus.
Setting this field will stop AP resets from getting to the cores.
Clearing this field will restart communication starting with AP0.
This allows test sequences to predict AP resets with much greater accuracy.
For diagnostic and test use only.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_4 : 1;
uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
Setting this field will force all DLLs to track clock changes.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
Setting this field will force all clocks on while they are in reset and
will dramatically increase power consumption.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Forces store-n-forward across clock domains. */
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Forces store-n-forward across clock domains. */
uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
Setting this field will force all clocks on while they are in reset and
will dramatically increase power consumption.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
Setting this field will force all DLLs to track clock changes.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_4 : 1;
uint64_t suspend_rstpwr : 1; /**< [ 5: 5](R/W) Stop RSTPWR bus.
Setting this field will stop AP resets from getting to the cores.
Clearing this field will restart communication starting with AP0.
This allows test sequences to predict AP resets with much greater accuracy.
For diagnostic and test use only.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_6_63 : 58;
#endif /* Word 0 - End */
} cn96xxp3;
/* struct cavm_rst_debug_cn96xxp3 cn98xx; */
/* struct cavm_rst_debug_cn96xxp1 cnf95xx; */
struct cavm_rst_debug_loki
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_6_63 : 58;
uint64_t suspend_rstpwr : 1; /**< [ 5: 5](R/W) Stop RSTPWR bus.
Setting this field will stop AP resets from getting to the cores.
Clearing this field will restart communication starting with AP0.
This will allow test sequences to predict AP resets with much greater accuracy.
For diagnostic and test use only.
This field is always reinitialized on a cold domain reset. */
uint64_t div_clk_rst : 1; /**< [ 4: 4](R/W) Forces Clock Divider Reset.
Setting this field will force fixed clock dividers into reset.
Clearing this field will enable clock dividers.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Currently only used in BPHY on f95n */
uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
Setting this field will force all DLLs to track clock changes.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
Setting this field will force all clocks on while they are in reset and
will dramatically increase power consumption.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Forces store-n-forward across clock domains. */
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Forces store-n-forward across clock domains. */
uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
Setting this field will force all clocks on while they are in reset and
will dramatically increase power consumption.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
Setting this field will force all DLLs to track clock changes.
For diagnostic use only.
This field is always reinitialized on a cold domain reset. */
uint64_t div_clk_rst : 1; /**< [ 4: 4](R/W) Forces Clock Divider Reset.
Setting this field will force fixed clock dividers into reset.
Clearing this field will enable clock dividers.
For diagnostic use only.
This field is always reinitialized on a cold domain reset.
Internal:
Currently only used in BPHY on f95n */
uint64_t suspend_rstpwr : 1; /**< [ 5: 5](R/W) Stop RSTPWR bus.
Setting this field will stop AP resets from getting to the cores.
Clearing this field will restart communication starting with AP0.
This will allow test sequences to predict AP resets with much greater accuracy.
For diagnostic and test use only.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_6_63 : 58;
#endif /* Word 0 - End */
} loki;
};
typedef union cavm_rst_debug cavm_rst_debug_t;
#define CAVM_RST_DEBUG CAVM_RST_DEBUG_FUNC()
static inline uint64_t CAVM_RST_DEBUG_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_DEBUG_FUNC(void)
{
return 0x87e0060017b0ll;
}
#define typedef_CAVM_RST_DEBUG cavm_rst_debug_t
#define bustype_CAVM_RST_DEBUG CSR_TYPE_RSL
#define basename_CAVM_RST_DEBUG "RST_DEBUG"
#define device_bar_CAVM_RST_DEBUG 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_DEBUG 0
#define arguments_CAVM_RST_DEBUG -1,-1,-1,-1
/**
* Register (RSL) rst_delay
*
* RST Delay Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_delay
{
uint64_t u;
struct cavm_rst_delay_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_32_63 : 32;
uint64_t warm_rst_dly : 16; /**< [ 31: 16](R/W) Warm reset delay. A warm reset immediately causes an early warm-reset notification, but
the assertion of warm reset is delayed this many coprocessor-clock cycles. A warm/soft
reset does not change this field.
This must be at least 0x200 coprocessor-clock cycles. */
uint64_t reserved_0_15 : 16;
#else /* Word 0 - Little Endian */
uint64_t reserved_0_15 : 16;
uint64_t warm_rst_dly : 16; /**< [ 31: 16](R/W) Warm reset delay. A warm reset immediately causes an early warm-reset notification, but
the assertion of warm reset is delayed this many coprocessor-clock cycles. A warm/soft
reset does not change this field.
This must be at least 0x200 coprocessor-clock cycles. */
uint64_t reserved_32_63 : 32;
#endif /* Word 0 - End */
} s;
struct cavm_rst_delay_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_32_63 : 32;
uint64_t warm_rst_dly : 16; /**< [ 31: 16](R/W) Warm reset delay. A warm reset immediately causes an early warm-reset notification, but
the assertion of warm reset is delayed this many coprocessor-clock cycles. A warm/soft
reset does not change this field.
This must be at least 0x200 coprocessor-clock cycles. */
uint64_t soft_rst_dly : 16; /**< [ 15: 0](R/W) Soft reset delay. A soft reset immediately causes an early soft-reset notification, but
the assertion of soft reset is delayed this many coprocessor-clock cycles. A warm/soft
reset does not change this field.
This must be at least 0x200 coprocessor-clock cycles. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst_dly : 16; /**< [ 15: 0](R/W) Soft reset delay. A soft reset immediately causes an early soft-reset notification, but
the assertion of soft reset is delayed this many coprocessor-clock cycles. A warm/soft
reset does not change this field.
This must be at least 0x200 coprocessor-clock cycles. */
uint64_t warm_rst_dly : 16; /**< [ 31: 16](R/W) Warm reset delay. A warm reset immediately causes an early warm-reset notification, but
the assertion of warm reset is delayed this many coprocessor-clock cycles. A warm/soft
reset does not change this field.
This must be at least 0x200 coprocessor-clock cycles. */
uint64_t reserved_32_63 : 32;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_delay_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_16_63 : 48;
uint64_t rst_dly : 16; /**< [ 15: 0](R/W) Reset delay. Chip and core domain resets immediately causes an early reset
notification to the DDR interface. The assertion of the domain reset is delayed
by this many 100 MHz PLL reference clocks. The minimum value is 1 uS.
Typical value is 4 uS once DDR has been initialized.
This field is reinitialized with a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t rst_dly : 16; /**< [ 15: 0](R/W) Reset delay. Chip and core domain resets immediately causes an early reset
notification to the DDR interface. The assertion of the domain reset is delayed
by this many 100 MHz PLL reference clocks. The minimum value is 1 uS.
Typical value is 4 uS once DDR has been initialized.
This field is reinitialized with a cold domain reset. */
uint64_t reserved_16_63 : 48;
#endif /* Word 0 - End */
} cn9;
/* struct cavm_rst_delay_cn9 cn96xxp1; */
struct cavm_rst_delay_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_16_63 : 48;
uint64_t rst_dly : 16; /**< [ 15: 0](R/W) Reset delay. Chip and core domain resets immediately causes an early reset
notification to the DDR interface. The assertion of the domain reset is delayed
by this many 100 MHz PLL reference clocks. The minimum value is 1 uS.
Typical value is 5 uS once core domain has been brought out of reset.
This field is reinitialized with a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t rst_dly : 16; /**< [ 15: 0](R/W) Reset delay. Chip and core domain resets immediately causes an early reset
notification to the DDR interface. The assertion of the domain reset is delayed
by this many 100 MHz PLL reference clocks. The minimum value is 1 uS.
Typical value is 5 uS once core domain has been brought out of reset.
This field is reinitialized with a cold domain reset. */
uint64_t reserved_16_63 : 48;
#endif /* Word 0 - End */
} cn96xxp3;
/* struct cavm_rst_delay_cn96xxp3 cn98xx; */
/* struct cavm_rst_delay_cn96xxp3 cnf95xx; */
/* struct cavm_rst_delay_cn96xxp3 loki; */
};
typedef union cavm_rst_delay cavm_rst_delay_t;
#define CAVM_RST_DELAY CAVM_RST_DELAY_FUNC()
static inline uint64_t CAVM_RST_DELAY_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_DELAY_FUNC(void)
{
return 0x87e006001608ll;
}
#define typedef_CAVM_RST_DELAY cavm_rst_delay_t
#define bustype_CAVM_RST_DELAY CSR_TYPE_RSL
#define basename_CAVM_RST_DELAY "RST_DELAY"
#define device_bar_CAVM_RST_DELAY 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_DELAY 0
#define arguments_CAVM_RST_DELAY -1,-1,-1,-1
/**
* Register (RSL) rst_dev_map#
*
* RST Device Map Register
* This register configures the reset domain of devices. Index {a} is enumerated by RST_DEV_E.
* Writes to these registers should only occur when all the bits of RST_BIST_ACTIVE are clear.
* See RST_BIST_ACTIVE for details.
* Only one RST_DEV_MAP() should be written at a time.
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_dev_mapx
{
uint64_t u;
struct cavm_rst_dev_mapx_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_3_63 : 61;
uint64_t dmn : 3; /**< [ 2: 0](R/W) Map of programmable devices to reset domains. When the specified domain reset
occurs the corresponding device will reset. Devices are numbered according to
RST_DEV_E.
GSERs should be mapped to the same domain as the PEM, CGX or NCSI device they are
associated with.
If any PCIEx_EP_STRAP is set then all RST_DEV_MAP(GSERx) are mapped to chip reset.
See RST_DOMAIN_E for field encodings.
This field is always reinitialized on a cold domain reset.
Internal:
RST_DEV_MAP()[DMN] resets to core domain for everything except AVS, EMM, MPI\<1:0\>
and NCSI which reset to SCP domain, and GSER which are set to chip in EP mode.
This is based on cold reset so software could e.g. choose to put a PEM GSER into
endpoint based on knowledge outside the straps (that RST uses to reset this
table). */
#else /* Word 0 - Little Endian */
uint64_t dmn : 3; /**< [ 2: 0](R/W) Map of programmable devices to reset domains. When the specified domain reset
occurs the corresponding device will reset. Devices are numbered according to
RST_DEV_E.
GSERs should be mapped to the same domain as the PEM, CGX or NCSI device they are
associated with.
If any PCIEx_EP_STRAP is set then all RST_DEV_MAP(GSERx) are mapped to chip reset.
See RST_DOMAIN_E for field encodings.
This field is always reinitialized on a cold domain reset.
Internal:
RST_DEV_MAP()[DMN] resets to core domain for everything except AVS, EMM, MPI\<1:0\>
and NCSI which reset to SCP domain, and GSER which are set to chip in EP mode.
This is based on cold reset so software could e.g. choose to put a PEM GSER into
endpoint based on knowledge outside the straps (that RST uses to reset this
table). */
uint64_t reserved_3_63 : 61;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_dev_mapx_s cn; */
};
typedef union cavm_rst_dev_mapx cavm_rst_dev_mapx_t;
static inline uint64_t CAVM_RST_DEV_MAPX(unsigned long a) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_DEV_MAPX(unsigned long a)
{
if (cavm_is_model(OCTEONTX_CN9XXX) && (a<=47))
return 0x87e00a001a00ll + 8ll * ((a) & 0x3f);
__cavm_csr_fatal("RST_DEV_MAPX", 1, a, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_DEV_MAPX(a) cavm_rst_dev_mapx_t
#define bustype_CAVM_RST_DEV_MAPX(a) CSR_TYPE_RSL
#define basename_CAVM_RST_DEV_MAPX(a) "RST_DEV_MAPX"
#define device_bar_CAVM_RST_DEV_MAPX(a) 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_DEV_MAPX(a) (a)
#define arguments_CAVM_RST_DEV_MAPX(a) (a),-1,-1,-1
/**
* Register (RSL) rst_dsp_pll
*
* RST DSP Clock PLL Control Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_dsp_pll
{
uint64_t u;
struct cavm_rst_dsp_pll_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) DSP clockout select.
0x0 = DSP clock divided by 32.
0x1 = DSP clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) DSP clockout reset. The dsp clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occured.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 bclk/dsp_clk/sclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) DSP PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) DSP PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) DSP clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[DSP_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) DSP PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[DSP_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) DSP clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[DSP_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) DSP clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[DSP_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) DSP PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[DSP_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) DSP clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[DSP_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) DSP PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) DSP PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 bclk/dsp_clk/sclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occured.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) DSP clockout reset. The dsp clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) DSP clockout select.
0x0 = DSP clock divided by 32.
0x1 = DSP clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_dsp_pll_s cn9; */
/* struct cavm_rst_dsp_pll_s cnf95xxp1; */
struct cavm_rst_dsp_pll_cnf95xxp2
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) DSP clockout select.
0x0 = DSP clock divided by 32.
0x1 = DSP clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) DSP clockout reset. The DSP clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occured.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 bclk/dsp_clk/sclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) DSP PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) DSP PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) DSP clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[DSP_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) DSP PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[DSP_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) DSP clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[DSP_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) DSP clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[DSP_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) DSP PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[DSP_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) DSP clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[DSP_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) DSP PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) DSP PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 bclk/dsp_clk/sclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occured.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) DSP clockout reset. The DSP clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) DSP clockout select.
0x0 = DSP clock divided by 32.
0x1 = DSP clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cnf95xxp2;
/* struct cavm_rst_dsp_pll_cnf95xxp2 loki; */
};
typedef union cavm_rst_dsp_pll cavm_rst_dsp_pll_t;
#define CAVM_RST_DSP_PLL CAVM_RST_DSP_PLL_FUNC()
static inline uint64_t CAVM_RST_DSP_PLL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_DSP_PLL_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CNF95XX))
return 0x87e00a001770ll;
if (cavm_is_model(OCTEONTX_LOKI))
return 0x87e00a001770ll;
__cavm_csr_fatal("RST_DSP_PLL", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_DSP_PLL cavm_rst_dsp_pll_t
#define bustype_CAVM_RST_DSP_PLL CSR_TYPE_RSL
#define basename_CAVM_RST_DSP_PLL "RST_DSP_PLL"
#define device_bar_CAVM_RST_DSP_PLL 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_DSP_PLL 0
#define arguments_CAVM_RST_DSP_PLL -1,-1,-1,-1
/**
* Register (RSL) rst_eco
*
* INTERNAL: RST ECO Register
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_eco
{
uint64_t u;
struct cavm_rst_eco_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_32_63 : 32;
uint64_t eco_rw : 32; /**< [ 31: 0](R/W) ECO flops. */
#else /* Word 0 - Little Endian */
uint64_t eco_rw : 32; /**< [ 31: 0](R/W) ECO flops. */
uint64_t reserved_32_63 : 32;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_eco_s cn8; */
struct cavm_rst_eco_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_32_63 : 32;
uint64_t eco_rw : 32; /**< [ 31: 0](R/W) ECO flops.
This field is always reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t eco_rw : 32; /**< [ 31: 0](R/W) ECO flops.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_32_63 : 32;
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_eco cavm_rst_eco_t;
#define CAVM_RST_ECO CAVM_RST_ECO_FUNC()
static inline uint64_t CAVM_RST_ECO_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_ECO_FUNC(void)
{
return 0x87e0060017b8ll;
}
#define typedef_CAVM_RST_ECO cavm_rst_eco_t
#define bustype_CAVM_RST_ECO CSR_TYPE_RSL
#define basename_CAVM_RST_ECO "RST_ECO"
#define device_bar_CAVM_RST_ECO 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_ECO 0
#define arguments_CAVM_RST_ECO -1,-1,-1,-1
/**
* Register (RSL) rst_gclk_pll
*
* RST GSERR Clock PLL Control Register
* This register should only be programmed while GSERR logic is in reset.
* It is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_gclk_pll
{
uint64_t u;
struct cavm_rst_gclk_pll_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_16_63 : 48;
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Programs the active PLL using [NXT_MUL]. Hardware automatically
clears bit when PLL has been updated. Software should wait at least 20uS
for clock frequency to be reached before releasing GSERRs from reset.
This field is always reinitialized on a chip domain reset.
Changing GCLK frequency is for diagnostic use only; changes can only be made
while all GSERR are in reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) GSERR PLL frequency to be program in 50 MHz increments. The
actual value must be in the range between 200 MHz and 600 MHz.
Value will be 400 MHz immediately after a cold domain reset. */
uint64_t reserved_7 : 1;
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) GSERR clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [NXT_PGM] has been set or 400 MHz
immediately after a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) GSERR clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [NXT_PGM] has been set or 400 MHz
immediately after a cold domain reset. */
uint64_t reserved_7 : 1;
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) GSERR PLL frequency to be program in 50 MHz increments. The
actual value must be in the range between 200 MHz and 600 MHz.
Value will be 400 MHz immediately after a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Programs the active PLL using [NXT_MUL]. Hardware automatically
clears bit when PLL has been updated. Software should wait at least 20uS
for clock frequency to be reached before releasing GSERRs from reset.
This field is always reinitialized on a chip domain reset.
Changing GCLK frequency is for diagnostic use only; changes can only be made
while all GSERR are in reset. */
uint64_t reserved_16_63 : 48;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_gclk_pll_s cn9; */
/* struct cavm_rst_gclk_pll_s cn96xx; */
/* struct cavm_rst_gclk_pll_s cn98xx; */
/* struct cavm_rst_gclk_pll_s cnf95xx; */
struct cavm_rst_gclk_pll_loki
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_16_63 : 48;
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Programs the active PLL using [NXT_MUL]. Hardware automatically
clears bit when PLL has been updated. Software should wait at least 20uS
for clock frequency to be reached before releasing RFIFs from reset.
This field is always reinitialized on a chip domain reset.
Changing GSERR Clock frequency is for diagnostic use only; changes can only be made
while GSERR logic is in reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) GSERR PLL frequency to be program in 50 MHz increments. The
actual value must be in the range between 200 MHz and 600 MHz.
Value will be 400 MHz immediately after a cold domain reset. */
uint64_t reserved_7 : 1;
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) GSERR clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [NXT_PGM] has been set or 400 MHz
immediately after a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) GSERR clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [NXT_PGM] has been set or 400 MHz
immediately after a cold domain reset. */
uint64_t reserved_7 : 1;
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) GSERR PLL frequency to be program in 50 MHz increments. The
actual value must be in the range between 200 MHz and 600 MHz.
Value will be 400 MHz immediately after a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Programs the active PLL using [NXT_MUL]. Hardware automatically
clears bit when PLL has been updated. Software should wait at least 20uS
for clock frequency to be reached before releasing RFIFs from reset.
This field is always reinitialized on a chip domain reset.
Changing GSERR Clock frequency is for diagnostic use only; changes can only be made
while GSERR logic is in reset. */
uint64_t reserved_16_63 : 48;
#endif /* Word 0 - End */
} loki;
};
typedef union cavm_rst_gclk_pll cavm_rst_gclk_pll_t;
#define CAVM_RST_GCLK_PLL CAVM_RST_GCLK_PLL_FUNC()
static inline uint64_t CAVM_RST_GCLK_PLL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_GCLK_PLL_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN96XX_PASS3_X))
return 0x87e00a0017f8ll;
if (cavm_is_model(OCTEONTX_CN98XX))
return 0x87e00a0017f8ll;
if (cavm_is_model(OCTEONTX_CNF95XX_PASS2_X))
return 0x87e00a0017f8ll;
if (cavm_is_model(OCTEONTX_LOKI))
return 0x87e00a0017f8ll;
__cavm_csr_fatal("RST_GCLK_PLL", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_GCLK_PLL cavm_rst_gclk_pll_t
#define bustype_CAVM_RST_GCLK_PLL CSR_TYPE_RSL
#define basename_CAVM_RST_GCLK_PLL "RST_GCLK_PLL"
#define device_bar_CAVM_RST_GCLK_PLL 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_GCLK_PLL 0
#define arguments_CAVM_RST_GCLK_PLL -1,-1,-1,-1
/**
* Register (RSL) rst_int
*
* RST Interrupt Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_int
{
uint64_t u;
struct cavm_rst_int_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) BPHY domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) A controller power down (PEM in L2 state) occurred while RST_CTL()[RST_PWRDWN] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_4_31 : 28;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
uint64_t reserved_4_31 : 28;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) A controller power down (PEM in L2 state) occurred while RST_CTL()[RST_PWRDWN] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) BPHY domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} s;
struct cavm_rst_int_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_12_63 : 52;
uint64_t perst : 4; /**< [ 11: 8](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
corresponds to each controller. */
uint64_t reserved_4_7 : 4;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
uint64_t reserved_4_7 : 4;
uint64_t perst : 4; /**< [ 11: 8](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
corresponds to each controller. */
uint64_t reserved_12_63 : 52;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_int_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_11_63 : 53;
uint64_t perst : 3; /**< [ 10: 8](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
corresponds to each controller. */
uint64_t reserved_3_7 : 5;
uint64_t rst_link : 3; /**< [ 2: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 3; /**< [ 2: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
uint64_t reserved_3_7 : 5;
uint64_t perst : 3; /**< [ 10: 8](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
corresponds to each controller. */
uint64_t reserved_11_63 : 53;
#endif /* Word 0 - End */
} cn81xx;
/* struct cavm_rst_int_cn8 cn83xx; */
struct cavm_rst_int_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) BPHY domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) A controller power down (PEM in L2 state) occurred while RST_CTL()[RST_PWRDWN] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_20_31 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_4_15 : 12;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_4_15 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_20_31 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) A controller power down (PEM in L2 state) occurred while RST_CTL()[RST_PWRDWN] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) BPHY domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} cn9;
struct cavm_rst_int_cn96xxp1
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) A controller power down (PEM in L2 state) occurred while RST_CTL()[RST_PWRDWN] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_20_31 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_4_15 : 12;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_4_15 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_20_31 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) A controller power down (PEM in L2 state) occurred while RST_CTL()[RST_PWRDWN] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cn96xxp1;
struct cavm_rst_int_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_0_47 : 48;
#else /* Word 0 - Little Endian */
uint64_t reserved_0_47 : 48;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cn96xxp3;
/* struct cavm_rst_int_cn96xxp3 cn98xx; */
struct cavm_rst_int_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) BPHY domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_33_47 : 15;
uint64_t rst_pwrdwn : 1; /**< [ 32: 32](R/W1C/H) A controller power down (PEM in L2 state) occurred while RST_CTL()[RST_PWRDWN] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_17_31 : 15;
uint64_t perst : 1; /**< [ 16: 16](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_1_15 : 15;
uint64_t rst_link : 1; /**< [ 0: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 1; /**< [ 0: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_1_15 : 15;
uint64_t perst : 1; /**< [ 16: 16](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_17_31 : 15;
uint64_t rst_pwrdwn : 1; /**< [ 32: 32](R/W1C/H) A controller power down (PEM in L2 state) occurred while RST_CTL()[RST_PWRDWN] = 0. Software must
assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_33_47 : 15;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) BPHY domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} cnf95xx;
struct cavm_rst_int_loki
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) BPHY domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_0_47 : 48;
#else /* Word 0 - Little Endian */
uint64_t reserved_0_47 : 48;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Core domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) MCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) SCP domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) BPHY domain entered reset.
This field is reinitialized with a chip domain reset. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} loki;
};
typedef union cavm_rst_int cavm_rst_int_t;
#define CAVM_RST_INT CAVM_RST_INT_FUNC()
static inline uint64_t CAVM_RST_INT_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_INT_FUNC(void)
{
return 0x87e006001628ll;
}
#define typedef_CAVM_RST_INT cavm_rst_int_t
#define bustype_CAVM_RST_INT CSR_TYPE_RSL
#define basename_CAVM_RST_INT "RST_INT"
#define device_bar_CAVM_RST_INT 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_INT 0
#define arguments_CAVM_RST_INT -1,-1,-1,-1
/**
* Register (RSL) rst_int_ena_w1c
*
* RST Interrupt Enable Clear Register
* This register clears interrupt enable bits.
*/
union cavm_rst_int_ena_w1c
{
uint64_t u;
struct cavm_rst_int_ena_w1c_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) Reads or clears enable for RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) Reads or clears enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_4_31 : 28;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
uint64_t reserved_4_31 : 28;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) Reads or clears enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) Reads or clears enable for RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} s;
struct cavm_rst_int_ena_w1c_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_12_63 : 52;
uint64_t perst : 4; /**< [ 11: 8](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
uint64_t reserved_4_7 : 4;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
uint64_t reserved_4_7 : 4;
uint64_t perst : 4; /**< [ 11: 8](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
uint64_t reserved_12_63 : 52;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_int_ena_w1c_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_11_63 : 53;
uint64_t perst : 3; /**< [ 10: 8](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
uint64_t reserved_3_7 : 5;
uint64_t rst_link : 3; /**< [ 2: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 3; /**< [ 2: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
uint64_t reserved_3_7 : 5;
uint64_t perst : 3; /**< [ 10: 8](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
uint64_t reserved_11_63 : 53;
#endif /* Word 0 - End */
} cn81xx;
/* struct cavm_rst_int_ena_w1c_cn8 cn83xx; */
struct cavm_rst_int_ena_w1c_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) Reads or clears enable for RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) Reads or clears enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_20_31 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
uint64_t reserved_4_15 : 12;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
uint64_t reserved_4_15 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
uint64_t reserved_20_31 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) Reads or clears enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) Reads or clears enable for RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} cn9;
struct cavm_rst_int_ena_w1c_cn96xxp1
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) Reads or clears enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_20_31 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
uint64_t reserved_4_15 : 12;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
uint64_t reserved_4_15 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
uint64_t reserved_20_31 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1C/H) Reads or clears enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cn96xxp1;
struct cavm_rst_int_ena_w1c_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t reserved_0_47 : 48;
#else /* Word 0 - Little Endian */
uint64_t reserved_0_47 : 48;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cn96xxp3;
/* struct cavm_rst_int_ena_w1c_cn96xxp3 cn98xx; */
struct cavm_rst_int_ena_w1c_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) Reads or clears enable for RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t reserved_33_47 : 15;
uint64_t rst_pwrdwn : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_17_31 : 15;
uint64_t perst : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
uint64_t reserved_1_15 : 15;
uint64_t rst_link : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
uint64_t reserved_1_15 : 15;
uint64_t perst : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
uint64_t reserved_17_31 : 15;
uint64_t rst_pwrdwn : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_33_47 : 15;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) Reads or clears enable for RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} cnf95xx;
struct cavm_rst_int_ena_w1c_loki
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) Reads or clears enable for RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t reserved_0_47 : 48;
#else /* Word 0 - Little Endian */
uint64_t reserved_0_47 : 48;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1C/H) Reads or clears enable for RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} loki;
};
typedef union cavm_rst_int_ena_w1c cavm_rst_int_ena_w1c_t;
#define CAVM_RST_INT_ENA_W1C CAVM_RST_INT_ENA_W1C_FUNC()
static inline uint64_t CAVM_RST_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_INT_ENA_W1C_FUNC(void)
{
return 0x87e0060016a8ll;
}
#define typedef_CAVM_RST_INT_ENA_W1C cavm_rst_int_ena_w1c_t
#define bustype_CAVM_RST_INT_ENA_W1C CSR_TYPE_RSL
#define basename_CAVM_RST_INT_ENA_W1C "RST_INT_ENA_W1C"
#define device_bar_CAVM_RST_INT_ENA_W1C 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_INT_ENA_W1C 0
#define arguments_CAVM_RST_INT_ENA_W1C -1,-1,-1,-1
/**
* Register (RSL) rst_int_ena_w1s
*
* RST Interrupt Enable Set Register
* This register sets interrupt enable bits.
*/
union cavm_rst_int_ena_w1s
{
uint64_t u;
struct cavm_rst_int_ena_w1s_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets enable for RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_4_31 : 28;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
uint64_t reserved_4_31 : 28;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets enable for RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} s;
struct cavm_rst_int_ena_w1s_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_12_63 : 52;
uint64_t perst : 4; /**< [ 11: 8](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
uint64_t reserved_4_7 : 4;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
uint64_t reserved_4_7 : 4;
uint64_t perst : 4; /**< [ 11: 8](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
uint64_t reserved_12_63 : 52;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_int_ena_w1s_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_11_63 : 53;
uint64_t perst : 3; /**< [ 10: 8](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
uint64_t reserved_3_7 : 5;
uint64_t rst_link : 3; /**< [ 2: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 3; /**< [ 2: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
uint64_t reserved_3_7 : 5;
uint64_t perst : 3; /**< [ 10: 8](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
uint64_t reserved_11_63 : 53;
#endif /* Word 0 - End */
} cn81xx;
/* struct cavm_rst_int_ena_w1s_cn8 cn83xx; */
struct cavm_rst_int_ena_w1s_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets enable for RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_20_31 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
uint64_t reserved_4_15 : 12;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
uint64_t reserved_4_15 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
uint64_t reserved_20_31 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets enable for RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} cn9;
struct cavm_rst_int_ena_w1s_cn96xxp1
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_20_31 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
uint64_t reserved_4_15 : 12;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
uint64_t reserved_4_15 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
uint64_t reserved_20_31 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cn96xxp1;
struct cavm_rst_int_ena_w1s_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t reserved_0_47 : 48;
#else /* Word 0 - Little Endian */
uint64_t reserved_0_47 : 48;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cn96xxp3;
/* struct cavm_rst_int_ena_w1s_cn96xxp3 cn98xx; */
struct cavm_rst_int_ena_w1s_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets enable for RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t reserved_33_47 : 15;
uint64_t rst_pwrdwn : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_17_31 : 15;
uint64_t perst : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
uint64_t reserved_1_15 : 15;
uint64_t rst_link : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
uint64_t reserved_1_15 : 15;
uint64_t perst : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
uint64_t reserved_17_31 : 15;
uint64_t rst_pwrdwn : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for RST_INT[RST_PWRDWN]. */
uint64_t reserved_33_47 : 15;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets enable for RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} cnf95xx;
struct cavm_rst_int_ena_w1s_loki
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets enable for RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t reserved_0_47 : 48;
#else /* Word 0 - Little Endian */
uint64_t reserved_0_47 : 48;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets enable for RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} loki;
};
typedef union cavm_rst_int_ena_w1s cavm_rst_int_ena_w1s_t;
#define CAVM_RST_INT_ENA_W1S CAVM_RST_INT_ENA_W1S_FUNC()
static inline uint64_t CAVM_RST_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_INT_ENA_W1S_FUNC(void)
{
return 0x87e0060016a0ll;
}
#define typedef_CAVM_RST_INT_ENA_W1S cavm_rst_int_ena_w1s_t
#define bustype_CAVM_RST_INT_ENA_W1S CSR_TYPE_RSL
#define basename_CAVM_RST_INT_ENA_W1S "RST_INT_ENA_W1S"
#define device_bar_CAVM_RST_INT_ENA_W1S 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_INT_ENA_W1S 0
#define arguments_CAVM_RST_INT_ENA_W1S -1,-1,-1,-1
/**
* Register (RSL) rst_int_w1s
*
* RST Interrupt Set Register
* This register sets interrupt bits.
*/
union cavm_rst_int_w1s
{
uint64_t u;
struct cavm_rst_int_w1s_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets RST_INT[RST_PWRDWN]. */
uint64_t reserved_4_31 : 28;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
uint64_t reserved_4_31 : 28;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets RST_INT[RST_PWRDWN]. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} s;
struct cavm_rst_int_w1s_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_12_63 : 52;
uint64_t perst : 4; /**< [ 11: 8](R/W1S/H) Reads or sets RST_INT[PERST]. */
uint64_t reserved_4_7 : 4;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
uint64_t reserved_4_7 : 4;
uint64_t perst : 4; /**< [ 11: 8](R/W1S/H) Reads or sets RST_INT[PERST]. */
uint64_t reserved_12_63 : 52;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_int_w1s_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_11_63 : 53;
uint64_t perst : 3; /**< [ 10: 8](R/W1S/H) Reads or sets RST_INT[PERST]. */
uint64_t reserved_3_7 : 5;
uint64_t rst_link : 3; /**< [ 2: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 3; /**< [ 2: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
uint64_t reserved_3_7 : 5;
uint64_t perst : 3; /**< [ 10: 8](R/W1S/H) Reads or sets RST_INT[PERST]. */
uint64_t reserved_11_63 : 53;
#endif /* Word 0 - End */
} cn81xx;
/* struct cavm_rst_int_w1s_cn8 cn83xx; */
struct cavm_rst_int_w1s_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets RST_INT[RST_PWRDWN]. */
uint64_t reserved_20_31 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets RST_INT[PERST]. */
uint64_t reserved_4_15 : 12;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
uint64_t reserved_4_15 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets RST_INT[PERST]. */
uint64_t reserved_20_31 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets RST_INT[RST_PWRDWN]. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} cn9;
struct cavm_rst_int_w1s_cn96xxp1
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t reserved_36_47 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets RST_INT[RST_PWRDWN]. */
uint64_t reserved_20_31 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets RST_INT[PERST]. */
uint64_t reserved_4_15 : 12;
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
uint64_t reserved_4_15 : 12;
uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets RST_INT[PERST]. */
uint64_t reserved_20_31 : 12;
uint64_t rst_pwrdwn : 4; /**< [ 35: 32](R/W1S/H) Reads or sets RST_INT[RST_PWRDWN]. */
uint64_t reserved_36_47 : 12;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cn96xxp1;
struct cavm_rst_int_w1s_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t reserved_0_47 : 48;
#else /* Word 0 - Little Endian */
uint64_t reserved_0_47 : 48;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cn96xxp3;
/* struct cavm_rst_int_w1s_cn96xxp3 cn98xx; */
struct cavm_rst_int_w1s_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t reserved_33_47 : 15;
uint64_t rst_pwrdwn : 1; /**< [ 32: 32](R/W1S/H) Reads or sets RST_INT[RST_PWRDWN]. */
uint64_t reserved_17_31 : 15;
uint64_t perst : 1; /**< [ 16: 16](R/W1S/H) Reads or sets RST_INT[PERST]. */
uint64_t reserved_1_15 : 15;
uint64_t rst_link : 1; /**< [ 0: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 1; /**< [ 0: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
uint64_t reserved_1_15 : 15;
uint64_t perst : 1; /**< [ 16: 16](R/W1S/H) Reads or sets RST_INT[PERST]. */
uint64_t reserved_17_31 : 15;
uint64_t rst_pwrdwn : 1; /**< [ 32: 32](R/W1S/H) Reads or sets RST_INT[RST_PWRDWN]. */
uint64_t reserved_33_47 : 15;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} cnf95xx;
struct cavm_rst_int_w1s_loki
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_52_63 : 12;
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets RST_INT[BPHY_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t reserved_0_47 : 48;
#else /* Word 0 - Little Endian */
uint64_t reserved_0_47 : 48;
uint64_t core_reset : 1; /**< [ 48: 48](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
uint64_t mcp_reset : 1; /**< [ 49: 49](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
uint64_t scp_reset : 1; /**< [ 50: 50](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
uint64_t bphy_reset : 1; /**< [ 51: 51](R/W1S/H) Reads or sets RST_INT[BPHY_RESET]. */
uint64_t reserved_52_63 : 12;
#endif /* Word 0 - End */
} loki;
};
typedef union cavm_rst_int_w1s cavm_rst_int_w1s_t;
#define CAVM_RST_INT_W1S CAVM_RST_INT_W1S_FUNC()
static inline uint64_t CAVM_RST_INT_W1S_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_INT_W1S_FUNC(void)
{
return 0x87e006001630ll;
}
#define typedef_CAVM_RST_INT_W1S cavm_rst_int_w1s_t
#define bustype_CAVM_RST_INT_W1S CSR_TYPE_RSL
#define basename_CAVM_RST_INT_W1S "RST_INT_W1S"
#define device_bar_CAVM_RST_INT_W1S 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_INT_W1S 0
#define arguments_CAVM_RST_INT_W1S -1,-1,-1,-1
/**
* Register (RSL) rst_lboot
*
* RST Last Boot Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_lboot
{
uint64_t u;
struct cavm_rst_lboot_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_50_63 : 14;
uint64_t lboot : 50; /**< [ 49: 0](R/W1C/H) Bit vector of last reset cause(es). The value reset with a
cold domain reset.
Bit numbers are enumerated by RST_SOURCE_E. */
#else /* Word 0 - Little Endian */
uint64_t lboot : 50; /**< [ 49: 0](R/W1C/H) Bit vector of last reset cause(es). The value reset with a
cold domain reset.
Bit numbers are enumerated by RST_SOURCE_E. */
uint64_t reserved_50_63 : 14;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_lboot_s cn9; */
struct cavm_rst_lboot_cn96xxp1
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_48_63 : 16;
uint64_t lboot : 48; /**< [ 47: 0](R/W1C/H) Bit vector of last reset cause(es). The value reset with a
cold domain reset.
Bit numbers are enumerated by RST_SOURCE_E. */
#else /* Word 0 - Little Endian */
uint64_t lboot : 48; /**< [ 47: 0](R/W1C/H) Bit vector of last reset cause(es). The value reset with a
cold domain reset.
Bit numbers are enumerated by RST_SOURCE_E. */
uint64_t reserved_48_63 : 16;
#endif /* Word 0 - End */
} cn96xxp1;
struct cavm_rst_lboot_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_48_63 : 16;
uint64_t lboot : 48; /**< [ 47: 0](R/W1C/H) Bit vector of last reset cause(es).
Bit numbers are enumerated by RST_SOURCE_E.
Unused bits always read as zero.
The value reset with a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t lboot : 48; /**< [ 47: 0](R/W1C/H) Bit vector of last reset cause(es).
Bit numbers are enumerated by RST_SOURCE_E.
Unused bits always read as zero.
The value reset with a cold domain reset. */
uint64_t reserved_48_63 : 16;
#endif /* Word 0 - End */
} cn96xxp3;
struct cavm_rst_lboot_cn98xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_32_63 : 32;
uint64_t lboot : 32; /**< [ 31: 0](R/W1C/H) Bit vector of last reset cause(es). The value reset with a
cold domain reset.
Bit numbers are enumerated by RST_SOURCE_E. */
#else /* Word 0 - Little Endian */
uint64_t lboot : 32; /**< [ 31: 0](R/W1C/H) Bit vector of last reset cause(es). The value reset with a
cold domain reset.
Bit numbers are enumerated by RST_SOURCE_E. */
uint64_t reserved_32_63 : 32;
#endif /* Word 0 - End */
} cn98xx;
/* struct cavm_rst_lboot_s cnf95xx; */
/* struct cavm_rst_lboot_s loki; */
};
typedef union cavm_rst_lboot cavm_rst_lboot_t;
#define CAVM_RST_LBOOT CAVM_RST_LBOOT_FUNC()
static inline uint64_t CAVM_RST_LBOOT_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_LBOOT_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001620ll;
__cavm_csr_fatal("RST_LBOOT", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_LBOOT cavm_rst_lboot_t
#define bustype_CAVM_RST_LBOOT CSR_TYPE_RSL
#define basename_CAVM_RST_LBOOT "RST_LBOOT"
#define device_bar_CAVM_RST_LBOOT 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_LBOOT 0
#define arguments_CAVM_RST_LBOOT -1,-1,-1,-1
/**
* Register (RSL) rst_mcp_domain_w1c
*
* RST MCP Domain Soft Reset Clear Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_mcp_domain_w1c
{
uint64_t u;
struct cavm_rst_mcp_domain_w1c_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear software-initiated reset of the MCP processor and associated logic.
When set to one, the soft reset of the MCP is removed.
Reads of this register show the soft reset state. Not the actual MCP domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[MCP] shows
the actual reset state. To compensate for delays in reset, this field should only
be set if RST_RESET_ACTIVE[MCP] is set.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear software-initiated reset of the MCP processor and associated logic.
When set to one, the soft reset of the MCP is removed.
Reads of this register show the soft reset state. Not the actual MCP domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[MCP] shows
the actual reset state. To compensate for delays in reset, this field should only
be set if RST_RESET_ACTIVE[MCP] is set.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_mcp_domain_w1c_s cn; */
};
typedef union cavm_rst_mcp_domain_w1c cavm_rst_mcp_domain_w1c_t;
#define CAVM_RST_MCP_DOMAIN_W1C CAVM_RST_MCP_DOMAIN_W1C_FUNC()
static inline uint64_t CAVM_RST_MCP_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_MCP_DOMAIN_W1C_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001838ll;
__cavm_csr_fatal("RST_MCP_DOMAIN_W1C", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_MCP_DOMAIN_W1C cavm_rst_mcp_domain_w1c_t
#define bustype_CAVM_RST_MCP_DOMAIN_W1C CSR_TYPE_RSL
#define basename_CAVM_RST_MCP_DOMAIN_W1C "RST_MCP_DOMAIN_W1C"
#define device_bar_CAVM_RST_MCP_DOMAIN_W1C 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_MCP_DOMAIN_W1C 0
#define arguments_CAVM_RST_MCP_DOMAIN_W1C -1,-1,-1,-1
/**
* Register (RSL) rst_mcp_domain_w1s
*
* RST MCP Domain Soft Reset Set Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_mcp_domain_w1s
{
uint64_t u;
struct cavm_rst_mcp_domain_w1s_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set software-initiated reset of MCP core and associated logic.
When set to one, all logic associated with the MCP domain is placed in reset.
Reads of this register show the soft reset state. Not the actual MCP domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[MCP] shows
the actual reset state.
It is typically cleared by writing to RST_MCP_DOMAIN_W1C.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set software-initiated reset of MCP core and associated logic.
When set to one, all logic associated with the MCP domain is placed in reset.
Reads of this register show the soft reset state. Not the actual MCP domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[MCP] shows
the actual reset state.
It is typically cleared by writing to RST_MCP_DOMAIN_W1C.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_mcp_domain_w1s_s cn; */
};
typedef union cavm_rst_mcp_domain_w1s cavm_rst_mcp_domain_w1s_t;
#define CAVM_RST_MCP_DOMAIN_W1S CAVM_RST_MCP_DOMAIN_W1S_FUNC()
static inline uint64_t CAVM_RST_MCP_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_MCP_DOMAIN_W1S_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001830ll;
__cavm_csr_fatal("RST_MCP_DOMAIN_W1S", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_MCP_DOMAIN_W1S cavm_rst_mcp_domain_w1s_t
#define bustype_CAVM_RST_MCP_DOMAIN_W1S CSR_TYPE_RSL
#define basename_CAVM_RST_MCP_DOMAIN_W1S "RST_MCP_DOMAIN_W1S"
#define device_bar_CAVM_RST_MCP_DOMAIN_W1S 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_MCP_DOMAIN_W1S 0
#define arguments_CAVM_RST_MCP_DOMAIN_W1S -1,-1,-1,-1
/**
* Register (RSL) rst_msix_pba#
*
* RST MSI-X Pending Bit Array Registers
* This register is the MSI-X PBA table; the bit number is indexed by the RST_INT_VEC_E
* enumeration.
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_msix_pbax
{
uint64_t u;
struct cavm_rst_msix_pbax_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated RST_MSIX_VEC()_CTL, enumerated by
RST_INT_VEC_E. Bits that have no associated RST_INT_VEC_E are 0. */
#else /* Word 0 - Little Endian */
uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated RST_MSIX_VEC()_CTL, enumerated by
RST_INT_VEC_E. Bits that have no associated RST_INT_VEC_E are 0. */
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_msix_pbax_s cn8; */
struct cavm_rst_msix_pbax_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated RST_MSIX_VEC()_CTL, enumerated by
RST_INT_VEC_E. Bits that have no associated RST_INT_VEC_E are 0.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated RST_MSIX_VEC()_CTL, enumerated by
RST_INT_VEC_E. Bits that have no associated RST_INT_VEC_E are 0.
This field is always reinitialized on a chip domain reset. */
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_msix_pbax cavm_rst_msix_pbax_t;
static inline uint64_t CAVM_RST_MSIX_PBAX(unsigned long a) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_MSIX_PBAX(unsigned long a)
{
if (a==0)
return 0x87e006ff0000ll + 8ll * ((a) & 0x0);
__cavm_csr_fatal("RST_MSIX_PBAX", 1, a, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_MSIX_PBAX(a) cavm_rst_msix_pbax_t
#define bustype_CAVM_RST_MSIX_PBAX(a) CSR_TYPE_RSL
#define basename_CAVM_RST_MSIX_PBAX(a) "RST_MSIX_PBAX"
#define device_bar_CAVM_RST_MSIX_PBAX(a) 0x4 /* PF_BAR4 */
#define busnum_CAVM_RST_MSIX_PBAX(a) (a)
#define arguments_CAVM_RST_MSIX_PBAX(a) (a),-1,-1,-1
/**
* Register (RSL) rst_msix_vec#_addr
*
* RST MSI-X Vector-Table Address Register
* This register is the MSI-X vector table, indexed by the RST_INT_VEC_E enumeration.
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_msix_vecx_addr
{
uint64_t u;
struct cavm_rst_msix_vecx_addr_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_53_63 : 11;
uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
uint64_t reserved_1 : 1;
uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
0 = This vector can be read or written by either secure or nonsecure states.
1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
by the nonsecure world.
If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
set, all vectors are secure and function as if [SECVEC] was set. */
#else /* Word 0 - Little Endian */
uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
0 = This vector can be read or written by either secure or nonsecure states.
1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
by the nonsecure world.
If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
set, all vectors are secure and function as if [SECVEC] was set. */
uint64_t reserved_1 : 1;
uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
uint64_t reserved_53_63 : 11;
#endif /* Word 0 - End */
} s;
struct cavm_rst_msix_vecx_addr_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_49_63 : 15;
uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
uint64_t reserved_1 : 1;
uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
0 = This vector can be read or written by either secure or nonsecure states.
1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
by the nonsecure world.
If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
set, all vectors are secure and function as if [SECVEC] was set. */
#else /* Word 0 - Little Endian */
uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
0 = This vector can be read or written by either secure or nonsecure states.
1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
by the nonsecure world.
If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
set, all vectors are secure and function as if [SECVEC] was set. */
uint64_t reserved_1 : 1;
uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
uint64_t reserved_49_63 : 15;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_msix_vecx_addr_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_53_63 : 11;
uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_1 : 1;
uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
0 = This vector can be read or written by either secure or nonsecure states.
1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause
a fault when accessed by the nonsecure world.
If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
set, all vectors are secure and function as if [SECVEC] was set.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
0 = This vector can be read or written by either secure or nonsecure states.
1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause
a fault when accessed by the nonsecure world.
If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
set, all vectors are secure and function as if [SECVEC] was set.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_1 : 1;
uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_53_63 : 11;
#endif /* Word 0 - End */
} cn9;
/* struct cavm_rst_msix_vecx_addr_cn9 cn96xxp1; */
struct cavm_rst_msix_vecx_addr_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_53_63 : 11;
uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_1 : 1;
uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
0 = This vector may be read or written by either secure or nonsecure states.
The vector's IOVA is sent to the SMMU as nonsecure (though this only affects
physical addresses if PCCPF_XXX_VSEC_SCTL[MSIX_PHYS]=1).
1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause
a fault when accessed by the nonsecure world.
The vector's IOVA is sent to the SMMU as secure (though this only affects
physical addresses if PCCPF_XXX_VSEC_SCTL[MSIX_PHYS]=1 or
PCCPF_XXX_VSEC_SCTL[MSIX_SEC_PHYS]=1).
If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
set, all vectors are secure and function as if [SECVEC] was set.
This field is always reinitialized on a chip domain reset.
Also note the following:
* When PCCPF_XXX_VSEC_SCTL[MSIX_SEC_EN]=1, all secure vectors (including secure
VF vectors) will act as if PCCPF/PCCVF_XXX_MSIX_CAP_HDR[MSIXEN]=1,
PCCPF/PCCVF_XXX_MSIX_CAP_HDR[FUNM]=0 and PCCPF/PCCVF_XXX_CMD[ME]=1.
* When PCCPF_XXX_VSEC_SCTL[MSIX_SEC_PHYS]=1, all secure vectors (including
secure VF vectors) are considered physical, regardless of
PCCPF_XXX_VSEC_SCTL[MSIX_PHYS]. */
#else /* Word 0 - Little Endian */
uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
0 = This vector may be read or written by either secure or nonsecure states.
The vector's IOVA is sent to the SMMU as nonsecure (though this only affects
physical addresses if PCCPF_XXX_VSEC_SCTL[MSIX_PHYS]=1).
1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause
a fault when accessed by the nonsecure world.
The vector's IOVA is sent to the SMMU as secure (though this only affects
physical addresses if PCCPF_XXX_VSEC_SCTL[MSIX_PHYS]=1 or
PCCPF_XXX_VSEC_SCTL[MSIX_SEC_PHYS]=1).
If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
set, all vectors are secure and function as if [SECVEC] was set.
This field is always reinitialized on a chip domain reset.
Also note the following:
* When PCCPF_XXX_VSEC_SCTL[MSIX_SEC_EN]=1, all secure vectors (including secure
VF vectors) will act as if PCCPF/PCCVF_XXX_MSIX_CAP_HDR[MSIXEN]=1,
PCCPF/PCCVF_XXX_MSIX_CAP_HDR[FUNM]=0 and PCCPF/PCCVF_XXX_CMD[ME]=1.
* When PCCPF_XXX_VSEC_SCTL[MSIX_SEC_PHYS]=1, all secure vectors (including
secure VF vectors) are considered physical, regardless of
PCCPF_XXX_VSEC_SCTL[MSIX_PHYS]. */
uint64_t reserved_1 : 1;
uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_53_63 : 11;
#endif /* Word 0 - End */
} cn96xxp3;
/* struct cavm_rst_msix_vecx_addr_cn96xxp3 cn98xx; */
/* struct cavm_rst_msix_vecx_addr_cn96xxp3 cnf95xx; */
/* struct cavm_rst_msix_vecx_addr_cn96xxp3 loki; */
};
typedef union cavm_rst_msix_vecx_addr cavm_rst_msix_vecx_addr_t;
static inline uint64_t CAVM_RST_MSIX_VECX_ADDR(unsigned long a) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_MSIX_VECX_ADDR(unsigned long a)
{
if (a==0)
return 0x87e006f00000ll + 0x10ll * ((a) & 0x0);
__cavm_csr_fatal("RST_MSIX_VECX_ADDR", 1, a, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_MSIX_VECX_ADDR(a) cavm_rst_msix_vecx_addr_t
#define bustype_CAVM_RST_MSIX_VECX_ADDR(a) CSR_TYPE_RSL
#define basename_CAVM_RST_MSIX_VECX_ADDR(a) "RST_MSIX_VECX_ADDR"
#define device_bar_CAVM_RST_MSIX_VECX_ADDR(a) 0x4 /* PF_BAR4 */
#define busnum_CAVM_RST_MSIX_VECX_ADDR(a) (a)
#define arguments_CAVM_RST_MSIX_VECX_ADDR(a) (a),-1,-1,-1
/**
* Register (RSL) rst_msix_vec#_ctl
*
* RST MSI-X Vector-Table Control and Data Register
* This register is the MSI-X vector table, indexed by the RST_INT_VEC_E enumeration.
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_msix_vecx_ctl
{
uint64_t u;
struct cavm_rst_msix_vecx_ctl_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_33_63 : 31;
uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
#else /* Word 0 - Little Endian */
uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
uint64_t reserved_33_63 : 31;
#endif /* Word 0 - End */
} s;
struct cavm_rst_msix_vecx_ctl_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_33_63 : 31;
uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
uint64_t reserved_20_31 : 12;
uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
#else /* Word 0 - Little Endian */
uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
uint64_t reserved_20_31 : 12;
uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
uint64_t reserved_33_63 : 31;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_msix_vecx_ctl_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_33_63 : 31;
uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector.
This field is always reinitialized on a chip domain reset. */
uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector.
This field is always reinitialized on a chip domain reset. */
uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_33_63 : 31;
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_msix_vecx_ctl cavm_rst_msix_vecx_ctl_t;
static inline uint64_t CAVM_RST_MSIX_VECX_CTL(unsigned long a) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_MSIX_VECX_CTL(unsigned long a)
{
if (a==0)
return 0x87e006f00008ll + 0x10ll * ((a) & 0x0);
__cavm_csr_fatal("RST_MSIX_VECX_CTL", 1, a, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_MSIX_VECX_CTL(a) cavm_rst_msix_vecx_ctl_t
#define bustype_CAVM_RST_MSIX_VECX_CTL(a) CSR_TYPE_RSL
#define basename_CAVM_RST_MSIX_VECX_CTL(a) "RST_MSIX_VECX_CTL"
#define device_bar_CAVM_RST_MSIX_VECX_CTL(a) 0x4 /* PF_BAR4 */
#define busnum_CAVM_RST_MSIX_VECX_CTL(a) (a)
#define arguments_CAVM_RST_MSIX_VECX_CTL(a) (a),-1,-1,-1
/**
* Register (RSL) rst_ocx
*
* INTERNAL: RST OCX Register
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_ocx
{
uint64_t u;
struct cavm_rst_ocx_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_3_63 : 61;
uint64_t rst_link : 3; /**< [ 2: 0](R/W) Reserved. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 3; /**< [ 2: 0](R/W) Reserved. */
uint64_t reserved_3_63 : 61;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_ocx_s cn8; */
struct cavm_rst_ocx_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t rst_link : 1; /**< [ 0: 0](R/W) Reserved.
Internal:
Controls whether the OCX CCPI link going down causes a reset.
This field is reinitialized with a core domain reset. */
#else /* Word 0 - Little Endian */
uint64_t rst_link : 1; /**< [ 0: 0](R/W) Reserved.
Internal:
Controls whether the OCX CCPI link going down causes a reset.
This field is reinitialized with a core domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_ocx cavm_rst_ocx_t;
#define CAVM_RST_OCX CAVM_RST_OCX_FUNC()
static inline uint64_t CAVM_RST_OCX_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_OCX_FUNC(void)
{
return 0x87e006001618ll;
}
#define typedef_CAVM_RST_OCX cavm_rst_ocx_t
#define bustype_CAVM_RST_OCX CSR_TYPE_RSL
#define basename_CAVM_RST_OCX "RST_OCX"
#define device_bar_CAVM_RST_OCX 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_OCX 0
#define arguments_CAVM_RST_OCX -1,-1,-1,-1
/**
* Register (RSL) rst_osc_cntr
*
* INTERNAL: RST Internal Ring-Oscillator Counter Register
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_osc_cntr
{
uint64_t u;
struct cavm_rst_osc_cntr_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t cnt : 64; /**< [ 63: 0](RO/H) Internal ring-oscillator clock count. Updated every 16 reference clocks. */
#else /* Word 0 - Little Endian */
uint64_t cnt : 64; /**< [ 63: 0](RO/H) Internal ring-oscillator clock count. Updated every 16 reference clocks. */
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_osc_cntr_s cn8; */
struct cavm_rst_osc_cntr_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t cnt : 64; /**< [ 63: 0](RO/H) Internal ring-oscillator clock count.
Updated every 16 PLL reference clocks.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
#else /* Word 0 - Little Endian */
uint64_t cnt : 64; /**< [ 63: 0](RO/H) Internal ring-oscillator clock count.
Updated every 16 PLL reference clocks.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_osc_cntr cavm_rst_osc_cntr_t;
#define CAVM_RST_OSC_CNTR CAVM_RST_OSC_CNTR_FUNC()
static inline uint64_t CAVM_RST_OSC_CNTR_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_OSC_CNTR_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN8XXX))
return 0x87e006001778ll;
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001768ll;
__cavm_csr_fatal("RST_OSC_CNTR", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_OSC_CNTR cavm_rst_osc_cntr_t
#define bustype_CAVM_RST_OSC_CNTR CSR_TYPE_RSL
#define basename_CAVM_RST_OSC_CNTR "RST_OSC_CNTR"
#define device_bar_CAVM_RST_OSC_CNTR 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_OSC_CNTR 0
#define arguments_CAVM_RST_OSC_CNTR -1,-1,-1,-1
/**
* Register (RSL) rst_out_ctl
*
* RST External Reset Control Register
* This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_out_ctl
{
uint64_t u;
struct cavm_rst_out_ctl_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_5_63 : 59;
uint64_t bphy_rst : 1; /**< [ 4: 4](R/W) BPHY reset output. When set by software, this field drives the GPIO_PIN_SEL_E::BPHY_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a BPHY
domain reset.
This field is always reinitialized on a BPHY domain reset. */
uint64_t scp_rst : 1; /**< [ 3: 3](R/W) SCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::SCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a SCP
domain reset.
This field is always reinitialized on an SCP domain reset. */
uint64_t mcp_rst : 1; /**< [ 2: 2](R/W) MCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::MCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a MCP
domain reset.
This field is always reinitialized on an MCP domain reset. */
uint64_t core_rst : 1; /**< [ 1: 1](R/W) Core reset output. When set by software, this field drives the GPIO_PIN_SEL_E::CORE_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a core
domain reset.
This field is always reinitialized on a core domain reset. */
uint64_t reserved_0 : 1;
#else /* Word 0 - Little Endian */
uint64_t reserved_0 : 1;
uint64_t core_rst : 1; /**< [ 1: 1](R/W) Core reset output. When set by software, this field drives the GPIO_PIN_SEL_E::CORE_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a core
domain reset.
This field is always reinitialized on a core domain reset. */
uint64_t mcp_rst : 1; /**< [ 2: 2](R/W) MCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::MCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a MCP
domain reset.
This field is always reinitialized on an MCP domain reset. */
uint64_t scp_rst : 1; /**< [ 3: 3](R/W) SCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::SCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a SCP
domain reset.
This field is always reinitialized on an SCP domain reset. */
uint64_t bphy_rst : 1; /**< [ 4: 4](R/W) BPHY reset output. When set by software, this field drives the GPIO_PIN_SEL_E::BPHY_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a BPHY
domain reset.
This field is always reinitialized on a BPHY domain reset. */
uint64_t reserved_5_63 : 59;
#endif /* Word 0 - End */
} s;
struct cavm_rst_out_ctl_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W) Soft reset. When set to 1 by software, this field drives the CHIP_RESET_OUT_L pin
active low. In this case the field must also be cleared by software to deassert
the pin. The pin is also automatically asserted and deasserted by hardware
during a cold/warm/soft reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W) Soft reset. When set to 1 by software, this field drives the CHIP_RESET_OUT_L pin
active low. In this case the field must also be cleared by software to deassert
the pin. The pin is also automatically asserted and deasserted by hardware
during a cold/warm/soft reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_out_ctl_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_5_63 : 59;
uint64_t bphy_rst : 1; /**< [ 4: 4](R/W) BPHY reset output. When set by software, this field drives the GPIO_PIN_SEL_E::BPHY_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a BPHY
domain reset.
This field is always reinitialized on a BPHY domain reset. */
uint64_t scp_rst : 1; /**< [ 3: 3](R/W) SCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::SCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a SCP
domain reset.
This field is always reinitialized on an SCP domain reset. */
uint64_t mcp_rst : 1; /**< [ 2: 2](R/W) MCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::MCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a MCP
domain reset.
This field is always reinitialized on an MCP domain reset. */
uint64_t core_rst : 1; /**< [ 1: 1](R/W) Core reset output. When set by software, this field drives the GPIO_PIN_SEL_E::CORE_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a core
domain reset.
This field is always reinitialized on a core domain reset. */
uint64_t chip_rst : 1; /**< [ 0: 0](R/W) Chip domain reset output. When set to one by software, this field drives the
CHIP_RESET_OUT_L pin active low. If this field is set my software then it must also be
cleared to deassert the pin. The pin is also automatically asserted and deasserted by
hardware during a chip domain reset.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t chip_rst : 1; /**< [ 0: 0](R/W) Chip domain reset output. When set to one by software, this field drives the
CHIP_RESET_OUT_L pin active low. If this field is set my software then it must also be
cleared to deassert the pin. The pin is also automatically asserted and deasserted by
hardware during a chip domain reset.
This field is always reinitialized on a chip domain reset. */
uint64_t core_rst : 1; /**< [ 1: 1](R/W) Core reset output. When set by software, this field drives the GPIO_PIN_SEL_E::CORE_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a core
domain reset.
This field is always reinitialized on a core domain reset. */
uint64_t mcp_rst : 1; /**< [ 2: 2](R/W) MCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::MCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a MCP
domain reset.
This field is always reinitialized on an MCP domain reset. */
uint64_t scp_rst : 1; /**< [ 3: 3](R/W) SCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::SCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a SCP
domain reset.
This field is always reinitialized on an SCP domain reset. */
uint64_t bphy_rst : 1; /**< [ 4: 4](R/W) BPHY reset output. When set by software, this field drives the GPIO_PIN_SEL_E::BPHY_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a BPHY
domain reset.
This field is always reinitialized on a BPHY domain reset. */
uint64_t reserved_5_63 : 59;
#endif /* Word 0 - End */
} cn9;
struct cavm_rst_out_ctl_cn96xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_4_63 : 60;
uint64_t scp_rst : 1; /**< [ 3: 3](R/W) SCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::SCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a SCP
domain reset.
This field is always reinitialized on an SCP domain reset. */
uint64_t mcp_rst : 1; /**< [ 2: 2](R/W) MCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::MCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a MCP
domain reset.
This field is always reinitialized on an MCP domain reset. */
uint64_t core_rst : 1; /**< [ 1: 1](R/W) Core reset output. When set by software, this field drives the GPIO_PIN_SEL_E::CORE_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a core
domain reset.
This field is always reinitialized on a core domain reset. */
uint64_t chip_rst : 1; /**< [ 0: 0](R/W) Chip domain reset output. When set to one by software, this field drives the
CHIP_RESET_OUT_L pin active low. If this field is set my software then it must also be
cleared to deassert the pin. The pin is also automatically asserted and deasserted by
hardware during a chip domain reset.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t chip_rst : 1; /**< [ 0: 0](R/W) Chip domain reset output. When set to one by software, this field drives the
CHIP_RESET_OUT_L pin active low. If this field is set my software then it must also be
cleared to deassert the pin. The pin is also automatically asserted and deasserted by
hardware during a chip domain reset.
This field is always reinitialized on a chip domain reset. */
uint64_t core_rst : 1; /**< [ 1: 1](R/W) Core reset output. When set by software, this field drives the GPIO_PIN_SEL_E::CORE_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a core
domain reset.
This field is always reinitialized on a core domain reset. */
uint64_t mcp_rst : 1; /**< [ 2: 2](R/W) MCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::MCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a MCP
domain reset.
This field is always reinitialized on an MCP domain reset. */
uint64_t scp_rst : 1; /**< [ 3: 3](R/W) SCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::SCP_RESET_OUT
selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
field is set by software then it must also be cleared to deassert the pin.
The pin is also automatically asserted and deasserted by hardware during a SCP
domain reset.
This field is always reinitialized on an SCP domain reset. */
uint64_t reserved_4_63 : 60;
#endif /* Word 0 - End */
} cn96xx;
/* struct cavm_rst_out_ctl_cn96xx cn98xx; */
/* struct cavm_rst_out_ctl_cn9 cnf95xx; */
/* struct cavm_rst_out_ctl_cn9 loki; */
};
typedef union cavm_rst_out_ctl cavm_rst_out_ctl_t;
#define CAVM_RST_OUT_CTL CAVM_RST_OUT_CTL_FUNC()
static inline uint64_t CAVM_RST_OUT_CTL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_OUT_CTL_FUNC(void)
{
return 0x87e006001688ll;
}
#define typedef_CAVM_RST_OUT_CTL cavm_rst_out_ctl_t
#define bustype_CAVM_RST_OUT_CTL CSR_TYPE_RSL
#define basename_CAVM_RST_OUT_CTL "RST_OUT_CTL"
#define device_bar_CAVM_RST_OUT_CTL 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_OUT_CTL 0
#define arguments_CAVM_RST_OUT_CTL -1,-1,-1,-1
/**
* Register (RSL) rst_pll_limit
*
* RST PLL Maximum Frequency Limit Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_pll_limit
{
uint64_t u;
struct cavm_rst_pll_limit_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_23_63 : 41;
uint64_t cpt_max_mul : 7; /**< [ 22: 16](R/W/H) Crypto clock maximum PLL multiplier.
This field is used to limit the RST_CPT_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-3 are considered illegal
since the minimum PLL frequency is 200 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CPT_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_15 : 1;
uint64_t core_max_mul : 7; /**< [ 14: 8](R/W/H) Core clock maximum PLL multiplier.
This field is used to limit the RST_CORE_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CORE_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_7 : 1;
uint64_t pnr_max_mul : 7; /**< [ 6: 0](R/W/H) Coprocessor clock maximum PLL multiplier.
This field is used to limit the RST_PNR_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::PNR_MAX_MUL() fuses on a chip domain
reset. */
#else /* Word 0 - Little Endian */
uint64_t pnr_max_mul : 7; /**< [ 6: 0](R/W/H) Coprocessor clock maximum PLL multiplier.
This field is used to limit the RST_PNR_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::PNR_MAX_MUL() fuses on a chip domain
reset. */
uint64_t reserved_7 : 1;
uint64_t core_max_mul : 7; /**< [ 14: 8](R/W/H) Core clock maximum PLL multiplier.
This field is used to limit the RST_CORE_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CORE_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_15 : 1;
uint64_t cpt_max_mul : 7; /**< [ 22: 16](R/W/H) Crypto clock maximum PLL multiplier.
This field is used to limit the RST_CPT_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-3 are considered illegal
since the minimum PLL frequency is 200 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CPT_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_23_63 : 41;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_pll_limit_s cn9; */
/* struct cavm_rst_pll_limit_s cn96xx; */
struct cavm_rst_pll_limit_cn98xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_39_63 : 25;
uint64_t rxp_max_mul : 7; /**< [ 38: 32](R/W/H) RXP clock maximum PLL multiplier.
This field is used to limit the RST_RXP_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-3 are considered illegal
since the minimum PLL frequency is 200 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::RXP_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_31 : 1;
uint64_t cpt1_max_mul : 7; /**< [ 30: 24](R/W/H) Crypto clock maximum PLL multiplier for CPT1.
This field is used to limit the RST_CPT1_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-3 are considered illegal
since the minimum PLL frequency is 200 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CPT_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_23 : 1;
uint64_t cpt_max_mul : 7; /**< [ 22: 16](R/W/H) Crypto clock maximum PLL multiplier for CPT0.
This field is used to limit the RST_CPT_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-3 are considered illegal
since the minimum PLL frequency is 200 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CPT_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_15 : 1;
uint64_t core_max_mul : 7; /**< [ 14: 8](R/W/H) Core clock maximum PLL multiplier.
This field is used to limit the RST_CORE_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CORE_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_7 : 1;
uint64_t pnr_max_mul : 7; /**< [ 6: 0](R/W/H) Coprocessor clock maximum PLL multiplier.
This field is used to limit the RST_PNR_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::PNR_MAX_MUL() fuses on a chip domain
reset. */
#else /* Word 0 - Little Endian */
uint64_t pnr_max_mul : 7; /**< [ 6: 0](R/W/H) Coprocessor clock maximum PLL multiplier.
This field is used to limit the RST_PNR_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::PNR_MAX_MUL() fuses on a chip domain
reset. */
uint64_t reserved_7 : 1;
uint64_t core_max_mul : 7; /**< [ 14: 8](R/W/H) Core clock maximum PLL multiplier.
This field is used to limit the RST_CORE_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CORE_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_15 : 1;
uint64_t cpt_max_mul : 7; /**< [ 22: 16](R/W/H) Crypto clock maximum PLL multiplier for CPT0.
This field is used to limit the RST_CPT_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-3 are considered illegal
since the minimum PLL frequency is 200 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CPT_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_23 : 1;
uint64_t cpt1_max_mul : 7; /**< [ 30: 24](R/W/H) Crypto clock maximum PLL multiplier for CPT1.
This field is used to limit the RST_CPT1_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-3 are considered illegal
since the minimum PLL frequency is 200 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CPT_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_31 : 1;
uint64_t rxp_max_mul : 7; /**< [ 38: 32](R/W/H) RXP clock maximum PLL multiplier.
This field is used to limit the RST_RXP_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-3 are considered illegal
since the minimum PLL frequency is 200 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::RXP_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_39_63 : 25;
#endif /* Word 0 - End */
} cn98xx;
struct cavm_rst_pll_limit_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_39_63 : 25;
uint64_t bphy_max_mul : 7; /**< [ 38: 32](R/W/H) BPHY clock maximum PLL multiplier.
This field is used to limit the RST_DSP_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::BPHY_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_31 : 1;
uint64_t dsp_max_mul : 7; /**< [ 30: 24](R/W/H) DSP clock maximum PLL multiplier.
This field is used to limit the RST_DSP_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::DSP_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_23 : 1;
uint64_t cpt_max_mul : 7; /**< [ 22: 16](R/W/H) Reserved.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CPT_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_15 : 1;
uint64_t core_max_mul : 7; /**< [ 14: 8](R/W/H) Core clock maximum PLL multiplier.
This field is used to limit the RST_CORE_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CORE_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_7 : 1;
uint64_t pnr_max_mul : 7; /**< [ 6: 0](R/W/H) Coprocessor clock maximum PLL multiplier.
This field is used to limit the RST_PNR_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::PNR_MAX_MUL() fuses on a chip domain
reset. */
#else /* Word 0 - Little Endian */
uint64_t pnr_max_mul : 7; /**< [ 6: 0](R/W/H) Coprocessor clock maximum PLL multiplier.
This field is used to limit the RST_PNR_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::PNR_MAX_MUL() fuses on a chip domain
reset. */
uint64_t reserved_7 : 1;
uint64_t core_max_mul : 7; /**< [ 14: 8](R/W/H) Core clock maximum PLL multiplier.
This field is used to limit the RST_CORE_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CORE_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_15 : 1;
uint64_t cpt_max_mul : 7; /**< [ 22: 16](R/W/H) Reserved.
Internal:
The field is initialized to FUS_FUSE_NUM_E::CPT_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_23 : 1;
uint64_t dsp_max_mul : 7; /**< [ 30: 24](R/W/H) DSP clock maximum PLL multiplier.
This field is used to limit the RST_DSP_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::DSP_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_31 : 1;
uint64_t bphy_max_mul : 7; /**< [ 38: 32](R/W/H) BPHY clock maximum PLL multiplier.
This field is used to limit the RST_DSP_PLL[CUR_MUL] value.
A value of zero is considered unlimited. Once the value
of this field is nonzero, any new values written into this field
cannot exceed the previous value. Values 1-5 are considered illegal
since the minimum PLL frequency is 300 MHz.
Internal:
The field is initialized to FUS_FUSE_NUM_E::BPHY_MAX_MUL() fuses on a chip domain reset. */
uint64_t reserved_39_63 : 25;
#endif /* Word 0 - End */
} cnf95xx;
/* struct cavm_rst_pll_limit_cnf95xx loki; */
};
typedef union cavm_rst_pll_limit cavm_rst_pll_limit_t;
#define CAVM_RST_PLL_LIMIT CAVM_RST_PLL_LIMIT_FUNC()
static inline uint64_t CAVM_RST_PLL_LIMIT_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_PLL_LIMIT_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e00a001790ll;
__cavm_csr_fatal("RST_PLL_LIMIT", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_PLL_LIMIT cavm_rst_pll_limit_t
#define bustype_CAVM_RST_PLL_LIMIT CSR_TYPE_RSL
#define basename_CAVM_RST_PLL_LIMIT "RST_PLL_LIMIT"
#define device_bar_CAVM_RST_PLL_LIMIT 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_PLL_LIMIT 0
#define arguments_CAVM_RST_PLL_LIMIT -1,-1,-1,-1
/**
* Register (RSL) rst_pnr_pll
*
* RST Coprocessor Clock PLL Control Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_pnr_pll
{
uint64_t u;
struct cavm_rst_pnr_pll_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Coprocessor clockout select.
0x0 = Coprocessor clock divided by 32.
0x1 = Coprocessor clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Coprocessor clockout reset. The coprocessor clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) PNR PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) PNR PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Coprocessor clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[PNR_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLLs are updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Coprocessor PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[PNR_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Coprocessor clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[PNR_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Coprocessor clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[PNR_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Coprocessor PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[PNR_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLLs are updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Coprocessor clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[PNR_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) PNR PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) PNR PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Coprocessor clockout reset. The coprocessor clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Coprocessor clockout select.
0x0 = Coprocessor clock divided by 32.
0x1 = Coprocessor clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_pnr_pll_s cn9; */
/* struct cavm_rst_pnr_pll_s cn96xx; */
struct cavm_rst_pnr_pll_cn98xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Coprocessor clockout select.
0x0 = Coprocessor clock divided by 32.
0x1 = Coprocessor clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Coprocessor clockout reset. The coprocessor clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 rxp_clk/cpt_clk/sclk/rclk notification to
hardware. Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) PNR PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) PNR PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Coprocessor clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[PNR_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLLs are updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Coprocessor PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[PNR_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Coprocessor clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[PNR_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Coprocessor clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[PNR_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Coprocessor PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[PNR_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLLs are updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Coprocessor clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[PNR_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) PNR PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) PNR PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 rxp_clk/cpt_clk/sclk/rclk notification to
hardware. Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Coprocessor clockout reset. The coprocessor clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Coprocessor clockout select.
0x0 = Coprocessor clock divided by 32.
0x1 = Coprocessor clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cn98xx;
struct cavm_rst_pnr_pll_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Coprocessor clockout select.
0x0 = Coprocessor clock divided by 32.
0x1 = Coprocessor clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Coprocessor clockout reset. The coprocessor clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 sclk/rclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) PNR PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) PNR PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Coprocessor clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[PNR_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLLs are updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Coprocessor PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[PNR_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Coprocessor clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[PNR_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Coprocessor clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[PNR_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Coprocessor PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[PNR_MAX_MUL] and
a minimum setting of 300 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLLs are updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) Coprocessor clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[PNR_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) PNR PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) PNR PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 sclk/rclk notification to hardware.
Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Coprocessor clockout reset. The coprocessor clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Coprocessor clockout select.
0x0 = Coprocessor clock divided by 32.
0x1 = Coprocessor clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} cnf95xx;
/* struct cavm_rst_pnr_pll_cnf95xx loki; */
};
typedef union cavm_rst_pnr_pll cavm_rst_pnr_pll_t;
#define CAVM_RST_PNR_PLL CAVM_RST_PNR_PLL_FUNC()
static inline uint64_t CAVM_RST_PNR_PLL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_PNR_PLL_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e00a001788ll;
__cavm_csr_fatal("RST_PNR_PLL", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_PNR_PLL cavm_rst_pnr_pll_t
#define bustype_CAVM_RST_PNR_PLL CSR_TYPE_RSL
#define basename_CAVM_RST_PNR_PLL "RST_PNR_PLL"
#define device_bar_CAVM_RST_PNR_PLL 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_PNR_PLL 0
#define arguments_CAVM_RST_PNR_PLL -1,-1,-1,-1
/**
* Register (RSL) rst_power_dbg
*
* RST Core-Power Debug-Control Register
*/
union cavm_rst_power_dbg
{
uint64_t u;
struct cavm_rst_power_dbg_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_3_63 : 61;
uint64_t str : 3; /**< [ 2: 0](R/W) Reserved.
Internal:
Internal power driver strength. Resets only on cold reset. */
#else /* Word 0 - Little Endian */
uint64_t str : 3; /**< [ 2: 0](R/W) Reserved.
Internal:
Internal power driver strength. Resets only on cold reset. */
uint64_t reserved_3_63 : 61;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_power_dbg_s cn; */
};
typedef union cavm_rst_power_dbg cavm_rst_power_dbg_t;
#define CAVM_RST_POWER_DBG CAVM_RST_POWER_DBG_FUNC()
static inline uint64_t CAVM_RST_POWER_DBG_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_POWER_DBG_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN8XXX))
return 0x87e006001708ll;
__cavm_csr_fatal("RST_POWER_DBG", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_POWER_DBG cavm_rst_power_dbg_t
#define bustype_CAVM_RST_POWER_DBG CSR_TYPE_RSL
#define basename_CAVM_RST_POWER_DBG "RST_POWER_DBG"
#define device_bar_CAVM_RST_POWER_DBG 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_POWER_DBG 0
#define arguments_CAVM_RST_POWER_DBG -1,-1,-1,-1
/**
* Register (RSL) rst_pp_available
*
* RST Core Availability Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_pp_available
{
uint64_t u;
struct cavm_rst_pp_available_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_36_63 : 28;
uint64_t present : 36; /**< [ 35: 0](RO) Each bit set indicates a physical core is present. */
#else /* Word 0 - Little Endian */
uint64_t present : 36; /**< [ 35: 0](RO) Each bit set indicates a physical core is present. */
uint64_t reserved_36_63 : 28;
#endif /* Word 0 - End */
} s;
struct cavm_rst_pp_available_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_24_63 : 40;
uint64_t present : 24; /**< [ 23: 0](RO) Each bit set indicates a physical core is present. */
#else /* Word 0 - Little Endian */
uint64_t present : 24; /**< [ 23: 0](RO) Each bit set indicates a physical core is present. */
uint64_t reserved_24_63 : 40;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_pp_available_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_4_63 : 60;
uint64_t present : 4; /**< [ 3: 0](RO) Each bit set indicates a physical core is present. */
#else /* Word 0 - Little Endian */
uint64_t present : 4; /**< [ 3: 0](RO) Each bit set indicates a physical core is present. */
uint64_t reserved_4_63 : 60;
#endif /* Word 0 - End */
} cn81xx;
/* struct cavm_rst_pp_available_cn8 cn83xx; */
/* struct cavm_rst_pp_available_s cn9; */
/* struct cavm_rst_pp_available_cn8 cn96xx; */
/* struct cavm_rst_pp_available_s cn98xx; */
struct cavm_rst_pp_available_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_6_63 : 58;
uint64_t present : 6; /**< [ 5: 0](RO) Each bit set indicates a physical core is present. */
#else /* Word 0 - Little Endian */
uint64_t present : 6; /**< [ 5: 0](RO) Each bit set indicates a physical core is present. */
uint64_t reserved_6_63 : 58;
#endif /* Word 0 - End */
} cnf95xx;
/* struct cavm_rst_pp_available_cnf95xx loki; */
};
typedef union cavm_rst_pp_available cavm_rst_pp_available_t;
#define CAVM_RST_PP_AVAILABLE CAVM_RST_PP_AVAILABLE_FUNC()
static inline uint64_t CAVM_RST_PP_AVAILABLE_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_PP_AVAILABLE_FUNC(void)
{
return 0x87e006001738ll;
}
#define typedef_CAVM_RST_PP_AVAILABLE cavm_rst_pp_available_t
#define bustype_CAVM_RST_PP_AVAILABLE CSR_TYPE_RSL
#define basename_CAVM_RST_PP_AVAILABLE "RST_PP_AVAILABLE"
#define device_bar_CAVM_RST_PP_AVAILABLE 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_PP_AVAILABLE 0
#define arguments_CAVM_RST_PP_AVAILABLE -1,-1,-1,-1
/**
* Register (RSL) rst_pp_pending
*
* RST Cores Reset Pending Register
* This register contains the reset status for each core.
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_pp_pending
{
uint64_t u;
struct cavm_rst_pp_pending_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_36_63 : 28;
uint64_t pend : 36; /**< [ 35: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
management.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t pend : 36; /**< [ 35: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
management.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_36_63 : 28;
#endif /* Word 0 - End */
} s;
struct cavm_rst_pp_pending_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_24_63 : 40;
uint64_t pend : 24; /**< [ 23: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
management.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t pend : 24; /**< [ 23: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
management.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_24_63 : 40;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_pp_pending_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_4_63 : 60;
uint64_t pend : 4; /**< [ 3: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
management.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t pend : 4; /**< [ 3: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
management.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_4_63 : 60;
#endif /* Word 0 - End */
} cn81xx;
/* struct cavm_rst_pp_pending_cn8 cn83xx; */
struct cavm_rst_pp_pending_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_36_63 : 28;
uint64_t pend : 36; /**< [ 35: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 32K core-clock cycles between each core reset applies to satisfy power
management.
This field is always reinitialized on a core domain reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t pend : 36; /**< [ 35: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 32K core-clock cycles between each core reset applies to satisfy power
management.
This field is always reinitialized on a core domain reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_36_63 : 28;
#endif /* Word 0 - End */
} cn9;
struct cavm_rst_pp_pending_cn96xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_24_63 : 40;
uint64_t pend : 24; /**< [ 23: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 32K core-clock cycles between each core reset applies to satisfy power
management.
This field is always reinitialized on a core domain reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t pend : 24; /**< [ 23: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 32K core-clock cycles between each core reset applies to satisfy power
management.
This field is always reinitialized on a core domain reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_24_63 : 40;
#endif /* Word 0 - End */
} cn96xx;
/* struct cavm_rst_pp_pending_cn9 cn98xx; */
struct cavm_rst_pp_pending_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_6_63 : 58;
uint64_t pend : 6; /**< [ 5: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 32K core-clock cycles between each core reset applies to satisfy power
management.
This field is always reinitialized on a core domain reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t pend : 6; /**< [ 5: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
reset a delay of 32K core-clock cycles between each core reset applies to satisfy power
management.
This field is always reinitialized on a core domain reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_6_63 : 58;
#endif /* Word 0 - End */
} cnf95xx;
/* struct cavm_rst_pp_pending_cnf95xx loki; */
};
typedef union cavm_rst_pp_pending cavm_rst_pp_pending_t;
#define CAVM_RST_PP_PENDING CAVM_RST_PP_PENDING_FUNC()
static inline uint64_t CAVM_RST_PP_PENDING_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_PP_PENDING_FUNC(void)
{
return 0x87e006001748ll;
}
#define typedef_CAVM_RST_PP_PENDING cavm_rst_pp_pending_t
#define bustype_CAVM_RST_PP_PENDING CSR_TYPE_RSL
#define basename_CAVM_RST_PP_PENDING "RST_PP_PENDING"
#define device_bar_CAVM_RST_PP_PENDING 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_PP_PENDING 0
#define arguments_CAVM_RST_PP_PENDING -1,-1,-1,-1
/**
* Register (RSL) rst_pp_power
*
* RST Core Power Control Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_pp_power
{
uint64_t u;
struct cavm_rst_pp_power_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_36_63 : 28;
uint64_t gate : 36; /**< [ 35: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
set,
the core
has voltage removed to save power. In typical operation these bits are set up during
initialization and core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t gate : 36; /**< [ 35: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
set,
the core
has voltage removed to save power. In typical operation these bits are set up during
initialization and core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_36_63 : 28;
#endif /* Word 0 - End */
} s;
struct cavm_rst_pp_power_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_24_63 : 40;
uint64_t gate : 24; /**< [ 23: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
set,
the core
has voltage removed to save power. In typical operation these bits are set up during
initialization and core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t gate : 24; /**< [ 23: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
set,
the core
has voltage removed to save power. In typical operation these bits are set up during
initialization and core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_24_63 : 40;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_pp_power_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_4_63 : 60;
uint64_t gate : 4; /**< [ 3: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
set,
the core
has voltage removed to save power. In typical operation these bits are set up during
initialization and core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t gate : 4; /**< [ 3: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
set,
the core
has voltage removed to save power. In typical operation these bits are set up during
initialization and core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_4_63 : 60;
#endif /* Word 0 - End */
} cn81xx;
/* struct cavm_rst_pp_power_cn8 cn83xx; */
struct cavm_rst_pp_power_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_36_63 : 28;
uint64_t gate : 36; /**< [ 35: 0](R/W) When a bit in this field and the corresponding
RST_PP_RESET bit are set, the AP core is reduced to minimum power consumption.
In typical operation these bits are set up during initialization and the
AP core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding AP core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is always reinitialized on a core domain reset.
Internal:
Note this does not power off the cores, but only reduces power. There is no
per-core power gating in CNXXXX. */
#else /* Word 0 - Little Endian */
uint64_t gate : 36; /**< [ 35: 0](R/W) When a bit in this field and the corresponding
RST_PP_RESET bit are set, the AP core is reduced to minimum power consumption.
In typical operation these bits are set up during initialization and the
AP core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding AP core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is always reinitialized on a core domain reset.
Internal:
Note this does not power off the cores, but only reduces power. There is no
per-core power gating in CNXXXX. */
uint64_t reserved_36_63 : 28;
#endif /* Word 0 - End */
} cn9;
struct cavm_rst_pp_power_cn96xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_24_63 : 40;
uint64_t gate : 24; /**< [ 23: 0](R/W) When a bit in this field and the corresponding
RST_PP_RESET bit are set, the AP core is reduced to minimum power consumption.
In typical operation these bits are set up during initialization and the
AP core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding AP core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is always reinitialized on a core domain reset.
Internal:
Note this does not power off the cores, but only reduces power. There is no
per-core power gating in CNXXXX. */
#else /* Word 0 - Little Endian */
uint64_t gate : 24; /**< [ 23: 0](R/W) When a bit in this field and the corresponding
RST_PP_RESET bit are set, the AP core is reduced to minimum power consumption.
In typical operation these bits are set up during initialization and the
AP core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding AP core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is always reinitialized on a core domain reset.
Internal:
Note this does not power off the cores, but only reduces power. There is no
per-core power gating in CNXXXX. */
uint64_t reserved_24_63 : 40;
#endif /* Word 0 - End */
} cn96xx;
/* struct cavm_rst_pp_power_cn9 cn98xx; */
struct cavm_rst_pp_power_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_6_63 : 58;
uint64_t gate : 6; /**< [ 5: 0](R/W) When a bit in this field and the corresponding
RST_PP_RESET bit are set, the AP core is reduced to minimum power consumption.
In typical operation these bits are set up during initialization and the
AP core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding AP core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is always reinitialized on a core domain reset.
Internal:
Note this does not power off the cores, but only reduces power. There is no
per-core power gating in CNXXXX. */
#else /* Word 0 - Little Endian */
uint64_t gate : 6; /**< [ 5: 0](R/W) When a bit in this field and the corresponding
RST_PP_RESET bit are set, the AP core is reduced to minimum power consumption.
In typical operation these bits are set up during initialization and the
AP core resets are controlled through RST_PP_RESET. These bits can only be
changed when the corresponding AP core is in reset.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is always reinitialized on a core domain reset.
Internal:
Note this does not power off the cores, but only reduces power. There is no
per-core power gating in CNXXXX. */
uint64_t reserved_6_63 : 58;
#endif /* Word 0 - End */
} cnf95xx;
/* struct cavm_rst_pp_power_cnf95xx loki; */
};
typedef union cavm_rst_pp_power cavm_rst_pp_power_t;
#define CAVM_RST_PP_POWER CAVM_RST_PP_POWER_FUNC()
static inline uint64_t CAVM_RST_PP_POWER_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_PP_POWER_FUNC(void)
{
return 0x87e006001700ll;
}
#define typedef_CAVM_RST_PP_POWER cavm_rst_pp_power_t
#define bustype_CAVM_RST_PP_POWER CSR_TYPE_RSL
#define basename_CAVM_RST_PP_POWER "RST_PP_POWER"
#define device_bar_CAVM_RST_PP_POWER 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_PP_POWER 0
#define arguments_CAVM_RST_PP_POWER -1,-1,-1,-1
/**
* Register (RSL) rst_pp_power_stat
*
* RST Core-Power Status Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_pp_power_stat
{
uint64_t u;
struct cavm_rst_pp_power_stat_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_36_63 : 28;
uint64_t down : 36; /**< [ 35: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t down : 36; /**< [ 35: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_36_63 : 28;
#endif /* Word 0 - End */
} s;
struct cavm_rst_pp_power_stat_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_24_63 : 40;
uint64_t down : 24; /**< [ 23: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t down : 24; /**< [ 23: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_24_63 : 40;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_pp_power_stat_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_4_63 : 60;
uint64_t down : 4; /**< [ 3: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
#else /* Word 0 - Little Endian */
uint64_t down : 4; /**< [ 3: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_4_63 : 60;
#endif /* Word 0 - End */
} cn81xx;
/* struct cavm_rst_pp_power_stat_cn8 cn83xx; */
struct cavm_rst_pp_power_stat_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_36_63 : 28;
uint64_t down : 36; /**< [ 35: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t down : 36; /**< [ 35: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is reinitialized on a cold domain reset. */
uint64_t reserved_36_63 : 28;
#endif /* Word 0 - End */
} cn9;
struct cavm_rst_pp_power_stat_cn96xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_24_63 : 40;
uint64_t down : 24; /**< [ 23: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t down : 24; /**< [ 23: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is reinitialized on a cold domain reset. */
uint64_t reserved_24_63 : 40;
#endif /* Word 0 - End */
} cn96xx;
/* struct cavm_rst_pp_power_stat_cn9 cn98xx; */
struct cavm_rst_pp_power_stat_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_6_63 : 58;
uint64_t down : 6; /**< [ 5: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t down : 6; /**< [ 5: 0](RO/H) Reserved.
Internal:
Core Powerdown. When set, each bit indicates the core is currently powered down.
Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
core should be reset again by setting the RST_PP_RESET and then clearing it.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
This field is reinitialized on a cold domain reset. */
uint64_t reserved_6_63 : 58;
#endif /* Word 0 - End */
} cnf95xx;
/* struct cavm_rst_pp_power_stat_cnf95xx loki; */
};
typedef union cavm_rst_pp_power_stat cavm_rst_pp_power_stat_t;
#define CAVM_RST_PP_POWER_STAT CAVM_RST_PP_POWER_STAT_FUNC()
static inline uint64_t CAVM_RST_PP_POWER_STAT_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_PP_POWER_STAT_FUNC(void)
{
return 0x87e006001710ll;
}
#define typedef_CAVM_RST_PP_POWER_STAT cavm_rst_pp_power_stat_t
#define bustype_CAVM_RST_PP_POWER_STAT CSR_TYPE_RSL
#define basename_CAVM_RST_PP_POWER_STAT "RST_PP_POWER_STAT"
#define device_bar_CAVM_RST_PP_POWER_STAT 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_PP_POWER_STAT 0
#define arguments_CAVM_RST_PP_POWER_STAT -1,-1,-1,-1
/**
* Register (RSL) rst_pp_reset
*
* RST Core Reset Register
* This register contains the reset control for each core.
* Write operations to this register should occur only if
* RST_PP_PENDING is cleared.
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_pp_reset
{
uint64_t u;
struct cavm_rst_pp_reset_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_0_63 : 64;
#else /* Word 0 - Little Endian */
uint64_t reserved_0_63 : 64;
#endif /* Word 0 - End */
} s;
struct cavm_rst_pp_reset_cn8
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_24_63 : 40;
uint64_t rst : 23; /**< [ 23: 1](R/W/H) Core reset for cores 1 and above. Writing a 1 holds the corresponding core in reset,
writing a 0 releases from reset. These bits may also be cleared by either DAP or CIC
activity.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t rst0 : 1; /**< [ 0: 0](R/W/H) Core reset for core 0, depends on if GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE.
This bit may also be cleared by either DAP or CIC activity. */
#else /* Word 0 - Little Endian */
uint64_t rst0 : 1; /**< [ 0: 0](R/W/H) Core reset for core 0, depends on if GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE.
This bit may also be cleared by either DAP or CIC activity. */
uint64_t rst : 23; /**< [ 23: 1](R/W/H) Core reset for cores 1 and above. Writing a 1 holds the corresponding core in reset,
writing a 0 releases from reset. These bits may also be cleared by either DAP or CIC
activity.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_24_63 : 40;
#endif /* Word 0 - End */
} cn8;
struct cavm_rst_pp_reset_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_4_63 : 60;
uint64_t rst : 3; /**< [ 3: 1](R/W/H) Core reset for cores 1 and above. Writing a 1 holds the corresponding core in reset,
writing a 0 releases from reset. These bits may also be cleared by either DAP or CIC
activity.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t rst0 : 1; /**< [ 0: 0](R/W/H) Core reset for core 0, depends on if GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE.
This bit may also be cleared by either DAP or CIC activity. */
#else /* Word 0 - Little Endian */
uint64_t rst0 : 1; /**< [ 0: 0](R/W/H) Core reset for core 0, depends on if GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE.
This bit may also be cleared by either DAP or CIC activity. */
uint64_t rst : 3; /**< [ 3: 1](R/W/H) Core reset for cores 1 and above. Writing a 1 holds the corresponding core in reset,
writing a 0 releases from reset. These bits may also be cleared by either DAP or CIC
activity.
The upper bits of this field remain accessible but will have no effect if the cores
are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
uint64_t reserved_4_63 : 60;
#endif /* Word 0 - End */
} cn81xx;
/* struct cavm_rst_pp_reset_cn8 cn83xx; */
struct cavm_rst_pp_reset_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_36_63 : 28;
uint64_t rst : 36; /**< [ 35: 0](R/W/H) AP core resets. Writing a one holds the corresponding AP core in reset,
writing a zero releases it from reset. These bits may also be cleared by
either DAP or CIC activity.
This field is always reinitialized on a core domain reset. */
#else /* Word 0 - Little Endian */
uint64_t rst : 36; /**< [ 35: 0](R/W/H) AP core resets. Writing a one holds the corresponding AP core in reset,
writing a zero releases it from reset. These bits may also be cleared by
either DAP or CIC activity.
This field is always reinitialized on a core domain reset. */
uint64_t reserved_36_63 : 28;
#endif /* Word 0 - End */
} cn9;
struct cavm_rst_pp_reset_cn96xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_24_63 : 40;
uint64_t rst : 24; /**< [ 23: 0](R/W/H) AP core resets. Writing a one holds the corresponding AP core in reset,
writing a zero releases it from reset. These bits may also be cleared by
either DAP or CIC activity.
This field is always reinitialized on a core domain reset. */
#else /* Word 0 - Little Endian */
uint64_t rst : 24; /**< [ 23: 0](R/W/H) AP core resets. Writing a one holds the corresponding AP core in reset,
writing a zero releases it from reset. These bits may also be cleared by
either DAP or CIC activity.
This field is always reinitialized on a core domain reset. */
uint64_t reserved_24_63 : 40;
#endif /* Word 0 - End */
} cn96xx;
/* struct cavm_rst_pp_reset_cn9 cn98xx; */
struct cavm_rst_pp_reset_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_6_63 : 58;
uint64_t rst : 6; /**< [ 5: 0](R/W/H) AP core resets. Writing a one holds the corresponding AP core in reset,
writing a zero releases it from reset. These bits may also be cleared by
either DAP or CIC activity.
This field is always reinitialized on a core domain reset. */
#else /* Word 0 - Little Endian */
uint64_t rst : 6; /**< [ 5: 0](R/W/H) AP core resets. Writing a one holds the corresponding AP core in reset,
writing a zero releases it from reset. These bits may also be cleared by
either DAP or CIC activity.
This field is always reinitialized on a core domain reset. */
uint64_t reserved_6_63 : 58;
#endif /* Word 0 - End */
} cnf95xx;
/* struct cavm_rst_pp_reset_cnf95xx loki; */
};
typedef union cavm_rst_pp_reset cavm_rst_pp_reset_t;
#define CAVM_RST_PP_RESET CAVM_RST_PP_RESET_FUNC()
static inline uint64_t CAVM_RST_PP_RESET_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_PP_RESET_FUNC(void)
{
return 0x87e006001740ll;
}
#define typedef_CAVM_RST_PP_RESET cavm_rst_pp_reset_t
#define bustype_CAVM_RST_PP_RESET CSR_TYPE_RSL
#define basename_CAVM_RST_PP_RESET "RST_PP_RESET"
#define device_bar_CAVM_RST_PP_RESET 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_PP_RESET 0
#define arguments_CAVM_RST_PP_RESET -1,-1,-1,-1
/**
* Register (RSL) rst_ref_check
*
* INTERNAL: RST Reference Clock Checker Register
*
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_ref_check
{
uint64_t u;
struct cavm_rst_ref_check_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
* Reference clock was outside operating range of 25 to 100 MHz.
* Reference clock increased or decreased in frequency. */
uint64_t reserved_48_62 : 15;
uint64_t pcycle : 16; /**< [ 47: 32](RO/H) Previous cycle count. Sum of last [CNT0] and [CNT1]. */
uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was high.
When used with [CNT0] the internal ring-oscillator frequency can be determined. */
uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was low.
When used with [CNT1] the internal ring-oscillator frequency can be determined. */
#else /* Word 0 - Little Endian */
uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was low.
When used with [CNT1] the internal ring-oscillator frequency can be determined. */
uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was high.
When used with [CNT0] the internal ring-oscillator frequency can be determined. */
uint64_t pcycle : 16; /**< [ 47: 32](RO/H) Previous cycle count. Sum of last [CNT0] and [CNT1]. */
uint64_t reserved_48_62 : 15;
uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
* Reference clock was outside operating range of 25 to 100 MHz.
* Reference clock increased or decreased in frequency. */
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_ref_check_s cn8; */
struct cavm_rst_ref_check_cn81xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
* Reference clock was outside operating range of 25 to 100 MHz.
* Reference clock increased or decreased in frequency. */
uint64_t reserved_48_62 : 15;
uint64_t reserved_32_47 : 16;
uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was high.
When used with [CNT0] the internal ring-oscillator frequency can be determined. */
uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was low.
When used with [CNT1] the internal ring-oscillator frequency can be determined. */
#else /* Word 0 - Little Endian */
uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was low.
When used with [CNT1] the internal ring-oscillator frequency can be determined. */
uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was high.
When used with [CNT0] the internal ring-oscillator frequency can be determined. */
uint64_t reserved_32_47 : 16;
uint64_t reserved_48_62 : 15;
uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
* Reference clock was outside operating range of 25 to 100 MHz.
* Reference clock increased or decreased in frequency. */
#endif /* Word 0 - End */
} cn81xx;
/* struct cavm_rst_ref_check_s cn83xx; */
struct cavm_rst_ref_check_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
* Reference clock was outside operating range of 85 to 115 MHz.
* Reference increased or decreased in frequency.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t reserved_48_62 : 15;
uint64_t pcycle : 16; /**< [ 47: 32](RO/H) Previous cycle count. Sum of last [CNT0] and [CNT1]. */
uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was high.
When used with [CNT0] the internal ring-oscillator frequency can be determined.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was low.
When used with [CNT1] the internal ring-oscillator frequency can be determined.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
#else /* Word 0 - Little Endian */
uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was low.
When used with [CNT1] the internal ring-oscillator frequency can be determined.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
while reference clock was high.
When used with [CNT0] the internal ring-oscillator frequency can be determined.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
uint64_t pcycle : 16; /**< [ 47: 32](RO/H) Previous cycle count. Sum of last [CNT0] and [CNT1]. */
uint64_t reserved_48_62 : 15;
uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
* Reference clock was outside operating range of 85 to 115 MHz.
* Reference increased or decreased in frequency.
This field is reinitialized on a cold domain reset.
Internal:
This field is reinitialized on the falling edge of dcok. */
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_ref_check cavm_rst_ref_check_t;
#define CAVM_RST_REF_CHECK CAVM_RST_REF_CHECK_FUNC()
static inline uint64_t CAVM_RST_REF_CHECK_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_REF_CHECK_FUNC(void)
{
return 0x87e006001770ll;
}
#define typedef_CAVM_RST_REF_CHECK cavm_rst_ref_check_t
#define bustype_CAVM_RST_REF_CHECK CSR_TYPE_RSL
#define basename_CAVM_RST_REF_CHECK "RST_REF_CHECK"
#define device_bar_CAVM_RST_REF_CHECK 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_REF_CHECK 0
#define arguments_CAVM_RST_REF_CHECK -1,-1,-1,-1
/**
* Register (RSL) rst_ref_cntr
*
* RST Reference-Counter Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_ref_cntr
{
uint64_t u;
struct cavm_rst_ref_cntr_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t cnt : 64; /**< [ 63: 0](R/W/H) Count. The counter is initialized to 0x0 during a cold reset and is otherwise continuously
running.
CNT is incremented every reference-clock cycle (i.e. at 50 MHz). */
#else /* Word 0 - Little Endian */
uint64_t cnt : 64; /**< [ 63: 0](R/W/H) Count. The counter is initialized to 0x0 during a cold reset and is otherwise continuously
running.
CNT is incremented every reference-clock cycle (i.e. at 50 MHz). */
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_ref_cntr_s cn8; */
struct cavm_rst_ref_cntr_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t cnt : 64; /**< [ 63: 0](R/W/H) Reference count. [CNT] is incremented every 100 MHz reference clock.
This field is always reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t cnt : 64; /**< [ 63: 0](R/W/H) Reference count. [CNT] is incremented every 100 MHz reference clock.
This field is always reinitialized on a cold domain reset. */
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_ref_cntr cavm_rst_ref_cntr_t;
#define CAVM_RST_REF_CNTR CAVM_RST_REF_CNTR_FUNC()
static inline uint64_t CAVM_RST_REF_CNTR_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_REF_CNTR_FUNC(void)
{
return 0x87e006001758ll;
}
#define typedef_CAVM_RST_REF_CNTR cavm_rst_ref_cntr_t
#define bustype_CAVM_RST_REF_CNTR CSR_TYPE_RSL
#define basename_CAVM_RST_REF_CNTR "RST_REF_CNTR"
#define device_bar_CAVM_RST_REF_CNTR 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_REF_CNTR 0
#define arguments_CAVM_RST_REF_CNTR -1,-1,-1,-1
/**
* Register (RSL) rst_refc_ctl
*
* RST Common Reference Clock Input Control Register
* This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_refc_ctl
{
uint64_t u;
struct cavm_rst_refc_ctl_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_9_63 : 55;
uint64_t cclk2_sel : 2; /**< [ 8: 7](R/W) Common clock 2 termination select.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = HCSL termination.
The field is initialized on a cold domain reset. */
uint64_t cclk2_pwdn : 1; /**< [ 6: 6](R/W) Common clock 2 receiver power down.
When set, receiver is powered down.
The field is initialized on a cold domain reset.
Internal:
The receiver is also forced into powerdown when jtg__rst_pll.iddq_mode is set. */
uint64_t cclk1_sel : 2; /**< [ 5: 4](R/W) Common clock 1 termination select.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = HCSL termination.
The field is initialized on a cold domain reset. */
uint64_t cclk1_pwdn : 1; /**< [ 3: 3](R/W) Common clock 1 receiver power down.
When set, receiver is powered down.
The field is initialized on a cold domain reset.
Internal:
The receiver is also forced into powerdown when jtg__rst_pll.iddq_mode is set. */
uint64_t cclk0_sel : 2; /**< [ 2: 1](RO/H) Common clock 0 termination select determined by hardware.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = HCSL termination.
The value is determined at DC_OK assertion from the straps
GPIO_STRAP_PIN_E::GSER_CLK0_TERM_SEL0 and 1. */
uint64_t cclk0_pwdn : 1; /**< [ 0: 0](RAZ) Common clock 0 receiver power down.
Never powered down. Reads as zero. */
#else /* Word 0 - Little Endian */
uint64_t cclk0_pwdn : 1; /**< [ 0: 0](RAZ) Common clock 0 receiver power down.
Never powered down. Reads as zero. */
uint64_t cclk0_sel : 2; /**< [ 2: 1](RO/H) Common clock 0 termination select determined by hardware.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = HCSL termination.
The value is determined at DC_OK assertion from the straps
GPIO_STRAP_PIN_E::GSER_CLK0_TERM_SEL0 and 1. */
uint64_t cclk1_pwdn : 1; /**< [ 3: 3](R/W) Common clock 1 receiver power down.
When set, receiver is powered down.
The field is initialized on a cold domain reset.
Internal:
The receiver is also forced into powerdown when jtg__rst_pll.iddq_mode is set. */
uint64_t cclk1_sel : 2; /**< [ 5: 4](R/W) Common clock 1 termination select.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = HCSL termination.
The field is initialized on a cold domain reset. */
uint64_t cclk2_pwdn : 1; /**< [ 6: 6](R/W) Common clock 2 receiver power down.
When set, receiver is powered down.
The field is initialized on a cold domain reset.
Internal:
The receiver is also forced into powerdown when jtg__rst_pll.iddq_mode is set. */
uint64_t cclk2_sel : 2; /**< [ 8: 7](R/W) Common clock 2 termination select.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = HCSL termination.
The field is initialized on a cold domain reset. */
uint64_t reserved_9_63 : 55;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_refc_ctl_s cn9; */
/* struct cavm_rst_refc_ctl_s cn96xxp1; */
struct cavm_rst_refc_ctl_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_9_63 : 55;
uint64_t cclk2_sel : 2; /**< [ 8: 7](R/W) Reserved. See GSERR()_COMMON_PHY_CTRL_BCFG[REFCLK_HIZ_ENA]. */
uint64_t cclk2_pwdn : 1; /**< [ 6: 6](R/W) Reserved. See GSERR()_COMMON_PHY_CTRL_BCFG[REFCLK_PAD_ENA]. */
uint64_t cclk1_sel : 2; /**< [ 5: 4](R/W) Reserved. See GSERP()_COMMON_PHY_CTRL_BCFG[REFCLK_HIZ_ENA]. */
uint64_t cclk1_pwdn : 1; /**< [ 3: 3](R/W) Reserved. See GSERP()_COMMON_PHY_CTRL_BCFG[REFCLK_PAD_ENA]. */
uint64_t cclk0_sel : 2; /**< [ 2: 1](RO/H) Common clock 0 termination select determined by hardware.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = Reserved.
The value is determined at DC_OK assertion from the straps
GPIO_STRAP_PIN_E::GSER_CLK0_TERM_SEL0 and 1. */
uint64_t cclk0_pwdn : 1; /**< [ 0: 0](RAZ) Common clock 0 receiver power down.
Never powered down. Reads as zero. */
#else /* Word 0 - Little Endian */
uint64_t cclk0_pwdn : 1; /**< [ 0: 0](RAZ) Common clock 0 receiver power down.
Never powered down. Reads as zero. */
uint64_t cclk0_sel : 2; /**< [ 2: 1](RO/H) Common clock 0 termination select determined by hardware.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = Reserved.
The value is determined at DC_OK assertion from the straps
GPIO_STRAP_PIN_E::GSER_CLK0_TERM_SEL0 and 1. */
uint64_t cclk1_pwdn : 1; /**< [ 3: 3](R/W) Reserved. See GSERP()_COMMON_PHY_CTRL_BCFG[REFCLK_PAD_ENA]. */
uint64_t cclk1_sel : 2; /**< [ 5: 4](R/W) Reserved. See GSERP()_COMMON_PHY_CTRL_BCFG[REFCLK_HIZ_ENA]. */
uint64_t cclk2_pwdn : 1; /**< [ 6: 6](R/W) Reserved. See GSERR()_COMMON_PHY_CTRL_BCFG[REFCLK_PAD_ENA]. */
uint64_t cclk2_sel : 2; /**< [ 8: 7](R/W) Reserved. See GSERR()_COMMON_PHY_CTRL_BCFG[REFCLK_HIZ_ENA]. */
uint64_t reserved_9_63 : 55;
#endif /* Word 0 - End */
} cn96xxp3;
/* struct cavm_rst_refc_ctl_cn96xxp3 cn98xx; */
/* struct cavm_rst_refc_ctl_s cnf95xxp1; */
struct cavm_rst_refc_ctl_cnf95xxp2
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_9_63 : 55;
uint64_t cclk2_sel : 2; /**< [ 8: 7](R/W) Reserved. */
uint64_t cclk2_pwdn : 1; /**< [ 6: 6](R/W) Reserved. */
uint64_t cclk1_sel : 2; /**< [ 5: 4](R/W) Reserved. */
uint64_t cclk1_pwdn : 1; /**< [ 3: 3](R/W) Reserved. */
uint64_t cclk0_sel : 2; /**< [ 2: 1](RO/H) Common clock 0 termination select determined by hardware.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = Reserved.
The value is determined at DC_OK assertion from the straps
GPIO_STRAP_PIN_E::GSER_CLK0_TERM_SEL0 and 1. */
uint64_t cclk0_pwdn : 1; /**< [ 0: 0](RAZ) Common clock 0 receiver power down.
Never powered down. Reads as zero. */
#else /* Word 0 - Little Endian */
uint64_t cclk0_pwdn : 1; /**< [ 0: 0](RAZ) Common clock 0 receiver power down.
Never powered down. Reads as zero. */
uint64_t cclk0_sel : 2; /**< [ 2: 1](RO/H) Common clock 0 termination select determined by hardware.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = Reserved.
The value is determined at DC_OK assertion from the straps
GPIO_STRAP_PIN_E::GSER_CLK0_TERM_SEL0 and 1. */
uint64_t cclk1_pwdn : 1; /**< [ 3: 3](R/W) Reserved. */
uint64_t cclk1_sel : 2; /**< [ 5: 4](R/W) Reserved. */
uint64_t cclk2_pwdn : 1; /**< [ 6: 6](R/W) Reserved. */
uint64_t cclk2_sel : 2; /**< [ 8: 7](R/W) Reserved. */
uint64_t reserved_9_63 : 55;
#endif /* Word 0 - End */
} cnf95xxp2;
struct cavm_rst_refc_ctl_loki
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_9_63 : 55;
uint64_t cclk2_sel : 2; /**< [ 8: 7](R/W) Reserved. See GSERR/GSERC()_COMMON_PHY_CTRL_BCFG[REFCLK_HIZ_ENA]. */
uint64_t cclk2_pwdn : 1; /**< [ 6: 6](R/W) Reserved. See GSERR/GSERC()_COMMON_PHY_CTRL_BCFG[REFCLK_PAD_ENA]. */
uint64_t cclk1_sel : 2; /**< [ 5: 4](R/W) Reserved. See GSERP()_COMMON_PHY_CTRL_BCFG[REFCLK_HIZ_ENA]. */
uint64_t cclk1_pwdn : 1; /**< [ 3: 3](R/W) Reserved. See GSERP()_COMMON_PHY_CTRL_BCFG[REFCLK_PAD_ENA]. */
uint64_t cclk0_sel : 2; /**< [ 2: 1](RO/H) Common clock 0 termination select determined by hardware.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = Reserved.
The value is determined at DC_OK assertion from the straps
GPIO_STRAP_PIN_E::GSER_CLK0_TERM_SEL0 and 1. */
uint64_t cclk0_pwdn : 1; /**< [ 0: 0](RAZ) Common clock 0 receiver power down.
Never powered down. Reads as zero. */
#else /* Word 0 - Little Endian */
uint64_t cclk0_pwdn : 1; /**< [ 0: 0](RAZ) Common clock 0 receiver power down.
Never powered down. Reads as zero. */
uint64_t cclk0_sel : 2; /**< [ 2: 1](RO/H) Common clock 0 termination select determined by hardware.
0x0 = No termination.
0x1 = LVPECL termination.
0x2 = Reserved.
0x3 = Reserved.
The value is determined at DC_OK assertion from the straps
GPIO_STRAP_PIN_E::GSER_CLK0_TERM_SEL0 and 1. */
uint64_t cclk1_pwdn : 1; /**< [ 3: 3](R/W) Reserved. See GSERP()_COMMON_PHY_CTRL_BCFG[REFCLK_PAD_ENA]. */
uint64_t cclk1_sel : 2; /**< [ 5: 4](R/W) Reserved. See GSERP()_COMMON_PHY_CTRL_BCFG[REFCLK_HIZ_ENA]. */
uint64_t cclk2_pwdn : 1; /**< [ 6: 6](R/W) Reserved. See GSERR/GSERC()_COMMON_PHY_CTRL_BCFG[REFCLK_PAD_ENA]. */
uint64_t cclk2_sel : 2; /**< [ 8: 7](R/W) Reserved. See GSERR/GSERC()_COMMON_PHY_CTRL_BCFG[REFCLK_HIZ_ENA]. */
uint64_t reserved_9_63 : 55;
#endif /* Word 0 - End */
} loki;
};
typedef union cavm_rst_refc_ctl cavm_rst_refc_ctl_t;
#define CAVM_RST_REFC_CTL CAVM_RST_REFC_CTL_FUNC()
static inline uint64_t CAVM_RST_REFC_CTL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_REFC_CTL_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e00a001798ll;
__cavm_csr_fatal("RST_REFC_CTL", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_REFC_CTL cavm_rst_refc_ctl_t
#define bustype_CAVM_RST_REFC_CTL CSR_TYPE_RSL
#define basename_CAVM_RST_REFC_CTL "RST_REFC_CTL"
#define device_bar_CAVM_RST_REFC_CTL 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_REFC_CTL 0
#define arguments_CAVM_RST_REFC_CTL -1,-1,-1,-1
/**
* Register (RSL) rst_reset_active
*
* RST Domain Reset Active Status Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_reset_active
{
uint64_t u;
struct cavm_rst_reset_active_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_5_63 : 59;
uint64_t bphy : 1; /**< [ 4: 4](RO/H) BPHY domain reset status. When set, BPHY domain is in reset.
Default reset value is one after a chip or core reset. */
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain reset status. When set, SCP domain is in reset.
Default reset value is zero after a chip reset. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain reset status. When set, MCP domain is in reset.
Default reset value is one after a chip reset. */
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain reset status. When set, core domain is in reset.
Default reset value is one after a chip reset. */
uint64_t chip : 1; /**< [ 0: 0](RO/H) Chip domain reset status. Always reads 0. */
#else /* Word 0 - Little Endian */
uint64_t chip : 1; /**< [ 0: 0](RO/H) Chip domain reset status. Always reads 0. */
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain reset status. When set, core domain is in reset.
Default reset value is one after a chip reset. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain reset status. When set, MCP domain is in reset.
Default reset value is one after a chip reset. */
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain reset status. When set, SCP domain is in reset.
Default reset value is zero after a chip reset. */
uint64_t bphy : 1; /**< [ 4: 4](RO/H) BPHY domain reset status. When set, BPHY domain is in reset.
Default reset value is one after a chip or core reset. */
uint64_t reserved_5_63 : 59;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_reset_active_s cn9; */
struct cavm_rst_reset_active_cn96xxp1
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_4_63 : 60;
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain reset status. When set, SCP domain is in reset.
Default reset value is zero after a chip reset. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain reset status. When set, MCP domain is in reset.
Default reset value is one after a chip reset. */
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain reset status. When set, core domain is in reset.
Default reset value is one after a chip reset. */
uint64_t reserved_0 : 1;
#else /* Word 0 - Little Endian */
uint64_t reserved_0 : 1;
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain reset status. When set, core domain is in reset.
Default reset value is one after a chip reset. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain reset status. When set, MCP domain is in reset.
Default reset value is one after a chip reset. */
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain reset status. When set, SCP domain is in reset.
Default reset value is zero after a chip reset. */
uint64_t reserved_4_63 : 60;
#endif /* Word 0 - End */
} cn96xxp1;
struct cavm_rst_reset_active_cn96xxp3
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_4_63 : 60;
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain reset status. When set, SCP domain is in reset.
Default reset value is zero after a chip reset. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain reset status. When set, MCP domain is in reset.
Default reset value is one after a chip reset. */
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain reset status. When set, core domain is in reset.
Default reset value is one after a chip reset. */
uint64_t chip : 1; /**< [ 0: 0](RO/H) Chip domain reset status. Always reads 0. */
#else /* Word 0 - Little Endian */
uint64_t chip : 1; /**< [ 0: 0](RO/H) Chip domain reset status. Always reads 0. */
uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain reset status. When set, core domain is in reset.
Default reset value is one after a chip reset. */
uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain reset status. When set, MCP domain is in reset.
Default reset value is one after a chip reset. */
uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain reset status. When set, SCP domain is in reset.
Default reset value is zero after a chip reset. */
uint64_t reserved_4_63 : 60;
#endif /* Word 0 - End */
} cn96xxp3;
/* struct cavm_rst_reset_active_cn96xxp3 cn98xx; */
/* struct cavm_rst_reset_active_s cnf95xx; */
/* struct cavm_rst_reset_active_s loki; */
};
typedef union cavm_rst_reset_active cavm_rst_reset_active_t;
#define CAVM_RST_RESET_ACTIVE CAVM_RST_RESET_ACTIVE_FUNC()
static inline uint64_t CAVM_RST_RESET_ACTIVE_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_RESET_ACTIVE_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001888ll;
__cavm_csr_fatal("RST_RESET_ACTIVE", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_RESET_ACTIVE cavm_rst_reset_active_t
#define bustype_CAVM_RST_RESET_ACTIVE CSR_TYPE_RSL
#define basename_CAVM_RST_RESET_ACTIVE "RST_RESET_ACTIVE"
#define device_bar_CAVM_RST_RESET_ACTIVE 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_RESET_ACTIVE 0
#define arguments_CAVM_RST_RESET_ACTIVE -1,-1,-1,-1
/**
* Register (RSL) rst_rxp_pll
*
* RST Regular Expression Clock PLL Control Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_rxp_pll
{
uint64_t u;
struct cavm_rst_rxp_pll_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_51_63 : 13;
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) RXP clockout select.
0x0 = RXP clock divided by 32.
0x1 = RXP clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) RXP clockout reset. The RXP clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 rxp_clk/cpt_clk/sclk/rclk notification to
hardware. Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) RXP PLL1 power down. When set PLL is currently powered down. */
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) RXP PLL0 power down. When set PLL is currently powered down. */
uint64_t reserved_23_29 : 7;
uint64_t init_mul : 7; /**< [ 22: 16](R/W) RXP clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[RXP_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) RXP PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[RXP_MAX_MUL] and
a minimum setting of 200 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) RXP clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[RXP_MAX_MUL]. */
#else /* Word 0 - Little Endian */
uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) RXP clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
immediately after a cold or chip domain reset. In both cases, value
is limited by RST_PLL_LIMIT[RXP_MAX_MUL]. */
uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) RXP PLL frequency to be program in 50 MHz increments. The
actual value used is limited by RST_PLL_LIMIT[RXP_MAX_MUL] and
a minimum setting of 200 MHz.
Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
clears bit when both PLL is updated and any delay specified
in [DLY_SWITCH] has completed.
This field is always reinitialized on a chip domain reset. */
uint64_t init_mul : 7; /**< [ 22: 16](R/W) RXP clock multiplier to be used during a core or chip domain
reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
used is limited by RST_PLL_LIMIT[RXP_MAX_MUL].
This field maintains its current value when written with a zero.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_23_29 : 7;
uint64_t pll0_pd : 1; /**< [ 30: 30](RO) RXP PLL0 power down. When set PLL is currently powered down. */
uint64_t pll1_pd : 1; /**< [ 31: 31](RO) RXP PLL1 power down. When set PLL is currently powered down. */
uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
When set to a nonzero value, the hardware will wait for
any PLL programming to complete and then switch to the inactive
PLL after the specified number of PLL reference clocks. Hardware
will add additional clocks if required.
This field is always reinitialized on a cold domain reset.
Internal:
Hardware will add counts to maintain 256 rxp_clk/cpt_clk/sclk/rclk notification to
hardware. Additional time will be added to wake up powered-down AP cores but that
time not be included in this count. */
uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
powers down the inactive PLL after the switch has occurred.
When cleared, the inactive PLL remains in operation.
If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
[NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
Note that a powered-down PLL requires an additional 575 reference
clocks to become active. This time is automatically added by the
hardware.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_45_47 : 3;
uint64_t cout_reset : 1; /**< [ 48: 48](R/W) RXP clockout reset. The RXP clockout should be placed in
reset at least 10 PLL reference clocks prior
to changing [COUT_SEL]. It should remain under reset for at least 10
PLL reference clocks after [COUT_SEL] changes.
This field is always reinitialized on a cold domain reset. */
uint64_t cout_sel : 2; /**< [ 50: 49](R/W) RXP clockout select.
0x0 = RXP clock divided by 32.
0x1 = RXP clock tree output divided by 32.
0x2 = PLL0 output divided by 32.
0x3 = PLL1 output divided by 32.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_51_63 : 13;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_rxp_pll_s cn; */
};
typedef union cavm_rst_rxp_pll cavm_rst_rxp_pll_t;
#define CAVM_RST_RXP_PLL CAVM_RST_RXP_PLL_FUNC()
static inline uint64_t CAVM_RST_RXP_PLL_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_RXP_PLL_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN98XX))
return 0x87e00a0017a8ll;
__cavm_csr_fatal("RST_RXP_PLL", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_RXP_PLL cavm_rst_rxp_pll_t
#define bustype_CAVM_RST_RXP_PLL CSR_TYPE_RSL
#define basename_CAVM_RST_RXP_PLL "RST_RXP_PLL"
#define device_bar_CAVM_RST_RXP_PLL 0x2 /* PF_BAR2 */
#define busnum_CAVM_RST_RXP_PLL 0
#define arguments_CAVM_RST_RXP_PLL -1,-1,-1,-1
/**
* Register (RSL) rst_scp_domain_w1c
*
* RST SCP Domain Soft Reset Clear Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_scp_domain_w1c
{
uint64_t u;
struct cavm_rst_scp_domain_w1c_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear software-initiated reset of the SCP processor and associated logic.
When set to one, the soft reset of the SCP is removed.
Reads of this register show the soft reset state. Not the actual SCP domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[SCP] shows
the actual reset state. To compensate for delays in reset, this field should only
be set if RST_RESET_ACTIVE[SCP] is set.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear software-initiated reset of the SCP processor and associated logic.
When set to one, the soft reset of the SCP is removed.
Reads of this register show the soft reset state. Not the actual SCP domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[SCP] shows
the actual reset state. To compensate for delays in reset, this field should only
be set if RST_RESET_ACTIVE[SCP] is set.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_scp_domain_w1c_s cn; */
};
typedef union cavm_rst_scp_domain_w1c cavm_rst_scp_domain_w1c_t;
#define CAVM_RST_SCP_DOMAIN_W1C CAVM_RST_SCP_DOMAIN_W1C_FUNC()
static inline uint64_t CAVM_RST_SCP_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_SCP_DOMAIN_W1C_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001848ll;
__cavm_csr_fatal("RST_SCP_DOMAIN_W1C", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_SCP_DOMAIN_W1C cavm_rst_scp_domain_w1c_t
#define bustype_CAVM_RST_SCP_DOMAIN_W1C CSR_TYPE_RSL
#define basename_CAVM_RST_SCP_DOMAIN_W1C "RST_SCP_DOMAIN_W1C"
#define device_bar_CAVM_RST_SCP_DOMAIN_W1C 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_SCP_DOMAIN_W1C 0
#define arguments_CAVM_RST_SCP_DOMAIN_W1C -1,-1,-1,-1
/**
* Register (RSL) rst_scp_domain_w1s
*
* RST SCP Domain Soft Reset Set Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_scp_domain_w1s
{
uint64_t u;
struct cavm_rst_scp_domain_w1s_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set software-initiated reset of SCP core and associated logic.
When set to one, all logic associated with the SCP domain is placed in reset.
If RST_BOOT[RBOOT] is set, the SCP soft reset will stay asserted until
RST_SCP_DOMAIN_W1C is written. Otherwise it will automatically deassert.
Reads of this register show the soft reset state. Not the actual SCP domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[SCP] shows
the actual reset state.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set software-initiated reset of SCP core and associated logic.
When set to one, all logic associated with the SCP domain is placed in reset.
If RST_BOOT[RBOOT] is set, the SCP soft reset will stay asserted until
RST_SCP_DOMAIN_W1C is written. Otherwise it will automatically deassert.
Reads of this register show the soft reset state. Not the actual SCP domain reset.
Other factors may keep the reset active, reading RST_RESET_ACTIVE[SCP] shows
the actual reset state.
This field is always reinitialized on a chip domain reset. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_scp_domain_w1s_s cn; */
};
typedef union cavm_rst_scp_domain_w1s cavm_rst_scp_domain_w1s_t;
#define CAVM_RST_SCP_DOMAIN_W1S CAVM_RST_SCP_DOMAIN_W1S_FUNC()
static inline uint64_t CAVM_RST_SCP_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_SCP_DOMAIN_W1S_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001840ll;
__cavm_csr_fatal("RST_SCP_DOMAIN_W1S", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_SCP_DOMAIN_W1S cavm_rst_scp_domain_w1s_t
#define bustype_CAVM_RST_SCP_DOMAIN_W1S CSR_TYPE_RSL
#define basename_CAVM_RST_SCP_DOMAIN_W1S "RST_SCP_DOMAIN_W1S"
#define device_bar_CAVM_RST_SCP_DOMAIN_W1S 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_SCP_DOMAIN_W1S 0
#define arguments_CAVM_RST_SCP_DOMAIN_W1S -1,-1,-1,-1
/**
* Register (RSL) rst_soft_prst#
*
* RST PCIe Soft Reset Registers
* This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_soft_prstx
{
uint64_t u;
struct cavm_rst_soft_prstx_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_prst : 1; /**< [ 0: 0](R/W) Soft PCIe reset. Resets the PCIe logic and corresponding common logic associated with the
SLI controller in
all modes, not just RC mode.
* If RST_CTL()[HOST_MODE] = 0, [SOFT_PRST] resets to 0.
* If RST_CTL()[HOST_MODE] = 1, [SOFT_PRST] resets to 1.
When CNXXXX is configured to drive PERST*_L (i.e.
RST_CTL()[RST_DRV] = 1), this controls the output value on PERST*_L.
Internal:
This bit is also forced high if the corresponding PEM Cripple Fuse is set. */
#else /* Word 0 - Little Endian */
uint64_t soft_prst : 1; /**< [ 0: 0](R/W) Soft PCIe reset. Resets the PCIe logic and corresponding common logic associated with the
SLI controller in
all modes, not just RC mode.
* If RST_CTL()[HOST_MODE] = 0, [SOFT_PRST] resets to 0.
* If RST_CTL()[HOST_MODE] = 1, [SOFT_PRST] resets to 1.
When CNXXXX is configured to drive PERST*_L (i.e.
RST_CTL()[RST_DRV] = 1), this controls the output value on PERST*_L.
Internal:
This bit is also forced high if the corresponding PEM Cripple Fuse is set. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_soft_prstx_s cn8; */
struct cavm_rst_soft_prstx_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_prst : 1; /**< [ 0: 0](R/W/H) Soft PCIe reset. Resets the PEM and corresponding GSER SerDes logic.
This field is initialized as follows during cold domain resets:
* If RST_CTL()[HOST_MODE] is clear, [SOFT_PRST] resets to 0.
* If RST_CTL()[HOST_MODE] is set, [SOFT_PRST] resets to 1.
It is set by hardware under three conditions:
* If RST_CTL()[HOST_MODE] and the PEM domain is reset.
* If RST_CTL()[PRST_LINK] is set and the link goes down.
* If RST_CTL()[PRST_PWRDWN] is set and the PEM is powered down.
When RST_CTL()[RST_DRV] is set, this controls the output value on PERST*_L.
While RST_CTL()[RST_DRV] is set, hardware does not guarantee a minimum assertion time.
Table 2-4 in section 2.6.2 of the PCIE CEM spec states that PERST*_L must be
asserted for at least 100 us.
In the endpoint case, the hardware requires that this signal be set for a
minimum of 5 us to guarantee that the PCIe interface shuts down completely.
These time period must be implemented by software.
When RST_CTL()[RST_DRV] is clear and [SOFT_PRST] has been set by either hardware
or software, a minimum assertion time of 2uS is required.
Internal:
This bit is also forced high if the corresponding PEM cripple fuse is set. */
#else /* Word 0 - Little Endian */
uint64_t soft_prst : 1; /**< [ 0: 0](R/W/H) Soft PCIe reset. Resets the PEM and corresponding GSER SerDes logic.
This field is initialized as follows during cold domain resets:
* If RST_CTL()[HOST_MODE] is clear, [SOFT_PRST] resets to 0.
* If RST_CTL()[HOST_MODE] is set, [SOFT_PRST] resets to 1.
It is set by hardware under three conditions:
* If RST_CTL()[HOST_MODE] and the PEM domain is reset.
* If RST_CTL()[PRST_LINK] is set and the link goes down.
* If RST_CTL()[PRST_PWRDWN] is set and the PEM is powered down.
When RST_CTL()[RST_DRV] is set, this controls the output value on PERST*_L.
While RST_CTL()[RST_DRV] is set, hardware does not guarantee a minimum assertion time.
Table 2-4 in section 2.6.2 of the PCIE CEM spec states that PERST*_L must be
asserted for at least 100 us.
In the endpoint case, the hardware requires that this signal be set for a
minimum of 5 us to guarantee that the PCIe interface shuts down completely.
These time period must be implemented by software.
When RST_CTL()[RST_DRV] is clear and [SOFT_PRST] has been set by either hardware
or software, a minimum assertion time of 2uS is required.
Internal:
This bit is also forced high if the corresponding PEM cripple fuse is set. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} cn9;
/* struct cavm_rst_soft_prstx_cn9 cn96xx; */
/* struct cavm_rst_soft_prstx_cn9 cnf95xxp1; */
struct cavm_rst_soft_prstx_cnf95xxp2
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_prst : 1; /**< [ 0: 0](R/W/H) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Soft PCIe reset. Resets the PEM and corresponding GSER SerDes logic.
This field is initialized as follows during cold domain resets:
* If RST_CTL()[HOST_MODE] is clear, [SOFT_PRST] resets to 0.
* If RST_CTL()[HOST_MODE] is set, [SOFT_PRST] resets to 1.
It is set by hardware under three conditions:
* If RST_CTL()[HOST_MODE] and the PEM domain is reset.
* If RST_CTL()[PRST_LINK] is set and the link goes down.
* If RST_CTL()[PRST_PWRDWN] is set and the PEM is powered down.
When RST_CTL()[RST_DRV] is set, this controls the output value on PERST*_L.
While RST_CTL()[RST_DRV] is set, hardware does not guarantee a minimum assertion time.
Table 2-4 in section 2.6.2 of the PCIE CEM spec states that PERST*_L must be
asserted for at least 100 us.
In the endpoint case, the hardware requires that this signal be set for a
minimum of 5 us to guarantee that the PCIe interface shuts down completely.
These time period must be implemented by software.
When RST_CTL()[RST_DRV] is clear and [SOFT_PRST] has been set by either hardware
or software, a minimum assertion time of 2uS is required.
This bit is also forced high if the corresponding PEM cripple fuse is set. */
#else /* Word 0 - Little Endian */
uint64_t soft_prst : 1; /**< [ 0: 0](R/W/H) Reserved.
Internal:
In pass A0, but PCI is defeatured.
Soft PCIe reset. Resets the PEM and corresponding GSER SerDes logic.
This field is initialized as follows during cold domain resets:
* If RST_CTL()[HOST_MODE] is clear, [SOFT_PRST] resets to 0.
* If RST_CTL()[HOST_MODE] is set, [SOFT_PRST] resets to 1.
It is set by hardware under three conditions:
* If RST_CTL()[HOST_MODE] and the PEM domain is reset.
* If RST_CTL()[PRST_LINK] is set and the link goes down.
* If RST_CTL()[PRST_PWRDWN] is set and the PEM is powered down.
When RST_CTL()[RST_DRV] is set, this controls the output value on PERST*_L.
While RST_CTL()[RST_DRV] is set, hardware does not guarantee a minimum assertion time.
Table 2-4 in section 2.6.2 of the PCIE CEM spec states that PERST*_L must be
asserted for at least 100 us.
In the endpoint case, the hardware requires that this signal be set for a
minimum of 5 us to guarantee that the PCIe interface shuts down completely.
These time period must be implemented by software.
When RST_CTL()[RST_DRV] is clear and [SOFT_PRST] has been set by either hardware
or software, a minimum assertion time of 2uS is required.
This bit is also forced high if the corresponding PEM cripple fuse is set. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} cnf95xxp2;
};
typedef union cavm_rst_soft_prstx cavm_rst_soft_prstx_t;
static inline uint64_t CAVM_RST_SOFT_PRSTX(unsigned long a) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_SOFT_PRSTX(unsigned long a)
{
if (cavm_is_model(OCTEONTX_CN81XX) && (a<=2))
return 0x87e0060016c0ll + 8ll * ((a) & 0x3);
if (cavm_is_model(OCTEONTX_CN83XX) && (a<=3))
return 0x87e0060016c0ll + 8ll * ((a) & 0x3);
if (cavm_is_model(OCTEONTX_CN96XX_PASS1_X) && (a<=3))
return 0x87e0060016c0ll + 8ll * ((a) & 0x3);
if (cavm_is_model(OCTEONTX_CNF95XX) && (a==0))
return 0x87e0060016c0ll + 8ll * ((a) & 0x0);
__cavm_csr_fatal("RST_SOFT_PRSTX", 1, a, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_SOFT_PRSTX(a) cavm_rst_soft_prstx_t
#define bustype_CAVM_RST_SOFT_PRSTX(a) CSR_TYPE_RSL
#define basename_CAVM_RST_SOFT_PRSTX(a) "RST_SOFT_PRSTX"
#define device_bar_CAVM_RST_SOFT_PRSTX(a) 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_SOFT_PRSTX(a) (a)
#define arguments_CAVM_RST_SOFT_PRSTX(a) (a),-1,-1,-1
/**
* Register (RSL) rst_soft_rst
*
* RST Soft Reset Register
*/
union cavm_rst_soft_rst
{
uint64_t u;
struct cavm_rst_soft_rst_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_1_63 : 63;
uint64_t soft_rst : 1; /**< [ 0: 0](WO) Soft reset. When set to 1, resets the CNXXXX core. When performing a soft reset from a
remote PCIe host,
always read this register and wait for the results before setting [SOFT_RST] to 1. */
#else /* Word 0 - Little Endian */
uint64_t soft_rst : 1; /**< [ 0: 0](WO) Soft reset. When set to 1, resets the CNXXXX core. When performing a soft reset from a
remote PCIe host,
always read this register and wait for the results before setting [SOFT_RST] to 1. */
uint64_t reserved_1_63 : 63;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_soft_rst_s cn; */
};
typedef union cavm_rst_soft_rst cavm_rst_soft_rst_t;
#define CAVM_RST_SOFT_RST CAVM_RST_SOFT_RST_FUNC()
static inline uint64_t CAVM_RST_SOFT_RST_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_SOFT_RST_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN8XXX))
return 0x87e006001680ll;
__cavm_csr_fatal("RST_SOFT_RST", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_SOFT_RST cavm_rst_soft_rst_t
#define bustype_CAVM_RST_SOFT_RST CSR_TYPE_RSL
#define basename_CAVM_RST_SOFT_RST "RST_SOFT_RST"
#define device_bar_CAVM_RST_SOFT_RST 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_SOFT_RST 0
#define arguments_CAVM_RST_SOFT_RST -1,-1,-1,-1
/**
* Register (RSL) rst_src_map
*
* RST Source Domain Map Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_src_map
{
uint64_t u;
struct cavm_rst_src_map_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_13_63 : 51;
uint64_t ocx_to_chip : 1; /**< [ 12: 12](R/W) Reserved.
Internal:
OCX linkdown mapped to chip domain reset.
When RST_OCX[RST_LINK] is set:
0 = OCX transition from link up to link down will cause a core domain reset.
1 = OCX transition from link up to link down will cause both a core domain reset
and a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_11 : 1;
uint64_t scp_to_mcp : 1; /**< [ 10: 10](R/W) SCP watchdog and pin resets mapped to MCP domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause an MCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t scp_to_core : 1; /**< [ 9: 9](R/W) SCP watchdog and pin resets mapped to core domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause a core domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t scp_to_chip : 1; /**< [ 8: 8](R/W) SCP watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t mcp_to_scp : 1; /**< [ 7: 7](R/W) MCP watchdog and pin resets mapped to SCP domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause an SCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_6 : 1;
uint64_t mcp_to_core : 1; /**< [ 5: 5](R/W) MCP watchdog and pin resets mapped to core domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause a core domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t mcp_to_chip : 1; /**< [ 4: 4](R/W) MCP watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t core_to_scp : 1; /**< [ 3: 3](R/W) Core watchdog and pin resets mapped to SCP domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause an SCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t core_to_mcp : 1; /**< [ 2: 2](R/W) Core watchdog and pin resets mapped to MCP domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause an MCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_1 : 1;
uint64_t core_to_chip : 1; /**< [ 0: 0](R/W) Core watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t core_to_chip : 1; /**< [ 0: 0](R/W) Core watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_1 : 1;
uint64_t core_to_mcp : 1; /**< [ 2: 2](R/W) Core watchdog and pin resets mapped to MCP domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause an MCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t core_to_scp : 1; /**< [ 3: 3](R/W) Core watchdog and pin resets mapped to SCP domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause an SCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t mcp_to_chip : 1; /**< [ 4: 4](R/W) MCP watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t mcp_to_core : 1; /**< [ 5: 5](R/W) MCP watchdog and pin resets mapped to core domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause a core domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_6 : 1;
uint64_t mcp_to_scp : 1; /**< [ 7: 7](R/W) MCP watchdog and pin resets mapped to SCP domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause an SCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t scp_to_chip : 1; /**< [ 8: 8](R/W) SCP watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t scp_to_core : 1; /**< [ 9: 9](R/W) SCP watchdog and pin resets mapped to core domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause a core domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t scp_to_mcp : 1; /**< [ 10: 10](R/W) SCP watchdog and pin resets mapped to MCP domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause an MCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_11 : 1;
uint64_t ocx_to_chip : 1; /**< [ 12: 12](R/W) Reserved.
Internal:
OCX linkdown mapped to chip domain reset.
When RST_OCX[RST_LINK] is set:
0 = OCX transition from link up to link down will cause a core domain reset.
1 = OCX transition from link up to link down will cause both a core domain reset
and a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_13_63 : 51;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_src_map_s cn9; */
/* struct cavm_rst_src_map_s cn96xx; */
/* struct cavm_rst_src_map_s cn98xx; */
struct cavm_rst_src_map_cnf95xx
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_13_63 : 51;
uint64_t ocx_to_chip : 1; /**< [ 12: 12](R/W) Reserved.
Internal:
OCX linkdown mapped to chip domain reset.
When RST_OCX[RST_LINK] is set:
0 = OCX transition from link up to link down will cause a core domain reset.
1 = OCX transition from link up to link down will cause both a core domain reset
and a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_11 : 1;
uint64_t scp_to_mcp : 1; /**< [ 10: 10](R/W) SCP watchdog and pin resets mapped to MCP domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause an MCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t scp_to_core : 1; /**< [ 9: 9](R/W) SCP watchdog and pin resets mapped to core domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause a core domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t scp_to_chip : 1; /**< [ 8: 8](R/W) SCP watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t mcp_to_scp : 1; /**< [ 7: 7](R/W) MCP watchdog and pin resets mapped to SCP domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause an SCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_6 : 1;
uint64_t mcp_to_core : 1; /**< [ 5: 5](R/W) MCP watchdog and pin resets mapped to core domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause a core domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t mcp_to_chip : 1; /**< [ 4: 4](R/W) MCP watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t core_to_scp : 1; /**< [ 3: 3](R/W) Core watchdog and pin resets mapped to SCP domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause an SCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t core_to_mcp : 1; /**< [ 2: 2](R/W) Core watchdog and pin resets mapped to MCP domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause an MCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_1 : 1;
uint64_t core_to_chip : 1; /**< [ 0: 0](R/W) Core watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
#else /* Word 0 - Little Endian */
uint64_t core_to_chip : 1; /**< [ 0: 0](R/W) Core watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_1 : 1;
uint64_t core_to_mcp : 1; /**< [ 2: 2](R/W) Core watchdog and pin resets mapped to MCP domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause an MCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t core_to_scp : 1; /**< [ 3: 3](R/W) Core watchdog and pin resets mapped to SCP domain reset.
0 = Mapping disabled.
1 = Core reset pin or the AP watchdog will additionally
cause an SCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t mcp_to_chip : 1; /**< [ 4: 4](R/W) MCP watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t mcp_to_core : 1; /**< [ 5: 5](R/W) MCP watchdog and pin resets mapped to core domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause a core domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_6 : 1;
uint64_t mcp_to_scp : 1; /**< [ 7: 7](R/W) MCP watchdog and pin resets mapped to SCP domain reset.
0 = Mapping disabled.
1 = MCP reset pin or the MCP watchdog will additionally
cause an SCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t scp_to_chip : 1; /**< [ 8: 8](R/W) SCP watchdog and pin resets mapped to chip domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t scp_to_core : 1; /**< [ 9: 9](R/W) SCP watchdog and pin resets mapped to core domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause a core domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t scp_to_mcp : 1; /**< [ 10: 10](R/W) SCP watchdog and pin resets mapped to MCP domain reset.
0 = Mapping disabled.
1 = SCP reset pin or the SCP watchdog will additionally
cause an MCP domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_11 : 1;
uint64_t ocx_to_chip : 1; /**< [ 12: 12](R/W) Reserved.
Internal:
OCX linkdown mapped to chip domain reset.
When RST_OCX[RST_LINK] is set:
0 = OCX transition from link up to link down will cause a core domain reset.
1 = OCX transition from link up to link down will cause both a core domain reset
and a chip domain reset.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_13_63 : 51;
#endif /* Word 0 - End */
} cnf95xx;
/* struct cavm_rst_src_map_cnf95xx loki; */
};
typedef union cavm_rst_src_map cavm_rst_src_map_t;
#define CAVM_RST_SRC_MAP CAVM_RST_SRC_MAP_FUNC()
static inline uint64_t CAVM_RST_SRC_MAP_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_SRC_MAP_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e006001898ll;
__cavm_csr_fatal("RST_SRC_MAP", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_SRC_MAP cavm_rst_src_map_t
#define bustype_CAVM_RST_SRC_MAP CSR_TYPE_RSL
#define basename_CAVM_RST_SRC_MAP "RST_SRC_MAP"
#define device_bar_CAVM_RST_SRC_MAP 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_SRC_MAP 0
#define arguments_CAVM_RST_SRC_MAP -1,-1,-1,-1
/**
* Register (RSL) rst_sw_w1s
*
* RST Software W1S Data Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_sw_w1s
{
uint64_t u;
struct cavm_rst_sw_w1s_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t data : 64; /**< [ 63: 0](R/W1S) Data register that can be set by software and is only cleared
on initialization.
This field is always reinitialized on a chip domain reset. */
#else /* Word 0 - Little Endian */
uint64_t data : 64; /**< [ 63: 0](R/W1S) Data register that can be set by software and is only cleared
on initialization.
This field is always reinitialized on a chip domain reset. */
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_sw_w1s_s cn; */
};
typedef union cavm_rst_sw_w1s cavm_rst_sw_w1s_t;
#define CAVM_RST_SW_W1S CAVM_RST_SW_W1S_FUNC()
static inline uint64_t CAVM_RST_SW_W1S_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_SW_W1S_FUNC(void)
{
if (cavm_is_model(OCTEONTX_CN9XXX))
return 0x87e0060017f0ll;
__cavm_csr_fatal("RST_SW_W1S", 0, 0, 0, 0, 0, 0, 0);
}
#define typedef_CAVM_RST_SW_W1S cavm_rst_sw_w1s_t
#define bustype_CAVM_RST_SW_W1S CSR_TYPE_RSL
#define basename_CAVM_RST_SW_W1S "RST_SW_W1S"
#define device_bar_CAVM_RST_SW_W1S 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_SW_W1S 0
#define arguments_CAVM_RST_SW_W1S -1,-1,-1,-1
/**
* Register (RSL) rst_thermal_alert
*
* RST Thermal Alert Register
* This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
*/
union cavm_rst_thermal_alert
{
uint64_t u;
struct cavm_rst_thermal_alert_s
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_9_63 : 55;
uint64_t trip : 1; /**< [ 8: 8](R/W1S/H) Thermal trip pin. When set to 1, drives the THERMAL_TRIP_N pin active low. This field is
set by either of the
on-board temperature sensors reaching a failure threshold or writing this bit.
The bit can only be cleared by a deassertion of the PLL_DC_OK pin which completely resets
the chip. */
uint64_t reserved_1_7 : 7;
uint64_t alert : 1; /**< [ 0: 0](RO/H) Thermal alert status. When set to 1, indicates the temperature sensor is currently at the
failure threshold. */
#else /* Word 0 - Little Endian */
uint64_t alert : 1; /**< [ 0: 0](RO/H) Thermal alert status. When set to 1, indicates the temperature sensor is currently at the
failure threshold. */
uint64_t reserved_1_7 : 7;
uint64_t trip : 1; /**< [ 8: 8](R/W1S/H) Thermal trip pin. When set to 1, drives the THERMAL_TRIP_N pin active low. This field is
set by either of the
on-board temperature sensors reaching a failure threshold or writing this bit.
The bit can only be cleared by a deassertion of the PLL_DC_OK pin which completely resets
the chip. */
uint64_t reserved_9_63 : 55;
#endif /* Word 0 - End */
} s;
/* struct cavm_rst_thermal_alert_s cn8; */
struct cavm_rst_thermal_alert_cn9
{
#if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
uint64_t reserved_9_63 : 55;
uint64_t trip : 1; /**< [ 8: 8](R/W1S/H) Thermal trip pin. When set, drives the THERMAL_TRIP_L pin active low.
This field is set by one of the on-board temperature sensors reaching a
failure threshold or writing this bit.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_1_7 : 7;
uint64_t alert : 1; /**< [ 0: 0](RO/H) Thermal alert status. When set to one, indicates a temperature sensor is
currently at the failure threshold. */
#else /* Word 0 - Little Endian */
uint64_t alert : 1; /**< [ 0: 0](RO/H) Thermal alert status. When set to one, indicates a temperature sensor is
currently at the failure threshold. */
uint64_t reserved_1_7 : 7;
uint64_t trip : 1; /**< [ 8: 8](R/W1S/H) Thermal trip pin. When set, drives the THERMAL_TRIP_L pin active low.
This field is set by one of the on-board temperature sensors reaching a
failure threshold or writing this bit.
This field is always reinitialized on a cold domain reset. */
uint64_t reserved_9_63 : 55;
#endif /* Word 0 - End */
} cn9;
};
typedef union cavm_rst_thermal_alert cavm_rst_thermal_alert_t;
#define CAVM_RST_THERMAL_ALERT CAVM_RST_THERMAL_ALERT_FUNC()
static inline uint64_t CAVM_RST_THERMAL_ALERT_FUNC(void) __attribute__ ((pure, always_inline));
static inline uint64_t CAVM_RST_THERMAL_ALERT_FUNC(void)
{
return 0x87e006001690ll;
}
#define typedef_CAVM_RST_THERMAL_ALERT cavm_rst_thermal_alert_t
#define bustype_CAVM_RST_THERMAL_ALERT CSR_TYPE_RSL
#define basename_CAVM_RST_THERMAL_ALERT "RST_THERMAL_ALERT"
#define device_bar_CAVM_RST_THERMAL_ALERT 0x0 /* PF_BAR0 */
#define busnum_CAVM_RST_THERMAL_ALERT 0
#define arguments_CAVM_RST_THERMAL_ALERT -1,-1,-1,-1
#endif /* __CAVM_CSRS_RST_H__ */
| 81.384039 | 166 | 0.442719 |
acff0ae52aac96fd5559aab5c4c03b8d8fec09b7 | 8,893 | c | C | homework/ch5/progs/prog5.6_omp_producer_consumer.c | impact-eintr/ipp-seurce | cb5bdfa6e9c4a66b9806ff6853ef3406240f7566 | [
"MIT"
] | 4 | 2021-07-07T07:02:12.000Z | 2021-12-09T13:01:53.000Z | homework/ch5/progs/prog5.6_omp_producer_consumer.c | impact-eintr/ipp-seurce | cb5bdfa6e9c4a66b9806ff6853ef3406240f7566 | [
"MIT"
] | null | null | null | homework/ch5/progs/prog5.6_omp_producer_consumer.c | impact-eintr/ipp-seurce | cb5bdfa6e9c4a66b9806ff6853ef3406240f7566 | [
"MIT"
] | 6 | 2021-07-07T07:02:27.000Z | 2022-01-23T07:11:48.000Z | /* File: prog5.6_omp_producer_comsumer.c
* Purpose: Implement a producer-consumer program in which some of the
* threads are producers and others are consumers. The
* producers read text from a collection of files, one per
* producer. They insert lines of text into a single shared
* queue. The consumers take the lines of text and tokenize
* them -- i.e., identify strings of characters separated by
* whitespace from the rest of the line. When a consumer
* finds a token, it writes to stdout.
*
* Compile: gcc -g -Wall -fopenmp -o prog5.6_omp_producer_comsumer
* prog5.6_omp_producer_comsumer.c
* Run: ./prog5.6_omp_producer_comsumer <producers> <consumers>
*
* Input: A file that contains list of filename to read as input text
* Output: Output tokens or strings of characters separated from the
* rest of the input by whitespace
*
* Notes:
* 1. There must be at least one producer and one consumer
* 2. There are two critical sections
* - One is protected by an atomic clause in Prod_cons
* - The other is protected by critical directives: one
* in Enqueue and the other in Dequeue
*
* IPP: Programming Assignment 5.6
*
*/
#include <stdio.h>
#include <stdlib.h>
#include <omp.h>
#include <string.h>
const int MAX_FILES = 50;
const int MAX_CHAR = 100;
/* struct for queue */
struct list_node_s {
char* data;
struct list_node_s* next;
};
void Usage(char* prog_name);
void Prod_cons(int prod_count, int cons_count, FILE* files[], int file_count);
void Get_files(FILE* files[], int* file_count_p);
void Read_file(FILE* file, struct list_node_s** queue_head,
struct list_node_s** queue_tail, int my_rank);
void Enqueue(char* line, struct list_node_s** queue_head,
struct list_node_s** queue_tail);
struct list_node_s* Dequeue(struct list_node_s** queue_head,
struct list_node_s** queue_tail, int my_rank);
void Tokenize(char* data, int my_rank);
void Print_queue(int my_rank, struct list_node_s* queue_head);
int main(int argc, char* argv[]) {
int prod_count, cons_count;
FILE* files[MAX_FILES];
int file_count;
if (argc != 3) Usage(argv[0]);
prod_count = strtol(argv[1], NULL, 10);
cons_count = strtol(argv[2], NULL, 10);
/* Read in list of filenames and open files */
Get_files(files, &file_count);
# ifdef DEBUG
printf("prod_count = %d, cons_count = %d, file_count = %d\n",
prod_count, cons_count, file_count);
# endif
/* Producer-consumer */
Prod_cons(prod_count, cons_count, files, file_count);
return 0;
} /* main */
/*--------------------------------------------------------------------
* Function: Usage
* Purpose: Print command line for function and terminate
* In arg: prog_name
*/
void Usage(char* prog_name) {
fprintf(stderr, "usage: %s <producer count> <consumer count>\n",
prog_name);
exit(0);
} /* Usage */
/*--------------------------------------------------------------------
* Function: Get_files
* Purpose: Read list of files and open them
* Out args: files: array of files
* file_count_p: total number of files
*/
void Get_files(FILE* files[], int* file_count_p) {
int i = 0;
char filename[MAX_CHAR];
while (scanf("%s", filename) != -1) {
files[i] = fopen(filename, "r");
# ifdef DEBUG
printf("file %d = %s, desc = %p\n", i, filename, files[i]);
# endif
if (files[i] == NULL) {
fprintf(stderr, "Can't open %s\n", filename);
fprintf(stderr, "Quitting . . . \n");
exit(-1);
}
i++;
}
*file_count_p = i;
} /* Get_files */
/*--------------------------------------------------------------------
* Function: Prod_cons
* Purpose: Divides tasks among threads
* In args: thread_count, files, file_count
*/
void Prod_cons(int prod_count, int cons_count, FILE* files[],
int file_count) {
int thread_count = prod_count + cons_count;
struct list_node_s* queue_head = NULL;
struct list_node_s* queue_tail = NULL;
int prod_done_count = 0;
# pragma omp parallel num_threads(thread_count) default(none) \
shared(file_count, queue_head, queue_tail, files, prod_count, \
cons_count, prod_done_count)
{
int my_rank = omp_get_thread_num(), f;
if (my_rank < prod_count) {
/* Producer code */
/* A cyclic partition of the files among the producers */
for (f = my_rank; f < file_count; f += prod_count) {
# ifdef DEBUG
printf("Th %d > about to read file %d\n", my_rank, f);
# endif
Read_file(files[f], &queue_head, &queue_tail, my_rank);
# ifdef DEBUG
// Print_queue(my_rank, queue_head);
# endif
}
# pragma omp atomic
prod_done_count++;
} else {
/* Consumer code */
struct list_node_s* tmp_node;
while (prod_done_count < prod_count) {
tmp_node = Dequeue(&queue_head, &queue_tail, my_rank);
if (tmp_node != NULL) {
Tokenize(tmp_node->data, my_rank);
free(tmp_node);
}
}
# ifdef DEBUG
// Print_queue(my_rank, queue_head);
# endif
while (queue_head != NULL) {
tmp_node = Dequeue(&queue_head, &queue_tail, my_rank);
if (tmp_node != NULL) {
Tokenize(tmp_node->data, my_rank);
free(tmp_node);
}
}
}
} /* pragma omp parallel */
} /* Prod_cons */
/*--------------------------------------------------------------------
* Function: Read_file
* Purpose: read text line from file into the queue linkedlist
* In arg: file, my_rank
* In/out arg: queue_head, queue_tail
*/
void Read_file(FILE* file, struct list_node_s** queue_head,
struct list_node_s** queue_tail, int my_rank) {
char* line = malloc(MAX_CHAR*sizeof(char));
while (fgets(line, MAX_CHAR, file) != NULL) {
printf("Th %d > read line: %s", my_rank, line);
Enqueue(line, queue_head, queue_tail);
line = malloc(MAX_CHAR*sizeof(char));
}
fclose(file);
} /* Read_file */
/*--------------------------------------------------------------------
* Function: Enqueue
* Purpose: create data node, add into queue linkedlist
* In arg: line
* In/out arg: queue_head, queue_tail
*/
void Enqueue(char* line, struct list_node_s** queue_head,
struct list_node_s** queue_tail) {
struct list_node_s* tmp_node = NULL;
tmp_node = malloc(sizeof(struct list_node_s));
tmp_node->data = line;
tmp_node->next = NULL;
# pragma omp critical
if (*queue_tail == NULL) { // list is empty
*queue_head = tmp_node;
*queue_tail = tmp_node;
} else {
(*queue_tail)->next = tmp_node;
*queue_tail = tmp_node;
}
} /* Enqueue */
/*--------------------------------------------------------------------
* Function: Dequeue
* Purpose: remove a node from queue linkedlist and tokenize them
* In arg: my_rank
* In/out arg: queue_head, queue_tail
* Ret val: Node at head of queue, or NULL if queue is empty
*/
struct list_node_s* Dequeue(struct list_node_s** queue_head,
struct list_node_s** queue_tail, int my_rank) {
struct list_node_s* tmp_node = NULL;
if (*queue_head == NULL) // empty
return NULL;
# pragma omp critical
{
if (*queue_head == *queue_tail) // last node
*queue_tail = (*queue_tail)->next;
tmp_node = *queue_head;
*queue_head = (*queue_head)->next;
}
return tmp_node;
} /* Dequeue */
/*--------------------------------------------------------------------
* Function: Tokenize
* Purpose: Identify words (i.e., sequences of characters separated
* by white space and print them out)
* In arg: data, my_rank
*
*/
void Tokenize(char* data, int my_rank) {
char* my_token, *word;
# ifdef DEBUG
printf("Th %d > dequeue line: %s\n", my_rank, data);
# endif
my_token = strtok_r(data, " \t\n", &word);
while (my_token != NULL) {
printf("Th %d token: %s\n", my_rank, my_token);
my_token = strtok_r(NULL, " \t\n", &word);
}
} /* Tokenize */
/*--------------------------------------------------------------------
* Function: Print_queue
* Purpose: Print the contents of the queue
* In args: queue_head, queue_tail
*/
void Print_queue(int my_rank, struct list_node_s* queue_head) {
struct list_node_s* curr_p = queue_head;
printf("Th %d > queue = \n", my_rank);
# pragma omp critical
while (curr_p != NULL) {
printf("%s", curr_p->data);
curr_p = curr_p->next;
}
printf("\n");
} /* Print_queue */
| 31.31338 | 78 | 0.577308 |
3514d2c9201aeacbc6435693e80bd52766795b28 | 5,227 | h | C | SPHINXsys/src/shared/materials/weakly_compressible_fluid.h | buaayhq/SPHinXsys | 7cde66340a3fb3244ef4c252bd99c053a81ca181 | [
"Apache-2.0"
] | null | null | null | SPHINXsys/src/shared/materials/weakly_compressible_fluid.h | buaayhq/SPHinXsys | 7cde66340a3fb3244ef4c252bd99c053a81ca181 | [
"Apache-2.0"
] | null | null | null | SPHINXsys/src/shared/materials/weakly_compressible_fluid.h | buaayhq/SPHinXsys | 7cde66340a3fb3244ef4c252bd99c053a81ca181 | [
"Apache-2.0"
] | null | null | null | /* -------------------------------------------------------------------------*
* SPHinXsys *
* --------------------------------------------------------------------------*
* SPHinXsys (pronunciation: s'finksis) is an acronym from Smoothed Particle *
* Hydrodynamics for industrial compleX systems. It provides C++ APIs for *
* physical accurate simulation and aims to model coupled industrial dynamic *
* systems including fluid, solid, multi-body dynamics and beyond with SPH *
* (smoothed particle hydrodynamics), a meshless computational method using *
* particle discretization. *
* *
* SPHinXsys is partially funded by German Research Foundation *
* (Deutsche Forschungsgemeinschaft) DFG HU1527/6-1, HU1527/10-1 *
* and HU1527/12-1. *
* *
* Portions copyright (c) 2017-2020 Technical University of Munich and *
* the authors' affiliations. *
* *
* Licensed under the Apache License, Version 2.0 (the "License"); you may *
* not use this file except in compliance with the License. You may obtain a *
* copy of the License at http://www.apache.org/licenses/LICENSE-2.0. *
* *
* --------------------------------------------------------------------------*/
/**
* @file weakly_compressible_fluid.h
* @brief Describe the weakly compressible fluid which is used
* model incompressible fluids. Here, we have included several equation of states.
* Futhermore, A typical non-newtonian fluid model is included.
* @author Xiangyu Hu, Luhui Han and Chi Zhang
*/
#ifndef WEAKLY_COMPRESSIBLE_FLUID_H
#define WEAKLY_COMPRESSIBLE_FLUID_H
#include "base_material.h"
namespace SPH
{
class ViscoelasticFluidParticles;
/**
* @class WeaklyCompressibleFluid
* @brief Linear equation of state (EOS).
*/
class WeaklyCompressibleFluid : public Fluid
{
protected:
Real c0_, p0_; /**< reference sound speed and pressure */
public:
explicit WeaklyCompressibleFluid(Real rho0, Real c0, Real mu = 0.0)
: Fluid(rho0, mu), c0_(c0), p0_(rho0 * c0 * c0)
{
material_type_ = "WeaklyCompressibleFluid";
};
virtual ~WeaklyCompressibleFluid(){};
Real ReferenceSoundSpeed() { return c0_; };
virtual Real getPressure(Real rho) override;
virtual Real DensityFromPressure(Real p) override;
virtual Real getSoundSpeed(Real p = 0.0, Real rho = 1.0) override;
virtual WeaklyCompressibleFluid *ThisObjectPtr() override { return this; };
};
/**
* @class WeaklyCompressibleFluidFreeSurface
* @brief Equation of state (EOS) with cut-off pressure.
*/
template <class WeaklyCompressibleFluidType>
class WeaklyCompressibleFluidFreeSurface : public WeaklyCompressibleFluidType
{
protected:
Real cutoff_pressure_, cutoff_density_;
public:
template <typename... ConstructorArgs>
explicit WeaklyCompressibleFluidFreeSurface(Real cutoff_pressure, ConstructorArgs &&...args)
: WeaklyCompressibleFluidType(std::forward<ConstructorArgs>(args)...),
cutoff_pressure_(cutoff_pressure),
cutoff_density_(WeaklyCompressibleFluidType::DensityFromPressure(cutoff_pressure))
{
WeaklyCompressibleFluidType::aterial_type_ += "FreeSurface";
};
virtual ~WeaklyCompressibleFluidFreeSurface(){};
virtual Real getPressure(Real rho) override
{
return rho < cutoff_density_ ? cutoff_pressure_ : WeaklyCompressibleFluid::getPressure(rho);
};
};
/**
* @class SymmetricTaitFluid
* @brief Tait EOS for positive and negative pressure symmetrically.
*/
class SymmetricTaitFluid : public WeaklyCompressibleFluid
{
protected:
int gamma_; /**< determine the stiffness of the fluid */
public:
explicit SymmetricTaitFluid(Real rho0, Real c0, int gamma)
: WeaklyCompressibleFluid(rho0, c0), gamma_(gamma)
{
material_type_ = "SymmetricTaitFluid";
};
virtual ~SymmetricTaitFluid(){};
virtual Real getPressure(Real rho) override;
virtual Real DensityFromPressure(Real p) override;
virtual Real getSoundSpeed(Real p = 0.0, Real rho = 1.0) override;
};
/**
* @class Oldroyd_B_Fluid
* @brief linear EOS with relaxation time and polymetric viscosity.
*/
class Oldroyd_B_Fluid : public WeaklyCompressibleFluid
{
protected:
Real lambda_; /**< relaxation time */
Real mu_p_; /**< polymeric viscosity */
ViscoelasticFluidParticles *viscoelastic_fluid_particles_;
public:
explicit Oldroyd_B_Fluid(Real rho0, Real c0, Real mu, Real lambda, Real mu_p)
: WeaklyCompressibleFluid(rho0, c0, mu),
lambda_(lambda), mu_p_(mu_p), viscoelastic_fluid_particles_(nullptr)
{
material_type_ = "Oldroyd_B_Fluid";
};
virtual ~Oldroyd_B_Fluid(){};
void assignViscoelasticFluidParticles(ViscoelasticFluidParticles *viscoelastic_fluid_particles)
{
viscoelastic_fluid_particles_ = viscoelastic_fluid_particles;
};
Real getReferenceRelaxationTime() { return lambda_; };
Real ReferencePolymericViscosity() { return mu_p_; };
virtual Oldroyd_B_Fluid *ThisObjectPtr() override { return this; };
};
}
#endif //WEAKLY_COMPRESSIBLE_FLUID_H | 37.070922 | 97 | 0.672087 |
014f9a7b69fbbb25ef07c3041f6ff94175af53e6 | 4,093 | h | C | nodebox/ext/psyco/src/c/ivm/ipyencoding.h | mcjocobe/drawExploration | 2c50526ef14dea5bc3802b7fda08871919d62ac4 | [
"BSD-3-Clause"
] | 76 | 2015-01-21T11:21:08.000Z | 2022-02-04T13:33:19.000Z | nodebox/ext/psyco/src/c/ivm/ipyencoding.h | pepsipepsi/nodebox_opengl_python3 | cfb2633df1055a028672b11311603cc2241a1378 | [
"BSD-3-Clause"
] | 8 | 2015-11-12T07:42:58.000Z | 2020-06-09T10:01:15.000Z | nodebox/ext/psyco/src/c/ivm/ipyencoding.h | pepsipepsi/nodebox_opengl_python3 | cfb2633df1055a028672b11311603cc2241a1378 | [
"BSD-3-Clause"
] | 23 | 2015-01-12T12:07:40.000Z | 2020-04-13T16:32:15.000Z | /***************************************************************/
/*** Processor- and language-dependent code producers ***/
/***************************************************************/
#ifndef _IPYENCODING_H
#define _IPYENCODING_H
#include "iencoding.h"
#include "ivm-insns.h"
/* See comments in i386/ipyencoding.h about these functions */
PSY_INLINE void* dictitem_check_change(PsycoObject* po,
PyDictObject* dict, PyDictEntry* ep)
{
int index = ep - dict->ma_table;
PyObject* key = ep->me_key;
PyObject* result = ep->me_value;
word_t* arg1;
word_t* arg2;
word_t* arg3;
word_t* arg4;
Py_INCREF(key); /* XXX these become immortal */
Py_INCREF(result); /* XXX */
BEGIN_CODE
NEED_CC();
/* this special instruction quickly checks that the same
object is still in place in the dictionary */
INSN_checkdict(&arg1, &arg2, &arg3, &arg4);
*arg1 = (word_t) dict;
*arg2 = (word_t) key;
*arg3 = (word_t) result;
*arg4 = index;
END_CODE
return arg4;
}
#define DICT_ITEM_CHECK_CC CC_FLAG
PSY_INLINE void dictitem_update_nochange(void* originalmacrocode,
PyDictObject* dict, PyDictEntry* new_ep)
{
int index = new_ep - dict->ma_table;
word_t* arg5 = (word_t*) originalmacrocode;
*arg5 = index;
}
PSY_INLINE void psyco_incref_nv(PsycoObject* po, vinfo_t* v)
{
BEGIN_CODE
INSN_nv_push(v->source);
INSN_incref();
END_CODE
}
PSY_INLINE void psyco_incref_rt(PsycoObject* po, vinfo_t* v)
{
BEGIN_CODE
INSN_rt_push(v->source);
INSN_incref();
END_CODE
}
PSY_INLINE void psyco_decref_rt(PsycoObject* po, vinfo_t* v)
{
BEGIN_CODE
INSN_rt_push(v->source);
INSN_decref();
END_CODE
}
PSY_INLINE void psyco_decref_c(PsycoObject* po, PyObject* o)
{
word_t* arg;
BEGIN_CODE
INSN_decrefnz(&arg);
*arg = (word_t) o;
END_CODE
}
EXTERNFN void decref_create_new_ref(PsycoObject* po, vinfo_t* w);
EXTERNFN bool decref_create_new_lastref(PsycoObject* po, vinfo_t* w);
/* called by psyco_emit_header() */
#define INITIALIZE_FRAME_LOCALS(nframelocal) do { \
STACK_CORRECTION(sizeof(long)*((nframelocal)-1)); \
INSN_immed(0); /* f_exc_type, initially NULL */ \
} while (0)
/* called by psyco_finish_return() */
#define WRITE_FRAME_EPILOGUE(retval, nframelocal) do { \
/* load the return value into the dedicated 'retval' register */ \
/* which actually shares with 'flag' */ \
if (retval != SOURCE_DUMMY) { \
if (is_runtime(retval) && getstack(retval) == po->stack_depth) \
INSNPOPPED(1); \
else \
INSN_nv_push(retval); \
INSN_retval(); \
} \
if (nframelocal > 0) \
{ \
/* psyco_emit_header() was used; first clear the stack only up to and not \
including the frame-local data */ \
int framelocpos = getstack(LOC_CONTINUATION->array->items[0]->source); \
STACK_CORRECTION(framelocpos - po->stack_depth); \
po->stack_depth = framelocpos; \
\
/* perform Python-specific cleanup */ \
INSN_exitframe(); \
INSNPOPPED(3); \
} \
} while (0)
#endif /* _IPYENCODING_H */
| 34.686441 | 81 | 0.485952 |
2ba17509c5179be0aa036e4e1b327be9ac51b654 | 885 | h | C | src/dxbc/dxbc_tag.h | lacc97/dxvk | 5fe8d823a03cc1c90361a4e89c385cefee8cbcf6 | [
"Zlib"
] | 8,148 | 2017-10-29T10:51:20.000Z | 2022-03-31T12:52:51.000Z | src/dxbc/dxbc_tag.h | lacc97/dxvk | 5fe8d823a03cc1c90361a4e89c385cefee8cbcf6 | [
"Zlib"
] | 2,270 | 2017-12-04T12:08:13.000Z | 2022-03-31T19:56:41.000Z | src/dxbc/dxbc_tag.h | lacc97/dxvk | 5fe8d823a03cc1c90361a4e89c385cefee8cbcf6 | [
"Zlib"
] | 732 | 2017-11-28T13:08:15.000Z | 2022-03-31T21:05:59.000Z | #pragma once
#include "dxbc_include.h"
namespace dxvk {
/**
* \brief Four-character tag
*
* Used to identify chunks in the
* compiled DXBC file by name.
*/
class DxbcTag {
public:
DxbcTag() {
for (size_t i = 0; i < 4; i++)
m_chars[i] = '\0';
}
DxbcTag(const char* tag) {
for (size_t i = 0; i < 4; i++)
m_chars[i] = tag[i];
}
bool operator == (const DxbcTag& other) const {
bool result = true;
for (size_t i = 0; i < 4; i++)
result &= m_chars[i] == other.m_chars[i];
return result;
}
bool operator != (const DxbcTag& other) const {
return !this->operator == (other);
}
const char* operator & () const { return m_chars; }
char* operator & () { return m_chars; }
private:
char m_chars[4];
};
} | 18.829787 | 55 | 0.498305 |
6d07d24275958c6088d4c59a24022803d3ee9e33 | 33,216 | c | C | crankbase/crankrange.c | WSID/crank-system | 7c94f829050815392259c227e38b34f97886f7fc | [
"MIT"
] | null | null | null | crankbase/crankrange.c | WSID/crank-system | 7c94f829050815392259c227e38b34f97886f7fc | [
"MIT"
] | null | null | null | crankbase/crankrange.c | WSID/crank-system | 7c94f829050815392259c227e38b34f97886f7fc | [
"MIT"
] | null | null | null | /* Copyright (C) 2015, WSID */
/* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define _CRANKBASE_INSIDE
#include <math.h>
#include <glib.h>
#include <glib-object.h>
#include "crankbasemacro.h"
#include "crankrange.h"
/**
* SECTION: crankrange
* @title: Range of primitives.
* @short_description: Structures represent ranges.
* @usability: unstable
* @include: crankbase.h
*
* Crank System provides simple range representations for convenience.
*
* Ranges can be used for requirements of values, specifying memory block, and
* basic of shape processing.
*
* # Get and Index of
*
* Getting operations on range can be thought as mix operation of start and end
* point.
*
* Index of operations on range can be thought as inverse operations of get
* operations.
*
* # Differece of contains and clamp in meaning of range.
*
* The range represents a range with one open end, which is in form of [a, b).
* As a result, contains function will return %FALSE on end point.
*
* But, for clamp, it would not work as we cannot determine valid value when
* value is out of range at end side. so for clamp operation, it will work as if
* range was [a, b], instead of [a, b).
*
* This will make some wicked point that a clamped value might still out of
* range.
*
* # Pointer Range
*
* Pointer ranges are generally used for memory block. So this has more
* operations, specialized for pointers. Note that they all also requires
* size of chunk/steps.
* <itemizedlist>
* <listitem>count: number of chunk in range.</listitem>
* <listitem>get_step: get value after steps with given size (which probably
* size of element type)</listitem>
* <listitem>n_step: get index of step with given size.</listitem>
* </itemizedlist>
*/
G_DEFINE_BOXED_TYPE(CrankRanUint, crank_ran_uint, crank_ran_uint_dup, g_free)
G_DEFINE_BOXED_TYPE(CrankRanInt, crank_ran_int, crank_ran_int_dup, g_free)
G_DEFINE_BOXED_TYPE(CrankRanFloat, crank_ran_float, crank_ran_float_dup, g_free)
G_DEFINE_BOXED_TYPE(CrankRanPtr, crank_ran_ptr, crank_ran_ptr_dup, g_free)
//////// Initialization ////////////////////////////////////////////////////////
/**
* crank_ran_uint_init:
* @ran: (out): A Range
* @start: Start of range.
* @end: End of range.
*
* Initialize a range with given two points.
*/
void
crank_ran_uint_init (CrankRanUint *ran,
const guint start,
const guint end)
{
ran->start = start;
ran->end = end;
}
/**
* crank_ran_uint_init_diff:
* @ran: (out): A Range
* @start: Start of range.
* @diff: Difference of start and end.
*
* Initialize a range with start point and difference.
*/
void
crank_ran_uint_init_diff (CrankRanUint *ran,
const guint start,
const guint diff)
{
crank_ran_uint_init (ran, start, start + diff);
}
/**
* crank_ran_uint_init_unit:
* @ran: (out): A Range
* @start: Start of range.
*
* Initialize a range with start point, with unit length.
*
* For numeric values, it is 1.
*/
void
crank_ran_uint_init_unit (CrankRanUint *ran,
const guint start)
{
crank_ran_uint_init_diff (ran, start, 1);
}
//////// Basic Functions ///////////////////////////////////////////////////////
/**
* crank_ran_uint_copy:
* @ran: A Range
* @other: (out): Copied range.
*
* Copies a range to other
*/
void
crank_ran_uint_copy (CrankRanUint *ran,
CrankRanUint *other)
{
crank_ran_uint_init (other, ran->start, ran->end);
}
/**
* crank_ran_uint_dup:
* @ran: A Range
*
* Allocates new range and copies on it.
*
* Returns: (transfer full): Copied range, free with g_free()
*/
CrankRanUint*
crank_ran_uint_dup (CrankRanUint *ran)
{
CrankRanUint *result = g_new (CrankRanUint, 1);
crank_ran_uint_copy (ran, result);
return result;
}
/**
* crank_ran_uint_equal:
* @a: (type CrankRanUint): A Range
* @b: (type CrankRanUint): A Range
*
* Compares two range and checks they are same.
*
* Returns: Whether the two are same.
*/
gboolean
crank_ran_uint_equal (gconstpointer a,
gconstpointer b)
{
CrankRanUint *aran = (CrankRanUint*) a;
CrankRanUint *bran = (CrankRanUint*) b;
return ((aran->start == bran->start) && (aran->end == bran->end));
}
/**
* crank_ran_uint_hash:
* @a: (type CrankRanUint): A Range
*
* Gets hash value of range.
*
* Returns: Hash value of range.
*/
guint
crank_ran_uint_hash (gconstpointer a)
{
CrankRanUint *ran = (CrankRanUint*) a;
return g_int_hash (&(ran->start)) * 33 +
g_int_hash (&(ran->end));
}
/**
* crank_ran_uint_to_string:
* @ran: A Range
*
* Gets string representation of range.
*
* Returns: (transfer full): String representation, free with g_free().
*/
gchar*
crank_ran_uint_to_string (CrankRanUint *ran)
{
return crank_ran_uint_to_string_full (ran, CRANK_RAN_UINT_DEFFORMAT);
}
/**
* crank_ran_uint_to_string_full:
* @ran: A Range
* @format: Format string for range. Consumes two uint parameters.
*
* Gets string representation of range, with given format.
*
* Returns: (transfer full): String representation, free with g_free().
*/
gchar*
crank_ran_uint_to_string_full (CrankRanUint *ran,
const gchar *format)
{
return g_strdup_printf (format, ran->start, ran->end);
}
//////// Classification ////////////////////////////////////////////////////////
/**
* crank_ran_uint_is_empty:
* @ran: A Range
*
* Checks whether it is empty range, which has zero-length.
*
* Returns: whether it is empty range.
*/
gboolean
crank_ran_uint_is_empty (CrankRanUint *ran)
{
return (ran->start == ran->end);
}
/**
* crank_ran_uint_is_unit:
* @ran: A Range
*
* Checks whether it is unit range, which has unit length.
*
* Returns: whether it is unit range.
*/
gboolean
crank_ran_uint_is_unit (CrankRanUint *ran)
{
return (crank_ran_uint_get_length (ran) == 1);
}
//////// Attributes ////////////////////////////////////////////////////////////
/**
* crank_ran_uint_get_length:
* @ran: A Range.
*
* Gets length of range.
*
* Returns: The length of range.
*/
guint
crank_ran_uint_get_length (CrankRanUint *ran)
{
return ran->end - ran->start;
}
//////// Range function ////////////////////////////////////////////////////////
/**
* crank_ran_uint_contains:
* @ran: A Range.
* @value: A Value
*
* Checks whether the value is in the range.
*
* Returns: Whetehr the value is in the range.
*/
gboolean
crank_ran_uint_contains (CrankRanUint *ran,
const guint value)
{
return ((ran->start) <= value) && (value < (ran->end));
}
/**
* crank_ran_uint_get:
* @ran: A Range.
* @index: A Index.
*
* Gets interpolated value between start and end point.
*
* If @index is out of range of [0, 1], the appropriate value is returned, which
* also out of range [@ran->start, @ran->end].
*
* Returns: A interpolated value.
*/
guint
crank_ran_uint_get (CrankRanUint *ran,
const gfloat index)
{
guint len = crank_ran_uint_get_length (ran);
if (index < 0)
return ran->start - (guint)(-index * len);
else
return ran->start + (guint)(index * len);
}
/**
* crank_ran_uint_index_of:
* @ran: A Range.
* @value: A Value.
*
* Gets index from value, which index meets,
* * (@ran->start * (1 - index)) + (@ran->end * index) == @value.
*
* You can think this as inverse operation of crank_ran_uint_get().
*
* Returns: A index for given value.
*/
gfloat
crank_ran_uint_index_of (CrankRanUint *ran,
const guint value)
{
guint len = crank_ran_uint_get_length (ran);
if (value < ran->start)
return -(gfloat)(ran->start - value) / len;
else
return (gfloat)(value - ran->start) / len;
}
/**
* crank_ran_uint_clamp:
* @ran: A Range.
* @value: A Value.
*
* Clamps a given value with in the range.
*
* Note
* crank_ran_uint_contains() checks for [start, end), while this function
* works for [start, end]. So the result does not guaranteed to be evaluated
* to be %TRUE in crank_ran_uint_contains().
*
* Returns: A Clamped value.
*/
guint
crank_ran_uint_clamp (CrankRanUint *ran,
const guint value)
{
return CLAMP (value, ran->start, ran->end);
}
//////// Range - Range operations //////////////////////////////////////////////
/**
* crank_ran_uint_intersection:
* @a: A Range.
* @b: A Range
* @r: (out): A Intersection of @a and @b, or empty range if there is no intersection.
*
* Gets intersection of two range.
*
* If there is no intersection, it returns %FALSE, and initialize @r with empty
* range.
*
* Returns: whether if @a and @b has intersection.
*/
gboolean
crank_ran_uint_intersection (CrankRanUint *a,
CrankRanUint *b,
CrankRanUint *r)
{
if ((b->start) < (a->end) && (a->start) < (b->end))
{
crank_ran_uint_init (r,
MAX(a->start, b->start),
MIN(a->end, b->end) );
return TRUE;
}
else
{
r->start = 0;
r->end = 0;
return FALSE;
}
}
//////// Initialization ////////////////////////////////////////////////////////
/**
* crank_ran_int_init:
* @ran: (out): A Range
* @start: Start of range.
* @end: End of range.
*
* Initialize a range with given two points.
*/
void
crank_ran_int_init (CrankRanInt *ran,
const gint start,
const gint end)
{
ran->start = start;
ran->end = end;
}
/**
* crank_ran_int_init_diff:
* @ran: (out): A Range
* @start: Start of range.
* @diff: Difference of start and end.
*
* Initialize a range with start point and difference.
*/
void
crank_ran_int_init_diff (CrankRanInt *ran,
const gint start,
const guint diff)
{
crank_ran_int_init (ran, start, start + diff);
}
/**
* crank_ran_int_init_unit:
* @ran: (out): A Range
* @start: Start of range.
*
* Initialize a range with start point, with unit length.
*
* For numeric values, it is 1.
*/
void
crank_ran_int_init_unit (CrankRanInt *ran,
const gint start)
{
crank_ran_int_init_diff (ran, start, 1);
}
//////// Basic Functions ///////////////////////////////////////////////////////
/**
* crank_ran_int_copy:
* @ran: A Range
* @other: (out): Copied range.
*
* Copies a range to other
*/
void
crank_ran_int_copy (CrankRanInt *ran,
CrankRanInt *other)
{
crank_ran_int_init (other, ran->start, ran->end);
}
/**
* crank_ran_int_dup:
* @ran: A Range
*
* Allocates new range and copies on it.
*
* Returns: (transfer full): Copied range, free with g_free()
*/
CrankRanInt*
crank_ran_int_dup (CrankRanInt *ran)
{
CrankRanInt *result = g_new (CrankRanInt, 1);
crank_ran_int_copy (ran, result);
return result;
}
/**
* crank_ran_int_equal:
* @a: (type CrankRanInt): A Range
* @b: (type CrankRanInt): A Range
*
* Compares two range and checks they are same.
*
* Returns: Whether the two are same.
*/
gboolean
crank_ran_int_equal (gconstpointer a,
gconstpointer b)
{
CrankRanInt *rana = (CrankRanInt*)a;
CrankRanInt *ranb = (CrankRanInt*)b;
return (rana->start == ranb->start) && (rana->end == ranb->end);
}
/**
* crank_ran_int_hash:
* @a: (type CrankRanInt): A Range
*
* Gets hash value of range.
*
* Returns: Hash value of range.
*/
guint
crank_ran_int_hash (gconstpointer a)
{
CrankRanInt *ran = (CrankRanInt*)a;
return g_int_hash (&ran->start) * 33 +
g_int_hash (&ran->end);
}
/**
* crank_ran_int_to_string:
* @ran: A Range
*
* Gets string representation of range.
*
* Returns: (transfer full): String representation, free with g_free().
*/
gchar*
crank_ran_int_to_string (CrankRanInt *ran)
{
return crank_ran_int_to_string_full (ran,
CRANK_RAN_INT_DEFFORMAT);
}
/**
* crank_ran_int_to_string_full:
* @ran: A Range
* @format: Format string for range. Consumes two int parameters.
*
* Gets string representation of range, with given format.
*
* Returns: (transfer full): String representation, free with g_free().
*/
gchar*
crank_ran_int_to_string_full (CrankRanInt *ran,
const gchar *format)
{
return g_strdup_printf (format, ran->start, ran->end);
}
//////// Classification ////////////////////////////////////////////////////////
/**
* crank_ran_int_is_empty:
* @ran: A Range
*
* Checks whether it is empty range, which has zero-length.
*
* Returns: whether it is empty range.
*/
gboolean
crank_ran_int_is_empty (CrankRanInt *ran)
{
return (ran->start == ran->end);
}
/**
* crank_ran_int_is_unit:
* @ran: A Range
*
* Checks whether it is unit range, which has unit length.
*
* Returns: whether it is unit range.
*/
gboolean
crank_ran_int_is_unit (CrankRanInt *ran)
{
return crank_ran_int_get_length (ran) == 1;
}
//////// Attributes ////////////////////////////////////////////////////////////
/**
* crank_ran_int_get_length:
* @ran: A Range.
*
* Gets length of range.
*
* Returns: The length of range.
*/
guint
crank_ran_int_get_length (CrankRanInt *ran)
{
return (guint)(ran->end - ran->start);
}
//////// Range function ////////////////////////////////////////////////////////
/**
* crank_ran_int_contains:
* @ran: A Range.
* @value: A Value
*
* Checks whether the value is in the range.
*
* Returns: Whether the value is in the range.
*/
gboolean
crank_ran_int_contains (CrankRanInt *ran,
const gint value)
{
return (ran->start < value) && (value < ran->end);
}
/**
* crank_ran_int_get:
* @ran: A Range.
* @index: A Index.
*
* Gets interpolated value between start and end point.
*
* If @index is out of range of [0, 1], the appropriate value is returned, which
* also out of range [@ran->start, @ran->end].
*
* Returns: A interpolated value.
*/
gint
crank_ran_int_get (CrankRanInt *ran,
const gfloat index)
{
guint len = crank_ran_int_get_length (ran);
if (index < 0)
return ran->start - (gint)(-index * len);
else
return ran->start + (gint)(index * len);
}
/**
* crank_ran_int_index_of:
* @ran: A Range.
* @value: A Value.
*
* Gets index from value, which index meets,
* * (@ran->start * (1 - index)) + (@ran->end * index) == @value.
*
* You can think this as inverse operation of crank_ran_int_get().
*
* Returns: A index for given value.
*/
gfloat
crank_ran_int_index_of (CrankRanInt *ran,
const gint value)
{
guint len = crank_ran_int_get_length (ran);
if (value < ran->start)
return -(gfloat)(ran->start - value) / len;
else
return (gfloat)(value - ran->start) / len;
}
/**
* crank_ran_int_clamp:
* @ran: A Range.
* @value: A Value.
*
* Clamps a given value with in the range.
*
* clamp function and contains function has different checking boundary. See
* crank_ran_uint_clamp() for detailed notes.
*
* Returns: A Clamped value.
*/
gint
crank_ran_int_clamp (CrankRanInt *ran,
const gint value)
{
return CLAMP (value, ran->start, ran->end);
}
/**
* crank_ran_int_intersection:
* @a: A Range.
* @b: A Range
* @r: (out): A Intersection of @a and @b, or empty range if there is no intersection.
*
* Gets intersection of two range.
*
* If there is no intersection, it returns %FALSE, and initialize @r with empty
* range.
*
* Returns: whether if @a and @b has intersection.
*/
gboolean
crank_ran_int_intersection (CrankRanInt *a,
CrankRanInt *b,
CrankRanInt *r)
{
if ((b->start) < (a->end) && (a->start) < (b->end))
{
crank_ran_int_init (r,
MAX(a->start, b->start),
MIN(a->end, b->end) );
return TRUE;
}
else
{
r->start = 0;
r->end = 0;
return FALSE;
}
}
//////// Initialization ////////////////////////////////////////////////////////
/**
* crank_ran_float_init:
* @ran: (out): A Range
* @start: Start of range.
* @end: End of range.
*
* Initialize a range with given two points.
*/
void
crank_ran_float_init (CrankRanFloat *ran,
const gfloat start,
const gfloat end)
{
ran->start = start;
ran->end = end;
}
/**
* crank_ran_float_init_diff:
* @ran: (out): A Range
* @start: Start of range.
* @diff: Difference of start and end.
*
* Initialize a range with start point and difference.
*/
void
crank_ran_float_init_diff (CrankRanFloat *ran,
const gfloat start,
const gfloat diff)
{
crank_ran_float_init (ran, start, start + diff);
}
/**
* crank_ran_float_init_unit:
* @ran: (out): A Range
* @start: Start of range.
*
* Initialize a range with start point, with unit length.
*
* For numeric values, it is 1.
*/
void
crank_ran_float_init_unit (CrankRanFloat *ran,
const gfloat start)
{
crank_ran_float_init_diff (ran, start, 1);
}
//////// Basic Functions ///////////////////////////////////////////////////////
/**
* crank_ran_float_copy:
* @ran: A Range
* @other: (out): Copied range.
*
* Copies a range to other
*/
void
crank_ran_float_copy (CrankRanFloat *ran,
CrankRanFloat *other)
{
crank_ran_float_init (other, ran->start, ran->end);
}
/**
* crank_ran_float_dup:
* @ran: A Range
*
* Allocates new range and copies on it.
*
* Returns: (transfer full): Copied range, free with g_free()
*/
CrankRanFloat*
crank_ran_float_dup (CrankRanFloat *ran)
{
CrankRanFloat *result = g_new (CrankRanFloat, 1);
crank_ran_float_copy (ran, result);
return result;
}
/**
* crank_ran_float_equal:
* @a: (type CrankRanFloat): A Range
* @b: (type CrankRanFloat): A Range
*
* Compares two range and checks they are same.
*
* Returns: Whether the two are same.
*/
gboolean
crank_ran_float_equal (gconstpointer a,
gconstpointer b)
{
return crank_ran_float_equal_delta (a, b, 0.0001f);
}
/**
* crank_ran_float_equal_delta:
* @a: (type CrankRanFloat): A Range
* @b: (type CrankRanFloat): A Range
* @d: A Delta
*
* Compares two range and checks they are sufficiently same, which has difference
* less than given delta.
*
* Returns: Whether the two are sufficiently same.
*/
gboolean
crank_ran_float_equal_delta (gconstpointer a,
gconstpointer b,
const gfloat d)
{
CrankRanFloat *rana;
CrankRanFloat *ranb;
gfloat err;
err = ABS(ranb->start - rana->start) + ABS(ranb->end - rana->end);
return (err < d);
}
/**
* crank_ran_float_hash:
* @a: (type CrankRanFloat): A Range
*
* Gets hash value of range.
*
* Returns: Hash value of range.
*/
guint
crank_ran_float_hash (gconstpointer a)
{
CrankRanFloat *ran;
gdouble start = ran->start;
gdouble end = ran->end;
return g_double_hash (&start) * 33 +
g_double_hash (&end);
}
/**
* crank_ran_float_to_string:
* @ran: A Range
*
* Gets string representation of range.
*
* Returns: (transfer full): String representation, free with g_free().
*/
gchar*
crank_ran_float_to_string (CrankRanFloat *ran)
{
return crank_ran_float_to_string_full (ran,
CRANK_RAN_FLOAT_DEFFORMAT);
}
/**
* crank_ran_float_to_string_full:
* @ran: A Range
* @format: Format string for range. Consumes two float parameters.
*
* Gets string representation of range, with given format.
*
* Returns: (transfer full): String representation, free with g_free().
*/
gchar*
crank_ran_float_to_string_full (CrankRanFloat *ran,
const gchar *format)
{
return g_strdup_printf (format, ran->start, ran->end);
}
//////// Classification ////////////////////////////////////////////////////////
/**
* crank_ran_float_is_empty:
* @ran: A Range
*
* Checks whether it is empty range, which has zero-length.
*
* Returns: whether it is empty range.
*/
gboolean
crank_ran_float_is_empty (CrankRanFloat *ran)
{
return (ran->start == ran->end);
}
/**
* crank_ran_float_is_unit:
* @ran: A Range
*
* Checks whether it is unit range, which has unit length.
*
* Returns: whether it is unit range.
*/
gboolean
crank_ran_float_is_unit (CrankRanFloat *ran)
{
return crank_ran_float_get_length (ran) == 1;
}
/**
* crank_ran_float_is_nan:
* @ran: A Range
*
* Checks whether it is undetermined range. If any one of end points is NaN, then
* the whole range is considered NaN, as it cannot determine which numbers are
* in the range.
*
* NaN ranges returns %FALSE for most boolean functions and NaN for most value
* functions.
*
* Returns: whether it is NaN range.
*/
gboolean
crank_ran_float_is_nan (CrankRanFloat *ran)
{
return isnanf(ran->start) || isnanf(ran->end);
}
/**
* crank_ran_float_has_inf:
* @ran: A Range
*
* Checks whether any end point is infinity.
*
* Returns: whether it has infinity.
*/
gboolean
crank_ran_float_has_inf (CrankRanFloat *ran)
{
return crank_ran_float_has_pinf (ran) ||
crank_ran_float_has_ninf (ran);
}
/**
* crank_ran_float_has_pinf:
* @ran: A Range
*
* Checks whether end point is positive infinity.
*
* Returns: whether it has positive infinity.
*/
gboolean
crank_ran_float_has_pinf (CrankRanFloat *ran)
{
return isinff (ran->end) && (0 < ran->end);
}
/**
* crank_ran_float_has_ninf:
* @ran: A Range
*
* Checks whether start point is negative infinity.
*
* Returns: whether it has negative infinity.
*/
gboolean
crank_ran_float_has_ninf (CrankRanFloat *ran)
{
return isinff (ran->start) && (ran->start < 0);
}
//////// Attributes ////////////////////////////////////////////////////////////
/**
* crank_ran_float_get_length:
* @ran: A Range.
*
* Gets length of range.
*
* Returns: The length of range.
*/
gfloat
crank_ran_float_get_length (CrankRanFloat *ran)
{
return ran->end - ran->start;
}
//////// Range function ////////////////////////////////////////////////////////
/**
* crank_ran_float_contains:
* @ran: A Range.
* @value: A Value
*
* Checks whether the value is in the range.
*
* Returns: Whether the value is in the range.
*/
gboolean
crank_ran_float_contains (CrankRanFloat *ran,
const gfloat value)
{
return (ran->start <= value) && (value < ran->end);
}
/**
* crank_ran_float_get:
* @ran: A Range.
* @index: A Index.
*
* Gets interpolated value between start and end point.
*
* If @index is out of range of [0, 1], the appropriate value is returned, which
* also out of range [@ran->start, @ran->end].
*
* Returns: A interpolated value.
*/
gfloat
crank_ran_float_get (CrankRanFloat *ran,
const gfloat index)
{
return fmaf (crank_ran_float_get_length (ran), index, ran->start);
}
/**
* crank_ran_float_index_of:
* @ran: A Range.
* @value: A Value.
*
* Gets index from value, which index meets,
* * (@ran->start * (1 - index)) + (@ran->end * index) == @value.
*
* You can think this as inverse operation of crank_ran_int_get().
*
* Returns: A index for given value.
*/
gfloat
crank_ran_float_index_of (CrankRanFloat *ran,
const gfloat value)
{
gfloat len = crank_ran_float_get_length (ran);
gfloat diff = value - ran->start;
return diff / len;
}
/**
* crank_ran_float_clamp:
* @ran: A Range.
* @value: A Value.
*
* Clamps a given value with in the range.
*
* clamp function and contains function has different checking boundary. See
* crank_ran_uint_clamp() for detailed notes.
*
* Returns: A Clamped value.
*/
gfloat
crank_ran_float_clamp (CrankRanFloat *ran,
const gfloat value)
{
return CLAMP(value, ran->start, ran->end);
}
/**
* crank_ran_float_intersection:
* @a: A Range.
* @b: A Range
* @r: (out): A Intersection of @a and @b, or empty range if there is no intersection.
*
* Gets intersection of two range.
*
* If there is no intersection, it returns %FALSE, and initialize @r with empty
* range.
*
* Returns: whether if @a and @b has intersection.
*/
gboolean
crank_ran_float_intersection (CrankRanFloat *a,
CrankRanFloat *b,
CrankRanFloat *r)
{
if ((b->start) < (a->end) && (a->start) < (b->end))
{
crank_ran_float_init (r,
MAX(a->start, b->start),
MIN(a->end, b->end) );
return TRUE;
}
else
{
r->start = 0;
r->end = 0;
return FALSE;
}
}
//////// Initialization ////////////////////////////////////////////////////////
/**
* crank_ran_ptr_init:
* @ran: (out): A Range
* @start: Start of range.
* @end: End of range.
*
* Initialize a range with given two points.
*/
void
crank_ran_ptr_init (CrankRanPtr *ran,
gpointer start,
gpointer end)
{
ran->start = start;
ran->end = end;
}
/**
* crank_ran_ptr_init_diff:
* @ran: (out): A Range
* @start: Start of range.
* @diff: Difference of start and end.
*
* Initialize a range with start point and difference.
*/
void
crank_ran_ptr_init_diff (CrankRanPtr *ran,
gpointer start,
gsize diff)
{
crank_ran_ptr_init (ran, start, CRANK_PTR_ADD (start, diff));
}
//////// Basic Functions ///////////////////////////////////////////////////////
/**
* crank_ran_ptr_copy:
* @ran: A Range
* @other: (out): Copied range.
*
* Copies a range to other
*/
void
crank_ran_ptr_copy (CrankRanPtr *ran,
CrankRanPtr *other)
{
crank_ran_ptr_init (other, ran->start, ran->end);
}
/**
* crank_ran_ptr_dup:
* @ran: A Range
*
* Allocates new range and copies on it.
*
* Returns: (transfer full): Copied range, free with g_free()
*/
CrankRanPtr*
crank_ran_ptr_dup (CrankRanPtr *ran)
{
CrankRanPtr *result = g_new (CrankRanPtr, 1);
crank_ran_ptr_copy (ran, result);
return result;
}
/**
* crank_ran_ptr_equal:
* @a: (type CrankRanPtr): A Range
* @b: (type CrankRanPtr): A Range
*
* Compares two range and checks they are same.
*
* Returns: Whether the two are same.
*/
gboolean
crank_ran_ptr_equal (gconstpointer a,
gconstpointer b)
{
CrankRanPtr *rana = (CrankRanPtr*)a;
CrankRanPtr *ranb = (CrankRanPtr*)b;
return (rana->start == ranb->start) && (rana->end == ranb->end);
}
/**
* crank_ran_ptr_hash:
* @a: (type CrankRanPtr): A Range
*
* Gets hash value of range.
*
* Returns: Hash value of range.
*/
guint
crank_ran_ptr_hash (gconstpointer a)
{
CrankRanPtr *ran = (CrankRanPtr*)a;
return g_direct_hash (ran->start) * 33 +
g_direct_hash (ran->end);
}
/**
* crank_ran_ptr_to_string:
* @ran: A Range
*
* Gets string representation of range.
*
* Returns: (transfer full): String representation, free with g_free().
*/
gchar*
crank_ran_ptr_to_string (CrankRanPtr *ran)
{
return crank_ran_ptr_to_string_full (ran,
CRANK_RAN_PTR_DEFFORMAT);
}
/**
* crank_ran_ptr_to_string_full:
* @ran: A Range
* @format: Format string for range. Consumes two int parameters.
*
* Gets string representation of range, with given format.
*
* Returns: (transfer full): String representation, free with g_free().
*/
gchar*
crank_ran_ptr_to_string_full (CrankRanPtr *ran,
const gchar *format)
{
return g_strdup_printf (format, ran->start, ran->end);
}
//////// Classification ////////////////////////////////////////////////////////
/**
* crank_ran_ptr_is_empty:
* @ran: A Range
*
* Checks whether it is empty range, which has zero-length.
*
* Returns: whether it is empty range.
*/
gboolean
crank_ran_ptr_is_empty (CrankRanPtr *ran)
{
return ran->start == ran->end;
}
//////// Attributes ////////////////////////////////////////////////////////////
/**
* crank_ran_ptr_get_length:
* @ran: A Range.
*
* Gets length of range.
*
* Returns: The length of range.
*/
gsize
crank_ran_ptr_get_length (CrankRanPtr *ran)
{
return CRANK_PTR_DIFF(ran->end, ran->start);
}
//////// Range function ////////////////////////////////////////////////////////
/**
* crank_ran_ptr_get_count:
* @ran: A Range.
* @size: size of chunks.
*
* Gets count of chunk in range. This might be useful if the range represents
* array.
*
* Returns: The count of chunk.
*/
guint
crank_ran_ptr_get_count (CrankRanPtr *ran,
const gsize size)
{
return (guint)(crank_ran_ptr_get_length(ran) / size);
}
/**
* crank_ran_ptr_contains:
* @ran: A Range.
* @value: A Value
*
* Checks whether the value is in the range.
*
* Returns: Whether the value is in the range.
*/
gboolean
crank_ran_ptr_contains (CrankRanPtr *ran,
gpointer value)
{
return (ran->start <= value) && (value < ran->end);
}
/**
* crank_ran_ptr_get:
* @ran: A Range.
* @index: A Index.
*
* Gets interpolated value between start and end point.
*
* If @index is out of range of [0, 1], the appropriate value is returned, which
* also out of range [@ran->start, @ran->end].
*
* Returns: (transfer none): A interpolated value.
*/
gpointer
crank_ran_ptr_get (CrankRanPtr *ran,
const gfloat index)
{
gsize len = crank_ran_ptr_get_length (ran);
return CRANK_PTR_ADD(ran->start, (gsize)(len * index));
}
/**
* crank_ran_ptr_index_of:
* @ran: A Range.
* @value: A Value.
*
* Gets index from value, which index meets,
* * (@ran->start * (1 - index)) + (@ran->end * index) == @value.
*
* You can think this as inverse operation of crank_ran_int_get().
*
* Returns: A index for given value.
*/
gfloat
crank_ran_ptr_index_of (CrankRanPtr *ran,
gpointer value)
{
gsize len = crank_ran_ptr_get_length (ran);
gsize diff = (gsize)value - (gsize)ran->start;
return ((gfloat)diff) / len;
}
/**
* crank_ran_ptr_clamp:
* @ran: A Range.
* @value: A Value.
*
* Clamps a given value with in the range.
*
* clamp function and contains function has different checking boundary. See
* crank_ran_uint_clamp() for detailed notes.
*
* Returns: (transfer none): A Clamped value.
*/
gpointer
crank_ran_ptr_clamp (CrankRanPtr *ran,
gpointer value)
{
return CLAMP (value, ran->start, ran->end);
}
/**
* crank_ran_ptr_get_step:
* @ran: A Range.
* @step: Count of steps.
* @step_size: Size of steps.
*
* Gets pointer that away given step from start. It might be useful for working
* with arrays.
*
* Returns: (transfer none): A Stepped pointer from start.
*/
gpointer
crank_ran_ptr_get_step (CrankRanPtr *ran,
const guint step,
const gsize step_size)
{
return CRANK_PTR_ADD2 (ran->start, step_size, step);
}
/**
* crank_ran_ptr_n_step:
* @ran: A Range.
* @value: value to count steps.
* @step_size: Size of steps.
*
* Count the steps to @value. It might be useful for working with arrays.
*
* Returns: Count of step to @value.
*/
guint
crank_ran_ptr_n_step (CrankRanPtr *ran,
gpointer value,
const gsize step_size)
{
return (guint)(((gsize)value - (gsize)ran->start) / step_size);
}
/**
* crank_ran_ptr_intersection:
* @a: A Range.
* @b: A Range
* @r: (out): A Intersection of @a and @b, or empty range if there is no intersection.
*
* Gets intersection of two range.
*
* If there is no intersection, it returns %FALSE, and initialize @r with empty
* range.
*
* Returns: whether if @a and @b has intersection.
*/
gboolean
crank_ran_ptr_intersection (CrankRanPtr *a,
CrankRanPtr *b,
CrankRanPtr *r)
{
if ((b->start) < (a->end) && (a->start) < (b->end))
{
crank_ran_ptr_init (r,
MAX(a->start, b->start),
MIN(a->end, b->end) );
return TRUE;
}
else
{
r->start = NULL;
r->end = NULL;
return FALSE;
}
}
| 22.458418 | 86 | 0.615396 |
f3ff61149efe0ce9374328787a7c01857b2bd3f2 | 525 | c | C | Parallel_Distributed_Computing_CSE_4001/OpenMP_Constructs_Lab_2/sections_construct.c | aadhityasw/VIT-Labs | 2c449f64f4fdd8c0ed5f2b51d05a7c586e6ab2ab | [
"CC0-1.0"
] | 2 | 2021-11-18T05:30:24.000Z | 2022-03-07T06:28:06.000Z | Parallel_Distributed_Computing_CSE_4001/OpenMP_Constructs_Lab_2/sections_construct.c | aadhityasw/VIT-Labs | 2c449f64f4fdd8c0ed5f2b51d05a7c586e6ab2ab | [
"CC0-1.0"
] | null | null | null | Parallel_Distributed_Computing_CSE_4001/OpenMP_Constructs_Lab_2/sections_construct.c | aadhityasw/VIT-Labs | 2c449f64f4fdd8c0ed5f2b51d05a7c586e6ab2ab | [
"CC0-1.0"
] | 3 | 2021-10-14T01:10:34.000Z | 2022-03-18T14:33:52.000Z | #include <omp.h>
#include <stdio.h>
void sum_num(int a,int b)
{
printf("Adding %d and %d gives %d on thread %d\n",a,b,a+b, omp_get_thread_num());
}
void sum_n_num(int n)
{
int i;
int sum=0;
for(i=0;i<=n;i++)
{
sum+=i;
}
printf("\nSum of first %d numbers is %d from thread %d\n",n,sum,omp_get_thread_num());
}
int main(int argc, char** argv[])
{
#pragma omp parallel sections num_threads(2)
{
#pragma omp section
sum_num(2,3);
#pragma omp section
sum_n_num(5);
}
}
| 18.75 | 90 | 0.590476 |
2811f9f1dbe72a93dde21593093b9b62031bf19e | 1,264 | c | C | tetris/src/game/display_info_game.c | Bluberia/Tetris | 9573b8f6d9f96d5fe01ec63991fcb3b346481d96 | [
"Apache-2.0"
] | null | null | null | tetris/src/game/display_info_game.c | Bluberia/Tetris | 9573b8f6d9f96d5fe01ec63991fcb3b346481d96 | [
"Apache-2.0"
] | null | null | null | tetris/src/game/display_info_game.c | Bluberia/Tetris | 9573b8f6d9f96d5fe01ec63991fcb3b346481d96 | [
"Apache-2.0"
] | null | null | null | /*
** EPITECH PROJECT, 2018
** tetris
** File description:
** display info of the game
*/
#include "proto.h"
#include "my.h"
void display_shape_info(void)
{
mvprintw(7, 0, "/-----------------------------\\");
mvprintw(8, 0, "|");
mvprintw(8, 30, "|");
mvprintw(9, 0, "|");
mvprintw(9, 30, "|");
mvprintw(10, 0, "|");
mvprintw(10, 30, "|");
mvprintw(11, 0, "|");
mvprintw(11, 30, "|");
mvprintw(12, 0, "|");
mvprintw(12, 30, "|");
mvprintw(13, 0, "|");
mvprintw(13, 30, "|");
mvprintw(14, 0, "|");
mvprintw(14, 30, "|");
mvprintw(15, 0, "|");
mvprintw(15, 30, "|");
mvprintw(16, 0, "|");
mvprintw(16, 30, "|");
mvprintw(17, 0, "\\-----------------------------/");
}
void display_informations(game_t *info)
{
time_t actual = time(NULL);
mvprintw(9, 2, "High score");
mvprintw(9, 17, int_to_string(info->data.high_score));
mvprintw(10, 2, "Score");
mvprintw(10, 17, int_to_string(info->data.score));
mvprintw(12, 2, "Lines");
mvprintw(12, 17, int_to_string(info->data.line));
mvprintw(13, 2, "Level");
mvprintw(13, 17, info->level);
mvprintw(15, 2, "Timer");
mvprintw(15, 17, "%ld", (actual - info->data.time));
}
void display_info_game(game_t *info)
{
attron(COLOR_PAIR(7));
display_shape_info();
display_informations(info);
}
| 22.175439 | 55 | 0.576741 |
93205f911f29c4ac6d22bfc07e7330cb86711b38 | 23,427 | c | C | STM32_proj/Core/Src/Iris_img.c | keshikan/Iris_LCD_sample | 048c99a62c8d26a4dc5c3bcdbf7904e9e4e7e425 | [
"BSD-3-Clause"
] | 11 | 2021-01-09T00:13:59.000Z | 2021-02-21T21:47:57.000Z | STM32_proj/Core/Src/Iris_img.c | keshikan/Iris_LCD_sample | 048c99a62c8d26a4dc5c3bcdbf7904e9e4e7e425 | [
"BSD-3-Clause"
] | null | null | null | STM32_proj/Core/Src/Iris_img.c | keshikan/Iris_LCD_sample | 048c99a62c8d26a4dc5c3bcdbf7904e9e4e7e425 | [
"BSD-3-Clause"
] | null | null | null | /*
* Iris_img.c
*
* Created on: Jan 8, 2021
* Author: Keshikan
*/
#include "Iris_img.h"
const uint8_t dvd[48][80]={
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0b, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0c, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x0b, 0x0d, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x09, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0e, 0x0a, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0e, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0d, 0x0c, 0x0c, 0x0c, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x04, 0x08, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0c, 0x02, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x08, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0e, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x05, 0x08, 0x09, 0x09, 0x09, 0x09, 0x09, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0e, 0x0b, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0e, 0x03, 0x05, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0e, 0x07, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x08, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x05, 0x00, 0x0a, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x04, 0x0a, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x08, 0x00, 0x00, 0x06, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x06, 0x00, 0x01, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0e, 0x01, 0x06, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0c, 0x00, 0x03, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x08, 0x00, 0x00, 0x03, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0a, 0x00, 0x02, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0e, 0x05, 0x0c, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x06, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0e, 0x03, 0x00, 0x00, 0x0a, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x09, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x0a, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0e, 0x05, 0x00, 0x00, 0x00, 0x05, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x04, 0x09, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x07, 0x07, 0x08, 0x0a, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0d, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x02, 0x00, 0x00, 0x00, 0x00, 0x02, 0x0e, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0d, 0x08, 0x08, 0x09, 0x0a, 0x0c, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0c, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
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{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x0f, 0x0c, 0x0f, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0x07, 0x00, 0x00, 0x00, 0x02, 0x0f, 0x0b, 0x00, 0x00, 0x00, 0x09, 0x0f, 0x07, 0x00, 0x00, 0x00, 0x03, 0x0f, 0x0f, 0x05, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0f, 0x0d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0c, 0x0f, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0x07, 0x00, 0x00, 0x00, 0x02, 0x0f, 0x0d, 0x05, 0x05, 0x09, 0x0f, 0x0a, 0x01, 0x00, 0x00, 0x00, 0x03, 0x0f, 0x0f, 0x06, 0x04, 0x04, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0f, 0x0c, 0x06, 0x04, 0x08, 0x0e, 0x0e, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0c, 0x05, 0x00, 0x00, 0x00, 0x01, 0x0b, 0x0c, 0x0c, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x0b, 0x0c, 0x0b, 0x0b, 0x0b, 0x0c, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0c, 0x0d, 0x0d, 0x0d, 0x0a, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
};
| 377.854839 | 484 | 0.658855 |
4f270c7b3971776b81780c9dc075c163f765a4a3 | 1,963 | h | C | PrivateFrameworks/GeoServices/GEORoadAccessPoint.h | phatblat/macOSPrivateFrameworks | 9047371eb80f925642c8a7c4f1e00095aec66044 | [
"MIT"
] | 17 | 2018-11-13T04:02:58.000Z | 2022-01-20T09:27:13.000Z | PrivateFrameworks/GeoServices/GEORoadAccessPoint.h | phatblat/macOSPrivateFrameworks | 9047371eb80f925642c8a7c4f1e00095aec66044 | [
"MIT"
] | 3 | 2018-04-06T02:02:27.000Z | 2018-10-02T01:12:10.000Z | PrivateFrameworks/GeoServices/GEORoadAccessPoint.h | phatblat/macOSPrivateFrameworks | 9047371eb80f925642c8a7c4f1e00095aec66044 | [
"MIT"
] | 1 | 2018-09-28T13:54:23.000Z | 2018-09-28T13:54:23.000Z | //
// Generated by class-dump 3.5 (64 bit).
//
// class-dump is Copyright (C) 1997-1998, 2000-2001, 2004-2013 by Steve Nygard.
//
#import "PBCodable.h"
#import "NSCopying.h"
@class GEOLatLng, PBUnknownFields;
@interface GEORoadAccessPoint : PBCodable <NSCopying>
{
PBUnknownFields *_unknownFields;
GEOLatLng *_location;
int _drivingDirection;
unsigned int _significance;
int _transitDirection;
int _walkingDirection;
BOOL _isApproximate;
struct {
unsigned int has_drivingDirection:1;
unsigned int has_significance:1;
unsigned int has_transitDirection:1;
unsigned int has_walkingDirection:1;
unsigned int has_isApproximate:1;
} _flags;
}
+ (BOOL)isValid:(id)arg1;
- (void).cxx_destruct;
- (void)clearUnknownFields:(BOOL)arg1;
@property(readonly, nonatomic) PBUnknownFields *unknownFields;
- (void)mergeFrom:(id)arg1;
- (unsigned long long)hash;
- (BOOL)isEqual:(id)arg1;
- (id)copyWithZone:(struct _NSZone *)arg1;
- (void)copyTo:(id)arg1;
- (void)writeTo:(id)arg1;
- (BOOL)readFrom:(id)arg1;
- (void)readAll:(BOOL)arg1;
- (id)dictionaryRepresentation;
- (id)description;
@property(nonatomic) BOOL hasSignificance;
@property(nonatomic) unsigned int significance;
- (int)StringAsTransitDirection:(id)arg1;
- (id)transitDirectionAsString:(int)arg1;
@property(nonatomic) BOOL hasTransitDirection;
@property(nonatomic) int transitDirection;
- (int)StringAsDrivingDirection:(id)arg1;
- (id)drivingDirectionAsString:(int)arg1;
@property(nonatomic) BOOL hasDrivingDirection;
@property(nonatomic) int drivingDirection;
- (int)StringAsWalkingDirection:(id)arg1;
- (id)walkingDirectionAsString:(int)arg1;
@property(nonatomic) BOOL hasWalkingDirection;
@property(nonatomic) int walkingDirection;
@property(nonatomic) BOOL hasIsApproximate;
@property(nonatomic) BOOL isApproximate;
@property(retain, nonatomic) GEOLatLng *location;
@property(readonly, nonatomic) BOOL hasLocation;
@end
| 29.742424 | 83 | 0.750382 |
9e098c9272e455e89906074d4ab2c84fc3c746a9 | 980 | c | C | Blik2D/addon/libgit2-0.22.2_for_blik/src/hash.c | BonexGu/Blik2D | 8e0592787e5c8e8a28682d0e1826b8223eae5983 | [
"MIT"
] | 13 | 2017-02-22T02:20:06.000Z | 2018-06-06T04:18:03.000Z | Blik2D/addon/libgit2-0.22.2_for_blik/src/hash.c | BonexGu/Blik2D | 8e0592787e5c8e8a28682d0e1826b8223eae5983 | [
"MIT"
] | null | null | null | Blik2D/addon/libgit2-0.22.2_for_blik/src/hash.c | BonexGu/Blik2D | 8e0592787e5c8e8a28682d0e1826b8223eae5983 | [
"MIT"
] | null | null | null | /*
* Copyright (C) the libgit2 contributors. All rights reserved.
*
* This file is part of libgit2, distributed under the GNU GPL v2 with
* a Linking Exception. For full terms see the included COPYING file.
*/
#include BLIK_LIBGIT2_U_common_h //original-code:"common.h"
#include BLIK_LIBGIT2_U_hash_h //original-code:"hash.h"
int git_hash_buf(git_oid *out, const void *data, size_t len)
{
git_hash_ctx ctx;
int error = 0;
if (git_hash_ctx_init(&ctx) < 0)
return -1;
if ((error = git_hash_update(&ctx, data, len)) >= 0)
error = git_hash_final(out, &ctx);
git_hash_ctx_cleanup(&ctx);
return error;
}
int git_hash_vec(git_oid *out, git_buf_vec *vec, size_t n)
{
git_hash_ctx ctx;
size_t i;
int error = 0;
if (git_hash_ctx_init(&ctx) < 0)
return -1;
for (i = 0; i < n; i++) {
if ((error = git_hash_update(&ctx, vec[i].data, vec[i].len)) < 0)
goto done;
}
error = git_hash_final(out, &ctx);
done:
git_hash_ctx_cleanup(&ctx);
return error;
}
| 20.416667 | 70 | 0.684694 |
7fef4bd778e5872041d32aba8468e35fd11cecb4 | 2,728 | h | C | core/cd_hw/cd_cart.h | Loxrie/genplus-gx | 4737ea32c9938b433256488b533b96863292a1be | [
"BSD-3-Clause"
] | 1 | 2015-03-16T08:22:16.000Z | 2015-03-16T08:22:16.000Z | core/cd_hw/cd_cart.h | Loxrie/genplus-gx | 4737ea32c9938b433256488b533b96863292a1be | [
"BSD-3-Clause"
] | 1 | 2017-09-07T14:15:50.000Z | 2017-09-07T14:15:50.000Z | core/cd_hw/cd_cart.h | Loxrie/genplus-gx | 4737ea32c9938b433256488b533b96863292a1be | [
"BSD-3-Clause"
] | null | null | null | /***************************************************************************************
* Genesis Plus
* CD compatible ROM/RAM cartridge support
*
* Copyright (C) 2012 Eke-Eke (Genesis Plus GX)
*
* Redistribution and use of this code or any derivative works are permitted
* provided that the following conditions are met:
*
* - Redistributions may not be sold, nor may they be used in a commercial
* product or activity.
*
* - Redistributions that are modified from the original source must include the
* complete source code, including the source code for all components used by a
* binary built from the modified sources. However, as a special exception, the
* source code distributed need not include anything that is normally distributed
* (in either source or binary form) with the major components (compiler, kernel,
* and so on) of the operating system on which the executable runs, unless that
* component itself accompanies the executable.
*
* - Redistributions must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* CD compatible ROM/RAM cartridge */
typedef struct
{
uint8 area[0x810000]; /* cartridge ROM/RAM area (max. 8MB + 64KB backup) */
uint8 boot; /* cartridge boot mode (0x00: boot from CD with ROM/RAM cartridge enabled, 0x40: boot from ROM cartridge with CD enabled) */
uint8 id; /* RAM cartridge ID (related to RAM size, 0 if disabled) */
uint8 prot; /* RAM cartridge write protection */
uint32 mask; /* RAM cartridge size mask */
} cd_cart_t;
/* Function prototypes */
extern void cd_cart_init(void);
| 52.461538 | 150 | 0.662757 |
7ff12fe12a8dfcf379ce100a6ded2acd94e53409 | 737 | c | C | lucet-wasi/tests/guests/getrusage.c | torch2424/lucet | 23305e5d8e08bed442c244d282b1a0389ed3d822 | [
"Apache-2.0"
] | 1 | 2019-07-26T14:17:45.000Z | 2019-07-26T14:17:45.000Z | lucet-wasi/tests/guests/getrusage.c | torch2424/lucet | 23305e5d8e08bed442c244d282b1a0389ed3d822 | [
"Apache-2.0"
] | 4 | 2019-12-14T02:56:43.000Z | 2021-07-06T22:18:23.000Z | lucet-wasi/tests/guests/getrusage.c | torch2424/lucet | 23305e5d8e08bed442c244d282b1a0389ed3d822 | [
"Apache-2.0"
] | 3 | 2019-12-05T02:21:42.000Z | 2021-04-06T08:06:52.000Z | #include <assert.h>
#include <sys/resource.h>
// Temporary fix until
// https://github.com/CraneStation/wasi-sysroot/pull/24/
// is available in wasi-sdk package
extern int getrusage(int who, struct rusage *usage);
int main()
{
struct rusage ru1;
getrusage(RUSAGE_SELF, &ru1);
for (int i = 0; i < 1000; i++) {
}
struct rusage ru2;
getrusage(RUSAGE_SELF, &ru2);
// assert that some time has passed
long long s1 = ru1.ru_utime.tv_sec;
long long us1 = ru1.ru_utime.tv_usec;
long long s2 = ru2.ru_utime.tv_sec;
long long us2 = ru2.ru_utime.tv_usec;
assert(s1 <= s2);
if (s1 == s2) {
// strictly less than, so the timestamps can't be equal
assert(us1 < us2);
}
}
| 23.774194 | 63 | 0.63365 |
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