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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
9f19a06c81edadd299155fac50268d2b29118284 | 5,659 | vhd | VHDL | board/FPGAMiner/FPGAMiner.ip_user_files/bd/design_1/ipshared/da11/hdl/MinerCoprocessor_v1_0.vhd | bkukanov/FPGA-Miner | a18cbf5e71c7641d8f3cbf77cc00b19df7199dfc | [
"MIT"
] | 21 | 2021-02-25T10:27:55.000Z | 2022-03-29T12:32:48.000Z | board/ip_repo/MinerCoprocessor_1.0/hdl/MinerCoprocessor_v1_0.vhd | AEW2015/fpga-miner | a18cbf5e71c7641d8f3cbf77cc00b19df7199dfc | [
"MIT"
] | 2 | 2022-03-26T17:35:16.000Z | 2022-03-28T17:44:56.000Z | board/FPGAMiner/FPGAMiner.ip_user_files/bd/design_1/ipshared/da11/hdl/MinerCoprocessor_v1_0.vhd | diogofferreira/fpga-miner | a18cbf5e71c7641d8f3cbf77cc00b19df7199dfc | [
"MIT"
] | 11 | 2021-02-25T10:36:26.000Z | 2022-03-25T04:27:31.000Z | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MinerCoprocessor_v1_0 is
generic (
-- Users to add parameters here
HASH_LENGTH : integer := 256;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave B... | 37.979866 | 94 | 0.615656 |
ed6e921291ef00188ded0e85771ad85f4b8cdd41 | 1,586 | vhd | VHDL | src/Logikanalysator/cpld-firmware/src/Mega_Control/send_control_datapath.vhd | dm7h/fpga-event-recorder | 4e53babbbb514ee375f4b5585b1d24e5b40f8df7 | [
"0BSD"
] | null | null | null | src/Logikanalysator/cpld-firmware/src/Mega_Control/send_control_datapath.vhd | dm7h/fpga-event-recorder | 4e53babbbb514ee375f4b5585b1d24e5b40f8df7 | [
"0BSD"
] | null | null | null | src/Logikanalysator/cpld-firmware/src/Mega_Control/send_control_datapath.vhd | dm7h/fpga-event-recorder | 4e53babbbb514ee375f4b5585b1d24e5b40f8df7 | [
"0BSD"
] | null | null | null | -- Projekt Logikanalysator an der FH-Augsburg
-- 5. Semester, Technische Informatik, WS2013/2014
-- A. Gareis, S. Vockinger
-- CPLD Komponente: send_control_datapath
-- Datum: 16.11.2013
-- Vers.: 1.0
-- ===========================================================================
library ieee;
use ieee.std_logic_1164.... | 29.924528 | 78 | 0.674653 |
3baa0c2a6efef58493fb8aff557af3d9026070df | 295 | vhd | VHDL | simulation/modelsim/rtl_work/@oscill_adc_clk/_primary.vhd | zxb-0/FPGA2 | 97c825c668bce6b9a64c1aa998497d6cdefb24ef | [
"MIT"
] | null | null | null | simulation/modelsim/rtl_work/@oscill_adc_clk/_primary.vhd | zxb-0/FPGA2 | 97c825c668bce6b9a64c1aa998497d6cdefb24ef | [
"MIT"
] | null | null | null | simulation/modelsim/rtl_work/@oscill_adc_clk/_primary.vhd | zxb-0/FPGA2 | 97c825c668bce6b9a64c1aa998497d6cdefb24ef | [
"MIT"
] | null | null | null | library verilog;
use verilog.vl_types.all;
entity Oscill_adc_clk is
port(
rst_n : in vl_logic;
clk : in vl_logic;
adc_clk_sel : in vl_logic_vector(4 downto 0);
clk_adc : out vl_logic
);
end Oscill_adc_clk;
| 26.818182 | 61 | 0.542373 |
90fba9f492ea0fcb821294a6ebbf5250df0fbe3e | 2,134 | vhd | VHDL | ps1/challenges/5_challenge/tb/tb.vhd | Clockfix/RTR710 | 15a6dcd170c8c4b5ce9be35fdc9c9478d5b99842 | [
"MIT"
] | null | null | null | ps1/challenges/5_challenge/tb/tb.vhd | Clockfix/RTR710 | 15a6dcd170c8c4b5ce9be35fdc9c9478d5b99842 | [
"MIT"
] | null | null | null | ps1/challenges/5_challenge/tb/tb.vhd | Clockfix/RTR710 | 15a6dcd170c8c4b5ce9be35fdc9c9478d5b99842 | [
"MIT"
] | null | null | null | library ieee;
library rtu;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use rtu.random.all;
entity tb is
end entity;
architecture RTL of tb is
-- Test constants
constant TEST_COUNT : natural := 1000;
-- DUT signals
signal input : std_logic_vector(15 downto 0) := (others => ... | 29.232877 | 84 | 0.547329 |
a7c6df9463c67e8f21850b29b39d7ac9e62ce2cf | 2,082 | vhd | VHDL | VHDL/testbench/tb_clockgen.vhd | djmatt/VHDL-Lib | a1a047533cdf2c0a50e741b7b26f1c422de04d88 | [
"MIT"
] | null | null | null | VHDL/testbench/tb_clockgen.vhd | djmatt/VHDL-Lib | a1a047533cdf2c0a50e741b7b26f1c422de04d88 | [
"MIT"
] | null | null | null | VHDL/testbench/tb_clockgen.vhd | djmatt/VHDL-Lib | a1a047533cdf2c0a50e741b7b26f1c422de04d88 | [
"MIT"
] | null | null | null | --------------------------------------------------------------------------------------------------
-- Clock generator for test-benches
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
-------------------------------------... | 39.283019 | 98 | 0.391451 |
2302b20b4e8c33a57dbdf8ddb9858527d314e5a7 | 903 | vhdl | VHDL | Hardware/Xilinx_AWSF1_HDK/cl_hello_world_drm1act/design/drm_hdk/activator0/sim/drm_license_package.vhdl | Accelize/GettingStarted_Examples | d010f6969d801088a1671f9145a59f916c1f4d15 | [
"Apache-2.0"
] | 6 | 2019-07-03T12:51:44.000Z | 2021-06-22T00:23:17.000Z | Hardware/Xilinx_AWSF1_HDK/cl_hello_world_drm1act/design/drm_hdk/activator0/sim/drm_license_package.vhdl | Accelize/GettingStarted_Examples | d010f6969d801088a1671f9145a59f916c1f4d15 | [
"Apache-2.0"
] | null | null | null | Hardware/Xilinx_AWSF1_HDK/cl_hello_world_drm1act/design/drm_hdk/activator0/sim/drm_license_package.vhdl | Accelize/GettingStarted_Examples | d010f6969d801088a1671f9145a59f916c1f4d15 | [
"Apache-2.0"
] | 1 | 2019-10-11T09:37:04.000Z | 2019-10-11T09:37:04.000Z | ---------------------------------------------------------------------
----
---- AUTOGENERATED FILE - DO NOT EDIT
---- DRM SCRIPT VERSION 2.2.0
---- DRM HDK VERSION 6.0.0.0
---- DRM VERSION 6.0.0
---- COPYRIGHT (C) ALGODONE
----
---------------------------------------------------------------------
library IEEE;
use IEE... | 45.15 | 397 | 0.708749 |
4be8f210e3386d45665b89bbac53e39a40f52f35 | 5,067 | vhd | VHDL | soc_arty_top.vhd | bonfireprocessor/bonfire-basic-soc | 947333c0dcea6c3668f1a3871230a0ca7e6ecd8a | [
"MIT"
] | 1 | 2020-05-18T21:04:51.000Z | 2020-05-18T21:04:51.000Z | soc_arty_top.vhd | bonfireprocessor/bonfire-basic-soc | 947333c0dcea6c3668f1a3871230a0ca7e6ecd8a | [
"MIT"
] | null | null | null | soc_arty_top.vhd | bonfireprocessor/bonfire-basic-soc | 947333c0dcea6c3668f1a3871230a0ca7e6ecd8a | [
"MIT"
] | null | null | null | ----------------------------------------------------------------------------------
-- Module Name: bonfire_basic_soc - Behavioral
-- The Bonfire Processor Project, (c) 2016,2017 Thomas Hornschuh
--
-- License: See LICENSE or LICENSE.txt File in git project root.
--
--
---------------------------------------------... | 28.627119 | 101 | 0.559108 |
11334f4039e433787d5420c94f3be92956dedb79 | 141,071 | vhd | VHDL | rpi-camera/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_s2mm_linebuf.vhd | security-geeks/parallella-examples | 364595c1a5547b6c1d2007481747147430fcdadb | [
"BSD-3-Clause"
] | 312 | 2015-01-03T17:04:30.000Z | 2022-02-22T20:44:45.000Z | rpi-camera/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_s2mm_linebuf.vhd | security-geeks/parallella-examples | 364595c1a5547b6c1d2007481747147430fcdadb | [
"BSD-3-Clause"
] | 15 | 2015-02-11T22:52:42.000Z | 2019-04-09T02:45:30.000Z | rpi-camera/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_s2mm_linebuf.vhd | security-geeks/parallella-examples | 364595c1a5547b6c1d2007481747147430fcdadb | [
"BSD-3-Clause"
] | 135 | 2015-01-13T02:13:25.000Z | 2022-01-25T12:23:31.000Z | -------------------------------------------------------------------------------
-- axi_vdma_s2mm_linebuf
-------------------------------------------------------------------------------
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All righ... | 41.224722 | 188 | 0.455508 |
e472de2390e7a6ad0df6a72bb10dff7fcfa32052 | 967 | vhd | VHDL | vhd/05-pipelined_FP_adder/02-shift_right.vhd | stark-dev/dlx-processor | 607ba09d0cd83c053fedce2994cb2b7de4fc14a6 | [
"MIT"
] | null | null | null | vhd/05-pipelined_FP_adder/02-shift_right.vhd | stark-dev/dlx-processor | 607ba09d0cd83c053fedce2994cb2b7de4fc14a6 | [
"MIT"
] | null | null | null | vhd/05-pipelined_FP_adder/02-shift_right.vhd | stark-dev/dlx-processor | 607ba09d0cd83c053fedce2994cb2b7de4fc14a6 | [
"MIT"
] | null | null | null | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.DLX_package.all;
ENTITY shift_right IS
PORT( SIGNIFICAND : IN std_logic_vector(23 downto 0);
D : IN std_logic_vector(7 downto 0);
SIG_OUT : OUT std_logic_vector(23 downto 0);
G : OUT std_logic;
R ... | 25.447368 | 79 | 0.670114 |
2267ea5923657f471382f41134bc3606c379c6b8 | 101,528 | vhd | VHDL | boards/ip/iprepo/SpectrumAnalyser_v1_1/hdl/vhdl/SpectrumAnalyser_src_Spectrum_Options.vhd | dnorthcote/rfsoc_sam_spectrum_map | cd6b78e642d9fec36c0f9a7fea904a6d07db8272 | [
"BSD-3-Clause"
] | 39 | 2020-02-22T00:40:51.000Z | 2022-03-30T00:39:45.000Z | boards/ip/iprepo/SpectrumAnalyser_v1_1/hdl/vhdl/SpectrumAnalyser_src_Spectrum_Options.vhd | dnorthcote/rfsoc_sam_spectrum_map | cd6b78e642d9fec36c0f9a7fea904a6d07db8272 | [
"BSD-3-Clause"
] | 7 | 2021-01-19T18:46:19.000Z | 2022-03-10T10:25:43.000Z | boards/ip/iprepo/SpectrumAnalyser_v1_1/hdl/vhdl/SpectrumAnalyser_src_Spectrum_Options.vhd | dnorthcote/rfsoc_sam_spectrum_map | cd6b78e642d9fec36c0f9a7fea904a6d07db8272 | [
"BSD-3-Clause"
] | 19 | 2020-02-25T10:42:51.000Z | 2021-12-15T06:40:41.000Z | -- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\spectrum_analyser\SpectrumAnalyser_src_Spectrum_Options.vhd
-- Created: 2021-03-09 14:00:48
--
-- Generated by MATLAB 9.8 and HDL Coder 3.16
--
-- -------------------------------------------------------------
-- ------... | 48.186047 | 220 | 0.665688 |
a701166abbcb329f3cec5057d9b788002d9a660d | 2,762 | vhd | VHDL | src/MultGpio.vhd | leonardoaraujodf/fpga_projects | 1d115472ff588397feba451b177eecea9048f372 | [
"MIT"
] | null | null | null | src/MultGpio.vhd | leonardoaraujodf/fpga_projects | 1d115472ff588397feba451b177eecea9048f372 | [
"MIT"
] | null | null | null | src/MultGpio.vhd | leonardoaraujodf/fpga_projects | 1d115472ff588397feba451b177eecea9048f372 | [
"MIT"
] | null | null | null | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.11.2019 09:35:36
-- Design Name:
-- Module Name: MultGpio - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
--... | 27.078431 | 82 | 0.627082 |
e9b63830ed17c91384977ac77f4c81066ca06d6d | 35,794 | vhd | VHDL | example/VCU118/fpga_25g/fpga/fpga.gen/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_Tx_Nibble.vhd | Endurancex/verilog-ethernet | 0c2f0940c6882c350405640bb8f9de1802e8e6d6 | [
"MIT"
] | null | null | null | example/VCU118/fpga_25g/fpga/fpga.gen/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_Tx_Nibble.vhd | Endurancex/verilog-ethernet | 0c2f0940c6882c350405640bb8f9de1802e8e6d6 | [
"MIT"
] | null | null | null | example/VCU118/fpga_25g/fpga/fpga.gen/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_Tx_Nibble.vhd | Endurancex/verilog-ethernet | 0c2f0940c6882c350405640bb8f9de1802e8e6d6 | [
"MIT"
] | null | null | null | --------------------------------------------------------------------------------
-- Author : Xilinx
--------------------------------------------------------------------------------
-- (c) Copyright 2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx,... | 63.352212 | 160 | 0.534782 |
6918a3eae08b6fab1b135869749b4999bd081213 | 3,902 | vhdl | VHDL | modelsim/data_detection/magnitude_grz.vhdl | gggmmm/BFSK-demodulator | 580e171e7b2604f10eb940b06db54f632aa69bbf | [
"MIT"
] | null | null | null | modelsim/data_detection/magnitude_grz.vhdl | gggmmm/BFSK-demodulator | 580e171e7b2604f10eb940b06db54f632aa69bbf | [
"MIT"
] | null | null | null | modelsim/data_detection/magnitude_grz.vhdl | gggmmm/BFSK-demodulator | 580e171e7b2604f10eb940b06db54f632aa69bbf | [
"MIT"
] | null | null | null | -- This module receives as input a complex number with FP representation of both
-- real and imag as 5|7 (integer|fractionary). It returns its magnitude with FP
-- representation 5|5, therefore, when viewing the output in modelsim, the result
-- (if expressed with unsigned), has to be divided by 32.
library ieee;
us... | 34.22807 | 87 | 0.545105 |
9487a8d62d8c740183e3f36b9667e239731a7366 | 17,690 | vhd | VHDL | VGATest_MultiTriRasterizeFramebuffer2/VGATest_MultiTriRasterizeFramebuffer2.srcs/sources_1/new/TexSample.vhd | code-tom-code/FPGAGPUTesting | 88c19263351c3520f6fbb34a16a07b3c8fcafe37 | [
"Zlib"
] | 1 | 2021-03-27T07:00:50.000Z | 2021-03-27T07:00:50.000Z | VGATest_MultiTriRasterizeFramebuffer2/VGATest_MultiTriRasterizeFramebuffer2.srcs/sources_1/new/TexSample.vhd | code-tom-code/FPGAGPUTesting | 88c19263351c3520f6fbb34a16a07b3c8fcafe37 | [
"Zlib"
] | null | null | null | VGATest_MultiTriRasterizeFramebuffer2/VGATest_MultiTriRasterizeFramebuffer2.srcs/sources_1/new/TexSample.vhd | code-tom-code/FPGAGPUTesting | 88c19263351c3520f6fbb34a16a07b3c8fcafe37 | [
"Zlib"
] | null | null | null | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
library work;
use work.EarthTextureData.ALL;
entity TexSample is
Port ( clk : in STD_LOGIC;
writeStrobe : in STD_LOGIC; --... | 42.626506 | 103 | 0.512549 |
753663cd57e1c3de89b910aa21eee03554b70b0d | 2,253 | vhd | VHDL | vhdl/src/rf_blocks_tb/dds_tb.vhd | Cognoscan/BoostDSP | 41c405b09d3ca3654f51d03c8a4b76b9ec8bd35e | [
"Apache-2.0"
] | 11 | 2017-06-25T22:24:17.000Z | 2022-01-09T11:49:15.000Z | vhdl/src/rf_blocks_tb/dds_tb.vhd | Cognoscan/BoostDSP | 41c405b09d3ca3654f51d03c8a4b76b9ec8bd35e | [
"Apache-2.0"
] | null | null | null | vhdl/src/rf_blocks_tb/dds_tb.vhd | Cognoscan/BoostDSP | 41c405b09d3ca3654f51d03c8a4b76b9ec8bd35e | [
"Apache-2.0"
] | 4 | 2016-10-05T12:25:40.000Z | 2018-11-02T02:13:59.000Z | --! @file dds_tb.vhd
--! @brief Direct Digital Synthesizer Testbench
--! @author Scott Teal (Scott@Teals.org)
--! @date 2013-11-04
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the... | 24.758242 | 79 | 0.656458 |
22844ee6a6cd8f5bd73d85966b95f352d20f0474 | 3,134 | vhdl | VHDL | boards/Pynq-Z2/base/base/base.cache/ip/2020.1.1/6a6c5efa481f79f6/base_collector_pmoda_rpi_0_sim_netlist.vhdl | DhirenWijesinghe/OV7670_PYNQ | 3405571c7724fdb64b33bf1893c108dfa1c425da | [
"BSD-3-Clause"
] | null | null | null | boards/Pynq-Z2/base/base/base.cache/ip/2020.1.1/6a6c5efa481f79f6/base_collector_pmoda_rpi_0_sim_netlist.vhdl | DhirenWijesinghe/OV7670_PYNQ | 3405571c7724fdb64b33bf1893c108dfa1c425da | [
"BSD-3-Clause"
] | null | null | null | boards/Pynq-Z2/base/base/base.cache/ip/2020.1.1/6a6c5efa481f79f6/base_collector_pmoda_rpi_0_sim_netlist.vhdl | DhirenWijesinghe/OV7670_PYNQ | 3405571c7724fdb64b33bf1893c108dfa1c425da | [
"BSD-3-Clause"
] | null | null | null | -- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1.1 (win64) Build 2960000 Wed Aug 5 22:57:20 MDT 2020
-- Date : Mon May 17 23:23:09 2021
-- Host : DESKTOP-LL0QRS1 running 64-bit maj... | 58.037037 | 137 | 0.72208 |
4a317301aac0b1aad82ea56fa73389456b631af9 | 21,077 | vhd | VHDL | WD_HLS/WeedD/solution1/sim/vhdl/duplicateMat_1.vhd | joseluisnoguera/FPGA_Weed_Detection | 6e3559df65ba021e0c75de08fa8101734f9eca32 | [
"MIT"
] | null | null | null | WD_HLS/WeedD/solution1/sim/vhdl/duplicateMat_1.vhd | joseluisnoguera/FPGA_Weed_Detection | 6e3559df65ba021e0c75de08fa8101734f9eca32 | [
"MIT"
] | null | null | null | WD_HLS/WeedD/solution1/sim/vhdl/duplicateMat_1.vhd | joseluisnoguera/FPGA_Weed_Detection | 6e3559df65ba021e0c75de08fa8101734f9eca32 | [
"MIT"
] | 1 | 2022-01-01T04:01:30.000Z | 2022-01-01T04:01:30.000Z | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
-- Version: 2019.2.1
-- Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.... | 43.819127 | 118 | 0.723822 |
0dda2362609612101f8cc265c28360c5ea0ab67c | 2,864 | vhd | VHDL | Uart/Uart.srcs/sources_1/imports/project_1/uart_rx.vhd | Bkisa/Uart | 0e2de3f5f4b923fc4f70ea2a46c6ea75d841ae48 | [
"Unlicense"
] | null | null | null | Uart/Uart.srcs/sources_1/imports/project_1/uart_rx.vhd | Bkisa/Uart | 0e2de3f5f4b923fc4f70ea2a46c6ea75d841ae48 | [
"Unlicense"
] | null | null | null | Uart/Uart.srcs/sources_1/imports/project_1/uart_rx.vhd | Bkisa/Uart | 0e2de3f5f4b923fc4f70ea2a46c6ea75d841ae48 | [
"Unlicense"
] | 1 | 2020-07-12T15:05:11.000Z | 2020-07-12T15:05:11.000Z | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity uart_rx is
generic ( M : integer ;
D : integer := 8 );
port ( clk, rst: in std_logic;
rx_i : in std_logic;
data_o : out std_logic_vector(D-1 downto 0);
rx_ready_o : out ... | 32.179775 | 80 | 0.339385 |
4dc8170c1bcfc9be7d8840202f19582736188436 | 2,318 | vhd | VHDL | A8 - Elementos operativos de um Datapath single-cycle/mips_single_cycle.vhd | ZePaiva/ACI | 5f20234e2901ff78f731c04977dabd9ce1ab629c | [
"BSD-3-Clause"
] | null | null | null | A8 - Elementos operativos de um Datapath single-cycle/mips_single_cycle.vhd | ZePaiva/ACI | 5f20234e2901ff78f731c04977dabd9ce1ab629c | [
"BSD-3-Clause"
] | null | null | null | A8 - Elementos operativos de um Datapath single-cycle/mips_single_cycle.vhd | ZePaiva/ACI | 5f20234e2901ff78f731c04977dabd9ce1ab629c | [
"BSD-3-Clause"
] | 1 | 2019-10-22T09:48:53.000Z | 2019-10-22T09:48:53.000Z | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.MIPS_pkg.all;
use work.DisplayUnit_pkg.all;
entity mips_single_cycle is
port(CLOCK_50 : in std_logic;
SW : in std_logic_vector(2 downto 0);
KEY : in std_logic_vector(3 downto 0);
HEX0 : out std_logic_vector(6 downto 0);
HEX1... | 27.270588 | 78 | 0.623382 |
71743ef8d72380bb77423b868b7ff636a1238e2a | 5,842 | vhd | VHDL | src/j1b/wb/j1b2wb.vhd | wzab/AFCK_J1B_FORTH | 09ba5288f7a16e22902c170487084f32684c2907 | [
"BSD-3-Clause"
] | 3 | 2016-08-11T17:04:44.000Z | 2021-03-31T23:45:26.000Z | src/j1b/wb/j1b2wb.vhd | wzab/AFCK_J1B_FORTH | 09ba5288f7a16e22902c170487084f32684c2907 | [
"BSD-3-Clause"
] | null | null | null | src/j1b/wb/j1b2wb.vhd | wzab/AFCK_J1B_FORTH | 09ba5288f7a16e22902c170487084f32684c2907 | [
"BSD-3-Clause"
] | null | null | null | -------------------------------------------------------------------------------
-- Title : j1b2wb
-- Project :
-------------------------------------------------------------------------------
-- File : j1b2wb.vhd
-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
-- Company : Institute of Elec... | 35.192771 | 85 | 0.548613 |
d4dfca3ff0a6aa9c972b3929445a1e3fa31f1380 | 73,773 | vhd | VHDL | src/h264cavlc.vhd | Versemongerr/hardh264 | a1c84e027fd666d29a5678874c459dcab9aa8c78 | [
"BSD-3-Clause"
] | 212 | 2016-01-03T17:12:01.000Z | 2022-03-26T03:07:42.000Z | src/h264cavlc.vhd | lizn520/hardh264 | ce5e6c4791bb82546fd8cd5d09af6fbc1523a5ed | [
"BSD-3-Clause"
] | 7 | 2016-05-02T13:13:57.000Z | 2022-02-04T07:27:44.000Z | src/h264cavlc.vhd | lizn520/hardh264 | ce5e6c4791bb82546fd8cd5d09af6fbc1523a5ed | [
"BSD-3-Clause"
] | 58 | 2016-08-08T10:28:39.000Z | 2022-03-01T13:30:59.000Z | -------------------------------------------------------------------------
-- H264 CAVLC encoding - VHDL
--
-- Written by Andy Henson
-- Copyright (c) 2008 Zexia Access Ltd
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided th... | 56.101141 | 115 | 0.721253 |
b352f93765d52fba8a14b7e85fba843ebb2c7a81 | 96 | vhd | VHDL | Hardware/quanta/simulation/qsim/work/quanta_vlg_vec_tst/_primary.vhd | ViniciusLambardozzi/quanta | d4074216fe6bd812b500c0d7e6b06e8cb825b321 | [
"MIT"
] | null | null | null | Hardware/quanta/simulation/qsim/work/quanta_vlg_vec_tst/_primary.vhd | ViniciusLambardozzi/quanta | d4074216fe6bd812b500c0d7e6b06e8cb825b321 | [
"MIT"
] | null | null | null | Hardware/quanta/simulation/qsim/work/quanta_vlg_vec_tst/_primary.vhd | ViniciusLambardozzi/quanta | d4074216fe6bd812b500c0d7e6b06e8cb825b321 | [
"MIT"
] | null | null | null | library verilog;
use verilog.vl_types.all;
entity quanta_vlg_vec_tst is
end quanta_vlg_vec_tst;
| 19.2 | 28 | 0.854167 |
bf54280a149ddd83a90d83a0be1bc6e04580813a | 460,975 | vhdl | VHDL | soc/rtl/xilinx_ip/axi_crossbar_0/axi_crossbar_0_sim_netlist.vhdl | mrDrivingDuck/mips32-CPU | 2688faa38855a580f707b462aae722222ee7c05f | [
"MIT"
] | null | null | null | soc/rtl/xilinx_ip/axi_crossbar_0/axi_crossbar_0_sim_netlist.vhdl | mrDrivingDuck/mips32-CPU | 2688faa38855a580f707b462aae722222ee7c05f | [
"MIT"
] | null | null | null | soc/rtl/xilinx_ip/axi_crossbar_0/axi_crossbar_0_sim_netlist.vhdl | mrDrivingDuck/mips32-CPU | 2688faa38855a580f707b462aae722222ee7c05f | [
"MIT"
] | 2 | 2019-12-12T01:06:37.000Z | 2020-06-13T10:53:30.000Z | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017
-- Date : Fri Jul 7 21:59:08 2017
-- Host : zyw-PC running 64-bit Service Pack 1... | 35.121905 | 294 | 0.634371 |
3cd0ba8ca8b4d7b484064e1f058bb37cb1b8be81 | 1,155 | vhd | VHDL | SIKEp503/src/expand.vhd | kozielbrian/VHDL-SIKE_R2 | fcd86dbbfbe5dea3917e1187e49aa64a4c3b401b | [
"MIT"
] | 1 | 2020-04-21T05:46:01.000Z | 2020-04-21T05:46:01.000Z | SIKEp503/src/expand.vhd | kozielbrian/VHDL-SIKE_R2 | fcd86dbbfbe5dea3917e1187e49aa64a4c3b401b | [
"MIT"
] | null | null | null | SIKEp503/src/expand.vhd | kozielbrian/VHDL-SIKE_R2 | fcd86dbbfbe5dea3917e1187e49aa64a4c3b401b | [
"MIT"
] | 1 | 2021-01-05T09:05:36.000Z | 2021-01-05T09:05:36.000Z | --********************************************************************************************
--* VHDL-SIKE: a speed optimized hardware implementation of the
--* Supersingular Isogeny Key Encapsulation scheme
--*
--* Copyright (c) Brian Koziel, Reza Azarderakhsh, and Rami El Khatib
--*
--***************... | 28.170732 | 96 | 0.464069 |
58c13893e225c44964024bce48e5ac26cdf5aea4 | 26,304 | vhd | VHDL | 03_capi_integration/accelerator_synth/psl_fpga/quartus_ip/sfpp_reconfig/simulation/submodules/sfpp_reconfig_mm_interconnect_0.vhd | atmughrabi/AccelGraph_Express | 09a69364c4fb98d77936fd4b21065220a0d55c4c | [
"BSD-2-Clause"
] | 3 | 2021-10-10T20:15:56.000Z | 2022-01-28T20:27:07.000Z | 03_capi_integration/accelerator_synth/psl_fpga/quartus_ip/sfpp_reconfig/simulation/submodules/sfpp_reconfig_mm_interconnect_0.vhd | atmughrabi/AccelGraph_Express | 09a69364c4fb98d77936fd4b21065220a0d55c4c | [
"BSD-2-Clause"
] | null | null | null | 03_capi_integration/accelerator_synth/psl_fpga/quartus_ip/sfpp_reconfig/simulation/submodules/sfpp_reconfig_mm_interconnect_0.vhd | atmughrabi/AccelGraph_Express | 09a69364c4fb98d77936fd4b21065220a0d55c4c | [
"BSD-2-Clause"
] | 1 | 2022-01-06T21:06:07.000Z | 2022-01-06T21:06:07.000Z | -- sfpp_reconfig_mm_interconnect_0.vhd
-- This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
-- will probably be lost.
--
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sfpp_reconfig_mm_interconnect_0 is... | 85.126214 | 221 | 0.47259 |
1c8f5295abae9952f88d1479d6fbd338610cd42d | 964 | vhd | VHDL | rtl/MUX2X1_VEC.vhd | abdelazeem201/Intel-8085-is-an-8-bit-microprocessor | df2c2aa0743d4a88b5a6fd4e3d22179263d467af | [
"MIT"
] | 1 | 2022-03-16T15:13:34.000Z | 2022-03-16T15:13:34.000Z | rtl/MUX2X1_VEC.vhd | abdelazeem201/Intel-8085-is-an-8-bit-microprocessor | df2c2aa0743d4a88b5a6fd4e3d22179263d467af | [
"MIT"
] | null | null | null | rtl/MUX2X1_VEC.vhd | abdelazeem201/Intel-8085-is-an-8-bit-microprocessor | df2c2aa0743d4a88b5a6fd4e3d22179263d467af | [
"MIT"
] | null | null | null | ------------------------------------------------------------
--DESIGN MUX2X1_VEC BEGINS here
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity MUX2X1_VEC is
port( dat_out : out std_logic_vector(7 downto 0);
EN : in std_logic;
... | 31.096774 | 62 | 0.41805 |
96d84f681837d1a8a37a4ec80f1318d8ddc8c445 | 1,712 | vhd | VHDL | models/Beamer/ip/fft_filter/fft_filters_FFT_Frame_Pulse_Gen_block.vhd | trintinwibul/simulink_models | 832b4da0ff91d34097fcb6118eeec3b09854d745 | [
"MIT"
] | 3 | 2021-06-02T08:10:22.000Z | 2021-06-02T09:57:26.000Z | models/Beamer/ip/fft_filter/fft_filters_FFT_Frame_Pulse_Gen_block.vhd | trintinwibul/simulink_models | 832b4da0ff91d34097fcb6118eeec3b09854d745 | [
"MIT"
] | 68 | 2019-09-27T18:18:57.000Z | 2021-06-02T17:04:43.000Z | models/Beamer/ip/fft_filter/fft_filters_FFT_Frame_Pulse_Gen_block.vhd | trintinwibul/simulink_models | 832b4da0ff91d34097fcb6118eeec3b09854d745 | [
"MIT"
] | 3 | 2019-11-14T20:05:08.000Z | 2021-06-02T07:31:02.000Z | -- -------------------------------------------------------------
--
-- File Name: C:\Users\conno\Documents\NIH-GitHub\simulink_models\models\fft_filters\hdlsrc\fft_filters\fft_filters_FFT_Frame_Pulse_Gen_block.vhd
--
-- Generated by MATLAB 9.9 and HDL Coder 3.17
--
-- ------------------------------------------------... | 32.923077 | 145 | 0.607477 |
bce168d945cb0d88c7209dabd3a706df2fc813d7 | 4,900 | vhd | VHDL | image_file.vhd | SamTheDev/VGA-VHDL-SIMULATOR | 3294f1518a69df6f8fdf834922ffe6dc840e0dcb | [
"MIT"
] | 3 | 2016-11-20T18:04:29.000Z | 2019-08-31T19:32:54.000Z | image_file.vhd | SamTheDev/VGA-VHDL-SIMULATOR | 3294f1518a69df6f8fdf834922ffe6dc840e0dcb | [
"MIT"
] | null | null | null | image_file.vhd | SamTheDev/VGA-VHDL-SIMULATOR | 3294f1518a69df6f8fdf834922ffe6dc840e0dcb | [
"MIT"
] | 1 | 2018-02-07T13:19:23.000Z | 2018-02-07T13:19:23.000Z | ------------------------------------------------------------
-- VGA SimuLator projet VHDL
-- Save a picture to a spesific location on the disk
-- S. Rubini, septembre 2015
-- save one picture after the Reset is seted using the sun raster format
-- no control uppon the count of pixels
----------------------------------... | 33.561644 | 72 | 0.667755 |
48d69ce18558e0bd5d4752ade299d80fa2dc9fb5 | 762 | vhd | VHDL | Moduli/ADD7.vhd | FilipRin/Basketball_Scoreboard_Quartus | c4bf5b8cb9db672482c151ff1840d3cfafe24030 | [
"MIT"
] | null | null | null | Moduli/ADD7.vhd | FilipRin/Basketball_Scoreboard_Quartus | c4bf5b8cb9db672482c151ff1840d3cfafe24030 | [
"MIT"
] | null | null | null | Moduli/ADD7.vhd | FilipRin/Basketball_Scoreboard_Quartus | c4bf5b8cb9db672482c151ff1840d3cfafe24030 | [
"MIT"
] | null | null | null | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ADD7 is
port
(
A : in std_logic_vector (6 downto 0);
B : in std_logic_vector (6 downto 0);
Cin : in std_logic;
F : out std_logic_vector (6 downto 0);
Cout : out std_logic
);
end entity;
architecture rtl of ADD7 i... | 18.585366 | 63 | 0.635171 |
852ae90f2ef1742d47daf6e56ebfdeba5ae5f7d6 | 4,258 | vhd | VHDL | rtl/techmap/pll/clkp90_k7.vhd | hossameldin1995/riscv_vhdl | aab7196a6b9962626ed7314b7c86b93760e76f83 | [
"Apache-2.0"
] | 432 | 2015-11-08T20:32:45.000Z | 2022-03-30T07:53:01.000Z | rtl/techmap/pll/clkp90_k7.vhd | hossameldin1995/riscv_vhdl | aab7196a6b9962626ed7314b7c86b93760e76f83 | [
"Apache-2.0"
] | 37 | 2016-02-23T13:13:34.000Z | 2021-09-27T14:06:50.000Z | rtl/techmap/pll/clkp90_k7.vhd | hossameldin1995/riscv_vhdl | aab7196a6b9962626ed7314b7c86b93760e76f83 | [
"Apache-2.0"
] | 99 | 2015-12-07T05:17:18.000Z | 2022-02-17T11:17:14.000Z | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Clock phase offset generator (90 deg) for Kintex7 FPGA.
----------------------------------------... | 36.393162 | 93 | 0.558948 |
cc41aef5d898ad4d1e63a2479112c0caf83b26fa | 307 | vhd | VHDL | book/exercise3.27/design.vhd | schoeberl/digital-electronics | a7539b070cd63483d8b699a1bdf251c68a6eca92 | [
"BSD-2-Clause"
] | 1 | 2022-03-17T00:14:40.000Z | 2022-03-17T00:14:40.000Z | book/exercise3.27/design.vhd | schoeberl/digital-electronics | a7539b070cd63483d8b699a1bdf251c68a6eca92 | [
"BSD-2-Clause"
] | null | null | null | book/exercise3.27/design.vhd | schoeberl/digital-electronics | a7539b070cd63483d8b699a1bdf251c68a6eca92 | [
"BSD-2-Clause"
] | null | null | null | -- Exercise 3.27
-- logic function
library ieee;
use ieee.std_logic_1164.all;
entity foo is
port(x, y, z : in std_logic;
output : out std_logic);
end foo;
architecture impl of foo is
begin
-- Add your code here (start)
output <= ...;
-- Add your code here (end)
end impl; | 13.954545 | 32 | 0.62215 |
3bac2fb9027a4765557e3d09ab1ed274a3aaf40c | 2,328 | vhd | VHDL | soc/pp_soc_memory.vhd | jeanthom/potato | 24d62ec589f240882b368a5cc6871d1944cb4f4c | [
"BSD-3-Clause"
] | 218 | 2015-11-24T20:59:00.000Z | 2022-03-08T07:34:04.000Z | soc/pp_soc_memory.vhd | jeanthom/potato | 24d62ec589f240882b368a5cc6871d1944cb4f4c | [
"BSD-3-Clause"
] | 24 | 2015-11-29T21:03:25.000Z | 2021-08-03T12:43:07.000Z | soc/pp_soc_memory.vhd | jeanthom/potato | 24d62ec589f240882b368a5cc6871d1944cb4f4c | [
"BSD-3-Clause"
] | 47 | 2015-11-26T05:58:33.000Z | 2021-11-13T14:52:01.000Z | -- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_utilities.all;
--! @brief Simp... | 26.758621 | 107 | 0.63445 |
2cee2d22fff10f148072cb9ad63617bf8f129561 | 1,463 | vhd | VHDL | VHDL/04-03-14/04-03-14_TEST.vhd | AlessandroSpallina/CalcolatoriElettronici | f9109168bcf6779b9964c88a2f5dd590d5497d8b | [
"MIT"
] | 1 | 2019-04-16T21:41:35.000Z | 2019-04-16T21:41:35.000Z | VHDL/04-03-14/04-03-14_TEST.vhd | AlessandroSpallina/CalcolatoriElettronici | f9109168bcf6779b9964c88a2f5dd590d5497d8b | [
"MIT"
] | null | null | null | VHDL/04-03-14/04-03-14_TEST.vhd | AlessandroSpallina/CalcolatoriElettronici | f9109168bcf6779b9964c88a2f5dd590d5497d8b | [
"MIT"
] | null | null | null | -- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity TEST is
end TEST;
architecture BEH of TEST is
component gianni is
port (
op : in std_logic_vector(1 downto 0);
din : in std_logic_vector(31 downto 0);
nw, clk : in std_logic;
... | 24.79661 | 92 | 0.658237 |
b93f745ff74620ba37cb1a154b4acac3988f9a04 | 7,076 | vhd | VHDL | DMA/Orig/data_path.vhd | shriud/LowPower | bc2a807235d44b62fcee176c9fed963546d4a374 | [
"MIT"
] | 1 | 2019-01-09T15:16:58.000Z | 2019-01-09T15:16:58.000Z | DMA/Orig/data_path.vhd | shriud/LowPower | bc2a807235d44b62fcee176c9fed963546d4a374 | [
"MIT"
] | null | null | null | DMA/Orig/data_path.vhd | shriud/LowPower | bc2a807235d44b62fcee176c9fed963546d4a374 | [
"MIT"
] | null | null | null | --
-- See LICENSE.txt for license details
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.dma_types.all;
entity data_path is
generic(
addr_msb_g: address_range; -- address width - 1
data_msb_g: data_range; -- d... | 32.0181 | 94 | 0.596382 |
73cef6106c2905ee7c18daa3e27ab8a4d111880b | 975 | vhd | VHDL | VHDL/LAB_2/m.vhd | BismarckBamfo/Learning-VHDL | dafa1f9fff78d4ecb691433b09659117c6c88bcc | [
"MIT"
] | null | null | null | VHDL/LAB_2/m.vhd | BismarckBamfo/Learning-VHDL | dafa1f9fff78d4ecb691433b09659117c6c88bcc | [
"MIT"
] | null | null | null | VHDL/LAB_2/m.vhd | BismarckBamfo/Learning-VHDL | dafa1f9fff78d4ecb691433b09659117c6c88bcc | [
"MIT"
] | null | null | null | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:29:49 01/31/2020
-- Design Name:
-- Module Name: m - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
--... | 20.3125 | 82 | 0.558974 |
491f42815364c0accc8cb38f265ebbd16ffda006 | 480 | vhd | VHDL | lab01/full_adder/full_adder_bit.vhd | ciroceissler/mc602 | 010af17bbba01e86e2484cf724db5ec1746abc9b | [
"MIT"
] | 1 | 2017-10-06T01:08:50.000Z | 2017-10-06T01:08:50.000Z | lab01/full_adder/full_adder_bit.vhd | ciroceissler/mc602 | 010af17bbba01e86e2484cf724db5ec1746abc9b | [
"MIT"
] | null | null | null | lab01/full_adder/full_adder_bit.vhd | ciroceissler/mc602 | 010af17bbba01e86e2484cf724db5ec1746abc9b | [
"MIT"
] | null | null | null | -- project: lab01 - mc602
-- company: unicamp
-- author : ciro.ceissler@gmail.com
-- brief : full adder 1 bit
library ieee;
use ieee.std_logic_1164.all;
entity full_adder_bit is
port
(
a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out st... | 16.551724 | 50 | 0.614583 |
7f0fff5a77c0ca5a05bf0559bc58592f963ed18a | 433 | vhd | VHDL | load_use_case/load_use_case_detector.vhd | Passant-Abdelgalil/MIPS-Processor-Harvard-Architecture | f93a5781f659072261143f389575d5844cf46873 | [
"MIT"
] | 6 | 2022-01-11T20:18:58.000Z | 2022-02-09T20:19:33.000Z | load_use_case/load_use_case_detector.vhd | Passant-Abdelgalil/MIPS-Processor-Harvard-Architecture | f93a5781f659072261143f389575d5844cf46873 | [
"MIT"
] | null | null | null | load_use_case/load_use_case_detector.vhd | Passant-Abdelgalil/MIPS-Processor-Harvard-Architecture | f93a5781f659072261143f389575d5844cf46873 | [
"MIT"
] | 1 | 2022-02-09T19:41:04.000Z | 2022-02-09T19:41:04.000Z | library ieee;
use ieee.std_logic_1164.all;
ENTITY LOAD_USE_CASE_DETECTOR IS
PORT(
EX_MEMR:IN STD_LOGIC;
D_SRC1,D_SRC2,EX_dest:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
LOAD_USE_CASE_OUT:OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE LOAD_USE_CASE_DETECTOR_STRUCTURE OF LOAD_USE_CASE_DETECTOR IS
BEGIN
LOAD_USE_CASE_OUT<='1' WHEN ... | 18.041667 | 85 | 0.799076 |
54271a4f77011456cd848e0e5d809286eeaf65b9 | 38,466 | vhd | VHDL | loopback_microzed/vivado/demo/demo.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/d0c48dec/hdl/ramfifo/rd_fwft.vhd | sputnixru/PothosZynq | 85ac1253a346bb0f825b11df3d173bfbefcda887 | [
"BSL-1.0"
] | 11 | 2017-12-21T16:36:33.000Z | 2021-03-09T03:38:49.000Z | loopback_microzed/vivado/demo/demo.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/d0c48dec/hdl/ramfifo/rd_fwft.vhd | sputnixru/PothosZynq | 85ac1253a346bb0f825b11df3d173bfbefcda887 | [
"BSL-1.0"
] | 1 | 2016-05-27T17:46:22.000Z | 2016-05-28T21:11:01.000Z | loopback_microzed/vivado/demo/demo.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/d0c48dec/hdl/ramfifo/rd_fwft.vhd | sputnixru/PothosZynq | 85ac1253a346bb0f825b11df3d173bfbefcda887 | [
"BSL-1.0"
] | 10 | 2015-04-28T13:31:55.000Z | 2017-03-29T08:52:45.000Z | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | 74.402321 | 109 | 0.948682 |
e9161de24266b4ac85497e3829e937dfe74479af | 1,498 | vhd | VHDL | src/AUT_modif.vhd | Kzel/Monocycle-Processeur | 76910ac5516abb682f05a09663657a00286d9aec | [
"MIT"
] | 2 | 2021-01-24T21:51:36.000Z | 2021-01-24T22:24:24.000Z | src/AUT_modif.vhd | Kzel/Monocycle-Processeur | 76910ac5516abb682f05a09663657a00286d9aec | [
"MIT"
] | null | null | null | src/AUT_modif.vhd | Kzel/Monocycle-Processeur | 76910ac5516abb682f05a09663657a00286d9aec | [
"MIT"
] | null | null | null | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity AUT_modif is --assembleur de unite de traitement apres la modification
port(
Clk:in std_logic;
RegWr,RegSel:in std_logic;
Rn,Rd,Rm:in std_logic_vector(3 downto 0);
Imm:in std_logic_vector(7 downto 0);
COM1,COM2... | 40.486486 | 112 | 0.716956 |
c7ae552a770e2ac3898c7eb692900b826b305f86 | 4,279 | vhd | VHDL | Labs/07-ffs/flip_flops/flip_flops.srcs/sim_1/new/tb_jk_ff_rst.vhd | Dan5049/Digital-electronics-1 | f7f301180d08f847a53420a8d0d759a8ab4b166d | [
"MIT"
] | null | null | null | Labs/07-ffs/flip_flops/flip_flops.srcs/sim_1/new/tb_jk_ff_rst.vhd | Dan5049/Digital-electronics-1 | f7f301180d08f847a53420a8d0d759a8ab4b166d | [
"MIT"
] | null | null | null | Labs/07-ffs/flip_flops/flip_flops.srcs/sim_1/new/tb_jk_ff_rst.vhd | Dan5049/Digital-electronics-1 | f7f301180d08f847a53420a8d0d759a8ab4b166d | [
"MIT"
] | 1 | 2021-04-26T16:11:03.000Z | 2021-04-26T16:11:03.000Z | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.03.2021 19:56:48
-- Design Name:
-- Module Name: tb_jk_ff_rst - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision... | 26.91195 | 82 | 0.437953 |
1094303c38827488d49eee6871823064ad6d6813 | 401 | vhd | VHDL | vote_condit.vhd | LeeSuper666/TJU-SEIE-Digital-System-Design-And-HDL | f6e51cf7167e43b333f09d0f77c15e90d319738b | [
"MIT"
] | 1 | 2020-02-11T01:53:27.000Z | 2020-02-11T01:53:27.000Z | vote_condit.vhd | LeeSuper666/TJU-SEIE-Digital-System-Design-And-HDL | f6e51cf7167e43b333f09d0f77c15e90d319738b | [
"MIT"
] | null | null | null | vote_condit.vhd | LeeSuper666/TJU-SEIE-Digital-System-Design-And-HDL | f6e51cf7167e43b333f09d0f77c15e90d319738b | [
"MIT"
] | null | null | null | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY vote_condit IS
PORT (vote: IN BIT_VECTOR(0 TO 2);
y: OUT BIT);
END ENTITY vote_condit;
Architecture condition OF vote_condit IS
BEGIN
y<='0' WHEN vote="000" ELSE
'0' WHEN vote="001" ELSE
'0' WHEN vote="010" ELSE
'1' WHEN VOTE="011" ELSE
'0' WHEN VOTE="10... | 21.105263 | 41 | 0.678304 |
7f67e0fb12546c40ef274c718e2aae5d2b74a454 | 380 | vhd | VHDL | Entrega 3/Sumador32bits.vhd | gustavogarciautp/Procesador | 9cfcfb963f0b03baa4ba09e0091370a24b997dac | [
"MIT"
] | null | null | null | Entrega 3/Sumador32bits.vhd | gustavogarciautp/Procesador | 9cfcfb963f0b03baa4ba09e0091370a24b997dac | [
"MIT"
] | null | null | null | Entrega 3/Sumador32bits.vhd | gustavogarciautp/Procesador | 9cfcfb963f0b03baa4ba09e0091370a24b997dac | [
"MIT"
] | null | null | null | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity Sumador32bits is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Result : out STD_LOGIC_VECTOR (31 downto 0));
end Sumador32bits;
architecture Behavioral of Suma... | 20 | 57 | 0.723684 |
38e419dd33743646f1dcf32956783b97b0e70f8a | 2,617 | vhd | VHDL | code/generators/inline_03d.vhd | dat4087/System-Designers-Guide-to-VHDL-AMS | b82154c712accd2eb64c211a0d09bb5f0ab0abbe | [
"Apache-2.0"
] | 1 | 2020-04-07T14:52:22.000Z | 2020-04-07T14:52:22.000Z | code/generators/inline_03d.vhd | dat4087/System-Designers-Guide-to-VHDL-AMS | b82154c712accd2eb64c211a0d09bb5f0ab0abbe | [
"Apache-2.0"
] | null | null | null | code/generators/inline_03d.vhd | dat4087/System-Designers-Guide-to-VHDL-AMS | b82154c712accd2eb64c211a0d09bb5f0ab0abbe | [
"Apache-2.0"
] | null | null | null | library ieee; use ieee.std_logic_1164.all;
entity buf is
port ( a : in std_logic; y : out std_logic );
end buf;
architecture basic of buf is
begin
y <= a;
end basic;
library ieee; use ieee.std_logic_1164.all;
entity fanout_tree is
generic ( height : natural );
port ( input : in std_logic;
ou... | 21.991597 | 72 | 0.636607 |
699ab091023410e7f5b123674685d33e706d60ec | 41,576 | vhd | VHDL | roms/caos42_c.vhd | Niels3RT/KC854_MiSTer | 66babbc34ce8ba20430c6fea9da0e5e2e839b05c | [
"Unlicense"
] | 1 | 2022-02-22T15:12:01.000Z | 2022-02-22T15:12:01.000Z | roms/caos42_c.vhd | Niels3RT/KC854_MiSTer | 66babbc34ce8ba20430c6fea9da0e5e2e839b05c | [
"Unlicense"
] | null | null | null | roms/caos42_c.vhd | Niels3RT/KC854_MiSTer | 66babbc34ce8ba20430c6fea9da0e5e2e839b05c | [
"Unlicense"
] | 1 | 2021-03-24T05:57:29.000Z | 2021-03-24T05:57:29.000Z | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity caos_c is
generic(
ADDR_WIDTH : integer := 12
);
port (
clk : in std_logic;
addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data : out std_logic_vector(7 downto 0)
);
end caos_c;
architect... | 77.135436 | 84 | 0.354195 |
35215c9b56d5b25cff81553c44c1144532514329 | 25,729 | vhd | VHDL | vivado-library_of_digilent_ip/ip/usb2device_v1_0/src/Transmit_Path.vhd | Psomvanshi/Sobel_edge_detection | 1e6018286868b36a9ccaff3f1cb6208c5d97eebc | [
"MIT"
] | 1 | 2020-07-07T13:19:26.000Z | 2020-07-07T13:19:26.000Z | vivado-library_of_digilent_ip/ip/usb2device_v1_0/src/Transmit_Path.vhd | OhmVikrant/Sobel_edge_detection | 7980ea20887bf7186335591d46f6e71cd03d0d75 | [
"MIT"
] | null | null | null | vivado-library_of_digilent_ip/ip/usb2device_v1_0/src/Transmit_Path.vhd | OhmVikrant/Sobel_edge_detection | 7980ea20887bf7186335591d46f6e71cd03d0d75 | [
"MIT"
] | 2 | 2020-07-07T13:19:29.000Z | 2020-07-10T05:55:09.000Z | -------------------------------------------------------------------------------
--
-- File: Transmit_Path.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Cop... | 40.138846 | 168 | 0.661355 |
c6f1e5fc3a7048f5d2787cb66606e2f4ad1d9f96 | 1,846 | vhd | VHDL | sim/sim_tx.vhd | MJoergen/lan8720a | eb65bd7f9c1842abdc3509afb42dd6b1e7cf8595 | [
"MIT"
] | null | null | null | sim/sim_tx.vhd | MJoergen/lan8720a | eb65bd7f9c1842abdc3509afb42dd6b1e7cf8595 | [
"MIT"
] | null | null | null | sim/sim_tx.vhd | MJoergen/lan8720a | eb65bd7f9c1842abdc3509afb42dd6b1e7cf8595 | [
"MIT"
] | null | null | null | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;
-- This module generates framing for data to be transmitted.
-- This reads the signal 'start' and when asserted
-- generates an Ethernet frames based on 'data' and 'len'.
-- It finally asserts the 'done' signal.
entity sim_tx is
port (
... | 26.371429 | 83 | 0.62351 |
c7c25b4e812f737f8ae14e5944a7a8ae2f0498be | 23,780 | vhd | VHDL | vhdl/fixed_package_tb.vhd | fulvio-f/ann_mlp | 9ffd7b2c859c59aac320b2042569c901e14eb409 | [
"MIT"
] | null | null | null | vhdl/fixed_package_tb.vhd | fulvio-f/ann_mlp | 9ffd7b2c859c59aac320b2042569c901e14eb409 | [
"MIT"
] | null | null | null | vhdl/fixed_package_tb.vhd | fulvio-f/ann_mlp | 9ffd7b2c859c59aac320b2042569c901e14eb409 | [
"MIT"
] | null | null | null | --library std;
use std.textio.all;
--library work;
use work.fixed_package.all;
entity fixed_package_tb is
end entity fixed_package_tb;
architecture testbench of fixed_package_tb is
-- Auxiliary functions for testbench
function fixed2str(arg_L: fixed) return string is
variable fixed_str: string (arg_L'length downt... | 50.274841 | 127 | 0.630572 |
0c8436d42842b6ef0d5bfc010f4971ccf8e8a6f2 | 6,205 | vhd | VHDL | 2nd Year/Computer Architecture I/Final-Submission/Testbenches/datapath_tb.vhd | DanielNugent/College | 6b6807fd35334eb4bbcc65f800c5f5137f96be68 | [
"MIT"
] | 1 | 2020-03-13T12:20:39.000Z | 2020-03-13T12:20:39.000Z | 2nd Year/Computer Architecture I/Final-Submission/Testbenches/datapath_tb.vhd | Jascoco/College | 312956ec62b1a999cff3f7ba6c51fd02235b2759 | [
"MIT"
] | null | null | null | 2nd Year/Computer Architecture I/Final-Submission/Testbenches/datapath_tb.vhd | Jascoco/College | 312956ec62b1a999cff3f7ba6c51fd02235b2759 | [
"MIT"
] | 1 | 2020-05-12T14:01:07.000Z | 2020-05-12T14:01:07.000Z | --Daniel Nugent
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY datapath_tb IS
-- Port ( );
END datapath_tb;
ARCHITECTURE Behavioral OF datapath_tb IS
-- declare component to test
COMPONENT datapath IS
PORT (
data_in : IN std_logic_vector(15 DOWNTO 0);
PC_in : IN std_lo... | 25.746888 | 75 | 0.495729 |
364fccc79c2bc93770633ee4e925a395e82ebaf0 | 4,550 | vhd | VHDL | UART_Controller/UART_TX.vhd | MohammadNiknam17/UART_Receiver_Transmitter_Controller_VHDL-FPGA | af072affa34e0bcf84737936a0b24e5f2fe18c61 | [
"MIT"
] | 1 | 2022-02-22T08:30:27.000Z | 2022-02-22T08:30:27.000Z | UART_Controller/UART_TX.vhd | MohammadNiknam17/UART_Controller | af072affa34e0bcf84737936a0b24e5f2fe18c61 | [
"MIT"
] | null | null | null | UART_Controller/UART_TX.vhd | MohammadNiknam17/UART_Controller | af072affa34e0bcf84737936a0b24e5f2fe18c61 | [
"MIT"
] | 1 | 2021-09-19T21:12:03.000Z | 2021-09-19T21:12:03.000Z | -- Engineer: Mohammad Niknam
-- Project Name: UART_Controller
-- Module Name: UART_TX - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_TX is
Generic(CLK_PULSE_NUM : integer := 868); --868 for freq=100Mhz / BUADRATE 115200
port ( CLK : in std_logic;
n... | 27.245509 | 116 | 0.476264 |
6a457db6d53861e4525b71c6987ad22cbfdf87d4 | 1,976 | vhd | VHDL | ADL_PROJECT_FINAL/inv_CU_process.vhd | fiendwbc/Implementation-of-AES-encryption-algorithm | 8f40d8438116127a0f3908e51b8f3633b93447e9 | [
"MIT"
] | 1 | 2021-05-17T00:36:30.000Z | 2021-05-17T00:36:30.000Z | ADL_PROJECT_FINAL/inv_CU_process.vhd | fiendwbc/Implementation-of-AES-encryption-algorithm | 8f40d8438116127a0f3908e51b8f3633b93447e9 | [
"MIT"
] | null | null | null | ADL_PROJECT_FINAL/inv_CU_process.vhd | fiendwbc/Implementation-of-AES-encryption-algorithm | 8f40d8438116127a0f3908e51b8f3633b93447e9 | [
"MIT"
] | null | null | null | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE work.ALL;
ENTITY inv_CU_process IS
PORT(START: IN STD_LOGIC := '0';
CLK: IN STD_LOGIC := '0';
round_num: IN INTEGER := 1;
CNT_CLR: OUT STD_LOGIC; -- to reset initial number
INIT_ROUND: OUT INTEGER; -- to init round number
R_RDY: O... | 22.202247 | 60 | 0.493421 |
76e251510daee5bc2683152cc083ec8db9099001 | 13,241 | vhd | VHDL | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/shift_logic_bit.vhd | mkotormus/G3_OrchestraConductorDemo | 1ac61ed0e58136c13e2473d1542aa48c632b214d | [
"Apache-2.0"
] | null | null | null | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/shift_logic_bit.vhd | mkotormus/G3_OrchestraConductorDemo | 1ac61ed0e58136c13e2473d1542aa48c632b214d | [
"Apache-2.0"
] | null | null | null | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/shift_logic_bit.vhd | mkotormus/G3_OrchestraConductorDemo | 1ac61ed0e58136c13e2473d1542aa48c632b214d | [
"Apache-2.0"
] | null | null | null | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | 70.058201 | 109 | 0.933691 |
27755e2526a1ff38030ebb9ac13c92b06fa317d5 | 226,783 | vhd | VHDL | PyTorch_Installation/Example/Vivado_HLS_Files/backward_lite/backward_lite/solution1/impl/vhdl/backward_lite.vhd | manoharvhr/PYNQ-Torch | 2dbd8a332b38f92a91e96e9cfe27d96a3f86c225 | [
"BSD-3-Clause"
] | 45 | 2019-09-15T07:02:39.000Z | 2022-03-31T07:28:43.000Z | PyTorch_Installation/Example/Vivado_Files/Regression/Regression.srcs/sources_1/bd/custom_backward/ipshared/1937/hdl/vhdl/backward_lite.vhd | manoharvhr/PYNQ-Torch | 2dbd8a332b38f92a91e96e9cfe27d96a3f86c225 | [
"BSD-3-Clause"
] | 5 | 2020-01-06T07:50:44.000Z | 2022-01-14T21:36:38.000Z | PyTorch_Installation/Example/Vivado_HLS_Files/backward_lite/backward_lite/solution1/syn/vhdl/backward_lite.vhd | manoharvhr/PYNQ-Torch | 2dbd8a332b38f92a91e96e9cfe27d96a3f86c225 | [
"BSD-3-Clause"
] | 6 | 2020-05-15T03:41:56.000Z | 2021-03-30T05:08:11.000Z | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... | 52.887826 | 2,706 | 0.701296 |
8cb773ea0dd132368eca721d857eda8f64a9f8e3 | 5,189 | vhd | VHDL | source/bench/can_bfm/can_bfm_tb.vhd | svnesbo/canola | ba09767b6ea7f2c8dce80e8f9f0ecd71def23ab1 | [
"MIT"
] | 1 | 2020-10-01T13:25:07.000Z | 2020-10-01T13:25:07.000Z | source/bench/can_bfm/can_bfm_tb.vhd | svnesbo/canola | ba09767b6ea7f2c8dce80e8f9f0ecd71def23ab1 | [
"MIT"
] | null | null | null | source/bench/can_bfm/can_bfm_tb.vhd | svnesbo/canola | ba09767b6ea7f2c8dce80e8f9f0ecd71def23ab1 | [
"MIT"
] | null | null | null | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.can_bfm_pkg.all;
entity can_bfm_tb is
end entity can_bfm_tb;
architecture tb of can_bfm_tb is
signal clk : std_logic := '0';
signal can_bus_signal : std_logic;
signal can_tx1 ... | 28.510989 | 130 | 0.572557 |
a5ec75fd2f3f83ceb6775129f93642cfec760f43 | 4,624 | vhd | VHDL | rtl/soc/vgahdmi/vga2lcd.vhd | va1ery/f32c | 1fa0e7622d8b95548850f6cab6e5fd9792cbad53 | [
"BSD-2-Clause"
] | 1 | 2021-03-04T07:00:32.000Z | 2021-03-04T07:00:32.000Z | rtl/soc/vgahdmi/vga2lcd.vhd | totocmc/f32c | 1fa0e7622d8b95548850f6cab6e5fd9792cbad53 | [
"BSD-2-Clause"
] | null | null | null | rtl/soc/vgahdmi/vga2lcd.vhd | totocmc/f32c | 1fa0e7622d8b95548850f6cab6e5fd9792cbad53 | [
"BSD-2-Clause"
] | null | null | null | -- (c)2016 EMARD
-- LICENSE=BSD
-- takes VGA input and prepares output for LCD LVDS output drivers
-- clk_pixel = 36 MHz for 1280x768
-- clk_shift = 7x clk_pixel = 252 MHz
-- currently only SDR mode supported (no DDR) -- use only bit 0 from output
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.AL... | 36.992 | 114 | 0.722318 |
5d2e7b0ee284c26cd59a4bb7b275dcdf515b5dd3 | 241,527 | vhd | VHDL | PyTorch_Installation/Example/Vivado_Files/Regression/Regression.srcs/sources_1/bd/custom_backward/synth/custom_backward.vhd | manoharvhr/PYNQ-Torch | 2dbd8a332b38f92a91e96e9cfe27d96a3f86c225 | [
"BSD-3-Clause"
] | 45 | 2019-09-15T07:02:39.000Z | 2022-03-31T07:28:43.000Z | PyTorch_Installation/Example/Vivado_Files/Regression/Regression.srcs/sources_1/bd/custom_backward/sim/custom_backward.vhd | manoharvhr/PYNQ-Torch | 2dbd8a332b38f92a91e96e9cfe27d96a3f86c225 | [
"BSD-3-Clause"
] | 5 | 2020-01-06T07:50:44.000Z | 2022-01-14T21:36:38.000Z | PyTorch_Installation/Example/Vivado_Files/Regression/Regression.srcs/sources_1/bd/custom_backward/synth/custom_backward.vhd | manoharvhr/PYNQ-Torch | 2dbd8a332b38f92a91e96e9cfe27d96a3f86c225 | [
"BSD-3-Clause"
] | 6 | 2020-05-15T03:41:56.000Z | 2021-03-30T05:08:11.000Z | --Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
--Date : Tue Jan 29 21:54:23 2019
--Host : ManoharVohra-PC running 64-bit major rele... | 58.923396 | 422 | 0.768018 |
1f5888a9ab579613ae617113de6edc6b6cbe9d12 | 182,312 | vhd | VHDL | Acceleration/memcached/hls/memcachedPipeline_prj/solution1/syn/vhdl/demux.vhd | pratik0509/HLSx_Xilinx_edit | 14bdbcdb3107aa225e46a0bfe7d4a2a426e9e1ca | [
"BSD-3-Clause"
] | null | null | null | Acceleration/memcached/hls/memcachedPipeline_prj/solution1/syn/vhdl/demux.vhd | pratik0509/HLSx_Xilinx_edit | 14bdbcdb3107aa225e46a0bfe7d4a2a426e9e1ca | [
"BSD-3-Clause"
] | null | null | null | Acceleration/memcached/hls/memcachedPipeline_prj/solution1/syn/vhdl/demux.vhd | pratik0509/HLSx_Xilinx_edit | 14bdbcdb3107aa225e46a0bfe7d4a2a426e9e1ca | [
"BSD-3-Clause"
] | 1 | 2018-11-13T17:59:49.000Z | 2018-11-13T17:59:49.000Z | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... | 186.032653 | 8,381 | 0.81292 |
2847e61814455605399b1eac44a98c9f9030a18b | 81,515 | vhd | VHDL | final_piles/1_final_1209.vhd | lucamed/fpga_soul | cdd82ad10c43b306e7a5b9f9670c9c3117cd2389 | [
"MIT"
] | null | null | null | final_piles/1_final_1209.vhd | lucamed/fpga_soul | cdd82ad10c43b306e7a5b9f9670c9c3117cd2389 | [
"MIT"
] | null | null | null | final_piles/1_final_1209.vhd | lucamed/fpga_soul | cdd82ad10c43b306e7a5b9f9670c9c3117cd2389 | [
"MIT"
] | null | null | null | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity project is
Port ( FPGA_RSTB : in STD_LOGIC;
CLK : in STD_LOGIC;
LCD_A : out STD_LOGIC_VECTOR (1 downto 0);
LCD_EN : out STD_LOGIC;
LCD_D : out STD_LOGIC_VECTOR (7 downto 0);
... | 37.409362 | 132 | 0.437331 |
bb4bbedd2383b087031860b99a8e346497c42403 | 11,913 | vhd | VHDL | firmware/targets/Kcu105TenGigE/hdl/EthPortMapping.vhd | slaclab/smurf-pcie | 489c6d2e766dc784f60599aff571116fb7700a81 | [
"BSD-3-Clause-LBNL"
] | 2 | 2019-01-31T17:13:55.000Z | 2020-01-04T00:44:01.000Z | firmware/targets/Kcu105TenGigE/hdl/EthPortMapping.vhd | slaclab/smurf-pcie | 489c6d2e766dc784f60599aff571116fb7700a81 | [
"BSD-3-Clause-LBNL"
] | 3 | 2019-01-16T20:40:23.000Z | 2019-10-28T18:44:26.000Z | firmware/targets/Kcu105TenGigE/hdl/EthPortMapping.vhd | slaclab/smurf-pcie | 489c6d2e766dc784f60599aff571116fb7700a81 | [
"BSD-3-Clause-LBNL"
] | 1 | 2020-12-12T23:35:49.000Z | 2020-12-12T23:35:49.000Z | -------------------------------------------------------------------------------
-- File : EthPortMapping.vhd
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------... | 40.111111 | 134 | 0.559137 |
90662002f04111be56ff00c733757e94c0620209 | 987 | vhd | VHDL | Xilinx_Proj/Blinking_LED_DEEDS/Blinking_LED_DEEDS.srcs/sources_1/new/Components.vhd | abaelen/FPGA-DEEDS-Training-Material | 165f31d070376032a4ca7cb0b055847044cf5d65 | [
"MIT"
] | 1 | 2021-03-19T13:28:35.000Z | 2021-03-19T13:28:35.000Z | Xilinx_Proj/Blinking_LED_DEEDS/Blinking_LED_DEEDS.srcs/sources_1/new/Components.vhd | abaelen/FPGA-DEEDS-Training-Material | 165f31d070376032a4ca7cb0b055847044cf5d65 | [
"MIT"
] | null | null | null | Xilinx_Proj/Blinking_LED_DEEDS/Blinking_LED_DEEDS.srcs/sources_1/new/Components.vhd | abaelen/FPGA-DEEDS-Training-Material | 165f31d070376032a4ca7cb0b055847044cf5d65 | [
"MIT"
] | 1 | 2021-03-19T13:28:36.000Z | 2021-03-19T13:28:36.000Z | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.01.2021 18:52:01
-- Design Name:
-- Module Name: Components - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... | 23.5 | 82 | 0.591692 |
ab96f1a0dcb50b78e66df82a53591491fc697283 | 3,933 | vhd | VHDL | Vivado_HLS_Tutorial/RTL_Verification/lab2/duc_prj/solution1/syn/vhdl/duc_c.vhd | williambong/Vivado | 68efafbc44b65c0bb047dbafc0ff7f1b56ee36bb | [
"MIT"
] | null | null | null | Vivado_HLS_Tutorial/RTL_Verification/lab2/duc_prj/solution1/syn/vhdl/duc_c.vhd | williambong/Vivado | 68efafbc44b65c0bb047dbafc0ff7f1b56ee36bb | [
"MIT"
] | null | null | null | Vivado_HLS_Tutorial/RTL_Verification/lab2/duc_prj/solution1/syn/vhdl/duc_c.vhd | williambong/Vivado | 68efafbc44b65c0bb047dbafc0ff7f1b56ee36bb | [
"MIT"
] | null | null | null | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.2
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.st... | 30.968504 | 83 | 0.604119 |
6abbe367dba2b36f0a61fe617a38fc9e06a1a1f0 | 2,998 | vhd | VHDL | submit/direct/tb_trafo.vhd | maanjum95/VHDL_System_Design_Lab | 4b452d37c4f6eba9fd31e2cf80bd4202fc5f4940 | [
"MIT"
] | 1 | 2021-11-19T19:58:32.000Z | 2021-11-19T19:58:32.000Z | submit/direct/tb_trafo.vhd | maanjum95/VHDL_System_Design_Lab | 4b452d37c4f6eba9fd31e2cf80bd4202fc5f4940 | [
"MIT"
] | null | null | null | submit/direct/tb_trafo.vhd | maanjum95/VHDL_System_Design_Lab | 4b452d37c4f6eba9fd31e2cf80bd4202fc5f4940 | [
"MIT"
] | 1 | 2021-11-26T23:41:12.000Z | 2021-11-26T23:41:12.000Z | --------------------------------------------------------------------------------
-- Engineer: Muhammad Anjum
--
-- Create Date: 18:00:49 11/23/2019
-- Module Name: /nas/ei/share/TUEIEDA/LabHDL/2019w/ge46bod/submit/direct/tb_trafo.vhd
-- Project Name: IDEA Direct
--
-- VHDL Test Bench Created by ISE for modul... | 24.983333 | 87 | 0.542695 |
fd0e66e949975cfa6ef4dce3f5dfee6a85387554 | 4,608 | vhd | VHDL | hdl/quip/oc_simple_fm_receiver/adder_11bit.vhd | ispras/hdl-benchmarks | 8524809bcb0ca7f2332617ad7023d97d5779e3ee | [
"Apache-2.0"
] | 3 | 2019-10-09T12:33:36.000Z | 2019-10-21T15:56:44.000Z | hdl/quip/oc_simple_fm_receiver/adder_11bit.vhd | ispras/hdl-benchmarks | 8524809bcb0ca7f2332617ad7023d97d5779e3ee | [
"Apache-2.0"
] | 5 | 2019-10-04T12:05:17.000Z | 2022-03-02T13:56:12.000Z | hdl/quip/oc_simple_fm_receiver/adder_11bit.vhd | ispras/hdl-benchmarks | 8524809bcb0ca7f2332617ad7023d97d5779e3ee | [
"Apache-2.0"
] | null | null | null | -- $Id: adder_11bit.vhdl,v 1.1.1.1 2005/01/04 02:05:58 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Adder 11 bit
-- Project : FM Receiver
-------------------------------------------------------------------------------
-- File : adder_... | 27.266272 | 80 | 0.479167 |
81722b7e47f614ea2f9b4bb56f2b4886ed4621cc | 25,754 | vho | VHDL | Lab 2/Quartus Project/simulation/modelsim/g30_lab2.vho | seanstappas/breakout-vhdl | ea958c7343e587adce7d6b1807b77d8886d93373 | [
"MIT"
] | null | null | null | Lab 2/Quartus Project/simulation/modelsim/g30_lab2.vho | seanstappas/breakout-vhdl | ea958c7343e587adce7d6b1807b77d8886d93373 | [
"MIT"
] | null | null | null | Lab 2/Quartus Project/simulation/modelsim/g30_lab2.vho | seanstappas/breakout-vhdl | ea958c7343e587adce7d6b1807b77d8886d93373 | [
"MIT"
] | 1 | 2019-11-14T19:05:02.000Z | 2019-11-14T19:05:02.000Z | -- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... | 29.602299 | 128 | 0.686185 |
3532404e2f19d8858c78116e2e90fafdd9a5f66f | 203 | vhd | VHDL | test/vhdl/reports.vhd | azarmadr/moore | fa83bfe6ec4ef5e31ae6c01b89e228a7db827b6b | [
"Apache-2.0",
"MIT"
] | null | null | null | test/vhdl/reports.vhd | azarmadr/moore | fa83bfe6ec4ef5e31ae6c01b89e228a7db827b6b | [
"Apache-2.0",
"MIT"
] | null | null | null | test/vhdl/reports.vhd | azarmadr/moore | fa83bfe6ec4ef5e31ae6c01b89e228a7db827b6b | [
"Apache-2.0",
"MIT"
] | null | null | null | -- Codegen test
entity e0 is
end entity e0;
architecture demo of e0 is
begin
process is
begin
report "message";
wait;
end process;
report "message"; -- error
end architecture demo;
| 14.5 | 28 | 0.674877 |
c9b37a9132648f845639340d3195a9472936ac19 | 1,152 | vhd | VHDL | Multiplier/Project/VHDL/romMemOpB.vhd | beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA | 378be837fbb92a24fb17150671091d9cdefc7e72 | [
"MIT"
] | 2 | 2020-01-31T18:01:04.000Z | 2022-03-22T20:08:55.000Z | Multiplier/Project/VHDL/romMemOpB.vhd | beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA | 378be837fbb92a24fb17150671091d9cdefc7e72 | [
"MIT"
] | null | null | null | Multiplier/Project/VHDL/romMemOpB.vhd | beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA | 378be837fbb92a24fb17150671091d9cdefc7e72 | [
"MIT"
] | null | null | null | -------------------------------------------------------------------------------
-- Description: Implementation of a 32 x 8 ROM
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity romMemOpB is
port (
addr : ... | 29.538462 | 79 | 0.585938 |
3d4215159ceec1a818376dea487fe27e43a2c9e1 | 15,310 | vhd | VHDL | can_aximms/can_rx.vhd | rftafas/stdcores | 04f9fad3b91649ba1ee6bb1b9f24bf4d6254569f | [
"Apache-2.0"
] | 10 | 2021-02-28T12:06:44.000Z | 2022-02-23T23:50:55.000Z | can_aximms/can_rx.vhd | rftafas/stdcores | 04f9fad3b91649ba1ee6bb1b9f24bf4d6254569f | [
"Apache-2.0"
] | 17 | 2020-07-20T14:10:35.000Z | 2020-10-28T19:02:32.000Z | can_aximms/can_rx.vhd | rftafas/stdcores | 04f9fad3b91649ba1ee6bb1b9f24bf4d6254569f | [
"Apache-2.0"
] | 2 | 2020-05-18T10:27:04.000Z | 2020-07-20T14:44:40.000Z | ----------------------------------------------------------------------------------
--Copyright 2021 Ricardo F Tafas Jr
--Licensed under the Apache License, Version 2.0 (the "License"); you may not
--use this file except in compliance with the License. You may obtain a copy of
--the License at
-- http://www.apache.o... | 37.070218 | 95 | 0.40209 |
61fcaf9cb6e364cf44642e59a32aa7eddbadb172 | 185 | vhd | VHDL | Labs/POCP/POCP-1/src/source/OR4.vhd | VerkhovtsovPavel/BSUIR_Labs | 8fb6d304189b714a30db7f8611ec29bbca775e7f | [
"MIT"
] | 1 | 2018-11-09T18:02:47.000Z | 2018-11-09T18:02:47.000Z | Labs/POCP/POCP-1/src/source/OR4.vhd | VerkhovtsovPavel/BSUIR_Labs | 8fb6d304189b714a30db7f8611ec29bbca775e7f | [
"MIT"
] | null | null | null | Labs/POCP/POCP-1/src/source/OR4.vhd | VerkhovtsovPavel/BSUIR_Labs | 8fb6d304189b714a30db7f8611ec29bbca775e7f | [
"MIT"
] | 1 | 2020-10-07T03:07:14.000Z | 2020-10-07T03:07:14.000Z | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity OR4 is port(
A,B,C,D: in std_logic;
Z: out std_logic
);
end OR4;
architecture OR4 of OR4 is
begin
Z<=A or B or C or D;
end OR4;
| 13.214286 | 28 | 0.691892 |
794b2cfd8cda387737a61ecf9145b407e54e80c6 | 2,574 | vhd | VHDL | hdl/quip/radar20/obj_k.vhd | ispras/hdl-benchmarks | 8524809bcb0ca7f2332617ad7023d97d5779e3ee | [
"Apache-2.0"
] | 3 | 2019-10-09T12:33:36.000Z | 2019-10-21T15:56:44.000Z | hdl/quip/radar20/obj_k.vhd | ispras/hdl-benchmarks | 8524809bcb0ca7f2332617ad7023d97d5779e3ee | [
"Apache-2.0"
] | 5 | 2019-10-04T12:05:17.000Z | 2022-03-02T13:56:12.000Z | hdl/quip/radar20/obj_k.vhd | ispras/hdl-benchmarks | 8524809bcb0ca7f2332617ad7023d97d5779e3ee | [
"Apache-2.0"
] | null | null | null | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity obj_k is
port (
clock : in STD_LOGIC;
ev : in STD_LOGIC;
sp : in STD_LOGIC;
X0 : in STD_LOGIC_VECTOR(15 downto 0);
X1 :... | 31.012048 | 72 | 0.494949 |
9f54da9199dc7f9902b7bf11ab633924bbe742cd | 1,946 | vhd | VHDL | Milestone2/source/synchronize.vhd | CircuitBender/fpga_synth | 663039aa9d188c722000f02293c0b2721c7280a6 | [
"MIT"
] | 2 | 2019-03-22T10:04:18.000Z | 2019-06-13T21:47:52.000Z | Milestone4/source/synchronize.vhd | CircuitBender/fpga_synth | 663039aa9d188c722000f02293c0b2721c7280a6 | [
"MIT"
] | 1 | 2019-03-28T20:55:46.000Z | 2019-03-28T20:55:46.000Z | Milestone4/source/synchronize.vhd | CircuitBender/fpga_synth | 663039aa9d188c722000f02293c0b2721c7280a6 | [
"MIT"
] | null | null | null | -------------------------------------------------------------------------------
-- Title : synchronize
-- Project :
-------------------------------------------------------------------------------
-- File : synchronize.vhd<MS_stud>
-- Author : <Hans-Joachim@GELKE-LENOVO>
-- Company :
-- Created ... | 31.387097 | 79 | 0.36074 |
1128117f40847f4e4d99eebb4f35b89d96d365e4 | 1,079 | vhd | VHDL | ch6/ex_6.2/src/counter.vhd | LeoSf/book_circuit_design_2010 | 5dd8b5d7dfb7a88a6826208294bed272b5c41d2f | [
"MIT"
] | null | null | null | ch6/ex_6.2/src/counter.vhd | LeoSf/book_circuit_design_2010 | 5dd8b5d7dfb7a88a6826208294bed272b5c41d2f | [
"MIT"
] | null | null | null | ch6/ex_6.2/src/counter.vhd | LeoSf/book_circuit_design_2010 | 5dd8b5d7dfb7a88a6826208294bed272b5c41d2f | [
"MIT"
] | null | null | null | ----------------------------------------------------------------------------------
-- Company: None
-- Engineer: Leandro D. Medus
--
-- Create Date: 18:17:00 15/05/2020 (dd/mm/yyyy)
-- Design Name: Basic counter
-- Module Name: counter - Behavioral
-- Project Name: ... | 22.020408 | 82 | 0.444856 |
5622de76e5ac4b690e5ac7d779612f3de5b80a8d | 1,535 | vhd | VHDL | Episodes/ep06_Configuration/src/envelope_generator.vhd | MJoergen/ym2151 | 47c95a53e5d881fea0fe59a075f07697c39a275c | [
"MIT"
] | 4 | 2020-04-03T09:02:49.000Z | 2021-03-17T20:01:37.000Z | Episodes/ep05_Phase_Envelope_Generator/src/envelope_generator.vhd | MJoergen/ym2151 | 47c95a53e5d881fea0fe59a075f07697c39a275c | [
"MIT"
] | null | null | null | Episodes/ep05_Phase_Envelope_Generator/src/envelope_generator.vhd | MJoergen/ym2151 | 47c95a53e5d881fea0fe59a075f07697c39a275c | [
"MIT"
] | 1 | 2020-04-11T16:35:25.000Z | 2020-04-11T16:35:25.000Z | -- Author: Michael Jørgensen
-- License: Public domain; do with it what you like :-)
-- Project: YM2151 implementation
--
-- Description: The Envelope Generator is currently just a stub, in that it
-- just calculates the attenuation level (to be input to the operator module)
-- from the total_level values (received fr... | 28.425926 | 80 | 0.606515 |
082e96314ac6298195e5d1517768c2dd0be36e6a | 1,254 | vhd | VHDL | video_clock_for_DE/synthesis/video_clock_for_DE.vhd | TheeYo/oscilloscope_vhdl | f24f54331a43e7c5b2509130680c5dab972ca662 | [
"MIT"
] | null | null | null | video_clock_for_DE/synthesis/video_clock_for_DE.vhd | TheeYo/oscilloscope_vhdl | f24f54331a43e7c5b2509130680c5dab972ca662 | [
"MIT"
] | null | null | null | video_clock_for_DE/synthesis/video_clock_for_DE.vhd | TheeYo/oscilloscope_vhdl | f24f54331a43e7c5b2509130680c5dab972ca662 | [
"MIT"
] | null | null | null | -- video_clock_for_DE.vhd
-- Generated using ACDS version 17.1 593
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_clock_for_DE is
port (
ref_clk_clk : in std_logic := '0'; -- ref_clk.clk
ref_reset_reset : in std_logic := '0'; -- ref_reset.reset
r... | 32.153846 | 66 | 0.6563 |
a7b33d9a3a87f509b931a112f3586ea413ddb202 | 5,274 | vhd | VHDL | DPC_VHDL/boxplus1.vhd | paclopes/DPC | abaca46a4d7571d8e5da95f8b5f1da7be62f4651 | [
"MIT"
] | 2 | 2021-05-17T20:21:57.000Z | 2021-06-14T13:17:12.000Z | DPC_VHDL/boxplus1.vhd | paclopes/DPC | abaca46a4d7571d8e5da95f8b5f1da7be62f4651 | [
"MIT"
] | null | null | null | DPC_VHDL/boxplus1.vhd | paclopes/DPC | abaca46a4d7571d8e5da95f8b5f1da7be62f4651 | [
"MIT"
] | 2 | 2019-03-24T10:56:48.000Z | 2021-06-14T13:17:13.000Z | -- boxplus1.vhd 29-8-2019
--
-- Reads the values from the interleaver output memory and calculates the output to feed the log-MAP.
--
-- Runs in runs of cycle_length (22) that read 9 values (at most) from the interleaver memory
-- do the box plus operation and write 3 values to the output buffer in a mixed of se... | 34.927152 | 115 | 0.380736 |
82a40b1ee02e49329ca73744ec24ce0393821a6b | 58,729 | vhd | VHDL | avnet/IP/onsemi_vita_cam/hdl/iserdes_clocks.vhd | alexvonduar/fpga_embedded_vision | 793ca8e7d50bc0acaedf64bd4a36893401a27de3 | [
"MIT"
] | 1 | 2021-05-12T21:10:06.000Z | 2021-05-12T21:10:06.000Z | avnet/IP/onsemi_vita_cam/hdl/iserdes_clocks.vhd | alexvonduar/fpga_embedded_vision | 793ca8e7d50bc0acaedf64bd4a36893401a27de3 | [
"MIT"
] | null | null | null | avnet/IP/onsemi_vita_cam/hdl/iserdes_clocks.vhd | alexvonduar/fpga_embedded_vision | 793ca8e7d50bc0acaedf64bd4a36893401a27de3 | [
"MIT"
] | 1 | 2020-02-29T12:44:41.000Z | 2020-02-29T12:44:41.000Z | -- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must trea... | 39.336236 | 216 | 0.509237 |
57b1212dba6310ac7a8bdd207fc1710d9cbbe97c | 888 | vhi | VHDL | GCD-files/lab5-gcd/lab5_gcd.vhi | shreshthtuli/GCD-calculator-VHDL | c0fe4f59ec44aa3a69817959cd840eecf9be40d4 | [
"MIT"
] | null | null | null | GCD-files/lab5-gcd/lab5_gcd.vhi | shreshthtuli/GCD-calculator-VHDL | c0fe4f59ec44aa3a69817959cd840eecf9be40d4 | [
"MIT"
] | null | null | null | GCD-files/lab5-gcd/lab5_gcd.vhi | shreshthtuli/GCD-calculator-VHDL | c0fe4f59ec44aa3a69817959cd840eecf9be40d4 | [
"MIT"
] | null | null | null |
-- VHDL Instantiation Created from source file lab5_gcd.vhd -- 15:15:01 08/26/2017
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste... | 23.368421 | 82 | 0.676802 |
43e8aed8e650ccd36d7d877fae4dc41408d8789d | 16,774 | vhd | VHDL | AttackFiles/Attacks/memAttack/lib/techmap/maps/grfpw_net.vhd | impedimentToProgress/UCI-BlueChip | 53e5d48b79079eaf60d42f7cb65bb795743d19fc | [
"MIT"
] | null | null | null | AttackFiles/Attacks/memAttack/lib/techmap/maps/grfpw_net.vhd | impedimentToProgress/UCI-BlueChip | 53e5d48b79079eaf60d42f7cb65bb795743d19fc | [
"MIT"
] | null | null | null | AttackFiles/Attacks/memAttack/lib/techmap/maps/grfpw_net.vhd | impedimentToProgress/UCI-BlueChip | 53e5d48b79079eaf60d42f7cb65bb795743d19fc | [
"MIT"
] | 3 | 2016-06-13T13:20:56.000Z | 2019-12-05T02:31:23.000Z | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... | 42.573604 | 81 | 0.677358 |
b88776ad590a1fa61c9486511db32048d8c846b1 | 4,817 | vho | VHDL | exercicios/aula_6/exercicio_3/simulation/qsim/circuito.vho | itepifanio/vhdl | d5235cf6ccf1e2ab2c6155863e9e68b38f2c1baf | [
"MIT"
] | 1 | 2020-06-16T05:07:08.000Z | 2020-06-16T05:07:08.000Z | exercicios/aula_6/exercicio_3/simulation/qsim/circuito.vho | itepifanio/vhdl | d5235cf6ccf1e2ab2c6155863e9e68b38f2c1baf | [
"MIT"
] | null | null | null | exercicios/aula_6/exercicio_3/simulation/qsim/circuito.vho | itepifanio/vhdl | d5235cf6ccf1e2ab2c6155863e9e68b38f2c1baf | [
"MIT"
] | null | null | null | -- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- a... | 26.61326 | 93 | 0.714553 |
c049e7c5d0d4092778eb3dfef7e1420497bba831 | 2,823 | vhd | VHDL | vunit/vhdl/verification_components/src/stream_slave_pkg-body.vhd | olafvandenberg/vunit | 4f78fc4fa0f10b4cf50a6d377793d374ae19df64 | [
"Artistic-2.0",
"Apache-2.0"
] | null | null | null | vunit/vhdl/verification_components/src/stream_slave_pkg-body.vhd | olafvandenberg/vunit | 4f78fc4fa0f10b4cf50a6d377793d374ae19df64 | [
"Artistic-2.0",
"Apache-2.0"
] | 1 | 2021-09-05T19:34:01.000Z | 2021-09-05T19:34:01.000Z | vunit/vhdl/verification_components/src/stream_slave_pkg-body.vhd | olafvandenberg/vunit | 4f78fc4fa0f10b4cf50a6d377793d374ae19df64 | [
"Artistic-2.0",
"Apache-2.0"
] | null | null | null | -- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2014-2022, Lars Asplund lars.anders.asplund@gmail.com
package body stream_slave_pkg is
impure f... | 36.662338 | 81 | 0.629118 |
f1ffe28129ae11de3534b274d936a5ecc28529be | 2,209 | vhd | VHDL | ALEX/Vivado/src/dig_in/hdl/MAX7301_in_TB.vhd | KTH-EPE/HVDC_IED | fb7526bfae7739758255d39a0baff32b060b1d1f | [
"MIT"
] | 1 | 2022-02-08T03:02:25.000Z | 2022-02-08T03:02:25.000Z | ALEX/Vivado/src/dig_in/hdl/MAX7301_in_TB.vhd | KTH-EPE/HVDC_IED | fb7526bfae7739758255d39a0baff32b060b1d1f | [
"MIT"
] | null | null | null | ALEX/Vivado/src/dig_in/hdl/MAX7301_in_TB.vhd | KTH-EPE/HVDC_IED | fb7526bfae7739758255d39a0baff32b060b1d1f | [
"MIT"
] | 1 | 2020-02-20T20:56:57.000Z | 2020-02-20T20:56:57.000Z | -- ---------------------------------------------------------------------------
--
-- Project: Alex
--
-- Filename: MAX7301_in_TB.vhd
--
-- Description: VHDL testbench for MAX7301.
--
-- © Copyright 2019 KTH. All rights reserved.
--
-- ----------------------------------------------------------... | 24.274725 | 86 | 0.564056 |
0408dc46af68b69f0078e7068c03a81ab9fc1332 | 320 | vhd | VHDL | Lab1/Kamal_Faheem_Lab1_Code/Lab1_8to3Encoder/simulation/qsim/work/kamal_lab1_8to3@encoder_vlg_check_tst/_primary.vhd | FaheemAKamal/CS342Projects | adf4d5e378f68c40862632ee5b7eb9c4a021f5ed | [
"MIT"
] | null | null | null | Lab1/Kamal_Faheem_Lab1_Code/Lab1_8to3Encoder/simulation/qsim/work/kamal_lab1_8to3@encoder_vlg_check_tst/_primary.vhd | FaheemAKamal/CS342Projects | adf4d5e378f68c40862632ee5b7eb9c4a021f5ed | [
"MIT"
] | null | null | null | Lab1/Kamal_Faheem_Lab1_Code/Lab1_8to3Encoder/simulation/qsim/work/kamal_lab1_8to3@encoder_vlg_check_tst/_primary.vhd | FaheemAKamal/CS342Projects | adf4d5e378f68c40862632ee5b7eb9c4a021f5ed | [
"MIT"
] | null | null | null | library verilog;
use verilog.vl_types.all;
entity kamal_lab1_8to3Encoder_vlg_check_tst is
port(
kamal_outputY1 : in vl_logic;
kamal_outputY2 : in vl_logic;
kamal_outputY3 : in vl_logic;
sampler_rx : in vl_logic
);
end kamal_lab1_8to3Encoder_vlg_check_tst;
| 29.090909 | 46 | 0.66875 |
e4594bc6abb71d8ff5eb898f1e4a1a90b0987ba6 | 16,166 | vhd | VHDL | rtl/xilinx/zybo/top/zybo_xram_acram_emu.vhd | va1ery/f32c | 1fa0e7622d8b95548850f6cab6e5fd9792cbad53 | [
"BSD-2-Clause"
] | 1 | 2021-03-04T07:00:32.000Z | 2021-03-04T07:00:32.000Z | rtl/xilinx/zybo/top/zybo_xram_acram_emu.vhd | totocmc/f32c | 1fa0e7622d8b95548850f6cab6e5fd9792cbad53 | [
"BSD-2-Clause"
] | null | null | null | rtl/xilinx/zybo/top/zybo_xram_acram_emu.vhd | totocmc/f32c | 1fa0e7622d8b95548850f6cab6e5fd9792cbad53 | [
"BSD-2-Clause"
] | null | null | null | --
-- Copyright (c) 2015 Emanuel Stiebler
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of con... | 41.345269 | 144 | 0.671409 |
b555a8c73d564a616b866136bad688f77ec3f810 | 30,205 | vhd | VHDL | src/sigmoid.vhd | dicearr/neuron-vhdl | 02993633318507575f055a75736686f3aed977a1 | [
"MIT"
] | 17 | 2017-08-08T14:13:28.000Z | 2022-02-26T14:35:37.000Z | src/sigmoid.vhd | dicearr/neuron-vhdl | 02993633318507575f055a75736686f3aed977a1 | [
"MIT"
] | null | null | null | src/sigmoid.vhd | dicearr/neuron-vhdl | 02993633318507575f055a75736686f3aed977a1 | [
"MIT"
] | 5 | 2019-05-29T17:17:33.000Z | 2021-02-09T08:51:32.000Z | ----------------------------------------------------------------------------------
-- Engineer: Diego Ceresuela, Oscar Clemente.
--
-- Create Date: 13.04.2016 08:23:25
-- Module Name: sigmoid - Behavioral
-- Description: Implements a ROM containing the aproximation of the sigmoid function.
--
-- Dependencies: ... | 324.784946 | 27,323 | 0.613408 |
cd6dcaae65d7cb987100eda52bd49598d1e07fab | 2,379 | vhd | VHDL | Episodes/ep05_Phase_Envelope_Generator/src/configurator.vhd | MJoergen/ym2151 | 47c95a53e5d881fea0fe59a075f07697c39a275c | [
"MIT"
] | 4 | 2020-04-03T09:02:49.000Z | 2021-03-17T20:01:37.000Z | Episodes/ep05_Phase_Envelope_Generator/src/configurator.vhd | MJoergen/ym2151 | 47c95a53e5d881fea0fe59a075f07697c39a275c | [
"MIT"
] | null | null | null | Episodes/ep05_Phase_Envelope_Generator/src/configurator.vhd | MJoergen/ym2151 | 47c95a53e5d881fea0fe59a075f07697c39a275c | [
"MIT"
] | 1 | 2020-04-11T16:35:25.000Z | 2020-04-11T16:35:25.000Z | -- Author: Michael Jørgensen
-- License: Public domain; do with it what you like :-)
-- Project: YM2151 implementation
--
-- Description: This module stores the configuration for each of the 32 slots.
-- At each clock cycle it outputs the slot number and the corresponding
-- configuration for that slot.
library ieee;... | 30.5 | 80 | 0.531316 |
f915b4c86d19051ea3cc1c00c6d0fafcdc934cc2 | 4,150 | vhd | VHDL | Design for (1,5)-iPUF/Generate_Pos.vhd | emsec/TI-PUF | 46c0ed411c3baee8e16e480bb83a95bc914baefb | [
"BSD-3-Clause"
] | 3 | 2020-01-08T16:54:33.000Z | 2022-03-30T22:23:50.000Z | Design for (1,5)-iPUF/Generate_Pos.vhd | emsec/TI-PUF | 46c0ed411c3baee8e16e480bb83a95bc914baefb | [
"BSD-3-Clause"
] | null | null | null | Design for (1,5)-iPUF/Generate_Pos.vhd | emsec/TI-PUF | 46c0ed411c3baee8e16e480bb83a95bc914baefb | [
"BSD-3-Clause"
] | 1 | 2020-08-11T20:16:54.000Z | 2020-08-11T20:16:54.000Z | ----------------------------------------------------------------------------------
-- COMPANY: Ruhr University Bochum, Embedded Security
-- AUTHOR: Anita Aghaie, Amir Moradi
-- TOIPC: TI-PUF: Toward Side-Channel Resistant Physical Unclonable Functions
----------------------------------------------------... | 40.291262 | 91 | 0.699036 |
1debc363a84e26c2ffc0b0c5660e4741fafafa01 | 77,610 | vhd | VHDL | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/fifo_generator_v11_0/ramfifo/fifo_generator_ramfifo.vhd | tdaede/daala_zynq | c9d0052ed018c43f92c31f9a59563888d4086276 | [
"BSD-2-Clause"
] | 1 | 2015-11-14T16:35:24.000Z | 2015-11-14T16:35:24.000Z | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/fifo_generator_ramfifo.vhd | tdaede/daala_zynq | c9d0052ed018c43f92c31f9a59563888d4086276 | [
"BSD-2-Clause"
] | null | null | null | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/fifo_generator_ramfifo.vhd | tdaede/daala_zynq | c9d0052ed018c43f92c31f9a59563888d4086276 | [
"BSD-2-Clause"
] | 3 | 2015-04-28T13:28:10.000Z | 2019-10-09T16:27:46.000Z | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | 75.717073 | 109 | 0.95221 |
e9b8173b2253482ce5d5b36e9bbb606d0b2ea3a1 | 2,894 | vhd | VHDL | greth_library/techmap/pll/SysPLL_tech.vhd | lowRISC/greth-library | 2ccd6e2a203813afe035d34d35c127781b54e3d7 | [
"BSD-2-Clause"
] | 1 | 2022-03-16T23:01:21.000Z | 2022-03-16T23:01:21.000Z | greth_library/techmap/pll/SysPLL_tech.vhd | lowRISC/greth-library | 2ccd6e2a203813afe035d34d35c127781b54e3d7 | [
"BSD-2-Clause"
] | null | null | null | greth_library/techmap/pll/SysPLL_tech.vhd | lowRISC/greth-library | 2ccd6e2a203813afe035d34d35c127781b54e3d7 | [
"BSD-2-Clause"
] | null | null | null | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Implementation of the SysPLL_tech entity
--! @details This module file be included in all proj... | 30.787234 | 102 | 0.622668 |
6f2a04a64a58c59dba9ac17d84339557dcf10d11 | 1,997 | vhd | VHDL | ALU/ALUDesign/src/TestBench/alu_TB.vhd | Nikronic/CAD_2018 | 1b7f97c3f1d9eece7720bdec8f540ceb2e4361fe | [
"MIT"
] | 5 | 2018-07-03T10:00:44.000Z | 2021-06-24T22:21:12.000Z | ALU/ALUDesign/src/TestBench/alu_TB.vhd | Nikronic/CAD_2018 | 1b7f97c3f1d9eece7720bdec8f540ceb2e4361fe | [
"MIT"
] | null | null | null | ALU/ALUDesign/src/TestBench/alu_TB.vhd | Nikronic/CAD_2018 | 1b7f97c3f1d9eece7720bdec8f540ceb2e4361fe | [
"MIT"
] | null | null | null | library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
-- Add your library and packages declaration here ...
entity alu_tb is
end alu_tb;
architecture TB_ARCHITECTURE of alu_tb is
-- Component declaration of the tested unit
component alu
port(
Clk : in STD_LOGIC;... | 19.772277 | 83 | 0.677016 |
56243c228122f6cf545ea3107ec4377ea1edabe5 | 48,883 | vhd | VHDL | tce/hdb/altera_jtag_uart_vhdl/jtag_uart_r1k_w1k.vhd | kanishkan/tce | 430e764b4d43f46bd1dc754aeb1d5632fc742110 | [
"MIT"
] | 74 | 2015-10-22T15:34:10.000Z | 2022-03-25T07:57:23.000Z | tce/hdb/altera_jtag_uart_vhdl/jtag_uart_r1k_w1k.vhd | kanishkan/tce | 430e764b4d43f46bd1dc754aeb1d5632fc742110 | [
"MIT"
] | 79 | 2015-11-19T09:23:08.000Z | 2022-01-12T14:15:16.000Z | tce/hdb/altera_jtag_uart_vhdl/jtag_uart_r1k_w1k.vhd | kanishkan/tce | 430e764b4d43f46bd1dc754aeb1d5632fc742110 | [
"MIT"
] | 38 | 2015-11-17T10:12:23.000Z | 2022-03-25T07:57:24.000Z | --Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated do... | 35.2183 | 944 | 0.589387 |
72243e287b2f4b3705af1ce2fe5f991d5eded1a0 | 137 | vhd | VHDL | AD1939/Source_Files/IP/Serial2Parallel_32bits_inst.vhd | FE-OpenSpeech/Phase1System | 289c12d9ec639ce7e820bf1637dc1b50f7a09874 | [
"Unlicense",
"MIT"
] | null | null | null | AD1939/Source_Files/IP/Serial2Parallel_32bits_inst.vhd | FE-OpenSpeech/Phase1System | 289c12d9ec639ce7e820bf1637dc1b50f7a09874 | [
"Unlicense",
"MIT"
] | null | null | null | AD1939/Source_Files/IP/Serial2Parallel_32bits_inst.vhd | FE-OpenSpeech/Phase1System | 289c12d9ec639ce7e820bf1637dc1b50f7a09874 | [
"Unlicense",
"MIT"
] | null | null | null | Serial2Parallel_32bits_inst : Serial2Parallel_32bits PORT MAP (
clock => clock_sig,
shiftin => shiftin_sig,
q => q_sig
);
| 22.833333 | 64 | 0.686131 |
9741d5887e06e2835232739ff6f70d061651810f | 7,694 | vhd | VHDL | Designs/Lesson_25_Shift_register_with_clock_divide_VHDL/Lesson_25_Shift_register_with_clock_divide.vhd | abaelen/FPGA-DEEDS-Training-Material | 165f31d070376032a4ca7cb0b055847044cf5d65 | [
"MIT"
] | 1 | 2021-03-19T13:28:35.000Z | 2021-03-19T13:28:35.000Z | Designs/Lesson_25_Shift_register_with_clock_divide_VHDL/Lesson_25_Shift_register_with_clock_divide.vhd | abaelen/FPGA-DEEDS-Training-Material | 165f31d070376032a4ca7cb0b055847044cf5d65 | [
"MIT"
] | null | null | null | Designs/Lesson_25_Shift_register_with_clock_divide_VHDL/Lesson_25_Shift_register_with_clock_divide.vhd | abaelen/FPGA-DEEDS-Training-Material | 165f31d070376032a4ca7cb0b055847044cf5d65 | [
"MIT"
] | 1 | 2021-03-19T13:28:36.000Z | 2021-03-19T13:28:36.000Z | ------------------------------------------------------------
-- Deeds (Digital Electronics Education and Design Suite)
-- VHDL Code generated on (28/12/2020, 16:24:04)
-- by Deeds (Digital Circuit Simulator)(Deeds-DcS)
-- Ver. 2.30.041 (March 3, 2020)
-- Copyright (c) 2002-2020 University of Genoa, Italy
-- ... | 28.924812 | 73 | 0.537692 |
b1f1a8a18e88f9cb6a79d4e97a90b3b7d6fe6b91 | 718 | vhd | VHDL | CNN_codes/BF_ADD_MUL_DIV/FPswap_b.vhd | subhrajitmitra/CNN-Codes | d848e654465945509df90644644d2e05ee574357 | [
"MIT"
] | 1 | 2021-12-13T07:19:00.000Z | 2021-12-13T07:19:00.000Z | CNN_codes/BF_ADD_MUL_DIV/FPswap_b.vhd | subhrajitmitra/CNN-Codes | d848e654465945509df90644644d2e05ee574357 | [
"MIT"
] | null | null | null | CNN_codes/BF_ADD_MUL_DIV/FPswap_b.vhd | subhrajitmitra/CNN-Codes | d848e654465945509df90644644d2e05ee574357 | [
"MIT"
] | null | null | null | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY FPswap_b IS
GENERIC(
width : integer := 13
);
PORT(
A_in : IN std_logic_vector (width-1 DOWNTO 0);
B_in : IN std_logic_vector (width-1 DOWNTO 0);
swap_AB : IN std_logic;
A_out :... | 17.95 | 59 | 0.615599 |
d389f9ee30413ae5f990de3ce619e8eaebbf3b29 | 3,799 | vhd | VHDL | Neander-MultMatriz-SetBRAM/button_driver_longpress.vhd | gabriel-lando/SisDig-TrabalhoFinal | e6dcc1eb31b54bd2378a34570507796ac7649c3e | [
"MIT"
] | null | null | null | Neander-MultMatriz-SetBRAM/button_driver_longpress.vhd | gabriel-lando/SisDig-TrabalhoFinal | e6dcc1eb31b54bd2378a34570507796ac7649c3e | [
"MIT"
] | null | null | null | Neander-MultMatriz-SetBRAM/button_driver_longpress.vhd | gabriel-lando/SisDig-TrabalhoFinal | e6dcc1eb31b54bd2378a34570507796ac7649c3e | [
"MIT"
] | null | null | null | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity button_driver_longpress is
Port ( clk, rst : in STD_LOGIC;
btn_in : in STD_LOGIC;
btn_out : out STD_LOGIC);
end button_driver_longpress;
architecture Behavioral of button_driver_longpress is
constant DB_MAX :... | 26.943262 | 84 | 0.596999 |
e0aa4533b0c25441e3529aeb8a6b02beac661b1c | 3,335 | vhd | VHDL | src/vhdl/ram/bus_ram_toplevel_tb.vhd | maikmerten/riscv-tomthumb | 164ecd3645318392453835692057c1a3594b1f13 | [
"MIT"
] | 35 | 2016-05-23T20:20:25.000Z | 2021-08-18T11:51:24.000Z | src/vhdl/ram/bus_ram_toplevel_tb.vhd | maikmerten/riscv-tomthumb | 164ecd3645318392453835692057c1a3594b1f13 | [
"MIT"
] | 1 | 2017-11-27T07:32:52.000Z | 2017-11-28T07:18:08.000Z | src/vhdl/ram/bus_ram_toplevel_tb.vhd | maikmerten/riscv-tomthumb | 164ecd3645318392453835692057c1a3594b1f13 | [
"MIT"
] | 8 | 2017-05-08T14:22:03.000Z | 2020-07-23T04:43:45.000Z | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity bus_ram_toplevel_tb is
end bus_ram_toplevel_tb;
architecture Behavior of bus_ram_toplevel_tb is
component bus_ram_toplevel
Port(
I_clk: in std_logic;
I_reset: in std_logic;
I_en: in std_logi... | 26.054688 | 107 | 0.686357 |
50b35be8efcb7f4693c78a3d200cfd9b68b9ead7 | 512 | vhd | VHDL | PARITY_GEN.vhd | Abeergit/UART | e07dd4f63555aaba3c670f4f86502dca1188acce | [
"MIT"
] | null | null | null | PARITY_GEN.vhd | Abeergit/UART | e07dd4f63555aaba3c670f4f86502dca1188acce | [
"MIT"
] | null | null | null | PARITY_GEN.vhd | Abeergit/UART | e07dd4f63555aaba3c670f4f86502dca1188acce | [
"MIT"
] | null | null | null | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity parity_gen is
port(
vec_in : in std_logic_vector (7 downto 0);
parity_bit : out std_logic);
end parity_gen;
architecture main of parity_gen is
signal parity : std_logic;
begin
process(vec_in)
begin
parity... | 19.692308 | 142 | 0.673828 |
e4bd0771feaa3f0ae8cc8eda6f76a4ee35b5e43f | 2,688 | vhd | VHDL | Classifiers/RF.vhd | marcusbotacin/Reconfigurable-AV | 983a142226a43d7b2eb764425b714f74f1b9af39 | [
"MIT"
] | 1 | 2020-08-28T19:23:32.000Z | 2020-08-28T19:23:32.000Z | Classifiers/RF.vhd | marcusbotacin/Reconfigurable-AV | 983a142226a43d7b2eb764425b714f74f1b9af39 | [
"MIT"
] | null | null | null | Classifiers/RF.vhd | marcusbotacin/Reconfigurable-AV | 983a142226a43d7b2eb764425b714f74f1b9af39 | [
"MIT"
] | null | null | null | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package hpc_array_type is
type HPCArray is array(0 to 4) of std_logic_vector (31 downto 0);
end package hpc_array_type;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package rf_array_type is
type RFArray is array(0 t... | 25.358491 | 73 | 0.65253 |
2491397048269c3897bbeafb0e0641d022b5247a | 1,335 | vhd | VHDL | src/vhdl/mmc_core_pkg.vhd | kjellhar/axi_mmc | e5bbffdba1a42011d9e430c90eb135e816402e17 | [
"MIT"
] | 1 | 2016-01-29T22:58:35.000Z | 2016-01-29T22:58:35.000Z | src/vhdl/mmc_core_pkg.vhd | kjellhar/axi_mmc | e5bbffdba1a42011d9e430c90eb135e816402e17 | [
"MIT"
] | null | null | null | src/vhdl/mmc_core_pkg.vhd | kjellhar/axi_mmc | e5bbffdba1a42011d9e430c90eb135e816402e17 | [
"MIT"
] | null | null | null | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/01/2014 09:25:56 AM
-- Design Name:
-- Module Name: mmc_core_pkg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revis... | 30.340909 | 82 | 0.602247 |
0d039f61422a9c3c935d4b9f661a266b5ced6820 | 13,994 | vhd | VHDL | ip/hdl/vhdl/houghlines_accel_HoughLines_1u_2u_32_800_0_180_0_480_640_1_s.vhd | DIII-SDU-Group/hough-accel-ip | 4d708d58fe29b426f8aff7180aaf1f229add5a0e | [
"Apache-2.0"
] | null | null | null | ip/hdl/vhdl/houghlines_accel_HoughLines_1u_2u_32_800_0_180_0_480_640_1_s.vhd | DIII-SDU-Group/hough-accel-ip | 4d708d58fe29b426f8aff7180aaf1f229add5a0e | [
"Apache-2.0"
] | null | null | null | ip/hdl/vhdl/houghlines_accel_HoughLines_1u_2u_32_800_0_180_0_480_640_1_s.vhd | DIII-SDU-Group/hough-accel-ip | 4d708d58fe29b426f8aff7180aaf1f229add5a0e | [
"Apache-2.0"
] | null | null | null | -- ==============================================================
-- RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit)
-- Version: 2020.2
-- Copyright (C) Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
lib... | 48.255172 | 237 | 0.723739 |
d281e40048065f282156e8975611271217977e74 | 89,237 | vhd | VHDL | projects/video/20180219-tmc-test_pattern/vivado/test_pattern_5/test_pattern_5.ip_user_files/bd/design_1/ip/design_1_v_tpg_0_1/hdl/vhdl/design_1_v_tpg_0_1_tpgForeground.vhd | trevor-crowley/my_lab | aa5af79c5aae47696697d058a6b906ba875dcd48 | [
"MIT"
] | 1 | 2021-07-10T09:20:08.000Z | 2021-07-10T09:20:08.000Z | projects/video/20180219-tmc-test_pattern/vivado/test_pattern_5/test_pattern_5.ip_user_files/bd/design_1/ip/design_1_v_tpg_0_1/hdl/vhdl/design_1_v_tpg_0_1_tpgForeground.vhd | trevor-crowley/mylab | aa5af79c5aae47696697d058a6b906ba875dcd48 | [
"MIT"
] | null | null | null | projects/video/20180219-tmc-test_pattern/vivado/test_pattern_5/test_pattern_5.ip_user_files/bd/design_1/ip/design_1_v_tpg_0_1/hdl/vhdl/design_1_v_tpg_0_1_tpgForeground.vhd | trevor-crowley/mylab | aa5af79c5aae47696697d058a6b906ba875dcd48 | [
"MIT"
] | null | null | null | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gn0XipDGE... | 76.205807 | 109 | 0.953102 |
b817060f0d42f5a99998b0157d4e0df79a169939 | 1,755 | vhdl | VHDL | CPU_CP0_Memory/Minisys_1A_CPU/Minisys_1A_CPU.cache/ip/2017.4/80cbf0aace696fe3/data_memory_0_stub.vhdl | z1514/Minisystem-Computer-Design | ab7f318ff398143048b35f2bf853f164ef3b53a6 | [
"MIT"
] | null | null | null | CPU_CP0_Memory/Minisys_1A_CPU/Minisys_1A_CPU.cache/ip/2017.4/80cbf0aace696fe3/data_memory_0_stub.vhdl | z1514/Minisystem-Computer-Design | ab7f318ff398143048b35f2bf853f164ef3b53a6 | [
"MIT"
] | null | null | null | CPU_CP0_Memory/Minisys_1A_CPU/Minisys_1A_CPU.cache/ip/2017.4/80cbf0aace696fe3/data_memory_0_stub.vhdl | z1514/Minisystem-Computer-Design | ab7f318ff398143048b35f2bf853f164ef3b53a6 | [
"MIT"
] | null | null | null | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017
-- Date : Sat Jan 16 02:14:47 2021
-- Host : DESKTOP-HB7J7JB running 64-bit major... | 45 | 175 | 0.68604 |
9799a948c2c636ec846d6a9ed8c0fc73b38719e2 | 3,265 | vhd | VHDL | Firmware_Vivado_Project/redpitaya.srcs/sources_1/DigitalPLL/dac2_error_computation.vhd | nbhebert/Frequency-comb-DPLL | 4903e477de1bbd9c8f274f848238266d712afd36 | [
"BSD-3-Clause"
] | 26 | 2017-06-01T21:52:17.000Z | 2022-03-08T19:58:22.000Z | Firmware_Vivado_Project/redpitaya.srcs/sources_1/DigitalPLL/dac2_error_computation.vhd | nbhebert/Frequency-comb-DPLL | 4903e477de1bbd9c8f274f848238266d712afd36 | [
"BSD-3-Clause"
] | 6 | 2017-09-18T01:12:13.000Z | 2021-12-23T12:23:37.000Z | Firmware_Vivado_Project/redpitaya.srcs/sources_1/DigitalPLL/dac2_error_computation.vhd | jddes/Frequency-comb-DPLL | 4b742f852ab1545c54ee17674a5c9bef1f7e3350 | [
"BSD-3-Clause"
] | 26 | 2017-06-13T18:15:07.000Z | 2022-03-17T02:48:06.000Z | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:34:12 02/09/2014
-- Design Name:
-- Module Name: dac2_error_computation - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This computes the de... | 40.308642 | 154 | 0.687902 |
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