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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
c9b8630bc77515bacb9b73b6539e840dfee1039a | 261 | h | C | src/include/promptSaveView.h | pedrorambo/2048 | 91ca6f1355abcc077a2e681a9443686d8291a616 | [
"MIT"
] | null | null | null | src/include/promptSaveView.h | pedrorambo/2048 | 91ca6f1355abcc077a2e681a9443686d8291a616 | [
"MIT"
] | 1 | 2021-05-06T17:23:50.000Z | 2021-05-07T21:33:57.000Z | src/include/promptSaveView.h | pedrorambo/2048 | 91ca6f1355abcc077a2e681a9443686d8291a616 | [
"MIT"
] | null | null | null | #include <ncurses.h>
#include <core.h>
#include <config.h>
#ifndef PROMPT_SAVE_VIEW_H
#define PROMPT_SAVE_VIEW_H
/* Função para mostrar prompt para salvar o progresso do jogo ao usuário */
void renderPromptSave(WINDOW *window, t_tableData *tableData);
#endif | 23.727273 | 75 | 0.781609 |
6897cfbb6f6823109018d3fbd420fb788bfff5f5 | 3,251 | h | C | zircon/kernel/vm/pmm_node.h | zhangpf/fuchsia-rs | 903568f28ddf45f09157ead36d61b50322c9cf49 | [
"BSD-3-Clause"
] | 1 | 2019-10-09T10:50:57.000Z | 2019-10-09T10:50:57.000Z | zircon/kernel/vm/pmm_node.h | zhangpf/fuchsia-rs | 903568f28ddf45f09157ead36d61b50322c9cf49 | [
"BSD-3-Clause"
] | 5 | 2020-09-06T09:02:06.000Z | 2022-03-02T04:44:22.000Z | zircon/kernel/vm/pmm_node.h | ZVNexus/fuchsia | c5610ad15208208c98693618a79c705af935270c | [
"BSD-3-Clause"
] | null | null | null | // Copyright 2018 The Fuchsia Authors
//
// Use of this source code is governed by a MIT-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/MIT
#pragma once
#include <fbl/canary.h>
#include <fbl/intrusive_double_list.h>
#include <fbl/mutex.h>
#include <kernel/lockdep.h>
#include <vm/pmm.h>
#include "pmm_arena.h"
#define PMM_ENABLE_FREE_FILL 0
#define PMM_FREE_FILL_BYTE 0x42
// per numa node collection of pmm arenas and worker threads
class PmmNode {
public:
PmmNode();
~PmmNode();
DISALLOW_COPY_ASSIGN_AND_MOVE(PmmNode);
paddr_t PageToPaddr(const vm_page_t* page) TA_NO_THREAD_SAFETY_ANALYSIS;
vm_page_t* PaddrToPage(paddr_t addr) TA_NO_THREAD_SAFETY_ANALYSIS;
// main allocator routines
zx_status_t AllocPage(uint alloc_flags, vm_page_t** page, paddr_t* pa);
zx_status_t AllocPages(size_t count, uint alloc_flags, list_node* list);
zx_status_t AllocRange(paddr_t address, size_t count, list_node* list);
zx_status_t AllocContiguous(size_t count, uint alloc_flags, uint8_t alignment_log2, paddr_t* pa, list_node* list);
void FreePage(vm_page* page);
void FreeList(list_node* list);
uint64_t CountFreePages() const;
uint64_t CountTotalBytes() const;
// printf free and overall state of the internal arenas
// NOTE: both functions skip mutexes and can be called inside timer or crash context
// though the data they return may be questionable
void DumpFree() const TA_NO_THREAD_SAFETY_ANALYSIS;
void Dump(bool is_panic) const TA_NO_THREAD_SAFETY_ANALYSIS;
#if PMM_ENABLE_FREE_FILL
void EnforceFill() TA_NO_THREAD_SAFETY_ANALYSIS;
#endif
zx_status_t AddArena(const pmm_arena_info_t* info);
// add new pages to the free queue. used when boostrapping a PmmArena
void AddFreePages(list_node* list);
private:
void FreePageHelperLocked(vm_page* page) TA_REQ(lock_);
void FreeListLocked(list_node* list) TA_REQ(lock_);
fbl::Canary<fbl::magic("PNOD")> canary_;
mutable DECLARE_MUTEX(PmmNode) lock_;
uint64_t arena_cumulative_size_ TA_GUARDED(lock_) = 0;
uint64_t free_count_ TA_GUARDED(lock_) = 0;
fbl::DoublyLinkedList<PmmArena*> arena_list_ TA_GUARDED(lock_);
// page queues
list_node free_list_ TA_GUARDED(lock_) = LIST_INITIAL_VALUE(free_list_);
list_node inactive_list_ TA_GUARDED(lock_) = LIST_INITIAL_VALUE(inactive_list_);
list_node active_list_ TA_GUARDED(lock_) = LIST_INITIAL_VALUE(active_list_);
list_node modified_list_ TA_GUARDED(lock_) = LIST_INITIAL_VALUE(modified_list_);
list_node wired_list_ TA_GUARDED(lock_) = LIST_INITIAL_VALUE(wired_list_);
#if PMM_ENABLE_FREE_FILL
void FreeFill(vm_page_t* page);
void CheckFreeFill(vm_page_t* page);
bool enforce_fill_ = false;
#endif
};
// We don't need to hold the arena lock while executing this, since it is
// only accesses values that are set once during system initialization.
inline vm_page_t* PmmNode::PaddrToPage(paddr_t addr) TA_NO_THREAD_SAFETY_ANALYSIS {
for (auto& a : arena_list_) {
if (a.address_in_arena(addr)) {
size_t index = (addr - a.base()) / PAGE_SIZE;
return a.get_page(index);
}
}
return nullptr;
}
| 33.864583 | 118 | 0.745924 |
02a2c629bd0acd50b951907624ffca641d5e60d3 | 871 | c | C | Server/Srcs/GamePlayer/game_player_sound_b.c | AEnguerrand/zappy | 359453f13e48b37c15c762ffa53151b477ea40a7 | [
"MIT"
] | null | null | null | Server/Srcs/GamePlayer/game_player_sound_b.c | AEnguerrand/zappy | 359453f13e48b37c15c762ffa53151b477ea40a7 | [
"MIT"
] | null | null | null | Server/Srcs/GamePlayer/game_player_sound_b.c | AEnguerrand/zappy | 359453f13e48b37c15c762ffa53151b477ea40a7 | [
"MIT"
] | null | null | null | /*
** game_player_sound_b.c for PSU_2016_zappy in /home/enguerrand/delivery/PSU_2016_zappy/game_player_sound_b.c
**
** Made by Enguerrand Allamel
** Login <enguerrand.allamel@epitech.eu>
**
** Started on Sun Jul 02 17:22:57 2017 Enguerrand Allamel
** Last update Sun Jul 02 17:22:57 2017 Enguerrand Allamel
*/
#include "zappy.h"
static int check_sound_dia(double b)
{
if (b == -135)
return (4);
else if (b == -45)
return (2);
if (b == 45)
return (8);
else if (b == 135)
return (6);
return (1);
}
int game_player_sound_check_sound(double an, int sig_s)
{
double b;
b = (int)((180 / M_PI) * acos(an));
b = b * sig_s;
if (b > -45 && b < 45)
return (1);
else if (b > 45 && b < 135)
return (7);
else if (b > 135 && b < -135)
return (5);
else if (b < -45 && b > -135)
return (3);
return (check_sound_dia(b));
} | 21.243902 | 109 | 0.601607 |
27eb1f4cd34b094bc72a0c6a997aa73ad3889de9 | 241 | h | C | Client_Portals/CLS-ProtoBlue-macOS-Client-Portal-master/ProtoBlue/AppDelegate.h | lancewalk87/ProtoBlue | 300abb8e09dd3d208033abe8c99a79513935eafe | [
"MIT"
] | 2 | 2018-11-01T21:07:27.000Z | 2018-12-23T03:19:07.000Z | Client_Portals/CLS-ProtoBlue-macOS-Client-Portal-master/ProtoBlue/AppDelegate.h | lancewalk87/ProtoBlue | 300abb8e09dd3d208033abe8c99a79513935eafe | [
"MIT"
] | null | null | null | Client_Portals/CLS-ProtoBlue-macOS-Client-Portal-master/ProtoBlue/AppDelegate.h | lancewalk87/ProtoBlue | 300abb8e09dd3d208033abe8c99a79513935eafe | [
"MIT"
] | null | null | null | //
// AppDelegate.h
// ProtoBlue
//
// Created by Lance T. Walker on 10/19/18.
// Copyright © 2018 CodeLife-Productions. All rights reserved.
//
#import <Cocoa/Cocoa.h>
@interface AppDelegate : NSObject <NSApplicationDelegate>
@end
| 15.0625 | 63 | 0.697095 |
7e769c8d1a2bb1e1c4d759c39eeb23b0b8a4356b | 1,295 | h | C | network/Network.h | EmperDeon/Organizer | 94b7be51290027a15a68d7b2e98dd49840822a5d | [
"MIT"
] | 1 | 2017-09-27T11:56:00.000Z | 2017-09-27T11:56:00.000Z | network/Network.h | EmperDeon/Organizer | 94b7be51290027a15a68d7b2e98dd49840822a5d | [
"MIT"
] | null | null | null | network/Network.h | EmperDeon/Organizer | 94b7be51290027a15a68d7b2e98dd49840822a5d | [
"MIT"
] | null | null | null | /*
Copyright (c) 2017-2018 by Ilya Barykin
Released under the MIT License.
See the provided LICENSE.TXT file for details.
*/
#ifndef ORGANIZER_NETWORK_H
#define ORGANIZER_NETWORK_H
#include <vendor/additions.h>
#include <vendor/additions.h>
#include <QtCore/QMap>
#include <QtNetwork/QNetworkAccessManager>
#include <QtNetwork/QNetworkReply>
#include <network/NCrypt.h>
class NCrypt;
class Network : public QObject {
NCrypt *crypt;
QNetworkAccessManager manager;
json_o lastReply;
int lastTime, lastCode;
QNetworkReply::NetworkError lastError;
bool hasErrors();
QUrl prepareReq(QString path);
json processReq(QNetworkReply *rep);
json req_POST(QString path, QMap<QString, QString> params);
json req_POST(QString path, QHttpMultiPart *part);
// QString req_GET(QString path, QMap<QString, QString> params);
public:
Network();
void uploadFile(QString path, QString file);
json request(QString path, QMap<QString, QString> params = {});
QString getLastTime();
QString getLastCode();
// QString getParameter(QString par);
void checkEncryption();
friend class NAuth;
void writeToLog(QString qString, QMap<QString, QString> map, QString type, json_a tries = json_a());
};
#endif //ORGANIZER_NETWORK_H
| 20.234375 | 104 | 0.725097 |
448119498d12443614b89e8053ea91beed40900d | 1,675 | h | C | VKPCH.h | TheBearProject/bearvulkan | ea16b0fb4c99246b91088ea196e3448c8a8d680a | [
"MIT"
] | 3 | 2020-07-03T14:32:09.000Z | 2020-11-20T12:59:07.000Z | VKPCH.h | TheBearProject/bearvulkan | ea16b0fb4c99246b91088ea196e3448c8a8d680a | [
"MIT"
] | null | null | null | VKPCH.h | TheBearProject/bearvulkan | ea16b0fb4c99246b91088ea196e3448c8a8d680a | [
"MIT"
] | 2 | 2020-04-24T20:19:21.000Z | 2020-07-03T14:32:12.000Z | #pragma once
#include "../BearGraphics/BearRenderBase.h"
/////////////////////////////////////
///////////Configure/////////////////
/////////////////////////////////////
#ifdef VK_11
#if CURRENT_PROCCESOR == PROCCESOR_AMD64
#define RTX
#endif
#endif
/////////////////////////////////////
/////////////////////////////////////
/////////////////////////////////////
#ifdef DEVELOPER_VERSION
#ifdef RTX
#define NV_EXTENSIONS
#include "dxc/dxcapi.h"
#endif
#include "shaderc/shaderc.hpp"
#endif
#if CURRENT_PLATFORM == PLATFORM_WINDOWS
#ifndef VK_USE_PLATFORM_WIN32_KHR
#define VK_USE_PLATFORM_WIN32_KHR
#endif
#endif
#define VK_NO_PROTOTYPES
#include "vulkan/vulkan.h"
extern void VkError(VkResult result);
#define V_CHK(a) { VkResult __Result_ = a ;if(__Result_!=VK_SUCCESS)VkError(__Result_); }
enum EVKQuery
{
VKQ_None = 0,
VKQ_ShaderResource,
VKQ_UnorderedAccess,
VKQ_Pipeline,
VKQ_RayTracingPipeline
};
#include "VKImports.h"
#include "VKFactory.h"
#include "VKViewport.h"
#include "VKContext.h"
#include "VKShader.h"
#include "VKBufferTools.h"
#include "VKVertexBuffer.h"
#include "VKIndexBuffer.h"
#include "VKUniformBuffer.h"
#include "VKRootSignature.h"
#include "VKPipeline.h"
#include "VKPipelineGraphics.h"
#include "VKPipelineMesh.h"
#include "VKDescriptorHeap.h"
#include "VKSamplers.h"
#include "VKShaderResource.h"
#include "VKUnorderedAccess.h"
#include "VKTexture2D.h"
#include "VKStats.h"
#include "VKRenderPass.h"
#include "VKFrameBuffer.h"
#include "VKTextureCube.h"
#include "VKStructuredBuffer.h"
#include "VKPipelineRayTracing.h"
#include "VKRayTracingBottomLevel.h"
#include "VKRayTracingTopLevel.h"
#include "VKRayTracingShaderTable.h" | 22.635135 | 89 | 0.684179 |
6d24d027f894df09d2a682c0e1a71e0b44199747 | 4,895 | c | C | f446re/periph_i2c/echo_handler.c | ChuckM/nucleo | 068930d8f0b8207e56e8f6826be3105c50242d83 | [
"BSD-2-Clause"
] | 2 | 2021-01-28T01:09:51.000Z | 2022-03-01T01:41:14.000Z | f446re/periph_i2c/echo_handler.c | ChuckM/nucleo | 068930d8f0b8207e56e8f6826be3105c50242d83 | [
"BSD-2-Clause"
] | null | null | null | f446re/periph_i2c/echo_handler.c | ChuckM/nucleo | 068930d8f0b8207e56e8f6826be3105c50242d83 | [
"BSD-2-Clause"
] | null | null | null | /*
* Echo handler - An i2c handler driver for peripheral devices
*
* This simple handler stores bytes that are written to the device
* and returns them when the device is read.
*
* Much like USB devices, when you're the peripheral you don't get to drive.
* Writing code to support that can be a bit tricky. I've chosen to
* create the notion of a 'handler' which can be plugged into the
* i2c peripheral driver and together they give you some feature. The
* goal is maximum code re-use.
*
* BSD 2-Clause License
*
* Copyright (C) 2013-2020 Chuck McManis <cmcmanis@mcmanis.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include "ring.h"
#include "periph_i2c.h"
#include "echo_handler.h"
static void echo_start(void *state, uint8_t rw);
static uint8_t echo_send(void *);
static void echo_recv(void *state, uint8_t db);
static void echo_finish(void *state, uint8_t err);
/*
* Prototype handler structure for the echo
* device.
*/
const i2c_handler_t echo_handler = {
.send = echo_send,
.recv = echo_recv,
.start = echo_start,
.stop = echo_finish,
.addr = 0,
.state = NULL
};
/*
* Allocate and Initialize the custom "state" structure
*
* This allocates memory for it and then fills in all the
* pointer values.
*
* Note: it returns NULL if any of the allocations fail.
*/
struct echo_state_t *
echo_init(uint16_t buf_size)
{
struct echo_state_t *state;
state = calloc(1, sizeof(struct echo_state_t));
if (state == NULL) {
return NULL;
}
state->rb = calloc(1, sizeof(ringbuffer_t));
if (state->rb == NULL) {
free(state);
return NULL;
}
state->rb->buffer = calloc(buf_size, 1);
if (state->rb->buffer == NULL) {
free(state->rb);
free(state);
return NULL;
}
state->rb->size = buf_size;
ringbuffer_flush(state->rb);
return state;
}
/*
* Send a byte from the echo chamber to the master.
*
* The ringbuffer is FIFO so this will nominally just return
* what you previously sent it, caveat if you are asked to
* send more than you have received it sends 0xff instead and
* notes it as a send error.
*/
static uint8_t
echo_send(void *s)
{
struct echo_state_t *state = (struct echo_state_t *)(s);
uint8_t db;
if (ringbuffer_holding(state->rb)) {
db = ringbuffer_get(state->rb);
state->bytes_sent++;
} else {
db = 0xff;
state->send_errs++;
}
return db;
}
/*
* Receive a byte from the master and put it into the echo chamber.
*
* As noted above the ringbuffer is a FIFO. It is also limited in
* size set at allocation, so if you send more data than will fit before
* reading back from the echo chamber it starts dropping bytes on
* the floor (they are discarded, and receive errors are recorded
* in the state data.
*/
static void
echo_recv(void *s, uint8_t db)
{
struct echo_state_t *state = (struct echo_state_t *)(s);
if (ringbuffer_available(state->rb) == 0) {
state->recv_errs++;
return;
} else {
state->bytes_recv++;
}
ringbuffer_put(state->rb, db);
}
/*
* Start a transaction, pretty boring it just increments the
* transaction count.
*/
static void
echo_start(void *s, uint8_t rw)
{
struct echo_state_t *state = (struct echo_state_t *)(s);
if (rw == HANDLE_MODE_RECEIVING) {
state->receive_count++;
} else {
state->send_count++;
}
}
/*
* Finish a transaction
*
* If there was an error make a note of it.
*/
static void
echo_finish(void *s, uint8_t err)
{
struct echo_state_t *state = (struct echo_state_t *)(s);
if (err) {
state->err_count++;
fprintf(stderr, "Error transaction: %d\n", err);
}
state->total++;
}
| 27.5 | 79 | 0.714402 |
75ed780767832d9a0405c4c869784a97f3a1bbdb | 16,282 | c | C | libxc-4.2.3/src/maple2c/gga_c_p86.c | rdietric/lsms | 8d0d5f01186abf9a1cc54db3f97f9934b422cf92 | [
"BSD-3-Clause"
] | 16 | 2018-04-03T15:35:47.000Z | 2022-03-01T03:19:23.000Z | libxc-4.2.3/src/maple2c/gga_c_p86.c | rdietric/lsms | 8d0d5f01186abf9a1cc54db3f97f9934b422cf92 | [
"BSD-3-Clause"
] | 8 | 2019-07-30T13:59:18.000Z | 2022-03-31T17:43:35.000Z | libxc-4.2.3/src/maple2c/gga_c_p86.c | rdietric/lsms | 8d0d5f01186abf9a1cc54db3f97f9934b422cf92 | [
"BSD-3-Clause"
] | 9 | 2018-06-30T00:30:48.000Z | 2022-01-31T09:14:29.000Z | /*
This file was generated automatically with /nfs/data-012/marques/software/source/libxc/svn/scripts/maple2c.pl.
Do not edit this file directly as it can be overwritten!!
This Source Code Form is subject to the terms of the Mozilla Public
License, v. 2.0. If a copy of the MPL was not distributed with this
file, You can obtain one at http://mozilla.org/MPL/2.0/.
Maple version : Maple 2016 (X86 64 LINUX)
Maple source : ../maple/gga_c_p86.mpl
Type of functional: work_gga_c
*/
void xc_gga_c_p86_func
(const xc_func_type *p, xc_gga_work_c_t *r)
{
double t1, t4, t5, t6, t7, t9, t10, t11;
double t15, t16, t19, t24, t25, t35, t36, t37;
double t38, t39, t40, t41, t42, t44, t47, t49;
double t50, t51, t52, t53, t54, t55, t56, t58;
double t60, t62, t65, t67, t68, t70, t71, t72;
double t73, t74, t76, t77, t78, t79, t80, t81;
double t84, t85, t86, t87, t88, t89, t90, t91;
double t92, t94, t95, t96, t99, t100, t101, t102;
double t104, t106, t107, t109, t110, t112, t118, t121;
double t123, t124, t125, t127, t141, t144, t145, t146;
double t149, t150, t151, t152, t153, t155, t157, t158;
double t159, t162, t164, t168, t171, t173, t176, t177;
double t178, t182, t183, t187, t190, t193, t195, t196;
double t197, t200, t201, t204, t205, t206, t207, t211;
double t212, t216, t217, t218, t220, t223, t225, t226;
double t228, t230, t233, t235, t237, t239, t240, t242;
double t243, t246, t247, t248, t261, t269, t276, t280;
double t281, t282, t286, t288, t290, t291, t294, t295;
double t296, t299, t303, t304, t305, t309, t319, t320;
double t321, t325, t327, t330, t331, t332, t335, t340;
double t341, t342, t345, t350, t351, t354, t355, t358;
double t359, t365, t368, t369, t375, t376, t377, t380;
double t381, t382, t383, t389, t390, t396, t399, t401;
double t403, t404, t405, t411, t412, t413, t418, t419;
double t423, t424, t425, t426, t432, t435, t438, t443;
double t475, t485, t517, t520, t522, t523, t524, t529;
double t536, t551, t553, t557, t558, t560, t562, t566;
double t568, t573, t578, t580, t581, t589, t617, t623;
double t666, t669, t684, t768, t776;
t1 = sqrt(r->rs);
t4 = 0.1e1 + 0.10529e1 * t1 + 0.3334e0 * r->rs;
t5 = 0.1e1 / t4;
t6 = r->rs - 0.1e1;
t7 = Heaviside(t6);
t9 = 0.1423e0 * t5 * t7;
t10 = log(r->rs);
t11 = t10 * t7;
t15 = r->rs * t10;
t16 = t15 * t7;
t19 = r->rs * t7;
t24 = 0.1e1 + 0.13981e1 * t1 + 0.2611e0 * r->rs;
t25 = 0.1e1 / t24;
t35 = -0.843e-1 * t25 * t7 + 0.1555e-1 * t11 - 0.1555e-1 * t10 + 0.211e-1 - 0.211e-1 * t7 + 0.13e-2 * t16 - 0.13e-2 * t15 - 0.68e-2 * t19 + 0.68e-2 * r->rs + t9;
t36 = 0.1e1 + r->z;
t37 = cbrt(t36);
t38 = t37 * t36;
t39 = 0.1e1 - r->z;
t40 = cbrt(t39);
t41 = t40 * t39;
t42 = t38 + t41 - 0.2e1;
t44 = M_CBRT2;
t47 = 0.1e1 / (0.2e1 * t44 - 0.2e1);
t49 = r->xt * r->xt;
t50 = 0.1e1 / r->rs;
t51 = t49 * t50;
t52 = M_CBRT3;
t53 = M_CBRT4;
t54 = t53 * t53;
t55 = t52 * t54;
t56 = t51 * t55;
t58 = cbrt(0.1e1 / 0.31415926535897932385e1);
t60 = r->rs * r->rs;
t62 = 0.2568e-2 + 0.23266e-1 * r->rs + 0.7389e-5 * t60;
t65 = t60 * r->rs;
t67 = 0.1e1 + 0.8723e1 * r->rs + 0.472e0 * t60 + 0.73890e-1 * t65;
t68 = 0.1e1 / t67;
t70 = 0.1667e-2 + t62 * t68;
t71 = 0.1e1 / t70;
t72 = t71 * r->xt;
t73 = sqrt(0.3e1);
t74 = t52 * t52;
t76 = 0.1e1 / t58;
t77 = t53 * t76;
t78 = r->rs * t74 * t77;
t79 = sqrt(t78);
t80 = 0.1e1 / t79;
t81 = t73 * t80;
t84 = exp(-0.81290825e-3 * t72 * t81);
t85 = t58 * t84;
t86 = t37 * t37;
t87 = t86 * t36;
t88 = t40 * t40;
t89 = t88 * t39;
t90 = t87 + t89;
t91 = sqrt(t90);
t92 = 0.1e1 / t91;
t94 = M_SQRT2;
t95 = t70 * t92 * t94;
t96 = t85 * t95;
r->f = -t9 - 0.311e-1 * t11 + 0.311e-1 * t10 - 0.48e-1 + 0.48e-1 * t7 - 0.20e-2 * t16 + 0.20e-2 * t15 + 0.116e-1 * t19 - 0.116e-1 * r->rs + t35 * t42 * t47 + t56 * t96 / 0.4e1;
if(r->order < 1) return;
t99 = t4 * t4;
t100 = 0.1e1 / t99;
t101 = t100 * t7;
t102 = 0.1e1 / t1;
t104 = 0.52645000000000000000e0 * t102 + 0.3334e0;
t106 = 0.1423e0 * t101 * t104;
t107 = 0.0;
t109 = 0.1423e0 * t5 * t107;
t110 = t50 * t7;
t112 = t10 * t107;
t118 = t15 * t107;
t121 = r->rs * t107;
t123 = t24 * t24;
t124 = 0.1e1 / t123;
t125 = t124 * t7;
t127 = 0.69905000000000000000e0 * t102 + 0.2611e0;
t141 = 0.843e-1 * t125 * t127 - 0.843e-1 * t25 * t107 + 0.1555e-1 * t110 + 0.1555e-1 * t112 - 0.1555e-1 * t50 - 0.211e-1 * t107 + 0.13e-2 * t11 - 0.55e-2 * t7 + 0.13e-2 * t118 - 0.13e-2 * t10 + 0.55e-2 - 0.68e-2 * t121 - t106 + t109;
t144 = 0.1e1 / t60;
t145 = t49 * t144;
t146 = t145 * t55;
t149 = t55 * t58;
t150 = t51 * t149;
t151 = t70 * t70;
t152 = 0.1e1 / t151;
t153 = t152 * r->xt;
t155 = 0.23266e-1 + 0.14778e-4 * r->rs;
t157 = t67 * t67;
t158 = 0.1e1 / t157;
t159 = t62 * t158;
t162 = 0.8723e1 + 0.944e0 * r->rs + 0.221670e0 * t60;
t164 = t155 * t68 - t159 * t162;
t168 = pow(0.3e1, 0.1e1 / 0.6e1);
t171 = 0.1e1 / t79 / t78;
t173 = t171 * t53 * t76;
t176 = 0.81290825e-3 * t153 * t81 * t164 + 0.12193623750000000000e-2 * t72 * t168 * t173;
t177 = t176 * t84;
t178 = t177 * t95;
t182 = t164 * t92 * t94;
t183 = t85 * t182;
r->dfdrs = t106 - t109 - 0.311e-1 * t110 - 0.311e-1 * t112 + 0.311e-1 * t50 + 0.48e-1 * t107 - 0.20e-2 * t11 + 0.96e-2 * t7 - 0.20e-2 * t118 + 0.20e-2 * t10 - 0.96e-2 + 0.116e-1 * t121 + t141 * t42 * t47 - t146 * t96 / 0.4e1 + t150 * t178 / 0.4e1 + t56 * t183 / 0.4e1;
t187 = 0.4e1 / 0.3e1 * t37 - 0.4e1 / 0.3e1 * t40;
t190 = t84 * t70;
t193 = 0.1e1 / t91 / t90 * t94;
t195 = 0.5e1 / 0.3e1 * t86 - 0.5e1 / 0.3e1 * t88;
t196 = t193 * t195;
t197 = t190 * t196;
r->dfdz = t35 * t187 * t47 - t150 * t197 / 0.8e1;
t200 = r->xt * t50;
t201 = t200 * t55;
t204 = t168 * t168;
t205 = t204 * t204;
t206 = t205 * t168;
t207 = t206 * t54;
t211 = t84 * t92 * t94;
t212 = t58 * t80 * t211;
r->dfdxt = t201 * t96 / 0.2e1 - 0.20322706250000000000e-3 * t51 * t207 * t212;
r->dfdxs[0] = 0.0e0;
r->dfdxs[1] = 0.0e0;
if(r->order < 2) return;
t216 = 0.1e1 / t99 / t4;
t217 = t216 * t7;
t218 = t104 * t104;
t220 = 0.2846e0 * t217 * t218;
t223 = 0.0;
t225 = 0.1423e0 * t5 * t223;
t226 = t50 * t107;
t228 = t10 * t223;
t230 = r->rs * t223;
t233 = t100 * t107;
t235 = 0.2846e0 * t233 * t104;
t237 = 0.1e1 / t1 / r->rs;
t239 = 0.37456917500000000000e-1 * t101 * t237;
t240 = t144 * t7;
t242 = -t220 - 0.20e-2 * t110 - 0.40e-2 * t112 - t225 - 0.622e-1 * t226 - 0.311e-1 * t228 + 0.116e-1 * t230 + 0.192e-1 * t107 + t235 - t239 + 0.311e-1 * t240;
t243 = t15 * t223;
t246 = 0.1e1 / t123 / t24;
t247 = t246 * t7;
t248 = t127 * t127;
t261 = t124 * t107;
t269 = t220 - 0.1686e0 * t247 * t248 + 0.13e-2 * t110 + 0.26e-2 * t112 + t225 + 0.3110e-1 * t226 + 0.1555e-1 * t228 - 0.68e-2 * t230 - 0.843e-1 * t25 * t223 - 0.110e-1 * t107 - t235 + t239 - 0.1555e-1 * t240 + 0.13e-2 * t243 + 0.1686e0 * t261 * t127 - 0.29464957500000000000e-1 * t125 * t237 - 0.13e-2 * t50 - 0.211e-1 * t223 + 0.1555e-1 * t144;
t276 = t155 * t158;
t280 = 0.1e1 / t157 / t67;
t281 = t62 * t280;
t282 = t162 * t162;
t286 = 0.944e0 + 0.443340e0 * r->rs;
t288 = 0.14778e-4 * t68 - 0.2e1 * t276 * t162 + 0.2e1 * t281 * t282 - t159 * t286;
t290 = t288 * t92 * t94;
t291 = t85 * t290;
t294 = 0.1e1 / t65;
t295 = t49 * t294;
t296 = t295 * t55;
t299 = t145 * t149;
t303 = 0.1e1 / t151 / t70;
t304 = t303 * r->xt;
t305 = t164 * t164;
t309 = t153 * t168;
t319 = t58 * t58;
t320 = 0.1e1 / t319;
t321 = t54 * t320;
t325 = 0.1e1 / t79 / t60 / t52 / t321 / 0.3e1;
t327 = t325 * t54 * t320;
t330 = -0.162581650e-2 * t304 * t81 * t305 - 0.24387247500000000000e-2 * t309 * t171 * t164 * t77 + 0.81290825e-3 * t153 * t81 * t288 - 0.18290435625000000000e-2 * t72 * t206 * t327;
t331 = t330 * t84;
t332 = t331 * t95;
t335 = t177 * t182;
t340 = t176 * t176;
t341 = t340 * t84;
t342 = t341 * t95;
t345 = -0.20e-2 * t243 + t269 * t42 * t47 + 0.20e-2 * t50 - t146 * t183 / 0.2e1 + t56 * t291 / 0.4e1 + t296 * t96 / 0.2e1 - t299 * t178 / 0.2e1 + t150 * t332 / 0.4e1 + t150 * t335 / 0.2e1 + 0.48e-1 * t223 - 0.311e-1 * t144 + t150 * t342 / 0.4e1;
r->d2fdrs2 = t345 + t242;
t350 = t177 * t70;
t351 = t350 * t196;
t354 = t84 * t164;
t355 = t354 * t196;
r->d2fdrsz = t141 * t187 * t47 + t299 * t197 / 0.8e1 - t150 * t351 / 0.8e1 - t150 * t355 / 0.8e1;
t358 = r->xt * t144;
t359 = t358 * t55;
t365 = t200 * t149;
t368 = t152 * t73;
t369 = t80 * t164;
t375 = 0.81290825e-3 * t368 * t369 + 0.12193623750000000000e-2 * t71 * t168 * t173;
t376 = t375 * t84;
t377 = t376 * t95;
t380 = t207 * t58;
t381 = t51 * t380;
t382 = t176 * t80;
t383 = t382 * t211;
t389 = t71 * t80 * t84;
t390 = t389 * t182;
r->d2fdrsxt = -t359 * t96 / 0.2e1 + 0.20322706250000000000e-3 * t145 * t207 * t212 + t365 * t178 / 0.2e1 + t150 * t377 / 0.4e1 - 0.20322706250000000000e-3 * t381 * t383 + t201 * t183 / 0.2e1 - 0.20322706250000000000e-3 * t381 * t390;
r->d2fdrsxs[0] = 0.0e0;
r->d2fdrsxs[1] = 0.0e0;
t396 = 0.4e1 / 0.9e1 / t86 + 0.4e1 / 0.9e1 / t88;
t399 = t90 * t90;
t401 = 0.1e1 / t91 / t399;
t403 = t195 * t195;
t404 = t401 * t94 * t403;
t405 = t190 * t404;
t411 = 0.10e2 / 0.9e1 / t37 + 0.10e2 / 0.9e1 / t40;
t412 = t193 * t411;
t413 = t190 * t412;
r->d2fdz2 = t35 * t396 * t47 + 0.3e1 / 0.16e2 * t150 * t405 - t150 * t413 / 0.8e1;
t418 = t80 * t84;
t419 = t418 * t196;
r->d2fdzxt = -t365 * t197 / 0.4e1 + 0.10161353125000000000e-3 * t381 * t419;
r->d2fdzxs[0] = 0.0e0;
r->d2fdzxs[1] = 0.0e0;
t423 = t54 * t58;
t424 = t50 * t52 * t423;
t425 = t92 * t94;
t426 = t190 * t425;
t432 = t74 * t53;
t435 = t319 * t71 * t211;
r->d2fdxt2 = t424 * t426 / 0.2e1 - 0.81290825000000000000e-3 * t200 * t207 * t212 + 0.16520495572951562500e-6 * t145 * t432 * t435;
r->d2fdxtxs[0] = 0.0e0;
r->d2fdxtxs[1] = 0.0e0;
r->d2fdxs2[0] = 0.0e0;
r->d2fdxs2[1] = 0.0e0;
r->d2fdxs2[2] = 0.0e0;
if(r->order < 3) return;
t438 = t295 * t149;
t443 = t151 * t151;
t475 = t157 * t157;
t485 = -0.44334e-4 * t158 * t162 + 0.6e1 * t155 * t280 * t282 - 0.3e1 * t276 * t286 - 0.6e1 * t62 / t475 * t282 * t162 + 0.6e1 * t281 * t162 * t286 - 0.443340e0 * t159;
t517 = 0.8538e0 * t216 * t107 * t218;
t520 = 0.4269e0 * t100 * t223 * t104;
t522 = 0.11237075250000000000e0 * t233 * t237;
t523 = 0.0;
t524 = t15 * t523;
t529 = t123 * t123;
t536 = 0.1e1 / t1 / t60;
t551 = 0.22474150500000000000e0 * t217 * t104 * t237;
t553 = t517 - t520 + t522 + 0.13e-2 * t524 - 0.88394872500000000000e-1 * t261 * t237 + 0.5058e0 / t529 * t7 * t248 * t127 + 0.44197436250000000000e-1 * t125 * t536 - 0.5058e0 * t246 * t107 * t248 + 0.2529e0 * t124 * t223 * t127 - 0.211e-1 * t523 + 0.17678974500000000000e0 * t247 * t127 * t237 - t551 - 0.3110e-1 * t294;
t557 = 0.1423e0 * t5 * t523;
t558 = t50 * t223;
t560 = t10 * t523;
t562 = r->rs * t523;
t566 = t144 * t107;
t568 = t294 * t7;
t573 = t99 * t99;
t578 = 0.8538e0 / t573 * t7 * t218 * t104;
t580 = 0.56185376250000000000e-1 * t101 * t536;
t581 = -0.165e-1 * t223 + 0.13e-2 * t144 + t557 + 0.4665e-1 * t558 + 0.1555e-1 * t560 - 0.68e-2 * t562 - 0.843e-1 * t25 * t523 - 0.4665e-1 * t566 + 0.3110e-1 * t568 + 0.39e-2 * t226 + 0.39e-2 * t228 - 0.13e-2 * t240 - t578 - t580;
t589 = 0.3e1 / 0.2e1 * t438 * t178 - 0.3e1 / 0.4e1 * t299 * t332 + t150 * (0.487744950e-2 / t443 * r->xt * t81 * t305 * t164 + 0.73161742500000000000e-2 * t304 * t168 * t171 * t305 * t77 - 0.487744950e-2 * t304 * t73 * t369 * t288 + 0.54871306875000000000e-2 * t153 * t206 * t325 * t164 * t321 - 0.36580871250000000000e-2 * t309 * t171 * t288 * t77 + 0.81290825e-3 * t153 * t81 * t485 + 0.15242029687500000000e-2 * t72 * t73 / t79 / t65) * t84 * t95 / 0.4e1 + 0.3e1 / 0.4e1 * t150 * t331 * t182 - 0.3e1 / 0.4e1 * t299 * t342 + 0.3e1 / 0.4e1 * t150 * t341 * t182 + t150 * t340 * t176 * t84 * t95 / 0.4e1 - t517 + t520 - t522 - 0.20e-2 * t524 + (t581 + t553) * t42 * t47 + 0.48e-1 * t523 + t551 + 0.622e-1 * t294 + 0.288e-1 * t223 - 0.20e-2 * t144;
t617 = t60 * t60;
t623 = -t557 - 0.933e-1 * t558 - 0.311e-1 * t560 + 0.116e-1 * t562 + 0.933e-1 * t566 - 0.622e-1 * t568 - 0.60e-2 * t226 - 0.60e-2 * t228 + 0.20e-2 * t240 + t578 + t580 + 0.3e1 / 0.4e1 * t150 * t330 * t176 * t84 * t95 - 0.3e1 / 0.2e1 * t299 * t335 + 0.3e1 / 0.4e1 * t150 * t177 * t290 - 0.3e1 / 0.4e1 * t146 * t291 + t56 * t85 * t485 * t92 * t94 / 0.4e1 + 0.3e1 / 0.2e1 * t296 * t183 - 0.3e1 / 0.2e1 * t49 / t617 * t55 * t96;
r->d3fdrs3 = t623 + t589;
r->d3fdrs2z = t269 * t187 * t47 + t299 * t355 / 0.4e1 - t150 * t84 * t288 * t196 / 0.8e1 - t438 * t197 / 0.4e1 + t299 * t351 / 0.4e1 - t150 * t331 * t70 * t196 / 0.8e1 - t150 * t177 * t164 * t196 / 0.4e1 - t150 * t341 * t70 * t196 / 0.8e1;
r->d3fdrsz2 = t141 * t396 * t47 - 0.3e1 / 0.16e2 * t299 * t405 + t299 * t413 / 0.8e1 + 0.3e1 / 0.16e2 * t150 * t350 * t404 - t150 * t350 * t412 / 0.8e1 + 0.3e1 / 0.16e2 * t150 * t354 * t404 - t150 * t354 * t412 / 0.8e1;
t666 = t358 * t149;
t669 = t145 * t380;
t684 = t51 * t206;
r->d3fdrszxt = t666 * t197 / 0.4e1 - 0.10161353125000000000e-3 * t669 * t419 - t365 * t351 / 0.4e1 - t150 * t376 * t70 * t196 / 0.8e1 + 0.10161353125000000000e-3 * t381 * t382 * t84 * t196 - t365 * t355 / 0.4e1 + 0.10161353125000000000e-3 * t684 * t423 * t71 * t418 * t164 * t196;
r->d3fdrszxs[0] = 0.0e0;
r->d3fdrszxs[1] = 0.0e0;
r->d3fdrs2xt = -t359 * t183 + 0.40645412500000000000e-3 * t669 * t390 + t201 * t291 / 0.2e1 - 0.20322706250000000000e-3 * t381 * t389 * t290 + r->xt * t294 * t55 * t96 - 0.40645412500000000000e-3 * t295 * t207 * t212 - t666 * t178 - t299 * t377 / 0.2e1 + 0.40645412500000000000e-3 * t669 * t383 + t365 * t332 / 0.2e1 + t150 * (-0.162581650e-2 * t303 * t73 * t80 * t305 - 0.24387247500000000000e-2 * t152 * t168 * t171 * t164 * t53 * t76 + 0.81290825e-3 * t368 * t80 * t288 - 0.18290435625000000000e-2 * t71 * t206 * t327) * t84 * t95 / 0.4e1 - 0.20322706250000000000e-3 * t381 * t330 * t80 * t211 + t365 * t335 + t150 * t376 * t182 / 0.2e1 - 0.40645412500000000000e-3 * t684 * t423 * t176 * t390 + t365 * t342 / 0.2e1 + t150 * t350 * t425 * t375 / 0.2e1 - 0.20322706250000000000e-3 * t381 * t340 * t80 * t211;
t768 = t200 * t380;
t776 = t145 * t432 * t319;
r->d3fdrsxt2 = -t144 * t52 * t423 * t426 / 0.2e1 + 0.81290825000000000000e-3 * t358 * t207 * t212 - 0.16520495572951562500e-6 * t295 * t432 * t435 + t424 * t178 / 0.2e1 + t365 * t377 - 0.81290825000000000000e-3 * t768 * t383 - 0.40645412500000000000e-3 * t381 * t375 * t80 * t211 + 0.16520495572951562500e-6 * t776 * t176 * t71 * t211 + t424 * t354 * t425 / 0.2e1 - 0.81290825000000000000e-3 * t768 * t390 + 0.16520495572951562500e-6 * t776 * t152 * t84 * t182;
r->d3fdrsxtxs[0] = 0.0e0;
r->d3fdrsxtxs[1] = 0.0e0;
r->d3fdrs2xs[0] = 0.0e0;
r->d3fdrs2xs[1] = 0.0e0;
r->d3fdrsxs2[0] = 0.0e0;
r->d3fdrsxs2[1] = 0.0e0;
r->d3fdrsxs2[2] = 0.0e0;
r->d3fdz3 = t35 * (-0.8e1 / 0.27e2 / t87 + 0.8e1 / 0.27e2 / t89) * t47 - 0.15e2 / 0.32e2 * t150 * t190 / t91 / t399 / t90 * t94 * t403 * t195 + 0.9e1 / 0.16e2 * t150 * t190 * t401 * t94 * t195 * t411 - t150 * t190 * t193 * (-0.10e2 / 0.27e2 / t38 + 0.10e2 / 0.27e2 / t41) / 0.8e1;
r->d3fdz2xt = 0.3e1 / 0.8e1 * t365 * t405 - 0.15242029687500000000e-3 * t381 * t418 * t404 - t365 * t413 / 0.4e1 + 0.10161353125000000000e-3 * t381 * t418 * t412;
r->d3fdzxt2 = -t424 * t197 / 0.4e1 + 0.40645412500000000000e-3 * t768 * t419 - 0.82602477864757812500e-7 * t776 * t71 * t84 * t196;
r->d3fdzxtxs[0] = 0.0e0;
r->d3fdzxtxs[1] = 0.0e0;
r->d3fdz2xs[0] = 0.0e0;
r->d3fdz2xs[1] = 0.0e0;
r->d3fdzxs2[0] = 0.0e0;
r->d3fdzxs2[1] = 0.0e0;
r->d3fdzxs2[2] = 0.0e0;
r->d3fdxt3 = -0.12193623750000000000e-2 * t50 * t206 * t423 * t418 * t425 + 0.99122973437709375000e-6 * t358 * t432 * t435 - 0.40288941436022406020e-9 * t145 * t168 * t53 * t319 * t152 * t80 * t211;
r->d3fdxt2xs[0] = 0.0e0;
r->d3fdxt2xs[1] = 0.0e0;
r->d3fdxtxs2[0] = 0.0e0;
r->d3fdxtxs2[1] = 0.0e0;
r->d3fdxtxs2[2] = 0.0e0;
r->d3fdxs3[0] = 0.0e0;
r->d3fdxs3[1] = 0.0e0;
r->d3fdxs3[2] = 0.0e0;
r->d3fdxs3[3] = 0.0e0;
if(r->order < 4) return;
}
#define maple2c_order 3
#define maple2c_func xc_gga_c_p86_func
| 46.52 | 811 | 0.578307 |
922f3a059e73192588512a340798b8174c763a12 | 9,769 | c | C | t/base64.c | gonzus/pizza | 871190dea092a2c3fb5d499ef7f4f8faa75b52cb | [
"MIT"
] | null | null | null | t/base64.c | gonzus/pizza | 871190dea092a2c3fb5d499ef7f4f8faa75b52cb | [
"MIT"
] | null | null | null | t/base64.c | gonzus/pizza | 871190dea092a2c3fb5d499ef7f4f8faa75b52cb | [
"MIT"
] | null | null | null | #include <string.h>
#include <tap.h>
#include "base64.h"
#define ALEN(a) (int) ((sizeof(a) / sizeof((a)[0])))
static void test_base64(void) {
static struct {
const char* label;
const char* plain;
uint32_t use;
const char* encoded;
} data[] = {
{ "binary", "\x01\x02\x03", 0, "AQID" },
{ "tinier", "Hey", 0, "SGV5" },
{ "tiny, 0 EQ", "Amsterdam", 0, "QW1zdGVyZGFt" },
{ "tiny, 2 EQ", "Belgium", 0, "QmVsZ2l1bQ==" },
{ "short, 1 EQ", "Hello World!!!", 0, "SGVsbG8gV29ybGQhISE=" },
{ "shorter, 1 EQ", "Hello World!!!", 5, "SGVsbG8=" },
{ "medium", "Lorem ipsum dolor sit amet, consectetur adipiscing elit. Etiam ex nunc, rhoncus in blandit at, rutrum sed turpis. Aenean in bibendum dolor, vitae facilisis dolor. Quisque imperdiet et nulla non feugiat. Fusce elementum est eu nibh efficitur aliquet. Quisque elementum diam libero, eget auctor nunc condimentum in.", 0, "TG9yZW0gaXBzdW0gZG9sb3Igc2l0IGFtZXQsIGNvbnNlY3RldHVyIGFkaXBpc2NpbmcgZWxpdC4gRXRpYW0gZXggbnVuYywgcmhvbmN1cyBpbiBibGFuZGl0IGF0LCBydXRydW0gc2VkIHR1cnBpcy4gQWVuZWFuIGluIGJpYmVuZHVtIGRvbG9yLCB2aXRhZSBmYWNpbGlzaXMgZG9sb3IuIFF1aXNxdWUgaW1wZXJkaWV0IGV0IG51bGxhIG5vbiBmZXVnaWF0LiBGdXNjZSBlbGVtZW50dW0gZXN0IGV1IG5pYmggZWZmaWNpdHVyIGFsaXF1ZXQuIFF1aXNxdWUgZWxlbWVudHVtIGRpYW0gbGliZXJvLCBlZ2V0IGF1Y3RvciBudW5jIGNvbmRpbWVudHVtIGluLg==" },
{ "long", "Lorem ipsum dolor sit amet, consectetur adipiscing elit. Etiam ex nunc, rhoncus in blandit at, rutrum sed turpis. Aenean in bibendum dolor, vitae facilisis dolor. Quisque imperdiet et nulla non feugiat. Fusce elementum est eu nibh efficitur aliquet. Quisque elementum diam libero, eget auctor nunc condimentum in. Maecenas sit amet est maximus, ultricies quam ac, sagittis odio. Pellentesque habitant morbi tristique senectus et netus et malesuada fames ac turpis egestas. Vestibulum pharetra nisl non lacus pharetra lobortis. Vivamus vel tortor ac nulla lobortis scelerisque in sit amet enim.\nLorem ipsum dolor sit amet, consectetur adipiscing elit. Integer vitae erat accumsan quam eleifend suscipit. Nullam finibus mi a lacus lobortis vehicula. Nulla facilisi. Quisque molestie odio et nulla scelerisque, in maximus turpis posuere. Suspendisse magna quam, imperdiet ac diam eget, pharetra fringilla eros. Lorem ipsum dolor sit amet, consectetur adipiscing elit. Proin ac ex sapien. Praesent accumsan consequat sapien, vel pretium ligula hendrerit in. Aenean sit amet ligula nec leo tincidunt egestas. Nulla ullamcorper eros sed risus venenatis, ut eleifend nunc vulputate. Praesent egestas nisi sed quam gravida, a tempor sem interdum. Nam a arcu nibh.\nInteger vulputate nunc ac erat sollicitudin porta id id risus. Fusce nec aliquam risus, at tincidunt sapien. Suspendisse dignissim, erat eu rutrum mollis, lacus lorem lacinia enim, nec ornare nibh justo commodo nibh. Proin velit mi, dapibus non tincidunt id, pretium in metus. Morbi eu rhoncus tortor, ac tempor lacus. In vehicula non purus eu faucibus. Vestibulum volutpat nunc id pharetra posuere. Sed sagittis ligula in fermentum viverra. Aliquam aliquet sed nisi non sodales. Duis ullamcorper urna quam, in imperdiet urna ullamcorper quis. In hac habitasse platea dictumst.\nDonec cursus, felis a pulvinar tempus, elit mi hendrerit felis, et volutpat eros felis sed lacus. Nulla est ipsum, molestie sed nisl in, sagittis laoreet ex. Curabitur dapibus egestas lobortis. Morbi pulvinar placerat tellus sed sollicitudin. Ut finibus suscipit mi, at fermentum purus tincidunt eu. Nulla suscipit magna vel massa tincidunt laoreet at at odio. Fusce nec magna eros.\nInterdum et malesuada fames ac ante ipsum primis in faucibus. Nam condimentum, velit dictum scelerisque tincidunt, arcu libero fermentum libero, lacinia hendrerit lorem tellus quis lectus. Donec placerat sodales eros rutrum tincidunt. Aliquam erat volutpat. Interdum et malesuada fames ac ante ipsum primis in faucibus. Praesent id nulla at justo rutrum ultrices. Vestibulum hendrerit elit eget pharetra porta. Nunc euismod velit nulla, a faucibus purus venenatis sed. Donec id augue lobortis purus vestibulum fermentum. Suspendisse nibh nisi, malesuada in pulvinar et, pretium blandit turpis. Interdum et malesuada fames ac ante ipsum primis in faucibus. Etiam at mollis ex. Cras in nunc quis lacus aliquam laoreet. Ut tincidunt nisl ac sapien dictum, id suscipit elit mattis. Pellentesque tristique interdum lobortis.", 0, "TG9yZW0gaXBzdW0gZG9sb3Igc2l0IGFtZXQsIGNvbnNlY3RldHVyIGFkaXBpc2NpbmcgZWxpdC4gRXRpYW0gZXggbnVuYywgcmhvbmN1cyBpbiBibGFuZGl0IGF0LCBydXRydW0gc2VkIHR1cnBpcy4gQWVuZWFuIGluIGJpYmVuZHVtIGRvbG9yLCB2aXRhZSBmYWNpbGlzaXMgZG9sb3IuIFF1aXNxdWUgaW1wZXJkaWV0IGV0IG51bGxhIG5vbiBmZXVnaWF0LiBGdXNjZSBlbGVtZW50dW0gZXN0IGV1IG5pYmggZWZmaWNpdHVyIGFsaXF1ZXQuIFF1aXNxdWUgZWxlbWVudHVtIGRpYW0gbGliZXJvLCBlZ2V0IGF1Y3RvciBudW5jIGNvbmRpbWVudHVtIGluLiBNYWVjZW5hcyBzaXQgYW1ldCBlc3QgbWF4aW11cywgdWx0cmljaWVzIHF1YW0gYWMsIHNhZ2l0dGlzIG9kaW8uIFBlbGxlbnRlc3F1ZSBoYWJpdGFudCBtb3JiaSB0cmlzdGlxdWUgc2VuZWN0dXMgZXQgbmV0dXMgZXQgbWFsZXN1YWRhIGZhbWVzIGFjIHR1cnBpcyBlZ2VzdGFzLiBWZXN0aWJ1bHVtIHBoYXJldHJhIG5pc2wgbm9uIGxhY3VzIHBoYXJldHJhIGxvYm9ydGlzLiBWaXZhbXVzIHZlbCB0b3J0b3IgYWMgbnVsbGEgbG9ib3J0aXMgc2NlbGVyaXNxdWUgaW4gc2l0IGFtZXQgZW5pbS4KTG9yZW0gaXBzdW0gZG9sb3Igc2l0IGFtZXQsIGNvbnNlY3RldHVyIGFkaXBpc2NpbmcgZWxpdC4gSW50ZWdlciB2aXRhZSBlcmF0IGFjY3Vtc2FuIHF1YW0gZWxlaWZlbmQgc3VzY2lwaXQuIE51bGxhbSBmaW5pYnVzIG1pIGEgbGFjdXMgbG9ib3J0aXMgdmVoaWN1bGEuIE51bGxhIGZhY2lsaXNpLiBRdWlzcXVlIG1vbGVzdGllIG9kaW8gZXQgbnVsbGEgc2NlbGVyaXNxdWUsIGluIG1heGltdXMgdHVycGlzIHBvc3VlcmUuIFN1c3BlbmRpc3NlIG1hZ25hIHF1YW0sIGltcGVyZGlldCBhYyBkaWFtIGVnZXQsIHBoYXJldHJhIGZyaW5naWxsYSBlcm9zLiBMb3JlbSBpcHN1bSBkb2xvciBzaXQgYW1ldCwgY29uc2VjdGV0dXIgYWRpcGlzY2luZyBlbGl0LiBQcm9pbiBhYyBleCBzYXBpZW4uIFByYWVzZW50IGFjY3Vtc2FuIGNvbnNlcXVhdCBzYXBpZW4sIHZlbCBwcmV0aXVtIGxpZ3VsYSBoZW5kcmVyaXQgaW4uIEFlbmVhbiBzaXQgYW1ldCBsaWd1bGEgbmVjIGxlbyB0aW5jaWR1bnQgZWdlc3Rhcy4gTnVsbGEgdWxsYW1jb3JwZXIgZXJvcyBzZWQgcmlzdXMgdmVuZW5hdGlzLCB1dCBlbGVpZmVuZCBudW5jIHZ1bHB1dGF0ZS4gUHJhZXNlbnQgZWdlc3RhcyBuaXNpIHNlZCBxdWFtIGdyYXZpZGEsIGEgdGVtcG9yIHNlbSBpbnRlcmR1bS4gTmFtIGEgYXJjdSBuaWJoLgpJbnRlZ2VyIHZ1bHB1dGF0ZSBudW5jIGFjIGVyYXQgc29sbGljaXR1ZGluIHBvcnRhIGlkIGlkIHJpc3VzLiBGdXNjZSBuZWMgYWxpcXVhbSByaXN1cywgYXQgdGluY2lkdW50IHNhcGllbi4gU3VzcGVuZGlzc2UgZGlnbmlzc2ltLCBlcmF0IGV1IHJ1dHJ1bSBtb2xsaXMsIGxhY3VzIGxvcmVtIGxhY2luaWEgZW5pbSwgbmVjIG9ybmFyZSBuaWJoIGp1c3RvIGNvbW1vZG8gbmliaC4gUHJvaW4gdmVsaXQgbWksIGRhcGlidXMgbm9uIHRpbmNpZHVudCBpZCwgcHJldGl1bSBpbiBtZXR1cy4gTW9yYmkgZXUgcmhvbmN1cyB0b3J0b3IsIGFjIHRlbXBvciBsYWN1cy4gSW4gdmVoaWN1bGEgbm9uIHB1cnVzIGV1IGZhdWNpYnVzLiBWZXN0aWJ1bHVtIHZvbHV0cGF0IG51bmMgaWQgcGhhcmV0cmEgcG9zdWVyZS4gU2VkIHNhZ2l0dGlzIGxpZ3VsYSBpbiBmZXJtZW50dW0gdml2ZXJyYS4gQWxpcXVhbSBhbGlxdWV0IHNlZCBuaXNpIG5vbiBzb2RhbGVzLiBEdWlzIHVsbGFtY29ycGVyIHVybmEgcXVhbSwgaW4gaW1wZXJkaWV0IHVybmEgdWxsYW1jb3JwZXIgcXVpcy4gSW4gaGFjIGhhYml0YXNzZSBwbGF0ZWEgZGljdHVtc3QuCkRvbmVjIGN1cnN1cywgZmVsaXMgYSBwdWx2aW5hciB0ZW1wdXMsIGVsaXQgbWkgaGVuZHJlcml0IGZlbGlzLCBldCB2b2x1dHBhdCBlcm9zIGZlbGlzIHNlZCBsYWN1cy4gTnVsbGEgZXN0IGlwc3VtLCBtb2xlc3RpZSBzZWQgbmlzbCBpbiwgc2FnaXR0aXMgbGFvcmVldCBleC4gQ3VyYWJpdHVyIGRhcGlidXMgZWdlc3RhcyBsb2JvcnRpcy4gTW9yYmkgcHVsdmluYXIgcGxhY2VyYXQgdGVsbHVzIHNlZCBzb2xsaWNpdHVkaW4uIFV0IGZpbmlidXMgc3VzY2lwaXQgbWksIGF0IGZlcm1lbnR1bSBwdXJ1cyB0aW5jaWR1bnQgZXUuIE51bGxhIHN1c2NpcGl0IG1hZ25hIHZlbCBtYXNzYSB0aW5jaWR1bnQgbGFvcmVldCBhdCBhdCBvZGlvLiBGdXNjZSBuZWMgbWFnbmEgZXJvcy4KSW50ZXJkdW0gZXQgbWFsZXN1YWRhIGZhbWVzIGFjIGFudGUgaXBzdW0gcHJpbWlzIGluIGZhdWNpYnVzLiBOYW0gY29uZGltZW50dW0sIHZlbGl0IGRpY3R1bSBzY2VsZXJpc3F1ZSB0aW5jaWR1bnQsIGFyY3UgbGliZXJvIGZlcm1lbnR1bSBsaWJlcm8sIGxhY2luaWEgaGVuZHJlcml0IGxvcmVtIHRlbGx1cyBxdWlzIGxlY3R1cy4gRG9uZWMgcGxhY2VyYXQgc29kYWxlcyBlcm9zIHJ1dHJ1bSB0aW5jaWR1bnQuIEFsaXF1YW0gZXJhdCB2b2x1dHBhdC4gSW50ZXJkdW0gZXQgbWFsZXN1YWRhIGZhbWVzIGFjIGFudGUgaXBzdW0gcHJpbWlzIGluIGZhdWNpYnVzLiBQcmFlc2VudCBpZCBudWxsYSBhdCBqdXN0byBydXRydW0gdWx0cmljZXMuIFZlc3RpYnVsdW0gaGVuZHJlcml0IGVsaXQgZWdldCBwaGFyZXRyYSBwb3J0YS4gTnVuYyBldWlzbW9kIHZlbGl0IG51bGxhLCBhIGZhdWNpYnVzIHB1cnVzIHZlbmVuYXRpcyBzZWQuIERvbmVjIGlkIGF1Z3VlIGxvYm9ydGlzIHB1cnVzIHZlc3RpYnVsdW0gZmVybWVudHVtLiBTdXNwZW5kaXNzZSBuaWJoIG5pc2ksIG1hbGVzdWFkYSBpbiBwdWx2aW5hciBldCwgcHJldGl1bSBibGFuZGl0IHR1cnBpcy4gSW50ZXJkdW0gZXQgbWFsZXN1YWRhIGZhbWVzIGFjIGFudGUgaXBzdW0gcHJpbWlzIGluIGZhdWNpYnVzLiBFdGlhbSBhdCBtb2xsaXMgZXguIENyYXMgaW4gbnVuYyBxdWlzIGxhY3VzIGFsaXF1YW0gbGFvcmVldC4gVXQgdGluY2lkdW50IG5pc2wgYWMgc2FwaWVuIGRpY3R1bSwgaWQgc3VzY2lwaXQgZWxpdCBtYXR0aXMuIFBlbGxlbnRlc3F1ZSB0cmlzdGlxdWUgaW50ZXJkdW0gbG9ib3J0aXMu" },
};
Buffer b; buffer_build(&b);
for (unsigned int j = 0; j < ALEN(data); ++j) {
uint32_t len = 0;
uint32_t use = data[j].use > 0 ? data[j].use : strlen(data[j].plain);
Slice plain = slice_from_memory(data[j].plain, use);
Slice encoded = slice_from_string(data[j].encoded, 0);
buffer_clear(&b);
len = base64_encode(plain, &b);
Slice got_encoded = buffer_slice(&b);
ok(slice_equal(encoded, got_encoded), "Could encode %s [%d:%.*s%s]", data[j].label, plain.len, plain.len > 50 ? 50 : plain.len, plain.ptr, plain.len > 50 ? "..." : "");
ok(len == encoded.len, "For %s got %d == %d bytes while encoding", data[j].label, len, encoded.len);
buffer_clear(&b);
len = base64_decode(got_encoded, &b);
Slice got_plain = buffer_slice(&b);
ok(slice_equal(plain, got_plain), "Could decode %s [%d:%.*s%s]", data[j].label, plain.len, plain.len > 50 ? 50 : plain.len, plain.ptr, plain.len > 50 ? "..." : "");
ok(len == plain.len, "For %s got %d == %d bytes while decoding", data[j].label, len, plain.len);
}
buffer_destroy(&b);
}
int main (int argc, char* argv[]) {
(void) argc;
(void) argv;
test_base64();
done_testing();
}
| 177.618182 | 7,118 | 0.846351 |
ffddba1b997d9e5577d553ca1dd0f07856d3e724 | 1,963 | h | C | CallTraceForWeChat/CallTraceForWeChat/WeChat_Headers/EmoticonVideoInput.h | ceekay1991/CallTraceForWeChat | 5767cb6f781821b6bf9facc8c87e58e15fa88541 | [
"MIT"
] | 30 | 2020-03-22T12:30:21.000Z | 2022-02-09T08:49:13.000Z | CallTraceForWeChat/CallTraceForWeChat/WeChat_Headers/EmoticonVideoInput.h | ceekay1991/CallTraceForWeChat | 5767cb6f781821b6bf9facc8c87e58e15fa88541 | [
"MIT"
] | null | null | null | CallTraceForWeChat/CallTraceForWeChat/WeChat_Headers/EmoticonVideoInput.h | ceekay1991/CallTraceForWeChat | 5767cb6f781821b6bf9facc8c87e58e15fa88541 | [
"MIT"
] | 8 | 2020-03-22T12:30:23.000Z | 2020-09-22T04:01:47.000Z | //
// Generated by class-dump 3.5 (64 bit) (Debug version compiled Sep 17 2017 16:24:48).
//
// class-dump is Copyright (C) 1997-1998, 2000-2001, 2004-2015 by Steve Nygard.
//
#import <objc/NSObject.h>
@class AVAsset, AVAssetReader, AVAssetReaderTrackOutput, NSURL;
@protocol EmoticonVideoInputDelegate, OS_dispatch_queue;
@interface EmoticonVideoInput : NSObject
{
_Bool _restartWhenCompleted;
id <EmoticonVideoInputDelegate> _delegate;
NSURL *_url;
AVAsset *_asset;
AVAssetReader *_assetReader;
AVAssetReaderTrackOutput *_trackOutput;
NSObject<OS_dispatch_queue> *_inputQueue;
CDStruct_1b6d18a9 _currentTime;
CDStruct_1b6d18a9 _totalDuration;
}
@property(retain, nonatomic) NSObject<OS_dispatch_queue> *inputQueue; // @synthesize inputQueue=_inputQueue;
@property(retain, nonatomic) AVAssetReaderTrackOutput *trackOutput; // @synthesize trackOutput=_trackOutput;
@property(retain, nonatomic) AVAssetReader *assetReader; // @synthesize assetReader=_assetReader;
@property(retain, nonatomic) AVAsset *asset; // @synthesize asset=_asset;
@property(retain, nonatomic) NSURL *url; // @synthesize url=_url;
@property(nonatomic) CDStruct_1b6d18a9 totalDuration; // @synthesize totalDuration=_totalDuration;
@property(nonatomic) CDStruct_1b6d18a9 currentTime; // @synthesize currentTime=_currentTime;
@property(nonatomic) _Bool restartWhenCompleted; // @synthesize restartWhenCompleted=_restartWhenCompleted;
@property(nonatomic) __weak id <EmoticonVideoInputDelegate> delegate; // @synthesize delegate=_delegate;
- (void).cxx_destruct;
- (void)destorySampleBuffer:(struct opaqueCMSampleBuffer *)arg1;
- (struct opaqueCMSampleBuffer *)getVideoFrameSyncAtTime:(CDStruct_1b6d18a9)arg1;
- (void)readVideoFrameAtTime:(CDStruct_1b6d18a9)arg1;
- (void)readNextVideoFrameWithSkipFrame:(long long)arg1;
- (void)readNextVideoFrame;
- (void)reset;
- (_Bool)beginReading;
- (id)initWithFilePath:(id)arg1 inputQueue:(id)arg2;
@end
| 42.673913 | 108 | 0.788589 |
03fdac33c8d0bc587a37eed8b95ca5c2b18baf3d | 158 | h | C | src/TempFile.h | binarte/Tezuka | d461fbeb9b8669b842b583d75cd0a0f3e76bc598 | [
"BSD-3-Clause"
] | null | null | null | src/TempFile.h | binarte/Tezuka | d461fbeb9b8669b842b583d75cd0a0f3e76bc598 | [
"BSD-3-Clause"
] | null | null | null | src/TempFile.h | binarte/Tezuka | d461fbeb9b8669b842b583d75cd0a0f3e76bc598 | [
"BSD-3-Clause"
] | null | null | null | /*
* TempFile.h
*
* Created on: 7 de jul de 2019
* Author: jack
*/
#ifndef SRC_TEMPFILE_H_
#define SRC_TEMPFILE_H_
#endif /* SRC_TEMPFILE_H_ */
| 12.153846 | 32 | 0.64557 |
9ecab5770d0b8f12a0db4c0ef6f32ef75ce0f453 | 111,898 | c | C | videocodec/libvpx_internal/libvpx/vp9/encoder/vp9_onyx_if.c | Omegaphora/hardware_intel_common_omx-components | 2dc257bd12d2604f5bac67d039e2b7e53c255ac9 | [
"Apache-2.0"
] | 1 | 2015-10-28T18:54:21.000Z | 2015-10-28T18:54:21.000Z | videocodec/libvpx_internal/libvpx/vp9/encoder/vp9_onyx_if.c | Omegaphora/hardware_intel_common_omx-components | 2dc257bd12d2604f5bac67d039e2b7e53c255ac9 | [
"Apache-2.0"
] | null | null | null | videocodec/libvpx_internal/libvpx/vp9/encoder/vp9_onyx_if.c | Omegaphora/hardware_intel_common_omx-components | 2dc257bd12d2604f5bac67d039e2b7e53c255ac9 | [
"Apache-2.0"
] | 4 | 2017-02-21T13:59:45.000Z | 2019-02-24T09:56:57.000Z | /*
* Copyright (c) 2010 The WebM project authors. All Rights Reserved.
*
* Use of this source code is governed by a BSD-style license
* that can be found in the LICENSE file in the root of the source
* tree. An additional intellectual property rights grant can be found
* in the file PATENTS. All contributing project authors may
* be found in the AUTHORS file in the root of the source tree.
*/
#include <math.h>
#include <stdio.h>
#include <limits.h>
#include "./vpx_config.h"
#include "./vpx_scale_rtcd.h"
#include "vpx/internal/vpx_psnr.h"
#include "vpx_ports/vpx_timer.h"
#include "vp9/common/vp9_alloccommon.h"
#include "vp9/common/vp9_filter.h"
#include "vp9/common/vp9_idct.h"
#if CONFIG_VP9_POSTPROC
#include "vp9/common/vp9_postproc.h"
#endif
#include "vp9/common/vp9_reconinter.h"
#include "vp9/common/vp9_systemdependent.h"
#include "vp9/common/vp9_tile_common.h"
#include "vp9/encoder/vp9_aq_complexity.h"
#include "vp9/encoder/vp9_aq_cyclicrefresh.h"
#include "vp9/encoder/vp9_aq_variance.h"
#include "vp9/encoder/vp9_bitstream.h"
#include "vp9/encoder/vp9_encodeframe.h"
#include "vp9/encoder/vp9_encodemv.h"
#include "vp9/encoder/vp9_firstpass.h"
#include "vp9/encoder/vp9_mbgraph.h"
#include "vp9/encoder/vp9_onyx_int.h"
#include "vp9/encoder/vp9_picklpf.h"
#include "vp9/encoder/vp9_ratectrl.h"
#include "vp9/encoder/vp9_rdopt.h"
#include "vp9/encoder/vp9_segmentation.h"
#include "vp9/encoder/vp9_speed_features.h"
#include "vp9/encoder/vp9_temporal_filter.h"
#include "vp9/encoder/vp9_resize.h"
#include "vp9/encoder/vp9_svc_layercontext.h"
void vp9_coef_tree_initialize();
#define DEFAULT_INTERP_FILTER SWITCHABLE
#define SHARP_FILTER_QTHRESH 0 /* Q threshold for 8-tap sharp filter */
#define ALTREF_HIGH_PRECISION_MV 1 // Whether to use high precision mv
// for altref computation.
#define HIGH_PRECISION_MV_QTHRESH 200 // Q threshold for high precision
// mv. Choose a very high value for
// now so that HIGH_PRECISION is always
// chosen.
// Max rate target for 1080P and below encodes under normal circumstances
// (1920 * 1080 / (16 * 16)) * MAX_MB_RATE bits per MB
#define MAX_MB_RATE 250
#define MAXRATE_1080P 2025000
#if CONFIG_INTERNAL_STATS
extern double vp9_calc_ssim(YV12_BUFFER_CONFIG *source,
YV12_BUFFER_CONFIG *dest, int lumamask,
double *weight);
extern double vp9_calc_ssimg(YV12_BUFFER_CONFIG *source,
YV12_BUFFER_CONFIG *dest, double *ssim_y,
double *ssim_u, double *ssim_v);
#endif
// #define OUTPUT_YUV_REC
#ifdef OUTPUT_YUV_SRC
FILE *yuv_file;
#endif
#ifdef OUTPUT_YUV_REC
FILE *yuv_rec_file;
#endif
#if 0
FILE *framepsnr;
FILE *kf_list;
FILE *keyfile;
#endif
void vp9_init_quantizer(VP9_COMP *cpi);
static INLINE void Scale2Ratio(VPX_SCALING mode, int *hr, int *hs) {
switch (mode) {
case NORMAL:
*hr = 1;
*hs = 1;
break;
case FOURFIVE:
*hr = 4;
*hs = 5;
break;
case THREEFIVE:
*hr = 3;
*hs = 5;
break;
case ONETWO:
*hr = 1;
*hs = 2;
break;
default:
*hr = 1;
*hs = 1;
assert(0);
break;
}
}
static void set_high_precision_mv(VP9_COMP *cpi, int allow_high_precision_mv) {
MACROBLOCK *const mb = &cpi->mb;
cpi->common.allow_high_precision_mv = allow_high_precision_mv;
if (cpi->common.allow_high_precision_mv) {
mb->mvcost = mb->nmvcost_hp;
mb->mvsadcost = mb->nmvsadcost_hp;
} else {
mb->mvcost = mb->nmvcost;
mb->mvsadcost = mb->nmvsadcost;
}
}
static void setup_key_frame(VP9_COMP *cpi) {
vp9_setup_past_independence(&cpi->common);
// All buffers are implicitly updated on key frames.
cpi->refresh_golden_frame = 1;
cpi->refresh_alt_ref_frame = 1;
}
static void setup_inter_frame(VP9_COMMON *cm) {
if (cm->error_resilient_mode || cm->intra_only)
vp9_setup_past_independence(cm);
assert(cm->frame_context_idx < FRAME_CONTEXTS);
cm->fc = cm->frame_contexts[cm->frame_context_idx];
}
void vp9_initialize_enc() {
static int init_done = 0;
if (!init_done) {
vp9_init_neighbors();
vp9_init_quant_tables();
vp9_coef_tree_initialize();
vp9_tokenize_initialize();
vp9_init_me_luts();
vp9_rc_init_minq_luts();
vp9_entropy_mv_init();
vp9_entropy_mode_init();
init_done = 1;
}
}
static void dealloc_compressor_data(VP9_COMP *cpi) {
VP9_COMMON *const cm = &cpi->common;
int i;
// Delete sementation map
vpx_free(cpi->segmentation_map);
cpi->segmentation_map = NULL;
vpx_free(cm->last_frame_seg_map);
cm->last_frame_seg_map = NULL;
vpx_free(cpi->coding_context.last_frame_seg_map_copy);
cpi->coding_context.last_frame_seg_map_copy = NULL;
vpx_free(cpi->complexity_map);
cpi->complexity_map = NULL;
vp9_cyclic_refresh_free(cpi->cyclic_refresh);
cpi->cyclic_refresh = NULL;
vpx_free(cpi->active_map);
cpi->active_map = NULL;
vp9_free_frame_buffers(cm);
vp9_free_frame_buffer(&cpi->last_frame_uf);
vp9_free_frame_buffer(&cpi->scaled_source);
vp9_free_frame_buffer(&cpi->scaled_last_source);
vp9_free_frame_buffer(&cpi->alt_ref_buffer);
vp9_lookahead_destroy(cpi->lookahead);
vpx_free(cpi->tok);
cpi->tok = 0;
// Activity mask based per mb zbin adjustments
vpx_free(cpi->mb_activity_map);
cpi->mb_activity_map = 0;
vpx_free(cpi->mb_norm_activity_map);
cpi->mb_norm_activity_map = 0;
for (i = 0; i < cpi->svc.number_spatial_layers; ++i) {
LAYER_CONTEXT *const lc = &cpi->svc.layer_context[i];
vpx_free(lc->rc_twopass_stats_in.buf);
lc->rc_twopass_stats_in.buf = NULL;
lc->rc_twopass_stats_in.sz = 0;
}
}
// Computes a q delta (in "q index" terms) to get from a starting q value
// to a target q value
int vp9_compute_qdelta(const VP9_COMP *cpi, double qstart, double qtarget) {
const RATE_CONTROL *const rc = &cpi->rc;
int start_index = rc->worst_quality;
int target_index = rc->worst_quality;
int i;
// Convert the average q value to an index.
for (i = rc->best_quality; i < rc->worst_quality; ++i) {
start_index = i;
if (vp9_convert_qindex_to_q(i) >= qstart)
break;
}
// Convert the q target to an index
for (i = rc->best_quality; i < rc->worst_quality; ++i) {
target_index = i;
if (vp9_convert_qindex_to_q(i) >= qtarget)
break;
}
return target_index - start_index;
}
// Computes a q delta (in "q index" terms) to get from a starting q value
// to a value that should equate to the given rate ratio.
int vp9_compute_qdelta_by_rate(VP9_COMP *cpi, int qindex,
double rate_target_ratio) {
const FRAME_TYPE frame_type = cpi->common.frame_type;
const RATE_CONTROL *const rc = &cpi->rc;
int target_index = rc->worst_quality;
int i;
// Look up the current projected bits per block for the base index
const int base_bits_per_mb = vp9_rc_bits_per_mb(frame_type, qindex, 1.0);
// Find the target bits per mb based on the base value and given ratio.
const int target_bits_per_mb = (int)(rate_target_ratio * base_bits_per_mb);
// Convert the q target to an index
for (i = rc->best_quality; i < rc->worst_quality; ++i) {
target_index = i;
if (vp9_rc_bits_per_mb(frame_type, i, 1.0) <= target_bits_per_mb )
break;
}
return target_index - qindex;
}
static void configure_static_seg_features(VP9_COMP *cpi) {
VP9_COMMON *const cm = &cpi->common;
const RATE_CONTROL *const rc = &cpi->rc;
struct segmentation *const seg = &cm->seg;
int high_q = (int)(rc->avg_q > 48.0);
int qi_delta;
// Disable and clear down for KF
if (cm->frame_type == KEY_FRAME) {
// Clear down the global segmentation map
vpx_memset(cpi->segmentation_map, 0, cm->mi_rows * cm->mi_cols);
seg->update_map = 0;
seg->update_data = 0;
cpi->static_mb_pct = 0;
// Disable segmentation
vp9_disable_segmentation(seg);
// Clear down the segment features.
vp9_clearall_segfeatures(seg);
} else if (cpi->refresh_alt_ref_frame) {
// If this is an alt ref frame
// Clear down the global segmentation map
vpx_memset(cpi->segmentation_map, 0, cm->mi_rows * cm->mi_cols);
seg->update_map = 0;
seg->update_data = 0;
cpi->static_mb_pct = 0;
// Disable segmentation and individual segment features by default
vp9_disable_segmentation(seg);
vp9_clearall_segfeatures(seg);
// Scan frames from current to arf frame.
// This function re-enables segmentation if appropriate.
vp9_update_mbgraph_stats(cpi);
// If segmentation was enabled set those features needed for the
// arf itself.
if (seg->enabled) {
seg->update_map = 1;
seg->update_data = 1;
qi_delta = vp9_compute_qdelta(cpi, rc->avg_q, rc->avg_q * 0.875);
vp9_set_segdata(seg, 1, SEG_LVL_ALT_Q, qi_delta - 2);
vp9_set_segdata(seg, 1, SEG_LVL_ALT_LF, -2);
vp9_enable_segfeature(seg, 1, SEG_LVL_ALT_Q);
vp9_enable_segfeature(seg, 1, SEG_LVL_ALT_LF);
// Where relevant assume segment data is delta data
seg->abs_delta = SEGMENT_DELTADATA;
}
} else if (seg->enabled) {
// All other frames if segmentation has been enabled
// First normal frame in a valid gf or alt ref group
if (rc->frames_since_golden == 0) {
// Set up segment features for normal frames in an arf group
if (rc->source_alt_ref_active) {
seg->update_map = 0;
seg->update_data = 1;
seg->abs_delta = SEGMENT_DELTADATA;
qi_delta = vp9_compute_qdelta(cpi, rc->avg_q, rc->avg_q * 1.125);
vp9_set_segdata(seg, 1, SEG_LVL_ALT_Q, qi_delta + 2);
vp9_enable_segfeature(seg, 1, SEG_LVL_ALT_Q);
vp9_set_segdata(seg, 1, SEG_LVL_ALT_LF, -2);
vp9_enable_segfeature(seg, 1, SEG_LVL_ALT_LF);
// Segment coding disabled for compred testing
if (high_q || (cpi->static_mb_pct == 100)) {
vp9_set_segdata(seg, 1, SEG_LVL_REF_FRAME, ALTREF_FRAME);
vp9_enable_segfeature(seg, 1, SEG_LVL_REF_FRAME);
vp9_enable_segfeature(seg, 1, SEG_LVL_SKIP);
}
} else {
// Disable segmentation and clear down features if alt ref
// is not active for this group
vp9_disable_segmentation(seg);
vpx_memset(cpi->segmentation_map, 0, cm->mi_rows * cm->mi_cols);
seg->update_map = 0;
seg->update_data = 0;
vp9_clearall_segfeatures(seg);
}
} else if (rc->is_src_frame_alt_ref) {
// Special case where we are coding over the top of a previous
// alt ref frame.
// Segment coding disabled for compred testing
// Enable ref frame features for segment 0 as well
vp9_enable_segfeature(seg, 0, SEG_LVL_REF_FRAME);
vp9_enable_segfeature(seg, 1, SEG_LVL_REF_FRAME);
// All mbs should use ALTREF_FRAME
vp9_clear_segdata(seg, 0, SEG_LVL_REF_FRAME);
vp9_set_segdata(seg, 0, SEG_LVL_REF_FRAME, ALTREF_FRAME);
vp9_clear_segdata(seg, 1, SEG_LVL_REF_FRAME);
vp9_set_segdata(seg, 1, SEG_LVL_REF_FRAME, ALTREF_FRAME);
// Skip all MBs if high Q (0,0 mv and skip coeffs)
if (high_q) {
vp9_enable_segfeature(seg, 0, SEG_LVL_SKIP);
vp9_enable_segfeature(seg, 1, SEG_LVL_SKIP);
}
// Enable data update
seg->update_data = 1;
} else {
// All other frames.
// No updates.. leave things as they are.
seg->update_map = 0;
seg->update_data = 0;
}
}
}
// DEBUG: Print out the segment id of each MB in the current frame.
static void print_seg_map(VP9_COMP *cpi) {
VP9_COMMON *cm = &cpi->common;
int row, col;
int map_index = 0;
FILE *statsfile = fopen("segmap.stt", "a");
fprintf(statsfile, "%10d\n", cm->current_video_frame);
for (row = 0; row < cpi->common.mi_rows; row++) {
for (col = 0; col < cpi->common.mi_cols; col++) {
fprintf(statsfile, "%10d", cpi->segmentation_map[map_index]);
map_index++;
}
fprintf(statsfile, "\n");
}
fprintf(statsfile, "\n");
fclose(statsfile);
}
static void update_reference_segmentation_map(VP9_COMP *cpi) {
VP9_COMMON *const cm = &cpi->common;
MODE_INFO **mi_8x8_ptr = cm->mi_grid_visible;
uint8_t *cache_ptr = cm->last_frame_seg_map;
int row, col;
for (row = 0; row < cm->mi_rows; row++) {
MODE_INFO **mi_8x8 = mi_8x8_ptr;
uint8_t *cache = cache_ptr;
for (col = 0; col < cm->mi_cols; col++, mi_8x8++, cache++)
cache[0] = mi_8x8[0]->mbmi.segment_id;
mi_8x8_ptr += cm->mi_stride;
cache_ptr += cm->mi_cols;
}
}
static int is_slowest_mode(int mode) {
return (mode == MODE_SECONDPASS_BEST || mode == MODE_BESTQUALITY);
}
static void set_rd_speed_thresholds(VP9_COMP *cpi) {
int i;
// Set baseline threshold values
for (i = 0; i < MAX_MODES; ++i)
cpi->rd_thresh_mult[i] = is_slowest_mode(cpi->oxcf.mode) ? -500 : 0;
cpi->rd_thresh_mult[THR_NEARESTMV] = 0;
cpi->rd_thresh_mult[THR_NEARESTG] = 0;
cpi->rd_thresh_mult[THR_NEARESTA] = 0;
cpi->rd_thresh_mult[THR_DC] += 1000;
cpi->rd_thresh_mult[THR_NEWMV] += 1000;
cpi->rd_thresh_mult[THR_NEWA] += 1000;
cpi->rd_thresh_mult[THR_NEWG] += 1000;
cpi->rd_thresh_mult[THR_NEARMV] += 1000;
cpi->rd_thresh_mult[THR_NEARA] += 1000;
cpi->rd_thresh_mult[THR_COMP_NEARESTLA] += 1000;
cpi->rd_thresh_mult[THR_COMP_NEARESTGA] += 1000;
cpi->rd_thresh_mult[THR_TM] += 1000;
cpi->rd_thresh_mult[THR_COMP_NEARLA] += 1500;
cpi->rd_thresh_mult[THR_COMP_NEWLA] += 2000;
cpi->rd_thresh_mult[THR_NEARG] += 1000;
cpi->rd_thresh_mult[THR_COMP_NEARGA] += 1500;
cpi->rd_thresh_mult[THR_COMP_NEWGA] += 2000;
cpi->rd_thresh_mult[THR_ZEROMV] += 2000;
cpi->rd_thresh_mult[THR_ZEROG] += 2000;
cpi->rd_thresh_mult[THR_ZEROA] += 2000;
cpi->rd_thresh_mult[THR_COMP_ZEROLA] += 2500;
cpi->rd_thresh_mult[THR_COMP_ZEROGA] += 2500;
cpi->rd_thresh_mult[THR_H_PRED] += 2000;
cpi->rd_thresh_mult[THR_V_PRED] += 2000;
cpi->rd_thresh_mult[THR_D45_PRED ] += 2500;
cpi->rd_thresh_mult[THR_D135_PRED] += 2500;
cpi->rd_thresh_mult[THR_D117_PRED] += 2500;
cpi->rd_thresh_mult[THR_D153_PRED] += 2500;
cpi->rd_thresh_mult[THR_D207_PRED] += 2500;
cpi->rd_thresh_mult[THR_D63_PRED] += 2500;
/* disable frame modes if flags not set */
if (!(cpi->ref_frame_flags & VP9_LAST_FLAG)) {
cpi->rd_thresh_mult[THR_NEWMV ] = INT_MAX;
cpi->rd_thresh_mult[THR_NEARESTMV] = INT_MAX;
cpi->rd_thresh_mult[THR_ZEROMV ] = INT_MAX;
cpi->rd_thresh_mult[THR_NEARMV ] = INT_MAX;
}
if (!(cpi->ref_frame_flags & VP9_GOLD_FLAG)) {
cpi->rd_thresh_mult[THR_NEARESTG ] = INT_MAX;
cpi->rd_thresh_mult[THR_ZEROG ] = INT_MAX;
cpi->rd_thresh_mult[THR_NEARG ] = INT_MAX;
cpi->rd_thresh_mult[THR_NEWG ] = INT_MAX;
}
if (!(cpi->ref_frame_flags & VP9_ALT_FLAG)) {
cpi->rd_thresh_mult[THR_NEARESTA ] = INT_MAX;
cpi->rd_thresh_mult[THR_ZEROA ] = INT_MAX;
cpi->rd_thresh_mult[THR_NEARA ] = INT_MAX;
cpi->rd_thresh_mult[THR_NEWA ] = INT_MAX;
}
if ((cpi->ref_frame_flags & (VP9_LAST_FLAG | VP9_ALT_FLAG)) !=
(VP9_LAST_FLAG | VP9_ALT_FLAG)) {
cpi->rd_thresh_mult[THR_COMP_ZEROLA ] = INT_MAX;
cpi->rd_thresh_mult[THR_COMP_NEARESTLA] = INT_MAX;
cpi->rd_thresh_mult[THR_COMP_NEARLA ] = INT_MAX;
cpi->rd_thresh_mult[THR_COMP_NEWLA ] = INT_MAX;
}
if ((cpi->ref_frame_flags & (VP9_GOLD_FLAG | VP9_ALT_FLAG)) !=
(VP9_GOLD_FLAG | VP9_ALT_FLAG)) {
cpi->rd_thresh_mult[THR_COMP_ZEROGA ] = INT_MAX;
cpi->rd_thresh_mult[THR_COMP_NEARESTGA] = INT_MAX;
cpi->rd_thresh_mult[THR_COMP_NEARGA ] = INT_MAX;
cpi->rd_thresh_mult[THR_COMP_NEWGA ] = INT_MAX;
}
}
static void set_rd_speed_thresholds_sub8x8(VP9_COMP *cpi) {
const SPEED_FEATURES *const sf = &cpi->sf;
int i;
for (i = 0; i < MAX_REFS; ++i)
cpi->rd_thresh_mult_sub8x8[i] = is_slowest_mode(cpi->oxcf.mode) ? -500 : 0;
cpi->rd_thresh_mult_sub8x8[THR_LAST] += 2500;
cpi->rd_thresh_mult_sub8x8[THR_GOLD] += 2500;
cpi->rd_thresh_mult_sub8x8[THR_ALTR] += 2500;
cpi->rd_thresh_mult_sub8x8[THR_INTRA] += 2500;
cpi->rd_thresh_mult_sub8x8[THR_COMP_LA] += 4500;
cpi->rd_thresh_mult_sub8x8[THR_COMP_GA] += 4500;
// Check for masked out split cases.
for (i = 0; i < MAX_REFS; i++)
if (sf->disable_split_mask & (1 << i))
cpi->rd_thresh_mult_sub8x8[i] = INT_MAX;
// disable mode test if frame flag is not set
if (!(cpi->ref_frame_flags & VP9_LAST_FLAG))
cpi->rd_thresh_mult_sub8x8[THR_LAST] = INT_MAX;
if (!(cpi->ref_frame_flags & VP9_GOLD_FLAG))
cpi->rd_thresh_mult_sub8x8[THR_GOLD] = INT_MAX;
if (!(cpi->ref_frame_flags & VP9_ALT_FLAG))
cpi->rd_thresh_mult_sub8x8[THR_ALTR] = INT_MAX;
if ((cpi->ref_frame_flags & (VP9_LAST_FLAG | VP9_ALT_FLAG)) !=
(VP9_LAST_FLAG | VP9_ALT_FLAG))
cpi->rd_thresh_mult_sub8x8[THR_COMP_LA] = INT_MAX;
if ((cpi->ref_frame_flags & (VP9_GOLD_FLAG | VP9_ALT_FLAG)) !=
(VP9_GOLD_FLAG | VP9_ALT_FLAG))
cpi->rd_thresh_mult_sub8x8[THR_COMP_GA] = INT_MAX;
}
static void set_speed_features(VP9_COMP *cpi) {
#if CONFIG_INTERNAL_STATS
int i;
for (i = 0; i < MAX_MODES; ++i)
cpi->mode_chosen_counts[i] = 0;
#endif
vp9_set_speed_features(cpi);
// Set rd thresholds based on mode and speed setting
set_rd_speed_thresholds(cpi);
set_rd_speed_thresholds_sub8x8(cpi);
cpi->mb.fwd_txm4x4 = vp9_fdct4x4;
if (cpi->oxcf.lossless || cpi->mb.e_mbd.lossless) {
cpi->mb.fwd_txm4x4 = vp9_fwht4x4;
}
}
static void alloc_raw_frame_buffers(VP9_COMP *cpi) {
VP9_COMMON *cm = &cpi->common;
const VP9_CONFIG *oxcf = &cpi->oxcf;
cpi->lookahead = vp9_lookahead_init(oxcf->width, oxcf->height,
cm->subsampling_x, cm->subsampling_y,
oxcf->lag_in_frames);
if (!cpi->lookahead)
vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
"Failed to allocate lag buffers");
if (vp9_realloc_frame_buffer(&cpi->alt_ref_buffer,
oxcf->width, oxcf->height,
cm->subsampling_x, cm->subsampling_y,
VP9_ENC_BORDER_IN_PIXELS, NULL, NULL, NULL))
vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
"Failed to allocate altref buffer");
}
void vp9_alloc_compressor_data(VP9_COMP *cpi) {
VP9_COMMON *cm = &cpi->common;
if (vp9_alloc_frame_buffers(cm, cm->width, cm->height))
vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
"Failed to allocate frame buffers");
if (vp9_alloc_frame_buffer(&cpi->last_frame_uf,
cm->width, cm->height,
cm->subsampling_x, cm->subsampling_y,
VP9_ENC_BORDER_IN_PIXELS))
vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
"Failed to allocate last frame buffer");
if (vp9_alloc_frame_buffer(&cpi->scaled_source,
cm->width, cm->height,
cm->subsampling_x, cm->subsampling_y,
VP9_ENC_BORDER_IN_PIXELS))
vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
"Failed to allocate scaled source buffer");
if (vp9_alloc_frame_buffer(&cpi->scaled_last_source,
cm->width, cm->height,
cm->subsampling_x, cm->subsampling_y,
VP9_ENC_BORDER_IN_PIXELS))
vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
"Failed to allocate scaled last source buffer");
vpx_free(cpi->tok);
{
unsigned int tokens = get_token_alloc(cm->mb_rows, cm->mb_cols);
CHECK_MEM_ERROR(cm, cpi->tok, vpx_calloc(tokens, sizeof(*cpi->tok)));
}
vpx_free(cpi->mb_activity_map);
CHECK_MEM_ERROR(cm, cpi->mb_activity_map,
vpx_calloc(sizeof(unsigned int),
cm->mb_rows * cm->mb_cols));
vpx_free(cpi->mb_norm_activity_map);
CHECK_MEM_ERROR(cm, cpi->mb_norm_activity_map,
vpx_calloc(sizeof(unsigned int),
cm->mb_rows * cm->mb_cols));
}
static void update_frame_size(VP9_COMP *cpi) {
VP9_COMMON *const cm = &cpi->common;
MACROBLOCKD *const xd = &cpi->mb.e_mbd;
vp9_update_frame_size(cm);
// Update size of buffers local to this frame
if (vp9_realloc_frame_buffer(&cpi->last_frame_uf,
cm->width, cm->height,
cm->subsampling_x, cm->subsampling_y,
VP9_ENC_BORDER_IN_PIXELS, NULL, NULL, NULL))
vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
"Failed to reallocate last frame buffer");
if (vp9_realloc_frame_buffer(&cpi->scaled_source,
cm->width, cm->height,
cm->subsampling_x, cm->subsampling_y,
VP9_ENC_BORDER_IN_PIXELS, NULL, NULL, NULL))
vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
"Failed to reallocate scaled source buffer");
if (vp9_realloc_frame_buffer(&cpi->scaled_last_source,
cm->width, cm->height,
cm->subsampling_x, cm->subsampling_y,
VP9_ENC_BORDER_IN_PIXELS, NULL, NULL, NULL))
vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
"Failed to reallocate scaled last source buffer");
{
int y_stride = cpi->scaled_source.y_stride;
if (cpi->sf.search_method == NSTEP) {
vp9_init3smotion_compensation(&cpi->mb, y_stride);
} else if (cpi->sf.search_method == DIAMOND) {
vp9_init_dsmotion_compensation(&cpi->mb, y_stride);
}
}
init_macroblockd(cm, xd);
}
// Table that converts 0-63 Q range values passed in outside to the Qindex
// range used internally.
const int q_trans[] = {
0, 4, 8, 12, 16, 20, 24, 28,
32, 36, 40, 44, 48, 52, 56, 60,
64, 68, 72, 76, 80, 84, 88, 92,
96, 100, 104, 108, 112, 116, 120, 124,
128, 132, 136, 140, 144, 148, 152, 156,
160, 164, 168, 172, 176, 180, 184, 188,
192, 196, 200, 204, 208, 212, 216, 220,
224, 228, 232, 236, 240, 244, 249, 255,
};
int vp9_reverse_trans(int x) {
int i;
for (i = 0; i < 64; i++)
if (q_trans[i] >= x)
return i;
return 63;
};
void vp9_new_framerate(VP9_COMP *cpi, double framerate) {
VP9_COMMON *const cm = &cpi->common;
RATE_CONTROL *const rc = &cpi->rc;
VP9_CONFIG *const oxcf = &cpi->oxcf;
int vbr_max_bits;
oxcf->framerate = framerate < 0.1 ? 30 : framerate;
cpi->output_framerate = cpi->oxcf.framerate;
rc->av_per_frame_bandwidth = (int)(oxcf->target_bandwidth /
cpi->output_framerate);
rc->min_frame_bandwidth = (int)(rc->av_per_frame_bandwidth *
oxcf->two_pass_vbrmin_section / 100);
rc->min_frame_bandwidth = MAX(rc->min_frame_bandwidth, FRAME_OVERHEAD_BITS);
// A maximum bitrate for a frame is defined.
// The baseline for this aligns with HW implementations that
// can support decode of 1080P content up to a bitrate of MAX_MB_RATE bits
// per 16x16 MB (averaged over a frame). However this limit is extended if
// a very high rate is given on the command line or the the rate cannnot
// be acheived because of a user specificed max q (e.g. when the user
// specifies lossless encode.
//
vbr_max_bits = (int)(((int64_t)rc->av_per_frame_bandwidth *
oxcf->two_pass_vbrmax_section) / 100);
rc->max_frame_bandwidth = MAX(MAX((cm->MBs * MAX_MB_RATE), MAXRATE_1080P),
vbr_max_bits);
// Set Maximum gf/arf interval
rc->max_gf_interval = 16;
// Extended interval for genuinely static scenes
rc->static_scene_max_gf_interval = cpi->key_frame_frequency >> 1;
// Special conditions when alt ref frame enabled in lagged compress mode
if (oxcf->play_alternate && oxcf->lag_in_frames) {
if (rc->max_gf_interval > oxcf->lag_in_frames - 1)
rc->max_gf_interval = oxcf->lag_in_frames - 1;
if (rc->static_scene_max_gf_interval > oxcf->lag_in_frames - 1)
rc->static_scene_max_gf_interval = oxcf->lag_in_frames - 1;
}
if (rc->max_gf_interval > rc->static_scene_max_gf_interval)
rc->max_gf_interval = rc->static_scene_max_gf_interval;
}
int64_t vp9_rescale(int64_t val, int64_t num, int denom) {
int64_t llnum = num;
int64_t llden = denom;
int64_t llval = val;
return (llval * llnum / llden);
}
static void set_tile_limits(VP9_COMP *cpi) {
VP9_COMMON *const cm = &cpi->common;
int min_log2_tile_cols, max_log2_tile_cols;
vp9_get_tile_n_bits(cm->mi_cols, &min_log2_tile_cols, &max_log2_tile_cols);
cm->log2_tile_cols = clamp(cpi->oxcf.tile_columns,
min_log2_tile_cols, max_log2_tile_cols);
cm->log2_tile_rows = cpi->oxcf.tile_rows;
}
static void init_rate_control(const VP9_CONFIG *oxcf, int pass,
RATE_CONTROL *rc) {
if (pass == 0 && oxcf->end_usage == USAGE_STREAM_FROM_SERVER) {
rc->avg_frame_qindex[0] = oxcf->worst_allowed_q;
rc->avg_frame_qindex[1] = oxcf->worst_allowed_q;
rc->avg_frame_qindex[2] = oxcf->worst_allowed_q;
} else {
rc->avg_frame_qindex[0] = (oxcf->worst_allowed_q +
oxcf->best_allowed_q) / 2;
rc->avg_frame_qindex[1] = (oxcf->worst_allowed_q +
oxcf->best_allowed_q) / 2;
rc->avg_frame_qindex[2] = (oxcf->worst_allowed_q +
oxcf->best_allowed_q) / 2;
}
rc->last_q[0] = oxcf->best_allowed_q;
rc->last_q[1] = oxcf->best_allowed_q;
rc->last_q[2] = oxcf->best_allowed_q;
rc->buffer_level = oxcf->starting_buffer_level;
rc->bits_off_target = oxcf->starting_buffer_level;
rc->rolling_target_bits = rc->av_per_frame_bandwidth;
rc->rolling_actual_bits = rc->av_per_frame_bandwidth;
rc->long_rolling_target_bits = rc->av_per_frame_bandwidth;
rc->long_rolling_actual_bits = rc->av_per_frame_bandwidth;
rc->total_actual_bits = 0;
rc->total_target_vs_actual = 0;
}
static void init_config(struct VP9_COMP *cpi, VP9_CONFIG *oxcf) {
VP9_COMMON *const cm = &cpi->common;
int i;
cpi->oxcf = *oxcf;
cm->version = oxcf->version;
cm->width = oxcf->width;
cm->height = oxcf->height;
cm->subsampling_x = 0;
cm->subsampling_y = 0;
vp9_alloc_compressor_data(cpi);
// Spatial scalability.
cpi->svc.number_spatial_layers = oxcf->ss_number_layers;
// Temporal scalability.
cpi->svc.number_temporal_layers = oxcf->ts_number_layers;
if ((cpi->svc.number_temporal_layers > 1 &&
cpi->oxcf.end_usage == USAGE_STREAM_FROM_SERVER) ||
(cpi->svc.number_spatial_layers > 1 &&
cpi->oxcf.mode == MODE_SECONDPASS_BEST)) {
vp9_init_layer_context(cpi);
}
// change includes all joint functionality
vp9_change_config(cpi, oxcf);
cpi->static_mb_pct = 0;
cpi->lst_fb_idx = 0;
cpi->gld_fb_idx = 1;
cpi->alt_fb_idx = 2;
set_tile_limits(cpi);
cpi->fixed_divide[0] = 0;
for (i = 1; i < 512; i++)
cpi->fixed_divide[i] = 0x80000 / i;
}
void vp9_change_config(struct VP9_COMP *cpi, const VP9_CONFIG *oxcf) {
VP9_COMMON *const cm = &cpi->common;
RATE_CONTROL *const rc = &cpi->rc;
if (cm->version != oxcf->version)
cm->version = oxcf->version;
cpi->oxcf = *oxcf;
if (cpi->oxcf.cpu_used == -6)
cpi->oxcf.play_alternate = 0;
switch (cpi->oxcf.mode) {
// Real time and one pass deprecated in test code base
case MODE_GOODQUALITY:
cpi->pass = 0;
cpi->oxcf.cpu_used = clamp(cpi->oxcf.cpu_used, -5, 5);
break;
case MODE_BESTQUALITY:
cpi->pass = 0;
break;
case MODE_FIRSTPASS:
cpi->pass = 1;
break;
case MODE_SECONDPASS:
cpi->pass = 2;
cpi->oxcf.cpu_used = clamp(cpi->oxcf.cpu_used, -5, 5);
break;
case MODE_SECONDPASS_BEST:
cpi->pass = 2;
break;
case MODE_REALTIME:
cpi->pass = 0;
break;
}
cpi->oxcf.worst_allowed_q = q_trans[oxcf->worst_allowed_q];
cpi->oxcf.best_allowed_q = q_trans[oxcf->best_allowed_q];
cpi->oxcf.cq_level = q_trans[cpi->oxcf.cq_level];
cpi->oxcf.lossless = oxcf->lossless;
if (cpi->oxcf.lossless) {
// In lossless mode, make sure right quantizer range and correct transform
// is set.
cpi->oxcf.worst_allowed_q = 0;
cpi->oxcf.best_allowed_q = 0;
cpi->mb.e_mbd.itxm_add = vp9_iwht4x4_add;
} else {
cpi->mb.e_mbd.itxm_add = vp9_idct4x4_add;
}
rc->baseline_gf_interval = DEFAULT_GF_INTERVAL;
cpi->ref_frame_flags = VP9_ALT_FLAG | VP9_GOLD_FLAG | VP9_LAST_FLAG;
cpi->refresh_golden_frame = 0;
cpi->refresh_last_frame = 1;
cm->refresh_frame_context = 1;
cm->reset_frame_context = 0;
vp9_reset_segment_features(&cm->seg);
set_high_precision_mv(cpi, 0);
{
int i;
for (i = 0; i < MAX_SEGMENTS; i++)
cpi->segment_encode_breakout[i] = cpi->oxcf.encode_breakout;
}
cpi->encode_breakout = cpi->oxcf.encode_breakout;
// local file playback mode == really big buffer
if (cpi->oxcf.end_usage == USAGE_LOCAL_FILE_PLAYBACK) {
cpi->oxcf.starting_buffer_level = 60000;
cpi->oxcf.optimal_buffer_level = 60000;
cpi->oxcf.maximum_buffer_size = 240000;
}
// Convert target bandwidth from Kbit/s to Bit/s
cpi->oxcf.target_bandwidth *= 1000;
cpi->oxcf.starting_buffer_level =
vp9_rescale(cpi->oxcf.starting_buffer_level,
cpi->oxcf.target_bandwidth, 1000);
// Set or reset optimal and maximum buffer levels.
if (cpi->oxcf.optimal_buffer_level == 0)
cpi->oxcf.optimal_buffer_level = cpi->oxcf.target_bandwidth / 8;
else
cpi->oxcf.optimal_buffer_level =
vp9_rescale(cpi->oxcf.optimal_buffer_level,
cpi->oxcf.target_bandwidth, 1000);
if (cpi->oxcf.maximum_buffer_size == 0)
cpi->oxcf.maximum_buffer_size = cpi->oxcf.target_bandwidth / 8;
else
cpi->oxcf.maximum_buffer_size =
vp9_rescale(cpi->oxcf.maximum_buffer_size,
cpi->oxcf.target_bandwidth, 1000);
// Under a configuration change, where maximum_buffer_size may change,
// keep buffer level clipped to the maximum allowed buffer size.
rc->bits_off_target = MIN(rc->bits_off_target, cpi->oxcf.maximum_buffer_size);
rc->buffer_level = MIN(rc->buffer_level, cpi->oxcf.maximum_buffer_size);
// Set up frame rate and related parameters rate control values.
vp9_new_framerate(cpi, cpi->oxcf.framerate);
// Set absolute upper and lower quality limits
rc->worst_quality = cpi->oxcf.worst_allowed_q;
rc->best_quality = cpi->oxcf.best_allowed_q;
// active values should only be modified if out of new range
cpi->cq_target_quality = cpi->oxcf.cq_level;
cm->interp_filter = DEFAULT_INTERP_FILTER;
cm->display_width = cpi->oxcf.width;
cm->display_height = cpi->oxcf.height;
// VP8 sharpness level mapping 0-7 (vs 0-10 in general VPx dialogs)
cpi->oxcf.sharpness = MIN(7, cpi->oxcf.sharpness);
cpi->common.lf.sharpness_level = cpi->oxcf.sharpness;
if (cpi->initial_width) {
// Increasing the size of the frame beyond the first seen frame, or some
// otherwise signaled maximum size, is not supported.
// TODO(jkoleszar): exit gracefully.
assert(cm->width <= cpi->initial_width);
assert(cm->height <= cpi->initial_height);
}
update_frame_size(cpi);
if ((cpi->svc.number_temporal_layers > 1 &&
cpi->oxcf.end_usage == USAGE_STREAM_FROM_SERVER) ||
(cpi->svc.number_spatial_layers > 1 && cpi->pass == 2)) {
vp9_update_layer_context_change_config(cpi,
(int)cpi->oxcf.target_bandwidth);
}
cpi->speed = abs(cpi->oxcf.cpu_used);
// Limit on lag buffers as these are not currently dynamically allocated.
if (cpi->oxcf.lag_in_frames > MAX_LAG_BUFFERS)
cpi->oxcf.lag_in_frames = MAX_LAG_BUFFERS;
#if CONFIG_MULTIPLE_ARF
vp9_zero(cpi->alt_ref_source);
#else
cpi->alt_ref_source = NULL;
#endif
rc->is_src_frame_alt_ref = 0;
#if 0
// Experimental RD Code
cpi->frame_distortion = 0;
cpi->last_frame_distortion = 0;
#endif
set_tile_limits(cpi);
cpi->ext_refresh_frame_flags_pending = 0;
cpi->ext_refresh_frame_context_pending = 0;
}
#define M_LOG2_E 0.693147180559945309417
#define log2f(x) (log (x) / (float) M_LOG2_E)
static void cal_nmvjointsadcost(int *mvjointsadcost) {
mvjointsadcost[0] = 600;
mvjointsadcost[1] = 300;
mvjointsadcost[2] = 300;
mvjointsadcost[3] = 300;
}
static void cal_nmvsadcosts(int *mvsadcost[2]) {
int i = 1;
mvsadcost[0][0] = 0;
mvsadcost[1][0] = 0;
do {
double z = 256 * (2 * (log2f(8 * i) + .6));
mvsadcost[0][i] = (int)z;
mvsadcost[1][i] = (int)z;
mvsadcost[0][-i] = (int)z;
mvsadcost[1][-i] = (int)z;
} while (++i <= MV_MAX);
}
static void cal_nmvsadcosts_hp(int *mvsadcost[2]) {
int i = 1;
mvsadcost[0][0] = 0;
mvsadcost[1][0] = 0;
do {
double z = 256 * (2 * (log2f(8 * i) + .6));
mvsadcost[0][i] = (int)z;
mvsadcost[1][i] = (int)z;
mvsadcost[0][-i] = (int)z;
mvsadcost[1][-i] = (int)z;
} while (++i <= MV_MAX);
}
static void alloc_mode_context(VP9_COMMON *cm, int num_4x4_blk,
PICK_MODE_CONTEXT *ctx) {
int num_pix = num_4x4_blk << 4;
int i, k;
ctx->num_4x4_blk = num_4x4_blk;
CHECK_MEM_ERROR(cm, ctx->zcoeff_blk,
vpx_calloc(num_4x4_blk, sizeof(uint8_t)));
for (i = 0; i < MAX_MB_PLANE; ++i) {
for (k = 0; k < 3; ++k) {
CHECK_MEM_ERROR(cm, ctx->coeff[i][k],
vpx_memalign(16, num_pix * sizeof(int16_t)));
CHECK_MEM_ERROR(cm, ctx->qcoeff[i][k],
vpx_memalign(16, num_pix * sizeof(int16_t)));
CHECK_MEM_ERROR(cm, ctx->dqcoeff[i][k],
vpx_memalign(16, num_pix * sizeof(int16_t)));
CHECK_MEM_ERROR(cm, ctx->eobs[i][k],
vpx_memalign(16, num_pix * sizeof(uint16_t)));
ctx->coeff_pbuf[i][k] = ctx->coeff[i][k];
ctx->qcoeff_pbuf[i][k] = ctx->qcoeff[i][k];
ctx->dqcoeff_pbuf[i][k] = ctx->dqcoeff[i][k];
ctx->eobs_pbuf[i][k] = ctx->eobs[i][k];
}
}
}
static void free_mode_context(PICK_MODE_CONTEXT *ctx) {
int i, k;
vpx_free(ctx->zcoeff_blk);
ctx->zcoeff_blk = 0;
for (i = 0; i < MAX_MB_PLANE; ++i) {
for (k = 0; k < 3; ++k) {
vpx_free(ctx->coeff[i][k]);
ctx->coeff[i][k] = 0;
vpx_free(ctx->qcoeff[i][k]);
ctx->qcoeff[i][k] = 0;
vpx_free(ctx->dqcoeff[i][k]);
ctx->dqcoeff[i][k] = 0;
vpx_free(ctx->eobs[i][k]);
ctx->eobs[i][k] = 0;
}
}
}
static void init_pick_mode_context(VP9_COMP *cpi) {
int i;
VP9_COMMON *const cm = &cpi->common;
MACROBLOCK *const x = &cpi->mb;
for (i = 0; i < BLOCK_SIZES; ++i) {
const int num_4x4_w = num_4x4_blocks_wide_lookup[i];
const int num_4x4_h = num_4x4_blocks_high_lookup[i];
const int num_4x4_blk = MAX(4, num_4x4_w * num_4x4_h);
if (i < BLOCK_16X16) {
for (x->sb_index = 0; x->sb_index < 4; ++x->sb_index) {
for (x->mb_index = 0; x->mb_index < 4; ++x->mb_index) {
for (x->b_index = 0; x->b_index < 16 / num_4x4_blk; ++x->b_index) {
PICK_MODE_CONTEXT *ctx = get_block_context(x, i);
alloc_mode_context(cm, num_4x4_blk, ctx);
}
}
}
} else if (i < BLOCK_32X32) {
for (x->sb_index = 0; x->sb_index < 4; ++x->sb_index) {
for (x->mb_index = 0; x->mb_index < 64 / num_4x4_blk; ++x->mb_index) {
PICK_MODE_CONTEXT *ctx = get_block_context(x, i);
ctx->num_4x4_blk = num_4x4_blk;
alloc_mode_context(cm, num_4x4_blk, ctx);
}
}
} else if (i < BLOCK_64X64) {
for (x->sb_index = 0; x->sb_index < 256 / num_4x4_blk; ++x->sb_index) {
PICK_MODE_CONTEXT *ctx = get_block_context(x, i);
ctx->num_4x4_blk = num_4x4_blk;
alloc_mode_context(cm, num_4x4_blk, ctx);
}
} else {
PICK_MODE_CONTEXT *ctx = get_block_context(x, i);
ctx->num_4x4_blk = num_4x4_blk;
alloc_mode_context(cm, num_4x4_blk, ctx);
}
}
}
static void free_pick_mode_context(MACROBLOCK *x) {
int i;
for (i = 0; i < BLOCK_SIZES; ++i) {
const int num_4x4_w = num_4x4_blocks_wide_lookup[i];
const int num_4x4_h = num_4x4_blocks_high_lookup[i];
const int num_4x4_blk = MAX(4, num_4x4_w * num_4x4_h);
if (i < BLOCK_16X16) {
for (x->sb_index = 0; x->sb_index < 4; ++x->sb_index) {
for (x->mb_index = 0; x->mb_index < 4; ++x->mb_index) {
for (x->b_index = 0; x->b_index < 16 / num_4x4_blk; ++x->b_index) {
PICK_MODE_CONTEXT *ctx = get_block_context(x, i);
free_mode_context(ctx);
}
}
}
} else if (i < BLOCK_32X32) {
for (x->sb_index = 0; x->sb_index < 4; ++x->sb_index) {
for (x->mb_index = 0; x->mb_index < 64 / num_4x4_blk; ++x->mb_index) {
PICK_MODE_CONTEXT *ctx = get_block_context(x, i);
free_mode_context(ctx);
}
}
} else if (i < BLOCK_64X64) {
for (x->sb_index = 0; x->sb_index < 256 / num_4x4_blk; ++x->sb_index) {
PICK_MODE_CONTEXT *ctx = get_block_context(x, i);
free_mode_context(ctx);
}
} else {
PICK_MODE_CONTEXT *ctx = get_block_context(x, i);
free_mode_context(ctx);
}
}
}
VP9_COMP *vp9_create_compressor(VP9_CONFIG *oxcf) {
int i, j;
VP9_COMP *const cpi = vpx_memalign(32, sizeof(VP9_COMP));
VP9_COMMON *const cm = cpi != NULL ? &cpi->common : NULL;
RATE_CONTROL *const rc = cpi != NULL ? &cpi->rc : NULL;
if (!cm)
return NULL;
vp9_zero(*cpi);
if (setjmp(cm->error.jmp)) {
cm->error.setjmp = 0;
vp9_remove_compressor(cpi);
return 0;
}
cm->error.setjmp = 1;
CHECK_MEM_ERROR(cm, cpi->mb.ss, vpx_calloc(sizeof(search_site),
(MAX_MVSEARCH_STEPS * 8) + 1));
vp9_rtcd();
cpi->use_svc = 0;
init_config(cpi, oxcf);
init_rate_control(&cpi->oxcf, cpi->pass, &cpi->rc);
init_pick_mode_context(cpi);
cm->current_video_frame = 0;
// Set reference frame sign bias for ALTREF frame to 1 (for now)
cm->ref_frame_sign_bias[ALTREF_FRAME] = 1;
rc->baseline_gf_interval = DEFAULT_GF_INTERVAL;
cpi->gold_is_last = 0;
cpi->alt_is_last = 0;
cpi->gold_is_alt = 0;
// Create the encoder segmentation map and set all entries to 0
CHECK_MEM_ERROR(cm, cpi->segmentation_map,
vpx_calloc(cm->mi_rows * cm->mi_cols, 1));
// Create a complexity map used for rd adjustment
CHECK_MEM_ERROR(cm, cpi->complexity_map,
vpx_calloc(cm->mi_rows * cm->mi_cols, 1));
// Create a map used for cyclic background refresh.
CHECK_MEM_ERROR(cm, cpi->cyclic_refresh,
vp9_cyclic_refresh_alloc(cm->mi_rows, cm->mi_cols));
// And a place holder structure is the coding context
// for use if we want to save and restore it
CHECK_MEM_ERROR(cm, cpi->coding_context.last_frame_seg_map_copy,
vpx_calloc(cm->mi_rows * cm->mi_cols, 1));
CHECK_MEM_ERROR(cm, cpi->active_map, vpx_calloc(cm->MBs, 1));
vpx_memset(cpi->active_map, 1, cm->MBs);
cpi->active_map_enabled = 0;
for (i = 0; i < (sizeof(cpi->mbgraph_stats) /
sizeof(cpi->mbgraph_stats[0])); i++) {
CHECK_MEM_ERROR(cm, cpi->mbgraph_stats[i].mb_stats,
vpx_calloc(cm->MBs *
sizeof(*cpi->mbgraph_stats[i].mb_stats), 1));
}
/*Initialize the feed-forward activity masking.*/
cpi->activity_avg = 90 << 12;
cpi->key_frame_frequency = cpi->oxcf.key_freq;
rc->frames_since_key = 8; // Sensible default for first frame.
rc->this_key_frame_forced = 0;
rc->next_key_frame_forced = 0;
rc->source_alt_ref_pending = 0;
rc->source_alt_ref_active = 0;
cpi->refresh_alt_ref_frame = 0;
#if CONFIG_MULTIPLE_ARF
// Turn multiple ARF usage on/off. This is a quick hack for the initial test
// version. It should eventually be set via the codec API.
cpi->multi_arf_enabled = 1;
if (cpi->multi_arf_enabled) {
cpi->sequence_number = 0;
cpi->frame_coding_order_period = 0;
vp9_zero(cpi->frame_coding_order);
vp9_zero(cpi->arf_buffer_idx);
}
#endif
cpi->b_calculate_psnr = CONFIG_INTERNAL_STATS;
#if CONFIG_INTERNAL_STATS
cpi->b_calculate_ssimg = 0;
cpi->count = 0;
cpi->bytes = 0;
if (cpi->b_calculate_psnr) {
cpi->total_y = 0.0;
cpi->total_u = 0.0;
cpi->total_v = 0.0;
cpi->total = 0.0;
cpi->total_sq_error = 0;
cpi->total_samples = 0;
cpi->totalp_y = 0.0;
cpi->totalp_u = 0.0;
cpi->totalp_v = 0.0;
cpi->totalp = 0.0;
cpi->totalp_sq_error = 0;
cpi->totalp_samples = 0;
cpi->tot_recode_hits = 0;
cpi->summed_quality = 0;
cpi->summed_weights = 0;
cpi->summedp_quality = 0;
cpi->summedp_weights = 0;
}
if (cpi->b_calculate_ssimg) {
cpi->total_ssimg_y = 0;
cpi->total_ssimg_u = 0;
cpi->total_ssimg_v = 0;
cpi->total_ssimg_all = 0;
}
#endif
cpi->first_time_stamp_ever = INT64_MAX;
rc->frames_till_gf_update_due = 0;
rc->ni_av_qi = cpi->oxcf.worst_allowed_q;
rc->ni_tot_qi = 0;
rc->ni_frames = 0;
rc->tot_q = 0.0;
rc->avg_q = vp9_convert_qindex_to_q(cpi->oxcf.worst_allowed_q);
rc->rate_correction_factor = 1.0;
rc->key_frame_rate_correction_factor = 1.0;
rc->gf_rate_correction_factor = 1.0;
cal_nmvjointsadcost(cpi->mb.nmvjointsadcost);
cpi->mb.nmvcost[0] = &cpi->mb.nmvcosts[0][MV_MAX];
cpi->mb.nmvcost[1] = &cpi->mb.nmvcosts[1][MV_MAX];
cpi->mb.nmvsadcost[0] = &cpi->mb.nmvsadcosts[0][MV_MAX];
cpi->mb.nmvsadcost[1] = &cpi->mb.nmvsadcosts[1][MV_MAX];
cal_nmvsadcosts(cpi->mb.nmvsadcost);
cpi->mb.nmvcost_hp[0] = &cpi->mb.nmvcosts_hp[0][MV_MAX];
cpi->mb.nmvcost_hp[1] = &cpi->mb.nmvcosts_hp[1][MV_MAX];
cpi->mb.nmvsadcost_hp[0] = &cpi->mb.nmvsadcosts_hp[0][MV_MAX];
cpi->mb.nmvsadcost_hp[1] = &cpi->mb.nmvsadcosts_hp[1][MV_MAX];
cal_nmvsadcosts_hp(cpi->mb.nmvsadcost_hp);
#ifdef OUTPUT_YUV_SRC
yuv_file = fopen("bd.yuv", "ab");
#endif
#ifdef OUTPUT_YUV_REC
yuv_rec_file = fopen("rec.yuv", "wb");
#endif
#if 0
framepsnr = fopen("framepsnr.stt", "a");
kf_list = fopen("kf_list.stt", "w");
#endif
cpi->output_pkt_list = oxcf->output_pkt_list;
cpi->allow_encode_breakout = ENCODE_BREAKOUT_ENABLED;
if (cpi->pass == 1) {
vp9_init_first_pass(cpi);
} else if (cpi->pass == 2) {
const size_t packet_sz = sizeof(FIRSTPASS_STATS);
const int packets = (int)(oxcf->two_pass_stats_in.sz / packet_sz);
if (cpi->svc.number_spatial_layers > 1
&& cpi->svc.number_temporal_layers == 1) {
FIRSTPASS_STATS *const stats = oxcf->two_pass_stats_in.buf;
FIRSTPASS_STATS *stats_copy[VPX_SS_MAX_LAYERS] = {0};
int i;
for (i = 0; i < oxcf->ss_number_layers; ++i) {
FIRSTPASS_STATS *const last_packet_for_layer =
&stats[packets - oxcf->ss_number_layers + i];
const int layer_id = (int)last_packet_for_layer->spatial_layer_id;
const int packets_in_layer = (int)last_packet_for_layer->count + 1;
if (layer_id >= 0 && layer_id < oxcf->ss_number_layers) {
LAYER_CONTEXT *const lc = &cpi->svc.layer_context[layer_id];
vpx_free(lc->rc_twopass_stats_in.buf);
lc->rc_twopass_stats_in.sz = packets_in_layer * packet_sz;
CHECK_MEM_ERROR(cm, lc->rc_twopass_stats_in.buf,
vpx_malloc(lc->rc_twopass_stats_in.sz));
lc->twopass.stats_in_start = lc->rc_twopass_stats_in.buf;
lc->twopass.stats_in = lc->twopass.stats_in_start;
lc->twopass.stats_in_end = lc->twopass.stats_in_start
+ packets_in_layer - 1;
stats_copy[layer_id] = lc->rc_twopass_stats_in.buf;
}
}
for (i = 0; i < packets; ++i) {
const int layer_id = (int)stats[i].spatial_layer_id;
if (layer_id >= 0 && layer_id < oxcf->ss_number_layers
&& stats_copy[layer_id] != NULL) {
*stats_copy[layer_id] = stats[i];
++stats_copy[layer_id];
}
}
vp9_init_second_pass_spatial_svc(cpi);
} else {
cpi->twopass.stats_in_start = oxcf->two_pass_stats_in.buf;
cpi->twopass.stats_in = cpi->twopass.stats_in_start;
cpi->twopass.stats_in_end = &cpi->twopass.stats_in[packets - 1];
vp9_init_second_pass(cpi);
}
}
set_speed_features(cpi);
// Default rd threshold factors for mode selection
for (i = 0; i < BLOCK_SIZES; ++i) {
for (j = 0; j < MAX_MODES; ++j)
cpi->rd_thresh_freq_fact[i][j] = 32;
for (j = 0; j < MAX_REFS; ++j)
cpi->rd_thresh_freq_sub8x8[i][j] = 32;
}
#define BFP(BT, SDF, SDAF, VF, SVF, SVAF, SVFHH, SVFHV, SVFHHV, \
SDX3F, SDX8F, SDX4DF)\
cpi->fn_ptr[BT].sdf = SDF; \
cpi->fn_ptr[BT].sdaf = SDAF; \
cpi->fn_ptr[BT].vf = VF; \
cpi->fn_ptr[BT].svf = SVF; \
cpi->fn_ptr[BT].svaf = SVAF; \
cpi->fn_ptr[BT].svf_halfpix_h = SVFHH; \
cpi->fn_ptr[BT].svf_halfpix_v = SVFHV; \
cpi->fn_ptr[BT].svf_halfpix_hv = SVFHHV; \
cpi->fn_ptr[BT].sdx3f = SDX3F; \
cpi->fn_ptr[BT].sdx8f = SDX8F; \
cpi->fn_ptr[BT].sdx4df = SDX4DF;
BFP(BLOCK_32X16, vp9_sad32x16, vp9_sad32x16_avg,
vp9_variance32x16, vp9_sub_pixel_variance32x16,
vp9_sub_pixel_avg_variance32x16, NULL, NULL,
NULL, NULL, NULL,
vp9_sad32x16x4d)
BFP(BLOCK_16X32, vp9_sad16x32, vp9_sad16x32_avg,
vp9_variance16x32, vp9_sub_pixel_variance16x32,
vp9_sub_pixel_avg_variance16x32, NULL, NULL,
NULL, NULL, NULL,
vp9_sad16x32x4d)
BFP(BLOCK_64X32, vp9_sad64x32, vp9_sad64x32_avg,
vp9_variance64x32, vp9_sub_pixel_variance64x32,
vp9_sub_pixel_avg_variance64x32, NULL, NULL,
NULL, NULL, NULL,
vp9_sad64x32x4d)
BFP(BLOCK_32X64, vp9_sad32x64, vp9_sad32x64_avg,
vp9_variance32x64, vp9_sub_pixel_variance32x64,
vp9_sub_pixel_avg_variance32x64, NULL, NULL,
NULL, NULL, NULL,
vp9_sad32x64x4d)
BFP(BLOCK_32X32, vp9_sad32x32, vp9_sad32x32_avg,
vp9_variance32x32, vp9_sub_pixel_variance32x32,
vp9_sub_pixel_avg_variance32x32, vp9_variance_halfpixvar32x32_h,
vp9_variance_halfpixvar32x32_v,
vp9_variance_halfpixvar32x32_hv, vp9_sad32x32x3, vp9_sad32x32x8,
vp9_sad32x32x4d)
BFP(BLOCK_64X64, vp9_sad64x64, vp9_sad64x64_avg,
vp9_variance64x64, vp9_sub_pixel_variance64x64,
vp9_sub_pixel_avg_variance64x64, vp9_variance_halfpixvar64x64_h,
vp9_variance_halfpixvar64x64_v,
vp9_variance_halfpixvar64x64_hv, vp9_sad64x64x3, vp9_sad64x64x8,
vp9_sad64x64x4d)
BFP(BLOCK_16X16, vp9_sad16x16, vp9_sad16x16_avg,
vp9_variance16x16, vp9_sub_pixel_variance16x16,
vp9_sub_pixel_avg_variance16x16, vp9_variance_halfpixvar16x16_h,
vp9_variance_halfpixvar16x16_v,
vp9_variance_halfpixvar16x16_hv, vp9_sad16x16x3, vp9_sad16x16x8,
vp9_sad16x16x4d)
BFP(BLOCK_16X8, vp9_sad16x8, vp9_sad16x8_avg,
vp9_variance16x8, vp9_sub_pixel_variance16x8,
vp9_sub_pixel_avg_variance16x8, NULL, NULL, NULL,
vp9_sad16x8x3, vp9_sad16x8x8, vp9_sad16x8x4d)
BFP(BLOCK_8X16, vp9_sad8x16, vp9_sad8x16_avg,
vp9_variance8x16, vp9_sub_pixel_variance8x16,
vp9_sub_pixel_avg_variance8x16, NULL, NULL, NULL,
vp9_sad8x16x3, vp9_sad8x16x8, vp9_sad8x16x4d)
BFP(BLOCK_8X8, vp9_sad8x8, vp9_sad8x8_avg,
vp9_variance8x8, vp9_sub_pixel_variance8x8,
vp9_sub_pixel_avg_variance8x8, NULL, NULL, NULL,
vp9_sad8x8x3, vp9_sad8x8x8, vp9_sad8x8x4d)
BFP(BLOCK_8X4, vp9_sad8x4, vp9_sad8x4_avg,
vp9_variance8x4, vp9_sub_pixel_variance8x4,
vp9_sub_pixel_avg_variance8x4, NULL, NULL,
NULL, NULL, vp9_sad8x4x8,
vp9_sad8x4x4d)
BFP(BLOCK_4X8, vp9_sad4x8, vp9_sad4x8_avg,
vp9_variance4x8, vp9_sub_pixel_variance4x8,
vp9_sub_pixel_avg_variance4x8, NULL, NULL,
NULL, NULL, vp9_sad4x8x8,
vp9_sad4x8x4d)
BFP(BLOCK_4X4, vp9_sad4x4, vp9_sad4x4_avg,
vp9_variance4x4, vp9_sub_pixel_variance4x4,
vp9_sub_pixel_avg_variance4x4, NULL, NULL, NULL,
vp9_sad4x4x3, vp9_sad4x4x8, vp9_sad4x4x4d)
cpi->full_search_sad = vp9_full_search_sad;
cpi->diamond_search_sad = vp9_diamond_search_sad;
cpi->refining_search_sad = vp9_refining_search_sad;
/* vp9_init_quantizer() is first called here. Add check in
* vp9_frame_init_quantizer() so that vp9_init_quantizer is only
* called later when needed. This will avoid unnecessary calls of
* vp9_init_quantizer() for every frame.
*/
vp9_init_quantizer(cpi);
vp9_loop_filter_init(cm);
cm->error.setjmp = 0;
vp9_zero(cpi->common.counts.uv_mode);
#ifdef MODE_TEST_HIT_STATS
vp9_zero(cpi->mode_test_hits);
#endif
return cpi;
}
void vp9_remove_compressor(VP9_COMP *cpi) {
int i;
if (!cpi)
return;
if (cpi && (cpi->common.current_video_frame > 0)) {
#if CONFIG_INTERNAL_STATS
vp9_clear_system_state();
// printf("\n8x8-4x4:%d-%d\n", cpi->t8x8_count, cpi->t4x4_count);
if (cpi->pass != 1) {
FILE *f = fopen("opsnr.stt", "a");
double time_encoded = (cpi->last_end_time_stamp_seen
- cpi->first_time_stamp_ever) / 10000000.000;
double total_encode_time = (cpi->time_receive_data +
cpi->time_compress_data) / 1000.000;
double dr = (double)cpi->bytes * (double) 8 / (double)1000
/ time_encoded;
if (cpi->b_calculate_psnr) {
const double total_psnr =
vpx_sse_to_psnr((double)cpi->total_samples, 255.0,
(double)cpi->total_sq_error);
const double totalp_psnr =
vpx_sse_to_psnr((double)cpi->totalp_samples, 255.0,
(double)cpi->totalp_sq_error);
const double total_ssim = 100 * pow(cpi->summed_quality /
cpi->summed_weights, 8.0);
const double totalp_ssim = 100 * pow(cpi->summedp_quality /
cpi->summedp_weights, 8.0);
fprintf(f, "Bitrate\tAVGPsnr\tGLBPsnr\tAVPsnrP\tGLPsnrP\t"
"VPXSSIM\tVPSSIMP\t Time(ms)\n");
fprintf(f, "%7.2f\t%7.3f\t%7.3f\t%7.3f\t%7.3f\t%7.3f\t%7.3f\t%8.0f\n",
dr, cpi->total / cpi->count, total_psnr,
cpi->totalp / cpi->count, totalp_psnr, total_ssim, totalp_ssim,
total_encode_time);
}
if (cpi->b_calculate_ssimg) {
fprintf(f, "BitRate\tSSIM_Y\tSSIM_U\tSSIM_V\tSSIM_A\t Time(ms)\n");
fprintf(f, "%7.2f\t%6.4f\t%6.4f\t%6.4f\t%6.4f\t%8.0f\n", dr,
cpi->total_ssimg_y / cpi->count,
cpi->total_ssimg_u / cpi->count,
cpi->total_ssimg_v / cpi->count,
cpi->total_ssimg_all / cpi->count, total_encode_time);
}
fclose(f);
}
#endif
#ifdef MODE_TEST_HIT_STATS
if (cpi->pass != 1) {
double norm_per_pixel_mode_tests = 0;
double norm_counts[BLOCK_SIZES];
int i;
int sb64_per_frame;
int norm_factors[BLOCK_SIZES] =
{256, 128, 128, 64, 32, 32, 16, 8, 8, 4, 2, 2, 1};
FILE *f = fopen("mode_hit_stats.stt", "a");
// On average, how many mode tests do we do
for (i = 0; i < BLOCK_SIZES; ++i) {
norm_counts[i] = (double)cpi->mode_test_hits[i] /
(double)norm_factors[i];
norm_per_pixel_mode_tests += norm_counts[i];
}
// Convert to a number per 64x64 and per frame
sb64_per_frame = ((cpi->common.height + 63) / 64) *
((cpi->common.width + 63) / 64);
norm_per_pixel_mode_tests =
norm_per_pixel_mode_tests /
(double)(cpi->common.current_video_frame * sb64_per_frame);
fprintf(f, "%6.4f\n", norm_per_pixel_mode_tests);
fclose(f);
}
#endif
#if 0
{
printf("\n_pick_loop_filter_level:%d\n", cpi->time_pick_lpf / 1000);
printf("\n_frames recive_data encod_mb_row compress_frame Total\n");
printf("%6d %10ld %10ld %10ld %10ld\n", cpi->common.current_video_frame,
cpi->time_receive_data / 1000, cpi->time_encode_sb_row / 1000,
cpi->time_compress_data / 1000,
(cpi->time_receive_data + cpi->time_compress_data) / 1000);
}
#endif
}
free_pick_mode_context(&cpi->mb);
dealloc_compressor_data(cpi);
vpx_free(cpi->mb.ss);
vpx_free(cpi->tok);
for (i = 0; i < sizeof(cpi->mbgraph_stats) /
sizeof(cpi->mbgraph_stats[0]); ++i) {
vpx_free(cpi->mbgraph_stats[i].mb_stats);
}
vp9_remove_common(&cpi->common);
vpx_free(cpi);
#ifdef OUTPUT_YUV_SRC
fclose(yuv_file);
#endif
#ifdef OUTPUT_YUV_REC
fclose(yuv_rec_file);
#endif
#if 0
if (keyfile)
fclose(keyfile);
if (framepsnr)
fclose(framepsnr);
if (kf_list)
fclose(kf_list);
#endif
}
static uint64_t calc_plane_error(const uint8_t *orig, int orig_stride,
const uint8_t *recon, int recon_stride,
unsigned int cols, unsigned int rows) {
unsigned int row, col;
uint64_t total_sse = 0;
int diff;
for (row = 0; row + 16 <= rows; row += 16) {
for (col = 0; col + 16 <= cols; col += 16) {
unsigned int sse;
vp9_mse16x16(orig + col, orig_stride, recon + col, recon_stride, &sse);
total_sse += sse;
}
/* Handle odd-sized width */
if (col < cols) {
unsigned int border_row, border_col;
const uint8_t *border_orig = orig;
const uint8_t *border_recon = recon;
for (border_row = 0; border_row < 16; border_row++) {
for (border_col = col; border_col < cols; border_col++) {
diff = border_orig[border_col] - border_recon[border_col];
total_sse += diff * diff;
}
border_orig += orig_stride;
border_recon += recon_stride;
}
}
orig += orig_stride * 16;
recon += recon_stride * 16;
}
/* Handle odd-sized height */
for (; row < rows; row++) {
for (col = 0; col < cols; col++) {
diff = orig[col] - recon[col];
total_sse += diff * diff;
}
orig += orig_stride;
recon += recon_stride;
}
return total_sse;
}
typedef struct {
double psnr[4]; // total/y/u/v
uint64_t sse[4]; // total/y/u/v
uint32_t samples[4]; // total/y/u/v
} PSNR_STATS;
static void calc_psnr(const YV12_BUFFER_CONFIG *a, const YV12_BUFFER_CONFIG *b,
PSNR_STATS *psnr) {
const int widths[3] = {a->y_width, a->uv_width, a->uv_width };
const int heights[3] = {a->y_height, a->uv_height, a->uv_height};
const uint8_t *a_planes[3] = {a->y_buffer, a->u_buffer, a->v_buffer };
const int a_strides[3] = {a->y_stride, a->uv_stride, a->uv_stride};
const uint8_t *b_planes[3] = {b->y_buffer, b->u_buffer, b->v_buffer };
const int b_strides[3] = {b->y_stride, b->uv_stride, b->uv_stride};
int i;
uint64_t total_sse = 0;
uint32_t total_samples = 0;
for (i = 0; i < 3; ++i) {
const int w = widths[i];
const int h = heights[i];
const uint32_t samples = w * h;
const uint64_t sse = calc_plane_error(a_planes[i], a_strides[i],
b_planes[i], b_strides[i],
w, h);
psnr->sse[1 + i] = sse;
psnr->samples[1 + i] = samples;
psnr->psnr[1 + i] = vpx_sse_to_psnr(samples, 255.0, (double)sse);
total_sse += sse;
total_samples += samples;
}
psnr->sse[0] = total_sse;
psnr->samples[0] = total_samples;
psnr->psnr[0] = vpx_sse_to_psnr((double)total_samples, 255.0,
(double)total_sse);
}
static void generate_psnr_packet(VP9_COMP *cpi) {
struct vpx_codec_cx_pkt pkt;
int i;
PSNR_STATS psnr;
calc_psnr(cpi->Source, cpi->common.frame_to_show, &psnr);
for (i = 0; i < 4; ++i) {
pkt.data.psnr.samples[i] = psnr.samples[i];
pkt.data.psnr.sse[i] = psnr.sse[i];
pkt.data.psnr.psnr[i] = psnr.psnr[i];
}
pkt.kind = VPX_CODEC_PSNR_PKT;
vpx_codec_pkt_list_add(cpi->output_pkt_list, &pkt);
}
int vp9_use_as_reference(VP9_COMP *cpi, int ref_frame_flags) {
if (ref_frame_flags > 7)
return -1;
cpi->ref_frame_flags = ref_frame_flags;
return 0;
}
void vp9_update_reference(VP9_COMP *cpi, int ref_frame_flags) {
cpi->ext_refresh_golden_frame = (ref_frame_flags & VP9_GOLD_FLAG) != 0;
cpi->ext_refresh_alt_ref_frame = (ref_frame_flags & VP9_ALT_FLAG) != 0;
cpi->ext_refresh_last_frame = (ref_frame_flags & VP9_LAST_FLAG) != 0;
cpi->ext_refresh_frame_flags_pending = 1;
}
static YV12_BUFFER_CONFIG *get_vp9_ref_frame_buffer(VP9_COMP *cpi,
VP9_REFFRAME ref_frame_flag) {
MV_REFERENCE_FRAME ref_frame = NONE;
if (ref_frame_flag == VP9_LAST_FLAG)
ref_frame = LAST_FRAME;
else if (ref_frame_flag == VP9_GOLD_FLAG)
ref_frame = GOLDEN_FRAME;
else if (ref_frame_flag == VP9_ALT_FLAG)
ref_frame = ALTREF_FRAME;
return ref_frame == NONE ? NULL : get_ref_frame_buffer(cpi, ref_frame);
}
int vp9_copy_reference_enc(VP9_COMP *cpi, VP9_REFFRAME ref_frame_flag,
YV12_BUFFER_CONFIG *sd) {
YV12_BUFFER_CONFIG *cfg = get_vp9_ref_frame_buffer(cpi, ref_frame_flag);
if (cfg) {
vp8_yv12_copy_frame(cfg, sd);
return 0;
} else {
return -1;
}
}
int vp9_get_reference_enc(VP9_COMP *cpi, int index, YV12_BUFFER_CONFIG **fb) {
VP9_COMMON *cm = &cpi->common;
if (index < 0 || index >= REF_FRAMES)
return -1;
*fb = &cm->frame_bufs[cm->ref_frame_map[index]].buf;
return 0;
}
int vp9_set_reference_enc(VP9_COMP *cpi, VP9_REFFRAME ref_frame_flag,
YV12_BUFFER_CONFIG *sd) {
YV12_BUFFER_CONFIG *cfg = get_vp9_ref_frame_buffer(cpi, ref_frame_flag);
if (cfg) {
vp8_yv12_copy_frame(sd, cfg);
return 0;
} else {
return -1;
}
}
int vp9_update_entropy(VP9_COMP * cpi, int update) {
cpi->ext_refresh_frame_context = update;
cpi->ext_refresh_frame_context_pending = 1;
return 0;
}
#ifdef OUTPUT_YUV_SRC
void vp9_write_yuv_frame(YV12_BUFFER_CONFIG *s) {
uint8_t *src = s->y_buffer;
int h = s->y_height;
do {
fwrite(src, s->y_width, 1, yuv_file);
src += s->y_stride;
} while (--h);
src = s->u_buffer;
h = s->uv_height;
do {
fwrite(src, s->uv_width, 1, yuv_file);
src += s->uv_stride;
} while (--h);
src = s->v_buffer;
h = s->uv_height;
do {
fwrite(src, s->uv_width, 1, yuv_file);
src += s->uv_stride;
} while (--h);
}
#endif
#ifdef OUTPUT_YUV_REC
void vp9_write_yuv_rec_frame(VP9_COMMON *cm) {
YV12_BUFFER_CONFIG *s = cm->frame_to_show;
uint8_t *src = s->y_buffer;
int h = cm->height;
do {
fwrite(src, s->y_width, 1, yuv_rec_file);
src += s->y_stride;
} while (--h);
src = s->u_buffer;
h = s->uv_height;
do {
fwrite(src, s->uv_width, 1, yuv_rec_file);
src += s->uv_stride;
} while (--h);
src = s->v_buffer;
h = s->uv_height;
do {
fwrite(src, s->uv_width, 1, yuv_rec_file);
src += s->uv_stride;
} while (--h);
#if CONFIG_ALPHA
if (s->alpha_buffer) {
src = s->alpha_buffer;
h = s->alpha_height;
do {
fwrite(src, s->alpha_width, 1, yuv_rec_file);
src += s->alpha_stride;
} while (--h);
}
#endif
fflush(yuv_rec_file);
}
#endif
static void scale_and_extend_frame_nonnormative(YV12_BUFFER_CONFIG *src_fb,
YV12_BUFFER_CONFIG *dst_fb) {
const int in_w = src_fb->y_crop_width;
const int in_h = src_fb->y_crop_height;
const int out_w = dst_fb->y_crop_width;
const int out_h = dst_fb->y_crop_height;
const int in_w_uv = src_fb->uv_crop_width;
const int in_h_uv = src_fb->uv_crop_height;
const int out_w_uv = dst_fb->uv_crop_width;
const int out_h_uv = dst_fb->uv_crop_height;
int i;
uint8_t *srcs[4] = {src_fb->y_buffer, src_fb->u_buffer, src_fb->v_buffer,
src_fb->alpha_buffer};
int src_strides[4] = {src_fb->y_stride, src_fb->uv_stride, src_fb->uv_stride,
src_fb->alpha_stride};
uint8_t *dsts[4] = {dst_fb->y_buffer, dst_fb->u_buffer, dst_fb->v_buffer,
dst_fb->alpha_buffer};
int dst_strides[4] = {dst_fb->y_stride, dst_fb->uv_stride, dst_fb->uv_stride,
dst_fb->alpha_stride};
for (i = 0; i < MAX_MB_PLANE; ++i) {
if (i == 0 || i == 3) {
// Y and alpha planes
vp9_resize_plane(srcs[i], in_h, in_w, src_strides[i],
dsts[i], out_h, out_w, dst_strides[i]);
} else {
// Chroma planes
vp9_resize_plane(srcs[i], in_h_uv, in_w_uv, src_strides[i],
dsts[i], out_h_uv, out_w_uv, dst_strides[i]);
}
}
vp8_yv12_extend_frame_borders(dst_fb);
}
static void scale_and_extend_frame(YV12_BUFFER_CONFIG *src_fb,
YV12_BUFFER_CONFIG *dst_fb) {
const int in_w = src_fb->y_crop_width;
const int in_h = src_fb->y_crop_height;
const int out_w = dst_fb->y_crop_width;
const int out_h = dst_fb->y_crop_height;
int x, y, i;
uint8_t *srcs[4] = {src_fb->y_buffer, src_fb->u_buffer, src_fb->v_buffer,
src_fb->alpha_buffer};
int src_strides[4] = {src_fb->y_stride, src_fb->uv_stride, src_fb->uv_stride,
src_fb->alpha_stride};
uint8_t *dsts[4] = {dst_fb->y_buffer, dst_fb->u_buffer, dst_fb->v_buffer,
dst_fb->alpha_buffer};
int dst_strides[4] = {dst_fb->y_stride, dst_fb->uv_stride, dst_fb->uv_stride,
dst_fb->alpha_stride};
for (y = 0; y < out_h; y += 16) {
for (x = 0; x < out_w; x += 16) {
for (i = 0; i < MAX_MB_PLANE; ++i) {
const int factor = (i == 0 || i == 3 ? 1 : 2);
const int x_q4 = x * (16 / factor) * in_w / out_w;
const int y_q4 = y * (16 / factor) * in_h / out_h;
const int src_stride = src_strides[i];
const int dst_stride = dst_strides[i];
uint8_t *src = srcs[i] + y / factor * in_h / out_h * src_stride +
x / factor * in_w / out_w;
uint8_t *dst = dsts[i] + y / factor * dst_stride + x / factor;
vp9_convolve8(src, src_stride, dst, dst_stride,
vp9_sub_pel_filters_8[x_q4 & 0xf], 16 * in_w / out_w,
vp9_sub_pel_filters_8[y_q4 & 0xf], 16 * in_h / out_h,
16 / factor, 16 / factor);
}
}
}
vp8_yv12_extend_frame_borders(dst_fb);
}
static int find_fp_qindex() {
int i;
for (i = 0; i < QINDEX_RANGE; i++) {
if (vp9_convert_qindex_to_q(i) >= 30.0) {
break;
}
}
if (i == QINDEX_RANGE)
i--;
return i;
}
#define WRITE_RECON_BUFFER 0
#if WRITE_RECON_BUFFER
void write_cx_frame_to_file(YV12_BUFFER_CONFIG *frame, int this_frame) {
FILE *yframe;
int i;
char filename[255];
snprintf(filename, sizeof(filename), "cx\\y%04d.raw", this_frame);
yframe = fopen(filename, "wb");
for (i = 0; i < frame->y_height; i++)
fwrite(frame->y_buffer + i * frame->y_stride,
frame->y_width, 1, yframe);
fclose(yframe);
snprintf(filename, sizeof(filename), "cx\\u%04d.raw", this_frame);
yframe = fopen(filename, "wb");
for (i = 0; i < frame->uv_height; i++)
fwrite(frame->u_buffer + i * frame->uv_stride,
frame->uv_width, 1, yframe);
fclose(yframe);
snprintf(filename, sizeof(filename), "cx\\v%04d.raw", this_frame);
yframe = fopen(filename, "wb");
for (i = 0; i < frame->uv_height; i++)
fwrite(frame->v_buffer + i * frame->uv_stride,
frame->uv_width, 1, yframe);
fclose(yframe);
}
#endif
// Function to test for conditions that indicate we should loop
// back and recode a frame.
static int recode_loop_test(const VP9_COMP *cpi,
int high_limit, int low_limit,
int q, int maxq, int minq) {
const VP9_COMMON *const cm = &cpi->common;
const RATE_CONTROL *const rc = &cpi->rc;
int force_recode = 0;
// Special case trap if maximum allowed frame size exceeded.
if (rc->projected_frame_size > rc->max_frame_bandwidth) {
force_recode = 1;
// Is frame recode allowed.
// Yes if either recode mode 1 is selected or mode 2 is selected
// and the frame is a key frame, golden frame or alt_ref_frame
} else if ((cpi->sf.recode_loop == ALLOW_RECODE) ||
((cpi->sf.recode_loop == ALLOW_RECODE_KFARFGF) &&
(cm->frame_type == KEY_FRAME ||
cpi->refresh_golden_frame || cpi->refresh_alt_ref_frame))) {
// General over and under shoot tests
if ((rc->projected_frame_size > high_limit && q < maxq) ||
(rc->projected_frame_size < low_limit && q > minq)) {
force_recode = 1;
} else if (cpi->oxcf.end_usage == USAGE_CONSTRAINED_QUALITY) {
// Deal with frame undershoot and whether or not we are
// below the automatically set cq level.
if (q > cpi->cq_target_quality &&
rc->projected_frame_size < ((rc->this_frame_target * 7) >> 3)) {
force_recode = 1;
}
}
}
return force_recode;
}
void vp9_update_reference_frames(VP9_COMP *cpi) {
VP9_COMMON * const cm = &cpi->common;
// At this point the new frame has been encoded.
// If any buffer copy / swapping is signaled it should be done here.
if (cm->frame_type == KEY_FRAME) {
ref_cnt_fb(cm->frame_bufs,
&cm->ref_frame_map[cpi->gld_fb_idx], cm->new_fb_idx);
ref_cnt_fb(cm->frame_bufs,
&cm->ref_frame_map[cpi->alt_fb_idx], cm->new_fb_idx);
}
#if CONFIG_MULTIPLE_ARF
else if (!cpi->multi_arf_enabled && cpi->refresh_golden_frame &&
!cpi->refresh_alt_ref_frame) {
#else
else if (cpi->refresh_golden_frame && !cpi->refresh_alt_ref_frame &&
!cpi->use_svc) {
#endif
/* Preserve the previously existing golden frame and update the frame in
* the alt ref slot instead. This is highly specific to the current use of
* alt-ref as a forward reference, and this needs to be generalized as
* other uses are implemented (like RTC/temporal scaling)
*
* The update to the buffer in the alt ref slot was signaled in
* vp9_pack_bitstream(), now swap the buffer pointers so that it's treated
* as the golden frame next time.
*/
int tmp;
ref_cnt_fb(cm->frame_bufs,
&cm->ref_frame_map[cpi->alt_fb_idx], cm->new_fb_idx);
tmp = cpi->alt_fb_idx;
cpi->alt_fb_idx = cpi->gld_fb_idx;
cpi->gld_fb_idx = tmp;
} else { /* For non key/golden frames */
if (cpi->refresh_alt_ref_frame) {
int arf_idx = cpi->alt_fb_idx;
#if CONFIG_MULTIPLE_ARF
if (cpi->multi_arf_enabled) {
arf_idx = cpi->arf_buffer_idx[cpi->sequence_number + 1];
}
#endif
ref_cnt_fb(cm->frame_bufs,
&cm->ref_frame_map[arf_idx], cm->new_fb_idx);
}
if (cpi->refresh_golden_frame) {
ref_cnt_fb(cm->frame_bufs,
&cm->ref_frame_map[cpi->gld_fb_idx], cm->new_fb_idx);
}
}
if (cpi->refresh_last_frame) {
ref_cnt_fb(cm->frame_bufs,
&cm->ref_frame_map[cpi->lst_fb_idx], cm->new_fb_idx);
}
}
static void loopfilter_frame(VP9_COMP *cpi, VP9_COMMON *cm) {
MACROBLOCKD *xd = &cpi->mb.e_mbd;
struct loopfilter *lf = &cm->lf;
if (xd->lossless) {
lf->filter_level = 0;
} else {
struct vpx_usec_timer timer;
vp9_clear_system_state();
vpx_usec_timer_start(&timer);
vp9_pick_filter_level(cpi->Source, cpi, cpi->sf.lpf_pick);
vpx_usec_timer_mark(&timer);
cpi->time_pick_lpf += vpx_usec_timer_elapsed(&timer);
}
if (lf->filter_level > 0) {
vp9_loop_filter_frame(cm, xd, lf->filter_level, 0, 0);
}
vp9_extend_frame_inner_borders(cm->frame_to_show);
}
void vp9_scale_references(VP9_COMP *cpi) {
VP9_COMMON *cm = &cpi->common;
MV_REFERENCE_FRAME ref_frame;
for (ref_frame = LAST_FRAME; ref_frame <= ALTREF_FRAME; ++ref_frame) {
const int idx = cm->ref_frame_map[get_ref_frame_idx(cpi, ref_frame)];
YV12_BUFFER_CONFIG *const ref = &cm->frame_bufs[idx].buf;
if (ref->y_crop_width != cm->width ||
ref->y_crop_height != cm->height) {
const int new_fb = get_free_fb(cm);
vp9_realloc_frame_buffer(&cm->frame_bufs[new_fb].buf,
cm->width, cm->height,
cm->subsampling_x, cm->subsampling_y,
VP9_ENC_BORDER_IN_PIXELS, NULL, NULL, NULL);
scale_and_extend_frame(ref, &cm->frame_bufs[new_fb].buf);
cpi->scaled_ref_idx[ref_frame - 1] = new_fb;
} else {
cpi->scaled_ref_idx[ref_frame - 1] = idx;
cm->frame_bufs[idx].ref_count++;
}
}
}
static void release_scaled_references(VP9_COMP *cpi) {
VP9_COMMON *cm = &cpi->common;
int i;
for (i = 0; i < 3; i++)
cm->frame_bufs[cpi->scaled_ref_idx[i]].ref_count--;
}
static void full_to_model_count(unsigned int *model_count,
unsigned int *full_count) {
int n;
model_count[ZERO_TOKEN] = full_count[ZERO_TOKEN];
model_count[ONE_TOKEN] = full_count[ONE_TOKEN];
model_count[TWO_TOKEN] = full_count[TWO_TOKEN];
for (n = THREE_TOKEN; n < EOB_TOKEN; ++n)
model_count[TWO_TOKEN] += full_count[n];
model_count[EOB_MODEL_TOKEN] = full_count[EOB_TOKEN];
}
static void full_to_model_counts(vp9_coeff_count_model *model_count,
vp9_coeff_count *full_count) {
int i, j, k, l;
for (i = 0; i < PLANE_TYPES; ++i)
for (j = 0; j < REF_TYPES; ++j)
for (k = 0; k < COEF_BANDS; ++k)
for (l = 0; l < BAND_COEFF_CONTEXTS(k); ++l)
full_to_model_count(model_count[i][j][k][l], full_count[i][j][k][l]);
}
#if 0 && CONFIG_INTERNAL_STATS
static void output_frame_level_debug_stats(VP9_COMP *cpi) {
VP9_COMMON *const cm = &cpi->common;
FILE *const f = fopen("tmp.stt", cm->current_video_frame ? "a" : "w");
int recon_err;
vp9_clear_system_state();
recon_err = vp9_calc_ss_err(cpi->Source, get_frame_new_buffer(cm));
if (cpi->twopass.total_left_stats.coded_error != 0.0)
fprintf(f, "%10u %10d %10d %10d %10d %10d "
"%10"PRId64" %10"PRId64" %10d "
"%7.2lf %7.2lf %7.2lf %7.2lf %7.2lf"
"%6d %6d %5d %5d %5d "
"%10"PRId64" %10.3lf"
"%10lf %8u %10d %10d %10d\n",
cpi->common.current_video_frame, cpi->rc.this_frame_target,
cpi->rc.projected_frame_size,
cpi->rc.projected_frame_size / cpi->common.MBs,
(cpi->rc.projected_frame_size - cpi->rc.this_frame_target),
cpi->rc.total_target_vs_actual,
(cpi->oxcf.starting_buffer_level - cpi->rc.bits_off_target),
cpi->rc.total_actual_bits, cm->base_qindex,
vp9_convert_qindex_to_q(cm->base_qindex),
(double)vp9_dc_quant(cm->base_qindex, 0) / 4.0,
cpi->rc.avg_q,
vp9_convert_qindex_to_q(cpi->rc.ni_av_qi),
vp9_convert_qindex_to_q(cpi->cq_target_quality),
cpi->refresh_last_frame, cpi->refresh_golden_frame,
cpi->refresh_alt_ref_frame, cm->frame_type, cpi->rc.gfu_boost,
cpi->twopass.bits_left,
cpi->twopass.total_left_stats.coded_error,
cpi->twopass.bits_left /
(1 + cpi->twopass.total_left_stats.coded_error),
cpi->tot_recode_hits, recon_err, cpi->rc.kf_boost,
cpi->twopass.kf_zeromotion_pct);
fclose(f);
if (0) {
FILE *const fmodes = fopen("Modes.stt", "a");
int i;
fprintf(fmodes, "%6d:%1d:%1d:%1d ", cpi->common.current_video_frame,
cm->frame_type, cpi->refresh_golden_frame,
cpi->refresh_alt_ref_frame);
for (i = 0; i < MAX_MODES; ++i)
fprintf(fmodes, "%5d ", cpi->mode_chosen_counts[i]);
fprintf(fmodes, "\n");
fclose(fmodes);
}
}
#endif
static void encode_without_recode_loop(VP9_COMP *cpi,
size_t *size,
uint8_t *dest,
int q) {
VP9_COMMON *const cm = &cpi->common;
vp9_clear_system_state();
vp9_set_quantizer(cm, q);
// Set up entropy context depending on frame type. The decoder mandates
// the use of the default context, index 0, for keyframes and inter
// frames where the error_resilient_mode or intra_only flag is set. For
// other inter-frames the encoder currently uses only two contexts;
// context 1 for ALTREF frames and context 0 for the others.
if (cm->frame_type == KEY_FRAME) {
setup_key_frame(cpi);
} else {
if (!cm->intra_only && !cm->error_resilient_mode && !cpi->use_svc)
cm->frame_context_idx = cpi->refresh_alt_ref_frame;
setup_inter_frame(cm);
}
// Variance adaptive and in frame q adjustment experiments are mutually
// exclusive.
if (cpi->oxcf.aq_mode == VARIANCE_AQ) {
vp9_vaq_frame_setup(cpi);
} else if (cpi->oxcf.aq_mode == COMPLEXITY_AQ) {
vp9_setup_in_frame_q_adj(cpi);
} else if (cpi->oxcf.aq_mode == CYCLIC_REFRESH_AQ) {
vp9_cyclic_refresh_setup(cpi);
}
// transform / motion compensation build reconstruction frame
vp9_encode_frame(cpi);
// Update the skip mb flag probabilities based on the distribution
// seen in the last encoder iteration.
// update_base_skip_probs(cpi);
vp9_clear_system_state();
}
static void encode_with_recode_loop(VP9_COMP *cpi,
size_t *size,
uint8_t *dest,
int q,
int bottom_index,
int top_index) {
VP9_COMMON *const cm = &cpi->common;
RATE_CONTROL *const rc = &cpi->rc;
int loop_count = 0;
int loop = 0;
int overshoot_seen = 0;
int undershoot_seen = 0;
int q_low = bottom_index, q_high = top_index;
int frame_over_shoot_limit;
int frame_under_shoot_limit;
// Decide frame size bounds
vp9_rc_compute_frame_size_bounds(cpi, rc->this_frame_target,
&frame_under_shoot_limit,
&frame_over_shoot_limit);
do {
vp9_clear_system_state();
vp9_set_quantizer(cm, q);
if (loop_count == 0) {
// Set up entropy context depending on frame type. The decoder mandates
// the use of the default context, index 0, for keyframes and inter
// frames where the error_resilient_mode or intra_only flag is set. For
// other inter-frames the encoder currently uses only two contexts;
// context 1 for ALTREF frames and context 0 for the others.
if (cm->frame_type == KEY_FRAME) {
setup_key_frame(cpi);
} else {
if (!cm->intra_only && !cm->error_resilient_mode && !cpi->use_svc)
cpi->common.frame_context_idx = cpi->refresh_alt_ref_frame;
setup_inter_frame(cm);
}
}
// Variance adaptive and in frame q adjustment experiments are mutually
// exclusive.
if (cpi->oxcf.aq_mode == VARIANCE_AQ) {
vp9_vaq_frame_setup(cpi);
} else if (cpi->oxcf.aq_mode == COMPLEXITY_AQ) {
vp9_setup_in_frame_q_adj(cpi);
}
// transform / motion compensation build reconstruction frame
vp9_encode_frame(cpi);
// Update the skip mb flag probabilities based on the distribution
// seen in the last encoder iteration.
// update_base_skip_probs(cpi);
vp9_clear_system_state();
// Dummy pack of the bitstream using up to date stats to get an
// accurate estimate of output frame size to determine if we need
// to recode.
if (cpi->sf.recode_loop >= ALLOW_RECODE_KFARFGF) {
vp9_save_coding_context(cpi);
cpi->dummy_packing = 1;
if (!cpi->sf.use_nonrd_pick_mode)
vp9_pack_bitstream(cpi, dest, size);
rc->projected_frame_size = (int)(*size) << 3;
vp9_restore_coding_context(cpi);
if (frame_over_shoot_limit == 0)
frame_over_shoot_limit = 1;
}
if (cpi->oxcf.end_usage == USAGE_CONSTANT_QUALITY) {
loop = 0;
} else {
if ((cm->frame_type == KEY_FRAME) &&
rc->this_key_frame_forced &&
(rc->projected_frame_size < rc->max_frame_bandwidth)) {
int last_q = q;
int kf_err = vp9_calc_ss_err(cpi->Source, get_frame_new_buffer(cm));
int high_err_target = cpi->ambient_err;
int low_err_target = cpi->ambient_err >> 1;
// Prevent possible divide by zero error below for perfect KF
kf_err += !kf_err;
// The key frame is not good enough or we can afford
// to make it better without undue risk of popping.
if ((kf_err > high_err_target &&
rc->projected_frame_size <= frame_over_shoot_limit) ||
(kf_err > low_err_target &&
rc->projected_frame_size <= frame_under_shoot_limit)) {
// Lower q_high
q_high = q > q_low ? q - 1 : q_low;
// Adjust Q
q = (q * high_err_target) / kf_err;
q = MIN(q, (q_high + q_low) >> 1);
} else if (kf_err < low_err_target &&
rc->projected_frame_size >= frame_under_shoot_limit) {
// The key frame is much better than the previous frame
// Raise q_low
q_low = q < q_high ? q + 1 : q_high;
// Adjust Q
q = (q * low_err_target) / kf_err;
q = MIN(q, (q_high + q_low + 1) >> 1);
}
// Clamp Q to upper and lower limits:
q = clamp(q, q_low, q_high);
loop = q != last_q;
} else if (recode_loop_test(
cpi, frame_over_shoot_limit, frame_under_shoot_limit,
q, MAX(q_high, top_index), bottom_index)) {
// Is the projected frame size out of range and are we allowed
// to attempt to recode.
int last_q = q;
int retries = 0;
// Frame size out of permitted range:
// Update correction factor & compute new Q to try...
// Frame is too large
if (rc->projected_frame_size > rc->this_frame_target) {
// Special case if the projected size is > the max allowed.
if (rc->projected_frame_size >= rc->max_frame_bandwidth)
q_high = rc->worst_quality;
// Raise Qlow as to at least the current value
q_low = q < q_high ? q + 1 : q_high;
if (undershoot_seen || loop_count > 1) {
// Update rate_correction_factor unless
vp9_rc_update_rate_correction_factors(cpi, 1);
q = (q_high + q_low + 1) / 2;
} else {
// Update rate_correction_factor unless
vp9_rc_update_rate_correction_factors(cpi, 0);
q = vp9_rc_regulate_q(cpi, rc->this_frame_target,
bottom_index, MAX(q_high, top_index));
while (q < q_low && retries < 10) {
vp9_rc_update_rate_correction_factors(cpi, 0);
q = vp9_rc_regulate_q(cpi, rc->this_frame_target,
bottom_index, MAX(q_high, top_index));
retries++;
}
}
overshoot_seen = 1;
} else {
// Frame is too small
q_high = q > q_low ? q - 1 : q_low;
if (overshoot_seen || loop_count > 1) {
vp9_rc_update_rate_correction_factors(cpi, 1);
q = (q_high + q_low) / 2;
} else {
vp9_rc_update_rate_correction_factors(cpi, 0);
q = vp9_rc_regulate_q(cpi, rc->this_frame_target,
bottom_index, top_index);
// Special case reset for qlow for constrained quality.
// This should only trigger where there is very substantial
// undershoot on a frame and the auto cq level is above
// the user passsed in value.
if (cpi->oxcf.end_usage == USAGE_CONSTRAINED_QUALITY &&
q < q_low) {
q_low = q;
}
while (q > q_high && retries < 10) {
vp9_rc_update_rate_correction_factors(cpi, 0);
q = vp9_rc_regulate_q(cpi, rc->this_frame_target,
bottom_index, top_index);
retries++;
}
}
undershoot_seen = 1;
}
// Clamp Q to upper and lower limits:
q = clamp(q, q_low, q_high);
loop = q != last_q;
} else {
loop = 0;
}
}
// Special case for overlay frame.
if (rc->is_src_frame_alt_ref &&
rc->projected_frame_size < rc->max_frame_bandwidth)
loop = 0;
if (loop) {
loop_count++;
#if CONFIG_INTERNAL_STATS
cpi->tot_recode_hits++;
#endif
}
} while (loop);
}
static void get_ref_frame_flags(VP9_COMP *cpi) {
if (cpi->refresh_last_frame & cpi->refresh_golden_frame)
cpi->gold_is_last = 1;
else if (cpi->refresh_last_frame ^ cpi->refresh_golden_frame)
cpi->gold_is_last = 0;
if (cpi->refresh_last_frame & cpi->refresh_alt_ref_frame)
cpi->alt_is_last = 1;
else if (cpi->refresh_last_frame ^ cpi->refresh_alt_ref_frame)
cpi->alt_is_last = 0;
if (cpi->refresh_alt_ref_frame & cpi->refresh_golden_frame)
cpi->gold_is_alt = 1;
else if (cpi->refresh_alt_ref_frame ^ cpi->refresh_golden_frame)
cpi->gold_is_alt = 0;
cpi->ref_frame_flags = VP9_ALT_FLAG | VP9_GOLD_FLAG | VP9_LAST_FLAG;
if (cpi->gold_is_last)
cpi->ref_frame_flags &= ~VP9_GOLD_FLAG;
if (cpi->rc.frames_till_gf_update_due == INT_MAX)
cpi->ref_frame_flags &= ~VP9_GOLD_FLAG;
if (cpi->alt_is_last)
cpi->ref_frame_flags &= ~VP9_ALT_FLAG;
if (cpi->gold_is_alt)
cpi->ref_frame_flags &= ~VP9_ALT_FLAG;
}
static void set_ext_overrides(VP9_COMP *cpi) {
// Overrides the defaults with the externally supplied values with
// vp9_update_reference() and vp9_update_entropy() calls
// Note: The overrides are valid only for the next frame passed
// to encode_frame_to_data_rate() function
if (cpi->ext_refresh_frame_context_pending) {
cpi->common.refresh_frame_context = cpi->ext_refresh_frame_context;
cpi->ext_refresh_frame_context_pending = 0;
}
if (cpi->ext_refresh_frame_flags_pending) {
cpi->refresh_last_frame = cpi->ext_refresh_last_frame;
cpi->refresh_golden_frame = cpi->ext_refresh_golden_frame;
cpi->refresh_alt_ref_frame = cpi->ext_refresh_alt_ref_frame;
cpi->ext_refresh_frame_flags_pending = 0;
}
}
static void encode_frame_to_data_rate(VP9_COMP *cpi,
size_t *size,
uint8_t *dest,
unsigned int *frame_flags) {
VP9_COMMON *const cm = &cpi->common;
TX_SIZE t;
int q;
int top_index;
int bottom_index;
const SPEED_FEATURES *const sf = &cpi->sf;
const unsigned int max_mv_def = MIN(cm->width, cm->height);
struct segmentation *const seg = &cm->seg;
set_ext_overrides(cpi);
/* Scale the source buffer, if required. */
if (cm->mi_cols * MI_SIZE != cpi->un_scaled_source->y_width ||
cm->mi_rows * MI_SIZE != cpi->un_scaled_source->y_height) {
scale_and_extend_frame_nonnormative(cpi->un_scaled_source,
&cpi->scaled_source);
cpi->Source = &cpi->scaled_source;
} else {
cpi->Source = cpi->un_scaled_source;
}
// Scale the last source buffer, if required.
if (cpi->unscaled_last_source != NULL) {
if (cm->mi_cols * MI_SIZE != cpi->unscaled_last_source->y_width ||
cm->mi_rows * MI_SIZE != cpi->unscaled_last_source->y_height) {
scale_and_extend_frame_nonnormative(cpi->unscaled_last_source,
&cpi->scaled_last_source);
cpi->Last_Source = &cpi->scaled_last_source;
} else {
cpi->Last_Source = cpi->unscaled_last_source;
}
}
vp9_scale_references(cpi);
vp9_clear_system_state();
// Enable or disable mode based tweaking of the zbin.
// For 2 pass only used where GF/ARF prediction quality
// is above a threshold.
cpi->zbin_mode_boost = 0;
cpi->zbin_mode_boost_enabled = 0;
// Current default encoder behavior for the altref sign bias.
cm->ref_frame_sign_bias[ALTREF_FRAME] = cpi->rc.source_alt_ref_active;
// Set default state for segment based loop filter update flags.
cm->lf.mode_ref_delta_update = 0;
// Initialize cpi->mv_step_param to default based on max resolution.
cpi->mv_step_param = vp9_init_search_range(cpi, max_mv_def);
// Initialize cpi->max_mv_magnitude and cpi->mv_step_param if appropriate.
if (sf->auto_mv_step_size) {
if (frame_is_intra_only(cm)) {
// Initialize max_mv_magnitude for use in the first INTER frame
// after a key/intra-only frame.
cpi->max_mv_magnitude = max_mv_def;
} else {
if (cm->show_frame)
// Allow mv_steps to correspond to twice the max mv magnitude found
// in the previous frame, capped by the default max_mv_magnitude based
// on resolution.
cpi->mv_step_param = vp9_init_search_range(cpi, MIN(max_mv_def, 2 *
cpi->max_mv_magnitude));
cpi->max_mv_magnitude = 0;
}
}
// Set various flags etc to special state if it is a key frame.
if (frame_is_intra_only(cm)) {
setup_key_frame(cpi);
// Reset the loop filter deltas and segmentation map.
vp9_reset_segment_features(&cm->seg);
// If segmentation is enabled force a map update for key frames.
if (seg->enabled) {
seg->update_map = 1;
seg->update_data = 1;
}
// The alternate reference frame cannot be active for a key frame.
cpi->rc.source_alt_ref_active = 0;
cm->error_resilient_mode = (cpi->oxcf.error_resilient_mode != 0);
cm->frame_parallel_decoding_mode =
(cpi->oxcf.frame_parallel_decoding_mode != 0);
// By default, encoder assumes decoder can use prev_mi.
cm->coding_use_prev_mi = 1;
if (cm->error_resilient_mode) {
cm->coding_use_prev_mi = 0;
cm->frame_parallel_decoding_mode = 1;
cm->reset_frame_context = 0;
cm->refresh_frame_context = 0;
} else if (cm->intra_only) {
// Only reset the current context.
cm->reset_frame_context = 2;
}
}
// Configure experimental use of segmentation for enhanced coding of
// static regions if indicated.
// Only allowed in second pass of two pass (as requires lagged coding)
// and if the relevant speed feature flag is set.
if (cpi->pass == 2 && cpi->sf.static_segmentation)
configure_static_seg_features(cpi);
// For 1 pass CBR, check if we are dropping this frame.
// Never drop on key frame.
if (cpi->pass == 0 &&
cpi->oxcf.end_usage == USAGE_STREAM_FROM_SERVER &&
cm->frame_type != KEY_FRAME) {
if (vp9_rc_drop_frame(cpi)) {
vp9_rc_postencode_update_drop_frame(cpi);
++cm->current_video_frame;
return;
}
}
vp9_clear_system_state();
vp9_zero(cpi->rd_tx_select_threshes);
#if CONFIG_VP9_POSTPROC
if (cpi->oxcf.noise_sensitivity > 0) {
int l = 0;
switch (cpi->oxcf.noise_sensitivity) {
case 1:
l = 20;
break;
case 2:
l = 40;
break;
case 3:
l = 60;
break;
case 4:
case 5:
l = 100;
break;
case 6:
l = 150;
break;
}
vp9_denoise(cpi->Source, cpi->Source, l);
}
#endif
#ifdef OUTPUT_YUV_SRC
vp9_write_yuv_frame(cpi->Source);
#endif
set_speed_features(cpi);
// Decide q and q bounds.
q = vp9_rc_pick_q_and_bounds(cpi, &bottom_index, &top_index);
if (!frame_is_intra_only(cm)) {
cm->interp_filter = DEFAULT_INTERP_FILTER;
/* TODO: Decide this more intelligently */
set_high_precision_mv(cpi, q < HIGH_PRECISION_MV_QTHRESH);
}
if (cpi->sf.recode_loop == DISALLOW_RECODE) {
encode_without_recode_loop(cpi, size, dest, q);
} else {
encode_with_recode_loop(cpi, size, dest, q, bottom_index, top_index);
}
// Special case code to reduce pulsing when key frames are forced at a
// fixed interval. Note the reconstruction error if it is the frame before
// the force key frame
if (cpi->rc.next_key_frame_forced && cpi->rc.frames_to_key == 1) {
cpi->ambient_err = vp9_calc_ss_err(cpi->Source, get_frame_new_buffer(cm));
}
// If the encoder forced a KEY_FRAME decision
if (cm->frame_type == KEY_FRAME)
cpi->refresh_last_frame = 1;
cm->frame_to_show = get_frame_new_buffer(cm);
#if WRITE_RECON_BUFFER
if (cm->show_frame)
write_cx_frame_to_file(cm->frame_to_show,
cm->current_video_frame);
else
write_cx_frame_to_file(cm->frame_to_show,
cm->current_video_frame + 1000);
#endif
// Pick the loop filter level for the frame.
loopfilter_frame(cpi, cm);
#if WRITE_RECON_BUFFER
if (cm->show_frame)
write_cx_frame_to_file(cm->frame_to_show,
cm->current_video_frame + 2000);
else
write_cx_frame_to_file(cm->frame_to_show,
cm->current_video_frame + 3000);
#endif
// build the bitstream
cpi->dummy_packing = 0;
vp9_pack_bitstream(cpi, dest, size);
if (cm->seg.update_map)
update_reference_segmentation_map(cpi);
release_scaled_references(cpi);
vp9_update_reference_frames(cpi);
for (t = TX_4X4; t <= TX_32X32; t++)
full_to_model_counts(cm->counts.coef[t], cpi->coef_counts[t]);
if (!cm->error_resilient_mode && !cm->frame_parallel_decoding_mode)
vp9_adapt_coef_probs(cm);
if (!frame_is_intra_only(cm)) {
if (!cm->error_resilient_mode && !cm->frame_parallel_decoding_mode) {
vp9_adapt_mode_probs(cm);
vp9_adapt_mv_probs(cm, cm->allow_high_precision_mv);
}
}
#if 0
output_frame_level_debug_stats(cpi);
#endif
if (cpi->refresh_golden_frame == 1)
cm->frame_flags |= FRAMEFLAGS_GOLDEN;
else
cm->frame_flags &= ~FRAMEFLAGS_GOLDEN;
if (cpi->refresh_alt_ref_frame == 1)
cm->frame_flags |= FRAMEFLAGS_ALTREF;
else
cm->frame_flags &= ~FRAMEFLAGS_ALTREF;
get_ref_frame_flags(cpi);
vp9_rc_postencode_update(cpi, *size);
if (cm->frame_type == KEY_FRAME) {
// Tell the caller that the frame was coded as a key frame
*frame_flags = cm->frame_flags | FRAMEFLAGS_KEY;
#if CONFIG_MULTIPLE_ARF
// Reset the sequence number.
if (cpi->multi_arf_enabled) {
cpi->sequence_number = 0;
cpi->frame_coding_order_period = cpi->new_frame_coding_order_period;
cpi->new_frame_coding_order_period = -1;
}
#endif
} else {
*frame_flags = cm->frame_flags&~FRAMEFLAGS_KEY;
#if CONFIG_MULTIPLE_ARF
/* Increment position in the coded frame sequence. */
if (cpi->multi_arf_enabled) {
++cpi->sequence_number;
if (cpi->sequence_number >= cpi->frame_coding_order_period) {
cpi->sequence_number = 0;
cpi->frame_coding_order_period = cpi->new_frame_coding_order_period;
cpi->new_frame_coding_order_period = -1;
}
cpi->this_frame_weight = cpi->arf_weight[cpi->sequence_number];
assert(cpi->this_frame_weight >= 0);
}
#endif
}
// Clear the one shot update flags for segmentation map and mode/ref loop
// filter deltas.
cm->seg.update_map = 0;
cm->seg.update_data = 0;
cm->lf.mode_ref_delta_update = 0;
// keep track of the last coded dimensions
cm->last_width = cm->width;
cm->last_height = cm->height;
// reset to normal state now that we are done.
if (!cm->show_existing_frame)
cm->last_show_frame = cm->show_frame;
if (cm->show_frame) {
vp9_swap_mi_and_prev_mi(cm);
// Don't increment frame counters if this was an altref buffer
// update not a real frame
++cm->current_video_frame;
if (cpi->use_svc) {
LAYER_CONTEXT *lc;
if (cpi->svc.number_temporal_layers > 1) {
lc = &cpi->svc.layer_context[cpi->svc.temporal_layer_id];
} else {
lc = &cpi->svc.layer_context[cpi->svc.spatial_layer_id];
}
++lc->current_video_frame_in_layer;
}
}
// restore prev_mi
cm->prev_mi = cm->prev_mip + cm->mi_stride + 1;
cm->prev_mi_grid_visible = cm->prev_mi_grid_base + cm->mi_stride + 1;
}
static void SvcEncode(VP9_COMP *cpi, size_t *size, uint8_t *dest,
unsigned int *frame_flags) {
vp9_rc_get_svc_params(cpi);
encode_frame_to_data_rate(cpi, size, dest, frame_flags);
}
static void Pass0Encode(VP9_COMP *cpi, size_t *size, uint8_t *dest,
unsigned int *frame_flags) {
if (cpi->oxcf.end_usage == USAGE_STREAM_FROM_SERVER) {
vp9_rc_get_one_pass_cbr_params(cpi);
} else {
vp9_rc_get_one_pass_vbr_params(cpi);
}
encode_frame_to_data_rate(cpi, size, dest, frame_flags);
}
static void Pass1Encode(VP9_COMP *cpi, size_t *size, uint8_t *dest,
unsigned int *frame_flags) {
(void) size;
(void) dest;
(void) frame_flags;
vp9_rc_get_first_pass_params(cpi);
vp9_set_quantizer(&cpi->common, find_fp_qindex());
vp9_first_pass(cpi);
}
static void Pass2Encode(VP9_COMP *cpi, size_t *size,
uint8_t *dest, unsigned int *frame_flags) {
cpi->allow_encode_breakout = ENCODE_BREAKOUT_ENABLED;
vp9_rc_get_second_pass_params(cpi);
encode_frame_to_data_rate(cpi, size, dest, frame_flags);
vp9_twopass_postencode_update(cpi);
}
static void check_initial_width(VP9_COMP *cpi, int subsampling_x,
int subsampling_y) {
VP9_COMMON *const cm = &cpi->common;
if (!cpi->initial_width) {
cm->subsampling_x = subsampling_x;
cm->subsampling_y = subsampling_y;
alloc_raw_frame_buffers(cpi);
cpi->initial_width = cm->width;
cpi->initial_height = cm->height;
}
}
int vp9_receive_raw_frame(VP9_COMP *cpi, unsigned int frame_flags,
YV12_BUFFER_CONFIG *sd, int64_t time_stamp,
int64_t end_time) {
VP9_COMMON *cm = &cpi->common;
struct vpx_usec_timer timer;
int res = 0;
const int subsampling_x = sd->uv_width < sd->y_width;
const int subsampling_y = sd->uv_height < sd->y_height;
check_initial_width(cpi, subsampling_x, subsampling_y);
vpx_usec_timer_start(&timer);
if (vp9_lookahead_push(cpi->lookahead,
sd, time_stamp, end_time, frame_flags))
res = -1;
vpx_usec_timer_mark(&timer);
cpi->time_receive_data += vpx_usec_timer_elapsed(&timer);
if (cm->version == 0 && (subsampling_x != 1 || subsampling_y != 1)) {
vpx_internal_error(&cm->error, VPX_CODEC_INVALID_PARAM,
"Non-4:2:0 color space requires profile >= 1");
res = -1;
}
return res;
}
static int frame_is_reference(const VP9_COMP *cpi) {
const VP9_COMMON *cm = &cpi->common;
return cm->frame_type == KEY_FRAME ||
cpi->refresh_last_frame ||
cpi->refresh_golden_frame ||
cpi->refresh_alt_ref_frame ||
cm->refresh_frame_context ||
cm->lf.mode_ref_delta_update ||
cm->seg.update_map ||
cm->seg.update_data;
}
#if CONFIG_MULTIPLE_ARF
int is_next_frame_arf(VP9_COMP *cpi) {
// Negative entry in frame_coding_order indicates an ARF at this position.
return cpi->frame_coding_order[cpi->sequence_number + 1] < 0 ? 1 : 0;
}
#endif
void adjust_frame_rate(VP9_COMP *cpi) {
int64_t this_duration;
int step = 0;
if (cpi->source->ts_start == cpi->first_time_stamp_ever) {
this_duration = cpi->source->ts_end - cpi->source->ts_start;
step = 1;
} else {
int64_t last_duration = cpi->last_end_time_stamp_seen
- cpi->last_time_stamp_seen;
this_duration = cpi->source->ts_end - cpi->last_end_time_stamp_seen;
// do a step update if the duration changes by 10%
if (last_duration)
step = (int)((this_duration - last_duration) * 10 / last_duration);
}
if (this_duration) {
if (step) {
vp9_new_framerate(cpi, 10000000.0 / this_duration);
} else {
// Average this frame's rate into the last second's average
// frame rate. If we haven't seen 1 second yet, then average
// over the whole interval seen.
const double interval = MIN((double)(cpi->source->ts_end
- cpi->first_time_stamp_ever), 10000000.0);
double avg_duration = 10000000.0 / cpi->oxcf.framerate;
avg_duration *= (interval - avg_duration + this_duration);
avg_duration /= interval;
vp9_new_framerate(cpi, 10000000.0 / avg_duration);
}
}
cpi->last_time_stamp_seen = cpi->source->ts_start;
cpi->last_end_time_stamp_seen = cpi->source->ts_end;
}
int vp9_get_compressed_data(VP9_COMP *cpi, unsigned int *frame_flags,
size_t *size, uint8_t *dest,
int64_t *time_stamp, int64_t *time_end, int flush) {
VP9_COMMON *const cm = &cpi->common;
MACROBLOCKD *const xd = &cpi->mb.e_mbd;
RATE_CONTROL *const rc = &cpi->rc;
struct vpx_usec_timer cmptimer;
YV12_BUFFER_CONFIG *force_src_buffer = NULL;
MV_REFERENCE_FRAME ref_frame;
if (!cpi)
return -1;
if (cpi->svc.number_spatial_layers > 1 && cpi->pass == 2) {
vp9_restore_layer_context(cpi);
}
vpx_usec_timer_start(&cmptimer);
cpi->source = NULL;
cpi->last_source = NULL;
set_high_precision_mv(cpi, ALTREF_HIGH_PRECISION_MV);
// Normal defaults
cm->reset_frame_context = 0;
cm->refresh_frame_context = 1;
cpi->refresh_last_frame = 1;
cpi->refresh_golden_frame = 0;
cpi->refresh_alt_ref_frame = 0;
// Should we code an alternate reference frame.
if (cpi->oxcf.play_alternate && rc->source_alt_ref_pending) {
int frames_to_arf;
#if CONFIG_MULTIPLE_ARF
assert(!cpi->multi_arf_enabled ||
cpi->frame_coding_order[cpi->sequence_number] < 0);
if (cpi->multi_arf_enabled && (cpi->pass == 2))
frames_to_arf = (-cpi->frame_coding_order[cpi->sequence_number])
- cpi->next_frame_in_order;
else
#endif
frames_to_arf = rc->frames_till_gf_update_due;
assert(frames_to_arf <= rc->frames_to_key);
if ((cpi->source = vp9_lookahead_peek(cpi->lookahead, frames_to_arf))) {
#if CONFIG_MULTIPLE_ARF
cpi->alt_ref_source[cpi->arf_buffered] = cpi->source;
#else
cpi->alt_ref_source = cpi->source;
#endif
if (cpi->oxcf.arnr_max_frames > 0) {
// Produce the filtered ARF frame.
// TODO(agrange) merge these two functions.
vp9_configure_arnr_filter(cpi, frames_to_arf, rc->gfu_boost);
vp9_temporal_filter_prepare(cpi, frames_to_arf);
vp9_extend_frame_borders(&cpi->alt_ref_buffer);
force_src_buffer = &cpi->alt_ref_buffer;
}
cm->show_frame = 0;
cpi->refresh_alt_ref_frame = 1;
cpi->refresh_golden_frame = 0;
cpi->refresh_last_frame = 0;
rc->is_src_frame_alt_ref = 0;
#if CONFIG_MULTIPLE_ARF
if (!cpi->multi_arf_enabled)
#endif
rc->source_alt_ref_pending = 0;
} else {
rc->source_alt_ref_pending = 0;
}
}
if (!cpi->source) {
#if CONFIG_MULTIPLE_ARF
int i;
#endif
// Get last frame source.
if (cm->current_video_frame > 0) {
if ((cpi->last_source = vp9_lookahead_peek(cpi->lookahead, -1)) == NULL)
return -1;
}
if ((cpi->source = vp9_lookahead_pop(cpi->lookahead, flush))) {
cm->show_frame = 1;
cm->intra_only = 0;
#if CONFIG_MULTIPLE_ARF
// Is this frame the ARF overlay.
rc->is_src_frame_alt_ref = 0;
for (i = 0; i < cpi->arf_buffered; ++i) {
if (cpi->source == cpi->alt_ref_source[i]) {
rc->is_src_frame_alt_ref = 1;
cpi->refresh_golden_frame = 1;
break;
}
}
#else
rc->is_src_frame_alt_ref = cpi->alt_ref_source &&
(cpi->source == cpi->alt_ref_source);
#endif
if (rc->is_src_frame_alt_ref) {
// Current frame is an ARF overlay frame.
#if CONFIG_MULTIPLE_ARF
cpi->alt_ref_source[i] = NULL;
#else
cpi->alt_ref_source = NULL;
#endif
// Don't refresh the last buffer for an ARF overlay frame. It will
// become the GF so preserve last as an alternative prediction option.
cpi->refresh_last_frame = 0;
}
#if CONFIG_MULTIPLE_ARF
++cpi->next_frame_in_order;
#endif
}
}
if (cpi->source) {
cpi->un_scaled_source = cpi->Source = force_src_buffer ? force_src_buffer
: &cpi->source->img;
if (cpi->last_source != NULL) {
cpi->unscaled_last_source = &cpi->last_source->img;
} else {
cpi->unscaled_last_source = NULL;
}
*time_stamp = cpi->source->ts_start;
*time_end = cpi->source->ts_end;
*frame_flags = cpi->source->flags;
#if CONFIG_MULTIPLE_ARF
if (cm->frame_type != KEY_FRAME && cpi->pass == 2)
rc->source_alt_ref_pending = is_next_frame_arf(cpi);
#endif
} else {
*size = 0;
if (flush && cpi->pass == 1 && !cpi->twopass.first_pass_done) {
vp9_end_first_pass(cpi); /* get last stats packet */
cpi->twopass.first_pass_done = 1;
}
return -1;
}
if (cpi->source->ts_start < cpi->first_time_stamp_ever) {
cpi->first_time_stamp_ever = cpi->source->ts_start;
cpi->last_end_time_stamp_seen = cpi->source->ts_start;
}
// adjust frame rates based on timestamps given
if (cm->show_frame) {
adjust_frame_rate(cpi);
}
if (cpi->svc.number_temporal_layers > 1 &&
cpi->oxcf.end_usage == USAGE_STREAM_FROM_SERVER) {
vp9_update_temporal_layer_framerate(cpi);
vp9_restore_layer_context(cpi);
}
// start with a 0 size frame
*size = 0;
// Clear down mmx registers
vp9_clear_system_state();
/* find a free buffer for the new frame, releasing the reference previously
* held.
*/
cm->frame_bufs[cm->new_fb_idx].ref_count--;
cm->new_fb_idx = get_free_fb(cm);
#if CONFIG_MULTIPLE_ARF
/* Set up the correct ARF frame. */
if (cpi->refresh_alt_ref_frame) {
++cpi->arf_buffered;
}
if (cpi->multi_arf_enabled && (cm->frame_type != KEY_FRAME) &&
(cpi->pass == 2)) {
cpi->alt_fb_idx = cpi->arf_buffer_idx[cpi->sequence_number];
}
#endif
cm->frame_flags = *frame_flags;
// Reset the frame pointers to the current frame size
vp9_realloc_frame_buffer(get_frame_new_buffer(cm),
cm->width, cm->height,
cm->subsampling_x, cm->subsampling_y,
VP9_ENC_BORDER_IN_PIXELS, NULL, NULL, NULL);
for (ref_frame = LAST_FRAME; ref_frame <= ALTREF_FRAME; ++ref_frame) {
const int idx = cm->ref_frame_map[get_ref_frame_idx(cpi, ref_frame)];
YV12_BUFFER_CONFIG *const buf = &cm->frame_bufs[idx].buf;
RefBuffer *const ref_buf = &cm->frame_refs[ref_frame - 1];
ref_buf->buf = buf;
ref_buf->idx = idx;
vp9_setup_scale_factors_for_frame(&ref_buf->sf,
buf->y_crop_width, buf->y_crop_height,
cm->width, cm->height);
if (vp9_is_scaled(&ref_buf->sf))
vp9_extend_frame_borders(buf);
}
set_ref_ptrs(cm, xd, LAST_FRAME, LAST_FRAME);
if (cpi->oxcf.aq_mode == VARIANCE_AQ) {
vp9_vaq_init();
}
if (cpi->pass == 1 &&
(!cpi->use_svc || cpi->svc.number_temporal_layers == 1)) {
Pass1Encode(cpi, size, dest, frame_flags);
} else if (cpi->pass == 2 &&
(!cpi->use_svc || cpi->svc.number_temporal_layers == 1)) {
Pass2Encode(cpi, size, dest, frame_flags);
} else if (cpi->use_svc) {
SvcEncode(cpi, size, dest, frame_flags);
} else {
// One pass encode
Pass0Encode(cpi, size, dest, frame_flags);
}
if (cm->refresh_frame_context)
cm->frame_contexts[cm->frame_context_idx] = cm->fc;
// Frame was dropped, release scaled references.
if (*size == 0) {
release_scaled_references(cpi);
}
if (*size > 0) {
cpi->droppable = !frame_is_reference(cpi);
}
// Save layer specific state.
if ((cpi->svc.number_temporal_layers > 1 &&
cpi->oxcf.end_usage == USAGE_STREAM_FROM_SERVER) ||
(cpi->svc.number_spatial_layers > 1 && cpi->pass == 2)) {
vp9_save_layer_context(cpi);
}
vpx_usec_timer_mark(&cmptimer);
cpi->time_compress_data += vpx_usec_timer_elapsed(&cmptimer);
if (cpi->b_calculate_psnr && cpi->pass != 1 && cm->show_frame)
generate_psnr_packet(cpi);
#if CONFIG_INTERNAL_STATS
if (cpi->pass != 1) {
cpi->bytes += (int)(*size);
if (cm->show_frame) {
cpi->count++;
if (cpi->b_calculate_psnr) {
YV12_BUFFER_CONFIG *orig = cpi->Source;
YV12_BUFFER_CONFIG *recon = cpi->common.frame_to_show;
YV12_BUFFER_CONFIG *pp = &cm->post_proc_buffer;
PSNR_STATS psnr;
calc_psnr(orig, recon, &psnr);
cpi->total += psnr.psnr[0];
cpi->total_y += psnr.psnr[1];
cpi->total_u += psnr.psnr[2];
cpi->total_v += psnr.psnr[3];
cpi->total_sq_error += psnr.sse[0];
cpi->total_samples += psnr.samples[0];
{
PSNR_STATS psnr2;
double frame_ssim2 = 0, weight = 0;
#if CONFIG_VP9_POSTPROC
vp9_deblock(cm->frame_to_show, &cm->post_proc_buffer,
cm->lf.filter_level * 10 / 6);
#endif
vp9_clear_system_state();
calc_psnr(orig, pp, &psnr2);
cpi->totalp += psnr2.psnr[0];
cpi->totalp_y += psnr2.psnr[1];
cpi->totalp_u += psnr2.psnr[2];
cpi->totalp_v += psnr2.psnr[3];
cpi->totalp_sq_error += psnr2.sse[0];
cpi->totalp_samples += psnr2.samples[0];
frame_ssim2 = vp9_calc_ssim(orig, recon, 1, &weight);
cpi->summed_quality += frame_ssim2 * weight;
cpi->summed_weights += weight;
frame_ssim2 = vp9_calc_ssim(orig, &cm->post_proc_buffer, 1, &weight);
cpi->summedp_quality += frame_ssim2 * weight;
cpi->summedp_weights += weight;
#if 0
{
FILE *f = fopen("q_used.stt", "a");
fprintf(f, "%5d : Y%f7.3:U%f7.3:V%f7.3:F%f7.3:S%7.3f\n",
cpi->common.current_video_frame, y2, u2, v2,
frame_psnr2, frame_ssim2);
fclose(f);
}
#endif
}
}
if (cpi->b_calculate_ssimg) {
double y, u, v, frame_all;
frame_all = vp9_calc_ssimg(cpi->Source, cm->frame_to_show, &y, &u, &v);
cpi->total_ssimg_y += y;
cpi->total_ssimg_u += u;
cpi->total_ssimg_v += v;
cpi->total_ssimg_all += frame_all;
}
}
}
#endif
return 0;
}
int vp9_get_preview_raw_frame(VP9_COMP *cpi, YV12_BUFFER_CONFIG *dest,
vp9_ppflags_t *flags) {
VP9_COMMON *cm = &cpi->common;
if (!cm->show_frame) {
return -1;
} else {
int ret;
#if CONFIG_VP9_POSTPROC
ret = vp9_post_proc_frame(cm, dest, flags);
#else
if (cm->frame_to_show) {
*dest = *cm->frame_to_show;
dest->y_width = cm->width;
dest->y_height = cm->height;
dest->uv_width = cm->width >> cm->subsampling_x;
dest->uv_height = cm->height >> cm->subsampling_y;
ret = 0;
} else {
ret = -1;
}
#endif // !CONFIG_VP9_POSTPROC
vp9_clear_system_state();
return ret;
}
}
int vp9_set_roimap(VP9_COMP *cpi, unsigned char *map, unsigned int rows,
unsigned int cols, int delta_q[MAX_SEGMENTS],
int delta_lf[MAX_SEGMENTS],
unsigned int threshold[MAX_SEGMENTS]) {
signed char feature_data[SEG_LVL_MAX][MAX_SEGMENTS];
struct segmentation *seg = &cpi->common.seg;
int i;
if (cpi->common.mb_rows != rows || cpi->common.mb_cols != cols)
return -1;
if (!map) {
vp9_disable_segmentation(seg);
return 0;
}
// Set the segmentation Map
vp9_set_segmentation_map(cpi, map);
// Activate segmentation.
vp9_enable_segmentation(seg);
// Set up the quant, LF and breakout threshold segment data
for (i = 0; i < MAX_SEGMENTS; i++) {
feature_data[SEG_LVL_ALT_Q][i] = delta_q[i];
feature_data[SEG_LVL_ALT_LF][i] = delta_lf[i];
cpi->segment_encode_breakout[i] = threshold[i];
}
// Enable the loop and quant changes in the feature mask
for (i = 0; i < MAX_SEGMENTS; i++) {
if (delta_q[i])
vp9_enable_segfeature(seg, i, SEG_LVL_ALT_Q);
else
vp9_disable_segfeature(seg, i, SEG_LVL_ALT_Q);
if (delta_lf[i])
vp9_enable_segfeature(seg, i, SEG_LVL_ALT_LF);
else
vp9_disable_segfeature(seg, i, SEG_LVL_ALT_LF);
}
// Initialize the feature data structure
// SEGMENT_DELTADATA 0, SEGMENT_ABSDATA 1
vp9_set_segment_data(seg, &feature_data[0][0], SEGMENT_DELTADATA);
return 0;
}
int vp9_set_active_map(VP9_COMP *cpi, unsigned char *map,
unsigned int rows, unsigned int cols) {
if (rows == cpi->common.mb_rows && cols == cpi->common.mb_cols) {
if (map) {
vpx_memcpy(cpi->active_map, map, rows * cols);
cpi->active_map_enabled = 1;
} else {
cpi->active_map_enabled = 0;
}
return 0;
} else {
// cpi->active_map_enabled = 0;
return -1;
}
}
int vp9_set_internal_size(VP9_COMP *cpi,
VPX_SCALING horiz_mode, VPX_SCALING vert_mode) {
VP9_COMMON *cm = &cpi->common;
int hr = 0, hs = 0, vr = 0, vs = 0;
if (horiz_mode > ONETWO || vert_mode > ONETWO)
return -1;
Scale2Ratio(horiz_mode, &hr, &hs);
Scale2Ratio(vert_mode, &vr, &vs);
// always go to the next whole number
cm->width = (hs - 1 + cpi->oxcf.width * hr) / hs;
cm->height = (vs - 1 + cpi->oxcf.height * vr) / vs;
assert(cm->width <= cpi->initial_width);
assert(cm->height <= cpi->initial_height);
update_frame_size(cpi);
return 0;
}
int vp9_set_size_literal(VP9_COMP *cpi, unsigned int width,
unsigned int height) {
VP9_COMMON *cm = &cpi->common;
check_initial_width(cpi, 1, 1);
if (width) {
cm->width = width;
if (cm->width * 5 < cpi->initial_width) {
cm->width = cpi->initial_width / 5 + 1;
printf("Warning: Desired width too small, changed to %d\n", cm->width);
}
if (cm->width > cpi->initial_width) {
cm->width = cpi->initial_width;
printf("Warning: Desired width too large, changed to %d\n", cm->width);
}
}
if (height) {
cm->height = height;
if (cm->height * 5 < cpi->initial_height) {
cm->height = cpi->initial_height / 5 + 1;
printf("Warning: Desired height too small, changed to %d\n", cm->height);
}
if (cm->height > cpi->initial_height) {
cm->height = cpi->initial_height;
printf("Warning: Desired height too large, changed to %d\n", cm->height);
}
}
assert(cm->width <= cpi->initial_width);
assert(cm->height <= cpi->initial_height);
update_frame_size(cpi);
return 0;
}
void vp9_set_svc(VP9_COMP *cpi, int use_svc) {
cpi->use_svc = use_svc;
return;
}
int vp9_calc_ss_err(const YV12_BUFFER_CONFIG *source,
const YV12_BUFFER_CONFIG *reference) {
int i, j;
int total = 0;
const uint8_t *src = source->y_buffer;
const uint8_t *ref = reference->y_buffer;
// Loop through the Y plane raw and reconstruction data summing
// (square differences)
for (i = 0; i < source->y_height; i += 16) {
for (j = 0; j < source->y_width; j += 16) {
unsigned int sse;
total += vp9_mse16x16(src + j, source->y_stride,
ref + j, reference->y_stride, &sse);
}
src += 16 * source->y_stride;
ref += 16 * reference->y_stride;
}
return total;
}
int vp9_get_quantizer(VP9_COMP *cpi) {
return cpi->common.base_qindex;
}
| 31.92525 | 80 | 0.63893 |
b1343ba0612ecb0bcf8c37636063a1802b17eb2f | 888 | h | C | System/Library/PrivateFrameworks/OfficeImport.framework/OADCountedGraphicFeature.h | lechium/iOS1351Headers | 6bed3dada5ffc20366b27f7f2300a24a48a6284e | [
"MIT"
] | 2 | 2021-11-02T09:23:27.000Z | 2022-03-28T08:21:57.000Z | System/Library/PrivateFrameworks/OfficeImport.framework/OADCountedGraphicFeature.h | lechium/iOS1351Headers | 6bed3dada5ffc20366b27f7f2300a24a48a6284e | [
"MIT"
] | null | null | null | System/Library/PrivateFrameworks/OfficeImport.framework/OADCountedGraphicFeature.h | lechium/iOS1351Headers | 6bed3dada5ffc20366b27f7f2300a24a48a6284e | [
"MIT"
] | 1 | 2022-03-28T08:21:59.000Z | 2022-03-28T08:21:59.000Z | /*
* This header is generated by classdump-dyld 1.5
* on Wednesday, October 27, 2021 at 3:22:41 PM Mountain Standard Time
* Operating System: Version 13.5.1 (Build 17F80)
* Image Source: /System/Library/PrivateFrameworks/OfficeImport.framework/OfficeImport
* classdump-dyld is licensed under GPLv3, Copyright © 2013-2016 by Elias Limneos. Updated by Kevin Bradley.
*/
@interface OADCountedGraphicFeature : NSObject {
id mFeature;
unsigned long long mUsageCount;
}
@property (assign,nonatomic) unsigned long long usageCount;
-(void)dealloc;
-(id)feature;
-(id)initWithFeature:(id)arg1 ;
-(unsigned long long)usageCount;
-(void)setUsageCount:(unsigned long long)arg1 ;
-(void)incrementUsageCount;
-(long long)compareUsageCount:(id)arg1 ;
@end
| 32.888889 | 130 | 0.648649 |
366fceafd72aea42f49cfb8fc8b56fdbd44f9741 | 1,557 | h | C | MM_EMJGameProject/Plugins/Wwise/Source/AkAudio/Classes/Platforms/AkUEPlatform.h | MicosMacosGames/EpicMegaJam_MicosMacos | 1db45728a88c7af25ce2e6d0de23bf54c1f05bc6 | [
"MIT"
] | 1 | 2020-12-11T21:06:19.000Z | 2020-12-11T21:06:19.000Z | MM_EMJGameProject/Plugins/Wwise/Source/AkAudio/Classes/Platforms/AkUEPlatform.h | MicosMacosGames/EpicMegaJam_MicosMacos | 1db45728a88c7af25ce2e6d0de23bf54c1f05bc6 | [
"MIT"
] | null | null | null | MM_EMJGameProject/Plugins/Wwise/Source/AkAudio/Classes/Platforms/AkUEPlatform.h | MicosMacosGames/EpicMegaJam_MicosMacos | 1db45728a88c7af25ce2e6d0de23bf54c1f05bc6 | [
"MIT"
] | null | null | null | #pragma once
#include "AkInclude.h"
#if PLATFORM_ANDROID && !PLATFORM_LUMIN
#include "AkPlatform_Android/AkAndroidPlatform.h"
#elif PLATFORM_TVOS
#include "AkPlatform_tvOS/AkTVOSPlatform.h"
#elif PLATFORM_IOS && !PLATFORM_TVOS
#include "AkPlatform_iOS/AkIOSPlatform.h"
#elif PLATFORM_LINUX
#include "AkPlatform_Linux/AkLinuxPlatform.h"
#elif PLATFORM_LUMIN
#include "AkPlatform_Lumin/AkLuminPlatform.h"
#elif PLATFORM_MAC
#include "AkPlatform_Mac/AkMacPlatform.h"
#elif PLATFORM_PS4
#include "AkPlatform_PS4/AkPS4Platform.h"
#elif defined(PLATFORM_STADIA) && PLATFORM_STADIA
#include "AkPlatform_Stadia/AkStadiaPlatform.h"
#elif PLATFORM_SWITCH
#include "AkPlatform_Switch/AkSwitchPlatform.h"
#elif PLATFORM_HOLOLENS
#include "AkPlatform_Hololens/AkHololensPlatform.h"
#elif defined(AK_GDX)
#include "AkPlatform_GDX/AkGDXPlatform.h"
#elif PLATFORM_WINDOWS
#include "AkPlatform_Windows/AkWindowsPlatform.h"
#elif defined(AK_GX)
#include "AkPlatform_GX/AkGXPlatform.h"
#elif PLATFORM_XBOXONE
#include "AkPlatform_XboxOne/AkXboxOnePlatform.h"
#elif defined(AK_PELLEGRINO)
#include "AkPlatform_Pellegrino/AkPellegrinoPlatform.h"
#elif defined(AK_CHINOOK)
#include "AkPlatform_Chinook/AkChinookPlatform.h"
#else
#error "The Wwise plug-in does not support the current build platform."
#endif
namespace AkUnrealPlatformHelper
{
AKAUDIO_API TSet<FString> GetAllSupportedUnrealPlatforms();
AKAUDIO_API TSet<FString> GetAllSupportedUnrealPlatformsForProject();
AKAUDIO_API TArray<TSharedPtr<FString> > GetAllSupportedWwisePlatforms(bool ProjectScope = false);
} | 33.847826 | 99 | 0.836224 |
3c4c1c2bfb53abee072576d366a1b6bfac63513e | 499 | h | C | Squid/UILabel+FormattedText.h | ldong/Squid | 7337109c670b1661a99dc9ab63c243aabf2bef65 | [
"MIT"
] | null | null | null | Squid/UILabel+FormattedText.h | ldong/Squid | 7337109c670b1661a99dc9ab63c243aabf2bef65 | [
"MIT"
] | null | null | null | Squid/UILabel+FormattedText.h | ldong/Squid | 7337109c670b1661a99dc9ab63c243aabf2bef65 | [
"MIT"
] | null | null | null | //
// UILabel+FormattedText.h
// UILabel+FormattedText
//
// Created by Joao Costa on 3/1/13.
// Copyright (c) 2013 none. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface UILabel (FormattedText)
- (void)setTextColor:(UIColor *)textColor range:(NSRange)range;
- (void)setFont:(UIFont *)font range:(NSRange)range;
- (void)setTextColor:(UIColor *)textColor afterOccurenceOfString:(NSString*)separator;
- (void)setFont:(UIFont *)font afterOccurenceOfString:(NSString*)separator;
@end
| 24.95 | 86 | 0.735471 |
82d0fa6221eb30c28915cb94f177381425ee7666 | 6,510 | c | C | labs/lab6/code/ExceptionAndCache/isim/Datapath_isim_beh.exe.sim/work/a_1543952170_3212880686.c | Manwlis/MIPS-CPU | b2dcbc23d873f68089be798faba63ff76e78279c | [
"MIT"
] | 1 | 2018-12-20T00:22:19.000Z | 2018-12-20T00:22:19.000Z | labs/lab6/code/ExceptionAndCache/isim/Datapath_isim_beh.exe.sim/work/a_1543952170_3212880686.c | Manwlis/HRY312-lab | b2dcbc23d873f68089be798faba63ff76e78279c | [
"MIT"
] | null | null | null | labs/lab6/code/ExceptionAndCache/isim/Datapath_isim_beh.exe.sim/work/a_1543952170_3212880686.c | Manwlis/HRY312-lab | b2dcbc23d873f68089be798faba63ff76e78279c | [
"MIT"
] | null | null | null | /**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xc3576ebc */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "C:/Users/Mike/Desktop/organwsh/lab6/ExceptionAndCache/compareModule.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_1605435078_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_853553178_503743352(char *, unsigned char , unsigned char );
static void work_a_1543952170_3212880686_p_0(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
int t5;
unsigned int t6;
unsigned int t7;
unsigned int t8;
unsigned char t9;
char *t10;
char *t11;
int t12;
unsigned int t13;
unsigned int t14;
unsigned int t15;
unsigned char t16;
unsigned char t17;
char *t18;
char *t19;
int t20;
unsigned int t21;
unsigned int t22;
unsigned int t23;
unsigned char t24;
char *t25;
char *t26;
int t27;
unsigned int t28;
unsigned int t29;
unsigned int t30;
unsigned char t31;
unsigned char t32;
unsigned char t33;
char *t34;
char *t35;
int t36;
unsigned int t37;
unsigned int t38;
unsigned int t39;
unsigned char t40;
char *t41;
char *t42;
int t43;
unsigned int t44;
unsigned int t45;
unsigned int t46;
unsigned char t47;
unsigned char t48;
unsigned char t49;
char *t50;
char *t51;
int t52;
unsigned int t53;
unsigned int t54;
unsigned int t55;
unsigned char t56;
char *t57;
char *t58;
int t59;
unsigned int t60;
unsigned int t61;
unsigned int t62;
unsigned char t63;
unsigned char t64;
unsigned char t65;
char *t66;
char *t67;
int t68;
unsigned int t69;
unsigned int t70;
unsigned int t71;
unsigned char t72;
char *t73;
char *t74;
int t75;
unsigned int t76;
unsigned int t77;
unsigned int t78;
unsigned char t79;
unsigned char t80;
unsigned char t81;
unsigned char t82;
char *t83;
char *t84;
char *t85;
char *t86;
char *t87;
char *t88;
LAB0: xsi_set_current_line(15, ng0);
LAB3: t1 = (t0 + 1352U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1032U);
t4 = *((char **)t1);
t5 = (4 - 4);
t6 = (t5 * -1);
t7 = (1U * t6);
t8 = (0 + t7);
t1 = (t4 + t8);
t9 = *((unsigned char *)t1);
t10 = (t0 + 1192U);
t11 = *((char **)t10);
t12 = (4 - 4);
t13 = (t12 * -1);
t14 = (1U * t13);
t15 = (0 + t14);
t10 = (t11 + t15);
t16 = *((unsigned char *)t10);
t17 = ieee_p_2592010699_sub_853553178_503743352(IEEE_P_2592010699, t9, t16);
t18 = (t0 + 1032U);
t19 = *((char **)t18);
t20 = (3 - 4);
t21 = (t20 * -1);
t22 = (1U * t21);
t23 = (0 + t22);
t18 = (t19 + t23);
t24 = *((unsigned char *)t18);
t25 = (t0 + 1192U);
t26 = *((char **)t25);
t27 = (3 - 4);
t28 = (t27 * -1);
t29 = (1U * t28);
t30 = (0 + t29);
t25 = (t26 + t30);
t31 = *((unsigned char *)t25);
t32 = ieee_p_2592010699_sub_853553178_503743352(IEEE_P_2592010699, t24, t31);
t33 = ieee_p_2592010699_sub_1605435078_503743352(IEEE_P_2592010699, t17, t32);
t34 = (t0 + 1032U);
t35 = *((char **)t34);
t36 = (2 - 4);
t37 = (t36 * -1);
t38 = (1U * t37);
t39 = (0 + t38);
t34 = (t35 + t39);
t40 = *((unsigned char *)t34);
t41 = (t0 + 1192U);
t42 = *((char **)t41);
t43 = (2 - 4);
t44 = (t43 * -1);
t45 = (1U * t44);
t46 = (0 + t45);
t41 = (t42 + t46);
t47 = *((unsigned char *)t41);
t48 = ieee_p_2592010699_sub_853553178_503743352(IEEE_P_2592010699, t40, t47);
t49 = ieee_p_2592010699_sub_1605435078_503743352(IEEE_P_2592010699, t33, t48);
t50 = (t0 + 1032U);
t51 = *((char **)t50);
t52 = (1 - 4);
t53 = (t52 * -1);
t54 = (1U * t53);
t55 = (0 + t54);
t50 = (t51 + t55);
t56 = *((unsigned char *)t50);
t57 = (t0 + 1192U);
t58 = *((char **)t57);
t59 = (1 - 4);
t60 = (t59 * -1);
t61 = (1U * t60);
t62 = (0 + t61);
t57 = (t58 + t62);
t63 = *((unsigned char *)t57);
t64 = ieee_p_2592010699_sub_853553178_503743352(IEEE_P_2592010699, t56, t63);
t65 = ieee_p_2592010699_sub_1605435078_503743352(IEEE_P_2592010699, t49, t64);
t66 = (t0 + 1032U);
t67 = *((char **)t66);
t68 = (0 - 4);
t69 = (t68 * -1);
t70 = (1U * t69);
t71 = (0 + t70);
t66 = (t67 + t71);
t72 = *((unsigned char *)t66);
t73 = (t0 + 1192U);
t74 = *((char **)t73);
t75 = (0 - 4);
t76 = (t75 * -1);
t77 = (1U * t76);
t78 = (0 + t77);
t73 = (t74 + t78);
t79 = *((unsigned char *)t73);
t80 = ieee_p_2592010699_sub_853553178_503743352(IEEE_P_2592010699, t72, t79);
t81 = ieee_p_2592010699_sub_1605435078_503743352(IEEE_P_2592010699, t65, t80);
t82 = ieee_p_2592010699_sub_1605435078_503743352(IEEE_P_2592010699, t3, t81);
t83 = (t0 + 3072);
t84 = (t83 + 56U);
t85 = *((char **)t84);
t86 = (t85 + 56U);
t87 = *((char **)t86);
*((unsigned char *)t87) = t82;
xsi_driver_first_trans_fast_port(t83);
LAB2: t88 = (t0 + 2992);
*((int *)t88) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_1543952170_3212880686_init()
{
static char *pe[] = {(void *)work_a_1543952170_3212880686_p_0};
xsi_register_didat("work_a_1543952170_3212880686", "isim/Datapath_isim_beh.exe.sim/work/a_1543952170_3212880686.didat");
xsi_register_executes(pe);
}
| 27.125 | 121 | 0.514439 |
89ce436b7ca5d0a14ea2809749f449397e567ea0 | 23,824 | c | C | SecurityPkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.c | christopherco/RPi-UEFI | 48fd8bb20dd4d45a4cf0a8970a65837e45bbaa99 | [
"BSD-2-Clause"
] | 93 | 2016-10-27T12:03:57.000Z | 2022-03-29T15:22:10.000Z | SecurityPkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.c | khezami/RPi-UEFI | 5bfd48d674e6c7efea6e31f9eb97b9da90c20263 | [
"BSD-2-Clause"
] | 16 | 2016-11-02T02:08:40.000Z | 2021-06-03T21:18:06.000Z | SecurityPkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.c | khezami/RPi-UEFI | 5bfd48d674e6c7efea6e31f9eb97b9da90c20263 | [
"BSD-2-Clause"
] | 41 | 2016-11-02T00:05:02.000Z | 2022-03-29T14:33:09.000Z | /** @file
Execute pending TPM2 requests from OS or BIOS.
Caution: This module requires additional review when modified.
This driver will have external input - variable.
This external input must be validated carefully to avoid security issue.
TrEEExecutePendingTpmRequest() will receive untrusted input and do validation.
Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include <Protocol/TrEEProtocol.h>
#include <Protocol/VariableLock.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PrintLib.h>
#include <Library/HiiLib.h>
#include <Guid/EventGroup.h>
#include <Guid/TrEEPhysicalPresenceData.h>
#include <Library/Tpm2CommandLib.h>
#define TPM_PP_SUCCESS 0
#define TPM_PP_USER_ABORT ((TPM_RESULT)(-0x10))
#define TPM_PP_BIOS_FAILURE ((TPM_RESULT)(-0x0f))
#define CONFIRM_BUFFER_SIZE 4096
EFI_HII_HANDLE mTrEEPpStringPackHandle;
/**
Get string by string id from HII Interface.
@param[in] Id String ID.
@retval CHAR16 * String from ID.
@retval NULL If error occurs.
**/
CHAR16 *
TrEEPhysicalPresenceGetStringById (
IN EFI_STRING_ID Id
)
{
return HiiGetString (mTrEEPpStringPackHandle, Id, NULL);
}
/**
Send ClearControl and Clear command to TPM.
@param[in] PlatformAuth platform auth value. NULL means no platform auth change.
@retval EFI_SUCCESS Operation completed successfully.
@retval EFI_TIMEOUT The register can't run into the expected status in time.
@retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.
@retval EFI_DEVICE_ERROR Unexpected device behavior.
**/
EFI_STATUS
EFIAPI
TpmCommandClear (
IN TPM2B_AUTH *PlatformAuth OPTIONAL
)
{
EFI_STATUS Status;
TPMS_AUTH_COMMAND *AuthSession;
TPMS_AUTH_COMMAND LocalAuthSession;
if (PlatformAuth == NULL) {
AuthSession = NULL;
} else {
AuthSession = &LocalAuthSession;
ZeroMem (&LocalAuthSession, sizeof(LocalAuthSession));
LocalAuthSession.sessionHandle = TPM_RS_PW;
LocalAuthSession.hmac.size = PlatformAuth->size;
CopyMem (LocalAuthSession.hmac.buffer, PlatformAuth->buffer, PlatformAuth->size);
}
DEBUG ((EFI_D_INFO, "Tpm2ClearControl ... \n"));
Status = Tpm2ClearControl (TPM_RH_PLATFORM, AuthSession, NO);
DEBUG ((EFI_D_INFO, "Tpm2ClearControl - %r\n", Status));
if (EFI_ERROR (Status)) {
goto Done;
}
DEBUG ((EFI_D_INFO, "Tpm2Clear ... \n"));
Status = Tpm2Clear (TPM_RH_PLATFORM, AuthSession);
DEBUG ((EFI_D_INFO, "Tpm2Clear - %r\n", Status));
Done:
ZeroMem (&LocalAuthSession.hmac, sizeof(LocalAuthSession.hmac));
return Status;
}
/**
Execute physical presence operation requested by the OS.
@param[in] PlatformAuth platform auth value. NULL means no platform auth change.
@param[in] CommandCode Physical presence operation value.
@param[in, out] PpiFlags The physical presence interface flags.
@retval TPM_PP_BIOS_FAILURE Unknown physical presence operation.
@retval TPM_PP_BIOS_FAILURE Error occurred during sending command to TPM or
receiving response from TPM.
@retval Others Return code from the TPM device after command execution.
**/
TPM_RESULT
TrEEExecutePhysicalPresence (
IN TPM2B_AUTH *PlatformAuth, OPTIONAL
IN UINT8 CommandCode,
IN OUT UINT8 *PpiFlags
)
{
EFI_STATUS Status;
switch (CommandCode) {
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_2:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_3:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_4:
Status = TpmCommandClear (PlatformAuth);
if (EFI_ERROR (Status)) {
return TPM_PP_BIOS_FAILURE;
} else {
return TPM_PP_SUCCESS;
}
case TREE_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_FALSE:
*PpiFlags &= ~TREE_FLAG_NO_PPI_CLEAR;
return TPM_PP_SUCCESS;
case TREE_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_TRUE:
*PpiFlags |= TREE_FLAG_NO_PPI_CLEAR;
return TPM_PP_SUCCESS;
default:
if (CommandCode <= TREE_PHYSICAL_PRESENCE_NO_ACTION_MAX) {
return TPM_PP_SUCCESS;
} else {
return TPM_PP_BIOS_FAILURE;
}
}
}
/**
Read the specified key for user confirmation.
@param[in] CautionKey If true, F12 is used as confirm key;
If false, F10 is used as confirm key.
@retval TRUE User confirmed the changes by input.
@retval FALSE User discarded the changes.
**/
BOOLEAN
TrEEReadUserKey (
IN BOOLEAN CautionKey
)
{
EFI_STATUS Status;
EFI_INPUT_KEY Key;
UINT16 InputKey;
InputKey = 0;
do {
Status = gBS->CheckEvent (gST->ConIn->WaitForKey);
if (!EFI_ERROR (Status)) {
Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
if (Key.ScanCode == SCAN_ESC) {
InputKey = Key.ScanCode;
}
if ((Key.ScanCode == SCAN_F10) && !CautionKey) {
InputKey = Key.ScanCode;
}
if ((Key.ScanCode == SCAN_F12) && CautionKey) {
InputKey = Key.ScanCode;
}
}
} while (InputKey == 0);
if (InputKey != SCAN_ESC) {
return TRUE;
}
return FALSE;
}
/**
The constructor function register UNI strings into imageHandle.
It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
@param ImageHandle The firmware allocated handle for the EFI image.
@param SystemTable A pointer to the EFI System Table.
@retval EFI_SUCCESS The constructor successfully added string package.
@retval Other value The constructor can't add string package.
**/
EFI_STATUS
EFIAPI
TrEEPhysicalPresenceLibConstructor (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
mTrEEPpStringPackHandle = HiiAddPackages (&gEfiTrEEPhysicalPresenceGuid, ImageHandle, DxeTrEEPhysicalPresenceLibStrings, NULL);
ASSERT (mTrEEPpStringPackHandle != NULL);
return EFI_SUCCESS;
}
/**
Display the confirm text and get user confirmation.
@param[in] TpmPpCommand The requested TPM physical presence command.
@retval TRUE The user has confirmed the changes.
@retval FALSE The user doesn't confirm the changes.
**/
BOOLEAN
TrEEUserConfirm (
IN UINT8 TpmPpCommand
)
{
CHAR16 *ConfirmText;
CHAR16 *TmpStr1;
CHAR16 *TmpStr2;
UINTN BufSize;
BOOLEAN CautionKey;
UINT16 Index;
CHAR16 DstStr[81];
TmpStr2 = NULL;
CautionKey = FALSE;
BufSize = CONFIRM_BUFFER_SIZE;
ConfirmText = AllocateZeroPool (BufSize);
ASSERT (ConfirmText != NULL);
switch (TpmPpCommand) {
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_2:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_3:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_4:
CautionKey = TRUE;
TmpStr2 = TrEEPhysicalPresenceGetStringById (STRING_TOKEN (TPM_CLEAR));
TmpStr1 = TrEEPhysicalPresenceGetStringById (STRING_TOKEN (TPM_HEAD_STR));
UnicodeSPrint (ConfirmText, BufSize, TmpStr1, TmpStr2);
FreePool (TmpStr1);
TmpStr1 = TrEEPhysicalPresenceGetStringById (STRING_TOKEN (TPM_WARNING_CLEAR));
StrnCat (ConfirmText, TmpStr1, (BufSize / sizeof (CHAR16)) - StrLen (ConfirmText) - 1);
StrnCat (ConfirmText, L" \n\n", (BufSize / sizeof (CHAR16)) - StrLen (ConfirmText) - 1);
FreePool (TmpStr1);
TmpStr1 = TrEEPhysicalPresenceGetStringById (STRING_TOKEN (TPM_CAUTION_KEY));
StrnCat (ConfirmText, TmpStr1, (BufSize / sizeof (CHAR16)) - StrLen (ConfirmText) - 1);
FreePool (TmpStr1);
break;
case TREE_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_TRUE:
CautionKey = TRUE;
TmpStr2 = TrEEPhysicalPresenceGetStringById (STRING_TOKEN (TPM_CLEAR));
TmpStr1 = TrEEPhysicalPresenceGetStringById (STRING_TOKEN (TPM_PPI_HEAD_STR));
UnicodeSPrint (ConfirmText, BufSize, TmpStr1, TmpStr2);
FreePool (TmpStr1);
TmpStr1 = TrEEPhysicalPresenceGetStringById (STRING_TOKEN (TPM_NOTE_CLEAR));
StrnCat (ConfirmText, TmpStr1, (BufSize / sizeof (CHAR16)) - StrLen (ConfirmText) - 1);
FreePool (TmpStr1);
TmpStr1 = TrEEPhysicalPresenceGetStringById (STRING_TOKEN (TPM_WARNING_CLEAR));
StrnCat (ConfirmText, TmpStr1, (BufSize / sizeof (CHAR16)) - StrLen (ConfirmText) - 1);
StrnCat (ConfirmText, L" \n\n", (BufSize / sizeof (CHAR16)) - StrLen (ConfirmText) - 1);
FreePool (TmpStr1);
TmpStr1 = TrEEPhysicalPresenceGetStringById (STRING_TOKEN (TPM_CAUTION_KEY));
StrnCat (ConfirmText, TmpStr1, (BufSize / sizeof (CHAR16)) - StrLen (ConfirmText) - 1);
FreePool (TmpStr1);
TmpStr1 = TrEEPhysicalPresenceGetStringById (STRING_TOKEN (TPM_NO_PPI_INFO));
StrnCat (ConfirmText, TmpStr1, (BufSize / sizeof (CHAR16)) - StrLen (ConfirmText) - 1);
FreePool (TmpStr1);
break;
default:
;
}
if (TmpStr2 == NULL) {
FreePool (ConfirmText);
return FALSE;
}
TmpStr1 = TrEEPhysicalPresenceGetStringById (STRING_TOKEN (TPM_REJECT_KEY));
BufSize -= StrSize (ConfirmText);
UnicodeSPrint (ConfirmText + StrLen (ConfirmText), BufSize, TmpStr1, TmpStr2);
DstStr[80] = L'\0';
for (Index = 0; Index < StrLen (ConfirmText); Index += 80) {
StrnCpy(DstStr, ConfirmText + Index, 80);
Print (DstStr);
}
FreePool (TmpStr1);
FreePool (TmpStr2);
FreePool (ConfirmText);
if (TrEEReadUserKey (CautionKey)) {
return TRUE;
}
return FALSE;
}
/**
Check if there is a valid physical presence command request. Also updates parameter value
to whether the requested physical presence command already confirmed by user
@param[in] TcgPpData EFI TrEE Physical Presence request data.
@param[in] Flags The physical presence interface flags.
@param[out] RequestConfirmed If the physical presence operation command required user confirm from UI.
True, it indicates the command doesn't require user confirm, or already confirmed
in last boot cycle by user.
False, it indicates the command need user confirm from UI.
@retval TRUE Physical Presence operation command is valid.
@retval FALSE Physical Presence operation command is invalid.
**/
BOOLEAN
TrEEHaveValidTpmRequest (
IN EFI_TREE_PHYSICAL_PRESENCE *TcgPpData,
IN UINT8 Flags,
OUT BOOLEAN *RequestConfirmed
)
{
*RequestConfirmed = FALSE;
switch (TcgPpData->PPRequest) {
case TREE_PHYSICAL_PRESENCE_NO_ACTION:
*RequestConfirmed = TRUE;
return TRUE;
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_2:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_3:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_4:
if ((Flags & TREE_FLAG_NO_PPI_CLEAR) != 0) {
*RequestConfirmed = TRUE;
}
break;
case TREE_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_FALSE:
*RequestConfirmed = TRUE;
break;
case TREE_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_TRUE:
break;
default:
//
// Wrong Physical Presence command
//
return FALSE;
}
if ((Flags & TREE_FLAG_RESET_TRACK) != 0) {
//
// It had been confirmed in last boot, it doesn't need confirm again.
//
*RequestConfirmed = TRUE;
}
//
// Physical Presence command is correct
//
return TRUE;
}
/**
Check and execute the requested physical presence command.
Caution: This function may receive untrusted input.
TcgPpData variable is external input, so this function will validate
its data structure to be valid value.
@param[in] PlatformAuth platform auth value. NULL means no platform auth change.
@param[in] TcgPpData Point to the physical presence NV variable.
@param[in] Flags The physical presence interface flags.
**/
VOID
TrEEExecutePendingTpmRequest (
IN TPM2B_AUTH *PlatformAuth, OPTIONAL
IN EFI_TREE_PHYSICAL_PRESENCE *TcgPpData,
IN UINT8 Flags
)
{
EFI_STATUS Status;
UINTN DataSize;
BOOLEAN RequestConfirmed;
UINT8 NewFlags;
if (TcgPpData->PPRequest == TREE_PHYSICAL_PRESENCE_NO_ACTION) {
//
// No operation request
//
return;
}
if (!TrEEHaveValidTpmRequest(TcgPpData, Flags, &RequestConfirmed)) {
//
// Invalid operation request.
//
if (TcgPpData->PPRequest <= TREE_PHYSICAL_PRESENCE_NO_ACTION_MAX) {
TcgPpData->PPResponse = TPM_PP_SUCCESS;
} else {
TcgPpData->PPResponse = TPM_PP_BIOS_FAILURE;
}
TcgPpData->LastPPRequest = TcgPpData->PPRequest;
TcgPpData->PPRequest = TREE_PHYSICAL_PRESENCE_NO_ACTION;
DataSize = sizeof (EFI_TREE_PHYSICAL_PRESENCE);
Status = gRT->SetVariable (
TREE_PHYSICAL_PRESENCE_VARIABLE,
&gEfiTrEEPhysicalPresenceGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
DataSize,
TcgPpData
);
return;
}
if (!RequestConfirmed) {
//
// Print confirm text and wait for approval.
//
RequestConfirmed = TrEEUserConfirm (TcgPpData->PPRequest
);
}
//
// Execute requested physical presence command
//
TcgPpData->PPResponse = TPM_PP_USER_ABORT;
NewFlags = Flags;
if (RequestConfirmed) {
TcgPpData->PPResponse = TrEEExecutePhysicalPresence (PlatformAuth, TcgPpData->PPRequest,
&NewFlags);
}
//
// Save the flags if it is updated.
//
if (Flags != NewFlags) {
Status = gRT->SetVariable (
TREE_PHYSICAL_PRESENCE_FLAGS_VARIABLE,
&gEfiTrEEPhysicalPresenceGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
sizeof (UINT8),
&NewFlags
);
}
//
// Clear request
//
if ((NewFlags & TREE_FLAG_RESET_TRACK) == 0) {
TcgPpData->LastPPRequest = TcgPpData->PPRequest;
TcgPpData->PPRequest = TREE_PHYSICAL_PRESENCE_NO_ACTION;
}
//
// Save changes
//
DataSize = sizeof (EFI_TREE_PHYSICAL_PRESENCE);
Status = gRT->SetVariable (
TREE_PHYSICAL_PRESENCE_VARIABLE,
&gEfiTrEEPhysicalPresenceGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
DataSize,
TcgPpData
);
if (EFI_ERROR (Status)) {
return;
}
if (TcgPpData->PPResponse == TPM_PP_USER_ABORT) {
return;
}
//
// Reset system to make new TPM settings in effect
//
switch (TcgPpData->LastPPRequest) {
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_2:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_3:
case TREE_PHYSICAL_PRESENCE_CLEAR_CONTROL_CLEAR_4:
break;
default:
if (TcgPpData->PPRequest != TREE_PHYSICAL_PRESENCE_NO_ACTION) {
break;
}
return;
}
Print (L"Rebooting system to make TPM2 settings in effect\n");
gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
ASSERT (FALSE);
}
/**
Check and execute the pending TPM request.
The TPM request may come from OS or BIOS. This API will display request information and wait
for user confirmation if TPM request exists. The TPM request will be sent to TPM device after
the TPM request is confirmed, and one or more reset may be required to make TPM request to
take effect.
This API should be invoked after console in and console out are all ready as they are required
to display request information and get user input to confirm the request.
@param[in] PlatformAuth platform auth value. NULL means no platform auth change.
**/
VOID
EFIAPI
TrEEPhysicalPresenceLibProcessRequest (
IN TPM2B_AUTH *PlatformAuth OPTIONAL
)
{
EFI_STATUS Status;
UINTN DataSize;
EFI_TREE_PHYSICAL_PRESENCE TcgPpData;
EFI_TREE_PROTOCOL *TreeProtocol;
EDKII_VARIABLE_LOCK_PROTOCOL *VariableLockProtocol;
UINT8 PpiFlags;
Status = gBS->LocateProtocol (&gEfiTrEEProtocolGuid, NULL, (VOID **) &TreeProtocol);
if (EFI_ERROR (Status)) {
return ;
}
//
// Initialize physical presence flags.
//
DataSize = sizeof (UINT8);
Status = gRT->GetVariable (
TREE_PHYSICAL_PRESENCE_FLAGS_VARIABLE,
&gEfiTrEEPhysicalPresenceGuid,
NULL,
&DataSize,
&PpiFlags
);
if (EFI_ERROR (Status)) {
PpiFlags = 0;
Status = gRT->SetVariable (
TREE_PHYSICAL_PRESENCE_FLAGS_VARIABLE,
&gEfiTrEEPhysicalPresenceGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
sizeof (UINT8),
&PpiFlags
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "[TPM2] Set physical presence flag failed, Status = %r\n", Status));
return ;
}
}
DEBUG ((EFI_D_INFO, "[TPM2] PpiFlags = %x\n", PpiFlags));
//
// This flags variable controls whether physical presence is required for TPM command.
// It should be protected from malicious software. We set it as read-only variable here.
//
Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **)&VariableLockProtocol);
if (!EFI_ERROR (Status)) {
Status = VariableLockProtocol->RequestToLock (
VariableLockProtocol,
TREE_PHYSICAL_PRESENCE_FLAGS_VARIABLE,
&gEfiTrEEPhysicalPresenceGuid
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "[TPM2] Error when lock variable %s, Status = %r\n", TREE_PHYSICAL_PRESENCE_FLAGS_VARIABLE, Status));
ASSERT_EFI_ERROR (Status);
}
}
//
// Initialize physical presence variable.
//
DataSize = sizeof (EFI_TREE_PHYSICAL_PRESENCE);
Status = gRT->GetVariable (
TREE_PHYSICAL_PRESENCE_VARIABLE,
&gEfiTrEEPhysicalPresenceGuid,
NULL,
&DataSize,
&TcgPpData
);
if (EFI_ERROR (Status)) {
ZeroMem ((VOID*)&TcgPpData, sizeof (TcgPpData));
DataSize = sizeof (EFI_TREE_PHYSICAL_PRESENCE);
Status = gRT->SetVariable (
TREE_PHYSICAL_PRESENCE_VARIABLE,
&gEfiTrEEPhysicalPresenceGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
DataSize,
&TcgPpData
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "[TPM2] Set physical presence variable failed, Status = %r\n", Status));
return ;
}
}
DEBUG ((EFI_D_INFO, "[TPM2] Flags=%x, PPRequest=%x (LastPPRequest=%x)\n", PpiFlags, TcgPpData.PPRequest, TcgPpData.LastPPRequest));
//
// Execute pending TPM request.
//
TrEEExecutePendingTpmRequest (PlatformAuth, &TcgPpData, PpiFlags);
DEBUG ((EFI_D_INFO, "[TPM2] PPResponse = %x (LastPPRequest=%x, Flags=%x)\n", TcgPpData.PPResponse, TcgPpData.LastPPRequest, PpiFlags));
}
/**
Check if the pending TPM request needs user input to confirm.
The TPM request may come from OS. This API will check if TPM request exists and need user
input to confirmation.
@retval TRUE TPM needs input to confirm user physical presence.
@retval FALSE TPM doesn't need input to confirm user physical presence.
**/
BOOLEAN
EFIAPI
TrEEPhysicalPresenceLibNeedUserConfirm(
VOID
)
{
EFI_STATUS Status;
EFI_TREE_PHYSICAL_PRESENCE TcgPpData;
UINTN DataSize;
BOOLEAN RequestConfirmed;
EFI_TREE_PROTOCOL *TreeProtocol;
UINT8 PpiFlags;
Status = gBS->LocateProtocol (&gEfiTrEEProtocolGuid, NULL, (VOID **) &TreeProtocol);
if (EFI_ERROR (Status)) {
return FALSE;
}
//
// Check Tpm requests
//
DataSize = sizeof (EFI_TREE_PHYSICAL_PRESENCE);
Status = gRT->GetVariable (
TREE_PHYSICAL_PRESENCE_VARIABLE,
&gEfiTrEEPhysicalPresenceGuid,
NULL,
&DataSize,
&TcgPpData
);
if (EFI_ERROR (Status)) {
return FALSE;
}
DataSize = sizeof (UINT8);
Status = gRT->GetVariable (
TREE_PHYSICAL_PRESENCE_FLAGS_VARIABLE,
&gEfiTrEEPhysicalPresenceGuid,
NULL,
&DataSize,
&PpiFlags
);
if (EFI_ERROR (Status)) {
return FALSE;
}
if (TcgPpData.PPRequest == TREE_PHYSICAL_PRESENCE_NO_ACTION) {
//
// No operation request
//
return FALSE;
}
if (!TrEEHaveValidTpmRequest(&TcgPpData, PpiFlags, &RequestConfirmed)) {
//
// Invalid operation request.
//
return FALSE;
}
if (!RequestConfirmed) {
//
// Need UI to confirm
//
return TRUE;
}
return FALSE;
}
| 33.13491 | 138 | 0.618662 |
964823841efe955187d595e87768928b1f7ee658 | 7,168 | c | C | linux-5.0.1/net/tipc/trace.c | Ponny035/LFS | 7ae2280072d71f43e395149d0ad0692483a24b70 | [
"Unlicense"
] | null | null | null | linux-5.0.1/net/tipc/trace.c | Ponny035/LFS | 7ae2280072d71f43e395149d0ad0692483a24b70 | [
"Unlicense"
] | null | null | null | linux-5.0.1/net/tipc/trace.c | Ponny035/LFS | 7ae2280072d71f43e395149d0ad0692483a24b70 | [
"Unlicense"
] | null | null | null | /*
* net/tipc/trace.c: TIPC tracepoints code
*
* Copyright (c) 2018, Ericsson AB
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the names of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "ASIS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#define CREATE_TRACE_POINTS
#include "trace.h"
/**
* socket tuples for filtering in socket traces:
* (portid, sock type, name type, name lower, name upper)
*/
unsigned long sysctl_tipc_sk_filter[5] __read_mostly = {0, };
/**
* tipc_skb_dump - dump TIPC skb data
* @skb: skb to be dumped
* @more: dump more?
* - false: dump only tipc msg data
* - true: dump kernel-related skb data and tipc cb[] array as well
* @buf: returned buffer of dump data in format
*/
int tipc_skb_dump(struct sk_buff *skb, bool more, char *buf)
{
int i = 0;
size_t sz = (more) ? SKB_LMAX : SKB_LMIN;
struct tipc_msg *hdr;
struct tipc_skb_cb *skbcb;
if (!skb) {
i += scnprintf(buf, sz, "msg: (null)\n");
return i;
}
hdr = buf_msg(skb);
skbcb = TIPC_SKB_CB(skb);
/* tipc msg data section */
i += scnprintf(buf, sz, "msg: %u", msg_user(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_type(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_hdr_sz(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_data_sz(hdr));
i += scnprintf(buf + i, sz - i, " %x", msg_orignode(hdr));
i += scnprintf(buf + i, sz - i, " %x", msg_destnode(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_seqno(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_ack(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_bcast_ack(hdr));
switch (msg_user(hdr)) {
case LINK_PROTOCOL:
i += scnprintf(buf + i, sz - i, " %c", msg_net_plane(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_probe(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_peer_stopping(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_session(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_next_sent(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_seq_gap(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_bc_snd_nxt(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_bc_gap(hdr));
break;
case TIPC_LOW_IMPORTANCE:
case TIPC_MEDIUM_IMPORTANCE:
case TIPC_HIGH_IMPORTANCE:
case TIPC_CRITICAL_IMPORTANCE:
case CONN_MANAGER:
case SOCK_WAKEUP:
i += scnprintf(buf + i, sz - i, " | %u", msg_origport(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_destport(hdr));
switch (msg_type(hdr)) {
case TIPC_NAMED_MSG:
i += scnprintf(buf + i, sz - i, " %u",
msg_nametype(hdr));
i += scnprintf(buf + i, sz - i, " %u",
msg_nameinst(hdr));
break;
case TIPC_MCAST_MSG:
i += scnprintf(buf + i, sz - i, " %u",
msg_nametype(hdr));
i += scnprintf(buf + i, sz - i, " %u",
msg_namelower(hdr));
i += scnprintf(buf + i, sz - i, " %u",
msg_nameupper(hdr));
break;
default:
break;
};
i += scnprintf(buf + i, sz - i, " | %u",
msg_src_droppable(hdr));
i += scnprintf(buf + i, sz - i, " %u",
msg_dest_droppable(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_errcode(hdr));
i += scnprintf(buf + i, sz - i, " %u", msg_reroute_cnt(hdr));
break;
default:
/* need more? */
break;
};
i += scnprintf(buf + i, sz - i, "\n");
if (!more)
return i;
/* kernel-related skb data section */
i += scnprintf(buf + i, sz - i, "skb: %s",
(skb->dev) ? skb->dev->name : "n/a");
i += scnprintf(buf + i, sz - i, " %u", skb->len);
i += scnprintf(buf + i, sz - i, " %u", skb->data_len);
i += scnprintf(buf + i, sz - i, " %u", skb->hdr_len);
i += scnprintf(buf + i, sz - i, " %u", skb->truesize);
i += scnprintf(buf + i, sz - i, " %u", skb_cloned(skb));
i += scnprintf(buf + i, sz - i, " %p", skb->sk);
i += scnprintf(buf + i, sz - i, " %u", skb_shinfo(skb)->nr_frags);
i += scnprintf(buf + i, sz - i, " %llx",
ktime_to_ms(skb_get_ktime(skb)));
i += scnprintf(buf + i, sz - i, " %llx\n",
ktime_to_ms(skb_hwtstamps(skb)->hwtstamp));
/* tipc skb cb[] data section */
i += scnprintf(buf + i, sz - i, "cb[]: %u", skbcb->bytes_read);
i += scnprintf(buf + i, sz - i, " %u", skbcb->orig_member);
i += scnprintf(buf + i, sz - i, " %u",
jiffies_to_msecs(skbcb->nxt_retr));
i += scnprintf(buf + i, sz - i, " %u", skbcb->validated);
i += scnprintf(buf + i, sz - i, " %u", skbcb->chain_imp);
i += scnprintf(buf + i, sz - i, " %u\n", skbcb->ackers);
return i;
}
/**
* tipc_list_dump - dump TIPC skb list/queue
* @list: list of skbs to be dumped
* @more: dump more?
* - false: dump only the head & tail skbs
* - true: dump the first & last 5 skbs
* @buf: returned buffer of dump data in format
*/
int tipc_list_dump(struct sk_buff_head *list, bool more, char *buf)
{
int i = 0;
size_t sz = (more) ? LIST_LMAX : LIST_LMIN;
u32 count, len;
struct sk_buff *hskb, *tskb, *skb, *tmp;
if (!list) {
i += scnprintf(buf, sz, "(null)\n");
return i;
}
len = skb_queue_len(list);
i += scnprintf(buf, sz, "len = %d\n", len);
if (!len)
return i;
if (!more) {
hskb = skb_peek(list);
i += scnprintf(buf + i, sz - i, " head ");
i += tipc_skb_dump(hskb, false, buf + i);
if (len > 1) {
tskb = skb_peek_tail(list);
i += scnprintf(buf + i, sz - i, " tail ");
i += tipc_skb_dump(tskb, false, buf + i);
}
} else {
count = 0;
skb_queue_walk_safe(list, skb, tmp) {
count++;
if (count == 6)
i += scnprintf(buf + i, sz - i, " .\n .\n");
if (count > 5 && count <= len - 5)
continue;
i += scnprintf(buf + i, sz - i, " #%d ", count);
i += tipc_skb_dump(skb, false, buf + i);
}
}
return i;
}
| 34.628019 | 78 | 0.615374 |
aabd0940cb7c9d2cf746e186d23843f59ab84c38 | 452 | h | C | examples/OledClock/StoredInfo.h | dduehren/AceTime | 30b79b34d988aa26387cf2597e9152855eff011c | [
"MIT"
] | 1 | 2019-08-02T06:53:56.000Z | 2019-08-02T06:53:56.000Z | examples/OledClock/StoredInfo.h | dduehren/AceTime | 30b79b34d988aa26387cf2597e9152855eff011c | [
"MIT"
] | null | null | null | examples/OledClock/StoredInfo.h | dduehren/AceTime | 30b79b34d988aa26387cf2597e9152855eff011c | [
"MIT"
] | 1 | 2021-09-06T06:20:07.000Z | 2021-09-06T06:20:07.000Z | #ifndef OLED_CLOCK_STORED_INFO_H
#define OLED_CLOCK_STORED_INFO_H
#include <AceTime.h>
/** Data that is saved to and retrieved from EEPROM. */
struct StoredInfo {
/** 12:00:00 AM to 12:00:00 PM */
static uint8_t const kTwelve = 0;
/** 00:00:00 - 23:59:59 */
static uint8_t const kTwentyFour = 1;
/** Either kTwelve or kTwentyFour. */
uint8_t hourMode;
/** TimeZone serialization. */
ace_time::TimeZoneData timeZoneData;
};
#endif
| 20.545455 | 55 | 0.696903 |
306ab29edcf68d00cbecfbda1f993af3f059ee53 | 678 | h | C | PDxProjects/PSCExporter2nd/pch.h | bear1704/DX11_Portfolio | 8ab70c793cf7f10eceaea34afb786264828c09a0 | [
"Apache-2.0"
] | null | null | null | PDxProjects/PSCExporter2nd/pch.h | bear1704/DX11_Portfolio | 8ab70c793cf7f10eceaea34afb786264828c09a0 | [
"Apache-2.0"
] | null | null | null | PDxProjects/PSCExporter2nd/pch.h | bear1704/DX11_Portfolio | 8ab70c793cf7f10eceaea34afb786264828c09a0 | [
"Apache-2.0"
] | null | null | null | // pch.h: 미리 컴파일된 헤더 파일입니다.
// 아래 나열된 파일은 한 번만 컴파일되었으며, 향후 빌드에 대한 빌드 성능을 향상합니다.
// 코드 컴파일 및 여러 코드 검색 기능을 포함하여 IntelliSense 성능에도 영향을 미칩니다.
// 그러나 여기에 나열된 파일은 빌드 간 업데이트되는 경우 모두 다시 컴파일됩니다.
// 여기에 자주 업데이트할 파일을 추가하지 마세요. 그러면 성능이 저하됩니다.
#ifndef PCH_H
#define PCH_H
// 여기에 미리 컴파일하려는 헤더 추가
#include "framework.h"
// TODO: 프로그램에 필요한 추가 헤더는 여기에서 참조합니다.
#include <istdplug.h>
#include <iparamb2.h>
#include <iparamm2.h>
#include <maxtypes.h>
#include <utilapi.h>
#include <max.h>
#include <stdmat.h>
#include <decomp.h>
#include <iskin.h>
#define CTL_CHARS 31
#define SINGLE_QUOTE 39 // ( ' )
#define ALMOST_ZERO 1.0e-3f
//#include <bipexp.h>
//#include <phyexp.h>
#endif //PCH_H
| 21.1875 | 57 | 0.687316 |
307c3e9f745c0f93ae119e0402165312c9f9a16f | 2,168 | h | C | usr/lib/libnetwork.dylib/NWConcrete_nw_agent.h | lechium/tvOS145Headers | 9940da19adb0017f8037853e9cfccbe01b290dd5 | [
"MIT"
] | 5 | 2021-04-29T04:31:43.000Z | 2021-08-19T18:59:58.000Z | usr/lib/libnetwork.dylib/NWConcrete_nw_agent.h | lechium/tvOS145Headers | 9940da19adb0017f8037853e9cfccbe01b290dd5 | [
"MIT"
] | null | null | null | usr/lib/libnetwork.dylib/NWConcrete_nw_agent.h | lechium/tvOS145Headers | 9940da19adb0017f8037853e9cfccbe01b290dd5 | [
"MIT"
] | 1 | 2022-03-19T11:16:23.000Z | 2022-03-19T11:16:23.000Z | /*
* This header is generated by classdump-dyld 1.5
* on Wednesday, April 28, 2021 at 9:01:38 PM Mountain Standard Time
* Operating System: Version 14.5 (Build 18L204)
* Image Source: /usr/lib/libnetwork.dylib
* classdump-dyld is licensed under GPLv3, Copyright © 2013-2016 by Elias Limneos. Updated by Kevin Bradley.
*/
#import <libnetwork.dylib/libnetwork.dylib-Structs.h>
#import <libobjc.A.dylib/OS_nw_agent.h>
@protocol OS_dispatch_queue, OS_dispatch_data, OS_nw_context, OS_nw_nexus, OS_nw_dictionary, OS_nw_fd_wrapper, OS_dispatch_source;
@class NSObject, NSString;
@interface NWConcrete_nw_agent : NSObject <OS_nw_agent> {
os_unfair_lock_s lock;
unsigned logging_id;
AI last_client_id;
char domain[32];
char type[32];
char description[128];
NSObject*<OS_dispatch_queue> queue;
NSObject*<OS_dispatch_data> data;
int state;
int options;
NSObject*<OS_nw_context> context;
NSObject*<OS_nw_nexus> nexus;
int flow_protocol_level;
int flow_endpoint_type;
unsigned long long tx_slots;
unsigned long long rx_slots;
unsigned long long slot_size;
int flow_request_types[15];
unsigned char flow_request_type_count;
nw_agent_resolve_handlers resolve_handlers[16];
unsigned char resolve_handler_count;
unsigned char uuid[16];
NSObject*<OS_nw_dictionary> clients;
/*^block*/id activate_handler;
/*^block*/id assert_handler;
/*^block*/id unassert_handler;
/*^block*/id start_flow_handler;
/*^block*/id stop_flow_handler;
/*^block*/id start_browse_handler;
/*^block*/id stop_browse_handler;
NSObject*<OS_nw_fd_wrapper> fd_wrapper;
NSObject*<OS_dispatch_source> event_source;
unsigned registered : 1;
unsigned supports_listen : 1;
unsigned require_assert : 1;
unsigned nexus_agent : 1;
unsigned browse_agent : 1;
unsigned resolve_agent : 1;
unsigned __pad_bits : 2;
}
@property (readonly) unsigned long long hash;
@property (readonly) Class superclass;
@property (copy,readonly) NSString * description;
@property (copy,readonly) NSString * debugDescription;
-(id)init;
-(void)dealloc;
@end
| 32.358209 | 130 | 0.728782 |
5cb3597af158eaee01cad4bed96830319c1cff33 | 250 | c | C | raylib-sys/rgui_wrapper.c | RvNovae/raylib-rs | c0a5760a208d66f70d6ce0251888a61bafab651a | [
"Zlib"
] | null | null | null | raylib-sys/rgui_wrapper.c | RvNovae/raylib-rs | c0a5760a208d66f70d6ce0251888a61bafab651a | [
"Zlib"
] | null | null | null | raylib-sys/rgui_wrapper.c | RvNovae/raylib-rs | c0a5760a208d66f70d6ce0251888a61bafab651a | [
"Zlib"
] | null | null | null | #include "raylib.h"
#define RICONS_IMPLEMENTATION
#define RAYGUI_IMPLEMENTATION
#define RAYGUI_SUPPORT_ICONS
#define RLGL_IMPLEMENTATION
#define RLGL_SUPPORT_TRACELOG
// #include "rlgl.h" // Don't include rlgl since it's in raylib
#include "raygui.h" | 31.25 | 63 | 0.812 |
d69007fe6a180e2e6a090011c9f3d421fb22dae2 | 2,390 | c | C | ompi/mca/fs/pvfs2/fs_pvfs2_file_delete.c | raspbian-packages/openmpi | 38e7e633028faf35b2dd948a789fea95e543e567 | [
"BSD-3-Clause-Open-MPI"
] | null | null | null | ompi/mca/fs/pvfs2/fs_pvfs2_file_delete.c | raspbian-packages/openmpi | 38e7e633028faf35b2dd948a789fea95e543e567 | [
"BSD-3-Clause-Open-MPI"
] | null | null | null | ompi/mca/fs/pvfs2/fs_pvfs2_file_delete.c | raspbian-packages/openmpi | 38e7e633028faf35b2dd948a789fea95e543e567 | [
"BSD-3-Clause-Open-MPI"
] | null | null | null | /*
* Copyright (c) 2004-2005 The Trustees of Indiana University and Indiana
* University Research and Technology
* Corporation. All rights reserved.
* Copyright (c) 2004-2011 The University of Tennessee and The University
* of Tennessee Research Foundation. All rights
* reserved.
* Copyright (c) 2004-2005 High Performance Computing Center Stuttgart,
* University of Stuttgart. All rights reserved.
* Copyright (c) 2004-2005 The Regents of the University of California.
* All rights reserved.
* Copyright (c) 2008-2011 University of Houston. All rights reserved.
* $COPYRIGHT$
*
* Additional copyrights may follow
*
* $HEADER$
*/
/* This code is based on the PVFS2 ADIO module in ROMIO
* Copyright (C) 1997 University of Chicago.
* See COPYRIGHT notice in top-level directory.
*/
#include "ompi_config.h"
#include "fs_pvfs2.h"
#include "mpi.h"
#include "ompi/constants.h"
#include "ompi/mca/fs/fs.h"
/*
* file_delete_pvfs2
*
* Function: - deletes a file
* Accepts: - file name & info
* Returns: - Success if file closed
*/
int
mca_fs_pvfs2_file_delete (char* file_name,
struct ompi_info_t *info)
{
PVFS_credentials credentials;
PVFS_sysresp_getparent resp_getparent;
int ret;
PVFS_fs_id pvfs2_id;
char pvfs2_path[OMPIO_MAX_NAME] = {0};
char * ncache_timeout;
if (!mca_fs_pvfs2_IS_INITIALIZED) {
/* disable the pvfs2 ncache */
ncache_timeout = getenv("PVFS2_NCACHE_TIMEOUT");
if (ncache_timeout == NULL )
setenv("PVFS2_NCACHE_TIMEOUT", "0", 1);
ret = PVFS_util_init_defaults();
if (ret < 0) {
return OMPI_ERROR;
}
mca_fs_pvfs2_IS_INITIALIZED = 1;
}
memset (&credentials, 0, sizeof(PVFS_credentials));
PVFS_util_gen_credentials (&credentials);
ret = PVFS_util_resolve(file_name, &pvfs2_id, pvfs2_path, OMPIO_MAX_NAME);
if (ret != 0) {
return OMPI_ERROR;
}
ret = PVFS_sys_getparent(pvfs2_id, pvfs2_path, &credentials, &resp_getparent);
ret = PVFS_sys_remove(resp_getparent.basename,
resp_getparent.parent_ref, &credentials);
if (ret != 0) {
return OMPI_ERROR;
}
return OMPI_SUCCESS;
}
| 29.875 | 82 | 0.633054 |
682ef3a344caa591a77e9e51c8c2a833e01bf510 | 453 | h | C | GFDropDownMenu/GFDDIndexPath.h | tianguanghui/GFDropDownMenu | 7bb49b4aafb71ce32ed9b4d9f456de5a40c32921 | [
"MIT"
] | null | null | null | GFDropDownMenu/GFDDIndexPath.h | tianguanghui/GFDropDownMenu | 7bb49b4aafb71ce32ed9b4d9f456de5a40c32921 | [
"MIT"
] | null | null | null | GFDropDownMenu/GFDDIndexPath.h | tianguanghui/GFDropDownMenu | 7bb49b4aafb71ce32ed9b4d9f456de5a40c32921 | [
"MIT"
] | null | null | null | //
// GFDDIndexPath.h
// 60fen
//
// Created by TianGuanghui on 2017/5/23.
// Copyright © 2017年 Xuelang Borui Education Technology (Beijing) Co., Ltd. All rights reserved.
//
@interface GFDDIndexPath : NSObject
@property (nonatomic, assign) NSInteger column;
@property (nonatomic, assign) NSInteger row;
- (instancetype)initWithColumn:(NSInteger)column row:(NSInteger)row;
+ (instancetype)indexPathWithCol:(NSInteger)col row:(NSInteger)row;
@end
| 26.647059 | 97 | 0.750552 |
a93f90b4e947c3254d2c68fe6bab50a0ec9c4389 | 2,377 | h | C | engine/demos/ex-filetree/filetree.h | sfaure-witekio/qt-training-material | d166e4ed9cc5f5faab85b0337c5844c4cdcb206e | [
"BSD-3-Clause"
] | 16 | 2017-01-11T17:28:03.000Z | 2021-09-27T16:12:01.000Z | engine/demos/ex-filetree/filetree.h | sfaure-witekio/qt-training-material | d166e4ed9cc5f5faab85b0337c5844c4cdcb206e | [
"BSD-3-Clause"
] | null | null | null | engine/demos/ex-filetree/filetree.h | sfaure-witekio/qt-training-material | d166e4ed9cc5f5faab85b0337c5844c4cdcb206e | [
"BSD-3-Clause"
] | 4 | 2017-03-17T02:44:32.000Z | 2021-01-22T07:57:34.000Z | /*************************************************************************
*
* Copyright (c) 2016 The Qt Company
* All rights reserved.
*
* See the LICENSE.txt file shipped along with this file for the license.
*
*************************************************************************/
#include <QtCore/QFileInfo>
#include <QtCore/QDir>
#include <QtCore/QVector>
#include <QtXmlPatterns/QSimpleXmlNodeModel>
class FileTree : public QSimpleXmlNodeModel
{
public:
FileTree(const QXmlNamePool &namePool);
QXmlNodeModelIndex nodeFor(const QString &fileName) const;
QXmlNodeModelIndex::DocumentOrder compareOrder(const QXmlNodeModelIndex&, const QXmlNodeModelIndex&) const Q_DECL_OVERRIDE;
QXmlName name(const QXmlNodeModelIndex &node) const Q_DECL_OVERRIDE;
QUrl documentUri(const QXmlNodeModelIndex &node) const Q_DECL_OVERRIDE;
QXmlNodeModelIndex::NodeKind kind(const QXmlNodeModelIndex &node) const Q_DECL_OVERRIDE;
QXmlNodeModelIndex root(const QXmlNodeModelIndex &node) const Q_DECL_OVERRIDE;
QVariant typedValue(const QXmlNodeModelIndex &node) const Q_DECL_OVERRIDE;
protected:
QVector<QXmlNodeModelIndex> attributes(const QXmlNodeModelIndex &element) const Q_DECL_OVERRIDE;
QXmlNodeModelIndex nextFromSimpleAxis(SimpleAxis, const QXmlNodeModelIndex&) const Q_DECL_OVERRIDE;
private:
enum Type {
File,
Directory,
AttributeFileName,
AttributeFilePath,
AttributeSize,
AttributeMIMEType,
AttributeSuffix
};
inline QXmlNodeModelIndex nextSibling(const QXmlNodeModelIndex &nodeIndex,
const QFileInfo &from,
qint8 offset) const;
inline const QFileInfo &toFileInfo(const QXmlNodeModelIndex &index) const;
inline QXmlNodeModelIndex toNodeIndex(const QFileInfo &index,
Type attributeName) const;
inline QXmlNodeModelIndex toNodeIndex(const QFileInfo &index) const;
/*
One possible improvement is to use a hash, and use the &*&value()
trick to get a pointer, which would be stored in data() instead
of the index.
*/
mutable QVector<QFileInfo> m_fileInfos;
const QDir::Filters m_filterAllowAll;
const QDir::SortFlags m_sortFlags;
QVector<QXmlName> m_names;
};
| 38.967213 | 127 | 0.664283 |
ca001e725ca3deda0027e09ec734d1724026aaac | 2,277 | h | C | fmt_fmu/rtos/documentation/doxygen/hardware.h | CornerOfSkyline/FMT_Firmware | 7d36406e104d32a94a9c9046502b54b567c561eb | [
"Apache-2.0"
] | 1 | 2021-03-19T02:24:50.000Z | 2021-03-19T02:24:50.000Z | fmt_fmu/rtos/documentation/doxygen/hardware.h | CornerOfSkyline/FMT_Firmware | 7d36406e104d32a94a9c9046502b54b567c561eb | [
"Apache-2.0"
] | null | null | null | fmt_fmu/rtos/documentation/doxygen/hardware.h | CornerOfSkyline/FMT_Firmware | 7d36406e104d32a94a9c9046502b54b567c561eb | [
"Apache-2.0"
] | 3 | 2021-02-01T02:54:34.000Z | 2021-03-29T13:52:10.000Z | /*
* This file is only used for doxygen document generation.
*/
/**
* @defgroup bsp Hardware Related Package
*
* @brief Hardware Related Package includes board support package(BSP) and CSP(Chip
* Support Package).
*
* Board Support Package(BSP) is the hardware related wrapper, for example, peripherals
* in board, the pinmux setting etc. In RT-Thread RTOS, the bsp is placed under bsp
* directory.
*
* Chip Support Package (CSP) is a software set that contains chip specific software.
* A CSP usually includes operating system porting and peripheral device drivers inside
* chip. In RT-Thread RTOS, the csp is placed under libcpu directory.
*/
/**
* @addtogroup bsp
*/
/*@{*/
/**
* This function will return current system interrupt status and disable system
* interrupt.
*
* @return the current system interrupt status
*/
rt_base_t rt_hw_interrupt_disable(void);
/**
* This function will set the specified interrupt status, which shall saved by
* rt_hw_intterrupt_disable function. If the saved interrupt status is interrupt
* opened, this function will open system interrupt status.
*/
void rt_hw_interrupt_enable(rt_base_t level);
/**
* This function initializes interrupt.
*/
void rt_hw_interrupt_init(void);
/**
* This function masks the specified interrupt.
*
* @param vector the interrupt number to be masked.
*
* @note not all of platform provide this function.
*/
void rt_hw_interrupt_mask(int vector);
/**
* This function umasks the specified interrupt.
*
* @param vector the interrupt number to be unmasked.
*
* @note not all of platform provide this function.
*/
void rt_hw_interrupt_umask(int vector);
/**
* This function will install specified interrupt handler.
*
* @param vector the interrupt number to be installed.
* @param new_handler the new interrupt handler.
* @param old_handler the old interrupt handler. This parameter can be RT_NULL.
*
* @note not all of platform provide this function.
*/
void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler,
rt_isr_handler_t* old_handler);
/**
* This function will reset whole platform.
*/
void rt_hw_cpu_reset(void);
/**
* This function will halt whole platform.
*/
void rt_hw_cpu_shutdown(void);
/*@}*/
| 26.476744 | 87 | 0.733421 |
a9cb4bf56aa4656debad9cea5b5666249bed9f30 | 56,127 | h | C | lib/am335x_sdk/ti/csl/cslr_cxstm_tetris.h | brandonbraun653/Apollo | a1ece2cc3f1d3dae48fdf8fe94f0bbb59d405fce | [
"MIT"
] | 2 | 2021-12-27T10:19:01.000Z | 2022-03-15T07:09:06.000Z | lib/am335x_sdk/ti/csl/cslr_cxstm_tetris.h | brandonbraun653/Apollo | a1ece2cc3f1d3dae48fdf8fe94f0bbb59d405fce | [
"MIT"
] | null | null | null | lib/am335x_sdk/ti/csl/cslr_cxstm_tetris.h | brandonbraun653/Apollo | a1ece2cc3f1d3dae48fdf8fe94f0bbb59d405fce | [
"MIT"
] | null | null | null | /********************************************************************
* Copyright (C) 2013-2014 Texas Instruments Incorporated.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef CSLR_CXSTM_TETRIS_H_
#define CSLR_CXSTM_TETRIS_H_
#ifdef __cplusplus
extern "C"
{
#endif
#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>
/**************************************************************************
* Register Overlay Structure for cxstm_registers
**************************************************************************/
typedef struct {
volatile Uint32 STMDMASTARTR;
volatile Uint32 STMDMASTOPR;
volatile Uint32 STMDMASTATR;
volatile Uint32 STMDMACTLR;
volatile Uint8 RSVD0[232];
volatile Uint32 STMDMAIDR;
volatile Uint32 STMHEER;
volatile Uint8 RSVD1[28];
volatile Uint32 STMHETER;
volatile Uint8 RSVD2[64];
volatile Uint32 STMHEMCR;
volatile Uint8 RSVD3[140];
volatile Uint32 STMHEMASTR;
volatile Uint32 STMHEFEAT1R;
volatile Uint32 STMHEIDR;
volatile Uint32 STMSPER;
volatile Uint8 RSVD4[28];
volatile Uint32 STMSPTER;
volatile Uint8 RSVD5[60];
volatile Uint32 STMSPSCR;
volatile Uint32 STMSPMSCR;
volatile Uint32 STMSPOVERRIDER;
volatile Uint32 STMSPMOVERRIDER;
volatile Uint32 STMSPTRIGCSR;
volatile Uint8 RSVD6[12];
volatile Uint32 STMTCSR;
volatile Uint32 STMTSSTIMR;
volatile Uint8 RSVD7[4];
volatile Uint32 STMTSFREQR;
volatile Uint32 STMSYNCR;
volatile Uint32 STMAUXCR;
volatile Uint8 RSVD8[8];
volatile Uint32 STMSPFEAT1R;
volatile Uint32 STMSPFEAT2R;
volatile Uint32 STMSPFEAT3R;
volatile Uint8 RSVD9[60];
volatile Uint32 STMITTRIGGER;
volatile Uint32 STMITATBDATA0;
volatile Uint32 STMITATBCTR2;
volatile Uint32 STMITATBID;
volatile Uint32 STMITATBCTR0;
volatile Uint8 RSVD10[4];
volatile Uint32 STMITCTRL;
volatile Uint8 RSVD11[156];
volatile Uint32 STMCLAIMSET;
volatile Uint32 STMCLAIMCLR;
volatile Uint8 RSVD12[8];
volatile Uint32 STMLAR;
volatile Uint32 STMLSR;
volatile Uint32 STMAUTHSTATUS;
volatile Uint8 RSVD13[12];
volatile Uint32 STMDEVID;
volatile Uint32 STMDEVTYPE;
volatile Uint32 STMPIDR4;
volatile Uint32 STMPIDR5;
volatile Uint32 STMPIDR6;
volatile Uint32 STMPIDR7;
volatile Uint32 STMPIDR0;
volatile Uint32 STMPIDR1;
volatile Uint32 STMPIDR2;
volatile Uint32 STMPIDR3;
volatile Uint32 STMCIDR0;
volatile Uint32 STMCIDR1;
volatile Uint32 STMCIDR2;
volatile Uint32 STMCIDR3;
volatile Uint8 RSVD14[4];
} CSL_Cxstm_tetrisRegs;
/**************************************************************************
* Register Macros
**************************************************************************/
/* STMDMASTARTR */
#define CSL_CXSTM_TETRIS_STMDMASTARTR (0x0U)
/* STMDMASTOPR */
#define CSL_CXSTM_TETRIS_STMDMASTOPR (0x4U)
/* STMDMASTATR */
#define CSL_CXSTM_TETRIS_STMDMASTATR (0x8U)
/* STMDMACTLR */
#define CSL_CXSTM_TETRIS_STMDMACTLR (0xCU)
/* STMDMAIDR */
#define CSL_CXSTM_TETRIS_STMDMAIDR (0xF8U)
/* STMHEER */
#define CSL_CXSTM_TETRIS_STMHEER (0xFCU)
/* STMHETER */
#define CSL_CXSTM_TETRIS_STMHETER (0x11CU)
/* STMHEMCR */
#define CSL_CXSTM_TETRIS_STMHEMCR (0x160U)
/* STMHEMASTR */
#define CSL_CXSTM_TETRIS_STMHEMASTR (0x1F0U)
/* STMHEFEAT1R */
#define CSL_CXSTM_TETRIS_STMHEFEAT1R (0x1F4U)
/* STMHEIDR */
#define CSL_CXSTM_TETRIS_STMHEIDR (0x1F8U)
/* STMSPER */
#define CSL_CXSTM_TETRIS_STMSPER (0x1FCU)
/* STMSPTER */
#define CSL_CXSTM_TETRIS_STMSPTER (0x21CU)
/* STMSPSCR */
#define CSL_CXSTM_TETRIS_STMSPSCR (0x25CU)
/* This register allows a debugger to program which masters the STMSPSCR
* applies to. */
#define CSL_CXSTM_TETRIS_STMSPMSCR (0x260U)
/* STMSPOVERRIDER */
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER (0x264U)
/* STMSPMOVERRIDER */
#define CSL_CXSTM_TETRIS_STMSPMOVERRIDER (0x268U)
/* STMSPTRIGCSR */
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR (0x26CU)
/* STMTCSR */
#define CSL_CXSTM_TETRIS_STMTCSR (0x27CU)
/* STMTSSTIMR */
#define CSL_CXSTM_TETRIS_STMTSSTIMR (0x280U)
/* STMTSFREQR */
#define CSL_CXSTM_TETRIS_STMTSFREQR (0x288U)
/* STMSYNCR */
#define CSL_CXSTM_TETRIS_STMSYNCR (0x28CU)
/* STMAUXCR */
#define CSL_CXSTM_TETRIS_STMAUXCR (0x290U)
/* STMSPFEAT1R */
#define CSL_CXSTM_TETRIS_STMSPFEAT1R (0x29CU)
/* STMSPFEAT2R */
#define CSL_CXSTM_TETRIS_STMSPFEAT2R (0x2A0U)
/* Indicates the features of the STM. */
#define CSL_CXSTM_TETRIS_STMSPFEAT3R (0x2A4U)
/* Integration Test for Cross-Trigger Outputs Register */
#define CSL_CXSTM_TETRIS_STMITTRIGGER (0x2E4U)
/* Controls the value of the ATDATAM output in integration mode: */
#define CSL_CXSTM_TETRIS_STMITATBDATA0 (0x2E8U)
/* Returns the value of the ATREADYM and AFVALIDM inputs in integration mode. */
#define CSL_CXSTM_TETRIS_STMITATBCTR2 (0x2ECU)
/* Controls the value of the ATIDM output in integration mode. */
#define CSL_CXSTM_TETRIS_STMITATBID (0x2F0U)
/* Controls the value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in
* integration mode. */
#define CSL_CXSTM_TETRIS_STMITATBCTR0 (0x2F4U)
/* STMITCTRL */
#define CSL_CXSTM_TETRIS_STMITCTRL (0x2FCU)
/* STMCLAIMSET */
#define CSL_CXSTM_TETRIS_STMCLAIMSET (0x39CU)
/* STMCLAIMCLR */
#define CSL_CXSTM_TETRIS_STMCLAIMCLR (0x3A0U)
/* STMLAR */
#define CSL_CXSTM_TETRIS_STMLAR (0x3ACU)
/* STMLSR */
#define CSL_CXSTM_TETRIS_STMLSR (0x3B0U)
/* STMAUTHSTATUS */
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS (0x3B4U)
/* STMDEVID */
#define CSL_CXSTM_TETRIS_STMDEVID (0x3C4U)
/* STMDEVTYPE */
#define CSL_CXSTM_TETRIS_STMDEVTYPE (0x3C8U)
/* STMPIDR0 */
#define CSL_CXSTM_TETRIS_STMPIDR0 (0x3DCU)
/* STMPIDR1 */
#define CSL_CXSTM_TETRIS_STMPIDR1 (0x3E0U)
/* STMPIDR2 */
#define CSL_CXSTM_TETRIS_STMPIDR2 (0x3E4U)
/* STMPIDR3 */
#define CSL_CXSTM_TETRIS_STMPIDR3 (0x3E8U)
/* STMPIDR4 */
#define CSL_CXSTM_TETRIS_STMPIDR4 (0x3CCU)
/* STMPIDR5 */
#define CSL_CXSTM_TETRIS_STMPIDR5 (0x3D0U)
/* STMPIDR6 */
#define CSL_CXSTM_TETRIS_STMPIDR6 (0x3D4U)
/* STMPIDR7 */
#define CSL_CXSTM_TETRIS_STMPIDR7 (0x3D8U)
/* STMCIDR0 */
#define CSL_CXSTM_TETRIS_STMCIDR0 (0x3ECU)
/* STMCIDR1 */
#define CSL_CXSTM_TETRIS_STMCIDR1 (0x3F0U)
/* STMCIDR2 */
#define CSL_CXSTM_TETRIS_STMCIDR2 (0x3F4U)
/* STMCIDR3 */
#define CSL_CXSTM_TETRIS_STMCIDR3 (0x3F8U)
/**************************************************************************
* Field Definition Macros
**************************************************************************/
/* STMDMASTARTR */
#define CSL_CXSTM_TETRIS_STMDMASTARTR_START_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMDMASTARTR_START_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMDMASTARTR_START_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMDMASTARTR_START_START (0x00000001U)
#define CSL_CXSTM_TETRIS_STMDMASTARTR_RESETVAL (0x00000000U)
/* STMDMASTOPR */
#define CSL_CXSTM_TETRIS_STMDMASTOPR_STOP_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMDMASTOPR_STOP_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMDMASTOPR_STOP_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMDMASTOPR_STOP_STOP (0x00000001U)
#define CSL_CXSTM_TETRIS_STMDMASTOPR_RESETVAL (0x00000000U)
/* STMDMASTATR */
#define CSL_CXSTM_TETRIS_STMDMASTATR_STATUS_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMDMASTATR_STATUS_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMDMASTATR_STATUS_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMDMASTATR_STATUS_IDLE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMDMASTATR_STATUS_ACTIVE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMDMASTATR_RESETVAL (0x00000000U)
/* STMDMACTLR */
#define CSL_CXSTM_TETRIS_STMDMACTLR_SENS_MASK (0x0000000CU)
#define CSL_CXSTM_TETRIS_STMDMACTLR_SENS_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMDMACTLR_SENS_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMDMACTLR_SENS_EMPTY (0x00000000U)
#define CSL_CXSTM_TETRIS_STMDMACTLR_SENS_PCT25 (0x00000001U)
#define CSL_CXSTM_TETRIS_STMDMACTLR_SENS_PCT50 (0x00000002U)
#define CSL_CXSTM_TETRIS_STMDMACTLR_SENS_PCT75 (0x00000003U)
#define CSL_CXSTM_TETRIS_STMDMACTLR_RESETVAL (0x00000000U)
/* STMDMAIDR */
#define CSL_CXSTM_TETRIS_STMDMAIDR_CLASS_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMDMAIDR_CLASS_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMDMAIDR_CLASS_RESETVAL (0x00000002U)
#define CSL_CXSTM_TETRIS_STMDMAIDR_CLASS_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMDMAIDR_CLASSREV_MASK (0x000000F0U)
#define CSL_CXSTM_TETRIS_STMDMAIDR_CLASSREV_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMDMAIDR_CLASSREV_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMDMAIDR_CLASSREV_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMDMAIDR_VENDSPEC_MASK (0x00000F00U)
#define CSL_CXSTM_TETRIS_STMDMAIDR_VENDSPEC_SHIFT (8U)
#define CSL_CXSTM_TETRIS_STMDMAIDR_VENDSPEC_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMDMAIDR_VENDSPEC_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMDMAIDR_RESETVAL (0x00000002U)
/* STMHEER */
#define CSL_CXSTM_TETRIS_STMHEER_HEE_MASK (0xFFFFFFFFU)
#define CSL_CXSTM_TETRIS_STMHEER_HEE_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMHEER_HEE_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEER_HEE_MAX (0xffffffffU)
#define CSL_CXSTM_TETRIS_STMHEER_RESETVAL (0x00000000U)
/* STMHETER */
#define CSL_CXSTM_TETRIS_STMHETER_HETE_MASK (0xFFFFFFFFU)
#define CSL_CXSTM_TETRIS_STMHETER_HETE_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMHETER_HETE_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHETER_HETE_MAX (0xffffffffU)
#define CSL_CXSTM_TETRIS_STMHETER_RESETVAL (0x00000000U)
/* STMHEMCR */
#define CSL_CXSTM_TETRIS_STMHEMCR_EN_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEMCR_EN_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMHEMCR_EN_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_EN_DISABLE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_EN_ENABLE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEMCR_COMPEN_MASK (0x00000002U)
#define CSL_CXSTM_TETRIS_STMHEMCR_COMPEN_SHIFT (1U)
#define CSL_CXSTM_TETRIS_STMHEMCR_COMPEN_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_COMPEN_DISABLE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_COMPEN_ENABLE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEMCR_ERRDETECT_MASK (0x00000004U)
#define CSL_CXSTM_TETRIS_STMHEMCR_ERRDETECT_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMHEMCR_ERRDETECT_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_ERRDETECT_DISABLE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_ERRDETECT_ENABLE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGCTL_MASK (0x00000010U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGCTL_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGCTL_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGCTL_MULTI_SHOT (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGCTL_SINGLE_SHOT (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGSTATUS_MASK (0x00000020U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGSTATUS_SHIFT (5U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGSTATUS_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGSTATUS_NOT_OCCURRED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGSTATUS_OCCURRED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGCLEAR_MASK (0x00000040U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGCLEAR_SHIFT (6U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGCLEAR_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGCLEAR_NOEFFECT (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_TRIGCLEAR_CLEAR (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEMCR_ATBTRIGEN_MASK (0x00000080U)
#define CSL_CXSTM_TETRIS_STMHEMCR_ATBTRIGEN_SHIFT (7U)
#define CSL_CXSTM_TETRIS_STMHEMCR_ATBTRIGEN_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_ATBTRIGEN_DISABLE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEMCR_ATBTRIGEN_ENABLE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEMCR_RESETVAL (0x00000000U)
/* STMHEMASTR */
#define CSL_CXSTM_TETRIS_STMHEMASTR_MASTER_MASK (0x0000FFFFU)
#define CSL_CXSTM_TETRIS_STMHEMASTR_MASTER_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMHEMASTR_MASTER_RESETVAL (0x00000080U)
#define CSL_CXSTM_TETRIS_STMHEMASTR_MASTER_MAX (0x0000ffffU)
#define CSL_CXSTM_TETRIS_STMHEMASTR_RESETVAL (0x00000080U)
/* STMHEFEAT1R */
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HETER_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HETER_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HETER_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HETER_IMPLEMENTED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HEERR_MASK (0x00000004U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HEERR_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HEERR_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HEERR_IMPLEMENTED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HEMASTR_MASK (0x00000008U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HEMASTR_SHIFT (3U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HEMASTR_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HEMASTR_RO (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HECOMP_MASK (0x00000030U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HECOMP_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HECOMP_RESETVAL (0x00000003U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_HECOMP_RO (0x00000003U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_NUMHE_MASK (0x00FF8000U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_NUMHE_SHIFT (15U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_NUMHE_RESETVAL (0x00000020U)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_NUMHE_MAX (0x000001ffU)
#define CSL_CXSTM_TETRIS_STMHEFEAT1R_RESETVAL (0x00100035U)
/* STMHEIDR */
#define CSL_CXSTM_TETRIS_STMHEIDR_CLASS_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMHEIDR_CLASS_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMHEIDR_CLASS_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMHEIDR_CLASS_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMHEIDR_CLASSREV_MASK (0x000000F0U)
#define CSL_CXSTM_TETRIS_STMHEIDR_CLASSREV_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMHEIDR_CLASSREV_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEIDR_CLASSREV_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMHEIDR_VENDSPEC_MASK (0x00000F00U)
#define CSL_CXSTM_TETRIS_STMHEIDR_VENDSPEC_SHIFT (8U)
#define CSL_CXSTM_TETRIS_STMHEIDR_VENDSPEC_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMHEIDR_VENDSPEC_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMHEIDR_RESETVAL (0x00000001U)
/* STMSPER */
#define CSL_CXSTM_TETRIS_STMSPER_SPE_MASK (0xFFFFFFFFU)
#define CSL_CXSTM_TETRIS_STMSPER_SPE_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMSPER_SPE_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPER_SPE_MAX (0xffffffffU)
#define CSL_CXSTM_TETRIS_STMSPER_RESETVAL (0x00000000U)
/* STMSPTER */
#define CSL_CXSTM_TETRIS_STMSPTER_SPTE_MASK (0xFFFFFFFFU)
#define CSL_CXSTM_TETRIS_STMSPTER_SPTE_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMSPTER_SPTE_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPTER_SPTE_MAX (0xffffffffU)
#define CSL_CXSTM_TETRIS_STMSPTER_RESETVAL (0x00000000U)
/* STMSPSCR */
#define CSL_CXSTM_TETRIS_STMSPSCR_PORTCTL_MASK (0x00000003U)
#define CSL_CXSTM_TETRIS_STMSPSCR_PORTCTL_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMSPSCR_PORTCTL_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPSCR_PORTCTL_NOTUSED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPSCR_PORTCTL_STMSPTER_ONLY (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPSCR_PORTCTL_RESERVED (0x00000002U)
#define CSL_CXSTM_TETRIS_STMSPSCR_PORTCTL_STMSPERANDSTMSPTER (0x00000003U)
#define CSL_CXSTM_TETRIS_STMSPSCR_PORTSEL_MASK (0xFFF00000U)
#define CSL_CXSTM_TETRIS_STMSPSCR_PORTSEL_SHIFT (20U)
#define CSL_CXSTM_TETRIS_STMSPSCR_PORTSEL_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPSCR_PORTSEL_MAX (0x00000fffU)
#define CSL_CXSTM_TETRIS_STMSPSCR_RESETVAL (0x00000000U)
/* STMSPMSCR */
#define CSL_CXSTM_TETRIS_STMSPMSCR_MASTCTL_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPMSCR_MASTCTL_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMSPMSCR_MASTCTL_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPMSCR_MASTCTL_NOTUSED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPMSCR_MASTCTL_STMSPSCR (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPMSCR_MASTSEL_MASK (0x007F8000U)
#define CSL_CXSTM_TETRIS_STMSPMSCR_MASTSEL_SHIFT (15U)
#define CSL_CXSTM_TETRIS_STMSPMSCR_MASTSEL_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPMSCR_MASTSEL_MAX (0x000000ffU)
#define CSL_CXSTM_TETRIS_STMSPMSCR_RESETVAL (0x00000000U)
/* STMSPOVERRIDER */
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERCTL_MASK (0x00000003U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERCTL_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERCTL_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERCTL_DISABLED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERCTL_GUARANTEED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERCTL_INVARIANTTIMING (0x00000002U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERCTL_RESERVED (0x00000003U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERTS_MASK (0x00000004U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERTS_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERTS_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERTS_DISABLED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_OVERTS_ENABLED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_PORTSEL_MASK (0xFFFF8000U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_PORTSEL_SHIFT (15U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_PORTSEL_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_PORTSEL_MAX (0x0001ffffU)
#define CSL_CXSTM_TETRIS_STMSPOVERRIDER_RESETVAL (0x00000000U)
/* STMSPMOVERRIDER */
#define CSL_CXSTM_TETRIS_STMSPMOVERRIDER_MASTCTL_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPMOVERRIDER_MASTCTL_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMSPMOVERRIDER_MASTCTL_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPMOVERRIDER_MASTCTL_DISABLED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPMOVERRIDER_MASTCTL_ENABLED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPMOVERRIDER_MASTSEL_MASK (0x007F8000U)
#define CSL_CXSTM_TETRIS_STMSPMOVERRIDER_MASTSEL_SHIFT (15U)
#define CSL_CXSTM_TETRIS_STMSPMOVERRIDER_MASTSEL_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPMOVERRIDER_MASTSEL_MAX (0x000000ffU)
#define CSL_CXSTM_TETRIS_STMSPMOVERRIDER_RESETVAL (0x00000000U)
/* STMSPTRIGCSR */
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGCTL_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGCTL_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGCTL_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGCTL_MULTI_SHOT (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGCTL_SINGLE_SHOT (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGSTATUS_MASK (0x00000002U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGSTATUS_SHIFT (1U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGSTATUS_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGSTATUS_NOT_OCCURRED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGSTATUS_OCCURRED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGCLEAR_MASK (0x00000004U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGCLEAR_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGCLEAR_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGCLEAR_NOEFFECT (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_TRIGCLEAR_CLEAR (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_ATBTRIGEN_TE_MASK (0x00000008U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_ATBTRIGEN_TE_SHIFT (3U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_ATBTRIGEN_TE_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_ATBTRIGEN_TE_DISABLE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_ATBTRIGEN_TE_ENABLE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_ATBTRIGEN_DIR_MASK (0x00000010U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_ATBTRIGEN_DIR_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_ATBTRIGEN_DIR_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_ATBTRIGEN_DIR_DISABLE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_ATBTRIGEN_DIR_ENABLE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPTRIGCSR_RESETVAL (0x00000000U)
/* STMTCSR */
#define CSL_CXSTM_TETRIS_STMTCSR_EN_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMTCSR_EN_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMTCSR_EN_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMTCSR_EN_DISABLE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMTCSR_EN_ENABLE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMTCSR_TSEN_MASK (0x00000002U)
#define CSL_CXSTM_TETRIS_STMTCSR_TSEN_SHIFT (1U)
#define CSL_CXSTM_TETRIS_STMTCSR_TSEN_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMTCSR_TSEN_DISABLE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMTCSR_TSEN_ENABLE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMTCSR_SYNCEN_MASK (0x00000004U)
#define CSL_CXSTM_TETRIS_STMTCSR_SYNCEN_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMTCSR_SYNCEN_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMTCSR_SYNCEN_RAO (0x00000001U)
#define CSL_CXSTM_TETRIS_STMTCSR_COMPEN_MASK (0x00000020U)
#define CSL_CXSTM_TETRIS_STMTCSR_COMPEN_SHIFT (5U)
#define CSL_CXSTM_TETRIS_STMTCSR_COMPEN_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMTCSR_COMPEN_DISABLED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMTCSR_COMPEN_ENABLED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMTCSR_TRACEID_MASK (0x007F0000U)
#define CSL_CXSTM_TETRIS_STMTCSR_TRACEID_SHIFT (16U)
#define CSL_CXSTM_TETRIS_STMTCSR_TRACEID_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMTCSR_TRACEID_MAX (0x0000007fU)
#define CSL_CXSTM_TETRIS_STMTCSR_BUSY_MASK (0x00800000U)
#define CSL_CXSTM_TETRIS_STMTCSR_BUSY_SHIFT (23U)
#define CSL_CXSTM_TETRIS_STMTCSR_BUSY_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMTCSR_BUSY_IDLE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMTCSR_BUSY_BUSY (0x00000001U)
#define CSL_CXSTM_TETRIS_STMTCSR_RESETVAL (0x00000004U)
/* STMTSSTIMR */
#define CSL_CXSTM_TETRIS_STMTSSTIMR_FORCETS_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMTSSTIMR_FORCETS_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMTSSTIMR_FORCETS_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMTSSTIMR_FORCETS_FORCETS (0x00000001U)
#define CSL_CXSTM_TETRIS_STMTSSTIMR_RESETVAL (0x00000000U)
/* STMTSFREQR */
#define CSL_CXSTM_TETRIS_STMTSFREQR_FREQ_MASK (0xFFFFFFFFU)
#define CSL_CXSTM_TETRIS_STMTSFREQR_FREQ_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMTSFREQR_FREQ_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMTSFREQR_FREQ_MAX (0xffffffffU)
#define CSL_CXSTM_TETRIS_STMTSFREQR_RESETVAL (0x00000000U)
/* STMSYNCR */
#define CSL_CXSTM_TETRIS_STMSYNCR_COUNT_MASK (0x00000FFCU)
#define CSL_CXSTM_TETRIS_STMSYNCR_COUNT_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMSYNCR_COUNT_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSYNCR_COUNT_MAX (0x000003ffU)
#define CSL_CXSTM_TETRIS_STMSYNCR_MODE_MASK (0x00001000U)
#define CSL_CXSTM_TETRIS_STMSYNCR_MODE_SHIFT (12U)
#define CSL_CXSTM_TETRIS_STMSYNCR_MODE_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSYNCR_MODE_NBYTES (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSYNCR_MODE_TWOTOTHENBYTES (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSYNCR_RESETVAL (0x00000000U)
/* STMAUXCR */
#define CSL_CXSTM_TETRIS_STMAUXCR_FIFOAF_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMAUXCR_FIFOAF_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMAUXCR_FIFOAF_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMAUXCR_FIFOAF_DISABLED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMAUXCR_FIFOAF_ENABLED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMAUXCR_ASYNCPE_MASK (0x00000002U)
#define CSL_CXSTM_TETRIS_STMAUXCR_ASYNCPE_SHIFT (1U)
#define CSL_CXSTM_TETRIS_STMAUXCR_ASYNCPE_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMAUXCR_ASYNCPE_DISABLE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMAUXCR_ASYNCPE_ENABLE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMAUXCR_PRIORINVDIS_MASK (0x00000004U)
#define CSL_CXSTM_TETRIS_STMAUXCR_PRIORINVDIS_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMAUXCR_PRIORINVDIS_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMAUXCR_PRIORINVDIS_INVERSIONENABLED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMAUXCR_PRIORINVDIS_INVERSIONDISABLED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMAUXCR_CLKON_MASK (0x00000008U)
#define CSL_CXSTM_TETRIS_STMAUXCR_CLKON_SHIFT (3U)
#define CSL_CXSTM_TETRIS_STMAUXCR_CLKON_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMAUXCR_CLKON_NOOVERRIDE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMAUXCR_CLKON_OVERRIDE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMAUXCR_AFREADYHIGH_MASK (0x00000010U)
#define CSL_CXSTM_TETRIS_STMAUXCR_AFREADYHIGH_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMAUXCR_AFREADYHIGH_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMAUXCR_AFREADYHIGH_NOOVERRIDE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMAUXCR_AFREADYHIGH_OVERRIDE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMAUXCR_RESETVAL (0x00000000U)
/* STMSPFEAT1R */
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_PROT_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_PROT_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_PROT_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_PROT_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TS_MASK (0x00000030U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TS_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TS_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TS_ABSOLUT (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TSFREQ_MASK (0x00000040U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TSFREQ_SHIFT (6U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TSFREQ_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TSFREQ_RW (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_FORCETS_MASK (0x00000080U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_FORCETS_SHIFT (7U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_FORCETS_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_FORCETS_IMPLEMENTED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SYNC_MASK (0x00000300U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SYNC_SHIFT (8U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SYNC_RESETVAL (0x00000003U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SYNC_MODE (0x00000003U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TRACEBUS_MASK (0x00003C00U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TRACEBUS_SHIFT (10U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TRACEBUS_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TRACEBUS_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TRIGCTL_MASK (0x0000C000U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TRIGCTL_SHIFT (14U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TRIGCTL_RESETVAL (0x00000002U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TRIGCTL_MULTI_SHOTANDSINGLE_SHOT (0x00000002U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TSPRESCALE_MASK (0x00030000U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TSPRESCALE_SHIFT (16U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TSPRESCALE_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_TSPRESCALE_NOTIMPLEMENTED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_HWTEN_MASK (0x000C0000U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_HWTEN_SHIFT (18U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_HWTEN_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_HWTEN_NOTIMPLEMENTED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SYNCEN_MASK (0x00300000U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SYNCEN_SHIFT (20U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SYNCEN_RESETVAL (0x00000002U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SYNCEN_RAO (0x00000002U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SWOEN_MASK (0x00C00000U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SWOEN_SHIFT (22U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SWOEN_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_SWOEN_NOTIMPLEMENTED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT1R_RESETVAL (0x006587d1U)
/* STMSPFEAT2R */
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTER_MASK (0x00000003U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTER_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTER_RESETVAL (0x00000002U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTER_IMPLEMENTED (0x00000002U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPER_MASK (0x00000004U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPER_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPER_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPER_IMPLEMENTED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPCOMP_MASK (0x00000030U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPCOMP_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPCOMP_RESETVAL (0x00000003U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPCOMP_PROGRAMMABLE (0x00000003U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPOVERRIDE_MASK (0x00000040U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPOVERRIDE_SHIFT (6U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPOVERRIDE_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPOVERRIDE_IMPLEMENTED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_PRIVMASK_MASK (0x00000180U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_PRIVMASK_SHIFT (7U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_PRIVMASK_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_PRIVMASK_NOTIMPLEMENTED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTRTYPE_MASK (0x00000600U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTRTYPE_SHIFT (9U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTRTYPE_RESETVAL (0x00000002U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTRTYPE_INVARIANTTIMINGANDGUARANTEED (0x00000002U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_DSIZE_MASK (0x0000F000U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_DSIZE_SHIFT (12U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_DSIZE_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_DSIZE_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTYPE_MASK (0x00030000U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTYPE_SHIFT (16U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTYPE_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_SPTYPE_EXTENDEDONLY (0x00000001U)
#define CSL_CXSTM_TETRIS_STMSPFEAT2R_RESETVAL (0x000104f2U)
/* STMSPFEAT3R */
#define CSL_CXSTM_TETRIS_STMSPFEAT3R_NUMMAST_MASK (0x0000007FU)
#define CSL_CXSTM_TETRIS_STMSPFEAT3R_NUMMAST_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMSPFEAT3R_NUMMAST_RESETVAL (0x0000007fU)
#define CSL_CXSTM_TETRIS_STMSPFEAT3R_NUMMAST_MAX (0x0000007fU)
#define CSL_CXSTM_TETRIS_STMSPFEAT3R_RESETVAL (0x0000007fU)
/* STMITTRIGGER */
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTSPTE_W_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTSPTE_W_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTSPTE_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTSPTE_W_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTSPTE_W_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTSW_W_MASK (0x00000002U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTSW_W_SHIFT (1U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTSW_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTSW_W_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTSW_W_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTHETE_W_MASK (0x00000004U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTHETE_W_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTHETE_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTHETE_W_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_TRIGOUTHETE_W_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_ASYNCOUT_W_MASK (0x00000008U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_ASYNCOUT_W_SHIFT (3U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_ASYNCOUT_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_ASYNCOUT_W_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_ASYNCOUT_W_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITTRIGGER_RESETVAL (0x00000000U)
/* STMITATBDATA0 */
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM0_W_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM0_W_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM0_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM0_W_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM0_W_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM7_W_MASK (0x00000002U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM7_W_SHIFT (1U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM7_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM7_W_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM7_W_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM15_W_MASK (0x00000004U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM15_W_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM15_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM15_W_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM15_W_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM23_W_MASK (0x00000008U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM23_W_SHIFT (3U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM23_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM23_W_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM23_W_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM31_W_MASK (0x00000010U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM31_W_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM31_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM31_W_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_ATDATAM31_W_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBDATA0_RESETVAL (0x00000000U)
/* STMITATBCTR2 */
#define CSL_CXSTM_TETRIS_STMITATBCTR2_ATREADYM_R_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBCTR2_ATREADYM_R_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMITATBCTR2_ATREADYM_R_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBCTR2_ATREADYM_R_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBCTR2_ATREADYM_R_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBCTR2_AFVALIDM_R_MASK (0x00000002U)
#define CSL_CXSTM_TETRIS_STMITATBCTR2_AFVALIDM_R_SHIFT (1U)
#define CSL_CXSTM_TETRIS_STMITATBCTR2_AFVALIDM_R_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBCTR2_AFVALIDM_R_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBCTR2_AFVALIDM_R_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBCTR2_RESETVAL (0x00000000U)
/* STMITATBID */
#define CSL_CXSTM_TETRIS_STMITATBID_ATIDM_W_MASK (0x0000007FU)
#define CSL_CXSTM_TETRIS_STMITATBID_ATIDM_W_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMITATBID_ATIDM_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBID_ATIDM_W_MAX (0x0000007fU)
#define CSL_CXSTM_TETRIS_STMITATBID_RESETVAL (0x00000000U)
/* STMITATBCTR0 */
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATVALIDM_W_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATVALIDM_W_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATVALIDM_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATVALIDM_W_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATVALIDM_W_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_AFREADYM_W_MASK (0x00000002U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_AFREADYM_W_SHIFT (1U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_AFREADYM_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_AFREADYM_W_HIGH (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_AFREADYM_W_LOW (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATBYTESM_W_MASK (0x00000300U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATBYTESM_W_SHIFT (8U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATBYTESM_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATBYTESM_W_L11 (0x00000003U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATBYTESM_W_L10 (0x00000002U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATBYTESM_W_L01 (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_ATBYTESM_W_L00 (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITATBCTR0_RESETVAL (0x00000000U)
/* STMITCTRL */
#define CSL_CXSTM_TETRIS_STMITCTRL_INTEGRATION_MODE_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITCTRL_INTEGRATION_MODE_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMITCTRL_INTEGRATION_MODE_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITCTRL_INTEGRATION_MODE_INTEGRATIONMODE (0x00000001U)
#define CSL_CXSTM_TETRIS_STMITCTRL_INTEGRATION_MODE_FUNCTIONALMODE (0x00000000U)
#define CSL_CXSTM_TETRIS_STMITCTRL_RESETVAL (0x00000000U)
/* STMCLAIMSET */
#define CSL_CXSTM_TETRIS_STMCLAIMSET_CLAIMSET_R_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMCLAIMSET_CLAIMSET_R_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMCLAIMSET_CLAIMSET_R_RESETVAL (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMCLAIMSET_CLAIMSET_R_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMCLAIMSET_CLAIMSET_W_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMCLAIMSET_CLAIMSET_W_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMCLAIMSET_CLAIMSET_W_RESETVAL (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMCLAIMSET_CLAIMSET_W_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMCLAIMSET_RESETVAL (0x0000000fU)
/* STMCLAIMCLR */
#define CSL_CXSTM_TETRIS_STMCLAIMCLR_CLAIMCLR_R_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMCLAIMCLR_CLAIMCLR_R_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMCLAIMCLR_CLAIMCLR_R_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMCLAIMCLR_CLAIMCLR_R_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMCLAIMCLR_CLAIMCLR_W_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMCLAIMCLR_CLAIMCLR_W_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMCLAIMCLR_CLAIMCLR_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMCLAIMCLR_CLAIMCLR_W_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMCLAIMCLR_RESETVAL (0x00000000U)
/* STMLAR */
#define CSL_CXSTM_TETRIS_STMLAR_ACCESS_W_MASK (0xFFFFFFFFU)
#define CSL_CXSTM_TETRIS_STMLAR_ACCESS_W_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMLAR_ACCESS_W_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMLAR_ACCESS_W_MAX (0xffffffffU)
#define CSL_CXSTM_TETRIS_STMLAR_RESETVAL (0x00000000U)
/* STMLSR */
#define CSL_CXSTM_TETRIS_STMLSR_LOCKEXIST_MASK (0x00000001U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKEXIST_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKEXIST_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKEXIST_LOCKNOTPRESENT (0x00000000U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKEXIST_LOCKPRESENT (0x00000001U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKGRANT_MASK (0x00000002U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKGRANT_SHIFT (1U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKGRANT_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKGRANT_ACCESSPERMITTED (0x00000000U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKGRANT_DEVICELOCKED (0x00000001U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKTYPE_MASK (0x00000004U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKTYPE_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKTYPE_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMLSR_LOCKTYPE_LAR32BIT (0x00000000U)
#define CSL_CXSTM_TETRIS_STMLSR_RESETVAL (0x00000003U)
/* STMAUTHSTATUS */
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_NSID_MASK (0x00000003U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_NSID_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_NSID_RESETVAL (0x00000002U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_NSID_DISABLED (0x00000002U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_NSID_ENABLED (0x00000003U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_NSNID_MASK (0x0000000CU)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_NSNID_SHIFT (2U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_NSNID_RESETVAL (0x00000002U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_NSNID_DISABLED (0x00000002U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_NSNID_ENABLED (0x00000003U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_SID_MASK (0x00000030U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_SID_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_SID_RESETVAL (0x00000002U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_SID_DISABLED (0x00000002U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_SID_ENABLED (0x00000003U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_SNID_MASK (0x000000C0U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_SNID_SHIFT (6U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_SNID_RESETVAL (0x00000002U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_SNID_DISABLED (0x00000002U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_SNID_ENABLED (0x00000003U)
#define CSL_CXSTM_TETRIS_STMAUTHSTATUS_RESETVAL (0x000000aaU)
/* STMDEVID */
#define CSL_CXSTM_TETRIS_STMDEVID_NUMSP_MASK (0x0001FFFFU)
#define CSL_CXSTM_TETRIS_STMDEVID_NUMSP_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMDEVID_NUMSP_RESETVAL (0x00010000U)
#define CSL_CXSTM_TETRIS_STMDEVID_NUMSP_MAX (0x0001ffffU)
#define CSL_CXSTM_TETRIS_STMDEVID_RESETVAL (0x00010000U)
/* STMDEVTYPE */
#define CSL_CXSTM_TETRIS_STMDEVTYPE_MAJOR_TYPE_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMDEVTYPE_MAJOR_TYPE_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMDEVTYPE_MAJOR_TYPE_RESETVAL (0x00000003U)
#define CSL_CXSTM_TETRIS_STMDEVTYPE_MAJOR_TYPE_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMDEVTYPE_SUB_TYPE_MASK (0x000000F0U)
#define CSL_CXSTM_TETRIS_STMDEVTYPE_SUB_TYPE_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMDEVTYPE_SUB_TYPE_RESETVAL (0x00000006U)
#define CSL_CXSTM_TETRIS_STMDEVTYPE_SUB_TYPE_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMDEVTYPE_RESETVAL (0x00000063U)
/* STMPIDR0 */
#define CSL_CXSTM_TETRIS_STMPIDR0_PART_NUMBER_BITS7TO0_MASK (0x000000FFU)
#define CSL_CXSTM_TETRIS_STMPIDR0_PART_NUMBER_BITS7TO0_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMPIDR0_PART_NUMBER_BITS7TO0_RESETVAL (0x00000062U)
#define CSL_CXSTM_TETRIS_STMPIDR0_PART_NUMBER_BITS7TO0_MAX (0x000000ffU)
#define CSL_CXSTM_TETRIS_STMPIDR0_RESETVAL (0x00000062U)
/* STMPIDR1 */
#define CSL_CXSTM_TETRIS_STMPIDR1_PART_NUMBER_BITS11TO8_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMPIDR1_PART_NUMBER_BITS11TO8_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMPIDR1_PART_NUMBER_BITS11TO8_RESETVAL (0x00000009U)
#define CSL_CXSTM_TETRIS_STMPIDR1_PART_NUMBER_BITS11TO8_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMPIDR1_JEP106_BITS3TO0_MASK (0x000000F0U)
#define CSL_CXSTM_TETRIS_STMPIDR1_JEP106_BITS3TO0_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMPIDR1_JEP106_BITS3TO0_RESETVAL (0x0000000bU)
#define CSL_CXSTM_TETRIS_STMPIDR1_JEP106_BITS3TO0_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMPIDR1_RESETVAL (0x000000b9U)
/* STMPIDR2 */
#define CSL_CXSTM_TETRIS_STMPIDR2_JEP106_BITS6TO4_MASK (0x00000007U)
#define CSL_CXSTM_TETRIS_STMPIDR2_JEP106_BITS6TO4_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMPIDR2_JEP106_BITS6TO4_RESETVAL (0x00000003U)
#define CSL_CXSTM_TETRIS_STMPIDR2_JEP106_BITS6TO4_ARMJEP106IDENTITYCODE64 (0x00000003U)
#define CSL_CXSTM_TETRIS_STMPIDR2_JEDEC_MASK (0x00000008U)
#define CSL_CXSTM_TETRIS_STMPIDR2_JEDEC_SHIFT (3U)
#define CSL_CXSTM_TETRIS_STMPIDR2_JEDEC_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMPIDR2_JEDEC_JEDECIDENTITY (0x00000001U)
#define CSL_CXSTM_TETRIS_STMPIDR2_REVISION_MASK (0x000000F0U)
#define CSL_CXSTM_TETRIS_STMPIDR2_REVISION_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMPIDR2_REVISION_RESETVAL (0x00000001U)
#define CSL_CXSTM_TETRIS_STMPIDR2_REVISION_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMPIDR2_RESETVAL (0x0000001bU)
/* STMPIDR3 */
#define CSL_CXSTM_TETRIS_STMPIDR3_CUSTOMER_MODIFIED_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMPIDR3_CUSTOMER_MODIFIED_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMPIDR3_CUSTOMER_MODIFIED_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMPIDR3_CUSTOMER_MODIFIED_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMPIDR3_REVAND_MASK (0x000000F0U)
#define CSL_CXSTM_TETRIS_STMPIDR3_REVAND_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMPIDR3_REVAND_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMPIDR3_REVAND_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMPIDR3_RESETVAL (0x00000000U)
/* STMPIDR4 */
#define CSL_CXSTM_TETRIS_STMPIDR4_JEP106_CONT_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMPIDR4_JEP106_CONT_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMPIDR4_JEP106_CONT_RESETVAL (0x00000004U)
#define CSL_CXSTM_TETRIS_STMPIDR4_JEP106_CONT_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMPIDR4_FOURKB_COUNT_MASK (0x000000F0U)
#define CSL_CXSTM_TETRIS_STMPIDR4_FOURKB_COUNT_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMPIDR4_FOURKB_COUNT_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMPIDR4_FOURKB_COUNT_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMPIDR4_RESETVAL (0x00000004U)
/* STMPIDR5 */
#define CSL_CXSTM_TETRIS_STMPIDR5_RESETVAL (0x00000000U)
/* STMPIDR6 */
#define CSL_CXSTM_TETRIS_STMPIDR6_RESETVAL (0x00000000U)
/* STMPIDR7 */
#define CSL_CXSTM_TETRIS_STMPIDR7_RESETVAL (0x00000000U)
/* STMCIDR0 */
#define CSL_CXSTM_TETRIS_STMCIDR0_PREAMBLE_MASK (0x000000FFU)
#define CSL_CXSTM_TETRIS_STMCIDR0_PREAMBLE_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMCIDR0_PREAMBLE_RESETVAL (0x0000000dU)
#define CSL_CXSTM_TETRIS_STMCIDR0_PREAMBLE_MAX (0x000000ffU)
#define CSL_CXSTM_TETRIS_STMCIDR0_RESETVAL (0x0000000dU)
/* STMCIDR1 */
#define CSL_CXSTM_TETRIS_STMCIDR1_PREAMBLE_MASK (0x0000000FU)
#define CSL_CXSTM_TETRIS_STMCIDR1_PREAMBLE_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMCIDR1_PREAMBLE_RESETVAL (0x00000000U)
#define CSL_CXSTM_TETRIS_STMCIDR1_PREAMBLE_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMCIDR1_CLASS_MASK (0x000000F0U)
#define CSL_CXSTM_TETRIS_STMCIDR1_CLASS_SHIFT (4U)
#define CSL_CXSTM_TETRIS_STMCIDR1_CLASS_RESETVAL (0x00000009U)
#define CSL_CXSTM_TETRIS_STMCIDR1_CLASS_MAX (0x0000000fU)
#define CSL_CXSTM_TETRIS_STMCIDR1_RESETVAL (0x00000090U)
/* STMCIDR2 */
#define CSL_CXSTM_TETRIS_STMCIDR2_PREAMBLE_MASK (0x000000FFU)
#define CSL_CXSTM_TETRIS_STMCIDR2_PREAMBLE_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMCIDR2_PREAMBLE_RESETVAL (0x00000005U)
#define CSL_CXSTM_TETRIS_STMCIDR2_PREAMBLE_MAX (0x000000ffU)
#define CSL_CXSTM_TETRIS_STMCIDR2_RESETVAL (0x00000005U)
/* STMCIDR3 */
#define CSL_CXSTM_TETRIS_STMCIDR3_PREAMBLE_MASK (0x000000FFU)
#define CSL_CXSTM_TETRIS_STMCIDR3_PREAMBLE_SHIFT (0U)
#define CSL_CXSTM_TETRIS_STMCIDR3_PREAMBLE_RESETVAL (0x000000b1U)
#define CSL_CXSTM_TETRIS_STMCIDR3_PREAMBLE_MAX (0x000000ffU)
#define CSL_CXSTM_TETRIS_STMCIDR3_RESETVAL (0x000000b1U)
#ifdef __cplusplus
}
#endif
#endif
| 48.510804 | 89 | 0.719012 |
340298879bdc5fdbadf1c19e222115b06a6bc2ad | 26,859 | c | C | Tools/STM32FW/STM32Cube_FW_F7_V1.16.2/Projects/STM32F769I-Discovery/Examples/PWR/PWR_CurrentConsumption/Src/stm32f7xx_lp_modes.c | ramkumarkoppu/NUCLEO-F767ZI-ESW | 85e129d71ee8eccbd0b94b5e07e75b6b91679ee8 | [
"MIT"
] | null | null | null | Tools/STM32FW/STM32Cube_FW_F7_V1.16.2/Projects/STM32F769I-Discovery/Examples/PWR/PWR_CurrentConsumption/Src/stm32f7xx_lp_modes.c | ramkumarkoppu/NUCLEO-F767ZI-ESW | 85e129d71ee8eccbd0b94b5e07e75b6b91679ee8 | [
"MIT"
] | null | null | null | Tools/STM32FW/STM32Cube_FW_F7_V1.16.2/Projects/STM32F769I-Discovery/Examples/PWR/PWR_CurrentConsumption/Src/stm32f7xx_lp_modes.c | ramkumarkoppu/NUCLEO-F767ZI-ESW | 85e129d71ee8eccbd0b94b5e07e75b6b91679ee8 | [
"MIT"
] | null | null | null | /**
******************************************************************************
* @file PWR/PWR_CurrentConsumption/stm32f7xx_lp_modes.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* functionalities of the STM32F7xx Low Power Modes:
* - Sleep Mode
* - STOP mode with RTC
* - STANDBY mode without RTC and BKPSRAM
* - STANDBY mode with RTC
* - STANDBY mode with RTC and BKPSRAM
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/** @addtogroup STM32F7xx_HAL_Examples
* @{
*/
/** @addtogroup PWR_CurrentConsumption
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ULPI PHY */
#define USBULPI_PHYCR ((uint32_t)(0x40040000 + 0x034))
#define USBULPI_D07 ((uint32_t)0x000000FF)
#define USBULPI_New ((uint32_t)0x02000000)
#define USBULPI_RW ((uint32_t)0x00400000)
#define USBULPI_S_BUSY ((uint32_t)0x04000000)
#define USBULPI_S_DONE ((uint32_t)0x08000000)
#define Pattern_55 ((uint32_t)0x00000055)
#define Pattern_AA ((uint32_t)0x000000AA)
#define PHY_PWR_DOWN (1<<11)
#define PHY_ADDRESS 0x00 /* default ADDR for PHY: LAN8742 */
#define USB_OTG_READ_REG32(reg) (*(__IO uint32_t *)(reg))
#define USB_OTG_WRITE_REG32(reg,value) (*(__IO uint32_t *)(reg) = (value))
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* RTC handler declaration */
RTC_HandleTypeDef RTCHandle;
/* Private function prototypes -----------------------------------------------*/
static void SYSCLKConfig_STOP(void);
/* Private functions ---------------------------------------------------------*/
/**
* @brief This function configures the system to enter Sleep mode for
* current consumption measurement purpose.
* Sleep Mode
* ==========
* - System Running at PLL (216MHz)
* - Flash 5 wait state
* - Instruction and Data caches ON
* - Prefetch ON
* - Code running from Internal FLASH
* - All peripherals disabled.
* - Wakeup using EXTI Line (USER Button)
* @param None
* @retval None
*/
void SleepMode_Measure(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* Disable USB Clock */
__HAL_RCC_USB_OTG_HS_CLK_DISABLE();
__HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE();
/* Disable Ethernet Clock */
__HAL_RCC_ETH_CLK_DISABLE();
/* Configure all GPIO as analog to reduce current consumption on non used IOs */
/* Enable GPIOs clock */
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOJ_CLK_ENABLE();
__HAL_RCC_GPIOK_CLK_ENABLE();
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Pin = GPIO_PIN_All;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
/* Disable GPIOs clock */
__HAL_RCC_GPIOA_CLK_DISABLE();
__HAL_RCC_GPIOB_CLK_DISABLE();
__HAL_RCC_GPIOC_CLK_DISABLE();
__HAL_RCC_GPIOD_CLK_DISABLE();
__HAL_RCC_GPIOE_CLK_DISABLE();
__HAL_RCC_GPIOF_CLK_DISABLE();
__HAL_RCC_GPIOG_CLK_DISABLE();
__HAL_RCC_GPIOH_CLK_DISABLE();
__HAL_RCC_GPIOI_CLK_DISABLE();
__HAL_RCC_GPIOJ_CLK_DISABLE();
__HAL_RCC_GPIOK_CLK_DISABLE();
/* Configure USER Button */
BSP_PB_Init(BUTTON_USER, BUTTON_MODE_EXTI);
/* Suspend Tick increment to prevent wakeup by Systick interrupt.
Otherwise the Systick interrupt will wake up the device within 1ms (HAL time base) */
HAL_SuspendTick();
/* Request to enter SLEEP mode */
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
/* Resume Tick interrupt if disabled prior to sleep mode entry */
HAL_ResumeTick();
/* Exit USB Phy from LowPower mode */
USB_PhyExitFromLowPowerMode();
/* Exit Ethernet Phy from LowPower mode */
ETH_PhyExitFromPowerDownMode();
}
/**
* @brief This function configures the system to enter Stop mode with RTC
* clocked by LSE or LSI for current consumption measurement purpose.
* STOP Mode with RTC clocked by LSE/LSI
* =====================================
* - RTC Clocked by LSE or LSI
* - Regulator in LP mode
* - HSI, HSE OFF and LSI OFF if not used as RTC Clock source
* - No IWDG
* - FLASH in deep power down mode
* - Automatic Wakeup using RTC clocked by LSE/LSI (~20s)
* @param None
* @retval None
*/
void StopMode_Measure(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* Disable USB Clock */
__HAL_RCC_USB_OTG_HS_CLK_DISABLE();
__HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE();
/* Disable Ethernet Clock */
__HAL_RCC_ETH_CLK_DISABLE();
/* Configure all GPIO as analog to reduce current consumption on non used IOs */
/* Enable GPIOs clock */
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOJ_CLK_ENABLE();
__HAL_RCC_GPIOK_CLK_ENABLE();
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Pin = GPIO_PIN_All;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
/* Disable GPIOs clock */
__HAL_RCC_GPIOA_CLK_DISABLE();
__HAL_RCC_GPIOB_CLK_DISABLE();
__HAL_RCC_GPIOC_CLK_DISABLE();
__HAL_RCC_GPIOD_CLK_DISABLE();
__HAL_RCC_GPIOE_CLK_DISABLE();
__HAL_RCC_GPIOF_CLK_DISABLE();
__HAL_RCC_GPIOG_CLK_DISABLE();
__HAL_RCC_GPIOH_CLK_DISABLE();
__HAL_RCC_GPIOI_CLK_DISABLE();
__HAL_RCC_GPIOJ_CLK_DISABLE();
__HAL_RCC_GPIOK_CLK_DISABLE();
RTCHandle.Instance = RTC;
/* Configure RTC prescaler and RTC data registers as follow:
- Hour Format = Format 24
- Asynch Prediv = Value according to source clock
- Synch Prediv = Value according to source clock
- OutPut = Output Disable
- OutPutPolarity = High Polarity
- OutPutType = Open Drain */
RTCHandle.Init.HourFormat = RTC_HOURFORMAT_24;
RTCHandle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
RTCHandle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
RTCHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
RTCHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
RTCHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
if(HAL_RTC_Init(&RTCHandle) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
/*## Configure the Wake up timer ###########################################*/
/* RTC Wakeup Interrupt Generation:
Wakeup Time Base = (RTC_WAKEUPCLOCK_RTCCLK_DIV /(LSI))
Wakeup Time = Wakeup Time Base * WakeUpCounter
= (RTC_WAKEUPCLOCK_RTCCLK_DIV /(LSI)) * WakeUpCounter
==> WakeUpCounter = Wakeup Time / Wakeup Time Base
To configure the wake up timer to 20s the WakeUpCounter is set to 0xA017:
RTC_WAKEUPCLOCK_RTCCLK_DIV = RTCCLK_Div16 = 16
Wakeup Time Base = 16 /(~32.768KHz) = ~0,488 ms
Wakeup Time = ~20s = 0,488ms * WakeUpCounter
==> WakeUpCounter = ~20s/0,488ms = 40983 = 0xA017 */
HAL_RTCEx_SetWakeUpTimer_IT(&RTCHandle, 0xA017, RTC_WAKEUPCLOCK_RTCCLK_DIV16);
/* FLASH Deep Power Down Mode enabled */
HAL_PWREx_EnableFlashPowerDown();
/* Enter Stop Mode */
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
/* Configures system clock after wake-up from STOP: enable HSE, PLL and select
PLL as system clock source (HSE and PLL are disabled in STOP mode) */
SYSCLKConfig_STOP();
/* Exit USB Phy from low power mode */
USB_PhyExitFromLowPowerMode();
/* Exit Ethernet Phy from low power mode */
ETH_PhyExitFromPowerDownMode();
/* Disable Wake-up timer */
if(HAL_RTCEx_DeactivateWakeUpTimer(&RTCHandle) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
}
/**
* @brief This function configures the system to enter Standby mode for
* current consumption measurement purpose.
* STANDBY Mode
* ============
* - Backup SRAM and RTC OFF
* - IWDG and LSI OFF
* - Wakeup using WakeUp Pin1(PA.0)
* @param None
* @retval None
*/
void StandbyMode_Measure(void)
{
/* Disable all used wakeup sources: Pin1(PA.0) */
HAL_PWR_DisableWakeUpPin(PWR_WAKEUP_PIN1);
/* Clear the related wakeup pin flag */
__HAL_PWR_CLEAR_WAKEUP_FLAG(PWR_WAKEUP_PIN_FLAG1);
/* Re-enable all used wakeup sources: Pin1(PA.0) */
HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1);
/* Request to enter STANDBY mode */
HAL_PWR_EnterSTANDBYMode();
}
/**
* @brief This function configures the system to enter Standby mode with RTC
* clocked by LSE or LSI for current consumption measurement purpose.
* STANDBY Mode with RTC clocked by LSE/LSI
* ========================================
* - RTC Clocked by LSE/LSI
* - IWDG OFF
* - Backup SRAM OFF
* - Automatic Wakeup using RTC clocked by LSE/LSI (after ~20s)
* @param None
* @retval None
*/
void StandbyRTCMode_Measure(void)
{
RTCHandle.Instance = RTC;
/* Configure RTC prescaler and RTC data registers as follow:
- Hour Format = Format 24
- Asynch Prediv = Value according to source clock
- Synch Prediv = Value according to source clock
- OutPut = Output Disable
- OutPutPolarity = High Polarity
- OutPutType = Open Drain */
RTCHandle.Init.HourFormat = RTC_HOURFORMAT_24;
RTCHandle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
RTCHandle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
RTCHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
RTCHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
RTCHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
if(HAL_RTC_Init(&RTCHandle) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
/*## Configure the Wake up timer ###########################################*/
/* RTC Wakeup Interrupt Generation:
Wakeup Time Base = (RTC_WAKEUPCLOCK_RTCCLK_DIV /(LSI))
Wakeup Time = Wakeup Time Base * WakeUpCounter
= (RTC_WAKEUPCLOCK_RTCCLK_DIV /(LSI)) * WakeUpCounter
==> WakeUpCounter = Wakeup Time / Wakeup Time Base
To configure the wake up timer to 20s the WakeUpCounter is set to 0xA017:
RTC_WAKEUPCLOCK_RTCCLK_DIV = RTCCLK_Div16 = 16
Wakeup Time Base = 16 /(~32.768KHz) = ~0,488 ms
Wakeup Time = ~20s = 0,488ms * WakeUpCounter
==> WakeUpCounter = ~20s/0,488ms = 40983 = 0xA017 */
/* Disable Wake-up timer */
if(HAL_RTCEx_DeactivateWakeUpTimer(&RTCHandle) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
/*## Clear all related wakeup flags ########################################*/
/* Clear RTC Wake Up timer Flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&RTCHandle, RTC_FLAG_WUTF);
/*## Setting the Wake up time ##############################################*/
HAL_RTCEx_SetWakeUpTimer_IT(&RTCHandle, 0xA017, RTC_WAKEUPCLOCK_RTCCLK_DIV16);
/*## Enter the Standby mode ################################################*/
/* Request to enter STANDBY mode */
HAL_PWR_EnterSTANDBYMode();
}
/**
* @brief This function configures the system to enter Standby mode with
* backup SRAM ON for current consumption measurement purpose.
* STANDBY Mode
* ============
* - RTC Clocked by LSE/LSI
* - IWDG OFF
* - Backup SRAM ON
* - Automatic Wakeup using RTC clocked by LSE/LSI (after ~20s)
* @param None
* @retval None
*/
void StandbyBKPSRAMMode_Measure(void)
{
RTCHandle.Instance = RTC;
/* Configure RTC prescaler and RTC data registers as follow:
- Hour Format = Format 24
- Asynch Prediv = Value according to source clock
- Synch Prediv = Value according to source clock
- OutPut = Output Disable
- OutPutPolarity = High Polarity
- OutPutType = Open Drain */
RTCHandle.Init.HourFormat = RTC_HOURFORMAT_24;
RTCHandle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
RTCHandle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
RTCHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
RTCHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
RTCHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
if(HAL_RTC_Init(&RTCHandle) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
/*## Configure the Wake up timer ###########################################*/
/* RTC Wakeup Interrupt Generation:
Wakeup Time Base = (RTC_WAKEUPCLOCK_RTCCLK_DIV /(LSI))
Wakeup Time = Wakeup Time Base * WakeUpCounter
= (RTC_WAKEUPCLOCK_RTCCLK_DIV /(LSI)) * WakeUpCounter
==> WakeUpCounter = Wakeup Time / Wakeup Time Base
To configure the wake up timer to 20s the WakeUpCounter is set to 0xA017:
RTC_WAKEUPCLOCK_RTCCLK_DIV = RTCCLK_Div16 = 16
Wakeup Time Base = 16 /(~32.768KHz) = ~0,488 ms
Wakeup Time = ~20s = 0,488ms * WakeUpCounter
==> WakeUpCounter = ~20s/0,488ms = 40983 = 0xA017 */
/* Disable Wake-up timer */
if(HAL_RTCEx_DeactivateWakeUpTimer(&RTCHandle) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
/*## Clear all related wakeup flags ########################################*/
/* Clear RTC Wake Up timer Flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&RTCHandle, RTC_FLAG_WUTF);
/*## Setting the Wake up time ##############################################*/
HAL_RTCEx_SetWakeUpTimer_IT(&RTCHandle, 0xA017, RTC_WAKEUPCLOCK_RTCCLK_DIV16);
/* Enable BKPRAM Clock */
__HAL_RCC_BKPSRAM_CLK_ENABLE();
/* Enable the Backup SRAM low power Regulator */
HAL_PWREx_EnableBkUpReg();
/* Request to enter STANDBY mode */
HAL_PWR_EnterSTANDBYMode();
}
/**
* @brief Configures system clock after wake-up from STOP: enable HSE, PLL
* and select PLL as system clock source.
* @param None
* @retval None
*/
static void SYSCLKConfig_STOP(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
uint32_t pFLatency = 0;
/* Get the Oscillators configuration according to the internal RCC registers */
HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
/* After wake-up from STOP reconfigure the system clock: Enable HSE and PLL */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Get the Clocks configuration according to the internal RCC registers */
HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief Read CR value
* @param Addr the Address of the ULPI Register
* @retval Returns value of PHY CR register
*/
uint32_t USB_ULPI_Read(uint32_t Addr)
{
__IO uint32_t val = 0;
__IO uint32_t timeout = 100; /* Can be tuned based on the Clock or etc... */
USB_OTG_WRITE_REG32(USBULPI_PHYCR, USBULPI_New | (Addr << 16));
val = USB_OTG_READ_REG32(USBULPI_PHYCR);
while (((val & USBULPI_S_DONE) == 0) && (timeout--))
{
val = USB_OTG_READ_REG32(USBULPI_PHYCR);
}
val = USB_OTG_READ_REG32(USBULPI_PHYCR);
return (val & 0x000000ff);
}
/**
* @brief Write CR value
* @param Addr the Address of the ULPI Register
* @param Data Data to write
* @retval Returns value of PHY CR register
*/
uint32_t USB_ULPI_Write(uint32_t Addr, uint32_t Data) /* Parameter is the Address of the ULPI Register & Date to write */
{
__IO uint32_t val;
__IO uint32_t timeout = 10; /* Can be tuned based on the Clock or etc... */
USB_OTG_WRITE_REG32(USBULPI_PHYCR, USBULPI_New | USBULPI_RW | (Addr << 16) | (Data & 0x000000ff));
val = USB_OTG_READ_REG32(USBULPI_PHYCR);
while (((val & USBULPI_S_DONE) == 0) && (timeout--))
{
val = USB_OTG_READ_REG32(USBULPI_PHYCR);
}
val = USB_OTG_READ_REG32(USBULPI_PHYCR);
return 0;
}
/**
* @brief Configures GPIO for USB ULPI
* @param None
* @retval 0
*/
void USB_ULPI_MspInit(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* Enable GPIOs clock */
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
/* Common for all IOs */
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
/* D0 PA3*/
GPIO_InitStruct.Pin = GPIO_PIN_3;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* CLK PA5*/
GPIO_InitStruct.Pin = GPIO_PIN_5;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* D1 D2 D3 D4 D5 D6 D7 :PB0/1/5/10/11/12/13 */
GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_5 |\
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\
GPIO_PIN_13;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* NXT PH4*/
GPIO_InitStruct.Pin = GPIO_PIN_4;
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
/* STP PC0*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* DIR PI11 */
GPIO_InitStruct.Pin = GPIO_PIN_11;
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
__HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
}
/**
* @brief This function configures the USB PHY to enter the low power mode
* @param None
* @retval None
*/
void USB_PhyEnterLowPowerMode(void)
{
static __IO uint32_t regval = 0;
/* USB ULPI MspInit */
USB_ULPI_MspInit();
/* disable ULPI_CLK by accessing ULPI_PHY */
/* read Vendor ID : (Low, High) 0x24,0x04 for USB3300 */
regval = USB_ULPI_Read(0x00);
if(regval != 0x24)
{
while(regval != 0x24)
{
USB_ULPI_MspInit();
regval = USB_ULPI_Read(0x00);
}
}
regval = USB_ULPI_Read(0x01);
if(regval != 0x04)
{
Error_Handler();
}
/* read Product ID */
regval = USB_ULPI_Read(0x02);
if(regval != 0x07)
{
Error_Handler();
}
regval = USB_ULPI_Read(0x03);
if(regval != 0x00)
{
Error_Handler();
}
/* Write to scratch Register the Pattern_55 */
USB_ULPI_Write(0x16, 0x55);
/* Read to scratch Register and check-it again the written Pattern */
regval = USB_ULPI_Read(0x16);
if(regval != 0x55)
{
Error_Handler();
}
/* Write to scratch Register the Pattern_AA */
USB_ULPI_Write(0x16, 0xAA);
/* Read to scratch Register and check-it again the written Pattern */
regval = USB_ULPI_Read(0x16);
if(regval != 0xAA)
{
Error_Handler();
}
/* read InterfaceControl reg */
regval = USB_ULPI_Read(0x07);
/* write InterfaceControl reg,to disable PullUp on stp,
to avoid USB_PHY wake up when MCU entering standby */
USB_ULPI_Write(0x07, regval | 0x80) ;
/* read InterfaceControl reg */
regval = USB_ULPI_Read(0x07);
if(regval != 0x80)
{
Error_Handler();
}
/* read FunctionControl reg */
regval = USB_ULPI_Read(0x04);
if(regval != 0x49)/*0x49*/
{
Error_Handler();
}
/* write FunctionControl reg,to put PHY into LowPower mode */
USB_ULPI_Write(0x04, regval & (~0x40));
/* read FunctionControl reg again */
regval = USB_ULPI_Read(0x04);
if(regval != 0x00)
{
Error_Handler();
}
}
/**
* @brief This function wakeup the USB PHY from the Low power mode
* @param None
* @retval None
*/
void USB_PhyExitFromLowPowerMode(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* Enable GPIO clock for OTG USB STP pin (optional, clock should already be enabled at this phase) */
__HAL_RCC_GPIOC_CLK_ENABLE();
/* Set OTG STP pin as GP Output */
GPIO_InitStruct.Pin = GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* Set OTG STP pin to High state during 4 milliseconds */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_SET);
/* Delay 4 ms */
HAL_Delay(4);
}
/**
* @brief This function configures the ETH PHY to enter the power down mode
* This function should be called before entering the low power mode.
* @param None
* @retval None
*/
void ETH_PhyEnterPowerDownMode(void)
{
ETH_HandleTypeDef heth;
GPIO_InitTypeDef GPIO_InitStruct;
uint32_t phyregval = 0;
/* This part of code is used only when the ETH peripheral is disabled
when the ETH is used in the application this initialization code
is called in HAL_ETH_MspInit() function ***********************/
/* Enable GPIO clocks*/
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
/* Configure PA2: ETH_MDIO */
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_2;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* Configure PC1: ETH_MDC */
GPIO_InitStruct.Pin = GPIO_PIN_1;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* Enable the ETH peripheral clocks */
__HAL_RCC_ETH_CLK_ENABLE();
/* Set ETH Handle parameters */
heth.Instance = ETH;
heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
/* Configure MDC clock: the MDC Clock Range configuration
depend on the system clock: 216Mhz/102 = 2.1MHz */
/* MDC: a periodic clock that provides the timing reference for
the MDIO data transfer at the maximum frequency of 2.5 MHz.*/
heth.Instance->MACMIIAR = (uint32_t)ETH_MACMIIAR_CR_Div102;
/*****************************************************************/
/* ETH PHY configuration in Power Down mode **********************/
/* Read ETH PHY control register */
HAL_ETH_ReadPHYRegister(&heth, PHY_BCR, &phyregval);
/* Set Power down mode bit */
phyregval |= PHY_POWERDOWN;
/* Write new value to ETH PHY control register */
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, phyregval);
/*****************************************************************/
/* Disable periph CLKs */
__HAL_RCC_GPIOA_CLK_DISABLE();
__HAL_RCC_GPIOC_CLK_DISABLE();
__HAL_RCC_ETH_CLK_DISABLE();
}
/**
* @brief This function wakeup the ETH PHY from the power down mode
* When exiting from StandBy mode and the ETH is used in the example
* its better to call this function at the end of HAL_ETH_MspInit()
* then remove the code that initialize the ETH CLKs ang GPIOs.
* @param None
* @retval None
*/
void ETH_PhyExitFromPowerDownMode(void)
{
ETH_HandleTypeDef heth;
GPIO_InitTypeDef GPIO_InitStruct;
uint32_t phyregval = 0;
/* ETH CLKs and GPIOs initilization ******************************/
/* To be removed when the function is called from HAL_ETH_MspInit() when
exiting from Standby mode */
/* Enable GPIO clocks*/
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
/* Configure PA2 */
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_2;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* Configure PC1*/
GPIO_InitStruct.Pin = GPIO_PIN_1;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* Enable ETH CLK */
__HAL_RCC_ETH_CLK_ENABLE();
/*****************************************************************/
/* ETH PHY configuration to exit Power Down mode *****************/
/* Set ETH Handle parameters */
heth.Instance = ETH;
heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
/* Configure MDC clock: the MDC Clock Range configuration
depend on the system clock: 216Mhz/102 = 2.1MHz */
/* MDC: a periodic clock that provides the timing reference for
the MDIO data transfer at the maximum frequency of 2.5 MHz.*/
heth.Instance->MACMIIAR = (uint32_t)ETH_MACMIIAR_CR_Div102;
/* Read ETH PHY control register */
HAL_ETH_ReadPHYRegister(&heth, PHY_BCR, &phyregval);
/* check if the PHY is already in power down mode */
if ((phyregval & PHY_POWERDOWN) != RESET)
{
/* Disable Power down mode */
phyregval &= ~ PHY_POWERDOWN;
/* Write value to ETH PHY control register */
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, phyregval);
}
/*****************************************************************/
}
/**
* @}
*/
/**
* @}
*/
| 32.438406 | 123 | 0.654194 |
314599af65986b8094f3468f1ec0d260280c218b | 642 | h | C | include/thread.h | Spiikesan/C-modulaire | 43e83d17d3e0141391942ba4736feb62f1699a43 | [
"MIT"
] | 1 | 2017-07-14T11:28:45.000Z | 2017-07-14T11:28:45.000Z | include/thread.h | Spiikesan/C-modulaire | 43e83d17d3e0141391942ba4736feb62f1699a43 | [
"MIT"
] | null | null | null | include/thread.h | Spiikesan/C-modulaire | 43e83d17d3e0141391942ba4736feb62f1699a43 | [
"MIT"
] | null | null | null | #ifndef THREAD_H_
# define THREAD_H_
# ifdef __linux__
# include <pthread.h>
typedef pthread_t t_cthread;
typedef void *t_cth_ret;
typedef void *t_cth_params;
# elif _WIN32
# include <windows.h>
typedef struct s_cthread
{
DWORD thread_id;
HANDLE handle;
} t_cthread;
typedef DWORD t_cth_ret;
typedef LPVOID t_cth_params;
# endif
typedef t_cth_ret (*t_thread_routine)(t_cth_params);
# include "object.h"
# define t_thread_DEFINITION \
t_thread, \
(t_thread_routine, routine),\
(t_cth_params, params), \
(t_cth_ret, ret), \
(t_cthread, thread) \
CMETA_STRUCT_DEF(t_thread_DEFINITION);
#endif /* !THREAD_H_ */
| 16.461538 | 52 | 0.728972 |
2ebc624a92a348e440f5b8d8ea9b6bfd7032eae4 | 2,210 | h | C | Fujitsu/benchmarks/resnet/implementations/mxnet/3rdparty/tvm/3rdparty/HalideIR/src/ir/Range.h | mengkai94/training_results_v0.6 | 43dc3e250f8da47b5f8833197d74cb8cf1004fc9 | [
"Apache-2.0"
] | 193 | 2017-08-18T03:17:02.000Z | 2022-02-09T07:00:45.000Z | Fujitsu/benchmarks/resnet/implementations/mxnet/3rdparty/tvm/3rdparty/HalideIR/src/ir/Range.h | mengkai94/training_results_v0.6 | 43dc3e250f8da47b5f8833197d74cb8cf1004fc9 | [
"Apache-2.0"
] | 23 | 2019-07-29T05:21:52.000Z | 2020-08-31T18:51:42.000Z | Fujitsu/benchmarks/resnet/implementations/mxnet/3rdparty/tvm/3rdparty/HalideIR/src/ir/Range.h | mengkai94/training_results_v0.6 | 43dc3e250f8da47b5f8833197d74cb8cf1004fc9 | [
"Apache-2.0"
] | 58 | 2017-10-09T20:18:58.000Z | 2022-02-23T05:40:47.000Z | /*!
* Copyright (c) 2016 by Contributors
* \file Range.h
* \brief The Range data structure
*/
#ifndef HALIDEIR_IR_RANGE_H_
#define HALIDEIR_IR_RANGE_H_
#include <memory>
#include "Expr.h"
namespace HalideIR {
namespace IR {
// Internal node container of Range
class RangeNode;
/*! \brief Node range */
class Range : public NodeRef {
public:
/*! \brief constructor */
Range() {}
Range(NodePtr<Node> n) : NodeRef(n) {}
/*!
* \brief access the internal node container
* \return the pointer to the internal node container
*/
inline const RangeNode* operator->() const;
/*! \brief specify container node */
using ContainerType = RangeNode;
/*!
* \brief construct a new range with min and extent
* The corresponding constructor is removed,
* because that is counter convention of tradition meaning
* of range(begin, end)
*
* \param min The minimum range.
* \param extent The extent of the range.
*/
static inline Range make_by_min_extent(Expr min, Expr extent);
};
/*! \brief range over one dimension */
class RangeNode : public Node {
public:
/*! \brief beginning of the node */
Expr min;
/*! \brief the extend of range */
Expr extent;
/*! \brief constructor */
RangeNode() {}
RangeNode(Expr min, Expr extent) : min(min), extent(extent) {}
void VisitAttrs(IR::AttrVisitor* v) final {
v->Visit("min", &min);
v->Visit("extent", &extent);
}
static constexpr const char* _type_key = "Range";
TVM_DECLARE_NODE_TYPE_INFO(RangeNode, Node);
};
// implements of inline functions
inline const RangeNode* Range::operator->() const {
return static_cast<const RangeNode*>(node_.get());
}
inline Range Range::make_by_min_extent(Expr min, Expr extent) {
internal_assert(min.type() == extent.type())
<< "Region min and extent must have same type\n";
NodePtr<RangeNode> n = make_node<RangeNode>();
n->min = min;
n->extent = extent;
return Range(n);
}
// overload print function
inline std::ostream& operator<<(std::ostream &os, const Range& r) { // NOLINT(*)
os << "Range(min=" << r->min << ", extent=" << r->extent <<')';
return os;
}
} // namespace IR
} // namespace HalideIR
#endif // HALIDEIR_IR_H_
| 25.402299 | 81 | 0.667873 |
2c2a09cf98712bb0bc5889688f2c6bce50444a3a | 4,907 | c | C | pkgs/libs/glib/src/gobject/gatomicarray.c | manggoguy/parsec-modified | d14edfb62795805c84a4280d67b50cca175b95af | [
"BSD-3-Clause"
] | 64 | 2015-03-06T00:30:56.000Z | 2022-03-24T13:26:53.000Z | pkgs/libs/glib/src/gobject/gatomicarray.c | manggoguy/parsec-modified | d14edfb62795805c84a4280d67b50cca175b95af | [
"BSD-3-Clause"
] | 12 | 2020-12-15T08:30:19.000Z | 2022-03-13T03:54:24.000Z | pkgs/libs/glib/src/gobject/gatomicarray.c | manggoguy/parsec-modified | d14edfb62795805c84a4280d67b50cca175b95af | [
"BSD-3-Clause"
] | 46 | 2018-10-29T06:56:03.000Z | 2022-02-18T07:07:17.000Z | /* GObject - GLib Type, Object, Parameter and Signal Library
* Copyright (C) 2009 Benjamin Otte <otte@gnome.org>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General
* Public License along with this library; if not, write to the
* Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307, USA.
*/
#include "config.h"
#include "gatomicarray.h"
#include <string.h>
/* A GAtomicArray is a growable, mutable array of data
* generally of the form of a header of a specific size and
* then a array of items of a fixed size.
*
* It is possible to do lock-less read transactions from the
* array without any protection against other reads or writes,
* but such read operation must be aware that the data in the
* atomic array can change at any time during the transaction,
* and only at the end can we verify if the transaction succeeded
* or not. Thus the reading transaction cannot for instance
* dereference a pointer in the array inside the transaction.
*
* The size of an array however cannot change during a read
* transaction.
*
* Writes to the array is done in a copy-update style, but there
* is no real protection against multiple writers overwriting each
* others updates, so writes must be protected by an external lock.
*/
G_LOCK_DEFINE_STATIC (array);
typedef struct _FreeListNode FreeListNode;
struct _FreeListNode {
FreeListNode *next;
};
/* This is really a list of array memory blocks, using the
* first item as the next pointer to chain them together.
* Protected by array lock */
static FreeListNode *freelist = NULL;
/* must hold array lock */
static gpointer
freelist_alloc (gsize size, gboolean reuse)
{
gpointer mem;
FreeListNode *free, **prev;
gsize real_size;
if (reuse)
{
for (free = freelist, prev = &freelist; free != NULL; prev = &free->next, free = free->next)
{
if (G_ATOMIC_ARRAY_DATA_SIZE (free) == size)
{
*prev = free->next;
return (gpointer)free;
}
}
}
real_size = sizeof (gsize) + MAX (size, sizeof (FreeListNode));
mem = g_slice_alloc (real_size);
mem = ((char *) mem) + sizeof (gsize);
G_ATOMIC_ARRAY_DATA_SIZE (mem) = size;
return mem;
}
/* must hold array lock */
static void
freelist_free (gpointer mem)
{
FreeListNode *free;
free = mem;
free->next = freelist;
freelist = free;
}
void
_g_atomic_array_init (GAtomicArray *array)
{
array->data = NULL;
}
/* Get a copy of the data (if non-NULL) that
* can be changed and then re-applied with
* g_atomic_array_update().
*
* If additional_element_size is > 0 then
* then the new memory chunk is that much
* larger, or there were no data we return
* a chunk of header_size + additional_element_size.
* This means you can use this to grow the
* array part and it handles the first element
* being added automatically.
*/
gpointer
_g_atomic_array_copy (GAtomicArray *array,
gsize header_size,
gsize additional_element_size)
{
guint8 *new, *old;
gsize old_size, new_size;
/* We don't support shrinking arrays, as if
we then re-grow we may reuse an old pointer
value and confuse the transaction check. */
g_assert (additional_element_size >= 0);
G_LOCK (array);
old = g_atomic_pointer_get (&array->data);
if (old)
{
old_size = G_ATOMIC_ARRAY_DATA_SIZE (old);
new_size = old_size + additional_element_size;
/* Don't reuse if copying to same size, as this may end
up reusing the same pointer for the same array thus
confusing the transaction check */
new = freelist_alloc (new_size, additional_element_size != 0);
memcpy (new, old, old_size);
}
else if (additional_element_size != 0)
{
new_size = header_size + additional_element_size;
new = freelist_alloc (new_size, TRUE);
}
else
new = NULL;
G_UNLOCK (array);
return new;
}
/* Replace the data in the array with the new data,
* freeing the old data (for reuse). The new data may
* not be smaller than the current data.
*/
void
_g_atomic_array_update (GAtomicArray *array,
gpointer new_data)
{
guint8 *old;
G_LOCK (array);
old = g_atomic_pointer_get (&array->data);
g_assert (old == NULL || G_ATOMIC_ARRAY_DATA_SIZE (old) <= G_ATOMIC_ARRAY_DATA_SIZE (new_data));
g_atomic_pointer_set (&array->data, new_data);
if (old)
freelist_free (old);
G_UNLOCK (array);
}
| 28.864706 | 98 | 0.709395 |
2c3a4d28bc9e85ee3c05560a62447bbe86a00f4b | 16,602 | c | C | ffs/evol.c | GTkorvo/libffs | 25f9621a8a983f0e4e85a694290ab9624dd2c2bc | [
"BSD-3-Clause"
] | 190 | 2017-04-05T20:16:22.000Z | 2022-03-30T20:26:01.000Z | ffs/evol.c | GTkorvo/libffs | 25f9621a8a983f0e4e85a694290ab9624dd2c2bc | [
"BSD-3-Clause"
] | 1,514 | 2017-02-03T16:19:17.000Z | 2022-03-29T16:36:48.000Z | ffs/evol.c | GTkorvo/libffs | 25f9621a8a983f0e4e85a694290ab9624dd2c2bc | [
"BSD-3-Clause"
] | 114 | 2016-12-06T16:47:45.000Z | 2022-02-01T19:56:01.000Z | #include "config.h"
#include <stdio.h>
#include <string.h>
#include <assert.h>
#ifdef HAVE_UNISTD_H
#include <unistd.h>
#endif
#include <stdlib.h>
#include <ffs.h>
#include "fm_internal.h"
#include "ffs_internal.h"
#define MAX_DIFF 0xFFFF
#define COMPAT_THRESH 0.8
static FMStructDescList
build_struct_list(FMFormat format)
{
FMStructDescList ret;
int count = 0;
while (format->subformats[count] != NULL) count++;
count+=2;
ret = malloc(count * sizeof(ret[0]));
ret[0].format_name = format->format_name;
ret[0].field_list = format->field_list;
ret[0].struct_size = format->record_length;
ret[0].opt_info = NULL;
count = 0;
while(format->subformats[count] != NULL) {
FMFormat subformat = format->subformats[count];
ret[count+1].format_name = subformat->format_name;
ret[count+1].field_list = subformat->field_list;
ret[count+1].struct_size = subformat->record_length;
ret[count+1].opt_info = NULL;
count++;
}
ret[count+1].format_name = NULL;
ret[count+1].field_list = NULL;
ret[count+1].struct_size = 0;
ret[count+1].opt_info = NULL;
return ret;
}
extern int
FMformat_compat_cmp(FMFormat format, FMFormat *formatList,
int listSize, FMcompat_formats * older_format);
extern void
FFS_determine_conversion(FFSContext c, FFSTypeHandle format)
{
int i;
FMStructDescList struct_list;
int nearest_format = -1, j;
FMcompat_formats older_format = NULL;
FMFormat *formatList;
formatList =
(FMFormat *) malloc(c->handle_list_size * sizeof(FMFormat));
j = 0;
for (i = 0; i < c->handle_list_size; i++) {
if (c->handle_list[i] && c->handle_list[i]->is_fixed_target)
formatList[j++] = c->handle_list[i]->body;
}
nearest_format = FMformat_compat_cmp(format->body, formatList,
j, &older_format);
if (nearest_format == -1) {
free(formatList);
format->status = none_available;
return;
}
struct_list = build_struct_list(formatList[nearest_format]);
establish_conversion(c, format, struct_list);
format->conversion_target = FFSTypeHandle_by_index(c, formatList[nearest_format]->format_index);
format->status = conversion_set;
free(formatList);
free(struct_list);
return;
}
static int
IO_field_type_eq(str1, str2)
const char *str1;
const char *str2;
{
FMdata_type t1, t2;
long t1_count, t2_count;
t1 = FMarray_str_to_data_type(str1, &t1_count);
t2 = FMarray_str_to_data_type(str2, &t2_count);
if ((t1_count == -1) && (t2_count == -1)) {
/* variant array */
char *tmp_str1 = base_data_type(str1);
char *tmp_str2 = base_data_type(str2);
char *colon1 = strchr(tmp_str1, ':');
char *colon2 = strchr(tmp_str2, ':');
char *lparen1 = strchr(str1, '[');
char *lparen2 = strchr(str2, '[');
int count1 = 0;
int count2 = 0;
if (colon1 != NULL) {
count1 = colon1 - tmp_str1;
} else {
count1 = strlen(tmp_str1);
}
if (colon2 != NULL) {
count2 = colon2 - tmp_str2;
} else {
count2 = strlen(tmp_str2);
}
/*compare base type */
if (strncmp(tmp_str1, tmp_str2,(count1>count2)?count1:count2) != 0) {
/* base types differ */
return 0;
}
free(tmp_str1);
free(tmp_str2);
if ((lparen1 == NULL) || (lparen2 == NULL)) return -1;
return (strcmp(lparen1, lparen2) == 0);
}
return ((t1 == t2) && (t1_count == t2_count));
}
/*
* Compares the two formats.
* Returns FFSformat_order
* */
static FMformat_order
FMformat_cmp_diff(format1, format2, diff1, diff2)
FMFormat format1;
FMFormat format2;
int *diff1; /* Number of fields present in format1 and
* not in format2 */
int *diff2; /* Number of fields present in format2 and
* not in format1 */
{
FMformat_order tmp_result = Format_Equal;
FMFieldList orig_field_list1 = format1->field_list;
FMFieldList orig_field_list2 = format2->field_list;
FMFieldList field_list1, field_list2;
FMFormat *subformats1 = NULL, *subformats2 = NULL;
int field_count1, field_count2;
int i, j, limit;
if (format1 == format2) return Format_Equal;
/* count fields */
for (field_count1 = 0; orig_field_list1[field_count1].field_name != NULL;
field_count1++);
/* count fields */
for (field_count2 = 0; orig_field_list2[field_count2].field_name != NULL;
field_count2++);
field_list1 = malloc(sizeof(field_list1[0]) * (field_count1 + 1));
field_list2 = malloc(sizeof(field_list2[0]) * (field_count2 + 1));
memcpy(field_list1, orig_field_list1,
sizeof(field_list1[0]) * (field_count1 + 1));
memcpy(field_list2, orig_field_list2,
sizeof(field_list2[0]) * (field_count2 + 1));
qsort(field_list1, field_count1, sizeof(FMField), field_name_compar);
qsort(field_list2, field_count2, sizeof(FMField), field_name_compar);
limit = field_count1;
if (field_count2 < limit)
limit = field_count2;
i = j = 0;
while ((i < field_count1) && (j < field_count2)) {
int name_cmp;
if ((name_cmp = strcmp(field_list1[i].field_name,
field_list2[j].field_name)) == 0) {
/* fields have same name */
if (!IO_field_type_eq(field_list1[i].field_type,
field_list2[j].field_type)) {
(*diff1)++;
(*diff2)++;
}
i++;
j++;
} else if (name_cmp < 0) {
/* name_cmp<0 a field in field_list1 that doesn't appear in 2 */
(*diff1)++;
i++;
} else {
(*diff2)++;
j++;
}
}
(*diff1) += (field_count1 - i);
(*diff2) += (field_count2 - j);
/* go through subformats */
subformats1 = format1->subformats;
subformats2 = format2->subformats;
/* TODO: Fix for unmatched subformats
* -sandip */
while (subformats1 && (*subformats1 != NULL)) {
char *sub1_name = name_of_FMformat(*subformats1);
int i = 0;
if (*subformats1 == format1) {
/* self appears in subformat list, skip it */
subformats1++;
continue;
}
while (subformats2 && (subformats2[i] != NULL)) {
if (strcmp(sub1_name, name_of_FMformat(subformats2[i])) == 0) {
/* same name, compare */
FMformat_cmp_diff(*subformats1, subformats2[i], diff1,
diff2);
break;
}
i++;
}
subformats1++;
}
free(field_list1);
free(field_list2);
if (*diff1 == 0) {
if (*diff2 == 0)
tmp_result = Format_Equal;
else
tmp_result = Format_Less;
} else {
if (*diff2 == 0)
tmp_result = Format_Greater;
else
tmp_result = Format_Incompatible;
}
return tmp_result;
}
/*
* Basically counts the total number of nodes in a data structure tree
* */
static int
count_total_IOfield(FMFormat format)
{
int count = 0;
if (format) {
int i;
count = format->field_count;
for (i = 0; i < format->field_count; i++)
if (format->field_subformats[i] != NULL)
count += count_total_IOfield(format->field_subformats[i]);
}
return count;
}
/*
* Implements a simple threshold-based technique to decide whether or not
* we should do conversion at all when the comparison result between best
* possible pair is Format_Incompatible
* The idea is to keep the number of missing fields below a certain threshold.
* There is scope of smarter algorithm here.
* */
static int
check_compat_thresh(FMFormat_Comp_result * comp_result, FMFormat format)
{
float curr_thresh;
int field_count = count_total_IOfield(format);
curr_thresh = (float) comp_result->diff2 / (float) field_count;
return (curr_thresh < (1.0 - COMPAT_THRESH));
}
/*
* Try to find a format in 'formatList' which best matches the 'format'
* Returns the index of best match found or
* -1 if no better comparison (as specified by comp_result) found.
* comp_result is modified accordingly to indicate the current match purity
* */
static int
IOformat_list_cmp(FMFormat format, FMFormat *formatList, int listSize,
FMFormat_Comp_result * comp_result)
{
int i, diff1, diff2, nearest_format = -1;
FMformat_order result = Format_Incompatible;
for (i = 0; i < listSize; i++) {
int order;
if (formatList[i] == NULL)
continue;
order =
strcmp(name_of_FMformat(format),
name_of_FMformat(formatList[i]));
if (order != 0) continue;
diff1 = diff2 = 0;
result = FMformat_cmp_diff(format, formatList[i], &diff1, &diff2);
if (result == Format_Equal) {
comp_result->diff1 = comp_result->diff2 = 0;
nearest_format = i;
break;
}
if ((diff2 < comp_result->diff2) ||
(diff2 == comp_result->diff2 && diff1 < comp_result->diff1)) {
comp_result->diff1 = diff1;
comp_result->diff2 = diff2;
nearest_format = i;
}
}
return nearest_format;
}
static int
IOformat_list_cmp2(FMFormat format, FMFormat *formatList, int listSize,
FMFormat_Comp_result * comp_result)
{
int i, diff1, diff2, nearest_format = -1;
FMformat_order result = Format_Incompatible;
for (i = 0; i < listSize; i++) {
if (formatList[i] == NULL)
continue;
diff1 = diff2 = 0;
result = FMformat_cmp_diff(format, formatList[i], &diff1, &diff2);
if (result == Format_Equal) {
comp_result->diff1 = comp_result->diff2 = 0;
nearest_format = i;
break;
}
if ((diff2 < comp_result->diff2) ||
(diff2 == comp_result->diff2 && diff1 < comp_result->diff1)) {
comp_result->diff1 = diff1;
comp_result->diff2 = diff2;
nearest_format = i;
}
}
return nearest_format;
}
/*
* First check whether 'format' matches exactly with any of 'formatList'
* If exact match not found, try to match with compatible formats (formats
* that 'format' can be translated to)
* Returns the index of best match found or
* -1 if no better comparison (as specified by comp_result) found.
* */
extern int
FMformat_compat_cmp(FMFormat format, FMFormat *formatList,
int listSize, FMcompat_formats * older_format)
{
FMFormat prior_format;
int i = 0, nearest_format = -1;
FMcompat_formats compats;
FMFormat_Comp_result comp_result = { MAX_DIFF, MAX_DIFF };
*older_format = NULL;
nearest_format =
IOformat_list_cmp(format, formatList, listSize, &comp_result);
if (nearest_format != -1 && !comp_result.diff1 && !comp_result.diff2)
return nearest_format;
compats = FMget_compat_formats(format);
if (compats == NULL)
return -1;
while ((prior_format = compats[i].prior_format)) {
int tmp = IOformat_list_cmp(prior_format, formatList, listSize,
&comp_result);
if (tmp != -1) {
nearest_format = tmp;
*older_format = &compats[i];
}
if (comp_result.diff1 == 0 && comp_result.diff2 == 0)
break;
i++;
}
if (nearest_format != -1 &&
!check_compat_thresh(&comp_result, formatList[nearest_format])){
nearest_format = -1;
*older_format = NULL;
}
return nearest_format;
}
/*
* First check whether 'format' matches exactly with any of 'formatList'
* If exact match not found, try to match with compatible formats (formats
* that 'format' can be translated to)
* Returns the index of best match found or
* -1 if no better comparison (as specified by comp_result) found.
* */
extern int
FMformat_compat_cmp2(FMFormat format, FMFormat *formatList,
int listSize, FMcompat_formats * older_format)
{
FMFormat prior_format;
int i = 0, nearest_format = -1;
FMcompat_formats compats;
FMFormat_Comp_result saved_comp_result = { MAX_DIFF, MAX_DIFF };
*older_format = NULL;
nearest_format =
IOformat_list_cmp2(format, formatList, listSize, &saved_comp_result);
if (nearest_format != -1 && !saved_comp_result.diff1 &&
!saved_comp_result.diff2) {
/* exact match */
return nearest_format;
}
compats = FMget_compat_formats(format);
if (compats == NULL) {
if (!saved_comp_result.diff2) {
return nearest_format;
}
return -1;
}
while ((prior_format = compats[i].prior_format)) {
FMFormat_Comp_result comp_result={MAX_DIFF, MAX_DIFF};
int tmp = IOformat_list_cmp2(prior_format, formatList, listSize,
&comp_result);
if (tmp != -1) {
if (saved_comp_result.diff1 > comp_result.diff1) {
nearest_format = tmp;
*older_format = &compats[i];
saved_comp_result = comp_result;
}
}
if (comp_result.diff1 == 0 && comp_result.diff2 == 0)
break;
i++;
}
if (nearest_format != -1 &&
!check_compat_thresh(&saved_comp_result, formatList[nearest_format])){
nearest_format = -1;
*older_format = NULL;
}
return nearest_format;
}
extern void *
FFScreate_compat_info(prior_format, xform_code, len_p)
FMFormat prior_format;
char *xform_code;
int *len_p;
{
char *block;
int block_len = strlen(xform_code) + prior_format->server_ID.length +1;
block = malloc(block_len);
memcpy(block, prior_format->server_ID.value,
prior_format->server_ID.length);
memcpy(block + prior_format->server_ID.length,
xform_code, block_len - prior_format->server_ID.length);
*len_p = block_len;
return block;
}
#ifdef NOT_DEF
/**
* Localize the "format" and set the conversion context to convert the wire
* format to this localized format.
* Return the localized format list
*/
extern FMFormatList
IOlocalize_conv(FFSContext context, FMFormat format)
{
FMFormatList local_format_list = NULL;
FMFormat *wire_subformats = format->subformats;
int i = 0;
while (wire_subformats[i] != NULL) {
int local_struct_size;
FMFieldList wire_field_list = wire_subformats[i]->field_list;
FMFieldList local_field_list = copy_field_list(wire_field_list);
/*
* determine an appropriate native layout for this structure
* and set the conversion
*/
local_field_list = localize_field_list(local_field_list, context);
local_struct_size =
struct_size_field_list(local_field_list, sizeof(char *));
set_conversion_IOcontext(context, wire_subformats[i],
local_field_list, local_struct_size);
local_format_list =
realloc(local_format_list,
sizeof(local_format_list[0]) * (i + 2));
local_format_list[i].format_name =
strdup(name_of_FMformat(wire_subformats[i]));
local_format_list[i].field_list = local_field_list;
i++;
}
local_format_list[i].format_name = NULL;
free(wire_subformats);
return local_format_list;
}
/**
* Localize the "format".
* Register this localized format to the "context".
* Set the conversion context to convert this localized format to native
* format as specified by native_field_list and native_subformat_list.
* Return the localized format list.
*/
extern FMFormatList
IOlocalize_register_conv(FMContext context, FMFormat format,
FMFieldList native_field_list,
FMFormatList native_subformat_list,
FMFormat *local_prior_format,
int *local_struct_size_out)
{
FMFormatList local_f1_formats = NULL;
FMFormat *wire_subformats = format->subformats;
int i = 0, native_struct_size;
native_struct_size = struct_size_field_list(native_field_list,
sizeof(char *));
#ifdef NOTDEF
while (wire_subformats[i] != NULL) {
int local_struct_size;
FMFieldList wire_field_list =
field_list_of_IOformat(wire_subformats[i]);
FMFieldList local_field_list = copy_field_list(wire_field_list);
char *subformat_name = name_of_IOformat(wire_subformats[i]);
int j = 0;
/*
* determine an appropriate native layout for this structure
* and set the conversion
*/
local_field_list = localize_field_list(local_field_list, context);
local_struct_size =
struct_size_field_list(local_field_list, sizeof(char *));
/* We don't need the subformats. The last one will be the top
* level FMFormat */
*local_prior_format =
register_IOcontext_format(subformat_name, local_field_list,
context);
while (native_subformat_list
&& (native_subformat_list[j].format_name != NULL)) {
if (strcmp
(native_subformat_list[j].format_name,
subformat_name) == 0) {
FMFieldList sub_field_list;
int sub_struct_size;
sub_field_list = native_subformat_list[j].field_list;
sub_struct_size = struct_size_field_list(sub_field_list,
sizeof(char *));
set_conversion_IOcontext(context,
*local_prior_format,
sub_field_list, sub_struct_size);
break;
}
j++;
}
local_f1_formats = realloc(local_f1_formats,
sizeof(local_f1_formats[0]) * (i + 2));
local_f1_formats[i].format_name =
strdup(name_of_IOformat(wire_subformats[i]));
local_f1_formats[i].field_list = local_field_list;
if (wire_subformats[i + 1] == NULL) {
/* last one */
*local_struct_size_out = local_struct_size;
local_f1_formats[i + 1].format_name = NULL;
}
i++;
}
#endif
set_conversion_IOcontext(context, *local_prior_format,
native_field_list, native_struct_size);
free(wire_subformats);
return local_f1_formats;
}
#endif
| 28.574871 | 100 | 0.68817 |
c81de5e161824ed4dfc96a717c59c6e6b1efc8a3 | 514 | h | C | VulkanTrial/VulkanTrial/VulkanUtils/VulkanDescriptorSetLayout.h | PlateArmourProgrammer/VulkanLitter | 258f0088f9a35426e4b86f73e401c4a6b5dfb5a4 | [
"MIT"
] | 2 | 2018-03-26T14:44:07.000Z | 2018-08-03T07:29:08.000Z | VulkanTrial/VulkanTrial/VulkanUtils/VulkanDescriptorSetLayout.h | PlateArmourProgrammer/VulkanLitter | 258f0088f9a35426e4b86f73e401c4a6b5dfb5a4 | [
"MIT"
] | null | null | null | VulkanTrial/VulkanTrial/VulkanUtils/VulkanDescriptorSetLayout.h | PlateArmourProgrammer/VulkanLitter | 258f0088f9a35426e4b86f73e401c4a6b5dfb5a4 | [
"MIT"
] | null | null | null | #ifndef VulkanDescriptorSetLayout_h_
#define VulkanDescriptorSetLayout_h_
#include "Base/BaseObject.h"
#include "VulkanHeader.h"
namespace litter {
class VulkanLogicalDevice;
class VulkanDescriptorSetLayout : public BaseObject {
public:
VulkanDescriptorSetLayout(VulkanLogicalDevice* logicalDevice);
~VulkanDescriptorSetLayout();
vk::DescriptorSetLayout* getObject();
private:
vk::DescriptorSetLayout _layout;
VulkanLogicalDevice* _logicalDevice;
};
}
#endif // !VulkanDescriptorSetLayout_h_
| 20.56 | 64 | 0.805447 |
c8a150ee0ddcb7b94e9dc5f1bdca8f4c37985502 | 27,120 | c | C | usbfuzz-afl/qemu_mode/qemu/hw/usb/desc.c | HexHive/USBFuzz | be465af1db0d62310f8311ab7a3a6179659a51de | [
"Apache-2.0"
] | 60 | 2020-10-14T07:11:48.000Z | 2022-02-14T23:00:51.000Z | usbfuzz-afl/qemu_mode/qemu/hw/usb/desc.c | HexHive/USBFuzz | be465af1db0d62310f8311ab7a3a6179659a51de | [
"Apache-2.0"
] | 8 | 2020-10-19T02:17:19.000Z | 2022-01-15T05:52:46.000Z | usbfuzz-afl/qemu_mode/qemu/hw/usb/desc.c | HexHive/USBFuzz | be465af1db0d62310f8311ab7a3a6179659a51de | [
"Apache-2.0"
] | 17 | 2020-10-14T07:13:47.000Z | 2022-03-31T03:40:44.000Z | #include "qemu/osdep.h"
#include "hw/usb.h"
#include "hw/usb/desc.h"
#include "trace.h"
/* ------------------------------------------------------------------ */
int usb_desc_device(const USBDescID *id, const USBDescDevice *dev,
bool msos, uint8_t *dest, size_t len)
{
uint8_t bLength = 0x12;
USBDescriptor *d = (void *)dest;
if (len < bLength) {
return -1;
}
d->bLength = bLength;
d->bDescriptorType = USB_DT_DEVICE;
if (msos && dev->bcdUSB < 0x0200) {
/*
* Version 2.0+ required for microsoft os descriptors to work.
* Done this way so msos-desc compat property will handle both
* the version and the new descriptors being present.
*/
d->u.device.bcdUSB_lo = usb_lo(0x0200);
d->u.device.bcdUSB_hi = usb_hi(0x0200);
} else {
d->u.device.bcdUSB_lo = usb_lo(dev->bcdUSB);
d->u.device.bcdUSB_hi = usb_hi(dev->bcdUSB);
}
d->u.device.bDeviceClass = dev->bDeviceClass;
d->u.device.bDeviceSubClass = dev->bDeviceSubClass;
d->u.device.bDeviceProtocol = dev->bDeviceProtocol;
d->u.device.bMaxPacketSize0 = dev->bMaxPacketSize0;
d->u.device.idVendor_lo = usb_lo(id->idVendor);
d->u.device.idVendor_hi = usb_hi(id->idVendor);
d->u.device.idProduct_lo = usb_lo(id->idProduct);
d->u.device.idProduct_hi = usb_hi(id->idProduct);
d->u.device.bcdDevice_lo = usb_lo(id->bcdDevice);
d->u.device.bcdDevice_hi = usb_hi(id->bcdDevice);
d->u.device.iManufacturer = id->iManufacturer;
d->u.device.iProduct = id->iProduct;
d->u.device.iSerialNumber = id->iSerialNumber;
d->u.device.bNumConfigurations = dev->bNumConfigurations;
return bLength;
}
int usb_desc_device_qualifier(const USBDescDevice *dev,
uint8_t *dest, size_t len)
{
uint8_t bLength = 0x0a;
USBDescriptor *d = (void *)dest;
if (len < bLength) {
return -1;
}
d->bLength = bLength;
d->bDescriptorType = USB_DT_DEVICE_QUALIFIER;
d->u.device_qualifier.bcdUSB_lo = usb_lo(dev->bcdUSB);
d->u.device_qualifier.bcdUSB_hi = usb_hi(dev->bcdUSB);
d->u.device_qualifier.bDeviceClass = dev->bDeviceClass;
d->u.device_qualifier.bDeviceSubClass = dev->bDeviceSubClass;
d->u.device_qualifier.bDeviceProtocol = dev->bDeviceProtocol;
d->u.device_qualifier.bMaxPacketSize0 = dev->bMaxPacketSize0;
d->u.device_qualifier.bNumConfigurations = dev->bNumConfigurations;
d->u.device_qualifier.bReserved = 0;
return bLength;
}
int usb_desc_config(const USBDescConfig *conf, int flags,
uint8_t *dest, size_t len)
{
uint8_t bLength = 0x09;
uint16_t wTotalLength = 0;
USBDescriptor *d = (void *)dest;
int i, rc;
if (len < bLength) {
return -1;
}
d->bLength = bLength;
d->bDescriptorType = USB_DT_CONFIG;
d->u.config.bNumInterfaces = conf->bNumInterfaces;
d->u.config.bConfigurationValue = conf->bConfigurationValue;
d->u.config.iConfiguration = conf->iConfiguration;
d->u.config.bmAttributes = conf->bmAttributes;
d->u.config.bMaxPower = conf->bMaxPower;
wTotalLength += bLength;
/* handle grouped interfaces if any */
for (i = 0; i < conf->nif_groups; i++) {
rc = usb_desc_iface_group(&(conf->if_groups[i]), flags,
dest + wTotalLength,
len - wTotalLength);
if (rc < 0) {
return rc;
}
wTotalLength += rc;
}
/* handle normal (ungrouped / no IAD) interfaces if any */
for (i = 0; i < conf->nif; i++) {
rc = usb_desc_iface(conf->ifs + i, flags,
dest + wTotalLength, len - wTotalLength);
if (rc < 0) {
return rc;
}
wTotalLength += rc;
}
d->u.config.wTotalLength_lo = usb_lo(wTotalLength);
d->u.config.wTotalLength_hi = usb_hi(wTotalLength);
return wTotalLength;
}
int usb_desc_iface_group(const USBDescIfaceAssoc *iad, int flags,
uint8_t *dest, size_t len)
{
int pos = 0;
int i = 0;
/* handle interface association descriptor */
uint8_t bLength = 0x08;
if (len < bLength) {
return -1;
}
dest[0x00] = bLength;
dest[0x01] = USB_DT_INTERFACE_ASSOC;
dest[0x02] = iad->bFirstInterface;
dest[0x03] = iad->bInterfaceCount;
dest[0x04] = iad->bFunctionClass;
dest[0x05] = iad->bFunctionSubClass;
dest[0x06] = iad->bFunctionProtocol;
dest[0x07] = iad->iFunction;
pos += bLength;
/* handle associated interfaces in this group */
for (i = 0; i < iad->nif; i++) {
int rc = usb_desc_iface(&(iad->ifs[i]), flags, dest + pos, len - pos);
if (rc < 0) {
return rc;
}
pos += rc;
}
return pos;
}
int usb_desc_iface(const USBDescIface *iface, int flags,
uint8_t *dest, size_t len)
{
uint8_t bLength = 0x09;
int i, rc, pos = 0;
USBDescriptor *d = (void *)dest;
if (len < bLength) {
return -1;
}
d->bLength = bLength;
d->bDescriptorType = USB_DT_INTERFACE;
d->u.interface.bInterfaceNumber = iface->bInterfaceNumber;
d->u.interface.bAlternateSetting = iface->bAlternateSetting;
d->u.interface.bNumEndpoints = iface->bNumEndpoints;
d->u.interface.bInterfaceClass = iface->bInterfaceClass;
d->u.interface.bInterfaceSubClass = iface->bInterfaceSubClass;
d->u.interface.bInterfaceProtocol = iface->bInterfaceProtocol;
d->u.interface.iInterface = iface->iInterface;
pos += bLength;
for (i = 0; i < iface->ndesc; i++) {
rc = usb_desc_other(iface->descs + i, dest + pos, len - pos);
if (rc < 0) {
return rc;
}
pos += rc;
}
for (i = 0; i < iface->bNumEndpoints; i++) {
rc = usb_desc_endpoint(iface->eps + i, flags, dest + pos, len - pos);
if (rc < 0) {
return rc;
}
pos += rc;
}
return pos;
}
int usb_desc_endpoint(const USBDescEndpoint *ep, int flags,
uint8_t *dest, size_t len)
{
uint8_t bLength = ep->is_audio ? 0x09 : 0x07;
uint8_t extralen = ep->extra ? ep->extra[0] : 0;
uint8_t superlen = (flags & USB_DESC_FLAG_SUPER) ? 0x06 : 0;
USBDescriptor *d = (void *)dest;
if (len < bLength + extralen + superlen) {
return -1;
}
d->bLength = bLength;
d->bDescriptorType = USB_DT_ENDPOINT;
d->u.endpoint.bEndpointAddress = ep->bEndpointAddress;
d->u.endpoint.bmAttributes = ep->bmAttributes;
d->u.endpoint.wMaxPacketSize_lo = usb_lo(ep->wMaxPacketSize);
d->u.endpoint.wMaxPacketSize_hi = usb_hi(ep->wMaxPacketSize);
d->u.endpoint.bInterval = ep->bInterval;
if (ep->is_audio) {
d->u.endpoint.bRefresh = ep->bRefresh;
d->u.endpoint.bSynchAddress = ep->bSynchAddress;
}
if (superlen) {
USBDescriptor *d = (void *)(dest + bLength);
d->bLength = 0x06;
d->bDescriptorType = USB_DT_ENDPOINT_COMPANION;
d->u.super_endpoint.bMaxBurst = ep->bMaxBurst;
d->u.super_endpoint.bmAttributes = ep->bmAttributes_super;
d->u.super_endpoint.wBytesPerInterval_lo =
usb_lo(ep->wBytesPerInterval);
d->u.super_endpoint.wBytesPerInterval_hi =
usb_hi(ep->wBytesPerInterval);
}
if (ep->extra) {
memcpy(dest + bLength + superlen, ep->extra, extralen);
}
return bLength + extralen + superlen;
}
int usb_desc_other(const USBDescOther *desc, uint8_t *dest, size_t len)
{
int bLength = desc->length ? desc->length : desc->data[0];
if (len < bLength) {
return -1;
}
memcpy(dest, desc->data, bLength);
return bLength;
}
static int usb_desc_cap_usb2_ext(const USBDesc *desc, uint8_t *dest, size_t len)
{
uint8_t bLength = 0x07;
USBDescriptor *d = (void *)dest;
if (len < bLength) {
return -1;
}
d->bLength = bLength;
d->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
d->u.cap.bDevCapabilityType = USB_DEV_CAP_USB2_EXT;
d->u.cap.u.usb2_ext.bmAttributes_1 = (1 << 1); /* LPM */
d->u.cap.u.usb2_ext.bmAttributes_2 = 0;
d->u.cap.u.usb2_ext.bmAttributes_3 = 0;
d->u.cap.u.usb2_ext.bmAttributes_4 = 0;
return bLength;
}
static int usb_desc_cap_super(const USBDesc *desc, uint8_t *dest, size_t len)
{
uint8_t bLength = 0x0a;
USBDescriptor *d = (void *)dest;
if (len < bLength) {
return -1;
}
d->bLength = bLength;
d->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
d->u.cap.bDevCapabilityType = USB_DEV_CAP_SUPERSPEED;
d->u.cap.u.super.bmAttributes = 0;
d->u.cap.u.super.wSpeedsSupported_lo = 0;
d->u.cap.u.super.wSpeedsSupported_hi = 0;
d->u.cap.u.super.bFunctionalitySupport = 0;
d->u.cap.u.super.bU1DevExitLat = 0x0a;
d->u.cap.u.super.wU2DevExitLat_lo = 0x20;
d->u.cap.u.super.wU2DevExitLat_hi = 0;
if (desc->full) {
d->u.cap.u.super.wSpeedsSupported_lo |= (1 << 1);
d->u.cap.u.super.bFunctionalitySupport = 1;
}
if (desc->high) {
d->u.cap.u.super.wSpeedsSupported_lo |= (1 << 2);
if (!d->u.cap.u.super.bFunctionalitySupport) {
d->u.cap.u.super.bFunctionalitySupport = 2;
}
}
if (desc->super) {
d->u.cap.u.super.wSpeedsSupported_lo |= (1 << 3);
if (!d->u.cap.u.super.bFunctionalitySupport) {
d->u.cap.u.super.bFunctionalitySupport = 3;
}
}
return bLength;
}
static int usb_desc_bos(const USBDesc *desc, uint8_t *dest, size_t len)
{
uint8_t bLength = 0x05;
uint16_t wTotalLength = 0;
uint8_t bNumDeviceCaps = 0;
USBDescriptor *d = (void *)dest;
int rc;
if (len < bLength) {
return -1;
}
d->bLength = bLength;
d->bDescriptorType = USB_DT_BOS;
wTotalLength += bLength;
if (desc->high != NULL) {
rc = usb_desc_cap_usb2_ext(desc, dest + wTotalLength,
len - wTotalLength);
if (rc < 0) {
return rc;
}
wTotalLength += rc;
bNumDeviceCaps++;
}
if (desc->super != NULL) {
rc = usb_desc_cap_super(desc, dest + wTotalLength,
len - wTotalLength);
if (rc < 0) {
return rc;
}
wTotalLength += rc;
bNumDeviceCaps++;
}
d->u.bos.wTotalLength_lo = usb_lo(wTotalLength);
d->u.bos.wTotalLength_hi = usb_hi(wTotalLength);
d->u.bos.bNumDeviceCaps = bNumDeviceCaps;
return wTotalLength;
}
/* ------------------------------------------------------------------ */
static void usb_desc_ep_init(USBDevice *dev)
{
const USBDescIface *iface;
int i, e, pid, ep;
usb_ep_init(dev);
for (i = 0; i < dev->ninterfaces; i++) {
iface = dev->ifaces[i];
if (iface == NULL) {
continue;
}
for (e = 0; e < iface->bNumEndpoints; e++) {
pid = (iface->eps[e].bEndpointAddress & USB_DIR_IN) ?
USB_TOKEN_IN : USB_TOKEN_OUT;
ep = iface->eps[e].bEndpointAddress & 0x0f;
usb_ep_set_type(dev, pid, ep, iface->eps[e].bmAttributes & 0x03);
usb_ep_set_ifnum(dev, pid, ep, iface->bInterfaceNumber);
usb_ep_set_max_packet_size(dev, pid, ep,
iface->eps[e].wMaxPacketSize);
usb_ep_set_max_streams(dev, pid, ep,
iface->eps[e].bmAttributes_super);
}
}
}
static const USBDescIface *usb_desc_find_interface(USBDevice *dev,
int nif, int alt)
{
const USBDescIface *iface;
int g, i;
if (!dev->config) {
return NULL;
}
for (g = 0; g < dev->config->nif_groups; g++) {
for (i = 0; i < dev->config->if_groups[g].nif; i++) {
iface = &dev->config->if_groups[g].ifs[i];
if (iface->bInterfaceNumber == nif &&
iface->bAlternateSetting == alt) {
return iface;
}
}
}
for (i = 0; i < dev->config->nif; i++) {
iface = &dev->config->ifs[i];
if (iface->bInterfaceNumber == nif &&
iface->bAlternateSetting == alt) {
return iface;
}
}
return NULL;
}
static int usb_desc_set_interface(USBDevice *dev, int index, int value)
{
const USBDescIface *iface;
int old;
iface = usb_desc_find_interface(dev, index, value);
if (iface == NULL) {
return -1;
}
old = dev->altsetting[index];
dev->altsetting[index] = value;
dev->ifaces[index] = iface;
usb_desc_ep_init(dev);
if (old != value) {
usb_device_set_interface(dev, index, old, value);
}
return 0;
}
static int usb_desc_set_config(USBDevice *dev, int value)
{
int i;
if (value == 0) {
dev->configuration = 0;
dev->ninterfaces = 0;
dev->config = NULL;
} else {
for (i = 0; i < dev->device->bNumConfigurations; i++) {
if (dev->device->confs[i].bConfigurationValue == value) {
dev->configuration = value;
dev->ninterfaces = dev->device->confs[i].bNumInterfaces;
dev->config = dev->device->confs + i;
assert(dev->ninterfaces <= USB_MAX_INTERFACES);
}
}
if (i < dev->device->bNumConfigurations) {
return -1;
}
}
for (i = 0; i < dev->ninterfaces; i++) {
usb_desc_set_interface(dev, i, 0);
}
for (; i < USB_MAX_INTERFACES; i++) {
dev->altsetting[i] = 0;
dev->ifaces[i] = NULL;
}
return 0;
}
static void usb_desc_setdefaults(USBDevice *dev)
{
const USBDesc *desc = usb_device_get_usb_desc(dev);
assert(desc != NULL);
switch (dev->speed) {
case USB_SPEED_LOW:
case USB_SPEED_FULL:
dev->device = desc->full;
break;
case USB_SPEED_HIGH:
dev->device = desc->high;
break;
case USB_SPEED_SUPER:
dev->device = desc->super;
break;
}
usb_desc_set_config(dev, 0);
}
void usb_desc_init(USBDevice *dev)
{
const USBDesc *desc = usb_device_get_usb_desc(dev);
assert(desc != NULL);
dev->speed = USB_SPEED_FULL;
dev->speedmask = 0;
if (desc->full) {
dev->speedmask |= USB_SPEED_MASK_FULL;
}
if (desc->high) {
dev->speedmask |= USB_SPEED_MASK_HIGH;
}
if (desc->super) {
dev->speedmask |= USB_SPEED_MASK_SUPER;
}
if (desc->msos && (dev->flags & (1 << USB_DEV_FLAG_MSOS_DESC_ENABLE))) {
dev->flags |= (1 << USB_DEV_FLAG_MSOS_DESC_IN_USE);
usb_desc_set_string(dev, 0xee, "MSFT100Q");
}
usb_desc_setdefaults(dev);
}
void usb_desc_attach(USBDevice *dev)
{
usb_desc_setdefaults(dev);
}
void usb_desc_set_string(USBDevice *dev, uint8_t index, const char *str)
{
USBDescString *s;
QLIST_FOREACH(s, &dev->strings, next) {
if (s->index == index) {
break;
}
}
if (s == NULL) {
s = g_malloc0(sizeof(*s));
s->index = index;
QLIST_INSERT_HEAD(&dev->strings, s, next);
}
g_free(s->str);
s->str = g_strdup(str);
}
/*
* This function creates a serial number for a usb device.
* The serial number should:
* (a) Be unique within the virtual machine.
* (b) Be constant, so you don't get a new one each
* time the guest is started.
* So we are using the physical location to generate a serial number
* from it. It has three pieces: First a fixed, device-specific
* prefix. Second the device path of the host controller (which is
* the pci address in most cases). Third the physical port path.
* Results in serial numbers like this: "314159-0000:00:1d.7-3".
*/
void usb_desc_create_serial(USBDevice *dev)
{
DeviceState *hcd = dev->qdev.parent_bus->parent;
const USBDesc *desc = usb_device_get_usb_desc(dev);
int index = desc->id.iSerialNumber;
char *path, *serial;
if (dev->serial) {
/* 'serial' usb bus property has priority if present */
usb_desc_set_string(dev, index, dev->serial);
return;
}
assert(index != 0 && desc->str[index] != NULL);
path = qdev_get_dev_path(hcd);
if (path) {
serial = g_strdup_printf("%s-%s-%s", desc->str[index],
path, dev->port->path);
} else {
serial = g_strdup_printf("%s-%s", desc->str[index], dev->port->path);
}
usb_desc_set_string(dev, index, serial);
g_free(path);
g_free(serial);
}
const char *usb_desc_get_string(USBDevice *dev, uint8_t index)
{
USBDescString *s;
QLIST_FOREACH(s, &dev->strings, next) {
if (s->index == index) {
return s->str;
}
}
return NULL;
}
int usb_desc_string(USBDevice *dev, int index, uint8_t *dest, size_t len)
{
uint8_t bLength, pos, i;
const char *str;
if (len < 4) {
return -1;
}
if (index == 0) {
/* language ids */
dest[0] = 4;
dest[1] = USB_DT_STRING;
dest[2] = 0x09;
dest[3] = 0x04;
return 4;
}
str = usb_desc_get_string(dev, index);
if (str == NULL) {
str = usb_device_get_usb_desc(dev)->str[index];
if (str == NULL) {
return 0;
}
}
bLength = strlen(str) * 2 + 2;
dest[0] = bLength;
dest[1] = USB_DT_STRING;
i = 0; pos = 2;
while (pos+1 < bLength && pos+1 < len) {
dest[pos++] = str[i++];
dest[pos++] = 0;
}
return pos;
}
int usb_desc_get_descriptor(USBDevice *dev, USBPacket *p,
int value, uint8_t *dest, size_t len)
{
bool msos = (dev->flags & (1 << USB_DEV_FLAG_MSOS_DESC_IN_USE));
const USBDesc *desc = usb_device_get_usb_desc(dev);
const USBDescDevice *other_dev;
uint8_t buf[256];
uint8_t type = value >> 8;
uint8_t index = value & 0xff;
int flags, ret = -1;
if (dev->speed == USB_SPEED_HIGH) {
other_dev = usb_device_get_usb_desc(dev)->full;
} else {
other_dev = usb_device_get_usb_desc(dev)->high;
}
flags = 0;
if (dev->device->bcdUSB >= 0x0300) {
flags |= USB_DESC_FLAG_SUPER;
}
switch(type) {
case USB_DT_DEVICE:
ret = usb_desc_device(&desc->id, dev->device, msos, buf, sizeof(buf));
trace_usb_desc_device(dev->addr, len, ret);
break;
case USB_DT_CONFIG:
if (index < dev->device->bNumConfigurations) {
ret = usb_desc_config(dev->device->confs + index, flags,
buf, sizeof(buf));
}
trace_usb_desc_config(dev->addr, index, len, ret);
break;
case USB_DT_STRING:
ret = usb_desc_string(dev, index, buf, sizeof(buf));
trace_usb_desc_string(dev->addr, index, len, ret);
break;
case USB_DT_DEVICE_QUALIFIER:
if (other_dev != NULL) {
ret = usb_desc_device_qualifier(other_dev, buf, sizeof(buf));
}
trace_usb_desc_device_qualifier(dev->addr, len, ret);
break;
case USB_DT_OTHER_SPEED_CONFIG:
if (other_dev != NULL && index < other_dev->bNumConfigurations) {
ret = usb_desc_config(other_dev->confs + index, flags,
buf, sizeof(buf));
buf[0x01] = USB_DT_OTHER_SPEED_CONFIG;
}
trace_usb_desc_other_speed_config(dev->addr, index, len, ret);
break;
case USB_DT_BOS:
ret = usb_desc_bos(desc, buf, sizeof(buf));
trace_usb_desc_bos(dev->addr, len, ret);
break;
case USB_DT_DEBUG:
/* ignore silently */
break;
default:
fprintf(stderr, "%s: %d unknown type %d (len %zd)\n", __FUNCTION__,
dev->addr, type, len);
break;
}
if (ret > 0) {
if (ret > len) {
ret = len;
}
memcpy(dest, buf, ret);
p->actual_length = ret;
ret = 0;
}
return ret;
}
int usb_desc_handle_control(USBDevice *dev, USBPacket *p,
int request, int value, int index, int length, uint8_t *data)
{
bool msos = (dev->flags & (1 << USB_DEV_FLAG_MSOS_DESC_IN_USE));
const USBDesc *desc = usb_device_get_usb_desc(dev);
int ret = -1;
assert(desc != NULL);
switch(request) {
case DeviceOutRequest | USB_REQ_SET_ADDRESS:
dev->addr = value;
trace_usb_set_addr(dev->addr);
ret = 0;
break;
case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
ret = usb_desc_get_descriptor(dev, p, value, data, length);
break;
case DeviceRequest | USB_REQ_GET_CONFIGURATION:
/*
* 9.4.2: 0 should be returned if the device is unconfigured, otherwise
* the non zero value of bConfigurationValue.
*/
data[0] = dev->config ? dev->config->bConfigurationValue : 0;
p->actual_length = 1;
ret = 0;
break;
case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
ret = usb_desc_set_config(dev, value);
trace_usb_set_config(dev->addr, value, ret);
break;
case DeviceRequest | USB_REQ_GET_STATUS: {
const USBDescConfig *config = dev->config ?
dev->config : &dev->device->confs[0];
data[0] = 0;
/*
* Default state: Device behavior when this request is received while
* the device is in the Default state is not specified.
* We return the same value that a configured device would return if
* it used the first configuration.
*/
if (config->bmAttributes & USB_CFG_ATT_SELFPOWER) {
data[0] |= 1 << USB_DEVICE_SELF_POWERED;
}
if (dev->remote_wakeup) {
data[0] |= 1 << USB_DEVICE_REMOTE_WAKEUP;
}
data[1] = 0x00;
p->actual_length = 2;
ret = 0;
break;
}
case DeviceOutRequest | USB_REQ_CLEAR_FEATURE:
if (value == USB_DEVICE_REMOTE_WAKEUP) {
dev->remote_wakeup = 0;
ret = 0;
}
trace_usb_clear_device_feature(dev->addr, value, ret);
break;
case DeviceOutRequest | USB_REQ_SET_FEATURE:
if (value == USB_DEVICE_REMOTE_WAKEUP) {
dev->remote_wakeup = 1;
ret = 0;
}
trace_usb_set_device_feature(dev->addr, value, ret);
break;
case DeviceOutRequest | USB_REQ_SET_SEL:
case DeviceOutRequest | USB_REQ_SET_ISOCH_DELAY:
if (dev->speed == USB_SPEED_SUPER) {
ret = 0;
}
break;
case InterfaceRequest | USB_REQ_GET_INTERFACE:
if (index < 0 || index >= dev->ninterfaces) {
break;
}
data[0] = dev->altsetting[index];
p->actual_length = 1;
ret = 0;
break;
case InterfaceOutRequest | USB_REQ_SET_INTERFACE:
ret = usb_desc_set_interface(dev, index, value);
trace_usb_set_interface(dev->addr, index, value, ret);
break;
case VendorDeviceRequest | 'Q':
if (msos) {
ret = usb_desc_msos(desc, p, index, data, length);
trace_usb_desc_msos(dev->addr, index, length, ret);
}
break;
case VendorInterfaceRequest | 'Q':
if (msos) {
ret = usb_desc_msos(desc, p, index, data, length);
trace_usb_desc_msos(dev->addr, index, length, ret);
}
break;
}
return ret;
}
static void dump_descriptor_info(int request, int value, int length) {
uint8_t type = value >> 8;
switch(type) {
case USB_DT_DEVICE:
printf("USB_DT_DEVICE,");
break;
case USB_DT_CONFIG:
printf("USB_DT_CONFIG,");
break;
case USB_DT_STRING:
printf("USB_DT_STRING,");
break;
case USB_DT_DEVICE_QUALIFIER:
printf("USB_DT_DEVICE_QUALIFIER,");
break;
case USB_DT_OTHER_SPEED_CONFIG:
printf("USB_DT_OTHER_SPEED_CONFIG,");
break;
case USB_DT_BOS:
printf("USB_DT_BOS,");
break;
case USB_DT_DEBUG:
break;
default:
printf("Unkown descriptor,");
break;
}
}
void dump_request(int request, int value, int index, int length) {
int req_type = (request >> 8) & USB_TYPE_MASK;
switch (req_type) {
case USB_TYPE_STANDARD:
printf("USB_TYPE_STANDARD, ");
break;
case USB_TYPE_CLASS:
printf("USB_TYPE_CLASS, ");
break;
case USB_TYPE_VENDOR:
printf("USB_TYPE_VENDOR, ");
break;
default:
printf("USB_TYPE_UNKNOWN, ");
break;
}
switch(request) {
case DeviceOutRequest | USB_REQ_SET_ADDRESS:
printf("DeviceOutRequest|USB_REQ_SET_ADDRESS, ");
break;
case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
printf("DeviceRequest|USB_REQ_GET_DESCRIPTOR, ");
dump_descriptor_info(request, value, length);
break;
case DeviceRequest | USB_REQ_GET_CONFIGURATION:
printf("DeviceRequest|USB_REQ_GET_CONFIGURATION, ");
break;
case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
printf("DeviceOutRequest|USB_REQ_SET_CONFIGURATION, ");
break;
case DeviceRequest | USB_REQ_GET_STATUS:
printf("DeviceRequest|USB_REQ_GET_STATUS, ");
break;
case DeviceOutRequest | USB_REQ_CLEAR_FEATURE:
printf("DeviceOutRequest|USB_REQ_CLEAR_FEATURE, ");
break;
case DeviceOutRequest | USB_REQ_SET_FEATURE:
printf("DeviceOutRequest|USB_REQ_SET_FEATURE, ");
break;
case DeviceOutRequest | USB_REQ_SET_SEL:
case DeviceOutRequest | USB_REQ_SET_ISOCH_DELAY:
printf("DeviceOutRequest|(USB_REQ_SET_SEL|USB_REQ_SET_ISOCH_DELAY), ");
break;
case InterfaceRequest | USB_REQ_GET_INTERFACE:
printf("InterfaceRequest|USB_REQ_GET_INTERFACE, ");
break;
case InterfaceOutRequest | USB_REQ_SET_INTERFACE:
printf("InterfaceOutRequest|USB_REQ_SET_INTERFACE, ");
break;
case VendorDeviceRequest | 'Q':
printf("VendorDeviceRequest|'Q', ");
break;
case VendorInterfaceRequest | 'Q':
printf("VendorInterfaceRequest|'Q', ");
break;
default:
printf("UNKNOWN, request=%x, ", request);
}
printf("value:%08x, index:%08x, length:%08x\n", value, index, length);
}
| 29.16129 | 80 | 0.571866 |
0c02c27718dd7feb543e185d05ae135d59510033 | 4,151 | h | C | code/Game/MultipleRenderTargets_GLSL_ES3.h | warzes/MikoEngine | 1199f59a71ab3dfcbea5d02238639db55eded0d4 | [
"MIT"
] | 5 | 2020-08-04T17:57:01.000Z | 2021-02-07T12:19:02.000Z | code/Game/MultipleRenderTargets_GLSL_ES3.h | warzes/MikoEngine | 1199f59a71ab3dfcbea5d02238639db55eded0d4 | [
"MIT"
] | null | null | null | code/Game/MultipleRenderTargets_GLSL_ES3.h | warzes/MikoEngine | 1199f59a71ab3dfcbea5d02238639db55eded0d4 | [
"MIT"
] | null | null | null | #if SE_OPENGLES
if (rhi->getNameId() == Rhi::NameId::OPENGLES3)
{
//[-------------------------------------------------------]
//[ Vertex shader source code ]
//[-------------------------------------------------------]
if (rhi->getCapabilities().upperLeftOrigin)
{
// One vertex shader invocation per vertex
vertexShaderSourceCode = R"(#version 300 es // OpenGL ES 3.0
// Attribute input/output
in highp vec2 Position; // Clip space vertex position as input, left/bottom is (-1,-1) and right/top is (1,1)
out highp vec2 TexCoord; // Normalized texture coordinate as output
// Programs
void main()
{
// Pass through the clip space vertex position, left/bottom is (-1,-1) and right/top is (1,1)
gl_Position = vec4(Position, 0.5, 1.0);
// Calculate the texture coordinate by mapping the clip space coordinate to a texture space coordinate
// -> In OpenGL ES 3 with "GL_EXT_clip_control"-extension, the texture origin is left/top which does not map well to clip space coordinates
// -> We have to flip the y-axis to map the coordinate system to the texture coordinate system
// -> (-1,-1) -> (0,1)
// -> (1,1) -> (1,0)
TexCoord = vec2(Position.x * 0.5f + 0.5f, 1.0f - (Position.y * 0.5f + 0.5f));
}
)";
}
else
{
// One vertex shader invocation per vertex
vertexShaderSourceCode = R"(#version 300 es // OpenGL ES 3.0
// Attribute input/output
in highp vec2 Position; // Clip space vertex position as input, left/bottom is (-1,-1) and right/top is (1,1)
out highp vec2 TexCoord; // Normalized texture coordinate as output
// Programs
void main()
{
// Pass through the clip space vertex position, left/bottom is (-1,-1) and right/top is (1,1)
gl_Position = vec4(Position, 0.5, 1.0);
// Calculate the texture coordinate by mapping the clip space coordinate to a texture space coordinate
// -> In OpenGL ES 3 without "GL_EXT_clip_control"-extension, the texture origin is left/bottom which maps well to clip space coordinates
// -> (-1,-1) -> (0,0)
// -> (1,1) -> (1,1)
TexCoord = Position.xy * 0.5 + 0.5;
}
)";
}
//[-------------------------------------------------------]
//[ Fragment shader source code ]
//[-------------------------------------------------------]
// One fragment shader invocation per fragment
fragmentShaderSourceCode_MultipleRenderTargets = R"(#version 300 es // OpenGL ES 3.0
precision highp float; // Default precision to high for floating points
// Attribute input/output
in mediump vec2 TexCoord; // Normalized texture coordinate as input
out highp vec4 OutputColor[2]; // Output variable for fragment color
// Programs
void main()
{
OutputColor[0] = vec4(1.0f, 0.0f, 0.0f, 0.0f); // Red
OutputColor[1] = vec4(0.0f, 0.0f, 1.0f, 0.0f); // Blue
}
)";
//[-------------------------------------------------------]
//[ Fragment shader source code ]
//[-------------------------------------------------------]
// One fragment shader invocation per fragment
fragmentShaderSourceCode = R"(#version 300 es // OpenGL ES 3.0
precision highp float; // Default precision to high for floating points
// Attribute input/output
in mediump vec2 TexCoord; // Normalized texture coordinate as input
out highp vec4 OutputColor; // Output variable for fragment color
// Uniforms
uniform mediump sampler2D AlbedoMap0;
uniform mediump sampler2D AlbedoMap1;
// Programs
void main()
{
// Fetch the texel at the given texture coordinate from render target 0 (which should contain a red triangle)
vec4 color0 = texture(AlbedoMap0, TexCoord);
// Fetch the texel at the given texture coordinate from render target 1 (which should contain a blue triangle)
vec4 color1 = texture(AlbedoMap1, TexCoord);
// Calculate the final color by subtracting the colors of the both render targets from white
// -> The result should be white or green
OutputColor = vec4(1.0, 1.0, 1.0, 1.0) - color0 - color1;
}
)";
//[-------------------------------------------------------]
//[ Shader end ]
//[-------------------------------------------------------]
}
else
#endif
| 36.095652 | 141 | 0.605878 |
ae834b9f2a692284da1274fbe56146c201250b18 | 2,015 | h | C | src/mon-blows.h | takkaria/angband | 6a5df0b662caca9fff9d332c1ec6b21e7b36e595 | [
"CC-BY-3.0"
] | null | null | null | src/mon-blows.h | takkaria/angband | 6a5df0b662caca9fff9d332c1ec6b21e7b36e595 | [
"CC-BY-3.0"
] | null | null | null | src/mon-blows.h | takkaria/angband | 6a5df0b662caca9fff9d332c1ec6b21e7b36e595 | [
"CC-BY-3.0"
] | null | null | null | /**
* \file mon-blow-effects.h
* \brief Functions for managing monster melee effects.
*
* Copyright (c) 1997 Ben Harrison, David Reeve Sward, Keldon Jones.
* 2013 Ben Semmler
*
* This work is free software; you can redistribute it and/or modify it
* under the terms of either:
*
* a) the GNU General Public License as published by the Free Software
* Foundation, version 2, or
*
* b) the "Angband licence":
* This software may be copied and distributed for educational, research,
* and not for profit purposes provided that this copyright and statement
* are included in all such copies. Other copyrights may also apply.
*/
#ifndef MON_BLOW_EFFECTS_H
#define MON_BLOW_EFFECTS_H
#include "player.h"
#include "monster.h"
struct blow_method {
char *name;
bool cut;
bool stun;
bool miss;
bool phys;
int msgt;
char *act_msg;
char *desc;
struct blow_method *next;
};
struct blow_method *blow_methods;
/**
* Storage for context information for effect handlers called in
* make_attack_normal().
*
* The members of this struct are initialized in an order-dependent way
* (to be more cross-platform). If the members change, make sure to change
* any initializers. Ideally, this should eventually used named initializers.
*/
typedef struct melee_effect_handler_context_s {
struct player * const p;
struct monster * const mon;
const int rlev;
const struct blow_method *method;
const int ac;
const char *ddesc;
bool obvious;
bool blinked;
bool do_break;
int damage;
} melee_effect_handler_context_t;
/**
* Melee blow effect handler.
*/
typedef void (*melee_effect_handler_f)(melee_effect_handler_context_t *);
struct blow_effect {
char *name;
int power;
int eval;
char *desc;
struct blow_effect *next;
};
struct blow_effect *blow_effects;
/* Functions */
extern const char *monster_blow_method_action(struct blow_method *method);
extern melee_effect_handler_f melee_handler_for_blow_effect(const char *name);
#endif /* MON_BLOW_EFFECTS_H */
| 24.876543 | 78 | 0.740447 |
aeea66f62adfca25cced4aa26a3204e81b101e7d | 817,310 | h | C | 3rdparty/nuvoton/Library/Device/Nuvoton/Nano1X2Series/Include/Nano1x2Series.h | Lamyidity/Kasumi | 8d17c712a23c434009c51bdf4c25b92fce5dc781 | [
"OpenSSL"
] | 58 | 2015-12-03T09:00:43.000Z | 2022-01-15T12:51:34.000Z | 3rdparty/nuvoton/Library/Device/Nuvoton/Nano1X2Series/Include/Nano1x2Series.h | Lamyidity/Kasumi | 8d17c712a23c434009c51bdf4c25b92fce5dc781 | [
"OpenSSL"
] | 10 | 2016-04-11T11:29:51.000Z | 2020-09-07T08:44:50.000Z | 3rdparty/nuvoton/Library/Device/Nuvoton/Nano1X2Series/Include/Nano1x2Series.h | Lamyidity/Kasumi | 8d17c712a23c434009c51bdf4c25b92fce5dc781 | [
"OpenSSL"
] | 32 | 2016-02-04T12:20:48.000Z | 2022-02-07T22:04:29.000Z | /**************************************************************************//**
* @file Nano1X2Series.h
* @version V1.00
* $Revision: 89 $
* $Date: 14/12/26 9:22a $
* @brief Nano102/112 peripheral access layer header file.
* This file contains all the peripheral register's definitions,
* bits definitions and memory mapping for NuMicro Nano102/112 MCU.
*
* @note
* Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
/**
\mainpage NuMicro Nano102/112 Driver Reference Guide
*
* <b>Introduction</b>
*
* This user manual describes the usage of Nano102/112 Series MCU device driver
*
* <b>Disclaimer</b>
*
* The Software is furnished "AS IS", without warranty as to performance or results, and
* the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
* warranties, express, implied or otherwise, with regard to the Software, its use, or
* operation, including without limitation any and all warranties of merchantability, fitness
* for a particular purpose, and non-infringement of intellectual property rights.
*
* <b>Important Notice</b>
*
* Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
* any malfunction or failure of which may cause loss of human life, bodily injury or severe
* property damage. Such applications are deemed, "Insecure Usage".
*
* Insecure usage includes, but is not limited to: equipment for surgical implementation,
* atomic energy control instruments, airplane or spaceship instruments, the control or
* operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
* instruments, all types of safety devices, and other applications intended to support or
* sustain life.
*
* All Insecure Usage shall be made at customer's risk, and in the event that third parties
* lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
* the damages and liabilities thus incurred by Nuvoton.
*
* Please note that all data and specifications are subject to change without notice. All the
* trademarks of products and companies mentioned in this datasheet belong to their respective
* owners.
*
* <b>Copyright Notice</b>
*
* Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
*/
/**
* \page pg1 NuMicro Nano102/112 BSP Directory Structure
* Please refer to Readme.pdf under BSP root directory for the BSP directory structure
*
* \page pg2 Revision History
*
* <b>Revision 3.01.000</b>
* \li Fixed GPIO_DISABLE_DIGITAL_PATH(), GPIO_ENABLE_DIGITAL_PATH(),GPIO_DISABLE_DOUT_MASK(),GPIO_ENABLE_DOUT_MASK(), GPIO_DISABLE_PULL_UP(), and GPIO_ENABLE_PULL_UP() implementation error.
* \li Fixed SYS_PC_L_MFP_PC0_MFP_LCD_S11, SYS_PC_L_MFP_PC0_MFP_LCD_S18, SYS_PC_L_MFP_PC0_MFP_LCD_S22, SYS_PC_H_MFP_PC10_MFP_I2C1_SCL, SYS_PC_H_MFP_PC11_MFP_I2C1_SDA,
* SYS_PD_H_MFP_PD13_MFP_EINT1, SYS_PD_H_MFP_PD10_MFP_LCD_COM0, SYS_PD_H_MFP_PD10_MFP_LCD_COM0, SYS_PD_H_MFP_PD9_MFP_LCD_COM1, SYS_PD_H_MFP_PD8_MFP_LCD_COM2,
* SYS_PF_L_MFP_PF5_MFP_ICE_DAT, and SYS_PF_L_MFP_PF4_MFP_ICE_CLK definition error.
* \li Fixed SYS_DISABLE_BOD*(), and SYS_ENABLE_BOD*() implementation error.
* \li Fixed PDMA_WIDTH_* definition error
* \li Fixed PWM_ConfigOutputChannel() and PWM_ConfigCaptureChannel() PWM channel 2 and 3 clock setting error.
* \li Fixed SPI_SET_SSx_LOW(), SPI_SET_SSx_HIGH(), SPI_CLR_3WIRE_START_INT_FLAG(), and SPI_CLR_UNIT_TRANS_INT_FLAG()implementation error.
* \li Fixed SPI_Open(), SPI_SetBusClock() and SPI_GetBusClock() clock frequency calculation.
* \li Fixed I2C_Open(), I2C_GetBusClockFreq(), and I2C_SetBusClockFreq() clock frequency calculation error.
* \li Replaced the *_MFP_TIMERx_EXT setting with *_MFP_TIMERx_CNT and *_TIMERx_OUT.
* \li Renamed *_MFP_CKOHZ to *_MFP_CLK_Hz.
* \li Renamed SYS_PA_L_MFP_PA5_MFP_SC2_RST to SYS_PA_L_MFP_PA5_MFP_SC0_PWR.
* \li Renamed SYS_PA_H_MFP_PA10_MFP_SC0_DAT to SYS_PA_H_MFP_PA10_MFP_SC0_CLK.
* \li Renamed SYS_PA_H_MFP_PA12_MFP_I2C1_SCL to SYS_PA_H_MFP_PA12_MFP_I2C0_SCL.
* \li Renamed SYS_PA_H_MFP_PA13_MFP_I2C0_DAT to SYS_PA_H_MFP_PA13_MFP_I2C0_SDA.
* \li Renamed SYS_PA_H_MFP_PA15_MFP_I2C_DAT to SYS_PA_H_MFP_PA15_MFP_I2C1_SDA.
* \li Renamed SYS_PB_L_MFP_PB3_MFP_I2C_DAT to SYS_PB_L_MFP_PB3_MFP_I2C0_SDA.
* \li Renamed SYS_PB_L_MFP_PB5_MFP_SPI2_MOSI1 to SYS_PB_L_MFP_PB5_MFP_SPI1_MOSI1
* \li Renamed SYS_PB_L_MFP_PB7_MFP_CD to SYS_PB_L_MFP_PB7_MFP_SC0_CD.
* \li Renamed SYS_PB_H_MFP_PB10_MFP_SPI1_MOSI1 to SYS_PB_H_MFP_PB10_MFP_SPI0_MOSI1.
* \li Renamed SYS_PD_L_MFP_PD7_MFP_LCD_S3 to SYS_PD_L_MFP_PD7_MFP_LCD_COM3.
* \li Renamed SYS_PD_H_MFP_PD11_MFP_LCD_DH1 to SYS_PD_H_MFP_PD11_MFP_LCD_DH2.
* \li Renamed SYS_PD_H_MFP_PD12_MFP_LCD_DH2 to SYS_PD_H_MFP_PD12_MFP_LCD_DH1.
* \li Renamed SYS_PF_L_MFP_PF2_MFP_HXT_OUT to SYS_PF_L_MFP_PF2_MFP_XT1_IN.
* \li Renamed SYS_PF_L_MFP_PF3_MFP_HXT_IN to SYS_PF_L_MFP_PF3_MFP_XT1_OUT.
* \li Renamed SYS_PF_L_MFP_PF1_MFP_ICE_CLK to SYS_PF_L_MFP_PF4_MFP_ICE_CLK.
* \li Renamed SYS_PF_L_MFP_PF0_MFP_ICE_DAT to SYS_PF_L_MFP_PF5_MFP_ICE_DAT.
* \li Updated CLK_EnableCKO() to set clock source before output enable.
* \li Updated I2C_WAIT_READY() to clear I2C_INTSTS_INTSTS_Msk before exiting macro.
* \li Updated FMC_Erase() to avoid modifying FMC->ISPCON register setting.
* \li Added SYS_PD_H_MFP_PD11_MFP_PWM0_CH1 definition.
* \li Added ADC_PDMA, ADC_TimerTrigger, GPIO_PowerDown, Hard_Fault_Sample, PWM_CapturePDMA, SPI_TxRxLoopback_PDMA, SYS_PLLClockOutput, UART_FlowCtrl, and UART_Rx_Wakeup samples.
*
* <b>Revision 3.00.001</b>
* \li Improved PWM capture function performance.
* \li Added ADC_SET_REF_VOLTAGE macro to configure ADC reference voltage.
* \li Minor bug fix.
*
* <b>Revision 3.00.000</b>
* \li Changed major version number from 1 to 3.
* \li Renamed I2C_SetClockBusFreq() to I2C_SetBusClockFreq().
* \li Renamed I2C_SetSlaveMask() to I2C_SetSlaveAddrMask().
* \li Renamed RTC_GetDatAndTime() to RTC_GetDateAndTime().
* \li Added Learning Board sample.
* \li Moved Smartcard libraries one directory level up to "Library\SmartcardLib\".
* \li Minor bug fix.
*
* <b>Revision 1.00.000</b>
* \li Initial release.
*/
#ifndef __NANO1X2SERIES_H__
#define __NANO1X2SERIES_H__
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup NANO1X2_Definitions NANO102/112 Definitions
This file defines all structures and symbols for NANO102/112:
- interrupt numbers
- registers and bit fields
- peripheral base address
- peripheral ID
- Peripheral definitions
@{
*/
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup NANO1X2_CMSIS Device CMSIS Definitions
Configuration of the Cortex-M0 Processor and Core Peripherals
@{
*/
/**
* @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
*/
typedef enum IRQn {
/****** Cortex-M0 Processor Exceptions Numbers *****************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** NANO102/112 specific Interrupt Numbers ***********************************************/
BOD_IRQn = 0, /*!< Brownout low voltage detected interrupt */
WDT_IRQn = 1, /*!< Watch Dog Timer interrupt */
EINT0_IRQn = 2, /*!< External signal interrupt from PB.14 pin */
EINT1_IRQn = 3, /*!< External signal interrupt from PB.15 pin */
GPABC_IRQn = 4, /*!< External signal interrupt from PA[15:0]/PB[13:0]/PC[15:0] */
GPDEF_IRQn = 5, /*!< External interrupt from PD[15:0]/PE[15:0]/PF[15:0] */
PWM0_IRQn = 6, /*!< PWM 0 interrupt */
TMR0_IRQn = 8, /*!< Timer 0 interrupt */
TMR1_IRQn = 9, /*!< Timer 1 interrupt */
TMR2_IRQn = 10, /*!< Timer 2 interrupt */
TMR3_IRQn = 11, /*!< Timer 3 interrupt */
UART0_IRQn = 12, /*!< UART0 interrupt */
UART1_IRQn = 13, /*!< UART1 interrupt */
SPI0_IRQn = 14, /*!< SPI0 interrupt */
SPI1_IRQn = 15, /*!< SPI1 interrupt */
HIRC_IRQn = 17, /*!< HIRC interrupt */
I2C0_IRQn = 18, /*!< I2C0 interrupt */
I2C1_IRQn = 19, /*!< I2C1 interrupt */
SC0_IRQn = 21, /*!< Smart Card 0 interrupt */
SC1_IRQn = 22, /*!< Smart Card 1 interrupt */
ACMP_IRQn = 23, /*!< Analog Comparator interrupt */
LCD_IRQn = 25, /*!< LCD interrupt */
PDMA_IRQn = 26, /*!< PDMA interrupt */
PDWU_IRQn = 28, /*!< Power Down Wake up interrupt */
ADC_IRQn = 29, /*!< ADC interrupt */
RTC_IRQn = 31 /*!< Real time clock interrupt */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __CM0_REV 0x0201 /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __FPU_PRESENT 0 /*!< FPU present or not */
/*@}*/ /* end of group NANO1X2_CMSIS */
#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
#include "system_Nano1X2Series.h" /* NANO102/112 Series System include file */
#include <stdint.h>
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup NANO1X2_Peripherals NANO102/112 Peripherals
NANO102/112 Device Specific Peripheral registers structures
@{
*/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*---------------------- Analog Comparator Controller -------------------------*/
/**
@addtogroup ACMP Analog Comparator Controller(ACMP)
Memory Mapped Structure for ACMP Controller
@{ */
typedef struct {
/**
* CR0/1
* ===================================================================================================
* Offset: 0x00,0x04 Analog Comparator 0/1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPEN |Comparator ACMP0/1 Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |Note: Comparator output needs to wait 10 us stable time after ACMPEN(ACMP0EN/ACMP1EN) is set.
* |[1] |ACMPIE |Comparator ACMP Interrupt Enable Control
* | | |0 = ACMP interrupt function Disabled.
* | | |1 = ACMP interrupt function Enabled.
* | | |Note: Interrupt generated if ACMPIE(ACMP0IE/ACMP1IE) bit is set to "1" after ACMP0/1 output changed.
* |[2] |ACMP_HYSEN|Comparator ACMP0/1 Hysteresis Enable Control
* | | |0 = ACMP0 Hysteresis function Disabled.
* | | |1 = ACMP0 Hysteresis function Enabled. The typical range is 20mV.
* |[5:4] |CN |Comparator ACMP0/1 Negative Input Selection
* | | |00 = The comparator reference pin ACMP0/1_N is selected as the negative comparator input.
* | | |01 = The internal comparator reference voltage (CRV) is selected as the negative comparator input.
* | | |10 = The internal reference voltage (Int_VREF) is selected as the negative comparator input.
* | | |11 = The AGND is selected as the negative comparator input.
* |[16] |ACMP0_EX |Comparator ACMP0 Swap
* | | |0 = No swap to the comparator inputs and output.
* | | |1 = Swap the comparator inputs with ACMP0_Px and ACMP0_N, and invert the polarity of comparator 0 output.
* | | |Note: This bit swaps the comparator inputs and inverts the comparator output.
* |[19] |ACOMP0_PN_AutoEx|Comparator Analog ACMP0_Px & ACMP0_N Input Swap Function Automatically
* | | |This bit is only for sigma-delta ADC mode use.
* | | |0 = Disabled to swap comparator ACMP0 input function, ACMP0_Px and ACMP0_N, automatically.
* | | |1 = Enabled to swap comparator ACMP0 input function, ACMP0_Px and ACMP0_N, automatically.
* |[20] |ACMP0_FILTER|Comparator ACMP0 Output Filter
* | | |0 = Comparator ACMP0 output is not filtered by internal RC filter.
* | | |1 = Comparator ACMP0 output is filtered by internal RC filter.
* |[21] |CPO0_SEL |Comparator ACMP0 Output To Timer Path Selection
* | | |0 = Comparator ACMP0 output to Timer is through internal path.
* | | |1 = Comparator ACMP0 output to Timer is through external pin (through PF.4).
* |[30:29] |CPP0SEL |Comparator ACMP0 Positive Input Selection
* | | |00 = Input from PA.4.
* | | |01 = Input from PA.3.
* | | |10 = Input from PA.2.
* | | |11 = Input from PA.1.
* |[31] |ACMP_WKEUP_EN|Comparator ACMP0/1 Wake-Up Enable Control
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled when the system enters Power-down mode.
*/
__IO uint32_t CR[2];
/**
* SR
* ===================================================================================================
* Offset: 0x08 Analog Comparator Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPF0 |Comparator ACMP0 Flag
* | | |This bit is set by hardware whenever the comparator 0 output changes state.
* | | |This will generate an interrupt if ACMP0IE set.
* | | |Note: Write "1" to clear this bit to 0.
* |[1] |ACMPF1 |Comparator ACMP1 Flag
* | | |This bit is set by hardware whenever the comparator 1 output changes state.
* | | |This will generate an interrupt if ACMP1IE set.
* | | |Note: Write "1" to clear this bit to 0.
* |[2] |CO0 |Comparator ACMP0 Output
* | | |Synchronized to the PCLK to allow reading by software.
* | | |Cleared when the comparator is disabled (ACMP0EN = 0).
* |[3] |CO1 |Comparator ACMP1 Output
* | | |Synchronized to the PCLK to allow reading by software.
* | | |Cleared when the comparator is disabled (ACMP1EN = 0).
*/
__IO uint32_t SR;
/**
* RVCR
* ===================================================================================================
* Offset: 0x0C Analog Comparator Reference Voltage Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CRVS |Comparator Reference Voltage Setting
* | | |Comparator reference voltage = VIN * (1/6+CRVS[3:0]/24). VIN = AVDD or Int_VREF.
* |[4] |CRV_EN |CRV Enable Control
* | | |0 = CRV Disabled.
* | | |1 = CRV Enabled.
* |[5] |CRVSRC_SEL|CRV Source Selection
* | | |0 = From AVDD.
* | | |1 = From Int_VREF.
*/
__IO uint32_t RVCR;
/**
* MODCR0
* ===================================================================================================
* Offset: 0x10 Analog Comparator 0 Mode Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |MOD_SEL |Comparator Mode Selection
* | | |00 = Normal Comparator Mode.
* | | |01 = Sigma-Delta ADC Mode.
* | | |10 = Single Slope ADC Mode.
* | | |11 = Reserved.
* |[2] |TMR_SEL |Analog Comparator 0 Co-Operation Timer Selection
* | | |0 = Select TIMER0 as co-operation Timer.
* | | |1 = Select TIMER2 as co-operation Timer.
* |[3] |TMR_TRI_LV|Timer Trigger Level
* | | |This bit is for Sigma-Delta ADC Mode.
* | | |0 = Comparator Output Low to High to Enable Timer.
* | | |1 = Comparator Output High to Low to Enable Timer.
* |[6:4] |CH_DIS_PIN_SEL|Charge Or Discharge Pin Selection
* | | |000 = PA.1.
* | | |001 = PA.2.
* | | |010 = PA.3.
* | | |011 = PA.4.
* | | |100 = PA.5.
* | | |101 = PA.6.
* | | |110 = PA.14.
* | | |111 = PF.5.
* |[7] |CH_DIS_FUN_SEL|Charge Or Discharge Pin Function Option
* | | |This bit is for Single Slope ADC Mode only.
* | | |0 = Drive low on charge pin to dis-charge capacitor and drive high on charge pin to charge capacitor.
* | | |1 = Drive high on charge pin to dis-charge capacitor and drive low on charge pin to charge capacitor.
* |[8] |START |Start ADC Mode
* | | |0 = Stop Sigma-Delta ADC Mode or Single Slope ADC Mode.
* | | |1 = Start Sigma-Delta ADC Mode or Single Slope ADC Mode.
*/
__IO uint32_t MODCR0;
} ACMP_T;
/**
@addtogroup ACMP_CONST ACMP Bit Field Definition
Constant Definitions for ACMP Controller
@{ */
#define ACMP_CR_ACMPEN_Pos (0) /*!< ACMP CR: ACMPEN Position */
#define ACMP_CR_ACMPEN_Msk (0x1ul << ACMP_CR_ACMPEN_Pos) /*!< ACMP CR: ACMPEN Mask */
#define ACMP_CR_ACMPIE_Pos (1) /*!< ACMP CR: ACMPIE Position */
#define ACMP_CR_ACMPIE_Msk (0x1ul << ACMP_CR_ACMPIE_Pos) /*!< ACMP CR: ACMPIE Mask */
#define ACMP_CR_ACMP_HYSEN_Pos (2) /*!< ACMP CR: ACMP_HYSEN Position */
#define ACMP_CR_ACMP_HYSEN_Msk (0x1ul << ACMP_CR_ACMP_HYSEN_Pos) /*!< ACMP CR: ACMP_HYSEN Mask */
#define ACMP_CR_CN_Pos (4) /*!< ACMP CR: CN Position */
#define ACMP_CR_CN_Msk (0x3ul << ACMP_CR_CN_Pos) /*!< ACMP CR: CN Mask */
#define ACMP_CR_ACMP0_EX_Pos (16) /*!< ACMP CR: ACMP0_EX Position */
#define ACMP_CR_ACMP0_EX_Msk (0x1ul << ACMP_CR_ACMP0_EX_Pos) /*!< ACMP CR: ACMP0_EX Mask */
#define ACMP_CR_ACMP0_INV_Pos (17) /*!< ACMP CR: ACMP0_INV Position */
#define ACMP_CR_ACMP0_INV_Msk (0x1UL<<ACMP_CR_ACMP0_INV_Pos) /*!< ACMP CR: ACMP0_INV Mask */
#define ACMP_CR_ACOMP0_PN_AutoEx_Pos (19) /*!< ACMP CR: ACOMP0_PN_AutoEx Position */
#define ACMP_CR_ACOMP0_PN_AutoEx_Msk (0x1ul << ACMP_CR_ACOMP0_PN_AutoEx_Pos) /*!< ACMP CR: ACOMP0_PN_AutoEx Mask */
#define ACMP_CR_ACMP0_FILTER_Pos (20) /*!< ACMP CR: ACMP0_FILTER Position */
#define ACMP_CR_ACMP0_FILTER_Msk (0x1ul << ACMP_CR_ACMP0_FILTER_Pos) /*!< ACMP CR: ACMP0_FILTER Mask */
#define ACMP_CR_CPO0_SEL_Pos (21) /*!< ACMP CR: CPO0_SEL Position */
#define ACMP_CR_CPO0_SEL_Msk (0x1ul << ACMP_CR_CPO0_SEL_Pos) /*!< ACMP CR: CPO0_SEL Mask */
#define ACMP_CR_CPP0SEL_Pos (29) /*!< ACMP CR: CPP0SEL Position */
#define ACMP_CR_CPP0SEL_Msk (0x3ul << ACMP_CR_CPP0SEL_Pos) /*!< ACMP CR: CPP0SEL Mask */
#define ACMP_CR_ACMP_WKEUP_EN_Pos (31) /*!< ACMP CR: ACMP0_WKEUP_EN Position */
#define ACMP_CR_ACMP_WKEUP_EN_Msk (0x1ul << ACMP_CR_ACMP0_WKEUP_EN_Pos) /*!< ACMP CR: ACMP0_WKEUP_EN Mask */
#define ACMP_SR_ACMPF0_Pos (0) /*!< ACMP SR: ACMPF0 Position */
#define ACMP_SR_ACMPF0_Msk (0x1ul << ACMP_SR_ACMPF0_Pos) /*!< ACMP SR: ACMPF0 Mask */
#define ACMP_SR_ACMPF1_Pos (1) /*!< ACMP SR: ACMPF1 Position */
#define ACMP_SR_ACMPF1_Msk (0x1ul << ACMP_SR_ACMPF1_Pos) /*!< ACMP SR: ACMPF1 Mask */
#define ACMP_SR_CO0_Pos (2) /*!< ACMP SR: CO0 Position */
#define ACMP_SR_CO0_Msk (0x1ul << ACMP_SR_CO0_Pos) /*!< ACMP SR: CO0 Mask */
#define ACMP_SR_CO1_Pos (3) /*!< ACMP SR: CO1 Position */
#define ACMP_SR_CO1_Msk (0x1ul << ACMP_SR_CO1_Pos) /*!< ACMP SR: CO1 Mask */
#define ACMP_RVCR_CRVS_Pos (0) /*!< ACMP RVCR: CRVS Position */
#define ACMP_RVCR_CRVS_Msk (0xful << ACMP_RVCR_CRVS_Pos) /*!< ACMP RVCR: CRVS Mask */
#define ACMP_RVCR_CRV_EN_Pos (4) /*!< ACMP RVCR: CRV_EN Position */
#define ACMP_RVCR_CRV_EN_Msk (0x1ul << ACMP_RVCR_CRV_EN_Pos) /*!< ACMP RVCR: CRV_EN Mask */
#define ACMP_RVCR_CRVSRC_SEL_Pos (5) /*!< ACMP RVCR: CRVSRC_SEL Position */
#define ACMP_RVCR_CRVSRC_SEL_Msk (0x1ul << ACMP_RVCR_CRVSRC_SEL_Pos) /*!< ACMP RVCR: CRVSRC_SEL Mask */
#define ACMP_MODCR0_MOD_SEL_Pos (0) /*!< ACMP MODCR0: MOD_SEL Position */
#define ACMP_MODCR0_MOD_SEL_Msk (0x3ul << ACMP_MODCR0_MOD_SEL_Pos) /*!< ACMP MODCR0: MOD_SEL Mask */
#define ACMP_MODCR0_TMR_SEL_Pos (2) /*!< ACMP MODCR0: TMR_SEL Position */
#define ACMP_MODCR0_TMR_SEL_Msk (0x1ul << ACMP_MODCR0_TMR_SEL_Pos) /*!< ACMP MODCR0: TMR_SEL Mask */
#define ACMP_MODCR0_TMR_TRI_LV_Pos (3) /*!< ACMP MODCR0: TMR_TRI_LV Position */
#define ACMP_MODCR0_TMR_TRI_LV_Msk (0x1ul << ACMP_MODCR0_TMR_TRI_LV_Pos) /*!< ACMP MODCR0: TMR_TRI_LV Mask */
#define ACMP_MODCR0_CH_DIS_PIN_SEL_Pos (4) /*!< ACMP MODCR0: CH_DIS_PIN_SEL Position */
#define ACMP_MODCR0_CH_DIS_PIN_SEL_Msk (0x7ul << ACMP_MODCR0_CH_DIS_PIN_SEL_Pos) /*!< ACMP MODCR0: CH_DIS_PIN_SEL Mask */
#define ACMP_MODCR0_CH_DIS_FUN_SEL_Pos (7) /*!< ACMP MODCR0: CH_DIS_FUN_SEL Position */
#define ACMP_MODCR0_CH_DIS_FUN_SEL_Msk (0x1ul << ACMP_MODCR0_CH_DIS_FUN_SEL_Pos) /*!< ACMP MODCR0: CH_DIS_FUN_SEL Mask */
#define ACMP_MODCR0_START_Pos (8) /*!< ACMP MODCR0: START Position */
#define ACMP_MODCR0_START_Msk (0x1ul << ACMP_MODCR0_START_Pos) /*!< ACMP MODCR0: START Mask */
/**@}*/ /* ACMP_CONST */
/**@}*/ /* end of ACMP register group */
/*---------------------- Analog to Digital Converter -------------------------*/
/**
@addtogroup ADC Analog to Digital Converter(ADC)
Memory Mapped Structure for ADC Controller
@{ */
typedef struct {
/**
* RESULT
* ===================================================================================================
* Offset: 0x00 ~ 0x44 A/D Data Register 0 ~ 7 and 14 ~ 17
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |RSLT |A/D Conversion Result
* | | |This field contains 12 bits conversion results.
* |[16] |VALID |Data Valid Flag
* | | |After ADC converts finish, this field will set to high.
* | | |This field will clear when this register be read.
* |[17] |OVERRUN |Over Run Flag
* | | |When VALID is high and ADC converts finish, this field will set to high.
*/
__I uint32_t RESULT[18];
/**
* CR
* ===================================================================================================
* Offset: 0x48 A/D Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADEN |A/D Converter Enable
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |Before starting A/D conversion, this bit should be set to 1.
* | | |Clear it to 0 to disable A/D converter analog circuit power consumption.
* |[1] |ADIE |A/D Interrupt Enable
* | | |0 = A/D interrupt function Disabled.
* | | |1 = A/D interrupt function Enabled.
* | | |A/D conversion end interrupt request is generated if ADIE bit is set to 1.
* |[3:2] |ADMD |A/D Converter Operation Mode
* | | |00 = Single conversion
* | | |01 = Reserved
* | | |10 = Single-cycle scan
* | | |11 = Continuous scan
* |[5:4] |TRGS |Hardware Trigger Source
* | | |This field must keep 00
* | | |Software should disable TRGE and ADST before change TRGS.
* | | |In hardware trigger mode, the ADST bit is set by the external trigger from STADC, However software has the highest priority to set or cleared ADST bit at any time.
* |[7:6] |TRGCOND |External Trigger Condition
* | | |These two bits decide external pin STADC trigger event is level or edge.
* | | |The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.
* | | |00 = Low level
* | | |01 = High level
* | | |10 = Falling edge
* | | |11 = Rising edge
* |[8] |TRGE |External Trigger Enable
* | | |Enable or disable triggering of A/D conversion by external STADC pin.
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[9] |PTEN |PDMA Transfer Enable
* | | |0 = PDMA data transfer Disabled.
* | | |1 = PDMA data transfer in ADC_RESULT 0~17 Enabled.
* | | |When A/D conversion is completed, the converted data is loaded into ADC_RESULT 0~10, software can enable this bit to generate a PDMA data transfer request.
* | | |When PTEN=1, software must set ADIE=0 to disable interrupt.
* | | |PDMA can access ADC_RESULT 0-17 registers by block or single transfer mode.
* |[10] |DIFF |Differential Mode Selection
* | | |0 = ADC is operated in single-ended mode.
* | | |1 = ADC is operated in differential mode.
* | | |The A/D analog input ADC_CH0/ADC_CH1 consists of a differential pair.
* | | |So as ADC_CH2/ADC_CH3, ADC_CH4/ADC_CH5, ADC_CH6/ADC_CH7, ADC_CH8/ADC_CH9 and ADC_CH10/ADC_CH11.
* | | |The even channel defines as plus analog input voltage (Vplus) and the odd channel defines as minus analog input voltage (Vminus).
* | | |Differential input voltage (Vdiff) = Vplus - Vminus, where Vplus is the analog input; Vminus is the inverted analog input.
* | | |In differential input mode, only the even number of the two corresponding channels needs to be enabled in CHEN (ADCHER[11:0]).
* | | |The conversion result will be placed to the corresponding data register of the enabled channel.
* | | |Note: Calibration should calibrated each time when switching between single-ended and differential mode
* |[11] |ADST |A/D Conversion Start
* | | |0 = Conversion stopped and A/D converter enter idle state.
* | | |1 = Conversion starts.
* | | |ADST bit can be set to 1 from two sources: software write and external pin STADC.
* | | |ADST is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels.
* | | |In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset.
* | | |Note: After ADC conversion done, SW needs to wait at least one ADC clock before to set this bit high again.
* |[13:12] |TMSEL |Select A/D Enable Time-Out Source
* | | |00 = TMR0
* | | |01 = TMR1
* | | |10 = TMR2
* | | |11 = TMR3
* |[15] |TMTRGMOD |Timer Event Trigger ADC Conversion
* | | |0 = This function Disabled.
* | | |1 = ADC Enabled by TIMER OUT event. Setting TMSEL to select timer event from timer0~3
* |[17:16] |REFSEL |Reference Voltage Source Selection
* | | |00 = Reserved
* | | |01 = Select Int_VREF as reference voltage
* | | |10 = Select VREF as reference voltage
* | | |11 = Reserved
* |[19:18] |RESSEL |Resolution Selection
* | | |00 = 6 bits
* | | |01 = 8 bits
* | | |10 = 10 bits
* | | |11 = 12 bits
* |[31:24] |TMPDMACNT |PDMA Count
* | | |When each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting
* | | |Note: The total amount of PDMA transferring data should be set in PDMA byte count register.
* | | |When PDMA finish is set, ADC will not be enabled and start transfer even though the timer event occurred.
*/
__IO uint32_t CR;
/**
* CHEN
* ===================================================================================================
* Offset: 0x4C A/D Channel Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CHEN0 |Analog Input Channel 0 Enable Control (Convert Input Voltage From PA.0 )
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |If more than one channel in single mode is enabled by software, the least channel is converted and other enabled channels will be ignored.
* |[1] |CHEN1 |Analog Input Channel 1 Enable Control (Convert Input Voltage From PA.1 )
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[2] |CHEN2 |Analog Input Channel 2 Enable Control (Convert Input Voltage From PA.2 )
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[3] |CHEN3 |Analog Input Channel 3 Enable Control (Convert Input Voltage From PA.3 )
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[4] |CHEN4 |Analog Input Channel 4 Enable Control (Convert Input Voltage From PA.4 )
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[5] |CHEN5 |Analog Input Channel 5 Enable Control (Convert Input Voltage From PA.5 )
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[6] |CHEN6 |Analog Input Channel 6 Enable Control (Convert Input Voltage From PA.6 )
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[7] |CHEN7 |Analog Input Channel 7 Enable Control (Convert Input Voltage From PA.7 )
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[14] |CHEN14 |Analog Input Channel 14 Enable Control (Convert VTEMP)
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[15] |CHEN15 |Analog Input Channel 15 Enable Control (Convert Int_VREF)
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[16] |CHEN16 |Analog Input Channel 16 Enable Control (Convert AVDD)
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[17] |CHEN17 |Analog Input Channel 17 Enable Control (Convert AVSS)
* | | |0 = Disabled.
* | | |1 = Enabled.
*/
__IO uint32_t CHEN;
/**
* CMPR0
* ===================================================================================================
* Offset: 0x50 A/D Compare Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CMPEN |Compare Enable
* | | |0 = Compare Disabled.
* | | |1 = Compare Enabled.
* | | |Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.
* | | |When this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit
* |[1] |CMPIE |Compare Interrupt Enable
* | | |0 = Compare function interrupt Disabled.
* | | |1 = Compare function interrupt Enabled.
* | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
* |[2] |CMPCOND |Compare Condition
* | | |0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one.
* | | |1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one.
* | | |Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
* |[7:3] |CMPCH |Compare Channel Selection
* | | |This field selects the channel whose conversion result is selected to be compared.
* |[11:8] |CMPMATCNT |Compare Match Count
* | | |When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1.
* | | |When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
* |[27:16] |CMPD |Comparison Data
* | | |The 12 bits data is used to compare with conversion result of specified channel.
* | | |Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.
*/
__IO uint32_t CMPR0;
/**
* CMPR1
* ===================================================================================================
* Offset: 0x54 A/D Compare Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CMPEN |Compare Enable
* | | |0 = Compare Disabled.
* | | |1 = Compare Enabled.
* | | |Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.
* | | |When this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit
* |[1] |CMPIE |Compare Interrupt Enable
* | | |0 = Compare function interrupt Disabled.
* | | |1 = Compare function interrupt Enabled.
* | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
* |[2] |CMPCOND |Compare Condition
* | | |0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one.
* | | |1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one.
* | | |Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
* |[7:3] |CMPCH |Compare Channel Selection
* | | |This field selects the channel whose conversion result is selected to be compared.
* |[11:8] |CMPMATCNT |Compare Match Count
* | | |When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1.
* | | |When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
* |[27:16] |CMPD |Comparison Data
* | | |The 12 bits data is used to compare with conversion result of specified channel.
* | | |Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.
*/
__IO uint32_t CMPR1;
/**
* SR
* ===================================================================================================
* Offset: 0x58 A/D Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADF |A/D Conversion End Flag
* | | |A status flag that indicates the end of A/D conversion.
* | | |ADF is set to 1 at these two conditions:
* | | |When A/D conversion ends in single mode
* | | |When A/D conversion ends on all specified channels in scan mode.
* | | |This flag can be cleared by writing 1 to it.
* |[1] |CMPF0 |Compare Flag
* | | |When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1.
* | | |And it is cleared by writing 1 to self.
* | | |0 = Conversion result in ADC_RESULTx does not meet ADCMPR0setting.
* | | |1 = Conversion result in ADC_RESULTx meets ADCMPR0setting.
* | | |This flag can be cleared by writing 1 to it.
* | | |Note: When this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF0
* |[2] |CMPF1 |Compare Flag
* | | |When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1.
* | | |And it is cleared by writing 1 to self.
* | | |0 = Conversion result in ADC_RESULTx does not meet ADCMPR1 setting.
* | | |1 = Conversion result in ADC_RESULTx meets ADCMPR1 setting.
* | | |This flag can be cleared by writing 1 to it.
* | | |Note: when this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF1
* |[3] |BUSY |BUSY/IDLE
* | | |0 = A/D converter is in idle state.
* | | |1 = A/D converter is busy at conversion.
* | | |This bit is a mirror of ADST bit in ADCR. That is to say if ADST = 1,then BUSY is 1 and vice versa.
* | | |It is read only.
* |[8:4] |CHANNEL |Current Conversion Channel
* | | |This filed reflects current conversion channel when BUSY=1.
* | | |When BUSY=0, it shows the next channel to be converted.
* | | |It is read only.
* |[16] |INITRDY |ADC Power-Up Sequence Completed
* | | |0 = ADC not powered up after system reset.
* | | |1 = ADC has been powered up since the last system reset.
* | | |Note: This bit will be set after system reset occurred and automatically cleared by power-up event.
*/
__IO uint32_t SR;
uint32_t RESERVE1[1];
/**
* PDMA
* ===================================================================================================
* Offset: 0x60 A/D PDMA current transfer data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |AD_PDMA |ADC PDMA Current Transfer Data Register
* | | |When PDMA transferring, read this register can monitor current PDMA transfer data.
* | | |This is a read only register.
*/
__I uint32_t PDMA;
/**
* PWRCTL
* ===================================================================================================
* Offset: 0x64 ADC Power Management Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PWUPRDY |ADC Power-Up Sequence Completed And Ready For Conversion
* | | |0 = ADC is not ready for conversion; may be in power down state or in the progress of power up.
* | | |1 = ADC is ready for conversion.
* |[1] |PWDCALEN |Power Up Calibration Function Enable
* | | |1 = Power up with calibration.
* | | |0 = Power up without calibration.
* | | |Note: This bit work together with CALFBKSEL set 1
* |[3:2] |PWDMOD |Power-Down Mode
* | | |00 = Power down
* | | |01 = Reserved
* | | |10 = Standby mode
* | | |11 = Reserved
* | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in powe down and power up
*/
__IO uint32_t PWRCTL;
/**
* CALCTL
* ===================================================================================================
* Offset: 0x68 ADC Calibration Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CALEN |Calibration Function Enable
* | | |Enable this bit to turn on the calibration function block.
* | | |0 = Disable
* | | |1 = Enabled.
* |[1] |CALSTART |Calibration Functional Block Start
* | | |0 = Stops calibration functional block.
* | | |1 = Starts calibration functional block.
* | | |Note: This bit is set by SW and clear by HW; don't write 1 to this bit while CALEN = 0.
* |[2] |CALDONE |Calibrate Functional Block Complete
* | | |0 = Not yet.
* | | |1 = Selected functional block complete.
* |[3] |CALSEL |Select Calibration Functional Block
* | | |0 = Load calibration functional block.
* | | |1 = Calibration functional block.
*/
__IO uint32_t CALCTL;
/**
* CALWORD
* ===================================================================================================
* Offset: 0x6C A/D calibration load word register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |CALWORD |Calibration Word Register
* | | |Write to this register with the previous calibration word before load calibration action
* | | |Read this register after calibration done
* | | |Note: The calibration block contains two parts "CALIBRATION" and "LOAD CALIBRATION"; if the calibration block is config as "CALIBRATION"; then this register represent the result of calibration when calibration is completed; if config as "LOAD CALIBRATION" ; config this register before loading calibration action, after loading calibration complete, the loaded calibration word will apply to the ADC;while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.
*/
__IO uint32_t CALWORD;
/**
* SMPLCNT0
* ===================================================================================================
* Offset: 0x70 ADC Channel Sampling Time Counter Register Group 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CH0SAMPCNT|Channel 0 Sampling Counter
* | | |0000 = 0 ADC clock
* | | |0001 = 1 ADC clock
* | | |0010 = 2 ADC clocks
* | | |0011 = 4 ADC clocks
* | | |0100 = 8 ADC clocks
* | | |0101 = 16 ADC clocks
* | | |0110 = 32 ADC clocks
* | | |0111 = 64 ADC clocks
* | | |1000 = 128 ADC clocks
* | | |1001 = 256 ADC clocks
* | | |1010 = 512 ADC clocks
* | | |Others = 1024 ADC clocks
* |[7:4] |CH1SAMPCNT|Channel 1 Sampling Counter
* | | |The same as Channel 0 sampling counter table.
* |[11:8] |CH2SAMPCNT|Channel 2 Sampling Counter
* | | |The same as Channel 0 sampling counter table.
* |[15:12] |CH3SAMPCNT|Channel 3 Sampling Counter
* | | |The same as Channel 0 sampling counter table.
* |[19:16] |CH4SAMPCNT|Channel 4 Sampling Counter
* | | |The same as Channel 0 sampling counter table.
* |[23:20] |CH5SAMPCNT|Channel 5 Sampling Counter
* | | |The same as Channel 0 sampling counter table.
* |[27:24] |CH6SAMPCNT|Channel 6 Sampling Counter
* | | |The same as Channel 0 sampling counter table.
* |[31:28] |CH7SAMPCNT|Channel 7 Sampling Counter
* | | |The same as Channel 0 sampling counter table.
*/
__IO uint32_t SMPLCNT0;
/**
* SMPLCNT1
* ===================================================================================================
* Offset: 0x74 ADC Channel Sampling Time Counter Register Group 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[19:16] |INTCHSAMPCNT|Internal Channel (VTEMP, AVDD, AVSS, Int_VREF) Sampling Counter
* | | |The same as Channel 0 sampling counter table.
*/
__IO uint32_t SMPLCNT1;
} ADC_T;
/**
@addtogroup ADC_CONST ADC Bit Field Definition
Constant Definitions for ADC Controller
@{ */
#define ADC_RESULT_RSLT_Pos (0) /*!< ADC RESULT: RSLT Position */
#define ADC_RESULT_RSLT_Msk (0xffful << ADC_RESULT_RSLT_Pos) /*!< ADC RESULT: RSLT Mask */
#define ADC_RESULT_VALID_Pos (16) /*!< ADC RESULT: VALID Position */
#define ADC_RESULT_VALID_Msk (0x1ul << ADC_RESULT_VALID_Pos) /*!< ADC RESULT: VALID Mask */
#define ADC_RESULT_OVERRUN_Pos (17) /*!< ADC RESULT: OVERRUN Position */
#define ADC_RESULT_OVERRUN_Msk (0x1ul << ADC_RESULT_OVERRUN_Pos) /*!< ADC RESULT: OVERRUN Mask */
#define ADC_CR_ADEN_Pos (0) /*!< ADC CR: ADEN Position */
#define ADC_CR_ADEN_Msk (0x1ul << ADC_CR_ADEN_Pos) /*!< ADC CR: ADEN Mask */
#define ADC_CR_ADIE_Pos (1) /*!< ADC CR: ADIE Position */
#define ADC_CR_ADIE_Msk (0x1ul << ADC_CR_ADIE_Pos) /*!< ADC CR: ADIE Mask */
#define ADC_CR_ADMD_Pos (2) /*!< ADC CR: ADMD Position */
#define ADC_CR_ADMD_Msk (0x3ul << ADC_CR_ADMD_Pos) /*!< ADC CR: ADMD Mask */
#define ADC_CR_TRGS_Pos (4) /*!< ADC CR: TRGS Position */
#define ADC_CR_TRGS_Msk (0x3ul << ADC_CR_TRGS_Pos) /*!< ADC CR: TRGS Mask */
#define ADC_CR_TRGCOND_Pos (6) /*!< ADC CR: TRGCOND Position */
#define ADC_CR_TRGCOND_Msk (0x3ul << ADC_CR_TRGCOND_Pos) /*!< ADC CR: TRGCOND Mask */
#define ADC_CR_TRGE_Pos (8) /*!< ADC CR: TRGE Position */
#define ADC_CR_TRGE_Msk (0x1ul << ADC_CR_TRGE_Pos) /*!< ADC CR: TRGE Mask */
#define ADC_CR_PTEN_Pos (9) /*!< ADC CR: PTEN Position */
#define ADC_CR_PTEN_Msk (0x1ul << ADC_CR_PTEN_Pos) /*!< ADC CR: PTEN Mask */
#define ADC_CR_DIFF_Pos (10) /*!< ADC CR: DIFF Position */
#define ADC_CR_DIFF_Msk (0x1ul << ADC_CR_DIFF_Pos) /*!< ADC CR: DIFF Mask */
#define ADC_CR_ADST_Pos (11) /*!< ADC CR: ADST Position */
#define ADC_CR_ADST_Msk (0x1ul << ADC_CR_ADST_Pos) /*!< ADC CR: ADST Mask */
#define ADC_CR_TMSEL_Pos (12) /*!< ADC CR: TMSEL Position */
#define ADC_CR_TMSEL_Msk (0x3ul << ADC_CR_TMSEL_Pos) /*!< ADC CR: TMSEL Mask */
#define ADC_CR_TMTRGMOD_Pos (15) /*!< ADC CR: TMTRGMOD Position */
#define ADC_CR_TMTRGMOD_Msk (0x1ul << ADC_CR_TMTRGMOD_Pos) /*!< ADC CR: TMTRGMOD Mask */
#define ADC_CR_REFSEL_Pos (16) /*!< ADC CR: REFSEL Position */
#define ADC_CR_REFSEL_Msk (0x3ul << ADC_CR_REFSEL_Pos) /*!< ADC CR: REFSEL Mask */
#define ADC_CR_RESSEL_Pos (18) /*!< ADC CR: RESSEL Position */
#define ADC_CR_RESSEL_Msk (0x3ul << ADC_CR_RESSEL_Pos) /*!< ADC CR: RESSEL Mask */
#define ADC_CR_TMPDMACNT_Pos (24) /*!< ADC CR: TMPDMACNT Position */
#define ADC_CR_TMPDMACNT_Msk (0xfful << ADC_CR_TMPDMACNT_Pos) /*!< ADC CR: TMPDMACNT Mask */
#define ADC_CHEN_CHEN0_Pos (0) /*!< ADC CHEN: CHEN0 Position */
#define ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos) /*!< ADC CHEN: CHEN0 Mask */
#define ADC_CMPR_CMPEN_Pos (0) /*!< ADC CMPR: CMPEN Position */
#define ADC_CMPR_CMPEN_Msk (0x1ul << ADC_CMPR_CMPEN_Pos) /*!< ADC CMPR: CMPEN Mask */
#define ADC_CMPR_CMPIE_Pos (1) /*!< ADC CMPR: CMPIE Position */
#define ADC_CMPR_CMPIE_Msk (0x1ul << ADC_CMPR_CMPIE_Pos) /*!< ADC CMPR: CMPIE Mask */
#define ADC_CMPR_CMPCOND_Pos (2) /*!< ADC CMPR: CMPCOND Position */
#define ADC_CMPR_CMPCOND_Msk (0x1ul << ADC_CMPR_CMPCOND_Pos) /*!< ADC CMPR: CMPCOND Mask */
#define ADC_CMPR_CMPCH_Pos (3) /*!< ADC CMPR: CMPCH Position */
#define ADC_CMPR_CMPCH_Msk (0x1ful << ADC_CMPR_CMPCH_Pos) /*!< ADC CMPR: CMPCH Mask */
#define ADC_CMPR_CMPMATCNT_Pos (8) /*!< ADC CMPR: CMPMATCNT Position */
#define ADC_CMPR_CMPMATCNT_Msk (0xful << ADC_CMPR_CMPMATCNT_Pos) /*!< ADC CMPR: CMPMATCNT Mask */
#define ADC_CMPR_CMPD_Pos (16) /*!< ADC CMPR: CMPD Position */
#define ADC_CMPR_CMPD_Msk (0xffful << ADC_CMPR_CMPD_Pos) /*!< ADC CMPR: CMPD Mask */
#define ADC_SR_ADF_Pos (0) /*!< ADC SR: ADF Position */
#define ADC_SR_ADF_Msk (0x1ul << ADC_SR_ADF_Pos) /*!< ADC SR: ADF Mask */
#define ADC_SR_CMPF0_Pos (1) /*!< ADC SR: CMPF0 Position */
#define ADC_SR_CMPF0_Msk (0x1ul << ADC_SR_CMPF0_Pos) /*!< ADC SR: CMPF0 Mask */
#define ADC_SR_CMPF1_Pos (2) /*!< ADC SR: CMPF1 Position */
#define ADC_SR_CMPF1_Msk (0x1ul << ADC_SR_CMPF1_Pos) /*!< ADC SR: CMPF1 Mask */
#define ADC_SR_BUSY_Pos (3) /*!< ADC SR: BUSY Position */
#define ADC_SR_BUSY_Msk (0x1ul << ADC_SR_BUSY_Pos) /*!< ADC SR: BUSY Mask */
#define ADC_SR_CHANNEL_Pos (4) /*!< ADC SR: CHANNEL Position */
#define ADC_SR_CHANNEL_Msk (0x1ful << ADC_SR_CHANNEL_Pos) /*!< ADC SR: CHANNEL Mask */
#define ADC_SR_INITRDY_Pos (16) /*!< ADC SR: INITRDY Position */
#define ADC_SR_INITRDY_Msk (0x1ul << ADC_SR_INITRDY_Pos) /*!< ADC SR: INITRDY Mask */
#define ADC_PDMA_AD_PDMA_Pos (0) /*!< ADC PDMA: AD_PDMA Position */
#define ADC_PDMA_AD_PDMA_Msk (0xffful << ADC_PDMA_AD_PDMA_Pos) /*!< ADC PDMA: AD_PDMA Mask */
#define ADC_PWRCTL_PWUPRDY_Pos (0) /*!< ADC PWRCTL: PWUPRDY Position */
#define ADC_PWRCTL_PWUPRDY_Msk (0x1ul << ADC_PWRCTL_PWUPRDY_Pos) /*!< ADC PWRCTL: PWUPRDY Mask */
#define ADC_PWRCTL_PWDCALEN_Pos (1) /*!< ADC PWRCTL: PWDCALEN Position */
#define ADC_PWRCTL_PWDCALEN_Msk (0x1ul << ADC_PWRCTL_PWDCALEN_Pos) /*!< ADC PWRCTL: PWDCALEN Mask */
#define ADC_PWRCTL_PWDMOD_Pos (2) /*!< ADC PWRCTL: PWDMOD Position */
#define ADC_PWRCTL_PWDMOD_Msk (0x3ul << ADC_PWRCTL_PWDMOD_Pos) /*!< ADC PWRCTL: PWDMOD Mask */
#define ADC_CALCTL_CALEN_Pos (0) /*!< ADC CALCTL: CALEN Position */
#define ADC_CALCTL_CALEN_Msk (0x1ul << ADC_CALCTL_CALEN_Pos) /*!< ADC CALCTL: CALEN Mask */
#define ADC_CALCTL_CALSTART_Pos (1) /*!< ADC CALCTL: CALSTART Position */
#define ADC_CALCTL_CALSTART_Msk (0x1ul << ADC_CALCTL_CALSTART_Pos) /*!< ADC CALCTL: CALSTART Mask */
#define ADC_CALCTL_CALDONE_Pos (2) /*!< ADC CALCTL: CALDONE Position */
#define ADC_CALCTL_CALDONE_Msk (0x1ul << ADC_CALCTL_CALDONE_Pos) /*!< ADC CALCTL: CALDONE Mask */
#define ADC_CALCTL_CALSEL_Pos (3) /*!< ADC CALCTL: CALSEL Position */
#define ADC_CALCTL_CALSEL_Msk (0x1ul << ADC_CALCTL_CALSEL_Pos) /*!< ADC CALCTL: CALSEL Mask */
#define ADC_CALWORD_CALWORD_Pos (0) /*!< ADC CALWORD: CALWORD Position */
#define ADC_CALWORD_CALWORD_Msk (0x7ful << ADC_CALWORD_CALWORD_Pos) /*!< ADC CALWORD: CALWORD Mask */
#define ADC_SMPLCNT0_CH0SAMPCNT_Pos (0) /*!< ADC SMPLCNT0: CH0SAMPCNT Position */
#define ADC_SMPLCNT0_CH0SAMPCNT_Msk (0xful << ADC_SMPLCNT0_CH0SAMPCNT_Pos) /*!< ADC SMPLCNT0: CH0SAMPCNT Mask */
#define ADC_SMPLCNT1_CH8SAMPCNT_Pos (0) /*!< ADC SMPLCNT1: CH8SAMPCNT Position */
#define ADC_SMPLCNT1_CH8SAMPCNT_Msk (0xful << ADC_SMPLCNT1_CH8SAMPCNT_Pos) /*!< ADC SMPLCNT1: CH8SAMPCNT Mask */
#define ADC_SMPLCNT1_INTCHSAMPCNT_Pos (16) /*!< ADC SMPLCNT1: INTCHSAMPCNT Position */
#define ADC_SMPLCNT1_INTCHSAMPCNT_Msk (0xful << ADC_SMPLCNT1_INTCHSAMPCNT_Pos) /*!< ADC SMPLCNT1: INTCHSAMPCNT Mask */
/**@}*/ /* ADC_CONST */
/**@}*/ /* end of ADC register group */
/*---------------------- System Clock Controller -------------------------*/
/**
@addtogroup CLK System Clock Controller(CLK)
Memory Mapped Structure for CLK Controller
@{ */
typedef struct {
/**
* PWRCTL
* ===================================================================================================
* Offset: 0x00 System Power-down Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |HXT_EN |HXT Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |The bit default value is set by flash controller user configuration register config0 [26].
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |HXT is disabled by default.
* |[1] |LXT_EN |LXT Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |LXT is disabled by default.
* |[2] |HIRC_EN |HIRC Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |HIRC is enabled by default.
* |[3] |LIRC_EN |LIRC Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |LIRC is enabled by default.
* |[4] |WK_DLY |Wake-Up Delay Counter Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |When chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait HXT stable or 16 clock cycles to wait HIRC stable.
* | | |0 = Delay clock cycle Disabled.
* | | |1 = Delay clock cycle Enabled.
* |[5] |PD_WK_IE |Power-Down Mode Wake-Up Interrupt Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |PD_WK_INT will be set if both PD_WK_IS and PD_WK_IE are high.
* |[6] |PD_EN |Chip Power-Down Mode Enable Bit
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |When CPU sets this bit, the chip power down is enabled and chip will not enter Power-down mode until CPU sleep mode is also active.
* | | |When chip wakes up from Power-down mode, this bit will be auto cleared.
* | | |When chip is in Power-down mode, the LDO, HXT and HIRC will be disabled, but LXT and LIRC are not controlled by Power-down mode.
* | | |When power down, the PLL and system clock (CPU, HCLKx and PCLKx) are also disabled no matter the Clock Source selection.
* | | |Peripheral clocks are not controlled by this bit, if peripheral Clock Source is from LXT or LIRC.
* | | |In Power-down mode, flash macro power is ON.
* | | |0 = Chip operated in Normal mode.
* | | |1 = Chip power down Enabled.
* |[8] |HXT_SELXT |HXT SELXT
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = High frequency crystal loop back path Disabled. It is used for external oscillator.
* | | |1 = High frequency crystal loop back path Enabled. It is used for external crystal.
* |[9] |HXT_CUR_SEL|HXT Internal Current Selection
* | | |HXT has some internal current path to help crystal start-up.
* | | |However when these current path existence, HXT will consume more power.
* | | |User can use this bit to balance the start-up and power consumption.
* | | |0 = HXT current path always exists. HXT will consume more power.
* | | |For 16MHz to 24 MHz crystal.
* | | |1 = HXT current path will exist 2ms then cut down. HXT will consume less power.
* | | |For 4 MHz to 16 MHz crystal.
* |[11:10] |HXT_GAIN |HXT Gain Control Bit
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |Gain control is used to enlarge the gain of crystal to make sure crystal wok normally.
* | | |If gain control is enabled, crystal will consume more power than gain control off.
* | | |00 = HXT frequency is lower than from 8 MHz.
* | | |01 = HXT frequency is from 8 MHz to 12 MHz.
* | | |10 = HXT frequency is from 12 MHz to 16 MHz.
* | | |11 = HXT frequency is higher than 16 MHz.
* |[12] |HIRC_FSEL |HIRC Output Frequency Select
* | | |0 = HIRC will output 12MHz clock.
* | | |1 = HIRC will output 16MHz Clock.
* |[13] |HIRC_F_STOP|HIRC Stop Output When Frequency Changes
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = HIRC will continue to output when HIRC frequency changes.
* | | |1 = HIRC will suppress to output during first 16 clocks when HIRC frequency change.
*/
__IO uint32_t PWRCTL;
/**
* AHBCLK
* ===================================================================================================
* Offset: 0x04 AHB Devices Clock Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GPIO_EN |GPIO Controller Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[1] |DMA_EN |DMA Controller Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[2] |ISP_EN |Flash ISP Controller Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[4] |SRAM_EN |SRAM Controller Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[5] |TICK_EN |System Tick Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
*/
__IO uint32_t AHBCLK;
/**
* APBCLK
* ===================================================================================================
* Offset: 0x08 APB Devices Clock Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WDT_EN |Watchdog Timer Clock Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |This bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC.
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[1] |RTC_EN |Real-Time-Clock Clock Enable Control
* | | |This bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT.
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[2] |TMR0_EN |Timer0 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[3] |TMR1_EN |Timer1 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[4] |TMR2_EN |Timer2 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[5] |TMR3_EN |Timer3 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[6] |FDIV0_EN |Frequency Divider0 Output Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[7] |FDIV1_EN |Frequency Divider1 Output Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[8] |I2C0_EN |I2C0 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[9] |I2C1_EN |I2C1 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[11] |ACMP_EN |ACMP Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[12] |SPI0_EN |SPI0 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[13] |SPI1_EN |SPI1 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[16] |UART0_EN |UART0 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[17] |UART1_EN |UART1 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[20] |PWM0_CH01_EN|PWM0 Channel 0 And Channel 1Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[21] |PWM0_CH23_EN|PWM0 Channel 2 And Channel 3 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[26] |LCD_EN |LCD Controller Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[28] |ADC_EN |Analog-Digital-Converter (ADC) Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[30] |SC0_EN |SmartCard 0 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[31] |SC1_EN |SmartCard 1 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
*/
__IO uint32_t APBCLK;
/**
* CLKSTATUS
* ===================================================================================================
* Offset: 0x0C Clock status monitor Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |HXT_STB |HXT Clock Source Stable Flag
* | | |0 = HXT clock is not stable or not enable.
* | | |1 = HXT clock is stable.
* |[1] |LXT_STB |LXT Clock Source Stable Flag
* | | |0 = LXT clock is not stable or not enable.
* | | |1 = LXT clock is stable.
* |[2] |PLL_STB |PLL Clock Source Stable Flag
* | | |0 = PLL clock is not stable or not enable.
* | | |1 = PLL clock is stable.
* |[3] |LIRC_STB |LIRC Clock Source Stable Flag
* | | |0 = LIRC clock is not stable or not enable.
* | | |1 = LIRC clock is stable.
* |[4] |HIRC_STB |HIRC Clock Source Stable Flag
* | | |0 = HIRC clock is not stable or not enable.
* | | |1 = HIRC clock is stable.
* |[7] |CLK_SW_FAIL|Clock Switch Fail Flag
* | | |0 = Clock switch success.
* | | |1 = Clock switch fail.
* | | |This bit will be set when target switch Clock Source is not stable. This bit is write 1 clear
*/
__I uint32_t CLKSTATUS;
/**
* CLKSEL0
* ===================================================================================================
* Offset: 0x10 Clock Source Select Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |HCLK_S |HCLK Clock Source Selection
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |Note: Before Clock Source switches, the related clock sources (pre-select and new-select) must be turn on
* | | |The 3-bit default value is reloaded with the value of CFOSC (Config0[26:24]) in user configuration register in Flash controller by any reset.
* | | |Therefore the default value is either 000b or 111b.
* | | |000 = HXT
* | | |001 = LXT
* | | |010 = PLL Clock
* | | |011 = LIRC
* | | |111 = HIRC
* | | |Others = Reserved
*/
__IO uint32_t CLKSEL0;
/**
* CLKSEL1
* ===================================================================================================
* Offset: 0x14 Clock Source Select Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |UART_S |UART 0/1 Clock Source Selection (UART0 And UART1 Use The Same Clock Source Selection)
* | | |00 = HXT
* | | |01 = LXT
* | | |10 = PLL Clock
* | | |11 = HIRC
* |[5:4] |PWM0_CH01_S|PWM0 Channel 0 And Channel 1 Clock Source Selection
* | | |PWM0 channel 0 and channel 1 use the same Engine clock source, both of them with the same prescaler
* | | |00 = HXT
* | | |01 = LXT
* | | |10 = HCLK
* | | |11 = HIRC
* |[7:6] |PWM0_CH23_S|PWM0 Channel 2 And Channel 3 Clock Source Selection
* | | |PWM0 channel 2 and channel 3 use the same Engine clock source, both of them with the same prescaler
* | | |00 = HXT
* | | |01 = LXT
* | | |10 = HCLK
* | | |11 = HIRC
* |[10:8] |TMR0_S |Timer0 Clock Source Selection
* | | |000 = HXT
* | | |001 = LXT
* | | |010 = LIRC
* | | |011 = External Pin
* | | |100 = HIRC
* | | |Others = HCLK
* |[14:12] |TMR1_S |Timer1 Clock Source Selection
* | | |000 = HXT
* | | |001 = LXT
* | | |010 = LIRC
* | | |011 = External Pin
* | | |100 = HIRC
* | | |Others = HCLK
* |[18] |LCD_S |LCD Clock Source Selection
* | | |0 = Clock Source from LXT.
* | | |1 = Reserved.
* |[21:19] |ADC_S |ADC Clock Source Selection
* | | |000 = HXT
* | | |001 = LXT
* | | |010 = PLL clock
* | | |011 = HIRC
* | | |others = HCLK
*/
__IO uint32_t CLKSEL1;
/**
* CLKSEL2
* ===================================================================================================
* Offset: 0x18 Clock Source Select Control Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |FRQDIV1_S |Clock Divider Clock1 Source Selection
* | | |00 = HXT
* | | |01 = LXT
* | | |10 = HCLK
* | | |11 = HIRC
* |[3:2] |FRQDIV0_S |Clock Divider0 Clock Source Selection
* | | |00 = HXT
* | | |01 = LXT
* | | |10 = HCLK
* | | |11 = HIRC
* |[10:8] |TMR2_S |Timer2 Clock Source Selection
* | | |000 = HXT
* | | |001 = LXT
* | | |010 = LIRC
* | | |011 = External Pin
* | | |100 = HIRC
* | | |Others = HCLK
* |[14:12] |TMR3_S |Timer3 Clock Source Selection
* | | |000 = HXT
* | | |001 = LXT
* | | |010 = LIRC
* | | |011 = External Pin
* | | |100 = HIRC
* | | |Others = HCLK
* |[19:18] |SC_S |SC Clock Source Selection
* | | |00 = HXT
* | | |01 = PLL Clock
* | | |10 = HIRC
* | | |11 = HCLK
* |[20] |SPI0_S |SPI0 Clock Source Selection
* | | |0 = PLL.
* | | |1 = HCLK.
* |[21] |SPI1_S |SPI1 Clock Source Selection
* | | |0 = PLL.
* | | |1 = HCLK.
*/
__IO uint32_t CLKSEL2;
/**
* CLKDIV0
* ===================================================================================================
* Offset: 0x1C Clock Divider Number Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |HCLK_N |HCLK Clock Divide Number From HCLK Clock Source
* | | |The HCLK clock frequency = (HCLK Clock Source frequency) / (HCLK_N + 1).
* |[11:8] |UART_N |UART Clock Divide Number From UART Clock Source
* | | |The UART clock frequency = (UART Clock Source frequency ) / (UART_N + 1).
* |[23:16] |ADC_N |ADC Clock Divide Number From ADC Clock Source
* | | |The ADC clock frequency = (ADC Clock Source frequency ) / (ADC_N + 1).
* |[31:28] |SC0_N |SC 0 Clock Divide Number From SC 0 Clock Source
* | | |The SC 0 clock frequency = (SC0 Clock Source frequency ) / (SC0_N + 1).
*/
__IO uint32_t CLKDIV0;
/**
* CLKDIV1
* ===================================================================================================
* Offset: 0x20 Clock Divider Number Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |SC1_N |SC 1 Clock Divide Number From SC 1 Clock Source
* | | |The SC 1 clock frequency = (SC 1 Clock Source frequency ) / (SC1_N + 1).
* |[11:8] |TMR0_N |Timer0 Clock Divide Number From Timer0 Clock Source
* | | |The Timer0 clock frequency = (Timer0 Clock Source frequency ) / (TMR0_N + 1).
* |[15:12] |TMR1_N |Timer1 Clock Divide Number From Timer1 Clock Source
* | | |The Timer1 clock frequency = (Timer1 Clock Source frequency ) / (TMR1_N + 1).
* |[19:16] |TMR2_N |Timer2 Clock Divide Number From Timer2 Clock Source
* | | |The Timer2 clock frequency = (Timer2 Clock Source frequency ) / (TMR2_N + 1).
* |[23:20] |TMR3_N |Timer3 Clock Divide Number From Timer3 Clock Source
* | | |The Timer3 clock frequency = (Timer3 Clock Source frequency ) / (TMR3_N + 1).
*/
__IO uint32_t CLKDIV1;
/**
* PLLCTL
* ===================================================================================================
* Offset: 0x24 PLL Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |PLL_MLP |PLL Multiple
* | | |000000: Reserved
* | | |000001: X1
* | | |000010: X2
* | | |000011: X3
* | | |000100: X4
* | | |...
* | | |010000:X16
* | | |...
* | | |100000: X32
* | | |0thers: Reserved
* | | |PLL output frequency: PLL input frequency * PLL_MLP.
* | | |PLL output frequency range: 16MHz ~ 32MHz
* |[11:8] |PLL_SRC_N |PLL Input Source Divider
* | | |The PLL input clock frequency = (PLL Clock Source frequency ) / (PLL_SRC_N + 1).
* | | |PLL input clock frequency range: 0.8MHz ~ 2MHz
* |[16] |PD |Power-Down Mode
* | | |If set the PD_EN bit "1" in PWR_CTL register, the PLL will enter Power-down mode too
* | | |0 = PLL is in normal mode.
* | | |1 = PLL is in power-down mode (default).
* |[17] |PLL_SRC |PLL Source Clock Select
* | | |0 = PLL source clock from HXT.
* | | |1 = PLL source clock from HIRC.
*/
__IO uint32_t PLLCTL;
/**
* FRQDIV0
* ===================================================================================================
* Offset: 0x28 Frequency Divider0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |FSEL |Divider Output Frequency Selection Bits
* | | |The formula of output frequency is
* | | |FCLK0 = FRQDIV0_CLK/2^(N+1),.
* | | |Where FRQDIV0_CLK is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL[3:0].
* |[4] |FDIV_EN |Frequency Divider Enable Bit
* | | |0 = Frequency Divider Disabled.
* | | |1 = Frequency Divider Enabled.
* |[5] |DIV1 |Output Frequency Divide By 1
* | | |0 = Output frequency is equal to FCLK0.
* | | |1 = Output frequency is equal to FRQDIV0_CLK.
*/
__IO uint32_t FRQDIV0;
uint32_t RESERVE0[1];
/**
* WK_INTSTS
* ===================================================================================================
* Offset: 0x30 Wake-up Interrupt Status
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PD_WK_IS |Wake-Up Interrupt Status In Chip Power-Down Mode
* | | |This bit indicates that some event resumes chip from Power-down mode
* | | |The status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred.
* | | |Write 1 to clear this bit.
*/
__IO uint32_t WK_INTSTS;
/**
* APB_DIV
* ===================================================================================================
* Offset: 0x34 APB Clock Divider
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |APBDIV |APB Clock Divider
* | | |APB PCLK can be divided from HCLK.
* | | |000: PCLK = HCLK.
* | | |001: PCLK =1/2 HCLK.
* | | |010: PCLK = 1/4 HCLK.
* | | |011: PCLK = 1/8 HCLK.
* | | |100: PCLK = 1/16 HCLK.
* | | |Others: PCLK = HCLK.
*/
__IO uint32_t APB_DIV;
/**
* FRQDIV1
* ===================================================================================================
* Offset: 0x38 Frequency Divider1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |FSEL |Divider Output Frequency Selection Bits
* | | |The formula of output frequency is
* | | |FCLK1 = FRQDIV1_CLK /2^(N+1),.
* | | |Where FRQDIV1_CLK is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL[3:0].
* |[4] |FDIV_EN |Frequency Divider Enable Bit
* | | |0 = Frequency Divider Disabled.
* | | |1 = Frequency Divider Enabled.
* |[5] |DIV1 |Output Frequency Divide By 1
* | | |0 = Output frequency is equal to FCLK1.
* | | |1 = Output frequency is equal to FRQDIV1_CLK.
*/
__IO uint32_t FRQDIV1;
/**
* SP_DET
* ===================================================================================================
* Offset: 0x3C Clock Stop Detect Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |HCLK_DET |HCLK Stop Detect Enable Control
* | | |0 = HCLK stop detect Disabled.
* | | |1 = HCLK stop detect Enabled.
* | | |Once HCLK stop detected, hardware will force HCLK from LIRC.
* |[1] |HCLK_STOP_IE|HCLK Stop Detect Interrupt Enable Control
* | | |0 = HCLK stop detect interrupt Disabled.
* | | |1 = HCLK stop detect interrupt Enabled.
* |[2] |HXT_DET |HXT Stop Detect Enable Control
* | | |0 = HXT stop detect Disabled.
* | | |1 = HXT stop detect Enabled.
* |[3] |HXT_STOP_IE|HXT Stop Detect Interrupt Enable Control
* | | |0 = HXT stop detect interrupt Disabled.
* | | |1 = HXT stop detect interrupt Enabled.
* |[4] |HIRC_DET |HIRC Stop Detect Enable Control
* | | |0 = HIRC stop detect Disabled.
* | | |1 = HIRC stop detect Enabled.
* |[5] |HIRC_STOP_IE|HIRC Stop Detect Interrupt Enable Control
* | | |0 = HIRC stop detect interrupt Disabled.
* | | |1 = HIRC stop detect interrupt Enabled.
*/
__IO uint32_t SP_DET;
/**
* SP_STS
* ===================================================================================================
* Offset: 0x40 Clock Stop Detect Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |HCLK_SP_IS|HCLK Clock Stop Flag
* | | |0 = HCLK normal.
* | | |1 = HCLK abnormal.
* |[2] |HXT_SP_IS |HXT Stop Flag
* | | |0 = HXT normal.
* | | |1 = HXT abnormal.
* |[4] |HIRC_SP_IS|HIRC Stop Flag
* | | |0 = HIRC normal.
* | | |1 = HIRC abnormal.
* |[10:8] |HCLK_SEL |HCLK Target Clock Select
* | | |000 = HXT
* | | |001 = LXT
* | | |010 = PLL Clock
* | | |011 = LIRC
* | | |111 = HIRC
* | | |Others = Reserved
*/
__I uint32_t SP_STS;
} CLK_T;
/**
@addtogroup CLK_CONST CLK Bit Field Definition
Constant Definitions for CLK Controller
@{ */
#define CLK_PWRCTL_HXT_EN_Pos (0) /*!< CLK PWRCTL: HXT_EN Position */
#define CLK_PWRCTL_HXT_EN_Msk (0x1ul << CLK_PWRCTL_HXT_EN_Pos) /*!< CLK PWRCTL: HXT_EN Mask */
#define CLK_PWRCTL_LXT_EN_Pos (1) /*!< CLK PWRCTL: LXT_EN Position */
#define CLK_PWRCTL_LXT_EN_Msk (0x1ul << CLK_PWRCTL_LXT_EN_Pos) /*!< CLK PWRCTL: LXT_EN Mask */
#define CLK_PWRCTL_HIRC_EN_Pos (2) /*!< CLK PWRCTL: HIRC_EN Position */
#define CLK_PWRCTL_HIRC_EN_Msk (0x1ul << CLK_PWRCTL_HIRC_EN_Pos) /*!< CLK PWRCTL: HIRC_EN Mask */
#define CLK_PWRCTL_LIRC_EN_Pos (3) /*!< CLK PWRCTL: LIRC_EN Position */
#define CLK_PWRCTL_LIRC_EN_Msk (0x1ul << CLK_PWRCTL_LIRC_EN_Pos) /*!< CLK PWRCTL: LIRC_EN Mask */
#define CLK_PWRCTL_WK_DLY_Pos (4) /*!< CLK PWRCTL: WK_DLY Position */
#define CLK_PWRCTL_WK_DLY_Msk (0x1ul << CLK_PWRCTL_WK_DLY_Pos) /*!< CLK PWRCTL: WK_DLY Mask */
#define CLK_PWRCTL_PD_WK_IE_Pos (5) /*!< CLK PWRCTL: PD_WK_IE Position */
#define CLK_PWRCTL_PD_WK_IE_Msk (0x1ul << CLK_PWRCTL_PD_WK_IE_Pos) /*!< CLK PWRCTL: PD_WK_IE Mask */
#define CLK_PWRCTL_PD_EN_Pos (6) /*!< CLK PWRCTL: PD_EN Position */
#define CLK_PWRCTL_PD_EN_Msk (0x1ul << CLK_PWRCTL_PD_EN_Pos) /*!< CLK PWRCTL: PD_EN Mask */
#define CLK_PWRCTL_HXT_SELXT_Pos (8) /*!< CLK PWRCTL: HXT_SELXT Position */
#define CLK_PWRCTL_HXT_SELXT_Msk (0x1ul << CLK_PWRCTL_HXT_SELXT_Pos) /*!< CLK PWRCTL: HXT_SELXT Mask */
#define CLK_PWRCTL_HXT_CUR_SEL_Pos (9) /*!< CLK PWRCTL: HXT_CUR_SEL Position */
#define CLK_PWRCTL_HXT_CUR_SEL_Msk (0x1ul << CLK_PWRCTL_HXT_CUR_SEL_Pos) /*!< CLK PWRCTL: HXT_CUR_SEL Mask */
#define CLK_PWRCTL_HXT_GAIN_Pos (10) /*!< CLK PWRCTL: HXT_GAIN Position */
#define CLK_PWRCTL_HXT_GAIN_Msk (0x3ul << CLK_PWRCTL_HXT_GAIN_Pos) /*!< CLK PWRCTL: HXT_GAIN Mask */
#define CLK_PWRCTL_HIRC_FSEL_Pos (12) /*!< CLK PWRCTL: HIRC_FSEL Position */
#define CLK_PWRCTL_HIRC_FSEL_Msk (0x1ul << CLK_PWRCTL_HIRC_FSEL_Pos) /*!< CLK PWRCTL: HIRC_FSEL Mask */
#define CLK_PWRCTL_HIRC_F_STOP_Pos (13) /*!< CLK PWRCTL: HIRC_F_STOP Position */
#define CLK_PWRCTL_HIRC_F_STOP_Msk (0x1ul << CLK_PWRCTL_HIRC_F_STOP_Pos) /*!< CLK PWRCTL: HIRC_F_STOP Mask */
#define CLK_AHBCLK_GPIO_EN_Pos (0) /*!< CLK AHBCLK: GPIO_EN Position */
#define CLK_AHBCLK_GPIO_EN_Msk (0x1ul << CLK_AHBCLK_GPIO_EN_Pos) /*!< CLK AHBCLK: GPIO_EN Mask */
#define CLK_AHBCLK_DMA_EN_Pos (1) /*!< CLK AHBCLK: DMA_EN Position */
#define CLK_AHBCLK_DMA_EN_Msk (0x1ul << CLK_AHBCLK_DMA_EN_Pos) /*!< CLK AHBCLK: DMA_EN Mask */
#define CLK_AHBCLK_ISP_EN_Pos (2) /*!< CLK AHBCLK: ISP_EN Position */
#define CLK_AHBCLK_ISP_EN_Msk (0x1ul << CLK_AHBCLK_ISP_EN_Pos) /*!< CLK AHBCLK: ISP_EN Mask */
#define CLK_AHBCLK_SRAM_EN_Pos (4) /*!< CLK AHBCLK: SRAM_EN Position */
#define CLK_AHBCLK_SRAM_EN_Msk (0x1ul << CLK_AHBCLK_SRAM_EN_Pos) /*!< CLK AHBCLK: SRAM_EN Mask */
#define CLK_AHBCLK_TICK_EN_Pos (5) /*!< CLK AHBCLK: TICK_EN Position */
#define CLK_AHBCLK_TICK_EN_Msk (0x1ul << CLK_AHBCLK_TICK_EN_Pos) /*!< CLK AHBCLK: TICK_EN Mask */
#define CLK_APBCLK_WDT_EN_Pos (0) /*!< CLK APBCLK: WDT_EN Position */
#define CLK_APBCLK_WDT_EN_Msk (0x1ul << CLK_APBCLK_WDT_EN_Pos) /*!< CLK APBCLK: WDT_EN Mask */
#define CLK_APBCLK_RTC_EN_Pos (1) /*!< CLK APBCLK: RTC_EN Position */
#define CLK_APBCLK_RTC_EN_Msk (0x1ul << CLK_APBCLK_RTC_EN_Pos) /*!< CLK APBCLK: RTC_EN Mask */
#define CLK_APBCLK_TMR0_EN_Pos (2) /*!< CLK APBCLK: TMR0_EN Position */
#define CLK_APBCLK_TMR0_EN_Msk (0x1ul << CLK_APBCLK_TMR0_EN_Pos) /*!< CLK APBCLK: TMR0_EN Mask */
#define CLK_APBCLK_TMR1_EN_Pos (3) /*!< CLK APBCLK: TMR1_EN Position */
#define CLK_APBCLK_TMR1_EN_Msk (0x1ul << CLK_APBCLK_TMR1_EN_Pos) /*!< CLK APBCLK: TMR1_EN Mask */
#define CLK_APBCLK_TMR2_EN_Pos (4) /*!< CLK APBCLK: TMR2_EN Position */
#define CLK_APBCLK_TMR2_EN_Msk (0x1ul << CLK_APBCLK_TMR2_EN_Pos) /*!< CLK APBCLK: TMR2_EN Mask */
#define CLK_APBCLK_TMR3_EN_Pos (5) /*!< CLK APBCLK: TMR3_EN Position */
#define CLK_APBCLK_TMR3_EN_Msk (0x1ul << CLK_APBCLK_TMR3_EN_Pos) /*!< CLK APBCLK: TMR3_EN Mask */
#define CLK_APBCLK_FDIV0_EN_Pos (6) /*!< CLK APBCLK: FDIV0_EN Position */
#define CLK_APBCLK_FDIV0_EN_Msk (0x1ul << CLK_APBCLK_FDIV0_EN_Pos) /*!< CLK APBCLK: FDIV0_EN Mask */
#define CLK_APBCLK_FDIV1_EN_Pos (7) /*!< CLK APBCLK: FDIV1_EN Position */
#define CLK_APBCLK_FDIV1_EN_Msk (0x1ul << CLK_APBCLK_FDIV1_EN_Pos) /*!< CLK APBCLK: FDIV1_EN Mask */
#define CLK_APBCLK_I2C0_EN_Pos (8) /*!< CLK APBCLK: I2C0_EN Position */
#define CLK_APBCLK_I2C0_EN_Msk (0x1ul << CLK_APBCLK_I2C0_EN_Pos) /*!< CLK APBCLK: I2C0_EN Mask */
#define CLK_APBCLK_I2C1_EN_Pos (9) /*!< CLK APBCLK: I2C1_EN Position */
#define CLK_APBCLK_I2C1_EN_Msk (0x1ul << CLK_APBCLK_I2C1_EN_Pos) /*!< CLK APBCLK: I2C1_EN Mask */
#define CLK_APBCLK_ACMP_EN_Pos (11) /*!< CLK APBCLK: ACMP_EN Position */
#define CLK_APBCLK_ACMP_EN_Msk (0x1ul << CLK_APBCLK_ACMP_EN_Pos) /*!< CLK APBCLK: ACMP_EN Mask */
#define CLK_APBCLK_SPI0_EN_Pos (12) /*!< CLK APBCLK: SPI0_EN Position */
#define CLK_APBCLK_SPI0_EN_Msk (0x1ul << CLK_APBCLK_SPI0_EN_Pos) /*!< CLK APBCLK: SPI0_EN Mask */
#define CLK_APBCLK_SPI1_EN_Pos (13) /*!< CLK APBCLK: SPI1_EN Position */
#define CLK_APBCLK_SPI1_EN_Msk (0x1ul << CLK_APBCLK_SPI1_EN_Pos) /*!< CLK APBCLK: SPI1_EN Mask */
#define CLK_APBCLK_UART0_EN_Pos (16) /*!< CLK APBCLK: UART0_EN Position */
#define CLK_APBCLK_UART0_EN_Msk (0x1ul << CLK_APBCLK_UART0_EN_Pos) /*!< CLK APBCLK: UART0_EN Mask */
#define CLK_APBCLK_UART1_EN_Pos (17) /*!< CLK APBCLK: UART1_EN Position */
#define CLK_APBCLK_UART1_EN_Msk (0x1ul << CLK_APBCLK_UART1_EN_Pos) /*!< CLK APBCLK: UART1_EN Mask */
#define CLK_APBCLK_PWM0_CH01_EN_Pos (20) /*!< CLK APBCLK: PWM0_CH01_EN Position */
#define CLK_APBCLK_PWM0_CH01_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH01_EN_Pos) /*!< CLK APBCLK: PWM0_CH01_EN Mask */
#define CLK_APBCLK_PWM0_CH23_EN_Pos (21) /*!< CLK APBCLK: PWM0_CH23_EN Position */
#define CLK_APBCLK_PWM0_CH23_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH23_EN_Pos) /*!< CLK APBCLK: PWM0_CH23_EN Mask */
#define CLK_APBCLK_LCD_EN_Pos (26) /*!< CLK APBCLK: LCD_EN Position */
#define CLK_APBCLK_LCD_EN_Msk (0x1ul << CLK_APBCLK_LCD_EN_Pos) /*!< CLK APBCLK: LCD_EN Mask */
#define CLK_APBCLK_ADC_EN_Pos (28) /*!< CLK APBCLK: ADC_EN Position */
#define CLK_APBCLK_ADC_EN_Msk (0x1ul << CLK_APBCLK_ADC_EN_Pos) /*!< CLK APBCLK: ADC_EN Mask */
#define CLK_APBCLK_SC0_EN_Pos (30) /*!< CLK APBCLK: SC0_EN Position */
#define CLK_APBCLK_SC0_EN_Msk (0x1ul << CLK_APBCLK_SC0_EN_Pos) /*!< CLK APBCLK: SC0_EN Mask */
#define CLK_APBCLK_SC1_EN_Pos (31) /*!< CLK APBCLK: SC1_EN Position */
#define CLK_APBCLK_SC1_EN_Msk (0x1ul << CLK_APBCLK_SC1_EN_Pos) /*!< CLK APBCLK: SC1_EN Mask */
#define CLK_CLKSTATUS_HXT_STB_Pos (0) /*!< CLK CLKSTATUS: HXT_STB Position */
#define CLK_CLKSTATUS_HXT_STB_Msk (0x1ul << CLK_CLKSTATUS_HXT_STB_Pos) /*!< CLK CLKSTATUS: HXT_STB Mask */
#define CLK_CLKSTATUS_LXT_STB_Pos (1) /*!< CLK CLKSTATUS: LXT_STB Position */
#define CLK_CLKSTATUS_LXT_STB_Msk (0x1ul << CLK_CLKSTATUS_LXT_STB_Pos) /*!< CLK CLKSTATUS: LXT_STB Mask */
#define CLK_CLKSTATUS_PLL_STB_Pos (2) /*!< CLK CLKSTATUS: PLL_STB Position */
#define CLK_CLKSTATUS_PLL_STB_Msk (0x1ul << CLK_CLKSTATUS_PLL_STB_Pos) /*!< CLK CLKSTATUS: PLL_STB Mask */
#define CLK_CLKSTATUS_LIRC_STB_Pos (3) /*!< CLK CLKSTATUS: LIRC_STB Position */
#define CLK_CLKSTATUS_LIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_LIRC_STB_Pos) /*!< CLK CLKSTATUS: LIRC_STB Mask */
#define CLK_CLKSTATUS_HIRC_STB_Pos (4) /*!< CLK CLKSTATUS: HIRC_STB Position */
#define CLK_CLKSTATUS_HIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_HIRC_STB_Pos) /*!< CLK CLKSTATUS: HIRC_STB Mask */
#define CLK_CLKSTATUS_CLK_SW_FAIL_Pos (7) /*!< CLK CLKSTATUS: CLK_SW_FAIL Position */
#define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (0x1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos) /*!< CLK CLKSTATUS: CLK_SW_FAIL Mask */
#define CLK_CLKSEL0_HCLK_S_Pos (0) /*!< CLK CLKSEL0: HCLK_S Position */
#define CLK_CLKSEL0_HCLK_S_Msk (0x7ul << CLK_CLKSEL0_HCLK_S_Pos) /*!< CLK CLKSEL0: HCLK_S Mask */
#define CLK_CLKSEL1_UART_S_Pos (0) /*!< CLK CLKSEL1: UART_S Position */
#define CLK_CLKSEL1_UART_S_Msk (0x3ul << CLK_CLKSEL1_UART_S_Pos) /*!< CLK CLKSEL1: UART_S Mask */
#define CLK_CLKSEL1_PWM0_CH01_S_Pos (4) /*!< CLK CLKSEL1: PWM0_CH01_S Position */
#define CLK_CLKSEL1_PWM0_CH01_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!< CLK CLKSEL1: PWM0_CH01_S Mask */
#define CLK_CLKSEL1_PWM0_CH23_S_Pos (6) /*!< CLK CLKSEL1: PWM0_CH23_S Position */
#define CLK_CLKSEL1_PWM0_CH23_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!< CLK CLKSEL1: PWM0_CH23_S Mask */
#define CLK_CLKSEL1_TMR0_S_Pos (8) /*!< CLK CLKSEL1: TMR0_S Position */
#define CLK_CLKSEL1_TMR0_S_Msk (0x7ul << CLK_CLKSEL1_TMR0_S_Pos) /*!< CLK CLKSEL1: TMR0_S Mask */
#define CLK_CLKSEL1_TMR1_S_Pos (12) /*!< CLK CLKSEL1: TMR1_S Position */
#define CLK_CLKSEL1_TMR1_S_Msk (0x7ul << CLK_CLKSEL1_TMR1_S_Pos) /*!< CLK CLKSEL1: TMR1_S Mask */
#define CLK_CLKSEL1_LCD_S_Pos (18) /*!< CLK CLKSEL1: LCD_S Position */
#define CLK_CLKSEL1_LCD_S_Msk (0x1ul << CLK_CLKSEL1_LCD_S_Pos) /*!< CLK CLKSEL1: LCD_S Mask */
#define CLK_CLKSEL1_ADC_S_Pos (19) /*!< CLK CLKSEL1: ADC_S Position */
#define CLK_CLKSEL1_ADC_S_Msk (0x7ul << CLK_CLKSEL1_ADC_S_Pos) /*!< CLK CLKSEL1: ADC_S Mask */
#define CLK_CLKSEL2_FRQDIV1_S_Pos (0) /*!< CLK CLKSEL2: FRQDIV1_S Position */
#define CLK_CLKSEL2_FRQDIV1_S_Msk (0x3ul << CLK_CLKSEL2_FRQDIV1_S_Pos) /*!< CLK CLKSEL2: FRQDIV1_S Mask */
#define CLK_CLKSEL2_FRQDIV0_S_Pos (2) /*!< CLK CLKSEL2: FRQDIV0_S Position */
#define CLK_CLKSEL2_FRQDIV0_S_Msk (0x3ul << CLK_CLKSEL2_FRQDIV0_S_Pos) /*!< CLK CLKSEL2: FRQDIV0_S Mask */
#define CLK_CLKSEL2_TMR2_S_Pos (8) /*!< CLK CLKSEL2: TMR2_S Position */
#define CLK_CLKSEL2_TMR2_S_Msk (0x7ul << CLK_CLKSEL2_TMR2_S_Pos) /*!< CLK CLKSEL2: TMR2_S Mask */
#define CLK_CLKSEL2_TMR3_S_Pos (12) /*!< CLK CLKSEL2: TMR3_S Position */
#define CLK_CLKSEL2_TMR3_S_Msk (0x7ul << CLK_CLKSEL2_TMR3_S_Pos) /*!< CLK CLKSEL2: TMR3_S Mask */
#define CLK_CLKSEL2_SC_S_Pos (18) /*!< CLK CLKSEL2: SC_S Position */
#define CLK_CLKSEL2_SC_S_Msk (0x3ul << CLK_CLKSEL2_SC_S_Pos) /*!< CLK CLKSEL2: SC_S Mask */
#define CLK_CLKSEL2_SPI0_S_Pos (20) /*!< CLK CLKSEL2: SPI0_S Position */
#define CLK_CLKSEL2_SPI0_S_Msk (0x1ul << CLK_CLKSEL2_SPI0_S_Pos) /*!< CLK CLKSEL2: SPI0_S Mask */
#define CLK_CLKSEL2_SPI1_S_Pos (21) /*!< CLK CLKSEL2: SPI1_S Position */
#define CLK_CLKSEL2_SPI1_S_Msk (0x1ul << CLK_CLKSEL2_SPI1_S_Pos) /*!< CLK CLKSEL2: SPI1_S Mask */
#define CLK_CLKDIV0_HCLK_N_Pos (0) /*!< CLK CLKDIV0: HCLK_N Position */
#define CLK_CLKDIV0_HCLK_N_Msk (0xful << CLK_CLKDIV0_HCLK_N_Pos) /*!< CLK CLKDIV0: HCLK_N Mask */
#define CLK_CLKDIV0_UART_N_Pos (8) /*!< CLK CLKDIV0: UART_N Position */
#define CLK_CLKDIV0_UART_N_Msk (0xful << CLK_CLKDIV0_UART_N_Pos) /*!< CLK CLKDIV0: UART_N Mask */
#define CLK_CLKDIV0_ADC_N_Pos (16) /*!< CLK CLKDIV0: ADC_N Position */
#define CLK_CLKDIV0_ADC_N_Msk (0xfful << CLK_CLKDIV0_ADC_N_Pos) /*!< CLK CLKDIV0: ADC_N Mask */
#define CLK_CLKDIV0_SC0_N_Pos (28) /*!< CLK CLKDIV0: SC0_N Position */
#define CLK_CLKDIV0_SC0_N_Msk (0xful << CLK_CLKDIV0_SC0_N_Pos) /*!< CLK CLKDIV0: SC0_N Mask */
#define CLK_CLKDIV1_SC1_N_Pos (0) /*!< CLK CLKDIV1: SC1_N Position */
#define CLK_CLKDIV1_SC1_N_Msk (0xful << CLK_CLKDIV1_SC1_N_Pos) /*!< CLK CLKDIV1: SC1_N Mask */
#define CLK_CLKDIV1_TMR0_N_Pos (8) /*!< CLK CLKDIV1: TMR0_N Position */
#define CLK_CLKDIV1_TMR0_N_Msk (0xful << CLK_CLKDIV1_TMR0_N_Pos) /*!< CLK CLKDIV1: TMR0_N Mask */
#define CLK_CLKDIV1_TMR1_N_Pos (12) /*!< CLK CLKDIV1: TMR1_N Position */
#define CLK_CLKDIV1_TMR1_N_Msk (0xful << CLK_CLKDIV1_TMR1_N_Pos) /*!< CLK CLKDIV1: TMR1_N Mask */
#define CLK_CLKDIV1_TMR2_N_Pos (16) /*!< CLK CLKDIV1: TMR2_N Position */
#define CLK_CLKDIV1_TMR2_N_Msk (0xful << CLK_CLKDIV1_TMR2_N_Pos) /*!< CLK CLKDIV1: TMR2_N Mask */
#define CLK_CLKDIV1_TMR3_N_Pos (20) /*!< CLK CLKDIV1: TMR3_N Position */
#define CLK_CLKDIV1_TMR3_N_Msk (0xful << CLK_CLKDIV1_TMR3_N_Pos) /*!< CLK CLKDIV1: TMR3_N Mask */
#define CLK_PLLCTL_PLL_MLP_Pos (0) /*!< CLK PLLCTL: PLL_MLP Position */
#define CLK_PLLCTL_PLL_MLP_Msk (0x3ful << CLK_PLLCTL_PLL_MLP_Pos) /*!< CLK PLLCTL: PLL_MLP Mask */
#define CLK_PLLCTL_PLL_SRC_N_Pos (8) /*!< CLK PLLCTL: PLL_SRC_N Position */
#define CLK_PLLCTL_PLL_SRC_N_Msk (0xful << CLK_PLLCTL_PLL_SRC_N_Pos) /*!< CLK PLLCTL: PLL_SRC_N Mask */
#define CLK_PLLCTL_PD_Pos (16) /*!< CLK PLLCTL: PD Position */
#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK PLLCTL: PD Mask */
#define CLK_PLLCTL_PLL_SRC_Pos (17) /*!< CLK PLLCTL: PLL_SRC Position */
#define CLK_PLLCTL_PLL_SRC_Msk (0x1ul << CLK_PLLCTL_PLL_SRC_Pos) /*!< CLK PLLCTL: PLL_SRC Mask */
#define CLK_FRQDIV0_FSEL_Pos (0) /*!< CLK FRQDIV0: FSEL Position */
#define CLK_FRQDIV0_FSEL_Msk (0xful << CLK_FRQDIV0_FSEL_Pos) /*!< CLK FRQDIV0: FSEL Mask */
#define CLK_FRQDIV0_FDIV_EN_Pos (4) /*!< CLK FRQDIV0: FDIV_EN Position */
#define CLK_FRQDIV0_FDIV_EN_Msk (0x1ul << CLK_FRQDIV0_FDIV_EN_Pos) /*!< CLK FRQDIV0: FDIV_EN Mask */
#define CLK_FRQDIV0_DIV1_Pos (5) /*!< CLK FRQDIV0: DIV1 Position */
#define CLK_FRQDIV0_DIV1_Msk (0x1ul << CLK_FRQDIV0_DIV1_Pos) /*!< CLK FRQDIV0: DIV1 Mask */
#define CLK_WK_INTSTS_PD_WK_IS_Pos (0) /*!< CLK WK_INTSTS: PD_WK_IS Position */
#define CLK_WK_INTSTS_PD_WK_IS_Msk (0x1ul << CLK_WK_INTSTS_PD_WK_IS_Pos) /*!< CLK WK_INTSTS: PD_WK_IS Mask */
#define CLK_APB_DIV_APBDIV_Pos (0) /*!< CLK APB_DIV: APBDIV Position */
#define CLK_APB_DIV_APBDIV_Msk (0x7ul << CLK_APB_DIV_APBDIV_Pos) /*!< CLK APB_DIV: APBDIV Mask */
#define CLK_FRQDIV1_FSEL_Pos (0) /*!< CLK FRQDIV1: FSEL Position */
#define CLK_FRQDIV1_FSEL_Msk (0xful << CLK_FRQDIV1_FSEL_Pos) /*!< CLK FRQDIV1: FSEL Mask */
#define CLK_FRQDIV1_FDIV_EN_Pos (4) /*!< CLK FRQDIV1: FDIV_EN Position */
#define CLK_FRQDIV1_FDIV_EN_Msk (0x1ul << CLK_FRQDIV1_FDIV_EN_Pos) /*!< CLK FRQDIV1: FDIV_EN Mask */
#define CLK_FRQDIV1_DIV1_Pos (5) /*!< CLK FRQDIV1: DIV1 Position */
#define CLK_FRQDIV1_DIV1_Msk (0x1ul << CLK_FRQDIV1_DIV1_Pos) /*!< CLK FRQDIV1: DIV1 Mask */
#define CLK_SP_DET_HCLK_DET_Pos (0) /*!< CLK SP_DET: HCLK_DET Position */
#define CLK_SP_DET_HCLK_DET_Msk (0x1ul << CLK_SP_DET_HCLK_DET_Pos) /*!< CLK SP_DET: HCLK_DET Mask */
#define CLK_SP_DET_HCLK_STOP_IE_Pos (1) /*!< CLK SP_DET: HCLK_STOP_IE Position */
#define CLK_SP_DET_HCLK_STOP_IE_Msk (0x1ul << CLK_SP_DET_HCLK_STOP_IE_Pos) /*!< CLK SP_DET: HCLK_STOP_IE Mask */
#define CLK_SP_DET_HXT_DET_Pos (2) /*!< CLK SP_DET: HXT_DET Position */
#define CLK_SP_DET_HXT_DET_Msk (0x1ul << CLK_SP_DET_HXT_DET_Pos) /*!< CLK SP_DET: HXT_DET Mask */
#define CLK_SP_DET_HXT_STOP_IE_Pos (3) /*!< CLK SP_DET: HXT_STOP_IE Position */
#define CLK_SP_DET_HXT_STOP_IE_Msk (0x1ul << CLK_SP_DET_HXT_STOP_IE_Pos) /*!< CLK SP_DET: HXT_STOP_IE Mask */
#define CLK_SP_DET_HIRC_DET_Pos (4) /*!< CLK SP_DET: HIRC_DET Position */
#define CLK_SP_DET_HIRC_DET_Msk (0x1ul << CLK_SP_DET_HIRC_DET_Pos) /*!< CLK SP_DET: HIRC_DET Mask */
#define CLK_SP_DET_HIRC_STOP_IE_Pos (5) /*!< CLK SP_DET: HIRC_STOP_IE Position */
#define CLK_SP_DET_HIRC_STOP_IE_Msk (0x1ul << CLK_SP_DET_HIRC_STOP_IE_Pos) /*!< CLK SP_DET: HIRC_STOP_IE Mask */
#define CLK_SP_STS_HCLK_SP_IS_Pos (0) /*!< CLK SP_STS: HCLK_SP_IS Position */
#define CLK_SP_STS_HCLK_SP_IS_Msk (0x1ul << CLK_SP_STS_HCLK_SP_IS_Pos) /*!< CLK SP_STS: HCLK_SP_IS Mask */
#define CLK_SP_STS_HXT_SP_IS_Pos (2) /*!< CLK SP_STS: HXT_SP_IS Position */
#define CLK_SP_STS_HXT_SP_IS_Msk (0x1ul << CLK_SP_STS_HXT_SP_IS_Pos) /*!< CLK SP_STS: HXT_SP_IS Mask */
#define CLK_SP_STS_HIRC_SP_IS_Pos (4) /*!< CLK SP_STS: HIRC_SP_IS Position */
#define CLK_SP_STS_HIRC_SP_IS_Msk (0x1ul << CLK_SP_STS_HIRC_SP_IS_Pos) /*!< CLK SP_STS: HIRC_SP_IS Mask */
#define CLK_SP_STS_HCLK_SEL_Pos (8) /*!< CLK SP_STS: HCLK_SEL Position */
#define CLK_SP_STS_HCLK_SEL_Msk (0x7ul << CLK_SP_STS_HCLK_SEL_Pos) /*!< CLK SP_STS: HCLK_SEL Mask */
/**@}*/ /* CLK_CONST */
/**@}*/ /* end of CLK register group */
/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
/**
@addtogroup DMA Direct Memory Access Controller(DMA)
Memory Mapped Structure for DMA Controller
@{ */
typedef struct {
/**
* CTL
* ===================================================================================================
* Offset: 0x00 DMA CRC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRCCEN |CRC Channel Enable
* | | |Setting this bit to 1 enables CRC's operation.
* | | |When operating in CRC DMA mode (TRIG_EN = 1), if user clear this bit, the DMA operation will be continuous until all CRC DMA operation done, and the TRIG_EN bit will asserted until all CRC DMA operation done.
* | | |But in this case, the CRC_DMAISR [BLKD_IF] flag will inactive, user can read CRC result by reading CRC_CHECKSUM register when TRIG_EN = 0.
* | | |When operating in CRC DMA mode (TRIG_EN = 1), if user want to stop the transfer immediately, user can write 1 to CRC_RST bit to stop the transmission.
* |[1] |CRC_RST |CRC Engine Reset
* | | |0 = Writing 0 to this bit has no effect.
* | | |1 = Writing 1 to this bit will reset the internal CRC state machine and internal buffer.
* | | |The contents of control register will not be cleared.
* | | |This bit will be auto cleared after few clock cycles.
* | | |Note: When operating in CPU PIO mode, setting this bit will reload the initial seed value
* |[23] |TRIG_EN |Trigger Enable
* | | |0 = No effect.
* | | |1 = CRC DMA data read or write transfer Enabled.
* | | |Note1: If this bit assert that indicates the CRC engine operation in CRC DMA mode, so don't filled any data in CRC_WDATA register.
* | | |Note2: When CRC DMA transfer completed, this bit will be cleared automatically.
* | | |Note3: If the bus error occurs, all CRC DMA transfer will be stopped.
* | | |Software must reset all DMA channel, and then trigger again.
* |[24] |WDATA_RVS |Write Data Order Reverse
* | | |0 = No bit order reverse for CRC write data in.
* | | |1 = Bit order reverse for CRC write data in (per byre).
* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
* |[25] |CHECKSUM_RVS|Checksum Reverse
* | | |0 = No bit order reverse for CRC checksum.
* | | |1 = Bit order reverse for CRC checksum.
* | | |Note: If the checksum data is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB
* |[26] |WDATA_COM |Write Data Complement
* | | |0 = No bit order reverse for CRC write data in.
* | | |1 = 1's complement for CRC write data in.
* |[27] |CHECKSUM_COM|Checksum Complement
* | | |0 = No bit order reverse for CRC checksum.
* | | |1 = 1's complement for CRC checksum.
* |[29:28] |CPU_WDLEN |CPU Write Data Length
* | | |When operating in CPU PIO mode (CRCCEN= 1, TRIG_EN = 0), this field indicates the write data length.
* | | |00 = The data length is 8-bit mode
* | | |01 = The data length is 16-bit mode
* | | |10 = The data length is 32-bit mode
* | | |11 = Reserved
* | | |Note1: This field is only used for CPU PIO mode.
* | | |Note2: When the data length is 8-bit mode, the valid data is CRC_WDATA [7:0], and if the data length is 16 bit mode, the valid data is CRC_WDATA [15:0].
* |[31:30] |CRC_MODE |CRC Polynomial Mode
* | | |00 = CRC-CCITT Polynomial Mode
* | | |01 = CRC-8 Polynomial Mode
* | | |10 = CRC-16 Polynomial Mode
* | | |11 = CRC-32 Polynomial Mode
*/
__IO uint32_t CTL;
/**
* DMASAR
* ===================================================================================================
* Offset: 0x04 DMA CRC Source Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CRC_DMASAR|CRC DMA Transfer Source Address Register
* | | |This field indicates a 32-bit source address of CRC DMA.
* | | |Note : The source address must be word alignment
*/
__IO uint32_t DMASAR;
uint32_t RESERVE0[1];
/**
* DMABCR
* ===================================================================================================
* Offset: 0x0C DMA CRC Transfer Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CRC_DMABCR|CRC DMA Transfer Byte Count Register
* | | |This field indicates a 16-bit transfer byte count number of CRC DMA
*/
__IO uint32_t DMABCR;
uint32_t RESERVE1[1];
/**
* DMACSAR
* ===================================================================================================
* Offset: 0x14 DMA CRC Current Source Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CRC_DMACSAR|CRC DMA Current Source Address Register (Read Only)
* | | |This field indicates the source address where the CRC DMA transfer is just occurring.
*/
__I uint32_t DMACSAR;
uint32_t RESERVE2[1];
/**
* DMACBCR
* ===================================================================================================
* Offset: 0x1C DMA CRC Current Transfer Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CRC_DMACBCR|CRC DMA Current Byte Count Register (Read Only)
* | | |This field indicates the current remained byte count of CRC_DMA.
* | | |Note: CRC_RST will clear this register value.
*/
__I uint32_t DMACBCR;
/**
* DMAIER
* ===================================================================================================
* Offset: 0x20 DMA CRC Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TABORT_IE |CRC DMA Read/Write Target Abort Interrupt Enable
* | | |0 = Target abort interrupt generation Disabled during CRC DMA transfer.
* | | |1 = Target abort interrupt generation Enabled during CRC DMA transfer.
* |[1] |BLKD_IE |CRC DMA Transfer Done Interrupt Enable
* | | |0 = Interrupt generator Disabled during CRC DMA transfer done.
* | | |1 = Interrupt generator Enabled during CRC DMA transfer done.
*/
__IO uint32_t DMAIER;
/**
* DMAISR
* ===================================================================================================
* Offset: 0x24 DMA CRC Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TABORT_IF |CRC DMA Read/Write Target Abort Interrupt Flag
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Software can write 1 to clear this bit to zero
* | | |Note: The CRC_DMAISR [TABORT_IF] indicate bus master received ERROR response or not.
* | | |If bus master received ERROR response, it means that target abort is happened.
* | | |DMA will stop transfer and respond this event to software then go to IDLE state.
* | | |When target abort occurred, software must reset DMA, and then transfer those data again.
* |[1] |BLKD_IF |Block Transfer Done Interrupt Flag
* | | |This bit indicates that CRC DMA has finished all transfer.
* | | |0 = Not finished yet.
* | | |1 = Done.
* | | |Software can write 1 to clear this bit to zero
*/
__IO uint32_t DMAISR;
uint32_t RESERVE3[22];
/**
* WDATA
* ===================================================================================================
* Offset: 0x80 DMA CRC Write Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CRC_WDATA |CRC Write Data Register
* | | |When operating in CPU PIO (CRC_CTL [CRCCEN] = 1, CRC_CTL [TRIG_EN] = 0) mode, software can write data to this field to perform CRC operation;.
* | | |When operating in CRC DMA mode (CRC_CTL [CRCCEN] = 1, CRC_CTL [TRIG_EN] = 0), this field will be used for DMA internal buffer.
* | | |Note1: When operating in CRC DMA mode, so don't filled any data in this field.
* | | |Note2:The CRC_CTL [WDATA_COM] and CRC_CTL [WDATA_RVS] bit setting will affected this field; For example, if WDATA_RVS = 1, if the write data in CRC_WDATA register is 0xAABBCCDD, the read data from CRC_WDATA register will be 0x55DD33BB
*/
__IO uint32_t WDATA;
/**
* SEED
* ===================================================================================================
* Offset: 0x84 DMA CRC Seed Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CRC_SEED |CRC Seed Register
* | | |This field indicates the CRC seed value.
*/
__IO uint32_t SEED;
/**
* CHECKSUM
* ===================================================================================================
* Offset: 0x88 DMA CRC Check Sum Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CRC_CHECKSUM|CRC Checksum Register
* | | |This field indicates the CRC checksum
*/
__I uint32_t CHECKSUM;
} DMA_CRC_T;
typedef struct {
/**
* GCRCSR
* ===================================================================================================
* Offset: 0x00 DMA Global Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9] |CLK1_EN |PDMA Controller Channel 1 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[10] |CLK2_EN |PDMA Controller Channel 2 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[11] |CLK3_EN |PDMA Controller Channel 3 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[12] |CLK4_EN |PDMA Controller Channel 4 Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[24] |CRC_CLK_EN|CRC Controller Clock Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
*/
__IO uint32_t GCRCSR;
/**
* DSSR0
* ===================================================================================================
* Offset: 0x04 DMA Service Selection Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[12:8] |CH1_SEL |Channel 1 Selection
* | | |This filed defines which peripheral is connected to PDMA channel 1.
* | | |User can configure the peripheral by setting CH1_SEL.
* | | |00000 = Connect to SPI0_TX.
* | | |00001 = Connect to SPI1_TX.
* | | |00010 = Connect to UART0_TX.
* | | |00011 = Connect to UART1_TX.
* | | |00100 = Reserved.
* | | |00101 = Reserved.
* | | |00110 = Reserved.
* | | |00111 = Reserved.
* | | |01000 = Reserved.
* | | |01001 = Connect to TMR0.
* | | |01010 = Connect to TMR1.
* | | |01011 = Connect to TMR2.
* | | |01100 = Connect to TMR3.
* | | |10000 = Connect to SPI0_RX.
* | | |10001 = Connect to SPI1_RX.
* | | |10010 = Connect to UART0_RX.
* | | |10011 = Connect to UART1_RX.
* | | |10100 = Reserved.
* | | |10101 = Reserved.
* | | |10110 = Connect to ADC.
* | | |10111 = Reserved.
* | | |11000 = Reserved.
* | | |11001 = Connect to PWM0_CH0.
* | | |11010 = Connect to PWM0_CH2.
* | | |11011 = Reserved.
* | | |11100 = Reserved.
* | | |Others = Disable to connected any peripheral.
* |[20:16] |CH2_SEL |Channel 2 Selection
* | | |This filed defines which peripheral is connected to PDMA channel 2.
* | | |User can configure the peripheral setting by CH2_SEL.
* | | |The channel configuration is the same as CH1_SEL field.
* | | |Please refer to the explanation of CH1_SEL.
* |[28:24] |CH3_SEL |Channel 3 Selection
* | | |This filed defines which peripheral is connected to PDMA channel 3.
* | | |User can configure the peripheral setting by CH3_SEL.
* | | |The channel configuration is the same as CH1_SEL field.
* | | |Please refer to the explanation of CH1_SEL.
*/
__IO uint32_t DSSR0;
/**
* DSSR1
* ===================================================================================================
* Offset: 0x08 DMA Service Selection Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |CH4_SEL |Channel 4 Selection
* | | |This filed defines which peripheral is connected to PDMA channel 4.
* | | |User can configure the peripheral by setting CH4_SEL.
* | | |00000 = Connect to SPI0_TX.
* | | |00001 = Connect to SPI1_TX.
* | | |00010 = Connect to UART0_TX.
* | | |00011 = Connect to UART1_TX.
* | | |00100 = Reserved.
* | | |00101 = Reserved.
* | | |00110 = Reserved.
* | | |00111 = Reserved.
* | | |01000 = Reserved.
* | | |01001 = Connect to TMR0.
* | | |01010 = Connect to TMR1.
* | | |01011 = Connect to TMR2.
* | | |01100 = Connect to TMR3.
* | | |10000 = Connect to SPI0_RX.
* | | |10001 = Connect to SPI1_RX.
* | | |10010 = Connect to UART0_RX.
* | | |10011 = Connect to UART1_RX.
* | | |10100 = Reserved.
* | | |10101 = Reserved.
* | | |10110 = Connect to ADC.
* | | |10111 = Reserved.
* | | |11000 = Reserved.
* | | |11001 = Connect to PWM0_CH0.
* | | |11010 = Connect to PWM0_CH2.
* | | |11011 = Reserved.
* | | |11100 = Reserved.
* | | |Others = Disable to connected any peripheral.
*/
__IO uint32_t DSSR1;
/**
* GCRISR
* ===================================================================================================
* Offset: 0x0C DMA Global Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |INTR1 |Interrupt Status Of Channel 1 (Read Only)
* | | |This bit is the interrupt status of PDMA channel1.
* |[2] |INTR2 |Interrupt Status Of Channel 2 (Read Only)
* | | |This bit is the interrupt status of PDMA channel2.
* | | |Note: This bit is read only
* |[3] |INTR3 |Interrupt Status Of Channel 3 (Read Only)
* | | |This bit is the interrupt status of PDMA channel3.
* |[4] |INTR4 |Interrupt Status Of Channel 4 (Read Only)
* | | |This bit is the interrupt status of PDMA channel4.
* |[16] |INTRCRC |Interrupt Status Of CRC Controller (Read Only)
* | | |This bit is the interrupt status of CRC controller
*/
__I uint32_t GCRISR;
} DMA_GCR_T;
typedef struct {
/**
* CSR
* ===================================================================================================
* Offset: 0x00 PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PDMACEN |PDMA Channel Enable
* | | |Setting this bit to "1" enables PDMA's operation.
* | | |If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
* | | |Note: SW_RST will clear this bit.
* |[1] |SW_RST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset the internal state machine and pointers.
* | | |The contents of control register will not be cleared.
* | | |This bit will be auto cleared after few clock cycles.
* |[3:2] |MODE_SEL |PDMA Mode Select
* | | |00 = Memory to Memory mode (Memory-to-Memory).
* | | |01 = IP to Memory mode (APB-to-Memory)
* | | |10 = Memory to IP mode (Memory-to-APB).
* | | |11 = Reserved.
* |[5:4] |SAD_SEL |Transfer Source Address Direction Selection
* | | |00 = Transfer Source address is incremented successively.
* | | |01 = Reserved.
* | | |10 = Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations).
* | | |11 = Transfer Source address is wrap around (When the PDMA_CBCR is equal to zero, the PDMA_CSAR and PDMA_CBCR register will be updated by PDMA_SAR and PDMA_BCR automatically.
* | | |PDMA will start another transfer without software trigger until PDMA_EN disabled.
* | | |When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address).
* |[7:6] |DAD_SEL |Transfer Destination Address Direction Selection
* | | |00 = Transfer Destination address is incremented successively
* | | |01 = Reserved.
* | | |10 = Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
* | | |11 = Transfer Destination address is wrapped around (When the PDMA_CBCR is equal to zero, the PDMA_CDAR and PDMA_CBCR register will be updated by PDMA_DAR and PDMA_BCR automatically.
* | | |PDMA will start another transfer without software trigger until PDMA_EN disabled.
* | | |When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address).
* |[12] |TO_EN |Time-Out Enable
* | | |This bit will enable PDMA internal counter. While this counter counts to zero, the TO_IS will be set.
* | | |0 = PDMA internal counter Disabled.
* | | |1 = PDMA internal counter Enabled.
* |[20:19] |APB_TWS |Peripheral Transfer Width Selection
* | | |00 = One word (32 bits) is transferred for every PDMA operation.
* | | |01 = One byte (8 bits) is transferred for every PDMA operation.
* | | |10 = One half-word (16 bits) is transferred for every PDMA operation.
* | | |11 = Reserved.
* | | |Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
* |[23] |TRIG_EN |TRIG_EN
* | | |0 = No effect.
* | | |1 = PDMA data read or write transfer Enabled.
* | | |Note1: When PDMA transfer completed, this bit will be cleared automatically.
* | | |Note2: If the bus error occurs, all PDMA transfer will be stopped.
* | | |Software must reset all PDMA channel, and then trig again.
*/
__IO uint32_t CSR;
/**
* SAR
* ===================================================================================================
* Offset: 0x04 PDMA Source Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |PDMA_SAR |PDMA Transfer Source Address Register
* | | |This field indicates a 32-bit source address of PDMA.
* | | |Note: The source address must be word alignment.
*/
__IO uint32_t SAR;
/**
* DAR
* ===================================================================================================
* Offset: 0x08 PDMA Destination Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |PDMA_DAR |PDMA Transfer Destination Address Register
* | | |This field indicates a 32-bit destination address of PDMA.
* | | |Note : The destination address must be word alignment
*/
__IO uint32_t DAR;
/**
* BCR
* ===================================================================================================
* Offset: 0x0C PDMA Transfer Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PDMA_BCR |PDMA Transfer Byte Count Register
* | | |This field indicates a 16-bit transfer byte count of PDMA.
* | | |Note: In Memory-to-memory (PDMA_CSR [MODE_SEL] = 00) mode, the transfer byte count must be word alignment.
*/
__IO uint32_t BCR;
uint32_t RESERVE0[1];
/**
* CSAR
* ===================================================================================================
* Offset: 0x14 PDMA Current Source Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |PDMA_CSAR |PDMA Current Source Address Register (Read Only)
* | | |This field indicates the source address where the PDMA transfer is just occurring.
*/
__I uint32_t CSAR;
/**
* CDAR
* ===================================================================================================
* Offset: 0x18 PDMA Current Destination Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |PDMA_CDAR |PDMA Current Destination Address Register (Read Only)
* | | |This field indicates the destination address where the PDMA transfer is just occurring.
*/
__I uint32_t CDAR;
/**
* CBCR
* ===================================================================================================
* Offset: 0x1C PDMA Current Transfer Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |PDMA_CBCR |PDMA Current Byte Count Register (Read Only)
* | | |This field indicates the current remained byte count of PDMA.
* | | |Note: These fields will be changed when PDMA finish data transfer (data transfer to destination address),
*/
__I uint32_t CBCR;
/**
* IER
* ===================================================================================================
* Offset: 0x20 PDMA Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TABORT_IE |PDMA Read/Write Target Abort Interrupt Enable
* | | |0 = Target abort interrupt generation Disabled during PDMA transfer.
* | | |1 = Target abort interrupt generation Enabled during PDMA transfer.
* |[1] |TD_IE |PDMA Transfer Done Interrupt Enable
* | | |0 = Interrupt generator Disabled when PDMA transfer is done.
* | | |1 = Interrupt generator Enabled when PDMA transfer is done.
* |[5:2] |WRA_BCR_IE|Wrap Around Byte Count Interrupt Enable
* | | |0001 = Interrupt enable of PDMA_CBCR equals 0
* | | |0100 = Interrupt enable of PDMA_CBCR equals 1/2 PDMA_BCR.
* |[6] |TO_IE |Time-Out Interrupt Enable
* | | |0 = Time-out interrupt Disabled.
* | | |1 = Time-out interrupt Enabled.
*/
__IO uint32_t IER;
/**
* ISR
* ===================================================================================================
* Offset: 0x24 PDMA Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TABORT_IS |PDMA Read/Write Target Abort Interrupt Status Flag
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Note1: This bit is cleared by writing "1" to itself.
* | | |Note2: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not, if bus master received occur it means that target abort is happened.
* | | |PDMA controller will stop transfer and respond this event to software then go to IDLE state.
* | | |When target abort occurred, software must reset PDMA controller, and then transfer those data again.
* |[1] |TD_IS |Transfer Done Interrupt Status Flag
* | | |This bit indicates that PDMA has finished all transfer.
* | | |0 = Not finished yet.
* | | |1 = Done.
* | | |Note: This bit is cleared by writing "1" to itself.
* |[5:2] |WRA_BCR_IS|Wrap Around Transfer Byte Count Interrupt Status Flag
* | | |WRA_BCR_IS [0] (xxx1) = PDMA_CBCR equal 0 flag.
* | | |WRA_BCR_IS [2] (x1xx) = PDMA_CBCR equal 1/2 PDMA_BCR flag.
* | | |Note: Each bit is cleared by writing "1" to itself.
* | | |This field is only valid in wrap around mode.
* | | |(PDMA_CSR[DAD_SEL] =11 or PDMA_CSR[SAD_SEL] =11).
* |[6] |TO_IS |Time-Out Interrupt Status Flag
* | | |This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.
* | | |0 = No time-out flag.
* | | |1 = Time-out flag.
* | | |Note: This bit is cleared by writing "1" to itself.
*/
__IO uint32_t ISR;
/**
* TCR
* ===================================================================================================
* Offset: 0x28 PDMA Timer Counter Setting Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PDMA_TCR |PDMA Timer Count Setting Register
* | | |Each PDMA channel contains an internal counter.
* | | |The internal counter loads the value of PDAM_TCR and starts counting down when setting PDMA_CSRx [TO_EN] register.
* | | |PDMA will request interrupt when this internal counter reaches zero and PDMA_IERx[TO_IE] is high.
* | | |This internal counter will reload and start counting when completing each peripheral request service.
*/
__IO uint32_t TCR;
} PDMA_T;
/**
@addtogroup DMA_CRC_CONST DMA_CRC Bit Field Definition
Constant Definitions for DMA_CRC Controller
@{ */
#define DMA_CRC_CTL_CRCCEN_Pos (0) /*!< DMA_CRC CTL: CRCCEN Position */
#define DMA_CRC_CTL_CRCCEN_Msk (0x1ul << DMA_CRC_CTL_CRCCEN_Pos) /*!< DMA_CRC CTL: CRCCEN Mask */
#define DMA_CRC_CTL_CRC_RST_Pos (1) /*!< DMA_CRC CTL: CRC_RST Position */
#define DMA_CRC_CTL_CRC_RST_Msk (0x1ul << DMA_CRC_CTL_CRC_RST_Pos) /*!< DMA_CRC CTL: CRC_RST Mask */
#define DMA_CRC_CTL_TRIG_EN_Pos (23) /*!< DMA_CRC CTL: TRIG_EN Position */
#define DMA_CRC_CTL_TRIG_EN_Msk (0x1ul << DMA_CRC_CTL_TRIG_EN_Pos) /*!< DMA_CRC CTL: TRIG_EN Mask */
#define DMA_CRC_CTL_WDATA_RVS_Pos (24) /*!< DMA_CRC CTL: WDATA_RVS Position */
#define DMA_CRC_CTL_WDATA_RVS_Msk (0x1ul << DMA_CRC_CTL_WDATA_RVS_Pos) /*!< DMA_CRC CTL: WDATA_RVS Mask */
#define DMA_CRC_CTL_CHECKSUM_RVS_Pos (25) /*!< DMA_CRC CTL: CHECKSUM_RVS Position */
#define DMA_CRC_CTL_CHECKSUM_RVS_Msk (0x1ul << DMA_CRC_CTL_CHECKSUM_RVS_Pos) /*!< DMA_CRC CTL: CHECKSUM_RVS Mask */
#define DMA_CRC_CTL_WDATA_COM_Pos (26) /*!< DMA_CRC CTL: WDATA_COM Position */
#define DMA_CRC_CTL_WDATA_COM_Msk (0x1ul << DMA_CRC_CTL_WDATA_COM_Pos) /*!< DMA_CRC CTL: WDATA_COM Mask */
#define DMA_CRC_CTL_CHECKSUM_COM_Pos (27) /*!< DMA_CRC CTL: CHECKSUM_COM Position */
#define DMA_CRC_CTL_CHECKSUM_COM_Msk (0x1ul << DMA_CRC_CTL_CHECKSUM_COM_Pos) /*!< DMA_CRC CTL: CHECKSUM_COM Mask */
#define DMA_CRC_CTL_CPU_WDLEN_Pos (28) /*!< DMA_CRC CTL: CPU_WDLEN Position */
#define DMA_CRC_CTL_CPU_WDLEN_Msk (0x3ul << DMA_CRC_CTL_CPU_WDLEN_Pos) /*!< DMA_CRC CTL: CPU_WDLEN Mask */
#define DMA_CRC_CTL_CRC_MODE_Pos (30) /*!< DMA_CRC CTL: CRC_MODE Position */
#define DMA_CRC_CTL_CRC_MODE_Msk (0x3ul << DMA_CRC_CTL_CRC_MODE_Pos) /*!< DMA_CRC CTL: CRC_MODE Mask */
#define DMA_CRC_DMASAR_CRC_DMASAR_Pos (0) /*!< DMA_CRC DMASAR: CRC_DMASAR Position */
#define DMA_CRC_DMASAR_CRC_DMASAR_Msk (0xfffffffful << DMA_CRC_DMASAR_CRC_DMASAR_Pos) /*!< DMA_CRC DMASAR: CRC_DMASAR Mask */
#define DMA_CRC_DMABCR_CRC_DMABCR_Pos (0) /*!< DMA_CRC DMABCR: CRC_DMABCR Position */
#define DMA_CRC_DMABCR_CRC_DMABCR_Msk (0xfffful << DMA_CRC_DMABCR_CRC_DMABCR_Pos) /*!< DMA_CRC DMABCR: CRC_DMABCR Mask */
#define DMA_CRC_DMACSAR_CRC_DMACSAR_Pos (0) /*!< DMA_CRC DMACSAR: CRC_DMACSAR Position */
#define DMA_CRC_DMACSAR_CRC_DMACSAR_Msk (0xfffffffful << DMA_CRC_DMACSAR_CRC_DMACSAR_Pos) /*!< DMA_CRC DMACSAR: CRC_DMACSAR Mask */
#define DMA_CRC_DMACBCR_CRC_DMACBCR_Pos (0) /*!< DMA_CRC DMACBCR: CRC_DMACBCR Position */
#define DMA_CRC_DMACBCR_CRC_DMACBCR_Msk (0xfffful << DMA_CRC_DMACBCR_CRC_DMACBCR_Pos) /*!< DMA_CRC DMACBCR: CRC_DMACBCR Mask */
#define DMA_CRC_DMAIER_TABORT_IE_Pos (0) /*!< DMA_CRC DMAIER: TABORT_IE Position */
#define DMA_CRC_DMAIER_TABORT_IE_Msk (0x1ul << DMA_CRC_DMAIER_TABORT_IE_Pos) /*!< DMA_CRC DMAIER: TABORT_IE Mask */
#define DMA_CRC_DMAIER_BLKD_IE_Pos (1) /*!< DMA_CRC DMAIER: BLKD_IE Position */
#define DMA_CRC_DMAIER_BLKD_IE_Msk (0x1ul << DMA_CRC_DMAIER_BLKD_IE_Pos) /*!< DMA_CRC DMAIER: BLKD_IE Mask */
#define DMA_CRC_DMAISR_TABORT_IF_Pos (0) /*!< DMA_CRC DMAISR: TABORT_IF Position */
#define DMA_CRC_DMAISR_TABORT_IF_Msk (0x1ul << DMA_CRC_DMAISR_TABORT_IF_Pos) /*!< DMA_CRC DMAISR: TABORT_IF Mask */
#define DMA_CRC_DMAISR_BLKD_IF_Pos (1) /*!< DMA_CRC DMAISR: BLKD_IF Position */
#define DMA_CRC_DMAISR_BLKD_IF_Msk (0x1ul << DMA_CRC_DMAISR_BLKD_IF_Pos) /*!< DMA_CRC DMAISR: BLKD_IF Mask */
#define DMA_CRC_WDATA_CRC_WDATA_Pos (0) /*!< DMA_CRC WDATA: CRC_WDATA Position */
#define DMA_CRC_WDATA_CRC_WDATA_Msk (0xfffffffful << DMA_CRC_WDATA_CRC_WDATA_Pos) /*!< DMA_CRC WDATA: CRC_WDATA Mask */
#define DMA_CRC_SEED_CRC_SEED_Pos (0) /*!< DMA_CRC SEED: CRC_SEED Position */
#define DMA_CRC_SEED_CRC_SEED_Msk (0xfffffffful << DMA_CRC_SEED_CRC_SEED_Pos) /*!< DMA_CRC SEED: CRC_SEED Mask */
#define DMA_CRC_CHECKSUM_CRC_CHECKSUM_Pos (0) /*!< DMA_CRC CHECKSUM: CRC_CHECKSUM Position*/
#define DMA_CRC_CHECKSUM_CRC_CHECKSUM_Msk (0xfffffffful << DMA_CRC_CHECKSUM_CRC_CHECKSUM_Pos) /*!< DMA_CRC CHECKSUM: CRC_CHECKSUM Mask */
/**@}*/ /* DMA_CRC_CONST */
/**
@addtogroup DMA_GCR_CONST DMA_GCR Bit Field Definition
Constant Definitions for DMA_GCR Controller
@{ */
#define DMA_GCR_GCRCSR_CLK1_EN_Pos (9) /*!< DMA_GCR GCRCSR: CLK1_EN Position */
#define DMA_GCR_GCRCSR_CLK1_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK1_EN_Pos) /*!< DMA_GCR GCRCSR: CLK1_EN Mask */
#define DMA_GCR_GCRCSR_CLK2_EN_Pos (10) /*!< DMA_GCR GCRCSR: CLK2_EN Position */
#define DMA_GCR_GCRCSR_CLK2_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK2_EN_Pos) /*!< DMA_GCR GCRCSR: CLK2_EN Mask */
#define DMA_GCR_GCRCSR_CLK3_EN_Pos (11) /*!< DMA_GCR GCRCSR: CLK3_EN Position */
#define DMA_GCR_GCRCSR_CLK3_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK3_EN_Pos) /*!< DMA_GCR GCRCSR: CLK3_EN Mask */
#define DMA_GCR_GCRCSR_CLK4_EN_Pos (12) /*!< DMA_GCR GCRCSR: CLK4_EN Position */
#define DMA_GCR_GCRCSR_CLK4_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK4_EN_Pos) /*!< DMA_GCR GCRCSR: CLK4_EN Mask */
#define DMA_GCR_GCRCSR_CRC_CLK_EN_Pos (24) /*!< DMA_GCR GCRCSR: CRC_CLK_EN Position */
#define DMA_GCR_GCRCSR_CRC_CLK_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CRC_CLK_EN_Pos) /*!< DMA_GCR GCRCSR: CRC_CLK_EN Mask */
#define DMA_GCR_DSSR0_CH1_SEL_Pos (8) /*!< DMA_GCR DSSR0: CH1_SEL Position */
#define DMA_GCR_DSSR0_CH1_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH1_SEL_Pos) /*!< DMA_GCR DSSR0: CH1_SEL Mask */
#define DMA_GCR_DSSR0_CH2_SEL_Pos (16) /*!< DMA_GCR DSSR0: CH2_SEL Position */
#define DMA_GCR_DSSR0_CH2_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH2_SEL_Pos) /*!< DMA_GCR DSSR0: CH2_SEL Mask */
#define DMA_GCR_DSSR0_CH3_SEL_Pos (24) /*!< DMA_GCR DSSR0: CH3_SEL Position */
#define DMA_GCR_DSSR0_CH3_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH3_SEL_Pos) /*!< DMA_GCR DSSR0: CH3_SEL Mask */
#define DMA_GCR_DSSR1_CH4_SEL_Pos (0) /*!< DMA_GCR DSSR1: CH4_SEL Position */
#define DMA_GCR_DSSR1_CH4_SEL_Msk (0x1ful << DMA_GCR_DSSR1_CH4_SEL_Pos) /*!< DMA_GCR DSSR1: CH4_SEL Mask */
#define DMA_GCR_GCRISR_INTR1_Pos (1) /*!< DMA_GCR GCRISR: INTR1 Position */
#define DMA_GCR_GCRISR_INTR1_Msk (0x1ul << DMA_GCR_GCRISR_INTR1_Pos) /*!< DMA_GCR GCRISR: INTR1 Mask */
#define DMA_GCR_GCRISR_INTR2_Pos (2) /*!< DMA_GCR GCRISR: INTR2 Position */
#define DMA_GCR_GCRISR_INTR2_Msk (0x1ul << DMA_GCR_GCRISR_INTR2_Pos) /*!< DMA_GCR GCRISR: INTR2 Mask */
#define DMA_GCR_GCRISR_INTR3_Pos (3) /*!< DMA_GCR GCRISR: INTR3 Position */
#define DMA_GCR_GCRISR_INTR3_Msk (0x1ul << DMA_GCR_GCRISR_INTR3_Pos) /*!< DMA_GCR GCRISR: INTR3 Mask */
#define DMA_GCR_GCRISR_INTR4_Pos (4) /*!< DMA_GCR GCRISR: INTR4 Position */
#define DMA_GCR_GCRISR_INTR4_Msk (0x1ul << DMA_GCR_GCRISR_INTR4_Pos) /*!< DMA_GCR GCRISR: INTR4 Mask */
#define DMA_GCR_GCRISR_INTRCRC_Pos (16) /*!< DMA_GCR GCRISR: INTRCRC Position */
#define DMA_GCR_GCRISR_INTRCRC_Msk (0x1ul << DMA_GCR_GCRISR_INTRCRC_Pos) /*!< DMA_GCR GCRISR: INTRCRC Mask */
/**@}*/ /* DMA_GCR_CONST */
/**
@addtogroup PDMA_CONST PDMA Bit Field Definition
Constant Definitions for PDMA Controller
@{ */
#define PDMA_CSR_PDMACEN_Pos (0) /*!< PDMA CSR: PDMACEN Position */
#define PDMA_CSR_PDMACEN_Msk (0x1ul << PDMA_CSR_PDMACEN_Pos) /*!< PDMA CSR: PDMACEN Mask */
#define PDMA_CSR_SW_RST_Pos (1) /*!< PDMA CSR: SW_RST Position */
#define PDMA_CSR_SW_RST_Msk (0x1ul << PDMA_CSR_SW_RST_Pos) /*!< PDMA CSR: SW_RST Mask */
#define PDMA_CSR_MODE_SEL_Pos (2) /*!< PDMA CSR: MODE_SEL Position */
#define PDMA_CSR_MODE_SEL_Msk (0x3ul << PDMA_CSR_MODE_SEL_Pos) /*!< PDMA CSR: MODE_SEL Mask */
#define PDMA_CSR_SAD_SEL_Pos (4) /*!< PDMA CSR: SAD_SEL Position */
#define PDMA_CSR_SAD_SEL_Msk (0x3ul << PDMA_CSR_SAD_SEL_Pos) /*!< PDMA CSR: SAD_SEL Mask */
#define PDMA_CSR_DAD_SEL_Pos (6) /*!< PDMA CSR: DAD_SEL Position */
#define PDMA_CSR_DAD_SEL_Msk (0x3ul << PDMA_CSR_DAD_SEL_Pos) /*!< PDMA CSR: DAD_SEL Mask */
#define PDMA_CSR_TO_EN_Pos (12) /*!< PDMA CSR: TO_EN Position */
#define PDMA_CSR_TO_EN_Msk (0x1ul << PDMA_CSR_TO_EN_Pos) /*!< PDMA CSR: TO_EN Mask */
#define PDMA_CSR_APB_TWS_Pos (19) /*!< PDMA CSR: APB_TWS Position */
#define PDMA_CSR_APB_TWS_Msk (0x3ul << PDMA_CSR_APB_TWS_Pos) /*!< PDMA CSR: APB_TWS Mask */
#define PDMA_CSR_TRIG_EN_Pos (23) /*!< PDMA CSR: TRIG_EN Position */
#define PDMA_CSR_TRIG_EN_Msk (0x1ul << PDMA_CSR_TRIG_EN_Pos) /*!< PDMA CSR: TRIG_EN Mask */
#define PDMA_SAR_PDMA_SAR_Pos (0) /*!< PDMA SAR: PDMA_SAR Position */
#define PDMA_SAR_PDMA_SAR_Msk (0xfffffffful << PDMA_SAR_PDMA_SAR_Pos) /*!< PDMA SAR: PDMA_SAR Mask */
#define PDMA_DAR_PDMA_DAR_Pos (0) /*!< PDMA DAR: PDMA_DAR Position */
#define PDMA_DAR_PDMA_DAR_Msk (0xfffffffful << PDMA_DAR_PDMA_DAR_Pos) /*!< PDMA DAR: PDMA_DAR Mask */
#define PDMA_BCR_PDMA_BCR_Pos (0) /*!< PDMA BCR: PDMA_BCR Position */
#define PDMA_BCR_PDMA_BCR_Msk (0xfffful << PDMA_BCR_PDMA_BCR_Pos) /*!< PDMA BCR: PDMA_BCR Mask */
#define PDMA_CSAR_PDMA_CSAR_Pos (0) /*!< PDMA CSAR: PDMA_CSAR Position */
#define PDMA_CSAR_PDMA_CSAR_Msk (0xfffffffful << PDMA_CSAR_PDMA_CSAR_Pos) /*!< PDMA CSAR: PDMA_CSAR Mask */
#define PDMA_CDAR_PDMA_CDAR_Pos (0) /*!< PDMA CDAR: PDMA_CDAR Position */
#define PDMA_CDAR_PDMA_CDAR_Msk (0xfffffffful << PDMA_CDAR_PDMA_CDAR_Pos) /*!< PDMA CDAR: PDMA_CDAR Mask */
#define PDMA_CBCR_PDMA_CBCR_Pos (0) /*!< PDMA CBCR: PDMA_CBCR Position */
#define PDMA_CBCR_PDMA_CBCR_Msk (0xfffffful << PDMA_CBCR_PDMA_CBCR_Pos) /*!< PDMA CBCR: PDMA_CBCR Mask */
#define PDMA_IER_TABORT_IE_Pos (0) /*!< PDMA IER: TABORT_IE Position */
#define PDMA_IER_TABORT_IE_Msk (0x1ul << PDMA_IER_TABORT_IE_Pos) /*!< PDMA IER: TABORT_IE Mask */
#define PDMA_IER_TD_IE_Pos (1) /*!< PDMA IER: TD_IE Position */
#define PDMA_IER_TD_IE_Msk (0x1ul << PDMA_IER_TD_IE_Pos) /*!< PDMA IER: TD_IE Mask */
#define PDMA_IER_WRA_BCR_IE_Pos (2) /*!< PDMA IER: WRA_BCR_IE Position */
#define PDMA_IER_WRA_BCR_IE_Msk (0xful << PDMA_IER_WRA_BCR_IE_Pos) /*!< PDMA IER: WRA_BCR_IE Mask */
#define PDMA_IER_TO_IE_Pos (6) /*!< PDMA IER: TO_IE Position */
#define PDMA_IER_TO_IE_Msk (0x1ul << PDMA_IER_TO_IE_Pos) /*!< PDMA IER: TO_IE Mask */
#define PDMA_ISR_TABORT_IS_Pos (0) /*!< PDMA ISR: TABORT_IS Position */
#define PDMA_ISR_TABORT_IS_Msk (0x1ul << PDMA_ISR_TABORT_IS_Pos) /*!< PDMA ISR: TABORT_IS Mask */
#define PDMA_ISR_TD_IS_Pos (1) /*!< PDMA ISR: TD_IS Position */
#define PDMA_ISR_TD_IS_Msk (0x1ul << PDMA_ISR_TD_IS_Pos) /*!< PDMA ISR: TD_IS Mask */
#define PDMA_ISR_WRA_BCR_IS_Pos (2) /*!< PDMA ISR: WRA_BCR_IS Position */
#define PDMA_ISR_WRA_BCR_IS_Msk (0xful << PDMA_ISR_WRA_BCR_IS_Pos) /*!< PDMA ISR: WRA_BCR_IS Mask */
#define PDMA_ISR_TO_IS_Pos (6) /*!< PDMA ISR: TO_IS Position */
#define PDMA_ISR_TO_IS_Msk (0x1ul << PDMA_ISR_TO_IS_Pos) /*!< PDMA ISR: TO_IS Mask */
#define PDMA_TCR_PDMA_TCR_Pos (0) /*!< PDMA TCR: PDMA_TCR Position */
#define PDMA_TCR_PDMA_TCR_Msk (0xfffful << PDMA_TCR_PDMA_TCR_Pos) /*!< PDMA TCR: PDMA_TCR Mask */
/**@}*/ /* PDMA_CONST */
/**@}*/ /* end of DMA_GCR register group */
/*---------------------- Flash Memory Controller -------------------------*/
/**
@addtogroup FMC Flash Memory Controller(FMC)
Memory Mapped Structure for FMC Controller
@{ */
typedef struct {
/**
* ISPCON
* ===================================================================================================
* Offset: 0x00 ISP Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPEN |ISP Enable Control (Write Protect)
* | | |ISP function enable bit. Set this bit to enable ISP function.
* | | |0 = ISP function Disabled.
* | | |1 = ISP function Enabled.
* |[1] |BS |Boot Select (Write Protect)
* | | |Set/clear this bit to select next booting from LDROM/APROM, respectively.
* | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
* | | |This bit is initiated with the inversed value of CBS in Config0 after power-on reset; It keeps the same value at other reset.
* | | |0 = Boot from APROM.
* | | |1 = Boot from LDROM.
* |[3] |APUEN |APROM Update Enable Control (Write Protect)
* | | |0 = APROM cannot be updated.
* | | |1 = APROM can be updated.
* |[4] |CFGUEN |Enable Config-Bits Update By ISP (Write Protect)
* | | |0 = ISP update User Configuration Disabled.
* | | |1 = ISP update User Configuration Enabled.
* |[5] |LDUEN |LDROM Update Enable Control (Write Protect)
* | | |0 = LDROM cannot be updated.
* | | |1 = LDROM can be updated.
* |[6] |ISPFF |ISP Fail Flag (Write Protect)
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |(1) APROM writes to itself if APUEN is set to 0 or CBS[0]=1.
* | | |(2) LDROM writes to itself if LDUEN is set to 0 or CBS[0]=1.
* | | |(3) User Configuration is erased/programmed when CFGUEN is 0.
* | | |(4) Destination address is illegal, such as over an available range.
* | | |Note: Write 1 to clear this bit to 0.
*/
__IO uint32_t ISPCON;
/**
* ISPADR
* ===================================================================================================
* Offset: 0x04 ISP Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPADR |ISP Address
* | | |This chip supports word program only.
* | | |ISPADR[1:0] must be kept 00b for ISP operation, and ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command.
*/
__IO uint32_t ISPADR;
/**
* ISPDAT
* ===================================================================================================
* Offset: 0x08 ISP Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT |ISP Data
* | | |Write data to this register before ISP program operation
* | | |Read data from this register after ISP read operation
*/
__IO uint32_t ISPDAT;
/**
* ISPCMD
* ===================================================================================================
* Offset: 0x0C ISP Command Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |FCTRL |ISP Command
* | | |The ISP command table is shown as follows
* | | |Read (FOEN = 0, FCEN = 0, FCRTL = 0000)
* | | |Program (FOEN = 1, FCEN = 0, FCRTL = 0001)
* | | |Page Erase (FOEN = 1, FCEN = 0, FCRTL = 0010)
* | | |Read CID (FOEN = 0, FCEN = 0, FCRTL = 1011)
* | | |Read DID (FOEN = 0, FCEN = 0, FCRTL = 1100)
* |[4] |FCEN |ISP Command
* | | |The ISP command table is shown as above.
* |[5] |FOEN |ISP Command
* | | |The ISP command table is shown as above.
*/
__IO uint32_t ISPCMD;
/**
* ISPTRG
* ===================================================================================================
* Offset: 0x10 ISP Trigger Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPGO |ISP Start Trigger
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
* | | |0 = ISP operation is finished.
* | | |1 = ISP is progressing.
*/
__IO uint32_t ISPTRG;
/**
* DFBADR
* ===================================================================================================
* Offset: 0x14 Data Flash Base Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DFBADR |Data Flash Base Address
* | | |This register indicates data flash start address. It is a read only register.
* | | |The data flash start address is defined by user.
* | | |Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.
*/
__I uint32_t DFBADR;
uint32_t RESERVE0[10];
/**
* ISPSTA
* ===================================================================================================
* Offset: 0x40 ISP Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPBUSY |ISP Busy (Read Only)
* | | |0 = ISP operation is finished.
* | | |1 = ISP operation is busy.
* |[2:1] |CBS |Config Boot Selection Status (Read Only)
* | | |This filed is a mirror of CBS in CONFIG0.
* |[5] |PGFF |Auto Flash Program Verified Fail Flag
* | | |This chip will perform flash verification automatically at the end of ISP PROGRAM operation, and set 1 to this bit when flash data is not matched with programming.
* | | |This bit is clear to 0 by "ERASE" command.
* |[6] |ISPFF |ISP Fail Flag
* | | |(1) APROM writes to itself if APUEN is set to 0 or CBS[0]=1.
* | | |(2) LDROM writes to itself if LDUEN is set to 0 or CBS[0]=1.
* | | |(3) User Configuration is erased/programmed when CFGUEN is 0.
* | | |(4) Destination address is illegal, such as over an available range.
* | | |Note: Write 1 to clear this bit to 0.
*/
__I uint32_t ISPSTA;
} FMC_T;
/**
@addtogroup FMC_CONST FMC Bit Field Definition
Constant Definitions for FMC Controller
@{ */
#define FMC_ISPCON_ISPEN_Pos (0) /*!< FMC ISPCON: ISPEN Position */
#define FMC_ISPCON_ISPEN_Msk (0x1ul << FMC_ISPCON_ISPEN_Pos) /*!< FMC ISPCON: ISPEN Mask */
#define FMC_ISPCON_BS_Pos (1) /*!< FMC ISPCON: BS Position */
#define FMC_ISPCON_BS_Msk (0x1ul << FMC_ISPCON_BS_Pos) /*!< FMC ISPCON: BS Mask */
#define FMC_ISPCON_APUEN_Pos (3) /*!< FMC ISPCON: APUEN Position */
#define FMC_ISPCON_APUEN_Msk (0x1ul << FMC_ISPCON_APUEN_Pos) /*!< FMC ISPCON: APUEN Mask */
#define FMC_ISPCON_CFGUEN_Pos (4) /*!< FMC ISPCON: CFGUEN Position */
#define FMC_ISPCON_CFGUEN_Msk (0x1ul << FMC_ISPCON_CFGUEN_Pos) /*!< FMC ISPCON: CFGUEN Mask */
#define FMC_ISPCON_LDUEN_Pos (5) /*!< FMC ISPCON: LDUEN Position */
#define FMC_ISPCON_LDUEN_Msk (0x1ul << FMC_ISPCON_LDUEN_Pos) /*!< FMC ISPCON: LDUEN Mask */
#define FMC_ISPCON_ISPFF_Pos (6) /*!< FMC ISPCON: ISPFF Position */
#define FMC_ISPCON_ISPFF_Msk (0x1ul << FMC_ISPCON_ISPFF_Pos) /*!< FMC ISPCON: ISPFF Mask */
#define FMC_ISPADR_ISPADR_Pos (0) /*!< FMC ISPADR: ISPADR Position */
#define FMC_ISPADR_ISPADR_Msk (0xfffffffful << FMC_ISPADR_ISPADR_Pos) /*!< FMC ISPADR: ISPADR Mask */
#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC ISPDAT: ISPDAT Position */
#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC ISPDAT: ISPDAT Mask */
#define FMC_ISPCMD_FCTRL_Pos (0) /*!< FMC ISPCMD: FCTRL Position */
#define FMC_ISPCMD_FCTRL_Msk (0xful << FMC_ISPCMD_FCTRL_Pos) /*!< FMC ISPCMD: FCTRL Mask */
#define FMC_ISPCMD_FCEN_Pos (4) /*!< FMC ISPCMD: FCEN Position */
#define FMC_ISPCMD_FCEN_Msk (0x1ul << FMC_ISPCMD_FCEN_Pos) /*!< FMC ISPCMD: FCEN Mask */
#define FMC_ISPCMD_FOEN_Pos (5) /*!< FMC ISPCMD: FOEN Position */
#define FMC_ISPCMD_FOEN_Msk (0x1ul << FMC_ISPCMD_FOEN_Pos) /*!< FMC ISPCMD: FOEN Mask */
#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC ISPTRG: ISPGO Position */
#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC ISPTRG: ISPGO Mask */
#define FMC_DFBADR_DFBADR_Pos (0) /*!< FMC DFBADR: DFBADR Position */
#define FMC_DFBADR_DFBADR_Msk (0xfffffffful << FMC_DFBADR_DFBADR_Pos) /*!< FMC DFBADR: DFBADR Mask */
#define FMC_ISPSTA_ISPBUSY_Pos (0) /*!< FMC ISPSTA: ISPBUSY Position */
#define FMC_ISPSTA_ISPBUSY_Msk (0x1ul << FMC_ISPSTA_ISPBUSY_Pos) /*!< FMC ISPSTA: ISPBUSY Mask */
#define FMC_ISPSTA_CBS_Pos (1) /*!< FMC ISPSTA: CBS Position */
#define FMC_ISPSTA_CBS_Msk (0x3ul << FMC_ISPSTA_CBS_Pos) /*!< FMC ISPSTA: CBS Mask */
#define FMC_ISPSTA_PGFF_Pos (5) /*!< FMC ISPSTA: PGFF Position */
#define FMC_ISPSTA_PGFF_Msk (0x1ul << FMC_ISPSTA_PGFF_Pos) /*!< FMC ISPSTA: PGFF Mask */
#define FMC_ISPSTA_ISPFF_Pos (6) /*!< FMC ISPSTA: ISPFF Position */
#define FMC_ISPSTA_ISPFF_Msk (0x1ul << FMC_ISPSTA_ISPFF_Pos) /*!< FMC ISPSTA: ISPFF Mask */
/**@}*/ /* FMC_CONST */
/**@}*/ /* end of FMC register group */
/*---------------------- System Global Control Registers -------------------------*/
/**
@addtogroup SYS System Global Control Registers(SYS)
Memory Mapped Structure for SYS Controller
@{ */
typedef struct {
/**
* PDID
* ===================================================================================================
* Offset: 0x00 Part Device Identification Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |PDID |Part Device ID
* | | |This register reflects device part number code.
* | | |Software can read this register to identify which device is used.
*/
__I uint32_t PDID;
/**
* RST_SRC
* ===================================================================================================
* Offset: 0x04 System Reset Source Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RSTS_POR |The RSTS_POR Flag Is Set By The "Reset Signal" From The Power-On Reset (POR) Module Or Bit CHIP_RST (IPRSTC1[0]) To Indicate The Previous Reset Source
* | | |0 = No reset from POR or CHIP_RST.
* | | |1 = Power-on Reset (POR) or CHIP_RST had issued the reset signal to reset the system.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |RSTS_PAD |The RSTS_PAD Flag Is Set By The "Reset Signal" From The /RESET Pin Or Power Related Reset Sources To Indicate The Previous Reset Source
* | | |0 = No reset from nRESET pin.
* | | |1 = The /RESET pin had issued the reset signal to reset the system.
* | | |Note: This bit is cleared by writing 1 to it.
* |[2] |RSTS_WDT |The RSTS_WDT Flag Is Set By The "Reset Signal" From The Watchdog Timer Module To Indicate The Previous Reset Source
* | | |0 = No reset from Watchdog Timer.
* | | |1 = The Watchdog Timer module had issued the reset signal to reset the system.
* | | |Note: This bit is cleared by writing 1 to it.
* |[4] |RSTS_BOD |The RSTS_BOD Flag Is Set By The "Reset Signal" From The Brown-Out-Detected Module To Indicate The Previous Reset Source
* | | |0 = No reset from BOD.
* | | |1 = Brown-out-Detected module had issued the reset signal to reset the system.
* | | |Note: This bit is cleared by writing 1 to it.
* |[5] |RSTS_SYS |The RSTS_SYS Flag Is Set By The "Reset Signal" From The Cortex_M0 Kernel To Indicate The Previous Reset Source
* | | |0 = No reset from Cortex_M0.
* | | |1 = Cortex_M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel.
* | | |Note: This bit is cleared by writing 1 to it.
* |[7] |RSTS_CPU |The RSTS_CPU Flag Is Set By Hardware If Software Writes CPU_RST (IPRST_CTL1[1]) "1" To Rest Cortex-M0 Core And Flash Memory Controller (FMC)
* | | |0 = No reset from CPU.
* | | |1 = Cortex-M0 core and FMC are reset by software setting CPU_RST to 1.
* | | |Note: This bit is cleared by writing 1 to it.
*/
__IO uint32_t RST_SRC;
/**
* IPRST_CTL1
* ===================================================================================================
* Offset: 0x08 Peripheral Reset Control Resister1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CHIP_RST |Chip One-Shot Reset
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |Setting this bit will reset the whole chip, including Cortex-M0 core and all peripherals like power-on reset and this bit will automatically return to "0" after the 2 clock cycles.
* | | |The chip setting from flash will be also reloaded when chip one shot reset.
* | | |0 = Normal.
* | | |1 = Reset chip.
* | | |Note: In the following conditions, chip setting from flash will be reloaded.
* | | |Power-on Reset
* | | |Brown-out-Detected Reset
* | | |Low level on the nRESET pin
* | | |Set IPRST_CTL1[CHIP_RST]
* |[1] |CPU_RST |Cortex-M0 Core One-Shot Reset
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |Setting this bit will only reset the Cortex-M0 core and Flash Memory Controller (FMC), and this bit will automatically return to "0" after the 2 clock cycles
* | | |0 = Normal.
* | | |1 = Reset Cortex-M0 core.
* |[2] |DMA_RST |DMA Controller Reset
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |Set this bit "1" will generate a reset signal to the DMA.
* | | |SW needs to set this bit to low to release reset signal.
* | | |0 = Normal operation.
* | | |1 = DMA IP reset.
*/
__IO uint32_t IPRST_CTL1;
/**
* IPRST_CTL2
* ===================================================================================================
* Offset: 0x0C Peripheral Reset Control Resister2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |GPIO_RST |GPIO Controller Reset
* | | |0 = GPIO module normal operation.
* | | |1 = GPIO module reset.
* |[2] |TMR0_RST |Timer0 Controller Reset
* | | |0 = Timer0 module normal operation.
* | | |1 = Timer0 module reset.
* |[3] |TMR1_RST |Timer1 Controller Reset
* | | |0 = Timer1 module normal operation.
* | | |1 = Timer1 module reset.
* |[4] |TMR2_RST |Timer2 Controller Reset
* | | |0 = Timer2 module normal operation.
* | | |1 = Timer2 module reset.
* |[5] |TMR3_RST |Timer3 Controller Reset
* | | |0 = Timer3 module normal operation.
* | | |1 = Timer3 module reset.
* |[8] |I2C0_RST |I2C0 Controller Reset
* | | |0 = I2C0 module normal operation.
* | | |1 = I2C0 module reset.
* |[9] |I2C1_RST |I2C1 Controller Reset
* | | |0 = I2C1 module normal operation.
* | | |1 = I2C1 module reset.
* |[12] |SPI0_RST |SPI0 Controller Reset
* | | |0 = SPI0 module normal operation.
* | | |1 = SPI0 module reset.
* |[13] |SPI1_RST |SPI1 Controller Reset
* | | |0 = SPI1 module normal operation.
* | | |1 = SPI1 module reset.
* |[16] |UART0_RST |UART0 Controller Reset
* | | |0 = UART0 module normal operation.
* | | |1 = UART0 module reset.
* |[17] |UART1_RST |UART1 Controller Reset
* | | |0 = UART1 module normal operation.
* | | |1 = UART1 module reset.
* |[20] |PWM0_RST |PWM0 Controller Reset
* | | |0 = PWM0 module normal operation.
* | | |1 = PWM0 module reset.
* |[22] |ACMP01_RST|Comparator Controller Reset
* | | |0 = Comparator module normal operation.
* | | |1 = Comparator module reset.
* |[26] |LCD_RST |LCD Controller Reset
* | | |0 = LCD module normal operation.
* | | |1 = LCD module reset.
* |[28] |ADC_RST |ADC Controller Reset
* | | |0 = ADC module normal operation.
* | | |1 = ADC module reset.
* |[30] |SC0_RST |SmartCard 0 Controller Reset
* | | |0 = SmartCard module normal operation.
* | | |1 = SmartCard module reset.
* |[31] |SC1_RST |SmartCard1 Controller Reset
* | | |0 = SmartCard module normal operation.
* | | |1 = SmartCard module reset.
*/
__IO uint32_t IPRST_CTL2;
/**
* TEMPCTL
* ===================================================================================================
* Offset: 0x10 Temperature Sensor Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VTEMP_EN |Temperature Sensor Enable Control
* | | |0 = Temperature sensor function Disabled (default).
* | | |1 = Temperature sensor function Enabled.
*/
__IO uint32_t TEMPCTL;
uint32_t RESERVE0[7];
/**
* PA_L_MFP
* ===================================================================================================
* Offset: 0x30 Port A Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PA0_MFP |PA.0 Pin Function Selection
* | | |0000 = GPIOA[0]
* | | |0010 = ADC input channel 0
* |[6:4] |PA1_MFP |PA.1 Pin Function Selection
* | | |0000 = GPIOA[1]
* | | |0010 = ADC analog input1
* | | |0011 = Comparator0 P-end input3
* | | |1001 = Comparator0 charge/discharge path
* |[11:8] |PA2_MFP |PA.2 Pin Function Selection
* | | |0000 = GPIOA[2]
* | | |0001 = External interrupt0 input pin
* | | |0010 = ADC analog input2
* | | |0011 = Comparator0 P-end input2
* | | |0100 = SmartCard0 clock pin(SC0_UART_TXD)
* | | |1001 = Comparator0 charge/discharge path
* |[14:12] |PA3_MFP |PA.3 Pin Function Selection
* | | |0000 = GPIOA[3]
* | | |0001 = External interrupt 1
* | | |0010 = ADC analog input3
* | | |0011 = Comparator0 P-end input1
* | | |0100 = SmartCard0 DATA pin(SC0_UART_RXD)
* | | |1001 = Comparator0 charge/discharge path
* |[19:16] |PA4_MFP |PA.4 Pin Function Selection
* | | |0000 = GPIOA[4]
* | | |0010 = ADC analog input4
* | | |0011 = Comparator0 P-end input0
* | | |0100 = SmartCard0 card detect pin
* | | |1001 = Comparator0 charge/discharge path
* |[23:20] |PA5_MFP |PA.5 Pin Function Selection
* | | |0000 = GPIOA[5]
* | | |0010 = ADC analog input5
* | | |0011 = Comparator0 N-end input0
* | | |0100 = SmartCard0 Power pin
* | | |0101 = I2C1 data I/O pin
* | | |0110 = SPI1 1st slave select pin
* | | |1001 = Comparator0 charge/discharge path
* |[27:24] |PA6_MFP |PA.6 Pin Function Selection
* | | |0000 = GPIOA[6]
* | | |0010 = ADC analog input6
* | | |0011 = Comparator0 output
* | | |0100 = SmartCard0 RST pin
* | | |1001 = Comparator0 charge/discharge path
* |[31:28] |PA7_MFP |PA.7 Pin Function Selection
* | | |0000 = GPIOA[7]
* | | |0010 = ADC input channel 7
* | | |0100 = SmartCard1 card detect
*/
__IO uint32_t PA_L_MFP;
/**
* PA_H_MFP
* ===================================================================================================
* Offset: 0x34 Port A High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PA8_MFP |PA.8 Pin Function Selection
* | | |0000 = GPIOA[8]
* | | |0100 = SmartCard0 Power pin
* |[7:4] |PA9_MFP |PA.9 Pin Function Selection
* | | |0000 = GPIOA[9]
* | | |0100 = SmartCard0 RST pin
* |[11:8] |PA10_MFP |PA.10 Pin Function Selection
* | | |0000 = GPIOA[10]
* | | |0100 = SmartCard0 CLK pin
* |[15:12] |PA11_MFP |PA.11 Pin Function Selection
* | | |0000 = GPIOA[11]
* | | |0010 = ADC external trigger input.
* | | |0100 = SmartCard0 DATA pin(SC0_UART_RXD)
* |[18:16] |PA12_MFP |PA.12 Pin Function Selection
* | | |0000 = GPIOA[12]
* | | |0011 = Comparator1 P-end input
* | | |0101 = I2C 0 clock pin
* | | |0110 = SPI1 1st MOSI (Master Out, Slave In) pin
* | | |0111 = UART0 Data transmitter output pin(This pin could modulate with PWM0 output. Please refer PWM_SEL(UARTx_CTL[26:24])).
* | | |1000 = LCD segment output 19 at 48-pin package
* |[22:20] |PA13_MFP |PA.13 Pin Function Selection
* | | |0000 = GPIOA[13]
* | | |0011 = Comparator1 N-end input
* | | |0101 = I2C0 data I/O pin
* | | |0110 = SPI1 1st MISO (Master In, Slave Out) pin
* | | |0111 = UART0 Data receiver input pin
* | | |1000 = LCD segment output 18 at 48-pin package
* |[26:24] |PA14_MFP |PA.14 Pin Function Selection
* | | |0000 = GPIOA[14]
* | | |0101 = I2C1 clock pin
* | | |0110 = SPI1 serial clock pin
* | | |1000 = LCD segment output 17 at 48-pin package, LCD segment output 31 at 64-pin package
* | | |1001 = Comparator0 charge/discharge path
* |[31:28] |PA15_MFP |PA.15 Pin Function Selection
* | | |0000 = GPIOA[15]
* | | |0010 = Timer3 capture input
* | | |0011 = Comparator1 output
* | | |0101 = I2C1 data I/O pin
* | | |0110 = SPI1 1st slave select pin
* | | |1000 = LCD segment output 16 at 48-pin package, LCD segment output 30 at 64-pin package
*/
__IO uint32_t PA_H_MFP;
/**
* PB_L_MFP
* ===================================================================================================
* Offset: 0x38 Port B Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PB0_MFP |PB.0 Pin Function Selection
* | | |0000 = GPIOB[0]
* | | |0001 = Frequency Divider1 output pin
* | | |0111 = UART0 Data transmitter output pin(This pin could modulate with PWM0 output. Please refer PWM_SEL(UARTx_CTL[26:24])).
* | | |1000 = LCD segment output 29 at 64-pin package
* |[7:4] |PB1_MFP |PB.1 Pin Function Selection
* | | |0000 = GPIOB[1]
* | | |0001 = External interrupt1 input pin
* | | |0010 = Timer 2 capture input
* | | |0111 = UART0 Data receiver input pin
* | | |1000 = LCD segment output 28 at 64-pin package
* |[11:8] |PB2_MFP |PB.2 Pin Function Selection
* | | |0000 = GPIOB[2]
* | | |0010 = Timer3 external counter input
* | | |0101 = I2C0 clock pin
* | | |0110 = SPI1 2nd MOSI (Master Out, Slave In) pin
* | | |0111 = UART0 Request to Send output pin
* | | |1000 = LCD segment output 27 at 64-pin package
* |[15:12] |PB3_MFP |PB.3 Pin Function Selection
* | | |0000 = GPIOB[3]
* | | |0010 = Timer2 external counter input
* | | |0101 = I2C0 data I/O pin
* | | |0110 = SPI1 2nd MISO (Master In, Slave Out) pin
* | | |0111 = UART0 Clear to Send input pin
* | | |1000 = LCD segment output 26 at 64-pin package
* |[19:16] |PB4_MFP |PB.4 Pin Function Selection
* | | |0000 = GPIOB[4]
* | | |0110 = SPI1 2nd MISO (Master In, Slave Out) pin
* | | |0111 = UART1 Request to Send output pin
* |[23:20] |PB5_MFP |PB.5 Pin Function Selection
* | | |0000 = GPIOB[5]
* | | |0110 = SPI1 2nd MOSI (Master Out, Slave In) pin SmartCard0 RST
* | | |0111 = UART1 Data receiver input pin
* | | |1000 = LCD segment output 35 at 100-pin package
* |[27:24] |PB6_MFP |PB.6 Pin Function Selection
* | | |0000 = GPIOB[6]
* | | |0001 = Frequency Divider0 output pin
* | | |0110 = SPI1 2nd slave select pin
* | | |0111 = UART1 Data transmitter output pin(This pin could modulate with PWM0 output. Please refer PWM_SEL(UARTx_CTL[26:24])).
* | | |1000 = LCD segment output 25 at 64-pin package, LCD segment output 34 at 100-pin package
* |[31:28] |PB7_MFP |PB.7 Pin Function Selection
* | | |0000 = GPIOB[7]
* | | |0100 = SmartCard0 card detect
* | | |0111 = UART1 Clear to Send input pin
* | | |1000 = LCD segment output 33 at 100-pin package
*/
__IO uint32_t PB_L_MFP;
/**
* PB_H_MFP
* ===================================================================================================
* Offset: 0x3C Port B High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PB8_MFP |PB.8 Pin Function Selection
* | | |0000 = GPIOB[8]
* | | |0001 = External interrupt1 input pin
* | | |0010 = Timer0 external counter input or Timer0 toggle out.
* | | |0011 = PWM0 Channel0 output
* | | |0100 = Snooper pin
* | | |1000 = LCD segment output 32 at 100-pin package
* |[7:4] |PB9_MFP |PB.9 Pin Function Selection
* | | |0000 = GPIOB[9]
* | | |0011 = PWM0 Channel1 output
* | | |1000 = LCD segment output 31 at 100-pin package
* |[11:8] |PB10_MFP |PB.10 Pin Function Selection
* | | |0000 = GPIOB[10]
* | | |0110 = SPI0 2nd MOSI (Master Out, Slave In) pin
* | | |0111 = UART1 Data receiver input pin
* | | |1000 = LCD segment output 24 at 64-pin package, LCD segment output 28 at 100-pin package
* |[15:12] |PB11_MFP |PB.11 Pin Function Selection
* | | |0000 = GPIOB[11]
* | | |0010 = Timer1 external counter input or Timer1 toggle out
* | | |0110 = SPI0 2nd MISO (Master In, Slave Out) pin
* | | |0111 = UART1 Request to Send output pin
* | | |1000 = LCD segment output 23 at 64-pin package, LCD segment output 27 at 100-pin package
* |[19:16] |PB12_MFP |PB.12 Pin Function Selection
* | | |0000 = GPIOB[12]
* | | |0001 = Frequency Divider0 output pin
* | | |0010 = Timer0 external counter input or Timer0 toggle out.
* | | |0110 = SPI0 1st MOSI (Master Out, Slave In) pin
* | | |0111 = UART0 Request to Send output pin
* | | |1000 = LCD segment output 15 at 48-pin package, LCD segment output 22 at 64-pin package, LCD segment output 26 at 100-pin package
* |[23:20] |PB13_MFP |PB.13 Pin Function Selection
* | | |0000 = GPIOB[13]
* | | |0110 = SPI0 1st MISO (Master In, Slave Out) pin
* | | |0111 = UART0 Data receiver input pin
* | | |1000 = LCD segment output 14 at 48-pin package, LCD segment output 21 at 64-pin package, LCD segment output 25 at 100-pin package
* |[27:24] |PB14_MFP |PB.14 Pin Function Selection
* | | |0000 = GPIOB[14]
* | | |0110 = SPI0 serial clock pin
* | | |0111 = UART0 Data transmitter output pin(This pin could modulate with PWM0 output)
* | | |1000 = LCD segment output 13 at 48-pin package, LCD segment output 20 at 64-pin package, LCD segment output 24 at 100-pin package
* |[31:28] |PB15_MFP |PB.15 Pin Function Selection
* | | |0000 = GPIOB[15]
* | | |0110 = SPI0 1st slave select pin
* | | |0111 = UART0 Clear to Send input pin
* | | |1000 = LCD segment output 12 at 48-pin package, LCD segment output 19 at 64-pin package, LCD segment output 23 at 100-pin package
*/
__IO uint32_t PB_H_MFP;
/**
* PC_L_MFP
* ===================================================================================================
* Offset: 0x40 Port C Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PC0_MFP |PC.0 Pin Function Selection
* | | |0000 = GPIOC[0]
* | | |0011 = PWM0 Channel0 output
* | | |0101 = I2C0 clock pin
* | | |0110 = SPI0 2nd slave select pin
* | | |1000 = LCD segment output 11 at 48-pin package, LCD segment output 18 at 64-pin package, LCD segment output 22 at 100-pin package
* |[7:4] |PC1_MFP |PC.1 Pin Function Selection
* | | |0000 = GPIOC[1]
* | | |0011 = PWM0 Channel1 output
* | | |0101 = I2C0 data I/O pin
* | | |1000 = LCD segment output 10 at 48-pin package, LCD segment output 17 at 64-pin package, LCD segment output 21 at 100-pin package
* |[11:8] |PC2_MFP |PC.2 Pin Function Selection
* | | |0000 = GPIOC[2]
* | | |0011 = PWM0 Channel2 output
* | | |0101 = I2C1 clock pin
* | | |1000 = LCD segment output 9 at 48-pin package, LCD segment output 16 at 64-pin package, LCD segment output 20 at 100-pin package
* |[15:12] |PC3_MFP |PC.3 Pin Function Selection
* | | |0000 = GPIOC[3]
* | | |0011 = PWM0 Channel3 output
* | | |0101 = I2C1 data I/O pin
* | | |1000 = LCD segment output 8 at 48-pin package, LCD segment output 15 at 64-pin package, LCD segment output 19 at 100-pin package
* |[19:16] |PC4_MFP |PC.4 Pin Function Selection
* | | |0000 = GPIOC[4]
* | | |0001 = External interrupt0 input pin
* | | |0100 = SmartCard0 clock pin(SC0_UART_TXD)
* | | |0111 = UART1 Clear to Send input pin
* | | |1000 = LCD segment output 7 at 48-pin package, LCD segment output 14 at 64-pin package, LCD segment output 18 at 100-pin package
* |[23:20] |PC5_MFP |PC.5 Pin Function Selection
* | | |0000 = GPIOC[5]
* | | |0100 = SmartCard0 card detect pin
* | | |1000 = LCD segment output 6 at 48-pin package, LCD segment output 13 at 64-pin package, LCD segment output 17 at 100-pin package
* |[27:24] |PC6_MFP |PC.6 Pin Function Selection
* | | |0000 = GPIOC[6]
* | | |0100 = SmartCard0 DATA pin(SC0_UART_RXD)
* | | |0111 = UART1 Request to Send output pin
* | | |1000 = LCD segment output 5 at 48-pin package, LCD segment output 12 at 64-pin package, LCD segment output 16 at 100-pin package
* |[31:28] |PC7_MFP |PC.7 Pin Function Selection
* | | |0000 = GPIOC[7]
* | | |0100 = SmartCard0 Power pin
* | | |0111 = UART1 Data receiver input pin
* | | |1000 = LCD segment output 4 at 48-pin package, LCD segment output 11 at 64-pin package, LCD segment output 15 at 100-pin package
*/
__IO uint32_t PC_L_MFP;
/**
* PC_H_MFP
* ===================================================================================================
* Offset: 0x44 Port C High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PC8_MFP |PC.8 Pin Function Selection
* | | |0000 = GPIOC[8]
* | | |0100 = SmartCard0 RST pin
* | | |0111 = UART1 Data transmitter output pin(This pin could modulate with PWM0 output. Please refer PWM_SEL(UARTx_CTL[26:24])).
* | | |1000 = LCD segment output 3 at 48-pin package, LCD segment output 10 at 64-pin package, LCD segment output 14 at 100-pin package
* |[7:4] |PC9_MFP |PC.9 Pin Function Selection
* | | |1000 = LCD segment output 2 at 48-pin package, LCD segment output 9 at 64-pin package, LCD segment output 13 at 100-pin package
* | | |0000 = GPIOC[9]
* |[11:8] |PC10_MFP |PC.10 Pin Function Selection
* | | |0000 = GPIOC[10]
* | | |0100 = SmartCard1 card detect
* | | |0101 = I2C1 clock pin
* | | |1000 = LCD segment output 12 at 100-pin package
* |[15:12] |PC11_MFP |PC.11 Pin Function Selection
* | | |0000 = GPIOC[11]
* | | |0100 = SmartCard1 PWR pin
* | | |0101 = I2C 1 data I/O pin
* | | |1000 = LCD segment output 11 at 100-pin package
* |[19:16] |PC12_MFP |PC.12 Pin Function Selection
* | | |0000 = GPIOC[12]
* | | |0100 = SmartCard1 clock pin(SC1_UART_TXD)
* | | |1000 = LCD segment output 10 at 100-pin package
* |[23:20] |PC13_MFP |PC.13 Pin Function Selection
* | | |0000 = GPIOC[13]
* | | |0100 = SmartCard1 DATA pin(SC1_UART_RXD)
* | | |1000 = LCD segment output 9 at 100-pin package
* |[27:24] |PC14_MFP |PC.14 Pin Function Selection
* | | |0000 = GPIOC[14]
* | | |0100 = SmartCard1 card detect
* | | |1000 = LCD segment output 1 at 48-pin package, LCD segment output 8 at 64-pin package, LCD segment output 8 at 100-pin package
* |[31:28] |PC15_MFP |PC.15 Pin Function Selection
* | | |0000 = GPIOC[15]
* | | |0100 = SmartCard1 PWR pin
* | | |1000 = LCD segment output 0 at 48-pin package, LCD segment output 7 at 64-pin package, LCD segment output 7 at 100-pin package
*/
__IO uint32_t PC_H_MFP;
/**
* PD_L_MFP
* ===================================================================================================
* Offset: 0x48 Port D Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PD0_MFP |PD.0 Pin Function Selection
* | | |0000 = GPIOD[0]
* | | |1000 = LCD segment output 6 at 64-pin package, LCD segment output 6 at 100-pin package
* |[7:4] |PD1_MFP |PD.1 Pin Function Selection
* | | |0000 = GPIOD[1]
* | | |1000 = LCD segment output 5 at 64-pin package, LCD segment output 5 at 100-pin package
* |[11:8] |PD2_MFP |PD.2 Pin Function Selection
* | | |0000 = GPIOD[2]
* | | |1000 = LCD segment output 4 at 64-pin package, LCD segment output 4 at 100-pin package
* |[15:12] |PD3_MFP |PD.3 Pin Function Selection
* | | |0000 = GPIOD[3]
* | | |1000 = LCD segment output 3 at 64-pin package, LCD segment output 3 at 100-pin package
* |[19:16] |PD4_MFP |PD.4 Pin Function Selection
* | | |0000 = GPIOD[4]
* | | |0100 = SmartCard1 RST pin
* | | |1000 = LCD segment output 2 at 64-pin package, LCD segment output 2 at 100-pin package
* |[23:20] |PD5_MFP |PD.5 Pin Function Selection
* | | |0000 = GPIOD[5]
* | | |1000 = LCD segment output 1 at 64-pin package(or as LD_COM5), LCD segment output 1 at 100-pin package(or as LD_COM5)
* |[27:24] |PD6_MFP |PD.6 Pin Function Selection
* | | |0000 = GPIOD[6]
* | | |1000 = LCD segment output 0 at 64-pin package(or as LD_COM4), LCD segment output 0 at 100-pin package(or as LD_COM4)
* |[31:28] |PD7_MFP |PD.7 Pin Function Selection
* | | |0000 = GPIOD[7]
* | | |0100 = SmartCard1 clock pin(SC1_UART_TXD)
* | | |1000 = LCD common output 3 at 48-pin package, LCD common output 3 at 64-pin, LCD common output 3 at 100-pin package
*/
__IO uint32_t PD_L_MFP;
/**
* PD_H_MFP
* ===================================================================================================
* Offset: 0x4C Port D High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |PD8_MFP |PD.8 Pin Function Selection
* | | |0000 = GPIOD[8]
* | | |0100 = SmartCard1 DATA pin(SC1_UART_RXD)
* | | |1000 = LCD common output 2 at 48-pin, LCD common output 2 at 64-pin package, LCD common output 2 at 100-pin package
* |[6:4] |PD9_MFP |PD.9 Pin Function Selection
* | | |0000 = GPIOD[9]
* | | |0011 = PWM0 Channel3 output
* | | |0100 = SmartCard1 RST pin
* | | |1000 = LCD common output 1 at 48-pin, LCD common output 1 at 64-pin package, LCD common output 1 at 100-pin package
* |[10:8] |PD10_MFP |PD.10 Pin Function Selection
* | | |0000 = GPIOD[10]
* | | |0010 = Timer1 capture input
* | | |0011 = PWM0 Channel2 output
* | | |1000 = LCD common output 0 at 48-pin, LCD common output 0 at 64-pin package, LCD common output 0 at 100-pin package
* |[14:12] |PD11_MFP |PD.11 Pin Function Selection
* | | |0000 = GPIOD[11]
* | | |0010 = Timer0 capture input
* | | |0011 = PWM0 Channel1 output
* | | |1000 = LCD external capacitor pin of charge pump circuit at 64-pin package, LCD external capacitor pin of charge pump circuit at 100-pin package
* |[18:16] |PD12_MFP |PD.12 Pin Function Selection
* | | |0000 = GPIOD[12]
* | | |0001 = Frequency Divider0 output pin
* | | |0010 = Timer1 external counter input or Timer1 toggle out
* | | |0011 = PWM0 Channel0 output
* | | |1000 = LCD external capacitor pin of charge pump circuit at 64-pin package, LCD external capacitor pin of charge pump circuit at 100-pin package
* | | |1001 = 1, 1/2, 1/4, 1/16 Hz clock output
* |[22:20] |PD13_MFP |PD.13 Pin Function Selection
* | | |0000 = GPIOD[13]
* | | |0001 = External interrupt 1 input pin
* | | |1000 = LCD Unit voltage for LCD charge pump circuit at 48-pin package, LCD Unit voltage for LCD charge pump circuit at 64-pin package, LCD Unit voltage for LCD charge pump circuit at 100-pin package
* |[27:24] |PD14_MFP |PD.14 Pin Function Selection
* | | |0000 = GPIOD[14]
* | | |1000 = LCD Unit voltage for LCD charge pump circuit at 48-pin package, LCD Unit voltage for LCD charge pump circuit at 64-pin package, LCD Unit voltage for LCD charge pump circuit at 100-pin package
* |[30:28] |PD15_MFP |PD.15 Pin Function Selection
* | | |0000 = GPIOD[15]
* | | |1000 = LCD Unit voltage for LCD charge pump circuit at 48-pin package, LCD Unit voltage for LCD charge pump circuit at 64-pin package, LCD Unit voltage for LCD charge pump circuit at 100-pin package
*/
__IO uint32_t PD_H_MFP;
/**
* PE_L_MFP
* ===================================================================================================
* Offset: 0x50 Port E Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |PE0_MFP |PE.0 Pin Function Selection
* | | |0000 = GPIOE[0]
* | | |0110 = SPI0 1st MOSI (Master Out, Slave In) pin
* |[6:4] |PE1_MFP |PE.1 Pin Function Selection
* | | |0000 = GPIOE[1]
* | | |0110 = SPI0 1st MISO (Master In, Slave Out) pin
* |[10:8] |PE2_MFP |PE.2 Pin Function Selection
* | | |0000 = GPIOE[2]
* | | |0110 = SPI0 serial clock pin
* |[15] |PE3_MFP |PE.3 Pin Function Selection
* | | |0000 = GPIOE[4]
* | | |0110 = SPI0 1st slave select pin
* |[18:16] |PE4_MFP |PE.4 Pin Function Selection
* | | |0000 = GPIOE[4]
* | | |0100 = SmartCard1 RST pin
* |[23:20] |PE5_MFP |PE.5 Pin Function Selection
* | | |0000 = GPIOE[5]
* | | |0100 = SmartCard1 PWR pin
* |[27:24] |PE6_MFP |PE.6 Pin Function Selection
* | | |0000 = GPIOE[6]
* | | |0100 = SmartCard1 clock pin(SC1_UART_TXD)
* |[31:28] |PE7_MFP |PE.7 Pin Function Selection
* | | |0000 = GPIOE[7]
* | | |0100 = SmartCard1 DATA pin(SC1_UART_RXD)
*/
__IO uint32_t PE_L_MFP;
/**
* PE_H_MFP
* ===================================================================================================
* Offset: 0x54 Port E High Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PE8_MFP |PE.8 Pin Function Selection
* | | |0000 = GPIOE[8]
* | | |0011 = PWM0 Channel2 output
* | | |1000 = LCD segment output 30 at 100-pin package
* |[7:4] |PE9_MFP |PE.9 Pin Function Selection
* | | |0000 = GPIOE[9]
* | | |0011 = PWM0 Channel3 output
* | | |1000 = LCD segment output 29 at 100-pin package
*/
__IO uint32_t PE_H_MFP;
/**
* PF_L_MFP
* ===================================================================================================
* Offset: 0x58 Port F Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |PF0_MFP |PF.0 Pin Function Selection
* | | |0000 = GPIOF[1]
* | | |0010 = Timer3 external counter input or Timer3 toggle out.
* | | |1111 = External 32.768 kHz crystal input pin(default)
* |[7:4] |PF1_MFP |PF.1 Pin Function Selection
* | | |0000 = GPIOF[1]
* | | |0010 = Timer2 external counter input or Timer2 toggle out.
* | | |1111 = External 32.768 kHz crystal output pin(default)
* |[11:8] |PF2_MFP |PF.2 Pin Function Selection
* | | |0000 = GPIOF[2]
* | | |0001 = External interrupt1 input pin
* | | |0010 = Timer3 capture input
* | | |0111 = UART1 Data receiver input pin
* | | |1111 = External 4~24 MHz crystal input pin(default)
* |[15:12] |PF3_MFP |PF.3 Pin Function Selection
* | | |0000 = GPIOF[3]
* | | |0001 = External interrupt0 input pin
* | | |0010 = Timer 2 capture input
* | | |0111 = UART1 Data transmitter output pin(This pin could modulate with PWM0 output. Please refer PWM_SEL(UARTx_CTL[26:24])).
* | | |1111 = External 4~24 MHz crystal output pin
* |[19:16] |PF4_MFP |PF.4 Pin Function Selection
* | | |0000 = GPIOF[4]
* | | |0001 = Frequency Divider1 output pin
* | | |0010 = Timer1 capture input
* | | |0011 = PWM0 Channel2 output
* | | |1001 = 1, 1/2, 1/4, 1/8, 1/16 Hz clock output
* | | |1111 = Serial Wired Debugger Clock pin
* |[23:20] |PF5_MFP |PF.5 Pin Function Selection
* | | |0000 = GPIOF[5]
* | | |0010 = Timer0 capture input
* | | |0011 = PWM0 Channel3 output
* | | |1001 = Comparator0 charge/discharge path
* | | |1111 = Serial Wired Debugger Data pin
*/
__IO uint32_t PF_L_MFP;
uint32_t RESERVE1[1];
/**
* PORCTL
* ===================================================================================================
* Offset: 0x60 Power-On-Reset Controller Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |POR_DIS_CODE|Power-On Reset Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
* | | |If setting the POR_DIS_CODE to 0x5AA5, the POR reset function will be disabled and the POR function will be active again when POR_DIS_CODE is set to another value or POR_DIS_CODE is reset by chip other reset functions, including: /RESET, Watchdog Timer reset, BOD reset, ICE reset command and the software-chip reset function.
*/
__IO uint32_t PORCTL;
/**
* BODCTL
* ===================================================================================================
* Offset: 0x64 Brown-out Detector Controller Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BOD17_EN |Brown-Out Detector 1.7V Function Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |The default value is set by flash controller user configuration register config0 bit[20:19]
* | | |Users can disable BOD17_EN but it takes effective (disabled) only in Power-down mode.
* | | |Once existing Power-down mode, BOD17 will be enabled by HW automatically.
* | | |When CPU reads this bit, CPU will read whether BOD17 function enabled or not.
* | | |In other words,CPU will always read high.
* | | |0 = Brown-out Detector 1.7V function Disabled.
* | | |1 = Brown-out Detector 1.7V function Enabled.
* |[1] |BOD20_EN |Brown-Out Detector 2.0 V Function Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Brown-out Detector 2.0 V function Disabled.
* | | |1 = Brown-out Detector 2.0 V function Enabled.
* | | |BOD20_EN is default on.
* | | |If SW disables it, Brown-out Detector 2.0 V function is not disabled until chip enters power-down mode.
* | | |If system is not in power-down mode, BOD20_EN will be enabled by hardware automatically.
* |[2] |BOD25_EN |Brown-Out Detector 2.5 V Function Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Brown-out Detector 2.5 V function Disabled.
* | | |1 = Brown-out Detector 2.5 V function Enabled.
* |[4] |BOD17_RST_EN|BOD 1.7 V Reset Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Reset does not issue when BOD17 occurs.
* | | |1 = Reset issues when BOD17 occurs.
* | | |The default value is set by flash controller user configuration register config0 bit[20:19]
* |[5] |BOD20_RST_EN|BOD 2.0 V Reset Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Reset does not issue when BOD20 occurs.
* | | |1 = Reset issues when BOD20 occurs.
* | | |The default value is set by flash controller user configuration register config0 bit[20:19]
* |[6] |BOD25_RST_EN|BOD 2.5 V Reset Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Reset does not issue when BOD25 occurs.
* | | |1 = Reset issues when BOD25 occurs.
* | | |The default value is set by flash controller user configuration register config0 bit[20:19]
* |[8] |BOD17_INT_EN|BOD 1.7 V Interrupt Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Interrupt does not issue when BOD17 occurs.
* | | |1 = Interrupt issues when BOD17 occurs.
* |[9] |BOD20_INT_EN|BOD 2.0 V Interrupt Enable Control
* | | |0 = Interrupt does not issue when BOD20 occurs.
* | | |1 = Interrupt issues when BOD20 occurs.
* |[10] |BOD25_INT_EN|BOD 2.5 V Interrupt Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Interrupt does not issue when BOD25 occurs.
* | | |1 = Interrupt issues when BOD25 occurs.
* |[15:12] |BOD17_TRIM|BOD 1.7 TRIM Value
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |This value is used to control BOD17 detect voltage level, nominal 1.7 V.
* | | |Higher trim value, higher detection voltage.
* |[19:16] |BOD20_TRIM|BOD 2.0 TRIM Value
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |This value is used to control BOD20 detect voltage level, nominal 2.0 V.
* | | |Higher trim value, higher detection voltage.
* |[23:20] |BOD25_TRIM|BOD 2.5 TRIM Value
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |This value is used to control BOD25 detect voltage level, nominal 2.5 V.
* | | |Higher trim value, higher detection voltage.
*/
__IO uint32_t BODCTL;
/**
* BODSTS
* ===================================================================================================
* Offset: 0x68 Brown-out Detector Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BOD_INT |Brown-Out Detector Interrupt Status
* | | |0 = Brown-out Detector does not detect any voltage drift at VDD down through or up through the target detected voltage after interrupt is enabled.
* | | |1 = When Brown-out Detector detects the VDD is dropped down through the target detected voltage or the VDD is raised up through the target detected voltage and Brown-out interrupt is enabled, this bit will be set to 1.
* | | |This bit is cleared by writing 1 to it.
* |[1] |BOD17_drop|Brown-Out Detector Lower Than 1.7V Status
* | | |Setting BOD17_drop high means once the detected voltage is lower than target detected voltage setting (1.7V).
* | | |Software can write 1 to clear BOD17_drop.
* |[2] |BOD20_drop|Brown-Out Detector Lower Than 2.0V Status
* | | |Setting BOD20_drop high means once the detected voltage is lower than target detected voltage setting (2.0V).
* | | |Software can write 1 to clear BOD20_drop.
* |[3] |BOD25_drop|Brown-Out Detector Lower Than 2.5V Status
* | | |Setting BOD25_drop high means once the detected voltage is lower than target detected voltage setting (2.5V).
* | | |Software can write 1 to clear BOD25_drop.
* |[4] |BOD17_rise|Brown-Out Detector Higher Than 1.7V Status
* | | |Setting BOD17_rise high means once the detected voltage is higher than target detected voltage setting (1.7V).
* | | |Software can write 1 to clear BOD17_rise.
* |[5] |BOD20_rise|Brown-Out Detector Higher Than 2.0V Status
* | | |Setting BOD20_rise high means once the detected voltage is higher than target detected voltage setting (2.0V).
* | | |Software can write 1 to clear BOD20_rise.
* |[6] |BOD25_rise|Brown-Out Detector Higher Than 2.5V Status
* | | |Setting BOD25_rise high means once the detected voltage is higher than target detected voltage setting (2.5V).
* | | |Software can write 1 to clear BOD25_rise.
* |[8] |BOD17 |Brown-Out Detector 1.7V Status
* | | |This bit reflects the BOD17 status.
* | | |BOD17 is high if detected voltage is higher than 1.7 V.
* | | |BOD17 is low if detected voltage is lower than 1.7 V.
* | | |Note: This bit is ready-only.
* |[9] |BOD20 |Brown-Out Detector 2.0V Status
* | | |This bit reflects the BOD20 status.
* | | |BOD20 is high if detected voltage is higher than 2.0 V.
* | | |BOD20 is low if detected voltage is lower than 2.0 V.
* | | |Note: This bit is ready-only.
* |[10] |BOD25 |Brown-Out Detector 2.5V Status
* | | |This bit reflects the BOD25 status.
* | | |BOD25 is high if detected voltage is higher than 2.5 V.
* | | |BOD25 is low if detected voltage is lower than 2.5 V.
* | | |Note: This bit is ready-only.
*/
__IO uint32_t BODSTS;
/**
* Int_VREFCTL
* ===================================================================================================
* Offset: 0x6C Internal Voltage Reference Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BGP_EN |Band-Gap Enable Control
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |Band-gap is the reference voltage of internal reference voltage.
* | | |User must enable band-gap if want to enable internal 1.5, 1.8V or 2.5V reference voltage.
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[1] |REG_EN |Regulator Enable Control
* | | |Enable internal 1.5, 1.8V or 2.5V reference voltage.
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[3:2] |SEL25 |Regulator Output Voltage Selection
* | | |Select internal reference voltage level.
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |00 = 1.5V.
* | | |01 = 1.8V.
* | | |10 = 2.5V.
* | | |11 = 2.5V.
* |[4] |EXT_MODE |Regulator External Mode
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |Users can output regulator output voltage in VREF pin if EXT_MODE is high.
* | | |0 = No connection with external VREF pin.
* | | |1 = Connect to external VREF pin.
* | | |Connect a 1uF to 10uF capacitor to AVSS will let internal voltage reference be more stable.
* |[11:8] |VREF_TRIM |Internal Voltage Reference Trim
*/
__IO uint32_t Int_VREFCTL;
/**
* LDO_CTL
* ===================================================================================================
* Offset: 0x70 LDO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LDO_PD |LDO Power Off
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |Set this bit high will off LDO and cause Chip in unexpected state. User must keep this bit low.
* | | |0 = LDO Enabled.
* | | |1 = LDO Disabled.
* |[3:2] |LDO_LEVEL |LDO Output Voltage Select
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |00 = Reserved.
* | | |01 = 1.6V.
* | | |10 = 1.8V.
* | | |11 = 1.8V.
*/
__IO uint32_t LDO_CTL;
uint32_t RESERVE2[3];
/**
* IRCTRIMCTL
* ===================================================================================================
* Offset: 0x80 HIRC Trim Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |TRIM_SEL |Trim Frequency Selection
* | | |This field indicates the target frequency of HIRC auto trim.
* | | |If no any target frequency is selected (TRIM_SEL is 00), the HIRC auto trim function is disabled.
* | | |During auto trim operation, if 32.768 kHz clock error detected or trim retry limitation count reached, this field will be cleared to 00 automatically.
* | | |00 = Disable HIRC auto trim function
* | | |01 = Enable HIRC auto trim function and trim HIRC to 11.0592 MHz
* | | |10 = Enable HIRC auto trim function and trim HIRC to 12 MHz
* | | |11 = Enable HIRC auto trim function and trim HIRC to 16 MHz
* |[5:4] |TRIM_LOOP |Trim Calculation Loop
* | | |This field defines that trim value calculation is based on how many 32.768 kHz clock.
* | | |00 = 4 x 32.768 kHz clock
* | | |01 = 8 x 32.768 kHz clock
* | | |10 = 16 x 32.768 kHz clock
* | | |11 = 32 x 32.768 kHz clock
* |[7:6] |TRIM_RETRY_CNT|Trim Value Update Limitation Count
* | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
* | | |Once the HIRC locked, the internal trim value update counter will be reset.
* | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and TRIM_SEL will be cleared to 00.
* | | |00 = Trim retry count limitation is 64
* | | |01 = Trim retry count limitation is 128
* | | |10 = Trim retry count limitation is 256
* | | |11 = Trim retry count limitation is 512
* |[8] |ERR_STOP |Trim Stop When 32.768 KHz Error Detected
* | | |This bit is used to control if stop the HIRC trim operation when 32.768 kHz clock error is detected.
* | | |If set this bit high and 32.768 kHz clock error detected, the status 32K_ERR_INT would be set high and HIRC trim operation was stopped.
* | | |If this bit is low and 32.768 kHz clock error detected, the status 23K_ERR_INT would be set high and HIRC trim operation is continuously.
* | | |0 = Continue the HIRC trim operation even if 32.768 kHz clock error detected.
* | | |1 = Stop the HIRC trim operation if 32.768 kHz clock error detected.
*/
__IO uint32_t IRCTRIMCTL;
/**
* IRCTRIMIEN
* ===================================================================================================
* Offset: 0x84 HIRC Trim Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TRIM_FAIL_IEN|Trim Failure Interrupt Enable Control
* | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL.
* | | |If this bit is high and TRIM_FAIL_INT is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
* | | |0 = TRIM_FAIL_INT status Disabled to trigger an interrupt to CPU.
* | | |1 = TRIM_FAIL_INT status Enabled to trigger an interrupt to CPU.
* |[2] |32K_ERR_IEN|32.768 KHz Clock Error Interrupt Enable Control
* | | |This bit controls if CPU would get an interrupt while 32.768 kHz clock is inaccuracy during auto trim operation.
* | | |If this bit is high, and 32K_ERR_INT is set during auto trim operation, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy.
* | | |0 = 32K_ERR_INT status Disabled to trigger an interrupt to CPU.
* | | |1 = 32K_ERR_INT status Enabled to trigger an interrupt to CPU.
*/
__IO uint32_t IRCTRIMIEN;
/**
* IRCTRIMINT
* ===================================================================================================
* Offset: 0x88 HIRC Trim Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FREQ_LOCK |HIRC Frequency Lock Status
* | | |This bit indicates the HIRC frequency lock.
* | | |This is a status bit and doesn't trigger any interrupt.
* |[1] |TRIM_FAIL_INT|Trim Failure Interrupt Status
* | | |This bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock.
* | | |Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically.
* | | |If this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
* | | |Write 1 to clear this to zero.
* | | |0 = Trim value update limitation count doesn't reach.
* | | |1 = Trim value update limitation count reached and HIRC frequency still doesn't lock.
* |[2] |32K_ERR_INT|32.768 KHz Clock Error Interrupt Status
* | | |This bit indicates that 32.768 kHz clock frequency is inaccuracy.
* | | |Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically.
* | | |If this bit is set and 32K_ERR_IEN is high, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy.
* | | |Write 1 to clear this to zero.
* | | |0 = 32.768 kHz clock frequency is accuracy.
* | | |1 = 32.768 kHz clock frequency is inaccuracy.
*/
__IO uint32_t IRCTRIMINT;
uint32_t RESERVE3[29];
/**
* RegLockAddr
* ===================================================================================================
* Offset: 0x100 Register Lock Key address
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RegUnLock |Protected Register Enable Control
* | | |0 = Protected register are Locked. Any write to the target register is ignored.
* | | |1 = Protected registers are Unlocked.
*/
__IO uint32_t RegLockAddr;
} SYS_T;
/**
@addtogroup SYS_CONST SYS Bit Field Definition
Constant Definitions for SYS Controller
@{ */
#define SYS_PDID_PDID_Pos (0) /*!< SYS PDID: PDID Position */
#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS PDID: PDID Mask */
#define SYS_RST_SRC_RSTS_POR_Pos (0) /*!< SYS SRC: RSTS_POR Position */
#define SYS_RST_SRC_RSTS_POR_Msk (0x1ul << SYS_RST_SRC_RSTS_POR_Pos) /*!< SYS SRC: RSTS_POR Mask */
#define SYS_RST_SRC_RSTS_PAD_Pos (1) /*!< SYS SRC: RSTS_PAD Position */
#define SYS_RST_SRC_RSTS_PAD_Msk (0x1ul << SYS_RST_SRC_RSTS_PAD_Pos) /*!< SYS SRC: RSTS_PAD Mask */
#define SYS_RST_SRC_RSTS_WDT_Pos (2) /*!< SYS SRC: RSTS_WDT Position */
#define SYS_RST_SRC_RSTS_WDT_Msk (0x1ul << SYS_RST_SRC_RSTS_WDT_Pos) /*!< SYS SRC: RSTS_WDT Mask */
#define SYS_RST_SRC_RSTS_BOD_Pos (4) /*!< SYS SRC: RSTS_BOD Position */
#define SYS_RST_SRC_RSTS_BOD_Msk (0x1ul << SYS_RST_SRC_RSTS_BOD_Pos) /*!< SYS SRC: RSTS_BOD Mask */
#define SYS_RST_SRC_RSTS_SYS_Pos (5) /*!< SYS SRC: RSTS_SYS Position */
#define SYS_RST_SRC_RSTS_SYS_Msk (0x1ul << SYS_RST_SRC_RSTS_SYS_Pos) /*!< SYS SRC: RSTS_SYS Mask */
#define SYS_RST_SRC_RSTS_CPU_Pos (7) /*!< SYS SRC: RSTS_CPU Position */
#define SYS_RST_SRC_RSTS_CPU_Msk (0x1ul << SYS_RST_SRC_RSTS_CPU_Pos) /*!< SYS SRC: RSTS_CPU Mask */
#define SYS_IPRST_CTL1_CHIP_RST_Pos (0) /*!< SYS IPRST_CTL1: CHIP_RST Position */
#define SYS_IPRST_CTL1_CHIP_RST_Msk (0x1ul << SYS_IPRST_CTL1_CHIP_RST_Pos) /*!< SYS IPRST_CTL1: CHIP_RST Mask */
#define SYS_IPRST_CTL1_CPU_RST_Pos (1) /*!< SYS IPRST_CTL1: CPU_RST Position */
#define SYS_IPRST_CTL1_CPU_RST_Msk (0x1ul << SYS_IPRST_CTL1_CPU_RST_Pos) /*!< SYS IPRST_CTL1: CPU_RST Mask */
#define SYS_IPRST_CTL1_DMA_RST_Pos (2) /*!< SYS IPRST_CTL1: DMA_RST Position */
#define SYS_IPRST_CTL1_DMA_RST_Msk (0x1ul << SYS_IPRST_CTL1_DMA_RST_Pos) /*!< SYS IPRST_CTL1: DMA_RST Mask */
#define SYS_IPRST_CTL2_GPIO_RST_Pos (1) /*!< SYS IPRST_CTL2: GPIO_RST Position */
#define SYS_IPRST_CTL2_GPIO_RST_Msk (0x1ul << SYS_IPRST_CTL2_GPIO_RST_Pos) /*!< SYS IPRST_CTL2: GPIO_RST Mask */
#define SYS_IPRST_CTL2_TMR0_RST_Pos (2) /*!< SYS IPRST_CTL2: TMR0_RST Position */
#define SYS_IPRST_CTL2_TMR0_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR0_RST_Pos) /*!< SYS IPRST_CTL2: TMR0_RST Mask */
#define SYS_IPRST_CTL2_TMR1_RST_Pos (3) /*!< SYS IPRST_CTL2: TMR1_RST Position */
#define SYS_IPRST_CTL2_TMR1_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR1_RST_Pos) /*!< SYS IPRST_CTL2: TMR1_RST Mask */
#define SYS_IPRST_CTL2_TMR2_RST_Pos (4) /*!< SYS IPRST_CTL2: TMR2_RST Position */
#define SYS_IPRST_CTL2_TMR2_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR2_RST_Pos) /*!< SYS IPRST_CTL2: TMR2_RST Mask */
#define SYS_IPRST_CTL2_TMR3_RST_Pos (5) /*!< SYS IPRST_CTL2: TMR3_RST Position */
#define SYS_IPRST_CTL2_TMR3_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR3_RST_Pos) /*!< SYS IPRST_CTL2: TMR3_RST Mask */
#define SYS_IPRST_CTL2_I2C0_RST_Pos (8) /*!< SYS IPRST_CTL2: I2C0_RST Position */
#define SYS_IPRST_CTL2_I2C0_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C0_RST_Pos) /*!< SYS IPRST_CTL2: I2C0_RST Mask */
#define SYS_IPRST_CTL2_I2C1_RST_Pos (9) /*!< SYS IPRST_CTL2: I2C1_RST Position */
#define SYS_IPRST_CTL2_I2C1_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C1_RST_Pos) /*!< SYS IPRST_CTL2: I2C1_RST Mask */
#define SYS_IPRST_CTL2_SPI0_RST_Pos (12) /*!< SYS IPRST_CTL2: SPI0_RST Position */
#define SYS_IPRST_CTL2_SPI0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI0_RST_Pos) /*!< SYS IPRST_CTL2: SPI0_RST Mask */
#define SYS_IPRST_CTL2_SPI1_RST_Pos (13) /*!< SYS IPRST_CTL2: SPI1_RST Position */
#define SYS_IPRST_CTL2_SPI1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI1_RST_Pos) /*!< SYS IPRST_CTL2: SPI1_RST Mask */
#define SYS_IPRST_CTL2_UART0_RST_Pos (16) /*!< SYS IPRST_CTL2: UART0_RST Position */
#define SYS_IPRST_CTL2_UART0_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART0_RST_Pos) /*!< SYS IPRST_CTL2: UART0_RST Mask */
#define SYS_IPRST_CTL2_UART1_RST_Pos (17) /*!< SYS IPRST_CTL2: UART1_RST Position */
#define SYS_IPRST_CTL2_UART1_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART1_RST_Pos) /*!< SYS IPRST_CTL2: UART1_RST Mask */
#define SYS_IPRST_CTL2_PWM0_RST_Pos (20) /*!< SYS IPRST_CTL2: PWM0_RST Position */
#define SYS_IPRST_CTL2_PWM0_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM0_RST_Pos) /*!< SYS IPRST_CTL2: PWM0_RST Mask */
#define SYS_IPRST_CTL2_ACMP01_RST_Pos (22) /*!< SYS IPRST_CTL2: ACMP01_RST Position */
#define SYS_IPRST_CTL2_ACMP01_RST_Msk (0x1ul << SYS_IPRST_CTL2_ACMP01_RST_Pos) /*!< SYS IPRST_CTL2: ACMP01_RST Mask */
#define SYS_IPRST_CTL2_LCD_RST_Pos (26) /*!< SYS IPRST_CTL2: LCD_RST Position */
#define SYS_IPRST_CTL2_LCD_RST_Msk (0x1ul << SYS_IPRST_CTL2_LCD_RST_Pos) /*!< SYS IPRST_CTL2: LCD_RST Mask */
#define SYS_IPRST_CTL2_ADC_RST_Pos (28) /*!< SYS IPRST_CTL2: ADC_RST Position */
#define SYS_IPRST_CTL2_ADC_RST_Msk (0x1ul << SYS_IPRST_CTL2_ADC_RST_Pos) /*!< SYS IPRST_CTL2: ADC_RST Mask */
#define SYS_IPRST_CTL2_SC0_RST_Pos (30) /*!< SYS IPRST_CTL2: SC0_RST Position */
#define SYS_IPRST_CTL2_SC0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC0_RST_Pos) /*!< SYS IPRST_CTL2: SC0_RST Mask */
#define SYS_IPRST_CTL2_SC1_RST_Pos (31) /*!< SYS IPRST_CTL2: SC1_RST Position */
#define SYS_IPRST_CTL2_SC1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC1_RST_Pos) /*!< SYS IPRST_CTL2: SC1_RST Mask */
#define SYS_TEMPCTL_VTEMP_EN_Pos (0) /*!< SYS TEMPCTL: VTEMP_EN Position */
#define SYS_TEMPCTL_VTEMP_EN_Msk (0x1ul << SYS_TEMPCTL_VTEMP_EN_Pos) /*!< SYS TEMPCTL: VTEMP_EN Mask */
#define SYS_PA_L_MFP_PA0_MFP_Pos (0) /*!< SYS PA_L_MFP: PA0_MFP Position */
#define SYS_PA_L_MFP_PA0_MFP_Msk (0xful << SYS_PA_L_MFP_PA0_MFP_Pos) /*!< SYS PA_L_MFP: PA0_MFP Mask */
#define SYS_PA_L_MFP_PA1_MFP_Pos (4) /*!< SYS PA_L_MFP: PA1_MFP Position */
#define SYS_PA_L_MFP_PA1_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA1_MFP_Pos) /*!< SYS PA_L_MFP: PA1_MFP Mask */
#define SYS_PA_L_MFP_PA2_MFP_Pos (8) /*!< SYS PA_L_MFP: PA2_MFP Position */
#define SYS_PA_L_MFP_PA2_MFP_Msk (0xful << SYS_PA_L_MFP_PA2_MFP_Pos) /*!< SYS PA_L_MFP: PA2_MFP Mask */
#define SYS_PA_L_MFP_PA3_MFP_Pos (12) /*!< SYS PA_L_MFP: PA3_MFP Position */
#define SYS_PA_L_MFP_PA3_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA3_MFP_Pos) /*!< SYS PA_L_MFP: PA3_MFP Mask */
#define SYS_PA_L_MFP_PA4_MFP_Pos (16) /*!< SYS PA_L_MFP: PA4_MFP Position */
#define SYS_PA_L_MFP_PA4_MFP_Msk (0xful << SYS_PA_L_MFP_PA4_MFP_Pos) /*!< SYS PA_L_MFP: PA4_MFP Mask */
#define SYS_PA_L_MFP_PA5_MFP_Pos (20) /*!< SYS PA_L_MFP: PA5_MFP Position */
#define SYS_PA_L_MFP_PA5_MFP_Msk (0xful << SYS_PA_L_MFP_PA5_MFP_Pos) /*!< SYS PA_L_MFP: PA5_MFP Mask */
#define SYS_PA_L_MFP_PA6_MFP_Pos (24) /*!< SYS PA_L_MFP: PA6_MFP Position */
#define SYS_PA_L_MFP_PA6_MFP_Msk (0xful << SYS_PA_L_MFP_PA6_MFP_Pos) /*!< SYS PA_L_MFP: PA6_MFP Mask */
#define SYS_PA_L_MFP_PA7_MFP_Pos (28) /*!< SYS PA_L_MFP: PA7_MFP Position */
#define SYS_PA_L_MFP_PA7_MFP_Msk (0xful << SYS_PA_L_MFP_PA7_MFP_Pos) /*!< SYS PA_L_MFP: PA7_MFP Mask */
#define SYS_PA_H_MFP_PA8_MFP_Pos (0) /*!< SYS PA_H_MFP: PA8_MFP Position */
#define SYS_PA_H_MFP_PA8_MFP_Msk (0xful << SYS_PA_H_MFP_PA8_MFP_Pos) /*!< SYS PA_H_MFP: PA8_MFP Mask */
#define SYS_PA_H_MFP_PA9_MFP_Pos (4) /*!< SYS PA_H_MFP: PA9_MFP Position */
#define SYS_PA_H_MFP_PA9_MFP_Msk (0xful << SYS_PA_H_MFP_PA9_MFP_Pos) /*!< SYS PA_H_MFP: PA9_MFP Mask */
#define SYS_PA_H_MFP_PA10_MFP_Pos (8) /*!< SYS PA_H_MFP: PA10_MFP Position */
#define SYS_PA_H_MFP_PA10_MFP_Msk (0xful << SYS_PA_H_MFP_PA10_MFP_Pos) /*!< SYS PA_H_MFP: PA10_MFP Mask */
#define SYS_PA_H_MFP_PA11_MFP_Pos (12) /*!< SYS PA_H_MFP: PA11_MFP Position */
#define SYS_PA_H_MFP_PA11_MFP_Msk (0xful << SYS_PA_H_MFP_PA11_MFP_Pos) /*!< SYS PA_H_MFP: PA11_MFP Mask */
#define SYS_PA_H_MFP_PA12_MFP_Pos (16) /*!< SYS PA_H_MFP: PA12_MFP Position */
#define SYS_PA_H_MFP_PA12_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA12_MFP_Pos) /*!< SYS PA_H_MFP: PA12_MFP Mask */
#define SYS_PA_H_MFP_PA13_MFP_Pos (20) /*!< SYS PA_H_MFP: PA13_MFP Position */
#define SYS_PA_H_MFP_PA13_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA13_MFP_Pos) /*!< SYS PA_H_MFP: PA13_MFP Mask */
#define SYS_PA_H_MFP_PA14_MFP_Pos (24) /*!< SYS PA_H_MFP: PA14_MFP Position */
#define SYS_PA_H_MFP_PA14_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA14_MFP_Pos) /*!< SYS PA_H_MFP: PA14_MFP Mask */
#define SYS_PA_H_MFP_PA15_MFP_Pos (28) /*!< SYS PA_H_MFP: PA15_MFP Position */
#define SYS_PA_H_MFP_PA15_MFP_Msk (0xful << SYS_PA_H_MFP_PA15_MFP_Pos) /*!< SYS PA_H_MFP: PA15_MFP Mask */
#define SYS_PB_L_MFP_PB0_MFP_Pos (0) /*!< SYS PB_L_MFP: PB0_MFP Position */
#define SYS_PB_L_MFP_PB0_MFP_Msk (0xful << SYS_PB_L_MFP_PB0_MFP_Pos) /*!< SYS PB_L_MFP: PB0_MFP Mask */
#define SYS_PB_L_MFP_PB1_MFP_Pos (4) /*!< SYS PB_L_MFP: PB1_MFP Position */
#define SYS_PB_L_MFP_PB1_MFP_Msk (0xful << SYS_PB_L_MFP_PB1_MFP_Pos) /*!< SYS PB_L_MFP: PB1_MFP Mask */
#define SYS_PB_L_MFP_PB2_MFP_Pos (8) /*!< SYS PB_L_MFP: PB2_MFP Position */
#define SYS_PB_L_MFP_PB2_MFP_Msk (0xful << SYS_PB_L_MFP_PB2_MFP_Pos) /*!< SYS PB_L_MFP: PB2_MFP Mask */
#define SYS_PB_L_MFP_PB3_MFP_Pos (12) /*!< SYS PB_L_MFP: PB3_MFP Position */
#define SYS_PB_L_MFP_PB3_MFP_Msk (0xful << SYS_PB_L_MFP_PB3_MFP_Pos) /*!< SYS PB_L_MFP: PB3_MFP Mask */
#define SYS_PB_L_MFP_PB4_MFP_Pos (16) /*!< SYS PB_L_MFP: PB4_MFP Position */
#define SYS_PB_L_MFP_PB4_MFP_Msk (0xful << SYS_PB_L_MFP_PB4_MFP_Pos) /*!< SYS PB_L_MFP: PB4_MFP Mask */
#define SYS_PB_L_MFP_PB5_MFP_Pos (20) /*!< SYS PB_L_MFP: PB5_MFP Position */
#define SYS_PB_L_MFP_PB5_MFP_Msk (0xful << SYS_PB_L_MFP_PB5_MFP_Pos) /*!< SYS PB_L_MFP: PB5_MFP Mask */
#define SYS_PB_L_MFP_PB6_MFP_Pos (24) /*!< SYS PB_L_MFP: PB6_MFP Position */
#define SYS_PB_L_MFP_PB6_MFP_Msk (0xful << SYS_PB_L_MFP_PB6_MFP_Pos) /*!< SYS PB_L_MFP: PB6_MFP Mask */
#define SYS_PB_L_MFP_PB7_MFP_Pos (28) /*!< SYS PB_L_MFP: PB7_MFP Position */
#define SYS_PB_L_MFP_PB7_MFP_Msk (0xful << SYS_PB_L_MFP_PB7_MFP_Pos) /*!< SYS PB_L_MFP: PB7_MFP Mask */
#define SYS_PB_H_MFP_PB8_MFP_Pos (0) /*!< SYS PB_H_MFP: PB8_MFP Position */
#define SYS_PB_H_MFP_PB8_MFP_Msk (0xful << SYS_PB_H_MFP_PB8_MFP_Pos) /*!< SYS PB_H_MFP: PB8_MFP Mask */
#define SYS_PB_H_MFP_PB9_MFP_Pos (4) /*!< SYS PB_H_MFP: PB9_MFP Position */
#define SYS_PB_H_MFP_PB9_MFP_Msk (0xful << SYS_PB_H_MFP_PB9_MFP_Pos) /*!< SYS PB_H_MFP: PB9_MFP Mask */
#define SYS_PB_H_MFP_PB10_MFP_Pos (8) /*!< SYS PB_H_MFP: PB10_MFP Position */
#define SYS_PB_H_MFP_PB10_MFP_Msk (0xful << SYS_PB_H_MFP_PB10_MFP_Pos) /*!< SYS PB_H_MFP: PB10_MFP Mask */
#define SYS_PB_H_MFP_PB11_MFP_Pos (12) /*!< SYS PB_H_MFP: PB11_MFP Position */
#define SYS_PB_H_MFP_PB11_MFP_Msk (0xful << SYS_PB_H_MFP_PB11_MFP_Pos) /*!< SYS PB_H_MFP: PB11_MFP Mask */
#define SYS_PB_H_MFP_PB12_MFP_Pos (16) /*!< SYS PB_H_MFP: PB12_MFP Position */
#define SYS_PB_H_MFP_PB12_MFP_Msk (0xful << SYS_PB_H_MFP_PB12_MFP_Pos) /*!< SYS PB_H_MFP: PB12_MFP Mask */
#define SYS_PB_H_MFP_PB13_MFP_Pos (20) /*!< SYS PB_H_MFP: PB13_MFP Position */
#define SYS_PB_H_MFP_PB13_MFP_Msk (0xful << SYS_PB_H_MFP_PB13_MFP_Pos) /*!< SYS PB_H_MFP: PB13_MFP Mask */
#define SYS_PB_H_MFP_PB14_MFP_Pos (24) /*!< SYS PB_H_MFP: PB14_MFP Position */
#define SYS_PB_H_MFP_PB14_MFP_Msk (0xful << SYS_PB_H_MFP_PB14_MFP_Pos) /*!< SYS PB_H_MFP: PB14_MFP Mask */
#define SYS_PB_H_MFP_PB15_MFP_Pos (28) /*!< SYS PB_H_MFP: PB15_MFP Position */
#define SYS_PB_H_MFP_PB15_MFP_Msk (0xful << SYS_PB_H_MFP_PB15_MFP_Pos) /*!< SYS PB_H_MFP: PB15_MFP Mask */
#define SYS_PC_L_MFP_PC0_MFP_Pos (0) /*!< SYS PC_L_MFP: PC0_MFP Position */
#define SYS_PC_L_MFP_PC0_MFP_Msk (0xful << SYS_PC_L_MFP_PC0_MFP_Pos) /*!< SYS PC_L_MFP: PC0_MFP Mask */
#define SYS_PC_L_MFP_PC1_MFP_Pos (4) /*!< SYS PC_L_MFP: PC1_MFP Position */
#define SYS_PC_L_MFP_PC1_MFP_Msk (0xful << SYS_PC_L_MFP_PC1_MFP_Pos) /*!< SYS PC_L_MFP: PC1_MFP Mask */
#define SYS_PC_L_MFP_PC2_MFP_Pos (8) /*!< SYS PC_L_MFP: PC2_MFP Position */
#define SYS_PC_L_MFP_PC2_MFP_Msk (0xful << SYS_PC_L_MFP_PC2_MFP_Pos) /*!< SYS PC_L_MFP: PC2_MFP Mask */
#define SYS_PC_L_MFP_PC3_MFP_Pos (12) /*!< SYS PC_L_MFP: PC3_MFP Position */
#define SYS_PC_L_MFP_PC3_MFP_Msk (0xful << SYS_PC_L_MFP_PC3_MFP_Pos) /*!< SYS PC_L_MFP: PC3_MFP Mask */
#define SYS_PC_L_MFP_PC4_MFP_Pos (16) /*!< SYS PC_L_MFP: PC4_MFP Position */
#define SYS_PC_L_MFP_PC4_MFP_Msk (0xful << SYS_PC_L_MFP_PC4_MFP_Pos) /*!< SYS PC_L_MFP: PC4_MFP Mask */
#define SYS_PC_L_MFP_PC5_MFP_Pos (20) /*!< SYS PC_L_MFP: PC5_MFP Position */
#define SYS_PC_L_MFP_PC5_MFP_Msk (0xful << SYS_PC_L_MFP_PC5_MFP_Pos) /*!< SYS PC_L_MFP: PC5_MFP Mask */
#define SYS_PC_L_MFP_PC6_MFP_Pos (24) /*!< SYS PC_L_MFP: PC6_MFP Position */
#define SYS_PC_L_MFP_PC6_MFP_Msk (0xful << SYS_PC_L_MFP_PC6_MFP_Pos) /*!< SYS PC_L_MFP: PC6_MFP Mask */
#define SYS_PC_L_MFP_PC7_MFP_Pos (28) /*!< SYS PC_L_MFP: PC7_MFP Position */
#define SYS_PC_L_MFP_PC7_MFP_Msk (0xful << SYS_PC_L_MFP_PC7_MFP_Pos) /*!< SYS PC_L_MFP: PC7_MFP Mask */
#define SYS_PC_H_MFP_PC8_MFP_Pos (0) /*!< SYS PC_H_MFP: PC8_MFP Position */
#define SYS_PC_H_MFP_PC8_MFP_Msk (0xful << SYS_PC_H_MFP_PC8_MFP_Pos) /*!< SYS PC_H_MFP: PC8_MFP Mask */
#define SYS_PC_H_MFP_PC9_MFP_Pos (4) /*!< SYS PC_H_MFP: PC9_MFP Position */
#define SYS_PC_H_MFP_PC9_MFP_Msk (0xful << SYS_PC_H_MFP_PC9_MFP_Pos) /*!< SYS PC_H_MFP: PC9_MFP Mask */
#define SYS_PC_H_MFP_PC10_MFP_Pos (8) /*!< SYS PC_H_MFP: PC10_MFP Position */
#define SYS_PC_H_MFP_PC10_MFP_Msk (0xful << SYS_PC_H_MFP_PC10_MFP_Pos) /*!< SYS PC_H_MFP: PC10_MFP Mask */
#define SYS_PC_H_MFP_PC11_MFP_Pos (12) /*!< SYS PC_H_MFP: PC11_MFP Position */
#define SYS_PC_H_MFP_PC11_MFP_Msk (0xful << SYS_PC_H_MFP_PC11_MFP_Pos) /*!< SYS PC_H_MFP: PC11_MFP Mask */
#define SYS_PC_H_MFP_PC12_MFP_Pos (16) /*!< SYS PC_H_MFP: PC12_MFP Position */
#define SYS_PC_H_MFP_PC12_MFP_Msk (0xful << SYS_PC_H_MFP_PC12_MFP_Pos) /*!< SYS PC_H_MFP: PC12_MFP Mask */
#define SYS_PC_H_MFP_PC13_MFP_Pos (20) /*!< SYS PC_H_MFP: PC13_MFP Position */
#define SYS_PC_H_MFP_PC13_MFP_Msk (0xful << SYS_PC_H_MFP_PC13_MFP_Pos) /*!< SYS PC_H_MFP: PC13_MFP Mask */
#define SYS_PC_H_MFP_PC14_MFP_Pos (24) /*!< SYS PC_H_MFP: PC14_MFP Position */
#define SYS_PC_H_MFP_PC14_MFP_Msk (0xful << SYS_PC_H_MFP_PC14_MFP_Pos) /*!< SYS PC_H_MFP: PC14_MFP Mask */
#define SYS_PC_H_MFP_PC15_MFP_Pos (28) /*!< SYS PC_H_MFP: PC15_MFP Position */
#define SYS_PC_H_MFP_PC15_MFP_Msk (0xful << SYS_PC_H_MFP_PC15_MFP_Pos) /*!< SYS PC_H_MFP: PC15_MFP Mask */
#define SYS_PD_L_MFP_PD0_MFP_Pos (0) /*!< SYS PD_L_MFP: PD0_MFP Position */
#define SYS_PD_L_MFP_PD0_MFP_Msk (0xful << SYS_PD_L_MFP_PD0_MFP_Pos) /*!< SYS PD_L_MFP: PD0_MFP Mask */
#define SYS_PD_L_MFP_PD1_MFP_Pos (4) /*!< SYS PD_L_MFP: PD1_MFP Position */
#define SYS_PD_L_MFP_PD1_MFP_Msk (0xful << SYS_PD_L_MFP_PD1_MFP_Pos) /*!< SYS PD_L_MFP: PD1_MFP Mask */
#define SYS_PD_L_MFP_PD2_MFP_Pos (8) /*!< SYS PD_L_MFP: PD2_MFP Position */
#define SYS_PD_L_MFP_PD2_MFP_Msk (0xful << SYS_PD_L_MFP_PD2_MFP_Pos) /*!< SYS PD_L_MFP: PD2_MFP Mask */
#define SYS_PD_L_MFP_PD3_MFP_Pos (12) /*!< SYS PD_L_MFP: PD3_MFP Position */
#define SYS_PD_L_MFP_PD3_MFP_Msk (0xful << SYS_PD_L_MFP_PD3_MFP_Pos) /*!< SYS PD_L_MFP: PD3_MFP Mask */
#define SYS_PD_L_MFP_PD4_MFP_Pos (16) /*!< SYS PD_L_MFP: PD4_MFP Position */
#define SYS_PD_L_MFP_PD4_MFP_Msk (0xful << SYS_PD_L_MFP_PD4_MFP_Pos) /*!< SYS PD_L_MFP: PD4_MFP Mask */
#define SYS_PD_L_MFP_PD5_MFP_Pos (20) /*!< SYS PD_L_MFP: PD5_MFP Position */
#define SYS_PD_L_MFP_PD5_MFP_Msk (0xful << SYS_PD_L_MFP_PD5_MFP_Pos) /*!< SYS PD_L_MFP: PD5_MFP Mask */
#define SYS_PD_L_MFP_PD6_MFP_Pos (24) /*!< SYS PD_L_MFP: PD6_MFP Position */
#define SYS_PD_L_MFP_PD6_MFP_Msk (0xful << SYS_PD_L_MFP_PD6_MFP_Pos) /*!< SYS PD_L_MFP: PD6_MFP Mask */
#define SYS_PD_L_MFP_PD7_MFP_Pos (28) /*!< SYS PD_L_MFP: PD7_MFP Position */
#define SYS_PD_L_MFP_PD7_MFP_Msk (0xful << SYS_PD_L_MFP_PD7_MFP_Pos) /*!< SYS PD_L_MFP: PD7_MFP Mask */
#define SYS_PD_H_MFP_PD8_MFP_Pos (0) /*!< SYS PD_H_MFP: PD8_MFP Position */
#define SYS_PD_H_MFP_PD8_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD8_MFP_Pos) /*!< SYS PD_H_MFP: PD8_MFP Mask */
#define SYS_PD_H_MFP_PD9_MFP_Pos (4) /*!< SYS PD_H_MFP: PD9_MFP Position */
#define SYS_PD_H_MFP_PD9_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD9_MFP_Pos) /*!< SYS PD_H_MFP: PD9_MFP Mask */
#define SYS_PD_H_MFP_PD10_MFP_Pos (8) /*!< SYS PD_H_MFP: PD10_MFP Position */
#define SYS_PD_H_MFP_PD10_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD10_MFP_Pos) /*!< SYS PD_H_MFP: PD10_MFP Mask */
#define SYS_PD_H_MFP_PD11_MFP_Pos (12) /*!< SYS PD_H_MFP: PD11_MFP Position */
#define SYS_PD_H_MFP_PD11_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD11_MFP_Pos) /*!< SYS PD_H_MFP: PD11_MFP Mask */
#define SYS_PD_H_MFP_PD12_MFP_Pos (16) /*!< SYS PD_H_MFP: PD12_MFP Position */
#define SYS_PD_H_MFP_PD12_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD12_MFP_Pos) /*!< SYS PD_H_MFP: PD12_MFP Mask */
#define SYS_PD_H_MFP_PD13_MFP_Pos (20) /*!< SYS PD_H_MFP: PD13_MFP Position */
#define SYS_PD_H_MFP_PD13_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD13_MFP_Pos) /*!< SYS PD_H_MFP: PD13_MFP Mask */
#define SYS_PD_H_MFP_PD14_MFP_Pos (24) /*!< SYS PD_H_MFP: PD14_MFP Position */
#define SYS_PD_H_MFP_PD14_MFP_Msk (0xful << SYS_PD_H_MFP_PD14_MFP_Pos) /*!< SYS PD_H_MFP: PD14_MFP Mask */
#define SYS_PD_H_MFP_PD15_MFP_Pos (28) /*!< SYS PD_H_MFP: PD15_MFP Position */
#define SYS_PD_H_MFP_PD15_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD15_MFP_Pos) /*!< SYS PD_H_MFP: PD15_MFP Mask */
#define SYS_PE_L_MFP_PE0_MFP_Pos (0) /*!< SYS PE_L_MFP: PE0_MFP Position */
#define SYS_PE_L_MFP_PE0_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE0_MFP_Pos) /*!< SYS PE_L_MFP: PE0_MFP Mask */
#define SYS_PE_L_MFP_PE1_MFP_Pos (4) /*!< SYS PE_L_MFP: PE1_MFP Position */
#define SYS_PE_L_MFP_PE1_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE1_MFP_Pos) /*!< SYS PE_L_MFP: PE1_MFP Mask */
#define SYS_PE_L_MFP_PE2_MFP_Pos (8) /*!< SYS PE_L_MFP: PE2_MFP Position */
#define SYS_PE_L_MFP_PE2_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE2_MFP_Pos) /*!< SYS PE_L_MFP: PE2_MFP Mask */
#define SYS_PE_L_MFP_PE3_MFP_Pos (15) /*!< SYS PE_L_MFP: PE3_MFP Position */
#define SYS_PE_L_MFP_PE3_MFP_Msk (0x1ul << SYS_PE_L_MFP_PE3_MFP_Pos) /*!< SYS PE_L_MFP: PE3_MFP Mask */
#define SYS_PE_L_MFP_PE4_MFP_Pos (16) /*!< SYS PE_L_MFP: PE4_MFP Position */
#define SYS_PE_L_MFP_PE4_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE4_MFP_Pos) /*!< SYS PE_L_MFP: PE4_MFP Mask */
#define SYS_PE_L_MFP_PE5_MFP_Pos (20) /*!< SYS PE_L_MFP: PE5_MFP Position */
#define SYS_PE_L_MFP_PE5_MFP_Msk (0xful << SYS_PE_L_MFP_PE5_MFP_Pos) /*!< SYS PE_L_MFP: PE5_MFP Mask */
#define SYS_PE_L_MFP_PE6_MFP_Pos (24) /*!< SYS PE_L_MFP: PE6_MFP Position */
#define SYS_PE_L_MFP_PE6_MFP_Msk (0xful << SYS_PE_L_MFP_PE6_MFP_Pos) /*!< SYS PE_L_MFP: PE6_MFP Mask */
#define SYS_PE_L_MFP_PE7_MFP_Pos (28) /*!< SYS PE_L_MFP: PE7_MFP Position */
#define SYS_PE_L_MFP_PE7_MFP_Msk (0xful << SYS_PE_L_MFP_PE7_MFP_Pos) /*!< SYS PE_L_MFP: PE7_MFP Mask */
#define SYS_PE_H_MFP_PE8_MFP_Pos (0) /*!< SYS PE_H_MFP: PE8_MFP Position */
#define SYS_PE_H_MFP_PE8_MFP_Msk (0xful << SYS_PE_H_MFP_PE8_MFP_Pos) /*!< SYS PE_H_MFP: PE8_MFP Mask */
#define SYS_PE_H_MFP_PE9_MFP_Pos (4) /*!< SYS PE_H_MFP: PE9_MFP Position */
#define SYS_PE_H_MFP_PE9_MFP_Msk (0xful << SYS_PE_H_MFP_PE9_MFP_Pos) /*!< SYS PE_H_MFP: PE9_MFP Mask */
#define SYS_PF_L_MFP_PF0_MFP_Pos (0) /*!< SYS PF_L_MFP: PF0_MFP Position */
#define SYS_PF_L_MFP_PF0_MFP_Msk (0xful << SYS_PF_L_MFP_PF0_MFP_Pos) /*!< SYS PF_L_MFP: PF0_MFP Mask */
#define SYS_PF_L_MFP_PF1_MFP_Pos (4) /*!< SYS PF_L_MFP: PF1_MFP Position */
#define SYS_PF_L_MFP_PF1_MFP_Msk (0xful << SYS_PF_L_MFP_PF1_MFP_Pos) /*!< SYS PF_L_MFP: PF1_MFP Mask */
#define SYS_PF_L_MFP_PF2_MFP_Pos (8) /*!< SYS PF_L_MFP: PF2_MFP Position */
#define SYS_PF_L_MFP_PF2_MFP_Msk (0xful << SYS_PF_L_MFP_PF2_MFP_Pos) /*!< SYS PF_L_MFP: PF2_MFP Mask */
#define SYS_PF_L_MFP_PF3_MFP_Pos (12) /*!< SYS PF_L_MFP: PF3_MFP Position */
#define SYS_PF_L_MFP_PF3_MFP_Msk (0xful << SYS_PF_L_MFP_PF3_MFP_Pos) /*!< SYS PF_L_MFP: PF3_MFP Mask */
#define SYS_PF_L_MFP_PF4_MFP_Pos (16) /*!< SYS PF_L_MFP: PF4_MFP Position */
#define SYS_PF_L_MFP_PF4_MFP_Msk (0xful << SYS_PF_L_MFP_PF4_MFP_Pos) /*!< SYS PF_L_MFP: PF4_MFP Mask */
#define SYS_PF_L_MFP_PF5_MFP_Pos (20) /*!< SYS PF_L_MFP: PF5_MFP Position */
#define SYS_PF_L_MFP_PF5_MFP_Msk (0xful << SYS_PF_L_MFP_PF5_MFP_Pos) /*!< SYS PF_L_MFP: PF5_MFP Mask */
#define SYS_PORCTL_POR_DIS_CODE_Pos (0) /*!< SYS PORCTL: POR_DIS_CODE Position */
#define SYS_PORCTL_POR_DIS_CODE_Msk (0xfffful << SYS_PORCTL_POR_DIS_CODE_Pos) /*!< SYS PORCTL: POR_DIS_CODE Mask */
#define SYS_BODCTL_BOD17_EN_Pos (0) /*!< SYS BODCTL: BOD17_EN Position */
#define SYS_BODCTL_BOD17_EN_Msk (0x1ul << SYS_BODCTL_BOD17_EN_Pos) /*!< SYS BODCTL: BOD17_EN Mask */
#define SYS_BODCTL_BOD20_EN_Pos (1) /*!< SYS BODCTL: BOD20_EN Position */
#define SYS_BODCTL_BOD20_EN_Msk (0x1ul << SYS_BODCTL_BOD20_EN_Pos) /*!< SYS BODCTL: BOD20_EN Mask */
#define SYS_BODCTL_BOD25_EN_Pos (2) /*!< SYS BODCTL: BOD25_EN Position */
#define SYS_BODCTL_BOD25_EN_Msk (0x1ul << SYS_BODCTL_BOD25_EN_Pos) /*!< SYS BODCTL: BOD25_EN Mask */
#define SYS_BODCTL_BOD17_RST_EN_Pos (4) /*!< SYS BODCTL: BOD17_RST_EN Position */
#define SYS_BODCTL_BOD17_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD17_RST_EN_Pos) /*!< SYS BODCTL: BOD17_RST_EN Mask */
#define SYS_BODCTL_BOD20_RST_EN_Pos (5) /*!< SYS BODCTL: BOD20_RST_EN Position */
#define SYS_BODCTL_BOD20_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD20_RST_EN_Pos) /*!< SYS BODCTL: BOD20_RST_EN Mask */
#define SYS_BODCTL_BOD25_RST_EN_Pos (6) /*!< SYS BODCTL: BOD25_RST_EN Position */
#define SYS_BODCTL_BOD25_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD25_RST_EN_Pos) /*!< SYS BODCTL: BOD25_RST_EN Mask */
#define SYS_BODCTL_BOD17_INT_EN_Pos (8) /*!< SYS BODCTL: BOD17_INT_EN Position */
#define SYS_BODCTL_BOD17_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD17_INT_EN_Pos) /*!< SYS BODCTL: BOD17_INT_EN Mask */
#define SYS_BODCTL_BOD20_INT_EN_Pos (9) /*!< SYS BODCTL: BOD20_INT_EN Position */
#define SYS_BODCTL_BOD20_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD20_INT_EN_Pos) /*!< SYS BODCTL: BOD20_INT_EN Mask */
#define SYS_BODCTL_BOD25_INT_EN_Pos (10) /*!< SYS BODCTL: BOD25_INT_EN Position */
#define SYS_BODCTL_BOD25_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD25_INT_EN_Pos) /*!< SYS BODCTL: BOD25_INT_EN Mask */
#define SYS_BODCTL_BOD17_TRIM_Pos (12) /*!< SYS BODCTL: BOD17_TRIM Position */
#define SYS_BODCTL_BOD17_TRIM_Msk (0xful << SYS_BODCTL_BOD17_TRIM_Pos) /*!< SYS BODCTL: BOD17_TRIM Mask */
#define SYS_BODCTL_BOD20_TRIM_Pos (16) /*!< SYS BODCTL: BOD20_TRIM Position */
#define SYS_BODCTL_BOD20_TRIM_Msk (0xful << SYS_BODCTL_BOD20_TRIM_Pos) /*!< SYS BODCTL: BOD20_TRIM Mask */
#define SYS_BODCTL_BOD25_TRIM_Pos (20) /*!< SYS BODCTL: BOD25_TRIM Position */
#define SYS_BODCTL_BOD25_TRIM_Msk (0xful << SYS_BODCTL_BOD25_TRIM_Pos) /*!< SYS BODCTL: BOD25_TRIM Mask */
#define SYS_BODSTS_BOD_INT_Pos (0) /*!< SYS BODSTS: BOD_INT Position */
#define SYS_BODSTS_BOD_INT_Msk (0x1ul << SYS_BODSTS_BOD_INT_Pos) /*!< SYS BODSTS: BOD_INT Mask */
#define SYS_BODSTS_BOD17_drop_Pos (1) /*!< SYS BODSTS: BOD17_drop Position */
#define SYS_BODSTS_BOD17_drop_Msk (0x1ul << SYS_BODSTS_BOD17_drop_Pos) /*!< SYS BODSTS: BOD17_drop Mask */
#define SYS_BODSTS_BOD20_drop_Pos (2) /*!< SYS BODSTS: BOD20_drop Position */
#define SYS_BODSTS_BOD20_drop_Msk (0x1ul << SYS_BODSTS_BOD20_drop_Pos) /*!< SYS BODSTS: BOD20_drop Mask */
#define SYS_BODSTS_BOD25_drop_Pos (3) /*!< SYS BODSTS: BOD25_drop Position */
#define SYS_BODSTS_BOD25_drop_Msk (0x1ul << SYS_BODSTS_BOD25_drop_Pos) /*!< SYS BODSTS: BOD25_drop Mask */
#define SYS_BODSTS_BOD17_rise_Pos (4) /*!< SYS BODSTS: BOD17_rise Position */
#define SYS_BODSTS_BOD17_rise_Msk (0x1ul << SYS_BODSTS_BOD17_rise_Pos) /*!< SYS BODSTS: BOD17_rise Mask */
#define SYS_BODSTS_BOD20_rise_Pos (5) /*!< SYS BODSTS: BOD20_rise Position */
#define SYS_BODSTS_BOD20_rise_Msk (0x1ul << SYS_BODSTS_BOD20_rise_Pos) /*!< SYS BODSTS: BOD20_rise Mask */
#define SYS_BODSTS_BOD25_rise_Pos (6) /*!< SYS BODSTS: BOD25_rise Position */
#define SYS_BODSTS_BOD25_rise_Msk (0x1ul << SYS_BODSTS_BOD25_rise_Pos) /*!< SYS BODSTS: BOD25_rise Mask */
#define SYS_BODSTS_BOD17_Pos (8) /*!< SYS BODSTS: BOD17 Position */
#define SYS_BODSTS_BOD17_Msk (0x1ul << SYS_BODSTS_BOD17_Pos) /*!< SYS BODSTS: BOD17 Mask */
#define SYS_BODSTS_BOD20_Pos (9) /*!< SYS BODSTS: BOD20 Position */
#define SYS_BODSTS_BOD20_Msk (0x1ul << SYS_BODSTS_BOD20_Pos) /*!< SYS BODSTS: BOD20 Mask */
#define SYS_BODSTS_BOD25_Pos (10) /*!< SYS BODSTS: BOD25 Position */
#define SYS_BODSTS_BOD25_Msk (0x1ul << SYS_BODSTS_BOD25_Pos) /*!< SYS BODSTS: BOD25 Mask */
#define SYS_VREFCTL_BGP_EN_Pos (0) /*!< SYS VREFCTL: BGP_EN Position */
#define SYS_VREFCTL_BGP_EN_Msk (0x1ul << SYS_VREFCTL_BGP_EN_Pos) /*!< SYS VREFCTL: BGP_EN Mask */
#define SYS_VREFCTL_REG_EN_Pos (1) /*!< SYS VREFCTL: REG_EN Position */
#define SYS_VREFCTL_REG_EN_Msk (0x1ul << SYS_VREFCTL_REG_EN_Pos) /*!< SYS VREFCTL: REG_EN Mask */
#define SYS_VREFCTL_SEL25_Pos (2) /*!< SYS VREFCTL: SEL25 Position */
#define SYS_VREFCTL_SEL25_Msk (0x3ul << SYS_VREFCTL_SEL25_Pos) /*!< SYS VREFCTL: SEL25 Mask */
#define SYS_VREFCTL_EXT_MODE_Pos (4) /*!< SYS VREFCTL: EXT_MODE Position */
#define SYS_VREFCTL_EXT_MODE_Msk (0x1ul << SYS_VREFCTL_EXT_MODE_Pos) /*!< SYS VREFCTL: EXT_MODE Mask */
#define SYS_VREFCTL_VREF_TRIM_Pos (8) /*!< SYS VREFCTL: VREF_TRIM Position */
#define SYS_VREFCTL_VREF_TRIM_Msk (0xful << SYS_VREFCTL_VREF_TRIM_Pos) /*!< SYS VREFCTL: VREF_TRIM Mask */
#define SYS_CTL_LDO_PD_Pos (0) /*!< SYS CTL: LDO_PD Position */
#define SYS_CTL_LDO_PD_Msk (0x1ul << SYS_CTL_LDO_PD_Pos) /*!< SYS CTL: LDO_PD Mask */
#define SYS_CTL_LDO_LEVEL_Pos (2) /*!< SYS CTL: LDO_LEVEL Position */
#define SYS_CTL_LDO_LEVEL_Msk (0x3ul << SYS_CTL_LDO_LEVEL_Pos) /*!< SYS CTL: LDO_LEVEL Mask */
#define SYS_IRCTRIMCTL_TRIM_SEL_Pos (0) /*!< SYS IRCTRIMCTL: TRIM_SEL Position */
#define SYS_IRCTRIMCTL_TRIM_SEL_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_SEL_Pos) /*!< SYS IRCTRIMCTL: TRIM_SEL Mask */
#define SYS_IRCTRIMCTL_TRIM_LOOP_Pos (4) /*!< SYS IRCTRIMCTL: TRIM_LOOP Position */
#define SYS_IRCTRIMCTL_TRIM_LOOP_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_LOOP_Pos) /*!< SYS IRCTRIMCTL: TRIM_LOOP Mask */
#define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos (6) /*!< SYS IRCTRIMCTL: TRIM_RETRY_CNT Position*/
#define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) /*!< SYS IRCTRIMCTL: TRIM_RETRY_CNT Mask */
#define SYS_IRCTRIMCTL_ERR_STOP_Pos (8) /*!< SYS IRCTRIMCTL: ERR_STOP Position */
#define SYS_IRCTRIMCTL_ERR_STOP_Msk (0x1ul << SYS_IRCTRIMCTL_ERR_STOP_Pos) /*!< SYS IRCTRIMCTL: ERR_STOP Mask */
#define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos (1) /*!< SYS IRCTRIMIEN: TRIM_FAIL_IEN Position */
#define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos) /*!< SYS IRCTRIMIEN: TRIM_FAIL_IEN Mask */
#define SYS_IRCTRIMIEN_32K_ERR_IEN_Pos (2) /*!< SYS IRCTRIMIEN: 32K_ERR_IEN Position */
#define SYS_IRCTRIMIEN_32K_ERR_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_32K_ERR_IEN_Pos) /*!< SYS IRCTRIMIEN: 32K_ERR_IEN Mask */
#define SYS_IRCTRIMINT_FREQ_LOCK_Pos (0) /*!< SYS IRCTRIMINT: FREQ_LOCK Position */
#define SYS_IRCTRIMINT_FREQ_LOCK_Msk (0x1ul << SYS_IRCTRIMINT_FREQ_LOCK_Pos) /*!< SYS IRCTRIMINT: FREQ_LOCK Mask */
#define SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos (1) /*!< SYS IRCTRIMINT: TRIM_FAIL_INT Position */
#define SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk (0x1ul << SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos) /*!< SYS IRCTRIMINT: TRIM_FAIL_INT Mask */
#define SYS_IRCTRIMINT_32K_ERR_INT_Pos (2) /*!< SYS IRCTRIMINT: 32K_ERR_INT Position */
#define SYS_IRCTRIMINT_32K_ERR_INT_Msk (0x1ul << SYS_IRCTRIMINT_32K_ERR_INT_Pos) /*!< SYS IRCTRIMINT: 32K_ERR_INT Mask */
#define SYS_RegLockAddr_RegUnLock_Pos (0) /*!< SYS RegLockAddr: RegUnLock Position */
#define SYS_RegLockAddr_RegUnLock_Msk (0x1ul << SYS_RegLockAddr_RegUnLock_Pos) /*!< SYS RegLockAddr: RegUnLock Mask */
/**@}*/ /* SYS_CONST */
/**@}*/ /* end of SYS register group */
/*---------------------- General Purpose Input/Output Controller -------------------------*/
/**
@addtogroup GPIO General Purpose Input/Output Controller(GPIO)
Memory Mapped Structure for GPIO Controller
@{ */
typedef struct {
/**
* PMD
* ===================================================================================================
* Offset: 0x00 GPIO Port Pin I/O Mode Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |PMD0 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[3:2] |PMD1 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[5:4] |PMD2 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[7:6] |PMD3 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[9:8] |PMD4 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[11:10] |PMD5 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[13:12] |PMD6 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[15:14] |PMD7 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[17:16] |PMD8 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[19:18] |PMD9 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[21:20] |PMD10 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[23:22] |PMD11 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[25:24] |PMD12 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[27:26] |PMD13 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[29:28] |PMD14 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
* |[31:30] |PMD15 |GPIO Port [X] Pin [N] Mode Control
* | | |Determine the I/O type of GPIO port [x] pin [n]
* | | |00 = GPIO port [x] pin [n] is in INPUT mode.
* | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
* | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
* | | |11 = Reserved.
* | | |Note: For GPIOE_PMD, PMD10 ~ PMD15 are reserved.
* | | |For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
*/
__IO uint32_t PMD;
/**
* OFFD
* ===================================================================================================
* Offset: 0x04 GPIO Port Pin OFF Digital Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:16] |OFFD |GPIO Port [X] Pin [N] Digital Input Path Disable
* | | |Determine if the digital input path of GPIO port [x] pin [n] is disabled.
* | | |0 = Digital input path of GPIO port [x] pin [n] Enabled.
* | | |1 = Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low).
* | | |Note: For GPIOF_OFFD, bits [31:22] are reserved.
*/
__IO uint32_t OFFD;
/**
* DOUT
* ===================================================================================================
* Offset: 0x08 GPIO Port Data Output Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DOUT |GPIO Port [X] Pin [N] Output Value
* | | |Each of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode
* | | |0 = GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set.
* | | |1 = GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set.
* | | |Note: For GPIOF_DOUT, bits [15:6] are reserved.
*/
__IO uint32_t DOUT;
/**
* DMASK
* ===================================================================================================
* Offset: 0x0C GPIO Port Data Output Write Mask Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DMASK |GPIO Port [X] Pin [N] Data Output Write Mask
* | | |These bits are used to protect the corresponding register of GPIOx_DOUT bit [n].
* | | |When set the DMASK[n] to "1", the corresponding DOUT[n] bit is protected.
* | | |The write signal is masked, write data to the protect bit is ignored.
* | | |0 = The corresponding GPIO_DOUT bit [n] can be updated.
* | | |1 = The corresponding GPIO_DOUT bit [n] is protected.
* | | |Note: For GPIOF_DMASK, bits [15:6] are reserved.
* | | |Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT.
* | | |If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
*/
__IO uint32_t DMASK;
/**
* PIN
* ===================================================================================================
* Offset: 0x10 GPIO Port Pin Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PIN |GPIO Port [X] Pin [N] Value
* | | |The value read from each of these bit reflects the actual status of the respective GPI/O pin
* | | |Note: For GPIOF_PIN, bits [15:6] are reserved.
*/
__I uint32_t PIN;
/**
* DBEN
* ===================================================================================================
* Offset: 0x14 GPIO Port De-bounce Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DBEN |GPIO Port [X] Pin [N] Input Signal De-Bounce Enable
* | | |DBEN[n] used to enable the de-bounce function for each corresponding bit.
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
* | | |DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt
* | | |0 = The GPIO port [x] Pin [n] input signal de-bounce function is disabled.
* | | |1 = The GPIO port [x] Pin [n] input signal de-bounce function is enabled.
* | | |The de-bounce function is valid for edge triggered interrupt.
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note: For GPIOF_DBEN, bits [15:6] are reserved.
*/
__IO uint32_t DBEN;
/**
* IMD
* ===================================================================================================
* Offset: 0x18 GPIO Port Interrupt Mode Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |IMD |GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control
* | | |IMD[n] used to control the interrupt is by level trigger or by edge trigger.
* | | |If the interrupt is by edge trigger, the trigger source is control de-bounce.
* | | |If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt.
* | | |0 = Edge trigger interrupt.
* | | |1 = Level trigger interrupt.
* | | |If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER.
* | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
* | | |The de-bounce function is valid for edge triggered interrupt.
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note: For GPIOF_IMD, bits [15:6] are reserved.
*/
__IO uint32_t IMD;
/**
* IER
* ===================================================================================================
* Offset: 0x1C GPIO Port Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FIER0 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[1] |FIER1 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[2] |FIER2 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[3] |FIER3 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[4] |FIER4 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[5] |FIER5 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[6] |FIER6 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[7] |FIER7 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[8] |FIER8 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[9] |FIER9 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[10] |FIER10 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[11] |FIER11 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[12] |FIER12 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[13] |FIER13 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[14] |FIER14 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[15] |FIER15 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
* | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the FIER[n] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
* | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
* | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
* | | |Note: For GPIOF_IER, bits [15:6] are reserved.
* |[16] |RIER0 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[17] |RIER1 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[18] |RIER2 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[19] |RIER3 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[20] |RIER4 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[21] |RIER5 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[22] |RIER6 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[23] |RIER7 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[24] |RIER8 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[25] |RIER9 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[26] |RIER10 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[27] |RIER11 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[28] |RIER12 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[29] |RIER13 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[30] |RIER14 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
* |[31] |RIER15 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
* | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
* | | |Set bit "1" also enable the pin wake-up function.
* | | |When set the RIER[x] bit "1":
* | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
* | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
* | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
* | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
* | | |Note: For GPIOF_IE, bits [31:22] are reserved.
*/
__IO uint32_t IER;
/**
* ISRC
* ===================================================================================================
* Offset: 0x20 GPIO Port Interrupt Trigger Source Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |ISRC |GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator
* | | |Read :
* | | |1 = Port x[n] generate an interrupt.
* | | |0 = No interrupt at Port x[n].
* | | |Write:
* | | |1 = Clear the correspond pending interrupt.
* | | |0 = No action.
* | | |Note: For GPIOF_ISRC, bits [15:6] are reserved.
*/
__IO uint32_t ISRC;
/**
* PUEN
* ===================================================================================================
* Offset: 0x24 GPIO Port Pull-Up Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PUEN |GPIO Port [X] Pin [N] Pull-Up Enable Register
* | | |Read :
* | | |1 = GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled.
* | | |0 = GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled.
* | | |Note: For GPIOF_PUEN, bits [15:6] are reserved.
*/
__IO uint32_t PUEN;
} GPIO_T;
typedef struct {
/**
* DBNCECON
* ===================================================================================================
* Offset: 0x180 De-bounce Cycle Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection
* | | |0000 = Sample interrupt input once per 1 clock.
* | | |0001 = Sample interrupt input once per 2 clocks.
* | | |0010 = Sample interrupt input once per 4 clocks.
* | | |0011 = Sample interrupt input once per 8 clocks.
* | | |0100 = Sample interrupt input once per 16 clocks.
* | | |0101 = Sample interrupt input once per 32 clocks.
* | | |0110 = Sample interrupt input once per 64 clocks.
* | | |0111 = Sample interrupt input once per 128 clocks.
* | | |1000 = Sample interrupt input once per 256 clocks.
* | | |1001 = Sample interrupt input once per 2*256 clocks.
* | | |1010 = Sample interrupt input once per 4*256clocks.
* | | |1011 = Sample interrupt input once per 8*256 clocks.
* | | |1100 = Sample interrupt input once per 16*256 clocks.
* | | |1101 = Sample interrupt input once per 32*256 clocks.
* | | |1110 = Sample interrupt input once per 64*256 clocks.
* | | |1111 = Sample interrupt input once per 128*256 clocks.
* |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
* | | |0 = De-bounce counter Clock Source is the HCLK.
* | | |1 = De-bounce counter Clock Source is the internal 10 kHz clock.
* |[5] |DBCLK_ON |De-Bounce Clock Enable Control
* | | |This bit controls if the de-bounce clock is enabled.
* | | |However, if GPI/O pin's interrupt is enabled, the de-bounce clock will be enabled automatically no matter what the DBCLK_ON value is.
* | | |If CPU is in sleep mode, this bit didn't take effect.
* | | |And only the GPI/O pin with interrupt enable could get de-bounce clock.
* | | |0 = De-bounce clock Disabled.
* | | |1 = De-bounce clock Enabled.
*/
__IO uint32_t DBNCECON;
} GP_DB_T;
/**
@addtogroup GPIO_CONST GPIO Bit Field Definition
Constant Definitions for GPIO Controller
@{ */
#define GP_PMD_PMD0_Pos (0) /*!< GP PMD: PMD0 Position */
#define GP_PMD_PMD0_Msk (0x3ul << GP_PMD_PMD0_Pos) /*!< GP PMD: PMD0 Mask */
#define GP_PMD_PMD1_Pos (2) /*!< GP PMD: PMD1 Position */
#define GP_PMD_PMD1_Msk (0x3ul << GP_PMD_PMD1_Pos) /*!< GP PMD: PMD1 Mask */
#define GP_PMD_PMD2_Pos (4) /*!< GP PMD: PMD2 Position */
#define GP_PMD_PMD2_Msk (0x3ul << GP_PMD_PMD2_Pos) /*!< GP PMD: PMD2 Mask */
#define GP_PMD_PMD3_Pos (6) /*!< GP PMD: PMD3 Position */
#define GP_PMD_PMD3_Msk (0x3ul << GP_PMD_PMD3_Pos) /*!< GP PMD: PMD3 Mask */
#define GP_PMD_PMD4_Pos (8) /*!< GP PMD: PMD4 Position */
#define GP_PMD_PMD4_Msk (0x3ul << GP_PMD_PMD4_Pos) /*!< GP PMD: PMD4 Mask */
#define GP_PMD_PMD5_Pos (10) /*!< GP PMD: PMD5 Position */
#define GP_PMD_PMD5_Msk (0x3ul << GP_PMD_PMD5_Pos) /*!< GP PMD: PMD5 Mask */
#define GP_PMD_PMD6_Pos (12) /*!< GP PMD: PMD6 Position */
#define GP_PMD_PMD6_Msk (0x3ul << GP_PMD_PMD6_Pos) /*!< GP PMD: PMD6 Mask */
#define GP_PMD_PMD7_Pos (14) /*!< GP PMD: PMD7 Position */
#define GP_PMD_PMD7_Msk (0x3ul << GP_PMD_PMD7_Pos) /*!< GP PMD: PMD7 Mask */
#define GP_PMD_PMD8_Pos (16) /*!< GP PMD: PMD8 Position */
#define GP_PMD_PMD8_Msk (0x3ul << GP_PMD_PMD8_Pos) /*!< GP PMD: PMD8 Mask */
#define GP_PMD_PMD9_Pos (18) /*!< GP PMD: PMD9 Position */
#define GP_PMD_PMD9_Msk (0x3ul << GP_PMD_PMD9_Pos) /*!< GP PMD: PMD9 Mask */
#define GP_PMD_PMD10_Pos (20) /*!< GP PMD: PMD10 Position */
#define GP_PMD_PMD10_Msk (0x3ul << GP_PMD_PMD10_Pos) /*!< GP PMD: PMD10 Mask */
#define GP_PMD_PMD11_Pos (22) /*!< GP PMD: PMD11 Position */
#define GP_PMD_PMD11_Msk (0x3ul << GP_PMD_PMD11_Pos) /*!< GP PMD: PMD11 Mask */
#define GP_PMD_PMD12_Pos (24) /*!< GP PMD: PMD12 Position */
#define GP_PMD_PMD12_Msk (0x3ul << GP_PMD_PMD12_Pos) /*!< GP PMD: PMD12 Mask */
#define GP_PMD_PMD13_Pos (26) /*!< GP PMD: PMD13 Position */
#define GP_PMD_PMD13_Msk (0x3ul << GP_PMD_PMD13_Pos) /*!< GP PMD: PMD13 Mask */
#define GP_PMD_PMD14_Pos (28) /*!< GP PMD: PMD14 Position */
#define GP_PMD_PMD14_Msk (0x3ul << GP_PMD_PMD14_Pos) /*!< GP PMD: PMD14 Mask */
#define GP_PMD_PMD15_Pos (30) /*!< GP PMD: PMD15 Position */
#define GP_PMD_PMD15_Msk (0x3ul << GP_PMD_PMD15_Pos) /*!< GP PMD: PMD15 Mask */
#define GP_OFFD_OFFD_Pos (16) /*!< GP OFFD: OFFD Position */
#define GP_OFFD_OFFD_Msk (0xfffful << GP_OFFD_OFFD_Pos) /*!< GP OFFD: OFFD Mask */
#define GP_DOUT_DOUT_Pos (0) /*!< GP DOUT: DOUT Position */
#define GP_DOUT_DOUT_Msk (0xfffful << GP_DOUT_DOUT_Pos) /*!< GP DOUT: DOUT Mask */
#define GP_DMASK_DMASK_Pos (0) /*!< GP DMASK: DMASK Position */
#define GP_DMASK_DMASK_Msk (0xfffful << GP_DMASK_DMASK_Pos) /*!< GP DMASK: DMASK Mask */
#define GP_PIN_PIN_Pos (0) /*!< GP PIN: PIN Position */
#define GP_PIN_PIN_Msk (0xfffful << GP_PIN_PIN_Pos) /*!< GP PIN: PIN Mask */
#define GP_DBEN_DBEN_Pos (0) /*!< GP DBEN: DBEN Position */
#define GP_DBEN_DBEN_Msk (0xfffful << GP_DBEN_DBEN_Pos) /*!< GP DBEN: DBEN Mask */
#define GP_IMD_IMD_Pos (0) /*!< GP IMD: IMD Position */
#define GP_IMD_IMD_Msk (0xfffful << GP_IMD_IMD_Pos) /*!< GP IMD: IMD Mask */
#define GP_IER_FIER0_Pos (0) /*!< GP IER: FIER0 Position */
#define GP_IER_FIER0_Msk (0x1ul << GP_IER_FIER0_Pos) /*!< GP IER: FIER0 Mask */
#define GP_IER_FIER1_Pos (1) /*!< GP IER: FIER1 Position */
#define GP_IER_FIER1_Msk (0x1ul << GP_IER_FIER1_Pos) /*!< GP IER: FIER1 Mask */
#define GP_IER_FIER2_Pos (2) /*!< GP IER: FIER2 Position */
#define GP_IER_FIER2_Msk (0x1ul << GP_IER_FIER2_Pos) /*!< GP IER: FIER2 Mask */
#define GP_IER_FIER3_Pos (3) /*!< GP IER: FIER3 Position */
#define GP_IER_FIER3_Msk (0x1ul << GP_IER_FIER3_Pos) /*!< GP IER: FIER3 Mask */
#define GP_IER_FIER4_Pos (4) /*!< GP IER: FIER4 Position */
#define GP_IER_FIER4_Msk (0x1ul << GP_IER_FIER4_Pos) /*!< GP IER: FIER4 Mask */
#define GP_IER_FIER5_Pos (5) /*!< GP IER: FIER5 Position */
#define GP_IER_FIER5_Msk (0x1ul << GP_IER_FIER5_Pos) /*!< GP IER: FIER5 Mask */
#define GP_IER_FIER6_Pos (6) /*!< GP IER: FIER6 Position */
#define GP_IER_FIER6_Msk (0x1ul << GP_IER_FIER6_Pos) /*!< GP IER: FIER6 Mask */
#define GP_IER_FIER7_Pos (7) /*!< GP IER: FIER7 Position */
#define GP_IER_FIER7_Msk (0x1ul << GP_IER_FIER7_Pos) /*!< GP IER: FIER7 Mask */
#define GP_IER_FIER8_Pos (8) /*!< GP IER: FIER8 Position */
#define GP_IER_FIER8_Msk (0x1ul << GP_IER_FIER8_Pos) /*!< GP IER: FIER8 Mask */
#define GP_IER_FIER9_Pos (9) /*!< GP IER: FIER9 Position */
#define GP_IER_FIER9_Msk (0x1ul << GP_IER_FIER9_Pos) /*!< GP IER: FIER9 Mask */
#define GP_IER_FIER10_Pos (10) /*!< GP IER: FIER10 Position */
#define GP_IER_FIER10_Msk (0x1ul << GP_IER_FIER10_Pos) /*!< GP IER: FIER10 Mask */
#define GP_IER_FIER11_Pos (11) /*!< GP IER: FIER11 Position */
#define GP_IER_FIER11_Msk (0x1ul << GP_IER_FIER11_Pos) /*!< GP IER: FIER11 Mask */
#define GP_IER_FIER12_Pos (12) /*!< GP IER: FIER12 Position */
#define GP_IER_FIER12_Msk (0x1ul << GP_IER_FIER12_Pos) /*!< GP IER: FIER12 Mask */
#define GP_IER_FIER13_Pos (13) /*!< GP IER: FIER13 Position */
#define GP_IER_FIER13_Msk (0x1ul << GP_IER_FIER13_Pos) /*!< GP IER: FIER13 Mask */
#define GP_IER_FIER14_Pos (14) /*!< GP IER: FIER14 Position */
#define GP_IER_FIER14_Msk (0x1ul << GP_IER_FIER14_Pos) /*!< GP IER: FIER14 Mask */
#define GP_IER_FIER15_Pos (15) /*!< GP IER: FIER15 Position */
#define GP_IER_FIER15_Msk (0x1ul << GP_IER_FIER15_Pos) /*!< GP IER: FIER15 Mask */
#define GP_IER_RIER0_Pos (16) /*!< GP IER: RIER0 Position */
#define GP_IER_RIER0_Msk (0x1ul << GP_IER_RIER0_Pos) /*!< GP IER: RIER0 Mask */
#define GP_IER_RIER1_Pos (17) /*!< GP IER: RIER1 Position */
#define GP_IER_RIER1_Msk (0x1ul << GP_IER_RIER1_Pos) /*!< GP IER: RIER1 Mask */
#define GP_IER_RIER2_Pos (18) /*!< GP IER: RIER2 Position */
#define GP_IER_RIER2_Msk (0x1ul << GP_IER_RIER2_Pos) /*!< GP IER: RIER2 Mask */
#define GP_IER_RIER3_Pos (19) /*!< GP IER: RIER3 Position */
#define GP_IER_RIER3_Msk (0x1ul << GP_IER_RIER3_Pos) /*!< GP IER: RIER3 Mask */
#define GP_IER_RIER4_Pos (20) /*!< GP IER: RIER4 Position */
#define GP_IER_RIER4_Msk (0x1ul << GP_IER_RIER4_Pos) /*!< GP IER: RIER4 Mask */
#define GP_IER_RIER5_Pos (21) /*!< GP IER: RIER5 Position */
#define GP_IER_RIER5_Msk (0x1ul << GP_IER_RIER5_Pos) /*!< GP IER: RIER5 Mask */
#define GP_IER_RIER6_Pos (22) /*!< GP IER: RIER6 Position */
#define GP_IER_RIER6_Msk (0x1ul << GP_IER_RIER6_Pos) /*!< GP IER: RIER6 Mask */
#define GP_IER_RIER7_Pos (23) /*!< GP IER: RIER7 Position */
#define GP_IER_RIER7_Msk (0x1ul << GP_IER_RIER7_Pos) /*!< GP IER: RIER7 Mask */
#define GP_IER_RIER8_Pos (24) /*!< GP IER: RIER8 Position */
#define GP_IER_RIER8_Msk (0x1ul << GP_IER_RIER8_Pos) /*!< GP IER: RIER8 Mask */
#define GP_IER_RIER9_Pos (25) /*!< GP IER: RIER9 Position */
#define GP_IER_RIER9_Msk (0x1ul << GP_IER_RIER9_Pos) /*!< GP IER: RIER9 Mask */
#define GP_IER_RIER10_Pos (26) /*!< GP IER: RIER10 Position */
#define GP_IER_RIER10_Msk (0x1ul << GP_IER_RIER10_Pos) /*!< GP IER: RIER10 Mask */
#define GP_IER_RIER11_Pos (27) /*!< GP IER: RIER11 Position */
#define GP_IER_RIER11_Msk (0x1ul << GP_IER_RIER11_Pos) /*!< GP IER: RIER11 Mask */
#define GP_IER_RIER12_Pos (28) /*!< GP IER: RIER12 Position */
#define GP_IER_RIER12_Msk (0x1ul << GP_IER_RIER12_Pos) /*!< GP IER: RIER12 Mask */
#define GP_IER_RIER13_Pos (29) /*!< GP IER: RIER13 Position */
#define GP_IER_RIER13_Msk (0x1ul << GP_IER_RIER13_Pos) /*!< GP IER: RIER13 Mask */
#define GP_IER_RIER14_Pos (30) /*!< GP IER: RIER14 Position */
#define GP_IER_RIER14_Msk (0x1ul << GP_IER_RIER14_Pos) /*!< GP IER: RIER14 Mask */
#define GP_IER_RIER15_Pos (31) /*!< GP IER: RIER15 Position */
#define GP_IER_RIER15_Msk (0x1ul << GP_IER_RIER15_Pos) /*!< GP IER: RIER15 Mask */
#define GP_ISRC_ISRC_Pos (0) /*!< GP ISRC: ISRC Position */
#define GP_ISRC_ISRC_Msk (0xfffful << GP_ISRC_ISRC_Pos) /*!< GP ISRC: ISRC Mask */
#define GP_PUEN_PUEN_Pos (0) /*!< GP PUEN: PUEN Position */
#define GP_PUEN_PUEN_Msk (0xfffful << GP_PUEN_PUEN_Pos) /*!< GP PUEN: PUEN Mask */
/**@}*/ /* GPIO_CONST */
/**
@addtogroup GP_DB_CONST GP_DB Bit Field Definition
Constant Definitions for GP_DB Controller
@{ */
#define GP_DBNCECON_PUEN_Pos (0) /*!< GP DBNCECON: PUEN Position */
#define GP_DBNCECON_PUEN_Msk (0xful << GP_DBNCECON_PUEN_Pos) /*!< GP DBNCECON: PUEN Mask */
#define GP_DBNCECON_DBCLKSRC_Pos (4) /*!< GP DBNCECON: DBCLKSRC Position */
#define GP_DBNCECON_DBCLKSRC_Msk (0x1ul << GP_DBNCECON_DBCLKSRC_Pos) /*!< GP DBNCECON: DBCLKSRC Mask */
#define GP_DBNCECON_DBCLK_ON_Pos (5) /*!< GP DBNCECON: DBCLK_ON Position */
#define GP_DBNCECON_DBCLK_ON_Msk (0x1ul << GP_DBNCECON_DBCLK_ON_Pos) /*!< GP DBNCECON: DBCLK_ON Mask */
/**@}*/ /* GP_DB_CONST */
/**@}*/ /* end of GP register group */
/*---------------------- Inter-IC Bus Controller -------------------------*/
/**
@addtogroup I2C Inter-IC Bus Controller(I2C)
Memory Mapped Structure for I2C Controller
@{ */
typedef struct {
/**
* CON
* ===================================================================================================
* Offset: 0x00 I2C Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IPEN |I2C Function Enable Control
* | | |0 = I2C function Disabled.
* | | |1 = I2C function Enabled.
* |[1] |ACK |Assert Acknowledge Control Bit
* | | |0 = When this bit is set to 0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse.
* | | |1 = When this bit is set to 1 prior to address or data received, an acknowledged will be returned during the acknowledge clock pulse on the SCL line when:
* | | |(a): A slave is acknowledging the address sent from master.
* | | |(b): The receiver devices are acknowledging the data sent by transmitter.
* |[2] |STOP |I2C STOP Control Bit
* | | |In Master mode, set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically.
* | | |In Slave mode, set this bit to 1 to reset the controller to the defined "not addressed" Slave mode.
* | | |This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
* | | |0 = Will be cleared by hardware automatically if a STOP condition is detected.
* | | |1 = Sends a STOP condition to bus in Master mode or reset the controller to "not addressed" in Slave mode.
* |[3] |START |I2C START Command
* | | |Setting this bit to 1 to enter Master mode, the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated.
* | | |0 = After START or repeat START is active.
* | | |1 = Sends a START or repeat START condition to bus.
* |[4] |I2C_STS |I2C Status
* | | |When a new state is present in the I2CSTATUS register, if the INTEN bit is set, the I2C interrupt is requested.
* | | |It must write one by software to this bit after the I2CINTSTS[0] is set to 1 and the I2C protocol function will go ahead until the STOP is active or the IPEN is disabled.
* | | |0 = I2C's Status disabled and the I2C protocol function will go ahead.
* | | |1 = I2C's Status active.
* |[7] |INTEN |Interrupt Enable Control
* | | |0 = I2C interrupt Disabled.
* | | |1 = I2C interrupt Enabled.
*/
__IO uint32_t CON;
/**
* INTSTS
* ===================================================================================================
* Offset: 0x04 I2C Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |INTSTS |I2C STATUS's Interrupt Status
* | | |0 = No bus event occurred.
* | | |1 = New state is presented in the I2CSTATUS. Software can write 1 to cleat this bit.
* |[1] |TIF |Time-Out Status
* | | |0 = No Time-out flag. Software can cleat this flag.
* | | |1 = Time-Out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set.
* |[7] |WAKEUP_ACK_DONE|Wakeup Address Frame Acknowledge Bit Done
* | | |0 = The ACK bit cycle of address match frame isn't done.
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
*/
__IO uint32_t INTSTS;
/**
* STATUS
* ===================================================================================================
* Offset: 0x08 I2C Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |STATUS |I2C Status Bits (Read Only)
* | | |Indicates the current status code of the bus information.
* | | |The detail information about the status is described in the sections of I2C protocol register and operation mode.
*/
__I uint32_t STATUS;
/**
* DIV
* ===================================================================================================
* Offset: 0x0C I2C clock divided Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CLK_DIV |I2C Clock Divided Bits
* | | |The I2C clock rate bits: Data Baud Rate of I2C = PCLK /( 4 x ( CLK_DIV + 1)).
* | | |Note: the minimum value of CLK_DIV is 4.
*/
__IO uint32_t DIV;
/**
* TOUT
* ===================================================================================================
* Offset: 0x10 I2C Time-out control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOUTEN |Time-Out Counter Enable/Disable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |When set this bit to enable, the 14 bits time-out counter will start counting when INTSTS (I2CINTSTS[0]) is cleared.
* | | |Setting flag STAINTSTS to high or the falling edge of I2C clock or stop signal will reset counter and re-start up counting after INTSTS is cleared.
* |[1] |DIV4 |Time-Out Counter Input Clock Divider By 4
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |When Enabled, the time-out period is extended 4 times.
*/
__IO uint32_t TOUT;
/**
* DATA
* ===================================================================================================
* Offset: 0x14 I2C DATA Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DATA |I2C Data Bits
* | | |The DATA contains a byte of serial data to be transmitted or a byte which has just been received.
*/
__IO uint32_t DATA;
/**
* SADDR0
* ===================================================================================================
* Offset: 0x18 I2C Slave address Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GCALL |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[7:1] |SADDR |I2C Salve Address Bits
* | | |The content of this register is irrelevant when the device is in Master mode.
* | | |In the Slave mode, the seven most significant bits must be loaded with the device's own address.
* | | |The device will react if either of the address is matched.
*/
__IO uint32_t SADDR0;
/**
* SADDR1
* ===================================================================================================
* Offset: 0x1C I2C Slave address Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GCALL |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[7:1] |SADDR |I2C Salve Address Bits
* | | |The content of this register is irrelevant when the device is in Master mode.
* | | |In the Slave mode, the seven most significant bits must be loaded with the device's own address.
* | | |The device will react if either of the address is matched.
*/
__IO uint32_t SADDR1;
uint32_t RESERVE0[2];
/**
* SAMASK0
* ===================================================================================================
* Offset: 0x28 I2C Slave address Mask Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:1] |SAMASK |I2C Slave Address Mask Bits
* | | |0 = Mask disable (the received corresponding register bit should be exact the same as address register).
* | | |1 = Mask enable (the received corresponding address bit is don't care).
*/
__IO uint32_t SAMASK0;
/**
* SAMASK1
* ===================================================================================================
* Offset: 0x2C I2C Slave address Mask Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:1] |SAMASK |I2C Slave Address Mask Bits
* | | |0 = Mask disable (the received corresponding register bit should be exact the same as address register).
* | | |1 = Mask enable (the received corresponding address bit is don't care).
*/
__IO uint32_t SAMASK1;
uint32_t RESERVE1[3];
/**
* CON2
* ===================================================================================================
* Offset: 0x3C I2C Control Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKUPEN |I2C Wake-Up Function Enable Control
* | | |0 = I2C wake-up function Disabled.
* | | |1 = I2C wake-up function Enabled.
* |[1] |OVER_INTEN|I2C OVER RUN Interrupt Control Bit
* | | |0 = Overrun event interrupt Disabled.
* | | |1 = Send a interrupt to system when the TWOFF bit is enabled and there is over run event in received fifo.
* |[2] |UNDER_INTEN|I2C UNDER RUN Interrupt Control Bit
* | | |0 = Under run event interrupt Disabled.
* | | |1 = Send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted fifo.
* |[4] |TWOFF_EN |TWO LEVEL FIFO Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[5] |NOSTRETCH |NO STRETCH The I2C BUS
* | | |0 = The I2C SCL bus is stretched by hardware if the INTSTS (I2CINTSTS[0]) is not cleared in master mode.
* | | |1 = The I2C SCL bus is not stretched by hardware if the INTSTS is not cleared in master mode.
*/
__IO uint32_t CON2;
/**
* STATUS2
* ===================================================================================================
* Offset: 0x40 I2C Status Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKUPIF |Wake-Up Interrupt Flag
* | | |0 = Wake-up flag inactive.
* | | |1 = Wake-up flag active.
* | | |Software can write 1 to clear this flag
* |[1] |OVERUN |I2C OVER RUN Status Bit
* | | |0 = The received FIFO is not over run when the TWOFF_EN = 1.
* | | |1 = The received FIFO is over run when the TWOFF_EN = 1.
* |[2] |UNDERUN |I2C UNDER RUN Status Bit
* | | |0 = The transmitted FIFO is not under run when the TWOFF_EN = 1.
* | | |1 = The transmitted FIFO is under run when the TWOFF_EN = 1.
* |[3] |WR_STATUS |I2C Read/Write Status Bit In Address Wakeup Frame
* | | |0 = Write command be record on the address match wakeup frame.
* | | |1 = Read command be record on the address match wakeup frame.
* |[4] |FULL |I2C TWO LEVEL FIFO FULL
* | | |0 = TX FIFO no full when the TWOFF_EN = 1.
* | | |1 = TX FIFO full when the TWOFF_EN = 1.
* |[5] |EMPTY |I2C TWO LEVEL FIFO EMPTY
* | | |0 = RX FIFO no empty when the TWOFF_EN = 1.
* | | |1 = RX FIFO empty when the TWOFF_EN = 1.
* |[6] |BUS_FREE |Bus Free Status
* | | |The bus status in the controller.
* | | |0 = I2C's "Start" condition is detected on the bus.
* | | |1 = Bus free and it is released by "STOP" condition or the controller is disabled.
*/
__IO uint32_t STATUS2;
} I2C_T;
/**
@addtogroup I2C_CONST I2C Bit Field Definition
Constant Definitions for I2C Controller
@{ */
#define I2C_CON_IPEN_Pos (0) /*!< I2C CON: IPEN Position */
#define I2C_CON_IPEN_Msk (0x1ul << I2C_CON_IPEN_Pos) /*!< I2C CON: IPEN Mask */
#define I2C_CON_ACK_Pos (1) /*!< I2C CON: ACK Position */
#define I2C_CON_ACK_Msk (0x1ul << I2C_CON_ACK_Pos) /*!< I2C CON: ACK Mask */
#define I2C_CON_STOP_Pos (2) /*!< I2C CON: STOP Position */
#define I2C_CON_STOP_Msk (0x1ul << I2C_CON_STOP_Pos) /*!< I2C CON: STOP Mask */
#define I2C_CON_START_Pos (3) /*!< I2C CON: START Position */
#define I2C_CON_START_Msk (0x1ul << I2C_CON_START_Pos) /*!< I2C CON: START Mask */
#define I2C_CON_I2C_STS_Pos (4) /*!< I2C CON: I2C_STS Position */
#define I2C_CON_I2C_STS_Msk (0x1ul << I2C_CON_I2C_STS_Pos) /*!< I2C CON: I2C_STS Mask */
#define I2C_CON_INTEN_Pos (7) /*!< I2C CON: INTEN Position */
#define I2C_CON_INTEN_Msk (0x1ul << I2C_CON_INTEN_Pos) /*!< I2C CON: INTEN Mask */
#define I2C_INTSTS_INTSTS_Pos (0) /*!< I2C INTSTS: INTSTS Position */
#define I2C_INTSTS_INTSTS_Msk (0x1ul << I2C_INTSTS_INTSTS_Pos) /*!< I2C INTSTS: INTSTS Mask */
#define I2C_INTSTS_TIF_Pos (1) /*!< I2C INTSTS: TIF Position */
#define I2C_INTSTS_TIF_Msk (0x1ul << I2C_INTSTS_TIF_Pos) /*!< I2C INTSTS: TIF Mask */
#define I2C_INTSTS_WAKEUP_ACK_DONE_Pos (7) /*!< I2C INTSTS: WAKEUP_ACK_DONE Position*/
#define I2C_INTSTS_WAKEUP_ACK_DONE_Msk (0x1ul << I2C_INTSTS_WAKEUP_ACK_DONE_Pos) /*!< I2C INTSTS: WAKEUP_ACK_DONE Mask */
#define I2C_STATUS_STATUS_Pos (0) /*!< I2C STATUS: STATUS Position */
#define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) /*!< I2C STATUS: STATUS Mask */
#define I2C_DIV_CLK_DIV_Pos (0) /*!< I2C DIV: CLK_DIV Position */
#define I2C_DIV_CLK_DIV_Msk (0xfful << I2C_DIV_CLK_DIV_Pos) /*!< I2C DIV: CLK_DIV Mask */
#define I2C_TOUT_TOUTEN_Pos (0) /*!< I2C TOUT: TOUTEN Position */
#define I2C_TOUT_TOUTEN_Msk (0x1ul << I2C_TOUT_TOUTEN_Pos) /*!< I2C TOUT: TOUTEN Mask */
#define I2C_TOUT_DIV4_Pos (1) /*!< I2C TOUT: DIV4 Position */
#define I2C_TOUT_DIV4_Msk (0x1ul << I2C_TOUT_DIV4_Pos) /*!< I2C TOUT: DIV4 Mask */
#define I2C_DATA_DATA_Pos (0) /*!< I2C DATA: DATA Position */
#define I2C_DATA_DATA_Msk (0xfful << I2C_DATA_DATA_Pos) /*!< I2C DATA: DATA Mask */
#define I2C_SADDR0_GCALL_Pos (0) /*!< I2C SADDR0: GCALL Position */
#define I2C_SADDR0_GCALL_Msk (0x1ul << I2C_SADDR0_GCALL_Pos) /*!< I2C SADDR0: GCALL Mask */
#define I2C_SADDR0_SADDR_Pos (1) /*!< I2C SADDR0: SADDR Position */
#define I2C_SADDR0_SADDR_Msk (0x7ful << I2C_SADDR0_SADDR_Pos) /*!< I2C SADDR0: SADDR Mask */
#define I2C_SADDR1_GCALL_Pos (0) /*!< I2C SADDR1: GCALL Position */
#define I2C_SADDR1_GCALL_Msk (0x1ul << I2C_SADDR1_GCALL_Pos) /*!< I2C SADDR1: GCALL Mask */
#define I2C_SADDR1_SADDR_Pos (1) /*!< I2C SADDR1: SADDR Position */
#define I2C_SADDR1_SADDR_Msk (0x7ful << I2C_SADDR1_SADDR_Pos) /*!< I2C SADDR1: SADDR Mask */
#define I2C_SAMASK0_SAMASK_Pos (1) /*!< I2C SAMASK0: SAMASK Position */
#define I2C_SAMASK0_SAMASK_Msk (0x7ful << I2C_SAMASK0_SAMASK_Pos) /*!< I2C SAMASK0: SAMASK Mask */
#define I2C_SAMASK1_SAMASK_Pos (1) /*!< I2C SAMASK1: SAMASK Position */
#define I2C_SAMASK1_SAMASK_Msk (0x7ful << I2C_SAMASK1_SAMASK_Pos) /*!< I2C SAMASK1: SAMASK Mask */
#define I2C_CON2_WKUPEN_Pos (0) /*!< I2C CON2: WKUPEN Position */
#define I2C_CON2_WKUPEN_Msk (0x1ul << I2C_CON2_WKUPEN_Pos) /*!< I2C CON2: WKUPEN Mask */
#define I2C_CON2_OVER_INTEN_Pos (1) /*!< I2C CON2: OVER_INTEN Position */
#define I2C_CON2_OVER_INTEN_Msk (0x1ul << I2C_CON2_OVER_INTEN_Pos) /*!< I2C CON2: OVER_INTEN Mask */
#define I2C_CON2_UNDER_INTEN_Pos (2) /*!< I2C CON2: UNDER_INTEN Position */
#define I2C_CON2_UNDER_INTEN_Msk (0x1ul << I2C_CON2_UNDER_INTEN_Pos) /*!< I2C CON2: UNDER_INTEN Mask */
#define I2C_CON2_TWOFF_EN_Pos (4) /*!< I2C CON2: TWOFF_EN Position */
#define I2C_CON2_TWOFF_EN_Msk (0x1ul << I2C_CON2_TWOFF_EN_Pos) /*!< I2C CON2: TWOFF_EN Mask */
#define I2C_CON2_NOSTRETCH_Pos (5) /*!< I2C CON2: NOSTRETCH Position */
#define I2C_CON2_NOSTRETCH_Msk (0x1ul << I2C_CON2_NOSTRETCH_Pos) /*!< I2C CON2: NOSTRETCH Mask */
#define I2C_STATUS2_WKUPIF_Pos (0) /*!< I2C STATUS2: WKUPIF Position */
#define I2C_STATUS2_WKUPIF_Msk (0x1ul << I2C_STATUS2_WKUPIF_Pos) /*!< I2C STATUS2: WKUPIF Mask */
#define I2C_STATUS2_OVERUN_Pos (1) /*!< I2C STATUS2: OVERUN Position */
#define I2C_STATUS2_OVERUN_Msk (0x1ul << I2C_STATUS2_OVERUN_Pos) /*!< I2C STATUS2: OVERUN Mask */
#define I2C_STATUS2_UNDERUN_Pos (2) /*!< I2C STATUS2: UNDERUN Position */
#define I2C_STATUS2_UNDERUN_Msk (0x1ul << I2C_STATUS2_UNDERUN_Pos) /*!< I2C STATUS2: UNDERUN Mask */
#define I2C_STATUS2_WR_STATUS_Pos (3) /*!< I2C STATUS2: WR_STATUS Position */
#define I2C_STATUS2_WR_STATUS_Msk (0x1ul << I2C_STATUS2_WR_STATUS_Pos) /*!< I2C STATUS2: WR_STATUS Mask */
#define I2C_STATUS2_FULL_Pos (4) /*!< I2C STATUS2: FULL Position */
#define I2C_STATUS2_FULL_Msk (0x1ul << I2C_STATUS2_FULL_Pos) /*!< I2C STATUS2: FULL Mask */
#define I2C_STATUS2_EMPTY_Pos (5) /*!< I2C STATUS2: EMPTY Position */
#define I2C_STATUS2_EMPTY_Msk (0x1ul << I2C_STATUS2_EMPTY_Pos) /*!< I2C STATUS2: EMPTY Mask */
#define I2C_STATUS2_BUS_FREE_Pos (6) /*!< I2C STATUS2: BUS_FREE Position */
#define I2C_STATUS2_BUS_FREE_Msk (0x1ul << I2C_STATUS2_BUS_FREE_Pos) /*!< I2C STATUS2: BUS_FREE Mask */
/**@}*/ /* I2C_CONST */
/**@}*/ /* end of I2C register group */
/*---------------------- LCD Controller -------------------------*/
/**
@addtogroup LCD LCD Controller(LCD)
Memory Mapped Structure for LCD Controller
@{ */
typedef struct {
/**
* CTL
* ===================================================================================================
* Offset: 0x00 LCD Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |LCD Enable
* | | |0 = LCD controller operation Disabled.
* | | |1 = LCD controller operation Enabled.
* |[3:1] |MUX |Mux Select
* | | |000 = Static.
* | | |001 = 1/2 duty.
* | | |010 = 1/3 duty.
* | | |011 = 1/4 duty.
* | | |100 = 1/5 duty.
* | | |101 = 1/6 duty.
* | | |110 = Reserved.
* | | |111 = Reserved.
* | | |Note: User does not need to set PD_H_MFP bit field, but only to set the MUX bit field to switch LCD_SEG0 and LCD_SEG1 to LCD_COM4 and LCD_COM5.
* |[6:4] |FREQ |LCD Frequency Selection
* | | |000 = LCD_CLK Divided by 32.
* | | |001 = LCD_CLK Divided by 64.
* | | |010 = LCD_CLK Divided by 96.
* | | |011 = LCD_CLK Divided by 128.
* | | |100 = LCD_CLK Divided by 192.
* | | |101 = LCD_CLK Divided by 256.
* | | |110 = LCD_CLK Divided by 384.
* | | |111 = LCD_CLK Divided by 512.
* |[7] |BLINK |LCD Blinking Enable
* | | |0 = Blinking Disabled.
* | | |1 = Blinking Enabled.
* |[8] |PDDISP_EN |Power Down Display Enable
* | | |The LCD can be programmed to be displayed or not be displayed at power down state by PDDISP_EN setting.
* | | |0 = LCD display Disabled ( LCD is put out) at power down state.
* | | |1 = LCD display Enabled (LCD keeps the display) at power down state.
* |[9] |PDINT_EN |Power Down Interrupt Enable
* | | |If the power down request is triggered from system management, LCD controller will execute the frame completely to avoid the DC component.
* | | |When the frame is executed completely, the LCD power down interrupt signal is generated to inform system management that LCD controller is ready to enter power down state, if PDINT_EN is set to 1.
* | | |Otherwise, if PDINT_EN is set to 0, the LCD power down interrupt signal is blocked and the interrupt is disabled to send to system management.
* | | |0 = Power Down Interrupt Disabled.
* | | |1 = Power Down Interrupt Enabled.
*/
__IO uint32_t CTL;
/**
* DISPCTL
* ===================================================================================================
* Offset: 0x04 LCD Display Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CPUMP_EN |Charge Pump Enable
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[2:1] |BIAS_SEL |Bias Selection
* | | |00 = Static.
* | | |01 = 1/2 Bias.
* | | |10 = 1/3 Bias.
* | | |11 = Reserved.
* |[4] |IBRL_EN |Internal Bias Reference Ladder Enable
* | | |0 = Bias reference ladder Disabled.
* | | |1 = Bias reference ladder Enabled.
* |[6] |BV_SEL |Bias Voltage Type Selection
* | | |0 = C-Type bias mode. Bias voltage source from internal bias generator.
* | | |1 = R-Type bias mode. Bias voltage source from external bias generator.
* | | |Note: The external resistor ladder should be connected to the V1 pin, V2 pin, V3 pin and VSS.
* | | |The VLCD pin should also be connected to VDD.
* |[10:8] |CPUMP_VOL_SET|Charge Pump Voltage Selection
* | | |000 = 2.7V.
* | | |001 = 2.8V.
* | | |010 = 2.9V.
* | | |011 = 3.0V.
* | | |100 = 3.1V.
* | | |101 = 3.2V.
* | | |110 = 3.3V.
* | | |111 = 3.4V.
* |[13:11] |CPUMP_FREQ|Charge Pump Frequency Selection
* | | |000 = LCD_CLK.
* | | |001 = LCD_CLK/2.
* | | |010 = LCD_CLK/4.
* | | |011 = LCD_CLK/8.
* | | |100 = LCD_CLK/16.
* | | |101 = LCD_CLK/32.
* | | |110 = LCD_CLK/64.
* | | |111 = LCD_CLK/128.
* |[16] |Ext_C |Ext_C Mode Selection
* | | |This mode is similar to C-type LCD mode, but the operation current is lower than C-type mode.
* | | |The control register setting is same with C-type mode except this bit is set to "1".
* | | |0 = Disable.
* | | |1 = Enable.
* |[18:17] |Res_Sel |R-Type Resistor Value Selection
* | | |The LCD operation current will be different when we select different R-type resistor value.
* | | |00 = 200K Ohm.
* | | |01 = 300K Ohm.
* | | |10 = Reserved.
* | | |11 = 400K Ohm.
*/
__IO uint32_t DISPCTL;
/**
* MEM_0
* ===================================================================================================
* Offset: 0x08 LCD SEG3 ~ SEG0 data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
*/
__IO uint32_t MEM_0;
/**
* MEM_1
* ===================================================================================================
* Offset: 0x0C LCD SEG7 ~ SEG4 data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
*/
__IO uint32_t MEM_1;
/**
* MEM_2
* ===================================================================================================
* Offset: 0x10 LCD SEG11 ~ SEG8 data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
*/
__IO uint32_t MEM_2;
/**
* MEM_3
* ===================================================================================================
* Offset: 0x14 LCD SEG15 ~ SEG12 data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
*/
__IO uint32_t MEM_3;
/**
* MEM_4
* ===================================================================================================
* Offset: 0x18 LCD SEG19 ~ SEG16 data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
*/
__IO uint32_t MEM_4;
/**
* MEM_5
* ===================================================================================================
* Offset: 0x1C LCD SEG23 ~ SEG20 data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
*/
__IO uint32_t MEM_5;
/**
* MEM_6
* ===================================================================================================
* Offset: 0x20 LCD SEG27 ~ SEG24 data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
*/
__IO uint32_t MEM_6;
/**
* MEM_7
* ===================================================================================================
* Offset: 0x24 LCD SEG31 ~ SEG28 data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
*/
__IO uint32_t MEM_7;
/**
* MEM_8
* ===================================================================================================
* Offset: 0x28 LCD SEG35 ~ SEG32 data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
* |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM0 ~ COM5 (x= 0 ~ 8)
* | | |LCD display data
*/
__IO uint32_t MEM_8;
uint32_t RESERVE0[1];
/**
* FCR
* ===================================================================================================
* Offset: 0x30 LCD frame counter control register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FCEN |LCD Frame Counter Enable
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[1] |FCINTEN |LCD Frame Counter Interrupt Enable
* | | |0 = Frame counter interrupt Disabled.
* | | |1 = Frame counter interrupt Enabled.
* |[3:2] |PRESCL |Frame Counter Pre-Scaler Value
* | | |00 = CLKframe/1.
* | | |01 = CLKframe/2.
* | | |10 = CLKframe/4.
* | | |11 = CLKframe/8.
* |[9:4] |FCV |Frame Counter Top Value
* | | |These 6 bits contain the top value of the Frame counter.
*/
__IO uint32_t FCR;
/**
* FCSTS
* ===================================================================================================
* Offset: 0x34 LCD frame counter status
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FCSTS |LCD Frame Counter Status
* | | |0 = Frame counter value does not reach FCV (Frame Count TOP value).
* | | |1 = Frame counter value reaches FCV (Frame Count TOP value).
* | | |If the FCINTEN is s enabled, the frame counter overflow Interrupt is generated.
* |[1] |PDSTS |Power-Down Interrupt Status
* | | |0 = Inform system manager that LCD controller is not ready to enter power-down state until this bit becomes 1 if power down is set and one frame is not executed completely.
* | | |1 = Inform system manager that LCD controller is ready to enter power-down state if power down is set and one frame is executed completely
*/
__IO uint32_t FCSTS;
} LCD_T;
/**
@addtogroup LCD_CONST LCD Bit Field Definition
Constant Definitions for LCD Controller
@{ */
#define LCD_CTL_EN_Pos (0) /*!< LCD CTL: EN Position */
#define LCD_CTL_EN_Msk (0x1ul << LCD_CTL_EN_Pos) /*!< LCD CTL: EN Mask */
#define LCD_CTL_MUX_Pos (1) /*!< LCD CTL: MUX Position */
#define LCD_CTL_MUX_Msk (0x7ul << LCD_CTL_MUX_Pos) /*!< LCD CTL: MUX Mask */
#define LCD_CTL_FREQ_Pos (4) /*!< LCD CTL: FREQ Position */
#define LCD_CTL_FREQ_Msk (0x7ul << LCD_CTL_FREQ_Pos) /*!< LCD CTL: FREQ Mask */
#define LCD_CTL_BLINK_Pos (7) /*!< LCD CTL: BLINK Position */
#define LCD_CTL_BLINK_Msk (0x1ul << LCD_CTL_BLINK_Pos) /*!< LCD CTL: BLINK Mask */
#define LCD_CTL_PDDISP_EN_Pos (8) /*!< LCD CTL: PDDISP_EN Position */
#define LCD_CTL_PDDISP_EN_Msk (0x1ul << LCD_CTL_PDDISP_EN_Pos) /*!< LCD CTL: PDDISP_EN Mask */
#define LCD_CTL_PDINT_EN_Pos (9) /*!< LCD CTL: PDINT_EN Position */
#define LCD_CTL_PDINT_EN_Msk (0x1ul << LCD_CTL_PDINT_EN_Pos) /*!< LCD CTL: PDINT_EN Mask */
#define LCD_DISPCTL_CPUMP_EN_Pos (0) /*!< LCD DISPCTL: CPUMP_EN Position */
#define LCD_DISPCTL_CPUMP_EN_Msk (0x1ul << LCD_DISPCTL_CPUMP_EN_Pos) /*!< LCD DISPCTL: CPUMP_EN Mask */
#define LCD_DISPCTL_BIAS_SEL_Pos (1) /*!< LCD DISPCTL: BIAS_SEL Position */
#define LCD_DISPCTL_BIAS_SEL_Msk (0x3ul << LCD_DISPCTL_BIAS_SEL_Pos) /*!< LCD DISPCTL: BIAS_SEL Mask */
#define LCD_DISPCTL_IBRL_EN_Pos (4) /*!< LCD DISPCTL: IBRL_EN Position */
#define LCD_DISPCTL_IBRL_EN_Msk (0x1ul << LCD_DISPCTL_IBRL_EN_Pos) /*!< LCD DISPCTL: IBRL_EN Mask */
#define LCD_DISPCTL_BV_SEL_Pos (6) /*!< LCD DISPCTL: BV_SEL Position */
#define LCD_DISPCTL_BV_SEL_Msk (0x1ul << LCD_DISPCTL_BV_SEL_Pos) /*!< LCD DISPCTL: BV_SEL Mask */
#define LCD_DISPCTL_CPUMP_VOL_SET_Pos (8) /*!< LCD DISPCTL: CPUMP_VOL_SET Position */
#define LCD_DISPCTL_CPUMP_VOL_SET_Msk (0x7ul << LCD_DISPCTL_CPUMP_VOL_SET_Pos) /*!< LCD DISPCTL: CPUMP_VOL_SET Mask */
#define LCD_DISPCTL_CPUMP_FREQ_Pos (11) /*!< LCD DISPCTL: CPUMP_FREQ Position */
#define LCD_DISPCTL_CPUMP_FREQ_Msk (0x7ul << LCD_DISPCTL_CPUMP_FREQ_Pos) /*!< LCD DISPCTL: CPUMP_FREQ Mask */
#define LCD_DISPCTL_Ext_C_Pos (16) /*!< LCD DISPCTL: Ext_C Position */
#define LCD_DISPCTL_Ext_C_Msk (0x1ul << LCD_DISPCTL_Ext_C_Pos) /*!< LCD DISPCTL: Ext_C Mask */
#define LCD_DISPCTL_Res_Sel_Pos (17) /*!< LCD DISPCTL: Res_Sel Position */
#define LCD_DISPCTL_Res_Sel_Msk (0x3ul << LCD_DISPCTL_Res_Sel_Pos) /*!< LCD DISPCTL: Res_Sel Mask */
#define LCD_MEM_0_SEG_0_4x_Pos (0) /*!< LCD MEM_0: SEG_0_4x Position */
#define LCD_MEM_0_SEG_0_4x_Msk (0x3ful << LCD_MEM_0_SEG_0_4x_Pos) /*!< LCD MEM_0: SEG_0_4x Mask */
#define LCD_MEM_0_SEG_1_4x_Pos (8) /*!< LCD MEM_0: SEG_1_4x Position */
#define LCD_MEM_0_SEG_1_4x_Msk (0x7ful << LCD_MEM_0_SEG_1_4x_Pos) /*!< LCD MEM_0: SEG_1_4x Mask */
#define LCD_MEM_0_SEG_2_4x_Pos (16) /*!< LCD MEM_0: SEG_2_4x Position */
#define LCD_MEM_0_SEG_2_4x_Msk (0x3ful << LCD_MEM_0_SEG_2_4x_Pos) /*!< LCD MEM_0: SEG_2_4x Mask */
#define LCD_MEM_0_SEG_3_4x_Pos (24) /*!< LCD MEM_0: SEG_3_4x Position */
#define LCD_MEM_0_SEG_3_4x_Msk (0x3ful << LCD_MEM_0_SEG_3_4x_Pos) /*!< LCD MEM_0: SEG_3_4x Mask */
#define LCD_MEM_1_SEG_0_4x_Pos (0) /*!< LCD MEM_1: SEG_0_4x Position */
#define LCD_MEM_1_SEG_0_4x_Msk (0x3ful << LCD_MEM_1_SEG_0_4x_Pos) /*!< LCD MEM_1: SEG_0_4x Mask */
#define LCD_MEM_1_SEG_1_4x_Pos (8) /*!< LCD MEM_1: SEG_1_4x Position */
#define LCD_MEM_1_SEG_1_4x_Msk (0x7ful << LCD_MEM_1_SEG_1_4x_Pos) /*!< LCD MEM_1: SEG_1_4x Mask */
#define LCD_MEM_1_SEG_2_4x_Pos (16) /*!< LCD MEM_1: SEG_2_4x Position */
#define LCD_MEM_1_SEG_2_4x_Msk (0x3ful << LCD_MEM_1_SEG_2_4x_Pos) /*!< LCD MEM_1: SEG_2_4x Mask */
#define LCD_MEM_1_SEG_3_4x_Pos (24) /*!< LCD MEM_1: SEG_3_4x Position */
#define LCD_MEM_1_SEG_3_4x_Msk (0x3ful << LCD_MEM_1_SEG_3_4x_Pos) /*!< LCD MEM_1: SEG_3_4x Mask */
#define LCD_MEM_2_SEG_0_4x_Pos (0) /*!< LCD MEM_2: SEG_0_4x Position */
#define LCD_MEM_2_SEG_0_4x_Msk (0x3ful << LCD_MEM_2_SEG_0_4x_Pos) /*!< LCD MEM_2: SEG_0_4x Mask */
#define LCD_MEM_2_SEG_1_4x_Pos (8) /*!< LCD MEM_2: SEG_1_4x Position */
#define LCD_MEM_2_SEG_1_4x_Msk (0x7ful << LCD_MEM_2_SEG_1_4x_Pos) /*!< LCD MEM_2: SEG_1_4x Mask */
#define LCD_MEM_2_SEG_2_4x_Pos (16) /*!< LCD MEM_2: SEG_2_4x Position */
#define LCD_MEM_2_SEG_2_4x_Msk (0x3ful << LCD_MEM_2_SEG_2_4x_Pos) /*!< LCD MEM_2: SEG_2_4x Mask */
#define LCD_MEM_2_SEG_3_4x_Pos (24) /*!< LCD MEM_2: SEG_3_4x Position */
#define LCD_MEM_2_SEG_3_4x_Msk (0x3ful << LCD_MEM_2_SEG_3_4x_Pos) /*!< LCD MEM_2: SEG_3_4x Mask */
#define LCD_MEM_3_SEG_0_4x_Pos (0) /*!< LCD MEM_3: SEG_0_4x Position */
#define LCD_MEM_3_SEG_0_4x_Msk (0x3ful << LCD_MEM_3_SEG_0_4x_Pos) /*!< LCD MEM_3: SEG_0_4x Mask */
#define LCD_MEM_3_SEG_1_4x_Pos (8) /*!< LCD MEM_3: SEG_1_4x Position */
#define LCD_MEM_3_SEG_1_4x_Msk (0x7ful << LCD_MEM_3_SEG_1_4x_Pos) /*!< LCD MEM_3: SEG_1_4x Mask */
#define LCD_MEM_3_SEG_2_4x_Pos (16) /*!< LCD MEM_3: SEG_2_4x Position */
#define LCD_MEM_3_SEG_2_4x_Msk (0x3ful << LCD_MEM_3_SEG_2_4x_Pos) /*!< LCD MEM_3: SEG_2_4x Mask */
#define LCD_MEM_3_SEG_3_4x_Pos (24) /*!< LCD MEM_3: SEG_3_4x Position */
#define LCD_MEM_3_SEG_3_4x_Msk (0x3ful << LCD_MEM_3_SEG_3_4x_Pos) /*!< LCD MEM_3: SEG_3_4x Mask */
#define LCD_MEM_4_SEG_0_4x_Pos (0) /*!< LCD MEM_4: SEG_0_4x Position */
#define LCD_MEM_4_SEG_0_4x_Msk (0x3ful << LCD_MEM_4_SEG_0_4x_Pos) /*!< LCD MEM_4: SEG_0_4x Mask */
#define LCD_MEM_4_SEG_1_4x_Pos (8) /*!< LCD MEM_4: SEG_1_4x Position */
#define LCD_MEM_4_SEG_1_4x_Msk (0x7ful << LCD_MEM_4_SEG_1_4x_Pos) /*!< LCD MEM_4: SEG_1_4x Mask */
#define LCD_MEM_4_SEG_2_4x_Pos (16) /*!< LCD MEM_4: SEG_2_4x Position */
#define LCD_MEM_4_SEG_2_4x_Msk (0x3ful << LCD_MEM_4_SEG_2_4x_Pos) /*!< LCD MEM_4: SEG_2_4x Mask */
#define LCD_MEM_4_SEG_3_4x_Pos (24) /*!< LCD MEM_4: SEG_3_4x Position */
#define LCD_MEM_4_SEG_3_4x_Msk (0x3ful << LCD_MEM_4_SEG_3_4x_Pos) /*!< LCD MEM_4: SEG_3_4x Mask */
#define LCD_MEM_5_SEG_0_4x_Pos (0) /*!< LCD MEM_5: SEG_0_4x Position */
#define LCD_MEM_5_SEG_0_4x_Msk (0x3ful << LCD_MEM_5_SEG_0_4x_Pos) /*!< LCD MEM_5: SEG_0_4x Mask */
#define LCD_MEM_5_SEG_1_4x_Pos (8) /*!< LCD MEM_5: SEG_1_4x Position */
#define LCD_MEM_5_SEG_1_4x_Msk (0x7ful << LCD_MEM_5_SEG_1_4x_Pos) /*!< LCD MEM_5: SEG_1_4x Mask */
#define LCD_MEM_5_SEG_2_4x_Pos (16) /*!< LCD MEM_5: SEG_2_4x Position */
#define LCD_MEM_5_SEG_2_4x_Msk (0x3ful << LCD_MEM_5_SEG_2_4x_Pos) /*!< LCD MEM_5: SEG_2_4x Mask */
#define LCD_MEM_5_SEG_3_4x_Pos (24) /*!< LCD MEM_5: SEG_3_4x Position */
#define LCD_MEM_5_SEG_3_4x_Msk (0x3ful << LCD_MEM_5_SEG_3_4x_Pos) /*!< LCD MEM_5: SEG_3_4x Mask */
#define LCD_MEM_6_SEG_0_4x_Pos (0) /*!< LCD MEM_6: SEG_0_4x Position */
#define LCD_MEM_6_SEG_0_4x_Msk (0x3ful << LCD_MEM_6_SEG_0_4x_Pos) /*!< LCD MEM_6: SEG_0_4x Mask */
#define LCD_MEM_6_SEG_1_4x_Pos (8) /*!< LCD MEM_6: SEG_1_4x Position */
#define LCD_MEM_6_SEG_1_4x_Msk (0x7ful << LCD_MEM_6_SEG_1_4x_Pos) /*!< LCD MEM_6: SEG_1_4x Mask */
#define LCD_MEM_6_SEG_2_4x_Pos (16) /*!< LCD MEM_6: SEG_2_4x Position */
#define LCD_MEM_6_SEG_2_4x_Msk (0x3ful << LCD_MEM_6_SEG_2_4x_Pos) /*!< LCD MEM_6: SEG_2_4x Mask */
#define LCD_MEM_6_SEG_3_4x_Pos (24) /*!< LCD MEM_6: SEG_3_4x Position */
#define LCD_MEM_6_SEG_3_4x_Msk (0x3ful << LCD_MEM_6_SEG_3_4x_Pos) /*!< LCD MEM_6: SEG_3_4x Mask */
#define LCD_MEM_7_SEG_0_4x_Pos (0) /*!< LCD MEM_7: SEG_0_4x Position */
#define LCD_MEM_7_SEG_0_4x_Msk (0x3ful << LCD_MEM_7_SEG_0_4x_Pos) /*!< LCD MEM_7: SEG_0_4x Mask */
#define LCD_MEM_7_SEG_1_4x_Pos (8) /*!< LCD MEM_7: SEG_1_4x Position */
#define LCD_MEM_7_SEG_1_4x_Msk (0x7ful << LCD_MEM_7_SEG_1_4x_Pos) /*!< LCD MEM_7: SEG_1_4x Mask */
#define LCD_MEM_7_SEG_2_4x_Pos (16) /*!< LCD MEM_7: SEG_2_4x Position */
#define LCD_MEM_7_SEG_2_4x_Msk (0x3ful << LCD_MEM_7_SEG_2_4x_Pos) /*!< LCD MEM_7: SEG_2_4x Mask */
#define LCD_MEM_7_SEG_3_4x_Pos (24) /*!< LCD MEM_7: SEG_3_4x Position */
#define LCD_MEM_7_SEG_3_4x_Msk (0x3ful << LCD_MEM_7_SEG_3_4x_Pos) /*!< LCD MEM_7: SEG_3_4x Mask */
#define LCD_MEM_8_SEG_0_4x_Pos (0) /*!< LCD MEM_8: SEG_0_4x Position */
#define LCD_MEM_8_SEG_0_4x_Msk (0x3ful << LCD_MEM_8_SEG_0_4x_Pos) /*!< LCD MEM_8: SEG_0_4x Mask */
#define LCD_MEM_8_SEG_1_4x_Pos (8) /*!< LCD MEM_8: SEG_1_4x Position */
#define LCD_MEM_8_SEG_1_4x_Msk (0x7ful << LCD_MEM_8_SEG_1_4x_Pos) /*!< LCD MEM_8: SEG_1_4x Mask */
#define LCD_MEM_8_SEG_2_4x_Pos (16) /*!< LCD MEM_8: SEG_2_4x Position */
#define LCD_MEM_8_SEG_2_4x_Msk (0x3ful << LCD_MEM_8_SEG_2_4x_Pos) /*!< LCD MEM_8: SEG_2_4x Mask */
#define LCD_MEM_8_SEG_3_4x_Pos (24) /*!< LCD MEM_8: SEG_3_4x Position */
#define LCD_MEM_8_SEG_3_4x_Msk (0x3ful << LCD_MEM_8_SEG_3_4x_Pos) /*!< LCD MEM_8: SEG_3_4x Mask */
#define LCD_FCR_FCEN_Pos (0) /*!< LCD FCR: FCEN Position */
#define LCD_FCR_FCEN_Msk (0x1ul << LCD_FCR_FCEN_Pos) /*!< LCD FCR: FCEN Mask */
#define LCD_FCR_FCINTEN_Pos (1) /*!< LCD FCR: FCINTEN Position */
#define LCD_FCR_FCINTEN_Msk (0x1ul << LCD_FCR_FCINTEN_Pos) /*!< LCD FCR: FCINTEN Mask */
#define LCD_FCR_PRESCL_Pos (2) /*!< LCD FCR: PRESCL Position */
#define LCD_FCR_PRESCL_Msk (0x3ul << LCD_FCR_PRESCL_Pos) /*!< LCD FCR: PRESCL Mask */
#define LCD_FCR_FCV_Pos (4) /*!< LCD FCR: FCV Position */
#define LCD_FCR_FCV_Msk (0x3ful << LCD_FCR_FCV_Pos) /*!< LCD FCR: FCV Mask */
#define LCD_FCSTS_FCSTS_Pos (0) /*!< LCD FCSTS: FCSTS Position */
#define LCD_FCSTS_FCSTS_Msk (0x1ul << LCD_FCSTS_FCSTS_Pos) /*!< LCD FCSTS: FCSTS Mask */
#define LCD_FCSTS_PDSTS_Pos (1) /*!< LCD FCSTS: PDSTS Position */
#define LCD_FCSTS_PDSTS_Msk (0x1ul << LCD_FCSTS_PDSTS_Pos) /*!< LCD FCSTS: PDSTS Mask */
/**@}*/ /* LCD_CONST */
/**@}*/ /* end of LCD register group */
/*---------------------- Pulse Width Modulation Controller -------------------------*/
/**
@addtogroup PWM Pulse Width Modulation Controller(PWM)
Memory Mapped Structure for PWM Controller
@{ */
typedef struct {
/**
* PRES
* ===================================================================================================
* Offset: 0x00 PWM Prescaler Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CP01 |Clock Prescaler 0 For PWM Timer 0 & 1
* | | |Clock input is divided by (CP01 + 1) before it is fed to the PWM counter 0 & 1
* | | |If CP01 =0, the prescaler 0 output clock will be stopped. So PWM counter 0 and 1 will be stopped also.
* |[15:8] |CP23 |Clock Prescaler 2 For PWM Timer 2 & 3
* | | |Clock input is divided by (CP23 + 1) before it is fed to the PWM counter 2 & 3
* | | |If CP23=0, the prescaler 2 output clock will be stopped. So PWM counter 2 and 3 will be stopped also.
* |[23:16] |DZ01 |Dead Zone Interval Register For CH0 And CH1 Pair
* | | |These 8 bits determine dead zone length.
* | | |The unit time of dead zone length is received from clock selector 0.
* |[31:24] |DZ23 |Dead Zone Interval Register For CH2 And CH3 Pair
* | | |These 8 bits determine dead zone length.
* | | |The unit time of dead zone length is received from clock selector 2.
*/
__IO uint32_t PRES;
/**
* CLKSEL
* ===================================================================================================
* Offset: 0x04 PWM Clock Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |CLKSEL0 |Timer 0 Clock Source Selection
* | | |Select clock input for timer 0.
* | | |(Table is the same as CLKSEL3)
* |[6:4] |CLKSEL1 |Timer 1 Clock Source Selection
* | | |Select clock input for timer 1.
* | | |(Table is the same as CLKSEL3)
* |[10:8] |CLKSEL2 |Timer 2 Clock Source Selection
* | | |Select clock input for timer 2.
* | | |(Table is the same as CLKSEL3)
* |[14:12] |CLKSEL3 |Timer 3 Clock Source Selection
* | | |Select clock input for timer 3.
* | | |000 = input clock is divided by 2.
* | | |001 = input clock is divided by 4.
* | | |010 = input clock is divided by 8.
* | | |011 = input clock is divided by 16.
* | | |100 = input clock is divided by 1.
*/
__IO uint32_t CLKSEL;
/**
* CTL
* ===================================================================================================
* Offset: 0x08 PWM Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0EN |PWM-Timer 0 Enable/Disable Start Run
* | | |0 = PWM-Timer 0 Running Stopped.
* | | |1 = PWM-Timer 0 Start Run Enabled.
* |[2] |CH0INV |PWM-Timer 0 Output Inverter ON/OFF
* | | |0 = Inverter OFF.
* | | |1 = Inverter ON.
* |[3] |CH0MOD |PWM-Timer 0 Continuous/One-Shot Mode
* | | |0 = One-Shot Mode.
* | | |1 = Continuous Mode.
* | | |Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY0 to be cleared.
* |[4] |DZEN01 |Dead-Zone 0 Generator Enable/Disable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair.
* |[5] |DZEN23 |Dead-Zone 2 Generator Enable/Disable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* | | |Note: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair.
* |[8] |CH1EN |PWM-Timer 1 Enable/Disable Start Run
* | | |0 = PWM-Timer 1 Running Stopped.
* | | |1 = PWM-Timer 1 Start Run Enabled.
* |[10] |CH1INV |PWM-Timer 1 Output Inverter ON/OFF
* | | |0 = Inverter OFF.
* | | |1 = Inverter ON.
* |[11] |CH1MOD |PWM-Timer 1 Continuous/One-Shot Mode
* | | |0 = One-Shot Mode.
* | | |1 = Continuous Mode.
* | | |Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY1 to be cleared.
* |[16] |CH2EN |PWM-Timer 2 Enable/Disable Start Run
* | | |0 = PWM-Timer 2 Running Stopped.
* | | |1 = PWM-Timer 2 Start Run Enabled.
* |[18] |CH2INV |PWM-Timer 2 Output Inverter ON/OFF
* | | |0 = Inverter OFF.
* | | |1 = Inverter ON.
* |[19] |CH2MOD |PWM-Timer 2 Continuous/One-Shot Mode
* | | |0 = One-Shot Mode.
* | | |1 = Continuous Mode.
* | | |Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY2 be cleared.
* |[24] |CH3EN |PWM-Timer 3 Enable/Disable Start Run
* | | |0 = PWM-Timer 3 Running Stopped.
* | | |1 = PWM-Timer 3 Start Run Enabled.
* |[26] |CH3INV |PWM-Timer 3 Output Inverter ON/OFF
* | | |0 = Inverter OFF.
* | | |1 = Inverter ON.
* |[27] |CH3MOD |PWM-Timer 3 Continuous/One-Shot Mode
* | | |0 = One-Shot Mode.
* | | |1 = Continuous Mode.
* | | |Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY3 to be cleared.
* |[30] |PWMTYPE01 |Channel 0,1 Counter Mode
* | | |0 = Edge-aligned Mode.
* | | |1 = Center-aligned Mode.
* |[31] |PWMTYPE23 |Channel 2,3 Counter Mode
* | | |0 = Edge-aligned Mode.
* | | |1 = Center-aligned Mode.
*/
__IO uint32_t CTL;
/**
* INTEN
* ===================================================================================================
* Offset: 0x0C PWM Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TMIE0 |PWM Timer 0 Interrupt Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[1] |TMIE1 |PWM Timer 1 Interrupt Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[2] |TMIE2 |PWM Timer 2 Interrupt Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
* |[3] |TMIE3 |PWM Timer 3 Interrupt Enable Control
* | | |0 = Disabled.
* | | |1 = Enabled.
*/
__IO uint32_t INTEN;
/**
* INTSTS
* ===================================================================================================
* Offset: 0x10 PWM Interrupt Indication Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TMINT0 |PWM Timer 0 Interrupt Flag
* | | |Flag is set by hardware when PWM0 down counter reaches 0, software can clear this bit by writing a one to it.
* |[1] |TMINT1 |PWM Timer 1 Interrupt Flag
* | | |Flag is set by hardware when PWM1 down counter reaches 0, software can clear this bit by writing a one to it.
* |[2] |TMINT2 |PWM Timer 2 Interrupt Flag
* | | |Flag is set by hardware when PWM2 down counter reaches 0, software can clear this bit by writing a one to it.
* |[3] |TMINT3 |PWM Timer 3 Interrupt Flag
* | | |Flag is set by hardware when PWM3 down counter reaches 0, software can clear this bit by writing a one to it.
* |[4] |Duty0Syncflag|Duty0 Synchronize Flag
* | | |0 = Duty0 has been synchronized to PWM_CLK domain of channel 0, 1.
* | | |1 = Duty0 is synchronizing to PWM_CLK domain of channel 0, 1.
* | | |Note: software should check this flag when writing duty0, if this flag is set, and user ignore this flag and change duty0, the corresponding CNR and CMR may be wrong for one duty cycle
* |[5] |Duty1Syncflag|Duty1 Synchronize Flag
* | | |0 = Duty1 has been synchronized to PWM_CLK domain of channel 0, 1.
* | | |1 = Duty1 is synchronizing to PWM_CLK domain of channel 0, 1.
* | | |Note: software should check this flag when writing duty1, if this flag is set, and user ignore this flag and change duty1, the corresponding CNR and CMR may be wrong for one duty cycle
* |[6] |Duty2Syncflag|Duty2 Synchronize Flag
* | | |0 = Duty2 has been synchronized to PWM_CLK domain of channel 2, 3.
* | | |1 = Duty2 is synchronizing to PWM_CLK domain of channel 2, 3.
* | | |Note: software should check this flag when writing duty2, if this flag is set, and user ignore this flag and change duty2, the corresponding CNR and CMR may be wrong for one duty cycle
* |[7] |Duty3Syncflag|Duty3 Synchronize Flag
* | | |0 = Duty3 has been synchronized to PWM_CLK domain of channel 2, 3.
* | | |1 = Duty3 is synchronizing to PWM_CLK domain of channel 2, 3.
* | | |Note: software should check this flag when writing duty3, if this flag is set, and user ignore this flag and change duty3, the corresponding CNR and CMR may be wrong for one duty cycle
* |[8] |PresSyncFlag|Prescale Synchronize Flag
* | | |0 = Two Prescales have been synchronized to corresponding PWM_CLK (of channel 0,1 or channel 2, 3) domain respectively.
* | | |1 = Prescale01 is synchronizing to PWM_CLK domain of channel 0,1 or Prescaler23 is synchronizing to PWM_CLK domain of channel 2, 3.
* | | |Note: software should check this flag when writing Prescale, if this flag is set, and user ignore this flag and change Prescale, the Prescale may be wrong for one prescale cycle
*/
__IO uint32_t INTSTS;
/**
* OE
* ===================================================================================================
* Offset: 0x14 PWM Output Enable for PWM0~PWM3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0_OE |PWM CH0 Output Enable Control
* | | |0 = PWM CH0 output to pin Disabled.
* | | |1 = PWM CH0 output to pin Enabled.
* |[1] |CH1_OE |PWM CH1 Output Enable Control
* | | |0 = PWM CH1 output to pin Disabled.
* | | |1 = PWM CH1 output to pin Enabled.
* |[2] |CH2_OE |PWM CH2 Output Enable Control R
* | | |0 = PWM CH2 output to pin Disabled.
* | | |1 = PWM CH2 output to pin Enabled.
* |[3] |CH3_OE |PWM CH3 Output Enable Control
* | | |0 = PWM CH3 output to pin Disabled.
* | | |1 = PWM CH3 output to pin Enabled.
*/
__IO uint32_t OE;
uint32_t RESERVE0[1];
/**
* DUTY0
* ===================================================================================================
* Offset: 0x1C PWM Counter/Comparator Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CN |PWM Counter/Timer Loaded Value
* | | |CN determines the PWM period.
* | | |In edge-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (CM+1)/(CN+1).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
* | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |In center-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (2xCM+1)/(2x(CN+1)).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
* | | |CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |Note: Any write to CN will take effect in next PWM cycle.
* |[31:16] |CM |PWM Comparator Register
* | | |CM determines the PWM duty.
* | | |In edge-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (CM+1)/(CN+1).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
* | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |In center-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (2xCM+1)/(2x(CN+1)).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
* | | |CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |Note:Any write to CM will take effect in next PWM cycle.
*/
__IO uint32_t DUTY0;
/**
* DATA0
* ===================================================================================================
* Offset: 0x20 PWM Data Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DATA |PWM Data Register
* | | |User can monitor PWM_DATA to know the current value in 16-bit down count counter of corresponding channel.
* |[30:16] |DATA_H |PWM Data Register
* | | |User can monitor PWM_DATA to know the current value in 32-bit down count counter of corresponding channel.
* | | |Notes: This will be valid only for the corresponding cascade enable bit is set
* |[31] |sync |CN Value Sync With PWM Counter
* | | |0 = CN value is sync to PWM counter.
* | | |1 = CN value is not sync to PWM counter.
* | | |Note: when the corresponding cascade enable bit is set, this bit will not appear in the corresponding channel
*/
__I uint32_t DATA0;
uint32_t RESERVE1[1];
/**
* DUTY1
* ===================================================================================================
* Offset: 0x28 PWM Counter/Comparator Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CN |PWM Counter/Timer Loaded Value
* | | |CN determines the PWM period.
* | | |In edge-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (CM+1)/(CN+1).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
* | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |In center-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (2xCM+1)/(2x(CN+1)).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
* | | |CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |Note: Any write to CN will take effect in next PWM cycle.
* |[31:16] |CM |PWM Comparator Register
* | | |CM determines the PWM duty.
* | | |In edge-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (CM+1)/(CN+1).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
* | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |In center-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (2xCM+1)/(2x(CN+1)).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
* | | |CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |Note:Any write to CM will take effect in next PWM cycle.
*/
__IO uint32_t DUTY1;
/**
* DATA1
* ===================================================================================================
* Offset: 0x2C PWM Data Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DATA |PWM Data Register
* | | |User can monitor PWM_DATA to know the current value in 16-bit down count counter of corresponding channel.
* |[30:16] |DATA_H |PWM Data Register
* | | |User can monitor PWM_DATA to know the current value in 32-bit down count counter of corresponding channel.
* | | |Notes: This will be valid only for the corresponding cascade enable bit is set
* |[31] |sync |CN Value Sync With PWM Counter
* | | |0 = CN value is sync to PWM counter.
* | | |1 = CN value is not sync to PWM counter.
* | | |Note: when the corresponding cascade enable bit is set, this bit will not appear in the corresponding channel
*/
__I uint32_t DATA1;
uint32_t RESERVE2[1];
/**
* DUTY2
* ===================================================================================================
* Offset: 0x34 PWM Counter/Comparator Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CN |PWM Counter/Timer Loaded Value
* | | |CN determines the PWM period.
* | | |In edge-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (CM+1)/(CN+1).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
* | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |In center-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (2xCM+1)/(2x(CN+1)).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
* | | |CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |Note: Any write to CN will take effect in next PWM cycle.
* |[31:16] |CM |PWM Comparator Register
* | | |CM determines the PWM duty.
* | | |In edge-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (CM+1)/(CN+1).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
* | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |In center-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (2xCM+1)/(2x(CN+1)).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
* | | |CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |Note:Any write to CM will take effect in next PWM cycle.
*/
__IO uint32_t DUTY2;
/**
* DATA2
* ===================================================================================================
* Offset: 0x38 PWM Data Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DATA |PWM Data Register
* | | |User can monitor PWM_DATA to know the current value in 16-bit down count counter of corresponding channel.
* |[30:16] |DATA_H |PWM Data Register
* | | |User can monitor PWM_DATA to know the current value in 32-bit down count counter of corresponding channel.
* | | |Notes: This will be valid only for the corresponding cascade enable bit is set
* |[31] |sync |CN Value Sync With PWM Counter
* | | |0 = CN value is sync to PWM counter.
* | | |1 = CN value is not sync to PWM counter.
* | | |Note: when the corresponding cascade enable bit is set, this bit will not appear in the corresponding channel
*/
__I uint32_t DATA2;
uint32_t RESERVE3[1];
/**
* DUTY3
* ===================================================================================================
* Offset: 0x40 PWM Counter/Comparator Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CN |PWM Counter/Timer Loaded Value
* | | |CN determines the PWM period.
* | | |In edge-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (CM+1)/(CN+1).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
* | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |In center-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (2xCM+1)/(2x(CN+1)).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
* | | |CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |Note: Any write to CN will take effect in next PWM cycle.
* |[31:16] |CM |PWM Comparator Register
* | | |CM determines the PWM duty.
* | | |In edge-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (CM+1)/(CN+1).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
* | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |In center-aligned mode,
* | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(2x(CN+1)); where xy could be 01, 23, depending on the selected PWM channel.
* | | |Duty ratio = (2xCM+1)/(2x(CN+1)).
* | | |CM >= CN: PWM output is always high.
* | | |CM < CN: PWM low width = 2x(CN-CM)+1 unit; PWM high width = (2xCM+1) unit.
* | | |CM = 0: PWM low width = (2xCN+1) unit; PWM high width = 1 unit.
* | | |(Unit = one PWM clock cycle).
* | | |Note:Any write to CM will take effect in next PWM cycle.
*/
__IO uint32_t DUTY3;
/**
* DATA3
* ===================================================================================================
* Offset: 0x44 PWM Data Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DATA |PWM Data Register
* | | |User can monitor PWM_DATA to know the current value in 16-bit down count counter of corresponding channel.
* |[30:16] |DATA_H |PWM Data Register
* | | |User can monitor PWM_DATA to know the current value in 32-bit down count counter of corresponding channel.
* | | |Notes: This will be valid only for the corresponding cascade enable bit is set
* |[31] |sync |CN Value Sync With PWM Counter
* | | |0 = CN value is sync to PWM counter.
* | | |1 = CN value is not sync to PWM counter.
* | | |Note: when the corresponding cascade enable bit is set, this bit will not appear in the corresponding channel
*/
__I uint32_t DATA3;
uint32_t RESERVE4[3];
/**
* CAPCTL
* ===================================================================================================
* Offset: 0x54 Capture Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |INV0 |Channel 0 Inverter ON/OFF
* | | |0 = Inverter OFF.
* | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
* |[1] |CAPCH0EN |Capture Channel 0 Transition Enable/Disable Control
* | | |0 = Capture function on channel 0 Disabled.
* | | |1 = Capture function on channel 0 Enabled.
* | | |When Enabled, Capture latched the PWM-timer value and saved to CRL0 (PWM_CRL0[15:0]) for rising latch and CFL0 (PWM_CFL0[15:0]) for falling latch.
* | | |When Disabled, Capture does not update CRL0 (PWM_CRL0[15:0]) and CFL0 (PWM_CFL0[15:0]), and disable Channel 0 Interrupt.
* |[2] |CAPCH0PADEN|Capture Input Enable Control
* | | |0 = Disable the channel 0 input capture signal from corresponding multi-function pin.
* | | |1 = Enable the channel 0 input capture signal from corresponding multi-function pin.
* |[3] |CH0PDMAEN |Channel 0 PDMA Enable Control
* | | |0 = Channel 0 PDMA function Disabled.
* | | |1 = Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory.
* |[5:4] |PDMACAPMOD0|Select CRL0 Or CFL0 For PDMA Transfer
* | | |00 = reserved.
* | | |01 = CRL0 will be transmitted.
* | | |10 = CFL0 will be transmitted.
* | | |11 = Both CRL0 and CFL0 will be transmitted.
* |[6] |CAPRELOADREN0|Reload CNR0 When CH0 Capture Rising Event Comes
* | | |0 = Rising capture reload for CH0 Disabled.
* | | |1 = Rising capture reload for CH0 Enabled.
* |[7] |CAPRELOADFEN0|Reload CNR0 When CH0 Capture Falling Event Comes
* | | |0 = Falling capture reload for CH0 Disabled.
* | | |1 = Falling capture reload for CH0 Enabled.
* |[8] |INV1 |Channel 1 Inverter ON/OFF
* | | |0 = Inverter OFF.
* | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
* |[9] |CAPCH1EN |Capture Channel 1 Transition Enable/Disable Control
* | | |0 = Capture function on channel 1 Disabled.
* | | |1 = Capture function on channel 1 Enabled.
* | | |When Enabled, Capture latched the PMW-counter and saved to CRL1 (PWM_CRL1[15:0]) for rising latch and CFL1 (PWM_CFL1[15:0]) for falling latch.
* | | |When Disabled, Capture does not update CRL1 (PWM_CRL1[15:0]) and CFL1 (PWM_CFL1[15:0]), and disable Channel 1 Interrupt.
* |[10] |CAPCH1PADEN|Capture Input Enable Control
* | | |0 = Disable the channel 1 input capture signal from corresponding multi-function pin.
* | | |1 = Enable the channel 1 input capture signal from corresponding multi-function pin.
* |[12] |CH0RFORDER|Channel 0 capture order control
* | | |Set this bit to determine whether the PWM_CRL0 or PWM_CFL0 is the first captured data transferred to memory through PDMA when PDMACAPMOD0 =2'b11.
* | | |0 = PWM_CFL0 is the first captured data to memory.
* | | |1 = PWM_CRL0 is the first captured data to memory.
* |[13] |CH01CASK |Cascade channel 0 and channel 1 PWM timer for capturing usage
* |[14] |CAPRELOADREN1|Reload CNR1 When CH1 Capture Rising Event Comes
* | | |0 = Rising capture reload for CH1 Disabled.
* | | |1 = Rising capture reload for CH1 Enabled.
* |[15] |CAPRELOADFEN1|Reload CNR1 When CH1 Capture Falling Event Coming
* | | |0 = Capture falling reload for CH1 Disabled.
* | | |1 = Capture falling reload for CH1 Enabled.
* |[16] |INV2 |Channel 2 Inverter ON/OFF
* | | |0 = Inverter OFF.
* | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
* |[17] |CAPCH2EN |Capture Channel 2 Transition Enable/Disable Control
* | | |0 = Capture function on channel 2 Disabled.
* | | |1 = Capture function on channel 2 Enabled.
* | | |When Enabled, Capture latched the PWM-timer value and saved to CRL2 (PWM_CRL2[15:0]) for rising latch and CFL2 (PWM_CFL2[15:0]) for falling latch.
* | | |When Disabled, Capture does not update CRL2 (PWM_CRL2[15:0]) and CFL2 (PWM_CFL2[15:0]), and disable Channel 2 Interrupt.
* |[18] |CAPCH2PADEN|Capture Input Enable Control
* | | |0 = Disable the channel 2 input capture signal from corresponding multi-function pin.
* | | |1 = Enable the channel 2 input capture signal from corresponding multi-function pin.
* |[19] |CH2PDMAEN |Channel 2 PDMA Enable Control
* | | |0 = Channel 2 PDMA function Disabled.
* | | |1 = Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory.
* |[21:20] |PDMACAPMOD2|Select CRL2 Or CFL2 For PDMA Transfer
* | | |00 = reserved.
* | | |01 = CRL2 will be transmitted.
* | | |10 = CFL2 will be transmitted.
* | | |11 = Both CRL2 and CFL2 will be transmitted.
* |[22] |CAPRELOADREN2|Reload CNR2 When CH2 Capture Rising Event Coming
* | | |0 = Rising capture reload for CH2 Disabled.
* | | |1 = Rising capture reload for CH2 Enabled.
* |[23] |CAPRELOADFEN2|Reload CNR2 When CH2 Capture Failing Event Coming
* | | |0 = Failing capture reload for CH2 Disabled.
* | | |1 = Failing capture reload for CH2 Enabled.
* |[24] |INV3 |Channel 3 Inverter ON/OFF
* | | |0 = Inverter OFF.
* | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
* |[25] |CAPCH3EN |Capture Channel 3 Transition Enable/Disable Control
* | | |0 = Capture function on channel 3 Disabled.
* | | |1 = Capture function on channel 3 Enabled.
* | | |When Enabled, Capture latched the PMW-timer and saved to CRL3 (PWM_CRL3[15:0]) for rising latch and CFL3 (PWM_CFL3[15:0]) for falling latch.
* | | |When Disabled, Capture does not update CRL3 (PWM_CRL3[15:0]) and CFL3 (PWM_CFL3[15:0]), and disable Channel 3 Interrupt.
* |[26] |CAPCH3PADEN|Capture Input Enable Control
* | | |0 = Disable the channel 3 input capture signal from corresponding multi-function pin.
* | | |1 = Enable the channel 3 input capture signal from corresponding multi-function pin.
* |[28] |CH2RFORDER|Channel 2 capture order control
* | | |Set this bit to determine whether the PWM_CRL2 or PWM_CFL2 is the first captured data transferred to memory through PDMA when PDMACAPMOD2 = 2'b11.
* | | |0 = PWM_CFL2 is the first captured data to memory.
* | | |1 = PWM_CRL2 is the first captured data to memory.
* |[29] |CH23CASK |Cascade channel 2 and channel 3 PWM counter for capturing usage
* |[30] |CAPRELOADREN3|Reload CNR3 When CH3 Rising Capture Event Comes
* | | |0 = Rising capture reload for CH3 Disabled.
* | | |1 = Rising capture reload for CH3 Enabled.
* |[31] |CAPRELOADFEN3|Reload CNR3 When CH3 Falling Capture Event Comes
* | | |0 = Falling capture reload for CH3 Disabled.
* | | |1 = Falling capture reload for CH3 Enabled.
*/
__IO uint32_t CAPCTL;
/**
* CAPINTEN
* ===================================================================================================
* Offset: 0x58 Capture interrupt enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRL_IE0 |Channel 0 Rising Latch Interrupt Enable ON/OFF
* | | |0 = Rising latch interrupt Disabled.
* | | |1 = Rising latch interrupt Enabled.
* | | |When Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt.
* |[1] |CFL_IE0 |Channel 0 Falling Latch Interrupt Enable ON/OFF
* | | |0 = Falling latch interrupt Disabled.
* | | |1 = Falling latch interrupt Enabled.
* | | |When Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt.
* |[8] |CRL_IE1 |Channel 1 Rising Latch Interrupt Enable Control
* | | |0 = Rising latch interrupt Disabled.
* | | |1 = Rising latch interrupt Enabled.
* | | |When Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt.
* |[9] |CFL_IE1 |Channel 1 Falling Latch Interrupt Enable Control
* | | |0 = Falling latch interrupt Disabled.
* | | |1 = Falling latch interrupt Enabled.
* | | |When Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt.
* |[16] |CRL_IE2 |Channel 2 Rising Latch Interrupt Enable ON/OFF
* | | |0 = Rising latch interrupt Disabled.
* | | |1 = Rising latch interrupt Enabled.
* | | |When Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt.
* |[17] |CFL_IE2 |Channel 2 Falling Latch Interrupt Enable ON/OFF
* | | |0 = Falling latch interrupt Disabled.
* | | |1 = Falling latch interrupt Enabled.
* | | |When Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt.
* |[24] |CRL_IE3 |Channel 3 Rising Latch Interrupt Enable ON/OFF
* | | |0 = Rising latch interrupt Disabled.
* | | |1 = Rising latch interrupt Enabled.
* | | |When Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt.
* |[25] |CFL_IE3 |Channel 3 Falling Latch Interrupt Enable ON/OFF
* | | |0 = Falling latch interrupt Disabled.
* | | |1 = Falling latch interrupt Enabled.
* | | |When Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt.
*/
__IO uint32_t CAPINTEN;
/**
* CAPINTSTS
* ===================================================================================================
* Offset: 0x5C Capture Interrupt Indication Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPIF0 |Capture0 Interrupt Indication Flag
* | | |If channel 0 rising latch interrupt (CRL_IE0, PWM_CAPINTEN[0]) is enabled, a rising transition occurs at input channel 0 will result in CAPIF0 to high; Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt (CFL_IE0, PWM_CAPINTEN[1]) is enabled.
* | | |This flag is cleared by software with a write 1 on it.
* |[1] |CRLI0 |PWM_CRL0 Latched Indicator Bit
* | | |When input channel 0 has a rising transition, PWM0_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
* |[2] |CFLI0 |PWM_CFL0 Latched Indicator Bit
* | | |When input channel 0 has a falling transition, PWM0_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
* |[3] |CAPOVR0 |Capture Rising Flag Over Run For Channel 0
* | | |This flag indicate CRL0 update faster than software reading it when it is set
* | | |This bit will be cleared automatically when user clears CRLI0 (PWM_CAPINTSTS[1]).
* |[4] |CAPOVF0 |Capture Falling Flag Over Run For Channel 0
* | | |This flag indicate CFL0 update faster than software read it when it is set
* | | |This bit will be cleared automatically when user clear CFLI0 (PWM_CAPINTSTS[2])
* |[8] |CAPIF1 |Capture1 Interrupt Indication Flag
* | | |If channel 1 rising latch interrupt (CRL_IE1, PWM_CAPINTEN[8]) is enabled, a rising transition occurs at input channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt (CFL_IE1, PWM_CAPINTEN[9]) is enabled.
* | | |This flag is cleared by software with a write 1 on it.
* |[9] |CRLI1 |PWM_CRL1 Latched Indicator Bit
* | | |When input channel 1 has a rising transition, PWM_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
* |[10] |CFLI1 |PWM_CFL1 Latched Indicator Bit
* | | |When input channel 1 has a falling transition, PWM_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
* |[11] |CAPOVR1 |Capture Rising Flag Over Run For Channel 1
* | | |This flag indicate CRL1 update faster than software reading it when it is set
* | | |This bit will be cleared automatically when user clear CRLI1 (PWM_CAPINTSTS[9])
* |[12] |CAPOVF1 |Capture Falling Flag Over Run For Channel 1
* | | |This flag indicate CFL1 update faster than software reading it when it is set
* | | |This bit will be cleared automatically when user clear CFLI1 (PWM_CAPINTSTS[10])
* |[16] |CAPIF2 |Capture2 Interrupt Indication Flag
* | | |If channel 2 rising latch interrupt (CRL_IE2, PWM_CAPINTEN[16]) is enabled, a rising transition occurs at input channel 2 will result in CAPIF2 to high; Similarly, a falling transition will cause CAPIF2 to be set high if channel 2 falling latch interrupt (CFL_IE2, PWM_CAPINTEN[17]) is enabled.
* | | |This flag is cleared by software with a write 1 on it.
* |[17] |CRLI2 |PWM_CRL2 Latched Indicator Bit
* | | |When input channel 2 has a rising transition, PWM0_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
* |[18] |CFLI2 |PWM_CFL2 Latched Indicator Bit
* | | |When input channel 2 has a falling transition, PWM0_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
* |[19] |CAPOVR2 |Capture Rising Flag Over Run For Channel 2
* | | |This flag indicate CRL2 update faster than software reading it when it is set
* | | |This bit will be cleared automatically when user clear CRLI2 (PWM_CAPINTSTS[17])
* |[20] |CAPOVF2 |Capture Falling Flag Over Run For Channel 2
* | | |This flag indicate CFL2 update faster than software reading it when it is set
* | | |This bit will be cleared automatically when user clear CFLI2 (PWM_CAPINTSTS[18])
* |[24] |CAPIF3 |Capture3 Interrupt Indication Flag
* | | |If channel 3 rising latch interrupt (CRL_IE3, PWM_CAPINTEN[24]) is enabled, a rising transition occurs at input channel 3 will result in CAPIF3 to high; Similarly, a falling transition will cause CAPIF3 to be set high if channel 3 falling latch interrupt (CFL_IE3, PWM_CAPINTEN[25]) is enabled.
* | | |This flag is cleared by software with a write 1 on it.
* |[25] |CRLI3 |PWM_CRL3 Latched Indicator Bit
* | | |When input channel 3 has a rising transition, PWM_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
* |[26] |CFLI3 |PWM_CFL3 Latched Indicator Bit
* | | |When input channel 3 has a falling transition, PWM_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
* |[27] |CAPOVR3 |Capture Rising Flag Over Run For Channel 3
* | | |This flag indicate CRL3update faster than software reading it when it is set
* | | |This bit will be cleared automatically when user clear CRLI3 (PWM_CAPINTSTS[25])
* |[28] |CAPOVF3 |Capture Falling Flag Over Run For Channel 3
* | | |This flag indicate CFL3 update faster than software reading it when it is set
* | | |This bit will be cleared automatically when user clear CFLI3 (PWM_CAPINTSTS[26])
*/
__IO uint32_t CAPINTSTS;
/**
* CRL0
* ===================================================================================================
* Offset: 0x60 Capture Rising Latch Register (Channel 0)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CRL |Capture Rising Latch Register
* | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
* |[31:16] |CRL_H |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
* | | |When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit,
*/
__I uint32_t CRL0;
/**
* CFL0
* ===================================================================================================
* Offset: 0x64 Capture Falling Latch Register (Channel 0)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CFL |Capture Falling Latch Register
* | | |Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
* |[31:16] |CFL_H |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
* | | |When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit,
*/
__I uint32_t CFL0;
/**
* CRL1
* ===================================================================================================
* Offset: 0x68 Capture Rising Latch Register (Channel 1)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CRL |Capture Rising Latch Register
* | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
* |[31:16] |CRL_H |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
* | | |When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit,
*/
__I uint32_t CRL1;
/**
* CFL1
* ===================================================================================================
* Offset: 0x6C Capture Falling Latch Register (Channel 1)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CFL |Capture Falling Latch Register
* | | |Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
* |[31:16] |CFL_H |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
* | | |When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit,
*/
__I uint32_t CFL1;
/**
* CRL2
* ===================================================================================================
* Offset: 0x70 Capture Rising Latch Register (Channel 2)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CRL |Capture Rising Latch Register
* | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
* |[31:16] |CRL_H |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
* | | |When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit,
*/
__I uint32_t CRL2;
/**
* CFL2
* ===================================================================================================
* Offset: 0x74 Capture Falling Latch Register (Channel 2)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CFL |Capture Falling Latch Register
* | | |Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
* |[31:16] |CFL_H |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
* | | |When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit,
*/
__I uint32_t CFL2;
/**
* CRL3
* ===================================================================================================
* Offset: 0x78 Capture Rising Latch Register (Channel 3)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CRL |Capture Rising Latch Register
* | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
* |[31:16] |CRL_H |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
* | | |When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit,
*/
__I uint32_t CRL3;
/**
* CFL3
* ===================================================================================================
* Offset: 0x7C Capture Falling Latch Register (Channel 3)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CFL |Capture Falling Latch Register
* | | |Latch the PWM counter when Channel 0/1/2/3 has Falling transition.
* |[31:16] |CFL_H |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
* | | |When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit,
*/
__I uint32_t CFL3;
/**
* PDMACH0
* ===================================================================================================
* Offset: 0x80 PDMA Channel 0 Captured Data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PDMACH01 |Captured Data Of Channel 0 When CH01CASK Is Disabled, It Is The Capturing Value(CFL0/CRL0) For Channel 0
* | | |When CH01CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 0
* |[15:8] |PDMACH02 |Captured Data Of Channel 0
* | | |When CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0
* | | |When CH01CASK is enabled, It is the second byte of 32 bit capturing data for channel 0
* |[23:16] |PDMACH03 |Captured Data Of Channel 0 When CH01CASK Is Disabled, This Byte Is 0
* | | |When CH01CASK is enabled, It is the third byte of 32 bit capturing data for channel 0
* |[31:24] |PDMACH04 |Captured Data Of Channel 0
* | | |When CH01CASK is disabled, this byte is 0
* | | |When CH01CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 0
*/
__I uint32_t PDMACH0;
/**
* PDMACH2
* ===================================================================================================
* Offset: 0x84 PDMA Channel 2 Captured Data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PDMACH21 |Captured Data Of Channel 2 When CH23CASK Is Disabled, It Is The Capturing Value(CFL2/CRL2) For Channel 2
* | | |When CH23CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 2
* |[15:8] |PDMACH22 |Captured Data Of Channel 2
* | | |When CH23CASK is disabled, it is the capturing value(CFL2/CRL2) for channel 2
* | | |When CH23CASK is enabled, It is the second byte of 32 bit capturing data for channel 2
* |[23:16] |PDMACH23 |Captured Data Of Channel 2
* | | |When CH23CASK is disabled, this byte is 0
* | | |When CH23CASK is enabled, It is the third byte of 32 bit capturing data for channel 2
* |[31:24] |PDMACH24 |Captured Data Of Channel 2
* | | |When CH23CASK is disabled, this byte is 0
* | | |When CH23CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 2
*/
__I uint32_t PDMACH2;
/**
* ADTRGEN
* ===================================================================================================
* Offset: 0x88 PWM Center-Triggered Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TRGCH0EN |PWM CH0 Center-Triggered Enable Control
* | | |0 = PWM CH0 center-triggered function Disabled.
* | | |1 = PWM CH0 center-triggered function Enabled.
* | | |Note: The center-triggered function is only valid in PWM center-aligned mode.
* |[1] |TRGCH1EN |PWM CH1 Center-Triggered Enable Control
* | | |0 = PWM CH1 center-triggered function Disabled.
* | | |1 = PWM CH1 center-triggered function Enabled.
* | | |Note: The center-triggered function is only valid in PWM center-aligned mode.
* |[2] |TRGCH2EN |PWM CH2 Center-Triggered Enable Control
* | | |0 = PWM CH2 center-triggered function Disabled.
* | | |1 = PWM CH2 center-triggered function Enabled.
* | | |Note: The center-triggered function is only valid in PWM center-aligned mode.
* |[3] |TRGCH3EN |PWM CH3 Center-Triggered Enable Control
* | | |0 = PWM CH3 center-triggered function Disabled.
* | | |1 = PWM CH3 center-triggered function Enabled.
* | | |Note: The center-triggered function is only valid in PWM center-aligned mode.
*/
__IO uint32_t ADTRGEN;
/**
* ADTRGSTS
* ===================================================================================================
* Offset: 0x8C PWM Center-Triggered Indication Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADTRG0Flag|PWM CH0 Center-Triggered Flag
* | | |0 = PWM CH0 has not crossed half of PWM period yet.
* | | |1 = PWM CH0 has crossed half of PWM period.
* | | |Note: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag
* |[1] |ADTRG1Flag|PWM CH1 Center-Triggered Flag
* | | |0 = PWM CH1 has not crossed half of PWM period yet.
* | | |1 = PWM CH1 has crossed half of PWM period.
* | | |Note: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag
* |[2] |ADTRG2Flag|PWM CH2 Center-Triggered Flag
* | | |0 = PWM CH2 has not crossed half of PWM period yet.
* | | |1 = PWM CH2 has crossed half of PWM period.
* | | |Note: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag
* |[3] |ADTRG3Flag|PWM CH3 Center-Triggered Flag
* | | |0 = PWM CH3 has not crossed half of PWM period yet.
* | | |1 = PWM CH3 has crossed half of PWM period.
* | | |Note: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag
*/
__IO uint32_t ADTRGSTS;
} PWM_T;
/**
@addtogroup PWM_CONST PWM Bit Field Definition
Constant Definitions for PWM Controller
@{ */
#define PWM_PRES_CP01_Pos (0) /*!< PWM PRES: CP01 Position */
#define PWM_PRES_CP01_Msk (0xfful << PWM_PRES_CP01_Pos) /*!< PWM PRES: CP01 Mask */
#define PWM_PRES_CP23_Pos (8) /*!< PWM PRES: CP23 Position */
#define PWM_PRES_CP23_Msk (0xfful << PWM_PRES_CP23_Pos) /*!< PWM PRES: CP23 Mask */
#define PWM_PRES_DZ01_Pos (16) /*!< PWM PRES: DZ01 Position */
#define PWM_PRES_DZ01_Msk (0xfful << PWM_PRES_DZ01_Pos) /*!< PWM PRES: DZ01 Mask */
#define PWM_PRES_DZ23_Pos (24) /*!< PWM PRES: DZ23 Position */
#define PWM_PRES_DZ23_Msk (0xfful << PWM_PRES_DZ23_Pos) /*!< PWM PRES: DZ23 Mask */
#define PWM_CLKSEL_CLKSEL0_Pos (0) /*!< PWM CLKSEL: CLKSEL0 Position */
#define PWM_CLKSEL_CLKSEL0_Msk (0x7ul << PWM_CLKSEL_CLKSEL0_Pos) /*!< PWM CLKSEL: CLKSEL0 Mask */
#define PWM_CLKSEL_CLKSEL1_Pos (4) /*!< PWM CLKSEL: CLKSEL1 Position */
#define PWM_CLKSEL_CLKSEL1_Msk (0x7ul << PWM_CLKSEL_CLKSEL1_Pos) /*!< PWM CLKSEL: CLKSEL1 Mask */
#define PWM_CLKSEL_CLKSEL2_Pos (8) /*!< PWM CLKSEL: CLKSEL2 Position */
#define PWM_CLKSEL_CLKSEL2_Msk (0x7ul << PWM_CLKSEL_CLKSEL2_Pos) /*!< PWM CLKSEL: CLKSEL2 Mask */
#define PWM_CLKSEL_CLKSEL3_Pos (12) /*!< PWM CLKSEL: CLKSEL3 Position */
#define PWM_CLKSEL_CLKSEL3_Msk (0x7ul << PWM_CLKSEL_CLKSEL3_Pos) /*!< PWM CLKSEL: CLKSEL3 Mask */
#define PWM_CTL_CH0EN_Pos (0) /*!< PWM CTL: CH0EN Position */
#define PWM_CTL_CH0EN_Msk (0x1ul << PWM_CTL_CH0EN_Pos) /*!< PWM CTL: CH0EN Mask */
#define PWM_CTL_CH0INV_Pos (2) /*!< PWM CTL: CH0INV Position */
#define PWM_CTL_CH0INV_Msk (0x1ul << PWM_CTL_CH0INV_Pos) /*!< PWM CTL: CH0INV Mask */
#define PWM_CTL_CH0MOD_Pos (3) /*!< PWM CTL: CH0MOD Position */
#define PWM_CTL_CH0MOD_Msk (0x1ul << PWM_CTL_CH0MOD_Pos) /*!< PWM CTL: CH0MOD Mask */
#define PWM_CTL_DZEN01_Pos (4) /*!< PWM CTL: DZEN01 Position */
#define PWM_CTL_DZEN01_Msk (0x1ul << PWM_CTL_DZEN01_Pos) /*!< PWM CTL: DZEN01 Mask */
#define PWM_CTL_DZEN23_Pos (5) /*!< PWM CTL: DZEN23 Position */
#define PWM_CTL_DZEN23_Msk (0x1ul << PWM_CTL_DZEN23_Pos) /*!< PWM CTL: DZEN23 Mask */
#define PWM_CTL_CH1EN_Pos (8) /*!< PWM CTL: CH1EN Position */
#define PWM_CTL_CH1EN_Msk (0x1ul << PWM_CTL_CH1EN_Pos) /*!< PWM CTL: CH1EN Mask */
#define PWM_CTL_CH1INV_Pos (10) /*!< PWM CTL: CH1INV Position */
#define PWM_CTL_CH1INV_Msk (0x1ul << PWM_CTL_CH1INV_Pos) /*!< PWM CTL: CH1INV Mask */
#define PWM_CTL_CH1MOD_Pos (11) /*!< PWM CTL: CH1MOD Position */
#define PWM_CTL_CH1MOD_Msk (0x1ul << PWM_CTL_CH1MOD_Pos) /*!< PWM CTL: CH1MOD Mask */
#define PWM_CTL_CH2EN_Pos (16) /*!< PWM CTL: CH2EN Position */
#define PWM_CTL_CH2EN_Msk (0x1ul << PWM_CTL_CH2EN_Pos) /*!< PWM CTL: CH2EN Mask */
#define PWM_CTL_CH2INV_Pos (18) /*!< PWM CTL: CH2INV Position */
#define PWM_CTL_CH2INV_Msk (0x1ul << PWM_CTL_CH2INV_Pos) /*!< PWM CTL: CH2INV Mask */
#define PWM_CTL_CH2MOD_Pos (19) /*!< PWM CTL: CH2MOD Position */
#define PWM_CTL_CH2MOD_Msk (0x1ul << PWM_CTL_CH2MOD_Pos) /*!< PWM CTL: CH2MOD Mask */
#define PWM_CTL_CH3EN_Pos (24) /*!< PWM CTL: CH3EN Position */
#define PWM_CTL_CH3EN_Msk (0x1ul << PWM_CTL_CH3EN_Pos) /*!< PWM CTL: CH3EN Mask */
#define PWM_CTL_CH3INV_Pos (26) /*!< PWM CTL: CH3INV Position */
#define PWM_CTL_CH3INV_Msk (0x1ul << PWM_CTL_CH3INV_Pos) /*!< PWM CTL: CH3INV Mask */
#define PWM_CTL_CH3MOD_Pos (27) /*!< PWM CTL: CH3MOD Position */
#define PWM_CTL_CH3MOD_Msk (0x1ul << PWM_CTL_CH3MOD_Pos) /*!< PWM CTL: CH3MOD Mask */
#define PWM_CTL_PWMTYPE01_Pos (30) /*!< PWM CTL: PWMTYPE01 Position */
#define PWM_CTL_PWMTYPE01_Msk (0x1ul << PWM_CTL_PWMTYPE01_Pos) /*!< PWM CTL: PWMTYPE01 Mask */
#define PWM_CTL_PWMTYPE23_Pos (31) /*!< PWM CTL: PWMTYPE23 Position */
#define PWM_CTL_PWMTYPE23_Msk (0x1ul << PWM_CTL_PWMTYPE23_Pos) /*!< PWM CTL: PWMTYPE23 Mask */
#define PWM_INTEN_TMIE0_Pos (0) /*!< PWM INTEN: TMIE0 Position */
#define PWM_INTEN_TMIE0_Msk (0x1ul << PWM_INTEN_TMIE0_Pos) /*!< PWM INTEN: TMIE0 Mask */
#define PWM_INTEN_TMIE1_Pos (1) /*!< PWM INTEN: TMIE1 Position */
#define PWM_INTEN_TMIE1_Msk (0x1ul << PWM_INTEN_TMIE1_Pos) /*!< PWM INTEN: TMIE1 Mask */
#define PWM_INTEN_TMIE2_Pos (2) /*!< PWM INTEN: TMIE2 Position */
#define PWM_INTEN_TMIE2_Msk (0x1ul << PWM_INTEN_TMIE2_Pos) /*!< PWM INTEN: TMIE2 Mask */
#define PWM_INTEN_TMIE3_Pos (3) /*!< PWM INTEN: TMIE3 Position */
#define PWM_INTEN_TMIE3_Msk (0x1ul << PWM_INTEN_TMIE3_Pos) /*!< PWM INTEN: TMIE3 Mask */
#define PWM_INTSTS_TMINT0_Pos (0) /*!< PWM INTSTS: TMINT0 Position */
#define PWM_INTSTS_TMINT0_Msk (0x1ul << PWM_INTSTS_TMINT0_Pos) /*!< PWM INTSTS: TMINT0 Mask */
#define PWM_INTSTS_TMINT1_Pos (1) /*!< PWM INTSTS: TMINT1 Position */
#define PWM_INTSTS_TMINT1_Msk (0x1ul << PWM_INTSTS_TMINT1_Pos) /*!< PWM INTSTS: TMINT1 Mask */
#define PWM_INTSTS_TMINT2_Pos (2) /*!< PWM INTSTS: TMINT2 Position */
#define PWM_INTSTS_TMINT2_Msk (0x1ul << PWM_INTSTS_TMINT2_Pos) /*!< PWM INTSTS: TMINT2 Mask */
#define PWM_INTSTS_TMINT3_Pos (3) /*!< PWM INTSTS: TMINT3 Position */
#define PWM_INTSTS_TMINT3_Msk (0x1ul << PWM_INTSTS_TMINT3_Pos) /*!< PWM INTSTS: TMINT3 Mask */
#define PWM_INTSTS_Duty0Syncflag_Pos (4) /*!< PWM INTSTS: Duty0Syncflag Position */
#define PWM_INTSTS_Duty0Syncflag_Msk (0x1ul << PWM_INTSTS_Duty0Syncflag_Pos) /*!< PWM INTSTS: Duty0Syncflag Mask */
#define PWM_INTSTS_Duty1Syncflag_Pos (5) /*!< PWM INTSTS: Duty1Syncflag Position */
#define PWM_INTSTS_Duty1Syncflag_Msk (0x1ul << PWM_INTSTS_Duty1Syncflag_Pos) /*!< PWM INTSTS: Duty1Syncflag Mask */
#define PWM_INTSTS_Duty2Syncflag_Pos (6) /*!< PWM INTSTS: Duty2Syncflag Position */
#define PWM_INTSTS_Duty2Syncflag_Msk (0x1ul << PWM_INTSTS_Duty2Syncflag_Pos) /*!< PWM INTSTS: Duty2Syncflag Mask */
#define PWM_INTSTS_Duty3Syncflag_Pos (7) /*!< PWM INTSTS: Duty3Syncflag Position */
#define PWM_INTSTS_Duty3Syncflag_Msk (0x1ul << PWM_INTSTS_Duty3Syncflag_Pos) /*!< PWM INTSTS: Duty3Syncflag Mask */
#define PWM_INTSTS_PresSyncFlag_Pos (8) /*!< PWM INTSTS: PresSyncFlag Position */
#define PWM_INTSTS_PresSyncFlag_Msk (0x1ul << PWM_INTSTS_PresSyncFlag_Pos) /*!< PWM INTSTS: PresSyncFlag Mask */
#define PWM_OE_CH0_OE_Pos (0) /*!< PWM OE: CH0_OE Position */
#define PWM_OE_CH0_OE_Msk (0x1ul << PWM_OE_CH0_OE_Pos) /*!< PWM OE: CH0_OE Mask */
#define PWM_OE_CH1_OE_Pos (1) /*!< PWM OE: CH1_OE Position */
#define PWM_OE_CH1_OE_Msk (0x1ul << PWM_OE_CH1_OE_Pos) /*!< PWM OE: CH1_OE Mask */
#define PWM_OE_CH2_OE_Pos (2) /*!< PWM OE: CH2_OE Position */
#define PWM_OE_CH2_OE_Msk (0x1ul << PWM_OE_CH2_OE_Pos) /*!< PWM OE: CH2_OE Mask */
#define PWM_OE_CH3_OE_Pos (3) /*!< PWM OE: CH3_OE Position */
#define PWM_OE_CH3_OE_Msk (0x1ul << PWM_OE_CH3_OE_Pos) /*!< PWM OE: CH3_OE Mask */
#define PWM_DUTY0_CN_Pos (0) /*!< PWM DUTY0: CN Position */
#define PWM_DUTY0_CN_Msk (0xfffful << PWM_DUTY0_CN_Pos) /*!< PWM DUTY0: CN Mask */
#define PWM_DUTY0_CM_Pos (16) /*!< PWM DUTY0: CM Position */
#define PWM_DUTY0_CM_Msk (0xfffful << PWM_DUTY0_CM_Pos) /*!< PWM DUTY0: CM Mask */
#define PWM_DATA0_DATA_Pos (0) /*!< PWM DATA0: DATA Position */
#define PWM_DATA0_DATA_Msk (0xfffful << PWM_DATA0_DATA_Pos) /*!< PWM DATA0: DATA Mask */
#define PWM_DATA0_DATA_H_Pos (16) /*!< PWM DATA0: DATA_H Position */
#define PWM_DATA0_DATA_H_Msk (0x7ffful << PWM_DATA0_DATA_H_Pos) /*!< PWM DATA0: DATA_H Mask */
#define PWM_DATA0_sync_Pos (31) /*!< PWM DATA0: sync Position */
#define PWM_DATA0_sync_Msk (0x1ul << PWM_DATA0_sync_Pos) /*!< PWM DATA0: sync Mask */
#define PWM_DUTY1_CN_Pos (0) /*!< PWM DUTY1: CN Position */
#define PWM_DUTY1_CN_Msk (0xfffful << PWM_DUTY1_CN_Pos) /*!< PWM DUTY1: CN Mask */
#define PWM_DUTY1_CM_Pos (16) /*!< PWM DUTY1: CM Position */
#define PWM_DUTY1_CM_Msk (0xfffful << PWM_DUTY1_CM_Pos) /*!< PWM DUTY1: CM Mask */
#define PWM_DATA1_DATA_Pos (0) /*!< PWM DATA1: DATA Position */
#define PWM_DATA1_DATA_Msk (0xfffful << PWM_DATA1_DATA_Pos) /*!< PWM DATA1: DATA Mask */
#define PWM_DATA1_DATA_H_Pos (16) /*!< PWM DATA1: DATA_H Position */
#define PWM_DATA1_DATA_H_Msk (0x7ffful << PWM_DATA1_DATA_H_Pos) /*!< PWM DATA1: DATA_H Mask */
#define PWM_DATA1_sync_Pos (31) /*!< PWM DATA1: sync Position */
#define PWM_DATA1_sync_Msk (0x1ul << PWM_DATA1_sync_Pos) /*!< PWM DATA1: sync Mask */
#define PWM_DUTY2_CN_Pos (0) /*!< PWM DUTY2: CN Position */
#define PWM_DUTY2_CN_Msk (0xfffful << PWM_DUTY2_CN_Pos) /*!< PWM DUTY2: CN Mask */
#define PWM_DUTY2_CM_Pos (16) /*!< PWM DUTY2: CM Position */
#define PWM_DUTY2_CM_Msk (0xfffful << PWM_DUTY2_CM_Pos) /*!< PWM DUTY2: CM Mask */
#define PWM_DATA2_DATA_Pos (0) /*!< PWM DATA2: DATA Position */
#define PWM_DATA2_DATA_Msk (0xfffful << PWM_DATA2_DATA_Pos) /*!< PWM DATA2: DATA Mask */
#define PWM_DATA2_DATA_H_Pos (16) /*!< PWM DATA2: DATA_H Position */
#define PWM_DATA2_DATA_H_Msk (0x7ffful << PWM_DATA2_DATA_H_Pos) /*!< PWM DATA2: DATA_H Mask */
#define PWM_DATA2_sync_Pos (31) /*!< PWM DATA2: sync Position */
#define PWM_DATA2_sync_Msk (0x1ul << PWM_DATA2_sync_Pos) /*!< PWM DATA2: sync Mask */
#define PWM_DUTY3_CN_Pos (0) /*!< PWM DUTY3: CN Position */
#define PWM_DUTY3_CN_Msk (0xfffful << PWM_DUTY3_CN_Pos) /*!< PWM DUTY3: CN Mask */
#define PWM_DUTY3_CM_Pos (16) /*!< PWM DUTY3: CM Position */
#define PWM_DUTY3_CM_Msk (0xfffful << PWM_DUTY3_CM_Pos) /*!< PWM DUTY3: CM Mask */
#define PWM_DATA3_DATA_Pos (0) /*!< PWM DATA3: DATA Position */
#define PWM_DATA3_DATA_Msk (0xfffful << PWM_DATA3_DATA_Pos) /*!< PWM DATA3: DATA Mask */
#define PWM_DATA3_DATA_H_Pos (16) /*!< PWM DATA3: DATA_H Position */
#define PWM_DATA3_DATA_H_Msk (0x7ffful << PWM_DATA3_DATA_H_Pos) /*!< PWM DATA3: DATA_H Mask */
#define PWM_DATA3_sync_Pos (31) /*!< PWM DATA3: sync Position */
#define PWM_DATA3_sync_Msk (0x1ul << PWM_DATA3_sync_Pos) /*!< PWM DATA3: sync Mask */
#define PWM_CAPCTL_INV0_Pos (0) /*!< PWM CAPCTL: INV0 Position */
#define PWM_CAPCTL_INV0_Msk (0x1ul << PWM_CAPCTL_INV0_Pos) /*!< PWM CAPCTL: INV0 Mask */
#define PWM_CAPCTL_CAPCH0EN_Pos (1) /*!< PWM CAPCTL: CAPCH0EN Position */
#define PWM_CAPCTL_CAPCH0EN_Msk (0x1ul << PWM_CAPCTL_CAPCH0EN_Pos) /*!< PWM CAPCTL: CAPCH0EN Mask */
#define PWM_CAPCTL_CAPCH0PADEN_Pos (2) /*!< PWM CAPCTL: CAPCH0PADEN Position */
#define PWM_CAPCTL_CAPCH0PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH0PADEN_Pos) /*!< PWM CAPCTL: CAPCH0PADEN Mask */
#define PWM_CAPCTL_CH0PDMAEN_Pos (3) /*!< PWM CAPCTL: CH0PDMAEN Position */
#define PWM_CAPCTL_CH0PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH0PDMAEN_Pos) /*!< PWM CAPCTL: CH0PDMAEN Mask */
#define PWM_CAPCTL_PDMACAPMOD0_Pos (4) /*!< PWM CAPCTL: PDMACAPMOD0 Position */
#define PWM_CAPCTL_PDMACAPMOD0_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD0_Pos) /*!< PWM CAPCTL: PDMACAPMOD0 Mask */
#define PWM_CAPCTL_CAPRELOADREN0_Pos (6) /*!< PWM CAPCTL: CAPRELOADREN0 Position */
#define PWM_CAPCTL_CAPRELOADREN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN0_Pos) /*!< PWM CAPCTL: CAPRELOADREN0 Mask */
#define PWM_CAPCTL_CAPRELOADFEN0_Pos (7) /*!< PWM CAPCTL: CAPRELOADFEN0 Position */
#define PWM_CAPCTL_CAPRELOADFEN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN0_Pos) /*!< PWM CAPCTL: CAPRELOADFEN0 Mask */
#define PWM_CAPCTL_INV1_Pos (8) /*!< PWM CAPCTL: INV1 Position */
#define PWM_CAPCTL_INV1_Msk (0x1ul << PWM_CAPCTL_INV1_Pos) /*!< PWM CAPCTL: INV1 Mask */
#define PWM_CAPCTL_CAPCH1EN_Pos (9) /*!< PWM CAPCTL: CAPCH1EN Position */
#define PWM_CAPCTL_CAPCH1EN_Msk (0x1ul << PWM_CAPCTL_CAPCH1EN_Pos) /*!< PWM CAPCTL: CAPCH1EN Mask */
#define PWM_CAPCTL_CAPCH1PADEN_Pos (10) /*!< PWM CAPCTL: CAPCH1PADEN Position */
#define PWM_CAPCTL_CAPCH1PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH1PADEN_Pos) /*!< PWM CAPCTL: CAPCH1PADEN Mask */
#define PWM_CAPCTL_CH0RFORDER_Pos (12) /*!< PWM CAPCTL: CH0RFORDER Position */
#define PWM_CAPCTL_CH0RFORDER_Msk (0x1ul << PWM_CAPCTL_CH0RFORDER_Pos) /*!< PWM CAPCTL: CH0RFORDER Mask */
#define PWM_CAPCTL_CH01CASK_Pos (13) /*!< PWM CAPCTL: CH01CASK Position */
#define PWM_CAPCTL_CH01CASK_Msk (0x1ul << PWM_CAPCTL_CH01CASK_Pos) /*!< PWM CAPCTL: CH01CASK Mask */
#define PWM_CAPCTL_CAPRELOADREN1_Pos (14) /*!< PWM CAPCTL: CAPRELOADREN1 Position */
#define PWM_CAPCTL_CAPRELOADREN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN1_Pos) /*!< PWM CAPCTL: CAPRELOADREN1 Mask */
#define PWM_CAPCTL_CAPRELOADFEN1_Pos (15) /*!< PWM CAPCTL: CAPRELOADFEN1 Position */
#define PWM_CAPCTL_CAPRELOADFEN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN1_Pos) /*!< PWM CAPCTL: CAPRELOADFEN1 Mask */
#define PWM_CAPCTL_INV2_Pos (16) /*!< PWM CAPCTL: INV2 Position */
#define PWM_CAPCTL_INV2_Msk (0x1ul << PWM_CAPCTL_INV2_Pos) /*!< PWM CAPCTL: INV2 Mask */
#define PWM_CAPCTL_CAPCH2EN_Pos (17) /*!< PWM CAPCTL: CAPCH2EN Position */
#define PWM_CAPCTL_CAPCH2EN_Msk (0x1ul << PWM_CAPCTL_CAPCH2EN_Pos) /*!< PWM CAPCTL: CAPCH2EN Mask */
#define PWM_CAPCTL_CAPCH2PADEN_Pos (18) /*!< PWM CAPCTL: CAPCH2PADEN Position */
#define PWM_CAPCTL_CAPCH2PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH2PADEN_Pos) /*!< PWM CAPCTL: CAPCH2PADEN Mask */
#define PWM_CAPCTL_CH2PDMAEN_Pos (19) /*!< PWM CAPCTL: CH2PDMAEN Position */
#define PWM_CAPCTL_CH2PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH2PDMAEN_Pos) /*!< PWM CAPCTL: CH2PDMAEN Mask */
#define PWM_CAPCTL_PDMACAPMOD2_Pos (20) /*!< PWM CAPCTL: PDMACAPMOD2 Position */
#define PWM_CAPCTL_PDMACAPMOD2_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD2_Pos) /*!< PWM CAPCTL: PDMACAPMOD2 Mask */
#define PWM_CAPCTL_CAPRELOADREN2_Pos (22) /*!< PWM CAPCTL: CAPRELOADREN2 Position */
#define PWM_CAPCTL_CAPRELOADREN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN2_Pos) /*!< PWM CAPCTL: CAPRELOADREN2 Mask */
#define PWM_CAPCTL_CAPRELOADFEN2_Pos (23) /*!< PWM CAPCTL: CAPRELOADFEN2 Position */
#define PWM_CAPCTL_CAPRELOADFEN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN2_Pos) /*!< PWM CAPCTL: CAPRELOADFEN2 Mask */
#define PWM_CAPCTL_INV3_Pos (24) /*!< PWM CAPCTL: INV3 Position */
#define PWM_CAPCTL_INV3_Msk (0x1ul << PWM_CAPCTL_INV3_Pos) /*!< PWM CAPCTL: INV3 Mask */
#define PWM_CAPCTL_CAPCH3EN_Pos (25) /*!< PWM CAPCTL: CAPCH3EN Position */
#define PWM_CAPCTL_CAPCH3EN_Msk (0x1ul << PWM_CAPCTL_CAPCH3EN_Pos) /*!< PWM CAPCTL: CAPCH3EN Mask */
#define PWM_CAPCTL_CAPCH3PADEN_Pos (26) /*!< PWM CAPCTL: CAPCH3PADEN Position */
#define PWM_CAPCTL_CAPCH3PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH3PADEN_Pos) /*!< PWM CAPCTL: CAPCH3PADEN Mask */
#define PWM_CAPCTL_CH2RFORDER_Pos (28) /*!< PWM CAPCTL: CH2RFORDER Position */
#define PWM_CAPCTL_CH2RFORDER_Msk (0x1ul << PWM_CAPCTL_CH2RFORDER_Pos) /*!< PWM CAPCTL: CH2RFORDER Mask */
#define PWM_CAPCTL_CH23CASK_Pos (29) /*!< PWM CAPCTL: CH23CASK Position */
#define PWM_CAPCTL_CH23CASK_Msk (0x1ul << PWM_CAPCTL_CH23CASK_Pos) /*!< PWM CAPCTL: CH23CASK Mask */
#define PWM_CAPCTL_CAPRELOADREN3_Pos (30) /*!< PWM CAPCTL: CAPRELOADREN3 Position */
#define PWM_CAPCTL_CAPRELOADREN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN3_Pos) /*!< PWM CAPCTL: CAPRELOADREN3 Mask */
#define PWM_CAPCTL_CAPRELOADFEN3_Pos (31) /*!< PWM CAPCTL: CAPRELOADFEN3 Position */
#define PWM_CAPCTL_CAPRELOADFEN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN3_Pos) /*!< PWM CAPCTL: CAPRELOADFEN3 Mask */
#define PWM_CAPINTEN_CRL_IE0_Pos (0) /*!< PWM CAPINTEN: CRL_IE0 Position */
#define PWM_CAPINTEN_CRL_IE0_Msk (0x1ul << PWM_CAPINTEN_CRL_IE0_Pos) /*!< PWM CAPINTEN: CRL_IE0 Mask */
#define PWM_CAPINTEN_CFL_IE0_Pos (1) /*!< PWM CAPINTEN: CFL_IE0 Position */
#define PWM_CAPINTEN_CFL_IE0_Msk (0x1ul << PWM_CAPINTEN_CFL_IE0_Pos) /*!< PWM CAPINTEN: CFL_IE0 Mask */
#define PWM_CAPINTEN_CRL_IE1_Pos (8) /*!< PWM CAPINTEN: CRL_IE1 Position */
#define PWM_CAPINTEN_CRL_IE1_Msk (0x1ul << PWM_CAPINTEN_CRL_IE1_Pos) /*!< PWM CAPINTEN: CRL_IE1 Mask */
#define PWM_CAPINTEN_CFL_IE1_Pos (9) /*!< PWM CAPINTEN: CFL_IE1 Position */
#define PWM_CAPINTEN_CFL_IE1_Msk (0x1ul << PWM_CAPINTEN_CFL_IE1_Pos) /*!< PWM CAPINTEN: CFL_IE1 Mask */
#define PWM_CAPINTEN_CRL_IE2_Pos (16) /*!< PWM CAPINTEN: CRL_IE2 Position */
#define PWM_CAPINTEN_CRL_IE2_Msk (0x1ul << PWM_CAPINTEN_CRL_IE2_Pos) /*!< PWM CAPINTEN: CRL_IE2 Mask */
#define PWM_CAPINTEN_CFL_IE2_Pos (17) /*!< PWM CAPINTEN: CFL_IE2 Position */
#define PWM_CAPINTEN_CFL_IE2_Msk (0x1ul << PWM_CAPINTEN_CFL_IE2_Pos) /*!< PWM CAPINTEN: CFL_IE2 Mask */
#define PWM_CAPINTEN_CRL_IE3_Pos (24) /*!< PWM CAPINTEN: CRL_IE3 Position */
#define PWM_CAPINTEN_CRL_IE3_Msk (0x1ul << PWM_CAPINTEN_CRL_IE3_Pos) /*!< PWM CAPINTEN: CRL_IE3 Mask */
#define PWM_CAPINTEN_CFL_IE3_Pos (25) /*!< PWM CAPINTEN: CFL_IE3 Position */
#define PWM_CAPINTEN_CFL_IE3_Msk (0x1ul << PWM_CAPINTEN_CFL_IE3_Pos) /*!< PWM CAPINTEN: CFL_IE3 Mask */
#define PWM_CAPINTSTS_CAPIF0_Pos (0) /*!< PWM CAPINTSTS: CAPIF0 Position */
#define PWM_CAPINTSTS_CAPIF0_Msk (0x1ul << PWM_CAPINTSTS_CAPIF0_Pos) /*!< PWM CAPINTSTS: CAPIF0 Mask */
#define PWM_CAPINTSTS_CRLI0_Pos (1) /*!< PWM CAPINTSTS: CRLI0 Position */
#define PWM_CAPINTSTS_CRLI0_Msk (0x1ul << PWM_CAPINTSTS_CRLI0_Pos) /*!< PWM CAPINTSTS: CRLI0 Mask */
#define PWM_CAPINTSTS_CFLI0_Pos (2) /*!< PWM CAPINTSTS: CFLI0 Position */
#define PWM_CAPINTSTS_CFLI0_Msk (0x1ul << PWM_CAPINTSTS_CFLI0_Pos) /*!< PWM CAPINTSTS: CFLI0 Mask */
#define PWM_CAPINTSTS_CAPOVR0_Pos (3) /*!< PWM CAPINTSTS: CAPOVR0 Position */
#define PWM_CAPINTSTS_CAPOVR0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR0_Pos) /*!< PWM CAPINTSTS: CAPOVR0 Mask */
#define PWM_CAPINTSTS_CAPOVF0_Pos (4) /*!< PWM CAPINTSTS: CAPOVF0 Position */
#define PWM_CAPINTSTS_CAPOVF0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF0_Pos) /*!< PWM CAPINTSTS: CAPOVF0 Mask */
#define PWM_CAPINTSTS_CAPIF1_Pos (8) /*!< PWM CAPINTSTS: CAPIF1 Position */
#define PWM_CAPINTSTS_CAPIF1_Msk (0x1ul << PWM_CAPINTSTS_CAPIF1_Pos) /*!< PWM CAPINTSTS: CAPIF1 Mask */
#define PWM_CAPINTSTS_CRLI1_Pos (9) /*!< PWM CAPINTSTS: CRLI1 Position */
#define PWM_CAPINTSTS_CRLI1_Msk (0x1ul << PWM_CAPINTSTS_CRLI1_Pos) /*!< PWM CAPINTSTS: CRLI1 Mask */
#define PWM_CAPINTSTS_CFLI1_Pos (10) /*!< PWM CAPINTSTS: CFLI1 Position */
#define PWM_CAPINTSTS_CFLI1_Msk (0x1ul << PWM_CAPINTSTS_CFLI1_Pos) /*!< PWM CAPINTSTS: CFLI1 Mask */
#define PWM_CAPINTSTS_CAPOVR1_Pos (11) /*!< PWM CAPINTSTS: CAPOVR1 Position */
#define PWM_CAPINTSTS_CAPOVR1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR1_Pos) /*!< PWM CAPINTSTS: CAPOVR1 Mask */
#define PWM_CAPINTSTS_CAPOVF1_Pos (12) /*!< PWM CAPINTSTS: CAPOVF1 Position */
#define PWM_CAPINTSTS_CAPOVF1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF1_Pos) /*!< PWM CAPINTSTS: CAPOVF1 Mask */
#define PWM_CAPINTSTS_CAPIF2_Pos (16) /*!< PWM CAPINTSTS: CAPIF2 Position */
#define PWM_CAPINTSTS_CAPIF2_Msk (0x1ul << PWM_CAPINTSTS_CAPIF2_Pos) /*!< PWM CAPINTSTS: CAPIF2 Mask */
#define PWM_CAPINTSTS_CRLI2_Pos (17) /*!< PWM CAPINTSTS: CRLI2 Position */
#define PWM_CAPINTSTS_CRLI2_Msk (0x1ul << PWM_CAPINTSTS_CRLI2_Pos) /*!< PWM CAPINTSTS: CRLI2 Mask */
#define PWM_CAPINTSTS_CFLI2_Pos (18) /*!< PWM CAPINTSTS: CFLI2 Position */
#define PWM_CAPINTSTS_CFLI2_Msk (0x1ul << PWM_CAPINTSTS_CFLI2_Pos) /*!< PWM CAPINTSTS: CFLI2 Mask */
#define PWM_CAPINTSTS_CAPOVR2_Pos (19) /*!< PWM CAPINTSTS: CAPOVR2 Position */
#define PWM_CAPINTSTS_CAPOVR2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR2_Pos) /*!< PWM CAPINTSTS: CAPOVR2 Mask */
#define PWM_CAPINTSTS_CAPOVF2_Pos (20) /*!< PWM CAPINTSTS: CAPOVF2 Position */
#define PWM_CAPINTSTS_CAPOVF2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF2_Pos) /*!< PWM CAPINTSTS: CAPOVF2 Mask */
#define PWM_CAPINTSTS_CAPIF3_Pos (24) /*!< PWM CAPINTSTS: CAPIF3 Position */
#define PWM_CAPINTSTS_CAPIF3_Msk (0x1ul << PWM_CAPINTSTS_CAPIF3_Pos) /*!< PWM CAPINTSTS: CAPIF3 Mask */
#define PWM_CAPINTSTS_CRLI3_Pos (25) /*!< PWM CAPINTSTS: CRLI3 Position */
#define PWM_CAPINTSTS_CRLI3_Msk (0x1ul << PWM_CAPINTSTS_CRLI3_Pos) /*!< PWM CAPINTSTS: CRLI3 Mask */
#define PWM_CAPINTSTS_CFLI3_Pos (26) /*!< PWM CAPINTSTS: CFLI3 Position */
#define PWM_CAPINTSTS_CFLI3_Msk (0x1ul << PWM_CAPINTSTS_CFLI3_Pos) /*!< PWM CAPINTSTS: CFLI3 Mask */
#define PWM_CAPINTSTS_CAPOVR3_Pos (27) /*!< PWM CAPINTSTS: CAPOVR3 Position */
#define PWM_CAPINTSTS_CAPOVR3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR3_Pos) /*!< PWM CAPINTSTS: CAPOVR3 Mask */
#define PWM_CAPINTSTS_CAPOVF3_Pos (28) /*!< PWM CAPINTSTS: CAPOVF3 Position */
#define PWM_CAPINTSTS_CAPOVF3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF3_Pos) /*!< PWM CAPINTSTS: CAPOVF3 Mask */
#define PWM_CRL0_CRL_Pos (0) /*!< PWM CRL0: CRL Position */
#define PWM_CRL0_CRL_Msk (0xfffful << PWM_CRL0_CRL_Pos) /*!< PWM CRL0: CRL Mask */
#define PWM_CRL0_CRL_H_Pos (16) /*!< PWM CRL0: CRL_H Position */
#define PWM_CRL0_CRL_H_Msk (0xfffful << PWM_CRL0_CRL_H_Pos) /*!< PWM CRL0: CRL_H Mask */
#define PWM_CFL0_CFL_Pos (0) /*!< PWM CFL0: CFL Position */
#define PWM_CFL0_CFL_Msk (0xfffful << PWM_CFL0_CFL_Pos) /*!< PWM CFL0: CFL Mask */
#define PWM_CFL0_CFL_H_Pos (16) /*!< PWM CFL0: CFL_H Position */
#define PWM_CFL0_CFL_H_Msk (0xfffful << PWM_CFL0_CFL_H_Pos) /*!< PWM CFL0: CFL_H Mask */
#define PWM_CRL1_CRL_Pos (0) /*!< PWM CRL1: CRL Position */
#define PWM_CRL1_CRL_Msk (0xfffful << PWM_CRL1_CRL_Pos) /*!< PWM CRL1: CRL Mask */
#define PWM_CRL1_CRL_H_Pos (16) /*!< PWM CRL1: CRL_H Position */
#define PWM_CRL1_CRL_H_Msk (0xfffful << PWM_CRL1_CRL_H_Pos) /*!< PWM CRL1: CRL_H Mask */
#define PWM_CFL1_CFL_Pos (0) /*!< PWM CFL1: CFL Position */
#define PWM_CFL1_CFL_Msk (0xfffful << PWM_CFL1_CFL_Pos) /*!< PWM CFL1: CFL Mask */
#define PWM_CFL1_CFL_H_Pos (16) /*!< PWM CFL1: CFL_H Position */
#define PWM_CFL1_CFL_H_Msk (0xfffful << PWM_CFL1_CFL_H_Pos) /*!< PWM CFL1: CFL_H Mask */
#define PWM_CRL2_CRL_Pos (0) /*!< PWM CRL2: CRL Position */
#define PWM_CRL2_CRL_Msk (0xfffful << PWM_CRL2_CRL_Pos) /*!< PWM CRL2: CRL Mask */
#define PWM_CRL2_CRL_H_Pos (16) /*!< PWM CRL2: CRL_H Position */
#define PWM_CRL2_CRL_H_Msk (0xfffful << PWM_CRL2_CRL_H_Pos) /*!< PWM CRL2: CRL_H Mask */
#define PWM_CFL2_CFL_Pos (0) /*!< PWM CFL2: CFL Position */
#define PWM_CFL2_CFL_Msk (0xfffful << PWM_CFL2_CFL_Pos) /*!< PWM CFL2: CFL Mask */
#define PWM_CFL2_CFL_H_Pos (16) /*!< PWM CFL2: CFL_H Position */
#define PWM_CFL2_CFL_H_Msk (0xfffful << PWM_CFL2_CFL_H_Pos) /*!< PWM CFL2: CFL_H Mask */
#define PWM_CRL3_CRL_Pos (0) /*!< PWM CRL3: CRL Position */
#define PWM_CRL3_CRL_Msk (0xfffful << PWM_CRL3_CRL_Pos) /*!< PWM CRL3: CRL Mask */
#define PWM_CRL3_CRL_H_Pos (16) /*!< PWM CRL3: CRL_H Position */
#define PWM_CRL3_CRL_H_Msk (0xfffful << PWM_CRL3_CRL_H_Pos) /*!< PWM CRL3: CRL_H Mask */
#define PWM_CFL3_CFL_Pos (0) /*!< PWM CFL3: CFL Position */
#define PWM_CFL3_CFL_Msk (0xfffful << PWM_CFL3_CFL_Pos) /*!< PWM CFL3: CFL Mask */
#define PWM_CFL3_CFL_H_Pos (16) /*!< PWM CFL3: CFL_H Position */
#define PWM_CFL3_CFL_H_Msk (0xfffful << PWM_CFL3_CFL_H_Pos) /*!< PWM CFL3: CFL_H Mask */
#define PWM_PDMACH0_PDMACH01_Pos (0) /*!< PWM PDMACH0: PDMACH01 Position */
#define PWM_PDMACH0_PDMACH01_Msk (0xfful << PWM_PDMACH0_PDMACH01_Pos) /*!< PWM PDMACH0: PDMACH01 Mask */
#define PWM_PDMACH0_PDMACH02_Pos (8) /*!< PWM PDMACH0: PDMACH02 Position */
#define PWM_PDMACH0_PDMACH02_Msk (0xfful << PWM_PDMACH0_PDMACH02_Pos) /*!< PWM PDMACH0: PDMACH02 Mask */
#define PWM_PDMACH0_PDMACH03_Pos (16) /*!< PWM PDMACH0: PDMACH03 Position */
#define PWM_PDMACH0_PDMACH03_Msk (0xfful << PWM_PDMACH0_PDMACH03_Pos) /*!< PWM PDMACH0: PDMACH03 Mask */
#define PWM_PDMACH0_PDMACH04_Pos (24) /*!< PWM PDMACH0: PDMACH04 Position */
#define PWM_PDMACH0_PDMACH04_Msk (0xfful << PWM_PDMACH0_PDMACH04_Pos) /*!< PWM PDMACH0: PDMACH04 Mask */
#define PWM_PDMACH2_PDMACH21_Pos (0) /*!< PWM PDMACH2: PDMACH21 Position */
#define PWM_PDMACH2_PDMACH21_Msk (0xfful << PWM_PDMACH2_PDMACH21_Pos) /*!< PWM PDMACH2: PDMACH21 Mask */
#define PWM_PDMACH2_PDMACH22_Pos (8) /*!< PWM PDMACH2: PDMACH22 Position */
#define PWM_PDMACH2_PDMACH22_Msk (0xfful << PWM_PDMACH2_PDMACH22_Pos) /*!< PWM PDMACH2: PDMACH22 Mask */
#define PWM_PDMACH2_PDMACH23_Pos (16) /*!< PWM PDMACH2: PDMACH23 Position */
#define PWM_PDMACH2_PDMACH23_Msk (0xfful << PWM_PDMACH2_PDMACH23_Pos) /*!< PWM PDMACH2: PDMACH23 Mask */
#define PWM_PDMACH2_PDMACH24_Pos (24) /*!< PWM PDMACH2: PDMACH24 Position */
#define PWM_PDMACH2_PDMACH24_Msk (0xfful << PWM_PDMACH2_PDMACH24_Pos) /*!< PWM PDMACH2: PDMACH24 Mask */
#define PWM_ADTRGEN_TRGCH0EN_Pos (0) /*!< PWM ADTRGEN: TRGCH0EN Position */
#define PWM_ADTRGEN_TRGCH0EN_Msk (0x1ul << PWM_ADTRGEN_TRGCH0EN_Pos) /*!< PWM ADTRGEN: TRGCH0EN Mask */
#define PWM_ADTRGEN_TRGCH1EN_Pos (1) /*!< PWM ADTRGEN: TRGCH1EN Position */
#define PWM_ADTRGEN_TRGCH1EN_Msk (0x1ul << PWM_ADTRGEN_TRGCH1EN_Pos) /*!< PWM ADTRGEN: TRGCH1EN Mask */
#define PWM_ADTRGEN_TRGCH2EN_Pos (2) /*!< PWM ADTRGEN: TRGCH2EN Position */
#define PWM_ADTRGEN_TRGCH2EN_Msk (0x1ul << PWM_ADTRGEN_TRGCH2EN_Pos) /*!< PWM ADTRGEN: TRGCH2EN Mask */
#define PWM_ADTRGEN_TRGCH3EN_Pos (3) /*!< PWM ADTRGEN: TRGCH3EN Position */
#define PWM_ADTRGEN_TRGCH3EN_Msk (0x1ul << PWM_ADTRGEN_TRGCH3EN_Pos) /*!< PWM ADTRGEN: TRGCH3EN Mask */
#define PWM_ADTRGSTS_ADTRG0Flag_Pos (0) /*!< PWM ADTRGSTS: ADTRG0Flag Position */
#define PWM_ADTRGSTS_ADTRG0Flag_Msk (0x1ul << PWM_ADTRGSTS_ADTRG0Flag_Pos) /*!< PWM ADTRGSTS: ADTRG0Flag Mask */
#define PWM_ADTRGSTS_ADTRG1Flag_Pos (1) /*!< PWM ADTRGSTS: ADTRG1Flag Position */
#define PWM_ADTRGSTS_ADTRG1Flag_Msk (0x1ul << PWM_ADTRGSTS_ADTRG1Flag_Pos) /*!< PWM ADTRGSTS: ADTRG1Flag Mask */
#define PWM_ADTRGSTS_ADTRG2Flag_Pos (2) /*!< PWM ADTRGSTS: ADTRG2Flag Position */
#define PWM_ADTRGSTS_ADTRG2Flag_Msk (0x1ul << PWM_ADTRGSTS_ADTRG2Flag_Pos) /*!< PWM ADTRGSTS: ADTRG2Flag Mask */
#define PWM_ADTRGSTS_ADTRG3Flag_Pos (3) /*!< PWM ADTRGSTS: ADTRG3Flag Position */
#define PWM_ADTRGSTS_ADTRG3Flag_Msk (0x1ul << PWM_ADTRGSTS_ADTRG3Flag_Pos) /*!< PWM ADTRGSTS: ADTRG3Flag Mask */
/**@}*/ /* PWM_CONST */
/**@}*/ /* end of PWM register group */
/*---------------------- Real Time Clock Controller -------------------------*/
/**
@addtogroup RTC Real Time Clock Controller(RTC)
Memory Mapped Structure for RTC Controller
@{ */
typedef struct {
/**
* INIR
* ===================================================================================================
* Offset: 0x00 RTC Initiation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACTIVE |RTC Active Status (Read Only)
* | | |0 = RTC is at reset state.
* | | |1 = RTC is at normal active state.
* |[31:1] |INIR |RTC Initiation (Write Only)
* | | |When RTC block is powered on, RTC is at reset state.
* | | |User has to write a number (0x a5eb1357) to INIR to make RTC leaving reset state.
* | | |Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
* | | |The INIR is a write-only field and read value will be always "0".
*/
__IO uint32_t INIR;
/**
* AER
* ===================================================================================================
* Offset: 0x04 RTC Access Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |AER |RTC Register Access Enable Password (Write Only)
* | | |Enable RTC access after write 0xA965. Otherwise disable RTC access.
* |[16] |ENF |RTC Register Access Enable Flag (Read Only)
* | | |0 = RTC register read/write disable.
* | | |1 = RTC register read/write enable.
* | | |This bit will be set after AER[15:0] register is load a 0xA965, and be clear automatically 512 RTC clocks or AER[15:0] is not 0xA965.
*/
__O uint32_t AER;
/**
* FCR
* ===================================================================================================
* Offset: 0x08 RTC Frequency Compensation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[21:0] |FCR |Frequency Compensation Register
* | | |FCR = 32768 * 0x200000 / (LXT period).
* | | |LXT period: the clock period (Hz) of LXT.
*/
__IO uint32_t FCR;
/**
* TLR
* ===================================================================================================
* Offset: 0x0C Time Loading Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |1SEC |1 Sec Time Digit (0~9)
* |[6:4] |10SEC |10 Sec Time Digit (0~5)
* |[11:8] |1MIN |1 Min Time Digit (0~9)
* |[14:12] |10MIN |10 Min Time Digit (0~5)
* |[19:16] |1HR |1 Hour Time Digit (0~9)
* |[21:20] |10HR |10 Hour Time Digit (0~2)
*/
__IO uint32_t TLR;
/**
* CLR
* ===================================================================================================
* Offset: 0x10 Calendar Loading Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |1DAY |1 Day Calendar Digit (0~9)
* |[5:4] |10DAY |10 Day Calendar Digit (0~3)
* |[11:8] |1MON |1 Month Calendar Digit (0~9)
* |[12] |10MON |10 Month Calendar Digit (0~1)
* |[19:16] |1YEAR |1 Year Calendar Digit (0~9)
* |[23:20] |10YEAR |10 Year Calendar Digit (0~9)
*/
__IO uint32_t CLR;
/**
* TSSR
* ===================================================================================================
* Offset: 0x14 Time Scale Selection Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |24hr_12hr |24-Hour / 12-Hour Mode Selection
* | | |It indicates that TLR and TAR are in 24-hour mode or 12-hour mode
* | | |0 = select 12-hour time scale with AM and PM indication.
* | | |1 = select 24-hour time scale.
*/
__IO uint32_t TSSR;
/**
* DWR
* ===================================================================================================
* Offset: 0x18 Day of the Week Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |DWR |Day Of The Week Register
* | | |000 = Sunday.
* | | |001 = Monday.
* | | |010 = Tuesday.
* | | |011 = Wednesday.
* | | |100 = Thursday.
* | | |101 = Friday.
* | | |110 = Saturday.
*/
__IO uint32_t DWR;
/**
* TAR
* ===================================================================================================
* Offset: 0x1C Time Alarm Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |1SEC |1 Sec Time Digit of Alarm Setting (0~9)
* |[6:4] |10SEC |10 Sec Time Digit of Alarm Setting (0~5)
* |[11:8] |1MIN |1 Min Time Digit of Alarm Setting (0~9)
* |[14:12] |10MIN |10 Min Time Digit of Alarm Setting (0~5)
* |[19:16] |1HR |1 Hour Time Digit of Alarm Setting (0~9)
* |[21:20] |10HR |10 Hour Time Digit of Alarm Setting (0~2)
*/
__IO uint32_t TAR;
/**
* CAR
* ===================================================================================================
* Offset: 0x20 Calendar Alarm Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |1DAY |1 Day Calendar Digit of Alarm Setting (0~9)
* |[5:4] |10DAY |10 Day Calendar Digit of Alarm Setting (0~3)
* |[11:8] |1MON |1 Month Calendar Digit of Alarm Setting (0~9)
* |[12] |10MON |10 Month Calendar Digit of Alarm Setting (0~1)
* |[19:16] |1YEAR |1 Year Calendar Digit of Alarm Setting (0~9)
* |[23:20] |10YEAR |10 Year Calendar Digit of Alarm Setting (0~9)
*/
__IO uint32_t CAR;
/**
* LIR
* ===================================================================================================
* Offset: 0x24 Leap Year Indicator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LIR |Leap Year Indication REGISTER (Read Only)
* | | |0 = This year is not a leap year.
* | | |1 = This year is leap year.
*/
__I uint32_t LIR;
/**
* RIER
* ===================================================================================================
* Offset: 0x28 RTC Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |AIER |Alarm Interrupt Enable
* | | |0 = RTC Alarm Interrupt is disabled.
* | | |1 = RTC Alarm Interrupt is enabled.
* |[1] |TIER |Time Tick Interrupt And Wake-Up By Tick Enable
* | | |0 = RTC Time Tick Interrupt is disabled.
* | | |1 = RTC Time Tick Interrupt is enabled.
* |[2] |SNOOPIER |Snooper Pin Event Detection Interrupt Enable
* | | |0 = Snooper Pin Event Detection Interrupt is disabled.
* | | |1 = Snooper Pin Event Detection Interrupt is enabled.
*/
__IO uint32_t RIER;
/**
* RIIR
* ===================================================================================================
* Offset: 0x2C RTC Interrupt Indication Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |AIS |RTC Alarm Interrupt Status
* | | |RTC unit will set AIS to high once the RTC real time counters TLR and CLR reach the alarm setting time registers TAR and CAR.
* | | |When this bit is set and AIER is also high, RTC will generate an interrupt to CPU.
* | | |This bit is cleared by writing "1" to it through software.
* | | |0 = RCT Alarm Interrupt condition never occurred.
* | | |1 = RTC Alarm Interrupt is requested if AIER (RTC_RIER[0])=1.
* |[1] |TIS |RTC Time Tick Interrupt Status
* | | |RTC unit will set this bit to high periodically in the period selected by TTR (RTC_TTR[2:0]).
* | | |When this bit is set and TIER (RTC_RIER[1]) is also high, RTC will generate an interrupt to CPU.
* | | |This bit is cleared by writing "1" to it through software.
* | | |0 = RCT Time Tick Interrupt condition never occurred.
* | | |1 = RTC Time Tick Interrupt is requested.
* |[2] |SNOOPIF |Snooper Pin Event Detection Interrupt Flag
* | | |When SNOOPEN is high and an event defined by SNOOPEDGE detected in snooper pin, this flag will be set.
* | | |While this bit is set and SNOOPIER (RTC_RIER[2]) is also high, RTC will generate an interrupt to CPU.
* | | |Write "1" to clear this bit to "0".
* | | |0 = Snooper pin event defined by SNOOPEDGE (RTC_SPRCTL[1]) never detected.
* | | |1 = Snooper pin event defined by SNOOPEDGE (RTC_SPRCTL[1]) detected.
*/
__IO uint32_t RIIR;
/**
* TTR
* ===================================================================================================
* Offset: 0x30 RTC Time Tick Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |TTR |Time Tick Register
* | | |The RTC time tick period for Periodic Time Tick Interrupt request.
* | | |000 = 1 tick/second.
* | | |001 = 1/2 tick/second.
* | | |010 = 1/4 tick/second.
* | | |011 = 1/8 tick/second.
* | | |100 = 1/16 tick/second.
* | | |101 = 1/32 tick/second.
* | | |110 = 1/64 tick/second.
* | | |111 = 1/128 tick/second.
* | | |Note: This register can be read back after the RTC is active by AER.
* |[3] |TWKE |RTC Timer Wake-Up CPU Function Enable
* | | |If TWKE is set before CPU enters power-down mode, when a RTC Time Tick, CPU will be wakened up by RTC unit.
* | | |0 = Time Tick wake-up CPU function Disabled.
* | | |1 = Wake-up function Enabled so that CPU can be waken up from Power-down mode by Time Tick.
* | | |Note: Tick timer setting follows the TTR ( RTC_TTR[2:0]) description.
*/
__IO uint32_t TTR;
uint32_t RESERVE0[2];
/**
* SPRCTL
* ===================================================================================================
* Offset: 0x3C RTC Spare Functional Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SNOOPEN |Snooper Pin Event Detection Enable
* | | |This bit enables the snooper pin event detection.
* | | |When this bit is set high and an event defined by SNOOPEDGE detected, the 20 spare registers will be cleared to "0" by hardware automatically.
* | | |And, the SNOOPIF will also be set.
* | | |In addition, RTC will also generate wake-up event to wake system up.
* | | |0 = Snooper pin event detection function Disabled.
* | | |1 = Snooper pin event detection function Enabled.
* |[1] |SNOOPEDGE |Snooper Active Edge Selection
* | | |This bit defines which edge of snooper pin will generate a snooper pin detected event to clear the 20 spare registers.
* | | |0 = Rising edge of snooper pin generates snooper pin detected event.
* | | |1 = Falling edge of snooper pin generates snooper pin detected event.
*/
__IO uint32_t SPRCTL;
/**
* SPR0
* ===================================================================================================
* Offset: 0x40 RTC Spare Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR0;
/**
* SPR1
* ===================================================================================================
* Offset: 0x44 RTC Spare Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR1;
/**
* SPR2
* ===================================================================================================
* Offset: 0x48 RTC Spare Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR2;
/**
* SPR3
* ===================================================================================================
* Offset: 0x4C RTC Spare Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR3;
/**
* SPR4
* ===================================================================================================
* Offset: 0x50 RTC Spare Register 4
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR4;
/**
* SPR5
* ===================================================================================================
* Offset: 0x54 RTC Spare Register 5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR5;
/**
* SPR6
* ===================================================================================================
* Offset: 0x58 RTC Spare Register 6
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR6;
/**
* SPR7
* ===================================================================================================
* Offset: 0x5C RTC Spare Register 7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR7;
/**
* SPR8
* ===================================================================================================
* Offset: 0x60 RTC Spare Register 8
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR8;
/**
* SPR9
* ===================================================================================================
* Offset: 0x64 RTC Spare Register 9
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR9;
/**
* SPR10
* ===================================================================================================
* Offset: 0x68 RTC Spare Register 10
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR10;
/**
* SPR11
* ===================================================================================================
* Offset: 0x6C RTC Spare Register 11
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR11;
/**
* SPR12
* ===================================================================================================
* Offset: 0x70 RTC Spare Register 12
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR12;
/**
* SPR13
* ===================================================================================================
* Offset: 0x74 RTC Spare Register 13
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR13;
/**
* SPR14
* ===================================================================================================
* Offset: 0x78 RTC Spare Register 14
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR14;
/**
* SPR15
* ===================================================================================================
* Offset: 0x7C RTC Spare Register 15
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR15;
/**
* SPR16
* ===================================================================================================
* Offset: 0x80 RTC Spare Register 16
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR16;
/**
* SPR17
* ===================================================================================================
* Offset: 0x84 RTC Spare Register 17
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR17;
/**
* SPR18
* ===================================================================================================
* Offset: 0x88 RTC Spare Register 18
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR18;
/**
* SPR19
* ===================================================================================================
* Offset: 0x8C RTC Spare Register 19
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |SPARE
* | | |This field is used to store back-up information defined by software.
* | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
*/
__IO uint32_t SPR19;
} RTC_T;
/**
@addtogroup RTC_CONST RTC Bit Field Definition
Constant Definitions for RTC Controller
@{ */
#define RTC_INIR_ACTIVE_Pos (0) /*!< RTC INIR: ACTIVE Position */
#define RTC_INIR_ACTIVE_Msk (0x1ul << RTC_INIR_ACTIVE_Pos) /*!< RTC INIR: ACTIVE Mask */
#define RTC_INIR_INIR_Pos (0) /*!< RTC INIR: INIR Position */
#define RTC_INIR_INIR_Msk (0xfffffffful << RTC_INIR_INIR_Pos) /*!< RTC INIR: INIR Mask */
#define RTC_AER_AER_Pos (0) /*!< RTC AER: AER Position */
#define RTC_AER_AER_Msk (0xfffful << RTC_AER_AER_Pos) /*!< RTC AER: AER Mask */
#define RTC_AER_ENF_Pos (16) /*!< RTC AER: ENF Position */
#define RTC_AER_ENF_Msk (0x1ul << RTC_AER_ENF_Pos) /*!< RTC AER: ENF Mask */
#define RTC_FCR_FCR_Pos (0) /*!< RTC FCR: FCR Position */
#define RTC_FCR_FCR_Msk (0x3ffffful << RTC_FCR_FCR_Pos) /*!< RTC FCR: FCR Mask */
#define RTC_TLR_1SEC_Pos (0) /*!< RTC TLR: 1SEC Position */
#define RTC_TLR_1SEC_Msk (0xful << RTC_TLR_1SEC_Pos) /*!< RTC TLR: 1SEC Mask */
#define RTC_TLR_10SEC_Pos (4) /*!< RTC TLR: 10SEC Position */
#define RTC_TLR_10SEC_Msk (0x7ul << RTC_TLR_10SEC_Pos) /*!< RTC TLR: 10SEC Mask */
#define RTC_TLR_1MIN_Pos (8) /*!< RTC TLR: 1MIN Position */
#define RTC_TLR_1MIN_Msk (0xful << RTC_TLR_1MIN_Pos) /*!< RTC TLR: 1MIN Mask */
#define RTC_TLR_10MIN_Pos (12) /*!< RTC TLR: 10MIN Position */
#define RTC_TLR_10MIN_Msk (0x7ul << RTC_TLR_10MIN_Pos) /*!< RTC TLR: 10MIN Mask */
#define RTC_TLR_1HR_Pos (16) /*!< RTC TLR: 1HR Position */
#define RTC_TLR_1HR_Msk (0xful << RTC_TLR_1HR_Pos) /*!< RTC TLR: 1HR Mask */
#define RTC_TLR_10HR_Pos (20) /*!< RTC TLR: 10HR Position */
#define RTC_TLR_10HR_Msk (0x3ul << RTC_TLR_10HR_Pos) /*!< RTC TLR: 10HR Mask */
#define RTC_CLR_1DAY_Pos (0) /*!< RTC CLR: 1DAY Position */
#define RTC_CLR_1DAY_Msk (0xful << RTC_CLR_1DAY_Pos) /*!< RTC CLR: 1DAY Mask */
#define RTC_CLR_10DAY_Pos (4) /*!< RTC CLR: 10DAY Position */
#define RTC_CLR_10DAY_Msk (0x3ul << RTC_CLR_10DAY_Pos) /*!< RTC CLR: 10DAY Mask */
#define RTC_CLR_1MON_Pos (8) /*!< RTC CLR: 1MON Position */
#define RTC_CLR_1MON_Msk (0xful << RTC_CLR_1MON_Pos) /*!< RTC CLR: 1MON Mask */
#define RTC_CLR_10MON_Pos (12) /*!< RTC CLR: 10MON Position */
#define RTC_CLR_10MON_Msk (0x1ul << RTC_CLR_10MON_Pos) /*!< RTC CLR: 10MON Mask */
#define RTC_CLR_1YEAR_Pos (16) /*!< RTC CLR: 1YEAR Position */
#define RTC_CLR_1YEAR_Msk (0xful << RTC_CLR_1YEAR_Pos) /*!< RTC CLR: 1YEAR Mask */
#define RTC_CLR_10YEAR_Pos (20) /*!< RTC CLR: 10YEAR Position */
#define RTC_CLR_10YEAR_Msk (0xful << RTC_CLR_10YEAR_Pos) /*!< RTC CLR: 10YEAR Mask */
#define RTC_TSSR_24H_12H_Pos (0) /*!< RTC TSSR: 24hr_12hr Position */
#define RTC_TSSR_24H_12H_Msk (0x1ul << RTC_TSSR_24H_12H_Pos) /*!< RTC TSSR: 24hr_12hr Mask */
#define RTC_DWR_DWR_Pos (0) /*!< RTC DWR: DWR Position */
#define RTC_DWR_DWR_Msk (0x7ul << RTC_DWR_DWR_Pos) /*!< RTC DWR: DWR Mask */
#define RTC_TAR_1SEC_Pos (0) /*!< RTC TAR: 1SEC Position */
#define RTC_TAR_1SEC_Msk (0xful << RTC_TAR_1SEC_Pos) /*!< RTC TAR: 1SEC Mask */
#define RTC_TAR_10SEC_Pos (4) /*!< RTC TAR: 10SEC Position */
#define RTC_TAR_10SEC_Msk (0x7ul << RTC_TAR_10SEC_Pos) /*!< RTC TAR: 10SEC Mask */
#define RTC_TAR_1MIN_Pos (8) /*!< RTC TAR: 1MIN Position */
#define RTC_TAR_1MIN_Msk (0xful << RTC_TAR_1MIN_Pos) /*!< RTC TAR: 1MIN Mask */
#define RTC_TAR_10MIN_Pos (12) /*!< RTC TAR: 10MIN Position */
#define RTC_TAR_10MIN_Msk (0x7ul << RTC_TAR_10MIN_Pos) /*!< RTC TAR: 10MIN Mask */
#define RTC_TAR_1HR_Pos (16) /*!< RTC TAR: 1HR Position */
#define RTC_TAR_1HR_Msk (0xful << RTC_TAR_1HR_Pos) /*!< RTC TAR: 1HR Mask */
#define RTC_TAR_10HR_Pos (20) /*!< RTC TAR: 10HR Position */
#define RTC_TAR_10HR_Msk (0x3ul << RTC_TAR_10HR_Pos) /*!< RTC TAR: 10HR Mask */
#define RTC_CAR_1DAY_Pos (0) /*!< RTC CAR: 1DAY Position */
#define RTC_CAR_1DAY_Msk (0xful << RTC_CAR_1DAY_Pos) /*!< RTC CAR: 1DAY Mask */
#define RTC_CAR_10DAY_Pos (4) /*!< RTC CAR: 10DAY Position */
#define RTC_CAR_10DAY_Msk (0x3ul << RTC_CAR_10DAY_Pos) /*!< RTC CAR: 10DAY Mask */
#define RTC_CAR_1MON_Pos (8) /*!< RTC CAR: 1MON Position */
#define RTC_CAR_1MON_Msk (0xful << RTC_CAR_1MON_Pos) /*!< RTC CAR: 1MON Mask */
#define RTC_CAR_10MON_Pos (12) /*!< RTC CAR: 10MON Position */
#define RTC_CAR_10MON_Msk (0x1ul << RTC_CAR_10MON_Pos) /*!< RTC CAR: 10MON Mask */
#define RTC_CAR_1YEAR_Pos (16) /*!< RTC CAR: 1YEAR Position */
#define RTC_CAR_1YEAR_Msk (0xful << RTC_CAR_1YEAR_Pos) /*!< RTC CAR: 1YEAR Mask */
#define RTC_CAR_10YEAR_Pos (20) /*!< RTC CAR: 10YEAR Position */
#define RTC_CAR_10YEAR_Msk (0xful << RTC_CAR_10YEAR_Pos) /*!< RTC CAR: 10YEAR Mask */
#define RTC_LIR_LIR_Pos (0) /*!< RTC LIR: LIR Position */
#define RTC_LIR_LIR_Msk (0x1ul << RTC_LIR_LIR_Pos) /*!< RTC LIR: LIR Mask */
#define RTC_RIER_AIER_Pos (0) /*!< RTC RIER: AIER Position */
#define RTC_RIER_AIER_Msk (0x1ul << RTC_RIER_AIER_Pos) /*!< RTC RIER: AIER Mask */
#define RTC_RIER_TIER_Pos (1) /*!< RTC RIER: TIER Position */
#define RTC_RIER_TIER_Msk (0x1ul << RTC_RIER_TIER_Pos) /*!< RTC RIER: TIER Mask */
#define RTC_RIER_SNOOPIER_Pos (2) /*!< RTC RIER: SNOOPIER Position */
#define RTC_RIER_SNOOPIER_Msk (0x1ul << RTC_RIER_SNOOPIER_Pos) /*!< RTC RIER: SNOOPIER Mask */
#define RTC_RIIR_AIF_Pos (0) /*!< RTC RIIR: AIF Position */
#define RTC_RIIR_AIF_Msk (0x1ul << RTC_RIIR_AIF_Pos) /*!< RTC RIIR: AIF Mask */
#define RTC_RIIR_TIF_Pos (1) /*!< RTC RIIR: TIF Position */
#define RTC_RIIR_TIF_Msk (0x1ul << RTC_RIIR_TIF_Pos) /*!< RTC RIIR: TIF Mask */
#define RTC_RIIR_SNOOPIF_Pos (2) /*!< RTC RIIR: SNOOPIF Position */
#define RTC_RIIR_SNOOPIF_Msk (0x1ul << RTC_RIIR_SNOOPIF_Pos) /*!< RTC RIIR: SNOOPIF Mask */
#define RTC_TTR_TTR_Pos (0) /*!< RTC TTR: TTR Position */
#define RTC_TTR_TTR_Msk (0x7ul << RTC_TTR_TTR_Pos) /*!< RTC TTR: TTR Mask */
#define RTC_TTR_TWKE_Pos (3) /*!< RTC TTR: TWKE Position */
#define RTC_TTR_TWKE_Msk (0x1ul << RTC_TTR_TWKE_Pos) /*!< RTC TTR: TWKE Mask */
#define RTC_SPRCTL_SNOOPEN_Pos (0) /*!< RTC SPRCTL: SNOOPEN Position */
#define RTC_SPRCTL_SNOOPEN_Msk (0x1ul << RTC_SPRCTL_SNOOPEN_Pos) /*!< RTC SPRCTL: SNOOPEN Mask */
#define RTC_SPRCTL_SNOOPEDGE_Pos (1) /*!< RTC SPRCTL: SNOOPEDGE Position */
#define RTC_SPRCTL_SNOOPEDGE_Msk (0x1ul << RTC_SPRCTL_SNOOPEDGE_Pos) /*!< RTC SPRCTL: SNOOPEDGE Mask */
#define RTC_SPR0_SPARE_Pos (0) /*!< RTC SPR0: SPARE Position */
#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC SPR0: SPARE Mask */
#define RTC_SPR1_SPARE_Pos (0) /*!< RTC SPR1: SPARE Position */
#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC SPR1: SPARE Mask */
#define RTC_SPR2_SPARE_Pos (0) /*!< RTC SPR2: SPARE Position */
#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC SPR2: SPARE Mask */
#define RTC_SPR3_SPARE_Pos (0) /*!< RTC SPR3: SPARE Position */
#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC SPR3: SPARE Mask */
#define RTC_SPR4_SPARE_Pos (0) /*!< RTC SPR4: SPARE Position */
#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC SPR4: SPARE Mask */
#define RTC_SPR5_SPARE_Pos (0) /*!< RTC SPR5: SPARE Position */
#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC SPR5: SPARE Mask */
#define RTC_SPR6_SPARE_Pos (0) /*!< RTC SPR6: SPARE Position */
#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC SPR6: SPARE Mask */
#define RTC_SPR7_SPARE_Pos (0) /*!< RTC SPR7: SPARE Position */
#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC SPR7: SPARE Mask */
#define RTC_SPR8_SPARE_Pos (0) /*!< RTC SPR8: SPARE Position */
#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC SPR8: SPARE Mask */
#define RTC_SPR9_SPARE_Pos (0) /*!< RTC SPR9: SPARE Position */
#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC SPR9: SPARE Mask */
#define RTC_SPR10_SPARE_Pos (0) /*!< RTC SPR10: SPARE Position */
#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC SPR10: SPARE Mask */
#define RTC_SPR11_SPARE_Pos (0) /*!< RTC SPR11: SPARE Position */
#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC SPR11: SPARE Mask */
#define RTC_SPR12_SPARE_Pos (0) /*!< RTC SPR12: SPARE Position */
#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC SPR12: SPARE Mask */
#define RTC_SPR13_SPARE_Pos (0) /*!< RTC SPR13: SPARE Position */
#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC SPR13: SPARE Mask */
#define RTC_SPR14_SPARE_Pos (0) /*!< RTC SPR14: SPARE Position */
#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC SPR14: SPARE Mask */
#define RTC_SPR15_SPARE_Pos (0) /*!< RTC SPR15: SPARE Position */
#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC SPR15: SPARE Mask */
#define RTC_SPR16_SPARE_Pos (0) /*!< RTC SPR16: SPARE Position */
#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC SPR16: SPARE Mask */
#define RTC_SPR17_SPARE_Pos (0) /*!< RTC SPR17: SPARE Position */
#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC SPR17: SPARE Mask */
#define RTC_SPR18_SPARE_Pos (0) /*!< RTC SPR18: SPARE Position */
#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC SPR18: SPARE Mask */
#define RTC_SPR19_SPARE_Pos (0) /*!< RTC SPR19: SPARE Position */
#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC SPR19: SPARE Mask */
/**@}*/ /* RTC_CONST */
/**@}*/ /* end of RTC register group */
/*---------------------- Smart Card Host Interface Controller -------------------------*/
/**
@addtogroup SC Smart Card Host Interface Controller(SC)
Memory Mapped Structure for SC Controller
@{ */
typedef struct {
union {
/**
* RBR
* ===================================================================================================
* Offset: 0x00 SC Receive Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |RBR |Receiving Buffer
* | | |By reading this register, the SC Controller will return an 8-bit data received from RX pin (LSB first).
*/
__I uint32_t RBR;
/**
* THR
* ===================================================================================================
* Offset: 0x00 SC Transmit Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |THR |Transmit Buffer
* | | |By writing to this register, the SC sends out an 8-bit data through the TX pin (LSB first).
*/
__O uint32_t THR;
};
/**
* CTL
* ===================================================================================================
* Offset: 0x04 SC Control Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SC_CEN |SC Engine Enable
* | | |Set this bit to "1" to enable SC operation.
* | | |If this bit is cleared, SC will force all transition to IDLE state.
* |[1] |DIS_RX |RX Transition Disable
* | | |0 = Receiver Enabled.
* | | |1 = Receiver Disabled.
* |[2] |DIS_TX |TX Transition Disable
* | | |0 = Transceiver Enabled.
* | | |1 = Transceiver Disabled.
* |[3] |AUTO_CON_EN|Auto Convention Enable
* | | |0 = Auto-convention Disabled.
* | | |1 = Auto-convention Enabled.
* | | |When hardware receives TS in answer to reset state and the TS is direct convention, CON_SEL will be set to 00 automatically, otherwise if the TS is inverse convention, CON_SEL will be set to 11.
* | | |If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F.
* | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the SC_CTL[CON_SEL] register automatically.
* | | |If the first data is not 0x3B or 0x3F, hardware will generate an interrupt INT_ACON_ERR(if SC_IER [ACON_ERR_IE = "1"] to CPU.
* |[5:4] |CON_SEL |Convention Selection
* | | |00 = Direct convention.
* | | |01 = Reserved.
* | | |10 = Reserved.
* | | |11 = Inverse convention.
* | | |Note: If AUTO_CON_EN is enabled, this field must be ignored.
* |[7:6] |RX_FTRI_LEV|RX Buffer Trigger Level
* | | |When the number of bytes in the receiving buffer equals the RX_FTRI_LEV, the RDA_IF will be set (if IER [RDA_IEN] is enabled, an interrupt will be generated).
* | | |00 = INTR_RDA Trigger Level 1 byte.
* | | |01 = INTR_RDA Trigger Level 2 bytes.
* | | |10 = INTR_RDA Trigger Level 3 bytes.
* | | |11 = Reserved.
* |[12:8] |BGT |Block Guard Time (BGT)
* | | |This field indicates the counter for block guard time.
* | | |According to ISO7816-3, in T=0 mode, software must fill 15 (real block guard time = 16) to this field and in T=1 mode software must fill 21 (real block guard time = 22) to it.
* | | |In TX mode, hardware will auto hold off first character until BGT has elapsed regardless of the TX data.
* | | |In RX mode, software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing.
* | | |If the incoming data timing less than BGT, an interrupt will be generated.
* | | |Note: The real block guard time is BGT + 1.
* |[14:13] |TMR_SEL |Timer Selection
* | | |00 = Disable all internal timer function.
* | | |01 = Enable internal 24 bit timer.
* | | |Software can configure it by setting SC_TMR0 [23:0].
* | | |SC_TMR1 and SC_TMR2 will be ignored in this mode.
* | | |10 = Enable internal 24 bit timer and 8 bit internal timer.
* | | |Software can configure the 24 bit timer by setting SC_TMR0 [23:0] and configure the 8 bit timer by setting SC_TMR1 [7:0].
* | | |SC_TMR2 will be ignored in this mode.
* | | |11 = Enable internal 24 bit timer and two 8 bit timers.
* | | |Software can configure them by setting SC_TMR0 [23:0], SC_TMR1 [7:0] and SC_TMR2 [7:0].
* |[15] |SLEN |Stop Bit Length
* | | |This field indicates the length of stop bit.
* | | |0 = The stop bit length is 2 ETU.
* | | |1 = The stop bit length is 1 ETU.
* | | |Note: The default stop bit length is 2.
* |[18:16] |RX_ERETRY |RX Error Retry Register
* | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred.
* | | |Note1: The real maximum retry number is RX_ERETRY + 1, so 8 is the maximum retry number.
* | | |Note2: This field can not be changed when RX_ERETRY_EN enabled.
* | | |The change flow is to disable RX_ETRTRY_EN first and then fill new retry value.
* |[19] |RX_ERETRY_EN|RX Error Retry Enable Register
* | | |This bit enables receiver retry function when parity error has occurred.
* | | |0 = RX error retry function Disabled.
* | | |1 = RX error retry function Enabled.
* | | |Note: User must fill RX_ERETRY value before enabling this bit.
* |[22:20] |TX_ERETRY |TX Error Retry Register
* | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
* | | |Note1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number.
* | | |Note2: This field can not be changed when TX_ERETRY_EN enabled.
* | | |The change flow is to disable TX_ETRTRY_EN first and then fill new retry value.
* |[23] |TX_ERETRY_EN|TX Error Retry Enable Register
* | | |This bit enables transmitter retry function when parity error has occurred.
* | | |0 = TX error retry function Disabled.
* | | |1 = TX error retry function Enabled.
* | | |Note: User must fill TX_ERETRY value before enabling this bit.
* |[25:24] |CD_DEB_SEL|Card Detect De-Bounce Select Register
* | | |This field indicates the card detect de-bounce selection.
* | | |This field indicates the card detect de-bounce selection.
* | | |00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks.
* | | |01 = De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks.
* | | |10 = De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks.
* | | |11 = De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks.
*/
__IO uint32_t CTL;
/**
* ALTCTL
* ===================================================================================================
* Offset: 0x08 SC Alternate Control Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TX_RST |TX Software Reset
* | | |When TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the TX internal state machine and pointers.
* | | |Note: This bit will be auto cleared and needs at least 3 SC engine clock cycles.
* |[1] |RX_RST |RX Software Reset
* | | |When RX_RST is set, all the bytes in the receiver buffer and RX internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the RX internal state machine and pointers.
* | | |Note: This bit will be auto cleared and needs at least 3 SC engine clock cycles.
* |[2] |DACT_EN |Deactivation Sequence Generator Enable
* | | |This bit enables SC controller to initiate the card by deactivation sequence
* | | |0 = No effect.
* | | |1 = Deactivation sequence generator Enabled.
* | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to "1".
* | | |Note2: This field will be cleared by TX_RST and RX_RST.
* | | |So don't fill this bit, TX_RST, and RX_RST at the same time.
* | | |Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
* |[3] |ACT_EN |Activation Sequence Generator Enable
* | | |This bit enables SC controller to initiate the card by activation sequence
* | | |0 = No effect.
* | | |1 = Activation sequence generator Enabled.
* | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the SC_IS [INIT_IS] will be set to "1".
* | | |Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time.
* | | |Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
* |[4] |WARST_EN |Warm Reset Sequence Generator Enable
* | | |This bit enables SC controller to initiate the card by warm reset sequence
* | | |0 = No effect.
* | | |1 = Warm reset sequence generator Enabled.
* | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to "1".
* | | |Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time.
* | | |Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
* |[5] |TMR0_SEN |Internal Timer0 Start Enable
* | | |This bit enables Timer0 to start counting.
* | | |Software can fill "0" to stop it and set "1" to reload and count.
* | | |0 = Stops counting.
* | | |1 = Starts counting.
* | | |Note1: This field is used for internal 24 bit timer when SC_CTL [TMR_SEL] = 01.
* | | |Note2: If the operation mode is not in auto-reload mode (SC_TMR0 [26] = "0"), this bit will be auto-cleared by hardware.
* | | |Note3: This field will be cleared by TX_RST and RX_RST.
* | | |So don't fill this bit, TX_RST and RX_RST at the same time.
* | | |Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
* |[6] |TMR1_SEN |Internal Timer1 Start Enable
* | | |This bit enables Timer "1" to start counting.
* | | |Software can fill 0 to stop it and set "1" to reload and count.
* | | |0 = Stops counting.
* | | |1 = Starts counting.
* | | |Note1: This field is used for internal 8-bit timer when SC_CTL [TMR_SEL] = 01 or 10.
* | | |Don't filled TMR1_SEN when SC_CTL [TMR_SEL] = 00 or 11.
* | | |Note2: If the operation mode is not in auto-reload mode (SC_TMR1 [26] = "0"), this bit will be auto-cleared by hardware.
* | | |Note3: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time.
* | | |Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
* |[7] |TMR2_SEN |Internal Timer2 Start Enable
* | | |This bit enables Timer2 to start counting.
* | | |Software can fill "0" to stop it and set "1" to reload and count.
* | | |0 = Stops counting.
* | | |1 = Starts counting.
* | | |Note1: This field is used for internal 8-bit timer when SC_CTL [TMR_SEL] == 11.
* | | |Don't filled TMR2_SEN when SC_CTL [TMR_SEL] == 00 or 01 or 10.
* | | |Note2: If the operation mode is not in auto-reload mode (SC_TMR2 [26] = "0"), this bit will be auto-cleared by hardware.
* | | |Note3: This field will be cleared by TX_RST and RX_RST.
* | | |So don't fill this bit, TX_RST, and RX_RST at the same time.
* | | |Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
* |[9:8] |INIT_SEL |Initial Timing Selection
* | | |This field indicates the timing of hardware initial state (activation or warm-reset or deactivation).
* |[12] |RX_BGT_EN |Receiver Block Guard Time Function Enable
* | | |0 = Receiver block guard time function Disabled.
* | | |1 = Receiver block guard time function Enabled.
* |[13] |TMR0_ATV |Internal Timer0 Active State (Read Only)
* | | |This bit indicates the timer counter status of timer0.
* | | |0 = Timer0 is not active.
* | | |1 = Timer0 is active.
* |[14] |TMR1_ATV |Internal Timer1 Active State (Read Only)
* | | |This bit indicates the timer counter status of timer1.
* | | |0 = Timer1 is not active.
* | | |1 = Timer1 is active.
* |[15] |TMR2_ATV |Internal Timer2 Active State (Read Only)
* | | |This bit indicates the timer counter status of timer2.
* | | |0 = Timer2 is not active.
* | | |1 = Timer2 is active.
*/
__IO uint32_t ALTCTL;
/**
* EGTR
* ===================================================================================================
* Offset: 0x0C SC Extend Guard Time Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |EGT |Extended Guard Time
* | | |This field indicates the extended guard timer value.
* | | |Note: The counter is ETU based and the real extended guard time is EGT.
*/
__IO uint32_t EGTR;
/**
* RFTMR
* ===================================================================================================
* Offset: 0x10 SC Receive Buffer Time-Out Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |RFTM |SC Receiver Buffer Time-Out Register (ETU Based)
* | | |The time-out counter resets and starts counting whenever the RX buffer received a new data word.
* | | |Once the counter decrease to "1" and no new data is received or CPU does not read data by reading SC_RBR register, a receiver time-out interrupt INT_RTMR will be generated(if SC_IER[RTMR_IE] is high).
* | | |Note1: The counter is ETU based and the real count value is RFTM + 1
* | | |Note2: Fill all "0" to this field to disable this function.
*/
__IO uint32_t RFTMR;
/**
* ETUCR
* ===================================================================================================
* Offset: 0x14 SC ETU Control Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |ETU_RDIV |ETU Rate Divider
* | | |The field indicates the clock rate divider.
* | | |The real ETU is ETU_RDIV + 1.
* | | |Note1: Software can configure this field, but this field must be greater than 0x04.
* | | |Note2: Software can configure this field, but if the error rate is equal to 2%, this field must be greater than 0x040.
* |[15] |COMPEN_EN |Compensation Mode Enable
* | | |This bit enables clock compensation function.
* | | |When this bit enabled, hardware will alternate between n clock cycles and (n-1) clock cycles, where n is the value to be written into the ETU_RDIV register.
* | | |0 = Compensation function Disabled.
* | | |1 = Compensation function Enabled.
*/
__IO uint32_t ETUCR;
/**
* IER
* ===================================================================================================
* Offset: 0x18 SC Interrupt Enable Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDA_IE |Receive Data Reach Interrupt Enable
* | | |This field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable.
* | | |0 = INT_RDR Disabled.
* | | |1 = INT_RDR Enabled.
* |[1] |TBE_IE |Transmit Buffer Empty Interrupt Enable
* | | |This field is used for transmit buffer empty interrupt enable.
* | | |0 = INT_THRE Disabled.
* | | |1 = INT_THRE Enabled.
* |[2] |TERR_IE |Transfer Error Interrupt Enable
* | | |This field is used for transfer error interrupt enable.
* | | |The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F), receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY).
* | | |0 = INT_TERR Disabled.
* | | |1 = INT_TERR Enabled.
* |[3] |TMR0_IE |Timer0 Interrupt Enable
* | | |This field is used for TMR0 interrupt enable.
* | | |0 = INT_TMR0 Disabled.
* | | |1 = INT_TMR0 Enabled.
* |[4] |TMR1_IE |Timer1 Interrupt Enable
* | | |This field is used for TMR1 interrupt enable.
* | | |0 = INT_TMR1 Disabled.
* | | |1 = INT_TMR1 Enabled.
* |[5] |TMR2_IE |Timer2 Interrupt Enable
* | | |This field is used for TMR2 interrupt enable.
* | | |0 = INT_TMR2 Disabled.
* | | |1 = INT_TMR2 Enabled.
* |[6] |BGT_IE |Block Guard Time Interrupt Enable
* | | |This field is used for block guard time interrupt enable.
* | | |0 = INT_BGT Disabled.
* | | |1 = INT_BGT Enabled.
* |[7] |CD_IE |Card Detect Interrupt Enable
* | | |This field is used for card detect interrupt enable.
* | | |The card detect status register is SC_PINCSR [CD_CH] and SC_PINCSR[CD_CL].
* | | |0 = INT_CD Disabled.
* | | |1 = INT_CD Enabled.
* |[8] |INIT_IE |Initial End Interrupt Enable
* | | |This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable.
* | | |0 = INT_INIT Disabled.
* | | |1 = INT_INIT Enabled.
* |[9] |RTMR_IE |Receiver Buffer Time-Out Interrupt Enable
* | | |This field is used for receiver buffer time-out interrupt enable.
* | | |0 = INT_RTMR Disabled.
* | | |1 = INT_RTMR Enabled.
* |[10] |ACON_ERR_IE|Auto Convention Error Interrupt Enable
* | | |This field is used for auto convention error interrupt enable.
* | | |0 = INT_ACON_ERR Disabled.
* | | |1 = INT_ACON_ERR Enabled.
*/
__IO uint32_t IER;
/**
* ISR
* ===================================================================================================
* Offset: 0x1C SC Interrupt Status Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDA_IS |Receive Data Reach Interrupt Status Flag (Read Only)
* | | |This field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt status flag.
* | | |Note: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV].
* | | |If software reads data from SC_RBR and receiver pointer is less than SC_CTL [RX_FTRI_LEV], this bit will be cleared automatically.
* |[1] |TBE_IS |Transmit Buffer Empty Interrupt Status Flag (Read Only)
* | | |This field is used for transmit buffer empty interrupt status flag.
* | | |This bit is different with SC_TRSR [TX_EMPTY_F] flag and SC_TRSR [TX_ATV] flag; The TX_EMPTY_F will be set when the last byte data be read to shift register and TX_ATV flag indicates the transmitter is in active or not (the last data has been transmitted or not), but the TBE_IS may be set when the last byte data be read to shift register or the last data has been transmitted.
* | | |When this bit assert, software can write 1~4 byte data to SC_THR register.
* | | |Note: If software wants to clear this bit, software must write data to SC_THR register and then this bit will be cleared automatically.
* |[2] |TERR_IS |Transfer Error Interrupt Status Flag (Read Only)
* | | |This field is used for transfer error interrupt status flag.
* | | |The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F) and receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY).
* | | |Note: This field is the status flag of SC_TRSR [RX_EBR_F], SC_TRSR [RX_EFR_F], SC_TRSR [RX_EPA_F], SC_TRSR [RX_OVER_F], SC_TRSR [TX_OVER_F], SC_TRSR [RX_OVER_ERETRY] or SC_TRSR [TX_OVER_ERETRY].
* | | |So if software wants to clear this bit, software must write "1" to each field.
* |[3] |TMR0_IS |Timer0 Interrupt Status Flag (Read Only)
* | | |This field is used for TMR0 interrupt status flag.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
* |[4] |TMR1_IS |Timer1 Interrupt Status Flag (Read Only)
* | | |This field is used for TMR1 interrupt status flag.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
* |[5] |TMR2_IS |Timer2 Interrupt Status Flag (Read Only)
* | | |This field is used for TMR2 interrupt status flag.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
* |[6] |BGT_IS |Block Guard Time Interrupt Status Flag (Read Only)
* | | |This field is used for block guard time interrupt status flag.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
* |[7] |CD_IS |Card Detect Interrupt Status Flag (Read Only)
* | | |This field is used for card detect interrupt status flag.
* | | |The card detect status register is SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F].
* | | |Note: This field is the status flag of SC_PINCSR [CD_INS_F] or SC_PINCSR [CD_REM_F].
* | | |So if software wants to clear this bit, software must write "1" to this field.
* |[8] |INIT_IS |Initial End Interrupt Status Flag (Read Only)
* | | |This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
* |[9] |RTMR_IS |Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
* | | |This field is used for receiver buffer time-out interrupt status flag.
* | | |Note: This field is the status flag of receiver buffer time-out state.
* | | |If software wants to clear this bit, software must read the receiver buffer remaining data by reading SC_RBR register,.
* |[10] |ACON_ERR_IS|Auto Convention Error Interrupt Status Flag (Read Only)
* | | |This field indicates auto convention sequence error.
* | | |If the received TS at ATR state is not 0x3B or 0x3F, this bit will be set.
* | | |Note: This bit is read only, but can be cleared by writing "1" to it.
*/
__IO uint32_t ISR;
/**
* TRSR
* ===================================================================================================
* Offset: 0x20 SC Transfer Status Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RX_OVER_F |RX Overflow Error Status Flag (Read Only)
* | | |This bit is set when RX buffer overflow.
* | | |If the number of received bytes is greater than RX Buffer (SC_RBR) size, 4 bytes of SC, this bit will be set.
* | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
* | | |Note2: The overwrite data will be ignored.
* |[1] |RX_EMPTY_F|Receiver Buffer Empty Status Flag(Read Only)
* | | |This bit indicates RX buffer empty or not.
* | | |When the last byte of RX buffer has been read by CPU, hardware sets this bit high.
* | | |It will be cleared when SC receives any new data.
* |[2] |RX_FULL_F |Receiver Buffer Full Status Flag (Read Only)
* | | |This bit indicates RX buffer full or not.
* | | |This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
* |[4] |RX_EPA_F |Receiver Parity Error Status Flag (Read Only)
* | | |This bit is set to logic "1" whenever the received character does not have a valid "parity bit".
* | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
* | | |Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
* |[5] |RX_EFR_F |Receiver Frame Error Status Flag (Read Only)
* | | |This bit is set to logic "1" whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic "0").
* | | |Note1: This bit is read only, but can be cleared by writing "1" to it.
* | | |Note2: If CPI sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
* |[6] |RX_EBR_F |Receiver Break Error Status Flag (Read Only)
* | | |This bit is set to a logic "1" whenever the received data input (RX) held in the "spacing state" (logic "0") is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
* | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
* | | |Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
* |[8] |TX_OVER_F |TX Overflow Error Interrupt Status Flag (Read Only)
* | | |If TX buffer is full (TX_FULL_F = "1"), an additional write data to SC_THR will cause this bit to logic "1".
* | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
* | | |Note2: The additional write data will be ignored.
* |[9] |TX_EMPTY_F|Transmit Buffer Empty Status Flag (Read Only)
* | | |This bit indicates TX buffer empty or not.
* | | |When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
* | | |It will be cleared when writing data into SC_THR (TX buffer not empty).
* |[10] |TX_FULL_F |Transmit Buffer Full Status Flag (Read Only)
* | | |This bit indicates TX buffer full or not.
* | | |This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
* |[18:16] |RX_POINT_F|Receiver Buffer Pointer Status Flag (Read Only)
* | | |This field indicates the RX buffer pointer status flag.
* | | |When SC receives one byte from external device, RX_POINT_F increases one.
* | | |When one byte of RX buffer is read by CPU, RX_POINT_F decreases one.
* |[21] |RX_REERR |Receiver Retry Error (Read Only)
* | | |This bit is set by hardware when RX has any error and retries transfer.
* | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
* | | |Note2 This bit is a flag and can not generate any interrupt to CPU.
* | | |Note3: If CPU enables receiver retry function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
* |[22] |RX_OVER_ERETRY|Receiver Over Retry Error (Read Only)
* | | |This bit is set by hardware when RX transfer error retry over retry number limit.
* | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
* | | |Note2: If CPU enables receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
* |[23] |RX_ATV |Receiver In Active Status Flag (Read Only)
* | | |This bit is set by hardware when RX transfer is in active.
* | | |This bit is cleared automatically when RX transfer is finished.
* |[26:24] |TX_POINT_F|Transmit Buffer Pointer Status Flag (Read Only)
* | | |This field indicates the TX buffer pointer status flag.
* | | |When CPU writes data into SC_THR, TX_POINT_F increases one.
* | | |When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one.
* |[29] |TX_REERR |Transmitter Retry Error (Read Only)
* | | |This bit is set by hardware when transmitter re-transmits.
* | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
* | | |Note2 This bit is a flag and can not generate any interrupt to CPU.
* |[30] |TX_OVER_ERETRY|Transmitter Over Retry Error (Read Only)
* | | |This bit is set by hardware when transmitter re-transmits over retry number limitation.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
* |[31] |TX_ATV |Transmit In Active Status Flag (Read Only)
* | | |This bit is set by hardware when TX transfer is in active or the last byte transmission has not completed.
* | | |This bit is cleared automatically when TX transfer is finished and the STOP bit (include guard time) has been transmitted.
*/
__IO uint32_t TRSR;
/**
* PINCSR
* ===================================================================================================
* Offset: 0x24 SC Pin Control State Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |POW_EN |SC_POW_EN Pin Signal
* | | |This bit is the pin status of SC_POW_EN but user can drive SC_POW_EN pin to high or low by setting this bit.
* | | |0 = Drive SC_POW_EN pin to low.
* | | |1 = Drive SC_POW_EN pin to high.
* | | |Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically.
* | | |So don't fill this field When operating in these modes.
* |[1] |SC_RST |SC_RST Pin Signal
* | | |This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.
* | | |0 = Drive SC_RST pin to low.
* | | |1 = Drive SC_RST pin to high.
* | | |Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically.
* | | |So don't fill this field When operating in these modes.
* |[2] |CD_REM_F |Card Detect Removal Status Of SC_CD Pin (Read Only)
* | | |This bit is set whenever card has been removal.
* | | |0 = No effect.
* | | |1 = Card Removal.
* | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
* | | |Note2: Card detect engine will start after SC_CTL [SC_CEN] set.
* |[3] |CD_INS_F |Card Detect Insert Status Of SC_CD Pin (Read Only)
* | | |This bit is set whenever card has been inserted.
* | | |0 = No effect.
* | | |1 = Card insert.
* | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
* | | |Note2: Card detect engine will start after SC_CTL [SC_CEN] set.
* |[4] |CD_PIN_ST |Card Detect Status Of SC_CD Pin Status (Read Only)
* | | |This bit is the pin status flag of SC_CD
* | | |0 = SC_CD pin state at low.
* | | |1 = SC_CD pin state at high.
* |[6] |CLK_KEEP |SC Clock Enable
* | | |0 = SC clock generation Disabled.
* | | |1 = SC clock always keeps free running.
* | | |Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically.
* | | |So don't fill this field when operation in these modes.
* |[7] |ADAC_CD_EN|Auto Deactivation When Card Removal
* | | |0 = Auto deactivation Disabled when hardware detected the card is removal.
* | | |1 = Auto deactivation Enabled when hardware detected the card is removal.
* | | |Note1: When the card is removal, hardware will stop any process and then do deactivation sequence (if this bit be setting).
* | | |If this process completes.
* | | |Hardware will generate an interrupt INT_INIT to CPU.
* |[8] |SC_OEN_ST |SC Data Pin Output Enable Status (Read Only)
* | | |0 = SC data output enable pin status is at low.
* | | |1 = SC data output enable pin status is at high.
* |[9] |SC_DATA_O |Output Of SC Data Pin
* | | |This bit is the pin status of SC data output but user can drive this pin to high or low by setting this bit.
* | | |0 = Drive SC data output pin to low.
* | | |1 = Drive SC data output pin to high.
* | | |Note: When SC is at activation, warm re set or deactivation mode, this bit will be changed automatically.
* | | |So don't fill this field when SC is in these modes.
* |[10] |CD_LEV |Card Detect Level
* | | |0 = When hardware detects the card detect pin from high to low, it indicates a card is detected.
* | | |1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
* | | |Note: Software must select card detect level before Smart Card engine enable
* |[11] |POW_INV |SC_POW Pin Inverse
* | | |This bit is used for inverse the SC_POW pin.
* | | |There are four kinds of combination for SC_POW pin setting by POW_INV and
* | | |POW_EN(SC_PINCSR[0]). POW_INV is bit 1 and POW_EN is bit 0 for SC_POW_Pin as
* | | |high or low voltage selection.
* | | |POW_INV is 0 and POW_EN is 0, than SC_POW Pin output 0.
* | | |POW_INV is 0 and POW_EN is 1, than SC_POW Pin output 1.
* | | |POW_INV is 1 and POW_EN is 0, than SC_POW Pin output 1.
* | | |POW_INV is 1 and POW_EN is 1, than SC_POW Pin output 0.
* | | |Note: Software must select POW_INV before Smart Card is enabled by SC_CEN (SC_CTL[0])
* |[16] |SC_DATA_I_ST|SC Data Input Pin Status (Read Only)
* | | |This bit is the pin status of SC_DATA_I
* | | |0 = The SC_DATA_I pin is low.
* | | |1 = The SC_DATA_I pin is high.
*/
__IO uint32_t PINCSR;
/**
* TMR0
* ===================================================================================================
* Offset: 0x28 SC Internal Timer Control Register 0.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Timer 0 Counter Value Register (ETU Base)
* | | |This field indicates the internal timer operation values.
* |[27:24] |MODE |Timer 0 Operation Mode Selection
* | | |This field indicates the internal 24 bit timer operation selection.
*/
__IO uint32_t TMR0;
/**
* TMR1
* ===================================================================================================
* Offset: 0x2C SC Internal Timer Control Register 1.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 1 Counter Value Register (ETU Base)
* | | |This field indicates the internal timer operation values.
* |[27:24] |MODE |Timer 1 Operation Mode Selection
* | | |This field indicates the internal 8 bit timer operation selection.
*/
__IO uint32_t TMR1;
/**
* TMR2
* ===================================================================================================
* Offset: 0x30 SC Internal Timer Control Register 2.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 2 Counter Value Register (ETU Base)
* | | |This field indicates the internal timer operation values.
* |[27:24] |MODE |Timer 2 Operation Mode Selection
* | | |This field indicates the internal 8 bit timer operation selection.
*/
__IO uint32_t TMR2;
/**
* UACTL
* ===================================================================================================
* Offset: 0x34 SC UART Mode Control Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |UA_MODE_EN|UART Mode Enable
* | | |0 = Smart Card mode.
* | | |1 = UART mode.
* | | |Note1: When operating in UART mode, user must set SCx_CTL [CON_SEL] and SCx_CTL [AUTO_CON_EN] to "0".
* | | |Note2: When operating in smart card mode, user must set SCx_UACTL [7:0] register to "0".
* | | |Note3: When UART is enabled, hardware will generate a reset to reset internal buffer and internal state machine.
* |[5:4] |DATA_LEN |Data Length
* | | |00 = 8 bits
* | | |01 = 7 bits
* | | |10 = 6 bits
* | | |11 = 5 bits
* | | |Note: In Smart Card mode, this field must be '00'
* |[6] |PBDIS |Parity Bit Disable
* | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
* | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
* | | |Note: In Smart Card mode, this field must be '0' (default setting is with parity bit)
* |[7] |OPE |Odd Parity Enable
* | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
* | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
* | | |Note: This bit has effect only when PBDIS bit is '0'.
*/
__IO uint32_t UACTL;
/**
* TDRA
* ===================================================================================================
* Offset: 0x38 SC Timer Current Data Register A.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |TDR0 |Timer0 Current Data Register (Read Only)
* | | |This field indicates the current count values of timer0.
*/
__I uint32_t TDRA;
/**
* TDRB
* ===================================================================================================
* Offset: 0x3C SC Timer Current Data Register B.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |TDR1 |Timer1 Current Data Register (Read Only)
* | | |This field indicates the current count values of timer1.
* |[15:8] |TDR2 |Timer2 Current Data Register (Read Only)
* | | |This field indicates the current count values of timer2.
*/
__I uint32_t TDRB;
} SC_T;
/**
@addtogroup SC_CONST SC Bit Field Definition
Constant Definitions for SC Controller
@{ */
#define SC_DAT_DAT_Pos (0) /*!< SC DAT: DAT Position */
#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC DAT: DAT Mask */
#define SC_CTL_SC_CEN_Pos (0) /*!< SC CTL: SC_CEN Position */
#define SC_CTL_SC_CEN_Msk (0x1ul << SC_CTL_SC_CEN_Pos) /*!< SC CTL: SC_CEN Mask */
#define SC_CTL_DIS_RX_Pos (1) /*!< SC CTL: DIS_RX Position */
#define SC_CTL_DIS_RX_Msk (0x1ul << SC_CTL_DIS_RX_Pos) /*!< SC CTL: DIS_RX Mask */
#define SC_CTL_DIS_TX_Pos (2) /*!< SC CTL: DIS_TX Position */
#define SC_CTL_DIS_TX_Msk (0x1ul << SC_CTL_DIS_TX_Pos) /*!< SC CTL: DIS_TX Mask */
#define SC_CTL_AUTO_CON_EN_Pos (3) /*!< SC CTL: AUTO_CON_EN Position */
#define SC_CTL_AUTO_CON_EN_Msk (0x1ul << SC_CTL_AUTO_CON_EN_Pos) /*!< SC CTL: AUTO_CON_EN Mask */
#define SC_CTL_CON_SEL_Pos (4) /*!< SC CTL: CON_SEL Position */
#define SC_CTL_CON_SEL_Msk (0x3ul << SC_CTL_CON_SEL_Pos) /*!< SC CTL: CON_SEL Mask */
#define SC_CTL_RX_FTRI_LEV_Pos (6) /*!< SC CTL: RX_FTRI_LEV Position */
#define SC_CTL_RX_FTRI_LEV_Msk (0x3ul << SC_CTL_RX_FTRI_LEV_Pos) /*!< SC CTL: RX_FTRI_LEV Mask */
#define SC_CTL_BGT_Pos (8) /*!< SC CTL: BGT Position */
#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC CTL: BGT Mask */
#define SC_CTL_TMR_SEL_Pos (13) /*!< SC CTL: TMR_SEL Position */
#define SC_CTL_TMR_SEL_Msk (0x3ul << SC_CTL_TMR_SEL_Pos) /*!< SC CTL: TMR_SEL Mask */
#define SC_CTL_SLEN_Pos (15) /*!< SC CTL: SLEN Position */
#define SC_CTL_SLEN_Msk (0x1ul << SC_CTL_SLEN_Pos) /*!< SC CTL: SLEN Mask */
#define SC_CTL_RX_ERETRY_Pos (16) /*!< SC CTL: RX_ERETRY Position */
#define SC_CTL_RX_ERETRY_Msk (0x7ul << SC_CTL_RX_ERETRY_Pos) /*!< SC CTL: RX_ERETRY Mask */
#define SC_CTL_RX_ERETRY_EN_Pos (19) /*!< SC CTL: RX_ERETRY_EN Position */
#define SC_CTL_RX_ERETRY_EN_Msk (0x1ul << SC_CTL_RX_ERETRY_EN_Pos) /*!< SC CTL: RX_ERETRY_EN Mask */
#define SC_CTL_TX_ERETRY_Pos (20) /*!< SC CTL: TX_ERETRY Position */
#define SC_CTL_TX_ERETRY_Msk (0x7ul << SC_CTL_TX_ERETRY_Pos) /*!< SC CTL: TX_ERETRY Mask */
#define SC_CTL_TX_ERETRY_EN_Pos (23) /*!< SC CTL: TX_ERETRY_EN Position */
#define SC_CTL_TX_ERETRY_EN_Msk (0x1ul << SC_CTL_TX_ERETRY_EN_Pos) /*!< SC CTL: TX_ERETRY_EN Mask */
#define SC_CTL_CD_DEB_SEL_Pos (24) /*!< SC CTL: CD_DEB_SEL Position */
#define SC_CTL_CD_DEB_SEL_Msk (0x3ul << SC_CTL_CD_DEB_SEL_Pos) /*!< SC CTL: CD_DEB_SEL Mask */
#define SC_ALTCTL_TX_RST_Pos (0) /*!< SC ALTCTL: TX_RST Position */
#define SC_ALTCTL_TX_RST_Msk (0x1ul << SC_ALTCTL_TX_RST_Pos) /*!< SC ALTCTL: TX_RST Mask */
#define SC_ALTCTL_RX_RST_Pos (1) /*!< SC ALTCTL: RX_RST Position */
#define SC_ALTCTL_RX_RST_Msk (0x1ul << SC_ALTCTL_RX_RST_Pos) /*!< SC ALTCTL: RX_RST Mask */
#define SC_ALTCTL_DACT_EN_Pos (2) /*!< SC ALTCTL: DACT_EN Position */
#define SC_ALTCTL_DACT_EN_Msk (0x1ul << SC_ALTCTL_DACT_EN_Pos) /*!< SC ALTCTL: DACT_EN Mask */
#define SC_ALTCTL_ACT_EN_Pos (3) /*!< SC ALTCTL: ACT_EN Position */
#define SC_ALTCTL_ACT_EN_Msk (0x1ul << SC_ALTCTL_ACT_EN_Pos) /*!< SC ALTCTL: ACT_EN Mask */
#define SC_ALTCTL_WARST_EN_Pos (4) /*!< SC ALTCTL: WARST_EN Position */
#define SC_ALTCTL_WARST_EN_Msk (0x1ul << SC_ALTCTL_WARST_EN_Pos) /*!< SC ALTCTL: WARST_EN Mask */
#define SC_ALTCTL_TMR0_SEN_Pos (5) /*!< SC ALTCTL: TMR0_SEN Position */
#define SC_ALTCTL_TMR0_SEN_Msk (0x1ul << SC_ALTCTL_TMR0_SEN_Pos) /*!< SC ALTCTL: TMR0_SEN Mask */
#define SC_ALTCTL_TMR1_SEN_Pos (6) /*!< SC ALTCTL: TMR1_SEN Position */
#define SC_ALTCTL_TMR1_SEN_Msk (0x1ul << SC_ALTCTL_TMR1_SEN_Pos) /*!< SC ALTCTL: TMR1_SEN Mask */
#define SC_ALTCTL_TMR2_SEN_Pos (7) /*!< SC ALTCTL: TMR2_SEN Position */
#define SC_ALTCTL_TMR2_SEN_Msk (0x1ul << SC_ALTCTL_TMR2_SEN_Pos) /*!< SC ALTCTL: TMR2_SEN Mask */
#define SC_ALTCTL_INIT_SEL_Pos (8) /*!< SC ALTCTL: INIT_SEL Position */
#define SC_ALTCTL_INIT_SEL_Msk (0x3ul << SC_ALTCTL_INIT_SEL_Pos) /*!< SC ALTCTL: INIT_SEL Mask */
#define SC_ALTCTL_RX_BGT_EN_Pos (12) /*!< SC ALTCTL: RX_BGT_EN Position */
#define SC_ALTCTL_RX_BGT_EN_Msk (0x1ul << SC_ALTCTL_RX_BGT_EN_Pos) /*!< SC ALTCTL: RX_BGT_EN Mask */
#define SC_ALTCTL_TMR0_ATV_Pos (13) /*!< SC ALTCTL: TMR0_ATV Position */
#define SC_ALTCTL_TMR0_ATV_Msk (0x1ul << SC_ALTCTL_TMR0_ATV_Pos) /*!< SC ALTCTL: TMR0_ATV Mask */
#define SC_ALTCTL_TMR1_ATV_Pos (14) /*!< SC ALTCTL: TMR1_ATV Position */
#define SC_ALTCTL_TMR1_ATV_Msk (0x1ul << SC_ALTCTL_TMR1_ATV_Pos) /*!< SC ALTCTL: TMR1_ATV Mask */
#define SC_ALTCTL_TMR2_ATV_Pos (15) /*!< SC ALTCTL: TMR2_ATV Position */
#define SC_ALTCTL_TMR2_ATV_Msk (0x1ul << SC_ALTCTL_TMR2_ATV_Pos) /*!< SC ALTCTL: TMR2_ATV Mask */
#define SC_EGTR_EGT_Pos (0) /*!< SC EGTR: EGT Position */
#define SC_EGTR_EGT_Msk (0xfful << SC_EGTR_EGT_Pos) /*!< SC EGTR: EGT Mask */
#define SC_RFTMR_RFTM_Pos (0) /*!< SC RFTMR: RFTM Position */
#define SC_RFTMR_RFTM_Msk (0x1fful << SC_RFTMR_RFTM_Pos) /*!< SC RFTMR: RFTM Mask */
#define SC_ETUCR_ETU_RDIV_Pos (0) /*!< SC ETUCR: ETU_RDIV Position */
#define SC_ETUCR_ETU_RDIV_Msk (0xffful << SC_ETUCR_ETU_RDIV_Pos) /*!< SC ETUCR: ETU_RDIV Mask */
#define SC_ETUCR_COMPEN_EN_Pos (15) /*!< SC ETUCR: COMPEN_EN Position */
#define SC_ETUCR_COMPEN_EN_Msk (0x1ul << SC_ETUCR_COMPEN_EN_Pos) /*!< SC ETUCR: COMPEN_EN Mask */
#define SC_IER_RDA_IE_Pos (0) /*!< SC IER: RDA_IE Position */
#define SC_IER_RDA_IE_Msk (0x1ul << SC_IER_RDA_IE_Pos) /*!< SC IER: RDA_IE Mask */
#define SC_IER_TBE_IE_Pos (1) /*!< SC IER: TBE_IE Position */
#define SC_IER_TBE_IE_Msk (0x1ul << SC_IER_TBE_IE_Pos) /*!< SC IER: TBE_IE Mask */
#define SC_IER_TERR_IE_Pos (2) /*!< SC IER: TERR_IE Position */
#define SC_IER_TERR_IE_Msk (0x1ul << SC_IER_TERR_IE_Pos) /*!< SC IER: TERR_IE Mask */
#define SC_IER_TMR0_IE_Pos (3) /*!< SC IER: TMR0_IE Position */
#define SC_IER_TMR0_IE_Msk (0x1ul << SC_IER_TMR0_IE_Pos) /*!< SC IER: TMR0_IE Mask */
#define SC_IER_TMR1_IE_Pos (4) /*!< SC IER: TMR1_IE Position */
#define SC_IER_TMR1_IE_Msk (0x1ul << SC_IER_TMR1_IE_Pos) /*!< SC IER: TMR1_IE Mask */
#define SC_IER_TMR2_IE_Pos (5) /*!< SC IER: TMR2_IE Position */
#define SC_IER_TMR2_IE_Msk (0x1ul << SC_IER_TMR2_IE_Pos) /*!< SC IER: TMR2_IE Mask */
#define SC_IER_BGT_IE_Pos (6) /*!< SC IER: BGT_IE Position */
#define SC_IER_BGT_IE_Msk (0x1ul << SC_IER_BGT_IE_Pos) /*!< SC IER: BGT_IE Mask */
#define SC_IER_CD_IE_Pos (7) /*!< SC IER: CD_IE Position */
#define SC_IER_CD_IE_Msk (0x1ul << SC_IER_CD_IE_Pos) /*!< SC IER: CD_IE Mask */
#define SC_IER_INIT_IE_Pos (8) /*!< SC IER: INIT_IE Position */
#define SC_IER_INIT_IE_Msk (0x1ul << SC_IER_INIT_IE_Pos) /*!< SC IER: INIT_IE Mask */
#define SC_IER_RTMR_IE_Pos (9) /*!< SC IER: RTMR_IE Position */
#define SC_IER_RTMR_IE_Msk (0x1ul << SC_IER_RTMR_IE_Pos) /*!< SC IER: RTMR_IE Mask */
#define SC_IER_ACON_ERR_IE_Pos (10) /*!< SC IER: ACON_ERR_IE Position */
#define SC_IER_ACON_ERR_IE_Msk (0x1ul << SC_IER_ACON_ERR_IE_Pos) /*!< SC IER: ACON_ERR_IE Mask */
#define SC_ISR_RDA_IS_Pos (0) /*!< SC ISR: RDA_IS Position */
#define SC_ISR_RDA_IS_Msk (0x1ul << SC_ISR_RDA_IS_Pos) /*!< SC ISR: RDA_IS Mask */
#define SC_ISR_TBE_IS_Pos (1) /*!< SC ISR: TBE_IS Position */
#define SC_ISR_TBE_IS_Msk (0x1ul << SC_ISR_TBE_IS_Pos) /*!< SC ISR: TBE_IS Mask */
#define SC_ISR_TERR_IS_Pos (2) /*!< SC ISR: TERR_IS Position */
#define SC_ISR_TERR_IS_Msk (0x1ul << SC_ISR_TERR_IS_Pos) /*!< SC ISR: TERR_IS Mask */
#define SC_ISR_TMR0_IS_Pos (3) /*!< SC ISR: TMR0_IS Position */
#define SC_ISR_TMR0_IS_Msk (0x1ul << SC_ISR_TMR0_IS_Pos) /*!< SC ISR: TMR0_IS Mask */
#define SC_ISR_TMR1_IS_Pos (4) /*!< SC ISR: TMR1_IS Position */
#define SC_ISR_TMR1_IS_Msk (0x1ul << SC_ISR_TMR1_IS_Pos) /*!< SC ISR: TMR1_IS Mask */
#define SC_ISR_TMR2_IS_Pos (5) /*!< SC ISR: TMR2_IS Position */
#define SC_ISR_TMR2_IS_Msk (0x1ul << SC_ISR_TMR2_IS_Pos) /*!< SC ISR: TMR2_IS Mask */
#define SC_ISR_BGT_IS_Pos (6) /*!< SC ISR: BGT_IS Position */
#define SC_ISR_BGT_IS_Msk (0x1ul << SC_ISR_BGT_IS_Pos) /*!< SC ISR: BGT_IS Mask */
#define SC_ISR_CD_IS_Pos (7) /*!< SC ISR: CD_IS Position */
#define SC_ISR_CD_IS_Msk (0x1ul << SC_ISR_CD_IS_Pos) /*!< SC ISR: CD_IS Mask */
#define SC_ISR_INIT_IS_Pos (8) /*!< SC ISR: INIT_IS Position */
#define SC_ISR_INIT_IS_Msk (0x1ul << SC_ISR_INIT_IS_Pos) /*!< SC ISR: INIT_IS Mask */
#define SC_ISR_RTMR_IS_Pos (9) /*!< SC ISR: RTMR_IS Position */
#define SC_ISR_RTMR_IS_Msk (0x1ul << SC_ISR_RTMR_IS_Pos) /*!< SC ISR: RTMR_IS Mask */
#define SC_ISR_ACON_ERR_IS_Pos (10) /*!< SC ISR: ACON_ERR_IS Position */
#define SC_ISR_ACON_ERR_IS_Msk (0x1ul << SC_ISR_ACON_ERR_IS_Pos) /*!< SC ISR: ACON_ERR_IS Mask */
#define SC_TRSR_RX_OVER_F_Pos (0) /*!< SC TRSR: RX_OVER_F Position */
#define SC_TRSR_RX_OVER_F_Msk (0x1ul << SC_TRSR_RX_OVER_F_Pos) /*!< SC TRSR: RX_OVER_F Mask */
#define SC_TRSR_RX_EMPTY_F_Pos (1) /*!< SC TRSR: RX_EMPTY_F Position */
#define SC_TRSR_RX_EMPTY_F_Msk (0x1ul << SC_TRSR_RX_EMPTY_F_Pos) /*!< SC TRSR: RX_EMPTY_F Mask */
#define SC_TRSR_RX_FULL_F_Pos (2) /*!< SC TRSR: RX_FULL_F Position */
#define SC_TRSR_RX_FULL_F_Msk (0x1ul << SC_TRSR_RX_FULL_F_Pos) /*!< SC TRSR: RX_FULL_F Mask */
#define SC_TRSR_RX_EPA_F_Pos (4) /*!< SC TRSR: RX_EPA_F Position */
#define SC_TRSR_RX_EPA_F_Msk (0x1ul << SC_TRSR_RX_EPA_F_Pos) /*!< SC TRSR: RX_EPA_F Mask */
#define SC_TRSR_RX_EFR_F_Pos (5) /*!< SC TRSR: RX_EFR_F Position */
#define SC_TRSR_RX_EFR_F_Msk (0x1ul << SC_TRSR_RX_EFR_F_Pos) /*!< SC TRSR: RX_EFR_F Mask */
#define SC_TRSR_RX_EBR_F_Pos (6) /*!< SC TRSR: RX_EBR_F Position */
#define SC_TRSR_RX_EBR_F_Msk (0x1ul << SC_TRSR_RX_EBR_F_Pos) /*!< SC TRSR: RX_EBR_F Mask */
#define SC_TRSR_TX_OVER_F_Pos (8) /*!< SC TRSR: TX_OVER_F Position */
#define SC_TRSR_TX_OVER_F_Msk (0x1ul << SC_TRSR_TX_OVER_F_Pos) /*!< SC TRSR: TX_OVER_F Mask */
#define SC_TRSR_TX_EMPTY_F_Pos (9) /*!< SC TRSR: TX_EMPTY_F Position */
#define SC_TRSR_TX_EMPTY_F_Msk (0x1ul << SC_TRSR_TX_EMPTY_F_Pos) /*!< SC TRSR: TX_EMPTY_F Mask */
#define SC_TRSR_TX_FULL_F_Pos (10) /*!< SC TRSR: TX_FULL_F Position */
#define SC_TRSR_TX_FULL_F_Msk (0x1ul << SC_TRSR_TX_FULL_F_Pos) /*!< SC TRSR: TX_FULL_F Mask */
#define SC_TRSR_RX_POINT_F_Pos (16) /*!< SC TRSR: RX_POINT_F Position */
#define SC_TRSR_RX_POINT_F_Msk (0x7ul << SC_TRSR_RX_POINT_F_Pos) /*!< SC TRSR: RX_POINT_F Mask */
#define SC_TRSR_RX_REERR_Pos (21) /*!< SC TRSR: RX_REERR Position */
#define SC_TRSR_RX_REERR_Msk (0x1ul << SC_TRSR_RX_REERR_Pos) /*!< SC TRSR: RX_REERR Mask */
#define SC_TRSR_RX_OVER_ERETRY_Pos (22) /*!< SC TRSR: RX_OVER_ERETRY Position */
#define SC_TRSR_RX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_RX_OVER_ERETRY_Pos) /*!< SC TRSR: RX_OVER_ERETRY Mask */
#define SC_TRSR_RX_ATV_Pos (23) /*!< SC TRSR: RX_ATV Position */
#define SC_TRSR_RX_ATV_Msk (0x1ul << SC_TRSR_RX_ATV_Pos) /*!< SC TRSR: RX_ATV Mask */
#define SC_TRSR_TX_POINT_F_Pos (24) /*!< SC TRSR: TX_POINT_F Position */
#define SC_TRSR_TX_POINT_F_Msk (0x7ul << SC_TRSR_TX_POINT_F_Pos) /*!< SC TRSR: TX_POINT_F Mask */
#define SC_TRSR_TX_REERR_Pos (29) /*!< SC TRSR: TX_REERR Position */
#define SC_TRSR_TX_REERR_Msk (0x1ul << SC_TRSR_TX_REERR_Pos) /*!< SC TRSR: TX_REERR Mask */
#define SC_TRSR_TX_OVER_ERETRY_Pos (30) /*!< SC TRSR: TX_OVER_ERETRY Position */
#define SC_TRSR_TX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_TX_OVER_ERETRY_Pos) /*!< SC TRSR: TX_OVER_ERETRY Mask */
#define SC_TRSR_TX_ATV_Pos (31) /*!< SC TRSR: TX_ATV Position */
#define SC_TRSR_TX_ATV_Msk (0x1ul << SC_TRSR_TX_ATV_Pos) /*!< SC TRSR: TX_ATV Mask */
#define SC_PINCSR_POW_EN_Pos (0) /*!< SC PINCSR: POW_EN Position */
#define SC_PINCSR_POW_EN_Msk (0x1ul << SC_PINCSR_POW_EN_Pos) /*!< SC PINCSR: POW_EN Mask */
#define SC_PINCSR_SC_RST_Pos (1) /*!< SC PINCSR: SC_RST Position */
#define SC_PINCSR_SC_RST_Msk (0x1ul << SC_PINCSR_SC_RST_Pos) /*!< SC PINCSR: SC_RST Mask */
#define SC_PINCSR_CD_REM_F_Pos (2) /*!< SC PINCSR: CD_REM_F Position */
#define SC_PINCSR_CD_REM_F_Msk (0x1ul << SC_PINCSR_CD_REM_F_Pos) /*!< SC PINCSR: CD_REM_F Mask */
#define SC_PINCSR_CD_INS_F_Pos (3) /*!< SC PINCSR: CD_INS_F Position */
#define SC_PINCSR_CD_INS_F_Msk (0x1ul << SC_PINCSR_CD_INS_F_Pos) /*!< SC PINCSR: CD_INS_F Mask */
#define SC_PINCSR_CD_PIN_ST_Pos (4) /*!< SC PINCSR: CD_PIN_ST Position */
#define SC_PINCSR_CD_PIN_ST_Msk (0x1ul << SC_PINCSR_CD_PIN_ST_Pos) /*!< SC PINCSR: CD_PIN_ST Mask */
#define SC_PINCSR_CLK_KEEP_Pos (6) /*!< SC PINCSR: CLK_KEEP Position */
#define SC_PINCSR_CLK_KEEP_Msk (0x1ul << SC_PINCSR_CLK_KEEP_Pos) /*!< SC PINCSR: CLK_KEEP Mask */
#define SC_PINCSR_ADAC_CD_EN_Pos (7) /*!< SC PINCSR: ADAC_CD_EN Position */
#define SC_PINCSR_ADAC_CD_EN_Msk (0x1ul << SC_PINCSR_ADAC_CD_EN_Pos) /*!< SC PINCSR: ADAC_CD_EN Mask */
#define SC_PINCSR_SC_OEN_ST_Pos (8) /*!< SC PINCSR: SC_OEN_ST Position */
#define SC_PINCSR_SC_OEN_ST_Msk (0x1ul << SC_PINCSR_SC_OEN_ST_Pos) /*!< SC PINCSR: SC_OEN_ST Mask */
#define SC_PINCSR_SC_DATA_O_Pos (9) /*!< SC PINCSR: SC_DATA_O Position */
#define SC_PINCSR_SC_DATA_O_Msk (0x1ul << SC_PINCSR_SC_DATA_O_Pos) /*!< SC PINCSR: SC_DATA_O Mask */
#define SC_PINCSR_CD_LEV_Pos (10) /*!< SC PINCSR: CD_LEV Position */
#define SC_PINCSR_CD_LEV_Msk (0x1ul << SC_PINCSR_CD_LEV_Pos) /*!< SC PINCSR: CD_LEV Mask */
#define SC_PINCSR_POW_INV_Pos (11) /*!< SC PINCSR: POW_INV Position */
#define SC_PINCSR_POW_INV_Msk (0x1ul << SC_PINCSR_POW_INV_Pos) /*!< SC PINCSR: POW_INV Mask */
#define SC_PINCSR_SC_DATA_I_ST_Pos (16) /*!< SC PINCSR: SC_DATA_I_ST Position */
#define SC_PINCSR_SC_DATA_I_ST_Msk (0x1ul << SC_PINCSR_SC_DATA_I_ST_Pos) /*!< SC PINCSR: SC_DATA_I_ST Mask */
#define SC_TMR0_CNT_Pos (0) /*!< SC TMR0: CNT Position */
#define SC_TMR0_CNT_Msk (0xfffffful << SC_TMR0_CNT_Pos) /*!< SC TMR0: CNT Mask */
#define SC_TMR0_MODE_Pos (24) /*!< SC TMR0: MODE Position */
#define SC_TMR0_MODE_Msk (0xful << SC_TMR0_MODE_Pos) /*!< SC TMR0: MODE Mask */
#define SC_TMR1_CNT_Pos (0) /*!< SC TMR1: CNT Position */
#define SC_TMR1_CNT_Msk (0xfful << SC_TMR1_CNT_Pos) /*!< SC TMR1: CNT Mask */
#define SC_TMR1_MODE_Pos (24) /*!< SC TMR1: MODE Position */
#define SC_TMR1_MODE_Msk (0xful << SC_TMR1_MODE_Pos) /*!< SC TMR1: MODE Mask */
#define SC_TMR2_CNT_Pos (0) /*!< SC TMR2: CNT Position */
#define SC_TMR2_CNT_Msk (0xfful << SC_TMR2_CNT_Pos) /*!< SC TMR2: CNT Mask */
#define SC_TMR2_MODE_Pos (24) /*!< SC TMR2: MODE Position */
#define SC_TMR2_MODE_Msk (0xful << SC_TMR2_MODE_Pos) /*!< SC TMR2: MODE Mask */
#define SC_UACTL_UA_MODE_EN_Pos (0) /*!< SC UACTL: UA_MODE_EN Position */
#define SC_UACTL_UA_MODE_EN_Msk (0x1ul << SC_UACTL_UA_MODE_EN_Pos) /*!< SC UACTL: UA_MODE_EN Mask */
#define SC_UACTL_DATA_LEN_Pos (4) /*!< SC UACTL: DATA_LEN Position */
#define SC_UACTL_DATA_LEN_Msk (0x3ul << SC_UACTL_DATA_LEN_Pos) /*!< SC UACTL: DATA_LEN Mask */
#define SC_UACTL_PBDIS_Pos (6) /*!< SC UACTL: PBDIS Position */
#define SC_UACTL_PBDIS_Msk (0x1ul << SC_UACTL_PBDIS_Pos) /*!< SC UACTL: PBDIS Mask */
#define SC_UACTL_OPE_Pos (7) /*!< SC UACTL: OPE Position */
#define SC_UACTL_OPE_Msk (0x1ul << SC_UACTL_OPE_Pos) /*!< SC UACTL: OPE Mask */
#define SC_TDRA_TDR0_Pos (0) /*!< SC TDRA: TDR0 Position */
#define SC_TDRA_TDR0_Msk (0xfffffful << SC_TDRA_TDR0_Pos) /*!< SC TDRA: TDR0 Mask */
#define SC_TDRB_TDR1_Pos (0) /*!< SC TDRB: TDR1 Position */
#define SC_TDRB_TDR1_Msk (0xfful << SC_TDRB_TDR1_Pos) /*!< SC TDRB: TDR1 Mask */
#define SC_TDRB_TDR2_Pos (8) /*!< SC TDRB: TDR2 Position */
#define SC_TDRB_TDR2_Msk (0xfful << SC_TDRB_TDR2_Pos) /*!< SC TDRB: TDR2 Mask */
/**@}*/ /* SC_CONST */
/**@}*/ /* end of SC register group */
/*---------------------- Serial Peripheral Interface Controller -------------------------*/
/**
@addtogroup SPI Serial Peripheral Interface Controller(SPI)
Memory Mapped Structure for SPI Controller
@{ */
typedef struct {
/**
* CTL
* ===================================================================================================
* Offset: 0x00 SPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GO_BUSY |SPI Transfer Control Bit And Busy Status
* | | |0 = Writing this bit "0" will stop data transfer if SPI is transferring.
* | | |1 = In Master mode, writing "1" to this bit will start the SPI data transfer; In Slave mode, writing '1' to this bit indicates that the salve is ready to communicate with a master.
* | | |If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1'.
* | | |As the transfer is finished, this bit will be cleared automatically.
* | | |Software can read this bit to check if the SPI is in busy status.
* | | |In FIFO mode, this bit will be controlled by hardware.
* | | |Software should not modify this bit.
* | | |In slave mode, this bit always returns 1 when software reads this register.
* | | |In master mode, this bit reflects the busy or idle status of SPI.
* | | |Note1: When FIFO mode is disabled, all configurations should be set before writing "1" to the GO_BUSY bit in the SPI_CTL register.
* | | |Note2: When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer.
* |[1] |RX_NEG |Receive At Negative Edge
* | | |0 = The received data is latched on the rising edge of SPI_SCLK.
* | | |1 = The received data is latched on the falling edge of SPI_SCLK.
* |[2] |TX_NEG |Transmit At Negative Edge
* | | |0 = The transmitted data output is changed on the rising edge of SPI_SCLK.
* | | |1 = The transmitted data output is changed on the falling edge of SPI_SCLK.
* |[7:3] |TX_BIT_LEN|Transmit Bit Length
* | | |This field specifies how many bits can be transmitted / received in one transaction.
* | | |The minimum bit length is 8 bits and can be up to 32 bits.
* | | |00000 = 32 bits are transmitted in one transaction.
* | | |01000 = 8 bits are transmitted in one transaction.
* | | |01001 = 9 bits are transmitted in one transaction.
* | | |01010 = 10 bits are transmitted in one transaction.
* | | |-----
* | | |11111 = 31 bits are transmitted in one transaction.
* |[10] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of TX_BITLEN, is transmitted/received first.
* | | |1 = The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the SPI_RX register (SPI_RX0/1).
* |[11] |CLKP |Clock Polarity
* | | |0 = The default level of SCLK is low.
* | | |1 = The default level of SCLK is high.
* |[15:12] |SP_CYCLE |Suspend Interval (Master Only)
* | | |These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
* | | |The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = "0".
* | | |If CLKP = "1", the interval is from the rising clock edge to the falling clock edge.
* | | |The default value is 0x3. The desired suspend interval is obtained according to the following equation:
* | | |(SP_CYCLE[3:0) + 0.5) * period of SPICLK
* | | |Ex:
* | | |SP_CYCLE = 0x0 .... 0.5 SPICLK clock cycle.
* | | |SP_CYCLE = 0x1 .... 1.5 SPICLK clock cycle.
* | | |......
* | | |SP_CYCLE = 0xE .... 14.5 SPICLK clock cycle.
* | | |SP_CYCLE = 0xF .... 15.5 SPICLK clock cycle.
* | | |If the Variable Clock function is enabled, the minimum period of suspend interval (the transmit data in FIFO buffer is not empty) between the successive transaction is (6.5 + SP_CYCLE) * SPICLK clock cycle
* |[17] |INTEN |Interrupt Enable Control
* | | |0 = SPI Interrupt Disabled.
* | | |1 = SPI Interrupt Enabled.
* |[18] |SLAVE |Slave Mode
* | | |0 = SPI controller set as Master mode.
* | | |1 = SPI controller set as Slave mode.
* |[19] |REORDER |Byte Reorder Function Enable Control
* | | |0 = Disable byte reorder function.
* | | |1 = Enable byte reorder function and insert a byte suspend interval among each byte.
* | | |The setting of TX_BIT_LEN must be configured as 00b ( 32 bits/ word).
* | | |The suspend interval is defined in SP_CYCLE.
* | | |Note: Byte Suspend is only used in SPI Byte Reorder mode.
* |[21] |FIFOM |FIFO Mode Enable Control
* | | |0 = FIFO mode Disabled (in Normal mode).
* | | |1 = FIFO mode Enabled.
* |[22] |TWOB |2-Bit Transfer Mode Active
* | | |0 = 2-bit transfer mode Disabled.
* | | |1 = 2-bit transfer mode Enabled.
* |[23] |VARCLK_EN |Variable Clock Enable Control
* | | |0 = The serial clock output frequency is fixed and only decided by the value of DIVIDER1.
* | | |1 = The serial clock output frequency is variable.
* | | |The output frequency is decided by the value of VARCLK (SPI_VARCLK), DIVIDER1, and DIVIDER2.
* |[28] |DUAL_IO_DIR|Dual IO Mode Direction
* | | |0 = Date read in the Dual I/O Mode function.
* | | |1 = Data write in the Dual I/O Mode function.
* |[29] |DUAL_IO_EN|Dual IO Mode Enable Control
* | | |0 = Dual I/O Mode function Disabled.
* | | |1 = Dual I/O Mode function Enabled.
* |[31] |WKEUP_EN |Wake-Up Enable Control
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* | | |Note: When the system enters Power-down mode, the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port.
* | | |After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
*/
__IO uint32_t CTL;
/**
* STATUS
* ===================================================================================================
* Offset: 0x04 SPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RX_EMPTY |Received FIFO_EMPTY Status
* | | |0 = Received data FIFO is not empty in the FIFO mode.
* | | |1 = Received data FIFO is empty in the FIFO mode.
* |[1] |RX_FULL |Received FIFO_FULL Status
* | | |0 = Received data FIFO is not full in FIFO mode.
* | | |1 = Received data FIFO is full in the FIFO mode.
* |[2] |TX_EMPTY |Transmitted FIFO_EMPTY Status
* | | |0 = Transmitted data FIFO is not empty in the FIFO mode.
* | | |1 =Transmitted data FIFO is empty in the FIFO mode.
* |[3] |TX_FULL |Transmitted FIFO_FULL Status
* | | |0 = Transmitted data FIFO is not full in the FIFO mode.
* | | |1 = Transmitted data FIFO is full in the FIFO mode.
* |[4] |LTRIG_FLAG|Level Trigger Accomplish Flag (INTERNAL ONLY)
* | | |In Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.
* | | |0 = The transferred bit length of one transaction does not meet the specified requirement.
* | | |1 = The transferred bit length meets the specified requirement which defined in TX_BIT_LEN.
* | | |Note: This bit is READ only.
* | | |As the software sets the GO_BUSY bit to 1, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period.
* | | |In FIFO mode, this bit is unmeaning.
* |[6] |SLV_START_INTSTS|Slave Start Interrupt Status
* | | |It is used to dedicate that the transfer has started in Slave mode with no slave select.
* | | |0 = Slave started transfer no active.
* | | |1 = Transfer has started in Slave mode with no slave select.
* | | |It is auto clear by transfer done or writing one clear.
* |[7] |INTSTS |Interrupt Status
* | | |0 = Transfer is not finished yet.
* | | |1 = Transfer is done. The interrupt is requested when the INTEN(SPI_CTL[17]) bit is enabled.
* | | |Note: This bit is read only, but can be cleared by writing "1" to this bit.
* |[8] |RXINT_STS |RX FIFO Threshold Interrupt Status (Read Only)
* | | |0 = RX valid data counts small or equal than RXTHRESHOLD (SPI_FFCTL[27:24]).
* | | |1 = RX valid data counts bigger than RXTHRESHOLD.
* | | |Note: If RXINT_EN(SPI_FFCTL[2]) = 1 and RX_INTSTS = 1, SPI will generate interrupt.
* |[9] |RX_OVER_RUN|RX FIFO Over Run Status
* | | |0 = No FIFO is over run.
* | | |1 = Receive FIFO over run.
* | | |Note1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will dropped.
* | | |Note2: This bit will be cleared by writing 1 to it.
* |[10] |TXINT_STS |TX FIFO Threshold Interrupt Status (Read Only)
* | | |0 = TX valid data counts bigger than TXTHRESHOLD (SPI_FFCTL[31:28].
* | | |1 = TX valid data counts small or equal than TXTHRESHOLD.
* |[12] |TIME_OUT_STS|TIMEOUT Interrupt Flag
* | | |0 = There is not timeout event on the received buffer.
* | | |1 = Time out event active in RX FIFO is not empty.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[19:16] |RX_FIFO_CNT|Data counts in RX FIFO (Read Only)
* |[23:20] |TX_FIFO_CNT|Data counts in TX FIFO (Read Only)
*/
__IO uint32_t STATUS;
/**
* CLKDIV
* ===================================================================================================
* Offset: 0x08 SPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DIVIDER1 |Clock Divider 1
* | | |The value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK.
* | | |The desired frequency is obtained according to the following equation: fsclk = feclk / (DIVIDER1 + 1)
* | | |Where feclk is the SPI peripheral clock source.
* | | |It is defined in the CLK_SEL2[21:20] in Clock control section (CLK_BA + 0x18).
* |[23:16] |DIVIDER2 |Clock Divider 2
* | | |The value is the 2nd frequency divider of the PCLK to generate the serial clock of SPI_SCLK.
* | | |The desired frequency is obtained according to the following equation: fsclk = feclk / (DIVIDER2 + 1)
*/
__IO uint32_t CLKDIV;
/**
* SSR
* ===================================================================================================
* Offset: 0x0C SPI Slave Select Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |SSR |Slave Select Active Register (Master Only)
* | | |If AUTOSS bit (SPI_SSR[3]) is cleared, writing "1" to SSR[0] bit sets the SPISS[0] line to an active state and writing "0" sets the line back to inactive state.(the same as SSR[1] for SPISS[1])
* | | |AUTOSS = 0.
* | | |00 = Both SPISS[1] and SPISS[0] are inactive.
* | | |01 = SPISS[1] is inactive, SPISS[0] is active.
* | | |10 = SPISS[1] is active, SPISS[0] is inactive.
* | | |11 = Both SPISS[1] and SPISS[0] are active.
* | | |If AUTOSS bit is set, writing "1" to any bit location of this field will select appropriate SPISS[1:0] line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time.
* | | |(The active level of SPISS[1:0] is specified in SS_LVL).
* | | |AUTOSS =1.
* | | |00 = Both SPISS[1] and SPISS[0] are inactive.
* | | |01 = SPISS[1] is inactive, SPISS[0] is active on the duration of transaction.
* | | |10 = SPISS[1] is active on the duration of transaction, SPISS[0] is inactive.
* | | |11 = Both SPISS[1] and SPISS[0] are active on the duration of transaction.
* | | |Note1: This interface can only drive one device/slave at a given time.
* | | |Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer.
* | | |Note2: SPISS[0] is also defined as device/slave select input in Slave mode.
* | | |And that the slave select input must be driven by edge active trigger which level depend on the SS_LVL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software.
* |[2] |SS_LVL |Slave Select Active Level
* | | |It defines the active level of device/slave select signal (SPISS[1:0]).
* | | |0 = The SPI_SS slave select signal is active Low.
* | | |1 = The SPI_SS slave select signal is active High.
* |[3] |AUTOSS |Automatic Slave Selection (Master Only)
* | | |0 = If this bit is set as "0", slave select signals are asserted and de-asserted by setting and clearing related bits in SSR[1:0] register.
* | | |1 = If this bit is set as "1", SPISS[1:0] signals are generated automatically.
* | | |It means that device/slave select signal, which is set in SSR[1:0] register is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done.
* |[4] |SS_LTRIG |Slave Select Level Trigger
* | | |0 = The input slave select signal is edge-trigger.
* | | |1 = The slave select signal will be level-trigger.
* | | |It depends on SS_LVL to decide the signal is active low or active high.
* |[5] |NOSLVSEL |No Slave Selected In Slave Mode
* | | |This is used to ignore the slave select signal in Slave mode.
* | | |The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.
* | | |0 = The controller is 4-wire bi-direction interface.
* | | |1 = The controller is 3-wire bi-direction interface in Slave mode.
* | | |When this bit is set as 1, the controller start to transmit/receive data after the GO_BUSY bit active and the serial clock input.
* | | |Note: In no slave select signal mode, the SS_LTRIG (SPI_SSR[4]) shall be set as "1".
* |[8] |SLV_ABORT |Abort In Slave Mode With No Slave Selected
* | | |0 = No force the slave abort.
* | | |1 = Force the current transfer done in no slave select mode.
* | | |Note: It is auto cleared to "0" by hardware when the abort event is active.
* |[9] |SSTA_INTEN|Slave Start Interrupt Enable Control
* | | |0 = Transfer start interrupt Disabled in no slave select mode.
* | | |1 = Transaction start interrupt Enabled in no slave select mode.
* | | |It is cleared when the current transfer done or the SLV_START_INTSTS bit cleared (write 1 clear).
* |[16] |SS_INT_OPT|Slave Select Interrupt Option
* | | |It is used to enable the interrupt when the transfer has done in slave mode.
* | | |0 = No any interrupt, even there is slave select inactive event.
* | | |1 = There is interrupt event when the slave select becomes inactive from active condition.
* | | |It is used to inform the user to know that the transaction has finished and the slave select into the inactive state.
*/
__IO uint32_t SSR;
/**
* RX0
* ===================================================================================================
* Offset: 0x10 SPI Receive Data FIFO Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RDATA |Receive Data FIFO Bits(Read Only)
* | | |The received data can be read on it.
* | | |If the FIFO bit is set as 1, the user also checks the RX_EMPTY, SPI_STATUS[0], to check if there is any more received data or not.
* | | |Note1: The SPI_RX1 is used only in TWOB bit (SPI_CTL[22]) is set 1.
* | | |The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode.
* | | |SPI_RX0 shall be read first in TWOB mode.
* | | |In FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data.
* | | |Note2: These registers are read only.
*/
__I uint32_t RX0;
/**
* RX1
* ===================================================================================================
* Offset: 0x14 SPI Receive Data FIFO Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RDATA |Receive Data FIFO Bits(Read Only)
* | | |The received data can be read on it.
* | | |If the FIFO bit is set as 1, the user also checks the RX_EMPTY, SPI_STATUS[0], to check if there is any more received data or not.
* | | |Note1: The SPI_RX1 is used only in TWOB bit (SPI_CTL[22]) is set 1.
* | | |The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode.
* | | |SPI_RX0 shall be read first in TWOB mode.
* | | |In FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data.
* | | |Note2: These registers are read only.
*/
__I uint32_t RX1;
uint32_t RESERVE0[2];
/**
* TX0
* ===================================================================================================
* Offset: 0x20 SPI Transmit Data FIFO Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TDATA |Transmit Data FIFO Bits(Write Only)
* | | |The Data Transmit Registers hold the data to be transmitted in the next transfer.
* | | |The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.
* | | |For example, if TX_BIT_LEN is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer.
* | | |If TX_BIT_LEN is set to 0x0, the SPI controller will perform a 32-bit transfer.
* | | |Note1: The SPI_TX1 is used only in TWOB bit (SPI_CTL[22]) is set 1.
* | | |The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode.
* | | |SPI_TX0 shall be written first in TWOB mode.
* | | |In FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_RX0 is the second channel's transmitted data.
* | | |Note2: When the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1.
*/
__O uint32_t TX0;
/**
* TX1
* ===================================================================================================
* Offset: 0x24 SPI Transmit Data FIFO Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TDATA |Transmit Data FIFO Bits(Write Only)
* | | |The Data Transmit Registers hold the data to be transmitted in the next transfer.
* | | |The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.
* | | |For example, if TX_BIT_LEN is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer.
* | | |If TX_BIT_LEN is set to 0x0, the SPI controller will perform a 32-bit transfer.
* | | |Note1: The SPI_TX1 is used only in TWOB bit (SPI_CTL[22]) is set 1.
* | | |The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode.
* | | |SPI_TX0 shall be written first in TWOB mode.
* | | |In FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_RX0 is the second channel's transmitted data.
* | | |Note2: When the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1.
*/
__O uint32_t TX1;
uint32_t RESERVE1[3];
/**
* VARCLK
* ===================================================================================================
* Offset: 0x34 SPI Variable Clock Pattern Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |VARCLK |Variable Clock Pattern Flag
* | | |The value in this field is the frequency patterns of the SPICLK.
* | | |Note: It is used for CLKP = 0 only.
*/
__IO uint32_t VARCLK;
/**
* DMA
* ===================================================================================================
* Offset: 0x38 SPI DMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TX_DMA_EN |Transmit PDMA Enable Control
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Note1: Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.
* | | |Note2: If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period.
* | | |Hardware will clear this bit to 0 automatically after PDMA transfer done.
* |[1] |RX_DMA_EN |Receiving PDMA Enable Control
* | | |0 = Receiver PDMA function Disabled.
* | | |1 = Receiver PDMA function Enabled.
* | | |Note: Hardware will clear this bit to 0 automatically after PDMA transfer done.
* | | |In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock
* |[2] |PDMA_RST |PDMA Reset
* | | |It is used to reset the SPI PDMA function into default state.
* | | |0 = After reset PDMA function or in normal operation.
* | | |1 = Reset PDMA function.
* | | |Note: it is auto cleared to "0" after the reset function has done.
*/
__IO uint32_t DMA;
/**
* FFCTL
* ===================================================================================================
* Offset: 0x3C SPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RX_CLR |Receiving FIFO Counter Clear
* | | |0 = No clear the received FIFO.
* | | |1 = Clear the received FIFO.
* | | |Note: This bit is used to clear the receiver counter in FIFO Mode.
* | | |This bit can be written "1" to clear the receiver counter and this bit will be cleared to "0" automatically after clearing receiving counter.
* | | |After the clear operation, the flag of RX_EMPTY in SPI_STATUS[0] will be set to "1".
* |[1] |TX_CLR |Transmitting FIFO Counter Clear
* | | |0 = No clear the transmitted FIFO.
* | | |1 = Clear the transmitted FIFO.
* | | |Note: This bit is used to clear the transmit counter in FIFO Mode.
* | | |This bit can be written "1" to clear the transmitting counter and this bit will be cleared to "0" automatically after clearing transmitting counter.
* | | |After the clear operation, the flag of TX_EMPTY in SPI_STATUS[2] will be set to "1".
* |[2] |RXINT_EN |RX Threshold Interrupt Enable Control
* | | |0 = Rx threshold interrupt Disabled.
* | | |1 = RX threshold interrupt Enable.
* |[3] |TXINT_EN |TX Threshold Interrupt Enable Control
* | | |0 = TX threshold interrupt Disabled.
* | | |1 = TX threshold interrupt Enable.
* |[4] |RXOVINT_EN|RX FIFO Over Run Interrupt Enable Control
* | | |0 = RX FIFO over run interrupt Disabled.
* | | |1 = RX FIFO over run interrupt Enable.
* |[7] |TIMEOUT_EN|RX Read Time Out Function Enable Control
* | | |0 = RX read Timeout function Disabled.
* | | |1 = RX read Timeout function Enable.
* |[26:24] |RX_THRESHOLD|Received FIFO Threshold
* | | |If RX valid data counts large than RXTHRESHOLD, RXINT_STS (SPI_STATUS[8]) will set to 1,.
* |[30:28] |TX_THRESHOLD|Transmit FIFO Threshold
* | | |If TX valid data counts small or equal than TXTHRESHOLD, TXINT_STS (SPI_STATUS[10]) will set to 1.
*/
__IO uint32_t FFCTL;
uint32_t RESERVE2[4];
} SPI_T;
/**
@addtogroup SPI_CONST SPI Bit Field Definition
Constant Definitions for SPI Controller
@{ */
#define SPI_CTL_GO_BUSY_Pos (0) /*!< SPI CTL: GO_BUSY Position */
#define SPI_CTL_GO_BUSY_Msk (0x1ul << SPI_CTL_GO_BUSY_Pos) /*!< SPI CTL: GO_BUSY Mask */
#define SPI_CTL_RX_NEG_Pos (1) /*!< SPI CTL: RX_NEG Position */
#define SPI_CTL_RX_NEG_Msk (0x1ul << SPI_CTL_RX_NEG_Pos) /*!< SPI CTL: RX_NEG Mask */
#define SPI_CTL_TX_NEG_Pos (2) /*!< SPI CTL: TX_NEG Position */
#define SPI_CTL_TX_NEG_Msk (0x1ul << SPI_CTL_TX_NEG_Pos) /*!< SPI CTL: TX_NEG Mask */
#define SPI_CTL_TX_BIT_LEN_Pos (3) /*!< SPI CTL: TX_BIT_LEN Position */
#define SPI_CTL_TX_BIT_LEN_Msk (0x1ful << SPI_CTL_TX_BIT_LEN_Pos) /*!< SPI CTL: TX_BIT_LEN Mask */
#define SPI_CTL_LSB_Pos (10) /*!< SPI CTL: LSB Position */
#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI CTL: LSB Mask */
#define SPI_CTL_CLKP_Pos (11) /*!< SPI CTL: CLKP Position */
#define SPI_CTL_CLKP_Msk (0x1ul << SPI_CTL_CLKP_Pos) /*!< SPI CTL: CLKP Mask */
#define SPI_CTL_SP_CYCLE_Pos (12) /*!< SPI CTL: SP_CYCLE Position */
#define SPI_CTL_SP_CYCLE_Msk (0xful << SPI_CTL_SP_CYCLE_Pos) /*!< SPI CTL: SP_CYCLE Mask */
#define SPI_CTL_INTEN_Pos (17) /*!< SPI CTL: INTEN Position */
#define SPI_CTL_INTEN_Msk (0x1ul << SPI_CTL_INTEN_Pos) /*!< SPI CTL: INTEN Mask */
#define SPI_CTL_SLAVE_Pos (18) /*!< SPI CTL: SLAVE Position */
#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI CTL: SLAVE Mask */
#define SPI_CTL_REORDER_Pos (19) /*!< SPI CTL: REORDER Position */
#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI CTL: REORDER Mask */
#define SPI_CTL_FIFOM_Pos (21) /*!< SPI CTL: FIFOM Position */
#define SPI_CTL_FIFOM_Msk (0x1ul << SPI_CTL_FIFOM_Pos) /*!< SPI CTL: FIFOM Mask */
#define SPI_CTL_TWOB_Pos (22) /*!< SPI CTL: TWOB Position */
#define SPI_CTL_TWOB_Msk (0x1ul << SPI_CTL_TWOB_Pos) /*!< SPI CTL: TWOB Mask */
#define SPI_CTL_VARCLK_EN_Pos (23) /*!< SPI CTL: VARCLK_EN Position */
#define SPI_CTL_VARCLK_EN_Msk (0x1ul << SPI_CTL_VARCLK_EN_Pos) /*!< SPI CTL: VARCLK_EN Mask */
#define SPI_CTL_DUAL_IO_DIR_Pos (28) /*!< SPI CTL: DUAL_IO_DIR Position */
#define SPI_CTL_DUAL_IO_DIR_Msk (0x1ul << SPI_CTL_DUAL_IO_DIR_Pos) /*!< SPI CTL: DUAL_IO_DIR Mask */
#define SPI_CTL_DUAL_IO_EN_Pos (29) /*!< SPI CTL: DUAL_IO_EN Position */
#define SPI_CTL_DUAL_IO_EN_Msk (0x1ul << SPI_CTL_DUAL_IO_EN_Pos) /*!< SPI CTL: DUAL_IO_EN Mask */
#define SPI_CTL_WKEUP_EN_Pos (31) /*!< SPI CTL: WKEUP_EN Position */
#define SPI_CTL_WKEUP_EN_Msk (0x1ul << SPI_CTL_WKEUP_EN_Pos) /*!< SPI CTL: WKEUP_EN Mask */
#define SPI_STATUS_RX_EMPTY_Pos (0) /*!< SPI STATUS: RX_EMPTY Position */
#define SPI_STATUS_RX_EMPTY_Msk (0x1ul << SPI_STATUS_RX_EMPTY_Pos) /*!< SPI STATUS: RX_EMPTY Mask */
#define SPI_STATUS_RX_FULL_Pos (1) /*!< SPI STATUS: RX_FULL Position */
#define SPI_STATUS_RX_FULL_Msk (0x1ul << SPI_STATUS_RX_FULL_Pos) /*!< SPI STATUS: RX_FULL Mask */
#define SPI_STATUS_TX_EMPTY_Pos (2) /*!< SPI STATUS: TX_EMPTY Position */
#define SPI_STATUS_TX_EMPTY_Msk (0x1ul << SPI_STATUS_TX_EMPTY_Pos) /*!< SPI STATUS: TX_EMPTY Mask */
#define SPI_STATUS_TX_FULL_Pos (3) /*!< SPI STATUS: TX_FULL Position */
#define SPI_STATUS_TX_FULL_Msk (0x1ul << SPI_STATUS_TX_FULL_Pos) /*!< SPI STATUS: TX_FULL Mask */
#define SPI_STATUS_LTRIG_FLAG_Pos (4) /*!< SPI STATUS: LTRIG_FLAG Position */
#define SPI_STATUS_LTRIG_FLAG_Msk (0x1ul << SPI_STATUS_LTRIG_FLAG_Pos) /*!< SPI STATUS: LTRIG_FLAG Mask */
#define SPI_STATUS_SLV_START_INTSTS_Pos (6) /*!< SPI STATUS: SLV_START_INTSTS Position */
#define SPI_STATUS_SLV_START_INTSTS_Msk (0x1ul << SPI_STATUS_SLV_START_INTSTS_Pos) /*!< SPI STATUS: SLV_START_INTSTS Mask */
#define SPI_STATUS_INTSTS_Pos (7) /*!< SPI STATUS: INTSTS Position */
#define SPI_STATUS_INTSTS_Msk (0x1ul << SPI_STATUS_INTSTS_Pos) /*!< SPI STATUS: INTSTS Mask */
#define SPI_STATUS_RXINT_STS_Pos (8) /*!< SPI STATUS: RXINT_STS Position */
#define SPI_STATUS_RXINT_STS_Msk (0x1ul << SPI_STATUS_RXINT_STS_Pos) /*!< SPI STATUS: RXINT_STS Mask */
#define SPI_STATUS_RX_OVER_RUN_Pos (9) /*!< SPI STATUS: RX_OVER_RUN Position */
#define SPI_STATUS_RX_OVER_RUN_Msk (0x1ul << SPI_STATUS_RX_OVER_RUN_Pos) /*!< SPI STATUS: RX_OVER_RUN Mask */
#define SPI_STATUS_TXINT_STS_Pos (10) /*!< SPI STATUS: TXINT_STS Position */
#define SPI_STATUS_TXINT_STS_Msk (0x1ul << SPI_STATUS_TXINT_STS_Pos) /*!< SPI STATUS: TXINT_STS Mask */
#define SPI_STATUS_TIME_OUT_STS_Pos (12) /*!< SPI STATUS: TIME_OUT_STS Position */
#define SPI_STATUS_TIME_OUT_STS_Msk (0x1ul << SPI_STATUS_TIME_OUT_STS_Pos) /*!< SPI STATUS: TIME_OUT_STS Mask */
#define SPI_STATUS_RX_FIFO_CNT_Pos (16) /*!< SPI STATUS: RX_FIFO_CNT Position */
#define SPI_STATUS_RX_FIFO_CNT_Msk (0xful << SPI_STATUS_RX_FIFO_CNT_Pos) /*!< SPI STATUS: RX_FIFO_CNT Mask */
#define SPI_STATUS_TX_FIFO_CNT_Pos (20) /*!< SPI STATUS: TX_FIFO_CNT Position */
#define SPI_STATUS_TX_FIFO_CNT_Msk (0xful << SPI_STATUS_TX_FIFO_CNT_Pos) /*!< SPI STATUS: TX_FIFO_CNT Mask */
#define SPI_CLKDIV_DIVIDER1_Pos (0) /*!< SPI CLKDIV: DIVIDER1 Position */
#define SPI_CLKDIV_DIVIDER1_Msk (0xfful << SPI_CLKDIV_DIVIDER1_Pos) /*!< SPI CLKDIV: DIVIDER1 Mask */
#define SPI_CLKDIV_DIVIDER2_Pos (16) /*!< SPI CLKDIV: DIVIDER2 Position */
#define SPI_CLKDIV_DIVIDER2_Msk (0xfful << SPI_CLKDIV_DIVIDER2_Pos) /*!< SPI CLKDIV: DIVIDER2 Mask */
#define SPI_SSR_SSR_Pos (0) /*!< SPI SSR: SSR Position */
#define SPI_SSR_SSR_Msk (0x3ul << SPI_SSR_SSR_Pos) /*!< SPI SSR: SSR Mask */
#define SPI_SSR_SS_LVL_Pos (2) /*!< SPI SSR: SS_LVL Position */
#define SPI_SSR_SS_LVL_Msk (0x1ul << SPI_SSR_SS_LVL_Pos) /*!< SPI SSR: SS_LVL Mask */
#define SPI_SSR_AUTOSS_Pos (3) /*!< SPI SSR: AUTOSS Position */
#define SPI_SSR_AUTOSS_Msk (0x1ul << SPI_SSR_AUTOSS_Pos) /*!< SPI SSR: AUTOSS Mask */
#define SPI_SSR_SS_LTRIG_Pos (4) /*!< SPI SSR: SS_LTRIG Position */
#define SPI_SSR_SS_LTRIG_Msk (0x1ul << SPI_SSR_SS_LTRIG_Pos) /*!< SPI SSR: SS_LTRIG Mask */
#define SPI_SSR_NOSLVSEL_Pos (5) /*!< SPI SSR: NOSLVSEL Position */
#define SPI_SSR_NOSLVSEL_Msk (0x1ul << SPI_SSR_NOSLVSEL_Pos) /*!< SPI SSR: NOSLVSEL Mask */
#define SPI_SSR_SLV_ABORT_Pos (8) /*!< SPI SSR: SLV_ABORT Position */
#define SPI_SSR_SLV_ABORT_Msk (0x1ul << SPI_SSR_SLV_ABORT_Pos) /*!< SPI SSR: SLV_ABORT Mask */
#define SPI_SSR_SSTA_INTEN_Pos (9) /*!< SPI SSR: SSTA_INTEN Position */
#define SPI_SSR_SSTA_INTEN_Msk (0x1ul << SPI_SSR_SSTA_INTEN_Pos) /*!< SPI SSR: SSTA_INTEN Mask */
#define SPI_SSR_SS_INT_OPT_Pos (16) /*!< SPI SSR: SS_INT_OPT Position */
#define SPI_SSR_SS_INT_OPT_Msk (0x1ul << SPI_SSR_SS_INT_OPT_Pos) /*!< SPI SSR: SS_INT_OPT Mask */
#define SPI_RX0_RDATA_Pos (0) /*!< SPI RX0: RDATA Position */
#define SPI_RX0_RDATA_Msk (0xfffffffful << SPI_RX0_RDATA_Pos) /*!< SPI RX0: RDATA Mask */
#define SPI_RX1_RDATA_Pos (0) /*!< SPI RX1: RDATA Position */
#define SPI_RX1_RDATA_Msk (0xfffffffful << SPI_RX1_RDATA_Pos) /*!< SPI RX1: RDATA Mask */
#define SPI_TX0_TDATA_Pos (0) /*!< SPI TX0: TDATA Position */
#define SPI_TX0_TDATA_Msk (0xfffffffful << SPI_TX0_TDATA_Pos) /*!< SPI TX0: TDATA Mask */
#define SPI_TX1_TDATA_Pos (0) /*!< SPI TX1: TDATA Position */
#define SPI_TX1_TDATA_Msk (0xfffffffful << SPI_TX1_TDATA_Pos) /*!< SPI TX1: TDATA Mask */
#define SPI_VARCLK_VARCLK_Pos (0) /*!< SPI VARCLK: VARCLK Position */
#define SPI_VARCLK_VARCLK_Msk (0xfffffffful << SPI_VARCLK_VARCLK_Pos) /*!< SPI VARCLK: VARCLK Mask */
#define SPI_DMA_TX_DMA_EN_Pos (0) /*!< SPI DMA: TX_DMA_EN Position */
#define SPI_DMA_TX_DMA_EN_Msk (0x1ul << SPI_DMA_TX_DMA_EN_Pos) /*!< SPI DMA: TX_DMA_EN Mask */
#define SPI_DMA_RX_DMA_EN_Pos (1) /*!< SPI DMA: RX_DMA_EN Position */
#define SPI_DMA_RX_DMA_EN_Msk (0x1ul << SPI_DMA_RX_DMA_EN_Pos) /*!< SPI DMA: RX_DMA_EN Mask */
#define SPI_DMA_PDMA_RST_Pos (2) /*!< SPI DMA: PDMA_RST Position */
#define SPI_DMA_PDMA_RST_Msk (0x1ul << SPI_DMA_PDMA_RST_Pos) /*!< SPI DMA: PDMA_RST Mask */
#define SPI_FFCTL_RX_CLR_Pos (0) /*!< SPI FFCTL: RX_CLR Position */
#define SPI_FFCTL_RX_CLR_Msk (0x1ul << SPI_FFCTL_RX_CLR_Pos) /*!< SPI FFCTL: RX_CLR Mask */
#define SPI_FFCTL_TX_CLR_Pos (1) /*!< SPI FFCTL: TX_CLR Position */
#define SPI_FFCTL_TX_CLR_Msk (0x1ul << SPI_FFCTL_TX_CLR_Pos) /*!< SPI FFCTL: TX_CLR Mask */
#define SPI_FFCTL_RX_INTEN_Pos (2) /*!< SPI FFCTL: RX_INTEN Position */
#define SPI_FFCTL_RX_INTEN_Msk (0x1ul << SPI_FFCTL_RX_INTEN_Pos) /*!< SPI FFCTL: RX_INTEN Mask */
#define SPI_FFCTL_TX_INTEN_Pos (3) /*!< SPI FFCTL: TX_INTEN Position */
#define SPI_FFCTL_TX_INTEN_Msk (0x1ul << SPI_FFCTL_TX_INTEN_Pos) /*!< SPI FFCTL: TX_INTEN Mask */
#define SPI_FFCTL_RXOVR_INTEN_Pos (4) /*!< SPI FFCTL: RXOVR_INTEN Position */
#define SPI_FFCTL_RXOVR_INTEN_Msk (0x1ul << SPI_FFCTL_RXOVR_INTEN_Pos) /*!< SPI FFCTL: RXOVR_INTEN Mask */
#define SPI_FFCTL_TIMEOUT_EN_Pos (7) /*!< SPI FFCTL: TIMEOUT_EN Position */
#define SPI_FFCTL_TIMEOUT_EN_Msk (0x1ul << SPI_FFCTL_TIMEOUT_EN_Pos) /*!< SPI FFCTL: TIMEOUT_EN Mask */
#define SPI_FFCTL_RX_THRESHOLD_Pos (24) /*!< SPI FFCTL: RX_THRESHOLD Position */
#define SPI_FFCTL_RX_THRESHOLD_Msk (0x7ul << SPI_FFCTL_RX_THRESHOLD_Pos) /*!< SPI FFCTL: RX_THRESHOLD Mask */
#define SPI_FFCTL_TX_THRESHOLD_Pos (28) /*!< SPI FFCTL: TX_THRESHOLD Position */
#define SPI_FFCTL_TX_THRESHOLD_Msk (0x7ul << SPI_FFCTL_TX_THRESHOLD_Pos) /*!< SPI FFCTL: TX_THRESHOLD Mask */
/**@}*/ /* SPI_CONST */
/**@}*/ /* end of SPI register group */
/*---------------------- Timer Controller -------------------------*/
/**
@addtogroup TIMER Timer Controller(TIMER)
Memory Mapped Structure for TMR Controller
@{ */
typedef struct {
/**
* CTL
* ===================================================================================================
* Offset: 0x00 Timer x Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TMR_EN |Timer Counter Enable Control
* | | |0 = Stops/Suspends counting.
* | | |1 = Starts counting.
* | | |Note1: Set TMR_EN to 1 enables 24-bit counter keeps up counting from the last stop counting value.
* | | |Note2: This bit is auto-cleared by hardware in one-shot mode (MODE_SEL (TMRx_CTL[5:4]) = 00) once the value of 24-bit up counter equals the TMRx_CMPR.
* |[1] |SW_RST |Software Reset
* | | |Set this bit will reset the timer counter, pre-scale counter and also force TMR_EN (TMRx_CTL [0]) to 0.
* | | |0 = No effect.
* | | |1 = Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_EN (TMRx_CTL [0]) bit.
* | | |Note: This bit will be auto cleared and takes at least 3 TMRx_CLK clock cycles.
* |[2] |WAKE_EN |Wake-Up Enable Control
* | | |When WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set, the timer controller will generate a wake-up trigger event to CPU.
* | | |0 = Wake-up trigger event Disabled.
* | | |1 = Wake-up trigger event Enabled.
* |[3] |DBGACK_EN |ICE Debug Mode Acknowledge Ineffective Enable Control
* | | |0 = ICE debug mode acknowledgement effects TIMER counting and TIMER counter will be held while ICE debug mode acknowledged.
* | | |1 = ICE debug mode acknowledgement is ineffective and TIMER counter will keep going no matter ICE debug mode acknowledged or not.
* |[5:4] |MODE_SEL |Timer Operating Mode Select
* | | |00 = The timer is operating in the one-shot mode.
* | | |In this mode, the associated interrupt signal is generated (if TMR_IER [TMR_IE] is enabled) once the value of 24-bit up counter equals the TMRx_CMPR.
* | | |And TMR_CTL [TMR_EN] is automatically cleared by hardware.
* | | |01 = The timer is operating in the periodic mode.
* | | |In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPR.
* | | |After that, the 24-bit counter will be reset and starts counting from zero again.
* | | |10 = The timer is operating in the periodic mode with output toggling.
* | | |In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPR.
* | | |After that, the 24-bit counter will be reset and starts counting from zero again.
* | | |At the same time, timer controller will also toggle the output pin TMRx_TOG_OUT to its inverse level (from low to high or from high to low).
* | | |Note: The default level of TMRx_TOG_OUT after reset is low.
* | | |11 = The timer is operating in continuous counting mode.
* | | |In this mode, the associated interrupt signal is generated when TMR_DR = TMR_CMPR (if TMR_IER [TMR_IE] is enabled).
* | | |However, the 24-bit up-counter counts continuously without reset.
* |[6] |ACMP_EN_TMR|ACMP Trigger Timer Enable Control
* | | |This bit high enables the functionality that when ACMP0 is in sigma-delta mode, it could enable Timer.
* | | |0 = ACMP0 trigger timer functionality disabled.
* | | |1 = ACMP0 trigger timer functionality enabled.
* |[7] |TMR_ACT |Timer Active Status Bit (Read Only)
* | | |This bit indicates the timer counter status of timer.
* | | |0 = Timer is not active.
* | | |1 = Timer is in active.
* |[8] |ADC_TEEN |Timer Trigger ADC Enable Control
* | | |This bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.
* | | |When ADC_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to ADC controller.
* | | |When ADC_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to ADC controller.
* | | |0 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Disabled.
* | | |1 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Enabled.
* |[10] |PDMA_TEEN |Timer Trigger PDMA Enable Control
* | | |This bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA.
* | | |When PDMA_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to PDMA controller.
* | | |When PDMA_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to PDMA controller.
* | | |0 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger PDMA Disabled.
* | | |1 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger PDMA Enabled.
* |[11] |CAP_TRG_EN|TCAP_IS Trigger Mode Enable
* | | |This bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.
* | | |If this bit is low and TMR_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]) or ADC_TEEN (TMRx_CTL[8])) is set.
* | | |If this bit is set high and TCAP_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]) or ADC_TEEN (TMRx_CTL[8])) is set.
* | | |0 = TMR_IS (TMRx_ISR[0]) is used to trigger PDMA and ADC.
* | | |1 = TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC.
* |[12] |EVENT_EN |Event Counting Mode Enable Control
* | | |When EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin.
* | | |While the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]), the 24-bit up-counting timer increases by 1.
* | | |Or, the 24-bit up-counting timer will keep its value unchanged.
* | | |0 = Timer counting is not controlled by external event pin.
* | | |1 = Timer counting is controlled by external event pin.
* |[13] |EVENT_EDGE|Event Counting Mode Edge Selection
* | | |This bit indicates which edge of external event pin enabling the timer to increase 1.
* | | |0 = A falling edge of external event enabling the timer to increase 1.
* | | |1 = A rising edge of external event enabling the timer to increase 1.
* |[14] |EVNT_DEB_EN|External Event De-Bounce Enable Control
* | | |When EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.
* | | |In de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK.
* | | |0 = De-bounce circuit Disabled.
* | | |1 = De-bounce circuit Enabled.
* | | |Note: When EVENT_EN (TMRx_CTL[12]) is enabled, enable this bit is recommended.
* | | |And, while EVENT_EN (TMRx_CTL[12]) is disabled, disable this bit is recommended to save power consumption.
* |[16] |TCAP_EN |TC Pin Functional Enable Control
* | | |This bit controls if the transition on TC pin could be used as timer counter reset function or timer capture function.
* | | |0 = The transition on TC pin is ignored.
* | | |1 = The transition on TC pin will result in the capture or reset of 24-bit timer counter.
* | | |Note: For TMRx_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to low and the TC pin transition is ignored (where x = 0 or 2).
* | | |Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to high (where x = 0 or 2).
* |[17] |TCAP_MODE |TC Pin Function Mode Selection
* | | |This bit indicates if the transition on TC pin is used as timer counter reset function or timer capture function.
* | | |0 = The transition on TC pin is used as timer capture function.
* | | |1 = The transition on TC pin is used as timer counter reset function.
* | | |Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_MODE will be forced to low (where x = 0 or 2).
* |[19:18] |TCAP_EDGE |TC Pin Edge Detect Selection
* | | |This field defines that active transition of Tcapture pin is for timer counter reset function or for timer capture function.
* | | |For timer counter reset function and free-counting mode of timer capture function, the configurations are:
* | | |00 = A falling edge (1 to 0 transition) on Tcapture pin is an active transition.
* | | |01 = A rising edge (0 to 1 transition) on Tcapture pin is an active transition.
* | | |10 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on Tcapture pin are active transitions.
* | | |11 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on Tcapture pin are active transitions.
* | | |For trigger-counting mode of timer capture function, the configurations are:
* | | |00 = 1st falling edge on Tcapture pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting.
* | | |01 = 1st rising edge on Tcapture pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting.
* | | |10 = Falling edge on Tcapture pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting.
* | | |11 = Rising edge on Tcapture pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting.
* | | |Note: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_EDGE will be forced to 11.
* |[20] |TCAP_CNT_MOD|Timer Capture Counting Mode Selection
* | | |This bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high.
* | | |If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL (TMRx_CTL[5:4]) field.
* | | |When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and the transition of TC pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.
* | | |If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at 0.
* | | |When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting.
* | | |And then if the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting.
* | | |And its value will be saved into register TMRx_TCAP.
* | | |0 = Capture with free-counting timer mode.
* | | |1 = Capture with trigger-counting timer mode.
* | | |Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_CNT_MOD will be forced to high, the capture with Trigger-counting Timer mode (where x = 0 or 2).
* |[22] |TCAP_DEB_EN|TC Pin De-Bounce Enable Control
* | | |When CAP_DEB_EN (TMRx_CTL[22]) is set, the TC pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.
* | | |In de-bounce circuit the TC pin signal will be sampled 4 times by TMRx_CLK.
* | | |0 = De-bounce circuit Disabled.
* | | |1 = De-bounce circuit Enabled.
* | | |Note: When TCAP_EN (TMRx_CTL[16]) is enabled, enable this bit is recommended.
* | | |And, while TCAP_EN (TMRx_CTL[16]) is disabled, disable this bit is recommended to save power consumption.
* | | |Note: When CAP_SRC (TMRx_ECTL[16]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low.
* | | |Note: For Timer 1 and 3, when INTR_TRG_EN (TMRx_CTL[24]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low.
* |[24] |INTR_TRG_EN|Inter-Timer Trigger Function Enable Control
* | | |This bit controls if Inter-timer Trigger function is enabled.
* | | |If Inter-timer Trigger function is enabled, the TMRx will be in counter mode and counting with external Clock Source or event.
* | | |In addition, TMRx+1 will be in trigger-counting mode of capture function.
* | | |0 = Inter-timer trigger function Disabled.
* | | |1 = Inter-timer trigger function Enabled.
* | | |Note: For TMRx+1_CTL, this bit is ignored and the read back value is always 0.
* |[25] |INTR_TRG_MODE|Inter-Timer Trigger Mode Selection
* | | |This bit controls the timer operation mode when inter-timer trigger function is enabled.
* | | |When this bit is low, the TMRx will be in counter mode and counting with external Clock Source or event.
* | | |In addition, TMRx+1 will be in trigger-counting mode of capture function.
* | | |In this mode, TMRx_CMPR control when inter-timer trigger function terminated.
* | | |When this bit is high, the TMRx will be in counter mode and counting with external Clock Source or event.
* | | |In addition, TMRx+1 will be in trigger-counting mode of capture function.
* | | |In this mode, TMRx+1_CMPR control when inter-timer trigger function terminated.
* | | |In this mode, TMRx would ignore some incoming event based on the EVNT_DROP_CNT (TMRx_ECTL[31:24]).
* | | |And once the TMRx+1 counter value equal or large than TMRx+1_CMPR, TMRx would terminate the operation when next incoming event received.
* | | |0 = Inter-Timer Trigger function wouldn't ignore any incoming event.
* | | |1 = Inter-Timer Trigger function would ignore incoming event based on the EVNT_DROP_CNT (TMRx_ECTL[31:24]).
* | | |Note: For TMRx+1_CTL, this bit is ignored and the read back value is always 0.
*/
__IO uint32_t CTL;
/**
* PRECNT
* ===================================================================================================
* Offset: 0x04 Timer x Pre-Scale Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PRESCALE_CNT|Pre-Scale Counter
* | | |Clock input is divided by PRESCALE_CNT + 1 before it is fed to the counter.
* | | |If PRESCALE_CNT =0, then there is no scaling.
*/
__IO uint32_t PRECNT;
/**
* CMPR
* ===================================================================================================
* Offset: 0x08 Timer x Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |TMR_CMP |Timer Compared Value
* | | |TMR_CMP is a 24-bit compared register.
* | | |When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL [0]) is enabled.
* | | |The TMR_CMP value defines the timer counting cycle time.
* | | |Time-out period = (Period of timer clock input) * (8-bit PRESCALE_CNT + 1) * (24-bit TMR_CMP).
* | | |Note1: Never write 0x0 or 0x1 in TMR_CMP, or the core will run into unknown state.
* | | |Note2: No matter TMR_EN (TMRx_CTL [0]) is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.
*/
__IO uint32_t CMPR;
/**
* IER
* ===================================================================================================
* Offset: 0x0C Timer x Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TMR_IE |Timer Interrupt Enable Control
* | | |0 = Timer Interrupt Disabled.
* | | |1 = Timer Interrupt Enabled.
* | | |Note: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR.
* |[1] |TCAP_IE |Timer Capture Function Interrupt Enable Control
* | | |0 = Timer External Pin Function Interrupt Disabled.
* | | |1 = Timer External Pin Function Interrupt Enabled.
* | | |Note: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting
*/
__IO uint32_t IER;
/**
* ISR
* ===================================================================================================
* Offset: 0x10 Timer x Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TMR_IS |Timer Interrupt Status
* | | |This bit indicates the interrupt status of Timer.
* | | |This bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR).
* | | |Write 1 to clear this bit to 0.
* | | |If this bit is active and TMR_IE (TMRx_IER[0]) is enabled, Timer will trigger an interrupt to CPU.
* |[1] |TCAP_IS |Timer Capture Function Interrupt Status
* | | |This bit indicates the external pin function interrupt status of Timer.
* | | |This bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting.
* | | |Write 1 to clear this bit to 0.
* | | |If this bit is active and TCAP_IE (TMRx_IER[1]) is enabled, Timer will trigger an interrupt to CPU.
* |[4] |TMR_WAKE_STS|Timer Wake-Up Status
* | | |If timer causes CPU wakes up from power-down mode, this bit will be set to high.
* | | |It must be cleared by software with a write 1 to this bit.
* | | |0 = Timer does not cause system wake-up.
* | | |1 = Wakes system up from power-down mode by Timer timeout.
* |[5] |NCAP_DET_STS|New Capture Detected Status
* | | |This status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.
* | | |If the above condition occurred, the Timer will keep register TMRx_TCAP unchanged and drop the new capture value.
* | | |Write 1 to clear this bit to 0.
* | | |0 = New incoming capture event didn't detect before CPU clearing TCAP_IS (TMRx_ISR[1]) status.
* | | |1 = New incoming capture event detected before CPU clearing TCAP_IS (TMRx_ISR[1]) status.
* |[6] |TCAP_IS_FEDGE|TC Pin Edge Detect Is Falling
* | | |This flag indicates the edge detected in TC pin is rising edge or falling edge.
* | | |Timer only updates this flag when it updates the Timer Capture Data (TMR_TCAP[23:0]) value.
* | | |When a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status, Timer will keep this bit unchanged.
* | | |0 = TC pin edge detected is rising edge.
* | | |1 = TC pin edge detected is falling edge.
*/
__IO uint32_t ISR;
/**
* DR
* ===================================================================================================
* Offset: 0x14 Timer 0 Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |TDR |Timer Data Register (Read)
* | | |User can read this register for internal 24-bit timer up-counter value.
* | | |Counter Reset (Write)
* | | |User can write any value to this register to reset internal 24-bit timer up-counter and 8-bit pre-scale counter.
* | | |This reset operation wouldn't affect any other timer control registers and circuit.
* | | |After reset completed, the 24-bit timer up-counter and 8-bit pre-scale counter restart the counting based on the TMRx_CTL register setting.
* |[31] |RSTACT |Reset Active
* | | |This bit indicates if the counter reset operation active.
* | | |When user write this register, timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0.
* | | |In the same time, timer set this flag to 1 to indicate the counter reset operation is in progress.
* | | |Once the counter reset operation done, timer clear this bit to 0 automatically.
* | | |0 = Reset operation done.
* | | |1 = Reset operation triggered by writing TMR_DR is in progress.
* | | |Note: This bit is read only. Write operation wouldn't take any effect.
*/
__IO uint32_t DR;
/**
* TCAP
* ===================================================================================================
* Offset: 0x18 Timer x Capture Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CAP |Timer Capture Data Register
* | | |When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 0, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.
* | | |When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 1, and the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.
* | | |User can read this register to get the counter value.
* | | |When a new incoming capture event detected before CPU clearing the TCAP_IS (TMRxISR[1]) status, Timer will keep this filed value unchanged and drop the new capture value.
*/
__I uint32_t TCAP;
uint32_t RESERVE0[1];
/**
* ECTL
* ===================================================================================================
* Offset: 0x20 Timer x Extended Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EVNT_GEN_EN|Event Generator Function Enable Control
* | | |When this bit is high, timer would generate a high pulse event out when it increases the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is same as the polarity defined by EVNT_GEN_POL (TMRx_ECTL[1]).
* | | |0 = Event generator function disabled.
* | | |1 = Event generator function enabled.
* |[1] |EVNT_GEN_POL|Event Generator Reference Input Source Polarity Selection
* | | |When this bit is low and EVNT_GEN_EN (TMRx_ECTL[0]) is high, timer would generate a high pulse event out when it increases the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is low.
* | | |When this bit is high and EVNT_GEN_EN (TMRx_ECTL[0]) is high, timer would generate a low pulse event pulse out when it increases the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is high.
* | | |This bit only affects timer's operation when EVNT_GEN_EN (TMRx_ECTL[0]) is high.
* | | |0 = Timer generates a high pulse event out when it increase the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is low.
* | | |1 = Timer generates a high pulse event out when it increase the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is high.
* |[8] |EVNT_CNT_SRC|Event Counting Source Selection
* | | |This bit defines the TMRx+1 event counting source is from external event pin TMx+1 or internal signal from TMRx's event generator output (where x = 0 or 2).
* | | |0 = The event counting source is from external event pin.
* | | |1 = The event counting source is from TMRx's event generator output.
* | | |Note: This bit is only available in TMRx+1 (where x = 0 or 2).
* |[12] |EVNT_GEN_SRC|Event Generator Reference Input Source Selection
* | | |This bit defines the event generator function controlled by external event pin or internal event signals from ACMP0.
* | | |0 = The event generator reference source is from external event pin.
* | | |1 = The event generator reference source is from ACMP0.
* | | |Note: This bit is only available in TMRx (where x = 0 or 2).
* |[16] |CAP_SRC |Capture Function Source Selection
* | | |This bit defines timer counter reset function or timer capture function controlled by transition of TC pin or transition of internal signals from other functional blocks of this chip.
* | | |0 = Transition of TC pin selected.
* | | |1 = Transition of internal signals from ACMP0.
* | | |Note: When this bit is high, the EVNT_DEB_EN (TMRx_CTL[14]) would not take effect.
* |[31:24] |EVNT_DROP_CNT|Event Drop Count
* | | |This field indicates timer to drop how many events after inter-timer trigger function enable.
* | | |For example, if user writes 0x7 to this field, timer would drop 7 first incoming events and starts the inter-timer trigger operation when it get 8th event.
* | | |This field would affect timer's operation only when inter-timer trigger function enabled (INTR_TRG_EN (TMRx_CTL[24]) = 1) and ITNR_TRG_MODE (TMRx_CTL[25]) = 1.
*/
__IO uint32_t ECTL;
} TIMER_T;
/**
@addtogroup TMR_CONST TIMER Bit Field Definition
Constant Definitions for TIMER Controller
@{ */
#define TIMER_CTL_TMR_EN_Pos (0) /*!< TIMER CTL: TMR_EN Position */
#define TIMER_CTL_TMR_EN_Msk (0x1ul << TIMER_CTL_TMR_EN_Pos) /*!< TIMER CTL: TMR_EN Mask */
#define TIMER_CTL_SW_RST_Pos (1) /*!< TIMER CTL: SW_RST Position */
#define TIMER_CTL_SW_RST_Msk (0x1ul << TIMER_CTL_SW_RST_Pos) /*!< TIMER CTL: SW_RST Mask */
#define TIMER_CTL_WAKE_EN_Pos (2) /*!< TIMER CTL: WAKE_EN Position */
#define TIMER_CTL_WAKE_EN_Msk (0x1ul << TIMER_CTL_WAKE_EN_Pos) /*!< TIMER CTL: WAKE_EN Mask */
#define TIMER_CTL_DBGACK_EN_Pos (3) /*!< TIMER CTL: DBGACK_EN Position */
#define TIMER_CTL_DBGACK_EN_Msk (0x1ul << TIMER_CTL_DBGACK_EN_Pos) /*!< TIMER CTL: DBGACK_EN Mask */
#define TIMER_CTL_MODE_SEL_Pos (4) /*!< TIMER CTL: MODE_SEL Position */
#define TIMER_CTL_MODE_SEL_Msk (0x3ul << TIMER_CTL_MODE_SEL_Pos) /*!< TIMER CTL: MODE_SEL Mask */
#define TIMER_CTL_ACMP_EN_TMR_Pos (6) /*!< TIMER CTL: ACMP_EN_TMR Position */
#define TIMER_CTL_ACMP_EN_TMR_Msk (0x1ul << TIMER_CTL_ACMP_EN_TMR_Pos) /*!< TIMER CTL: ACMP_EN_TMR Mask */
#define TIMER_CTL_TMR_ACT_Pos (7) /*!< TIMER CTL: TMR_ACT Position */
#define TIMER_CTL_TMR_ACT_Msk (0x1ul << TIMER_CTL_TMR_ACT_Pos) /*!< TIMER CTL: TMR_ACT Mask */
#define TIMER_CTL_ADC_TEEN_Pos (8) /*!< TIMER CTL: ADC_TEEN Position */
#define TIMER_CTL_ADC_TEEN_Msk (0x1ul << TIMER_CTL_ADC_TEEN_Pos) /*!< TIMER CTL: ADC_TEEN Mask */
#define TIMER_CTL_DAC_TEEN_Pos (9) /*!< TIMER CTL: DAC_TEEN Position */
#define TIMER_CTL_DAC_TEEN_Msk (0x1ul << TIMER_CTL_DAC_TEEN_Pos) /*!< TIMER CTL: DAC_TEEN Mask */
#define TIMER_CTL_PDMA_TEEN_Pos (10) /*!< TIMER CTL: PDMA_TEEN Position */
#define TIMER_CTL_PDMA_TEEN_Msk (0x1ul << TIMER_CTL_PDMA_TEEN_Pos) /*!< TIMER CTL: PDMA_TEEN Mask */
#define TIMER_CTL_CAP_TRG_EN_Pos (11) /*!< TIMER CTL: CAP_TRG_EN Position */
#define TIMER_CTL_CAP_TRG_EN_Msk (0x1ul << TIMER_CTL_CAP_TRG_EN_Pos) /*!< TIMER CTL: CAP_TRG_EN Mask */
#define TIMER_CTL_EVENT_EN_Pos (12) /*!< TIMER CTL: EVENT_EN Position */
#define TIMER_CTL_EVENT_EN_Msk (0x1ul << TIMER_CTL_EVENT_EN_Pos) /*!< TIMER CTL: EVENT_EN Mask */
#define TIMER_CTL_EVENT_EDGE_Pos (13) /*!< TIMER CTL: EVENT_EDGE Position */
#define TIMER_CTL_EVENT_EDGE_Msk (0x1ul << TIMER_CTL_EVENT_EDGE_Pos) /*!< TIMER CTL: EVENT_EDGE Mask */
#define TIMER_CTL_EVNT_DEB_EN_Pos (14) /*!< TIMER CTL: EVNT_DEB_EN Position */
#define TIMER_CTL_EVNT_DEB_EN_Msk (0x1ul << TIMER_CTL_EVNT_DEB_EN_Pos) /*!< TIMER CTL: EVNT_DEB_EN Mask */
#define TIMER_CTL_TCAP_EN_Pos (16) /*!< TIMER CTL: TCAP_EN Position */
#define TIMER_CTL_TCAP_EN_Msk (0x1ul << TIMER_CTL_TCAP_EN_Pos) /*!< TIMER CTL: TCAP_EN Mask */
#define TIMER_CTL_TCAP_MODE_Pos (17) /*!< TIMER CTL: TCAP_MODE Position */
#define TIMER_CTL_TCAP_MODE_Msk (0x1ul << TIMER_CTL_TCAP_MODE_Pos) /*!< TIMER CTL: TCAP_MODE Mask */
#define TIMER_CTL_TCAP_EDGE_Pos (18) /*!< TIMER CTL: TCAP_EDGE Position */
#define TIMER_CTL_TCAP_EDGE_Msk (0x3ul << TIMER_CTL_TCAP_EDGE_Pos) /*!< TIMER CTL: TCAP_EDGE Mask */
#define TIMER_CTL_TCAP_CNT_MODE_Pos (20) /*!< TIMER CTL: TCAP_CNT_MODE Position */
#define TIMER_CTL_TCAP_CNT_MODE_Msk (0x1ul << TIMER_CTL_TCAP_CNT_MODE_Pos) /*!< TIMER CTL: TCAP_CNT_MODE Mask */
#define TIMER_CTL_TCAP_DEB_EN_Pos (22) /*!< TIMER CTL: TCAP_DEB_EN Position */
#define TIMER_CTL_TCAP_DEB_EN_Msk (0x1ul << TIMER_CTL_TCAP_DEB_EN_Pos) /*!< TIMER CTL: TCAP_DEB_EN Mask */
#define TIMER_CTL_INTR_TRG_EN_Pos (24) /*!< TIMER CTL: INTR_TRG_EN Position */
#define TIMER_CTL_INTR_TRG_EN_Msk (0x1ul << TIMER_CTL_INTR_TRG_EN_Pos) /*!< TIMER CTL: INTR_TRG_EN Mask */
#define TIMER_CTL_INTR_TRG_MODE_Pos (25) /*!< TIMER CTL: INTR_TRG_MODE Position */
#define TIMER_CTL_INTR_TRG_MODE_Msk (0x1ul << TIMER_CTL_INTR_TRG_MODE_Pos) /*!< TIMER CTL: INTR_TRG_MODE Mask */
#define TIMER_PRECNT_PRESCALE_CNT_Pos (0) /*!< TIMER PRECNT: PRESCALE_CNT Position */
#define TIMER_PRECNT_PRESCALE_CNT_Msk (0xfful << TIMER_PRECNT_PRESCALE_CNT_Pos) /*!< TIMER PRECNT: PRESCALE_CNT Mask */
#define TIMER_CMPR_TMR_CMP_Pos (0) /*!< TIMER CMPR: TMR_CMP Position */
#define TIMER_CMPR_TMR_CMP_Msk (0xfffffful << TIMER_CMPR_TMR_CMP_Pos) /*!< TIMER CMPR: TMR_CMP Mask */
#define TIMER_IER_TMR_IE_Pos (0) /*!< TIMER IER: TMR_IE Position */
#define TIMER_IER_TMR_IE_Msk (0x1ul << TIMER_IER_TMR_IE_Pos) /*!< TIMER IER: TMR_IE Mask */
#define TIMER_IER_TCAP_IE_Pos (1) /*!< TIMER IER: TCAP_IE Position */
#define TIMER_IER_TCAP_IE_Msk (0x1ul << TIMER_IER_TCAP_IE_Pos) /*!< TIMER IER: TCAP_IE Mask */
#define TIMER_ISR_TMR_IS_Pos (0) /*!< TIMER ISR: TMR_IS Position */
#define TIMER_ISR_TMR_IS_Msk (0x1ul << TIMER_ISR_TMR_IS_Pos) /*!< TIMER ISR: TMR_IS Mask */
#define TIMER_ISR_TCAP_IS_Pos (1) /*!< TIMER ISR: TCAP_IS Position */
#define TIMER_ISR_TCAP_IS_Msk (0x1ul << TIMER_ISR_TCAP_IS_Pos) /*!< TIMER ISR: TCAP_IS Mask */
#define TIMER_ISR_TMR_WAKE_STS_Pos (4) /*!< TIMER ISR: TMR_WAKE_STS Position */
#define TIMER_ISR_TMR_WAKE_STS_Msk (0x1ul << TIMER_ISR_TMR_WAKE_STS_Pos) /*!< TIMER ISR: TMR_WAKE_STS Mask */
#define TIMER_ISR_NCAP_DET_STS_Pos (5) /*!< TIMER ISR: NCAP_DET_STS Position */
#define TIMER_ISR_NCAP_DET_STS_Msk (0x1ul << TIMER_ISR_NCAP_DET_STS_Pos) /*!< TIMER ISR: NCAP_DET_STS Mask */
#define TIMER_ISR_TCAP_IS_FEDGE_Pos (6) /*!< TIMER ISR: TCAP_IS_FEDGE Position */
#define TIMER_ISR_TCAP_IS_FEDGE_Msk (0x1ul << TIMER_ISR_TCAP_IS_FEDGE_Pos) /*!< TIMER ISR: TCAP_IS_FEDGE Mask */
#define TIMER_DR_TDR_Pos (0) /*!< TIMER DR: TDR Position */
#define TIMER_DR_TDR_Msk (0xfffffful << TIMER_DR_TDR_Pos) /*!< TIMER DR: TDR Mask */
#define TIMER_DR_RSTACT_Pos (31) /*!< TIMER DR: RSTACT Position */
#define TIMER_DR_RSTACT_Msk (0x1ul << TIMER_DR_RSTACT_Pos) /*!< TIMER DR: RSTACT Mask */
#define TIMER_TCAP_CAP_Pos (0) /*!< TIMER TCAP: CAP Position */
#define TIMER_TCAP_CAP_Msk (0xfffffful << TIMER_TCAP_CAP_Pos) /*!< TIMER TCAP: CAP Mask */
#define TIMER_ECTL_EVNT_GEN_EN_Pos (0) /*!< TIMER ECTL: EVNT_GEN_EN Position */
#define TIMER_ECTL_EVNT_GEN_EN_Msk (0x1ul << TIMER_ECTL_EVNT_GEN_EN_Pos) /*!< TIMER ECTL: EVNT_GEN_EN Mask */
#define TIMER_ECTL_EVNT_GEN_POL_Pos (1) /*!< TIMER ECTL: EVNT_GEN_POL Position */
#define TIMER_ECTL_EVNT_GEN_POL_Msk (0x1ul << TIMER_ECTL_EVNT_GEN_POL_Pos) /*!< TIMER ECTL: EVNT_GEN_POL Mask */
#define TIMER_ECTL_EVNT_CNT_SRC_Pos (8) /*!< TIMER ECTL: EVNT_CNT_SRC Position */
#define TIMER_ECTL_EVNT_CNT_SRC_Msk (0x1ul << TIMER_ECTL_EVNT_CNT_SRC_Pos) /*!< TIMER ECTL: EVNT_CNT_SRC Mask */
#define TIMER_ECTL_EVNT_GEN_SRC_Pos (12) /*!< TIMER ECTL: EVNT_GEN_SRC Position */
#define TIMER_ECTL_EVNT_GEN_SRC_Msk (0x1ul << TIMER_ECTL_EVNT_GEN_SRC_Pos) /*!< TIMER ECTL: EVNT_GEN_SRC Mask */
#define TIMER_ECTL_CAP_SRC_Pos (16) /*!< TIMER ECTL: CAP_SRC Position */
#define TIMER_ECTL_CAP_SRC_Msk (0x1ul << TIMER_ECTL_CAP_SRC_Pos) /*!< TIMER ECTL: CAP_SRC Mask */
#define TIMER_ECTL_EVNT_DROP_CNT_Pos (24) /*!< TIMER ECTL: EVNT_DROP_CNT Position */
#define TIMER_ECTL_EVNT_DROP_CNT_Msk (0xfful << TIMER_ECTL_EVNT_DROP_CNT_Pos) /*!< TIMER ECTL: EVNT_DROP_CNT Mask */
/**@}*/ /* TMR_CONST */
/**@}*/ /* end of TMR register group */
/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
/**
@addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
Memory Mapped Structure for UART Controller
@{ */
typedef struct {
union {
/**
* RBR
* ===================================================================================================
* Offset: 0x00 UART Receive Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |RBR |Receiving Buffer
* | | |By reading this register, the UART Controller will return an 8-bit data received from RX pin (LSB first).
*/
__I uint32_t RBR;
/**
* THR
* ===================================================================================================
* Offset: 0x00 UART Transmit Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |THR |Transmit Buffer
* | | |By writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first).
*/
__O uint32_t THR;
};
/**
* CTL
* ===================================================================================================
* Offset: 0x04 UART Control State Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RX_RST |RX Software Reset
* | | |When RX_RST is set, all the bytes in the receiving FIFO and RX internal state machine are cleared.
* | | |0 = No effect.
* | | |1 = Reset the RX internal state machine and pointers.
* | | |Note: This bit will be auto cleared and take at least 3 UART engine clock cycles.
* |[1] |TX_RST |TX Software Reset
* | | |When TX_RST is set, all the bytes in the transmitting FIFO and TX internal state machine are cleared.
* | | |0 = No effect.
* | | |1 = Reset the TX internal state machine and pointers.
* | | |Note: This bit will be auto cleared and take at least 3 UART engine clock cycles.
* |[2] |RX_DIS |Receiver Disable Register
* | | |The receiver is disabled or not (set "1" to disable receiver)
* | | |0 = Receiver Enabled.
* | | |1 = Receiver Disabled.
* | | |Note1: In RS-485 NMM mode, user can set this bit to receive data before detecting address byte.
* | | |Note2: In RS-485 AAD mode, this bit will be setting to "1" automatically.
* | | |Note3: In RS-485 AUD mode and LIN "break + sync +PID" header mode, hardware will control data automatically, so don't fill any value to this bit.
* |[3] |TX_DIS |Transfer Disable Register
* | | |The transceiver is disabled or not (set "1" to disable transceiver)
* | | |0 = Transfer Enabled.
* | | |1 = Transfer Disabled.
* |[4] |AUTO_RTS_EN|RTSn Auto-Flow Control Enable
* | | |0 = RTSn auto-flow control. Disabled.
* | | |1 = RTSn auto-flow control Enabled.
* | | |Note: When RTSn auto-flow is enabled, if the number of bytes in the RX-FIFO equals the UART_FCR [RTS_Tri_Lev], the UART will reassert RTSn signal.
* |[5] |AUTO_CTS_EN|CTSn Auto-Flow control Enable
* | | |0 = CTSn auto-flow control Disabled
* | | |1 = CTSn auto-flow control Enabled.
* | | |Note: When CTSn auto-flow is enabled, the UART will send data to external device when CTSn input assert (UART will not send data to device until CTSn is asserted).
* |[6] |DMA_RX_EN |RX DMA Enable
* | | |This bit can enable or disable RX PDMA service.
* | | |0 = RX PDMA service function Disabled.
* | | |1 = RX PDMA service function Enabled.
* |[7] |DMA_TX_EN |TX DMA Enable
* | | |This bit can enable or disable TX PDMA service.
* | | |0 = TX PDMA service function Disabled.
* | | |1 = TX PDMA service function Enabled.
* |[8] |WAKE_CTS_EN|CTSn Wake-Up Function Enable
* | | |0 = CTSn wake-up system function Disabled.
* | | |1 = Wake-up function Enabled when the system is in power-down mode, an external CTSn change will wake-up system from power-down mode.
* |[9] |WAKE_DATA_EN|Incoming Data Wake-Up Function Enable
* | | |0 = Incoming data wake-up system Disabled.
* | | |1 = Incoming data wake-up function Enabled when the system is in power-down mode, incoming data will wake-up system from power-down mode.
* | | |Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable
* |[12] |ABAUD_EN |Auto-Baud Rate Detect Enable
* | | |0 = Auto-baud rate detect function Disabled.
* | | |1 = Auto-baud rate detect function Enabled.
* | | |Note: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (INT_ABAUD) will be generated (If ABAUD_IE (UART_IER [7]) be enabled).
* |[17] |WAKE_THRESH_EN|FIFO Threshold Reach Wake-Up Function Enable Control
* | | |0 = Received FIFO threshold reach wake-up function Disabled.
* | | |1 = Received FIFO threshold reach wake-up function Enabled when the system is in power-down mode.
* |[18] |WAKE_RS485_AAD_EN|RS-485 Address Match Wake-Up Function Enable Control
* | | |0 = RS-485 ADD mode address match wake-up function Disabled.
* | | |1 = RS-485 AAD mode address match wake-up function Enabled when the system is in power-down mode.
* |[26:24] |PWM_SEL |PWM Channel Select For Modulation
* | | |Select the PWM channel to modulate with the UART transmit bus.
* | | |000 = PWM channel 0 modulate with UART TX.
* | | |001 = PWM channel 1 modulate with UART TX.
* | | |010 = PWM channel 2 modulate with UART TX.
* | | |011 = PWM channel 3 modulate with UART TX.
* | | |The others, no modulation of UART with PWM
*/
__IO uint32_t CTL;
/**
* TLCTL
* ===================================================================================================
* Offset: 0x08 UART Transfer Line Control Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |DATA_LEN |Data Length
* | | |00 = 5 bits.
* | | |01 = 6 bits.
* | | |10 = 7 bits.
* | | |11 = 8 bits.
* |[2] |NSB |Number Of STOP Bit Length
* | | |1 = 1.5 "STOP bit" is generated in the transmitted data when 5-bit word length is selected, and 2 STOP bit" is generated when 6, 7 and 8 bits data length is selected.
* | | |0 = 1 " STOP bit" is generated in the transmitted data.
* |[3] |PBE |Parity Bit Enable
* | | |1 = Parity bit is generated or checked between the "last data"word "it" and "stop bit" of the serial data.
* | | |0 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
* |[4] |EPE |Even Parity Enable
* | | |1 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
* | | |0 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
* | | |Note: This bit has effect only when PBE bit (parity bit enable) is set.
* |[5] |SPE |Stick Parity Enable
* | | |1 = When bits PBE, EPE and SPE are set, the parity bit is transmitted and checked as "0".
* | | |When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as "1".
* | | |In RS-485 mode, PBE, EPE and SPE can control bit 9.
* | | |0 = Stick parity Disabled.
* |[6] |BCB |Break Control Bit
* | | |When this bit is set to logic "1", the serial data output (TX) is forced to the Spacing State (logic "0").
* | | |This bit acts only on TX pin and has no effect on the transmitter logic.
* | | |1 = Break control Enabled.
* | | |0 = Break control Disabled.
* |[9:8] |RFITL |RX-FIFO Interrupt (INT_RDA) Trigger Level
* | | |When the number of bytes in the receiving FIFO is equal to the RFITL then the RDA_IF will be set (if RDA_IE(IER[0]) is enabled, an interrupt will be generated)
* | | |00 = RX FIFO Interrupt Trigger Level is 1 byte.
* | | |01 = RX FIFO Interrupt Trigger Level is 4 bytes.
* | | |10 = RX FIFO Interrupt Trigger Level is 8 bytes.
* | | |11 = RX FIFO Interrupt Trigger Level is 14 bytes.
* | | |Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to "0".
* |[13:12] |RTS_TRI_LEV|RTSn Trigger Level (For Auto-Flow Control Use)
* | | |00 = RTS Trigger Level is 1 byte.
* | | |01 = RTS Trigger Level is 4 bytes.
* | | |10 = RTS Trigger Level is 8 bytes.
* | | |11 = RTS Trigger Level is 14 bytes.
* | | |Note: This field is used for auto RTSn flow control.
*/
__IO uint32_t TLCTL;
/**
* IER
* ===================================================================================================
* Offset: 0x0C UART Interrupt Enable Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDA_IE |Receive Data Available Interrupt Enable
* | | |0 = INT_RDA Masked off.
* | | |1 = INT_RDA Enabled.
* |[1] |THRE_IE |Transmit Holding Register Empty Interrupt Enable
* | | |0 = INT_THRE Masked off.
* | | |1 = INT_THRE Enabled.
* |[2] |RLS_IE |Receive Line Status Interrupt Enable
* | | |0 = INT_RLS Masked off.
* | | |1 = INT_RLS Enabled.
* |[3] |MODEM_IE |Modem Status Interrupt Enable
* | | |0 = INT_MOS Masked off.
* | | |1 = INT_MOS Enabled.
* |[4] |RTO_IE |RX Time-Out Interrupt Enable
* | | |0 = INT_TOUT Masked off.
* | | |1 = INT_TOUT Enabled.
* |[5] |BUF_ERR_IE|Buffer Error Interrupt Enable
* | | |0 = INT_BUT_ERR Masked off.
* | | |1 = INT_BUF_ERR Enabled.
* |[6] |WAKE_IE |Wake-Up Interrupt Enable
* | | |0 = INT_WAKE Masked off.
* | | |1 = INT_WAKE Enabled.
* |[7] |ABAUD_IE |Auto-Baud Rate Interrupt Enable
* | | |0 = INT_ABAUD Masked off.
* | | |1 = INT_ABAUD Enabled.
* |[8] |LIN_IE |LIN Interrupt Enable
* | | |0 = INT_LIN Masked off.
* | | |1 = INT_LIN Enabled.
*/
__IO uint32_t IER;
/**
* ISR
* ===================================================================================================
* Offset: 0x10 UART Interrupt Status Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDA_IS |Receive Data Available Interrupt Flag (Read Only)
* | | |When the number of bytes in the RX-FIFO equals the RFITL then the RDA_IF will be set.
* | | |If RDA_IEN (UART_IER[0]) is set then the RDA interrupt will be generated.
* | | |0 = No Receive Data available interrupt is generated.
* | | |1 = Receive Data available interrupt is generated.
* | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX-FIFO drops below the threshold level (RFITL).
* |[1] |THRE_IS |Transmit Holding Register Empty Interrupt Flag (Read Only)
* | | |This bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register.
* | | |If THRE_IEN (UART_IER[1]) is set that the THRE interrupt will be generated.
* | | |0 = No Transmit Holding register empty interrupt is generated.
* | | |1 = Transmit Holding register empty interrupt generated.
* | | |Note: This bit is read only and it will be cleared when writing data into THR (TX-FIFO not empty).
* |[2] |RLS_IS |Receive Line Interrupt Status Flag (Read Only)
* | | |This bit is set when the RX received data has parity error (PE_F (UART_FSR[4])), framing error (FE_F (UART_FSR[5])), break error (BI_F (UART_FSR[6])) or RS-485 detect address byte (RS-485_ADDET_F (UART_TRSR[0])).If RLS_IE (UART_IER[2]) is set then the RLS interrupt will be generated.
* | | |0 = No Receive Line interrupt is generated.
* | | |1 = Receive Line interrupt is generated.
* | | |Note1: This bit is read only, but can be cleared by it by writing "1" to BI_F (UART_FSR[6]), FE_F (UART_FSR[5]), PE_F (UART_FSR[4]) or RS-485_ADDET_F (UART_TRSR[0]).
* | | |Note2: This bit is cleared when the BI_F, FE_F, PE_F and RS-485_ADDET_F are cleared.
* |[3] |MODEM_IS |MODEM Interrupt Status Flag (Read Only)
* | | |This bit is set when the CTSn pin has state change (DCTSF = "1").
* | | |If MODEM_IEN (UART_IER[3]) is set then the modem interrupt will be generated.
* | | |0 = No MODEM interrupt is generated.
* | | |1 = MODEM interrupt is generated.
* | | |Note: This bit is read only, but can be cleared by it by writing "1" to DCT_F (UART_MCSR[18]).
* |[4] |RTO_IS |RX Time-Out Interrupt Status Flag (Read Only)
* | | |This bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC.
* | | |If RTO_IE (UART_IER[4]) is set then the tout interrupt will be generated.
* | | |0 = No RX Time-Out interrupt is generated.
* | | |1 = RX Time-Out interrupt is generated.
* | | |Note: This bit is read only and user can read UART_RBR (RX is in active) to clear it.
* |[5] |BUF_ERR_IS|Buffer Error Interrupt Status Flag (Read Only)
* | | |This bit is set when the TX or RX-FIFO overflowed.
* | | |When BUF_ERR_IS is set, the transfer maybe not correct.
* | | |If BUF_ERR_IE (UART_IER[5]) is set then the buffer error interrupt will be generated.
* | | |0 = No Buffer error interrupt is generated.
* | | |1 = Buffer error interrupt is generated.
* | | |Note1: This bit is read only, but can be cleared by it by writing "1" to TX_OVER_F (UART_FSR[8]) or RX_OVER_F (UART_FSR[0]).
* | | |Note2: This bit is cleared when both the TX_OVER_F and RX_OVER_F are cleared.
* |[6] |WAKE_IS |Wake-Up Interrupt Status Flag (Read Only)
* | | |This bit is set in Power-down mode, the receiver received data or CTSn signal.
* | | |If WAKE_IE (UART_IER[6]) is set then the wake-up interrupt will be generated.
* | | |0 = No Wake-Up interrupt is generated.
* | | |1 = Wake-Up interrupt is generated.
* | | |Note: This bit is read only, but can be cleared by it by writing "1" to it.
* |[7] |ABAUD_IS |Auto-Baud Rate Interrupt Status Flag (Read Only)
* | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABAUD_IE (UART_IER[7]) is set then the auto-baud rate interrupt will be generated.
* | | |0 = No Auto-Baud Rate interrupt is generated.
* | | |1 = Auto-Baud Rate interrupt is generated.
* | | |Note1: This bit is read only, but can be cleared by it by writing "1" to ABAUD_TOUT_F (UART_TRSR[2]) or ABAUD_F (UART_TRSR[1]).
* | | |Note2: This bit is cleared when both the ABAUD_TOUT_F and ABAUD_F are cleared.
* |[8] |LIN_IS |LIN Interrupt Status Flag (Read Only)
* | | |This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LIN_IE(UART_IER[8]) is set then the LIN interrupt will be generated.
* | | |0 = No LIN interrupt is generated.
* | | |1 = LIN interrupt is generated.
* | | |Note1: This bit is read only, but can be cleared by it by writing "1" to BIT_ERR_F (UART_TRSR[5]), LIN_TX_F (UART_TRSR[3]) or LIN_RX_F (UART_TRSR[4]).
* | | |Note2: This bit is cleared when both the BIT_ERR_F, LIN_TX_F and LIN_RX_F are cleared.
*/
__IO uint32_t ISR;
/**
* TRSR
* ===================================================================================================
* Offset: 0x14 UART Transfer State Status Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RS485_ADDET_F|RS-485 Address Byte Detection Status Flag (Read Only)
* | | |This bit is set to logic "1" and set RS-485_ADD_EN (UART_ALT_CTL[19]) whenever in RS-485 mode the receiver detected any address byte character (bit 9 ='1') bit".
* | | |This bit is reset whenever the CPU writes "1" to this bit.
* | | |0 = No RS-485 address detection interrupt is generated.
* | | |1 = RS-485 address detection interrupt is generated.
* | | |Note1: This field is used for RS-485 mode.
* | | |Note2: This bit is read only, but can be cleared by writing "1" to it.
* |[1] |ABAUD_F |Auto-Baud Rate Interrupt (Read Only)
* | | |This bit is set to logic "1" when auto-baud rate detect function finished.
* | | |0 = No Auto- Baud Rate interrupt is generated.
* | | |1= Auto-Baud Rate interrupt is generated.
* | | |Note: This bit is read only, but can be cleared by writing "1" to it.
* |[2] |ABAUD_TOUT_F|Auto-Baud Rate Time-Out Interrupt (Read Only)
* | | |This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.
* | | |0 = No Auto-Baud Rate Time-Out interrupt is generated.
* | | |1 = Auto-Baud Rate Time-Out interrupt is generated.
* | | |Note: This bit is read only, but can be cleared by writing "1" to it.
* |[3] |LIN_TX_F |LIN TX Interrupt Flag (Read Only)
* | | |This bit is set to logic "1" when LIN transmitted header field.
* | | |The header may be "break field" or "break field + sync field" or "break field + sync field + PID field", it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register.
* | | |0 = No LIN Tx interrupt is generated.
* | | |1 = LIN Tx interrupt is generated.
* | | |Note: This bit is read only, but can be cleared by writing "1" to it.
* |[4] |LIN_RX_F |LIN RX Interrupt Flag (Read Only)
* | | |This bit is set to logic "1" when received LIN header field.
* | | |The header may be "break field" or "break field + sync field" or "break field + sync field + PID field", and it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register.
* | | |0 = No LIN Rx interrupt is generated.
* | | |1 = LIN Rx interrupt is generated.
* | | |Note: This bit is read only, but can be cleared by writing "1" to it.
* |[5] |BIT_ERR_F |Bit Error Detect Status Flag (Read Only)
* | | |At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BIT_ERR_F will be set.
* | | |When occur bit error, hardware will generate an interrupt to CPU (INT_LIN).
* | | |0 = No Bit error interrupt is generated.
* | | |1 = Bit error interrupt is generated.
* | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
* | | |Note2: This bit is only valid when enabling the bit error detection function (BIT_ERR_EN (UART_ALT_CTL[8]) = "1").
* |[8] |LIN_RX_SYNC_ERR_F|LIN RX SYNC Error Flag (Read Only)
* | | |This bit is set to logic "1" when LIN received incorrect SYNC field.
* | | |User can choose the header by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register.
* | | |0 = No LIN Rx sync error is generated.
* | | |1 = LIN Rx sync error is generated.
* | | |Note: This bit is read only, but can be cleared by writing "1" to LIN_RX_F.
*/
__IO uint32_t TRSR;
/**
* FSR
* ===================================================================================================
* Offset: 0x18 UART FIFO State Status Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RX_OVER_F |RX Overflow Error Status Flag (Read Only)
* | | |This bit is set when RX-FIFO overflow.
* | | |If the number of bytes of received data is greater than RX-FIFO (UART_RBR) size, 16 bytes of UART0/UART1, this bit will be set.
* | | |0 = RX FIFO is not overflow.
* | | |1 = RX FIFO is overflow.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
* |[1] |RX_EMPTY_F|Receiver FIFO Empty (Read Only)
* | | |This bit initiate RX-FIFO empty or not.
* | | |When the last byte of RX-FIFO has been read by CPU, hardware sets this bit high.
* | | |It will be cleared when UART receives any new data.
* | | |0 = RX FIFO is not empty.
* | | |1 = RX FIFO is empty.
* |[2] |RX_FULL_F |Receiver FIFO Full (Read Only)
* | | |This bit initiates RX-FIFO full or not.
* | | |This bit is set when RX_POINTER_F is equal to 16, otherwise is cleared by hardware.
* | | |0 = RX FIFO is not full.
* | | |1 = RX FIFO is full.
* |[4] |PE_F |Parity Error State Status Flag (Read Only)
* | | |This bit is set to logic "1" whenever the received character does not have a valid "parity bit", and it is reset whenever the CPU writes "1" to this bit.
* | | |0 = No parity error is generated.
* | | |1 = Parity error is generated.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
* |[5] |FE_F |Framing Error Status Flag (Read Only)
* | | |This bit is set to logic "1" whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic "0"), and it is reset whenever the CPU writes "1" to this bit.
* | | |0 = No framing error is generated.
* | | |1 = Framing error is generated.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
* |[6] |BI_F |Break Status Flag (Read Only)
* | | |This bit is set to a logic "1" whenever the received data input(RX) is held in the "spacing state" (logic "0") for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and it is reset whenever the CPU writes "1" to this bit.
* | | |0 = No Break interrupt is generated.
* | | |1 = Break interrupt is generated.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
* |[8] |TX_OVER_F |TX Overflow Error Interrupt Status Flag (Read Only)
* | | |If TX-FIFO (UART_THR) is full, an additional write to UART_THR will cause this bit to logic "1".
* | | |0 = TX FIFO is not overflow.
* | | |1 = TX FIFO is overflow.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
* |[9] |TX_EMPTY_F|Transmitter FIFO Empty (Read Only)
* | | |This bit indicates TX-FIFO empty or not.
* | | |When the last byte of TX-FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
* | | |It will be cleared when writing data into THR (TX-FIFO not empty).
* | | |0 = TX FIFO is not empty.
* | | |1 = TX FIFO is empty.
* |[10] |TX_FULL_F |Transmitter FIFO Full (Read Only)
* | | |This bit indicates TX-FIFO full or not.
* | | |This bit is set when TX_POINTER_F is equal to 16, otherwise is cleared by hardware.
* | | |0 = TX FIFO is not full.
* | | |1 = TX FIFO is full.
* |[11] |TE_F |Transmitter Empty Status Flag (Read Only)
* | | |Bit is set by hardware when TX is inactive. (TX shift register does not have data)
* | | |Bit is cleared automatically when TX-FIFO is transfer data to TX shift register or TX is empty but the transfer does not finish.
* | | |0 = TX FIFO is not empty.
* | | |1 = TX FIFO is empty.
* |[20:16] |RX_POINTER_F|RX-FIFO Pointer (Read Only)
* | | |This field indicates the RX-FIFO Buffer Pointer.
* | | |When UART receives one byte from external device, RX_POINTER_F increases one.
* | | |When one byte of RX-FIFO is read by CPU, RX_POINTER_F decreases one.
* |[28:24] |TX_POINTER_F|TX-FIFO Pointer (Read Only)
* | | |This field indicates the TX-FIFO Buffer Pointer.
* | | |When CPU writes one byte data into UART_THR, TX_POINTER_F increases one.
* | | |When one byte of TX-FIFO is transferred to Transmitter Shift Register, TX_POINTER_F decreases one.
*/
__IO uint32_t FSR;
/**
* MCSR
* ===================================================================================================
* Offset: 0x1C UART Modem State Status Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LEV_RTS |RTSn Trigger Level
* | | |This bit can change the RTSn trigger level.
* | | |0 = low level triggered.
* | | |1 = high level triggered.
* | | |Note: In RS-485 AUD mode and RTS Auto-flow control mode, hardware will control the output RTS pin automatically, so the table indicates the default value.
* | | |Note: The default setting in UART mode is LEV_RTS = "0" and RTS_ST = "1".
* |[1] |RTS_ST |RTSn Pin State (Read Only)
* | | |This bit is the pin status of RTSn.
* | | |0 = RTS pin input is low level voltage logic state.
* | | |1 = RTS pin input is high level voltage logic state.
* |[16] |LEV_CTS |CTSn Trigger Level
* | | |This bit can change the CTSn trigger level.
* | | |0 = Low level triggered.
* | | |1 = High level triggered.
* |[17] |CTS_ST |CTSn Pin Status (Read Only)
* | | |This bit is the pin status of CTSn.
* | | |0 = CTS pin input is low level voltage logic state.
* | | |1 = CTS pin input is high level voltage logic state.
* |[18] |DCT_F |Detect CTSn State Change Status Flag (Read Only)
* | | |This bit is set whenever CTSn input has change state, and it will generate Modem interrupt to CPU when MODEM_IE (UART_IER[3]).
* | | |0 = CTS input has not change state.
* | | |1 = CTS input has change state.
* | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
*/
__IO uint32_t MCSR;
/**
* TMCTL
* ===================================================================================================
* Offset: 0x20 UART Time-Out Control State Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |TOIC |Time-Out Comparator
* | | |The time-out counter resets and starts counting whenever the RX-FIFO receives a new data word.
* | | |Note1: Fill all "0" to this field indicates to disable this function.
* | | |Note2: The real time-out value is TOIC + 1.
* | | |Note3: The counting clock is baud rate clock.
* | | |Note4: The UART data format is start bit + 8 data bits + parity bit + stop bit, although software can configure this field by any value but it is recommend to filled this field great than 0xA.
* |[23:16] |DLY |TX Delay Time Value
* | | |This field is use to program the transfer delay time between the last stop bit and next start bit.
* | | |Note1: Fill all "0" to this field indicates to disable this function.
* | | |Note2: The real delay value is DLY.
* | | |Note3: The counting clock is baud rate clock.
*/
__IO uint32_t TMCTL;
/**
* BAUD
* ===================================================================================================
* Offset: 0x24 UART Baud Rate Divisor Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |BRD |Baud Rate Divider
* |[31] |DIV_16_EN |Divider 16 Enable
* | | |The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = UART_CLK/ [16 * (BRD + 1)];
* | | |0 = The equation of baud rate is UART_CLK / [ (BRD+1)].
* | | |1 = The equation of baud rate is UART_CLK / [16 * (BRD+1)].
* | | |Note: In IrDA mode, this bit must disable.
*/
__IO uint32_t BAUD;
uint32_t RESERVE0[2];
/**
* IRCR
* ===================================================================================================
* Offset: 0x30 UART IrDA Control Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TX_SELECT |TX_SELECT
* | | |0 = IrDA receiver Enabled.
* | | |1 = IrDA transmitter Enabled.
* | | |Note: In IrDA mode, the DIV_16_EN (UART_BAUD[31]) register must be set (the baud equation must be Clock / 16 * (BRD)
* |[5] |INV_TX |INV_TX
* | | |0 = No inversion.
* | | |1 = Inverse TX output signal.
* |[6] |INV_RX |INV_RX
* | | |0 = No inversion.
* | | |1 = Inverse RX input signal.
*/
__IO uint32_t IRCR;
/**
* ALT_CTL
* ===================================================================================================
* Offset: 0x34 UART Alternate Control State Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |LIN_TX_BCNT|LIN TX Break Field Count Register
* | | |The field contains 3-bit LIN TX break field count.
* | | |Note: The break field length is LIN_TX_BCNT + 8.
* |[5:4] |LIN_HEAD_SEL|LIN Header Selection
* | | |00 = The LIN header includes "break field".
* | | |01 = The LIN header includes "break field + sync field".
* | | |10 = The LIN header includes "break field + sync field + PID field".
* | | |11 = Reserved.
* |[6] |LIN_RX_EN |LIN RX Enable
* | | |When LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (INT_LIN)
* | | |0 = LIN RX mode Disabled.
* | | |1 = LIN RX mode Enabled.
* |[7] |LIN_TX_EN |LIN TX Header Trigger Enable
* | | |0 = LIN TX Header Trigger Disabled.
* | | |1 = LIN TX Header Trigger Enabled.
* | | |Note1: This bit will be cleared automatically and generate a interrupt to CPU (INT_LIN).
* | | |Note2: If user wants to receive transmit data, it recommended to enable LIN_RX_EN bit.
* |[8] |BIT_ERR_EN|Bit Error Detect Enable
* | | |0 = Bit error detection Disabled.
* | | |1 = Bit error detection Enabled.
* | | |Note: In LIN function mode, when bit error occurs, hardware will generate an interrupt to CPU (INT_LIN).
* |[16] |RS485_NMM |RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode)
* | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
* | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
* | | |Note: It can't be active in RS-485_AAD Operation mode.
* |[17] |RS485_AAD |RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode)
* | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
* | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
* | | |Note: It can't be active in RS-485_NMM Operation mode.
* |[18] |RS485_AUD |RS-485 Auto Direction Mode (RS-485 AUD Mode)
* | | |0 = RS-485 Auto Direction mode (AUD) Disabled.
* | | |1 = RS-485 Auto Direction mode (AUD) Enabled.
* | | |Note: It can be active in RS-485_AAD or RS-485_NMM operation mode.
* |[19] |RS485_ADD_EN|RS-485 Address Detection Enable
* | | |This bit is used to enable RS-485 hardware address detection mode.
* | | |If hardware detects address byte, and then the controller will set UART_TRSR [RS485_ADDET_F] = "1".
* | | |0 = Address detection mode Disabled.
* | | |1 = Address detection mode Enabled.
* | | |Note: This field is used for RS-485 any operation mode.
* |[31:24] |ADDR_PID_MATCH|Address / PID Match Value Register
* | | |This field contains the RS-485 address match values in RS-485 Function mode.
* | | |This field contains the LIN protected identifier field n LIN Function mode, software fills ID0~ID5 (ADDR_PID_MATCH [5:0]), hardware will calculate P0 and P1.
* | | |Note: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID).
*/
__IO uint32_t ALT_CTL;
/**
* FUN_SEL
* ===================================================================================================
* Offset: 0x38 UART Function Select Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |FUN_SEL |Function Select Enable
* | | |00 = UART function mode.
* | | |01 = LIN function mode.
* | | |10 = IrDA Function.
* | | |11 = RS-485 Function.
*/
__IO uint32_t FUN_SEL;
/**
* BR_COMP
* ===================================================================================================
* Offset: 0x3C UART Baud Rate Compensation
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |BR_COMP |Baud Rate Compensation Patten
* | | |These 9-bits are used to define the relative bit is compensated or not.
* | | |BR_COMP[7:0] is used to define the compensation of UART data[7:0] and BR_COM[8] is used to define the parity bit.
* |[31] |BR_COMP_DEC|Baud Rate Compensation Decrease
* | | |0 = Positive (increase one module clock) compensation for each compensated bit.
* | | |1 = Negative (decrease one module clock) compensation for each compensated bit.
*/
__IO uint32_t BR_COMP;
} UART_T;
/**
@addtogroup UART_CONST UART Bit Field Definition
Constant Definitions for UART Controller
@{ */
#define UART_DAT_DAT_Pos (0) /*!< UART DAT: DAT Position */
#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART DAT: DAT Mask */
#define UART_CTL_RX_RST_Pos (0) /*!< UART CTL: RX_RST Position */
#define UART_CTL_RX_RST_Msk (0x1ul << UART_CTL_RX_RST_Pos) /*!< UART CTL: RX_RST Mask */
#define UART_CTL_TX_RST_Pos (1) /*!< UART CTL: TX_RST Position */
#define UART_CTL_TX_RST_Msk (0x1ul << UART_CTL_TX_RST_Pos) /*!< UART CTL: TX_RST Mask */
#define UART_CTL_RX_DIS_Pos (2) /*!< UART CTL: RX_DIS Position */
#define UART_CTL_RX_DIS_Msk (0x1ul << UART_CTL_RX_DIS_Pos) /*!< UART CTL: RX_DIS Mask */
#define UART_CTL_TX_DIS_Pos (3) /*!< UART CTL: TX_DIS Position */
#define UART_CTL_TX_DIS_Msk (0x1ul << UART_CTL_TX_DIS_Pos) /*!< UART CTL: TX_DIS Mask */
#define UART_CTL_AUTO_RTS_EN_Pos (4) /*!< UART CTL: AUTO_RTS_EN Position */
#define UART_CTL_AUTO_RTS_EN_Msk (0x1ul << UART_CTL_AUTO_RTS_EN_Pos) /*!< UART CTL: AUTO_RTS_EN Mask */
#define UART_CTL_AUTO_CTS_EN_Pos (5) /*!< UART CTL: AUTO_CTS_EN Position */
#define UART_CTL_AUTO_CTS_EN_Msk (0x1ul << UART_CTL_AUTO_CTS_EN_Pos) /*!< UART CTL: AUTO_CTS_EN Mask */
#define UART_CTL_DMA_RX_EN_Pos (6) /*!< UART CTL: DMA_RX_EN Position */
#define UART_CTL_DMA_RX_EN_Msk (0x1ul << UART_CTL_DMA_RX_EN_Pos) /*!< UART CTL: DMA_RX_EN Mask */
#define UART_CTL_DMA_TX_EN_Pos (7) /*!< UART CTL: DMA_TX_EN Position */
#define UART_CTL_DMA_TX_EN_Msk (0x1ul << UART_CTL_DMA_TX_EN_Pos) /*!< UART CTL: DMA_TX_EN Mask */
#define UART_CTL_WAKE_CTS_EN_Pos (8) /*!< UART CTL: WAKE_CTS_EN Position */
#define UART_CTL_WAKE_CTS_EN_Msk (0x1ul << UART_CTL_WAKE_CTS_EN_Pos) /*!< UART CTL: WAKE_CTS_EN Mask */
#define UART_CTL_WAKE_DATA_EN_Pos (9) /*!< UART CTL: WAKE_DATA_EN Position */
#define UART_CTL_WAKE_DATA_EN_Msk (0x1ul << UART_CTL_WAKE_DATA_EN_Pos) /*!< UART CTL: WAKE_DATA_EN Mask */
#define UART_CTL_ABAUD_EN_Pos (12) /*!< UART CTL: ABAUD_EN Position */
#define UART_CTL_ABAUD_EN_Msk (0x1ul << UART_CTL_ABAUD_EN_Pos) /*!< UART CTL: ABAUD_EN Mask */
#define UART_CTL_WAKE_THRESH_EN_Pos (17) /*!< UART CTL: WAKE_THRESH_EN Position */
#define UART_CTL_WAKE_THRESH_EN_Msk (0x1ul << UART_CTL_WAKE_THRESH_EN_Pos) /*!< UART CTL: WAKE_THRESH_EN Mask */
#define UART_CTL_WAKE_RS485_AAD_EN_Pos (18) /*!< UART CTL: WAKE_RS485_AAD_EN Position */
#define UART_CTL_WAKE_RS485_AAD_EN_Msk (0x1ul << UART_CTL_WAKE_RS485_AAD_EN_Pos) /*!< UART CTL: WAKE_RS485_AAD_EN Mask */
#define UART_CTL_PWM_SEL_Pos (24) /*!< UART CTL: PWM_SEL Position */
#define UART_CTL_PWM_SEL_Msk (0x7ul << UART_CTL_PWM_SEL_Pos) /*!< UART CTL: PWM_SEL Mask */
#define UART_TLCTL_DATA_LEN_Pos (0) /*!< UART TLCTL: DATA_LEN Position */
#define UART_TLCTL_DATA_LEN_Msk (0x3ul << UART_TLCTL_DATA_LEN_Pos) /*!< UART TLCTL: DATA_LEN Mask */
#define UART_TLCTL_NSB_Pos (2) /*!< UART TLCTL: NSB Position */
#define UART_TLCTL_NSB_Msk (0x1ul << UART_TLCTL_NSB_Pos) /*!< UART TLCTL: NSB Mask */
#define UART_TLCTL_PBE_Pos (3) /*!< UART TLCTL: PBE Position */
#define UART_TLCTL_PBE_Msk (0x1ul << UART_TLCTL_PBE_Pos) /*!< UART TLCTL: PBE Mask */
#define UART_TLCTL_EPE_Pos (4) /*!< UART TLCTL: EPE Position */
#define UART_TLCTL_EPE_Msk (0x1ul << UART_TLCTL_EPE_Pos) /*!< UART TLCTL: EPE Mask */
#define UART_TLCTL_SPE_Pos (5) /*!< UART TLCTL: SPE Position */
#define UART_TLCTL_SPE_Msk (0x1ul << UART_TLCTL_SPE_Pos) /*!< UART TLCTL: SPE Mask */
#define UART_TLCTL_BCB_Pos (6) /*!< UART TLCTL: BCB Position */
#define UART_TLCTL_BCB_Msk (0x1ul << UART_TLCTL_BCB_Pos) /*!< UART TLCTL: BCB Mask */
#define UART_TLCTL_RFITL_Pos (8) /*!< UART TLCTL: RFITL Position */
#define UART_TLCTL_RFITL_Msk (0x3ul << UART_TLCTL_RFITL_Pos) /*!< UART TLCTL: RFITL Mask */
#define UART_TLCTL_RTS_TRI_LEV_Pos (12) /*!< UART TLCTL: RTS_TRI_LEV Position */
#define UART_TLCTL_RTS_TRI_LEV_Msk (0x3ul << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART TLCTL: RTS_TRI_LEV Mask */
#define UART_IER_RDA_IE_Pos (0) /*!< UART IER: RDA_IE Position */
#define UART_IER_RDA_IE_Msk (0x1ul << UART_IER_RDA_IE_Pos) /*!< UART IER: RDA_IE Mask */
#define UART_IER_THRE_IE_Pos (1) /*!< UART IER: THRE_IE Position */
#define UART_IER_THRE_IE_Msk (0x1ul << UART_IER_THRE_IE_Pos) /*!< UART IER: THRE_IE Mask */
#define UART_IER_RLS_IE_Pos (2) /*!< UART IER: RLS_IE Position */
#define UART_IER_RLS_IE_Msk (0x1ul << UART_IER_RLS_IE_Pos) /*!< UART IER: RLS_IE Mask */
#define UART_IER_MODEM_IE_Pos (3) /*!< UART IER: MODEM_IE Position */
#define UART_IER_MODEM_IE_Msk (0x1ul << UART_IER_MODEM_IE_Pos) /*!< UART IER: MODEM_IE Mask */
#define UART_IER_RTO_IE_Pos (4) /*!< UART IER: RTO_IE Position */
#define UART_IER_RTO_IE_Msk (0x1ul << UART_IER_RTO_IE_Pos) /*!< UART IER: RTO_IE Mask */
#define UART_IER_BUF_ERR_IE_Pos (5) /*!< UART IER: BUF_ERR_IE Position */
#define UART_IER_BUF_ERR_IE_Msk (0x1ul << UART_IER_BUF_ERR_IE_Pos) /*!< UART IER: BUF_ERR_IE Mask */
#define UART_IER_WAKE_IE_Pos (6) /*!< UART IER: WAKE_IE Position */
#define UART_IER_WAKE_IE_Msk (0x1ul << UART_IER_WAKE_IE_Pos) /*!< UART IER: WAKE_IE Mask */
#define UART_IER_ABAUD_IE_Pos (7) /*!< UART IER: ABAUD_IE Position */
#define UART_IER_ABAUD_IE_Msk (0x1ul << UART_IER_ABAUD_IE_Pos) /*!< UART IER: ABAUD_IE Mask */
#define UART_IER_LIN_IE_Pos (8) /*!< UART IER: LIN_IE Position */
#define UART_IER_LIN_IE_Msk (0x1ul << UART_IER_LIN_IE_Pos) /*!< UART IER: LIN_IE Mask */
#define UART_ISR_RDA_IS_Pos (0) /*!< UART ISR: RDA_IS Position */
#define UART_ISR_RDA_IS_Msk (0x1ul << UART_ISR_RDA_IS_Pos) /*!< UART ISR: RDA_IS Mask */
#define UART_ISR_THRE_IS_Pos (1) /*!< UART ISR: THRE_IS Position */
#define UART_ISR_THRE_IS_Msk (0x1ul << UART_ISR_THRE_IS_Pos) /*!< UART ISR: THRE_IS Mask */
#define UART_ISR_RLS_IS_Pos (2) /*!< UART ISR: RLS_IS Position */
#define UART_ISR_RLS_IS_Msk (0x1ul << UART_ISR_RLS_IS_Pos) /*!< UART ISR: RLS_IS Mask */
#define UART_ISR_MODEM_IS_Pos (3) /*!< UART ISR: MODEM_IS Position */
#define UART_ISR_MODEM_IS_Msk (0x1ul << UART_ISR_MODEM_IS_Pos) /*!< UART ISR: MODEM_IS Mask */
#define UART_ISR_RTO_IS_Pos (4) /*!< UART ISR: RTO_IS Position */
#define UART_ISR_RTO_IS_Msk (0x1ul << UART_ISR_RTO_IS_Pos) /*!< UART ISR: RTO_IS Mask */
#define UART_ISR_BUF_ERR_IS_Pos (5) /*!< UART ISR: BUF_ERR_IS Position */
#define UART_ISR_BUF_ERR_IS_Msk (0x1ul << UART_ISR_BUF_ERR_IS_Pos) /*!< UART ISR: BUF_ERR_IS Mask */
#define UART_ISR_WAKE_IS_Pos (6) /*!< UART ISR: WAKE_IS Position */
#define UART_ISR_WAKE_IS_Msk (0x1ul << UART_ISR_WAKE_IS_Pos) /*!< UART ISR: WAKE_IS Mask */
#define UART_ISR_ABAUD_IS_Pos (7) /*!< UART ISR: ABAUD_IS Position */
#define UART_ISR_ABAUD_IS_Msk (0x1ul << UART_ISR_ABAUD_IS_Pos) /*!< UART ISR: ABAUD_IS Mask */
#define UART_ISR_LIN_IS_Pos (8) /*!< UART ISR: LIN_IS Position */
#define UART_ISR_LIN_IS_Msk (0x1ul << UART_ISR_LIN_IS_Pos) /*!< UART ISR: LIN_IS Mask */
#define UART_TRSR_RS485_ADDET_F_Pos (0) /*!< UART TRSR: RS485_ADDET_F Position */
#define UART_TRSR_RS485_ADDET_F_Msk (0x1ul << UART_TRSR_RS485_ADDET_F_Pos) /*!< UART TRSR: RS485_ADDET_F Mask */
#define UART_TRSR_ABAUD_F_Pos (1) /*!< UART TRSR: ABAUD_F Position */
#define UART_TRSR_ABAUD_F_Msk (0x1ul << UART_TRSR_ABAUD_F_Pos) /*!< UART TRSR: ABAUD_F Mask */
#define UART_TRSR_ABAUD_TOUT_F_Pos (2) /*!< UART TRSR: ABAUD_TOUT_F Position */
#define UART_TRSR_ABAUD_TOUT_F_Msk (0x1ul << UART_TRSR_ABAUD_TOUT_F_Pos) /*!< UART TRSR: ABAUD_TOUT_F Mask */
#define UART_TRSR_LIN_TX_F_Pos (3) /*!< UART TRSR: LIN_TX_F Position */
#define UART_TRSR_LIN_TX_F_Msk (0x1ul << UART_TRSR_LIN_TX_F_Pos) /*!< UART TRSR: LIN_TX_F Mask */
#define UART_TRSR_LIN_RX_F_Pos (4) /*!< UART TRSR: LIN_RX_F Position */
#define UART_TRSR_LIN_RX_F_Msk (0x1ul << UART_TRSR_LIN_RX_F_Pos) /*!< UART TRSR: LIN_RX_F Mask */
#define UART_TRSR_BIT_ERR_F_Pos (5) /*!< UART TRSR: BIT_ERR_F Position */
#define UART_TRSR_BIT_ERR_F_Msk (0x1ul << UART_TRSR_BIT_ERR_F_Pos) /*!< UART TRSR: BIT_ERR_F Mask */
#define UART_TRSR_LIN_RX_SYNC_ERR_F_Pos (8) /*!< UART TRSR: LIN_RX_SYNC_ERR_F Position */
#define UART_TRSR_LIN_RX_SYNC_ERR_F_Msk (0x1ul << UART_TRSR_LIN_RX_SYNC_ERR_F_Pos) /*!< UART TRSR: LIN_RX_SYNC_ERR_F Mask */
#define UART_FSR_RX_OVER_F_Pos (0) /*!< UART FSR: RX_OVER_F Position */
#define UART_FSR_RX_OVER_F_Msk (0x1ul << UART_FSR_RX_OVER_F_Pos) /*!< UART FSR: RX_OVER_F Mask */
#define UART_FSR_RX_EMPTY_F_Pos (1) /*!< UART FSR: RX_EMPTY_F Position */
#define UART_FSR_RX_EMPTY_F_Msk (0x1ul << UART_FSR_RX_EMPTY_F_Pos) /*!< UART FSR: RX_EMPTY_F Mask */
#define UART_FSR_RX_FULL_F_Pos (2) /*!< UART FSR: RX_FULL_F Position */
#define UART_FSR_RX_FULL_F_Msk (0x1ul << UART_FSR_RX_FULL_F_Pos) /*!< UART FSR: RX_FULL_F Mask */
#define UART_FSR_PE_F_Pos (4) /*!< UART FSR: PE_F Position */
#define UART_FSR_PE_F_Msk (0x1ul << UART_FSR_PE_F_Pos) /*!< UART FSR: PE_F Mask */
#define UART_FSR_FE_F_Pos (5) /*!< UART FSR: FE_F Position */
#define UART_FSR_FE_F_Msk (0x1ul << UART_FSR_FE_F_Pos) /*!< UART FSR: FE_F Mask */
#define UART_FSR_BI_F_Pos (6) /*!< UART FSR: BI_F Position */
#define UART_FSR_BI_F_Msk (0x1ul << UART_FSR_BI_F_Pos) /*!< UART FSR: BI_F Mask */
#define UART_FSR_TX_OVER_F_Pos (8) /*!< UART FSR: TX_OVER_F Position */
#define UART_FSR_TX_OVER_F_Msk (0x1ul << UART_FSR_TX_OVER_F_Pos) /*!< UART FSR: TX_OVER_F Mask */
#define UART_FSR_TX_EMPTY_F_Pos (9) /*!< UART FSR: TX_EMPTY_F Position */
#define UART_FSR_TX_EMPTY_F_Msk (0x1ul << UART_FSR_TX_EMPTY_F_Pos) /*!< UART FSR: TX_EMPTY_F Mask */
#define UART_FSR_TX_FULL_F_Pos (10) /*!< UART FSR: TX_FULL_F Position */
#define UART_FSR_TX_FULL_F_Msk (0x1ul << UART_FSR_TX_FULL_F_Pos) /*!< UART FSR: TX_FULL_F Mask */
#define UART_FSR_TE_F_Pos (11) /*!< UART FSR: TE_F Position */
#define UART_FSR_TE_F_Msk (0x1ul << UART_FSR_TE_F_Pos) /*!< UART FSR: TE_F Mask */
#define UART_FSR_RX_POINTER_F_Pos (16) /*!< UART FSR: RX_POINTER_F Position */
#define UART_FSR_RX_POINTER_F_Msk (0x1ful << UART_FSR_RX_POINTER_F_Pos) /*!< UART FSR: RX_POINTER_F Mask */
#define UART_FSR_TX_POINTER_F_Pos (24) /*!< UART FSR: TX_POINTER_F Position */
#define UART_FSR_TX_POINTER_F_Msk (0x1ful << UART_FSR_TX_POINTER_F_Pos) /*!< UART FSR: TX_POINTER_F Mask */
#define UART_MCSR_LEV_RTS_Pos (0) /*!< UART MCSR: LEV_RTS Position */
#define UART_MCSR_LEV_RTS_Msk (0x1ul << UART_MCSR_LEV_RTS_Pos) /*!< UART MCSR: LEV_RTS Mask */
#define UART_MCSR_RTS_ST_Pos (1) /*!< UART MCSR: RTS_ST Position */
#define UART_MCSR_RTS_ST_Msk (0x1ul << UART_MCSR_RTS_ST_Pos) /*!< UART MCSR: RTS_ST Mask */
#define UART_MCSR_LEV_CTS_Pos (16) /*!< UART MCSR: LEV_CTS Position */
#define UART_MCSR_LEV_CTS_Msk (0x1ul << UART_MCSR_LEV_CTS_Pos) /*!< UART MCSR: LEV_CTS Mask */
#define UART_MCSR_CTS_ST_Pos (17) /*!< UART MCSR: CTS_ST Position */
#define UART_MCSR_CTS_ST_Msk (0x1ul << UART_MCSR_CTS_ST_Pos) /*!< UART MCSR: CTS_ST Mask */
#define UART_MCSR_DCT_F_Pos (18) /*!< UART MCSR: DCT_F Position */
#define UART_MCSR_DCT_F_Msk (0x1ul << UART_MCSR_DCT_F_Pos) /*!< UART MCSR: DCT_F Mask */
#define UART_TMCTL_TOIC_Pos (0) /*!< UART TMCTL: TOIC Position */
#define UART_TMCTL_TOIC_Msk (0x1fful << UART_TMCTL_TOIC_Pos) /*!< UART TMCTL: TOIC Mask */
#define UART_TMCTL_DLY_Pos (16) /*!< UART TMCTL: DLY Position */
#define UART_TMCTL_DLY_Msk (0xfful << UART_TMCTL_DLY_Pos) /*!< UART TMCTL: DLY Mask */
#define UART_BAUD_BRD_Pos (0) /*!< UART BAUD: BRD Position */
#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART BAUD: BRD Mask */
#define UART_BAUD_DIV_16_EN_Pos (31) /*!< UART BAUD: DIV_16_EN Position */
#define UART_BAUD_DIV_16_EN_Msk (0x1ul << UART_BAUD_DIV_16_EN_Pos) /*!< UART BAUD: DIV_16_EN Mask */
#define UART_IRCR_TX_SELECT_Pos (1) /*!< UART IRCR: TX_SELECT Position */
#define UART_IRCR_TX_SELECT_Msk (0x1ul << UART_IRCR_TX_SELECT_Pos) /*!< UART IRCR: TX_SELECT Mask */
#define UART_IRCR_INV_TX_Pos (5) /*!< UART IRCR: INV_TX Position */
#define UART_IRCR_INV_TX_Msk (0x1ul << UART_IRCR_INV_TX_Pos) /*!< UART IRCR: INV_TX Mask */
#define UART_IRCR_INV_RX_Pos (6) /*!< UART IRCR: INV_RX Position */
#define UART_IRCR_INV_RX_Msk (0x1ul << UART_IRCR_INV_RX_Pos) /*!< UART IRCR: INV_RX Mask */
#define UART_ALT_CTL_LIN_TX_BCNT_Pos (0) /*!< UART ALT_CTL: LIN_TX_BCNT Position */
#define UART_ALT_CTL_LIN_TX_BCNT_Msk (0x7ul << UART_ALT_CTL_LIN_TX_BCNT_Pos) /*!< UART ALT_CTL: LIN_TX_BCNT Mask */
#define UART_ALT_CTL_LIN_HEAD_SEL_Pos (4) /*!< UART ALT_CTL: LIN_HEAD_SEL Position */
#define UART_ALT_CTL_LIN_HEAD_SEL_Msk (0x3ul << UART_ALT_CTL_LIN_HEAD_SEL_Pos) /*!< UART ALT_CTL: LIN_HEAD_SEL Mask */
#define UART_ALT_CTL_LIN_RX_EN_Pos (6) /*!< UART ALT_CTL: LIN_RX_EN Position */
#define UART_ALT_CTL_LIN_RX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_RX_EN_Pos) /*!< UART ALT_CTL: LIN_RX_EN Mask */
#define UART_ALT_CTL_LIN_TX_EN_Pos (7) /*!< UART ALT_CTL: LIN_TX_EN Position */
#define UART_ALT_CTL_LIN_TX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_TX_EN_Pos) /*!< UART ALT_CTL: LIN_TX_EN Mask */
#define UART_ALT_CTL_Bit_ERR_EN_Pos (8) /*!< UART ALT_CTL: Bit_ERR_EN Position */
#define UART_ALT_CTL_Bit_ERR_EN_Msk (0x1ul << UART_ALT_CTL_Bit_ERR_EN_Pos) /*!< UART ALT_CTL: Bit_ERR_EN Mask */
#define UART_ALT_CTL_RS485_NMM_Pos (16) /*!< UART ALT_CTL: RS485_NMM Position */
#define UART_ALT_CTL_RS485_NMM_Msk (0x1ul << UART_ALT_CTL_RS485_NMM_Pos) /*!< UART ALT_CTL: RS485_NMM Mask */
#define UART_ALT_CTL_RS485_AAD_Pos (17) /*!< UART ALT_CTL: RS485_AAD Position */
#define UART_ALT_CTL_RS485_AAD_Msk (0x1ul << UART_ALT_CTL_RS485_AAD_Pos) /*!< UART ALT_CTL: RS485_AAD Mask */
#define UART_ALT_CTL_RS485_AUD_Pos (18) /*!< UART ALT_CTL: RS485_AUD Position */
#define UART_ALT_CTL_RS485_AUD_Msk (0x1ul << UART_ALT_CTL_RS485_AUD_Pos) /*!< UART ALT_CTL: RS485_AUD Mask */
#define UART_ALT_CTL_RS485_ADD_EN_Pos (19) /*!< UART ALT_CTL: RS485_ADD_EN Position */
#define UART_ALT_CTL_RS485_ADD_EN_Msk (0x1ul << UART_ALT_CTL_RS485_ADD_EN_Pos) /*!< UART ALT_CTL: RS485_ADD_EN Mask */
#define UART_ALT_CTL_ADDR_PID_MATCH_Pos (24) /*!< UART ALT_CTL: ADDR_PID_MATCH Position */
#define UART_ALT_CTL_ADDR_PID_MATCH_Msk (0xfful << UART_ALT_CTL_ADDR_PID_MATCH_Pos) /*!< UART ALT_CTL: ADDR_PID_MATCH Mask */
#define UART_FUN_SEL_FUN_SEL_Pos (0) /*!< UART FUN_SEL: FUN_SEL Position */
#define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART FUN_SEL: FUN_SEL Mask */
#define UART_BR_COMP_BR_COMP_Pos (0) /*!< UART BR_COMP: BR_COMP Position */
#define UART_BR_COMP_BR_COMP_Msk (0x1fful << UART_BR_COMP_BR_COMP_Pos) /*!< UART BR_COMP: BR_COMP Mask */
#define UART_BR_COMP_BR_COMP_DEC_Pos (31) /*!< UART BR_COMP: BR_COMP_DEC Position */
#define UART_BR_COMP_BR_COMP_DEC_Msk (0x1ul << UART_BR_COMP_BR_COMP_DEC_Pos) /*!< UART BR_COMP: BR_COMP_DEC Mask */
/**@}*/ /* UART_CONST */
/**@}*/ /* end of UART register group */
/*---------------------- Watch Dog Timer Controller -------------------------*/
/**
@addtogroup WDT Watch Dog Timer Controller(WDT)
Memory Mapped Structure for WDT Controller
@{ */
typedef struct {
/**
* CTL
* ===================================================================================================
* Offset: 0x00 Watchdog Timer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WTR |Clear Watchdog Timer
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |Set this bit will clear the Watchdog timer.
* | | |0 = No effect.
* | | |1 = Reset the contents of the Watchdog timer.
* | | |Note: This bit will be auto cleared after few clock cycles.
* |[1] |WTRE |Watchdog Timer Reset Function Enable
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |Setting this bit will enable the Watchdog timer reset function.
* | | |0 = Watchdog timer reset function Disabled.
* | | |1 = Watchdog timer reset function Enabled.
* |[2] |WTWKE |Watchdog Timer Wake-Up Function Enable
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Watchdog timer Wake-up CPU function Disabled.
* | | |1 = Wake-up function Enabled so that Watchdog timer time-out can wake up CPU from power-down mode.
* |[3] |WTE |Watchdog Timer Enable
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = Watchdog timer Disabled (this action will reset the internal counter).
* | | |1 = Watchdog timer Enabled.
* |[6:4] |WTIS |Watchdog Timer Interval Selection
* | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |These three bits select the time-out interval for the Watchdog timer.
* | | |This count is free running counter.
* |[9:8] |WTRDSEL |Watchdog Timer Reset Delay Select
* | | |When watchdog timeout happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened.
* | | |Software can select a suitable value of watchdog reset delay period for different watchdog timeout period.
* | | |00 = Watchdog reset delay period is 1026 watchdog clock
* | | |01 = Watchdog reset delay period is 130 watchdog clock
* | | |10 = Watchdog reset delay period is 18 watchdog clock
* | | |11 = Watchdog reset delay period is 3 watchdog clock
* | | |This register will be reset if watchdog reset happened
*/
__IO uint32_t CTL;
/**
* IER
* ===================================================================================================
* Offset: 0x04 Watchdog Timer Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WDT_IE |Watchdog Timer Interrupt Enable
* | | |0 = Watchdog timer interrupt Disabled.
* | | |1 = Watchdog timer interrupt Enabled.
*/
__IO uint32_t IER;
/**
* ISR
* ===================================================================================================
* Offset: 0x08 Watchdog Timer Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IS |Watchdog Timer Interrupt Status
* | | |If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred.
* | | |If the Watchdog timer interrupt is not enabled, then this bit indicates that a time-out period has elapsed.
* | | |0 = Watchdog timer interrupt did not occur.
* | | |1 = Watchdog timer interrupt occurs.
* | | |Note: This bit is read only, but can be cleared by writing "1" to it.
* |[1] |RST_IS |Watchdog Timer Reset Status
* | | |When the Watchdog timer initiates a reset, the hardware will set this bit.
* | | |This flag can be read by software to determine the source of reset.
* | | |Software is responsible to clear it manually by writing "1" to it.
* | | |If WTRE is disabled, then the Watchdog timer has no effect on this bit.
* | | |0 = Watchdog timer reset did not occur.
* | | |1 = Watchdog timer reset occurs.
* | | |Note: This bit is read only, but can be cleared by writing "1" to it.
* |[2] |WAKE_IS |Watchdog Timer Wake-Up Status
* | | |If Watchdog timer causes system to wake up from power-down mode, this bit will be set to high.
* | | |It must be cleared by software with a write "1" to this bit.
* | | |0 = Watchdog timer does not cause system wake-up.
* | | |1 = Wake system up from power-down mode by Watchdog time-out.
* | | |Note1: When system in power-down mode and watchdog time-out, hardware will set WDT_WAKE_IS and WDT_IS.
* | | |Note2: After one engine clock, this bit can be cleared by writing "1" to it
*/
__IO uint32_t ISR;
} WDT_T;
/**
@addtogroup WDT_CONST WDT Bit Field Definition
Constant Definitions for WDT Controller
@{ */
#define WDT_CTL_WTR_Pos (0) /*!< WDT CTL: WTR Position */
#define WDT_CTL_WTR_Msk (0x1ul << WDT_CTL_WTR_Pos) /*!< WDT CTL: WTR Mask */
#define WDT_CTL_WTRE_Pos (1) /*!< WDT CTL: WTRE Position */
#define WDT_CTL_WTRE_Msk (0x1ul << WDT_CTL_WTRE_Pos) /*!< WDT CTL: WTRE Mask */
#define WDT_CTL_WTWKE_Pos (2) /*!< WDT CTL: WTWKE Position */
#define WDT_CTL_WTWKE_Msk (0x1ul << WDT_CTL_WTWKE_Pos) /*!< WDT CTL: WTWKE Mask */
#define WDT_CTL_WTE_Pos (3) /*!< WDT CTL: WTE Position */
#define WDT_CTL_WTE_Msk (0x1ul << WDT_CTL_WTE_Pos) /*!< WDT CTL: WTE Mask */
#define WDT_CTL_WTIS_Pos (4) /*!< WDT CTL: WTIS Position */
#define WDT_CTL_WTIS_Msk (0x7ul << WDT_CTL_WTIS_Pos) /*!< WDT CTL: WTIS Mask */
#define WDT_CTL_WTRDSEL_Pos (8) /*!< WDT CTL: WTRDSEL Position */
#define WDT_CTL_WTRDSEL_Msk (0x3ul << WDT_CTL_WTRDSEL_Pos) /*!< WDT CTL: WTRDSEL Mask */
#define WDT_IER_IE_Pos (0) /*!< WDT IER: IE Position */
#define WDT_IER_IE_Msk (0x1ul << WDT_IER_IE_Pos) /*!< WDT IER: IE Mask */
#define WDT_ISR_IS_Pos (0) /*!< WDT ISR: IS Position */
#define WDT_ISR_IS_Msk (0x1ul << WDT_ISR_IS_Pos) /*!< WDT ISR: IS Mask */
#define WDT_ISR_RST_IS_Pos (1) /*!< WDT ISR: RST_IS Position */
#define WDT_ISR_RST_IS_Msk (0x1ul << WDT_ISR_RST_IS_Pos) /*!< WDT ISR: RST_IS Mask */
#define WDT_ISR_WAKE_IS_Pos (2) /*!< WDT ISR: WAKE_IS Position */
#define WDT_ISR_WAKE_IS_Msk (0x1ul << WDT_ISR_WAKE_IS_Pos) /*!< WDT ISR: WAKE_IS Mask */
/**@}*/ /* WDT_CONST */
/**@}*/ /* end of WDT register group */
/*---------------------- Window Watchdog Timer -------------------------*/
/**
@addtogroup WWDT Window Watchdog Timer(WWDT)
Memory Mapped Structure for WWDT Controller
@{ */
typedef struct {
/**
* RLD
* ===================================================================================================
* Offset: 0x00 Window Watchdog Timer Reload Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RLD |Window Watchdog Timer Reload Counter Register
* | | |Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F.
* | | |Note: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP.
* | | |If SW writes WWDTRLD when WWDT counter value larger than WINCMP, WWDT will generate RESET signal.
*/
__O uint32_t RLD;
/**
* CR
* ===================================================================================================
* Offset: 0x04 Window Watchdog Timer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTEN |Window Watchdog Enable
* | | |Set this bit to enable Window Watchdog timer.
* | | |0 = Window Watchdog timer function Disabled.
* | | |1 = Window Watchdog timer function Enabled.
* |[11:8] |PERIODSEL |WWDT Pre-Scale Period Select
* | | |These three bits select the pre-scale for the WWDT counter period.
* |[21:16] |WINCMP |WWDT Window Compare Register
* | | |Set this register to adjust the valid reload window.
* | | |Note: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP.
* | | |If SW writes WWDTRLD when WWDT counter value larger than WWCMP, WWDT will generate RESET signal.
* |[31] |DBGEN |WWDT Debug Enable
* | | |0 = WWDT stopped count if system is in Debug mode.
* | | |1 = WWDT still counted even system is in Debug mode.
*/
__IO uint32_t CR;
/**
* IER
* ===================================================================================================
* Offset: 0x08 Window Watchdog Timer Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTIE |WWDT Interrupt Enable
* | | |Setting this bit will enable the Watchdog timer interrupt function.
* | | |0 = Watchdog timer interrupt function Disabled.
* | | |1 = Watchdog timer interrupt function Enabled.
*/
__IO uint32_t IER;
/**
* STS
* ===================================================================================================
* Offset: 0x0C Window Watchdog Timer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IF |WWDT Compare Match Interrupt Flag
* | | |When WWCMP match the WWDT counter, then this bit is set to 1.
* | | |This bit will be cleared by software write 1 to this bit.
* |[1] |RF |WWDT Reset Flag
* | | |When WWDT counter down count to 0 or write WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1.
* | | |Software can write 1 to clear this bit to 0.
*/
__IO uint32_t STS;
/**
* WWDTVAL
* ===================================================================================================
* Offset: 0x10 Window Watchdog Timer Counter Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |VAL |WWDT Counter Value
* | | |This register reflects the counter value of window watchdog. This register is read only
*/
__I uint32_t VAL;
} WWDT_T;
/**
@addtogroup WWDT_CONST WWDT Bit Field Definition
Constant Definitions for WWDT Controller
@{ */
#define WWDT_RLD_WWDTRLD_Pos (0) /*!< WWDT RLD: RLD Position */
#define WWDT_RLD_WWDTRLD_Msk (0xfffffffful << WWDT_RLD_RLD_Pos) /*!< WWDT RLD: RLD Mask */
#define WWDT_CR_WWDTEN_Pos (0) /*!< WWDT CR: WWDTEN Position */
#define WWDT_CR_WWDTEN_Msk (0x1ul << WWDT_CR_WWDTEN_Pos) /*!< WWDT CR: WWDTEN Mask */
#define WWDT_CR_PERIODSEL_Pos (8) /*!< WWDT CR: PERIODSEL Position */
#define WWDT_CR_PERIODSEL_Msk (0xful << WWDT_CR_PERIODSEL_Pos) /*!< WWDT CR: PERIODSEL Mask */
#define WWDT_CR_WINCMP_Pos (16) /*!< WWDT CR: WINCMP Position */
#define WWDT_CR_WINCMP_Msk (0x3ful << WWDT_CR_WINCMP_Pos) /*!< WWDT CR: WINCMP Mask */
#define WWDT_CR_DBGEN_Pos (31) /*!< WWDT CR: DBGEN Position */
#define WWDT_CR_DBGEN_Msk (0x1ul << WWDT_CR_DBGEN_Pos) /*!< WWDT CR: DBGEN Mask */
#define WWDT_IER_WWDTIE_Pos (0) /*!< WWDT IER: WWDTIE Position */
#define WWDT_IER_WWDTIE_Msk (0x1ul << WWDT_IER_WWDTIE_Pos) /*!< WWDT IER: WWDTIE Mask */
#define WWDT_STS_IF_Pos (0) /*!< WWDT STS: IF Position */
#define WWDT_STS_IF_Msk (0x1ul << WWDT_STS_IF_Pos) /*!< WWDT STS: IF Mask */
#define WWDT_STS_RF_Pos (1) /*!< WWDT STS: RF Position */
#define WWDT_STS_RF_Msk (0x1ul << WWDT_STS_RF_Pos) /*!< WWDT STS: RF Mask */
#define WWDT_VAL_WWDTVAL_Pos (0) /*!< WWDT VAL: WWDTVAL Position */
#define WWDT_VAL_WWDTVAL_Msk (0x3ful << WWDT_VAL_WWDTVAL_Pos) /*!< WWDT VAL: WWDTVAL Mask */
/**@}*/ /* WWDT_CONST */
/**@}*/ /* end of WWDT register group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/** @addtogroup NANO1X2_PERIPHERAL_MEM_MAP NANO102/112 Peripheral Memory Map
Memory Mapped Structure for NANO102/112 Series Peripheral
@{
*/
/*!<Peripheral and SRAM base address */
#define FLASH_BASE ((uint32_t)0x00000000) ///< Flash base address
#define SRAM_BASE ((uint32_t)0x20000000) ///< SRAM base address
#define APB1PERIPH_BASE ((uint32_t)0x40000000) ///< APB1 base address
#define APB2PERIPH_BASE ((uint32_t)0x40100000) ///< APB2 base address
#define AHBPERIPH_BASE ((uint32_t)0x50000000) ///< AHB base address
/*!<Peripheral memory map */
#define WDT_BASE (APB1PERIPH_BASE + 0x04000) ///< WDT register base address
#define WWDT_BASE (APB1PERIPH_BASE + 0x04100) ///< WWDT register base address
#define RTC_BASE (APB1PERIPH_BASE + 0x08000) ///< RTC register base address
#define TIMER0_BASE (APB1PERIPH_BASE + 0x10000) ///< TIMER0 register base address
#define TIMER1_BASE (APB1PERIPH_BASE + 0x10100) ///< TIMER1 register base address
#define I2C0_BASE (APB1PERIPH_BASE + 0x20000) ///< I2C0 register base address
#define SPI0_BASE (APB1PERIPH_BASE + 0x30000) ///< SPI0 register base address
#define PWM0_BASE (APB1PERIPH_BASE + 0x40000) ///< PWM0 register base address
#define UART0_BASE (APB1PERIPH_BASE + 0x50000) ///< UART0 register base address
#define LCD_BASE (APB1PERIPH_BASE + 0xB0000) ///< LCD register base address
#define ADC_BASE (APB1PERIPH_BASE + 0xE0000) ///< ADC register base address
#define TIMER2_BASE (APB2PERIPH_BASE + 0x10000) ///< TIMER2 register base address
#define TIMER3_BASE (APB2PERIPH_BASE + 0x10100) ///< TIMER3 register base address
#define I2C1_BASE (APB2PERIPH_BASE + 0x20000) ///< I2C1 register base address
#define SPI1_BASE (APB2PERIPH_BASE + 0x30000) ///< SPI1 register base address
#define UART1_BASE (APB2PERIPH_BASE + 0x50000) ///< UART1 register base address
#define SC0_BASE (APB2PERIPH_BASE + 0x90000) ///< SC0 register base address
#define SC1_BASE (APB2PERIPH_BASE + 0xB0000) ///< SC1 register base address
#define ACMP_BASE (APB2PERIPH_BASE + 0xD0000) ///< ACMP register base address
#define SYS_BASE (AHBPERIPH_BASE + 0x00000) ///< SYS register base address
#define CLK_BASE (AHBPERIPH_BASE + 0x00200) ///< CLK register base address
#define INTID_BASE (AHBPERIPH_BASE + 0x00300) ///< INT register base address
#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000) ///< GPIO port A register base address
#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040) ///< GPIO port B register base address
#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080) ///< GPIO port C register base address
#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0) ///< GPIO port D register base address
#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100) ///< GPIO port E register base address
#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140) ///< GPIO port F register base address
#define GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180) ///< GPIO debounce register base address
#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200) ///< GPIO bit access register base address
#define PDMA0_BASE (AHBPERIPH_BASE + 0x08000) ///< PDMA0 register base address
#define PDMA1_BASE (AHBPERIPH_BASE + 0x08100) ///< PDMA1 register base address
#define PDMA2_BASE (AHBPERIPH_BASE + 0x08200) ///< PDMA2 register base address
#define PDMA3_BASE (AHBPERIPH_BASE + 0x08300) ///< PDMA3 register base address
#define PDMA4_BASE (AHBPERIPH_BASE + 0x08400) ///< PDMA4 register base address
#define PDMACRC_BASE (AHBPERIPH_BASE + 0x08E00) ///< PDMA global control register base address
#define PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00) ///< PDMA CRC register base address
#define FMC_BASE (AHBPERIPH_BASE + 0x0C000) ///< FMC register base address
/*@}*/ /* end of group NANO1X2_PERIPHERAL_MEM_MAP */
/** @addtogroup NANO1X2_PERIPHERAL_DECLARATION NANO102/112 Peripheral Declaration
The Declaration of NANO102/112 Series Peripheral
@{
*/
#define WDT ((WDT_T *) WDT_BASE) ///< Pointer to WDT register structure
#define WWDT ((WWDT_T *) WWDT_BASE) ///< Pointer to WWDT register structure
#define RTC ((RTC_T *) RTC_BASE) ///< Pointer to RTC register structure
#define TIMER0 ((TIMER_T *) TIMER0_BASE) ///< Pointer to TIMER0 register structure
#define TIMER1 ((TIMER_T *) TIMER1_BASE) ///< Pointer to TIMER1 register structure
#define TIMER2 ((TIMER_T *) TIMER2_BASE) ///< Pointer to TIMER2 register structure
#define TIMER3 ((TIMER_T *) TIMER3_BASE) ///< Pointer to TIMER3 register structure
#define I2C0 ((I2C_T *) I2C0_BASE) ///< Pointer to I2C0 register structure
#define I2C1 ((I2C_T *) I2C1_BASE) ///< Pointer to I2C1 register structure
#define SPI0 ((SPI_T *) SPI0_BASE) ///< Pointer to SPI0 register structure
#define SPI1 ((SPI_T *) SPI1_BASE) ///< Pointer to SPI1 register structure
#define PWM0 ((PWM_T *) PWM0_BASE) ///< Pointer to PWM0 register structure
#define UART0 ((UART_T *) UART0_BASE) ///< Pointer to UART0 register structure
#define UART1 ((UART_T *) UART1_BASE) ///< Pointer to UART1 register structure
#define LCD ((LCD_T *) LCD_BASE) ///< Pointer to LCD register structure
#define ADC ((ADC_T *) ADC_BASE) ///< Pointer to ADC register structure
#define SC0 ((SC_T *) SC0_BASE) ///< Pointer to SC0 register structure
#define SC1 ((SC_T *) SC1_BASE) ///< Pointer to SC1 register structure
#define ACMP ((ACMP_T *) ACMP_BASE) ///< Pointer to ACMP register structure
#define SYS ((SYS_T *) SYS_BASE) ///< Pointer to SYS register structure
#define CLK ((CLK_T *) CLK_BASE) ///< Pointer to CLK register structure
#define PA ((GPIO_T *) GPIOA_BASE) ///< Pointer to GPIO port A register structure
#define PB ((GPIO_T *) GPIOB_BASE) ///< Pointer to GPIO port B register structure
#define PC ((GPIO_T *) GPIOC_BASE) ///< Pointer to GPIO port C register structure
#define PD ((GPIO_T *) GPIOD_BASE) ///< Pointer to GPIO port D register structure
#define PE ((GPIO_T *) GPIOE_BASE) ///< Pointer to GPIO port E register structure
#define PF ((GPIO_T *) GPIOF_BASE) ///< Pointer to GPIO port F register structure
#define GPIO ((GP_DB_T *) GPIODBNCE_BASE) ///< Pointer to GPIO debounce register structure
#define PDMA1 ((PDMA_T *) PDMA1_BASE) ///< Pointer to PDMA1 register structure
#define PDMA2 ((PDMA_T *) PDMA2_BASE) ///< Pointer to PDMA2 register structure
#define PDMA3 ((PDMA_T *) PDMA3_BASE) ///< Pointer to PDMA3 register structure
#define PDMA4 ((PDMA_T *) PDMA4_BASE) ///< Pointer to PDMA4 register structure
#define PDMACRC ((DMA_CRC_T *) PDMACRC_BASE) ///< Pointer to PDMA CRC register structure
#define PDMAGCR ((DMA_GCR_T *) PDMAGCR_BASE) ///< Pointer to PDMA global control register structure
#define FMC ((FMC_T *) FMC_BASE) ///< Pointer to FMC register structure
/*@}*/ /* end of group NANO1X2_PERIPHERAL_DECLARATION */
/*@}*/ /* end of group NANO1X2_Peripherals */
/** @addtogroup NANO1X2_IO_ROUTINE NANO102/112 I/O Routines
The Declaration of NANO102/112 I/O routines
@{
*/
typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type
typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type
typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type
/**
* @brief Get a 8-bit unsigned value from specified address
* @param[in] addr Address to get 8-bit data from
* @return 8-bit unsigned value stored in specified address
*/
#define M8(addr) (*((vu8 *) (addr)))
/**
* @brief Get a 16-bit unsigned value from specified address
* @param[in] addr Address to get 16-bit data from
* @return 16-bit unsigned value stored in specified address
* @note The input address must be 16-bit aligned
*/
#define M16(addr) (*((vu16 *) (addr)))
/**
* @brief Get a 32-bit unsigned value from specified address
* @param[in] addr Address to get 32-bit data from
* @return 32-bit unsigned value stored in specified address
* @note The input address must be 32-bit aligned
*/
#define M32(addr) (*((vu32 *) (addr)))
/**
* @brief Set a 32-bit unsigned value to specified I/O port
* @param[in] port Port address to set 32-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 32-bit aligned
*/
#define outpw(port,value) *((volatile unsigned int *)(port)) = value
/**
* @brief Get a 32-bit unsigned value from specified I/O port
* @param[in] port Port address to get 32-bit data from
* @return 32-bit unsigned value stored in specified I/O port
* @note The input port must be 32-bit aligned
*/
#define inpw(port) (*((volatile unsigned int *)(port)))
/**
* @brief Set a 16-bit unsigned value to specified I/O port
* @param[in] port Port address to set 16-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 16-bit aligned
*/
#define outps(port,value) *((volatile unsigned short *)(port)) = value
/**
* @brief Get a 16-bit unsigned value from specified I/O port
* @param[in] port Port address to get 16-bit data from
* @return 16-bit unsigned value stored in specified I/O port
* @note The input port must be 16-bit aligned
*/
#define inps(port) (*((volatile unsigned short *)(port)))
/**
* @brief Set a 8-bit unsigned value to specified I/O port
* @param[in] port Port address to set 8-bit data
* @param[in] value Value to write to I/O port
* @return None
*/
#define outpb(port,value) *((volatile unsigned char *)(port)) = value
/**
* @brief Get a 8-bit unsigned value from specified I/O port
* @param[in] port Port address to get 8-bit data from
* @return 8-bit unsigned value stored in specified I/O port
*/
#define inpb(port) (*((volatile unsigned char *)(port)))
/**
* @brief Set a 32-bit unsigned value to specified I/O port
* @param[in] port Port address to set 32-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 32-bit aligned
*/
#define outp32(port,value) *((volatile unsigned int *)(port)) = value
/**
* @brief Get a 32-bit unsigned value from specified I/O port
* @param[in] port Port address to get 32-bit data from
* @return 32-bit unsigned value stored in specified I/O port
* @note The input port must be 32-bit aligned
*/
#define inp32(port) (*((volatile unsigned int *)(port)))
/**
* @brief Set a 16-bit unsigned value to specified I/O port
* @param[in] port Port address to set 16-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 16-bit aligned
*/
#define outp16(port,value) *((volatile unsigned short *)(port)) = value
/**
* @brief Get a 16-bit unsigned value from specified I/O port
* @param[in] port Port address to get 16-bit data from
* @return 16-bit unsigned value stored in specified I/O port
* @note The input port must be 16-bit aligned
*/
#define inp16(port) (*((volatile unsigned short *)(port)))
/**
* @brief Set a 8-bit unsigned value to specified I/O port
* @param[in] port Port address to set 8-bit data
* @param[in] value Value to write to I/O port
* @return None
*/
#define outp8(port,value) *((volatile unsigned char *)(port)) = value
/**
* @brief Get a 8-bit unsigned value from specified I/O port
* @param[in] port Port address to get 8-bit data from
* @return 8-bit unsigned value stored in specified I/O port
*/
#define inp8(port) (*((volatile unsigned char *)(port)))
/*@}*/ /* end of group NANO1X2_IO_ROUTINE */
/******************************************************************************/
/* Legacy Constants */
/******************************************************************************/
/** @addtogroup NANO1X2_legacy_Constants NANO102/112 Legacy Constants
NANO102/112 Legacy Constants
@{
*/
#ifndef NULL
#define NULL (0) ///< NULL pointer
#endif
#define TRUE (1) ///< Boolean true, define to use in API parameters or return value
#define FALSE (0) ///< Boolean false, define to use in API parameters or return value
#define ENABLE (1) ///< Enable, define to use in API parameters
#define DISABLE (0) ///< Disable, define to use in API parameters
/* Define one bit mask */
#define BIT0 (0x00000001) ///< Bit 0 mask of an 32 bit integer
#define BIT1 (0x00000002) ///< Bit 1 mask of an 32 bit integer
#define BIT2 (0x00000004) ///< Bit 2 mask of an 32 bit integer
#define BIT3 (0x00000008) ///< Bit 3 mask of an 32 bit integer
#define BIT4 (0x00000010) ///< Bit 4 mask of an 32 bit integer
#define BIT5 (0x00000020) ///< Bit 5 mask of an 32 bit integer
#define BIT6 (0x00000040) ///< Bit 6 mask of an 32 bit integer
#define BIT7 (0x00000080) ///< Bit 7 mask of an 32 bit integer
#define BIT8 (0x00000100) ///< Bit 8 mask of an 32 bit integer
#define BIT9 (0x00000200) ///< Bit 9 mask of an 32 bit integer
#define BIT10 (0x00000400) ///< Bit 10 mask of an 32 bit integer
#define BIT11 (0x00000800) ///< Bit 11 mask of an 32 bit integer
#define BIT12 (0x00001000) ///< Bit 12 mask of an 32 bit integer
#define BIT13 (0x00002000) ///< Bit 13 mask of an 32 bit integer
#define BIT14 (0x00004000) ///< Bit 14 mask of an 32 bit integer
#define BIT15 (0x00008000) ///< Bit 15 mask of an 32 bit integer
#define BIT16 (0x00010000) ///< Bit 16 mask of an 32 bit integer
#define BIT17 (0x00020000) ///< Bit 17 mask of an 32 bit integer
#define BIT18 (0x00040000) ///< Bit 18 mask of an 32 bit integer
#define BIT19 (0x00080000) ///< Bit 19 mask of an 32 bit integer
#define BIT20 (0x00100000) ///< Bit 20 mask of an 32 bit integer
#define BIT21 (0x00200000) ///< Bit 21 mask of an 32 bit integer
#define BIT22 (0x00400000) ///< Bit 22 mask of an 32 bit integer
#define BIT23 (0x00800000) ///< Bit 23 mask of an 32 bit integer
#define BIT24 (0x01000000) ///< Bit 24 mask of an 32 bit integer
#define BIT25 (0x02000000) ///< Bit 25 mask of an 32 bit integer
#define BIT26 (0x04000000) ///< Bit 26 mask of an 32 bit integer
#define BIT27 (0x08000000) ///< Bit 27 mask of an 32 bit integer
#define BIT28 (0x10000000) ///< Bit 28 mask of an 32 bit integer
#define BIT29 (0x20000000) ///< Bit 29 mask of an 32 bit integer
#define BIT30 (0x40000000) ///< Bit 30 mask of an 32 bit integer
#define BIT31 (0x80000000) ///< Bit 31 mask of an 32 bit integer
/* Byte Mask Definitions */
#define BYTE0_Msk (0x000000FF) ///< Mask to get bit0~bit7 from a 32 bit integer
#define BYTE1_Msk (0x0000FF00) ///< Mask to get bit8~bit15 from a 32 bit integer
#define BYTE2_Msk (0x00FF0000) ///< Mask to get bit16~bit23 from a 32 bit integer
#define BYTE3_Msk (0xFF000000) ///< Mask to get bit24~bit31 from a 32 bit integer
#define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
#define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
#define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
#define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
/*@}*/ /* end of group NANO1X2_legacy_Constants */
/*@}*/ /* end of group NANO1X2_Definitions */
#ifdef __cplusplus
}
#endif
/******************************************************************************/
/* Peripheral header files */
/******************************************************************************/
#include "sys.h"
#include "clk.h"
#include "acmp.h"
#include "adc.h"
#include "fmc.h"
#include "gpio.h"
#include "i2c.h"
#include "crc.h"
#include "pdma.h"
#include "pwm.h"
#include "rtc.h"
#include "sc.h"
#include "scuart.h"
#include "spi.h"
#include "timer.h"
#include "uart.h"
#include "wdt.h"
#include "wwdt.h"
#endif // __NANO1X2SERIES_H__
/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
| 73.071971 | 552 | 0.461776 |
08aa7ce77770e60f4e88fc1bfdddfe41008dc045 | 232 | h | C | src/NugetPrimer/NugetPrimer.h | clearwaterstream/NugetPrimer | 482979eb9b2e061eb9dda1fafac65afdcd09a36b | [
"Apache-2.0"
] | null | null | null | src/NugetPrimer/NugetPrimer.h | clearwaterstream/NugetPrimer | 482979eb9b2e061eb9dda1fafac65afdcd09a36b | [
"Apache-2.0"
] | null | null | null | src/NugetPrimer/NugetPrimer.h | clearwaterstream/NugetPrimer | 482979eb9b2e061eb9dda1fafac65afdcd09a36b | [
"Apache-2.0"
] | null | null | null | #pragma once
#include <iostream>
using namespace std;
class NugetPrimer
{
public:
void Prime(wstring const &username, wstring const &domain, wstring const &password, wstring const ¤tDir);
NugetPrimer();
~NugetPrimer();
};
| 19.333333 | 112 | 0.75431 |
d3efe61440cbdfe203c50725d5673642c2e9b7a3 | 64,728 | h | C | C-CAN/C-CAN_PSoC_DevKit/C-CAN.cydsn/codegentemp/CAN_1.h | UNCAMotorsports/UNCAMotorsports-2017 | 3da72751bc9122acf85e625a15a7b0b8184ab00a | [
"MIT"
] | 2 | 2020-01-25T04:42:32.000Z | 2021-12-14T04:34:33.000Z | C-CAN/C-CAN_PSoC_DevKit/C-CAN.cydsn/codegentemp/CAN_1.h | UNCAMotorsports/UNCAMotorsports-2017 | 3da72751bc9122acf85e625a15a7b0b8184ab00a | [
"MIT"
] | null | null | null | C-CAN/C-CAN_PSoC_DevKit/C-CAN.cydsn/codegentemp/CAN_1.h | UNCAMotorsports/UNCAMotorsports-2017 | 3da72751bc9122acf85e625a15a7b0b8184ab00a | [
"MIT"
] | null | null | null | /*******************************************************************************
* File Name: CAN_1.h
* Version 3.0
*
* Description:
* Contains the function prototypes, constants and register definition
* of the CAN Component.
*
* Note:
* None
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CAN_CAN_1_H)
#define CY_CAN_CAN_1_H
#include "cyfitter.h"
#include "cytypes.h"
#include "CyLib.h"
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
#error Component CAN_v3_0 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
extern uint8 CAN_1_initVar;
#define CAN_1_INT_ISR_DISABLE (0u)
/***************************************
* Conditional Compilation Parameters
***************************************/
#define CAN_1_ARB_LOST (0u)
#define CAN_1_OVERLOAD (0u)
#define CAN_1_BIT_ERR (0u)
#define CAN_1_STUFF_ERR (0u)
#define CAN_1_ACK_ERR (0u)
#define CAN_1_FORM_ERR (0u)
#define CAN_1_CRC_ERR (0u)
#define CAN_1_BUS_OFF (0u)
#define CAN_1_RX_MSG_LOST (0u)
#define CAN_1_TX_MESSAGE (0u)
#define CAN_1_RX_MESSAGE (1u)
#define CAN_1_ARB_LOST_USE_HELPER (1u)
#define CAN_1_OVERLOAD_USE_HELPER (1u)
#define CAN_1_BIT_ERR_USE_HELPER (1u)
#define CAN_1_STUFF_ERR_USE_HELPER (1u)
#define CAN_1_ACK_ERR_USE_HELPER (1u)
#define CAN_1_FORM_ERR_USE_HELPER (1u)
#define CAN_1_CRC_ERR_USE_HELPER (1u)
#define CAN_1_BUS_OFF_USE_HELPER (1u)
#define CAN_1_RX_MSG_LOST_USE_HELPER (1u)
#define CAN_1_TX_MESSAGE_USE_HELPER (1u)
#define CAN_1_RX_MESSAGE_USE_HELPER (1u)
#if (!(CY_PSOC3 || CY_PSOC5))
#define CAN_1_RTR_AUTO_MSG_SENT (0u)
#define CAN_1_STUCK_AT_ZERO (0u)
#define CAN_1_SST_FAILURE (0u)
#define CAN_1_RTR_MESSAGE_USE_HELPER (1u)
#define CAN_1_STUCK_AT_ZERO_USE_HELPER (1u)
#define CAN_1_SST_FAILURE_USE_HELPER (1u)
#endif /* (!(CY_PSOC3 || CY_PSOC5)) */
#define CAN_1_ADVANCED_INTERRUPT_CFG (0u)
/* TX/RX Function Enable */
#define CAN_1_TX0_FUNC_ENABLE (0u)
#define CAN_1_TX1_FUNC_ENABLE (0u)
#define CAN_1_TX2_FUNC_ENABLE (0u)
#define CAN_1_TX3_FUNC_ENABLE (0u)
#define CAN_1_TX4_FUNC_ENABLE (0u)
#define CAN_1_TX5_FUNC_ENABLE (0u)
#define CAN_1_TX6_FUNC_ENABLE (0u)
#define CAN_1_TX7_FUNC_ENABLE (0u)
#define CAN_1_RX0_FUNC_ENABLE (1u)
#define CAN_1_RX1_FUNC_ENABLE (1u)
#define CAN_1_RX2_FUNC_ENABLE (1u)
#define CAN_1_RX3_FUNC_ENABLE (1u)
#define CAN_1_RX4_FUNC_ENABLE (1u)
#define CAN_1_RX5_FUNC_ENABLE (1u)
#define CAN_1_RX6_FUNC_ENABLE (1u)
#define CAN_1_RX7_FUNC_ENABLE (1u)
#define CAN_1_RX8_FUNC_ENABLE (1u)
#define CAN_1_RX9_FUNC_ENABLE (0u)
#define CAN_1_RX10_FUNC_ENABLE (0u)
#define CAN_1_RX11_FUNC_ENABLE (0u)
#define CAN_1_RX12_FUNC_ENABLE (0u)
#define CAN_1_RX13_FUNC_ENABLE (0u)
#define CAN_1_RX14_FUNC_ENABLE (0u)
#define CAN_1_RX15_FUNC_ENABLE (0u)
#define CAN_1_RX_MAILBOX_TYPE (0x1FFu)
#define CAN_1_TX_MAILBOX_TYPE (0x0u)
/***************************************
* Data Struct Definition
***************************************/
/* Struct for DATA of BASIC CAN mailbox */
typedef struct
{
uint8 byte[8u];
} CAN_1_DATA_BYTES_MSG;
/* Struct for DATA of CAN RX register */
typedef struct
{
reg8 byte[8u];
} CAN_1_DATA_BYTES;
/* Struct for 32-bit CAN register */
typedef struct
{
reg8 byte[4u];
} CAN_1_REG_32;
/* Struct for BASIC CAN mailbox to send messages */
typedef struct
{
uint32 id;
uint8 rtr;
uint8 ide;
uint8 dlc;
uint8 irq;
#if (!(CY_PSOC3 || CY_PSOC5))
uint8 sst;
#endif /* (!(CY_PSOC3 || CY_PSOC5)) */
CAN_1_DATA_BYTES_MSG *msg;
} CAN_1_TX_MSG;
/* Constant configuration of CAN RX */
typedef struct
{
uint8 rxmailbox;
uint32 rxcmd;
uint32 rxamr;
uint32 rxacr;
} CAN_1_RX_CFG;
/* Constant configuration of CAN TX */
typedef struct
{
uint8 txmailbox;
uint32 txcmd;
uint32 txid;
} CAN_1_TX_CFG;
/* CAN RX registers */
typedef struct
{
CAN_1_REG_32 rxcmd;
CAN_1_REG_32 rxid;
CAN_1_DATA_BYTES rxdata;
CAN_1_REG_32 rxamr;
CAN_1_REG_32 rxacr;
CAN_1_REG_32 rxamrd;
CAN_1_REG_32 rxacrd;
} CAN_1_RX_STRUCT;
/* CAN TX registers */
typedef struct
{
CAN_1_REG_32 txcmd;
CAN_1_REG_32 txid;
CAN_1_DATA_BYTES txdata;
} CAN_1_TX_STRUCT;
/* Sleep Mode API Support */
typedef struct
{
uint8 enableState;
#if (CY_PSOC3 || CY_PSOC5)
uint32 intSr;
uint32 intEn;
uint32 cmd;
uint32 cfg;
#endif /* CY_PSOC3 || CY_PSOC5 */
} CAN_1_BACKUP_STRUCT;
/***************************************
* Function Prototypes
***************************************/
uint8 CAN_1_Init(void) ;
uint8 CAN_1_Start(void) ;
uint8 CAN_1_Stop(void) ;
uint8 CAN_1_Enable(void) ;
uint8 CAN_1_GlobalIntEnable(void) ;
uint8 CAN_1_GlobalIntDisable(void) ;
uint8 CAN_1_SetPreScaler(uint16 bitrate) ;
uint8 CAN_1_SetArbiter(uint8 arbiter) ;
uint8 CAN_1_SetTsegSample(uint8 cfgTseg1, uint8 cfgTseg2, uint8 sjw, uint8 sm)
;
uint8 CAN_1_SetRestartType(uint8 reset) ;
uint8 CAN_1_SetEdgeMode(uint8 edge) ;
uint8 CAN_1_SetOpMode(uint8 opMode) ;
uint8 CAN_1_RXRegisterInit(reg32 *regAddr, uint32 config)
;
uint8 CAN_1_SetIrqMask(uint16 mask) ;
uint8 CAN_1_GetTXErrorFlag(void) ;
uint8 CAN_1_GetRXErrorFlag(void) ;
uint8 CAN_1_GetTXErrorCount(void) ;
uint8 CAN_1_GetRXErrorCount(void) ;
uint8 CAN_1_GetErrorState(void) ;
void CAN_1_Sleep(void) ;
void CAN_1_Wakeup(void) ;
void CAN_1_SaveConfig(void) ;
void CAN_1_RestoreConfig(void) ;
#if (!(CY_PSOC3 || CY_PSOC5))
uint8 CAN_1_SetSwapDataEndianness(uint8 swap);
uint8 CAN_1_SetErrorCaptureRegisterMode(uint8 ecrMode);
uint32 CAN_1_ReadErrorCaptureRegister(void);
uint8 CAN_1_ArmErrorCaptureRegister(void);
#endif /* (!(CY_PSOC3 || CY_PSOC5)) */
#if (CAN_1_ARB_LOST)
void CAN_1_ArbLostIsr(void) ;
#endif /* CAN_1_ARB_LOST */
#if (CAN_1_OVERLOAD)
void CAN_1_OvrLdErrorIsr(void) ;
#endif /* CAN_1_OVERLOAD */
#if (CAN_1_BIT_ERR)
void CAN_1_BitErrorIsr(void) ;
#endif /* CAN_1_BIT_ERR */
#if (CAN_1_STUFF_ERR)
void CAN_1_BitStuffErrorIsr(void) ;
#endif /* CAN_1_STUFF_ERR */
#if (CAN_1_ACK_ERR)
void CAN_1_AckErrorIsr(void) ;
#endif /* CAN_1_ACK_ERR */
#if (CAN_1_FORM_ERR)
void CAN_1_MsgErrorIsr(void) ;
#endif /* CAN_1_FORM_ERR */
#if (CAN_1_CRC_ERR)
void CAN_1_CrcErrorIsr(void) ;
#endif /* CAN_1_CRC_ERR */
#if (CAN_1_BUS_OFF)
void CAN_1_BusOffIsr(void) ;
#endif /* CAN_1_BUS_OFF */
#if (CAN_1_RX_MSG_LOST)
void CAN_1_MsgLostIsr(void) ;
#endif /* CAN_1_RX_MSG_LOST */
#if (CAN_1_TX_MESSAGE)
void CAN_1_MsgTXIsr(void) ;
#endif /* CAN_1_TX_MESSAGE */
#if (CAN_1_RX_MESSAGE)
void CAN_1_MsgRXIsr(void) ;
#endif /* CAN_1_RX_MESSAGE */
#if (!(CY_PSOC3 || CY_PSOC5))
#if (CAN_1_RTR_AUTO_MSG_SENT)
void CAN_1_RtrAutoMsgSentIsr(void);
#endif /* CAN_1_RTR_MESSAGE */
#if (CAN_1_STUCK_AT_ZERO)
void CAN_1_StuckAtZeroIsr(void);
#endif /* CAN_1_STUCK_AT_ZERO */
#if (CAN_1_SST_FAILURE)
void CAN_1_SSTErrorIsr(void);
#endif /* CAN_1_SST_ERROR */
#endif /* (!(CY_PSOC3 || CY_PSOC5)) */
uint8 CAN_1_RxBufConfig(const CAN_1_RX_CFG *rxConfig) \
;
uint8 CAN_1_TxBufConfig(const CAN_1_TX_CFG *txConfig) \
;
uint8 CAN_1_RxTxBuffersConfig(void) ;
uint8 CAN_1_SendMsg(const CAN_1_TX_MSG *message) ;
void CAN_1_TxCancel(uint8 bufferId) ;
void CAN_1_ReceiveMsg(uint8 rxMailbox) ;
#if (CAN_1_TX0_FUNC_ENABLE)
uint8 CAN_1_SendMsg0(void) ;
#endif /* CAN_1_TX0_FUNC_ENABLE */
#if (CAN_1_TX1_FUNC_ENABLE)
uint8 CAN_1_SendMsg1(void) ;
#endif /* CAN_1_TX1_FUNC_ENABLE */
#if (CAN_1_TX2_FUNC_ENABLE)
uint8 CAN_1_SendMsg2(void) ;
#endif /* CAN_1_TX2_FUNC_ENABLE */
#if (CAN_1_TX3_FUNC_ENABLE)
uint8 CAN_1_SendMsg3(void) ;
#endif /* CAN_1_TX3_FUNC_ENABLE */
#if (CAN_1_TX4_FUNC_ENABLE)
uint8 CAN_1_SendMsg4(void) ;
#endif /* CAN_1_TX4_FUNC_ENABLE */
#if (CAN_1_TX5_FUNC_ENABLE)
uint8 CAN_1_SendMsg5(void) ;
#endif /* CAN_1_TX5_FUNC_ENABLE */
#if (CAN_1_TX6_FUNC_ENABLE)
uint8 CAN_1_SendMsg6(void) ;
#endif /* CAN_1_TX6_FUNC_ENABLE */
#if (CAN_1_TX7_FUNC_ENABLE)
uint8 CAN_1_SendMsg7(void) ;
#endif /* CAN_1_TX7_FUNC_ENABLE */
#if (CAN_1_RX0_FUNC_ENABLE)
void CAN_1_ReceiveMsgStart(void) ;
#endif /* CAN_1_RX0_FUNC_ENABLE */
#if (CAN_1_RX1_FUNC_ENABLE)
void CAN_1_ReceiveMsgMode(void) ;
#endif /* CAN_1_RX1_FUNC_ENABLE */
#if (CAN_1_RX2_FUNC_ENABLE)
void CAN_1_ReceiveMsgID(void) ;
#endif /* CAN_1_RX2_FUNC_ENABLE */
#if (CAN_1_RX3_FUNC_ENABLE)
void CAN_1_ReceiveMsgName(void) ;
#endif /* CAN_1_RX3_FUNC_ENABLE */
#if (CAN_1_RX4_FUNC_ENABLE)
void CAN_1_ReceiveMsgStatus(void) ;
#endif /* CAN_1_RX4_FUNC_ENABLE */
#if (CAN_1_RX5_FUNC_ENABLE)
void CAN_1_ReceiveMsgGetConfig(void) ;
#endif /* CAN_1_RX5_FUNC_ENABLE */
#if (CAN_1_RX6_FUNC_ENABLE)
void CAN_1_ReceiveMsgUpdateConfig(void) ;
#endif /* CAN_1_RX6_FUNC_ENABLE */
#if (CAN_1_RX7_FUNC_ENABLE)
void CAN_1_ReceiveMsgSoftReset(void) ;
#endif /* CAN_1_RX7_FUNC_ENABLE */
#if (CAN_1_RX8_FUNC_ENABLE)
void CAN_1_ReceiveMsgHalt(void) ;
#endif /* CAN_1_RX8_FUNC_ENABLE */
#if (CAN_1_RX9_FUNC_ENABLE)
void CAN_1_ReceiveMsg9(void) ;
#endif /* CAN_1_RX9_FUNC_ENABLE */
#if (CAN_1_RX10_FUNC_ENABLE)
void CAN_1_ReceiveMsg10(void) ;
#endif /* CAN_1_RX10_FUNC_ENABLE */
#if (CAN_1_RX11_FUNC_ENABLE)
void CAN_1_ReceiveMsg11(void) ;
#endif /* CAN_1_RX11_FUNC_ENABLE */
#if (CAN_1_RX12_FUNC_ENABLE)
void CAN_1_ReceiveMsg12(void) ;
#endif /* CAN_1_RX12_FUNC_ENABLE */
#if (CAN_1_RX13_FUNC_ENABLE)
void CAN_1_ReceiveMsg13(void) ;
#endif /* CAN_1_RX13_FUNC_ENABLE */
#if (CAN_1_RX14_FUNC_ENABLE)
void CAN_1_ReceiveMsg14(void) ;
#endif /* CAN_1_RX14_FUNC_ENABLE */
#if (CAN_1_RX15_FUNC_ENABLE)
void CAN_1_ReceiveMsg15(void) ;
#endif /* CAN_1_RX15_FUNC_ENABLE */
#if(!CAN_1_INT_ISR_DISABLE)
/* Interrupt handler */
CY_ISR_PROTO(CAN_1_ISR);
#endif /* !CAN_1_INT_ISR_DISABLE */
/***************************************
* API Constants
***************************************/
#if (!CAN_1_INT_ISR_DISABLE)
/* Number of CAN_1_isr interrupt */
#define CAN_1_ISR_NUMBER ((uint8) CAN_1_isr__INTC_NUMBER)
/* Priority of CAN_1_isr interrupt */
#define CAN_1_ISR_PRIORITY ((uint8) CAN_1_isr__INTC_PRIOR_NUM)
#endif /* !CAN_1_INT_ISR_DISABLE */
/* One bit time in CAN clock cycles */
#define CAN_1_ONE_BIT_TIME ((CAN_1_BITRATE + 1u) * \
((CAN_1_CFG_REG_TSEG1 + 1u) + (CAN_1_CFG_REG_TSEG2 + 1u) + 1u))
/* Timeout for CAN state machine to switch operation mode to Run */
#define CAN_1_MODE_STATE_RUN_TIMEOUT (12u * CAN_1_ONE_BIT_TIME)
/* Timeout for CAN state machine to switch operation mode to Stop */
#define CAN_1_MODE_STATE_STOP_TIMEOUT (160u * CAN_1_ONE_BIT_TIME)
/* One or more parameters to function were invalid. */
#define CAN_1_FAIL (0x01u)
#define CAN_1_OUT_OF_RANGE (0x02u)
#if (CY_PSOC3 || CY_PSOC5)
/* PM_ACT_CFG (Active Power Mode CFG Register) */
#define CAN_1_ACT_PWR_EN (CAN_1_CanIP__PM_ACT_MSK) /* Power enable mask */
/* PM_STBY_CFG (Alternate Active (Standby) Power Mode CFG Register) */
#define CAN_1_STBY_PWR_EN (CAN_1_CanIP__PM_STBY_MSK) /* Power enable mask */
#endif /* CY_PSOC3 || CY_PSOC5 */
/* Number of TX and RX mailboxes */
#define CAN_1_NUMBER_OF_TX_MAILBOXES (8u)
#define CAN_1_NUMBER_OF_RX_MAILBOXES (16u)
/* Error status of CAN */
#define CAN_1_ERROR_ACTIVE (0x00u)
#define CAN_1_ERROR_PASIVE (0x01u)
#define CAN_1_ERROR_BUS_OFF (0x10u)
/* Operation mode */
#define CAN_1_INITIAL_MODE (0x00u)
#define CAN_1_STOP_MODE (0x00u)
#define CAN_1_ACTIVE_RUN_MODE (0x01u)
#define CAN_1_LISTEN_ONLY_MODE (0x02u)
#if (!(CY_PSOC3 || CY_PSOC5))
#define CAN_1_INTERNAL_LOOP_BACK (0x06u)
#define CAN_1_EXTERNAL_LOOP_BACK (0x04u)
#endif /* (!(CY_PSOC3 || CY_PSOC5)) */
/* TX Defines to link mailbox names with mailbox numbers */
#define CAN_1_TX_MAILBOX_0 (0u)
#define CAN_1_TX_MAILBOX_1 (1u)
#define CAN_1_TX_MAILBOX_2 (2u)
#define CAN_1_TX_MAILBOX_3 (3u)
#define CAN_1_TX_MAILBOX_4 (4u)
#define CAN_1_TX_MAILBOX_5 (5u)
#define CAN_1_TX_MAILBOX_6 (6u)
#define CAN_1_TX_MAILBOX_7 (7u)
/* RX Defines to link mailbox names with mailbox numbers */
#define CAN_1_RX_MAILBOX_Start (0u)
#define CAN_1_RX_MAILBOX_Mode (1u)
#define CAN_1_RX_MAILBOX_ID (2u)
#define CAN_1_RX_MAILBOX_Name (3u)
#define CAN_1_RX_MAILBOX_Status (4u)
#define CAN_1_RX_MAILBOX_GetConfig (5u)
#define CAN_1_RX_MAILBOX_UpdateConfig (6u)
#define CAN_1_RX_MAILBOX_SoftReset (7u)
#define CAN_1_RX_MAILBOX_Halt (8u)
#define CAN_1_RX_MAILBOX_9 (9u)
#define CAN_1_RX_MAILBOX_10 (10u)
#define CAN_1_RX_MAILBOX_11 (11u)
#define CAN_1_RX_MAILBOX_12 (12u)
#define CAN_1_RX_MAILBOX_13 (13u)
#define CAN_1_RX_MAILBOX_14 (14u)
#define CAN_1_RX_MAILBOX_15 (15u)
/***************************************
* Initial Parameter Constants
***************************************/
/* General */
#define CAN_1_BITRATE (3u)
#define CAN_1_CFG_REG_TSEG1 (14u - 1u)
#define CAN_1_CFG_REG_TSEG2 (3u - 1u)
#define CAN_1_CFG_REG_SJW (3u - 1u)
#define CAN_1_SAMPLING_MODE (1u)
#define CAN_1_ARBITER (1u)
#define CAN_1_RESET_TYPE (0u)
#define CAN_1_SYNC_EDGE (0u)
#if (!(CY_PSOC3 || CY_PSOC5))
#define CAN_1_SWAP_DATA_END (0u)
#endif /* (!(CY_PSOC3 || CY_PSOC5)) */
/* Interrupts */
#define CAN_1_INT_ENABLE (1u)
#if (CY_PSOC3 || CY_PSOC5)
#define CAN_1_INIT_INTERRUPT_MASK (((uint16) CAN_1_INT_ENABLE) | \
((uint16) ((uint16) CAN_1_ARB_LOST << CAN_1_ARBITRATION_LOST_SHIFT)) | \
((uint16) ((uint16) CAN_1_OVERLOAD << CAN_1_OVERLOAD_ERROR_SHIFT)) | \
((uint16) ((uint16) CAN_1_BIT_ERR << CAN_1_BIT_ERROR_SHIFT)) | \
((uint16) ((uint16) CAN_1_STUFF_ERR << CAN_1_STUFF_ERROR_SHIFT)) | \
((uint16) ((uint16) CAN_1_ACK_ERR << CAN_1_ACK_ERROR_SHIFT)) | \
((uint16) ((uint16) CAN_1_FORM_ERR << CAN_1_FORM_ERROR_SHIFT)) | \
((uint16) ((uint16) CAN_1_CRC_ERR << (CAN_1_ONE_BYTE_OFFSET + \
CAN_1_CRC_ERROR_SHIFT))) | \
((uint16) ((uint16) CAN_1_BUS_OFF << (CAN_1_ONE_BYTE_OFFSET + \
CAN_1_BUS_OFF_SHIFT))) | \
((uint16) ((uint16) CAN_1_RX_MSG_LOST << (CAN_1_ONE_BYTE_OFFSET + \
CAN_1_RX_MSG_LOST_SHIFT))) | \
((uint16) ((uint16) CAN_1_TX_MESSAGE << (CAN_1_ONE_BYTE_OFFSET + \
CAN_1_TX_MESSAGE_SHIFT))) | \
((uint16) ((uint16) CAN_1_RX_MESSAGE << (CAN_1_ONE_BYTE_OFFSET + \
CAN_1_RX_MESSAGE_SHIFT))))
#else /* CY_PSOC4 */
#define CAN_1_INIT_INTERRUPT_MASK (((uint16) CAN_1_INT_ENABLE) | \
((uint16) ((uint16) CAN_1_ARB_LOST << CAN_1_ARBITRATION_LOST_SHIFT)) | \
((uint16) ((uint16) CAN_1_OVERLOAD << CAN_1_OVERLOAD_ERROR_SHIFT)) | \
((uint16) ((uint16) CAN_1_BIT_ERR << CAN_1_BIT_ERROR_SHIFT)) | \
((uint16) ((uint16) CAN_1_STUFF_ERR << CAN_1_STUFF_ERROR_SHIFT)) | \
((uint16) ((uint16) CAN_1_ACK_ERR << CAN_1_ACK_ERROR_SHIFT)) | \
((uint16) ((uint16) CAN_1_FORM_ERR << CAN_1_FORM_ERROR_SHIFT)) | \
((uint16) ((uint16) CAN_1_CRC_ERR << CAN_1_CRC_ERROR_SHIFT)) | \
((uint16) ((uint16) CAN_1_BUS_OFF << CAN_1_BUS_OFF_SHIFT)) | \
((uint16) ((uint16) CAN_1_RX_MSG_LOST << CAN_1_RX_MSG_LOST_SHIFT)) | \
((uint16) ((uint16) CAN_1_TX_MESSAGE << CAN_1_TX_MESSAGE_SHIFT)) | \
((uint16) ((uint16) CAN_1_RX_MESSAGE << CAN_1_RX_MESSAGE_SHIFT)) | \
((uint16) ((uint16) CAN_1_RTR_AUTO_MSG_SENT << CAN_1_RTR_MSG_SHIFT)) | \
((uint16) ((uint16) CAN_1_STUCK_AT_ZERO << CAN_1_STUCK_AT_ZERO_SHIFT)) | \
((uint16) ((uint16) CAN_1_SST_FAILURE << CAN_1_SST_FAILURE_SHIFT)))
#endif /* (CY_PSOC3 || CY_PSOC5) */
/***************************************
* Registers
***************************************/
#if (CY_PSOC3 || CY_PSOC5)
#define CAN_1_TX ( (volatile CAN_1_TX_STRUCT XDATA *) CAN_1_CanIP__TX0_CMD)
#define CAN_1_RX ( (volatile CAN_1_RX_STRUCT XDATA *) CAN_1_CanIP__RX0_CMD)
#define CAN_1_INT_SR_REG (*(volatile CAN_1_REG_32 XDATA *) CAN_1_CanIP__CSR_INT_SR)
#define CAN_1_INT_SR_PTR ( (reg32 *) CAN_1_CanIP__CSR_INT_SR)
#define CAN_1_INT_EN_REG (*(volatile CAN_1_REG_32 XDATA *) CAN_1_CanIP__CSR_INT_EN)
#define CAN_1_INT_EN_PTR ( (reg32 *) CAN_1_CanIP__CSR_INT_EN)
#define CAN_1_BUF_SR_REG (*(volatile CAN_1_REG_32 XDATA *) CAN_1_CanIP__CSR_BUF_SR)
#define CAN_1_BUF_SR_PTR ( (reg32 *) CAN_1_CanIP__CSR_BUF_SR)
#define CAN_1_ERR_SR_REG (*(volatile CAN_1_REG_32 XDATA *) CAN_1_CanIP__CSR_ERR_SR)
#define CAN_1_ERR_SR_PTR ( (reg32 *) CAN_1_CanIP__CSR_ERR_SR)
#define CAN_1_CMD_REG (*(volatile CAN_1_REG_32 XDATA *) CAN_1_CanIP__CSR_CMD)
#define CAN_1_CMD_PTR ( (reg32 *) CAN_1_CanIP__CSR_CMD)
#define CAN_1_CFG_REG (*(volatile CAN_1_REG_32 XDATA *) CAN_1_CanIP__CSR_CFG)
#define CAN_1_CFG_PTR ( (reg32 *) CAN_1_CanIP__CSR_CFG)
/* Power manager */
#define CAN_1_PM_ACT_CFG_REG (*(reg8 *) CAN_1_CanIP__PM_ACT_CFG)
#define CAN_1_PM_ACT_CFG_PTR ( (reg8 *) CAN_1_CanIP__PM_ACT_CFG)
#define CAN_1_PM_STBY_CFG_REG (*(reg8 *) CAN_1_CanIP__PM_STBY_CFG)
#define CAN_1_PM_STBY_CFG_PTR ( (reg8 *) CAN_1_CanIP__PM_STBY_CFG)
#define CAN_1_RX_FIRST_REGISTER_PTR ((reg32 *) CAN_1_CanIP__RX0_CMD)
#define CAN_1_RX_LAST_REGISTER_PTR ((reg32 *) CAN_1_CanIP__RX15_ACRD)
#else /* CY_PSOC4 */
#define CAN_1_TX ((volatile CAN_1_TX_STRUCT XDATA *) CAN_1_CanIP__CAN_TX0_CONTROL)
#define CAN_1_RX ((volatile CAN_1_RX_STRUCT XDATA *) CAN_1_CanIP__CAN_RX0_CONTROL)
#define CAN_1_TX_REG (*(reg32 *) CAN_1_CanIP__CAN_TX0_CONTROL)
#define CAN_1_TX_PTR ( (reg32 *) CAN_1_CanIP__CAN_TX0_CONTROL)
#define CAN_1_RX_REG (*(reg32 *) CAN_1_CanIP__CAN_RX0_CONTROL)
#define CAN_1_RX_PTR ( (reg32 *) CAN_1_CanIP__CAN_RX0_CONTROL)
#define CAN_1_INT_SR_REG (*(reg32 *) CAN_1_CanIP__INT_STATUS)
#define CAN_1_INT_SR_PTR ( (reg32 *) CAN_1_CanIP__INT_STATUS)
#define CAN_1_INT_EN_REG (*(reg32 *) CAN_1_CanIP__INT_EBL)
#define CAN_1_INT_EN_PTR ( (reg32 *) CAN_1_CanIP__INT_EBL)
#define CAN_1_BUF_SR_REG (*(reg32 *) CAN_1_CanIP__BUFFER_STATUS)
#define CAN_1_BUF_SR_PTR ( (reg32 *) CAN_1_CanIP__BUFFER_STATUS)
#define CAN_1_ERR_SR_REG (*(reg32 *) CAN_1_CanIP__ERROR_STATUS)
#define CAN_1_ERR_SR_PTR ( (reg32 *) CAN_1_CanIP__ERROR_STATUS)
#define CAN_1_CNTL_REG (*(reg32 *) CAN_1_CanIP__CNTL)
#define CAN_1_CNTL_PTR ( (reg32 *) CAN_1_CanIP__CNTL)
#define CAN_1_CMD_REG (*(reg32 *) CAN_1_CanIP__COMMAND)
#define CAN_1_CMD_PTR ( (reg32 *) CAN_1_CanIP__COMMAND)
#define CAN_1_CFG_REG (*(reg32 *) CAN_1_CanIP__CONFIG)
#define CAN_1_CFG_PTR ( (reg32 *) CAN_1_CanIP__CONFIG)
#define CAN_1_ECR_REG (*(reg32 *) CAN_1_CanIP__ECR)
#define CAN_1_ECR_PTR ( (reg32 *) CAN_1_CanIP__ECR)
#define CAN_1_RX_FIRST_REGISTER_PTR ( (reg32 *) CAN_1_CanIP__CAN_RX0_CONTROL)
#define CAN_1_RX_LAST_REGISTER_PTR ( (reg32 *) CAN_1_CanIP__CAN_RX15_ACR_DATA)
#define CAN_1_TX_DATA_LO_REG(i) (*(reg32 *) (&CAN_1_TX[i].txdata))
#define CAN_1_TX_DATA_HI_REG(i) (*(reg32 *) ((uint32) (&CAN_1_TX[i].txdata) + \
CAN_1_DATA_HIGH_ADDR))
#define CAN_1_RX_DATA_LO_REG(i) (*(reg32 *) (&CAN_1_RX[i].rxdata))
#define CAN_1_RX_DATA_HI_REG(i) (*(reg32 *) ((uint32) (&CAN_1_RX[i].rxdata) + \
CAN_1_DATA_HIGH_ADDR))
#endif /* (CY_PSOC3 || CY_PSOC5) */
#define CAN_1_TX_CMD_PTR(i) ( (reg32 *) (&CAN_1_TX[i].txcmd))
#define CAN_1_TX_CMD_REG(i) (*(reg32 *) (&CAN_1_TX[i].txcmd))
#define CAN_1_RX_CMD_PTR(i) ( (reg32 *) (&CAN_1_RX[i].rxcmd))
#define CAN_1_RX_CMD_REG(i) (*(reg32 *) (&CAN_1_RX[i].rxcmd))
#define CAN_1_RX_ID_PTR(i) ( (reg32 *) (&CAN_1_RX[i].rxid))
#define CAN_1_RX_ID_REG(i) (*(reg32 *) (&CAN_1_RX[i].rxid))
#define CAN_1_TX_ID_PTR(i) ( (reg32 *) (&CAN_1_TX[i].txid))
#define CAN_1_TX_ID_REG(i) (*(reg32 *) (&CAN_1_TX[i].txid))
/***************************************
* Register Constants
***************************************/
/* Run/Stop mode */
#define CAN_1_MODE_STOP (0x00u)
#define CAN_1_MODE_START (0x01u)
/* Transmit buffer arbiter */
#define CAN_1_ROUND_ROBIN (0x00u)
#define CAN_1_FIXED_PRIORITY (0x01u)
/* Restart type */
#define CAN_1_MANUAL_RESTART (0x00u)
#define CAN_1_AUTO_RESTART (0x01u)
/* Sampling mode */
#define CAN_1_ONE_SAMPLE_POINT (0x00u)
#define CAN_1_THREE_SAMPLE_POINTS (0x01u)
/* Edge mode */
#define CAN_1_EDGE_R_TO_D (0x00u)
#define CAN_1_BOTH_EDGES (0x01u)
/* Extended identifier */
#define CAN_1_STANDARD_MESSAGE (0x00u)
#define CAN_1_EXTENDED_MESSAGE (0x01u)
/* Write Protect Mask for Basic and Full mailboxes */
#define CAN_1_TX_WPN_CLEAR ((uint32) (~CAN_1_TX_WPN_SET))
#define CAN_1_RX_WPN_CLEAR ((uint32) (~CAN_1_RX_WPN_SET))
#define CAN_1_TX_RSVD_MASK ((uint32) 0x00FF00FFu)
#define CAN_1_TX_READ_BACK_MASK (CAN_1_TX_WPN_CLEAR & CAN_1_TX_RSVD_MASK)
#define CAN_1_RX_READ_BACK_MASK (CAN_1_RX_WPN_CLEAR & CAN_1_TX_RSVD_MASK)
#define CAN_1_RX_CMD_REG_WIDTH (0x20u)
#if (CY_PSOC3 || CY_PSOC5)
#define CAN_1_TX_WPN_SET (((uint32) ((uint32) 0x00000001u << CAN_1_TX_WPNL_SHIFT)) | \
((uint32) ((uint32) 0x00000001u << (CAN_1_TWO_BYTE_OFFSET + CAN_1_TX_WPNH_SHIFT))))
#define CAN_1_RX_WPN_SET (((uint32) ((uint32) 0x00000001u << CAN_1_RX_WPNL_SHIFT)) | \
((uint32) ((uint32) 0x00000001u << (CAN_1_TWO_BYTE_OFFSET + CAN_1_RX_WPNH_SHIFT))))
#else /* CY_PSOC4 */
#define CAN_1_TX_WPN_SET (((uint32) ((uint32) 0x00000001u << CAN_1_TX_WPNL_SHIFT)) | \
((uint32) ((uint32) 0x00000001u << CAN_1_TX_WPNH_SHIFT)))
#define CAN_1_RX_WPN_SET (((uint32) ((uint32) 0x00000001u << CAN_1_RX_WPNL_SHIFT)) | \
((uint32) ((uint32) 0x00000001u << CAN_1_RX_WPNH_SHIFT)))
/* CAN IP Block Enable */
#define CAN_1_IP_ENABLE_SHIFT (31u)
#define CAN_1_IP_ENABLE ((uint32) ((uint32) 0x00000001u << CAN_1_IP_ENABLE_SHIFT))
/* Error Capture register mode setting */
#define CAN_1_ECR_FREE_RUNNING (0x00u)
#define CAN_1_ECR_ERROR_CAPTURE (0x01u)
/* Swap Endian */
#define CAN_1_SWAP_ENDIANNESS_DISABLE (0x00u)
#define CAN_1_SWAP_ENDIANNESS_ENABLE (0x01u)
#endif /* (CY_PSOC3 || CY_PSOC5) */
/* TX send message */
#define CAN_1_TX_REQUEST_PENDING (0x01u)
#define CAN_1_RETRY_NUMBER (0x03u)
#define CAN_1_SEND_MESSAGE_SHIFT (0u)
#define CAN_1_SEND_MESSAGE ((uint32) ((uint32) 0x00000001u << CAN_1_SEND_MESSAGE_SHIFT))
/* Offsets to maintain bytes within uint32 */
#define CAN_1_ONE_BYTE_OFFSET (8u)
#define CAN_1_TWO_BYTE_OFFSET (16u)
#define CAN_1_THREE_BYTE_OFFSET (24u)
#if (CY_PSOC3 || CY_PSOC5)
/* Set/Clear bits macro for CAN_1_RX mailbox(i) */
/* Bit 0 within RX_CMD[i] */
#define CAN_1_RX_ACK_MSG_SHIFT (0u)
#define CAN_1_RX_ACK_MSG ((uint8) ((uint8) 0x01u << CAN_1_RX_ACK_MSG_SHIFT))
/* Bit 2 within RX_CMD[i] */
#define CAN_1_RX_RTR_ABORT_SHIFT (2u)
#define CAN_1_RX_RTR_ABORT_MASK ((uint8) ((uint8) 0x01u << CAN_1_RX_RTR_ABORT_SHIFT))
/* Bit 3 within RX_CMD[i] */
#define CAN_1_RX_BUF_ENABLE_SHIFT (3u)
#define CAN_1_RX_BUF_ENABLE_MASK ((uint8) ((uint8) 0x01u << CAN_1_RX_BUF_ENABLE_SHIFT))
/* Bit 4 within RX_CMD[i] */
#define CAN_1_RX_RTRREPLY_SHIFT (4u)
#define CAN_1_RX_RTRREPLY_MASK ((uint8) ((uint8) 0x01u << CAN_1_RX_RTRREPLY_SHIFT))
/* Bit 5 within RX_CMD[i] */
#define CAN_1_RX_INT_ENABLE_SHIFT (5u)
#define CAN_1_RX_INT_ENABLE_MASK ((uint8) ((uint8) 0x01u << CAN_1_RX_INT_ENABLE_SHIFT))
/* Bit 6 within RX_CMD[i] */
#define CAN_1_RX_LINKING_SHIFT (6u)
#define CAN_1_RX_LINKING_MASK ((uint8) ((uint8) 0x01u << CAN_1_RX_LINKING_SHIFT))
/* Bit 7 within RX_CMD[i] */
#define CAN_1_RX_WPNL_SHIFT (7u)
#define CAN_1_RX_WPNL_MASK ((uint8) ((uint8) 0x01u << CAN_1_RX_WPNL_SHIFT))
/* Bits 19-16 within RX_CMD[i] */
#define CAN_1_RX_DLC_VALUE_SHIFT (0u)
#define CAN_1_RX_DLC_VALUE_MASK ((uint8) ((uint8) 0x0Fu << CAN_1_RX_DLC_VALUE_SHIFT))
/* Bit 20 within RX_CMD[i] */
#define CAN_1_RX_IDE_SHIFT (4u)
#define CAN_1_RX_IDE_MASK ((uint8) ((uint8) 0x01u << CAN_1_RX_IDE_SHIFT))
/* Bit 23 within RX_CMD[i] */
#define CAN_1_RX_WPNH_SHIFT (7u)
#define CAN_1_RX_WPNH_MASK ((uint8) ((uint8) 0x01u << CAN_1_RX_WPNH_SHIFT))
#define CAN_1_RX_ACK_MESSAGE(i) (CAN_1_RX[i].rxcmd.byte[0u] |= CAN_1_RX_ACK_MSG)
#define CAN_1_RX_RTR_ABORT_MESSAGE(i) \
(CAN_1_RX[i].rxcmd.byte[0u] |= CAN_1_RX_RTR_ABORT_MASK)
#define CAN_1_RX_BUF_ENABLE(i) \
(CAN_1_RX[i].rxcmd.byte[0u] |= CAN_1_RX_BUF_ENABLE_MASK)
#define CAN_1_RX_BUF_DISABLE(i) \
(CAN_1_RX[i].rxcmd.byte[0u] &= (uint8) (~CAN_1_RX_BUF_ENABLE_MASK))
#define CAN_1_SET_RX_RTRREPLY(i) \
(CAN_1_RX[i].rxcmd.byte[0u] |= CAN_1_RX_RTRREPLY_MASK)
#define CAN_1_CLEAR_RX_RTRREPLY(i) \
(CAN_1_RX[i].rxcmd.byte[0u] &= (uint8) (~CAN_1_RX_RTRREPLY_MASK))
#define CAN_1_RX_INT_ENABLE(i) \
(CAN_1_RX[i].rxcmd.byte[0u] |= CAN_1_RX_INT_ENABLE_MASK)
#define CAN_1_RX_INT_DISABLE(i) \
(CAN_1_RX[i].rxcmd.byte[0u] &= (uint8) (~CAN_1_RX_INT_ENABLE_MASK))
#define CAN_1_SET_RX_LINKING(i) \
(CAN_1_RX[i].rxcmd.byte[0u] |= CAN_1_RX_LINKING_MASK)
#define CAN_1_CLEAR_RX_LINKING(i) \
(CAN_1_RX[i].rxcmd.byte[0u] &= (uint8) (~CAN_1_RX_LINKING_MASK))
#define CAN_1_SET_RX_WNPL(i) (CAN_1_RX[i].rxcmd.byte[0u] |= CAN_1_RX_WPNL_MASK)
#define CAN_1_CLEAR_RX_WNPL(i) \
(CAN_1_RX[i].rxcmd.byte[0u] &= (uint8) (~CAN_1_RX_WPNL_MASK))
#define CAN_1_SET_RX_WNPH(i) (CAN_1_RX[i].rxcmd.byte[2u] |= CAN_1_RX_WPNH_MASK)
#define CAN_1_CLEAR_RX_WNPH(i) \
(CAN_1_RX[i].rxcmd.byte[2u] &= (uint8) (~CAN_1_RX_WPNH_MASK))
#define CAN_1_GET_DLC(i) \
(CAN_1_RX[i].rxcmd.byte[2u] & CAN_1_RX_DLC_VALUE_MASK)
#define CAN_1_GET_RX_IDE(i) ((uint8) \
(CAN_1_RX[i].rxcmd.byte[2u] & CAN_1_RX_IDE_MASK) >> CAN_1_RX_IDE_SHIFT)
#define CAN_1_GET_RX_ID(i) ((CAN_1_GET_RX_IDE(i)) ? \
(CY_GET_REG32(CAN_1_RX_ID_PTR(i)) >> CAN_1_SET_TX_ID_EXTENDED_MSG_SHIFT) : \
(CY_GET_REG32(CAN_1_RX_ID_PTR(i)) >> CAN_1_SET_TX_ID_STANDARD_MSG_SHIFT))
/* Set/Clear bits macro for CAN_1_TX mailbox(i) */
/* Bit 0 within TX_CMD[i] */
#define CAN_1_TX_TRANSMIT_REQUEST_SHIFT (0u)
#define CAN_1_TX_TRANSMIT_REQUEST ((uint8) ((uint8) 0x01u << CAN_1_TX_TRANSMIT_REQUEST_SHIFT))
/* Bit 1 within TX_CMD[i] */
#define CAN_1_TX_ABORT_SHIFT (1u)
#define CAN_1_TX_ABORT_MASK ((uint8) ((uint8) 0x01u << CAN_1_TX_ABORT_SHIFT))
/* Bit 2 within TX_CMD[i] */
#define CAN_1_TRANSMIT_INT_ENABLE (0x01u)
#define CAN_1_TRANSMIT_INT_DISABLE (0x00u)
#define CAN_1_TX_INT_ENABLE_SHIFT (2u)
#define CAN_1_TX_INT_ENABLE_MASK \
((uint32) ((uint32) 0x00000001u << CAN_1_TX_INT_ENABLE_SHIFT))
/* Bit 3 within TX_CMD[i] */
#define CAN_1_TX_WPNL_SHIFT (3u)
#define CAN_1_TX_WPNL_MASK ((uint8) ((uint8) 0x01u << CAN_1_TX_WPNL_SHIFT))
/* Bits 19-16 within TX_CMD[i] */
#define CAN_1_TX_DLC_VALUE_SHIFT (0u)
#define CAN_1_TX_DLC_UPPER_VALUE_SHIFT (19u)
#define CAN_1_TX_DLC_UPPER_VALUE \
((uint32) ((uint32) 0x00000001u << CAN_1_TX_DLC_UPPER_VALUE_SHIFT))
#define CAN_1_TX_DLC_VALUE_MASK ((uint8) ((uint8) 0x0Fu << CAN_1_TX_DLC_VALUE_SHIFT))
#define CAN_1_TX_DLC_MAX_VALUE (8u)
/* Bit 20 within TX_CMD[i] */
#define CAN_1_TX_IDE_SHIFT (20u)
#define CAN_1_TX_IDE_MASK ((uint32) ((uint32) 0x00000001u << CAN_1_TX_IDE_SHIFT))
/* Bit 21 within TX_CMD[i] */
#define CAN_1_TX_RTR_SHIFT (21u)
#define CAN_1_TX_RTR_MASK ((uint32) ((uint32) 0x00000001u << CAN_1_TX_RTR_SHIFT))
/* Bit 23 within TX_CMD[i] */
#define CAN_1_TX_WPNH_SHIFT (7u)
#define CAN_1_TX_WPNH_MASK ((uint8) ((uint8) 0x01u << CAN_1_TX_WPNH_SHIFT))
#define CAN_1_TX_TRANSMIT_MESSAGE(i) \
(CAN_1_TX[i].txcmd.byte[0u] |= CAN_1_TX_TRANSMIT_REQUEST)
#define CAN_1_TX_ABORT_MESSAGE(i) \
(CAN_1_TX[i].txcmd.byte[0u] = (CAN_1_TX[i].txcmd.byte[0u] & \
(uint8) (~CAN_1_TX_TRANSMIT_REQUEST)) | CAN_1_TX_ABORT_MASK)
#define CAN_1_TX_INT_ENABLE(i) \
(CAN_1_TX[i].txcmd.byte[0u] |= (uint8) CAN_1_TX_INT_ENABLE_MASK)
#define CAN_1_TX_INT_DISABLE(i) \
(CAN_1_TX[i].txcmd.byte[0u] &= (uint8) (~CAN_1_TX_INT_ENABLE_MASK))
#define CAN_1_SET_TX_WNPL(i) \
(CAN_1_TX[i].txcmd.byte[0u] |= CAN_1_TX_WPNL_MASK)
#define CAN_1_CLEAR_TX_WNPL(i) \
(CAN_1_TX[i].txcmd.byte[0u] &= (uint8) (~CAN_1_TX_WPNL_MASK))
#define CAN_1_SET_TX_IDE(i) (CAN_1_TX[i].txcmd.byte[2u] |= \
(uint8) (CAN_1_TX_IDE_MASK >> CAN_1_TWO_BYTE_OFFSET))
#define CAN_1_CLEAR_TX_IDE(i) (CAN_1_TX[i].txcmd.byte[2u] &= \
(uint8) (((uint32) (~CAN_1_TX_IDE_MASK)) >> CAN_1_TWO_BYTE_OFFSET))
#define CAN_1_SET_TX_RTR(i) (CAN_1_TX[i].txcmd.byte[2u] |= \
(uint8) (CAN_1_TX_RTR_MASK >> CAN_1_TWO_BYTE_OFFSET))
#define CAN_1_CLEAR_TX_RTR(i) (CAN_1_TX[i].txcmd.byte[2u] &= \
(uint8) (((uint32) (~CAN_1_TX_RTR_MASK)) >> CAN_1_TWO_BYTE_OFFSET))
#define CAN_1_SET_TX_WNPH(i) \
(CAN_1_TX[i].txcmd.byte[2u] |= CAN_1_TX_WPNH_MASK)
#define CAN_1_CLEAR_TX_WNPH(i) \
(CAN_1_TX[i].txcmd.byte[2u] &= (uint8) (~CAN_1_TX_WPNH_MASK))
#define CAN_1_RX_DATA_BYTE(mailbox, i) (CAN_1_RX[mailbox].rxdata.byte[((i) > 3u) ? \
(7u - ((i) - 4u)) : (3u - (i))])
#define CAN_1_TX_DATA_BYTE(mailbox, i) (CAN_1_TX[mailbox].txdata.byte[((i) > 3u) ? \
(7u - ((i) - 4u)) : (3u - (i))])
#else /* CY_PSOC4 */
/* Set/Clear bits macro for CAN_1_RX mailbox(i) */
/* Bit 0 within RX_CMD[i] */
#define CAN_1_RX_ACK_MSG_SHIFT (0u)
#define CAN_1_RX_ACK_MSG ((uint32) ((uint32) 0x01u << CAN_1_RX_ACK_MSG_SHIFT))
/* Bit 2 within RX_CMD[i] */
#define CAN_1_RX_RTR_ABORT_SHIFT (2u)
#define CAN_1_RX_RTR_ABORT_MASK ((uint32) ((uint32) 0x01u << CAN_1_RX_RTR_ABORT_SHIFT))
/* Bit 3 within RX_CMD[i] */
#define CAN_1_RX_BUF_ENABLE_SHIFT (3u)
#define CAN_1_RX_BUF_ENABLE_MASK ((uint32) ((uint32) 0x01u << CAN_1_RX_BUF_ENABLE_SHIFT))
/* Bit 4 within RX_CMD[i] */
#define CAN_1_RX_RTRREPLY_SHIFT (4u)
#define CAN_1_RX_RTRREPLY_MASK ((uint32) ((uint32) 0x01u << CAN_1_RX_RTRREPLY_SHIFT))
/* Bit 5 within RX_CMD[i] */
#define CAN_1_RX_INT_ENABLE_SHIFT (5u)
#define CAN_1_RX_INT_ENABLE_MASK ((uint32) ((uint32) 0x01u << CAN_1_RX_INT_ENABLE_SHIFT))
/* Bit 6 within RX_CMD[i] */
#define CAN_1_RX_LINKING_SHIFT (6u)
#define CAN_1_RX_LINKING_MASK ((uint32) ((uint32) 0x01u << CAN_1_RX_LINKING_SHIFT))
/* Bit 7 within RX_CMD[i] */
#define CAN_1_RX_WPNL_SHIFT (7u)
#define CAN_1_RX_WPNL_MASK ((uint32) ((uint32) 0x01u << CAN_1_RX_WPNL_SHIFT))
/* Bits 19-16 within RX_CMD[i] */
#define CAN_1_RX_DLC_VALUE_SHIFT (16u)
#define CAN_1_RX_DLC_VALUE_MASK ((uint32) ((uint32) 0x0Fu << CAN_1_RX_DLC_VALUE_SHIFT))
/* Bit 20 within RX_CMD[i] */
#define CAN_1_RX_IDE_SHIFT (20u)
#define CAN_1_RX_IDE_MASK ((uint32) ((uint32) 0x01u << CAN_1_RX_IDE_SHIFT))
/* Bit 23 within RX_CMD[i] */
#define CAN_1_RX_WPNH_SHIFT (23u)
#define CAN_1_RX_WPNH_MASK ((uint32) ((uint32) 0x01u << CAN_1_RX_WPNH_SHIFT))
#define CAN_1_RX_ACK_MESSAGE(i) (CAN_1_RX_CMD_REG(i) |= CAN_1_RX_ACK_MSG)
#define CAN_1_RX_RTR_ABORT_MESSAGE(i) (CAN_1_RX_CMD_REG(i) |= \
CAN_1_RX_RTR_ABORT_MASK)
#define CAN_1_RX_BUF_ENABLE(i) (CAN_1_RX_CMD_REG(i) |= \
CAN_1_RX_BUF_ENABLE_MASK)
#define CAN_1_RX_BUF_DISABLE(i) (CAN_1_RX_CMD_REG(i) &= \
(uint32) (~CAN_1_RX_BUF_ENABLE_MASK))
#define CAN_1_SET_RX_RTRREPLY(i) (CAN_1_RX_CMD_REG(i) |= \
CAN_1_RX_RTRREPLY_MASK)
#define CAN_1_CLEAR_RX_RTRREPLY(i) (CAN_1_RX_CMD_REG(i) &= \
(uint32) (~CAN_1_RX_RTRREPLY_MASK))
#define CAN_1_RX_INT_ENABLE(i) (CAN_1_RX_CMD_REG(i) |= \
CAN_1_RX_INT_ENABLE_MASK)
#define CAN_1_RX_INT_DISABLE(i) (CAN_1_RX_CMD_REG(i) &= \
(uint32) (~CAN_1_RX_INT_ENABLE_MASK))
#define CAN_1_SET_RX_LINKING(i) (CAN_1_RX_CMD_REG(i) |= CAN_1_RX_LINKING_MASK)
#define CAN_1_CLEAR_RX_LINKING(i) (CAN_1_RX_CMD_REG(i) &= \
(uint32) (~CAN_1_RX_LINKING_MASK))
#define CAN_1_SET_RX_WNPL(i) (CAN_1_RX_CMD_REG(i) |= CAN_1_RX_WPNL_MASK)
#define CAN_1_CLEAR_RX_WNPL(i) (CAN_1_RX_CMD_REG(i) &= \
(uint32) (~CAN_1_RX_WPNL_MASK))
#define CAN_1_SET_RX_WNPH(i) (CAN_1_RX_CMD_REG(i) |= CAN_1_RX_WPNH_MASK)
#define CAN_1_CLEAR_RX_WNPH(i) (CAN_1_RX_CMD_REG(i) &= \
(uint32) (~CAN_1_RX_WPNH_MASK))
#define CAN_1_GET_DLC(i) ((uint32) ((CAN_1_RX_CMD_REG(i) & \
CAN_1_RX_DLC_VALUE_MASK) >> CAN_1_RX_DLC_VALUE_SHIFT))
#define CAN_1_GET_RX_IDE(i) ((uint32) ((CAN_1_RX_CMD_REG(i) & \
CAN_1_RX_IDE_MASK) >> CAN_1_RX_IDE_SHIFT))
#define CAN_1_GET_RX_ID(i) ((CAN_1_GET_RX_IDE(i) == 0u) ? \
(CAN_1_RX_ID_REG(i) >> CAN_1_SET_TX_ID_STANDARD_MSG_SHIFT) : \
(CAN_1_RX_ID_REG(i) >> CAN_1_SET_TX_ID_EXTENDED_MSG_SHIFT))
/* Set/Clear bits macro for CAN_1_TX mailbox(i) */
/* Bit 0 within TX_CMD[i] */
#define CAN_1_TX_TRANSMIT_REQUEST_SHIFT (0u)
#define CAN_1_TX_TRANSMIT_REQUEST \
((uint32) ((uint32) 0x01u << CAN_1_TX_TRANSMIT_REQUEST_SHIFT))
/* Bit 1 within TX_CMD[i] */
#define CAN_1_TX_ABORT_SHIFT (1u)
#define CAN_1_TX_ABORT_MASK ((uint32) ((uint32) 0x01u << CAN_1_TX_ABORT_SHIFT))
/* Bit 2 within TX_CMD[i] */
#define CAN_1_TRANSMIT_INT_ENABLE (0x01u)
#define CAN_1_TRANSMIT_INT_DISABLE (0x00u)
#define CAN_1_TX_INT_ENABLE_SHIFT (2u)
#define CAN_1_TX_INT_ENABLE_MASK \
((uint32) ((uint32) 0x00000001u << CAN_1_TX_INT_ENABLE_SHIFT))
/* Bit 3 within TX_CMD[i] */
#define CAN_1_TX_WPNL_SHIFT (3u)
#define CAN_1_TX_WPNL_MASK ((uint32) ((uint32) 0x01u << CAN_1_TX_WPNL_SHIFT))
/* Bits 19-16 within TX_CMD[i] */
#define CAN_1_TX_DLC_VALUE_SHIFT (0u)
#define CAN_1_TX_DLC_UPPER_VALUE_SHIFT (19u)
#define CAN_1_TX_DLC_UPPER_VALUE \
((uint32) ((uint32) 0x00000001u << CAN_1_TX_DLC_UPPER_VALUE_SHIFT))
#define CAN_1_TX_DLC_VALUE_MASK ((uint32) ((uint32) 0x0Fu << CAN_1_TX_DLC_VALUE_SHIFT))
#define CAN_1_TX_DLC_MAX_VALUE (8u)
/* Bit 20 within TX_CMD[i] */
#define CAN_1_TX_IDE_SHIFT (20u)
#define CAN_1_TX_IDE_MASK ((uint32) ((uint32) 0x00000001u << CAN_1_TX_IDE_SHIFT))
/* Bit 21 within TX_CMD[i] */
#define CAN_1_TX_RTR_SHIFT (21u)
#define CAN_1_TX_RTR_MASK ((uint32) ((uint32) 0x00000001u << CAN_1_TX_RTR_SHIFT))
/* Bit 23 within TX_CMD[i] */
#define CAN_1_TX_WPNH_SHIFT (23u)
#define CAN_1_TX_WPNH_MASK ((uint32) ((uint32) 0x01u << CAN_1_TX_WPNH_SHIFT))
#define CAN_1_TX_TRANSMIT_MESSAGE(i) \
(CAN_1_TX_CMD_REG(i) |= CAN_1_TX_TRANSMIT_REQUEST)
#define CAN_1_TX_ABORT_MESSAGE(i) (CAN_1_TX_CMD_REG(i) = (CAN_1_TX_CMD_REG(i) & \
(uint32) (~CAN_1_TX_TRANSMIT_REQUEST)) | CAN_1_TX_ABORT_MASK)
#define CAN_1_TX_INT_ENABLE(i) (CAN_1_TX_CMD_REG(i) |= CAN_1_TX_INT_ENABLE_MASK)
#define CAN_1_TX_INT_DISABLE(i) (CAN_1_TX_CMD_REG(i) &= \
(uint32) (~CAN_1_TX_INT_ENABLE_MASK))
#define CAN_1_SET_TX_WNPL(i) (CAN_1_TX_CMD_REG(i) |= CAN_1_TX_WPNL_MASK)
#define CAN_1_CLEAR_TX_WNPL(i) \
(CAN_1_TX_CMD_REG(i) &= (uint32)(~CAN_1_TX_WPNL_MASK))
#define CAN_1_SET_TX_IDE(i) (CAN_1_TX_CMD_REG(i) |= CAN_1_TX_IDE_MASK)
#define CAN_1_CLEAR_TX_IDE(i) \
(CAN_1_TX_CMD_REG(i) &= (uint32) (~CAN_1_TX_IDE_MASK))
#define CAN_1_SET_TX_RTR(i) (CAN_1_TX_CMD_REG(i) |= CAN_1_TX_RTR_MASK)
#define CAN_1_CLEAR_TX_RTR(i) \
(CAN_1_TX_CMD_REG(i) &= (uint32) (~CAN_1_TX_RTR_MASK))
#define CAN_1_SET_TX_WNPH(i) (CAN_1_TX_CMD_REG(i) |= CAN_1_TX_WPNH_MASK)
#define CAN_1_CLEAR_TX_WNPH(i) \
(CAN_1_TX_CMD_REG(i) &= (uint32)(~CAN_1_TX_WPNH_MASK))
#define CAN_1_DATA_HIGH_ADDR (4u)
#define CAN_1_DATA_BYTE_MASK ((uint32) 0xFFu)
#define CAN_1_RX_DATA_BYTE(mailbox, i) (((i) > 3u) ? \
(uint8) (CAN_1_RX_DATA_HI_REG(mailbox) >> ((7u - (i)) * CAN_1_ONE_BYTE_OFFSET)) : \
(uint8) (CAN_1_RX_DATA_LO_REG(mailbox) >> ((3u - (i)) * CAN_1_ONE_BYTE_OFFSET)))
#define CAN_1_TX_DATA_BYTE(mailbox, i, byte) (((i) > 3u) ? \
(CAN_1_TX_DATA_HI_REG(mailbox) = (CAN_1_TX_DATA_HI_REG(mailbox) & \
(uint32) (~((uint32) (CAN_1_DATA_BYTE_MASK << ((7u - (i)) * CAN_1_ONE_BYTE_OFFSET))))) | \
(uint32) ((uint32) (byte) << ((7u - (i)) * CAN_1_ONE_BYTE_OFFSET))) : \
(CAN_1_TX_DATA_LO_REG(mailbox) = (CAN_1_TX_DATA_LO_REG(mailbox) & \
(uint32) (~((uint32) (CAN_1_DATA_BYTE_MASK << ((3u - (i)) * CAN_1_ONE_BYTE_OFFSET))))) | \
(uint32) ((uint32) (byte) << ((3u - (i)) * CAN_1_ONE_BYTE_OFFSET))))
#endif /* CY_PSOC3 || CY_PSOC5 */
#if (CY_PSOC3 || CY_PSOC5)
#define CAN_1_DATA_BYTE_1 (3u)
#define CAN_1_DATA_BYTE_2 (2u)
#define CAN_1_DATA_BYTE_3 (1u)
#define CAN_1_DATA_BYTE_4 (0u)
#define CAN_1_DATA_BYTE_5 (7u)
#define CAN_1_DATA_BYTE_6 (6u)
#define CAN_1_DATA_BYTE_7 (5u)
#define CAN_1_DATA_BYTE_8 (4u)
/* Macros for access to RX DATA for mailbox(i) */
#define CAN_1_RX_DATA_BYTE1(i) CAN_1_RX[i].rxdata.byte[CAN_1_DATA_BYTE_1]
#define CAN_1_RX_DATA_BYTE2(i) CAN_1_RX[i].rxdata.byte[CAN_1_DATA_BYTE_2]
#define CAN_1_RX_DATA_BYTE3(i) CAN_1_RX[i].rxdata.byte[CAN_1_DATA_BYTE_3]
#define CAN_1_RX_DATA_BYTE4(i) CAN_1_RX[i].rxdata.byte[CAN_1_DATA_BYTE_4]
#define CAN_1_RX_DATA_BYTE5(i) CAN_1_RX[i].rxdata.byte[CAN_1_DATA_BYTE_5]
#define CAN_1_RX_DATA_BYTE6(i) CAN_1_RX[i].rxdata.byte[CAN_1_DATA_BYTE_6]
#define CAN_1_RX_DATA_BYTE7(i) CAN_1_RX[i].rxdata.byte[CAN_1_DATA_BYTE_7]
#define CAN_1_RX_DATA_BYTE8(i) CAN_1_RX[i].rxdata.byte[CAN_1_DATA_BYTE_8]
/* Macros for access to TX DATA for mailbox(i) */
#define CAN_1_TX_DATA_BYTE1(i) CAN_1_TX[i].txdata.byte[CAN_1_DATA_BYTE_1]
#define CAN_1_TX_DATA_BYTE2(i) CAN_1_TX[i].txdata.byte[CAN_1_DATA_BYTE_2]
#define CAN_1_TX_DATA_BYTE3(i) CAN_1_TX[i].txdata.byte[CAN_1_DATA_BYTE_3]
#define CAN_1_TX_DATA_BYTE4(i) CAN_1_TX[i].txdata.byte[CAN_1_DATA_BYTE_4]
#define CAN_1_TX_DATA_BYTE5(i) CAN_1_TX[i].txdata.byte[CAN_1_DATA_BYTE_5]
#define CAN_1_TX_DATA_BYTE6(i) CAN_1_TX[i].txdata.byte[CAN_1_DATA_BYTE_6]
#define CAN_1_TX_DATA_BYTE7(i) CAN_1_TX[i].txdata.byte[CAN_1_DATA_BYTE_7]
#define CAN_1_TX_DATA_BYTE8(i) CAN_1_TX[i].txdata.byte[CAN_1_DATA_BYTE_8]
#else /* CY_PSOC4 */
/* Macros for access to RX DATA for mailbox(i) */
#define CAN_1_RX_DATA_BYTE1(i) \
((uint8) (CAN_1_RX_DATA_LO_REG(i) >> CAN_1_THREE_BYTE_OFFSET))
#define CAN_1_RX_DATA_BYTE2(i) \
((uint8) (CAN_1_RX_DATA_LO_REG(i) >> CAN_1_TWO_BYTE_OFFSET))
#define CAN_1_RX_DATA_BYTE3(i) \
((uint8) (CAN_1_RX_DATA_LO_REG(i) >> CAN_1_ONE_BYTE_OFFSET))
#define CAN_1_RX_DATA_BYTE4(i) ((uint8) CAN_1_RX_DATA_LO_REG(i))
#define CAN_1_RX_DATA_BYTE5(i) \
((uint8) (CAN_1_RX_DATA_HI_REG(i) >> CAN_1_THREE_BYTE_OFFSET))
#define CAN_1_RX_DATA_BYTE6(i) \
((uint8) (CAN_1_RX_DATA_HI_REG(i) >> CAN_1_TWO_BYTE_OFFSET))
#define CAN_1_RX_DATA_BYTE7(i) \
((uint8) (CAN_1_RX_DATA_HI_REG(i) >> CAN_1_ONE_BYTE_OFFSET))
#define CAN_1_RX_DATA_BYTE8(i) ((uint8) CAN_1_RX_DATA_HI_REG(i))
/* Macros for access to TX DATA for mailbox(i) */
#define CAN_1_TX_DATA_BYTE1(i, byte) \
(CAN_1_TX_DATA_LO_REG(i) = (CAN_1_TX_DATA_LO_REG(i) & \
(uint32) (~((uint32) (CAN_1_DATA_BYTE_MASK << CAN_1_THREE_BYTE_OFFSET)))) | \
(uint32) ((uint32) (byte) << CAN_1_THREE_BYTE_OFFSET))
#define CAN_1_TX_DATA_BYTE2(i, byte) \
(CAN_1_TX_DATA_LO_REG(i) = (CAN_1_TX_DATA_LO_REG(i) & \
(uint32) (~((uint32) (CAN_1_DATA_BYTE_MASK << CAN_1_TWO_BYTE_OFFSET)))) | \
(uint32) ((uint32) (byte) << CAN_1_TWO_BYTE_OFFSET))
#define CAN_1_TX_DATA_BYTE3(i, byte) \
(CAN_1_TX_DATA_LO_REG(i) = (CAN_1_TX_DATA_LO_REG(i) & \
(uint32) (~((uint32) (CAN_1_DATA_BYTE_MASK << CAN_1_ONE_BYTE_OFFSET)))) | \
(uint32) ((uint32) (byte) << CAN_1_ONE_BYTE_OFFSET))
#define CAN_1_TX_DATA_BYTE4(i, byte) \
(CAN_1_TX_DATA_LO_REG(i) = (CAN_1_TX_DATA_LO_REG(i) & \
(uint32) (~CAN_1_DATA_BYTE_MASK)) | (uint32) (byte))
#define CAN_1_TX_DATA_BYTE5(i, byte) \
(CAN_1_TX_DATA_HI_REG(i) = (CAN_1_TX_DATA_HI_REG(i) & \
(uint32) (~((uint32) (CAN_1_DATA_BYTE_MASK << CAN_1_THREE_BYTE_OFFSET)))) | \
(uint32) ((uint32) (byte) << CAN_1_THREE_BYTE_OFFSET))
#define CAN_1_TX_DATA_BYTE6(i, byte) \
(CAN_1_TX_DATA_HI_REG(i) = (CAN_1_TX_DATA_HI_REG(i) & \
(uint32) (~((uint32) (CAN_1_DATA_BYTE_MASK << CAN_1_TWO_BYTE_OFFSET)))) | \
(uint32) ((uint32) (byte) << CAN_1_TWO_BYTE_OFFSET))
#define CAN_1_TX_DATA_BYTE7(i, byte) \
(CAN_1_TX_DATA_HI_REG(i) = (CAN_1_TX_DATA_HI_REG(i) & \
(uint32) (~((uint32) (CAN_1_DATA_BYTE_MASK << CAN_1_ONE_BYTE_OFFSET)))) | \
(uint32) ((uint32) (byte) << CAN_1_ONE_BYTE_OFFSET))
#define CAN_1_TX_DATA_BYTE8(i, byte) \
(CAN_1_TX_DATA_HI_REG(i) = (CAN_1_TX_DATA_HI_REG(i) & \
(uint32) (~CAN_1_DATA_BYTE_MASK)) | (uint32) (byte))
#endif /* CY_PSOC3 || CY_PSOC5 */
/* Macros for setting Tx Msg Identifier in CAN_1_TX_ID register */
#define CAN_1_SET_TX_ID_STANDARD_MSG_SHIFT (21u)
#define CAN_1_SET_TX_ID_EXTENDED_MSG_SHIFT (3u)
#define CAN_1_SET_TX_ID_STANDARD_MSG(i, id) (CY_SET_REG32(CAN_1_TX_ID_PTR(i), \
(uint32) ((uint32) (id) << CAN_1_SET_TX_ID_STANDARD_MSG_SHIFT)))
#define CAN_1_SET_TX_ID_EXTENDED_MSG(i, id) (CY_SET_REG32(CAN_1_TX_ID_PTR(i), \
(uint32) ((uint32) (id) << CAN_1_SET_TX_ID_EXTENDED_MSG_SHIFT)))
/* Mask for bits within CAN_1_CSR_CFG */
#define CAN_1_EDGE_MODE_SHIFT (0u)
/* Bit 0 within CSR_CFG */
#define CAN_1_EDGE_MODE_MASK ((uint8) ((uint8) 0x01u << CAN_1_EDGE_MODE_SHIFT))
#define CAN_1_SAMPLE_MODE_SHIFT (1u)
/* Bit 1 within CSR_CFG */
#define CAN_1_SAMPLE_MODE_MASK ((uint8) ((uint8) 0x01u << CAN_1_SAMPLE_MODE_SHIFT))
#define CAN_1_CFG_REG_SJW_SHIFT (2u)
/* Bits 3-2 within CSR_CFG */
#define CAN_1_CFG_REG_SJW_MASK ((uint8) ((uint8) 0x03u << CAN_1_CFG_REG_SJW_SHIFT))
#define CAN_1_CFG_REG_SJW_LOWER_LIMIT (0x03u) /* the lowest allowed value of cfg_sjw */
#define CAN_1_RESET_SHIFT (4u)
/* Bit 4 within CSR_CFG */
#define CAN_1_RESET_MASK ((uint8) ((uint8) 0x01u << CAN_1_RESET_SHIFT))
#define CAN_1_CFG_REG_TSEG2_SHIFT (5u)
/* Bits 7-5 within CSR_CFG */
#define CAN_1_CFG_REG_TSEG2_MASK ((uint8) ((uint8) 0x07u << CAN_1_CFG_REG_TSEG2_SHIFT))
/* Highest allowed value of cfg_tseg2 */
#define CAN_1_CFG_REG_TSEG2_UPPER_LIMIT (0x07u)
/* Lowest allowed value of cfg_tseg2 */
#define CAN_1_CFG_REG_TSEG2_LOWER_LIMIT (0x02u)
/* Lowest allowed value of cfg_tseg2 if sample point is one point */
#define CAN_1_CFG_REG_TSEG2_EXCEPTION (0x01u)
/* Bits 11-8 within CSR_CFG */
#define CAN_1_CFG_REG_TSEG1_SHIFT (8u)
#define CAN_1_CFG_REG_TSEG1_MASK (0x0Fu)
/* Highest allowed value of cfg_tseg1 */
#define CAN_1_CFG_REG_TSEG1_UPPER_LIMIT (0x0Fu)
/* Lowest allowed value of cfg_tseg1 */
#define CAN_1_CFG_REG_TSEG1_LOWER_LIMIT (0x02u)
#define CAN_1_ARBITER_SHIFT (12u)
#if (CY_PSOC3 || CY_PSOC5)
#define CAN_1_ARBITRATION_SHIFT (4u)
/* Bit 12 within CSR_CFG */
#define CAN_1_ARBITRATION_MASK ((uint8) ((uint8) 0x01u << CAN_1_ARBITRATION_SHIFT))
#else /* CY_PSOC4 */
#define CAN_1_ARBITRATION_SHIFT (12u)
/* Bit 12 within CSR_CFG */
#define CAN_1_ARBITRATION_MASK ((uint32) ((uint32) 0x01u << CAN_1_ARBITRATION_SHIFT))
/* Bit 13 within CSR_CFG */
#define CAN_1_ENDIANNESS_SHIFT (13u)
#define CAN_1_ENDIANNESS_MASK ((uint32) ((uint32) 0x01u << CAN_1_ENDIANNESS_SHIFT))
/* Bit 14 within CSR_CFG */
#define CAN_1_ECR_MODE_SHIFT (14u)
#define CAN_1_ECR_MODE_MASK ((uint32) ((uint32) 0x01u << CAN_1_ECR_MODE_SHIFT))
#endif /* (CY_PSOC3 || CY_PSOC5) */
/* Bits 23-16 within CSR_CFG */
#define CAN_1_BITRATE_SHIFT (16u)
#define CAN_1_BITRATE_MASK (0x7FFFu)
#define CAN_1_BITRATE_MASK_SHIFTED \
((uint32) ((uint32) CAN_1_BITRATE_MASK << CAN_1_BITRATE_SHIFT))
/* Mask for bits within CAN_1_CSR_CMD */
#define CAN_1_MODE_SHIFT (0u)
/* Bit 0 within CSR_CMD */
#define CAN_1_MODE_MASK ((uint8) ((uint8) 0x01u << CAN_1_MODE_SHIFT))
#define CAN_1_OPMODE_MASK_SHIFT (1u)
/* Bit 1 within CSR_CMD */
#define CAN_1_OPMODE_MASK ((uint8) ((uint8) 0x01u << CAN_1_OPMODE_MASK_SHIFT))
#if (CY_PSOC3 || CY_PSOC5)
#define CAN_1_OPMODE_FIELD_MASK ((uint8) ((uint8) 0x03u << CAN_1_MODE_SHIFT))
#else /* CY_PSOC4 */
#define CAN_1_OPMODE_FIELD_MASK ((uint8) ((uint8) 0x07u << CAN_1_MODE_SHIFT))
#endif /* (CY_PSOC3 || CY_PSOC5) */
/* Mask for bits within CAN_1_CSR_CMD */
#define CAN_1_ERROR_STATE_SHIFT (0u)
/* Bit 17-16 within ERR_SR */
#define CAN_1_ERROR_STATE_MASK ((uint8) ((uint8) 0x03u << CAN_1_ERROR_STATE_SHIFT))
#if (CY_PSOC3 || CY_PSOC5)
#define CAN_1_TX_ERROR_FLAG_SHIFT (2u)
/* Bit 18 within ERR_SR */
#define CAN_1_TX_ERROR_FLAG_MASK ((uint8) ((uint8) 0x01u << CAN_1_TX_ERROR_FLAG_SHIFT))
#define CAN_1_RX_ERROR_FLAG_SHIFT (3u)
/* Bit 19 within ERR_SR */
#define CAN_1_RX_ERROR_FLAG_MASK ((uint8) ((uint8) 0x01u << CAN_1_RX_ERROR_FLAG_SHIFT))
#else /* CY_PSOC4 */
#define CAN_1_TX_ERROR_FLAG_SHIFT (18u)
/* Bit 18 within ERR_SR */
#define CAN_1_TX_ERROR_FLAG_MASK ((uint32) ((uint32) 0x01u << CAN_1_TX_ERROR_FLAG_SHIFT))
#define CAN_1_RX_ERROR_FLAG_SHIFT (19u)
/* Bit 19 within ERR_SR */
#define CAN_1_RX_ERROR_FLAG_MASK ((uint32) ((uint32) 0x01u << CAN_1_RX_ERROR_FLAG_SHIFT))
/* Mask and Macros for bits within CAN_1_ECR_REG */
#define CAN_1_ECR_STATUS_ARM (0x01u)
/* Mask for clearing CAN_1INT_STATUS */
#define CAN_1_INT_STATUS_MASK (0x00001FFCu)
#endif /* (CY_PSOC3 || CY_PSOC5) */
/* Mask and Macros for bits within CAN_1_INT_EN_REG */
#define CAN_1_GLOBAL_INT_SHIFT (0u)
#define CAN_1_ARBITRATION_LOST_SHIFT (2u)
#define CAN_1_OVERLOAD_ERROR_SHIFT (3u)
#define CAN_1_BIT_ERROR_SHIFT (4u)
#define CAN_1_STUFF_ERROR_SHIFT (5u)
#define CAN_1_ACK_ERROR_SHIFT (6u)
#define CAN_1_FORM_ERROR_SHIFT (7u)
#if (CY_PSOC3 || CY_PSOC5)
#define CAN_1_CRC_ERROR_SHIFT (0u)
#define CAN_1_BUS_OFF_SHIFT (1u)
#define CAN_1_RX_MSG_LOST_SHIFT (2u)
#define CAN_1_TX_MESSAGE_SHIFT (3u)
#define CAN_1_RX_MESSAGE_SHIFT (4u)
/* Bit 0 within INT_EN */
#define CAN_1_GLOBAL_INT_MASK ((uint8) ((uint8) 0x01u << CAN_1_GLOBAL_INT_SHIFT))
/* Bit 2 within INT_EN and INT_SR */
#define CAN_1_ARBITRATION_LOST_MASK ((uint8) ((uint8) 0x01u << CAN_1_ARBITRATION_LOST_SHIFT))
/* Bit 3 within INT_EN and INT_SR */
#define CAN_1_OVERLOAD_ERROR_MASK ((uint8) ((uint8) 0x01u << CAN_1_OVERLOAD_ERROR_SHIFT))
/* Bit 4 within INT_EN and INT_SR */
#define CAN_1_BIT_ERROR_MASK ((uint8) ((uint8) 0x01u << CAN_1_BIT_ERROR_SHIFT))
/* Bit 5 within INT_EN and INT_SR */
#define CAN_1_STUFF_ERROR_MASK ((uint8) ((uint8) 0x01u << CAN_1_STUFF_ERROR_SHIFT))
/* Bit 6 within INT_EN and INT_SR */
#define CAN_1_ACK_ERROR_MASK ((uint8) ((uint8) 0x01u << CAN_1_ACK_ERROR_SHIFT))
/* Bit 7 within INT_EN and INT_SR */
#define CAN_1_FORM_ERROR_MASK ((uint8) ((uint8) 0x01u << CAN_1_FORM_ERROR_SHIFT))
/* Bit 8 within INT_EN and INT_SR */
#define CAN_1_CRC_ERROR_MASK ((uint8) ((uint8) 0x01u << CAN_1_CRC_ERROR_SHIFT))
/* Bit 9 within INT_EN and INT_SR */
#define CAN_1_BUS_OFF_MASK ((uint8) ((uint8) 0x01u << CAN_1_BUS_OFF_SHIFT))
/* Bit 10 within INT_EN and INT_SR */
#define CAN_1_RX_MSG_LOST_MASK ((uint8) ((uint8) 0x01u << CAN_1_RX_MSG_LOST_SHIFT))
/* Bit 11 within INT_EN and INT_SR */
#define CAN_1_TX_MESSAGE_MASK ((uint8) ((uint8) 0x01u << CAN_1_TX_MESSAGE_SHIFT))
/* Bit 12 within INT_EN and INT_SR */
#define CAN_1_RX_MESSAGE_MASK ((uint8) ((uint8) 0x01u << CAN_1_RX_MESSAGE_SHIFT))
#define CAN_1_ARBITRATION_LOST_INT_ENABLE \
(CAN_1_INT_EN_REG.byte[0u] |= CAN_1_ARBITRATION_LOST_MASK)
#define CAN_1_ARBITRATION_LOST_INT_DISABLE \
(CAN_1_INT_EN_REG.byte[0u] &= (uint8) (~CAN_1_ARBITRATION_LOST_MASK))
#define CAN_1_OVERLOAD_ERROR_INT_ENABLE \
(CAN_1_INT_EN_REG.byte[0u] |= CAN_1_OVERLOAD_ERROR_MASK)
#define CAN_1_OVERLOAD_ERROR_INT_DISABLE \
(CAN_1_INT_EN_REG.byte[0u] &= (uint8) (~CAN_1_OVERLOAD_ERROR_MASK))
#define CAN_1_BIT_ERROR_LOST_INT_ENABLE \
(CAN_1_INT_EN_REG.byte[0u] |= CAN_1_BIT_ERROR_MASK)
#define CAN_1_BIT_ERROR_LOST_INT_DISABLE \
(CAN_1_INT_EN_REG.byte[0u] &= (uint8) (~CAN_1_BIT_ERROR_MASK))
#define CAN_1_STUFF_ERROR_INT_ENABLE \
(CAN_1_INT_EN_REG.byte[0u] |= CAN_1_STUFF_ERROR_MASK)
#define CAN_1_STUFF_ERROR_INT_DISABLE \
(CAN_1_INT_EN_REG.byte[0u] &= (uint8) (~CAN_1_STUFF_ERROR_MASK))
#define CAN_1_ACK_ERROR_INT_ENABLE \
(CAN_1_INT_EN_REG.byte[0u] |= CAN_1_ACK_ERROR_MASK)
#define CAN_1_ACK_ERROR_INT_DISABLE \
(CAN_1_INT_EN_REG.byte[0u] &= (uint8) (~CAN_1_ACK_ERROR_MASK))
#define CAN_1_FORM_ERROR_INT_ENABLE \
(CAN_1_INT_EN_REG.byte[0u] |= CAN_1_FORM_ERROR_MASK)
#define CAN_1_FORM_ERROR_INT_DISABLE \
(CAN_1_INT_EN_REG.byte[0u] &= (uint8) (~CAN_1_FORM_ERROR_MASK))
#define CAN_1_CRC_ERROR_INT_ENABLE \
(CAN_1_INT_EN_REG.byte[1u] |= CAN_1_CRC_ERROR_MASK)
#define CAN_1_CRC_ERROR_INT_DISABLE \
(CAN_1_INT_EN_REG.byte[1u] &= (uint8) (~CAN_1_CRC_ERROR_MASK))
#define CAN_1_BUS_OFF_INT_ENABLE \
(CAN_1_INT_EN_REG.byte[1u] |= CAN_1_BUS_OFF_MASK)
#define CAN_1_BUS_OFF_INT_DISABLE \
(CAN_1_INT_EN_REG.byte[1u] &= (uint8) (~CAN_1_BUS_OFF_MASK))
#define CAN_1_RX_MSG_LOST_INT_ENABLE \
(CAN_1_INT_EN_REG.byte[1u] |= CAN_1_RX_MSG_LOST_MASK)
#define CAN_1_RX_MSG_LOST_INT_DISABLE \
(CAN_1_INT_EN_REG.byte[1u] &= (uint8) (~CAN_1_RX_MSG_LOST_MASK))
#define CAN_1_TX_MSG_INT_ENABLE \
(CAN_1_INT_EN_REG.byte[1u] |= CAN_1_TX_MESSAGE_MASK)
#define CAN_1_TX_MSG_INT_DISABLE \
(CAN_1_INT_EN_REG.byte[1u] &= (uint8) (~CAN_1_TX_MESSAGE_MASK))
#define CAN_1_RX_MSG_INT_ENABLE \
(CAN_1_INT_EN_REG.byte[1u] |= CAN_1_RX_MESSAGE_MASK)
#define CAN_1_RX_MSG_INT_DISABLE \
(CAN_1_INT_EN_REG.byte[1u] &= (uint8) (~CAN_1_RX_MESSAGE_MASK))
#else /* CY_PSOC4 */
#define CAN_1_CRC_ERROR_SHIFT (8u)
#define CAN_1_BUS_OFF_SHIFT (9u)
#define CAN_1_RX_MSG_LOST_SHIFT (10u)
#define CAN_1_TX_MESSAGE_SHIFT (11u)
#define CAN_1_RX_MESSAGE_SHIFT (12u)
/* Mask and Macros for bits within CAN_1_INT_EN_REG */
/* Bit 0 within INT_EN */
#define CAN_1_GLOBAL_INT_MASK ((uint32) ((uint32) 0x01u << CAN_1_GLOBAL_INT_SHIFT))
/* Bit 2 within INT_EN and INT_SR */
#define CAN_1_ARBITRATION_LOST_MASK ((uint32) ((uint32) 0x01u << CAN_1_ARBITRATION_LOST_SHIFT))
/* Bit 3 within INT_EN and INT_SR */
#define CAN_1_OVERLOAD_ERROR_MASK ((uint32) ((uint32) 0x01u << CAN_1_OVERLOAD_ERROR_SHIFT))
/* Bit 4 within INT_EN and INT_SR */
#define CAN_1_BIT_ERROR_MASK ((uint32) ((uint32) 0x01u << CAN_1_BIT_ERROR_SHIFT))
/* Bit 5 within INT_EN and INT_SR */
#define CAN_1_STUFF_ERROR_MASK ((uint32) ((uint32) 0x01u << CAN_1_STUFF_ERROR_SHIFT))
/* Bit 6 within INT_EN and INT_SR */
#define CAN_1_ACK_ERROR_MASK ((uint32) ((uint32) 0x01u << CAN_1_ACK_ERROR_SHIFT))
/* Bit 7 within INT_EN and INT_SR */
#define CAN_1_FORM_ERROR_MASK ((uint32) ((uint32) 0x01u << CAN_1_FORM_ERROR_SHIFT))
/* Bit 8 within INT_EN and INT_SR */
#define CAN_1_CRC_ERROR_MASK ((uint32) ((uint32) 0x01u << CAN_1_CRC_ERROR_SHIFT))
/* Bit 9 within INT_EN and INT_SR */
#define CAN_1_BUS_OFF_MASK ((uint32) ((uint32) 0x01u << CAN_1_BUS_OFF_SHIFT))
/* Bit 10 within INT_EN and INT_SR */
#define CAN_1_RX_MSG_LOST_MASK ((uint32) ((uint32) 0x01u << CAN_1_RX_MSG_LOST_SHIFT))
/* Bit 11 within INT_EN and INT_SR */
#define CAN_1_TX_MESSAGE_MASK ((uint32) ((uint32) 0x01u << CAN_1_TX_MESSAGE_SHIFT))
/* Bit 12 within INT_EN and INT_SR */
#define CAN_1_RX_MESSAGE_MASK ((uint32) ((uint32) 0x01u << CAN_1_RX_MESSAGE_SHIFT))
#define CAN_1_ARBITRATION_LOST_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_ARBITRATION_LOST_MASK)
#define CAN_1_ARBITRATION_LOST_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_ARBITRATION_LOST_MASK))
#define CAN_1_OVERLOAD_ERROR_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_OVERLOAD_ERROR_MASK)
#define CAN_1_OVERLOAD_ERROR_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_OVERLOAD_ERROR_MASK))
#define CAN_1_BIT_ERROR_LOST_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_BIT_ERROR_MASK)
#define CAN_1_BIT_ERROR_LOST_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_BIT_ERROR_MASK))
#define CAN_1_STUFF_ERROR_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_STUFF_ERROR_MASK)
#define CAN_1_STUFF_ERROR_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_STUFF_ERROR_MASK))
#define CAN_1_ACK_ERROR_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_ACK_ERROR_MASK)
#define CAN_1_ACK_ERROR_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_ACK_ERROR_MASK))
#define CAN_1_FORM_ERROR_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_FORM_ERROR_MASK)
#define CAN_1_FORM_ERROR_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_FORM_ERROR_MASK))
#define CAN_1_CRC_ERROR_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_CRC_ERROR_MASK)
#define CAN_1_CRC_ERROR_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_CRC_ERROR_MASK))
#define CAN_1_BUS_OFF_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_BUS_OFF_MASK)
#define CAN_1_BUS_OFF_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_BUS_OFF_MASK))
#define CAN_1_RX_MSG_LOST_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_RX_MSG_LOST_MASK)
#define CAN_1_RX_MSG_LOST_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_RX_MSG_LOST_MASK))
#define CAN_1_TX_MSG_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_TX_MESSAGE_MASK)
#define CAN_1_TX_MSG_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_TX_MESSAGE_MASK))
#define CAN_1_RX_MSG_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_RX_MESSAGE_MASK)
#define CAN_1_RX_MSG_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_RX_MESSAGE_MASK))
/* Bit 13 within INT_EN and INT_SR */
#define CAN_1_RTR_MSG_SHIFT (13u)
#define CAN_1_RTR_MSG_MASK ((uint32) ((uint32) 0x01u << CAN_1_RTR_MSG_SHIFT))
#define CAN_1_RTR_MSG_INT_ENABLE (CAN_1_INT_EN_REG |= CAN_1_RTR_MSG_MASK)
#define CAN_1_RTR_MSG_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_RTR_MSG_MASK))
/* Bit 14 within INT_EN and INT_SR */
#define CAN_1_STUCK_AT_ZERO_SHIFT (14u)
#define CAN_1_STUCK_AT_ZERO_MASK \
((uint32) ((uint32) 0x01u << CAN_1_STUCK_AT_ZERO_SHIFT))
#define CAN_1_STUCK_AT_ZERO_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_STUCK_AT_ZERO_MASK)
#define CAN_1_STUCK_AT_ZERO_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_STUCK_AT_ZERO_MASK))
/* Bit 15 within INT_EN and INT_SR */
#define CAN_1_SST_FAILURE_SHIFT (15u)
#define CAN_1_SST_FAILURE_MASK \
((uint32) ((uint32) 0x01u << CAN_1_SST_FAILURE_SHIFT))
#define CAN_1_SST_FAILURE_INT_ENABLE \
(CAN_1_INT_EN_REG |= CAN_1_SST_FAILURE_MASK)
#define CAN_1_SST_FAILURE_INT_DISABLE \
(CAN_1_INT_EN_REG &= (uint32) (~CAN_1_SST_FAILURE_MASK))
#endif /* CY_PSOC3 || CY_PSOC5 */
#define CAN_1_GLOBAL_INT_ENABLE_SHIFT (0u)
#define CAN_1_ARBITRATION_LOST_ENABLE_SHIFT (2u)
#define CAN_1_OVERLOAD_ERROR_ENABLE_SHIFT (3u)
#define CAN_1_BIT_ERROR_ENABLE_SHIFT (4u)
#define CAN_1_STUFF_ERROR_ENABLE_SHIFT (5u)
#define CAN_1_ACK_ERROR_ENABLE_SHIFT (6u)
#define CAN_1_FORM_ERROR_ENABLE_SHIFT (7u)
#define CAN_1_CRC_ERROR_ENABLE_SHIFT (8u)
#define CAN_1_BUS_OFF_ENABLE_SHIFT (9u)
#define CAN_1_RX_MSG_LOST_ENABLE_SHIFT (10u)
#define CAN_1_TX_MESSAGE_ENABLE_SHIFT (11u)
#define CAN_1_RX_MESSAGE_ENABLE_SHIFT (12u)
#define CAN_1_GLOBAL_INT_ENABLE ((uint16) ((uint16) 0x01u << CAN_1_GLOBAL_INT_ENABLE_SHIFT))
#define CAN_1_ARBITRATION_LOST_ENABLE \
((uint16) ((uint16) 0x01u << CAN_1_ARBITRATION_LOST_ENABLE_SHIFT))
#define CAN_1_OVERLOAD_ERROR_ENABLE \
((uint16) ((uint16) 0x01u << CAN_1_OVERLOAD_ERROR_ENABLE_SHIFT))
#define CAN_1_BIT_ERROR_ENABLE ((uint16) ((uint16) 0x01u << CAN_1_BIT_ERROR_ENABLE_SHIFT))
#define CAN_1_STUFF_ERROR_ENABLE ((uint16) ((uint16) 0x01u << CAN_1_STUFF_ERROR_ENABLE_SHIFT))
#define CAN_1_ACK_ERROR_ENABLE ((uint16) ((uint16) 0x01u << CAN_1_ACK_ERROR_ENABLE_SHIFT))
#define CAN_1_FORM_ERROR_ENABLE ((uint16) ((uint16) 0x01u << CAN_1_FORM_ERROR_ENABLE_SHIFT))
#define CAN_1_CRC_ERROR_ENABLE ((uint16) ((uint16) 0x01u << CAN_1_CRC_ERROR_ENABLE_SHIFT))
#define CAN_1_BUS_OFF_ENABLE ((uint16) ((uint16) 0x01u << CAN_1_BUS_OFF_ENABLE_SHIFT))
#define CAN_1_RX_MSG_LOST_ENABLE ((uint16) ((uint16) 0x01u << CAN_1_RX_MSG_LOST_ENABLE_SHIFT))
#define CAN_1_TX_MESSAGE_ENABLE ((uint16) ((uint16) 0x01u << CAN_1_TX_MESSAGE_ENABLE_SHIFT))
#define CAN_1_RX_MESSAGE_ENABLE ((uint16) ((uint16) 0x01u << CAN_1_RX_MESSAGE_ENABLE_SHIFT))
#if (!(CY_PSOC3 || CY_PSOC5))
#define CAN_1_RTR_MESSAGE_ENABLE_SHIFT (13u)
#define CAN_1_STUCK_AT_ZERO_ENABLE_SHIFT (14u)
#define CAN_1_SST_FAILURE_ENABLE_SHIFT (15u)
#define CAN_1_RTR_MESSAGE_ENABLE \
((uint16) ((uint16) 0x01u << CAN_1_RTR_MESSAGE_ENABLE_SHIFT))
#define CAN_1_STUCK_AT_ZERO_ENABLE \
((uint16) ((uint16) 0x01u << CAN_1_STUCK_AT_ZERO_ENABLE_SHIFT))
#define CAN_1_SST_FAILURE_ENABLE \
((uint16) ((uint16) 0x01u << CAN_1_SST_FAILURE_ENABLE_SHIFT))
#endif /* (!(CY_PSOC3 || CY_PSOC5)) */
#define CAN_1_REG_ADDR_MASK ((uint32) 0x0000FFFFu)
/***************************************
* The following code is DEPRECATED and
* should not be used in new projects.
***************************************/
#define CAN_1_TREE_BYTE_OFFSET (CAN_1_THREE_BYTE_OFFSET)
/* CAN_1_SetRestartType() parameters */
#define CAN_1_RESTART_BY_HAND (CAN_1_MANUAL_RESTART)
/* CAN_1_SetOpMode() parameters */
#define CAN_1_LISTEN_ONLY (CAN_1_LISTEN_ONLY_MODE)
#define CAN_1_ACTIVE_MODE (CAN_1_INITIAL_MODE)
#ifdef CAN_1_ISR_CALLBACK
#define CAN_1_ISR_INTERRUPT_CALLBACK
#define CAN_1_ISR_InterruptCallback CAN_1_Isr_Callback
#endif
#endif /* CY_CAN_CAN_1_H */
/* [] END OF FILE */
| 48.196575 | 103 | 0.64493 |
2ff076180e18184aa080517f1ebcf3edd5d7d11c | 3,206 | h | C | src/vk_main/vk_main.h | aeroc7/LearningVulkan | 168435dc97191b89eda9b44ea2e01ccc89455d3b | [
"MIT"
] | null | null | null | src/vk_main/vk_main.h | aeroc7/LearningVulkan | 168435dc97191b89eda9b44ea2e01ccc89455d3b | [
"MIT"
] | null | null | null | src/vk_main/vk_main.h | aeroc7/LearningVulkan | 168435dc97191b89eda9b44ea2e01ccc89455d3b | [
"MIT"
] | null | null | null | #ifndef __VK_MAIN_H__
#define __VK_MAIN_H__
#include <glfw_window.h>
#include <vulkan/vulkan.h>
#include <string>
#include <tuple>
#include <vector>
#include <optional>
namespace vulkan_impl {
inline std::string
retrieve_version_string(uint32_t version) {
auto version_maj = VK_VERSION_MAJOR(version);
auto version_min = VK_VERSION_MINOR(version);
auto version_pat = VK_VERSION_PATCH(version);
std::string version_str =
std::to_string(version_maj) + '.' +
std::to_string(version_min) + '.' +
std::to_string(version_pat);
return version_str;
}
struct VulkanMainConfig {
uint16_t window_width = 1280;
uint16_t window_height = 720;
std::string window_title = "Vulkan Window";
std::string vulkan_app_name = "Vulkan Application";
uint32_t vulkan_app_version = VK_MAKE_VERSION(1, 0, 0);
std::string vulkan_engine_name = "Vulkan Engine";
uint32_t vulkan_engine_version = VK_MAKE_VERSION(1, 0, 0);
uint32_t vulkan_api_version = VK_API_VERSION_1_2;
std::vector<const char*>
validation_layers = { "VK_LAYER_KHRONOS_validation" };
bool enable_validation_layer = true;
};
// Quick reference:
/*
* KHR suffix: Command comes from an extension
*
* VkInstance - Vulkan instance/context
* VkPhysicalDevice - Physical device, like a GPU
* VkDevice - Vulkan's logical device, where things are executed
* VkBuffer - Chunk of GPU visible memory
* VkImage - A texture that you can read/write
* VkPipeline - Holds the state of the GPU (shaders, etc.)
* VkRenderPass - Holds information about images you are rendering to
* VkFrameBuffer - Holds target image (a framebuffer...)
* VkCommandBuffer - GPU commands
* VkQueue - GPU's have queues to execute different commands
* VkDescriptorSet - Basically a GPU-side pointer (connects shaders, textures)
* VkSwapchainKHR - Holds image for screen (to render to visible window)
* VkSemaphore - Synchronizes GPU to GPU execution of commands
* VkFence - Synchronizes GPU to CPU execution of commands
*/
// Main Vulkan entry (Initialization code)
class VulkanMain {
public:
VulkanMain(const VulkanMainConfig& config = {});
void init();
void fini();
private:
struct QueueFamilyData {
std::optional<uint32_t> graphics_family;
bool is_complete() {
return graphics_family.has_value();
}
};
void vulkan_instance_init();
std::vector<const char*> get_required_extensions();
bool verify_validation_layer_support();
static VKAPI_ATTR VkBool32 VKAPI_CALL debug_callback(
VkDebugUtilsMessageSeverityFlagBitsEXT messageSeverity,
VkDebugUtilsMessageTypeFlagsEXT messageType,
const VkDebugUtilsMessengerCallbackDataEXT* pCallbackData,
void* pUserData);
void init_debug_calls();
void query_physical_devices();
bool verify_device(VkPhysicalDevice device);
QueueFamilyData verify_queue_families(VkPhysicalDevice device);
VulkanMainConfig config;
VkInstance vkm_instance { VK_NULL_HANDLE };
VkDebugUtilsMessengerEXT debug_messenger { VK_NULL_HANDLE };
VkPhysicalDevice vkm_physical_device { VK_NULL_HANDLE };
VkDevice vkm_logical_device { VK_NULL_HANDLE };
GlfwWrapper window;
};
} // namespace vulkan_impl
#endif // __VK_MAIN_H__ | 31.126214 | 81 | 0.753275 |
1e368d20a911600f78e704b45f5d616043bbb632 | 335 | h | C | Core/Inc/USART.h | Mohamed-Galloul/Embedded-Final-Project---Complete-DMA-Driver | 94d72d56bba9d9d4196f1345753d3bafd30ca775 | [
"MIT"
] | null | null | null | Core/Inc/USART.h | Mohamed-Galloul/Embedded-Final-Project---Complete-DMA-Driver | 94d72d56bba9d9d4196f1345753d3bafd30ca775 | [
"MIT"
] | null | null | null | Core/Inc/USART.h | Mohamed-Galloul/Embedded-Final-Project---Complete-DMA-Driver | 94d72d56bba9d9d4196f1345753d3bafd30ca775 | [
"MIT"
] | null | null | null | /*
* USART.h
*
* Created on: Jan 1, 2022
* Author: galloul
*/
#ifndef INC_USART_H_
#define INC_USART_H_
void USART2_EnableClock(void);
void USART_Enable(void);
void Write_USART_DR(unsigned char data);
unsigned char Read_USART_DR(void);
unsigned char Read_TC_Bit(void);
void Clear_TC_Bit(void);
#endif /* INC_USART_H_ */
| 16.75 | 40 | 0.731343 |
37e55945129aa917f8e3b2262f76aecb966344cb | 24 | c | C | tests/stud/bad-main-parsing.c | MikhailTerekhov/RuC-GUI | ced72ce7ff1e3df97ab9854f073ce2d67a6b6421 | [
"Apache-2.0"
] | null | null | null | tests/stud/bad-main-parsing.c | MikhailTerekhov/RuC-GUI | ced72ce7ff1e3df97ab9854f073ce2d67a6b6421 | [
"Apache-2.0"
] | null | null | null | tests/stud/bad-main-parsing.c | MikhailTerekhov/RuC-GUI | ced72ce7ff1e3df97ab9854f073ce2d67a6b6421 | [
"Apache-2.0"
] | null | null | null | main[]]; //infinite loop | 24 | 24 | 0.666667 |
15a4ad03c27b89158682a05efa0befb3ba45427b | 3,776 | h | C | core/hash/hash_function.h | msiampou/neural-networks-for-wind-speed-prediction | 5e2297fbacd9f9b94bcfc883612ae488e54be491 | [
"MIT"
] | 7 | 2020-01-30T14:57:41.000Z | 2021-09-22T06:06:29.000Z | core/hash/hash_function.h | PanPapag/NNs-for-Wind-Speed-Prediction | 12ba4eb667ae9738f0d1effa9165507839252143 | [
"MIT"
] | null | null | null | core/hash/hash_function.h | PanPapag/NNs-for-Wind-Speed-Prediction | 12ba4eb667ae9738f0d1effa9165507839252143 | [
"MIT"
] | 1 | 2020-10-08T10:12:16.000Z | 2020-10-08T10:12:16.000Z | #ifndef HASH_FUNCTION
#define HASH_FUNCTION
#include <algorithm>
#include <cmath>
#include <chrono>
#include <iostream>
#include <iterator>
#include <random>
#include <stdlib.h>
#include <string>
#include <vector>
#include "../../core/utils/utils.h"
namespace hash {
template <typename T>
class HashFunction {
private:
std::default_random_engine generator;
std::uniform_real_distribution<double> distribution;
const uint16_t D;
const uint32_t m;
const uint32_t M;
const double w;
std::vector<double> s;
std::vector<int> a;
public:
/** \brief HashFunction class constructor
This class illustrates the following hash function:
h(x)= (a_d−1 + m*a_d−2 +···+ m^(d−1)*a_0) modM , m > max a_i
where a_i = floor((x_i - s_i) / w)
@par D - Space dimension
@par m - parameter m in the hash function
@par M - parameter M in the hash function
@par w - window size
*/
HashFunction(const uint16_t D, const uint32_t m, const uint32_t M,
const double w): D(D), m(m), M(M), w(w), distribution(0,w), s(D), a(D),
generator(std::chrono::system_clock::now().time_since_epoch().count()) {
/* Initialize s vector of dimension D using uniform_real_distribution */
for (size_t i = 0; i < D; ++i) {
s[i] = distribution(generator);
}
};
/**
\brief HashFunction class default destructor
*/
~HashFunction() = default;
/*
/** \brief Hash point as follows:
1) Compute a_i = floor((x_i - s_i) / w) for i = 0...D-1
2) Compute h(x) = (a_d−1 + m*a_d−2 +···+ m^(d−1)*a_0) modM
*/
uint32_t Hash(const std::vector<T> &points, int offset) {
uint32_t hash_value{};
/* Computing a_i */
for (size_t i = 0; i < D; ++i) {
a[i] = floor((points[offset * D + i] - s[i]) / w);
}
/* Reverse vector a */
std::reverse(a.begin(),a.end());
/* Computing h(x) */
for (size_t i = 0; i < D; ++i) {
hash_value += (utils::mod(a[i],M) * utils::mod_exp(m,i,M)) % M;
}
return hash_value % M;
};
};
template <typename T>
class AmplifiedHashFunction {
private:
std::vector<HashFunction<T>> h;
const uint8_t K;
const uint16_t D;
const uint32_t m;
const uint32_t M;
const double w;
public:
/** \brief AmplifiedHashFunction class constructor
This class illustrates g(x) = [h1(x)|h2(x)| · · · |hk (x)].
@par K - Number of Hash Functions selected uniformly
@par D - Space dimension
@par m - parameter m in the hash function
@par M - parameter M in the hash function
@par w - window size
*/
AmplifiedHashFunction(const uint8_t K, const uint16_t D, const uint32_t m,
const uint32_t M, const double w): K(K), D(D), m(m), M(M), w(w) {
/* Select uniformly K hash functions */
for (size_t i = 0; i < K; ++i) {
h.push_back(HashFunction<T>(D, m, M, w));
}
}
/**
\brief AmplifiedHashFunction class default destructor
*/
~AmplifiedHashFunction() = default;
/** Hash point as follows:
1) Hashing using h_i for i = 1..K
2) Concat h_i and modulo with table_size
*/
uint64_t Hash(const std::vector<T> &points, int offset) {
std::string str_value{};
for (size_t i = 0; i < K; ++i) {
str_value += std::to_string(h[i].Hash(points,offset));
}
// convert str_value to uint64_t
char *p_end;
uint64_t hash_value = strtoull(str_value.c_str(), &p_end, 10);
return hash_value;
}
};
}
#endif
| 30.95082 | 80 | 0.560911 |
15c8ab239fb378c2619982bd60b2197b0ddef30c | 313 | h | C | MediaPlayer/MediaPlayer/Util/Category/UIScrollView+KeyBoard.h | massacreformash/MFMediaPlayer | d95ce785f776a5a1b714af2cd1acbe4b11563e09 | [
"MIT"
] | null | null | null | MediaPlayer/MediaPlayer/Util/Category/UIScrollView+KeyBoard.h | massacreformash/MFMediaPlayer | d95ce785f776a5a1b714af2cd1acbe4b11563e09 | [
"MIT"
] | null | null | null | MediaPlayer/MediaPlayer/Util/Category/UIScrollView+KeyBoard.h | massacreformash/MFMediaPlayer | d95ce785f776a5a1b714af2cd1acbe4b11563e09 | [
"MIT"
] | null | null | null | //
// UIScrollView+KeyBoard.h
// StudentLive
//
// Created by hefanghui on 2017/10/23.
// Copyright © 2017年 hqyxedu. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface UIScrollView (KeyBoard)
@property (nonatomic, assign) CGFloat lastScrollOffsetY;
- (void)configDelegateAndKeyBoardMonitor;
@end
| 17.388889 | 56 | 0.734824 |
9bc9618dce3e8dd08bfa996f00f7cf4257a695db | 1,504 | c | C | labs/lab4/tcp_reno_verbose/tcp_reno_verbose.c | jamestiotio/networks | 8967ee34c423989ff68eec650ba6ebb492499cb4 | [
"MIT"
] | null | null | null | labs/lab4/tcp_reno_verbose/tcp_reno_verbose.c | jamestiotio/networks | 8967ee34c423989ff68eec650ba6ebb492499cb4 | [
"MIT"
] | null | null | null | labs/lab4/tcp_reno_verbose/tcp_reno_verbose.c | jamestiotio/networks | 8967ee34c423989ff68eec650ba6ebb492499cb4 | [
"MIT"
] | null | null | null | #include <linux/module.h>
#include <linux/vmalloc.h>
#include <net/tcp.h>
void tcp_vreno_in_ack_event(struct sock *sk, u32 flags)
{
const struct tcp_sock *tp = tcp_sk(sk);
const struct inet_sock *isock = inet_sk(sk);
uint16_t sport = ntohs(isock->inet_sport);
uint16_t dport = ntohs(isock->inet_dport);
struct sk_buff *skb = tcp_write_queue_tail(sk);
uint16_t length = skb == NULL ? 0 : skb->len;
trace_printk(KERN_INFO "ACK Received. %pI4:%u %pI4:%u %d %#x %#x %u %u %u %u %u\n",
&isock->inet_saddr, sport, &isock->inet_daddr, dport, length, tp->snd_nxt, tp->snd_una, tp->snd_cwnd, tcp_current_ssthresh(sk), tp->snd_wnd, tp->rcv_wnd, tp->srtt_us >> 3);
}
struct tcp_congestion_ops tcp_reno_verbose = {
.flags = TCP_CONG_NON_RESTRICTED,
.name = "reno_verbose",
.owner = THIS_MODULE,
.ssthresh = tcp_reno_ssthresh,
.cong_avoid = tcp_reno_cong_avoid,
.undo_cwnd = tcp_reno_undo_cwnd,
.in_ack_event = tcp_vreno_in_ack_event,
};
static int __init tcp_reno_verbose_register(void)
{
printk(KERN_INFO "Verbose Reno Going Up...");
return tcp_register_congestion_control(&tcp_reno_verbose);
}
static void __exit tcp_reno_verbose_unregister(void)
{
printk(KERN_INFO "Verbose Reno Shutting Down...");
tcp_unregister_congestion_control(&tcp_reno_verbose);
}
module_init(tcp_reno_verbose_register);
module_exit(tcp_reno_verbose_unregister);
MODULE_AUTHOR("Yanev");
MODULE_AUTHOR("James Raphael Tiovalen");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Verbose TCP Reno");
| 27.345455 | 175 | 0.744681 |
4b8ac70dbf01ebd2b0acc750a195b6e6c467fbdb | 411 | h | C | Tools/EditorFramework/IPropertyInitialisator.h | lmj0591/mygui | 311fb9d07089f64558eb7f77e9b37c4cb91e3559 | [
"MIT"
] | 590 | 2015-01-06T09:22:06.000Z | 2022-03-21T18:23:02.000Z | Tools/EditorFramework/IPropertyInitialisator.h | lmj0591/mygui | 311fb9d07089f64558eb7f77e9b37c4cb91e3559 | [
"MIT"
] | 159 | 2015-01-07T03:34:23.000Z | 2022-02-21T21:28:51.000Z | Tools/EditorFramework/IPropertyInitialisator.h | lmj0591/mygui | 311fb9d07089f64558eb7f77e9b37c4cb91e3559 | [
"MIT"
] | 212 | 2015-01-05T07:33:33.000Z | 2022-03-28T22:11:51.000Z | /*!
@file
@author Albert Semenov
@date 08/2010
*/
#ifndef _e1352c42_fc8c_43d0_90a9_b2bc8bb0deb6_
#define _e1352c42_fc8c_43d0_90a9_b2bc8bb0deb6_
#include <memory>
#include "IFactoryItem.h"
namespace tools
{
class Property;
class MYGUI_EXPORT_DLL IPropertyInitialisator :
public components::IFactoryItem
{
public:
virtual void initialise(std::shared_ptr<Property> _property) = 0;
};
}
#endif
| 14.678571 | 67 | 0.766423 |
176e1fb890c21c38bac0578ce02ba0229523d682 | 269,316 | c | C | base/cluster/service/nm/network.c | npocmaka/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 17 | 2020-11-13T13:42:52.000Z | 2021-09-16T09:13:13.000Z | base/cluster/service/nm/network.c | sancho1952007/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 2 | 2020-10-19T08:02:06.000Z | 2020-10-19T08:23:18.000Z | base/cluster/service/nm/network.c | sancho1952007/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 14 | 2020-11-14T09:43:20.000Z | 2021-08-28T08:59:57.000Z | /*++
Copyright (c) 1996-1999 Microsoft Corporation
Module Name:
network.c
Abstract:
Implements the Node Manager's network management routines.
Author:
Mike Massa (mikemas) 7-Nov-1996
Revision History:
--*/
#include "nmp.h"
/////////////////////////////////////////////////////////////////////////////
//
// Data
//
/////////////////////////////////////////////////////////////////////////////
ULONG NmpNextNetworkShortId = 0;
LIST_ENTRY NmpNetworkList = {NULL, NULL};
LIST_ENTRY NmpInternalNetworkList = {NULL, NULL};
LIST_ENTRY NmpDeletedNetworkList = {NULL, NULL};
DWORD NmpNetworkCount = 0;
DWORD NmpInternalNetworkCount = 0;
DWORD NmpClientNetworkCount = 0;
BOOLEAN NmpIsConnectivityReportWorkerRunning = FALSE;
BOOLEAN NmpNeedConnectivityReport = FALSE;
CLRTL_WORK_ITEM NmpConnectivityReportWorkItem;
RESUTIL_PROPERTY_ITEM
NmpNetworkProperties[] =
{
{
L"Id", NULL, CLUSPROP_FORMAT_SZ,
0, 0, 0,
0,
FIELD_OFFSET(NM_NETWORK_INFO, Id)
},
{
CLUSREG_NAME_NET_NAME, NULL, CLUSPROP_FORMAT_SZ,
0, 0, 0,
0,
FIELD_OFFSET(NM_NETWORK_INFO, Name)
},
{
CLUSREG_NAME_NET_DESC, NULL, CLUSPROP_FORMAT_SZ,
(DWORD_PTR) NmpNullString, 0, 0,
0,
FIELD_OFFSET(NM_NETWORK_INFO, Description)
},
{
CLUSREG_NAME_NET_ROLE, NULL, CLUSPROP_FORMAT_DWORD,
ClusterNetworkRoleClientAccess,
ClusterNetworkRoleNone,
ClusterNetworkRoleInternalAndClient,
0,
FIELD_OFFSET(NM_NETWORK_INFO, Role)
},
{
CLUSREG_NAME_NET_PRIORITY, NULL, CLUSPROP_FORMAT_DWORD,
0, 0, 0xFFFFFFFF,
0,
FIELD_OFFSET(NM_NETWORK_INFO, Priority)
},
{
CLUSREG_NAME_NET_TRANSPORT, NULL, CLUSPROP_FORMAT_SZ,
0, 0, 0,
0,
FIELD_OFFSET(NM_NETWORK_INFO, Transport)
},
{
CLUSREG_NAME_NET_ADDRESS, NULL, CLUSPROP_FORMAT_SZ,
0, 0, 0,
0,
FIELD_OFFSET(NM_NETWORK_INFO, Address)
},
{
CLUSREG_NAME_NET_ADDRESS_MASK, NULL, CLUSPROP_FORMAT_SZ,
0, 0, 0,
0,
FIELD_OFFSET(NM_NETWORK_INFO, AddressMask)
},
{
0
}
};
/////////////////////////////////////////////////////////////////////////////
//
// Initialization & cleanup routines
//
/////////////////////////////////////////////////////////////////////////////
DWORD
NmpInitializeNetworks(
VOID
)
/*++
Routine Description:
Initializes network resources.
Arguments:
None.
Return Value:
A Win32 status value.
--*/
{
DWORD status;
OM_OBJECT_TYPE_INITIALIZE networkTypeInitializer;
ClRtlLogPrint(LOG_NOISE,"[NM] Initializing networks.\n");
//
// Create the network object type
//
ZeroMemory(&networkTypeInitializer, sizeof(OM_OBJECT_TYPE_INITIALIZE));
networkTypeInitializer.ObjectSize = sizeof(NM_NETWORK);
networkTypeInitializer.Signature = NM_NETWORK_SIG;
networkTypeInitializer.Name = L"Network";
networkTypeInitializer.DeleteObjectMethod = &NmpDestroyNetworkObject;
status = OmCreateType(ObjectTypeNetwork, &networkTypeInitializer);
if (status != ERROR_SUCCESS) {
WCHAR errorString[12];
wsprintfW(&(errorString[0]), L"%u", status);
CsLogEvent1(LOG_CRITICAL, CS_EVENT_ALLOCATION_FAILURE, errorString);
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Unable to create network object type, status %1!u!\n",
status
);
return(status);
}
return(status);
} // NmpInitializeNetworks
VOID
NmpCleanupNetworks(
VOID
)
/*++
Routine Description:
Destroys all existing network resources.
Arguments:
None.
Return Value:
None.
--*/
{
PNM_NETWORK network;
PLIST_ENTRY entry;
DWORD status;
ClRtlLogPrint(LOG_NOISE,"[NM] Network cleanup starting...\n");
//
// Now clean up all the network objects.
//
NmpAcquireLock();
while (!IsListEmpty(&NmpNetworkList)) {
entry = NmpNetworkList.Flink;
network = CONTAINING_RECORD(entry, NM_NETWORK, Linkage);
CL_ASSERT(NM_OM_INSERTED(network));
NmpDeleteNetworkObject(network, FALSE);
}
NmpMulticastCleanup();
NmpReleaseLock();
ClRtlLogPrint(LOG_NOISE,"[NM] Network cleanup complete\n");
return;
} // NmpCleanupNetworks
/////////////////////////////////////////////////////////////////////////////
//
// Top-level routines called during network configuration
//
/////////////////////////////////////////////////////////////////////////////
DWORD
NmpCreateNetwork(
IN RPC_BINDING_HANDLE JoinSponsorBinding,
IN PNM_NETWORK_INFO NetworkInfo,
IN PNM_INTERFACE_INFO2 InterfaceInfo
)
/*++
Notes:
Must not be called with NM lock held.
--*/
{
DWORD status;
if (JoinSponsorBinding != NULL) {
//
// We are joining a cluster. Ask the sponsor to add the definition
// to the cluster database. The sponsor will also prompt all active
// nodes to instantiate a corresponding object. The object will be
// instantiated locally later in the join process.
//
status = NmRpcCreateNetwork2(
JoinSponsorBinding,
NmpJoinSequence,
NmLocalNodeIdString,
NetworkInfo,
InterfaceInfo
);
}
else if (NmpState == NmStateOnlinePending) {
HLOCALXSACTION xaction;
//
// We are forming a cluster. Add the definitions to the database.
// The corresponding object will be created later in
// the form process.
//
//
// Start a transaction - this must be done before acquiring the
// NM lock.
//
xaction = DmBeginLocalUpdate();
if (xaction == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to start a transaction, status %1!u!\n",
status
);
return(status);
}
status = NmpCreateNetworkDefinition(NetworkInfo, xaction);
if (status == ERROR_SUCCESS) {
status = NmpCreateInterfaceDefinition(InterfaceInfo, xaction);
}
//
// Complete the transaction - this must be done after releasing
// the NM lock.
//
if (status == ERROR_SUCCESS) {
DmCommitLocalUpdate(xaction);
}
else {
DmAbortLocalUpdate(xaction);
}
}
else {
//
// We are online. This is a PnP update.
//
NmpAcquireLock();
status = NmpGlobalCreateNetwork(NetworkInfo, InterfaceInfo);
NmpReleaseLock();
}
return(status);
} // NmpCreateNetwork
DWORD
NmpSetNetworkName(
IN PNM_NETWORK_INFO NetworkInfo
)
/*++
Notes:
Must not be called with NM lock held.
--*/
{
DWORD status;
if (NmpState == NmStateOnlinePending) {
HLOCALXSACTION xaction;
//
// We are forming a cluster. The local connectoid name has
// precedence. Fix the cluster network name stored in the
// cluster database.
//
//
// Start a transaction - this must be done before acquiring the
// NM lock.
//
xaction = DmBeginLocalUpdate();
if (xaction == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to start a transaction, status %1!u!\n",
status
);
return(status);
}
status = NmpSetNetworkNameDefinition(NetworkInfo, xaction);
//
// Complete the transaction - this must be done after releasing
// the NM lock.
//
if (status == ERROR_SUCCESS) {
DmCommitLocalUpdate(xaction);
}
else {
DmAbortLocalUpdate(xaction);
}
}
else {
//
// We are online. This is either a PnP update or we were called
// back to indicate that a local connectoid name changed.
// Issue a global update to set the cluster network name accordingly.
//
status = NmpGlobalSetNetworkName( NetworkInfo );
}
return(status);
} // NmpSetNetworkName
/////////////////////////////////////////////////////////////////////////////
//
// Remote procedures called by joining nodes.
//
/////////////////////////////////////////////////////////////////////////////
error_status_t
s_NmRpcCreateNetwork(
IN handle_t IDL_handle,
IN DWORD JoinSequence, OPTIONAL
IN LPWSTR JoinerNodeId, OPTIONAL
IN PNM_NETWORK_INFO NetworkInfo,
IN PNM_INTERFACE_INFO InterfaceInfo1
)
{
DWORD status;
NM_INTERFACE_INFO2 interfaceInfo2;
//
// Translate and call the V2.0 procedure. The NetIndex isn't used in this call.
//
CopyMemory(&interfaceInfo2, InterfaceInfo1, sizeof(NM_INTERFACE_INFO));
interfaceInfo2.AdapterId = NmpUnknownString;
interfaceInfo2.NetIndex = NmInvalidInterfaceNetIndex;
status = s_NmRpcCreateNetwork2(
IDL_handle,
JoinSequence,
JoinerNodeId,
NetworkInfo,
&interfaceInfo2
);
return(status);
} // s_NmRpcCreateNetwork
error_status_t
s_NmRpcCreateNetwork2(
IN handle_t IDL_handle,
IN DWORD JoinSequence, OPTIONAL
IN LPWSTR JoinerNodeId, OPTIONAL
IN PNM_NETWORK_INFO NetworkInfo,
IN PNM_INTERFACE_INFO2 InterfaceInfo
)
{
DWORD status = ERROR_SUCCESS;
ClRtlLogPrint(LOG_NOISE,
"[NMJOIN] Received request to create new network %1!ws! for "
"joining node.\n",
NetworkInfo->Id
);
NmpAcquireLock();
if (NmpLockedEnterApi(NmStateOnline)) {
PNM_NODE joinerNode = NULL;
if (lstrcmpW(JoinerNodeId, NmpInvalidJoinerIdString) != 0) {
joinerNode = OmReferenceObjectById(
ObjectTypeNode,
JoinerNodeId
);
if (joinerNode != NULL) {
if ( (JoinSequence == NmpJoinSequence) &&
(NmpJoinerNodeId == joinerNode->NodeId) &&
(NmpSponsorNodeId == NmLocalNodeId) &&
!NmpJoinAbortPending
)
{
CL_ASSERT(joinerNode->State == ClusterNodeJoining);
CL_ASSERT(NmpJoinerUp == FALSE);
CL_ASSERT(NmpJoinTimer != 0);
//
// Suspend the join timer while we are working on
// behalf of the joiner. This precludes an abort
// from occuring as well.
//
NmpJoinTimer = 0;
}
else {
status = ERROR_CLUSTER_JOIN_ABORTED;
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] CreateNetwork call for joining node %1!ws! "
"failed because the join was aborted.\n",
JoinerNodeId
);
}
}
else {
status = ERROR_CLUSTER_NODE_NOT_MEMBER;
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] CreateNetwork call for joining node %1!ws! "
"failed because the node is not a member of the "
"cluster.\n",
JoinerNodeId
);
}
}
if (status == ERROR_SUCCESS) {
status = NmpGlobalCreateNetwork(NetworkInfo, InterfaceInfo);
if (joinerNode != NULL) {
//
// Verify that the join is still in progress
//
if ( (JoinSequence == NmpJoinSequence) &&
(NmpJoinerNodeId == joinerNode->NodeId)
)
{
CL_ASSERT(joinerNode->State == ClusterNodeJoining);
CL_ASSERT(NmpJoinerUp == FALSE);
CL_ASSERT(NmpSponsorNodeId == NmLocalNodeId);
CL_ASSERT(NmpJoinTimer == 0);
CL_ASSERT(NmpJoinAbortPending == FALSE);
if (status == ERROR_SUCCESS) {
//
// Restart the join timer.
//
NmpJoinTimer = NM_JOIN_TIMEOUT;
}
else {
//
// Abort the join
//
NmpJoinAbort(status, joinerNode);
}
}
else {
status = ERROR_CLUSTER_JOIN_ABORTED;
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] CreateNetwork call for joining node %1!ws! "
"failed because the join was aborted.\n",
JoinerNodeId
);
}
}
}
if (joinerNode != NULL) {
OmDereferenceObject(joinerNode);
}
NmpLockedLeaveApi();
}
else {
status = ERROR_NODE_NOT_AVAILABLE;
ClRtlLogPrint(LOG_NOISE,
"[NMJOIN] Not in valid state to process CreateNetwork request.\n"
);
}
NmpReleaseLock();
return(status);
} // s_NmRpcCreateNetwork2
error_status_t
s_NmRpcSetNetworkName(
IN handle_t IDL_handle,
IN DWORD JoinSequence, OPTIONAL
IN LPWSTR JoinerNodeId, OPTIONAL
IN PNM_NETWORK_INFO NetworkInfo
)
{
DWORD status = ERROR_SUCCESS;
ClRtlLogPrint(LOG_NOISE,
"[NMJOIN] Received request to set name of network %1!ws! from "
"joining node %2!ws!.\n",
NetworkInfo->Id,
JoinerNodeId
);
NmpAcquireLock();
if (NmpLockedEnterApi(NmStateOnline)) {
PNM_NODE joinerNode = NULL;
if (lstrcmpW(JoinerNodeId, NmpInvalidJoinerIdString) != 0) {
joinerNode = OmReferenceObjectById(
ObjectTypeNode,
JoinerNodeId
);
if (joinerNode != NULL) {
if ( (JoinSequence == NmpJoinSequence) &&
(NmpJoinerNodeId == joinerNode->NodeId) &&
(NmpSponsorNodeId == NmLocalNodeId) &&
!NmpJoinAbortPending
)
{
CL_ASSERT(joinerNode->State == ClusterNodeJoining);
CL_ASSERT(NmpJoinerUp == FALSE);
CL_ASSERT(NmpJoinTimer != 0);
//
// Suspend the join timer while we are working on
// behalf of the joiner. This precludes an abort
// from occuring as well.
//
NmpJoinTimer = 0;
}
else {
status = ERROR_CLUSTER_JOIN_ABORTED;
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] SetNetworkName call for joining node "
"%1!ws! failed because the join was aborted.\n",
JoinerNodeId
);
}
}
else {
status = ERROR_CLUSTER_NODE_NOT_MEMBER;
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] SetNetworkName call for joining node %1!ws! "
"failed because the node is not a member of the cluster.\n",
JoinerNodeId
);
}
}
if (status == ERROR_SUCCESS) {
status = NmpGlobalSetNetworkName( NetworkInfo );
if (joinerNode != NULL) {
//
// Verify that the join is still in progress
//
if ( (JoinSequence == NmpJoinSequence) &&
(NmpJoinerNodeId == joinerNode->NodeId)
)
{
CL_ASSERT(joinerNode->State == ClusterNodeJoining);
CL_ASSERT(NmpJoinerUp == FALSE);
CL_ASSERT(NmpSponsorNodeId == NmLocalNodeId);
CL_ASSERT(NmpJoinTimer == 0);
CL_ASSERT(NmpJoinAbortPending == FALSE);
if (status == ERROR_SUCCESS) {
//
// Restart the join timer.
//
NmpJoinTimer = NM_JOIN_TIMEOUT;
}
else {
//
// Abort the join
//
NmpJoinAbort(status, joinerNode);
}
}
else {
status = ERROR_CLUSTER_JOIN_ABORTED;
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] SetNetworkName call for joining node "
"%1!ws! failed because the join was aborted.\n",
JoinerNodeId
);
}
}
}
if (joinerNode != NULL) {
OmDereferenceObject(joinerNode);
}
NmpLockedLeaveApi();
}
else {
status = ERROR_NODE_NOT_AVAILABLE;
ClRtlLogPrint(LOG_NOISE,
"[NMJOIN] Not in valid state to process SetNetworkName request.\n"
);
}
NmpReleaseLock();
return(status);
} // s_NmRpcSetNetworkName
error_status_t
s_NmRpcEnumNetworkDefinitions(
IN handle_t IDL_handle,
IN DWORD JoinSequence, OPTIONAL
IN LPWSTR JoinerNodeId, OPTIONAL
OUT PNM_NETWORK_ENUM * NetworkEnum
)
{
DWORD status = ERROR_SUCCESS;
PNM_NODE joinerNode = NULL;
NmpAcquireLock();
if (NmpLockedEnterApi(NmStateOnline)) {
ClRtlLogPrint(LOG_NOISE,
"[NMJOIN] Supplying network information to joining node.\n"
);
if (lstrcmpW(JoinerNodeId, NmpInvalidJoinerIdString) != 0) {
joinerNode = OmReferenceObjectById(
ObjectTypeNode,
JoinerNodeId
);
if (joinerNode != NULL) {
if ( (JoinSequence == NmpJoinSequence) &&
(NmpJoinerNodeId == joinerNode->NodeId) &&
(NmpSponsorNodeId == NmLocalNodeId) &&
!NmpJoinAbortPending
)
{
CL_ASSERT(joinerNode->State == ClusterNodeJoining);
CL_ASSERT(NmpJoinerUp == FALSE);
CL_ASSERT(NmpJoinTimer != 0);
//
// Suspend the join timer while we are working on
// behalf of the joiner. This precludes an abort
// from occuring as well.
//
NmpJoinTimer = 0;
}
else {
status = ERROR_CLUSTER_JOIN_ABORTED;
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] EnumNetworkDefinitions call for joining "
"node %1!ws! failed because the join was aborted.\n",
JoinerNodeId
);
}
}
else {
status = ERROR_CLUSTER_NODE_NOT_MEMBER;
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] EnumNetworkDefinitions call for joining "
"node %1!ws! failed because the node is not a member "
"of the cluster.\n",
JoinerNodeId
);
}
}
if (status == ERROR_SUCCESS) {
status = NmpEnumNetworkObjects(NetworkEnum);
if (joinerNode != NULL) {
if (status == ERROR_SUCCESS) {
//
// Restart the join timer.
//
NmpJoinTimer = NM_JOIN_TIMEOUT;
}
else {
ClRtlLogPrint(LOG_CRITICAL,
"[NMJOIN] Failed to enumerate network definitions, "
"status %1!u!.\n",
status
);
//
// Abort the join
//
NmpJoinAbort(status, joinerNode);
}
}
}
if (joinerNode != NULL) {
OmDereferenceObject(joinerNode);
}
NmpLockedLeaveApi();
}
else {
status = ERROR_NODE_NOT_AVAILABLE;
ClRtlLogPrint(LOG_NOISE,
"[NMJOIN] Not in valid state to process EnumNetworkDefinitions "
"request.\n"
);
}
NmpReleaseLock();
return(status);
} // s_NmRpcEnumNetworkDefinitions
error_status_t
s_NmRpcEnumNetworkAndInterfaceStates(
IN handle_t IDL_handle,
IN DWORD JoinSequence,
IN LPWSTR JoinerNodeId,
OUT PNM_NETWORK_STATE_ENUM * NetworkStateEnum,
OUT PNM_INTERFACE_STATE_ENUM * InterfaceStateEnum
)
{
DWORD status = ERROR_SUCCESS;
NmpAcquireLock();
if (NmpLockedEnterApi(NmStateOnline)) {
PNM_NODE joinerNode = OmReferenceObjectById(
ObjectTypeNode,
JoinerNodeId
);
ClRtlLogPrint(LOG_NOISE,
"[NMJOIN] Supplying network and interface state information "
"to joining node.\n"
);
if (joinerNode != NULL) {
if ( (JoinSequence != NmpJoinSequence) ||
(NmpJoinerNodeId != joinerNode->NodeId) ||
(NmpSponsorNodeId != NmLocalNodeId) ||
NmpJoinAbortPending
)
{
status = ERROR_CLUSTER_JOIN_ABORTED;
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] EnumNetworkAndInterfaceStates call for "
"joining node %1!ws! failed because the join was "
"aborted.\n",
JoinerNodeId
);
}
else {
CL_ASSERT(joinerNode->State == ClusterNodeJoining);
CL_ASSERT(NmpJoinerUp);
CL_ASSERT(NmpJoinTimer == 0);
}
}
else {
status = ERROR_CLUSTER_NODE_NOT_MEMBER;
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] EnumNetworkAndInterfaceStates call for joining "
"node %1!ws! failed because the node is not a member of "
"the cluster.\n",
JoinerNodeId
);
}
if (status == ERROR_SUCCESS) {
status = NmpEnumNetworkObjectStates(NetworkStateEnum);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NMJOIN] EnumNetworkAndInterfaceStates failed, "
"status %1!u!.\n",
status
);
//
// Abort the join
//
NmpJoinAbort(status, joinerNode);
}
status = NmpEnumInterfaceObjectStates(InterfaceStateEnum);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NMJOIN] EnumNetworkAndInterfaceStates failed, "
"status %1!u!.\n",
status
);
//
// Abort the join
//
NmpJoinAbort(status, joinerNode);
NmpFreeNetworkStateEnum(*NetworkStateEnum);
*NetworkStateEnum = NULL;
}
}
if (joinerNode != NULL) {
OmDereferenceObject(joinerNode);
}
NmpLockedLeaveApi();
}
else {
status = ERROR_NODE_NOT_AVAILABLE;
ClRtlLogPrint(LOG_NOISE,
"[NMJOIN] Not in valid state to process "
"EnumNetworkAndInterfaceStates request.\n"
);
}
NmpReleaseLock();
return(status);
} // s_NmRpcEnumNetworkAndInterfaceStates
error_status_t
s_NmRpcGetNetworkMulticastKey(
IN PRPC_ASYNC_STATE AsyncState,
IN handle_t IDL_handle,
IN LPWSTR JoinerNodeId,
IN LPWSTR NetworkId,
OUT PNM_NETWORK_MULTICASTKEY * NetworkMulticastKey
)
{
DWORD status = ERROR_SUCCESS;
RPC_STATUS tempStatus;
*NetworkMulticastKey = NULL;
NmpAcquireLock();
if (NmpLockedEnterApi(NmStateOnline))
{
PNM_NODE joinerNode;
ClRtlLogPrint(LOG_NOISE,
"[NMJOIN] Supplying multicast key for network %1!ws! "
"to joining node %2!ws!.\n",
NetworkId,
JoinerNodeId
);
joinerNode = OmReferenceObjectById(ObjectTypeNode,
JoinerNodeId
);
if (joinerNode == NULL) {
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] s_NmRpcGetNetworkMulticastKey call for joining "
"node %1!ws! failed because the node is not a member of "
"the cluster.\n",
JoinerNodeId
);
status = ERROR_CLUSTER_NODE_NOT_MEMBER;
}
else
{
status = NmpGetNetworkMulticastKey(NetworkId,
NetworkMulticastKey);
if (status != ERROR_SUCCESS)
{
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] NmpGetNetworkMulticastKey failed, "
"status %1!u!.\n",
status
);
}
OmDereferenceObject(joinerNode);
}
NmpLockedLeaveApi();
}
else
{
ClRtlLogPrint(LOG_UNUSUAL,
"[NMJOIN] Not in valid state to process "
"NmRpcGetNetworkMulticastKey request.\n"
);
status = ERROR_NODE_NOT_AVAILABLE;
}
NmpReleaseLock();
tempStatus = RpcAsyncCompleteCall(AsyncState, &status);
if(tempStatus != RPC_S_OK)
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] s_NmRpcGetNetworkMulticastKey, Error Completing "
"Async RPC call, status %1!u!\n",
tempStatus
);
return(status);
} // s_NmRpcGetNetworkMulticastKey
/////////////////////////////////////////////////////////////////////////////
//
// Routines used to make global configuration changes when the node
// is online.
//
/////////////////////////////////////////////////////////////////////////////
DWORD
NmpGlobalCreateNetwork(
IN PNM_NETWORK_INFO NetworkInfo,
IN PNM_INTERFACE_INFO2 InterfaceInfo
)
/*++
Notes:
Called with the NmpLock held.
--*/
{
DWORD status = ERROR_SUCCESS;
DWORD networkPropertiesSize;
PVOID networkProperties;
ClRtlLogPrint(LOG_NOISE,
"[NM] Issuing global update to create network %1!ws! and "
"interface %2!ws!.\n",
NetworkInfo->Id,
InterfaceInfo->Id
);
//
// Marshall the info structures into property lists.
//
status = NmpMarshallObjectInfo(
NmpNetworkProperties,
NetworkInfo,
&networkProperties,
&networkPropertiesSize
);
if (status == ERROR_SUCCESS) {
DWORD interfacePropertiesSize;
PVOID interfaceProperties;
status = NmpMarshallObjectInfo(
NmpInterfaceProperties,
InterfaceInfo,
&interfaceProperties,
&interfacePropertiesSize
);
if (status == ERROR_SUCCESS) {
NmpReleaseLock();
//
// Issue a global update to create the network
//
status = GumSendUpdateEx(
GumUpdateMembership,
NmUpdateCreateNetwork,
4,
networkPropertiesSize,
networkProperties,
sizeof(networkPropertiesSize),
&networkPropertiesSize,
interfacePropertiesSize,
interfaceProperties,
sizeof(interfacePropertiesSize),
&interfacePropertiesSize
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Global update to create network %1!ws! failed, "
"status %2!u!.\n",
NetworkInfo->Id,
status
);
}
NmpAcquireLock();
MIDL_user_free(interfaceProperties);
}
else {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to marshall properties for new interface "
"%1!ws!, status %2!u!\n",
InterfaceInfo->Id,
status
);
}
MIDL_user_free(networkProperties);
}
else {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to marshall properties for new network %1!ws!, "
"status %2!u!\n",
NetworkInfo->Id,
status
);
}
return(status);
} // NmpGlobalCreateNetwork
DWORD
NmpGlobalSetNetworkName(
IN PNM_NETWORK_INFO NetworkInfo
)
/*++
Routine Description:
Changes the name of a network defined for the cluster.
Arguments:
NetworkInfo - A pointer to info about the network to be modified.
Return Value:
ERROR_SUCCESS if the routine succeeds.
A Win32 error code otherwise.
Notes:
Must not be called with NM lock held.
--*/
{
DWORD status = ERROR_SUCCESS;
if (status == ERROR_SUCCESS) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Processing request to set name for network %1!ws! "
"to '%2!ws!'.\n",
NetworkInfo->Id,
NetworkInfo->Name
);
//
// Issue a global update
//
status = GumSendUpdateEx(
GumUpdateMembership,
NmUpdateSetNetworkName,
2,
NM_WCSLEN(NetworkInfo->Id),
NetworkInfo->Id,
NM_WCSLEN( NetworkInfo->Name ),
NetworkInfo->Name
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Global update to set name of network %1!ws! "
"failed, status %2!u!.\n",
NetworkInfo->Id,
status
);
}
}
else {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] New name parameter supplied for network %1!ws! is invalid\n",
NetworkInfo->Id
);
}
return(status);
} // NmpGlobalSetNetworkName
DWORD
NmpGlobalSetNetworkAndInterfaceStates(
PNM_NETWORK Network,
CLUSTER_NETWORK_STATE NewNetworkState
)
/*++
Notes:
Called with NmpLock held and the Network referenced.
--*/
{
DWORD status;
DWORD i;
LPCWSTR networkId = OmObjectId(Network);
DWORD entryCount = Network->ConnectivityVector->EntryCount;
DWORD vectorSize = sizeof(NM_STATE_ENTRY) * entryCount;
PNM_STATE_ENTRY ifStateVector;
ifStateVector = LocalAlloc(LMEM_FIXED, vectorSize);
if (ifStateVector != NULL ) {
for (i=0; i< entryCount; i++) {
ifStateVector[i] = Network->StateWorkVector[i].State;
}
// DavidDio 8/16/2001
// Bug 456951: Check the NmpGumUpdateHandlerRegistered flag
// rather than the NmState to determine whether a GUM
// update or a local routine should be used to set the
// state.
if (NmpGumUpdateHandlerRegistered) {
//
// Issue a global state update for this network.
//
NmpReleaseLock();
status = GumSendUpdateEx(
GumUpdateMembership,
NmUpdateSetNetworkAndInterfaceStates,
4,
NM_WCSLEN(networkId),
networkId,
sizeof(NewNetworkState),
&NewNetworkState,
vectorSize,
ifStateVector,
sizeof(entryCount),
&entryCount
);
NmpAcquireLock();
}
else {
CL_ASSERT(NmpState == NmStateOnlinePending);
//
// We're still in the form process. Bypass GUM.
//
NmpSetNetworkAndInterfaceStates(
Network,
NewNetworkState,
ifStateVector,
entryCount
);
status = ERROR_SUCCESS;
}
LocalFree(ifStateVector);
}
else {
status = ERROR_NOT_ENOUGH_MEMORY;
}
return(status);
} // NmpGlobalSetNetworkAndInterfaceStates
/////////////////////////////////////////////////////////////////////////////
//
// Routines called by other cluster service components
//
/////////////////////////////////////////////////////////////////////////////
CLUSTER_NETWORK_STATE
NmGetNetworkState(
IN PNM_NETWORK Network
)
/*++
Routine Description:
Arguments:
Return Value:
Notes:
Because the caller must have a reference on the object and the
call is so simple, there is no reason to put the call through the
EnterApi/LeaveApi dance.
--*/
{
CLUSTER_NETWORK_STATE state;
NmpAcquireLock();
state = Network->State;
NmpReleaseLock();
return(state);
} // NmGetNetworkState
DWORD
NmSetNetworkName(
IN PNM_NETWORK Network,
IN LPCWSTR Name
)
/*++
Routine Description:
Changes the name of a network defined for the cluster.
Arguments:
Network - A pointer to the object for the network to be modified.
Return Value:
ERROR_SUCCESS if the routine succeeds.
A Win32 error code otherwise.
Notes:
The network object must be referenced by the caller.
--*/
{
DWORD status = ERROR_SUCCESS;
if (NmpEnterApi(NmStateOnline)) {
LPCWSTR networkId = OmObjectId(Network);
DWORD nameLength;
//
// Validate the name
//
try {
nameLength = lstrlenW(Name);
if (nameLength == 0) {
status = ERROR_INVALID_PARAMETER;
}
}
except (EXCEPTION_EXECUTE_HANDLER) {
status = ERROR_INVALID_PARAMETER;
}
if (status == ERROR_SUCCESS) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Processing request to set name for network %1!ws! "
"to %2!ws!.\n",
networkId,
Name
);
//
// Issue a global update
//
status = GumSendUpdateEx(
GumUpdateMembership,
NmUpdateSetNetworkName,
2,
NM_WCSLEN(networkId),
networkId,
(nameLength + 1) * sizeof(WCHAR),
Name
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Global update to set name of network %1!ws! "
"failed, status %2!u!.\n",
networkId,
status
);
}
}
else {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] New name parameter supplied for network %1!ws! "
"is invalid\n",
networkId
);
}
NmpLeaveApi();
}
else {
status = ERROR_NODE_NOT_AVAILABLE;
ClRtlLogPrint(LOG_NOISE,
"[NM] Not in valid state to process SetNetworkName request.\n"
);
}
return(status);
} // NmSetNetworkName
DWORD
NmSetNetworkPriorityOrder(
IN DWORD NetworkCount,
IN LPWSTR * NetworkIdList
)
/*++
Routine Description:
Sets the priority ordering of internal networks.
Arguments:
NetworkCount - Contains the count of items in NetworkIdList.
NetworkIdList - A pointer to an array of pointers to unicode strings.
Each string contains the ID of one internal network.
The array is sorted in priority order. The highest
priority network is listed first in the array.
Return Value:
ERROR_SUCCESS if the routine is successful.
A Win32 error code othewise.
--*/
{
DWORD status = ERROR_SUCCESS;
if (NetworkCount == 0) {
return(ERROR_INVALID_PARAMETER);
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Received request to set network priority order.\n"
);
if (NmpEnterApi(NmStateOnline)) {
DWORD i;
DWORD multiSzLength = 0;
PVOID multiSz = NULL;
//
// Marshall the network ID list into a MULTI_SZ.
//
for (i=0; i< NetworkCount; i++) {
multiSzLength += NM_WCSLEN(NetworkIdList[i]);
}
multiSzLength += sizeof(UNICODE_NULL);
multiSz = MIDL_user_allocate(multiSzLength);
if (multiSz != NULL) {
LPWSTR tmp = multiSz;
for (i=0; i< NetworkCount; i++) {
lstrcpyW(tmp, NetworkIdList[i]);
tmp += lstrlenW(NetworkIdList[i]) + 1;
}
*tmp = UNICODE_NULL;
//
// Issue a global update
//
status = GumSendUpdateEx(
GumUpdateMembership,
NmUpdateSetNetworkPriorityOrder,
1,
multiSzLength,
multiSz
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Global update to reprioritize networks failed, "
"status %1!u!.\n",
status
);
}
MIDL_user_free(multiSz);
}
else {
status = ERROR_NOT_ENOUGH_MEMORY;
}
NmpLeaveApi();
}
else {
status = ERROR_NODE_NOT_AVAILABLE;
ClRtlLogPrint(LOG_NOISE,
"[NM] Not in valid state to process a request to set the "
"network priority order.\n"
);
}
return(status);
} // NmSetNetworkPriorityOrder
DWORD
NmEnumInternalNetworks(
OUT LPDWORD NetworkCount,
OUT PNM_NETWORK * NetworkList[]
)
/*++
Routine Description:
Returns a prioritized list of networks that are eligible to
carry internal communication.
Arguments:
NetworkCount - On output, contains the number of items in NetworkList.
NetworkList - On output, points to an array of pointers to network
objects. The highest priority network is first in the
array. Each pointer in the array must be dereferenced
by the caller. The storage for the array must be
deallocated by the caller.
Return Value:
ERROR_SUCCESS if the routine is successful.
A Win32 error code othewise.
--*/
{
DWORD status;
NmpAcquireLock();
if (NmpLockedEnterApi(NmStateOnline)) {
status = NmpEnumInternalNetworks(NetworkCount, NetworkList);
NmpLockedLeaveApi();
}
else {
status = ERROR_NODE_NOT_AVAILABLE;
ClRtlLogPrint(LOG_NOISE,
"[NM] Not in valid state to process EnumInternalNetworks "
"request.\n"
);
}
NmpReleaseLock();
return(status);
} // NmEnumInternalNetworks
DWORD
NmpEnumInternalNetworks(
OUT LPDWORD NetworkCount,
OUT PNM_NETWORK * NetworkList[]
)
/*++
Routine Description:
Returns a prioritized list of networks that are eligible to
carry internal communication.
Arguments:
NetworkCount - On output, contains the number of items in NetworkList.
NetworkList - On output, points to an array of pointers to network
objects. The highest priority network is first in the
array. Each pointer in the array must be dereferenced
by the caller. The storage for the array must be
deallocated by the caller.
Return Value:
ERROR_SUCCESS if the routine is successful.
A Win32 error code othewise.
Notes:
Called with NM Lock held.
--*/
{
DWORD status = ERROR_SUCCESS;
if (NmpInternalNetworkCount > 0) {
PNM_NETWORK * networkList = LocalAlloc(
LMEM_FIXED,
( sizeof(PNM_NETWORK) *
NmpInternalNetworkCount)
);
if (networkList != NULL) {
PNM_NETWORK network;
PLIST_ENTRY entry;
DWORD networkCount = 0;
//
// The internal network list is sorted in priority order.
// The highest priority network is at the head of the list.
//
for (entry = NmpInternalNetworkList.Flink;
entry != &NmpInternalNetworkList;
entry = entry->Flink
)
{
network = CONTAINING_RECORD(
entry,
NM_NETWORK,
InternalLinkage
);
CL_ASSERT(NmpIsNetworkForInternalUse(network));
OmReferenceObject(network);
networkList[networkCount++] = network;
}
CL_ASSERT(networkCount == NmpInternalNetworkCount);
*NetworkCount = networkCount;
*NetworkList = networkList;
}
else {
status = ERROR_NOT_ENOUGH_MEMORY;
}
}
else {
*NetworkCount = 0;
*NetworkList = NULL;
}
return(status);
} // NmpEnumInternalNetworks
DWORD
NmEnumNetworkInterfaces(
IN PNM_NETWORK Network,
OUT LPDWORD InterfaceCount,
OUT PNM_INTERFACE * InterfaceList[]
)
/*++
Routine Description:
Returns the list of interfaces associated with a specified network.
Arguments:
Network - A pointer to the network object for which to enumerate
interfaces.
InterfaceCount - On output, contains the number of items in InterfaceList.
InterfaceList - On output, points to an array of pointers to interface
objects. Each pointer in the array must be dereferenced
by the caller. The storage for the array must be
deallocated by the caller.
Return Value:
ERROR_SUCCESS if the routine is successful.
A Win32 error code othewise.
--*/
{
DWORD status = ERROR_SUCCESS;
NmpAcquireLock();
if (NmpLockedEnterApi(NmStateOnline)) {
if (Network->InterfaceCount > 0) {
PNM_INTERFACE * interfaceList = LocalAlloc(
LMEM_FIXED,
( sizeof(PNM_INTERFACE) *
Network->InterfaceCount)
);
if (interfaceList != NULL) {
PNM_INTERFACE netInterface;
PLIST_ENTRY entry;
DWORD i;
for (entry = Network->InterfaceList.Flink, i=0;
entry != &(Network->InterfaceList);
entry = entry->Flink, i++
)
{
netInterface = CONTAINING_RECORD(
entry,
NM_INTERFACE,
NetworkLinkage
);
OmReferenceObject(netInterface);
interfaceList[i] = netInterface;
}
*InterfaceCount = Network->InterfaceCount;
*InterfaceList = interfaceList;
}
else {
status = ERROR_NOT_ENOUGH_MEMORY;
}
}
else {
*InterfaceCount = 0;
*InterfaceList = NULL;
}
NmpLockedLeaveApi();
}
else {
status = ERROR_NODE_NOT_AVAILABLE;
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Not in valid state to process EnumNetworkInterfaces "
"request.\n"
);
}
NmpReleaseLock();
return(status);
} // NmEnumNetworkInterfaces
/////////////////////////////////////////////////////////////////////////////
//
// Handlers for global updates
//
/////////////////////////////////////////////////////////////////////////////
DWORD
NmpUpdateCreateNetwork(
IN BOOL IsSourceNode,
IN PVOID NetworkPropertyList,
IN LPDWORD NetworkPropertyListSize,
IN PVOID InterfacePropertyList,
IN LPDWORD InterfacePropertyListSize
)
/*++
Routine Description:
Global update handler for creating a new network. The network
definition is read from the cluster database, and a corresponding
object is instantiated. The cluster transport is also updated if
necessary.
Arguments:
IsSourceNode - Set to TRUE if this node is the source of the update.
Set to FALSE otherwise.
Return Value:
ERROR_SUCCESS if the routine succeeds.
A Win32 error code otherwise.
Notes:
This routine must not be called with NM lock held.
--*/
{
DWORD status;
NM_NETWORK_INFO networkInfo;
NM_INTERFACE_INFO2 interfaceInfo;
PNM_NETWORK network = NULL;
PNM_INTERFACE netInterface = NULL;
HLOCALXSACTION xaction = NULL;
BOOLEAN isInternalNetwork = FALSE;
BOOLEAN isLockAcquired = FALSE;
CL_NODE_ID joinerNodeId;
if (!NmpEnterApi(NmStateOnline)) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Not in valid state to process CreateNetwork update.\n"
);
return(ERROR_NODE_NOT_AVAILABLE);
}
//
// Unmarshall the property lists.
//
ZeroMemory(&networkInfo, sizeof(networkInfo));
ZeroMemory(&interfaceInfo, sizeof(interfaceInfo));
status = ClRtlVerifyPropertyTable(
NmpNetworkProperties,
NULL, // Reserved
FALSE, // Don't allow unknowns
NetworkPropertyList,
*NetworkPropertyListSize,
(LPBYTE) &networkInfo
);
if ( status != ERROR_SUCCESS ) {
ClRtlLogPrint( LOG_CRITICAL,
"[NM] Failed to unmarshall properties for new network, "
"status %1!u!.\n",
status
);
goto error_exit;
}
status = ClRtlVerifyPropertyTable(
NmpInterfaceProperties,
NULL, // Reserved
FALSE, // Don't allow unknowns
InterfacePropertyList,
*InterfacePropertyListSize,
(LPBYTE) &interfaceInfo
);
if ( status != ERROR_SUCCESS ) {
ClRtlLogPrint( LOG_CRITICAL,
"[NM] Failed to unmarshall properties for new interface, "
"status %1!u!.\n",
status
);
goto error_exit;
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Received update to create network %1!ws! & interface %2!ws!.\n",
networkInfo.Id,
interfaceInfo.Id
);
//
// Start a transaction - this must be done before acquiring the NM lock.
//
xaction = DmBeginLocalUpdate();
if (xaction == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to begin a transaction, status %1!u!\n",
status
);
goto error_exit;
}
NmpAcquireLock(); isLockAcquired = TRUE;
//
// Fix up the network's priority, if needed.
//
if (networkInfo.Role & ClusterNetworkRoleInternalUse) {
CL_ASSERT(networkInfo.Priority == 0xFFFFFFFF);
//
// The network's priority is one greater than that of the lowest
// priority network already in the internal network list.
//
if (IsListEmpty(&NmpInternalNetworkList)) {
networkInfo.Priority = 1;
}
else {
PNM_NETWORK lastnet = CONTAINING_RECORD(
NmpInternalNetworkList.Blink,
NM_NETWORK,
InternalLinkage
);
CL_ASSERT(lastnet->Priority != 0);
CL_ASSERT(lastnet->Priority != 0xFFFFFFFF);
networkInfo.Priority = lastnet->Priority + 1;
}
isInternalNetwork = TRUE;
}
//
// Update the database.
//
status = NmpCreateNetworkDefinition(&networkInfo, xaction);
if (status != ERROR_SUCCESS) {
goto error_exit;
}
status = NmpCreateInterfaceDefinition(&interfaceInfo, xaction);
if (status != ERROR_SUCCESS) {
goto error_exit;
}
joinerNodeId = NmpJoinerNodeId;
NmpReleaseLock(); isLockAcquired = FALSE;
network = NmpCreateNetworkObject(&networkInfo);
if (network == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to create object for network %1!ws!, "
"status %2!u!.\n",
networkInfo.Id,
status
);
goto error_exit;
}
netInterface = NmpCreateInterfaceObject(
&interfaceInfo,
TRUE // Do retry on failure
);
#ifdef CLUSTER_TESTPOINT
TESTPT(TpFailNmCreateNetwork) {
NmpAcquireLock();
NmpDeleteInterfaceObject(netInterface, FALSE); netInterface = NULL;
NmpReleaseLock();
SetLastError(999999);
}
#endif
NmpAcquireLock(); isLockAcquired = TRUE;
if (netInterface == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to create object for interface %1!ws!, "
"status %2!u!.\n",
interfaceInfo.Id,
status
);
NmpDeleteNetworkObject(network, FALSE);
OmDereferenceObject(network);
goto error_exit;
}
//
// If a node happens to be joining right now, flag the fact that
// it is now out of synch with the cluster config.
//
if ( ( (joinerNodeId != ClusterInvalidNodeId) &&
(netInterface->Node->NodeId != joinerNodeId)
) ||
( (NmpJoinerNodeId != ClusterInvalidNodeId) &&
(netInterface->Node->NodeId != NmpJoinerNodeId)
)
)
{
NmpJoinerOutOfSynch = TRUE;
}
ClusterEvent(CLUSTER_EVENT_NETWORK_ADDED, network);
ClusterEvent(CLUSTER_EVENT_NETINTERFACE_ADDED, netInterface);
if (isInternalNetwork) {
NmpIssueClusterPropertyChangeEvent();
}
OmDereferenceObject(netInterface);
OmDereferenceObject(network);
CL_ASSERT(status == ERROR_SUCCESS);
error_exit:
if (isLockAcquired) {
NmpLockedLeaveApi();
NmpReleaseLock();
}
else {
NmpLeaveApi();
}
if (xaction != NULL) {
//
// Complete the transaction - this must be done after releasing
// the NM lock.
//
if (status == ERROR_SUCCESS) {
DmCommitLocalUpdate(xaction);
}
else {
DmAbortLocalUpdate(xaction);
}
}
ClNetFreeNetworkInfo(&networkInfo);
ClNetFreeInterfaceInfo(&interfaceInfo);
return(status);
} // NmpUpdateCreateNetwork
DWORD
NmpUpdateSetNetworkName(
IN BOOL IsSourceNode,
IN LPWSTR NetworkId,
IN LPWSTR NewNetworkName
)
/*++
Routine Description:
Global update handler for setting the name of a network.
Arguments:
IsSourceNode - Set to TRUE if this node is the source of the update.
Set to FALSE otherwise.
NetworkId - A pointer to a unicode string containing the ID of the
network to update.
NewNetworkName - A pointer to a unicode string containing the new network name.
Return Value:
ERROR_SUCCESS if the routine succeeds.
A Win32 error code otherwise.
Notes:
This routine must not be called with NM lock held.
--*/
{
DWORD status;
DWORD i;
PLIST_ENTRY entry;
HLOCALXSACTION xaction = NULL;
HDMKEY networkKey;
HDMKEY netInterfaceKey;
PNM_NETWORK network = NULL;
PNM_INTERFACE netInterface;
LPCWSTR netInterfaceId;
LPCWSTR netInterfaceName;
LPCWSTR networkName;
LPCWSTR nodeName;
LPWSTR oldNetworkName = NULL;
LPWSTR * oldNameVector = NULL;
LPWSTR * newNameVector = NULL;
BOOLEAN isLockAcquired = FALSE;
DWORD interfaceCount;
if (!NmpEnterApi(NmStateOnline)) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Not in valid state to process SetNetworkName update.\n"
);
return(ERROR_NODE_NOT_AVAILABLE);
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Received update to set the name for network %1!ws! "
"to '%2!ws!'.\n",
NetworkId,
NewNetworkName
);
//
// Find the network's object
//
network = OmReferenceObjectById(ObjectTypeNetwork, NetworkId);
if (network == NULL) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Unable to find network %1!ws!.\n",
NetworkId
);
status = ERROR_CLUSTER_NETWORK_NOT_FOUND;
goto error_exit;
}
//
// Start a transaction - this must be done before acquiring the NM lock.
//
xaction = DmBeginLocalUpdate();
if (xaction == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to begin a transaction, status %1!u!\n",
status
);
goto error_exit;
}
NmpAcquireLock(); isLockAcquired = TRUE;
//
// compare the names. If the same, return success
//
if ( ClRtlStrICmp( OmObjectName( network ), NewNetworkName ) == 0 ) {
ClRtlLogPrint(LOG_NOISE, "[NM] Network name does not need changing.\n");
status = ERROR_SUCCESS;
goto error_exit;
}
networkName = OmObjectName(network);
oldNetworkName = LocalAlloc(LMEM_FIXED, NM_WCSLEN(networkName));
if (oldNetworkName == NULL) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to allocate memory for network %1!ws! name change!\n",
NetworkId
);
status = ERROR_NOT_ENOUGH_MEMORY;
goto error_exit;
}
wcscpy(oldNetworkName, networkName);
//
// Update the database.
//
// This processing can always be undone on error.
//
networkKey = DmOpenKey(DmNetworksKey, NetworkId, KEY_WRITE);
if (networkKey == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to open database key for network %1!ws!, "
"status %2!u!\n",
NetworkId,
status
);
goto error_exit;
}
status = DmLocalSetValue(
xaction,
networkKey,
CLUSREG_NAME_NET_NAME,
REG_SZ,
(CONST BYTE *) NewNetworkName,
NM_WCSLEN(NewNetworkName)
);
DmCloseKey(networkKey);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of name value failed for network %1!ws!, "
"status %2!u!.\n",
NetworkId,
status
);
goto error_exit;
}
//
// Update the names of all of the interfaces on this network
//
interfaceCount = network->InterfaceCount;
oldNameVector = LocalAlloc(
LMEM_FIXED | LMEM_ZEROINIT,
interfaceCount * sizeof(LPWSTR)
);
newNameVector = LocalAlloc(
LMEM_FIXED | LMEM_ZEROINIT,
interfaceCount * sizeof(LPWSTR)
);
if ((oldNameVector == NULL) || (newNameVector == NULL)) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to allocate memory for net interface name change.\n"
);
goto error_exit;
}
for (entry = network->InterfaceList.Flink, i = 0;
entry != &(network->InterfaceList);
entry = entry->Flink, i++
)
{
netInterface = CONTAINING_RECORD(entry, NM_INTERFACE, NetworkLinkage);
netInterfaceId = OmObjectId(netInterface);
netInterfaceName = OmObjectName(netInterface);
nodeName = OmObjectName(netInterface->Node);
oldNameVector[i] = LocalAlloc(
LMEM_FIXED,
NM_WCSLEN(netInterfaceName)
);
newNameVector[i] = ClNetMakeInterfaceName(
NULL,
(LPWSTR) nodeName,
NewNetworkName
);
if ((oldNameVector[i] == NULL) || (newNameVector[i] == NULL)) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to allocate memory for net interface name "
"change.\n"
);
goto error_exit;
}
wcscpy(oldNameVector[i], netInterfaceName);
netInterfaceKey = DmOpenKey(
DmNetInterfacesKey,
netInterfaceId,
KEY_WRITE
);
if (netInterfaceKey == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to open database key for net interface "
"%1!ws!, status %2!u!\n",
netInterfaceId,
status
);
goto error_exit;
}
status = DmLocalSetValue(
xaction,
netInterfaceKey,
CLUSREG_NAME_NETIFACE_NAME,
REG_SZ,
(CONST BYTE *) newNameVector[i],
NM_WCSLEN(newNameVector[i])
);
DmCloseKey(netInterfaceKey);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of name value failed for net interface %1!ws!, "
"status %2!u!.\n",
netInterfaceId,
status
);
goto error_exit;
}
}
//
// Update the in-memory objects.
//
// This processing may not be undoable on error.
//
//
// Update name of the network
//
status = OmSetObjectName(network, NewNetworkName);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to change name for network %1!ws!, status %2!u!\n",
NetworkId,
status
);
goto error_exit;
}
//
// Update the names of all of the interfaces on the network.
//
for (entry = network->InterfaceList.Flink, i = 0;
entry != &(network->InterfaceList);
entry = entry->Flink, i++
)
{
netInterface = CONTAINING_RECORD(entry, NM_INTERFACE, NetworkLinkage);
netInterfaceId = OmObjectId(netInterface);
status = OmSetObjectName(netInterface, newNameVector[i]);
if (status != ERROR_SUCCESS) {
//
// Try to undo what has already been done. If we fail, we must
// commit suicide to preserve consistency.
//
DWORD j;
PLIST_ENTRY entry2;
DWORD undoStatus;
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to change name for net interface %1!ws!, "
"status %2!u!\n",
netInterfaceId,
status
);
//
// Undo the update of the network name
//
undoStatus = OmSetObjectName(network, oldNetworkName);
if (undoStatus != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to undo change of name for network %1!ws!, "
"status %2!u!\n",
NetworkId,
undoStatus
);
CsInconsistencyHalt(undoStatus);
}
//
// Undo update of network interface names
//
for (j = 0, entry2 = network->InterfaceList.Flink;
j < i;
j++, entry2 = entry2->Flink
)
{
netInterface = CONTAINING_RECORD(
entry2,
NM_INTERFACE,
NetworkLinkage
);
netInterfaceId = OmObjectId(netInterface);
undoStatus = OmSetObjectName(netInterface, oldNameVector[i]);
if (undoStatus != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to undo change of name for net "
"interface %1!ws!, status %2!u!\n",
netInterfaceId,
undoStatus
);
CsInconsistencyHalt(undoStatus);
}
}
goto error_exit;
}
}
//
// Set the corresponding connectoid object name if necessary.
//
if (network->LocalInterface != NULL) {
INetConnection * connectoid;
LPWSTR connectoidName;
DWORD tempStatus;
connectoid = ClRtlFindConnectoidByGuid(
network->LocalInterface->AdapterId
);
if (connectoid != NULL) {
connectoidName = ClRtlGetConnectoidName(connectoid);
if (connectoidName != NULL) {
if (lstrcmpW(connectoidName, NewNetworkName) != 0) {
tempStatus = ClRtlSetConnectoidName(
connectoid,
NewNetworkName
);
if (tempStatus != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to set name of Network Connection "
"Object for interface on cluster network %1!ws! "
"(%2!ws!), status %3!u!\n",
oldNetworkName,
NetworkId,
tempStatus
);
} else {
// We expect to see a callback from the Network
// Connection Object with the name we just set.
// To avoid endless feedback loops, we need to
// ignore any other Network Connection Object
// callbacks until that one.
network->Flags |= NM_FLAG_NET_NAME_CHANGE_PENDING;
// We don't want to absolutely rely on the callback
// from the Network Connection Object, so we will
// set a timeout to clear the flag.
NmpStartNetworkNameChangePendingTimer(
network,
NM_NET_NAME_CHANGE_PENDING_TIMEOUT
);
}
}
}
else {
tempStatus = GetLastError();
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to query name of Network Connection Object "
"for interface on cluster network %1!ws! (%2!ws!), "
"status %3!u!\n",
oldNetworkName,
NetworkId,
tempStatus
);
}
INetConnection_Release( connectoid );
}
else {
tempStatus = GetLastError();
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to find Network Connection Object for "
"interface on cluster network %1!ws! (%2!ws!), "
"status %3!u!\n",
oldNetworkName,
NetworkId,
tempStatus
);
}
}
//
// Issue property change events.
//
ClusterEvent(CLUSTER_EVENT_NETWORK_PROPERTY_CHANGE, network);
for (entry = network->InterfaceList.Flink;
entry != &(network->InterfaceList);
entry = entry->Flink
)
{
netInterface = CONTAINING_RECORD(entry, NM_INTERFACE, NetworkLinkage);
ClusterEvent(
CLUSTER_EVENT_NETINTERFACE_PROPERTY_CHANGE,
netInterface
);
}
CL_ASSERT(status == ERROR_SUCCESS);
error_exit:
if (isLockAcquired) {
NmpLockedLeaveApi();
NmpReleaseLock();
}
else {
NmpLeaveApi();
}
if (xaction != NULL) {
//
// Complete the transaction - this must be done after releasing
// the NM lock.
//
if (status == ERROR_SUCCESS) {
DmCommitLocalUpdate(xaction);
}
else {
DmAbortLocalUpdate(xaction);
}
}
if (network != NULL) {
OmDereferenceObject(network);
if (oldNetworkName != NULL) {
LocalFree(oldNetworkName);
}
if (oldNameVector != NULL) {
for (i=0; i < interfaceCount; i++) {
if (oldNameVector[i] == NULL) {
break;
}
LocalFree(oldNameVector[i]);
}
LocalFree(oldNameVector);
}
if (newNameVector != NULL) {
for (i=0; i < interfaceCount; i++) {
if (newNameVector[i] == NULL) {
break;
}
LocalFree(newNameVector[i]);
}
LocalFree(newNameVector);
}
}
return(status);
} // NmpUpdateSetNetworkName
DWORD
NmpUpdateSetNetworkPriorityOrder(
IN BOOL IsSourceNode,
IN LPCWSTR NetworkIdList
)
{
DWORD status = ERROR_SUCCESS;
PNM_NETWORK network;
PLIST_ENTRY entry;
DWORD matchCount=0;
DWORD networkCount=0;
PNM_NETWORK * networkList=NULL;
DWORD i;
DWORD multiSzLength;
LPCWSTR networkId;
HLOCALXSACTION xaction = NULL;
BOOLEAN isLockAcquired = FALSE;
if (!NmpEnterApi(NmStateOnline)) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Not in valid state to process SetNetworkPriorityOrder "
"update.\n"
);
return(ERROR_NODE_NOT_AVAILABLE);
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Received update to set network priority order.\n"
);
//
// Unmarshall the MULTI_SZ
//
try {
multiSzLength = ClRtlMultiSzLength(NetworkIdList);
for (i=0; ; i++) {
networkId = ClRtlMultiSzEnum(
NetworkIdList,
multiSzLength,
i
);
if (networkId == NULL) {
break;
}
networkCount++;
}
}
except(EXCEPTION_EXECUTE_HANDLER) {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Hit exception while parsing network ID list for "
"priority change\n"
);
status = ERROR_INVALID_PARAMETER;
goto error_exit;
}
if (networkCount == 0) {
status = ERROR_INVALID_PARAMETER;
goto error_exit;
}
networkList = LocalAlloc(
LMEM_ZEROINIT| LMEM_FIXED,
networkCount * sizeof(PNM_NETWORK)
);
if (networkList == NULL) {
status = ERROR_NOT_ENOUGH_MEMORY;
goto error_exit;
}
//
// Start a transaction - this must be done before acquiring the NM lock.
//
xaction = DmBeginLocalUpdate();
if (xaction == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to start a transaction, status %1!u!\n",
status
);
goto error_exit;
}
NmpAcquireLock(); isLockAcquired = TRUE;
if (NmpJoinerNodeId != ClusterInvalidNodeId) {
status = ERROR_CLUSTER_JOIN_IN_PROGRESS;
ClRtlLogPrint(LOG_NOISE,
"[NM] Cannot set network priority order because a node is "
"joining the cluster.\n"
);
goto error_exit;
}
for (i=0; i<networkCount; i++) {
networkId = ClRtlMultiSzEnum(
NetworkIdList,
multiSzLength,
i
);
CL_ASSERT(networkId != NULL);
networkList[i] = OmReferenceObjectById(
ObjectTypeNetwork,
networkId
);
if (networkList[i] == NULL) {
goto error_exit;
}
}
//
// Verify that all of the networks specified are internal, and
// that all of the internal networks are specified.
//
if (networkCount != NmpInternalNetworkCount) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Supplied network count %1!u! doesn't match internal "
"network count %2!u!\n",
networkCount,
NmpInternalNetworkCount
);
status = ERROR_INVALID_PARAMETER;
goto error_exit;
}
for (entry = NmpInternalNetworkList.Flink, matchCount = 0;
entry != &NmpInternalNetworkList;
entry = entry->Flink
)
{
network = CONTAINING_RECORD(entry, NM_NETWORK, InternalLinkage);
if (NmpIsNetworkForInternalUse(network)) {
for (i=0; i<networkCount; i++) {
if (network == networkList[i]) {
matchCount++;
break;
}
}
if (i == networkCount) {
//
// This network is not in the list.
//
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Internal use network %1!ws! is not in priority "
"list\n",
(LPWSTR) OmObjectId(network)
);
status = ERROR_INVALID_PARAMETER;
goto error_exit;
}
}
}
if (matchCount != networkCount) {
//
// Some of the specified networks are not internal use.
//
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Some non-internal use networks are in priority list\n"
);
status = ERROR_INVALID_PARAMETER;
goto error_exit;
}
//
// The list is kosher. Set the priorities.
//
status = NmpSetNetworkPriorityOrder(networkCount, networkList, xaction);
error_exit:
if (isLockAcquired) {
NmpLockedLeaveApi();
NmpReleaseLock();
}
else {
NmpLeaveApi();
}
if (xaction != NULL) {
//
// Complete the transaction - this must be done after releasing
// the NM lock.
//
if (status == ERROR_SUCCESS) {
DmCommitLocalUpdate(xaction);
}
else {
DmAbortLocalUpdate(xaction);
}
}
if (networkList != NULL) {
for (i=0; i<networkCount; i++) {
if (networkList[i] != NULL) {
OmDereferenceObject(networkList[i]);
}
}
LocalFree(networkList);
}
return(status);
} // NmpUpdateSetNetworkPriorityOrder
DWORD
NmpSetNetworkPriorityOrder(
IN DWORD NetworkCount,
IN PNM_NETWORK * NetworkList,
IN HLOCALXSACTION Xaction
)
/*++
Notes:
Called with NM Lock held.
--*/
{
DWORD status = ERROR_SUCCESS;
PNM_NETWORK network;
DWORD i;
LPCWSTR networkId;
HDMKEY networkKey;
DWORD priority;
//
// Update the database first.
//
for (i=0, priority = 1; i<NetworkCount; i++, priority++) {
network = NetworkList[i];
networkId = OmObjectId(network);
CL_ASSERT(NmpIsNetworkForInternalUse(network));
if (network->Priority != priority) {
networkKey = DmOpenKey(DmNetworksKey, networkId, KEY_WRITE);
if (networkKey == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to open database key for network %1!ws!, "
"status %2!u!\n",
networkId,
status
);
return(status);
}
status = DmLocalSetValue(
Xaction,
networkKey,
CLUSREG_NAME_NET_PRIORITY,
REG_DWORD,
(CONST BYTE *) &priority,
sizeof(priority)
);
DmCloseKey(networkKey);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of priority value failed for network %1!ws!, "
"status %2!u!.\n",
networkId,
status
);
return(status);
}
}
}
#ifdef CLUSTER_TESTPOINT
TESTPT(TpFailNmSetNetworkPriorityOrder) {
status = 999999;
return(status);
}
#endif
//
// Update the in-memory representation
//
InitializeListHead(&NmpInternalNetworkList);
for (i=0, priority = 1; i<NetworkCount; i++, priority++) {
network = NetworkList[i];
networkId = OmObjectId(network);
InsertTailList(
&NmpInternalNetworkList,
&(network->InternalLinkage)
);
if (network->Priority != priority) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Set priority for network %1!ws! to %2!u!.\n",
networkId,
priority
);
network->Priority = priority;
//
// If the local node is attached to this network, set its
// priority in the cluster transport
//
if (NmpIsNetworkRegistered(network)) {
status = ClusnetSetNetworkPriority(
NmClusnetHandle,
network->ShortId,
network->Priority
);
#ifdef CLUSTER_TESTPOINT
TESTPT(TpFailNmSetNetworkPriorityOrder2) {
status = 999999;
}
#endif
if (status != ERROR_SUCCESS) {
//
// We can't easily abort here. We must either continue
// or commit suicide. We choose to continue and log an
// event.
//
WCHAR string[16];
wsprintfW(&(string[0]), L"%u", status);
CsLogEvent2(
LOG_UNUSUAL,
NM_EVENT_SET_NETWORK_PRIORITY_FAILED,
OmObjectName(network),
string
);
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Cluster transport failed to set priority for "
"network %1!ws!, status %2!u!\n",
networkId,
status
);
status = ERROR_SUCCESS;
}
}
}
}
CL_ASSERT(status == ERROR_SUCCESS);
//
// Issue a cluster property change event.
//
NmpIssueClusterPropertyChangeEvent();
return(ERROR_SUCCESS);
} // NmpSetNetworkPriorityOrder
DWORD
NmpUpdateSetNetworkCommonProperties(
IN BOOL IsSourceNode,
IN LPWSTR NetworkId,
IN UCHAR * PropertyList,
IN LPDWORD PropertyListLength
)
/*++
Routine Description:
Global update handler for setting the common properties of a network.
Arguments:
IsSourceNode - Set to TRUE if this node is the source of the update.
Set to FALSE otherwise.
NetworkId - A pointer to a unicode string containing the ID of the
network to update.
Return Value:
ERROR_SUCCESS if the routine succeeds.
A Win32 error code otherwise.
--*/
{
DWORD status = ERROR_SUCCESS;
NM_NETWORK_INFO networkInfo;
PNM_NETWORK network = NULL;
HLOCALXSACTION xaction = NULL;
HDMKEY networkKey = NULL;
DWORD descSize = 0;
LPWSTR descBuffer = NULL;
BOOLEAN propertyChanged = FALSE;
BOOLEAN isLockAcquired = FALSE;
if (!NmpEnterApi(NmStateOnline)) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Not in valid state to process SetNetworkCommonProperties "
"update.\n"
);
return(ERROR_NODE_NOT_AVAILABLE);
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Received update to set common properties for network %1!ws!.\n",
NetworkId
);
ZeroMemory(&networkInfo, sizeof(NM_NETWORK_INFO));
//
// Find the network's object
//
network = OmReferenceObjectById(ObjectTypeNetwork, NetworkId);
if (network == NULL) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Unable to find network %1!ws!.\n",
NetworkId
);
status = ERROR_CLUSTER_NETWORK_NOT_FOUND;
goto error_exit;
}
//
// Open the network's database key
//
networkKey = DmOpenKey(DmNetworksKey, NetworkId, KEY_WRITE);
if (networkKey == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to open database key for network %1!ws!, "
"status %2!u!\n",
NetworkId,
status
);
goto error_exit;
}
//
// Start a transaction - this must be done before acquiring the NM lock.
//
xaction = DmBeginLocalUpdate();
if (xaction == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to begin a transaction, status %1!u!\n",
status
);
goto error_exit;
}
NmpAcquireLock(); isLockAcquired = TRUE;
if (NmpJoinerNodeId != ClusterInvalidNodeId) {
status = ERROR_CLUSTER_JOIN_IN_PROGRESS;
ClRtlLogPrint(LOG_NOISE,
"[NM] Cannot set network common properties because a node is "
"joining the cluster.\n"
);
goto error_exit;
}
//
// Validate the property list and convert it to a network params struct.
//
status = NmpNetworkValidateCommonProperties(
network,
PropertyList,
*PropertyListLength,
&networkInfo
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Property list validation failed, status %1!u!.\n",
status
);
goto error_exit;
}
CL_ASSERT(network->Priority == networkInfo.Priority);
CL_ASSERT(wcscmp(NetworkId, networkInfo.Id) == 0);
CL_ASSERT(wcscmp(OmObjectName(network), networkInfo.Name) == 0);
CL_ASSERT(wcscmp(network->Transport, networkInfo.Transport) == 0);
CL_ASSERT(wcscmp(network->Address, networkInfo.Address) == 0);
CL_ASSERT(wcscmp(network->AddressMask, networkInfo.AddressMask) == 0);
//
// Check if the network's description has changed.
//
if (wcscmp(network->Description, networkInfo.Description) != 0) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Setting description for network %1!ws! to %2!ws!.\n",
NetworkId,
networkInfo.Description
);
//
// Allocate a buffer for the description string
//
descSize = NM_WCSLEN(networkInfo.Description);
descBuffer = MIDL_user_allocate(descSize);
if (descBuffer == NULL) {
status = ERROR_NOT_ENOUGH_MEMORY;
goto error_exit;
}
RtlMoveMemory(descBuffer, networkInfo.Description, descSize);
//
// Update the database
//
status = DmLocalSetValue(
xaction,
networkKey,
CLUSREG_NAME_NET_DESC,
REG_SZ,
(CONST BYTE *) networkInfo.Description,
descSize
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of description value failed for network %1!ws!, "
"status %2!u!.\n",
NetworkId,
status
);
goto error_exit;
}
//
// Updating the network object is deferred until the transaction
// commits.
//
propertyChanged = TRUE;
}
#ifdef CLUSTER_TESTPOINT
TESTPT(TpFailNmSetNetworkCommonProperties) {
status = 999999;
goto error_exit;
}
#endif
//
// Check if the network's role has changed.
//
//
// NOTE: This operation is not guaranteed to be reversible, so it must
// be the last thing we do in this routine. If it succeeds, the
// update must be committed.
//
if ( network->Role != ((CLUSTER_NETWORK_ROLE) networkInfo.Role) ) {
status = NmpSetNetworkRole(
network,
networkInfo.Role,
xaction,
networkKey
);
if (status != ERROR_SUCCESS) {
goto error_exit;
}
propertyChanged = TRUE;
}
if (propertyChanged) {
//
// Commit the updates to the network object in memory
//
if (descBuffer != NULL) {
MIDL_user_free(network->Description);
network->Description = descBuffer;
descBuffer = NULL;
}
//
// Issue a network property change event.
//
if (propertyChanged && (status == ERROR_SUCCESS)) {
ClusterEvent(CLUSTER_EVENT_NETWORK_PROPERTY_CHANGE, network);
}
}
CL_ASSERT(status == ERROR_SUCCESS);
error_exit:
if (isLockAcquired) {
NmpLockedLeaveApi();
NmpReleaseLock();
}
else {
NmpLeaveApi();
}
if (xaction != NULL) {
//
// Complete the transaction - this must be done after releasing
// the NM lock.
//
if (propertyChanged && (status == ERROR_SUCCESS)) {
DmCommitLocalUpdate(xaction);
}
else {
DmAbortLocalUpdate(xaction);
}
}
ClNetFreeNetworkInfo(&networkInfo);
if (descBuffer != NULL) {
MIDL_user_free(descBuffer);
}
if (networkKey != NULL) {
DmCloseKey(networkKey);
}
if (network != NULL) {
OmDereferenceObject(network);
}
return(status);
} // NmpUpdateSetNetworkCommonProperties
DWORD
NmpUpdateSetNetworkAndInterfaceStates(
IN BOOL IsSourceNode,
IN LPWSTR NetworkId,
IN CLUSTER_NETWORK_STATE * NewNetworkState,
IN PNM_STATE_ENTRY InterfaceStateVector,
IN LPDWORD InterfaceStateVectorSize
)
{
DWORD status = ERROR_SUCCESS;
PNM_NETWORK network;
NmpAcquireLock();
if (NmpLockedEnterApi(NmStateOnline)) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Received update to set state for network %1!ws!.\n",
NetworkId
);
//
// Find the network's object
//
network = OmReferenceObjectById(ObjectTypeNetwork, NetworkId);
if (network != NULL) {
NmpSetNetworkAndInterfaceStates(
network,
*NewNetworkState,
InterfaceStateVector,
*InterfaceStateVectorSize
);
OmDereferenceObject(network);
}
else {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Unable to find network %1!ws!.\n",
NetworkId
);
status = ERROR_CLUSTER_NETWORK_NOT_FOUND;
}
}
else {
ClRtlLogPrint(LOG_NOISE,
"[NM] Not in valid state to process SetNetworkAndInterfaceStates "
"update.\n"
);
status = ERROR_NODE_NOT_AVAILABLE;
}
NmpLockedLeaveApi();
NmpReleaseLock();
return(status);
} // NmpUpdateSetNetworkAndInterfaceStates
/////////////////////////////////////////////////////////////////////////////
//
// Helper routines for updates
//
/////////////////////////////////////////////////////////////////////////////
DWORD
NmpSetNetworkRole(
PNM_NETWORK Network,
CLUSTER_NETWORK_ROLE NewRole,
HLOCALXSACTION Xaction,
HDMKEY NetworkKey
)
/*++
Called with the NmpLock acquired.
This operation is not guaranteed to be reversible, so this
function is coded such that it either succeeds and makes the update
or it fails and no update is made.
--*/
{
DWORD status = ERROR_SUCCESS;
CLUSTER_NETWORK_ROLE oldRole = Network->Role;
DWORD dwordNewRole = (DWORD) NewRole;
LPCWSTR networkId = OmObjectId(Network);
DWORD oldPriority = Network->Priority;
DWORD newPriority = oldPriority;
BOOLEAN internalNetworkListChanged = FALSE;
ClRtlLogPrint(LOG_NOISE,
"[NM] Changing role for network %1!ws! to %2!u!\n",
networkId,
NewRole
);
CL_ASSERT(NewRole != oldRole);
CL_ASSERT(
NmpValidateNetworkRoleChange(Network, NewRole) == ERROR_SUCCESS
);
//
// First, make any registry updates since these can be
// aborted by the caller.
//
//
// Update the role property.
//
status = DmLocalSetValue(
Xaction,
NetworkKey,
CLUSREG_NAME_NET_ROLE,
REG_DWORD,
(CONST BYTE *) &dwordNewRole,
sizeof(DWORD)
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of role value failed for network %1!ws!, "
"status %2!u!.\n",
networkId,
status
);
return(status);
}
//
// Update the priority property, if needed.
//
if (oldRole & ClusterNetworkRoleInternalUse) {
if (!(NewRole & ClusterNetworkRoleInternalUse)) {
//
// This network is no longer used for internal communication.
// Invalidate its priority value.
//
newPriority = 0xFFFFFFFF;
internalNetworkListChanged = TRUE;
}
}
else if (NewRole & ClusterNetworkRoleInternalUse) {
//
// This network is now used for internal communication.
// The network's priority is one greater than that of the lowest
// (numerically highest) priority network already in the list.
//
if (IsListEmpty(&NmpInternalNetworkList)) {
newPriority = 1;
}
else {
PNM_NETWORK network = CONTAINING_RECORD(
NmpInternalNetworkList.Blink,
NM_NETWORK,
InternalLinkage
);
CL_ASSERT(network->Priority != 0);
CL_ASSERT(network->Priority != 0xFFFFFFFF);
newPriority = network->Priority + 1;
}
internalNetworkListChanged = TRUE;
}
if (newPriority != oldPriority) {
status = DmLocalSetValue(
Xaction,
NetworkKey,
CLUSREG_NAME_NET_PRIORITY,
REG_DWORD,
(CONST BYTE *) &newPriority,
sizeof(newPriority)
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to set priority value for network %1!ws!, "
"status %2!u!.\n",
networkId,
status
);
return(status);
}
}
//
// Update the network object. Some of the subsequent subroutine calls
// depend on this.
//
Network->Role = NewRole;
Network->Priority = newPriority;
//
// Do other housekeeping based on the change.
//
// Note that the housekeeping work is coded such that none of it needs
// to be reversed if an error occurs.
//
if (NewRole == ClusterNetworkRoleNone) {
PLIST_ENTRY entry;
PNM_INTERFACE netInterface;
//
// Case 1: This network is no longer used for clustering.
//
if (NmpIsNetworkRegistered(Network)) {
//
// Delete the network from the cluster transport.
// This will delete all of its interfaces as well.
//
NmpDeregisterNetwork(Network);
ClRtlLogPrint(LOG_NOISE,
"[NM] No longer hearbeating on network %1!ws!.\n",
networkId
);
}
//
// Invalidate the connectivity data for all interfaces on
// the network.
//
for ( entry = Network->InterfaceList.Flink;
entry != &(Network->InterfaceList);
entry = entry->Flink
)
{
netInterface = CONTAINING_RECORD(
entry,
NM_INTERFACE,
NetworkLinkage
);
NmpSetInterfaceConnectivityData(
Network,
netInterface->NetIndex,
ClusterNetInterfaceUnavailable
);
}
//
// Clean up tracking data.
//
if (oldRole & ClusterNetworkRoleInternalUse) {
RemoveEntryList(&(Network->InternalLinkage));
CL_ASSERT(NmpInternalNetworkCount > 0);
NmpInternalNetworkCount--;
}
if (oldRole & ClusterNetworkRoleClientAccess) {
CL_ASSERT(NmpClientNetworkCount > 0);
NmpClientNetworkCount--;
}
//
// Use the NT5 state logic.
//
if (NmpLeaderNodeId == NmLocalNodeId) {
//
// Schedule an immediate state update.
//
NmpScheduleNetworkStateRecalc(Network);
}
//
// Stop multicast configuration.
//
NmpStopMulticast(Network);
}
else if (oldRole == ClusterNetworkRoleNone) {
//
// Case 2: This network is now used for clustering.
//
if (Network->LocalInterface != NULL) {
//
// Register this network with the cluster transport.
//
// Note that this action will trigger a connectivity report,
// which will in turn trigger a state update under the NT5 logic.
//
status = NmpRegisterNetwork(
Network,
TRUE // Do retry on failure
);
if (status != ERROR_SUCCESS) {
goto error_exit;
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Now heartbeating on network %1!ws!.\n",
networkId
);
}
else if (NmpLeaderNodeId == NmLocalNodeId) {
//
// Schedule a delayed state update in case none of the other
// nodes attached to this network are up right now.
//
NmpStartNetworkStateRecalcTimer(
Network,
NM_NET_STATE_RECALC_TIMEOUT
);
}
//
// Update tracking data.
//
if (NewRole & ClusterNetworkRoleInternalUse) {
InsertTailList(
&NmpInternalNetworkList,
&(Network->InternalLinkage)
);
NmpInternalNetworkCount++;
}
if (NewRole & ClusterNetworkRoleClientAccess) {
NmpClientNetworkCount++;
}
//
// Start multicast.
//
NmpStartMulticast(Network, NmStartMulticastDynamic);
}
else {
//
// Case 3: We are using the network in a different way now.
// Note that the network is already registered with
// the cluster transport and will remain so. As a result,
// there is no need to perform a state update.
//
//
// First, examine the former and new use of the
// network for internal communication, and make any
// necessary updates to the cluster transport.
//
if (oldRole & ClusterNetworkRoleInternalUse) {
if (!(NewRole & ClusterNetworkRoleInternalUse)) {
//
// This network is no longer used for internal communication.
// It is used for client access.
//
CL_ASSERT(NewRole & ClusterNetworkRoleClientAccess);
if (NmpIsNetworkRegistered(Network)) {
//
// Restrict the network to heartbeats only.
//
status = ClusnetSetNetworkRestriction(
NmClusnetHandle,
Network->ShortId,
TRUE, // Network is restricted
0
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to restrict network %1!ws!, "
"status %2!u!.\n",
networkId,
status
);
goto error_exit;
}
}
//
// Update tracking data
//
RemoveEntryList(&(Network->InternalLinkage));
CL_ASSERT(NmpInternalNetworkCount > 0);
NmpInternalNetworkCount--;
}
}
else {
//
// The network is now used for internal communication.
//
CL_ASSERT(NewRole & ClusterNetworkRoleInternalUse);
if (NmpIsNetworkRegistered(Network)) {
//
// Clear the restriction and set the priority.
//
status = ClusnetSetNetworkRestriction(
NmClusnetHandle,
Network->ShortId,
FALSE, // Network is not restricted
newPriority
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to unrestrict network %1!ws!, "
"status %2!u!.\n",
networkId,
status
);
goto error_exit;
}
}
//
// Update the tracking data
//
InsertTailList(
&NmpInternalNetworkList,
&(Network->InternalLinkage)
);
NmpInternalNetworkCount++;
}
//
// Now update the remaining tracking data based on former and
// current use of the network for client access.
//
if (oldRole & ClusterNetworkRoleClientAccess) {
if (!(NewRole & ClusterNetworkRoleClientAccess)) {
//
// This network is no longer used for client access.
//
CL_ASSERT(NmpClientNetworkCount > 0);
NmpClientNetworkCount--;
}
}
else {
//
// This network is now used for client access.
//
CL_ASSERT(NewRole & ClusterNetworkRoleClientAccess);
NmpClientNetworkCount++;
}
}
if (internalNetworkListChanged) {
NmpIssueClusterPropertyChangeEvent();
}
return(ERROR_SUCCESS);
error_exit:
//
// Undo the updates to the network object.
//
Network->Role = oldRole;
Network->Priority = oldPriority;
return(status);
} // NmpSetNetworkRole
VOID
NmpSetNetworkAndInterfaceStates(
IN PNM_NETWORK Network,
IN CLUSTER_NETWORK_STATE NewNetworkState,
IN PNM_STATE_ENTRY InterfaceStateVector,
IN DWORD VectorSize
)
/*++
Notes:
Called with NmpLock held.
Because NM_STATE_ENTRY is an unsigned type, while
CLUSTER_NETINTERFACE_STATE is a signed type, and
ClusterNetInterfaceStateUnknown is defined to be -1, we cannot cast
from NM_STATE_ENTRY to CLUSTER_NETINTERFACE_STATE and preserve the
value of ClusterNetInterfaceStateUnknown.
--*/
{
PLIST_ENTRY entry;
PNM_INTERFACE netInterface;
PNM_NODE node;
DWORD logLevel, logCode;
DWORD ifNetIndex;
LPCWSTR netInterfaceId;
LPCWSTR nodeName;
LPCWSTR networkName = OmObjectName(Network);
LPCWSTR networkId = OmObjectId(Network);
//
// Examine each interface on this network to see if its state
// has changed.
//
for ( entry = Network->InterfaceList.Flink;
entry != &(Network->InterfaceList);
entry = entry->Flink
)
{
netInterface = CONTAINING_RECORD(
entry,
NM_INTERFACE,
NetworkLinkage
);
ifNetIndex = netInterface->NetIndex;
netInterfaceId = OmObjectId(netInterface);
node = netInterface->Node;
nodeName = OmObjectName(node);
if ( (ifNetIndex < VectorSize) &&
(InterfaceStateVector[ifNetIndex] !=
(NM_STATE_ENTRY) netInterface->State
)
)
{
BOOLEAN logEvent = FALSE;
CLUSTER_EVENT eventCode = 0;
NM_STATE_ENTRY newState = InterfaceStateVector[ifNetIndex];
if (newState == (NM_STATE_ENTRY) ClusterNetInterfaceUnavailable) {
//
// Either the node has gone down or the network has been
// disabled.
//
netInterface->State = ClusterNetInterfaceUnavailable;
eventCode = CLUSTER_EVENT_NETINTERFACE_UNAVAILABLE;
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Interface %1!ws! is unavailable (node: %2!ws!, "
"network: %3!ws!).\n",
netInterfaceId,
nodeName,
networkName
);
}
else if (newState == (NM_STATE_ENTRY) ClusterNetInterfaceUp) {
netInterface->State = ClusterNetInterfaceUp;
eventCode = CLUSTER_EVENT_NETINTERFACE_UP;
logCode = NM_EVENT_CLUSTER_NETINTERFACE_UP;
logLevel = LOG_NOISE;
logEvent = TRUE;
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!ws! is up (node: %2!ws!, "
"network: %3!ws!).\n",
netInterfaceId,
nodeName,
networkName
);
}
else if ( newState ==
(NM_STATE_ENTRY) ClusterNetInterfaceUnreachable
)
{
netInterface->State = ClusterNetInterfaceUnreachable;
eventCode = CLUSTER_EVENT_NETINTERFACE_UNREACHABLE;
logCode = NM_EVENT_CLUSTER_NETINTERFACE_UNREACHABLE;
logLevel = LOG_UNUSUAL;
logEvent = TRUE;
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Interface %1!ws! is unreachable (node: %2!ws!, "
"network: %3!ws!).\n",
netInterfaceId,
nodeName,
networkName
);
}
else if (newState == (NM_STATE_ENTRY) ClusterNetInterfaceFailed) {
netInterface->State = ClusterNetInterfaceFailed;
eventCode = CLUSTER_EVENT_NETINTERFACE_FAILED;
logCode = NM_EVENT_CLUSTER_NETINTERFACE_FAILED;
logLevel = LOG_UNUSUAL;
logEvent = TRUE;
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Interface %1!ws! failed (node: %2!ws!, "
"network: %3!ws!).\n",
netInterfaceId,
nodeName,
networkName
);
}
else if ( newState ==
(NM_STATE_ENTRY) ClusterNetInterfaceStateUnknown
)
{
//
// This case can happen if a create update races with a
// state update. This will be the new interface. Just
// ignore it. Another state update will arrive shortly.
//
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] State for interface %1!ws! is unknown "
"(node: %2!ws!, network: %3!ws!).\n",
netInterfaceId,
nodeName,
networkName
);
}
else {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] UpdateInterfaceState: Invalid state %1!u! "
"specified for interface %2!ws!\n",
newState,
netInterfaceId
);
CL_ASSERT(FALSE);
}
if (eventCode != 0) {
ClusterEvent(eventCode, netInterface);
}
if (logEvent && (NmpLeaderNodeId == NmLocalNodeId)) {
CsLogEvent2(
logLevel,
logCode,
nodeName,
networkName
);
}
}
}
if (Network->State != NewNetworkState) {
BOOLEAN logEvent = FALSE;
CLUSTER_EVENT eventCode = 0;
if (NewNetworkState == ClusterNetworkUnavailable) {
Network->State = ClusterNetworkUnavailable;
eventCode = CLUSTER_EVENT_NETWORK_UNAVAILABLE;
}
else if (NewNetworkState == ClusterNetworkUp) {
Network->State = ClusterNetworkUp;
eventCode = CLUSTER_EVENT_NETWORK_UP;
logCode = NM_EVENT_CLUSTER_NETWORK_UP;
logLevel = LOG_NOISE;
logEvent = TRUE;
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Network %1!ws! (%2!ws!) is up.\n",
networkId,
networkName
);
}
else if (NewNetworkState == ClusterNetworkDown) {
Network->State = ClusterNetworkDown;
eventCode = CLUSTER_EVENT_NETWORK_DOWN;
logCode = NM_EVENT_CLUSTER_NETWORK_DOWN;
logLevel = LOG_UNUSUAL;
logEvent = TRUE;
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Network %1!ws! (%2!ws!) is down.\n",
networkId,
networkName
);
}
else if (NewNetworkState == ClusterNetworkPartitioned) {
Network->State = ClusterNetworkPartitioned;
eventCode = CLUSTER_EVENT_NETWORK_PARTITIONED;
logCode = NM_EVENT_CLUSTER_NETWORK_PARTITIONED;
logLevel = LOG_UNUSUAL;
logEvent = TRUE;
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Network %1!ws! (%2!ws!) is partitioned.\n",
networkId,
networkName
);
}
else {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Invalid state %1!u! for network %2!ws!\n",
Network->State,
networkId
);
CL_ASSERT(FALSE);
}
if (eventCode != 0) {
ClusterEvent(eventCode, Network);
}
if (logEvent && (NmpLeaderNodeId == NmLocalNodeId)) {
CsLogEvent1(
logLevel,
logCode,
networkName
);
}
}
return;
} // NmpSetNetworkAndInterfaceStates
/////////////////////////////////////////////////////////////////////////////
//
// Network state management routines
//
/////////////////////////////////////////////////////////////////////////////
VOID
NmpRecomputeNT5NetworkAndInterfaceStates(
VOID
)
{
PNM_NETWORK network;
PLIST_ENTRY entry;
for (entry = NmpNetworkList.Flink;
entry != &NmpNetworkList;
entry = entry->Flink
)
{
network = CONTAINING_RECORD(
entry,
NM_NETWORK,
Linkage
);
NmpStartNetworkStateRecalcTimer(
network,
NM_NET_STATE_RECALC_TIMEOUT_AFTER_REGROUP
);
}
return;
} // NmpRecomputeNT5NetworkAndInterfaceStates
BOOLEAN
NmpComputeNetworkAndInterfaceStates(
IN PNM_NETWORK Network,
IN BOOLEAN IsolateFailure,
OUT CLUSTER_NETWORK_STATE * NewNetworkState
)
/*++
Routine Description:
Computes the state of a network and all of its interfaces based on
connectivity reports from each constituent interface. Attempts
to distinguish between failures of individual interfaces and
failure of an entire network.
Arguments:
Network - A pointer to the network object to be processed.
IsolateFailure - Triggers failure isolation analysis if set to true.
NewNetworkState - A pointer to a variable that, upon return, contains
the new state of the network.
Return Value:
TRUE if either the state of the network or the state of at least one
of its constituent interfaces changed. FALSE otherwise.
Notes:
Called with NmpLock held and the network object referenced.
--*/
{
DWORD numIfUnavailable = 0;
DWORD numIfFailed = 0;
DWORD numIfUnreachable = 0;
DWORD numIfUp = 0;
DWORD numIfReachable = 0;
PNM_CONNECTIVITY_MATRIX matrix = Network->ConnectivityMatrix;
PNM_CONNECTIVITY_MATRIX matrixEntry;
PNM_STATE_WORK_VECTOR workVector = Network->StateWorkVector;
DWORD entryCount =
Network->ConnectivityVector->EntryCount;
DWORD reporter, ifNetIndex;
BOOLEAN stateChanged = FALSE;
LPCWSTR networkId = OmObjectId(Network);
LPCWSTR netInterfaceId;
PLIST_ENTRY entry;
PNM_INTERFACE netInterface;
NM_STATE_ENTRY state;
BOOLEAN selfDeclaredFailure = FALSE;
DWORD interfaceFailureTimeout = 0;
BOOLEAN abortComputation = FALSE;
ClRtlLogPrint(LOG_NOISE,
"[NM] Beginning phase 1 of state computation for network %1!ws!.\n",
networkId
);
//
// Phase 1 - Compute the state of each interface from the data
// in the connectivity matrix.
//
for ( entry = Network->InterfaceList.Flink;
entry != &(Network->InterfaceList);
entry = entry->Flink
)
{
netInterface = CONTAINING_RECORD(
entry,
NM_INTERFACE,
NetworkLinkage
);
netInterfaceId = OmObjectId(netInterface);
ifNetIndex = netInterface->NetIndex;
workVector[ifNetIndex].ReachableCount = 0;
if (NmpIsNetworkEnabledForUse(Network)) {
//
// First, check what the interface thinks its own state is
//
matrixEntry = NM_GET_CONNECTIVITY_MATRIX_ENTRY(
matrix,
ifNetIndex,
ifNetIndex,
entryCount
);
if ( *matrixEntry ==
(NM_STATE_ENTRY) ClusterNetInterfaceStateUnknown
)
{
//
// This case should never happen.
//
// An existing interface cannot think its own state is
// unknown. The reflexive entry is always initialized to
// Unavailable whenever an interface is created.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] No data for interface %1!u! (%2!ws!) on network "
"%3!ws!\n",
ifNetIndex,
netInterfaceId,
networkId
);
CL_ASSERT(
*matrixEntry !=
(NM_STATE_ENTRY) ClusterNetInterfaceStateUnknown
);
state = ClusterNetInterfaceUnavailable;
numIfUnavailable++;
}
else if ( *matrixEntry ==
(NM_STATE_ENTRY) ClusterNetInterfaceUnavailable
)
{
if (NM_NODE_UP(netInterface->Node)) {
//
// The node is up, but its connectivity report has
// not been received yet. This case may happen while a
// node is joining. It can also happen if this node has
// just become the new leader.
//
// Abort the state computation.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Data is not yet valid for interface %1!u! "
"(%2!ws!) on network %3!ws!.\n",
ifNetIndex,
netInterfaceId,
networkId
);
abortComputation = TRUE;
break;
}
else {
//
// The owning node is down or joining.
// The interface is in the unavailable state.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Node is down for interface %1!u! (%2!ws!) on "
"network %3!ws!\n",
ifNetIndex,
netInterfaceId,
networkId
);
state = ClusterNetInterfaceUnavailable;
numIfUnavailable++;
}
}
else if ( *matrixEntry ==
(NM_STATE_ENTRY) ClusterNetInterfaceFailed
)
{
//
// The node declared its own interface as failed.
// The interface is in the failed state.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! (%2!ws!) has failed on network "
"%3!ws!\n",
ifNetIndex,
netInterfaceId,
networkId
);
state = ClusterNetInterfaceFailed;
numIfFailed++;
if (netInterface->State == ClusterNetInterfaceUp) {
selfDeclaredFailure = TRUE;
}
}
else {
CL_ASSERT(
*matrixEntry == (NM_STATE_ENTRY) ClusterNetInterfaceUp
);
//
// The owning node thinks its interface is Up.
//
// If there are no other operational interfaces on the
// network, then the interface is in the Up state.
//
// If there are other operational interfaces on the
// network, but all of their reports are not yet valid,
// then we defer calculating a new state for the interface.
//
// If there are other operational interfaces on the network,
// and all of their reports are valid, then if at least one
// of the operational interfaces reports that the interface
// is unreachable, then then the interface is in the
// Unreachable state. If all of the other operational
// interfaces report that the interface is reachable, then
// the interface is in the Up state.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Examining connectivity data for interface %1!u! "
"(%2!ws!) on network %3!ws!.\n",
ifNetIndex,
netInterfaceId,
networkId
);
//
// Assume that the interface is Up until proven otherwise.
//
state = ClusterNetInterfaceUp;
//
// Examine the reports from other interfaces -
// i.e. scan the matrix column - to see if any node with
// an operational interface reports this interface to
// be unreachable.
//
for (reporter=0; reporter<entryCount; reporter++) {
if (reporter == ifNetIndex) {
continue;
}
//
// First, see if the reporting interface is operational
// by checking what the repoerter thinks of its own
// interface.
//
matrixEntry = NM_GET_CONNECTIVITY_MATRIX_ENTRY(
matrix,
reporter,
reporter,
entryCount
);
if (*matrixEntry == ClusterNetInterfaceUp) {
PNM_CONNECTIVITY_MATRIX matrixEntry2;
//
// Both the reporter and the reportee believe that
// their respective interfaces are operational.
// Check if they agree on the state of their
// connectivity before going any further.
// ClusNet guarantees that eventually they will
// agree.
//
matrixEntry = NM_GET_CONNECTIVITY_MATRIX_ENTRY(
matrix,
reporter,
ifNetIndex,
entryCount
);
matrixEntry2 = NM_GET_CONNECTIVITY_MATRIX_ENTRY(
matrix,
ifNetIndex,
reporter,
entryCount
);
if (*matrixEntry == *matrixEntry2) {
//
// The two interfaces agree on the state of
// their connectivity. Check what they agree on.
//
if (*matrixEntry == ClusterNetInterfaceUp) {
//
// The interface is reported to be up.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! reports interface "
"%2!u! is up on network %3!ws!\n",
reporter,
ifNetIndex,
networkId
);
workVector[ifNetIndex].ReachableCount++;
}
else if ( *matrixEntry ==
ClusterNetInterfaceUnreachable
)
{
//
// The interface is reported to be
// unreachable.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! reports interface "
"%2!u! is unreachable on network %3!ws!\n",
reporter,
ifNetIndex,
networkId
);
state = ClusterNetInterfaceUnreachable;
//
// If this interface is already in failed state do fault isolation immediately.
//
if(workVector[ifNetIndex].State == ClusterNetInterfaceFailed)
IsolateFailure = TRUE;
}
else {
CL_ASSERT(
*matrixEntry != ClusterNetInterfaceFailed
);
//
// The interface report is not valid yet.
// Abort the computation.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Report from interface %1!u! for "
"interface %2!u! is not valid yet on "
"network %3!ws!.\n",
reporter,
ifNetIndex,
networkId
);
abortComputation = TRUE;
break;
}
}
else {
//
// The two interfaces do not yet agree on
// their connectivity. Abort the computation.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! and interface %2!u! do "
"not agree on their connectivity on network "
"%3!ws!\n",
reporter,
ifNetIndex,
networkId
);
abortComputation = TRUE;
break;
}
}
else {
//
// The reporter does not think its own interface is
// operational.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] The report from interface %1!u! is not "
"valid on network %2!ws!.\n",
reporter,
networkId
);
}
} // end of connectivity matrix scan loop
if (abortComputation) {
//
// Abort Phase 1 computation.
//
break;
}
if (state == ClusterNetInterfaceUp) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! (%2!ws!) is up on network "
"%3!ws!.\n",
ifNetIndex,
netInterfaceId,
networkId
);
numIfUp++;
}
else {
CL_ASSERT(state == ClusterNetInterfaceUnreachable);
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! (%2!ws!) is unreachable on "
"network %3!ws!\n",
ifNetIndex,
netInterfaceId,
networkId
);
numIfUnreachable++;
}
}
}
else {
//
// The network is disabled. It is in the Unavailable state.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! (%2!ws!) is unavailable because "
"network %3!ws! is disabled. \n",
ifNetIndex,
netInterfaceId,
networkId
);
state = ClusterNetInterfaceUnavailable;
numIfUnavailable++;
}
workVector[ifNetIndex].State = state;
//
// Keep track of how many interfaces on the network are
// reachable by at least one peer.
//
if ( (state == ClusterNetInterfaceUp) ||
(workVector[ifNetIndex].ReachableCount > 0)
) {
numIfReachable++;
}
if (netInterface->State != state) {
stateChanged = TRUE;
}
} // end of phase one interface loop
if (!abortComputation && !IsolateFailure && selfDeclaredFailure) {
interfaceFailureTimeout =
NmpGetNetworkInterfaceFailureTimerValue(networkId);
if (interfaceFailureTimeout > 0) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Delaying state computation for network %1!ws! "
"for %2!u! ms to damp self-declared failure event.\n",
networkId, interfaceFailureTimeout
);
NmpStartNetworkFailureIsolationTimer(
Network,
interfaceFailureTimeout
);
abortComputation = TRUE;
}
}
if (abortComputation) {
if (interfaceFailureTimeout == 0) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Aborting state computation for network %1!ws! "
" until connectivity data is valid.\n",
networkId
);
}
//
// Undo any changes we made to the work vector.
//
for ( entry = Network->InterfaceList.Flink;
entry != &(Network->InterfaceList);
entry = entry->Flink
)
{
netInterface = CONTAINING_RECORD(
entry,
NM_INTERFACE,
NetworkLinkage
);
ifNetIndex = netInterface->NetIndex;
workVector[ifNetIndex].State = (NM_STATE_ENTRY)
netInterface->State;
}
*NewNetworkState = Network->State;
return(FALSE);
}
//
// Phase 2
//
// Try to determine the scope of any failures and recompute the
// interface states. There are two cases in which we can isolate
// failures.
//
// Case 1: Three or more interfaces are operational. At least two
// interfaces can communicate with a peer. One or more
// interfaces cannot communicate with any peer.
// Those that cannot communicate at all have failed.
//
// Case 2: Exactly two interfaces are operational and they cannot
// communicate with one another. If one interface can
// communicate with an external host while the other
// cannot communicate with any external host, then the one
// that cannot communicate has failed.
//
// In any other situation, we do nothing.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Completed phase 1 of state computation for network "
"%1!ws!.\n",
networkId
);
ClRtlLogPrint(LOG_NOISE,
"[NM] Unavailable=%1!u!, Failed = %2!u!, Unreachable=%3!u!, "
"Reachable=%4!u!, Up=%5!u! on network %6!ws! \n",
numIfUnavailable,
numIfFailed,
numIfUnreachable,
numIfReachable,
numIfUp,
networkId
);
if (numIfUnreachable > 0) {
//
// Some interfaces are unreachable.
//
if ( ((numIfUp + numIfUnreachable) >= 3) && (numIfReachable >= 2) ) {
if (IsolateFailure) {
//
// Case 1.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Trying to determine scope of connectivity failure "
"for >3 interfaces on network %1!ws!.\n",
networkId
);
//
// Any operational interface that cannot communicate with at
// least one other operational interface has failed.
//
for ( entry = Network->InterfaceList.Flink;
entry != &(Network->InterfaceList);
entry = entry->Flink
)
{
netInterface = CONTAINING_RECORD(
entry,
NM_INTERFACE,
NetworkLinkage
);
ifNetIndex = netInterface->NetIndex;
netInterfaceId = OmObjectId(netInterface);
if ( ( workVector[ifNetIndex].State ==
ClusterNetInterfaceUnreachable
)
&&
(workVector[ifNetIndex].ReachableCount == 0)
)
{
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! (%2!ws!) has failed on "
"network %3!ws!\n",
ifNetIndex,
netInterfaceId,
networkId
);
workVector[ifNetIndex].State =
ClusterNetInterfaceFailed;
numIfUnreachable--;
numIfFailed++;
}
}
//
// If any interface, whose state is still unreachable, can see
// all other reachable interfaces, change its state to up.
//
for ( entry = Network->InterfaceList.Flink;
entry != &(Network->InterfaceList);
entry = entry->Flink
)
{
netInterface = CONTAINING_RECORD(
entry,
NM_INTERFACE,
NetworkLinkage
);
ifNetIndex = netInterface->NetIndex;
if ( ( workVector[ifNetIndex].State ==
ClusterNetInterfaceUnreachable
)
&&
( workVector[ifNetIndex].ReachableCount ==
(numIfUp + numIfUnreachable - 1)
)
)
{
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! (%2!ws!) is up on network "
"%3!ws!\n",
ifNetIndex,
netInterfaceId,
networkId
);
workVector[ifNetIndex].State = ClusterNetInterfaceUp;
numIfUnreachable--;
numIfUp++;
}
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Connectivity failure scope determination complete "
"for network %1!ws!.\n",
networkId
);
}
else {
//
// Schedule a failure isolation calculation to run later.
// Declaring a failure can affect cluster resources, so we
// don't want to do it unless we are sure. Delaying for a
// while reduces the risk of a false positive.
//
NmpStartNetworkFailureIsolationTimer(Network,
NM_NET_STATE_FAILURE_ISOLATION_TIMEOUT);
}
}
else if ((numIfUnreachable == 2) && (numIfUp == 0)) {
if (IsolateFailure) {
//
// Case 2.
//
PNM_INTERFACE interface1 = NULL;
BOOLEAN interface1HasConnectivity;
LPCWSTR interfaceId1;
PNM_INTERFACE interface2 = NULL;
BOOLEAN interface2HasConnectivity;
LPCWSTR interfaceId2;
DWORD status;
ClRtlLogPrint(LOG_NOISE,
"[NM] Trying to determine scope of connectivity failure "
"for 2 interfaces on network %1!ws!.\n",
networkId
);
for ( entry = Network->InterfaceList.Flink;
entry != &(Network->InterfaceList);
entry = entry->Flink
)
{
netInterface = CONTAINING_RECORD(
entry,
NM_INTERFACE,
NetworkLinkage
);
ifNetIndex = netInterface->NetIndex;
if ( workVector[ifNetIndex].State ==
ClusterNetInterfaceUnreachable
)
{
if (interface1 == NULL) {
interface1 = netInterface;
interfaceId1 = OmObjectId(interface1);
ClRtlLogPrint(LOG_NOISE,
"[NM] Unreachable interface 1 = %1!ws! on "
"network %2!ws!\n",
interfaceId1,
networkId
);
}
else {
interface2 = netInterface;
interfaceId2 = OmObjectId(interface2);
ClRtlLogPrint(LOG_NOISE,
"[NM] Unreachable interface 2 = %1!ws! on "
"network %2!ws!\n",
interfaceId2,
networkId
);
break;
}
}
}
//
// NmpTestInterfaceConnectivity releases and reacquires
// the NmpLock. We must reference the interface objects
// to ensure that they are still valid upon return from
// that routine.
//
OmReferenceObject(interface1);
OmReferenceObject(interface2);
status = NmpTestInterfaceConnectivity(
interface1,
&interface1HasConnectivity,
interface2,
&interface2HasConnectivity
);
if (status == ERROR_SUCCESS) {
if ( interface1HasConnectivity &&
!interface2HasConnectivity
)
{
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! (%2!ws!) has Failed on "
"network %3!ws!\n",
interface2->NetIndex,
interfaceId2,
networkId
);
workVector[interface2->NetIndex].State =
ClusterNetInterfaceFailed;
numIfUnreachable--;
numIfFailed++;
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! (%2!ws!) is Up on network "
"%3!ws!\n",
interface1->NetIndex,
interfaceId1,
networkId
);
workVector[interface1->NetIndex].State =
ClusterNetInterfaceUp;
numIfUnreachable--;
numIfUp++;
}
else if ( !interface1HasConnectivity &&
interface2HasConnectivity
)
{
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! (%2!ws!) has Failed on "
"network %3!ws!\n",
interface1->NetIndex,
interfaceId1,
networkId
);
workVector[interface1->NetIndex].State =
ClusterNetInterfaceFailed;
numIfUnreachable--;
numIfFailed++;
ClRtlLogPrint(LOG_NOISE,
"[NM] Interface %1!u! (%2!ws!) is Up on network "
"%3!ws!\n",
interface2->NetIndex,
interfaceId2,
networkId
);
workVector[interface2->NetIndex].State =
ClusterNetInterfaceUp;
numIfUnreachable--;
numIfUp++;
}
else {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Network %1!ws! state is indeterminate, Scheduling"
" Failure Isolation poll\n",
networkId
);
NmpStartNetworkFailureIsolationTimer(Network,
NmpGetIsolationPollTimerValue());
}
}
else {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Error in Interface Connectivity test for Network %1!ws!"
", Scheduling Failure Isolation poll\n",
networkId
);
NmpStartNetworkFailureIsolationTimer(Network,
NmpGetIsolationPollTimerValue());
}
OmDereferenceObject(interface1);
OmDereferenceObject(interface2);
ClRtlLogPrint(LOG_NOISE,
"[NM] Connectivity failure scope determination complete "
"for network %1!ws!.\n",
networkId
);
}
else {
//
// Schedule a failure isolation calculation to run later.
// Declaring a failure can affect cluster resources, so we
// don't want to do it unless we are sure. Delaying for a
// while reduces the risk of a false positive.
//
NmpStartNetworkFailureIsolationTimer(Network,
NM_NET_STATE_FAILURE_ISOLATION_TIMEOUT);
}
}
else {
ClRtlLogPrint(LOG_NOISE,
"[NM] Cannot determine scope of connectivity failure on "
"network %1!ws!.\n",
networkId
);
}
}
else {
//
// No unreachable interfaces. Disable the failure isolation timer,
// if it is running.
//
Network->FailureIsolationTimer = 0;
Network->Flags &= ~NM_FLAG_NET_ISOLATE_FAILURE;
}
//
// Phase 3 - Compute the new network state.
//
if (numIfUnavailable == Network->InterfaceCount) {
//
// All interfaces are unavailable.
//
*NewNetworkState = ClusterNetworkUnavailable;
}
else if (numIfUnreachable > 0) {
//
// Some operational interfaces have experienced
// a loss of connectivity, but the fault could not be
// isolated to them.
//
if (numIfReachable > 0) {
CL_ASSERT(numIfReachable >= 2);
//
// At least two interfaces can still communicate
// with each other, so the network is not completely down.
//
*NewNetworkState = ClusterNetworkPartitioned;
}
else {
CL_ASSERT(numIfUp == 0);
//
// None of the operational interfaces can communicate
//
*NewNetworkState = ClusterNetworkDown;
}
}
else if (numIfUp > 0) {
//
// Some interfaces are Up, all others are Failed or Unavailable
//
*NewNetworkState = ClusterNetworkUp;
}
else {
//
// Some interfaces are Unavailable, rest are Failed.
//
*NewNetworkState = ClusterNetworkDown;
}
if (Network->State != *NewNetworkState) {
stateChanged = TRUE;
ClRtlLogPrint(LOG_NOISE,
"[NM] Network %1!ws! is now in state %2!u!\n",
networkId,
*NewNetworkState
);
}
return(stateChanged);
} // NmpComputeNetworkAndInterfaceStates
DWORD
NmpGetIsolationPollTimerValue(
VOID
)
/*--
* Reads the IsolationPollTimerValue Parameter from the registry if it's there
* else returns default value.
*/
{
DWORD value;
DWORD type;
DWORD len = sizeof(value);
DWORD status;
// Release NM Lock to avoid deadlock with DM lock
NmpReleaseLock();
status = DmQueryValue(
DmClusterParametersKey,
L"IsolationPollTimerValue",
&type,
(LPBYTE)&value,
&len
);
NmpAcquireLock();
if((status != ERROR_SUCCESS) || (type != REG_DWORD) ||
(value < 10) || (value > 600000)) {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to read IsolationPollTimerValue or value out of range,"
"status %1!u! using default %2!u! ms\n",
status,
NM_NET_STATE_FAILURE_ISOLATION_POLL
);
return NM_NET_STATE_FAILURE_ISOLATION_POLL;
}
else {
ClRtlLogPrint(LOG_NOISE,
"[NM] IsolationPollTimerValue = %1!u!\n",
value
);
return value;
}
}
DWORD
NmpGetNetworkInterfaceFailureTimerValue(
IN LPCWSTR NetworkId
)
/*++
Routine Description:
Reads InterfaceFailure timer value from registry.
If a value is located in the network key, it is used.
Otherwise the cluster parameters key is checked.
If no value is present, returns default.
Arguments:
NetworkId - id of network whose timer value to determine
Return value:
InterfaceFailure timer value
Notes:
Called with NM lock held (from NmpComputeNetworkAndInterfaceStates).
This routine queries the cluster database; hence, it drops the
NM lock. Since NmpComputeNetworkAndInterfaceStates is always called
in the context of the NmpWorkerThread, the Network is always
referenced during execution of this routine.
--*/
{
HDMKEY networkKey, paramKey;
DWORD status;
DWORD type;
DWORD value = NM_NET_STATE_INTERFACE_FAILURE_TIMEOUT;
DWORD len = sizeof(value);
BOOLEAN found = FALSE;
//
// To avoid deadlock, the DM lock must be acquired before the
// NM lock. Hence, release the NM lock prior to querying the
// cluster database.
//
NmpReleaseLock();
//
// First check the network key
//
networkKey = DmOpenKey(DmNetworksKey, NetworkId, KEY_READ);
if (networkKey == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to open key for network %1!ws!, "
"status %1!u!\n",
NetworkId, status
);
}
else {
paramKey = DmOpenKey(networkKey, L"Parameters", KEY_READ);
if (paramKey == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_NOISE,
"[NM] Failed to find Parameters key "
"for network %1!ws!, status %2!u!. Checking "
"cluster parameters ...\n",
NetworkId, status
);
}
else {
status = DmQueryValue(
paramKey,
L"InterfaceFailureTimeout",
&type,
(LPBYTE) &value,
&len
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Failed to read InterfaceFailureTimeout "
"for network %1!ws!, status %2!u!. Checking "
"cluster parameters ...\n",
NetworkId, status
);
}
else if (type != REG_DWORD) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Unexpected type (%1!u!) for network "
"%2!ws! InterfaceFailureTimeout, status %3!u!. "
"Checking cluster parameters ...\n",
type, NetworkId, status
);
}
else {
found = TRUE;
}
DmCloseKey(paramKey);
}
DmCloseKey(networkKey);
}
//
// If no value was found under the network key, check the
// cluster parameters key.
//
if (!found) {
paramKey = DmOpenKey(DmClusterParametersKey, L"Parameters", KEY_READ);
if (paramKey == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_NOISE,
"[NM] Failed to find cluster Parameters key, status %1!u!.\n",
status
);
}
else {
status = DmQueryValue(
paramKey,
L"InterfaceFailureTimeout",
&type,
(LPBYTE) &value,
&len
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Failed to read cluster "
"InterfaceFailureTimeout, status %1!u!. "
"Using default value ...\n",
status
);
value = NM_NET_STATE_INTERFACE_FAILURE_TIMEOUT;
}
else if (type != REG_DWORD) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Unexpected type (%1!u!) for cluster "
"InterfaceFailureTimeout, status %2!u!. "
"Using default value ...\n",
type, status
);
value = NM_NET_STATE_INTERFACE_FAILURE_TIMEOUT;
}
DmCloseKey(paramKey);
}
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Using InterfaceFailureTimeout of %1!u! ms "
"for network %2!ws!.\n",
value, NetworkId
);
//
// Reacquire NM lock.
//
NmpAcquireLock();
return(value);
}
VOID
NmpConnectivityReportWorker(
IN PCLRTL_WORK_ITEM WorkItem,
IN DWORD Status,
IN DWORD BytesTransferred,
IN ULONG_PTR IoContext
)
/*++
Routine Description:
Worker routine for deferred operations on network objects.
Invoked to process items placed in the cluster delayed work queue.
Arguments:
WorkItem - Ignored.
Status - Ignored.
BytesTransferred - Ignored.
IoContext - Ignored.
Return Value:
None.
Notes:
This routine is run in an asynchronous worker thread.
The NmpActiveThreadCount was incremented when the thread was
scheduled.
--*/
{
BOOLEAN rescheduled = FALSE;
NmpAcquireLock();
ClRtlLogPrint(LOG_NOISE,
"[NM] Connectivity report worker thread running.\n"
);
CL_ASSERT(NmpIsConnectivityReportWorkerRunning == TRUE);
CL_ASSERT(NmpNeedConnectivityReport == TRUE);
if (NmpState >= NmStateOnlinePending) {
PNM_NETWORK network;
LPCWSTR networkId;
PLIST_ENTRY entry;
DWORD status;
while(TRUE) {
NmpNeedConnectivityReport = FALSE;
for (entry = NmpNetworkList.Flink;
entry != &NmpNetworkList;
entry = entry->Flink
)
{
network = CONTAINING_RECORD(entry, NM_NETWORK, Linkage);
if (!NM_DELETE_PENDING(network)) {
networkId = OmObjectId(network);
//
// Deliver an InterfaceFailed event for the local interface
// if needed.
//
if (network->Flags & NM_FLAG_NET_REPORT_LOCAL_IF_FAILED) {
network->Flags &= ~NM_FLAG_NET_REPORT_LOCAL_IF_FAILED;
if (NmpIsNetworkRegistered(network)) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Processing local interface failed "
" event for network %1!ws!.\n",
networkId
);
NmpProcessLocalInterfaceStateEvent(
network->LocalInterface,
ClusterNetInterfaceFailed
);
}
}
//
// Deliver an InterfaceUp event for the local interface
// if needed.
//
if (network->Flags & NM_FLAG_NET_REPORT_LOCAL_IF_UP) {
network->Flags &= ~NM_FLAG_NET_REPORT_LOCAL_IF_UP;
if (NmpIsNetworkRegistered(network)) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Processing local interface up event "
"for network %1!ws!.\n",
networkId
);
NmpProcessLocalInterfaceStateEvent(
network->LocalInterface,
ClusterNetInterfaceUp
);
}
}
//
// Send a connectivity report if needed.
//
if (network->Flags & NM_FLAG_NET_REPORT_CONNECTIVITY) {
CL_NODE_ID leaderNodeId = NmpLeaderNodeId;
network->Flags &= ~NM_FLAG_NET_REPORT_CONNECTIVITY;
//
// Report our connectivity to the leader.
//
status = NmpReportNetworkConnectivity(network);
if (status == ERROR_SUCCESS) {
//
// Clear the report retry count.
//
network->ConnectivityReportRetryCount = 0;
}
else {
if (NmpLeaderNodeId == leaderNodeId) {
if (network->ConnectivityReportRetryCount++ <
NM_CONNECTIVITY_REPORT_RETRY_LIMIT
)
{
//
// Try again in 500ms.
//
network->ConnectivityReportTimer = 500;
}
else {
//
// We have failed to communicate with
// the leader for too long. Mutiny.
//
NmpAdviseNodeFailure(
NmpIdArray[NmpLeaderNodeId],
status
);
network->ConnectivityReportRetryCount = 0;
}
}
else {
//
// New leader, clear the retry count. We
// already scheduled another connectivity
// report in the node down handling.
//
network->ConnectivityReportRetryCount = 0;
}
}
}
}
} // end network for loop
if (NmpNeedConnectivityReport == FALSE) {
//
// No more work to do - break out of loop.
//
break;
}
//
// More work to do. Resubmit the work item. We do this instead
// of looping so we don't hog the worker thread. If
// rescheduling fails, we will loop again in this thread.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] More connectivity reports to send. Rescheduling "
"worker thread.\n"
);
status = NmpScheduleConnectivityReportWorker();
if (status == ERROR_SUCCESS) {
rescheduled = TRUE;
break;
}
} // end while(TRUE)
}
if (!rescheduled) {
NmpIsConnectivityReportWorkerRunning = FALSE;
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Connectivity report worker thread finished.\n"
);
//
// Decrement active thread reference count.
//
NmpLockedLeaveApi();
NmpReleaseLock();
return;
} // NmpConnectivityReportWorker
VOID
NmpNetworkWorker(
IN PCLRTL_WORK_ITEM WorkItem,
IN DWORD Status,
IN DWORD BytesTransferred,
IN ULONG_PTR IoContext
)
/*++
Routine Description:
Worker routine for deferred operations on network objects.
Invoked to process items placed in the cluster delayed work queue.
Arguments:
WorkItem - A pointer to a work item structure that identifies the
network for which to perform work.
Status - Ignored.
BytesTransferred - Ignored.
IoContext - Ignored.
Return Value:
None.
Notes:
This routine is run in an asynchronous worker thread.
The NmpActiveThreadCount was incremented when the thread was
scheduled. The network object was also referenced.
--*/
{
PNM_NETWORK network = (PNM_NETWORK) WorkItem->Context;
LPCWSTR networkId = OmObjectId(network);
BOOLEAN rescheduled = FALSE;
NmpAcquireLock();
ClRtlLogPrint(LOG_NOISE,
"[NM] Worker thread processing network %1!ws!.\n",
networkId
);
if ((NmpState >= NmStateOnlinePending) && !NM_DELETE_PENDING(network)) {
DWORD status;
while(TRUE) {
CL_ASSERT(network->Flags & NM_FLAG_NET_WORKER_RUNNING);
//
// Register the network if needed.
//
if (network->Flags & NM_FLAG_NET_NEED_TO_REGISTER) {
network->Flags &= ~NM_FLAG_NET_NEED_TO_REGISTER;
if (network->LocalInterface != NULL) {
(VOID) NmpRegisterNetwork(
network,
TRUE // Do retry on failure
);
}
}
//
// Isolate a network failure if needed.
//
if (network->Flags & NM_FLAG_NET_ISOLATE_FAILURE) {
BOOLEAN stateChanged;
CLUSTER_NETWORK_STATE newNetworkState;
network->Flags &= ~NM_FLAG_NET_ISOLATE_FAILURE;
//
// Turn off the state recalc timer and flag, since we will
// do a recalc here.
//
network->Flags &= ~NM_FLAG_NET_RECALC_STATE;
network->StateRecalcTimer = 0;
CL_ASSERT(NmpLeaderNodeId == NmLocalNodeId);
//
// Recompute the interface and network states
// with failure isolation enabled.
//
stateChanged = NmpComputeNetworkAndInterfaceStates(
network,
TRUE,
&newNetworkState
);
if (stateChanged) {
//
// Broadcast the new network and interface states to
// all nodes
//
status = NmpGlobalSetNetworkAndInterfaceStates(
network,
newNetworkState
);
if (status != ERROR_SUCCESS) {
//
// Try again in 1 second.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Global update failed for network %1!ws!, "
"status %2!u! - restarting failure isolation "
"timer.\n",
networkId,
status
);
network->FailureIsolationTimer = 1000;
}
}
}
//
// Recalculate the network and interface states if needed.
//
if (network->Flags & NM_FLAG_NET_RECALC_STATE) {
BOOLEAN stateChanged;
CLUSTER_NETWORK_STATE newNetworkState;
network->Flags &= ~NM_FLAG_NET_RECALC_STATE;
CL_ASSERT(NmpLeaderNodeId == NmLocalNodeId);
//
// Recompute the interface and network states
// with failure isolation disabled. It will be
// enabled if needed.
//
stateChanged = NmpComputeNetworkAndInterfaceStates(
network,
FALSE,
&newNetworkState
);
if (stateChanged) {
//
// Broadcast the new network and interface states to
// all nodes
//
status = NmpGlobalSetNetworkAndInterfaceStates(
network,
newNetworkState
);
if (status != ERROR_SUCCESS) {
//
// Try again in 500ms.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] NetworkStateUpdateWorker failed issue "
"global update for network %1!ws!, status "
"%2!u! - restarting update timer.\n",
networkId,
status
);
network->StateRecalcTimer = 500;
}
}
}
//
// Refresh the network multicast configurtion if needed.
//
if (network->Flags & NM_FLAG_NET_REFRESH_MCAST) {
network->Flags &= ~NM_FLAG_NET_REFRESH_MCAST;
status = NmpRefreshMulticastConfiguration(network);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Failed to refresh multicast "
"configuration for network %1!ws!, "
"status %2!u!.\n",
networkId, status
);
}
}
if (!(network->Flags & NM_NET_WORK_FLAGS)) {
//
// No more work to do - break out of loop.
//
break;
}
//
// More work to do. Resubmit the work item. We do this instead
// of looping so we don't hog the worker thread. If
// rescheduling fails, we will loop again in this thread.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] More work to do for network %1!ws!. Rescheduling "
"worker thread.\n",
networkId
);
status = NmpScheduleNetworkWorker(network);
if (status == ERROR_SUCCESS) {
rescheduled = TRUE;
break;
}
}
}
else {
network->Flags &= ~NM_NET_WORK_FLAGS;
}
if (!rescheduled) {
network->Flags &= ~NM_FLAG_NET_WORKER_RUNNING;
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Worker thread finished processing network %1!ws!.\n",
networkId
);
NmpLockedLeaveApi();
NmpReleaseLock();
OmDereferenceObject(network);
return;
} // NmpNetworkWorker
VOID
NmpNetworkTimerTick(
IN DWORD MsTickInterval
)
/*++
Routine Description:
Called by NM periodic timer to decrement network timers.
Arguments:
MsTickInterval - The number of milliseconds that have passed since
the last timer tick.
Return Value:
None.
Notes:
Called with NmpLock held.
--*/
{
if (NmpLockedEnterApi(NmStateOnlinePending)) {
PLIST_ENTRY entry;
PNM_NETWORK network;
//
// Walk thru the list of networks and decrement any running timers.
//
for ( entry = NmpNetworkList.Flink;
entry != &NmpNetworkList;
entry = entry->Flink
)
{
network = CONTAINING_RECORD(entry, NM_NETWORK, Linkage);
//
// Network registration retry timer.
//
if (network->RegistrationRetryTimer != 0) {
if (network->RegistrationRetryTimer > MsTickInterval) {
network->RegistrationRetryTimer -= MsTickInterval;
}
else {
//
// The timer has expired. Schedule a worker thread
// to register the network.
//
LPCWSTR networkId = OmObjectId(network);
LPCWSTR networkName = OmObjectName(network);
ClRtlLogPrint(LOG_NOISE,
"[NM] Registration retry timer expired for "
"network %1!ws! (%2!ws!).\n",
networkId,
networkName
);
NmpScheduleNetworkRegistration(network);
}
}
//
// Connectivity report generation timer.
//
if (network->ConnectivityReportTimer != 0) {
if (network->ConnectivityReportTimer > MsTickInterval) {
network->ConnectivityReportTimer -= MsTickInterval;
}
else {
//
// The timer has expired. Schedule a worker thread
// to deliver a connectivity report.
//
LPCWSTR networkId = OmObjectId(network);
LPCWSTR networkName = OmObjectName(network);
ClRtlLogPrint(LOG_NOISE,
"[NM] Connectivity report timer expired for "
"network %1!ws! (%2!ws!).\n",
networkId,
networkName
);
NmpScheduleNetworkConnectivityReport(network);
}
}
//
// Network state recalculation timer.
//
if (network->StateRecalcTimer != 0) {
if (network->StateRecalcTimer > MsTickInterval) {
network->StateRecalcTimer -= MsTickInterval;
}
else {
//
// The timer has expired. Schedule a worker thread
// to recalculate the state of the network.
//
LPCWSTR networkId = OmObjectId(network);
LPCWSTR networkName = OmObjectName(network);
ClRtlLogPrint(LOG_NOISE,
"[NM] State recalculation timer expired for "
"network %1!ws! (%2!ws!).\n",
networkId,
networkName
);
NmpScheduleNetworkStateRecalc(network);
}
}
//
// Network multicast address renewal timer.
//
if (network->McastAddressRenewTimer != 0) {
if (network->McastAddressRenewTimer > MsTickInterval) {
network->McastAddressRenewTimer -= MsTickInterval;
}
else {
//
// The timer has expired. Schedule a worker thread
// to renew the network's multicast address.
//
LPCWSTR networkId = OmObjectId(network);
LPCWSTR networkName = OmObjectName(network);
ClRtlLogPrint(LOG_NOISE,
"[NM] Multicast address lease renewal timer "
"expired for network %1!ws! (%2!ws!).\n",
networkId,
networkName
);
NmpScheduleMulticastAddressRenewal(network);
}
}
//
// Network multicast address release timer.
//
if (network->McastAddressReleaseRetryTimer != 0) {
if (network->McastAddressReleaseRetryTimer > MsTickInterval) {
network->McastAddressReleaseRetryTimer -= MsTickInterval;
}
else {
//
// The timer has expired. Schedule a worker thread
// to release the network's multicast address.
//
LPCWSTR networkId = OmObjectId(network);
LPCWSTR networkName = OmObjectName(network);
ClRtlLogPrint(LOG_NOISE,
"[NM] Multicast address release timer "
"expired for network %1!ws! (%2!ws!).\n",
networkId,
networkName
);
NmpScheduleMulticastAddressRelease(network);
}
}
//
// Network multicast reconfiguration timer.
//
if (network->McastAddressReconfigureRetryTimer != 0) {
if (network->McastAddressReconfigureRetryTimer > MsTickInterval) {
network->McastAddressReconfigureRetryTimer -= MsTickInterval;
}
else {
//
// The timer has expired. Schedule a worker thread
// to recreate the network's multicast configuration.
//
LPCWSTR networkId = OmObjectId(network);
LPCWSTR networkName = OmObjectName(network);
ClRtlLogPrint(LOG_NOISE,
"[NM] Multicast reconfiguration timer "
"expired for network %1!ws! (%2!ws!).\n",
networkId,
networkName
);
NmpScheduleMulticastReconfiguration(network);
}
}
//
// Network multicast configuration refresh timer.
//
if (network->McastAddressRefreshRetryTimer != 0) {
if (network->McastAddressRefreshRetryTimer > MsTickInterval) {
network->McastAddressRefreshRetryTimer -= MsTickInterval;
}
else {
//
// The timer has expired. Schedule a worker thread
// to refresh the network's multicast configuration.
//
LPCWSTR networkId = OmObjectId(network);
LPCWSTR networkName = OmObjectName(network);
ClRtlLogPrint(LOG_NOISE,
"[NM] Multicast address refresh timer "
"expired for network %1!ws! (%2!ws!).\n",
networkId,
networkName
);
NmpScheduleMulticastRefresh(network);
}
}
//
// Network failure isolation timer.
//
if (network->FailureIsolationTimer != 0) {
if (network->FailureIsolationTimer > MsTickInterval) {
network->FailureIsolationTimer -= MsTickInterval;
}
else {
//
// The timer has expired. Schedule a worker thread
// to perform failure isolation on the network.
//
DWORD status = ERROR_SUCCESS;
LPCWSTR networkId = OmObjectId(network);
LPCWSTR networkName = OmObjectName(network);
ClRtlLogPrint(LOG_NOISE,
"[NM] Failure isolation timer expired for network "
"%1!ws! (%2!ws!).\n",
networkId,
networkName
);
if (!NmpIsNetworkWorkerRunning(network)) {
status = NmpScheduleNetworkWorker(network);
}
//
// Zero out the timer if we succeeded in scheduling a
// worker thread. If we failed, leave the timer value
// non-zero and we'll try again on the next tick.
//
if (status == ERROR_SUCCESS) {
network->FailureIsolationTimer = 0;
network->Flags |= NM_FLAG_NET_ISOLATE_FAILURE;
}
}
}
//
// Network name change pending timer.
//
if (network->NameChangePendingTimer != 0) {
if (network->NameChangePendingTimer > MsTickInterval) {
network->NameChangePendingTimer -= MsTickInterval;
}
else {
LPCWSTR networkId = OmObjectId(network);
LPCWSTR networkName = OmObjectName(network);
ClRtlLogPrint(LOG_NOISE,
"[NM] Name change pending timer expired for network "
"%1!ws! (%2!ws!).\n",
networkId,
networkName
);
// Clear the name change pending flag
network->Flags &= ~NM_FLAG_NET_NAME_CHANGE_PENDING;
}
}
//
// Network multicast key regenerate timer.
//
if (network->McastKeyRegenerateTimer != 0) {
if (network->McastKeyRegenerateTimer > MsTickInterval) {
// test
LPCWSTR networkId = OmObjectId(network);
LPCWSTR networkName = OmObjectName(network);
// test
network->McastKeyRegenerateTimer -= MsTickInterval;
}
else {
//
// The timer has expired. Schedule a worker thread
// to regenerate the network's multicast key.
//
LPCWSTR networkId = OmObjectId(network);
LPCWSTR networkName = OmObjectName(network);
ClRtlLogPrint(LOG_NOISE,
"[NM] Multicast key regenerate timer "
"expired for network %1!ws! (%2!ws!).\n",
networkId,
networkName
);
NmpScheduleMulticastKeyRegeneration(network);
}
}
}
NmpLockedLeaveApi();
}
return;
} // NmpNetworkTimerTick
VOID
NmpStartNetworkConnectivityReportTimer(
PNM_NETWORK Network
)
/*++
Routine Description:
Starts the connectivity report timer for a network. Connectivity
reports are delayed in order to aggregate events when a failure
occurs that affects multiple nodes.
Arguments:
Network - A pointer to the network for which to start the timer.
Return Value
None.
Notes:
Called with NM lock held.
--*/
{
//
// Check if the timer is already running.
//
if (Network->ConnectivityReportTimer == 0) {
//
// Check how many nodes are attached to this network.
//
if (Network->InterfaceCount <= 2) {
//
// There is no point in waiting to aggregate reports when
// only two nodes are connected to the network.
// Just schedule a worker thread to deliver the report.
//
NmpScheduleNetworkConnectivityReport(Network);
}
else {
//
// More than two nodes are connected to this network.
// Start the timer.
//
LPCWSTR networkId = OmObjectId(Network);
LPCWSTR networkName = OmObjectName(Network);
Network->ConnectivityReportTimer =
NM_NET_CONNECTIVITY_REPORT_TIMEOUT;
ClRtlLogPrint(LOG_NOISE,
"[NM] Started connectivity report timer (%1!u!ms) for "
"network %2!ws! (%3!ws!)\n",
Network->ConnectivityReportTimer,
networkId,
networkName
);
}
}
return;
} // NmpStartNetworkConnectivityReportTimer
VOID
NmpStartNetworkStateRecalcTimer(
PNM_NETWORK Network,
DWORD Timeout
)
{
LPCWSTR networkId = OmObjectId(Network);
LPCWSTR networkName = OmObjectName(Network);
if (Network->StateRecalcTimer == 0) {
Network->StateRecalcTimer = Timeout;
ClRtlLogPrint(LOG_NOISE,
"[NM] Started state recalculation timer (%1!u!ms) for "
"network %2!ws! (%3!ws!)\n",
Network->StateRecalcTimer,
networkId,
networkName
);
}
return;
} // NmpStartNetworkStateRecalcTimer
VOID
NmpStartNetworkFailureIsolationTimer(
PNM_NETWORK Network,
DWORD Timeout
)
{
if (Network->FailureIsolationTimer == 0) {
Network->FailureIsolationTimer = Timeout;
ClRtlLogPrint(LOG_NOISE,
"[NM] Started failure isolation timer (%1!u!ms) for "
"network %2!ws! (%3!ws!)\n",
Network->FailureIsolationTimer,
OmObjectId(Network),
OmObjectName(Network)
);
}
return;
} // NmpStartNetworkFailureIsolationTimer
VOID
NmpStartNetworkRegistrationRetryTimer(
PNM_NETWORK Network
)
{
if (Network->RegistrationRetryTimer == 0) {
if (Network->RegistrationRetryTimeout == 0) {
Network->RegistrationRetryTimeout =
NM_NET_MIN_REGISTRATION_RETRY_TIMEOUT;
}
else {
//
// Exponential backoff
//
Network->RegistrationRetryTimeout *= 2;
if ( Network->RegistrationRetryTimeout >
NM_NET_MAX_REGISTRATION_RETRY_TIMEOUT
)
{
Network->RegistrationRetryTimeout =
NM_NET_MAX_REGISTRATION_RETRY_TIMEOUT;
}
}
Network->RegistrationRetryTimer = Network->RegistrationRetryTimeout;
ClRtlLogPrint(LOG_NOISE,
"[NM] Started registration retry timer (%1!u!ms) for "
"network %2!ws! (%3!ws!)\n",
Network->RegistrationRetryTimer,
OmObjectId(Network),
OmObjectName(Network)
);
}
return;
} // NmpStartNetworkRegistrationRetryTimer
VOID
NmpStartNetworkNameChangePendingTimer(
IN PNM_NETWORK Network,
IN DWORD Timeout
)
{
if (Network->NameChangePendingTimer != Timeout) {
Network->NameChangePendingTimer = Timeout;
ClRtlLogPrint(LOG_NOISE,
"[NM] %1!ws! name change pending timer (%2!u!ms) for "
"network %3!ws! (%4!ws!)\n",
((Timeout != 0) ? L"Started" : L"Cleared"),
Network->NameChangePendingTimer,
OmObjectId(Network),
OmObjectName(Network)
);
}
return;
} // NmpStartNetworkNameChangePendingTimer
VOID
NmpScheduleNetworkConnectivityReport(
PNM_NETWORK Network
)
/*++
Routine Description:
Schedules a worker thread to deliver a connectivity report to
the leader node for the specified network. Called when the
ConnectivityReport timer expires for a network. Also called
directly in some cases.
Arguments:
A pointer to the network object for which to generate a report.
Return Value:
None.
Notes:
This routine is called with the NM lock held.
--*/
{
DWORD status = ERROR_SUCCESS;
//
// Check if a worker thread is already scheduled.
//
if (!NmpIsConnectivityReportWorkerRunning) {
status = NmpScheduleConnectivityReportWorker();
}
if (status == ERROR_SUCCESS) {
//
// We succeeded in scheduling a worker thread. Stop the
// ConnectivityReport timer and set the work flag to generate
// a report.
//
Network->ConnectivityReportTimer = 0;
Network->Flags |= NM_FLAG_NET_REPORT_CONNECTIVITY;
NmpNeedConnectivityReport = TRUE;
}
else {
//
// We failed to schedule a worker thread. Set the
// ConnecivityReport timer to expire on the next tick, so we
// can try again.
//
Network->ConnectivityReportTimer = 1;
}
return;
} // NmpScheduleNetworkConnectivityReport
VOID
NmpScheduleNetworkStateRecalc(
PNM_NETWORK Network
)
/*++
Routine Description:
Schedules a worker thread to recalculate the state of the
specified network and all of the network's interface. A network
state recalculation can be triggered by the arrival of a connectivity
report, the joining/death of a node, or a network role change.
Arguments:
A pointer to the network object whose state is to be recalculated.
Return Value:
None.
Notes:
This routine is called with the NM lock held.
--*/
{
DWORD status = ERROR_SUCCESS;
//
// Check if a worker thread is already scheduled to
// service this network.
//
if (!NmpIsNetworkWorkerRunning(Network)) {
status = NmpScheduleNetworkWorker(Network);
}
if (status == ERROR_SUCCESS) {
//
// We succeeded in scheduling a worker thread. Stop the
// StateRecalc timer and set the state recalculation work flag.
//
Network->StateRecalcTimer = 0;
Network->Flags |= NM_FLAG_NET_RECALC_STATE;
}
else {
//
// We failed to schedule a worker thread. Set the StateRecalc
// timer to expire on the next tick, so we can try again.
//
Network->ConnectivityReportTimer = 1;
}
return;
} // NmpScheduleNetworkStateRecalc
VOID
NmpScheduleNetworkRegistration(
PNM_NETWORK Network
)
/*++
Routine Description:
Schedules a worker thread to register a network with the cluster
transport.
Arguments:
A pointer to the network to register.
Return Value:
None.
Notes:
This routine is called with the NM lock held.
--*/
{
DWORD status = ERROR_SUCCESS;
//
// Check if a worker thread is already scheduled to
// service this network.
//
if (!NmpIsNetworkWorkerRunning(Network)) {
status = NmpScheduleNetworkWorker(Network);
}
if (status == ERROR_SUCCESS) {
//
// We succeeded in scheduling a worker thread. Stop the
// retry timer and set the registration work flag.
//
Network->RegistrationRetryTimer = 0;
Network->Flags |= NM_FLAG_NET_NEED_TO_REGISTER;
}
else {
//
// We failed to schedule a worker thread. Set the retry
// timer to expire on the next tick, so we can try again.
//
Network->RegistrationRetryTimer = 1;
}
return;
} // NmpScheduleNetworkRegistration
DWORD
NmpScheduleConnectivityReportWorker(
VOID
)
/*++
Routine Description:
Schedule a worker thread to deliver network connectivity reports.
Arguments:
None.
Return Value:
A Win32 status code.
Notes:
Called with the NM global lock held.
--*/
{
DWORD status;
ClRtlInitializeWorkItem(
&NmpConnectivityReportWorkItem,
NmpConnectivityReportWorker,
NULL
);
status = ClRtlPostItemWorkQueue(
CsDelayedWorkQueue,
&NmpConnectivityReportWorkItem,
0,
0
);
if (status == ERROR_SUCCESS) {
NmpActiveThreadCount++;
NmpIsConnectivityReportWorkerRunning = TRUE;
ClRtlLogPrint(LOG_NOISE,
"[NM] Scheduled network connectivity report worker thread.\n"
);
}
else {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to schedule network connectivity report worker "
"thread, status %1!u!\n",
status
);
}
return(status);
} // NmpScheduleConnectivityReportWorker
DWORD
NmpScheduleNetworkWorker(
PNM_NETWORK Network
)
/*++
Routine Description:
Schedule a worker thread to service this network
Arguments:
Network - Pointer to the network for which to schedule a worker thread.
Return Value:
A Win32 status code.
Notes:
Called with the NM global lock held.
--*/
{
DWORD status;
LPCWSTR networkId = OmObjectId(Network);
ClRtlInitializeWorkItem(
&(Network->WorkItem),
NmpNetworkWorker,
(PVOID) Network
);
status = ClRtlPostItemWorkQueue(
CsDelayedWorkQueue,
&(Network->WorkItem),
0,
0
);
if (status == ERROR_SUCCESS) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Scheduled worker thread to service network %1!ws!.\n",
networkId
);
NmpActiveThreadCount++;
Network->Flags |= NM_FLAG_NET_WORKER_RUNNING;
OmReferenceObject(Network);
}
else {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to schedule worker thread to service network "
"%1!ws!, status %2!u!\n",
networkId,
status
);
}
return(status);
} // NmpScheduleNetworkWorker
DWORD
NmpReportNetworkConnectivity(
IN PNM_NETWORK Network
)
/*+
Notes:
Called with the NmpLock held.
May be called by asynchronous worker threads.
--*/
{
DWORD status = ERROR_SUCCESS;
LPCWSTR networkId = OmObjectId(Network);
//
// Since this routine is called by asynchronous worker threads,
// check if the report is still valid.
//
if (NmpIsNetworkRegistered(Network)) {
PNM_CONNECTIVITY_VECTOR vector = Network->ConnectivityVector;
PNM_INTERFACE localInterface = Network->LocalInterface;
//
// Record the information in our local data structures.
//
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Updating local connectivity info for network %1!ws!.\n",
networkId
);
NmpProcessInterfaceConnectivityReport(
localInterface,
vector
);
if (NmpLeaderNodeId != NmLocalNodeId) {
//
// Send the report to the leader via RPC.
//
PNM_CONNECTIVITY_VECTOR tmpVector;
DWORD vectorSize;
LPCWSTR localInterfaceId =
OmObjectId(localInterface);
//
// Allocate a temporary connectivity vector, since the
// one in the network object can be resized during the
// RPC call.
//
vectorSize = sizeof(NM_CONNECTIVITY_VECTOR) +
((vector->EntryCount - 1) * sizeof(NM_STATE_ENTRY));
tmpVector = LocalAlloc(LMEM_FIXED, vectorSize);
if (tmpVector != NULL) {
CopyMemory(tmpVector, vector, vectorSize);
OmReferenceObject(Network);
OmReferenceObject(localInterface);
if (NM_NODE_UP(NmLocalNode) && (NmpState == NmStateOnline)) {
//
// This node is fully operational. Send the report
// directly to the leader.
//
PNM_NODE node = NmpIdArray[NmpLeaderNodeId];
RPC_BINDING_HANDLE rpcBinding = node->ReportRpcBinding;
OmReferenceObject(node);
status = NmpReportInterfaceConnectivity(
rpcBinding,
(LPWSTR) localInterfaceId,
tmpVector,
(LPWSTR) networkId
);
OmDereferenceObject(node);
}
else if (CsJoinSponsorBinding != NULL) {
//
// This node is joining. Forward the report to the
// sponsor.
//
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Reporting connectivity to sponsor for "
"network %1!ws!.\n",
networkId
);
NmpReleaseLock();
status = NmRpcReportJoinerInterfaceConnectivity(
CsJoinSponsorBinding,
NmpJoinSequence,
NmLocalNodeIdString,
(LPWSTR) localInterfaceId,
tmpVector
);
NmpAcquireLock();
}
else {
//
// This node must be shutting down
//
CL_ASSERT(NmpState == NmStateOfflinePending);
status = ERROR_SUCCESS;
}
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Failed to report connectivity for network "
"%1!ws!, status %2!u!.\n",
networkId,
status
);
}
LocalFree(tmpVector);
OmDereferenceObject(localInterface);
OmDereferenceObject(Network);
}
else {
status = ERROR_NOT_ENOUGH_MEMORY;
}
}
}
return(status);
} // NmpReportNetworkConnectivity
VOID
NmpUpdateNetworkConnectivityForDownNode(
PNM_NODE Node
)
/*++
Notes:
Called with NmpLock held.
--*/
{
PLIST_ENTRY entry;
PNM_NETWORK network;
LPCWSTR networkId;
PNM_INTERFACE netInterface;
DWORD entryCount;
DWORD i;
PNM_CONNECTIVITY_MATRIX matrixEntry;
ClRtlLogPrint(LOG_NOISE,
"[NM] Cleaning up network and interface states for dead node %1!u!\n",
Node->NodeId
);
//
// Walk the dead node's interface list and clean up the network and
// interface states.
//
for (entry = Node->InterfaceList.Flink;
entry != &(Node->InterfaceList);
entry = entry->Flink
)
{
netInterface = CONTAINING_RECORD(
entry,
NM_INTERFACE,
NodeLinkage
);
network = netInterface->Network;
networkId = OmObjectId(network);
ClRtlLogPrint(LOG_NOISE,
"[NM] Cleaning up state of network %1!ws!\n",
networkId
);
//
// Invalidate the connectivity data for this interface.
//
NmpSetInterfaceConnectivityData(
network,
netInterface->NetIndex,
ClusterNetInterfaceUnavailable
);
//
// If the local node is attached to the network, schedule a
// connectivity report to the new leader.
//
if (NmpIsNetworkRegistered(network)) {
NmpScheduleNetworkConnectivityReport(network);
}
//
// If the local node is the (possibly new) leader, schedule
// a state update. We explicitly enable this timer here in case
// there are no active nodes attached to the network.
//
if (NmpLeaderNodeId == NmLocalNodeId) {
NmpStartNetworkStateRecalcTimer(
network,
NM_NET_STATE_RECALC_TIMEOUT_AFTER_REGROUP
);
}
}
return;
} // NmpUpdateNetworkConnectivityForDownNode
VOID
NmpFreeNetworkStateEnum(
PNM_NETWORK_STATE_ENUM NetworkStateEnum
)
{
PNM_NETWORK_STATE_INFO networkStateInfo;
DWORD i;
for (i=0; i<NetworkStateEnum->NetworkCount; i++) {
networkStateInfo = &(NetworkStateEnum->NetworkList[i]);
if (networkStateInfo->Id != NULL) {
MIDL_user_free(networkStateInfo->Id);
}
}
MIDL_user_free(NetworkStateEnum);
return;
} // NmpFreeNetworkStateEnum
/////////////////////////////////////////////////////////////////////////////
//
// Database management routines
//
/////////////////////////////////////////////////////////////////////////////
DWORD
NmpCreateNetworkDefinition(
IN PNM_NETWORK_INFO NetworkInfo,
IN HLOCALXSACTION Xaction
)
/*++
Routine Description:
Creates a new network definition in the cluster database.
Arguments:
NetworkInfo - A pointer to the information structure describing the
network to create.
Return Value:
ERROR_SUCCESS if successful.
A Win32 error code otherwise.
--*/
{
DWORD status;
HDMKEY networkKey = NULL;
DWORD valueLength;
DWORD disposition;
ClRtlLogPrint(LOG_NOISE,
"[NM] Creating database entry for network %1!ws!\n",
NetworkInfo->Id
);
networkKey = DmLocalCreateKey(
Xaction,
DmNetworksKey,
NetworkInfo->Id,
0,
KEY_WRITE,
NULL,
&disposition
);
if (networkKey == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to create network key, status %1!u!\n",
status
);
return(status);
}
CL_ASSERT(disposition == REG_CREATED_NEW_KEY);
//
// Write the name value for this network
//
valueLength = (wcslen(NetworkInfo->Name) + 1) * sizeof(WCHAR);
status = DmLocalSetValue(
Xaction,
networkKey,
CLUSREG_NAME_NET_NAME,
REG_SZ,
(CONST BYTE *) NetworkInfo->Name,
valueLength
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of network name value failed, status %1!u!.\n",
status
);
goto error_exit;
}
//
// Write the description value for this network
//
valueLength = (wcslen(NetworkInfo->Description) + 1) * sizeof(WCHAR);
status = DmLocalSetValue(
Xaction,
networkKey,
CLUSREG_NAME_NET_DESC,
REG_SZ,
(CONST BYTE *) NetworkInfo->Description,
valueLength
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of network description value failed, status %1!u!.\n",
status
);
goto error_exit;
}
//
// Write the role value for this network
//
status = DmLocalSetValue(
Xaction,
networkKey,
CLUSREG_NAME_NET_ROLE,
REG_DWORD,
(CONST BYTE *) &(NetworkInfo->Role),
sizeof(DWORD)
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of network role value failed, status %1!u!.\n",
status
);
goto error_exit;
}
//
// Write the priority value for this network
//
status = DmLocalSetValue(
Xaction,
networkKey,
CLUSREG_NAME_NET_PRIORITY,
REG_DWORD,
(CONST BYTE *) &(NetworkInfo->Priority),
sizeof(DWORD)
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of network priority value failed, status %1!u!.\n",
status
);
goto error_exit;
}
//
// Write the transport value for this network
//
valueLength = (wcslen(NetworkInfo->Transport) + 1) * sizeof(WCHAR);
status = DmLocalSetValue(
Xaction,
networkKey,
CLUSREG_NAME_NET_TRANSPORT,
REG_SZ,
(CONST BYTE *) NetworkInfo->Transport,
valueLength
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of network transport value failed, status %1!u!.\n",
status
);
goto error_exit;
}
//
// Write the address value for this network
//
valueLength = (wcslen(NetworkInfo->Address) + 1) * sizeof(WCHAR);
status = DmLocalSetValue(
Xaction,
networkKey,
CLUSREG_NAME_NET_ADDRESS,
REG_SZ,
(CONST BYTE *) NetworkInfo->Address,
valueLength
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of network address value failed, status %1!u!.\n",
status
);
goto error_exit;
}
//
// Write the address mask value for this network
//
valueLength = (wcslen(NetworkInfo->AddressMask) + 1) * sizeof(WCHAR);
status = DmLocalSetValue(
Xaction,
networkKey,
CLUSREG_NAME_NET_ADDRESS_MASK,
REG_SZ,
(CONST BYTE *) NetworkInfo->AddressMask,
valueLength
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of network address mask value failed, status %1!u!.\n",
status
);
goto error_exit;
}
CL_ASSERT(status == ERROR_SUCCESS);
error_exit:
if (networkKey != NULL) {
DmCloseKey(networkKey);
}
return(status);
} // NmpCreateNetworkDefinition
DWORD
NmpSetNetworkNameDefinition(
IN PNM_NETWORK_INFO NetworkInfo,
IN HLOCALXSACTION Xaction
)
/*++
Routine Description:
Changes the network name in the local database
Arguments:
NetworkInfo - A pointer to the information structure describing the
network to create.
Return Value:
ERROR_SUCCESS if successful.
A Win32 error code otherwise.
--*/
{
DWORD status;
HDMKEY networkKey = NULL;
DWORD disposition;
ClRtlLogPrint(LOG_NOISE,
"[NM] Changing network name database entry for network %1!ws!\n",
NetworkInfo->Id
);
//
// Open the network's key.
//
networkKey = DmOpenKey(DmNetworksKey, NetworkInfo->Id, KEY_WRITE);
if (networkKey == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to open network key, status %1!u!\n",
status
);
goto error_exit;
}
//
// Write the name value for this network
//
status = DmLocalSetValue(
Xaction,
networkKey,
CLUSREG_NAME_NET_NAME,
REG_SZ,
(CONST BYTE *) NetworkInfo->Name,
NM_WCSLEN( NetworkInfo->Name )
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Set of network name value failed, status %1!u!.\n",
status
);
goto error_exit;
}
CL_ASSERT(status == ERROR_SUCCESS);
error_exit:
if (networkKey != NULL) {
DmCloseKey(networkKey);
}
return(status);
} // NmpSetNetworkNameDefinition
DWORD
NmpGetNetworkDefinition(
IN LPWSTR NetworkId,
OUT PNM_NETWORK_INFO NetworkInfo
)
/*++
Routine Description:
Reads information about a defined cluster network from the cluster
database and fills in a structure describing it.
Arguments:
NetworkId - A pointer to a unicode string containing the ID of the
network to query.
NetworkInfo - A pointer to the network info structure to fill in.
Return Value:
ERROR_SUCCESS if the routine succeeds.
A Win32 error code otherwise.
--*/
{
DWORD status;
HDMKEY networkKey = NULL;
DWORD valueLength, valueSize;
DWORD i;
ZeroMemory(NetworkInfo, sizeof(NM_NETWORK_INFO));
//
// Open the network's key.
//
networkKey = DmOpenKey(DmNetworksKey, NetworkId, KEY_READ);
if (networkKey == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to open network key, status %1!u!\n",
status
);
goto error_exit;
}
//
// Copy the ID value.
//
NetworkInfo->Id = MIDL_user_allocate(NM_WCSLEN(NetworkId));
if (NetworkInfo->Id == NULL) {
status = ERROR_NOT_ENOUGH_MEMORY;
goto error_exit;
}
wcscpy(NetworkInfo->Id, NetworkId);
//
// Read the network's name.
//
valueLength = 0;
status = NmpQueryString(
networkKey,
CLUSREG_NAME_NET_NAME,
REG_SZ,
&(NetworkInfo->Name),
&valueLength,
&valueSize
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Query of name value failed for network %1!ws!, "
"status %2!u!.\n",
NetworkId,
status
);
goto error_exit;
}
//
// Read the description value.
//
valueLength = 0;
status = NmpQueryString(
networkKey,
CLUSREG_NAME_NET_DESC,
REG_SZ,
&(NetworkInfo->Description),
&valueLength,
&valueSize
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Query of description value failed for network %1!ws!, "
"status %2!u!.\n",
NetworkId,
status
);
goto error_exit;
}
//
// Read the role value.
//
status = DmQueryDword(
networkKey,
CLUSREG_NAME_NET_ROLE,
&(NetworkInfo->Role),
NULL
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Query of role value failed for network %1!ws!, "
"status %2!u!.\n",
NetworkId,
status
);
goto error_exit;
}
//
// Read the priority value.
//
status = DmQueryDword(
networkKey,
CLUSREG_NAME_NET_PRIORITY,
&(NetworkInfo->Priority),
NULL
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Query of priority value failed for network %1!ws!, "
"status %2!u!.\n",
NetworkId,
status
);
goto error_exit;
}
//
// Read the address value.
//
valueLength = 0;
status = NmpQueryString(
networkKey,
CLUSREG_NAME_NET_ADDRESS,
REG_SZ,
&(NetworkInfo->Address),
&valueLength,
&valueSize
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Query of address value failed for network %1!ws!, "
"status %2!u!.\n",
NetworkId,
status
);
goto error_exit;
}
//
// Read the address mask.
//
valueLength = 0;
status = NmpQueryString(
networkKey,
CLUSREG_NAME_NET_ADDRESS_MASK,
REG_SZ,
&(NetworkInfo->AddressMask),
&valueLength,
&valueSize
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Query of address mask value failed for network %1!ws!, "
"status %2!u!.\n",
NetworkId,
status
);
goto error_exit;
}
//
// Read the transport name.
//
valueLength = 0;
status = NmpQueryString(
networkKey,
CLUSREG_NAME_NET_TRANSPORT,
REG_SZ,
&(NetworkInfo->Transport),
&valueLength,
&valueSize
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Query of transport value failed for network %1!ws!, "
"status %2!u!.\n",
NetworkId,
status
);
goto error_exit;
}
CL_ASSERT(status == ERROR_SUCCESS);
error_exit:
if (status != ERROR_SUCCESS) {
ClNetFreeNetworkInfo(NetworkInfo);
}
if (networkKey != NULL) {
DmCloseKey(networkKey);
}
return(status);
} // NmpGetNetworkDefinition
DWORD
NmpEnumNetworkDefinitions(
OUT PNM_NETWORK_ENUM * NetworkEnum
)
/*++
Routine Description:
Reads information about defined cluster networks from the cluster
database. and builds an enumeration structure to hold the information.
Arguments:
NetworkEnum - A pointer to the variable into which to place a pointer to
the allocated network enumeration.
Return Value:
ERROR_SUCCESS if the routine succeeds.
A Win32 error code otherwise.
--*/
{
DWORD status;
PNM_NETWORK_ENUM networkEnum = NULL;
PNM_NETWORK_INFO networkInfo;
WCHAR networkId[CS_NETWORK_ID_LENGTH + 1];
DWORD i;
DWORD valueLength;
DWORD numNetworks;
DWORD ignored;
FILETIME fileTime;
*NetworkEnum = NULL;
//
// First count the number of networks.
//
status = DmQueryInfoKey(
DmNetworksKey,
&numNetworks,
&ignored, // MaxSubKeyLen
&ignored, // Values
&ignored, // MaxValueNameLen
&ignored, // MaxValueLen
&ignored, // lpcbSecurityDescriptor
&fileTime
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to query Networks key information, status %1!u!\n",
status
);
return(status);
}
if (numNetworks == 0) {
valueLength = sizeof(NM_NETWORK_ENUM);
}
else {
valueLength = sizeof(NM_NETWORK_ENUM) +
(sizeof(NM_NETWORK_INFO) * (numNetworks-1));
}
valueLength = sizeof(NM_NETWORK_ENUM) +
(sizeof(NM_NETWORK_INFO) * (numNetworks-1));
networkEnum = MIDL_user_allocate(valueLength);
if (networkEnum == NULL) {
ClRtlLogPrint(LOG_CRITICAL, "[NM] Failed to allocate memory.\n");
return(ERROR_NOT_ENOUGH_MEMORY);
}
ZeroMemory(networkEnum, valueLength);
for (i=0; i < numNetworks; i++) {
networkInfo = &(networkEnum->NetworkList[i]);
valueLength = sizeof(networkId);
status = DmEnumKey(
DmNetworksKey,
i,
&(networkId[0]),
&valueLength,
NULL
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to enumerate network key, status %1!u!\n",
status
);
goto error_exit;
}
status = NmpGetNetworkDefinition(networkId, networkInfo);
if (status != ERROR_SUCCESS) {
goto error_exit;
}
networkEnum->NetworkCount++;
}
*NetworkEnum = networkEnum;
return(ERROR_SUCCESS);
error_exit:
if (networkEnum != NULL) {
ClNetFreeNetworkEnum(networkEnum);
}
return(status);
}
/////////////////////////////////////////////////////////////////////////////
//
// Object management routines
//
/////////////////////////////////////////////////////////////////////////////
DWORD
NmpCreateNetworkObjects(
IN PNM_NETWORK_ENUM NetworkEnum
)
/*++
Routine Description:
Processes a network information enumeration and creates network objects.
Arguments:
NetworkEnum - A pointer to a network information enumeration structure.
Return Value:
ERROR_SUCCESS if the routine completes successfully.
A Win32 error code otherwise.
--*/
{
DWORD status = ERROR_SUCCESS;
PNM_NETWORK_INFO networkInfo;
PNM_NETWORK network;
DWORD i;
for (i=0; i < NetworkEnum->NetworkCount; i++) {
networkInfo = &(NetworkEnum->NetworkList[i]);
network = NmpCreateNetworkObject(networkInfo);
if (network == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to create network %1!ws!, status %2!u!.\n",
networkInfo->Id,
status
);
break;
}
else {
OmDereferenceObject(network);
}
}
return(status);
} // NmpCreateNetworkObjects
PNM_NETWORK
NmpCreateNetworkObject(
IN PNM_NETWORK_INFO NetworkInfo
)
/*++
Routine Description:
Instantiates a cluster network object.
Arguments:
NetworkInfo - A pointer to a structure describing the network to create.
Return Value:
A pointer to the new network object on success.
NULL on failure.
--*/
{
DWORD status;
PNM_NETWORK network = NULL;
BOOL created = FALSE;
DWORD i;
ClRtlLogPrint(LOG_NOISE,
"[NM] Creating object for network %1!ws! (%2!ws!).\n",
NetworkInfo->Id,
NetworkInfo->Name
);
//
// Make sure that an object with the same name doesn't already exist.
//
network = OmReferenceObjectById(ObjectTypeNetwork, NetworkInfo->Id);
if (network != NULL) {
OmDereferenceObject(network);
ClRtlLogPrint(LOG_CRITICAL,
"[NM] A network object named %1!ws! already exists. Cannot "
"create a new network with the same name.\n",
NetworkInfo->Id
);
SetLastError(ERROR_OBJECT_ALREADY_EXISTS);
return(NULL);
}
//
// Ensure that the IP (sub)network is unique in the cluster. Two
// nodes can race to create a new network in some cases.
//
// [RajDas] Need to check mask too for uniqueness.
network = NmpReferenceNetworkByAddress(
NetworkInfo->Address,
NetworkInfo->AddressMask
);
if (network != NULL) {
OmDereferenceObject(network);
ClRtlLogPrint(LOG_CRITICAL,
"[NM] A network object already exists for IP network %1!ws!. "
"Cannot create a new network with the same address.\n",
NetworkInfo->Address
);
SetLastError(ERROR_OBJECT_ALREADY_EXISTS);
return(NULL);
}
//
// Create a network object.
//
network = OmCreateObject(
ObjectTypeNetwork,
NetworkInfo->Id,
NetworkInfo->Name,
&created
);
if (network == NULL) {
status = GetLastError();
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to create object for network %1!ws! (%2!ws!), status %3!u!\n",
NetworkInfo->Id,
NetworkInfo->Name,
status
);
goto error_exit;
}
CL_ASSERT(created == TRUE);
//
// Initialize the network object
//
ZeroMemory(network, sizeof(NM_NETWORK));
network->ShortId = InterlockedIncrement(&NmpNextNetworkShortId);
network->State = ClusterNetworkUnavailable;
network->Role = NetworkInfo->Role;
network->Priority = NetworkInfo->Priority;
network->Description = NetworkInfo->Description;
NetworkInfo->Description = NULL;
network->Transport = NetworkInfo->Transport;
NetworkInfo->Transport = NULL;
network->Address = NetworkInfo->Address;
NetworkInfo->Address = NULL;
network->AddressMask = NetworkInfo->AddressMask;
NetworkInfo->AddressMask = NULL;
InitializeListHead(&(network->InterfaceList));
InitializeListHead(&(network->McastAddressReleaseList));
//
// Allocate an initial connectivity vector.
// Note that we get one vector entry as part of
// the NM_CONNECTIVITY_VECTOR structure.
//
#define NM_INITIAL_VECTOR_SIZE 2
network->ConnectivityVector = LocalAlloc(
LMEM_FIXED,
( sizeof(NM_CONNECTIVITY_VECTOR) +
( ((NM_INITIAL_VECTOR_SIZE) - 1) *
sizeof(NM_STATE_ENTRY)
)
));
if (network->ConnectivityVector == NULL) {
status = ERROR_NOT_ENOUGH_MEMORY;
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to allocate memory for connectivity vector\n"
);
goto error_exit;
}
network->ConnectivityVector->EntryCount = NM_INITIAL_VECTOR_SIZE;
FillMemory(
&(network->ConnectivityVector->Data[0]),
NM_INITIAL_VECTOR_SIZE * sizeof(NM_STATE_ENTRY),
(UCHAR) ClusterNetInterfaceStateUnknown
);
//
// Allocate a state work vector
//
network->StateWorkVector = LocalAlloc(
LMEM_FIXED,
(NM_INITIAL_VECTOR_SIZE) *
sizeof(NM_STATE_WORK_ENTRY)
);
if (network->StateWorkVector == NULL) {
status = ERROR_NOT_ENOUGH_MEMORY;
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to allocate memory for state work vector\n"
);
goto error_exit;
}
//
// Initialize the state work vector
//
for (i=0; i<NM_INITIAL_VECTOR_SIZE; i++) {
network->StateWorkVector[i].State =
(NM_STATE_ENTRY) ClusterNetInterfaceStateUnknown;
}
//
// Put a reference on the object for the caller.
//
OmReferenceObject(network);
NmpAcquireLock();
//
// Allocate the corresponding connectivity matrix
//
network->ConnectivityMatrix =
LocalAlloc(
LMEM_FIXED,
NM_SIZEOF_CONNECTIVITY_MATRIX(NM_INITIAL_VECTOR_SIZE)
);
if (network->ConnectivityMatrix == NULL) {
status = ERROR_NOT_ENOUGH_MEMORY;
NmpReleaseLock();
OmDereferenceObject(network);
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to allocate memory for connectivity matrix\n"
);
goto error_exit;
}
//
// Initialize the matrix
//
FillMemory(
network->ConnectivityMatrix,
NM_SIZEOF_CONNECTIVITY_MATRIX(NM_INITIAL_VECTOR_SIZE),
(UCHAR) ClusterNetInterfaceStateUnknown
);
//
// Make the network object available.
//
InsertTailList(&NmpNetworkList, &(network->Linkage));
NmpNetworkCount++;
if (NmpIsNetworkForInternalUse(network)) {
NmpInsertInternalNetwork(network);
NmpInternalNetworkCount++;
}
if (NmpIsNetworkForClientAccess(network)) {
NmpClientNetworkCount++;
}
network->Flags |= NM_FLAG_OM_INSERTED;
OmInsertObject(network);
NmpReleaseLock();
return(network);
error_exit:
if (network != NULL) {
NmpAcquireLock();
NmpDeleteNetworkObject(network, FALSE);
NmpReleaseLock();
}
SetLastError(status);
return(NULL);
} // NmpCreateNetworkObject
DWORD
NmpGetNetworkObjectInfo(
IN PNM_NETWORK Network,
OUT PNM_NETWORK_INFO NetworkInfo
)
/*++
Routine Description:
Reads information about a defined cluster network from the
network object and fills in a structure describing it.
Arguments:
Network - A pointer to the network object to query.
NetworkInfo - A pointer to the structure to fill in with network
information.
Return Value:
ERROR_SUCCESS if the routine succeeds.
A Win32 error code otherwise.
Notes:
Called with NmpLock held.
--*/
{
DWORD status = ERROR_NOT_ENOUGH_MEMORY;
LPWSTR tmpString = NULL;
LPWSTR networkId = (LPWSTR) OmObjectId(Network);
LPWSTR networkName = (LPWSTR) OmObjectName(Network);
ZeroMemory(NetworkInfo, sizeof(NM_NETWORK_INFO));
tmpString = MIDL_user_allocate(NM_WCSLEN(networkId));
if (tmpString == NULL) {
goto error_exit;
}
wcscpy(tmpString, networkId);
NetworkInfo->Id = tmpString;
tmpString = MIDL_user_allocate(NM_WCSLEN(networkName));
if (tmpString == NULL) {
goto error_exit;
}
wcscpy(tmpString, networkName);
NetworkInfo->Name = tmpString;
tmpString = MIDL_user_allocate(NM_WCSLEN(Network->Description));
if (tmpString == NULL) {
goto error_exit;
}
wcscpy(tmpString, Network->Description);
NetworkInfo->Description = tmpString;
NetworkInfo->Role = Network->Role;
NetworkInfo->Priority = Network->Priority;
tmpString = MIDL_user_allocate(NM_WCSLEN(Network->Transport));
if (tmpString == NULL) {
goto error_exit;
}
wcscpy(tmpString, Network->Transport);
NetworkInfo->Transport = tmpString;
tmpString = MIDL_user_allocate(NM_WCSLEN(Network->Address));
if (tmpString == NULL) {
goto error_exit;
}
wcscpy(tmpString, Network->Address);
NetworkInfo->Address = tmpString;
tmpString = MIDL_user_allocate(NM_WCSLEN(Network->AddressMask));
if (tmpString == NULL) {
goto error_exit;
}
wcscpy(tmpString, Network->AddressMask);
NetworkInfo->AddressMask = tmpString;
return(ERROR_SUCCESS);
error_exit:
ClNetFreeNetworkInfo(NetworkInfo);
return(status);
} // NmpGetNetworkObjectInfo
VOID
NmpDeleteNetworkObject(
IN PNM_NETWORK Network,
IN BOOLEAN IssueEvent
)
/*++
Routine Description:
Deletes a cluster network object.
Arguments:
Network - A pointer to the network object to delete.
IssueEvent - TRUE if a NETWORK_DELETED event should be issued when this
object is created. FALSE otherwise.
Return Value:
None.
Notes:
Called with NM global lock held.
--*/
{
DWORD status;
PLIST_ENTRY entry;
LPWSTR networkId = (LPWSTR) OmObjectId(Network);
BOOLEAN wasInternalNetwork = FALSE;
if (NM_DELETE_PENDING(Network)) {
CL_ASSERT(!NM_OM_INSERTED(Network));
return;
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Deleting object for network %1!ws!.\n",
networkId
);
CL_ASSERT(IsListEmpty(&(Network->InterfaceList)));
Network->Flags |= NM_FLAG_DELETE_PENDING;
//
// Remove from the object lists
//
if (NM_OM_INSERTED(Network)) {
status = OmRemoveObject(Network);
CL_ASSERT(status == ERROR_SUCCESS);
Network->Flags &= ~NM_FLAG_OM_INSERTED;
RemoveEntryList(&(Network->Linkage));
CL_ASSERT(NmpNetworkCount > 0);
NmpNetworkCount--;
if (NmpIsNetworkForInternalUse(Network)) {
RemoveEntryList(&(Network->InternalLinkage));
CL_ASSERT(NmpInternalNetworkCount > 0);
NmpInternalNetworkCount--;
wasInternalNetwork = TRUE;
}
if (NmpIsNetworkForClientAccess(Network)) {
CL_ASSERT(NmpClientNetworkCount > 0);
NmpClientNetworkCount--;
}
}
//
// Place the object on the deleted list
//
#if DBG
{
PLIST_ENTRY entry;
for ( entry = NmpDeletedNetworkList.Flink;
entry != &NmpDeletedNetworkList;
entry = entry->Flink
)
{
if (entry == &(Network->Linkage)) {
break;
}
}
CL_ASSERT(entry != &(Network->Linkage));
}
#endif DBG
InsertTailList(&NmpDeletedNetworkList, &(Network->Linkage));
if (NmpIsNetworkEnabledForUse(Network)) {
//
// Deregister the network from the cluster transport
//
NmpDeregisterNetwork(Network);
}
//
// Issue an event if needed
//
if (IssueEvent) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Issuing network deleted event for network %1!ws!.\n",
networkId
);
ClusterEvent(CLUSTER_EVENT_NETWORK_DELETED, Network);
//
// Issue a cluster property change event if this network was
// used for internal communication. The network priority list
// was changed.
//
if (wasInternalNetwork) {
NmpIssueClusterPropertyChangeEvent();
}
}
//
// Remove the initial reference so the object can be destroyed.
//
OmDereferenceObject(Network);
return;
} // NmpDeleteNetworkObject
BOOL
NmpDestroyNetworkObject(
PNM_NETWORK Network
)
{
DWORD status;
ClRtlLogPrint(LOG_NOISE,
"[NM] destroying object for network %1!ws!\n",
OmObjectId(Network)
);
CL_ASSERT(NM_DELETE_PENDING(Network));
CL_ASSERT(!NM_OM_INSERTED(Network));
CL_ASSERT(Network->InterfaceCount == 0);
//
// Remove the network from the deleted list
//
#if DBG
{
PLIST_ENTRY entry;
for ( entry = NmpDeletedNetworkList.Flink;
entry != &NmpDeletedNetworkList;
entry = entry->Flink
)
{
if (entry == &(Network->Linkage)) {
break;
}
}
CL_ASSERT(entry == &(Network->Linkage));
}
#endif DBG
RemoveEntryList(&(Network->Linkage));
NM_FREE_OBJECT_FIELD(Network, Description);
NM_FREE_OBJECT_FIELD(Network, Transport);
NM_FREE_OBJECT_FIELD(Network, Address);
NM_FREE_OBJECT_FIELD(Network, AddressMask);
if (Network->ConnectivityVector != NULL) {
LocalFree(Network->ConnectivityVector);
Network->ConnectivityVector = NULL;
}
if (Network->StateWorkVector != NULL) {
LocalFree(Network->StateWorkVector);
Network->StateWorkVector = NULL;
}
if (Network->ConnectivityMatrix != NULL) {
LocalFree(Network->ConnectivityMatrix);
Network->ConnectivityMatrix = NULL;
}
NM_MIDL_FREE_OBJECT_FIELD(Network, MulticastAddress);
if (Network->EncryptedMulticastKey != NULL) {
LocalFree(Network->EncryptedMulticastKey);
Network->EncryptedMulticastKey = NULL;
}
NM_MIDL_FREE_OBJECT_FIELD(Network, MulticastLeaseServer);
NM_MIDL_FREE_OBJECT_FIELD(Network, MulticastLeaseRequestId.ClientUID);
NmpFreeMulticastAddressReleaseList(Network);
return(TRUE);
} // NmpDestroyNetworkObject
DWORD
NmpEnumNetworkObjects(
OUT PNM_NETWORK_ENUM * NetworkEnum
)
/*++
Routine Description:
Reads information about defined cluster networks from the cluster
objects and builds an enumeration structure to hold the information.
Arguments:
NetworkEnum - A pointer to the variable into which to place a pointer to
the allocated network enumeration.
Return Value:
ERROR_SUCCESS if the routine succeeds.
A Win32 error code otherwise.
Notes:
Called with the NmpLock held.
--*/
{
DWORD status = ERROR_SUCCESS;
PNM_NETWORK_ENUM networkEnum = NULL;
DWORD i;
DWORD valueLength;
PLIST_ENTRY entry;
PNM_NETWORK network;
*NetworkEnum = NULL;
if (NmpNetworkCount == 0) {
valueLength = sizeof(NM_NETWORK_ENUM);
}
else {
valueLength = sizeof(NM_NETWORK_ENUM) +
(sizeof(NM_NETWORK_INFO) * (NmpNetworkCount - 1));
}
networkEnum = MIDL_user_allocate(valueLength);
if (networkEnum == NULL) {
return(ERROR_NOT_ENOUGH_MEMORY);
}
ZeroMemory(networkEnum, valueLength);
for (entry = NmpNetworkList.Flink, i=0;
entry != &NmpNetworkList;
entry = entry->Flink, i++
)
{
network = CONTAINING_RECORD(entry, NM_NETWORK, Linkage);
status = NmpGetNetworkObjectInfo(
network,
&(networkEnum->NetworkList[i])
);
if (status != ERROR_SUCCESS) {
ClNetFreeNetworkEnum(networkEnum);
return(status);
}
}
networkEnum->NetworkCount = NmpNetworkCount;
*NetworkEnum = networkEnum;
networkEnum = NULL;
return(ERROR_SUCCESS);
} // NmpEnumNetworkObjects
DWORD
NmpEnumNetworkObjectStates(
OUT PNM_NETWORK_STATE_ENUM * NetworkStateEnum
)
/*++
Routine Description:
Reads state information for all defined cluster networks
and fills in an enumeration structure.
Arguments:
NetworkStateEnum - A pointer to the variable into which to place a
pointer to the allocated interface enumeration.
Return Value:
ERROR_SUCCESS if the routine succeeds.
A Win32 error code otherwise.
Notes:
Called with the NmpLock held.
--*/
{
DWORD status = ERROR_SUCCESS;
PNM_NETWORK_STATE_ENUM networkStateEnum = NULL;
PNM_NETWORK_STATE_INFO networkStateInfo;
DWORD i;
DWORD valueLength;
PLIST_ENTRY entry;
PNM_NETWORK network;
LPWSTR networkId;
*NetworkStateEnum = NULL;
if (NmpNetworkCount == 0) {
valueLength = sizeof(NM_NETWORK_STATE_ENUM);
}
else {
valueLength =
sizeof(NM_NETWORK_STATE_ENUM) +
(sizeof(NM_NETWORK_STATE_INFO) * (NmpNetworkCount - 1));
}
networkStateEnum = MIDL_user_allocate(valueLength);
if (networkStateEnum == NULL) {
return(ERROR_NOT_ENOUGH_MEMORY);
}
ZeroMemory(networkStateEnum, valueLength);
for (entry = NmpNetworkList.Flink, i=0;
entry != &NmpNetworkList;
entry = entry->Flink, i++
)
{
network = CONTAINING_RECORD(entry, NM_NETWORK, Linkage);
networkId = (LPWSTR) OmObjectId(network);
networkStateInfo = &(networkStateEnum->NetworkList[i]);
networkStateInfo->State = network->State;
networkStateInfo->Id = MIDL_user_allocate(NM_WCSLEN(networkId));
if (networkStateInfo->Id == NULL) {
NmpFreeNetworkStateEnum(networkStateEnum);
return(ERROR_NOT_ENOUGH_MEMORY);
}
lstrcpyW(networkStateInfo->Id, networkId);
}
networkStateEnum->NetworkCount = NmpNetworkCount;
*NetworkStateEnum = networkStateEnum;
return(ERROR_SUCCESS);
} // NmpEnumNetworkObjectStates
DWORD
NmpGetNetworkMulticastKey(
IN LPWSTR NetworkId,
OUT PNM_NETWORK_MULTICASTKEY * NetworkMulticastKey
)
/*++
Routine Description:
Reads network multicast key for networt NetworkId.
Arguments:
NetworkId - Id of the network whose multicast key should be read.
NetworkMulticastKey - A pointer to the variable into which to place
the network multicast key.
Return Value:
ERROR_SUCCESS if the routine succeeds.
A Win32 error code otherwise.
Notes:
Called with the NmpLock held.
--*/
{
PNM_NETWORK_MULTICASTKEY networkMulticastKey;
PLIST_ENTRY entry;
PNM_NETWORK network;
PVOID MulticastKey = NULL;
DWORD MulticastKeyLength;
DWORD status = ERROR_SUCCESS;
LPWSTR networkId;
PVOID EncryptionKey = NULL;
DWORD EncryptionKeyLength;
PBYTE Salt = NULL;
PBYTE EncryptedMulticastKey = NULL;
DWORD EncryptedMulticastKeyLength;
PBYTE MAC = NULL;
DWORD MACLength;
BOOL found = FALSE;
networkMulticastKey = MIDL_user_allocate(sizeof(NM_NETWORK_MULTICASTKEY));
if (networkMulticastKey == NULL)
{
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to allocate %1!u! bytes to marshall "
"encrypted multicast key.\n",
sizeof(NM_NETWORK_MULTICASTKEY)
);
return(ERROR_NOT_ENOUGH_MEMORY);
}
ZeroMemory(networkMulticastKey, sizeof(NM_NETWORK_MULTICASTKEY));
for (entry = NmpNetworkList.Flink;
entry != &NmpNetworkList;
entry = entry->Flink
)
{
network = CONTAINING_RECORD(entry, NM_NETWORK, Linkage);
networkId = (LPWSTR) OmObjectId(network);
if (wcscmp(NetworkId, networkId) == 0)
{
found = TRUE;
if (network->EncryptedMulticastKey != NULL)
{
//
// Set MulticastKeyExpires
//
networkMulticastKey->MulticastKeyExpires =
network->MulticastKeyExpires;
//
// Set EncryptedMulticastKey
//
status = NmpUnprotectData(network->EncryptedMulticastKey,
network->EncryptedMulticastKeyLength,
&MulticastKey,
&MulticastKeyLength
);
if (status != ERROR_SUCCESS)
{
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to decrypt multicast key "
"for network %1!ws!, status %2!u!.\n",
networkId,
status
);
goto error_exit;
}
status = NmpDeriveClusterKey(
networkId,
NM_WCSLEN(networkId),
&EncryptionKey,
&EncryptionKeyLength
);
if (status != ERROR_SUCCESS)
{
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to derive cluster key for "
"network %1!ws!, status %2!u!.\n",
networkId, status
);
goto error_exit;
}
MACLength = NMP_MAC_DATA_LENGTH_EXPECTED;
status = NmpEncryptDataAndCreateMAC(
NmCryptServiceProvider,
NMP_ENCRYPT_ALGORITHM,
NMP_KEY_LENGTH,
MulticastKey, // Data
MulticastKeyLength, // Data length
EncryptionKey,
EncryptionKeyLength,
TRUE, // Create salt
&Salt,
NMP_SALT_BUFFER_LEN,
&EncryptedMulticastKey,
&EncryptedMulticastKeyLength,
&MAC,
&MACLength
);
if (status != ERROR_SUCCESS)
{
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to "
"encrypt data or generate MAC for "
"network %1!ws!, status %2!u!.\n",
networkId,
status
);
goto error_exit;
}
networkMulticastKey->EncryptedMulticastKey =
MIDL_user_allocate(EncryptedMulticastKeyLength);
if (networkMulticastKey->EncryptedMulticastKey == NULL) {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to allocate %1!u! bytes "
"for encrypted multicast key.\n",
EncryptedMulticastKeyLength
);
status = ERROR_NOT_ENOUGH_MEMORY;
goto error_exit;
}
CopyMemory(networkMulticastKey->EncryptedMulticastKey,
EncryptedMulticastKey,
EncryptedMulticastKeyLength
);
networkMulticastKey->EncryptedMulticastKeyLength =
EncryptedMulticastKeyLength;
//
// Set Salt
//
networkMulticastKey->Salt =
MIDL_user_allocate(NMP_SALT_BUFFER_LEN);
if (networkMulticastKey->Salt == NULL) {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to allocate %1!u! bytes "
"for encrypted multicast key salt.\n",
NMP_SALT_BUFFER_LEN
);
status = ERROR_NOT_ENOUGH_MEMORY;
goto error_exit;
}
CopyMemory(networkMulticastKey->Salt,
Salt,
NMP_SALT_BUFFER_LEN
);
networkMulticastKey->SaltLength =
NMP_SALT_BUFFER_LEN;
//
// Set MAC
//
networkMulticastKey->MAC =
MIDL_user_allocate(MACLength);
if (networkMulticastKey->MAC == NULL) {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to allocate %1!u! bytes "
"for encrypted multicast key MAC.\n",
MACLength
);
status = ERROR_NOT_ENOUGH_MEMORY;
goto error_exit;
}
CopyMemory(networkMulticastKey->MAC,
MAC,
MACLength
);
networkMulticastKey->MACLength =
MACLength;
//
// release MulticastKey
//
if (MulticastKey != NULL)
{
RtlSecureZeroMemory(MulticastKey, MulticastKeyLength);
LocalFree(MulticastKey);
MulticastKey = NULL;
}
//
// release EncryptionKey
//
if (EncryptionKey != NULL)
{
RtlSecureZeroMemory(EncryptionKey, EncryptionKeyLength);
LocalFree(EncryptionKey);
EncryptionKey = NULL;
}
} // if (network->EncryptedMulticastKey != NULL)
else {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Network %1!ws! has no multicast key.\n",
networkId
);
}
break;
} // if (wcscmp(NetworkId, networkId) == 0)
} // for
if (found == FALSE)
{
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Unable to find network %1!ws!.\n",
networkId
);
status = ERROR_CLUSTER_NETWORK_NOT_FOUND;
goto error_exit;
}
*NetworkMulticastKey = networkMulticastKey;
error_exit:
if (MulticastKey != NULL)
{
RtlSecureZeroMemory(MulticastKey, MulticastKeyLength);
LocalFree(MulticastKey);
MulticastKey = NULL;
}
if (EncryptionKey != NULL)
{
RtlSecureZeroMemory(EncryptionKey, EncryptionKeyLength);
LocalFree(EncryptionKey);
EncryptionKey = NULL;
}
if (EncryptedMulticastKey != NULL)
{
HeapFree(GetProcessHeap(), 0, EncryptedMulticastKey);
}
if (Salt != NULL)
{
HeapFree(GetProcessHeap(), 0, Salt);
}
if (MAC != NULL)
{
HeapFree(GetProcessHeap(), 0, MAC);
}
if (status != ERROR_SUCCESS)
{
NmpFreeNetworkMulticastKey(networkMulticastKey
);
}
return (status);
} // NmpGetNetworkMulticastKey
/////////////////////////////////////////////////////////////////////////////
//
// Miscellaneous routines
//
/////////////////////////////////////////////////////////////////////////////
DWORD
NmpRegisterNetwork(
IN PNM_NETWORK Network,
IN BOOLEAN RetryOnFailure
)
/*++
Routine Description:
Registers a network and the associated interfaces with the
cluster transport and brings the network online.
Arguments:
Network - A pointer to the network to register.
Return Value:
ERROR_SUCCESS if successful.
A Win32 error code otherwise.
Notes:
Called with the NmpLock held.
--*/
{
PLIST_ENTRY entry;
PNM_INTERFACE netInterface;
DWORD status = ERROR_SUCCESS;
DWORD tempStatus;
PVOID tdiAddress = NULL;
ULONG tdiAddressLength = 0;
LPWSTR networkId = (LPWSTR) OmObjectId(Network);
PVOID tdiAddressInfo = NULL;
ULONG tdiAddressInfoLength = 0;
DWORD responseLength;
PNM_INTERFACE localInterface = Network->LocalInterface;
BOOLEAN restricted = FALSE;
BOOLEAN registered = FALSE;
if (Network->LocalInterface != NULL) {
if (!NmpIsNetworkRegistered(Network)) {
//
// Register the network
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Registering network %1!ws! (%2!ws!) with cluster "
"transport.\n",
networkId,
OmObjectName(Network)
);
if (!NmpIsNetworkForInternalUse(Network)) {
restricted = TRUE;
}
status = ClusnetRegisterNetwork(
NmClusnetHandle,
Network->ShortId,
Network->Priority,
restricted
);
if (status == ERROR_SUCCESS) {
registered = TRUE;
//
// Bring the network online.
//
ClRtlLogPrint(LOG_NOISE,
"[NM] Bringing network %1!ws! online.\n",
networkId
);
status = ClRtlBuildTcpipTdiAddress(
localInterface->Address,
localInterface->ClusnetEndpoint,
&tdiAddress,
&tdiAddressLength
);
if (status == ERROR_SUCCESS) {
ClRtlQueryTcpipInformation(
NULL,
NULL,
&tdiAddressInfoLength
);
tdiAddressInfo = LocalAlloc(
LMEM_FIXED,
tdiAddressInfoLength
);
if (tdiAddressInfo != NULL) {
responseLength = tdiAddressInfoLength;
status = ClusnetOnlineNetwork(
NmClusnetHandle,
Network->ShortId,
L"\\Device\\Udp",
tdiAddress,
tdiAddressLength,
localInterface->AdapterId,
tdiAddressInfo,
&responseLength
);
if (status != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Cluster transport failed to bring "
"network %1!ws! online, status %2!u!.\n",
networkId,
status
);
}
else {
CL_ASSERT(responseLength == tdiAddressInfoLength);
}
LocalFree(tdiAddressInfo);
}
else {
status = ERROR_NOT_ENOUGH_MEMORY;
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to allocate memory to register "
"network %1!ws! with cluster transport.\n",
networkId
);
}
LocalFree(tdiAddress);
}
else {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to build address to register "
"network %1!ws! withh cluster transport, "
"status %2!u!.\n",
networkId,
status
);
}
}
else {
ClRtlLogPrint(LOG_CRITICAL,
"[NM] Failed to register network %1!ws! with cluster "
"transport, status %2!u!.\n",
networkId,
status
);
}
if (status == ERROR_SUCCESS) {
Network->Flags |= NM_FLAG_NET_REGISTERED;
Network->RegistrationRetryTimeout = 0;
//
// Start multicast.
//
NmpStartMulticast(Network, NmStartMulticastDynamic);
}
else {
WCHAR string[16];
wsprintfW(&(string[0]), L"%u", status);
CsLogEvent2(
LOG_UNUSUAL,
NM_EVENT_REGISTER_NETWORK_FAILED,
OmObjectName(Network),
string
);
if (registered) {
NmpDeregisterNetwork(Network);
}
//
// Retry if the error is transient.
//
if ( RetryOnFailure &&
( (status == ERROR_INVALID_NETNAME) ||
(status == ERROR_NOT_ENOUGH_MEMORY) ||
(status == ERROR_NO_SYSTEM_RESOURCES)
)
)
{
NmpStartNetworkRegistrationRetryTimer(Network);
status = ERROR_SUCCESS;
}
return(status);
}
}
//
// Register the network's interfaces.
//
for (entry = Network->InterfaceList.Flink;
entry != &(Network->InterfaceList);
entry = entry->Flink
)
{
netInterface = CONTAINING_RECORD(
entry,
NM_INTERFACE,
NetworkLinkage
);
if (!NmpIsInterfaceRegistered(netInterface)) {
tempStatus = NmpRegisterInterface(
netInterface,
RetryOnFailure
);
if (tempStatus != ERROR_SUCCESS) {
status = tempStatus;
}
}
}
}
return(status);
} // NmpRegisterNetwork
VOID
NmpDeregisterNetwork(
IN PNM_NETWORK Network
)
/*++
Routine Description:
Deregisters a network and the associated interfaces from the
cluster transport.
Arguments:
Network - A pointer to the network to deregister.
Return Value:
None.
Notes:
Called with the NmpLock held.
--*/
{
DWORD status;
PNM_INTERFACE netInterface;
PLIST_ENTRY entry;
ClRtlLogPrint(LOG_NOISE,
"[NM] Deregistering network %1!ws! (%2!ws!) from cluster transport.\n",
OmObjectId(Network),
OmObjectName(Network)
);
status = ClusnetDeregisterNetwork(
NmClusnetHandle,
Network->ShortId
);
CL_ASSERT(
(status == ERROR_SUCCESS) ||
(status == ERROR_CLUSTER_NETWORK_NOT_FOUND)
);
//
// Mark all of the network's interfaces as deregistered.
//
for (entry = Network->InterfaceList.Flink;
entry != &(Network->InterfaceList);
entry = entry->Flink
)
{
netInterface = CONTAINING_RECORD(entry, NM_INTERFACE, NetworkLinkage);
netInterface->Flags &= ~NM_FLAG_IF_REGISTERED;
}
//
// Mark the network as deregistered
//
Network->Flags &= ~NM_FLAG_NET_REGISTERED;
return;
} // NmpDeregisterNetwork
VOID
NmpInsertInternalNetwork(
PNM_NETWORK Network
)
/*++
Routine Description:
Inserts a network into internal networks list based on its priority.
Arguments:
Network - A pointer to the network object to be inserted.
Return Value:
None.
Notes:
Called with the NmpLock held.
--*/
{
PLIST_ENTRY entry;
PNM_NETWORK network;
//
// Maintain internal networks in highest to lowest
// (numerically lowest to highest) priority order.
//
for (entry = NmpInternalNetworkList.Flink;
entry != &NmpInternalNetworkList;
entry = entry->Flink
)
{
network = CONTAINING_RECORD(entry, NM_NETWORK, InternalLinkage);
if (Network->Priority < network->Priority) {
break;
}
}
//
// Insert the network in front of this entry.
//
InsertTailList(entry, &(Network->InternalLinkage));
return;
} // NmpInsertNetwork
DWORD
NmpValidateNetworkRoleChange(
PNM_NETWORK Network,
CLUSTER_NETWORK_ROLE NewRole
)
{
if ( !(NewRole & ClusterNetworkRoleInternalUse) &&
NmpIsNetworkForInternalUse(Network)
)
{
//
// This change eliminates an internal network. This is only
// legal if we would still have at least one internal network
// between all active nodes.
//
if ((NmpInternalNetworkCount < 2) || !NmpVerifyConnectivity(Network)) {
return(ERROR_CLUSTER_LAST_INTERNAL_NETWORK);
}
}
if ( ( !(NewRole & ClusterNetworkRoleClientAccess) )
&&
NmpIsNetworkForClientAccess(Network)
)
{
BOOL hasDependents;
//
// This change eliminates a public network. This is only
// legal if there are no dependencies (IP address resources) on
// the network.
//
NmpReleaseLock();
hasDependents = FmCheckNetworkDependency(OmObjectId(Network));
NmpAcquireLock();
if (hasDependents) {
return(ERROR_CLUSTER_NETWORK_HAS_DEPENDENTS);
}
}
return(ERROR_SUCCESS);
} // NmpValidateNetworkRoleChange
BOOLEAN
NmpVerifyNodeConnectivity(
PNM_NODE Node1,
PNM_NODE Node2,
PNM_NETWORK ExcludedNetwork
)
{
PLIST_ENTRY ifEntry1, ifEntry2;
PNM_NETWORK network;
PNM_INTERFACE interface1, interface2;
for (ifEntry1 = Node1->InterfaceList.Flink;
ifEntry1 != &(Node1->InterfaceList);
ifEntry1 = ifEntry1->Flink
)
{
interface1 = CONTAINING_RECORD(
ifEntry1,
NM_INTERFACE,
NodeLinkage
);
network = interface1->Network;
if ( (network != ExcludedNetwork) &&
NmpIsNetworkForInternalUse(network)
)
{
for (ifEntry2 = Node2->InterfaceList.Flink;
ifEntry2 != &(Node2->InterfaceList);
ifEntry2 = ifEntry2->Flink
)
{
interface2 = CONTAINING_RECORD(
ifEntry2,
NM_INTERFACE,
NodeLinkage
);
if (interface2->Network == interface1->Network) {
ClRtlLogPrint(LOG_NOISE,
"[NM] nodes %1!u! & %2!u! are connected over "
"network %3!ws!\n",
Node1->NodeId,
Node2->NodeId,
OmObjectId(interface1->Network)
);
return(TRUE);
}
}
}
}
ClRtlLogPrint(LOG_NOISE,
"[NM] Nodes %1!u! & %2!u! are not connected over any internal "
"networks\n",
Node1->NodeId,
Node2->NodeId
);
return(FALSE);
} // NmpVerifyNodeConnectivity
BOOLEAN
NmpVerifyConnectivity(
PNM_NETWORK ExcludedNetwork
)
{
PLIST_ENTRY node1Entry, node2Entry;
PNM_NODE node1, node2;
ClRtlLogPrint(LOG_NOISE, "[NM] Verifying connectivity\n");
for (node1Entry = NmpNodeList.Flink;
node1Entry != &NmpNodeList;
node1Entry = node1Entry->Flink
)
{
node1 = CONTAINING_RECORD(
node1Entry,
NM_NODE,
Linkage
);
if (NM_NODE_UP(node1)) {
for (node2Entry = node1->Linkage.Flink;
node2Entry != &NmpNodeList;
node2Entry = node2Entry->Flink
)
{
node2 = CONTAINING_RECORD(
node2Entry,
NM_NODE,
Linkage
);
if (NM_NODE_UP(node2)) {
ClRtlLogPrint(LOG_NOISE,
"[NM] Verifying nodes %1!u! & %2!u! are connected\n",
node1->NodeId,
node2->NodeId
);
if (!NmpVerifyNodeConnectivity(
node1,
node2,
ExcludedNetwork
)
)
{
return(FALSE);
}
}
}
}
}
return(TRUE);
} // NmpVerifyConnectivity
VOID
NmpIssueClusterPropertyChangeEvent(
VOID
)
{
DWORD status;
DWORD valueLength = 0;
DWORD valueSize = 0;
PWCHAR clusterName = NULL;
//
// The notification API expects a
// cluster name to be associated with this event.
//
status = NmpQueryString(
DmClusterParametersKey,
CLUSREG_NAME_CLUS_NAME,
REG_SZ,
&clusterName,
&valueLength,
&valueSize
);
if (status == ERROR_SUCCESS) {
ClusterEventEx(
CLUSTER_EVENT_PROPERTY_CHANGE,
EP_CONTEXT_VALID | EP_FREE_CONTEXT,
clusterName
);
//
// clusterName will be freed by the event processing code.
//
}
else {
ClRtlLogPrint(LOG_WARNING,
"[NM] Failed to issue cluster property change event, "
"status %1!u!.\n",
status
);
}
return;
} // NmpIssueClusterPropertyChangeEvent
DWORD
NmpMarshallObjectInfo(
IN const PRESUTIL_PROPERTY_ITEM PropertyTable,
IN PVOID ObjectInfo,
OUT PVOID * PropertyList,
OUT LPDWORD PropertyListSize
)
{
DWORD status;
PVOID propertyList = NULL;
DWORD propertyListSize = 0;
DWORD bytesReturned = 0;
DWORD bytesRequired = 0;
status = ClRtlPropertyListFromParameterBlock(
PropertyTable,
NULL,
&propertyListSize,
(LPBYTE) ObjectInfo,
&bytesReturned,
&bytesRequired
);
if (status != ERROR_MORE_DATA) {
CL_ASSERT(status != ERROR_SUCCESS);
return(status);
}
CL_ASSERT(bytesRequired > 0);
propertyList = MIDL_user_allocate(bytesRequired);
if (propertyList == NULL) {
return(ERROR_NOT_ENOUGH_MEMORY);
}
propertyListSize = bytesRequired;
status = ClRtlPropertyListFromParameterBlock(
PropertyTable,
propertyList,
&propertyListSize,
(LPBYTE) ObjectInfo,
&bytesReturned,
&bytesRequired
);
if (status != ERROR_SUCCESS) {
CL_ASSERT(status != ERROR_MORE_DATA);
MIDL_user_free(propertyList);
}
else {
CL_ASSERT(bytesReturned == propertyListSize);
*PropertyList = propertyList;
*PropertyListSize = bytesReturned;
}
return(status);
} // NmpMarshallObjectInfo
VOID
NmpReferenceNetwork(
PNM_NETWORK Network
)
{
OmReferenceObject(Network);
return;
}
VOID
NmpDereferenceNetwork(
PNM_NETWORK Network
)
{
OmDereferenceObject(Network);
return;
}
PNM_NETWORK
NmpReferenceNetworkByAddress(
LPWSTR NetworkAddress,
LPWSTR NetworkMask
)
/*++
Notes:
Called with NM lock held.
--*/
{
PNM_NETWORK network;
PLIST_ENTRY entry;
for ( entry = NmpNetworkList.Flink;
entry != &NmpNetworkList;
entry = entry->Flink
)
{
network = CONTAINING_RECORD(entry, NM_NETWORK, Linkage);
if ((lstrcmpW(network->Address, NetworkAddress) == 0) &&
(lstrcmpW(network->AddressMask, NetworkMask) == 0)) {
NmpReferenceNetwork(network);
return(network);
}
}
return(NULL);
} // NmpReferenceNetworkByAddress
PNM_NETWORK
NmpReferenceNetworkByRemoteAddress(
LPWSTR RemoteAddress
)
/*++
Routine Description:
Search for the network object whose address and subnet mask
match RemoteAddress. Reference and return that network object.
Arguments:
RemoteAddress - remote network address
Return value:
Reference network object, or NULL if no match found
Notes:
Called with NM lock held.
--*/
{
ULONG remoteAddress;
PNM_NETWORK network;
PLIST_ENTRY entry;
DWORD error;
error = ClRtlTcpipStringToAddress(RemoteAddress, &remoteAddress);
if (error != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to parse remote address %1!ws!, error %2!u!.\n",
RemoteAddress, error
);
return(NULL);
}
for ( entry = NmpNetworkList.Flink;
entry != &NmpNetworkList;
entry = entry->Flink
)
{
ULONG networkAddress;
ULONG networkMask;
network = CONTAINING_RECORD(entry, NM_NETWORK, Linkage);
if (network->Address == NULL || network->AddressMask == NULL) {
continue;
}
error = ClRtlTcpipStringToAddress(network->Address, &networkAddress);
if (error != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to parse network address %1!ws!, error %2!u!.\n",
network->Address, error
);
continue;
}
error = ClRtlTcpipStringToAddress(network->AddressMask, &networkMask);
if (error != ERROR_SUCCESS) {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to parse network address mask %1!ws!, error %2!u!.\n",
network->AddressMask, error
);
continue;
}
if (ClRtlAreTcpipAddressesOnSameSubnet(
remoteAddress,
networkAddress,
networkMask
)) {
NmpReferenceNetwork(network);
return(network);
}
}
return(NULL);
} // NmpReferenceNetworkByRemoteAddress
BOOLEAN
NmpCheckForNetwork(
VOID
)
/*++
Routine Description:
Checks whether at least one network on this node configured for MSCS
has media sense.
Arguments:
None.
Return Value:
TRUE if a viable network is found. FALSE otherwise.
Notes:
Called with and returns with no locks held.
--*/
{
PLIST_ENTRY entry;
PNM_NETWORK network;
BOOLEAN haveNetwork = FALSE;
DWORD lockRetries = 3;
BOOL lockAcquired = FALSE;
//
// In order to examine our network interfaces, we need to
// acquire the NM lock, but if the NM lock is tied up for
// a long time (e.g. a local transaction with a lost MNS
// share), then we don't want to block arbitration forever.
// Try to obtain the lock four times, sleeping 150 msecs before
// retries, for a total of approximately one half second.
//
lockAcquired = TryEnterCriticalSection(&NmpLock);
while (!lockAcquired && lockRetries-- > 0) {
Sleep(150);
lockAcquired = TryEnterCriticalSection(&NmpLock);
}
if (!lockAcquired) {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Failed to acquire NM lock while checking "
"networks prior to arbitration. Assuming we have "
"network connectivity to avoid further arbitration "
"delay.\n"
);
return(TRUE);
}
for (entry = NmpNetworkList.Flink;
entry != &NmpNetworkList;
entry = entry->Flink
)
{
network = CONTAINING_RECORD(
entry,
NM_NETWORK,
Linkage
);
// if a network's local interface is disabled, it is not
// considered a viable network. in this case the
// LocalInterface field is NULL.
if (network->LocalInterface != NULL) {
if (NmpVerifyLocalInterfaceConnected(network->LocalInterface)) {
haveNetwork = TRUE;
break;
} else {
ClRtlLogPrint(LOG_UNUSUAL,
"[NM] Network adapter %1!ws! with address %2!ws! "
"reported not connected.\n",
network->LocalInterface->AdapterId,
network->LocalInterface->Address
);
}
}
}
NmpReleaseLock();
if (!haveNetwork) {
SetLastError(ERROR_NETWORK_NOT_AVAILABLE);
}
return(haveNetwork);
} // NmpCheckForNetwork
| 29.398101 | 112 | 0.473778 |
8d4664fa0efa4c80e0227a8c5f2f7c7efb7c6d56 | 609 | h | C | Platforms/Shared/Orbital.Video.D3D12.Native/Texture.h | reignstudios/Orbital-Framework | 76a5e6197cd86a4813d402f790aca24a766d8492 | [
"MIT"
] | 35 | 2019-11-05T01:35:59.000Z | 2021-11-20T17:16:13.000Z | Platforms/Shared/Orbital.Video.D3D12.Native/Texture.h | reignstudios/Orbital-Framework | 76a5e6197cd86a4813d402f790aca24a766d8492 | [
"MIT"
] | null | null | null | Platforms/Shared/Orbital.Video.D3D12.Native/Texture.h | reignstudios/Orbital-Framework | 76a5e6197cd86a4813d402f790aca24a766d8492 | [
"MIT"
] | 3 | 2020-01-27T05:42:34.000Z | 2021-05-12T11:42:25.000Z | #pragma once
#include "Device.h"
struct TextureNode
{
ID3D12Resource* resource;
ID3D12DescriptorHeap* shaderResourceHeap;
ID3D12DescriptorHeap* renderTargetResourceHeap;
ID3D12DescriptorHeap* randomAccessResourceHeap;
D3D12_CPU_DESCRIPTOR_HANDLE renderTargetResourceDescCPUHandle;
D3D12_RESOURCE_STATES resourceState;
};
struct Texture
{
Device* device;
TextureMode mode;
TextureNode* nodes;
DXGI_FORMAT format;
DXGI_SAMPLE_DESC msaaSampleDesc;
};
void Orbital_Video_D3D12_Texture_ChangeState(Texture* handle, UINT nodeIndex, D3D12_RESOURCE_STATES state, ID3D12GraphicsCommandList* commandList); | 26.478261 | 147 | 0.848933 |
8d6f3754638eb2273eb3babb072bca1ef66d5060 | 413 | c | C | mwc/romana/relic/d/usr/src/examples/frexp.c | gspu/Coherent | 299bea1bb52a4dcc42a06eabd5b476fce77013ef | [
"BSD-3-Clause"
] | 20 | 2019-10-10T14:14:56.000Z | 2022-02-24T02:54:38.000Z | mwc/romana/relic/d/usr/src/examples/frexp.c | gspu/Coherent | 299bea1bb52a4dcc42a06eabd5b476fce77013ef | [
"BSD-3-Clause"
] | null | null | null | mwc/romana/relic/d/usr/src/examples/frexp.c | gspu/Coherent | 299bea1bb52a4dcc42a06eabd5b476fce77013ef | [
"BSD-3-Clause"
] | 1 | 2022-03-25T18:38:37.000Z | 2022-03-25T18:38:37.000Z | #include <stdio.h>
main()
{
extern char *gets();
extern double frexp(), atof();
double real, fraction;
int ep;
char string[64];
for (;;) {
printf("Enter number: ");
if (gets(string) == NULL)
break;
real = atof(string);
fraction = frexp(real, &ep);
printf("%lf is the fraction of %lf\n",
fraction, real);
printf("%d is the binary exponent of %lf\n",
ep, real);
}
putchar('\n');
}
| 15.296296 | 46 | 0.590799 |
f214544896afa349ada9d6597170cecaa322d0c5 | 5,475 | c | C | src/glue.c | hsinshengliu/Xmodem6 | 832c068162e431369ab066715e32fb3748dcc2f9 | [
"MIT"
] | null | null | null | src/glue.c | hsinshengliu/Xmodem6 | 832c068162e431369ab066715e32fb3748dcc2f9 | [
"MIT"
] | null | null | null | src/glue.c | hsinshengliu/Xmodem6 | 832c068162e431369ab066715e32fb3748dcc2f9 | [
"MIT"
] | null | null | null | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdbool.h>
#include <unistd.h>
#include <windows.h>
#include "sp.h"
#include "xmodem.h"
#define LOG_LEVEL_ERR 0
#define LOG_LEVEL_WARN 1
#define LOG_LEVEL_INFO 2
#define LOG_LEVEL_DBG 3
static int log_level = LOG_LEVEL_ERR;
#define log_level_set(ll) (log_level = ll)
#define log_err(fmt, ...) \
do { if(log_level >= LOG_LEVEL_ERR) printf(fmt, __VA_ARGS__); } while(0)
#define log_warn(fmt, ...) \
do { if(log_level >= LOG_LEVEL_WARN) printf(fmt, __VA_ARGS__); } while(0)
#define log_info(fmt, ...) \
do { if(log_level >= LOG_LEVEL_INFO) printf(fmt, __VA_ARGS__); } while(0)
#define log_dbg(fmt, ...) \
do { if(log_level >= LOG_LEVEL_DBG) printf(fmt, __VA_ARGS__); } while(0)
static bool keep = true;
static int is_xfer_keep(void)
{
return (keep == true)?1:0;
}
static BOOL WINAPI console_handler(DWORD dwType)
{
switch(dwType)
{
case CTRL_BREAK_EVENT:
{
log_warn("halt (%s).\n", "ctrl-BREAK");
keep = false;
}
break;
case CTRL_C_EVENT:
{
log_warn("halt (%s).\n", "ctrl-C");
keep = false;
}
break;
default:
{
log_dbg("some other event (%ld)\n", dwType);
}
break;
}
return TRUE;
}
int main(int argc, char* argv[])
{
bool usage = (argc >= 2)?false:true;
unsigned long baud = 0;
int port_number = 0;
const short WAITING_TIME_MIN = 1;
const short WAITING_TIME_MAX = 1*60*60;
const short WAITING_TIME_DFT = 6;
short waiting_time = WAITING_TIME_DFT;
bool is_query_only = false;
char fn[260] = {'\0'};
bool is_receiver = false;
bool is_xmodem_1k = false;
bool verbose = false;
const char* fmt = "b:f:p:w:rxvqkh";
bool has_error = false;
int opt = '\0';
while((opt = getopt(argc, argv, fmt)) != -1)
{
switch(opt)
{
case 'b':
{
baud = strtoul(optarg, NULL, 0);
}
break;
case 'p':
{
port_number = (int)strtoul(optarg, NULL, 0);
}
break;
case 'w':
{
waiting_time = (short)strtol(optarg, NULL, 0);
if(waiting_time < WAITING_TIME_MIN || waiting_time > WAITING_TIME_MAX)
{
has_error = true;
}
}
break;
case 'f':
{
memset(fn, '\0', sizeof(fn));
strncpy(fn, optarg, sizeof(fn)-sizeof(char));
}
break;
case 'r':
{
is_receiver = true; //i.e. receiver
}
break;
case 'x':
{
is_receiver = false; //i.e. transmitter
}
break;
case 'q':
{
is_query_only = true;
}
break;
case 'k':
{
is_xmodem_1k = true;
}
break;
case 'v':
{
verbose = true;
}
break;
case 'h':
{
usage = true;
}
break;
case '?':
default:
{
has_error = true;
}
break;
}
}
if(usage == true || has_error == true)
{
printf("xmodem6 [-h]\n");
printf(" [-q]\n");
printf(" [-v] [-p port_number] [-b baud_rate] [-w waiting_time] [-f fn] [-r|-x] [-k]\n");
printf("\n");
printf(" -h : show usage\n");
printf(" -q : query existing serial port\n");
printf(" -v : verbose\n");
printf(" -p port_number : specify serial port number, such as 6 (i.e. \\\\.\\COM6)\n");
printf(" -b baud_rate : specify baud rate, such as 115200\n");
printf(" -w waiting_time: specify waiting time in seconds (from %hd to %hd), such as %hd (by default)\n", WAITING_TIME_MIN, WAITING_TIME_MAX, WAITING_TIME_DFT);
printf(" -f fn : specify the filename, such as input.txt or \"C:\\Users\\Leo\\Downloads\\sample data\\output.txt\"\n");
printf(" -r : lauch xmodem receiver\n");
printf(" -x : lauch xmodem transmitter\n");
printf(" -k : lauch xmodem transmitter using XMODEM-1K, otherwise, XMODEM-CRC (by default)\n");
return EXIT_SUCCESS;
}
if(verbose == true)
{
sp_verb_set();
xmodem_verb_set();
log_level_set(LOG_LEVEL_DBG);
}
if(is_query_only == true || port_number == 0)
{
int* port_number_list = NULL;
int port_cnt = 0;
int qret = sp_query(&port_number_list, &port_cnt);
if(qret == 0)
{
if(is_query_only == true)
{
int k = 0;
for(k = 0; k < port_cnt; k++)
{
printf("port_number_list[%d] = %d\n", k, port_number_list[k]);
}
}
if(port_cnt > 0)
{
if(port_number == 0)
{
if(is_receiver == true)
{
port_number = port_number_list[0];
}
else
{
port_number = port_number_list[port_cnt-1];
}
}
}
else
{
log_err("no available serial port (%d)!\n", port_cnt);
}
if(port_number_list != NULL)
{
free(port_number_list);
}
}
}
log_info("is_query_only = %s; baud = %ld; port_number = %d; waiting_time = %d; is_receiver = %s; is_xmodem_1k = %s, fn = %s\n",
is_query_only==true?"true":"false",
baud,
port_number,
waiting_time,
is_receiver==true?"true":"false",
is_xmodem_1k==true?"true":"false",
fn);
if(is_query_only == true)
{
return EXIT_SUCCESS;
}
if (!SetConsoleCtrlHandler((PHANDLER_ROUTINE)console_handler,TRUE))
{
log_err("fail to set signal handler (%p)!\n", console_handler);
return EXIT_FAILURE;
}
int xret = -1;
HANDLE hComm = sp_open(port_number, baud);
if(is_receiver == true)
{
xret = xmodem_receive(hComm, waiting_time, fn, is_xfer_keep);
}
else
{
xret = xmodem_transmit(hComm, waiting_time, fn, is_xmodem_1k, is_xfer_keep);
}
sp_close(hComm);
log_dbg("xret = %d\n", xret);
return (xret == 0)?EXIT_SUCCESS:EXIT_FAILURE;
}
| 21.640316 | 169 | 0.595616 |
3ebac542c5001f3726b39a4bc33478d8895b869d | 3,315 | h | C | src/ManifestAssetStore.h | dinodeck/dinodeck | 091f0e31ba9e921eab7fa6dd219f5c40ea3ed78c | [
"MIT"
] | 110 | 2016-06-23T23:07:23.000Z | 2022-03-25T03:18:16.000Z | src/ManifestAssetStore.h | dinodeck/dinodeck | 091f0e31ba9e921eab7fa6dd219f5c40ea3ed78c | [
"MIT"
] | 9 | 2016-06-24T13:20:01.000Z | 2020-05-05T18:43:46.000Z | src/ManifestAssetStore.h | dinodeck/dinodeck | 091f0e31ba9e921eab7fa6dd219f5c40ea3ed78c | [
"MIT"
] | 23 | 2016-04-26T23:37:13.000Z | 2021-09-27T07:10:08.000Z | #ifndef MANIFESTASSETSTORE_H
#define MANIFESTASSETSTORE_H
#include <map>
#include <string>
#include "IAssetOwner.h"
#include "AssetStore.h"
class Asset;
class DDFile;
class FTTextureFont;
struct lua_State;
//
// An asset store controlled by an manifest file.
//
class ManifestAssetStore : public IAssetOwner
{
public:
enum eOwnerFlags
{
Required,
Optional
};
private:
Asset* mManifest;
AssetStore mAssetStore;
struct AssetOwner
{
const char* id;
IAssetOwner* owner;
eOwnerFlags flags;
AssetOwner() :
owner(NULL), flags(Required) {}
AssetOwner(const char* id, IAssetOwner* owner, eOwnerFlags flags) :
id(id), owner(owner), flags(flags) {}
};
struct AssetDef
{
Asset::eAssetType type;
std::string name;
std::string path;
std::map<std::string, std::string> flags;
AssetDef(Asset::eAssetType type, const char* name, const char* path) :
type(type), name(name), path(path) {}
AssetDef(Asset::eAssetType type, const char* name, const char* path,
std::map<std::string, std::string> flags) :
type(type), name(name), path(path), flags(flags) {}
};
struct FontAsset
{
FTTextureFont* mFont;
DDFile* mFontFile; // The file data needs to be kept in memory!
FontAsset(DDFile* fontFile, FTTextureFont* font) :
mFont(font), mFontFile(fontFile) {}
};
// Who handles what by default
// [.lua] -> Dindeck etc
std::map<std::string, AssetOwner> mAssetOwnerMap;
std::map<std::string, FontAsset> mFontStore;
bool LoadLuaTableToAssetDefs(lua_State* state,
const char* tableName,
std::map<std::string, ManifestAssetStore::AssetDef>& destination);
bool LoadAssetSubTable(lua_State* state, const char* tableName, const char* path);
bool LoadAssetDef(lua_State* state,
std::map<std::string, ManifestAssetStore::AssetDef>& destination,
Asset::eAssetType assetType);
void RemoveAssetsNotInManifest();
static bool AreAssetFlagsEqual(const std::map<std::string, std::string>& a,
const std::map<std::string, std::string>& b);
public:
ManifestAssetStore();
~ManifestAssetStore();
// Callbacks for Assets
virtual bool OnAssetReload(Asset& asset);
virtual void OnAssetDestroyed(Asset& asset);
bool AssetExists(const char* name)
{
return mAssetStore.AssetExists(name);
}
Asset* GetAssetByName(const char* name)
{
return mAssetStore.GetAssetByName(name);
}
bool Reload(std::string manifest); // Copy string is on purpose
bool Reload();
void Clear();
// Used when loading assets from the manifest
void RegisterAssetOwner(const char* name, IAssetOwner* callback);
void RegisterAssetOwner(const char* name, IAssetOwner* callback, eOwnerFlags flags);
FTTextureFont* GetFont(const char* name);
void SetAsNotLoaded(Asset::eAssetType type) { mAssetStore.SetAsNotLoaded(type); }
};
#endif | 30.136364 | 100 | 0.608145 |
e345ad972b02b3bfefedbf2f8725d4779aa285ec | 1,466 | h | C | inetsrv/pop3/admin/p3admin/p3domainenum.h | npocmaka/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 17 | 2020-11-13T13:42:52.000Z | 2021-09-16T09:13:13.000Z | inetsrv/pop3/admin/p3admin/p3domainenum.h | sancho1952007/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 2 | 2020-10-19T08:02:06.000Z | 2020-10-19T08:23:18.000Z | inetsrv/pop3/admin/p3admin/p3domainenum.h | sancho1952007/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 14 | 2020-11-14T09:43:20.000Z | 2021-08-28T08:59:57.000Z | // P3DomainEnum.h : Declaration of the CP3DomainEnum
#ifndef __P3DOMAINENUM_H_
#define __P3DOMAINENUM_H_
#include "resource.h" // main symbols
/////////////////////////////////////////////////////////////////////////////
// CP3DomainEnum
class ATL_NO_VTABLE CP3DomainEnum :
public CComObjectRootEx<CComSingleThreadModel>,
public CComCoClass<CP3DomainEnum, &CLSID_P3DomainEnum>,
public IEnumVARIANT
{
public:
CP3DomainEnum();
virtual ~CP3DomainEnum();
DECLARE_REGISTRY_RESOURCEID(IDR_P3DOMAINENUM)
DECLARE_PROTECT_FINAL_CONSTRUCT()
BEGIN_COM_MAP(CP3DomainEnum)
COM_INTERFACE_ENTRY(IEnumVARIANT)
END_COM_MAP()
// IEnumVARIANT
public:
HRESULT STDMETHODCALLTYPE Next( /* [in] */ ULONG celt, /* [length_is][size_is][out] */ VARIANT __RPC_FAR *rgVar, /* [out] */ ULONG __RPC_FAR *pCeltFetched);
HRESULT STDMETHODCALLTYPE Skip( /* [in] */ ULONG celt);
HRESULT STDMETHODCALLTYPE Reset( void);
HRESULT STDMETHODCALLTYPE Clone( /* [out] */ IEnumVARIANT __RPC_FAR *__RPC_FAR *ppEnum);
// Implementation
public:
HRESULT Init( IUnknown *pIUnk, CP3AdminWorker *pAdminX, IEnumVARIANT *pIEnumVARIANT );
// Attributes
protected:
IUnknown *m_pIUnk;
CP3AdminWorker *m_pAdminX; // This is the object that actually does all the work.
IEnumVARIANT *m_pIEnumVARIANT;// IADsContainer::get__NewEnum for L"IIS://LocalHost/SMTPSVC/1/Domain"
};
#endif //__P3DOMAINENUM_H_
| 31.191489 | 161 | 0.686903 |
e936ea441cb7970b553d957c20f0acf9fc070903 | 227 | h | C | Graphics/resourcemesh.h | mizquierdo97/Graphics | 816a665b5f7729c08d49099a7f19f0c00c9ee4df | [
"MIT"
] | null | null | null | Graphics/resourcemesh.h | mizquierdo97/Graphics | 816a665b5f7729c08d49099a7f19f0c00c9ee4df | [
"MIT"
] | null | null | null | Graphics/resourcemesh.h | mizquierdo97/Graphics | 816a665b5f7729c08d49099a7f19f0c00c9ee4df | [
"MIT"
] | null | null | null | #ifndef RESOURCEMESH_H
#define RESOURCEMESH_H
#include "resource.h"
#include "mesh.h"
class ResourceMesh : public Resource
{
public:
ResourceMesh();
void Load();
Mesh* mesh = nullptr;
};
#endif // RESOURCEMESH_H
| 14.1875 | 36 | 0.700441 |
3a7397eccae2dac6b6304a5218ab120a6c3b8b2e | 1,427 | h | C | inc/ird.h | LCA2-EPFL/iprp | 62af8d5787c5336dceec138aacf5f73f4ac6e110 | [
"MIT"
] | 2 | 2018-06-22T10:01:02.000Z | 2018-09-05T12:10:03.000Z | inc/ird.h | LCA2-EPFL/iprp | 62af8d5787c5336dceec138aacf5f73f4ac6e110 | [
"MIT"
] | null | null | null | inc/ird.h | LCA2-EPFL/iprp | 62af8d5787c5336dceec138aacf5f73f4ac6e110 | [
"MIT"
] | null | null | null | /**\file ird.h
* Header file for IRD
*
* \author Loic Ottet (loic.ottet@epfl.ch)
*/
#ifndef __IPRP_IRD_
#define __IPRP_IRD_
#include <stdbool.h>
#include <stdint.h>
#include "global.h"
#define IPRP_DD_MAX_LOST_PACKETS 1024
#define IPRP_STATS_PATH_LENGTH 58
/* Thread routines */
void* handle_routine(void* arg);
void* si_routine(void* arg);
/* Receiver statistics structure */
typedef struct {
int pkts[IPRP_MAX_INDS];
time_t last_seen[IPRP_MAX_INDS];
int wrong[IPRP_MAX_INDS];
int acc[IPRP_MAX_INDS];
} iprp_receiver_stats_t;
/* Receiver link structure */
typedef struct {
// Info (fixed) vars
IPRP_INADDR src_addr;
uint16_t src_port;
unsigned char snsid[20];
// State (variable) vars
uint32_t list_sn[IPRP_DD_MAX_LOST_PACKETS];
uint32_t high_sn;
time_t last_seen;
// Statistics
iprp_receiver_stats_t stats;
} iprp_receiver_link_t;
#ifdef IPRP_MULTICAST
/* SSM-specific structures */
#ifndef MCAST_JOIN_SOURCE_GROUP
#define MCAST_JOIN_SOURCE_GROUP 46
#endif
struct ip_mreqn {
struct in_addr imr_multiaddr;
struct in_addr imr_address;
int imr_ifindex;
};
struct ip_mreq_source {
struct in_addr imr_multiaddr;
struct in_addr imr_interface;
struct in_addr imr_sourceaddr;
};
// TODO ipv6
#endif
/* Statistics functions */
int stats_store(const char* path, iprp_receiver_link_t *stats);
int stats_load(const char* path, iprp_receiver_link_t *stats);
#endif /* __IPRP_IRD_ */ | 20.681159 | 63 | 0.756833 |
b15e457b6125bf5b5c32ac64ad71f29dbae71b02 | 1,632 | h | C | include/apollo/perfcntrs/PapiCounters.h | gregbolet/apollo | 7c95581478059fd2ec8cd19192ed4c0ec5d4f06d | [
"MIT"
] | null | null | null | include/apollo/perfcntrs/PapiCounters.h | gregbolet/apollo | 7c95581478059fd2ec8cd19192ed4c0ec5d4f06d | [
"MIT"
] | null | null | null | include/apollo/perfcntrs/PapiCounters.h | gregbolet/apollo | 7c95581478059fd2ec8cd19192ed4c0ec5d4f06d | [
"MIT"
] | null | null | null |
#ifndef APOLLO_PAPI_CNTRS_H
#define APOLLO_PAPI_CNTRS_H
#include <stdlib.h>
#include <stdio.h>
#include <string>
#include <omp.h>
#include <mutex>
#include <vector>
#include <map>
#include "papi.h"
#include "apollo/perfcntrs/PerfCounter.h"
#include "util/spinlock.h"
// This class assumes OMP is being used for threading
// We will change this use case in the future once we get something working
// For now, when setting up threads we don't do error handling
class Apollo::PapiCounters : public Apollo::PerfCounter{
public:
PapiCounters(int isMultiplexed, std::vector<std::string> eventNames);
//PapiCounters();
~PapiCounters();
void startThread() override;
void stopThread() override;
void clearAllCntrValues() override;
std::vector<float> getSummaryStats() override;
private:
friend class Apollo::Region;
int isMultiplexed;
int numEvents;
//int runWithCounters;
// Keep our event names in here
std::vector<std::string> event_names_to_track;
// Shared spinlock for setting up threads
mutable util::spinlock thread_lock;
// Map the threadID to the counter value pointers
std::vector<long long*> all_cntr_values;
// Mapping of threadID to eventSet
std::map<int, int> thread_id_to_eventset;
// Mapping of threadID to cntr values
std::map<int, long long*> thread_id_to_cntr_ptr;
// At initialization, convert the string
// event names to their integer codes
int* events_to_track;
};
#endif | 28.137931 | 77 | 0.659314 |
16c46d1bb4f2494cb1572aaf7af5e9c4dfaa5192 | 602 | h | C | ElegantTableViewFramework/ElegantTableViewFramework.h | YJManager/ElegantTableView | 8b35ceded2c987b2152d8003cc3a670a082c99e2 | [
"MIT"
] | 145 | 2017-10-14T01:02:37.000Z | 2018-04-16T16:05:38.000Z | ElegantTableViewFramework/ElegantTableViewFramework.h | YJManager/ElegantTableView | 8b35ceded2c987b2152d8003cc3a670a082c99e2 | [
"MIT"
] | null | null | null | ElegantTableViewFramework/ElegantTableViewFramework.h | YJManager/ElegantTableView | 8b35ceded2c987b2152d8003cc3a670a082c99e2 | [
"MIT"
] | 20 | 2017-12-14T07:00:59.000Z | 2017-12-31T17:36:42.000Z | //
// ElegantTableViewFramework.h
// ElegantTableViewFramework
//
// Created by YJHou on 2017/7/3.
// Copyright © 2017年 MonkeyKing. All rights reserved.
//
#import <UIKit/UIKit.h>
//! Project version number for ElegantTableViewFramework.
FOUNDATION_EXPORT double ElegantTableViewFrameworkVersionNumber;
//! Project version string for ElegantTableViewFramework.
FOUNDATION_EXPORT const unsigned char ElegantTableViewFrameworkVersionString[];
// In this header, you should import all the public headers of your framework using statements like #import <ElegantTableViewFramework/PublicHeader.h>
| 30.1 | 150 | 0.803987 |
df8004b2fe928693226b18494eeace6c1869186b | 25,352 | h | C | test/e2e/test_input/podofo/base/PdfError.h | BlueCannonBall/cppparser | 9ae5f0c21268be6696532cf5b90c0384d6eb4940 | [
"MIT"
] | 50 | 2018-01-12T14:32:26.000Z | 2022-03-30T10:36:30.000Z | test/e2e/test_input/podofo/base/PdfError.h | BlueCannonBall/cppparser | 9ae5f0c21268be6696532cf5b90c0384d6eb4940 | [
"MIT"
] | 8 | 2021-02-18T14:52:08.000Z | 2022-03-09T08:51:39.000Z | test/e2e/test_input/podofo/base/PdfError.h | BlueCannonBall/cppparser | 9ae5f0c21268be6696532cf5b90c0384d6eb4940 | [
"MIT"
] | 12 | 2019-04-02T11:51:47.000Z | 2022-03-07T11:07:39.000Z | /***************************************************************************
* Copyright (C) 2006 by Dominik Seichter *
* domseichter@web.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU Library General Public License as *
* published by the Free Software Foundation; either version 2 of the *
* License, or (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU Library General Public *
* License along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
* *
* In addition, as a special exception, the copyright holders give *
* permission to link the code of portions of this program with the *
* OpenSSL library under certain conditions as described in each *
* individual source file, and distribute linked combinations *
* including the two. *
* You must obey the GNU General Public License in all respects *
* for all of the code used other than OpenSSL. If you modify *
* file(s) with this exception, you may extend this exception to your *
* version of the file(s), but you are not obligated to do so. If you *
* do not wish to do so, delete this exception statement from your *
* version. If you delete this exception statement from all source *
* files in the program, then also delete it here. *
***************************************************************************/
#ifndef _PDF_ERROR_H_
#define _PDF_ERROR_H_
// PdfError.h should not include PdfDefines.h, since it is included by it.
// It should avoid depending on anything defined in PdfDefines.h .
#include "podofoapi.h"
#include <string>
#include <queue>
#include <cstdarg>
#if defined(_MSC_VER) && _MSC_VER <= 1200 // same pragma as in PdfDefines.h which we cannot include here
#pragma warning(disable: 4251)
#pragma warning(disable: 4275)
#endif
/** \file PdfError.h
* Error information and logging is implemented in this file.
*/
namespace PoDoFo {
/** Error Code enum values which are used in PdfError to describe the error.
*
* If you add an error code to this enum, please also add it
* to PdfError::ErrorName() and PdfError::ErrorMessage().
*
* \see PdfError
*/
enum EPdfError {
ePdfError_ErrOk = 0, /**< The default value indicating no error. */
ePdfError_TestFailed, /**< Used in PoDoFo tests, to indicate that a test failed for some reason. */
ePdfError_InvalidHandle, /**< Null pointer was passed, but null pointer is not allowed. */
ePdfError_FileNotFound, /**< A file was not found or cannot be opened. */
ePdfError_InvalidDeviceOperation, /**< Tried to do something unsupported to an I/O device like seek a non-seekable input device */
ePdfError_UnexpectedEOF, /**< End of file was reached but data was expected. */
ePdfError_OutOfMemory, /**< Not enough memory to complete an operation. */
ePdfError_ValueOutOfRange, /**< The specified memory is out of the allowed range. */
ePdfError_InternalLogic, /**< An internal sanity check or assertion failed. */
ePdfError_InvalidEnumValue, /**< An invalid enum value was specified. */
ePdfError_BrokenFile, /**< The file content is broken. */
ePdfError_PageNotFound, /**< The requested page could not be found in the PDF. */
ePdfError_NoPdfFile, /**< The file is no PDF file. */
ePdfError_NoXRef, /**< The PDF file has no or an invalid XRef table. */
ePdfError_NoTrailer, /**< The PDF file has no or an invalid trailer. */
ePdfError_NoNumber, /**< A number was expected in the PDF file, but the read string is no number. */
ePdfError_NoObject, /**< A object was expected and none was found. */
ePdfError_NoEOFToken, /**< The PDF file has no or an invalid EOF marker. */
ePdfError_InvalidTrailerSize, /**< The trailer size is invalid. */
ePdfError_InvalidLinearization, /**< The linearization directory of a web-optimized PDF file is invalid. */
ePdfError_InvalidDataType, /**< The passed datatype is invalid or was not recognized */
ePdfError_InvalidXRef, /**< The XRef table is invalid */
ePdfError_InvalidXRefStream, /**< A XRef steam is invalid */
ePdfError_InvalidXRefType, /**< The XRef type is invalid or was not found */
ePdfError_InvalidPredictor, /**< Invalid or unimplemented predictor */
ePdfError_InvalidStrokeStyle, /**< Invalid stroke style during drawing */
ePdfError_InvalidHexString, /**< Invalid hex string */
ePdfError_InvalidStream, /**< The stream is invalid */
ePdfError_InvalidStreamLength, /**< The stream length is invalid */
ePdfError_InvalidKey, /**< The specified key is invalid */
ePdfError_InvalidName, /**< The specified Name is not valid in this context */
ePdfError_InvalidEncryptionDict, /**< The encryption dictionary is invalid or misses a required key */
ePdfError_InvalidPassword, /**< The password used to open the PDF file was invalid */
ePdfError_InvalidFontFile, /**< The font file is invalid */
ePdfError_InvalidContentStream, /**< The content stream is invalid due to mismatched context pairing or other problems */
ePdfError_UnsupportedFilter, /**< The requested filter is not yet implemented. */
ePdfError_UnsupportedFontFormat, /**< This font format is not supported by PoDoFo. */
ePdfError_ActionAlreadyPresent, /**< An Action was already present when trying to add a Destination */
ePdfError_WrongDestinationType, /**< The requested field is not available for the given destination type */
ePdfError_MissingEndStream, /**< The required token endstream was not found. */
ePdfError_Date, /**< Date/time error */
ePdfError_Flate, /**< Error in zlib */
ePdfError_FreeType, /**< Error in FreeType */
ePdfError_SignatureError, /**< Error in signature */
ePdfError_MutexError, /**< Error during a mutex operation */
ePdfError_UnsupportedImageFormat, /**< This image format is not supported by PoDoFo. */
ePdfError_CannotConvertColor, /**< This color format cannot be converted. */
ePdfError_NotImplemented, /**< This feature is currently not implemented. */
ePdfError_DestinationAlreadyPresent,/**< A destination was already present when trying to add an Action */
ePdfError_ChangeOnImmutable, /**< Changing values on immutable objects is not allowed. */
ePdfError_NotCompiled, /**< This feature was disabled at compile time. */
ePdfError_OutlineItemAlreadyPresent,/**< An outline item to be inserted was already in that outlines tree. */
ePdfError_NotLoadedForUpdate, /**< The document had not been loaded for update. */
ePdfError_CannotEncryptedForUpdate, /**< Cannot load encrypted documents for update. */
ePdfError_Unknown = 0xffff /**< Unknown error */
};
/**
* Used in PdfError::LogMessage to specify the log level.
*
* \see PdfError::LogMessage
*/
enum ELogSeverity {
eLogSeverity_Critical, /**< Critical unexpected error */
eLogSeverity_Error, /**< Error */
eLogSeverity_Warning, /**< Warning */
eLogSeverity_Information, /**< Information message */
eLogSeverity_Debug, /**< Debug information */
eLogSeverity_None, /**< No specified level */
eLogSeverity_Unknown = 0xffff /**< Unknown log level */
};
/** \def PODOFO_RAISE_ERROR( x )
*
* Throw an exception of type PdfError with the error code x, which should be
* one of the values of the enum EPdfError. File and line info are included.
*/
#define PODOFO_RAISE_ERROR( x ) throw ::PoDoFo::PdfError( x, __FILE__, __LINE__ );
/** \def PODOFO_RAISE_ERROR_INFO( x, y )
*
* Throw an exception of type PdfError with the error code x, which should be
* one of the values of the enum EPdfError. File and line info are included.
* Additionally extra information on the error, y is set, which will also be
* output by PdfError::PrintErrorMsg().
* y can be a C string, but can also be a C++ std::string.
*/
#define PODOFO_RAISE_ERROR_INFO( x, y ) throw ::PoDoFo::PdfError( x, __FILE__, __LINE__, y );
/** \def PODOFO_RAISE_LOGIC_IF( x, y )
*
* Evaluate `x' as a binary predicate and if it is true, raise a logic error with the
* info string `y' .
*/
#define PODOFO_RAISE_LOGIC_IF( x, y ) { if (x) throw ::PoDoFo::PdfError( ePdfError_InternalLogic, __FILE__, __LINE__, y ); };
class PODOFO_API PdfErrorInfo {
public:
PdfErrorInfo();
PdfErrorInfo( int line, const char* pszFile, const char* pszInfo );
PdfErrorInfo( int line, const char* pszFile, std::string pszInfo );
PdfErrorInfo( int line, const char* pszFile, const wchar_t* pszInfo );
PdfErrorInfo( const PdfErrorInfo & rhs );
const PdfErrorInfo & operator=( const PdfErrorInfo & rhs );
inline int GetLine() const { return m_nLine; }
inline const std::string & GetFilename() const { return m_sFile; }
inline const std::string & GetInformation() const { return m_sInfo; }
inline const std::wstring & GetInformationW() const { return m_swInfo; }
inline void SetInformation( const char* pszInfo ) { m_sInfo = pszInfo ? pszInfo : ""; }
inline void SetInformation( std::string pszInfo ) { m_sInfo = pszInfo; }
inline void SetInformation( const wchar_t* pszInfo ) { m_swInfo = pszInfo ? pszInfo : L""; }
private:
int m_nLine;
std::string m_sFile;
std::string m_sInfo;
std::wstring m_swInfo;
};
typedef std::deque<PdfErrorInfo> TDequeErrorInfo;
typedef TDequeErrorInfo::iterator TIDequeErrorInfo;
typedef TDequeErrorInfo::const_iterator TCIDequeErrorInfo;
// This is required to generate the documentation with Doxygen.
// Without this define doxygen thinks we have a class called PODOFO_EXCEPTION_API(PODOFO_API) ...
#define PODOFO_EXCEPTION_API_DOXYGEN PODOFO_EXCEPTION_API(PODOFO_API)
/** The error handling class of the PoDoFo library.
* If a method encounters an error,
* a PdfError object is thrown as a C++ exception.
*
* This class does not inherit from std::exception.
*
* This class also provides meaningful error descriptions
* for the error codes which are values of the enum EPdfError,
* which are all codes PoDoFo uses (except the first and last one).
*/
class PODOFO_EXCEPTION_API_DOXYGEN PdfError {
public:
// OC 17.08.2010 New to optionally replace stderr output by a callback:
class LogMessageCallback
{
public:
virtual ~LogMessageCallback() {} // every class with virtual methods needs a virtual destructor
virtual void LogMessage( ELogSeverity eLogSeverity, const char* pszPrefix, const char* pszMsg, va_list & args ) = 0;
virtual void LogMessage( ELogSeverity eLogSeverity, const wchar_t* pszPrefix, const wchar_t* pszMsg, va_list & args ) = 0;
};
/** Set a global static LogMessageCallback functor to replace stderr output in LogMessageInternal.
* \param fLogMessageCallback the pointer to the new callback functor object
* \returns the pointer to the previous callback functor object
*/
static LogMessageCallback* SetLogMessageCallback(LogMessageCallback* fLogMessageCallback);
/** Create a PdfError object initialized to ePdfError_ErrOk.
*/
PdfError();
/** Create a PdfError object with a given error code.
* \param eCode the error code of this object
* \param pszFile the file in which the error has occured.
* Use the compiler macro __FILE__ to initialize the field.
* \param line the line in which the error has occured.
* Use the compiler macro __LINE__ to initialize the field.
* \param pszInformation additional information on this error
*/
PdfError( const EPdfError & eCode, const char* pszFile = NULL, int line = 0,
const char* pszInformation = NULL );
/** Create a PdfError object with a given error code.
* \param eCode the error code of this object
* \param pszFile the file in which the error has occured.
* Use the compiler macro __FILE__ to initialize the field.
* \param line the line in which the error has occured.
* Use the compiler macro __LINE__ to initialize the field.
* \param sInformation additional information on this error
*/
explicit PdfError( const EPdfError & eCode, const char* pszFile, int line,
std::string sInformation );
/** Copy constructor
* \param rhs copy the contents of rhs into this object
*/
PdfError( const PdfError & rhs );
virtual ~PdfError() throw();
/** Assignment operator
* \param rhs another PdfError object
* \returns this object
*/
const PdfError & operator=( const PdfError & rhs );
/** Overloaded assignment operator
* \param eCode a EPdfError code
* \returns this object
*/
const PdfError & operator=( const EPdfError & eCode );
/** Comparison operator, compares 2 PdfError objects
* \param rhs another PdfError object
* \returns true if both objects have the same error code.
*/
bool operator==( const PdfError & rhs );
/** Overloaded comparison operator, compares this PdfError object
* with an error code
* \param eCode an error code (value of the enum EPdfError)
* \returns true if this object has the same error code.
*/
bool operator==( const EPdfError & eCode );
/** Comparison operator, compares 2 PdfError objects
* \param rhs another PdfError object
* \returns true if the objects have different error codes.
*/
bool operator!=( const PdfError & rhs );
/** Overloaded comparison operator, compares this PdfError object
* with an error code
* \param eCode an error code (value of the enum EPdfError)
* \returns true if this object has a different error code.
*/
bool operator!=( const EPdfError & eCode );
/** Return the error code of this object.
* \returns the error code of this object
*/
inline EPdfError GetError() const;
/** Get access to the internal callstack of this error.
* \returns the callstack deque of PdfErrorInfo objects.
*/
inline const TDequeErrorInfo & GetCallstack() const;
/** Set the error code of this object.
* \param eCode the error code of this object
* \param pszFile the filename of the source file causing
* the error or NULL. Typically you will use
* the gcc macro __FILE__ here.
* \param line the line of source causing the error
* or 0. Typically you will use the gcc
* macro __LINE__ here.
* \param sInformation additional information on the error.
* e.g. how to fix the error. This string is intended to
* be shown to the user.
*/
inline void SetError( const EPdfError & eCode, const char* pszFile, int line,
std::string sInformation );
/** Set the error code of this object.
* \param eCode the error code of this object
* \param pszFile the filename of the source file causing
* the error or NULL. Typically you will use
* the gcc macro __FILE__ here.
* \param line the line of source causing the error
* or 0. Typically you will use the gcc
* macro __LINE__ here.
* \param pszInformation additional information on the error,
* e.g. how to fix the error. This string is intended to
* be shown to the user.
*/
inline void SetError( const EPdfError & eCode, const char* pszFile = NULL, int line = 0, const char* pszInformation = NULL );
/** Set additional error information.
* \param pszInformation additional information on the error,
* e.g. how to fix the error. This string is intended to
* be shown to the user.
*/
inline void SetErrorInformation( const char* pszInformation );
/** Set additional error information.
* \param pszInformation additional information on the error,
* e.g. how to fix the error. This string is intended to
* be shown to the user.
*/
inline void SetErrorInformation( const wchar_t* pszInformation );
/** Add callstack information to an error object. Always call this function
* if you get an error object but do not handle the error but throw it again.
*
* \param pszFile the filename of the source file causing
* the error or NULL. Typically you will use
* the gcc macro __FILE__ here.
* \param line the line of source causing the error
* or 0. Typically you will use the gcc
* macro __LINE__ here.
* \param pszInformation additional information on the error,
* e.g. how to fix the error. This string is intended to
* be shown to the user.
*/
inline void AddToCallstack( const char* pszFile = NULL, int line = 0, const char* pszInformation = NULL );
/** Add callstack information to an error object. Always call this function
* if you get an error object but do not handle the error but throw it again.
*
* \param pszFile the filename of the source file causing
* the error or NULL. Typically you will use
* the gcc macro __FILE__ here.
* \param line the line of source causing the error
* or 0. Typically you will use the gcc
* macro __LINE__ here.
* \param sInformation additional information on the error,
* e.g. how to fix the error. This string is intended to
* be shown to the user.
*/
inline void AddToCallstack( const char* pszFile, int line, std::string sInformation );
/** \returns true if an error code was set
* and false if the error code is ePdfError_ErrOk.
*/
inline bool IsError() const;
/** Print an error message to stderr. This includes callstack
* and extra info, if any of either was set.
*/
void PrintErrorMsg() const;
/** Obtain error description.
* \returns a C string describing the error.
*/
const char* what() const;
/** Get the name for a certain error code.
* \returns the name or NULL if no name for the specified
* error code is available.
*/
PODOFO_NOTHROW static const char* ErrorName( EPdfError eCode );
/** Get the error message for a certain error code.
* \returns the error message or NULL if no error
* message for the specified error code
* is available.
*/
static const char* ErrorMessage( EPdfError eCode );
/** Log a message to the logging system defined for PoDoFo.
* \param eLogSeverity the severity of the log message
* \param pszMsg the message to be logged
*/
static void LogMessage( ELogSeverity eLogSeverity, const char* pszMsg, ... );
/** Log a message to the logging system defined for PoDoFo.
* \param eLogSeverity the severity of the log message
* \param pszMsg the message to be logged
*/
static void LogMessage( ELogSeverity eLogSeverity, const wchar_t* pszMsg, ... );
/** Enable or disable logging.
* \param bEnable enable (true) or disable (false)
*/
static void EnableLogging( bool bEnable );
/** Is the display of debugging messages enabled or not?
*/
static bool LoggingEnabled();
/** Log a message to the logging system defined for PoDoFo for debugging.
* \param pszMsg the message to be logged
*/
static void DebugMessage( const char* pszMsg, ... );
/** Enable or disable the display of debugging messages.
* \param bEnable enable (true) or disable (false)
*/
static void EnableDebug( bool bEnable );
/** Is the display of debugging messages enabled or not?
*/
static bool DebugEnabled();
private:
/** Log a message to the logging system defined for PoDoFo.
*
* This call does not check if logging is enabled and always
* prints the error message.
*
* \param eLogSeverity the severity of the log message
* \param pszMsg the message to be logged
*/
static void LogErrorMessage( ELogSeverity eLogSeverity, const char* pszMsg, ... );
/** Log a message to the logging system defined for PoDoFo.
*
* This call does not check if logging is enabled and always
* prints the error message
*
* \param eLogSeverity the severity of the log message
* \param pszMsg the message to be logged
*/
static void LogErrorMessage( ELogSeverity eLogSeverity, const wchar_t* pszMsg, ... );
static void LogMessageInternal( ELogSeverity eLogSeverity, const char* pszMsg, va_list & args );
static void LogMessageInternal( ELogSeverity eLogSeverity, const wchar_t* pszMsg, va_list & args );
private:
EPdfError m_error;
TDequeErrorInfo m_callStack;
static bool s_DgbEnabled;
static bool s_LogEnabled;
// OC 17.08.2010 New to optionally replace stderr output by a callback:
static LogMessageCallback* m_fLogMessageCallback;
};
// -----------------------------------------------------
//
// -----------------------------------------------------
EPdfError PdfError::GetError() const
{
return m_error;
}
// -----------------------------------------------------
//
// -----------------------------------------------------
const TDequeErrorInfo & PdfError::GetCallstack() const
{
return m_callStack;
}
// -----------------------------------------------------
//
// -----------------------------------------------------
void PdfError::SetError( const EPdfError & eCode, const char* pszFile, int line, const char* pszInformation )
{
m_error = eCode;
this->AddToCallstack( pszFile, line, pszInformation );
}
// -----------------------------------------------------
//
// -----------------------------------------------------
void PdfError::AddToCallstack( const char* pszFile, int line, const char* pszInformation )
{
m_callStack.push_front( PdfErrorInfo( line, pszFile, pszInformation ) );
}
// -----------------------------------------------------
//
// -----------------------------------------------------
void PdfError::SetError( const EPdfError & eCode, const char* pszFile, int line, std::string sInformation )
{
m_error = eCode;
this->AddToCallstack( pszFile, line, sInformation );
}
// -----------------------------------------------------
//
// -----------------------------------------------------
void PdfError::AddToCallstack( const char* pszFile, int line, std::string sInformation )
{
m_callStack.push_front( PdfErrorInfo( line, pszFile, sInformation ) );
}
// -----------------------------------------------------
//
// -----------------------------------------------------
void PdfError::SetErrorInformation( const char* pszInformation )
{
if( m_callStack.size() )
m_callStack.front().SetInformation( pszInformation ? pszInformation : "" );
}
// -----------------------------------------------------
//
// -----------------------------------------------------
void PdfError::SetErrorInformation( const wchar_t* pszInformation )
{
if( m_callStack.size() )
m_callStack.front().SetInformation( pszInformation ? pszInformation : L"" );
}
// -----------------------------------------------------
//
// -----------------------------------------------------
bool PdfError::IsError() const
{
return (m_error != ePdfError_ErrOk);
}
};
#endif /* _PDF_ERROR_H_ */
| 44.244328 | 134 | 0.612417 |
d4f0e52314cb7b8877ea30e99777dd22f759147c | 658 | h | C | WBChatIMKit/Classes/Extra/Category/NSString/NSString+OPSize.h | ivine/WBChatIMKit | 99761819aea555d11d279d4430f214417915798c | [
"MIT"
] | 10 | 2018-04-19T10:55:13.000Z | 2021-02-22T09:37:26.000Z | WBChatIMKit/Classes/Extra/Category/NSString/NSString+OPSize.h | ivine/WBChatIMKit | 99761819aea555d11d279d4430f214417915798c | [
"MIT"
] | null | null | null | WBChatIMKit/Classes/Extra/Category/NSString/NSString+OPSize.h | ivine/WBChatIMKit | 99761819aea555d11d279d4430f214417915798c | [
"MIT"
] | 3 | 2019-01-07T06:17:33.000Z | 2021-11-21T14:44:01.000Z | //
// NSString+OPSize.h
// LCGOptimusPrime
//
// Created by RedRain on 2017/8/9.
// Copyright © 2017年 erics. All rights reserved.
//
#import <UIKit/UIKit.h>
@interface NSString (OPSize)
- (CGSize)lcg_sizeWithFont:(UIFont *)font maxW:(CGFloat)maxW;
- (CGSize)lcg_sizeWithFont:(UIFont *)font;
/**
去除字符串收尾空格,以及回车换行符
@return 处理后的字符串
*/
- (NSString *)lcg_removeWhitespaceAndNewlineCharacterSet;
/**
排除自身特殊字符
@return 处理后的字符串
*/
- (NSString *)lcg_filterSpecialStr;
- (BOOL)isLegalExpressCode:(NSString *)expressCode;
- (NSString *)wb_MD5String;
- (NSMutableAttributedString *)wb_makeSearchString:(NSString *)search color:(UIColor *)color;
@end
| 17.783784 | 93 | 0.723404 |
e19ff6e238939f8e0996bff2f0bec4d69b79271b | 5,045 | c | C | EdkCompatibilityPkg/Sample/Tools/Source/HiiPack/FindFiles.c | James992927108/uEFI_Edk2_Practice | 2cac7618dfee10bfa5104a2e167c85425fde0100 | [
"BSD-2-Clause"
] | 8 | 2019-06-03T10:47:48.000Z | 2021-08-21T19:11:38.000Z | EdkCompatibilityPkg/Sample/Tools/Source/HiiPack/FindFiles.c | James992927108/uEFI_Edk2_Practice | 2cac7618dfee10bfa5104a2e167c85425fde0100 | [
"BSD-2-Clause"
] | null | null | null | EdkCompatibilityPkg/Sample/Tools/Source/HiiPack/FindFiles.c | James992927108/uEFI_Edk2_Practice | 2cac7618dfee10bfa5104a2e167c85425fde0100 | [
"BSD-2-Clause"
] | 1 | 2021-04-21T06:20:00.000Z | 2021-04-21T06:20:00.000Z | /*++
Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
FindFiles.c
Abstract:
OS-specific functions to assist in finding files in
subdirectories.
--*/
#include <windows.h>
#include <direct.h>
//
// #include <io.h> // for _chmod()
//
#include <sys/stat.h>
//
// #include <errno.h> // for errno
//
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <ctype.h>
#include "HiiPack.h"
extern
void
Error (
char *Name,
UINT32 LineNumber,
UINT32 MessageCode,
char *Text,
char *MsgFmt,
...
);
static
int
ProcessDirectory (
char *RootDirectory,
char *FileMask,
FIND_FILE_CALLBACK Callback
);
/*****************************************************************************/
int
FindFiles (
char *RootDirectory,
char *FileMask,
FIND_FILE_CALLBACK Callback
)
/*++
Routine Description:
Find files of a given name under a root directory
Arguments:
RootDirectory - base directory -- look in this directory and
all its subdirectories for files matching FileMask.
FileMask - file mask of files to find
Callback - function to call for each file found
Returns:
--*/
{
char FullPath[MAX_PATH];
//
// If RootDirectory is relative, then append to cwd.
//
if (isalpha (RootDirectory[0]) && (RootDirectory[1] == ':')) {
strcpy (FullPath, RootDirectory);
} else {
//
// Get current working directory
//
if (_getcwd (FullPath, sizeof (FullPath)) == NULL) {
Error (NULL, 0, 0, "failed to get current working directory", NULL);
return 1;
}
//
// Append the relative path they passed in
//
if (FullPath[strlen (FullPath) - 1] != '\\') {
strcat (FullPath, "\\");
}
strcat (FullPath, RootDirectory);
}
if (FullPath[strlen (FullPath) - 1] == '\\') {
FullPath[strlen (FullPath) - 1] = 0;
}
//
// Process the directory
//
return ProcessDirectory (FullPath, FileMask, Callback);
}
static
int
ProcessDirectory (
char *RootDirectory,
char *FileMask,
FIND_FILE_CALLBACK Callback
)
/*++
Routine Description:
Process a directory to find all files matching a given file mask
Arguments:
RootDirectory - base directory -- look in this directory and
all its subdirectories for files matching FileMask.
FileMask - file mask of files to find
Callback - function to call for each file found
Returns:
--*/
{
HANDLE Handle;
WIN32_FIND_DATA FindData;
char TempName[MAX_PATH];
Handle = INVALID_HANDLE_VALUE;
//
// Concatenate the filemask to the directory to create the full
// path\mask path name.
//
strcpy (TempName, RootDirectory);
strcat (TempName, "\\");
strcat (TempName, FileMask);
memset (&FindData, 0, sizeof (FindData));
Handle = FindFirstFile (TempName, &FindData);
if (Handle != INVALID_HANDLE_VALUE) {
do {
if ((FindData.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) == 0) {
strcpy (TempName, RootDirectory);
strcat (TempName, "\\");
strcat (TempName, FindData.cFileName);
if (Callback (TempName) != 0) {
goto Done;
}
}
} while (FindNextFile (Handle, &FindData));
}
if (Handle != INVALID_HANDLE_VALUE) {
FindClose (Handle);
Handle = INVALID_HANDLE_VALUE;
}
//
// Now create a *.* file mask to get all subdirectories and recursive call this
// function to handle each one found.
//
strcpy (TempName, RootDirectory);
strcat (TempName, "\\*.*");
memset (&FindData, 0, sizeof (FindData));
Handle = FindFirstFile (TempName, &FindData);
//
// Loop until no more files/directories
//
if (Handle != INVALID_HANDLE_VALUE) {
do {
if (FindData.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) {
//
// Make sure it's not "." or ".."
//
if ((strcmp (FindData.cFileName, ".") != 0) && (strcmp (FindData.cFileName, "..") != 0)) {
//
// Found a valid directory. Put it all together and make a recursive call
// to process it.
//
strcpy (TempName, RootDirectory);
strcat (TempName, "\\");
strcat (TempName, FindData.cFileName);
if (ProcessDirectory (TempName, FileMask, Callback) != 0) {
goto Done;
}
}
}
} while (FindNextFile (Handle, &FindData));
}
Done:
//
// Free the handle
//
if (Handle != INVALID_HANDLE_VALUE) {
FindClose (Handle);
}
return 0;
}
| 24.138756 | 98 | 0.609118 |
e089376504491861792d9d41f6a6d8b6f7b02b9e | 160 | h | C | kernel/include/jiffies.h | lucic71/ZeldaOS | b0f6875f4a71cebb9f08da7bf64881a6883ae62a | [
"BSD-3-Clause"
] | 19 | 2018-12-17T05:44:19.000Z | 2021-12-21T07:56:02.000Z | kernel/include/jiffies.h | chillancezen/Zelda | 29a115fb38a71078366483c44dfda7f38c5a151c | [
"BSD-3-Clause"
] | 3 | 2018-05-28T14:58:23.000Z | 2019-11-12T10:07:11.000Z | kernel/include/jiffies.h | chillancezen/Zelda | 29a115fb38a71078366483c44dfda7f38c5a151c | [
"BSD-3-Clause"
] | 2 | 2020-04-28T20:17:52.000Z | 2020-07-04T17:34:28.000Z | /*
* Copyright (c) 2018 Jie Zheng
*/
#ifndef _JIFFIES_H
#define _JIFFIES_H
#include <lib/include/types.h>
#define HZ 1000
extern uint64_t jiffies;
#endif
| 11.428571 | 31 | 0.71875 |
d480065846661aae40e78d4e5b914c095be5b591 | 8,180 | c | C | Montage/mDiffExec.c | tsey2015/Montage | 1fa9ffa8a29d0b0689415a320a42437db3ade63d | [
"BSD-3-Clause"
] | 87 | 2015-06-02T14:08:22.000Z | 2022-02-04T18:14:46.000Z | Montage/mDiffExec.c | tsey2015/Montage | 1fa9ffa8a29d0b0689415a320a42437db3ade63d | [
"BSD-3-Clause"
] | 54 | 2015-10-24T19:39:20.000Z | 2021-11-17T21:28:15.000Z | Montage/mDiffExec.c | tsey2015/Montage | 1fa9ffa8a29d0b0689415a320a42437db3ade63d | [
"BSD-3-Clause"
] | 35 | 2015-10-30T16:25:23.000Z | 2021-11-06T11:27:08.000Z | /* Module: mDiffExec.c
Version Developer Date Change
------- --------------- ------- -----------------------
1.5 Daniel S. Katz 04Aug04 Added optional parallel roundrobin
computation
1.4 John Good 16May04 Added "noAreas" option
1.3 John Good 25Nov03 Added extern optarg references
1.2 John Good 25Aug03 Added status file processing
1.1 John Good 14Mar03 Added filePath() processing,
-p argument, and getopt()
argument processing. Return error
if mDiff not in path. Check for
missing/invalid diffs table or diffs
directory.
1.0 John Good 29Jan03 Baseline code
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <mtbl.h>
#ifdef MPI
#include <mpi.h>
#endif
#include "montage.h"
#define MAXSTR 4096
char *svc_value();
char *svc_run (char *cmd);
char *filePath (char *path, char *fname);
int checkFile(char *filename);
int checkHdr (char *infile, int hdrflag, int hdu);
extern char *optarg;
extern int optind, opterr;
extern int getopt(int argc, char *const *argv, const char *options);
int debug;
/*******************************************************************/
/* */
/* mDiffExec */
/* */
/* Read the table of overlaps found by mOverlap and rune mDiff to */
/* generate the difference files. */
/* */
/*******************************************************************/
int main(int argc, char **argv)
{
int c, istat, ncols, count, failed, noAreas;
int icntr1;
int icntr2;
int ifname1;
int ifname2;
int idiffname;
int cntr1;
int cntr2;
char path [MAXSTR];
char fname1 [MAXSTR];
char fname2 [MAXSTR];
char diffname[MAXSTR];
char tblfile [MAXSTR];
char diffdir [MAXSTR];
char template[MAXSTR];
char cmd [MAXSTR];
char msg [MAXSTR];
char status [32];
struct stat type;
#ifdef MPI
int row_number = 0;
int MPI_size, MPI_rank, MPI_err;
int exit_flag = 0;
int sum_tmp;
#endif
#ifdef MPI
/******************/
/* Initialize MPI */
/******************/
MPI_err = MPI_Init(&argc,&argv);
MPI_err |= MPI_Comm_size(MPI_COMM_WORLD,&MPI_size);
MPI_err |= MPI_Comm_rank(MPI_COMM_WORLD,&MPI_rank);
if (MPI_err != 0) {
printf("[struct stat=\"ERROR\", msg=\"MPI initialization failed\"]\n");
exit(1);
}
#endif
/***************************************/
/* Process the command-line parameters */
/***************************************/
debug = 0;
noAreas = 0;
strcpy(path, "");
opterr = 0;
fstatus = stdout;
while ((c = getopt(argc, argv, "np:ds:")) != EOF)
{
switch (c)
{
case 'p':
strcpy(path, optarg);
break;
case 'd':
debug = 1;
break;
case 'n':
noAreas = 1;
break;
case 's':
if((fstatus = fopen(optarg, "w+")) == (FILE *)NULL)
{
printf("[struct stat=\"ERROR\", msg=\"Cannot open status file: %s\"]\n",
optarg);
#ifdef MPI
exit_flag = 1;
#else
exit(1);
#endif
}
break;
default:
printf("[struct stat=\"ERROR\", msg=\"Usage: %s [-p projdir] [-d] [-n(o-areas)] [-s statusfile] diffs.tbl template.hdr diffdir\"]\n", argv[0]);
#ifdef MPI
exit_flag = 1;
#else
exit(1);
#endif
break;
}
}
#ifdef MPI
MPI_err = MPI_Allreduce(&exit_flag, &sum_tmp, 1, MPI_INT, MPI_SUM, MPI_COMM_WORLD);
if (sum_tmp != 0) exit(1);
exit_flag = 0;
#endif
if (argc - optind < 3)
{
printf("[struct stat=\"ERROR\", msg=\"Usage: %s [-p projdir] [-d] [-n(o-areas)] [-s statusfile] diffs.tbl template.hdr diffdir\"]\n", argv[0]);
#ifdef MPI
exit_flag = 1;
#else
exit(1);
#endif
}
#ifdef MPI
MPI_err = MPI_Allreduce(&exit_flag, &sum_tmp, 1, MPI_INT, MPI_SUM, MPI_COMM_WORLD);
if (sum_tmp != 0) exit(1);
exit_flag = 0;
#endif
strcpy(tblfile, argv[optind]);
strcpy(template, argv[optind + 1]);
strcpy(diffdir, argv[optind + 2]);
checkHdr(template, 1, 0);
/**********************************/
/* Check to see if diffdir exists */
/**********************************/
istat = stat(diffdir, &type);
if(istat < 0)
{
fprintf(fstatus, "[struct stat=\"ERROR\", msg=\"Cannot access %s\"]\n", diffdir);
#ifdef MPI
exit_flag = 1;
#else
exit(1);
#endif
}
else if (S_ISDIR(type.st_mode) != 1)
{
fprintf(fstatus, "[struct stat=\"ERROR\", msg=\"%s is not a directory\"]\n", diffdir);
#ifdef MPI
exit_flag = 1;
#else
exit(1);
#endif
}
#ifdef MPI
MPI_err = MPI_Allreduce(&exit_flag, &sum_tmp, 1, MPI_INT, MPI_SUM, MPI_COMM_WORLD);
if (sum_tmp != 0) exit(1);
exit_flag = 0;
#endif
/***************************************/
/* Open the difference list table file */
/***************************************/
ncols = topen(tblfile);
if(ncols <= 0)
{
fprintf(fstatus, "[struct stat=\"ERROR\", msg=\"Invalid image metadata file: %s\"]\n",
tblfile);
#ifdef MPI
exit_flag = 1;
#else
exit(1);
#endif
}
#ifdef MPI
MPI_err = MPI_Allreduce(&exit_flag, &sum_tmp, 1, MPI_INT, MPI_SUM, MPI_COMM_WORLD);
if (sum_tmp != 0) exit(1);
exit_flag = 0;
#endif
icntr1 = tcol( "cntr1");
icntr2 = tcol( "cntr2");
ifname1 = tcol( "plus");
ifname2 = tcol( "minus");
idiffname = tcol( "diff");
if(icntr1 < 0
|| icntr2 < 0
|| ifname1 < 0
|| ifname2 < 0
|| idiffname < 0)
{
fprintf(fstatus, "[struct stat=\"ERROR\", msg=\"Need columns: cntr1 cntr2 plus minus diff\"]\n");
#ifdef MPI
exit_flag = 1;
#else
exit(1);
#endif
}
#ifdef MPI
MPI_err = MPI_Allreduce(&exit_flag, &sum_tmp, 1, MPI_INT, MPI_SUM, MPI_COMM_WORLD);
if (sum_tmp != 0) exit(1);
exit_flag = 0;
#endif
/***********************************/
/* Read the records and call mDiff */
/***********************************/
count = 0;
failed = 0;
while(1)
{
istat = tread();
if(istat < 0)
break;
#ifdef MPI
if (row_number % MPI_size == MPI_rank) {
#endif
cntr1 = atoi(tval(icntr1));
cntr2 = atoi(tval(icntr2));
strcpy(fname1, filePath(path, tval(ifname1)));
strcpy(fname2, filePath(path, tval(ifname2)));
strcpy(diffname, tval(idiffname));
if(noAreas)
sprintf(cmd, "mDiff -n %s %s %s %s", fname1, fname2,
filePath(diffdir, diffname), template);
else
sprintf(cmd, "mDiff %s %s %s %s", fname1, fname2,
filePath(diffdir, diffname), template);
if(debug)
{
printf("[%s]\n", cmd);
fflush(stdout);
}
svc_run(cmd);
strcpy( status, svc_value( "stat" ));
if(strcmp( status, "ABORT") == 0)
{
strcpy( msg, svc_value( "msg" ));
fprintf(fstatus, "[struct stat=\"ERROR\", msg=\"%s\"]\n", msg);
fflush(stdout);
exit(1);
}
++count;
if(strcmp( status, "ERROR" ) == 0
|| strcmp( status, "WARNING") == 0)
++failed;
#ifdef MPI
} // end if (row_number % MPI_size == MPI_rank)
row_number++;
#endif
}
#ifdef MPI
MPI_err = MPI_Allreduce(&count, &sum_tmp, 1, MPI_INT, MPI_SUM, MPI_COMM_WORLD);
count = sum_tmp;
MPI_err = MPI_Allreduce(&failed, &sum_tmp, 1, MPI_INT, MPI_SUM, MPI_COMM_WORLD);
failed = sum_tmp;
if (MPI_rank == 0) {
#endif
fprintf(fstatus, "[struct stat=\"OK\", count=%d, failed=%d]\n", count, failed);
fflush(stdout);
#ifdef MPI
} // end if (MPI_rank == 0)
MPI_err = MPI_Finalize();
#endif
exit(0);
}
| 22.977528 | 149 | 0.506112 |
dcd4e32870830533528c8528b8a4b870b739b01d | 4,642 | c | C | libdcpu-ld-policy/policyfree.c | DCPUTeam/DCPUToolchain | 1882aadbcbd4226064e4d8be9e7178ba771491d8 | [
"MIT"
] | 7 | 2015-10-31T19:11:46.000Z | 2022-02-20T23:55:03.000Z | libdcpu-ld-policy/policyfree.c | DCPUTeam/DCPUToolchain | 1882aadbcbd4226064e4d8be9e7178ba771491d8 | [
"MIT"
] | 2 | 2016-10-07T06:33:34.000Z | 2017-12-13T16:00:11.000Z | libdcpu-ld-policy/policyfree.c | DCPUTeam/DCPUToolchain | 1882aadbcbd4226064e4d8be9e7178ba771491d8 | [
"MIT"
] | 4 | 2015-10-08T02:24:35.000Z | 2022-02-20T21:39:29.000Z | ///
/// @addtogroup LibDCPU-LD-Policy
/// @{
///
/// @file
/// @brief Defines functions for correctly free'ing policy data.
/// @author James Rhodes
///
#include <stdlib.h>
#include "policyast.h"
#include "policyfree.h"
#include "parser.h"
void free_policy(bool runtime, policy_t* policy)
{
if (runtime)
return;
if (policy->name != NULL)
bdestroy(policy->name);
if (policy->instructions != NULL)
{
list_iterator_start(policy->instructions);
while (list_iterator_hasnext(policy->instructions))
free_policy_instruction(runtime, list_iterator_next(policy->instructions));
list_iterator_stop(policy->instructions);
list_destroy(policy->instructions);
free(policy->instructions);
}
if (policy->settings != NULL)
{
list_iterator_start(policy->settings);
while (list_iterator_hasnext(policy->settings))
free_policy_setting(runtime, list_iterator_next(policy->settings));
list_iterator_stop(policy->settings);
list_destroy(policy->settings);
free(policy->settings);
}
free(policy);
}
void free_policies(bool runtime, policies_t* policies)
{
if (runtime)
return;
list_iterator_start(&policies->policies);
while (list_iterator_hasnext(&policies->policies))
free_policy(runtime, list_iterator_next(&policies->policies));
list_iterator_stop(&policies->policies);
list_destroy(&policies->policies);
if (policies->settings != NULL)
free_policy(runtime, policies->settings);
free(policies);
}
void free_policy_function_call(bool runtime, policy_function_call_t* call)
{
if (runtime)
return;
if (call->parameters != NULL)
{
list_iterator_start(call->parameters);
while (list_iterator_hasnext(call->parameters))
free_policy_value(runtime, list_iterator_next(call->parameters));
list_iterator_stop(call->parameters);
list_destroy(call->parameters);
free(call->parameters);
}
free(call);
}
void free_policy_value(bool runtime, policy_value_t* value)
{
if ((runtime && !value->runtime) ||
(!runtime && value->runtime))
return;
switch (value->type)
{
case NUMBER:
case TABLE:
case FIELD:
break;
case WORD:
case VARIABLE:
bdestroy(value->string);
break;
case FUNCTION:
free_policy_function_call(runtime, value->function);
break;
case LIST:
list_iterator_start(value->list);
while (list_iterator_hasnext(value->list))
free_policy_value(runtime, list_iterator_next(value->list));
list_iterator_stop(value->list);
list_destroy(value->list);
free(value->list);
break;
default:
break;
}
free(value);
}
void free_policy_variable(bool runtime, policy_variable_t* variable)
{
if (!runtime)
return;
bdestroy(variable->name);
free_policy_value(runtime, variable->value);
free(variable);
}
void free_policy_instruction(bool runtime, policy_instruction_t* instruction)
{
if (runtime)
return;
if (instruction->value != NULL)
free_policy_value(runtime, instruction->value);
if (instruction->for_variable != NULL)
bdestroy(instruction->for_variable);
if (instruction->for_start != NULL)
free_policy_value(runtime, instruction->for_start);
if (instruction->for_end != NULL)
free_policy_value(runtime, instruction->for_end);
if (instruction->for_instructions != NULL)
{
list_iterator_start(instruction->for_instructions);
while (list_iterator_hasnext(instruction->for_instructions))
free_policy_instruction(runtime, list_iterator_next(instruction->for_instructions));
list_iterator_stop(instruction->for_instructions);
list_destroy(instruction->for_instructions);
free(instruction->for_instructions);
}
free(instruction);
}
void free_policy_setting(bool runtime, policy_setting_t* setting)
{
if (runtime)
return;
bdestroy(setting->key);
bdestroy(setting->value);
}
void free_policy_state(bool runtime, policy_state_t* state)
{
if (runtime)
return;
list_iterator_start(&state->variables);
while (list_iterator_hasnext(&state->variables))
free_policy_instruction(runtime, list_iterator_next(&state->variables));
list_iterator_stop(&state->variables);
list_destroy(&state->variables);
free(state);
}
///
/// @}
/// | 29.194969 | 96 | 0.654675 |
7c16d253f69144f0ed3292cfe8b131b644ff9b7b | 3,789 | c | C | src/qip/mempool.c | dasfaha/sky | 4f2696e9abe54f4818f94337ed3bceae798e5a6d | [
"MIT"
] | 2 | 2018-01-16T07:26:53.000Z | 2021-12-08T03:12:40.000Z | src/qip/mempool.c | dasfaha/sky | 4f2696e9abe54f4818f94337ed3bceae798e5a6d | [
"MIT"
] | null | null | null | src/qip/mempool.c | dasfaha/sky | 4f2696e9abe54f4818f94337ed3bceae798e5a6d | [
"MIT"
] | null | null | null | #include <stdlib.h>
#include "mempool.h"
#include "dbg.h"
//==============================================================================
//
// Functions
//
//==============================================================================
//======================================
// Lifecycle
//======================================
// Creates a memory pool.
qip_mempool *qip_mempool_create()
{
qip_mempool *mempool = malloc(sizeof(qip_mempool));
check_mem(mempool);
mempool->blocks = NULL;
mempool->block_count = 0;
mempool->ptr = NULL;
return mempool;
error:
qip_mempool_free(mempool);
return NULL;
}
// Frees an mempool.
//
// mempool - The mempool to free.
//
// Returns nothing.
void qip_mempool_free(qip_mempool *mempool)
{
if(mempool) {
qip_mempool_free_blocks(mempool);
free(mempool);
}
}
// Frees the blocks in a memory pool.
//
// mempool - The memory pool.
//
// Returns nothing.
void qip_mempool_free_blocks(qip_mempool *mempool)
{
if(mempool) {
uint32_t i;
for(i=0; i<mempool->block_count; i++) {
free(mempool->blocks[i]);
mempool->blocks[i] = NULL;
}
if(mempool->blocks) free(mempool->blocks);
mempool->blocks = NULL;
mempool->block_count = 0;
mempool->ptr = NULL;
}
}
//======================================
// Allocation
//======================================
// Allocates a given number of bytes within the memory pool.
//
// mempool - The memory pool.
// size - The number of bytes to allocate.
// ptr - A pointer to where the allocated pointer should be returned.
//
// Returns 0 if successful, otherwise returns -1.
int qip_mempool_malloc(qip_mempool *mempool, size_t size, void **ptr)
{
// Determine actual allocation size after alignment.
size_t offset = (size % QIP_MEMPOOL_ALIGN_SIZE);
if(offset > 0) {
size += QIP_MEMPOOL_ALIGN_SIZE - offset;
}
// Validation.
check(mempool != NULL, "Memory pool required");
check(size > 0, "Allocation size must be greater than zero");
check(size <= QIP_MEMPOOL_BLOCK_SIZE, "Allocation size (%ld) is greater than max size (%d)", size, QIP_MEMPOOL_BLOCK_SIZE);
// If there are no blocks or there is not enough space left in the
// current block then allocate a new block.
if(mempool->block_count == 0 || (mempool->ptr + size) > (mempool->blocks[mempool->block_count-1] + QIP_MEMPOOL_BLOCK_SIZE)) {
// Resize block list.
mempool->block_count++;
mempool->blocks = realloc(mempool->blocks, mempool->block_count * sizeof(*mempool->blocks));
check_mem(mempool->blocks);
// Allocate new block.
mempool->blocks[mempool->block_count-1] = malloc(QIP_MEMPOOL_BLOCK_SIZE);
check_mem(mempool->blocks[mempool->block_count-1]);
// Move pointer to point at beginning of new block.
mempool->ptr = mempool->blocks[mempool->block_count-1];
}
// Return a pointer to the current location.
*ptr = mempool->ptr;
// Move pointer by the number of bytes allocated.
mempool->ptr += size;
return 0;
error:
*ptr = NULL;
return -1;
}
// Resets the allocation pointer to the beginning of the first block. No
// memory in the pool is freed though.
//
// mempool - The memory pool.
//
// Returns 0 if successful, otherwise returns -1.
int qip_mempool_reset(qip_mempool *mempool)
{
check(mempool != NULL, "Memory pool required");
// Only update the allocation pointer if blocks exists. If no blocks exist
// then the allocation pointer should be null anyway.
if(mempool->block_count > 0) {
mempool->ptr = mempool->blocks[0];
}
return 0;
error:
return -1;
}
| 26.87234 | 129 | 0.58749 |
32a6d0f8b138c8d2553eccda5473115130adde27 | 9,674 | c | C | adamant/adamant_window.c | gcracker/parameter-toolkit | ef8e525d2cc53627892a89954926453348623beb | [
"BSD-3-Clause"
] | 2 | 2021-11-19T09:37:58.000Z | 2022-03-30T06:58:55.000Z | adamant/adamant_window.c | gcracker/parameter-toolkit | ef8e525d2cc53627892a89954926453348623beb | [
"BSD-3-Clause"
] | null | null | null | adamant/adamant_window.c | gcracker/parameter-toolkit | ef8e525d2cc53627892a89954926453348623beb | [
"BSD-3-Clause"
] | null | null | null | /*#*STARTLICENCE*#
Copyright (c) 2005-2009, Regents of the University of Colorado
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
Neither the name of the University of Colorado nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
#*ENDLICENCE*#*/
/*****************************************************************************
* adamant_window.c
****************************************************************************/
#include <string.h>
#include "adamant_window.h"
#include "adamant_meminfo_pagetable.h" // SchedInfo
#include "misc.h"
#define ADAMANT_WINDOW_OOO(window) ((AdamantWindowOoO *) (window))
#define ADAMANT_WINDOW_ROB(window) ((AdamantWindowRob *) (window))
/**
* Static variables
*/
static guint adamant_window_next_id = 0;
/**
* Local function declarations
*/
static gint u64CmpFcn(foint a, foint b);
static void
adamant_window_ooo_insert(AdamantWindowOoO * ooo, guint64 ready);
static void
adamant_window_rob_insert(AdamantWindowRob * rob, guint64 ready);
/* ========================================================================
* adamant window base class implementation
* ========================================================================
*/
static void
adamant_window_init(AdamantWindow * window,
AdamantWindowType windowtype,
guint windowsize)
{
window->type = windowtype;
window->id = adamant_window_next_id++;
window->size = windowsize;
window->head = 0;
window->tail = 0;
window->sum = 0;
window->last_mispredicted_branch.ready = 0;
window->last_mispredicted_branch.din_src = 0;
window->last_mispredicted_branch.thread_id = 0;
}
void
adamant_window_insert(AdamantWindow * window, guint64 ready)
{
switch(window->type) {
case ADAMANT_WINDOW_TYPE_OOO:
adamant_window_ooo_insert((AdamantWindowOoO*) window, ready);
break;
case ADAMANT_WINDOW_TYPE_ROB:
adamant_window_rob_insert((AdamantWindowRob*) window, ready);
break;
}
}
/* ========================================================================
* adamant out-of-order window implementation
* ========================================================================
*/
void
adamant_window_ooo_init(AdamantWindowOoO * ooo, guint windowsize)
{
foint val;
// init base
adamant_window_init(&ooo->w_base, ADAMANT_WINDOW_TYPE_OOO, windowsize);
// init self
if (ooo->ooo_heap)
HeapFree(ooo->ooo_heap);
ooo->ooo_heap = HeapAlloc(windowsize, &u64CmpFcn);
val.u64 = 0;
do { HeapInsert(ooo->ooo_heap, val); } while (--windowsize);
}
void
adamant_window_ooo_destroy(AdamantWindowOoO * ooo)
{
if (ooo->ooo_heap)
HeapFree(ooo->ooo_heap);
}
void
adamant_window_ooo_insert(AdamantWindowOoO * ooo, guint64 ready)
{
foint val;
// value at head is lost
val = HeapNext(ooo->ooo_heap);
// insert new value
val.u64 = ready;
HeapInsert(ooo->ooo_heap, val);
// set new head and tail
ooo->w_base.head = HeapPeek(ooo->ooo_heap).u64;
if ( val.u64 > ooo->w_base.tail ) {
ooo->w_base.tail = val.u64;
}
}
gint u64CmpFcn(foint a, foint b)
{
return ((a.u64<b.u64) ? -1 : ((a.u64==b.u64)?0:1));
}
/* ========================================================================
* adamant reorder buffer (ROB) implementation
* ========================================================================
*/
void
adamant_window_rob_init(AdamantWindowRob * rob, guint windowsize)
{
// init base
adamant_window_init(&rob->w_base, ADAMANT_WINDOW_TYPE_ROB, windowsize);
// init self
rob->ptr = 0;
rob->rob = g_new0(guint64, windowsize);
}
void
adamant_window_rob_destroy(AdamantWindowRob * rob)
{
g_free(rob->rob);
}
void
adamant_window_rob_insert(AdamantWindowRob * rob, guint64 ready)
{
// insert at head (head now becomes tail in circular buffer)
rob->rob[rob->ptr] = MAX(ready,
rob->rob[MOD_MINUS(rob->ptr, 1, rob->w_base.size)]);
rob->w_base.tail = rob->rob[rob->ptr];
// increment head
rob->ptr = MOD_PLUS(rob->ptr, 1, rob->w_base.size);
rob->w_base.head = rob->rob[rob->ptr];
}
/* ========================================================================
* adamant window runtime implementation
* ========================================================================
*/
void
adamant_window_runtime_init(AdamantWindowRuntime * wrt,
AdamantWindowConfig * config)
{
// copy the configuration
memcpy(&wrt->config, config, sizeof(AdamantWindowConfig));
wrt->windows = NULL;
// allocate memory for specified type of window
switch(wrt->config.w_type) {
case ADAMANT_WINDOW_TYPE_OOO:
wrt->windows =
(AdamantWindow *) g_new0(AdamantWindowOoO, wrt->config.w_num);
break;
case ADAMANT_WINDOW_TYPE_ROB:
wrt->windows =
(AdamantWindow *) g_new0(AdamantWindowRob, wrt->config.w_num);
break;
}
// initialize windows
switch(wrt->config.w_type) {
guint i;
case ADAMANT_WINDOW_TYPE_OOO:
for (i=0; i<wrt->config.w_num; i++) {
adamant_window_ooo_init(ADAMANT_WINDOW_OOO(adamant_window_runtime_index(wrt, i)),
wrt->config.w_size);
}
break;
case ADAMANT_WINDOW_TYPE_ROB:
for (i=0; i<wrt->config.w_num; i++) {
adamant_window_rob_init(ADAMANT_WINDOW_ROB(adamant_window_runtime_index(wrt, i)),
wrt->config.w_size);
}
break;
}
}
void
adamant_window_runtime_destroy(AdamantWindowRuntime * wrt)
{
switch(wrt->config.w_type) {
guint i;
case ADAMANT_WINDOW_TYPE_OOO:
for (i=0; i<wrt->config.w_num; i++) {
adamant_window_ooo_destroy(ADAMANT_WINDOW_OOO(adamant_window_runtime_index(wrt, i)));
}
break;
case ADAMANT_WINDOW_TYPE_ROB:
for (i=0; i<wrt->config.w_num; i++) {
adamant_window_rob_destroy(ADAMANT_WINDOW_ROB(adamant_window_runtime_index(wrt, i)));
}
break;
}
}
guint
adamant_window_runtime_choose(AdamantWindowRuntime * wrt,
GArray *src_sched_info,
guint src_sched_info_len,
guint communication_latency)
{
guint i,j;
guint64 cost;
guint64 min_cost = G_MAXUINT64;
guint best_w_id = 0;
guint64 *ready_cost;
//guint64 *head_cost;
//guint64 *tail_cost;
guint64 min_ready;
/* Optimize the case of one window */
if(wrt->config.w_num == 1) return 0;
ready_cost = alloca(sizeof(guint64) * wrt->config.w_num);
//head_cost = alloca(sizeof(guint64) * wrt->config.w_num);
//tail_cost = alloca(sizeof(guint64) * wrt->config.w_num);
for(j = 0; j < wrt->config.w_num; j++) {
AdamantWindow * w = adamant_window_runtime_index(wrt, j);
// Initialize ready_cost, more processing later
ready_cost[j] = MAX(adamant_window_head(w),
w->last_mispredicted_branch.ready);
// FIXME: Calculate head cost
// head_cost[j] = rob->rob[MOD_PLUS(rob->ptr, 1, rob->size)] -
// adamant_window_rob_head(rob);
// head_cost[j] = 0;
}
// Compute the ready time of this instr for all ROBs
for(i = 0; i < src_sched_info_len; i++) {
SchedInfo * si = g_array_index(src_sched_info, SchedInfo*, i);
guint64 local_ready = si->ready;
for(j = 0; j < wrt->config.w_num; j++) {
guint64 w_local_ready = local_ready;
AdamantWindow * w = adamant_window_runtime_index(wrt, j);
if (adamant_window_id(w) != si->thread_id) {
w_local_ready += communication_latency;
}
ready_cost[j] = MAX(ready_cost[j], w_local_ready);
}
}
// Compute the tail cost (uses ready times just computed)
/*
for(j = 0; j < wrt->config.w_num; j++) {
AdamantWindow * w = adamant_window_runtime_index(wrt, j);
if (adamant_window_tail(w) > ready_cost[j])
tail_cost[j] = 0;
else
tail_cost[j] = ready_cost[j] - adamant_window_tail(w);
}
*/
// Find the minimum ready time across all ROBs
min_ready = ready_cost[0];
for(j = 1; j < wrt->config.w_num; j++)
min_ready = MIN(min_ready, ready_cost[j]);
// Subtract this minimum from all ROB readys to get a ready_cost
for(j = 0; j < wrt->config.w_num; j++)
ready_cost[j] -= min_ready;
// Calculate total cost using weights
for(j = 0; j < wrt->config.w_num; j++) {
cost = ready_cost[j];
/*
cost =
wrt->config.w_ready_weight * ready_cost[j] +
wrt->config.w_head_weight * head_cost[j] +
wrt->config.w_tail_weight * tail_cost[j];
*/
if(cost < min_cost) {
best_w_id = j;
min_cost = cost;
}
}
return (best_w_id);
}
| 29.226586 | 91 | 0.646475 |
fd083eb39848702c6f9148b5273546b4ed56c437 | 15,552 | h | C | apps/wolfssl_tcp_server/firmware/src/config/pic32mz_ef_sk_sw/library/tcpip/smtp.h | carlosearm/net_apps_pic32mz | f6f36ead86f7a41f59dc52a4aec5a4108718f63f | [
"0BSD"
] | 4 | 2021-07-23T18:37:34.000Z | 2022-01-09T17:31:40.000Z | apps/wolfssl_tcp_server/firmware/src/config/pic32mz_ef_sk_sw/library/tcpip/smtp.h | carlosearm/net_apps_pic32mz | f6f36ead86f7a41f59dc52a4aec5a4108718f63f | [
"0BSD"
] | 2 | 2021-02-16T20:26:10.000Z | 2022-01-05T15:19:32.000Z | apps/tcpip_tcp_client/firmware/src/config/pic32mx_eth_sk2_encx24j600/library/tcpip/smtp.h | Microchip-MPLAB-Harmony/net_apps_pic32mx | 004772bd2226b3e778af937505a86cf845c5b850 | [
"0BSD"
] | 6 | 2021-02-02T13:51:49.000Z | 2021-08-31T18:35:37.000Z | /*******************************************************************************
Simple Mail Transfer Protocol (SMTP) Client
Company:
Microchip Technology Inc.
File Name:
smtp.h
Summary:
Module for Microchip TCP/IP Stack.
Description:
The SMTP client module in the TCP/IP Stack lets applications send e-mails
to any recipient worldwide. These message could include status information
or important alerts. Using the e-mail to SMS gateways provided by most cell
phone carriers, these messages can also be delivered directly to cell phone
handsets.
*******************************************************************************/
//DOM-IGNORE-BEGIN
/*****************************************************************************
Copyright (C) 2012-2018 Microchip Technology Inc. and its subsidiaries.
Microchip Technology Inc. and its subsidiaries.
Subject to your compliance with these terms, you may use Microchip software
and any derivatives exclusively with Microchip products. It is your
responsibility to comply with third party license terms applicable to your
use of third party software (including open source software) that may
accompany Microchip software.
THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR
PURPOSE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*****************************************************************************/
//DOM-IGNORE-END
#ifndef __SMTP_H
#define __SMTP_H
// DOM-IGNORE-BEGIN
#ifdef __cplusplus // Provide C++ Compatibility
extern "C" {
#endif
// DOM-IGNORE-END
// NOTE: The SMTP module is deprecated and should not be used for new projects. The new SMTPC module should be used.
//
// #warning "The SMTP module is obsolete. The new SMTPC module should be used!"
// *****************************************************************************
// *****************************************************************************
// Section: Data Type Definitions
// *****************************************************************************
// *****************************************************************************
#define SMTP_SUCCESS (0x0000u) // Message was successfully sent
#define SMTP_RESOLVE_ERROR (0x8000u) // DNS lookup for SMTP server failed
#define SMTP_CONNECT_ERROR (0x8001u) // Connection to SMTP server failed
//****************************************************************************
/*
Function:
typedef struct TCPIP_SMTP_CLIENT_MESSAGE
Summary:
Configures the SMTP client to send a message.
Description:
This structure of pointers configures the SMTP Client to send an e-mail
message.
Parameters:
Server - the SMTP server to relay the message through
Username - the user name to use when logging into the SMTP server,
if any is required
Password - the password to supply when logging in, if any is required
To - the destination address for this message. May be a
comma-separated list of address, and/or formatted.
CC - The CC addresses for this message, if any. May be a
comma-separated list of address, and/or formatted.
BCC - The BCC addresses for this message, if any. May be a
comma-separated list of address, and/or formatted.
From - The From address for this message. May be formatted.
Subject - The Subject header for this message.
OtherHeaders - Any additional headers for this message. Each additional
header, including the last one, must be terminated with
a CRLF pair.
Body - When sending a message from memory, the location of the
body of this message in memory. Leave as NULL to build
a message on-the-fly.
UseSSL - This flag causes the SMTP client to make a secure connection to the server.
ServerPort - (uint16_t value) Indicates the port on which to connect to the
remote SMTP server.
Remarks:
When formatting an e-mail address, the SMTP standard format for associating a
printable name may be used. This format places the printable name in quotation
marks, with the address following in pointed brackets, such as "John Smith"
<john.smith@domain.com>.
*/
typedef struct
{
char* Server;
char* Username;
char* Password;
char* To;
char* CC;
char* BCC;
char* From;
char* Subject;
char* OtherHeaders;
char* Body;
bool UseSSL;
uint16_t ServerPort;
} TCPIP_SMTP_CLIENT_MESSAGE;
typedef struct
{
void* reserved;
}TCPIP_SMTP_CLIENT_MODULE_CONFIG;
// *****************************************************************************
// *****************************************************************************
// Section: SMTP Function Prototypes
// *****************************************************************************
// *****************************************************************************
//*****************************************************************************
/*
Function:
bool TCPIP_SMTP_UsageBegin(void)
Summary:
Requests control of the SMTP client module.
Description:
Call this function before calling any other SMTP Client APIs. This
function obtains a lock on the SMTP Client, which can only be used by
one stack application at a time. Once the application is finished
with the SMTP client, it must call TCPIP_SMTP_UsageEnd to release control
of the module to any other waiting applications.
This function initializes all the SMTP state machines and variables
back to their default state.
Precondition:
None.
Parameters:
None.
Return Values:
- true - The application has successfully obtained control of the module
- false - The SMTP module is in use by another application. Call the
TCPIP_SMTP_UsageBegin function again later, after returning to
the main program loop
*/
bool TCPIP_SMTP_UsageBegin(void);
//*****************************************************************************
/*
Function:
uint16_t TCPIP_SMTP_UsageEnd(void)
Summary:
Releases control of the SMTP client module.
Description:
Call this function to release control of the SMTP client module once
an application is finished using it. This function releases the lock
obtained by TCPIP_SMTP_UsageBegin, and frees the SMTP client to be used by
another application.
Precondition:
TCPIP_SMTP_UsageBegin returned true on a previous call.
Parameters:
None.
Return Values:
- SMTP_SUCCESS - A message was successfully sent
- SMTP_RESOLVE_ERROR - The SMTP server could not be resolved
- SMTP_CONNECT_ERROR - The connection to the SMTP server failed or was
prematurely terminated
- other code - The last SMTP server response code
*/
uint16_t TCPIP_SMTP_UsageEnd(void);
//*****************************************************************************
/*
Function:
void TCPIP_SMTP_MailSend(TCPIP_SMTP_CLIENT_MESSAGE* smtpClientMessage)
Summary:
Initializes the message sending process.
Description:
This function starts the state machine that performs the actual
transmission of the message. Call this function after all the fields
in SMTPClient have been set.
Precondition:
TCPIP_SMTP_UsageBegin returned true on a previous call.
Parameters:
smtpClientMessage - pointer to a TCPIP_SMTP_CLIENT_MESSAGE structure that configures
the message to send
Returns:
None.
Remarks:
The fields pointed by the smtpClientMessage have to be non-volatile
until the SMTP send mail process is completed!
*/
void TCPIP_SMTP_MailSend(TCPIP_SMTP_CLIENT_MESSAGE* smtpClientMessage);
//*****************************************************************************
/*
Function:
bool TCPIP_SMTP_IsBusy(void)
Summary:
Determines if the SMTP client is busy.
Description:
Call this function to determine if the SMTP client is busy performing
background tasks. This function should be called after any call to
TCPIP_SMTP_MailSend, TCPIP_SMTP_PutIsDone to determine if the stack has finished
performing its internal tasks. It should also be called prior to any
call to TCPIP_SMTP_IsPutReady to verify that the SMTP client has not
prematurely disconnected. When this function returns false, the next
call should be to TCPIP_SMTP_UsageEnd to release the module and obtain the
status code for the operation.
Precondition:
TCPIP_SMTP_UsageBegin returned true on a previous call.
Parameters:
None.
Return Values:
- true - The SMTP Client is busy with internal tasks or sending an
on-the-fly message
- false - The SMTP Client is terminated and is ready to be released
*/
bool TCPIP_SMTP_IsBusy(void);
//*****************************************************************************
/*
Function:
uint16_t TCPIP_SMTP_IsPutReady(void)
Summary:
Determines how much data can be written to the SMTP client.
Description:
Use this function to determine how much data can be written to the SMTP
client when generating an on-the-fly message.
Precondition:
TCPIP_SMTP_UsageBegin returned true on a previous call, and an on-the-fly
message is being generated. This requires that TCPIP_SMTP_MailSend was called
with SMTPClient.Body set to NULL.
Parameters:
None.
Returns:
The number of free bytes the SMTP TX FIFO.
Remarks:
This function should only be called externally when the SMTP client is
generating an on-the-fly message (i.e., TCPIP_SMTP_MailSend was called
with SMTPClient.Body set to NULL).
*/
uint16_t TCPIP_SMTP_IsPutReady(void);
//*****************************************************************************
/*
Function:
bool TCPIP_SMTP_Put(char c)
Summary:
Writes a single byte to the SMTP client.
Description:
This function writes a single byte to the SMTP client.
Precondition:
TCPIP_SMTP_UsageBegin returned true on a previous call.
Parameters:
c - The byte to be written
Return Values:
- true - The byte was successfully written
- false - The byte was not written, most likely because the buffer was full
Remarks:
This function is obsolete and will be eventually removed.
TCPIP_SMTP_ArrayPut and TCPIP_SMTP_StringPut should be used.
This function cannot be used on an encrypted connection.
It is difficult to estimate the amount of TX buffer space needed
when transmitting byte by byte, which could cause intermediary write
operations to the underlying TCP socket.
This function should only be called externally when the SMTP client is
generating an on-the-fly message (i.e., TCPIP_SMTP_MailSend was called
with SMTPClient.Body set to NULL).
*/
bool TCPIP_SMTP_Put(char c);
//*****************************************************************************
/*
Function:
uint16_t TCPIP_SMTP_ArrayPut(uint8_t* Data, uint16_t Len)
Summary:
Writes a series of bytes to the SMTP client.
Description:
This function writes a series of bytes to the SMTP client.
Precondition:
TCPIP_SMTP_UsageBegin returned true on a previous call.
Parameters:
Data - The data to be written
Len - How many bytes should be written
Returns:
The number of bytes written. If less than Len, then the TX FIFO became
full before all bytes could be written.
Remarks:
This function should only be called externally when the SMTP client is
generating an on-the-fly message (i.e., TCPIP_SMTP_MailSend was called
with SMTPClient.Body set to NULL).
*/
uint16_t TCPIP_SMTP_ArrayPut(uint8_t* Data, uint16_t Len);
//*****************************************************************************
/*
Function:
uint16_t TCPIP_SMTP_StringPut(char* Data)
Summary:
Writes a string to the SMTP client.
Description:
This function writes a string to the SMTP client.
Precondition:
TCPIP_SMTP_UsageBegin returned true on a previous call.
Parameters:
Data - The data to be written
Returns:
The number of bytes written. If less than the length of Data, then the
TX FIFO became full before all bytes could be written.
Remarks:
This function should only be called externally when the SMTP client is
generating an on-the-fly message. (That is, TCPIP_SMTP_MailSend was called
with SMTPClient.Body set to NULL.)
*/
uint16_t TCPIP_SMTP_StringPut(char* Data);
//*****************************************************************************
/*
Function:
void TCPIP_SMTP_Flush(void)
Summary:
Flushes the SMTP socket and forces all data to be sent.
Description:
This function flushes the SMTP socket and forces all data to be sent.
Precondition:
TCPIP_SMTP_UsageBegin returned true on a previous call.
Parameters:
None.
Returns:
None.
Remarks:
This function should only be called externally when the SMTP client is
generating an on-the-fly message (i.e., TCPIP_SMTP_MailSend was called
with SMTPClient.Body set to NULL).
*/
void TCPIP_SMTP_Flush(void);
//*****************************************************************************
/*
Function:
void TCPIP_SMTP_PutIsDone(void)
Summary:
Indicates that the on-the-fly message is complete.
Description:
This function indicates that the on-the-fly message is complete.
Precondition:
TCPIP_SMTP_UsageBegin returned true on a previous call, and the SMTP client is
generated an on-the-fly message (i.e., TCPIP_SMTP_MailSend was called
with SMTPClient.Body set to NULL).
Parameters:
None.
Returns:
None.
*/
void TCPIP_SMTP_PutIsDone(void);
// *****************************************************************************
/*
Function:
void TCPIP_SMTP_ClientTask(void)
Summary:
Standard TCP/IP stack module task function.
Description:
this function performs SMTP module tasks in the TCP/IP stack.
Precondition:
SMTP module should have been initialized.
Parameters:
None.
Returns:
None.
Remarks:
None.
*/
void TCPIP_SMTP_ClientTask(void);
//DOM-IGNORE-BEGIN
#ifdef __cplusplus
}
#endif
//DOM-IGNORE-END
#endif // __SMTP_H
| 32 | 117 | 0.613169 |
f9cedd90de54f5b2d92fafea311c782846606460 | 6,879 | h | C | platform/common/inc/aarch64/pal_arch_helpers.h | QPC-database/ff-a-acs | f3a730bc421d8f265a1509aec9dcccbde6b8335b | [
"BSD-3-Clause"
] | 1 | 2021-07-04T00:04:39.000Z | 2021-07-04T00:04:39.000Z | platform/common/inc/aarch64/pal_arch_helpers.h | QPC-database/ff-a-acs | f3a730bc421d8f265a1509aec9dcccbde6b8335b | [
"BSD-3-Clause"
] | null | null | null | platform/common/inc/aarch64/pal_arch_helpers.h | QPC-database/ff-a-acs | f3a730bc421d8f265a1509aec9dcccbde6b8335b | [
"BSD-3-Clause"
] | null | null | null | /*
* Copyright (c) 2021, Arm Limited or its affliates. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef ARCH_HELPERS_H
#define ARCH_HELPERS_H
#include "pal_arch.h"
#include <stdbool.h>
#include <stdint.h>
typedef unsigned long u_register_t;
/**********************************************************************
* Macros which create inline functions to read or write CPU system
* registers
*********************************************************************/
#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
static inline u_register_t read_ ## _name(void) \
{ \
u_register_t v; \
__asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
return v; \
}
#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
static inline void write_ ## _name(u_register_t v) \
{ \
__asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
}
#define SYSREG_WRITE_CONST(reg_name, v) \
__asm__ volatile ("msr " #reg_name ", %0" : : "i" (v))
/* Define read function for system register */
#define DEFINE_SYSREG_READ_FUNC(_name) \
_DEFINE_SYSREG_READ_FUNC(_name, _name)
/* Define read & write function for system register */
#define DEFINE_SYSREG_RW_FUNCS(_name) \
_DEFINE_SYSREG_READ_FUNC(_name, _name) \
_DEFINE_SYSREG_WRITE_FUNC(_name, _name)
/* Define read & write function for renamed system register */
#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
_DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
_DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
/* Define read function for renamed system register */
#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
_DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
/* Define write function for renamed system register */
#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
_DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
/**********************************************************************
* Macros to create inline functions for system instructions
*********************************************************************/
/* Define function for simple system instruction */
#define DEFINE_SYSOP_FUNC(_op) \
static inline void _op(void) \
{ \
__asm__ (#_op); \
}
/* Define function for system instruction with type specifier */
#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
static inline void _op ## _type(void) \
{ \
__asm__ (#_op " " #_type); \
}
/* Define function for system instruction with register parameter */
#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
static inline void _op ## _type(uint64_t v) \
{ \
__asm__ (#_op " " #_type ", %0" : : "r" (v)); \
}
/*******************************************************************************
* Cache maintenance accessor prototypes
******************************************************************************/
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
void dcsw_op_louis(u_register_t op_type);
void dcsw_op_all(u_register_t op_type);
void disable_mmu(void);
void disable_mmu_icache(void);
/*******************************************************************************
* Misc. accessor prototypes
******************************************************************************/
#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
DEFINE_SYSREG_RW_FUNCS(par_el1)
DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
DEFINE_SYSREG_READ_FUNC(id_afr0_el1)
DEFINE_SYSREG_READ_FUNC(CurrentEl)
DEFINE_SYSREG_READ_FUNC(ctr_el0)
DEFINE_SYSREG_RW_FUNCS(daif)
DEFINE_SYSREG_RW_FUNCS(spsr_el1)
DEFINE_SYSREG_RW_FUNCS(elr_el1)
DEFINE_SYSOP_FUNC(wfi)
DEFINE_SYSOP_FUNC(wfe)
DEFINE_SYSOP_FUNC(sev)
DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
DEFINE_SYSOP_TYPE_FUNC(dmb, st)
DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
DEFINE_SYSOP_FUNC(isb)
/*******************************************************************************
* System register accessor prototypes
******************************************************************************/
DEFINE_SYSREG_READ_FUNC(midr_el1)
DEFINE_SYSREG_READ_FUNC(mpidr_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
DEFINE_SYSREG_READ_FUNC(cntpct_el0)
/* GICv3 System Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
#define IS_IN_EL(x) \
(GET_EL(read_CurrentEl()) == MODE_EL##x)
#define IS_IN_EL1() IS_IN_EL(1)
#define IS_IN_EL2() IS_IN_EL(2)
#define IS_IN_EL3() IS_IN_EL(3)
static inline unsigned int get_current_el(void)
{
return GET_EL(read_CurrentEl());
}
/*
* Check if an EL is implemented from AA64PFR0 register fields.
*/
static inline uint64_t el_implemented(unsigned int el)
{
if (el > 3U)
{
return EL_IMPL_NONE;
}
else
{
unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
}
}
#endif /* ARCH_HELPERS_H */
| 33.8867 | 80 | 0.657944 |
501548c86ee5423286867ca58fc5cfebe172f053 | 2,020 | h | C | examples/c/rkh/shared_freertos/app/inc/client.h | mrds90/firmware_v3 | 52e36085fd3fa8917786bdffc2143de2ae3d1b9a | [
"BSD-3-Clause"
] | 23 | 2019-08-01T07:55:41.000Z | 2021-11-28T15:44:52.000Z | examples/c/rkh/shared_freertos/app/inc/client.h | td3-frm/freeRTOS | 967665cafb3d8e1d626f063898fa0bb4d6111eb5 | [
"BSD-3-Clause"
] | 21 | 2019-10-04T13:20:02.000Z | 2021-08-07T00:16:08.000Z | examples/c/rkh/shared_freertos/app/inc/client.h | td3-frm/freeRTOS | 967665cafb3d8e1d626f063898fa0bb4d6111eb5 | [
"BSD-3-Clause"
] | 52 | 2019-07-20T22:56:21.000Z | 2022-02-10T20:03:16.000Z | /**
* \file client.h
* \brief Example application
*/
/* -------------------------- Development history -------------------------- */
/*
* 2016.03.17 LeFr v1.0.00 Initial version
*/
/* -------------------------------- Authors -------------------------------- */
/*
* LeFr Leandro Francucci lf@vortexmakes.com
*/
/* --------------------------------- Notes --------------------------------- */
/* --------------------------------- Module -------------------------------- */
#ifndef __CLIENT_H__
#define __CLIENT_H__
/* ----------------------------- Include files ----------------------------- */
#include "rkh.h"
#include "shared.h"
/* ---------------------- External C language linkage ---------------------- */
#ifdef __cplusplus
extern "C" {
#endif
/* --------------------------------- Macros -------------------------------- */
#define CLI(clino_) RKH_ARRAY_SMA(clis, clino_)
#define CLI0 CLI(0)
#define CLI1 CLI(1)
#define CLI2 CLI(2)
#define CLI3 CLI(3)
#define CLI_STK_SIZE (2048 / sizeof(RKH_THREAD_STK_TYPE))
/* -------------------------------- Constants ------------------------------ */
/* ................................ Signals ................................ */
/* ........................ Declares active object ......................... */
enum
{
CLI_PRIO_0 = 1, CLI_PRIO_1, CLI_PRIO_2, CLI_PRIO_3,
MAX_CLI_PRIO,
NUM_CLIENTS = MAX_CLI_PRIO - 1,
};
RKH_ARRAY_SMA_DCLR( clis, NUM_CLIENTS );
/* ------------------------------- Data types ------------------------------ */
/* -------------------------- External variables --------------------------- */
/* -------------------------- Function prototypes -------------------------- */
/* -------------------- External C language linkage end -------------------- */
#ifdef __cplusplus
}
#endif
/* ------------------------------ Module end ------------------------------- */
#endif
/* ------------------------------ End of file ------------------------------ */
| 32.580645 | 79 | 0.333663 |
a1cf2b944ed63046f61ea7f663b3d99c3404e98f | 683 | h | C | Guasap/include/UsuarioMensaje.h | matbentancur/pavlab6gr4 | 2447cb4137f34749b0e0512d28f67afcab5eb4fa | [
"MIT"
] | null | null | null | Guasap/include/UsuarioMensaje.h | matbentancur/pavlab6gr4 | 2447cb4137f34749b0e0512d28f67afcab5eb4fa | [
"MIT"
] | null | null | null | Guasap/include/UsuarioMensaje.h | matbentancur/pavlab6gr4 | 2447cb4137f34749b0e0512d28f67afcab5eb4fa | [
"MIT"
] | null | null | null | #ifndef USUARIOMENSAJE_H
#define USUARIOMENSAJE_H
#include "Usuario.h"
class Usuario;
class UsuarioMensaje {
private:
bool visto;
FechaHora vistoFechaHora;
bool eliminado;
Usuario* usuario;
public:
UsuarioMensaje(bool, bool, Usuario*);
UsuarioMensaje(bool, FechaHora, bool, Usuario*);
bool getVisto();
void setVisto(bool);
FechaHora getVistoFechaHora();
void setVistoFechaHora(FechaHora);
bool getEliminado();
void setEliminado(bool);
Usuario* getUsuario();
DtReceptor getDtReceptor();
virtual ~UsuarioMensaje();
};
#endif // USUARIOMENSAJE_H
| 18.459459 | 56 | 0.63104 |
1cd141698045542bb61a23b40401134cdde98e2d | 184 | h | C | include/kernel/kernel.h | svenpilz/idaeus | d9686cfe0f63e70eec9a0b426c238b8a83f8d466 | [
"MIT"
] | null | null | null | include/kernel/kernel.h | svenpilz/idaeus | d9686cfe0f63e70eec9a0b426c238b8a83f8d466 | [
"MIT"
] | null | null | null | include/kernel/kernel.h | svenpilz/idaeus | d9686cfe0f63e70eec9a0b426c238b8a83f8d466 | [
"MIT"
] | null | null | null | #ifndef INCLUDE_KERNEL_KERNEL_H
#define INCLUDE_KERNEL_KERNEL_H
#include "interfaces/arch.h"
arch_register_set_t* kernel_handle_interrupt(arch_register_set_t* register_set);
#endif
| 20.444444 | 80 | 0.858696 |
f7db8e8608c7996baf9f08a5e2c3bf4414ab9ff0 | 566 | h | C | unit_tests/include/XCacheTest.h | MultiSight/multisight-xsdk | 02268e1aeb1313cfb2f9515d08d131a4389e49f2 | [
"BSL-1.0"
] | null | null | null | unit_tests/include/XCacheTest.h | MultiSight/multisight-xsdk | 02268e1aeb1313cfb2f9515d08d131a4389e49f2 | [
"BSL-1.0"
] | null | null | null | unit_tests/include/XCacheTest.h | MultiSight/multisight-xsdk | 02268e1aeb1313cfb2f9515d08d131a4389e49f2 | [
"BSL-1.0"
] | null | null | null | #ifndef XCacheTest_h
#define XCacheTest_h
#include "framework.h"
class XCacheTest : public test_fixture
{
public:
TEST_SUITE(XCacheTest);
TEST(XCacheTest::TestDefaultConstructor);
TEST(XCacheTest::TestAdd);
TEST(XCacheTest::TestAddTillFull);
TEST(XCacheTest::TestDestroysCorrectItem);
TEST_SUITE_END();
virtual ~XCacheTest() throw() {}
void setup();
void teardown();
protected:
void TestDefaultConstructor();
void TestAdd();
void TestAddTillFull();
void TestDestroysCorrectItem();
};
#endif
| 18.866667 | 50 | 0.687279 |
08fd579e605549a08f631c614eef2fc4b5f85bef | 1,716 | c | C | tests/swf/trace/system-onstatus-netstream.c | lieff/lvg | d8f8f77ba42c714532c40380ce6b013a82ffb43b | [
"CC0-1.0"
] | 100 | 2016-08-02T07:26:37.000Z | 2022-03-27T15:15:28.000Z | tests/swf/trace/system-onstatus-netstream.c | lieff/lvg | d8f8f77ba42c714532c40380ce6b013a82ffb43b | [
"CC0-1.0"
] | 4 | 2018-08-12T18:28:29.000Z | 2022-02-28T03:06:16.000Z | tests/swf/trace/system-onstatus-netstream.c | lieff/lvg | d8f8f77ba42c714532c40380ce6b013a82ffb43b | [
"CC0-1.0"
] | 9 | 2018-01-11T13:35:00.000Z | 2021-08-09T07:15:25.000Z | /* gcc `pkg-config --libs --cflags libming` system-onstatus-netstream.c -o system-onstatus-netstream && ./system-onstatus-netstream
*/
#include <ming.h>
int
main (int argc, char **argv)
{
SWFMovie movie;
SWFVideoStream video;
SWFDisplayItem item;
SWFAction action;
if (Ming_init ())
return 1;
Ming_useSWFVersion (7);
movie = newSWFMovie();
SWFMovie_setRate (movie, 1);
SWFMovie_setDimension (movie, 200, 150);
video = newSWFVideoStream ();
SWFVideoStream_setDimension (video, 200, 150);
item = SWFMovie_add (movie, (SWFBlock) video);
SWFDisplayItem_setName (item, "video");
action = compileSWFActionCode (""
"trace (\"Test System.onStatus\");"
""
"System.onStatus = function (info)"
"{"
" trace ('System.onStatus ' + info.code);"
" trace (arguments);"
" trace (arguments.caller);"
" trace (arguments.callee);"
" delete (ns.onStatus);"
""
" ns.onStatus = function () {"
" trace ('ns.onStatus ' + info.code);"
" getURL ('fscommand:quit', '');"
" };"
""
" trace (\"Calling play\");"
" ns.play (\"404.flv\");"
"};"
""
"var nc = new NetConnection ();"
"nc.connect (null);"
"var ns = new NetStream (nc);"
"video.attachVideo (ns);"
"ns.setBufferTime (5);"
""
"function get () { trace ('get'); return null; };"
"function set () { trace ('set: ' + arguments); };"
"ns.addProperty ('onStatus', get, set);"
""
"trace (\"Calling play\");"
"ns.play (\"404.flv\");"
"");
SWFMovie_add (movie, (SWFBlock) action);
SWFMovie_save (movie, "system-onstatus-netstream.swf");
return 0;
}
| 27.677419 | 131 | 0.566434 |
203168417492ce27a25225bb53096e48c8751f2b | 31,715 | h | C | hi_dsp/ProcessorInterfaces.h | Matt-Dub/HISE | ae2dd1653e1c8d749a9088edcd573de6252b0b96 | [
"Intel"
] | null | null | null | hi_dsp/ProcessorInterfaces.h | Matt-Dub/HISE | ae2dd1653e1c8d749a9088edcd573de6252b0b96 | [
"Intel"
] | null | null | null | hi_dsp/ProcessorInterfaces.h | Matt-Dub/HISE | ae2dd1653e1c8d749a9088edcd573de6252b0b96 | [
"Intel"
] | null | null | null | /* ===========================================================================
*
* This file is part of HISE.
* Copyright 2016 Christoph Hart
*
* HISE is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* HISE is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with HISE. If not, see <http://www.gnu.org/licenses/>.
*
* Commercial licenses for using HISE in an closed source project are
* available on request. Please visit the project's website to get more
* information about commercial licensing:
*
* http://www.hise.audio/
*
* HISE is based on the JUCE library,
* which must be separately licensed for closed source applications:
*
* http://www.juce.com
*
* ===========================================================================
*/
#ifndef PROCESSORINTERFACES_H_INCLUDED
#define PROCESSORINTERFACES_H_INCLUDED
namespace hise { using namespace juce;
using namespace snex;
class ProcessorWithExternalData : public ExternalDataHolder
{
public:
ProcessorWithExternalData(MainController* mc) :
mc_internal(mc)
{};
virtual ~ProcessorWithExternalData() {};
bool removeDataObject(ExternalData::DataType t, int index) override
{
return true;
}
void linkTo(ExternalData::DataType type, ExternalDataHolder& src, int srcIndex, int dstIndex) override
{
Random r;
Colour c((uint32)r.nextInt());
SharedReference d1(type, srcIndex, c);
SharedReference d2(type, dstIndex, c);
if(auto ped = dynamic_cast<ProcessorWithExternalData*>(&src))
{
ped->sharedReferences.addIfNotAlreadyThere(d1);
sharedReferences.addIfNotAlreadyThere(d2);
referenceShared(type, dstIndex);
}
else
{
jassertfalse;
}
}
FilterDataObject* getFilterData(int index) override
{
jassertfalse; // soon...
return nullptr;
}
Colour getSharedReferenceColour(ExternalData::DataType t, int index) const
{
SharedReference d(t, index, Colours::transparentBlack);
for (const auto& r : sharedReferences)
{
if (d == r)
return r.c;
}
return Colours::transparentBlack;
}
protected:
ComplexDataUIBase* createAndInit(ExternalData::DataType t)
{
ComplexDataUIBase* d;
d = ExternalData::create(t);
if (auto af = dynamic_cast<MultiChannelAudioBuffer*>(d))
af->setProvider(new hise::PooledAudioFileDataProvider(mc_internal));
d->setGlobalUIUpdater(getUpdater());
d->setUndoManager(getUndoManager());
return d;
}
virtual void referenceShared(ExternalData::DataType type, int index)
{
jassertfalse;
}
private:
struct SharedReference
{
SharedReference(ExternalData::DataType type_, int index_, Colour c_) :
type(type_),
index(index_),
c(c_)
{};
bool operator==(const SharedReference& other) const
{
return index == other.index && type == other.type;
}
ExternalData::DataType type;
int index;
Colour c;
};
Array<SharedReference> sharedReferences;
PooledUIUpdater* getUpdater()
{
return mc_internal->getGlobalUIUpdater();
}
UndoManager* getUndoManager()
{
return mc_internal->getControlUndoManager();
}
MainController* mc_internal = nullptr;
};
/** A baseclass interface for processors with a single data type. */
class ProcessorWithSingleStaticExternalData: public ProcessorWithExternalData
{
public:
ProcessorWithSingleStaticExternalData(MainController* mc, ExternalData::DataType t, int numObjects=1):
ProcessorWithExternalData(mc),
dataType(t)
{
for (int i = 0; i < numObjects; i++)
{
ownedObjects.add(createAndInit(t));
}
}
virtual ~ProcessorWithSingleStaticExternalData() {};
Table* getTable(int index) final override
{
return static_cast<Table*>(getWithoutCreating(ExternalData::DataType::Table, index));
}
SliderPackData* getSliderPack(int index) final override
{
return static_cast<SliderPackData*>(getWithoutCreating(ExternalData::DataType::SliderPack, index));
}
MultiChannelAudioBuffer* getAudioFile(int index) final override
{
return static_cast<MultiChannelAudioBuffer*>(getWithoutCreating(ExternalData::DataType::AudioFile, index));
}
SimpleRingBuffer* getDisplayBuffer(int index) final override
{
return static_cast<SimpleRingBuffer*>(getWithoutCreating(ExternalData::DataType::DisplayBuffer, index));
}
int getNumDataObjects(ExternalData::DataType t) const final override
{
return t == dataType ? ownedObjects.size() : 0;
}
void linkTo(ExternalData::DataType type, ExternalDataHolder& src, int srcIndex, int dstIndex) override
{
jassert(type == dataType);
if(isPositiveAndBelow(srcIndex, src.getNumDataObjects(dataType)))
{
ComplexDataUIBase::Ptr old = getComplexBaseType(type, dstIndex);
auto otherData = src.getComplexBaseType(type, srcIndex);
ownedObjects.set(dstIndex, otherData);
ProcessorWithExternalData::linkTo(type, src, srcIndex, dstIndex);
}
}
private:
friend class LookupTableProcessor;
friend class SliderPackProcessor;
friend class AudioSampleProcessor;
ComplexDataUIBase* getWithoutCreating(ExternalData::DataType requiredType, int index) const
{
if (dataType == requiredType && isPositiveAndBelow(index, ownedObjects.size()))
{
return ownedObjects[index].get();
}
return nullptr;
}
const ExternalData::DataType dataType;
ReferenceCountedArray<ComplexDataUIBase> ownedObjects;
};
/** A baseclass interface for a constant amount of multiple data types. */
class ProcessorWithStaticExternalData : public ProcessorWithExternalData
{
public:
ProcessorWithStaticExternalData(MainController* mc, int numTables, int numSliderPacks, int numAudioFiles, int numDisplayBuffers):
ProcessorWithExternalData(mc)
{
for (int i = 0; i < numTables; i++)
tables.add(static_cast<Table*>(createAndInit(ExternalData::DataType::Table)));
for (int i = 0; i < numSliderPacks; i++)
sliderPacks.add(static_cast<SliderPackData*>(createAndInit(ExternalData::DataType::SliderPack)));
for (int i = 0; i < numAudioFiles; i++)
audioFiles.add(static_cast<MultiChannelAudioBuffer*>(createAndInit(ExternalData::DataType::AudioFile)));
for (int i = 0; i < numDisplayBuffers; i++)
displayBuffers.add(static_cast<SimpleRingBuffer*>(createAndInit(ExternalData::DataType::DisplayBuffer)));
}
int getNumDataObjects(ExternalData::DataType t) const final override
{
switch (t)
{
case ExternalData::DataType::Table: return tables.size();
case ExternalData::DataType::SliderPack: return sliderPacks.size();
case ExternalData::DataType::AudioFile: return audioFiles.size();
case ExternalData::DataType::DisplayBuffer: return displayBuffers.size();
default: return 0;
}
return 0;
}
Table* getTable(int index) final override
{
if(isPositiveAndBelow(index, tables.size()))
return tables[index].get();
return nullptr;
}
SliderPackData* getSliderPack(int index) final override
{
if (isPositiveAndBelow(index, sliderPacks.size()))
return sliderPacks[index].get();
return nullptr;
}
MultiChannelAudioBuffer* getAudioFile(int index) final override
{
if (isPositiveAndBelow(index, audioFiles.size()))
return audioFiles[index].get();
return nullptr;
}
SimpleRingBuffer* getDisplayBuffer(int index) final override
{
if (isPositiveAndBelow(index, displayBuffers.size()))
return displayBuffers[index].get();
return nullptr;
}
SampleLookupTable* getTableUnchecked(int index = 0)
{
return static_cast<SampleLookupTable*>(*(tables.begin() + index));
}
const SampleLookupTable* getTableUnchecked(int index = 0) const
{
return static_cast<SampleLookupTable*>(*(tables.begin() + index));
}
SliderPackData* getSliderPackDataUnchecked(int index = 0)
{
return *(sliderPacks.begin() + index);
}
const SliderPackData* getSliderPackDataUnchecked(int index = 0) const
{
return *(sliderPacks.begin() + index);
}
MultiChannelAudioBuffer* getAudioFileUnchecked(int index = 0)
{
return *(audioFiles.begin() + index);
}
const MultiChannelAudioBuffer* getAudioFileUnchecked(int index = 0) const
{
return *(audioFiles.begin() + index);
}
SimpleRingBuffer* getDisplayBufferUnchecked(int index = 0)
{
return *(displayBuffers.begin() + index);
}
const SimpleRingBuffer* getDisplayBufferUnchecked(int index = 0) const
{
return *(displayBuffers.begin() + index);
}
void linkTo(ExternalData::DataType type, ExternalDataHolder& src, int srcIndex, int dstIndex) override
{
if(isPositiveAndBelow(dstIndex, getNumDataObjects(type)))
{
ComplexDataUIBase::Ptr old = getComplexBaseType(type, dstIndex);
auto externalData = src.getComplexBaseType(type, srcIndex);
switch(type)
{
case ExternalData::DataType::Table:
tables.set(dstIndex, dynamic_cast<Table*>(externalData));
break;
case ExternalData::DataType::SliderPack:
sliderPacks.set(dstIndex, dynamic_cast<SliderPackData*>(externalData));
break;
case ExternalData::DataType::AudioFile:
audioFiles.set(dstIndex, dynamic_cast<MultiChannelAudioBuffer*>(externalData));
break;
case ExternalData::DataType::DisplayBuffer:
displayBuffers.set(dstIndex, dynamic_cast<SimpleRingBuffer*>(externalData));
break;
default:
jassertfalse;
break;
}
ProcessorWithExternalData::linkTo(type, src, srcIndex, dstIndex);
}
}
private:
ReferenceCountedArray<SliderPackData> sliderPacks;
ReferenceCountedArray<Table> tables;
ReferenceCountedArray<MultiChannelAudioBuffer> audioFiles;
ReferenceCountedArray<SimpleRingBuffer> displayBuffers;
};
/** A baseclass for processors with multiple data types that can be resized
*/
class ProcessorWithDynamicExternalData : public ProcessorWithExternalData
{
public:
ProcessorWithDynamicExternalData(MainController* mc) :
ProcessorWithExternalData(mc)
{
};
virtual ~ProcessorWithDynamicExternalData() {};
SliderPackData* getSliderPack(int index) final override
{
if (auto d = sliderPacks[index])
return d.get();
auto s = createAndInit(snex::ExternalData::DataType::SliderPack);
sliderPacks.set(index, static_cast<SliderPackData*>(s));
return sliderPacks[index].get();
}
Table* getTable(int index) final override
{
if (auto d = tables[index])
return d.get();
auto s = createAndInit(snex::ExternalData::DataType::Table);
tables.set(index, static_cast<Table*>(s));
return tables[index].get();
}
MultiChannelAudioBuffer* getAudioFile(int index) final override
{
if (auto d = audioFiles[index])
return d.get();
auto s = createAndInit(snex::ExternalData::DataType::AudioFile);
audioFiles.set(index, static_cast<MultiChannelAudioBuffer*>(s));
return audioFiles[index].get();
}
SimpleRingBuffer* getDisplayBuffer(int index) final override
{
if (auto d = ringBuffers[index])
return d.get();
auto s = createAndInit(snex::ExternalData::DataType::DisplayBuffer);
ringBuffers.set(index, static_cast<SimpleRingBuffer*>(s));
return ringBuffers[index].get();
}
FilterDataObject* getFilterData(int index) final override
{
if (auto d = filterData[index])
return d.get();
auto s = createAndInit(snex::ExternalData::DataType::FilterCoefficients);
filterData.set(index, static_cast<FilterDataObject*>(s));
return filterData[index].get();
}
int getNumDataObjects(ExternalData::DataType t) const
{
switch (t)
{
case ExternalData::DataType::SliderPack: return sliderPacks.size();
case ExternalData::DataType::Table: return tables.size();
case ExternalData::DataType::AudioFile: return audioFiles.size();
case ExternalData::DataType::DisplayBuffer: return ringBuffers.size();
case ExternalData::DataType::FilterCoefficients: return filterData.size();
default: return 0;
}
return 0;
}
void saveComplexDataTypeAmounts(ValueTree& v) const
{
using namespace scriptnode;
ExternalData::forEachType([&v, this](ExternalData::DataType t)
{
auto numObjects = getNumDataObjects(t);
if (numObjects > 0)
v.setProperty(ExternalData::getNumIdentifier(t), numObjects, nullptr);
});
}
void restoreComplexDataTypes(const ValueTree& v)
{
using namespace scriptnode;
ExternalData::forEachType([this, &v](ExternalData::DataType t)
{
auto numObjects = (int)v.getProperty(ExternalData::getNumIdentifier(t), 0);
for (int i = 0; i < numObjects; i++)
getComplexBaseType(t, i);
});
}
void registerExternalObject(ExternalData::DataType t, int index, ComplexDataUIBase* obj)
{
switch (t)
{
case ExternalData::DataType::Table:
tables.set(index, dynamic_cast<Table*>(obj)); break;
case ExternalData::DataType::SliderPack:
sliderPacks.set(index, dynamic_cast<SliderPackData*>(obj)); break;
case ExternalData::DataType::AudioFile:
audioFiles.set(index, dynamic_cast<MultiChannelAudioBuffer*>(obj)); break;
case ExternalData::DataType::DisplayBuffer:
ringBuffers.set(index, dynamic_cast<SimpleRingBuffer*>(obj)); break;
case ExternalData::DataType::FilterCoefficients:
filterData.set(index, dynamic_cast<FilterDataObject*>(obj)); break;
default: jassertfalse; break;
}
}
void linkTo(ExternalData::DataType type, ExternalDataHolder& src, int srcIndex, int dstIndex) override
{
if(isPositiveAndBelow(dstIndex, getNumDataObjects(type)))
{
auto ed = src.getComplexBaseType(type, srcIndex);
registerExternalObject(type, dstIndex, ed);
ProcessorWithExternalData::linkTo(type, src, srcIndex, dstIndex);
}
}
private:
ReferenceCountedArray<SliderPackData> sliderPacks;
ReferenceCountedArray<Table> tables;
ReferenceCountedArray<MultiChannelAudioBuffer> audioFiles;
ReferenceCountedArray<SimpleRingBuffer> ringBuffers;
ReferenceCountedArray<FilterDataObject> filterData;
JUCE_DECLARE_WEAK_REFERENCEABLE(ProcessorWithDynamicExternalData);
};
/** A Processor that uses a Table.
* @ingroup processor_interfaces
*
* If your Processor uses a Table object for anything, you can subclass it from this interface class and use its Table.
* */
class LookupTableProcessor: public ProcessorWithSingleStaticExternalData
{
public:
struct ProcessorValueConverter
{
ProcessorValueConverter() :
converter(Table::getDefaultTextValue),
processor(nullptr)
{};
ProcessorValueConverter(const Table::ValueTextConverter& c, Processor* p) :
converter(c),
processor(p)
{};
ProcessorValueConverter(Processor* p) :
converter(Table::getDefaultTextValue),
processor(p)
{};
bool operator==(const ProcessorValueConverter& other) const
{
return other.processor == processor;
}
explicit operator bool() const
{
return processor != nullptr;
}
String getDefaultTextValue(float input)
{
if (processor.get())
return converter(input);
else
return Table::getDefaultTextValue(input);
}
Table::ValueTextConverter converter;
WeakReference<Processor> processor;
private:
JUCE_DECLARE_NON_COPYABLE_WITH_LEAK_DETECTOR(ProcessorValueConverter);
};
// ================================================================================================================
LookupTableProcessor(MainController* mc, int numTables);
virtual ~LookupTableProcessor();
//SET_PROCESSOR_CONNECTOR_TYPE_ID("LookupTableProcessor");
// ================================================================================================================
void addYValueConverter(const Table::ValueTextConverter& converter, Processor* p)
{
if (p == dynamic_cast<Processor*>(this))
defaultYConverter = converter;
else
{
for (int i = 0; i < yConverters.size(); i++)
{
auto thisP = yConverters[i]->processor.get();
if (thisP == nullptr || thisP == p)
yConverters.remove(i--);
}
yConverters.add(new ProcessorValueConverter(converter, p ));
}
updateYConverters();
}
void refreshYConvertersAfterRemoval()
{
for (int i = 0; i < yConverters.size(); i++)
{
auto thisP = yConverters[i]->processor.get();
if (thisP == nullptr)
yConverters.remove(i--);
}
updateYConverters();
}
SampleLookupTable* getTableUnchecked(int index = 0)
{
return static_cast<SampleLookupTable*>(ownedObjects.getUnchecked(index).get());
}
const SampleLookupTable* getTableUnchecked(int index = 0) const
{
return static_cast<const SampleLookupTable*>(ownedObjects.getUnchecked(index).get());
}
protected:
Table::ValueTextConverter defaultYConverter = Table::getDefaultTextValue;
private:
void updateYConverters()
{
const auto cToUse = yConverters.size() == 1 ? yConverters.getFirst()->converter : defaultYConverter;
for (int i = 0; i < getNumDataObjects(snex::ExternalData::DataType::Table); i++)
getTable(i)->setYTextConverterRaw(cToUse);
}
OwnedArray<ProcessorValueConverter> yConverters;
JUCE_DECLARE_NON_COPYABLE_WITH_LEAK_DETECTOR(LookupTableProcessor);
JUCE_DECLARE_WEAK_REFERENCEABLE(LookupTableProcessor);
// ================================================================================================================
};
class SliderPackData;
/** A Processor that uses a SliderPack.
* @ingroup processor_interfaces
*
* It is a pure virtual class interface without member data to prevent the Diamond of Death.
*/
class SliderPackProcessor: public ProcessorWithSingleStaticExternalData
{
public:
// ================================================================================================================
SliderPackProcessor(MainController* mc, int numSliderPacks):
ProcessorWithSingleStaticExternalData(mc, ExternalData::DataType::SliderPack, numSliderPacks)
{};
SliderPackData* getSliderPackUnchecked(int index = 0)
{
return static_cast<SliderPackData*>(ownedObjects.getUnchecked(index).get());
}
const SliderPackData* getSliderPackUnchecked(int index = 0) const
{
return static_cast<const SliderPackData*>(ownedObjects.getUnchecked(index).get());
}
private:
JUCE_DECLARE_NON_COPYABLE_WITH_LEAK_DETECTOR(SliderPackProcessor);
JUCE_DECLARE_WEAK_REFERENCEABLE(SliderPackProcessor);
// ================================================================================================================
};
using namespace snex;
/** A Processor that uses a single audio sample.
* @ingroup processor_interfaces
*
* Be
*
* In order to use this class with a AudioSampleBufferComponent, just follow these steps:
*
* 1. Create a AudioSampleBufferComponent and use the method getCache() in the constructor.
* 2. Set the reference to the AudioSampleBuffer with AudioSampleBufferComponent::setAudioSampleBuffer();
* 3. Add the AudioSampleBuffer as ChangeListener (and remove it in the destructor!)
* 4. Add an AreaListener to the AudioSampleBufferComponent and call setRange() and setLoadedFile in the rangeChanged() callback
Additional functions:
- load / save to valuetree
- reload when pool reference has changed
- loop stuff
*/
class AudioSampleProcessor: public PoolBase::Listener,
public ProcessorWithSingleStaticExternalData
{
public:
// ================================================================================================================
enum SyncToHostMode
{
FreeRunning = 1,
OneBeat,
TwoBeats,
OneBar,
TwoBars,
FourBars
};
AudioSampleProcessor(MainController* mc) :
ProcessorWithSingleStaticExternalData(mc, ExternalData::DataType::AudioFile, 1)
{
currentPool = &mc->getActiveFileHandler()->pool->getAudioSampleBufferPool();
};
/** Automatically releases the sample in the pool. */
virtual ~AudioSampleProcessor();
// ================================================================================================================
/** Call this method within your exportAsValueTree method to store the sample settings. */
void saveToValueTree(ValueTree &v) const;;
/** Call this method within your restoreFromValueTree() method to load the sample settings. */
void restoreFromValueTree(const ValueTree &v);
/** This loads the file from disk (or from the pool, if existing and loadThisFile is false. */
void setLoadedFile(const String &fileName, bool loadThisFile = false, bool forceReload = false);
/** Sets the sample range that should be used in the plugin.
*
* This is called automatically if a AudioSampleBufferComponent is set up correctly.
*/
void poolEntryReloaded(PoolReference referenceThatWasChanged) override;
/** Returns the filename that was loaded.
*
* It is possible that the file does not exist on your system:
* If you restore a pool completely from a ValueTree, it still uses the absolute filename as identification.
*/
String getFileName() const { return getBuffer().toBase64String(); };
double getSampleRateForLoadedFile() const { return getBuffer().sampleRate; }
AudioSampleBuffer& getAudioSampleBuffer() { return getBuffer().getBuffer(); }
const AudioSampleBuffer& getAudioSampleBuffer() const { return getBuffer().getBuffer(); }
MultiChannelAudioBuffer& getBuffer() { return *getAudioFileUnchecked(0); }
const MultiChannelAudioBuffer& getBuffer() const { return *getAudioFileUnchecked(0); }
MultiChannelAudioBuffer* getAudioFileUnchecked(int index = 0)
{
return static_cast<MultiChannelAudioBuffer*>(ownedObjects.getUnchecked(index).get());
}
const MultiChannelAudioBuffer* getAudioFileUnchecked(int index = 0) const
{
return static_cast<const MultiChannelAudioBuffer*>(ownedObjects.getUnchecked(index).get());
}
protected:
WeakReference<AudioSampleBufferPool> currentPool;
private:
int getConstrainedLoopValue(String metadata);
// ================================================================================================================
};
/** A Processor that has a dynamic size of child processors.
* @ingroup processor_interfaces
*
* If your Processor has more than a fixed amount of internal child processors, derive it from this class, write a Chain::Handler subclass with all
* needed operations and you can add / delete Processors on runtime.
*
* You might want to overwrite the Processors functions getNumChildProcessors() and getChildProcessor() with the handlers methods (handle internal chains manually)
* This allows the restoreState function to only clear the dynamic list of processors.
*/
class Chain
{
public:
// ====================================================================================================================
/**
*
* Subclass this, put it in your subclassed Chain and return a member object of the chain in Chain::getHandler().
*/
class Handler
{
public:
struct Listener
{
enum EventType
{
ProcessorAdded,
ProcessorDeleted,
ProcessorOrderChanged,
Cleared,
numEventTypes
};
virtual ~Listener() {};
virtual void processorChanged(EventType t, Processor* p) = 0;
JUCE_DECLARE_WEAK_REFERENCEABLE(Listener);
};
// ================================================================================================================
virtual ~Handler() {};
/** Adds a new processor to the chain. It must be owned by the chain. */
virtual void add(Processor *newProcessor, Processor *siblingToInsertBefore) = 0;
/** Deletes a processor from the chain. */
virtual void remove(Processor *processorToBeRemoved, bool deleteProcessor=true) = 0;
/** Returns the processor at the index. */
virtual Processor *getProcessor(int processorIndex) = 0;
virtual const Processor *getProcessor(int processorIndex) const = 0;
/** Overwrite this method and implement a move operation. */
virtual void moveProcessor(Processor* /*processorInChain*/, int /*delta*/) {};
/** Returns the amount of processors. */
virtual int getNumProcessors() const = 0;
/** Deletes all Processors in the Chain. */
virtual void clear() = 0;
void clearAsync(Processor* parent);
void addListener(Listener* l)
{
listeners.addIfNotAlreadyThere(l);
}
void removeListener(Listener* l)
{
listeners.removeAllInstancesOf(l);
}
void addPostEventListener(Listener* l)
{
postEventlisteners.addIfNotAlreadyThere(l);
}
void removePostEventListener(Listener* l)
{
postEventlisteners.removeAllInstancesOf(l);
}
void notifyListeners(Listener::EventType t, Processor* p)
{
ScopedLock sl(listeners.getLock());
for (auto l : listeners)
{
if (l != nullptr)
l->processorChanged(t, p);
}
}
void notifyPostEventListeners(Listener::EventType t, Processor* p)
{
ScopedLock sl(postEventlisteners.getLock());
for (auto l : postEventlisteners)
{
if (l != nullptr)
l->processorChanged(t, p);
}
}
private:
Array<WeakReference<Listener>, CriticalSection> listeners;
Array<WeakReference<Listener>, CriticalSection> postEventlisteners;
};
// ===================================================================================================================
/** Restores a Chain from a ValueTree. It creates all processors and restores their values. It returns false, if anything went wrong. */
bool restoreChain(const ValueTree &v);
/** Overwrite this and return the processor that owns this chain if it exists. */
virtual Processor *getParentProcessor() = 0;
/** Overwrite this and return the processor that owns this chain if it exists. */
virtual const Processor *getParentProcessor() const = 0;
/** return your subclassed Handler. */
virtual Handler *getHandler() = 0;
/** read only access to the Handler. */
virtual const Handler *getHandler() const = 0;
virtual ~Chain() {};
/** Sets the FactoryType that will be used. */
virtual void setFactoryType(FactoryType *newType) = 0;
/** Returns the Factory type this processor is using. */
virtual FactoryType *getFactoryType() const = 0;
// ================================================================================================================
};
#define ADD_NAME_TO_TYPELIST(x) (typeNames.add(FactoryType::ProcessorEntry(x::getClassType(), x::getClassName())))
/** This interface class lets the MainController do its work.
* @ingroup factory
*
* You can tell a Processor (which should also be a Chain to make sense) to use a specific FactoryType
* with Processor::setFactoryType(), which will then use it in its popup menu to create the possible Processors.
* Simply overwrite these two functions in your subclass:
*
* Processor* createProcessor (int typeIndex, const String &id);
* const StringArray& getTypeNames() const;
*
* A FactoryType constrains the number of creatable Processors by
*
* - Type (will be defined by the subclass)
* - Constrainer (can be added to a FactoryType and uses runtime information like parent processor etc.)
*
*/
class FactoryType
{
public:
// ================================================================================================================
/** A Constrainer objects can impose restrictions on a particular FactoryType
*
* If you want to restrict the selection of possible Processor types, you can
* subclass this, overwrite allowType with your custom rules and call
* setConstrainer() on the FactoryType you want to limit.
*/
class Constrainer: public BaseConstrainer
{
public:
virtual ~Constrainer() {};
/** Overwrite this and return true if the FactoryType can create this Processor and false, if not. */
virtual bool allowType(const Identifier &typeName) = 0;
virtual String getDescription() const = 0;
};
// ================================================================================================================
/** a simple POD which contains the id and the name of a Processor type. */
struct ProcessorEntry
{
ProcessorEntry(const Identifier t, const String &n);;
ProcessorEntry() {};
Identifier type;
String name;
};
// ================================================================================================================
/** Creates a Factory type. */
FactoryType(Processor *owner_);;
virtual ~FactoryType();
// ================================================================================================================
/** Fills a popupmenu with all allowed processor types.
*
* You can pass in a startIndex, if you overwrite this method for nested calls.
*
* It returns the last index that can be used for the next menus.
*/
virtual int fillPopupMenu(PopupMenu &m, int startIndex = 1);;
/** Overwrite this function and return a processor of the specific type index. */
virtual Processor *createProcessor(int typeIndex, const String &ProcessorId) = 0;
/** Returns the typeName using the result from the previously created popupmenu. */
Identifier getTypeNameFromPopupMenuResult(int resultFromPopupMenu);
/** Returns the typeName using the result from the previously created popupmenu. */
String getNameFromPopupMenuResult(int resultFromPopupMenu);
/** Returns the index of the type. */
virtual int getProcessorTypeIndex(const Identifier &typeName) const;;
/** Returns the number of Processors that this factory can create.
*
* the rules defined in allowType are applied before counting the possible processors.
*/
virtual int getNumProcessors();
const Processor *getOwnerProcessor() const { return owner.get(); };
Processor *getOwnerProcessor() { return owner.get(); };
/** Checks if the type of the processor is found in the type name.
*
* You can overwrite this and add more conditions (in this case, call the base class method first to keep things safe!
*/
virtual bool allowType(const Identifier &typeName) const;;
/** Returns a unique ID for the new Processor.
*
* It scans all Processors and returns something like "Processor12" if there are 11 other Processors with the same ID
*/
static String getUniqueName(Processor *id, String name = String());
/** Returns a string array with all allowed types that this factory can produce. */
virtual Array<ProcessorEntry> getAllowedTypes();;
/** adds a Constrainer to a FactoryType. It will be owned by the FactoryType. You can pass nullptr. */
virtual void setConstrainer(Constrainer *newConstrainer, bool ownConstrainer = true);
Constrainer *getConstrainer();
// ================================================================================================================
protected:
/** This should only be overwritten by the subclasses. For external usage, use getAllowedTypes(). */
virtual const Array<ProcessorEntry> &getTypeNames() const = 0;
WeakReference<Processor> owner;
private:
// iterates all child processors and counts the number of same IDs.
static bool countProcessorsWithSameId(int &index, const Processor *p,
Processor *processorToLookFor, const String &nameToLookFor);
ScopedPointer<Constrainer> ownedConstrainer;
Constrainer *constrainer;
mutable bool baseClassCalled;
JUCE_DECLARE_NON_COPYABLE_WITH_LEAK_DETECTOR(FactoryType);
// ================================================================================================================
};
} // namespace hise
#endif // PROCESSORINTERFACES_H_INCLUDED
| 29.392956 | 162 | 0.678259 |
ee7583b610b2198d12d8ea2a9834ab9cba29167c | 588 | c | C | tests/handle_test.c | mihail-8480/mh | 9e2469ebaad9236458c7f1e8af3c771386051883 | [
"MIT"
] | 1 | 2021-04-23T20:18:35.000Z | 2021-04-23T20:18:35.000Z | tests/handle_test.c | mihail-8480/mh | 9e2469ebaad9236458c7f1e8af3c771386051883 | [
"MIT"
] | 17 | 2021-05-02T19:30:20.000Z | 2021-05-25T09:06:06.000Z | tests/handle_test.c | mihail-8480/mh | 9e2469ebaad9236458c7f1e8af3c771386051883 | [
"MIT"
] | null | null | null | #include "lib/default_tests.h"
#include "../inc/mh_handle.h"
typedef mh_version_t (*mh_get_version_t)(void);
#ifdef WIN32
static mh_const_string_t libmh_lib = "libmh.dll";
#else
static mh_const_string_t libmh_lib = "libmh.so";
#endif
MH_TEST_ADD(handle_test) {
mh_handle_t *handle = mh_handle_new(MH_GLOBAL, libmh_lib);
mh_get_version_t libmh_get_version = (mh_get_version_t) (size_t) mh_handle_find_symbol(handle, "mh_get_version");
mh_version_t version = libmh_get_version();
MH_TEST_EXPECT(version.patch + version.minor + version.major > 0);
MH_TEST_PASSED();
}
| 30.947368 | 117 | 0.761905 |
2d187322f8dad422d5eb2951db18d55d39b7e871 | 611 | h | C | provisioning_client/deps/RIoT/Simulation/FW/Loader.h | rajaggrawal/azure-iot-c-sdk | 2cbd9f21b0984e92f53b435335d14487ec0d08d6 | [
"MIT"
] | 42 | 2019-05-07T13:03:01.000Z | 2022-02-16T00:27:16.000Z | provisioning_client/deps/RIoT/Simulation/FW/Loader.h | rajaggrawal/azure-iot-c-sdk | 2cbd9f21b0984e92f53b435335d14487ec0d08d6 | [
"MIT"
] | 10 | 2017-09-21T08:55:02.000Z | 2019-03-19T17:25:56.000Z | provisioning_client/deps/RIoT/Simulation/FW/Loader.h | rajaggrawal/azure-iot-c-sdk | 2cbd9f21b0984e92f53b435335d14487ec0d08d6 | [
"MIT"
] | 15 | 2017-09-26T19:50:05.000Z | 2019-04-19T12:18:09.000Z | /*
* Copyright (c) Microsoft Corporation. All rights reserved.
* Licensed under the MIT License. See LICENSE in the project root.
*/
#ifdef __cplusplus
extern "C" {
#endif
#include "RIoT.h"
#include "RIoTSim.h"
#ifdef LOADER_EXPORTS
#define FW_API __declspec(dllexport)
#else
#define FW_API __declspec(dllimport)
#endif
FW_API void FirmwareEntry(
char *rootCert,
RIOT_ECC_PUBLIC *DeviceIDPub,
char *DeiceCert,
RIOT_ECC_PUBLIC *AliasKeyPub,
RIOT_ECC_PRIVATE *AliasKeyPriv,
char *AliasKeyCert
);
#ifdef __cplusplus
}
#endif
| 20.366667 | 68 | 0.669394 |
5a97b6df04ce403760be3c168d6af646a1206fff | 291 | c | C | tests/lutl_tests.c | Saend/cutl | 31c091ec3155185a7764682654ad9ed3932f6267 | [
"MIT"
] | null | null | null | tests/lutl_tests.c | Saend/cutl | 31c091ec3155185a7764682654ad9ed3932f6267 | [
"MIT"
] | null | null | null | tests/lutl_tests.c | Saend/cutl | 31c091ec3155185a7764682654ad9ed3932f6267 | [
"MIT"
] | null | null | null | #include "tests.h"
#include <lutl.h>
// LUTL SUITE
int main(int argc, char *argv[])
{
Cutl *cutl = cutl_new("LUTL self-tests");
cutl_parse_args(cutl, argc, argv);
lutl_dofile(cutl, NULL, "tests/lutl_tests.lua");
int failed = cutl_summary(cutl);
cutl_free(cutl);
return failed;
}
| 15.315789 | 49 | 0.683849 |
561e11aa162cea4655a21c0383a2e0d3793ed3cf | 1,265 | h | C | .References/src/github.com/elucideye/drishti_real-time_eye_tracking/src/lib/drishti/hci/gpu/BlobFilter.h | roscopecoltran/SniperKit-Core | 4600dffe1cddff438b948b6c22f586d052971e04 | [
"MIT"
] | null | null | null | .References/src/github.com/elucideye/drishti_real-time_eye_tracking/src/lib/drishti/hci/gpu/BlobFilter.h | roscopecoltran/SniperKit-Core | 4600dffe1cddff438b948b6c22f586d052971e04 | [
"MIT"
] | null | null | null | .References/src/github.com/elucideye/drishti_real-time_eye_tracking/src/lib/drishti/hci/gpu/BlobFilter.h | roscopecoltran/SniperKit-Core | 4600dffe1cddff438b948b6c22f586d052971e04 | [
"MIT"
] | null | null | null | /*!
@file gpu/BlobFilter.cpp
@author David Hirvonen
@brief Illuminate the scene with pulses of LCD light.
\copyright Copyright 2014-2016 Elucideye, Inc. All rights reserved.
\license{This project is released under the 3 Clause BSD License.}
*/
#ifndef __drishti_hci_gpu_BlobFilter_h__
#define __drishti_hci_gpu_BlobFilter_h__
#include "ogles_gpgpu/common/proc/base/multipassproc.h"
#include <opencv2/core.hpp> // for paint()
#include <memory>
// #### Simple flash filter ####
BEGIN_OGLES_GPGPU
class BlobFilter : public MultiPassProc
{
public:
class Impl;
BlobFilter();
~BlobFilter();
virtual ProcInterface* getInputFilter() const;
virtual ProcInterface* getOutputFilter() const;
ProcInterface* getHessian() const;
ProcInterface* getHessianPeaks() const;
/**
* Return the processor's name.
*/
virtual const char* getProcName() { return "BlobFilter"; }
virtual int init(int inW, int inH, unsigned int order, bool prepareForExternalInput = false);
virtual int reinit(int inW, int inH, bool prepareForExternalInput = false);
virtual int render(int position = 0);
cv::Mat paint();
std::shared_ptr<Impl> m_impl;
};
END_OGLES_GPGPU
#endif // __drishti_hci_gpu_BlobFilter_h__
| 23.425926 | 97 | 0.719368 |
737ef92a5524d9eb2c610ca6e959d6b4dfa12bed | 162 | h | C | app/C/includes/user.h | koreaneggroll/Arin-Virtual-Assistant | 79f429c30ed0d960c48f21b787cea9250086928c | [
"MIT"
] | 12 | 2021-02-21T08:22:20.000Z | 2021-04-24T22:48:51.000Z | app/C/includes/user.h | koreaneggroll/Arin-Virtual-Assistant | 79f429c30ed0d960c48f21b787cea9250086928c | [
"MIT"
] | null | null | null | app/C/includes/user.h | koreaneggroll/Arin-Virtual-Assistant | 79f429c30ed0d960c48f21b787cea9250086928c | [
"MIT"
] | null | null | null | #ifndef USER_H
#define USER_H
#include "./commands.h"
typedef struct{
char name[25];
char password[25];
}User;
typedef User usr;
#endif //USER_H | 8.526316 | 23 | 0.654321 |
bc79aa22d4be858a9ac6d630e655c7bbbf4feb5c | 430 | h | C | WakeServer/StarMenuItem.h | bni/WakeServer | 22a5350889934d9ce267ca2e1c0b69bcf729ffb2 | [
"Unlicense"
] | 1 | 2019-12-17T10:36:23.000Z | 2019-12-17T10:36:23.000Z | WakeServer/StarMenuItem.h | bni/WakeServer | 22a5350889934d9ce267ca2e1c0b69bcf729ffb2 | [
"Unlicense"
] | null | null | null | WakeServer/StarMenuItem.h | bni/WakeServer | 22a5350889934d9ce267ca2e1c0b69bcf729ffb2 | [
"Unlicense"
] | 1 | 2015-05-27T07:31:22.000Z | 2015-05-27T07:31:22.000Z | #import <Foundation/Foundation.h>
#import "wol.h"
#define STATE_OFF 0
#define STATE_STARTING 1
#define STATE_RUNNING 2
#define STATE_STOPPING 3
@interface StarMenuItem : NSObject {
NSStatusItem *statusItem;
int state;
NSTimer *updateTimer;
bool starEnabled;
int nrTimerTicks;
NSString *networkBroadcastAddress;
NSString *serverHardwareAddress;
NSString *serverShutdownCommand;
}
@end
| 15.357143 | 38 | 0.730233 |
5dccc90e0af05ee7a3802de689ee31a6c956f385 | 1,131 | h | C | libkoki/include/contour.h | jonsbartlett/SummerSchoolRobot | 1954c14e0094c1b4af5810b69061582f2d453333 | [
"MIT"
] | null | null | null | libkoki/include/contour.h | jonsbartlett/SummerSchoolRobot | 1954c14e0094c1b4af5810b69061582f2d453333 | [
"MIT"
] | null | null | null | libkoki/include/contour.h | jonsbartlett/SummerSchoolRobot | 1954c14e0094c1b4af5810b69061582f2d453333 | [
"MIT"
] | null | null | null | /* Copyright 2011 Chris Kirkham
This file is part of libkoki
libkoki is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
libkoki is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with libkoki. If not, see <http://www.gnu.org/licenses/>. */
#ifndef _KOKI_CONTOUR_H_
#define _KOKI_CONTOUR_H_
/**
* @file contour.h
* @brief Header file for extracting contours from a labelled image
*/
#include <stdint.h>
#include <glib.h>
#include "labelling.h"
GSList* koki_contour_find(koki_labelled_image_t *labelled_image,
label_t region);
void koki_contour_free(GSList *contour);
void koki_contour_draw(IplImage *frame, GSList *contour);
#endif /* _KOKI_CONTOUR_H_ */
| 29.763158 | 71 | 0.749779 |
866994b7e77ba15c295c3b084abd7d3ceea2e50f | 216 | h | C | Example/Chrono/CHViewController.h | larssondaniel/Chrono | b7ab9efa3f5af379565beda08ca025eab994862d | [
"MIT"
] | null | null | null | Example/Chrono/CHViewController.h | larssondaniel/Chrono | b7ab9efa3f5af379565beda08ca025eab994862d | [
"MIT"
] | null | null | null | Example/Chrono/CHViewController.h | larssondaniel/Chrono | b7ab9efa3f5af379565beda08ca025eab994862d | [
"MIT"
] | null | null | null | //
// CHViewController.h
// Chrono
//
// Created by larssondaniel on 02/04/2017.
// Copyright (c) 2017 larssondaniel. All rights reserved.
//
@import UIKit;
@interface CHViewController : UIViewController
@end
| 15.428571 | 58 | 0.712963 |
5e9c8d20e3fc3e3f42e3223e8945e6c99fb3b21e | 516 | h | C | src/l4/a/x86/h/l4/machine/asm/msr.h | archibate/h2os | 04bf2a16519969eeb605ec97d8cb04d16da93ee9 | [
"MIT"
] | 1 | 2020-07-06T02:44:00.000Z | 2020-07-06T02:44:00.000Z | src/l4/a/x86/h/l4/machine/asm/msr.h | archibate/h2os | 04bf2a16519969eeb605ec97d8cb04d16da93ee9 | [
"MIT"
] | null | null | null | src/l4/a/x86/h/l4/machine/asm/msr.h | archibate/h2os | 04bf2a16519969eeb605ec97d8cb04d16da93ee9 | [
"MIT"
] | null | null | null | #pragma once
static uint32_t rdmsr_lo(uint32_t ecx)
{
uint32_t eax;
asm volatile ("rdmsr" : "=a" (eax) : "c" (ecx) : "edx");
return eax;
}
static uint32_t rdmsr_hi(uint32_t ecx)
{
uint32_t edx;
asm volatile ("rdmsr" : "=d" (edx) : "c" (ecx) : "eax");
return edx;
}
static uint64_t rdmsr(uint32_t ecx)
{
uint64_t res;
asm volatile ("rdmsr" : "=A" (res) : "c" (ecx));
return res;
}
static void wrmsr(uint32_t ecx, uint64_t val)
{
asm volatile ("wrmsr" :: "A" (val), "c" (ecx));
}
#include "msr-adrs.h"
| 16.645161 | 57 | 0.620155 |
ab03b1449769f9b6ea2466f828815766fea59fde | 8,003 | c | C | daemon/src/common/ipc_session.c | Daisy000888/AwaLWM2M | 2f3d3f8533bdde80796b51b32a325c229fab271e | [
"BSD-3-Clause"
] | 58 | 2017-06-09T14:29:03.000Z | 2022-01-26T21:20:16.000Z | daemon/src/common/ipc_session.c | Daisy000888/AwaLWM2M | 2f3d3f8533bdde80796b51b32a325c229fab271e | [
"BSD-3-Clause"
] | 195 | 2016-03-03T05:00:43.000Z | 2017-05-28T08:26:40.000Z | daemon/src/common/ipc_session.c | Daisy000888/AwaLWM2M | 2f3d3f8533bdde80796b51b32a325c229fab271e | [
"BSD-3-Clause"
] | 60 | 2016-03-03T04:08:16.000Z | 2017-05-10T01:03:43.000Z | /************************************************************************************************************************
Copyright (c) 2016, Imagination Technologies Limited and/or its affiliated group companies.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote
products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
************************************************************************************************************************/
#include "ipc_session.h"
#include <stdlib.h>
#include <sys/types.h>
#include <sys/time.h>
#include <unistd.h>
#include "lwm2m_debug.h"
#include "lwm2m_list.h"
#include "lwm2m_util.h"
// This number is used to space out session IDs. It is multiplied by the process ID to generate the Session ID.
// It is fairly arbitrary but large enough to provide a reasonable numerical distance between adjacent process IDs.
#define SUITABLY_LARGE_NUMBER (7487)
typedef struct
{
int Sockfd;
struct sockaddr FromAddr;
int AddrLen;
} IPCChannel;
struct _IPCSession
{
struct ListHead list;
IPCSessionID SessionID;
IPCChannel RequestChannel;
IPCChannel NotifyChannel;
};
static struct ListHead sessionList;
void IPCSession_Init(void)
{
ListInit(&sessionList);
}
void IPCSession_Shutdown(void)
{
struct ListHead * i, * n;
ListForEachSafe(i, n, &sessionList)
{
IPCSession * session = ListEntry(i, IPCSession, list);
free(session);
}
}
static IPCSession * FindSessionByID(IPCSessionID sessionID)
{
IPCSession * result = NULL;
struct ListHead * i;
ListForEach(i, &sessionList)
{
IPCSession * session = ListEntry(i, IPCSession, list);
if (session != NULL)
{
if (session->SessionID == sessionID)
{
result = session;
break;
}
}
}
return result;
}
int IPCSession_New(IPCSessionID sessionID)
{
int result = -1;
if (FindSessionByID(sessionID) == NULL)
{
// add new session record
IPCSession * session = malloc(sizeof(*session));
if (session != NULL)
{
memset(session, 0, sizeof(*session));
session->SessionID = sessionID;
ListAdd(&session->list, &sessionList);
result = 0;
}
else
{
Lwm2m_Error("Out of memory\n");
result = -1;
}
}
else
{
Lwm2m_Error("Session ID %d is already in use\n", sessionID);
result = -1;
}
return result;
}
static void AddChannel(IPCChannel * channel, int sockfd, const struct sockaddr * fromAddr, int addrLen)
{
channel->Sockfd = sockfd;
channel->FromAddr = *fromAddr;
channel->AddrLen = addrLen;
}
int IPCSession_AddRequestChannel(IPCSessionID sessionID, int sockfd, const struct sockaddr * fromAddr, int addrLen)
{
int result = -1;
IPCSession * session = NULL;
if ((session = FindSessionByID(sessionID)) != NULL)
{
AddChannel(&session->RequestChannel, sockfd, fromAddr, addrLen);
result = 0;
}
else
{
Lwm2m_Error("No session with ID %d found\n", sessionID);
result = -1;
}
return result;
}
int IPCSession_GetRequestChannel(IPCSessionID sessionID, int * sockfd, const struct sockaddr ** fromAddr, int * addrLen)
{
int result = -1;
IPCSession * session = NULL;
if ((session = FindSessionByID(sessionID)) != NULL)
{
if ((sockfd != NULL) && (fromAddr != NULL) && (addrLen != NULL))
{
*sockfd = session->RequestChannel.Sockfd;
*fromAddr = &session->RequestChannel.FromAddr;
*addrLen = session->RequestChannel.AddrLen;
result = 0;
}
else
{
Lwm2m_Error("NULL parameter - could not return notification channel information\n");
result = -1;
}
}
else
{
Lwm2m_Error("No session with ID %d found\n", sessionID);
result = -1;
}
return result;
}
int IPCSession_AddNotifyChannel(IPCSessionID sessionID, int sockfd, const struct sockaddr * fromAddr, int addrLen)
{
int result = -1;
IPCSession * session = NULL;
if ((session = FindSessionByID(sessionID)) != NULL)
{
AddChannel(&session->NotifyChannel, sockfd, fromAddr, addrLen);
result = 0;
}
else
{
Lwm2m_Error("No session with ID %d found\n", sessionID);
result = -1;
}
return result;
}
int IPCSession_GetNotifyChannel(IPCSessionID sessionID, int * sockfd, const struct sockaddr ** fromAddr, int * addrLen)
{
int result = -1;
IPCSession * session = NULL;
if ((session = FindSessionByID(sessionID)) != NULL)
{
if ((sockfd != NULL) && (fromAddr != NULL) && (addrLen != NULL))
{
*sockfd = session->NotifyChannel.Sockfd;
*fromAddr = &session->NotifyChannel.FromAddr;
*addrLen = session->NotifyChannel.AddrLen;
result = 0;
}
else
{
Lwm2m_Error("NULL parameter - could not return notification channel information\n");
result = -1;
}
}
else
{
Lwm2m_Error("No session with ID %d found\n", sessionID);
result = -1;
}
return result;
}
IPCSessionID IPCSession_AssignSessionID(void)
{
static int seed = 1;
// generate a pseudo-random number between 10000000 and 99999999 inclusive.
enum { MIN_SESSION_ID = 10000000 };
enum { MAX_SESSION_ID = 99999999 };
struct timeval tv = { 0 };
gettimeofday(&tv, NULL);
unsigned long long combined = abs(seed++ * getpid() * SUITABLY_LARGE_NUMBER * tv.tv_sec * tv.tv_usec);
IPCSessionID sessionID = (combined % (MAX_SESSION_ID - MIN_SESSION_ID + 1)) + MIN_SESSION_ID;
return sessionID;
}
bool IPCSession_IsValid(IPCSessionID sessionID)
{
return FindSessionByID(sessionID);
}
void IPCSession_Dump(void)
{
struct ListHead * i;
ListForEach(i, &sessionList)
{
IPCSession * session = ListEntry(i, IPCSession, list);
if (session != NULL)
{
printf("Session ID %d:\n", session->SessionID);
#ifndef CONTIKI
printf(" Request Channel: Sockfd %d, FromAddr %s, AddrLen %d\n", session->RequestChannel.Sockfd, Lwm2mCore_DebugPrintSockAddr(&session->RequestChannel.FromAddr), session->RequestChannel.AddrLen);
printf(" Notify Channel: Sockfd %d, FromAddr %s, AddrLen %d\n", session->NotifyChannel.Sockfd, Lwm2mCore_DebugPrintSockAddr(&session->NotifyChannel.FromAddr), session->NotifyChannel.AddrLen);
#endif
}
}
}
| 32.012 | 208 | 0.634637 |
3964af0f6aa842450b11d885bb4fb6054196741a | 1,457 | h | C | lib/memory_dc_t.h | dejbug/fen2ppm | 54f6b80d18dbad003a4111443049312bd3377a77 | [
"MIT"
] | null | null | null | lib/memory_dc_t.h | dejbug/fen2ppm | 54f6b80d18dbad003a4111443049312bd3377a77 | [
"MIT"
] | null | null | null | lib/memory_dc_t.h | dejbug/fen2ppm | 54f6b80d18dbad003a4111443049312bd3377a77 | [
"MIT"
] | null | null | null | #pragma once
#include <windows.h>
struct memory_dc_context_t
{
HWND dh = nullptr;
HDC dc = nullptr;
~memory_dc_context_t() { free(); }
bool create()
{
dh = GetDesktopWindow();
dc = GetDC(dh);
lib::log("Context DC: %p / HWND: %p\n", (void *)dc, (void *)dh);
return dc;
}
void free()
{
if (!dc) return;
ReleaseDC(dh, dc);
dh = NULL;
dc = NULL;
lib::log("* free: Context DC\n");
}
};
struct memory_dc_t
{
memory_dc_context_t ctx;
HDC dc = NULL;
HBITMAP bmp = NULL;
~memory_dc_t() { free(); }
bool create(int width, int height)
{
free();
if (!ctx.create()) return false;
lib::log("Desktop HWND: %p / DC: %p\n", (void *)ctx.dh, (void *)ctx.dc);
dc = CreateCompatibleDC(ctx.dc);
if (!dc) return false;
lib::log("Memory HDC: %p\n", (void *)dc);
bmp = CreateCompatibleBitmap(ctx.dc, width, height);
if (!bmp) return false;
lib::log("Memory HBITMAP: %p\n", (void *)bmp);
SelectObject(dc, bmp);
return test();
}
bool test() const
{
COLORREF const a = GetPixel(dc, 0, 0);
SetPixel(dc, 0, 0, a+1);
COLORREF const b = GetPixel(dc, 0, 0);
return a != b;
}
void free()
{
ctx.free();
if (bmp)
{
if (dc) SelectObject(dc, (HBITMAP)NULL);
DeleteObject(bmp);
bmp = NULL;
lib::log("* free: Memory HBITMAP\n");
}
if (dc)
{
DeleteDC(dc);
dc = NULL;
lib::log("* free: Memory DC\n");
}
}
};
| 18.679487 | 75 | 0.553191 |
6187726163fa0a38ada0d40b1259839d862f11d0 | 109 | c | C | aoapc2/chap01/code01-06.c | yaominzh/CodeLrn2019 | adc727d92904c5c5d445a2621813dfa99474206d | [
"Apache-2.0"
] | 2 | 2021-03-25T05:26:55.000Z | 2021-04-20T03:33:24.000Z | aoapc2/chap01/code01-06.c | mcuallen/CodeLrn2019 | adc727d92904c5c5d445a2621813dfa99474206d | [
"Apache-2.0"
] | 6 | 2019-12-04T06:08:32.000Z | 2021-05-10T20:22:47.000Z | aoapc2/chap01/code01-06.c | mcuallen/CodeLrn2019 | adc727d92904c5c5d445a2621813dfa99474206d | [
"Apache-2.0"
] | null | null | null | #include<stdio.h>
int main(){
int n;
scanf("%d", &n);
printf("%d%d%d\n",n%10,n/10%10,n/100);
return 0;
}
| 13.625 | 39 | 0.550459 |
0f69b4b789e23eda110ee0c2fe2362d6206a5cb4 | 3,104 | h | C | packages/PIPS/validation/Scilab/Scilab2C-2/includes/sign.h | DVSR1966/par4all | 86b33ca9da736e832b568c5637a2381f360f1996 | [
"MIT"
] | 51 | 2015-01-31T01:51:39.000Z | 2022-02-18T02:01:50.000Z | packages/PIPS/validation/Scilab/Scilab2C-2/includes/sign.h | DVSR1966/par4all | 86b33ca9da736e832b568c5637a2381f360f1996 | [
"MIT"
] | 7 | 2017-05-29T09:29:00.000Z | 2019-03-11T16:01:39.000Z | packages/PIPS/validation/Scilab/Scilab2C-2/includes/sign.h | DVSR1966/par4all | 86b33ca9da736e832b568c5637a2381f360f1996 | [
"MIT"
] | 12 | 2015-03-26T08:05:38.000Z | 2022-02-18T02:01:51.000Z | /*
* Scilab ( http://www.scilab.org/ ) - This file is part of Scilab
* Copyright (C) 2007-2008 - INRIA - Bruno JOFRET
*
* This file must be used under the terms of the CeCILL.
* This source file is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at
* http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt
*
*/
#ifndef __SIGN_H__
#define __SIGN_H__
#include <math.h>
#include "dynlib_auxiliaryfunctions.h"
#include "floatComplex.h"
#include "doubleComplex.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
** \brief Float Signe function
** Determine the sign of in (assume that 0 is positive).
** \param in : the float we must determine sign.
** \return -1 or +1 depending on the sign of in.
**/
EXTERN_AUXFUNCT float ssigns(float in);
/**
** \brief Double Signe function
** Determine the sign of in (assume that 0 is positive).
** \param in : the double we must determine sign.
** \return -1 or +1 depending on the sign of in.
**/
EXTERN_AUXFUNCT double dsigns(double in);
/**
** \brief Float Complex Signe function
** Determine the sign of in (assume that 0 is positive).
** \param in : the float we must determine sign.
** \return -1 or +1 depending on the sign of in.
**/
EXTERN_AUXFUNCT floatComplex csigns(floatComplex in);
/**
** \brief Double Complex Signe function
** Determine the sign of in (assume that 0 is positive).
** \param in : the double we must determine sign.
** \return -1 or +1 depending on the sign of in.
**/
EXTERN_AUXFUNCT doubleComplex zsigns(doubleComplex in);
/**
** \brief Float Signe Array function
** Determine the sign of an array in (assume that 0 is positive).
** \param in : the float array we must determine sign.
** \param size : the number of elements.
** \return -1 or +1 depending on the sign of in elements.
**/
EXTERN_AUXFUNCT void ssigna(float *in, int size, float *out);
/**
** \brief Double Signe Array function
** Determine the sign of an array in (assume that 0 is positive).
** \param in : the double array we must determine sign.
** \param size : the number of elements.
** \return -1 or +1 depending on the sign of in elements.
**/
EXTERN_AUXFUNCT void dsigna(double *in, int size, double *out);
/**
** \brief Float Signe Complex Array function
** Determine the sign of an array in (assume that 0 is positive).
** \param in : the float complex array we must determine sign.
** \param size : the number of elements.
** \return -1 or +1 depending on the sign of in elements.
**/
EXTERN_AUXFUNCT void csigna(floatComplex *in, int size, floatComplex *out);
/**
** \brief Double Signe Complex Array function
** Determine the sign of an array in (assume that 0 is positive).
** \param in : the double complex array we must determine sign.
** \param size : the number of elements.
** \return -1 or +1 depending on the sign of in elements.
**/
EXTERN_AUXFUNCT void zsigna(doubleComplex *in, int size, doubleComplex *out);
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* !__SIGN_H__ */
| 31.04 | 77 | 0.698776 |
c92391d6fec8b5c1fba0340e4fcdda8aabd737dd | 2,153 | h | C | Src/analyzer/rtc/DS3231.h | maker99/Antenna_Analyzer_EU1KY_var_DH1AKF | 4b8929ec148a165bca47894fc8511952b06a27d4 | [
"Unlicense"
] | null | null | null | Src/analyzer/rtc/DS3231.h | maker99/Antenna_Analyzer_EU1KY_var_DH1AKF | 4b8929ec148a165bca47894fc8511952b06a27d4 | [
"Unlicense"
] | null | null | null | Src/analyzer/rtc/DS3231.h | maker99/Antenna_Analyzer_EU1KY_var_DH1AKF | 4b8929ec148a165bca47894fc8511952b06a27d4 | [
"Unlicense"
] | null | null | null |
#ifndef DS3231_H_
#define DS3231_H_
#include <stdint.h>
#include "config.h"
#define DS3231_Address 0x68
#define DS3231_Read_addr ((DS3231_Address << 1) | 0x01)
#define DS3231_Write_addr ((DS3231_Address << 1) & 0xFE)
#define secondREG 0x00
#define minuteREG 0x01
#define hourREG 0x02
#define dayREG 0x03
#define dateREG 0x04
#define monthREG 0x05
#define yearREG 0x06
#define alarm1secREG 0x07
#define alarm1minREG 0x08
#define alarm1hrREG 0x09
#define alarm1dateREG 0x0A
#define alarm2minREG 0x0B
#define alarm2hrREG 0x0C
#define alarm2dateREG 0x0D
#define controlREG 0x0E
#define statusREG 0x0F
#define ageoffsetREG 0x10
#define tempMSBREG 0x11
#define tempLSBREG 0x12
#define _24_hour_format 0
#define _12_hour_format 1
#define am 0
#define pm 1
//Ext I2C port used for camera is wired to Arduino UNO connector when SB4 and SB1 jumpers are set instead of SB5 and SB3.
extern void CAMERA_IO_Init(void);
extern void CAMERA_IO_Write(uint8_t addr, uint8_t reg, uint8_t value);
extern uint8_t CAMERA_IO_Read(uint8_t addr, uint8_t reg);
extern void CAMERA_Delay(uint32_t delay);
extern void CAMERA_IO_WriteBulk(uint8_t addr, uint8_t reg, uint8_t* values, uint16_t nvalues);
extern void Sleep(uint32_t);
unsigned char bcd_to_decimal(unsigned char d);
unsigned char decimal_to_bcd(unsigned char d);
unsigned char DS3231_Read(unsigned char address);
void DS3231_Write(unsigned char address, unsigned char value);
void DS3231_init();
void getTime(uint32_t *rtctime, unsigned char *second, short *AMPM, short hour_format);
void getDate(uint32_t *date);
void setTime(uint32_t timeSet, unsigned char sSet, short am_pm_state, short hour_format);
void setDate(uint32_t dateSet);
float getTemp();
#endif
| 35.295082 | 121 | 0.634464 |
bf91429c545315bc668ac081ff48f0c2c1ff8e18 | 666 | h | C | FS/src/at24c02.h | hyeonsoo-kim/2019_CortexM3_Electronic_Piano | e0bea9c4153c8e43c1d1c9e77f6aabc6e9d13f00 | [
"MIT"
] | null | null | null | FS/src/at24c02.h | hyeonsoo-kim/2019_CortexM3_Electronic_Piano | e0bea9c4153c8e43c1d1c9e77f6aabc6e9d13f00 | [
"MIT"
] | null | null | null | FS/src/at24c02.h | hyeonsoo-kim/2019_CortexM3_Electronic_Piano | e0bea9c4153c8e43c1d1c9e77f6aabc6e9d13f00 | [
"MIT"
] | null | null | null |
#ifndef __AT24C02_H
#define __AT24C02_H
#define AT24C01 127
#define AT24C02 255
#define AT24C04 511
#define AT24C08 1023
#define AT24C16 2047
#define AT24C32 4095
#define AT24C64 8191
#define AT24C128 16383
#define AT24C256 32767
#define EE_TYPE AT24C02
void bsp_at24c02_gpio_init(void);
u8 AT24CXX_ReadOneByte(u16 ReadAdder);
void AT24CXX_WriteOneByte(u16 WriteAddr,u8 DataToWrite);
void AT24CXX_WriteLenByte(u16 WriteAddr,u32 DataToWrite,u8 Len);
u32 AT24CXX_ReadLenByte(u16 ReadAddr,u8 Len);
void AT24CXX_Read(u16 ReadAddr,u8 *pBuffer,u16 NumToRead);
void AT24CXX_Write(u16 WriteAddr,u8 *pBuffer,u16 NumToWrite);
void AT24CXX_Init(void);
#endif
| 20.8125 | 64 | 0.804805 |
a7beb6fd6a2d1f2c597fad23afb4250dfde89c69 | 7,469 | h | C | source code/finalproject/datastruct.h | tomatoeater/CS2309-Principles-and-Practice-of-Problem-Solving | 387250473185a5319c93363ff072ee26c9f27d26 | [
"MIT"
] | null | null | null | source code/finalproject/datastruct.h | tomatoeater/CS2309-Principles-and-Practice-of-Problem-Solving | 387250473185a5319c93363ff072ee26c9f27d26 | [
"MIT"
] | null | null | null | source code/finalproject/datastruct.h | tomatoeater/CS2309-Principles-and-Practice-of-Problem-Solving | 387250473185a5319c93363ff072ee26c9f27d26 | [
"MIT"
] | null | null | null | /*
* all the data structures for my program
*/
#ifndef DATASTRUCT_H
#define DATASTRUCT_H
#include <QString>
#include <QDateTime>
struct Time
{
int year;
int month;
int day;
int hour;
int minute;
int second;
Time(int _y = 0, int _mo = 0, int _d = 0, int _h = 0, int _mi = 0, int _s = 0)
:year(_y),month(_mo),day(_d),hour(_h),minute(_mi),second(_s){}
Time(const Time &o)
:year(o.year),month(o.month),day(o.day),hour(o.hour),minute(o.minute),second(o.second){}
bool operator<(Time const &oth)
{
if(year < oth.year)
return true;
else if (year > oth.year)
return false;
if(month < oth.month)
return true;
else if(month > oth.month)
return false;
if(day < oth.day)
return true;
else if(day > oth.day)
return false;
if(hour < oth.hour)
return true;
else if(hour > oth.hour)
return false;
if(minute < oth.minute)
return true;
else if(minute > oth.minute)
return false;
if(second < oth.second)
return true;
else
return false;
}
bool operator<=(Time const &oth)
{
if(year < oth.year)
return true;
else if (year > oth.year)
return false;
if(month < oth.month)
return true;
else if(month > oth.month)
return false;
if(day < oth.day)
return true;
else if(day > oth.day)
return false;
if(hour < oth.hour)
return true;
else if(hour > oth.hour)
return false;
if(minute < oth.minute)
return true;
else if(minute > oth.minute)
return false;
if(second <= oth.second)
return true;
else
return false;
}
bool operator>(Time const &oth)
{
if(year > oth.year)
return true;
else if (year < oth.year)
return false;
if(month > oth.month)
return true;
else if(month < oth.month)
return false;
if(day > oth.day)
return true;
else if(day < oth.day)
return false;
if(hour > oth.hour)
return true;
else if(hour < oth.hour)
return false;
if(minute > oth.minute)
return true;
else if(minute < oth.minute)
return false;
if(second > oth.second)
return true;
else
return false;
}
bool operator>=(Time const &oth)
{
if(year > oth.year)
return true;
else if (year < oth.year)
return false;
if(month > oth.month)
return true;
else if(month < oth.month)
return false;
if(day > oth.day)
return true;
else if(day < oth.day)
return false;
if(hour > oth.hour)
return true;
else if(hour < oth.hour)
return false;
if(minute > oth.minute)
return true;
else if(minute < oth.minute)
return false;
if(second >= oth.second)
return true;
else
return false;
}
bool operator==(Time const &oth)
{
return year == oth.year && month == oth.month && day == oth.day && hour == oth.hour && minute == oth.minute && second == oth.second;
}
operator QString() const
{
QString ret;
ret.append(QString::number(year));
ret.append('/');
ret.append(QString::number(month));
ret.append('/');
ret.append(QString::number(day));
ret.append(' ');
ret.append(QString::number(hour));
ret.append(':');
ret.append(QString::number(minute));
ret.append(':');
ret.append(QString::number(second));
return ret;
}
Time& operator=(const Time &o)
{
if (this == &o)
return *this;
year = o.year;
month = o.month;
minute = o.minute;
second = o.second;
day = o.day;
hour = o.hour;
return *this;
}
//两个日期差多少天 ，必须大的减小的
friend int operator-(const Time &a, const Time &b)
{
QDate end(a.year, a.month, a.day);
QDate sta(b.year, b.month, b.day);
int cnt = 0;
while(sta < end)
{
++cnt;
sta = sta.addDays(1);
}
return cnt;
}
};
struct Location
{
double latitude;
double longitude;
Location(double _la, double _lo)
:latitude(_la),longitude(_lo){}
};
struct Checkin
{
int userID;
int locationID;
Time time;
Checkin(int _u, int _l, Time _t)
:userID(_u),locationID(_l),time(_t){}
};
struct allInfo
{
int userID;
int locationID;
Time time;
double latitude;
double longitude;
allInfo(int _u=0,int _l=0, Time _t=Time(), double _la=0, double _lo=0)
:userID(_u),locationID(_l),time(_t),latitude(_la),longitude(_lo){}
};
struct POIIDandTime
{
int POIID;
int times;
bool operator < (const POIIDandTime &o)
{
return times > o.times;
}
bool operator <= (const POIIDandTime &o)
{
return times >= o.times;
}
bool operator > (const POIIDandTime &o)
{
return times < o.times;
}
bool operator >= (const POIIDandTime &o)
{
return times <= o.times;
}
bool operator == (const POIIDandTime &o)
{
return times == o.times;
}
};
struct yearMonth
{
int year;
int month;
yearMonth(int _y = 0, int _m = 0) : year(_y), month(_m){}
bool operator < (const yearMonth &o)
{
if (year < o.year)
return true;
if (year > o.year)
return false;
if (month < o.month)
return true;
return false;
}
bool operator > (const yearMonth &o)
{
if (year > o.year)
return true;
if (year < o.year)
return false;
if (month > o.month)
return true;
return false;
}
bool operator == (const yearMonth &o)
{
return (year == o.year) && (month == o.month);
}
bool operator <= (const yearMonth &o)
{
if (year < o.year)
return true;
if (year > o.year)
return false;
if (month <= o.month)
return true;
return false;
}
bool operator >= (const yearMonth &o)
{
if (year > o.year)
return true;
if (year < o.year)
return false;
if (month >= o.month)
return true;
return false;
}
operator QString() const
{
QString ret;
ret.append(QString::number(year));
ret.append('/');
ret.append(QString::number(month));
return ret;
}
friend int operator-(const yearMonth &a, const yearMonth &b)
{
return (a.year-b.year)*12+a.month-b.month;
}
friend yearMonth operator+(const yearMonth &a, const int &b)
{
int month = a.month+b;
int year = a.year;
if (month > 12)
{
month -= 12;
year++;
}
yearMonth ret(year,month);
return ret;
}
};
#endif // DATASTRUCT_H
| 23.711111 | 140 | 0.496184 |
db47c2fb2dccdcf9fdcc89a6ccd948964709aaad | 12,213 | c | C | v4l2apps/v4l2ops.c | AdvantechRISC/apq8016_vendor_qcom-opensource_kernel_kernel-tests | d117f383a91dc75886aa0147569b1bbfa344184f | [
"BSD-3-Clause"
] | null | null | null | v4l2apps/v4l2ops.c | AdvantechRISC/apq8016_vendor_qcom-opensource_kernel_kernel-tests | d117f383a91dc75886aa0147569b1bbfa344184f | [
"BSD-3-Clause"
] | null | null | null | v4l2apps/v4l2ops.c | AdvantechRISC/apq8016_vendor_qcom-opensource_kernel_kernel-tests | d117f383a91dc75886aa0147569b1bbfa344184f | [
"BSD-3-Clause"
] | null | null | null | /*
-----------------------------------------------------------------------------
Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above
copyright notice, this list of conditions and the following
disclaimer in the documentation and/or other materials provided
with the distribution.
* Neither the name of The Linux Foundation nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <errno.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include "v4l2ops.h"
static int _v4l2_pushy_ioctl(int fd, int cmd, void *data)
{
int num_attempts = 0;
int ret;
do {
ret = ioctl(fd, cmd, data);
if(ret == 0 || (errno != EINTR && errno != EAGAIN))
break;
} while (++num_attempts < 100);
return ret;
}
static int _v4l2_querycap(int fd, int capabilities)
{
int ret;
struct v4l2_capability cap;
memset(&cap, 0, sizeof(struct v4l2_capability));
ret = ioctl(fd, VIDIOC_QUERYCAP, &cap);
if (ret < 0) {
printf ("VIDIOC_QUERYCAP failed\n");
return ret;
}
if (~cap.capabilities & capabilities)
return -1;
return 0;
}
static int _v4l2_cropcap(int fd, enum v4l2_buf_type type,
struct v4l2_rect *crop)
{
int ret;
struct v4l2_cropcap cropcap;
memset(&cropcap, 0, sizeof(struct v4l2_cropcap));
cropcap.type = type;
ret = ioctl(fd, VIDIOC_CROPCAP, &cropcap);
if (ret < 0) {
printf ("VIDIOC_CROPCAP failed\n");
return ret;
}
if ((crop->left < cropcap.bounds.left) &&
(crop->top < cropcap.bounds.top) &&
(crop->width > cropcap.bounds.width) &&
(crop->height > cropcap.bounds.height)) {
printf ("(%d,%d %dx%d) is out of bound(%d,%d %dx%d)\n",
crop->left, crop->top, crop->width, crop->height,
cropcap.bounds.left, cropcap.bounds.top,
cropcap.bounds.width, cropcap.bounds.height);
return -1;
}
return ret;
}
static int _v4l2_g_fmt(int fd, struct v4l2_format *format)
{
int ret = ioctl(fd, VIDIOC_G_FMT, format);
if (ret < 0) {
printf ("VIDIOC_G_FMT failed\n");
return ret;
}
return 0;
}
static int _v4l2_s_fmt(int fd, struct v4l2_format *format)
{
int ret = ioctl(fd, VIDIOC_S_FMT, format);
if (ret < 0) {
printf ("VIDIOC_S_FMT failed\n");
return ret;
}
return 0;
}
static int _v4l2_g_fbuf(int fd, struct v4l2_framebuffer *frame)
{
int ret = ioctl(fd, VIDIOC_G_FBUF, frame);
if (ret < 0) {
printf ("VIDIOC_G_FBUF failed\n");
return ret;
}
return 0;
}
static int _v4l2_s_fbuf(int fd, struct v4l2_framebuffer *frame)
{
int ret = ioctl(fd, VIDIOC_S_FBUF, frame);
if (ret < 0) {
printf ("VIDIOC_S_FBUF failed\n");
}
return ret;
}
static int _v4l2_s_crop(int fd, struct v4l2_crop *crop)
{
int ret = ioctl(fd, VIDIOC_S_CROP, crop);
if (ret < 0) {
printf ("VIDIOC_S_CROP failed\n");
}
return ret;
}
static int _v4l2_g_ctrl(int fd, struct v4l2_control *ctrl)
{
int ret = ioctl(fd, VIDIOC_G_CTRL, ctrl);
if (ret < 0) {
printf ("VIDIOC_G_CTRL failed\n");
}
return ret;
}
static int _v4l2_s_ctrl(int fd, struct v4l2_control *ctrl)
{
int ret = ioctl(fd, VIDIOC_S_CTRL, ctrl);
if (ret < 0) {
printf ("VIDIOC_S_CTRL failed\n");
}
return ret;
}
static int _v4l2_streamon(int fd, enum v4l2_buf_type type)
{
int ret = _v4l2_pushy_ioctl(fd, VIDIOC_STREAMON, &type);
if (ret < 0) {
printf ("VIDIOC_STREAMON failed\n");
}
return ret;
}
static int _v4l2_streamoff(int fd, enum v4l2_buf_type type)
{
int ret = _v4l2_pushy_ioctl(fd, VIDIOC_STREAMOFF, &type);
if (ret < 0) {
printf ("VIDIOC_STREAMOFF failed \n");
return ret;
}
return ret;
}
static int _v4l2_reqbuf(int fd, struct v4l2_requestbuffers *req)
{
int ret = _v4l2_pushy_ioctl(fd, VIDIOC_REQBUFS, req);
if (ret < 0) {
printf ("VIDIOC_REQBUFS failed\n");
}
return ret;
}
static int _v4l2_querybuf (int fd, struct v4l2_buffer *set_buf)
{
int ret = _v4l2_pushy_ioctl(fd, VIDIOC_QUERYBUF, set_buf);
if (ret < 0) {
printf ("VIDIOC_QUERYBUF failed\n");
}
return ret;
}
static int _v4l2_queue(int fd, struct v4l2_buffer *buf)
{
int ret = _v4l2_pushy_ioctl(fd, VIDIOC_QBUF, buf);
if (ret < 0) {
printf ("VIDIOC_QBUF failed\n");
}
return ret;
}
static int _v4l2_dequeue(int fd, struct v4l2_buffer *buf)
{
int ret = _v4l2_pushy_ioctl(fd, VIDIOC_DQBUF, buf);
if (ret < 0) {
printf ("VIDIOC_DQBUF failed\n");
}
return ret;
}
int v4l2_set_src(int fd, int width, int height,
int crop_x, int crop_y, int crop_w, int crop_h,
unsigned int pixelformat)
{
int capabilities;
int ret;
struct v4l2_format format;
struct v4l2_crop crop;
memset(&format, 0, sizeof(struct v4l2_format));
memset(&crop, 0, sizeof(struct v4l2_crop));
printf ("SetSrc : image(%dx%d) crop(%d,%d %dx%d) pixfmt(0x%08x) \n",
width, height,
crop_x, crop_y, crop_w, crop_h,
pixelformat);
/* check if capabilities is valid */
capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_OUTPUT;
ret = _v4l2_querycap(fd, capabilities);
if (ret < 0)
return ret;
/* set the size and format of SRC */
format.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
ret = _v4l2_g_fmt (fd, &format);
if (ret < 0)
return ret;
format.fmt.pix.width = width;
format.fmt.pix.height = height;
format.fmt.pix.pixelformat = pixelformat;
format.fmt.pix.field = V4L2_FIELD_NONE;
ret = _v4l2_s_fmt (fd, &format);
if (ret < 0) {
return ret;
}
/* set the crop area of SRC */
crop.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
crop.c.left = crop_x;
crop.c.top = crop_y;
crop.c.width = crop_w;
crop.c.height = crop_h;
ret = _v4l2_cropcap (fd, crop.type, &crop.c);
if (ret < 0)
return ret;
ret = _v4l2_s_crop (fd, &crop);
if (ret < 0)
return ret;
return 0;
}
int v4l2_set_dst(int fd,
int dst_x, int dst_y, int dst_w, int dst_h, void *addr)
{
struct v4l2_format format;
struct v4l2_framebuffer fbuf;
int ret;
memset(&format, 0, sizeof(struct v4l2_format));
memset(&fbuf, 0, sizeof(struct v4l2_framebuffer));
printf("SetDst : dst(%d,%d %dx%d) \n", dst_x, dst_y, dst_w, dst_h);
/* set the size and format of DST */
ret = _v4l2_g_fbuf(fd, &fbuf);
if (ret < 0)
return ret;
if (addr != NULL)
/* set the output buffer */
fbuf.base = addr;
fbuf.fmt.width = dst_w;
fbuf.fmt.height = dst_h;
fbuf.fmt.pixelformat = V4L2_PIX_FMT_RGB32;
ret = _v4l2_s_fbuf(fd, &fbuf);
if (ret < 0)
return ret;
/* set the size of WIN */
format.type = V4L2_BUF_TYPE_VIDEO_OVERLAY;
ret = _v4l2_g_fmt(fd, &format);
if (ret < 0)
return ret;
format.fmt.win.w.left = dst_x;
format.fmt.win.w.top = dst_y;
format.fmt.win.w.width = dst_w;
format.fmt.win.w.height = dst_h;
ret = !_v4l2_s_fmt(fd, &format);
if (ret < 0)
return ret;
return 0;
}
int v4l2_set_buffer (int fd,
enum v4l2_memory memory,
int num_buf,
struct mem_buffer **mem_buf)
{
struct v4l2_requestbuffers req;
int ret;
memset(&req, 0, sizeof(struct v4l2_requestbuffers));
printf ("SetBuffer : memory(%d) num_buf(%d) mem_buf(%p)\n",
memory, num_buf, mem_buf);
req.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
req.count = num_buf;
req.memory = memory;
ret = _v4l2_reqbuf (fd, &req);
if (ret < 0)
return ret;
if (memory == V4L2_MEMORY_MMAP && mem_buf)
{
struct mem_buffer *out_buf;
int i;
out_buf = calloc(num_buf, sizeof(struct mem_buffer));
if (!out_buf)
return -1;
for (i = 0; i < num_buf; i++)
{
struct v4l2_buffer buffer;
memset(&buffer, 0, sizeof(struct v4l2_buffer));
buffer.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
buffer.index = i;
buffer.memory = V4L2_MEMORY_MMAP;
ret = _v4l2_querybuf (fd, &buffer);
if (ret < 0) {
free(out_buf);
return ret;
}
out_buf[i].index = buffer.index;
out_buf[i].size = buffer.length;
out_buf[i].buf = (void*)mmap (NULL, buffer.length,
PROT_READ | PROT_WRITE , \
MAP_SHARED , fd, buffer.m.offset);
if (out_buf[i].buf == MAP_FAILED)
{
printf ("mmap failed. index(%d)\n", i);
free(out_buf);
return -1;
}
}
*mem_buf = out_buf;
}
return 0;
}
int v4l2_clear_buffer(int fd,
enum v4l2_memory memory,
int num_buf,
struct mem_buffer *mem_buf)
{
int ret;
/*
* The = {0} syntax gives warnings on gcc version in OE,
* hence the memset
*/
struct v4l2_requestbuffers req;
memset(&req, 0, sizeof(struct v4l2_requestbuffers));
printf ("ClearBuffer : memory(%d) num_buf(%d) mem_buf(%p)\n", memory,
num_buf, mem_buf);
if (memory == V4L2_MEMORY_MMAP && mem_buf)
{
int i;
for (i = 0; i < num_buf; i++)
if (mem_buf[i].buf)
if (munmap(mem_buf[i].buf, mem_buf[i].size)
== -1)
printf("Failed to unmap v4l2 buffer at"
"index %d\n", i);
free(mem_buf);
}
req.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
req.count = 0;
req.memory = memory;
ret = _v4l2_reqbuf (fd, &req);
if (ret < 0)
return ret;
return 0;
}
int v4l2_set_rotation(int fd, int rotation)
{
int ret;
struct v4l2_control ctrl;
if(rotation == -1)
return 0;
memset(&ctrl, 0, sizeof(struct v4l2_control));
/* set the rotation value */
ctrl.id = V4L2_CID_ROTATE;
ret = _v4l2_g_ctrl (fd, &ctrl);
if (ret < 0)
return ret;
ctrl.value = rotation;
ret = _v4l2_s_ctrl (fd, &ctrl);
if (ret < 0)
return ret;
return 0;
}
int v4l2_set_flip(int fd, int hflip, int vflip)
{
int ret;
struct v4l2_control ctrl;
if(hflip == 0 && vflip == 0)
return 0;
memset(&ctrl, 0, sizeof(struct v4l2_control));
/* set the hflip value */
ctrl.id = V4L2_CID_HFLIP;
ret = _v4l2_g_ctrl (fd, &ctrl);
if (ret < 0)
return ret;
ctrl.value = hflip;
ret = _v4l2_s_ctrl (fd, &ctrl);
if (ret < 0)
return ret;
/* set the vflip value */
ctrl.id = V4L2_CID_VFLIP;
ret = _v4l2_g_ctrl (fd, &ctrl);
if (ret < 0)
return ret;
ctrl.value = vflip;
ret = _v4l2_s_ctrl (fd, &ctrl);
if (ret < 0)
return ret;
return 0;
}
int v4l2_stream_on(int fd)
{
int ret;
ret = _v4l2_streamon (fd, V4L2_BUF_TYPE_VIDEO_OUTPUT);
if (ret < 0)
return ret;
return 0;
}
int v4l2_stream_off(int fd)
{
int ret;
ret = _v4l2_streamoff (fd, V4L2_BUF_TYPE_VIDEO_OUTPUT);
if (ret < 0)
return ret;
return 0;
}
int v4l2_dequeue(int fd, enum v4l2_memory memory, int *index)
{
int ret;
struct v4l2_buffer buf;
memset(&buf, 0, sizeof(struct v4l2_buffer));
buf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
buf.memory = memory;
ret = _v4l2_dequeue (fd, &buf);
if (ret < 0)
return ret;
*index = buf.index;
return 0;
}
int v4l2_queue(int fd, int index, enum v4l2_memory memory, __u32 bytes)
{
int ret, i;
struct v4l2_buffer buf;
memset(&buf, 0, sizeof(struct v4l2_buffer));
buf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
buf.index = index;
buf.memory = memory;
buf.bytesused = bytes;
if (memory == V4L2_MEMORY_USERPTR) {
buf.m.userptr = (unsigned long) userptr;
buf.length = bytes;
}
ret = _v4l2_queue (fd, &buf);
if (ret < 0)
return ret;
return 0;
}
| 21.926391 | 78 | 0.662245 |
86f0db47b0536b7a13b1b2a9d80bb2cc7a8eb734 | 3,054 | c | C | module/probing-function.c | emisilve86/Probing-Interrupt-Handlers | f8bcd447e2cd6da2195b761f20b2f722fe7266d2 | [
"Apache-2.0"
] | null | null | null | module/probing-function.c | emisilve86/Probing-Interrupt-Handlers | f8bcd447e2cd6da2195b761f20b2f722fe7266d2 | [
"Apache-2.0"
] | null | null | null | module/probing-function.c | emisilve86/Probing-Interrupt-Handlers | f8bcd447e2cd6da2195b761f20b2f722fe7266d2 | [
"Apache-2.0"
] | null | null | null | /*****************************************************************************
* Copyright 2021 Emisilve86 *
* *
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at *
* *
* http://www.apache.org/licenses/LICENSE-2.0 *
* *
* Unless required by applicable law or agreed to in writing, software *
* distributed under the License is distributed on an "AS IS" BASIS, *
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
* See the License for the specific language governing permissions and *
* limitations under the License. *
*****************************************************************************/
#include "probing-function.h"
/*****************************************************************************
* Here is where you have to declare all the functions (including variables) *
* that are desired to be shown in the list of available probing functions, *
* whose addresses are valid values in order to update the selected NOP. *
*****************************************************************************/
#include <linux/version.h>
#include <asm/atomic.h>
atomic_t example_var = { .counter = 0 };
DECLARE_PF(example_foo_add)
{
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,17,0)
arch_atomic_inc(&example_var);
#else
atomic_inc(&example_var);
#endif
return;
}
DECLARE_PF(example_foo_sub)
{
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,17,0)
arch_atomic_dec(&example_var);
#else
atomic_dec(&example_var);
#endif
return;
}
/*****************************************************************************
* Once all the available probing funtions have been declared, rembere to *
* insert the relative wrapper within the array devoted to keep track of any *
* one of them. *
*****************************************************************************/
static pf_wrapper pf_array[] = {
WRAP_PF(example_foo_add),
WRAP_PF(example_foo_sub),
WRAP_END /* DO NOT REMOVE */
};
int get_pf_array_size(void)
{
int i;
for (i=0; pf_array[i].pf_ptr != NULL; i++);
return i;
}
char *get_pf_name(int i)
{
if (i < 0 || i >= get_pf_array_size())
return NULL;
return pf_array[i].pf_name;
}
unsigned long get_pf_address(int i)
{
if (i < 0 || i >= get_pf_array_size())
return 0;
return (unsigned long) pf_array[i].pf_ptr;
}
int check_pf_exists(unsigned long addr)
{
int i;
for (i=0; i<get_pf_array_size(); i++)
if (addr == get_pf_address(i))
return 1;
return 0;
} | 31.8125 | 79 | 0.487885 |
4911315e9cb9d245ea2f32bf868c0dca5ccd9ee2 | 899 | c | C | src/malloc/terrible.c | LynnKirby/zeno | fb78f85a308b584448b637552a9fd0d131349041 | [
"CC0-1.0"
] | null | null | null | src/malloc/terrible.c | LynnKirby/zeno | fb78f85a308b584448b637552a9fd0d131349041 | [
"CC0-1.0"
] | null | null | null | src/malloc/terrible.c | LynnKirby/zeno | fb78f85a308b584448b637552a9fd0d131349041 | [
"CC0-1.0"
] | null | null | null | /*
* SPDX-License-Identifier: CC0-1.0
*
* Bump-pointer allocator with 10 MB static size. Used at this stage of
* development so we can allocate things without having to write or import a
* real malloc implementation.
*/
#include "basic/cdefs.h"
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#define DATA_SIZE (10 * 1024 * 1024)
static char data[DATA_SIZE];
static char *current;
size_t count;
void *malloc(size_t size)
{
size = size + 16;
if (count + size > DATA_SIZE) return NULL;
if (!current) {
current = data;
}
char *allocation = (char *)(((uintptr_t)current + 15) & ~15);
current += size;
return allocation;
}
void *calloc(size_t n, size_t size)
{
size *= n; /* Who cares about overflow, really? */
char *a = malloc(size);
return memset(a, 0, size);
}
void free(void *p)
{
UNUSED_PARAM(p);
/* Nothing! */
}
| 18.729167 | 76 | 0.636263 |
d01ec15c16bbcbae041e7f2dbca12f3146068b3a | 2,439 | h | C | FindSecret/Classes/Native/UnityEngine_UnityEngine_AI_NavMeshBuildMarkup1313583865.h | GodIsWord/NewFindSecret | 4f98f316d29936380f9665d6a6d89962d9ee5478 | [
"MIT"
] | null | null | null | FindSecret/Classes/Native/UnityEngine_UnityEngine_AI_NavMeshBuildMarkup1313583865.h | GodIsWord/NewFindSecret | 4f98f316d29936380f9665d6a6d89962d9ee5478 | [
"MIT"
] | null | null | null | FindSecret/Classes/Native/UnityEngine_UnityEngine_AI_NavMeshBuildMarkup1313583865.h | GodIsWord/NewFindSecret | 4f98f316d29936380f9665d6a6d89962d9ee5478 | [
"MIT"
] | null | null | null | #pragma once
#include "il2cpp-config.h"
#ifndef _MSC_VER
# include <alloca.h>
#else
# include <malloc.h>
#endif
#include <stdint.h>
#include "mscorlib_System_ValueType3640485471.h"
#ifdef __clang__
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Winvalid-offsetof"
#pragma clang diagnostic ignored "-Wunused-variable"
#endif
// UnityEngine.AI.NavMeshBuildMarkup
struct NavMeshBuildMarkup_t1313583865
{
public:
// System.Int32 UnityEngine.AI.NavMeshBuildMarkup::m_OverrideArea
int32_t ___m_OverrideArea_0;
// System.Int32 UnityEngine.AI.NavMeshBuildMarkup::m_Area
int32_t ___m_Area_1;
// System.Int32 UnityEngine.AI.NavMeshBuildMarkup::m_IgnoreFromBuild
int32_t ___m_IgnoreFromBuild_2;
// System.Int32 UnityEngine.AI.NavMeshBuildMarkup::m_InstanceID
int32_t ___m_InstanceID_3;
public:
inline static int32_t get_offset_of_m_OverrideArea_0() { return static_cast<int32_t>(offsetof(NavMeshBuildMarkup_t1313583865, ___m_OverrideArea_0)); }
inline int32_t get_m_OverrideArea_0() const { return ___m_OverrideArea_0; }
inline int32_t* get_address_of_m_OverrideArea_0() { return &___m_OverrideArea_0; }
inline void set_m_OverrideArea_0(int32_t value)
{
___m_OverrideArea_0 = value;
}
inline static int32_t get_offset_of_m_Area_1() { return static_cast<int32_t>(offsetof(NavMeshBuildMarkup_t1313583865, ___m_Area_1)); }
inline int32_t get_m_Area_1() const { return ___m_Area_1; }
inline int32_t* get_address_of_m_Area_1() { return &___m_Area_1; }
inline void set_m_Area_1(int32_t value)
{
___m_Area_1 = value;
}
inline static int32_t get_offset_of_m_IgnoreFromBuild_2() { return static_cast<int32_t>(offsetof(NavMeshBuildMarkup_t1313583865, ___m_IgnoreFromBuild_2)); }
inline int32_t get_m_IgnoreFromBuild_2() const { return ___m_IgnoreFromBuild_2; }
inline int32_t* get_address_of_m_IgnoreFromBuild_2() { return &___m_IgnoreFromBuild_2; }
inline void set_m_IgnoreFromBuild_2(int32_t value)
{
___m_IgnoreFromBuild_2 = value;
}
inline static int32_t get_offset_of_m_InstanceID_3() { return static_cast<int32_t>(offsetof(NavMeshBuildMarkup_t1313583865, ___m_InstanceID_3)); }
inline int32_t get_m_InstanceID_3() const { return ___m_InstanceID_3; }
inline int32_t* get_address_of_m_InstanceID_3() { return &___m_InstanceID_3; }
inline void set_m_InstanceID_3(int32_t value)
{
___m_InstanceID_3 = value;
}
};
#ifdef __clang__
#pragma clang diagnostic pop
#endif
| 32.52 | 157 | 0.804018 |
c64b61d44e3a1344b9b20a9065fea3722d997253 | 502 | h | C | client/appliance.h | ortogonal/dbus-properties | 6b62b2d3d96f955790a85f0956958f4e88b823eb | [
"MIT"
] | null | null | null | client/appliance.h | ortogonal/dbus-properties | 6b62b2d3d96f955790a85f0956958f4e88b823eb | [
"MIT"
] | null | null | null | client/appliance.h | ortogonal/dbus-properties | 6b62b2d3d96f955790a85f0956958f4e88b823eb | [
"MIT"
] | null | null | null | #pragma once
#include "dbusinterfaceobject.h"
#include "appliance_interface.h"
class Appliance : public DBusInterfaceObject<org::appliance>
{
Q_OBJECT
Q_PROPERTY(bool running READ running NOTIFY runningChanged)
public:
explicit Appliance(QObject *parent = nullptr);
bool start();
Q_INVOKABLE bool running() const;
signals:
void runningChanged();
public slots:
void setProperties(const QVariantMap &propertyChanges) override;
private:
bool m_running = false;
};
| 17.928571 | 68 | 0.739044 |
f461be1deda63b5371d45874bdc4450404dd9b46 | 2,524 | c | C | src/ft_shadow.c | yvillepo/rt | 3f2ab35f70df98bb80fc31c51afe08cfd3785121 | [
"MIT"
] | 1 | 2020-05-22T22:20:20.000Z | 2020-05-22T22:20:20.000Z | src/ft_shadow.c | jalloulik/raytracer | 27154810da57146359c7b608ca128a99c345d2f6 | [
"MIT"
] | null | null | null | src/ft_shadow.c | jalloulik/raytracer | 27154810da57146359c7b608ca128a99c345d2f6 | [
"MIT"
] | null | null | null | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* ft_shadow.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: kjalloul <kjalloul@student.42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2018/05/29 16:00:08 by kjalloul #+# #+# */
/* Updated: 2018/06/21 17:22:22 by kjalloul ### ########.fr */
/* */
/* ************************************************************************** */
#include "rtv1.h"
int ft_check_obst(t_3dpt *o, t_prim *obst, t_l_p *light_path)
{
double t;
t = ft_return_prim_dist(obst, &(light_path->p_to_light), o);
if (t >= 0 && t < light_path->dist)
return (0);
else
return (1);
}
void ft_resolve_single_prim(t_prim *prim, t_3dpt *ray_dir, t_3dpt *origin)
{
double t;
t = ft_return_prim_dist(prim, ray_dir, origin);
if (t > 0)
{
ft_calculate_vec_end(&(prim->p), origin,
ray_dir, t);
ft_calculate_normal(prim, &(prim->p));
}
}
void ft_shad_rfrct(t_prim *prim, t_prim *small, t_color *clr, t_l_p *l_path)
{
l_path->percent = (l_path->percent + (1 - prim->refract_ratio)) / 2;
if (prim->textur.valid == TRUE || prim->checkers.valid == TRUE)
{
ft_resolve_single_prim(prim, &(l_path->p_to_light), &(small->p));
ft_get_prim_texture_color_main(prim);
ft_shadow_texture(clr, &(prim->color2));
}
}
void ft_light_path(t_obj *obj, t_prim *small, t_l_p *light_path)
{
light_path->dist = ft_get_dist_to_light(obj, small);
ft_calculate_vec_to_light(&(light_path->p_to_light), obj, small);
}
double ft_shadow_percent(t_obj *obj, t_prim *small, int *lit, t_color *color)
{
t_prim *prim;
t_l_p light_path;
light_path.percent = 1;
prim = obj->prim;
ft_light_path(obj, small, &light_path);
while (prim != NULL)
{
if (prim != small)
{
*lit = ft_check_obst(&(small->p), prim, &light_path);
if (*lit == 0)
{
if (prim->refractive == 1)
ft_shad_rfrct(prim, small, color, &light_path);
else
{
light_path.percent = (light_path.percent + 1) / 2;
break ;
}
}
}
prim = prim->next;
}
return (light_path.percent);
}
| 30.047619 | 80 | 0.466323 |
98126746c141da533981ca8553c742134e8f2e97 | 245 | h | C | BigDeal/Sources/types.h | Hubert51/Randomness_Test | d87ee46d092c5c36687981d4cddc5882c8d5becc | [
"MIT"
] | 3 | 2019-04-20T03:38:54.000Z | 2020-02-16T16:21:02.000Z | BigDeal/Sources/types.h | Hubert51/Randomness_Test | d87ee46d092c5c36687981d4cddc5882c8d5becc | [
"MIT"
] | null | null | null | BigDeal/Sources/types.h | Hubert51/Randomness_Test | d87ee46d092c5c36687981d4cddc5882c8d5becc | [
"MIT"
] | null | null | null | /*
* $Header: /home/sater/bridge/bigdeal/RCS/types.h,v 1.2 1999/12/11 09:42:54 sater Exp $
*/
typedef unsigned char byte;
typedef unsigned long dword;
#define RMDsize 160
#define RMDbytes (RMDsize/8)
#define RMDdwords (RMDsize/32)
| 22.272727 | 89 | 0.697959 |
71505c176f48dacef43196d75d03c846ae4f0142 | 13,928 | c | C | src/fourat.c | kernsuite-debian/tirific | 05fddee80e715dfee5d0f4e2f994b2f17c5d2ca9 | [
"MIT"
] | 4 | 2015-07-01T12:07:09.000Z | 2018-01-04T08:22:01.000Z | src/fourat.c | gigjozsa/tirific | 462a58a8312ce437ac5e2c87060cde751774f1de | [
"MIT"
] | 2 | 2017-02-24T12:40:08.000Z | 2019-08-20T06:37:26.000Z | src/fourat.c | kernsuite-debian/tirific | 05fddee80e715dfee5d0f4e2f994b2f17c5d2ca9 | [
"MIT"
] | 3 | 2017-08-28T03:17:38.000Z | 2022-01-03T15:02:35.000Z | /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/**
@file fourat.c
@brief Arithmetics on fourier coefficients
This module contains arithmetics on fourier coefficients. Main
purpose is to filter higher order modes in curves.
$Source: /Volumes/DATA_J_II/data/CVS/tirific/src/fourat.c,v $
$Date: 2011/05/25 22:23:53 $
$Revision: 1.1 $
$Author: jozsa $
$Log: fourat.c,v $
Revision 1.1 2011/05/25 22:23:53 jozsa
added to CVS control
*/
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* EXTERNAL INCLUDES */
/* ------------------------------------------------------------ */
#include <stdlib.h>
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* INTERNAL INCLUDES */
/* ------------------------------------------------------------ */
#include <fourat.h>
#include <maths.h>
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* PRIVATE SYMBOLIC CONSTANTS */
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* PRIVATE MACROS */
/* ------------------------------------------------------------ */
#define FREE_COND(x) if ((x)) free(x)
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* (PRIVATE) GLOBAL VARIABLES */
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* PRIVATE TYPEDEFS */
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* PRIVATE STRUCTS */
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* PRIVATE FUNCTION DECLARATIONS */
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/**
@fn static int averarray(fourat_container *fourat_containerv)
@brief Average array, put the results in interarray
@param fourat_containerv (fourat_containerv *) Allocated fourat_container struct.
@return (success) int averarray 0 (FOURAT_ERR_NONE)
(error) FOURAT_ERR_NARRAY: narray is <= 0
FOURAT_ERR_NULL: NULL passed
*/
/* ------------------------------------------------------------ */
static int averarray(fourat_container *fourat_containerv);
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* FUNCTION CODE */
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* Constructor of a fourat_container struct */
fourat_container *fourat_container_const(void)
{
fourat_container *fc;
if(!(fc = (fourat_container *) malloc(sizeof(fourat_container))))
return NULL;
fc -> narray = 0;
fc -> array = NULL;
fc -> nact = 0;
fc -> act = NULL;
fc -> nnum = 0;
fc -> num = NULL;
fc -> nden = 0;
fc -> den = NULL;
fc -> huge_dbl = DBL_MAX;
fc -> harmarray = NULL;
fc -> avarray = NULL;
fc -> plan = NULL;
fc -> dephi = NULL;
fc -> deplo = NULL;
return fc;
}
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* Destructor of a fourat_container struct */
void fourat_container_destr(fourat_container *fc)
{
if (!fc)
return;
FREE_COND(fc -> array);
FREE_COND(fc -> act);
FREE_COND(fc -> num);
FREE_COND(fc -> den);
if (fc -> harmarray)
fftw_free(fc -> harmarray);
if (fc -> avarray)
fftw_free(fc -> avarray);
FREE_COND(fc -> dephi);
FREE_COND(fc -> deplo);
if ((fc -> plan))
fftw_destroy_plan(fc -> plan);
free(fc);
return;
}
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* Entering array lengths */
int fourat_put_length(fourat_container *fc, int narray, int nact, int nnum, int nden, double huge_dbl)
{
int errcode = FOURAT_ERR_NONE;
if (!(fc)) {
return FOURAT_ERR_NULL;
}
/* Check */
if (narray <= 0) {
errcode |= FOURAT_ERR_NARRAY;
}
else {
if (!fc -> array)
fc -> narray = narray;
}
if (nact < 0) {
errcode |= FOURAT_ERR_NACT;
}
else {
if (!fc -> act)
fc -> nact = nact;
}
if (nden < 0) {
errcode |= FOURAT_ERR_NDEN;
}
else {
if (!fc -> den)
fc -> nden = nden;
}
if (nnum < 0) {
errcode |= FOURAT_ERR_NNUM;
}
else {
if (!fc -> num)
fc -> nnum = nnum;
}
if (huge_dbl < 0.0) {
fc -> huge_dbl = DBL_MAX;
}
else {
fc -> huge_dbl = huge_dbl;
}
return errcode;
}
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* Entering vectors */
int fourat_put_vectors(fourat_container *fc, double *array, int *act, int *num, int *den)
{
int errm = FOURAT_ERR_NONE;
int i;
if (!(fc)) {
return FOURAT_ERR_NULL;
}
/* input array cannot cause an error */
for (i = 0; i < fc -> narray; ++i)
fc -> array[i] = array[i];
/* Now check whether the arrays contain proper numbers */
for (i = 0; i < fc -> nact; ++i) {
if (act[i] < 0)
errm |= FOURAT_ERR_OUTACT;
if (fc -> nact > 0){
if (act[i] >= fc -> narray)
errm |= FOURAT_ERR_OUTACT;
}
}
for (i = 0; i < fc -> nden; ++i) {
if (den[i] < 0)
errm |= FOURAT_ERR_OUTDEN;
if (fc -> nden > 0){
if (den[i] > (fc -> narray/2))
errm |= FOURAT_ERR_OUTDEN;
}
}
for (i = 0; i < fc -> nnum; ++i) {
if (num[i] < 0)
errm |= FOURAT_ERR_OUTDEN;
if (fc -> nnum > 0){
if (num[i] > (fc -> narray/2))
errm |= FOURAT_ERR_OUTNUM;
}
}
/* Then copy them into the allocated arrays */
if (!(errm & FOURAT_ERR_OUTACT)) {
for (i = 0; i < fc -> nact; ++i)
fc -> act[i] = act[i];
}
if (!(errm & FOURAT_ERR_OUTDEN)) {
for (i = 0; i < fc -> nden; ++i)
fc -> den[i] = den[i];
}
if (!(errm & FOURAT_ERR_OUTNUM)) {
for (i = 0; i < fc -> nnum; ++i)
fc -> num[i] = num[i];
}
return errm;
}
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* Initialisation of fourat_container struct, alias */
int fourat_meminit(fourat_container *fc)
{
return fourat_init(fc);
}
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* Initialisation of fourat_container struct */
int fourat_init(fourat_container *fc)
{
int errm = 0;
int i, j, loval, hival, curnext;
/* First look if everything is ok */
if (!(fc)) {
errm |= FOURAT_ERR_NULL;
goto error;
}
if (fc -> narray <= 0) {
errm |= FOURAT_ERR_NARRAY;
}
else {
/* Allocate */
if (!(fc -> array)) {
if (!(fc -> array = (double *) malloc(fc -> narray*sizeof(double)))) {
errm |= FOURAT_ERR_MEMORY;
goto error;
}
}
if (!(fc -> harmarray)) {
if (!(fc -> harmarray = (fftw_complex *) fftw_malloc((fc -> narray/2+1)*sizeof(fftw_complex)))) {
errm |= FOURAT_ERR_MEMORY;
goto error;
}
}
if (!(fc -> avarray)) {
if (!(fc -> avarray = (double *) fftw_malloc(fc -> narray*sizeof(double)))) {
errm |= FOURAT_ERR_MEMORY;
goto error;
}
}
/* Make a plan */
fc -> plan = fftw_plan_dft_r2c_1d(fc -> narray, fc -> avarray, fc -> harmarray, FFTW_ESTIMATE | FFTW_PRESERVE_INPUT);
}
if (fc -> nact < 0) {
errm |= FOURAT_ERR_NACT;
}
else {
if (!(fc -> act)) {
if (fc -> nact > 0) {
if (!(fc -> act = (int *) malloc(fc -> nact*sizeof(int)))) {
errm |= FOURAT_ERR_MEMORY;
goto error;
}
}
/* Set all the numbers to 0 */
for (i = 0; i < fc -> nact; ++i) {
fc -> act[i] = 0;
}
}
}
if (fc -> nnum < 0) {
errm |= FOURAT_ERR_NNUM;
}
else {
if (!(fc -> num)) {
if (fc -> nnum > 0) {
if (!(fc -> num = (int *) malloc(fc -> nnum*sizeof(int)))) {
errm |= FOURAT_ERR_MEMORY;
goto error;
}
}
/* Set all the numbers to 0 */
for (i = 0; i < fc -> nnum; ++i) {
fc -> num[i] = 0;
}
}
}
if (fc -> nden < 0) {
errm |= FOURAT_ERR_NDEN;
}
else {
if (!(fc -> den)) {
if (fc -> nden > 0) {
if (!(fc -> den = (int *) malloc(fc -> nden*sizeof(int)))) {
errm |= FOURAT_ERR_MEMORY;
goto error;
}
}
/* Set all the numbers to 0 */
for (i = 0; i < fc -> nden; ++i) {
fc -> den[i] = 0;
}
}
}
/* Now check whether the arrays contain proper numbers */
for (i = 0; i < fc -> nact; ++i) {
if (fc -> act[i] < 0)
errm |= FOURAT_ERR_OUTACT;
if (fc -> nact > 0){
if (fc -> act[i] >= fc -> narray)
errm |= FOURAT_ERR_OUTACT;
}
}
for (i = 0; i < fc -> nden; ++i) {
if (fc -> den[i] < 0)
errm |= FOURAT_ERR_OUTDEN;
if (fc -> nden > 0){
if (fc -> den[i] > (fc -> narray/2))
errm |= FOURAT_ERR_OUTDEN;
}
}
for (i = 0; i < fc -> nnum; ++i) {
if (fc -> num[i] < 0)
errm |= FOURAT_ERR_OUTDEN;
if (fc -> nnum > 0){
if (fc -> num[i] > (fc -> narray/2))
errm |= FOURAT_ERR_OUTNUM;
}
}
/* Now allocate and fill the dependant array */
/* a[k] = a[deplo[k]]+(k-deplo[k])*(a[dephi[k]]-a[deplo[k]])/(dephi[k]-deplo[k]) */
if ((fc -> narray)) {
if (!(fc -> dephi)) {
if (!(fc -> dephi = (int *) malloc(fc -> narray*sizeof(int)))) {
errm |= FOURAT_ERR_MEMORY;
goto error;
}
}
if (!(fc -> deplo)) {
if (!(fc -> deplo = (int *) malloc(fc -> narray*sizeof(int)))) {
errm |= FOURAT_ERR_MEMORY;
goto error;
}
}
}
/* Fill that array */
if (fc -> nact > 0) {
/* find the lowest value */
loval = fc -> narray;
for (i = 0; i < fc -> nact; ++i) {
if (fc -> act[i] < loval)
loval = fc -> act[i];
}
/* find the highest value */
hival = -1;
for (i = 0; i < fc -> nact; ++i) {
if (fc -> act[i] > hival)
hival = fc -> act[i];
}
/* Everything below loval points to loval */
for (i = 0; i < loval; ++i) {
fc -> deplo[i] = fc -> dephi[i] = loval;
}
/* loval points to loval */
fc -> deplo[i] = fc -> dephi[i] = loval;
++i;
/* Find the next higher active */
while (i < hival) {
curnext = fc -> narray;
for (j = 0; j < fc -> nact; ++j) {
if ((fc -> act[j] >= i) && (fc -> act[j] < curnext)) {
curnext = fc -> act[j];
}
}
if (curnext == i)
loval = i;
fc -> deplo[i] = loval;
fc -> dephi[i] = curnext;
++i;
}
while (i < fc -> narray) {
fc -> deplo[i] = fc -> dephi[i] = hival;
++i;
}
}
else {
/* This basically means that we filter all data points */
for (i = 0; i < fc -> narray; ++i) {
fc -> deplo[i] = fc -> dephi[i] = 0;
}
}
return errm;
error:
return errm;
}
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* Average array, put the results in avarray */
static int averarray(fourat_container *fc)
{
int i;
if (fc -> narray <= 0)
return FOURAT_ERR_NARRAY;
if (!(fc -> array))
return FOURAT_ERR_NULL;
for (i = 0; i < fc -> narray; ++i) {
if (fc -> deplo[i] == fc -> dephi[i]) {
fc -> avarray[i] = fc -> array[fc -> deplo[i]];
}
else {
fc -> avarray[i] = fc -> array[fc -> deplo[i]]+(((double) i)-((double) fc -> deplo[i]))*(fc -> array[fc -> dephi[i]]-fc -> array[fc -> deplo[i]])/(fc -> dephi[i]-fc -> deplo[i]);
}
}
return FOURAT_ERR_NONE;
}
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* Average array, put the results in avarray */
int fourat_rat(fourat_container *fc, double *ratio, int mode)
{
int errcode = 0, i;
double sumden = 0.0, sumnum = 0.0;
if (!fc) {
errcode |= FOURAT_ERR_NULL;
goto error;
}
if (!ratio) {
errcode |= FOURAT_ERR_NULL;
goto error;
}
/* Averaging */
if ((errcode = averarray(fc)))
goto error;
/* Fourier transform */
fftw_execute(fc -> plan);
for (i = 0; i < fc -> nnum; ++i) {
sumnum += sqrt(fc -> harmarray[fc -> num[i]][0]*fc -> harmarray[fc -> num[i]][0]+fc -> harmarray[fc -> num[i]][1]*fc -> harmarray[fc -> num[i]][1]);
}
if (mode == FOURAT_RAT_SUM) {
*ratio = sumnum;
return errcode;
}
/* Calculate the sum of the denominator elements */
for (i = 0; i < fc -> nden; ++i) {
sumden += sqrt(fc -> harmarray[fc -> den[i]][0]*fc -> harmarray[fc -> den[i]][0]+fc -> harmarray[fc -> den[i]][1]*fc -> harmarray[fc -> den[i]][1]);
}
if (sumnum == 0.0) {
*ratio = 0;
}
else {
if (sumden == 0.0) {
*ratio = fc -> huge_dbl;
}
else {
*ratio = sumnum/sumden;
}
}
return errcode;
error:
return errcode;
}
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* Entering the array to be Fourier-transformed */
void fourat_put_array(fourat_container *fc, double *array)
{
int i;
/* input array cannot cause an error */
for (i = 0; i < fc -> narray; ++i)
fc -> array[i] = array[i];
return;
}
/* ------------------------------------------------------------ */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
$Log: fourat.c,v $
Revision 1.1 2011/05/25 22:23:53 jozsa
added to CVS control
------------------------------------------------------------ */
| 23.097844 | 184 | 0.421884 |
19db6eaf4b2cb7bb16624be290ffc98f0e2808d5 | 45,560 | h | C | ds/ds/src/ldap/client/ldapp.h | npocmaka/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 17 | 2020-11-13T13:42:52.000Z | 2021-09-16T09:13:13.000Z | ds/ds/src/ldap/client/ldapp.h | sancho1952007/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 2 | 2020-10-19T08:02:06.000Z | 2020-10-19T08:23:18.000Z | ds/ds/src/ldap/client/ldapp.h | sancho1952007/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 14 | 2020-11-14T09:43:20.000Z | 2021-08-28T08:59:57.000Z | /*++
Copyright (c) 1996 Microsoft Corporation
Module Name:
ldapp.h LDAP client 32 API header file... internal structures
Abstract:
This module is the header file for the 32 bit LDAP client API code...
it contains all interal data structures.
Author:
Andy Herron (andyhe) 08-May-1996
Anoop Anantha (AnoopA) 24-Jun-1998
Revision History:
--*/
#ifndef LDAP_CLIENT_INTERNAL_DEFINED
#define LDAP_CLIENT_INTERNAL_DEFINED
#define LDAP_DEFAULT_LOCALE LOCALE_USER_DEFAULT
#define PLDAPDN PWCHAR
typedef struct ldap_memory_descriptor {
ULONG Tag;
DWORD Length;
} LDAP_MEMORY_DESCRIPTOR, *PLDAP_MEMORY_DESCRIPTOR;
// the following signature is "Lsec"
#define LDAP_SECURITY_SIGNATURE 0x6365734c
#define GENERIC_SECURITY_SIZE 1024
//
// State of the connection object
// Closed objects are kept alive till their ref count drops to zero.
// Ref count of a non-active object should never be incremented - it
// should be treated as dead as far as new users are concerned.
//
#define ConnObjectActive 1
#define ConnObjectClosing 2
#define ConnObjectClosed 3
//
// State of the connection inside the connection object
// These are valid only if the connection object is active
//
#define HostConnectStateUnconnected 0x01
#define HostConnectStateConnecting 0x02
#define HostConnectStateReconnecting 0x04
#define HostConnectStateConnected 0x08
#define HostConnectStateError 0x10
#define DEFAULT_NEGOTIATE_FLAGS (ISC_REQ_MUTUAL_AUTH | ISC_RET_EXTENDED_ERROR)
//
// The LDAP_CONNECTION block is one of the principal data structure for
// this library. It tracks the following :
//
// - destination server info (name, address, credentials, etc)
// - outstanding receives from this server
// - completed receives from this server
// - stats and other per connection info
//
// It contains within it the non-opaque structure exposed through the API
// that is compatible with the reference implementation not only at the
// source level but also at the obj level. ( That is, the fields such as
// sb_naddr that are exposed in the reference implementation correspond in
// offset to the friendlier names in this structure at the same offset. In
// the case of sb_naddr, it corresponds to UdpHandle. )
//
// All important fields that we don't want theoritically trashed by the client
// (since it's not clear what fields apps will use in the reference
// implementation) are in front of the external structure in the larger
// overall structure. That is, we only pass back a pointer to TcpHandle and
// below and everything above should never be touched by the client).
//
//
// This MUST match the ldap structure in WINLDAP.H! We just have it here
// so that we can use friendly names and hide opaque fields.
//
#if !defined(_WIN64)
#pragma pack(push, 4)
#endif
typedef struct ldap_connection {
LONG ReferenceCount; // for lifetime management
LIST_ENTRY ConnectionListEntry;
LIST_ENTRY PendingCryptoList;
LIST_ENTRY CompletedReceiveList;
PLDAPMessage PendingMessage; // pointer to LDAP message structure
// that we're currently receiving. This
// is used for receiving a message that
// spans multiple packets.
ULONG MaxReceivePacket;
ULONG HandlesGivenToCaller; // number of times we've given handle
// to caller
ULONG HandlesGivenAsReferrals; // protected by ConnectionListLock.
PLDAPDN DNOnBind; // user name specified in bind
LDAP_LOCK ScramblingLock; // protects access to the credentials.
PWCHAR CurrentCredentials; // user credentials specified on bind
UNICODE_STRING ScrambledCredentials; // contains the password part of CurrentCredentials
BOOLEAN Scrambled; // are the credentials scrambled ?
ULONG BindMethod; // method specified on bind
HANDLE ConnectEvent; // handle to wait on for during connect
LUID CurrentLogonId;
CredHandle hCredentials; // credential handle from SSPI
BOOLEAN UserSignDataChoice; // user's choice of whether to sign data
BOOLEAN UserSealDataChoice; // user's choice of whether to seal data
BOOLEAN CurrentSignStatus; // whether signing or sealing are CURRENTLY
BOOLEAN CurrentSealStatus; // being used on this connection
BOOLEAN WhistlerServer; // is server at least Whister?
BOOLEAN SupportsGSSAPI; // server advertises that it supports GSSAPI
BOOLEAN SupportsGSS_SPNEGO; // server advertises that it supports GSS-SPNEGO
BOOLEAN SupportsDIGEST; // server advertises that it supports DIGEST-MD5
ULONG HighestSupportedLdapVersion; // server advertised LDAP version.
TimeStamp CredentialExpiry; // local time credential expires.
CtxtHandle SecurityContext;
struct sockaddr_in SocketAddress;
PWCHAR ListOfHosts; // pointer to list of hosts.
BOOLEAN ProcessedListOfHosts; // whether ListOfHosts has been processed into NULL-sep list
BOOLEAN DefaultServer; // whether user requested we find default server/domain (passed in NULL init/open)
BOOLEAN AREC_Exclusive; // the given host string is not a domain name.
BOOLEAN ForceHostBasedSPN; // force use of LdapMakeServiceNameFromHostName to generate SPN
PWCHAR ServiceNameForBind; // service name for kerberos bind
PWCHAR ExplicitHostName; // host name given to us by caller
PWCHAR DnsSuppliedName; // host name supplied by DNS
PWCHAR DomainName; // Domain name returned from DsGetDcName
PWCHAR HostNameW; // Unicode version of LDAP_CONN.HostName
PCHAR OptHostNameA; // Placeholder for the ANSI value returned from LDAP_OPT_HOSTNAME
// which we need to free during ldap_unbind
PLDAP ExternalInfo; // points to lower portion of this structure
ULONG GetDCFlags; // flags ORed in on DsGetDCName
ULONG NegotiateFlags; // Flags for Negotiate SSPI provider.
BOOLEAN UserMutualAuthChoice; // user's choice of whether to enforce mutual auth
DWORD ResolvedGetDCFlags; // flags _returned_ by DsGetDcName
//
// fields required for keep alive logic
//
LONG ResponsesExpected; // number of responses that are pending
ULONGLONG TimeOfLastReceive; // tick count that we last received a response.
ULONG KeepAliveSecondCount;
ULONG PingWaitTimeInMilliseconds;
USHORT PingLimit;
USHORT NumberOfPingsSent; // number of unanswered pings we've sent before closing
USHORT GoodConsecutivePings; // number of consecutive answered pings we've sent before closing
BOOLEAN UseTCPKeepAlives; // whether to turn on TCP's keep-alive functionality
USHORT NumberOfHosts;
USHORT PortNumber; // port number used on connect
LDAP_LOCK StateLock; // protect updates to states below
UCHAR ConnObjectState; // state of connection object
UCHAR HostConnectState; // have we connected to the server?
BOOLEAN ServerDown; // State of server
BOOLEAN AutoReconnect; // whether autoreconnect is desired
BOOLEAN UserAutoRecChoice; // User's choice for Autoreconnect.
BOOLEAN Reconnecting;
LDAP_LOCK ReconnectLock; // to single thread autoreconnect requests
LONG WaiterCount; // Number of threads waiting on this connection
ULONGLONG LastReconnectAttempt; // Timestamp of last Autoreconnect attempt
ULONG SendDrainTimeSeconds; // how many seconds to spend draining receive data
// in LdapSendRaw
//
// Bind data for this connection.
//
BOOLEAN BindInProgress; // Are we currently exchanging bind packets?
BOOLEAN SspiNeedsResponse; // Does SSPI need the server response?
BOOLEAN SspiNeedsMoreData; // Is the SSPI token incomplete?
BOOLEAN TokenNeedsCompletion; // Does SSPI need to complete the token before we
// send it to the server?
BOOLEAN BindPerformed; // Is the bind complete?
BOOLEAN SentPacket; // have we sent a packet to this connection?
BOOLEAN SslPort; // Is this a connection to a well known SSL port 636/3269?
BOOLEAN SslSetupInProgress; // Are we currently setting up an SSL session?
BOOLEAN ConcurrentBind; // Are we running in fast concurrent bind mode?
ULONG PreTLSOptions; // Referral chasing options prior to Starting TLS.
BOOLEAN PromptForCredentials; // do we prompt for credentials?
PSecPkgInfoW PreferredSecurityPackage; // User wants to use this package if possible
PWCHAR SaslMethod; // The preferred SASL method for this connection
//
// when this flag is set to true, we reference connections for each
// message we get in for all the requests with this connection as primary.
//
BOOLEAN ReferenceConnectionsPerMessage;
PLDAPMessage BindResponse; // The response that holds the inbound token.
//
// The sicily server authentication requires a different bind method
// number depending on which packet of the authentication sequence
// we are currently in (YUCK), so we have to keep track.
//
ULONG CurrentAuthLeg;
//
// Important SSL Notes:
//
// When we have to do an SSL send, we may have to break the message up
// into multiple crypto blocks. We MUST send these blocks in order and
// back to back without any intervening sends. The SocketLock protects
// sends and socket closures on the connection in this manner; any thread
// wishing to do a send on an SSL connection MUST acquire this lock.
//
PVOID SecureStream; // Crypto stream object (handles all SSPI details).
CRITICAL_SECTION SocketLock;
//
// Callback routines to allow caching of connections by ADSI etc.
//
QUERYFORCONNECTION *ReferralQueryRoutine;
NOTIFYOFNEWCONNECTION *ReferralNotifyRoutine;
DEREFERENCECONNECTION *DereferenceNotifyRoutine;
//
// Callback routines to allow specifying client certificates and validating
// server certificates.
//
QUERYCLIENTCERT *ClientCertRoutine;
VERIFYSERVERCERT *ServerCertRoutine;
//
// this is considered the top of the struct LDAP structure that we pass
// back to the application.
//
LDAP publicLdapStruct;
} LDAP_CONN, * PLDAP_CONN;
#if !defined(_WIN64)
#pragma pack(pop)
#endif
#define TcpHandle publicLdapStruct.ld_sb.sb_sd
#define UdpHandle publicLdapStruct.ld_sb.sb_naddr
// the following signature is "LCon"
#define LDAP_CONN_SIGNATURE 0x6e6f434c
//
// This macro returns TRUE if a flag in a set of flags is on and FALSE
// otherwise. It is followed by two macros for setting and clearing
// flags
//
#define BooleanFlagOn(Flags,SingleFlag) \
((BOOLEAN)((((Flags) & (SingleFlag)) !=0)))
#define SetFlag(Flags,SingleFlag) { \
(Flags) |= (SingleFlag); \
}
#define ClearFlag(Flags,SingleFlag) { \
(Flags) &= ~(SingleFlag); \
}
//
// Entry that we keep off the THREAD_ENTRY block per connection that is being
// used on this thread.
//
typedef struct error_entry {
struct error_entry * pNext;
PLDAP_CONN Connection; // primary connection
ULONG ThreadId; // Thread for which this error applies
PWCHAR ErrorMessage; // Error message
} ERROR_ENTRY, *PERROR_ENTRY;
//
// Per thread current attribute for ldap_first_attribute. This structure is
// stored as a linked list in the THREAD_ENTRY, one for each connection being
// used on that thread.
//
typedef struct ldap_attr_name_per_thread {
struct ldap_attr_name_per_thread *pNext;
DWORD Thread;
PLDAP_CONN PrimaryConn;
LDAP_MEMORY_DESCRIPTOR AttrTag;
UCHAR AttributeName[ MAX_ATTRIBUTE_NAME_LENGTH ];
LDAP_MEMORY_DESCRIPTOR AttrTagW;
WCHAR AttributeNameW[ MAX_ATTRIBUTE_NAME_LENGTH ];
} LDAP_ATTR_NAME_THREAD_STORAGE, *PLDAP_ATTR_NAME_THREAD_STORAGE;
// the following signature is "LAtr"
#define LDAP_ATTR_THREAD_SIGNATURE 0x7274414c
//
// THREAD_ENTRY: A global linked list of these is maintained
// with one per thread. This is used to hold the linked lists
// of per-connection error and attribute entries for that thread.
//
typedef struct thread_entry {
LIST_ENTRY ThreadEntry;
DWORD dwThreadID;
PERROR_ENTRY pErrorList;
PLDAP_ATTR_NAME_THREAD_STORAGE pCurrentAttrList;
} THREAD_ENTRY, *PTHREAD_ENTRY;
//
// Entry that we keep off the LDAP_REQUEST block per referral we've chased
// for this request.
//
typedef struct referral_table_entry {
PLDAP_CONN ReferralServer; // referenced pointer
PWCHAR ReferralDN; // DN for referral
ULONG ScopeOfSearch; // Scope of search
PWCHAR SearchFilter; // Search Filter
PWCHAR *AttributeList; // List of attributes
PVOID BerMessageSent; // Message sent in BER format
ULONG RequestsPending;
USHORT ReferralInstance; // unique ID for this referral
BOOLEAN SingleLevelSearch; // is this a single level search where
// subordinate referrals would be base srch
BOOLEAN CallDerefCallback; // do we call caching deref callback?
ULONG ResentAttempts; // how many times has this referral been resent?
} REFERRAL_TABLE_ENTRY, *PREFERRAL_TABLE_ENTRY;
// the following signature is "LRTa"
#define LDAP_REFTABLE_SIGNATURE 0x6154524c
// the following signature is "LRDN"
#define LDAP_REFDN_SIGNATURE 0x4e44524c
//
// The LDAP_REQUEST block is another of the principal data structure for
// this library. Most other structures are linked off of it.
// It tracks the following :
//
// - list of responses received for this request, including referred
// - list of connections that this Request has used.
// - resource lock to protect lists and other important fields
//
typedef struct ldap_request {
LIST_ENTRY RequestListEntry;
LONG ReferenceCount;
PLDAPMessage MessageLinkedList; // pointer to head... pulled from here
PLDAP_CONN PrimaryConnection; // referenced pointer
//
// SecondayConnection points to an external referred server (if one exists)
// We redirect all of our paged searches to this searver
//
PLDAP_CONN SecondaryConnection;
LDAP_LOCK Lock;
ULONGLONG RequestTime;
ULONG TimeLimit; // 0 implies no limit
ULONG SizeLimit; // 0 implies no limit
ULONG ReturnCode; // error returned by server
LONG MessageId; // unique across all connections
//
// Per Request per Connection, we maintain a count of how many requests we
// have outstanding. This allows us to not hang when we call into
// DrainWinsock when we really don't have anything to wait on.
//
// This is stored off of the request block, where it's traversed at abandon
// time. It's cross referenced with the connection where it's searched
// when the connection goes down.
//
ULONG RequestsPending;
PVOID BerMessageSent; // Message sent in BER format
PREFERRAL_TABLE_ENTRY ReferralConnections; // pointer to table
USHORT ReferralTableSize;
USHORT ReferralHopLimit;
USHORT ReferralCount; // incremented every time we chase a new one
//
// Track the number of requests to different servers we have open such
// that we don't stop returning data prematurely.
//
USHORT ResponsesOutstanding; // sum of requests pending for all referrals
BOOLEAN Abandoned;
UCHAR ChaseReferrals;
UCHAR Operation;
//
// If the call is synchronous, then the pointers that we have below for
// the different parameters are not allocated, they simply point back to
// the original caller's parameters.
//
BOOLEAN Synchronous;
//
// When this has been closed, this will be true.
//
BOOLEAN Closed;
//
// when this flag is set to true, we reference connections for each
// message we get in so that the app can call ldap_conn_from_msg.
//
BOOLEAN ReferenceConnectionsPerMessage;
//
// When a notification control is detected, we set this to TRUE to
// avoid deleting the BER request buffer upon returning notifications.
//
BOOLEAN NotificationSearch;
//
// These store the original parameters for each operation. We have to
// store these since chasing a referral may mean we need to regenerate
// the ASN1 since the DN can change.
//
PWCHAR OriginalDN;
PLDAPControlW *ServerControls; // array of controls
PLDAPControlW *ClientControls; // array of controls
struct ldap_request *PageRequest; // Original Page request
LDAP_BERVAL *PagedSearchServerCookie;
union {
struct {
LDAPModW **AttributeList;
BOOLEAN Unicode;
} add;
struct {
PWCHAR Attribute;
PWCHAR Value;
struct berval Data;
} compare;
struct {
LDAPModW **AttributeList;
BOOLEAN Unicode;
} modify;
struct {
PWCHAR NewDistinguishedName;
PWCHAR NewParent;
INT DeleteOldRdn;
} rename;
struct {
ULONG ScopeOfSearch;
PWCHAR SearchFilter;
PWCHAR *AttributeList;
ULONG AttributesOnly;
BOOLEAN Unicode;
} search;
struct {
struct berval Data;
} extended;
};
LONG PendingPagedMessageId;
BOOLEAN GotExternalReferral; // we have to send requests to an alternate
// server (PrimaryConnection->ExternalReferredServer)
BOOLEAN AllocatedParms;
BOOLEAN AllocatedControls;
BOOLEAN PagedSearchBlock; // is this a block controlling a paged
// search? if FALSE, then normal request
BOOLEAN ReceivedData; // have we received data on this paged
// search request? also used on non-paged.
BOOLEAN CopyResultToCache; // Before closing the request, copy result
// contents to cache
BOOLEAN ResultsAreCached; // Don't go to the wire to get results. They
// are already queued to your recv buffers
ULONG ResentAttempts; // Number of times this request has been
// resent during autoreconnects
} LDAP_REQUEST, * PLDAP_REQUEST;
// the following signature is "LReq"
#define LDAP_REQUEST_SIGNATURE 0x7165524c
//
// The LDAP_RECVBUFFER structure is used to receive a server's response.
// It contains the necessary fields to passdown to the transport through
// winsock to receive data.
//
// These are linked into the LDAP_CONN structure via the CompletedReceiveList
// for messages that have already been received.
//
// The CompletedReceiveList is ordered... newly received LDAP_RECVBUFFER
// structures are put on the end. This is so that if a server sends
// responses ordered, we maintain the order when we pass the results up to
// the calling program.
//
typedef struct ldap_recvbuffer {
PLDAP_CONN Connection;
LIST_ENTRY ReceiveListEntry;
DWORD NumberOfBytesReceived;
DWORD NumberOfBytesTaken; // number of bytes already copied off to msgs
DWORD BufferSize;
UCHAR DataBuffer[1];
} LDAP_RECVBUFFER, * PLDAP_RECVBUFFER;
// the following signature is "LRec"
#define LDAP_RECV_SIGNATURE 0x6365524c
//
// this structure is used to track the messages we have to check for waiters.
// we store them off rather than calling directly so as not to muck with the
// locking order.
//
typedef struct message_id_list_entry {
struct message_id_list_entry *Next;
ULONG MessageId;
} MESSAGE_ID_LIST_ENTRY, *PMESSAGE_ID_LIST_ENTRY;
#define LDAP_MSGID_SIGNATURE 0x64494d4c
//
// The LDAP_MESSAGEWAIT structure is used by a thread that wants to wait for
// a message from a server.
// It allocates one by calling LdapGetMessageWaitStructure
// This initializes an event the thread can wait on and puts the block on
// a global list of waiting threads.
//
// When a message comes in, the receive thread will satisfy a wait for a thread
// on the waiters list. This thread will then process the message and satisfy
// any other waiters that should be.
//
// These structures are freed by the calling thread using
// LdapFreeMessageWaitStructure.
//
// The structure has a few fields of interest :
// - event for thread to wait on that is triggered when message comes in
// - message number that waiting thread is interested in (0 if interested
// in all messages from server)
// - list entry for list of outstanding wait structures
// - connection that client is interested in, null is ok. Just means the
// thread is waiting for any message
//
typedef struct ldap_messagewait {
LIST_ENTRY WaitListEntry;
PLDAP_CONN Connection; // referenced pointer
HANDLE Event;
ULONG MessageNumber; // may be zero
ULONG AllOfMessage; // for search results, trigger at last response?
BOOLEAN Satisfied;
BOOLEAN PendingSendOnly; // is this wait only a pending send?
} LDAP_MESSAGEWAIT, * PLDAP_MESSAGEWAIT;
typedef struct _SOCKHOLDER {
SOCKET sock; // socket used in the connection
LPSOCKET_ADDRESS psocketaddr; // corresponding pointer to connecting address
PWCHAR DnsSuppliedName; // Name returned from DNS
} SOCKHOLDER, *PSOCKHOLDER;
typedef struct _SOCKHOLDER2 {
LPSOCKET_ADDRESS psocketaddr; // address to connect to
PWCHAR DnsSuppliedName; // Name returned from DNS
} SOCKHOLDER2, *PSOCKHOLDER2;
typedef struct _LDAPReferralDN
{
PWCHAR ReferralDN; // DN present in the referral
PWCHAR * AttributeList; // Attributes requested
ULONG AttribCount; // Number of attributes requested
ULONG ScopeOfSearch; // Search scope
PWCHAR SearchFilter; // search filter
PWCHAR Extension; // Extension part of the URL
PWCHAR BindName; // A bindname extension for the URL
} LDAPReferralDN, * PLDAPReferralDN;
typedef struct _EncryptHeader_v1
{
ULONG EncryptMessageSize;
} EncryptHeader_v1, *PEncryptHeader_v1;
//
// On the wire, the following signature appears as "ENCRYPTD"
//
#define LDAP_ENCRYPT_SIGNATURE 0x4454505952434e45
//
// hd.exe which is found in the idw directory was used to create these tags.
//
// the following signature is "LWai"
#define LDAP_WAIT_SIGNATURE 0x6961574c
// the following signature is "LBer"
#define LDAP_LBER_SIGNATURE 0x7265424c
// the following signature is "LMsg"
#define LDAP_MESG_SIGNATURE 0x67734d4c
// the following signature is "LStr"
#define LDAP_STRING_SIGNATURE 0x7274534c
// the following signature is "LVal"
#define LDAP_VALUE_SIGNATURE 0x6C61564c
// the following signature is "LVll"
#define LDAP_VALUE_LIST_SIGNATURE 0x6C6C564c
// the following signature is "LBuf"
#define LDAP_BUFFER_SIGNATURE 0x6675424c
// the following signature is "LUDn"
#define LDAP_USER_DN_SIGNATURE 0x6e44554c
// the following signature is "LGDn"
#define LDAP_GENERATED_DN_SIGNATURE 0x6e44474c
// the following signature is "LCre"
#define LDAP_CREDENTIALS_SIGNATURE 0x6572434c
// the following signature is "LBCl"
#define LDAP_LDAP_CLASS_SIGNATURE 0x6c43424c
// the following signature is "LAns"
#define LDAP_ANSI_SIGNATURE 0x736e414c
// the following signature is "LUni"
#define LDAP_UNICODE_SIGNATURE 0x696e554c
// the following signature is "LSsl"
#define LDAP_SSL_CLASS_SIGNATURE 0x6c73534c
// the following signature is "LAtM"
#define LDAP_ATTRIBUTE_MODIFY_SIGNATURE 0x4d74414c
// the following signature is "LMVa"
#define LDAP_MOD_VALUE_SIGNATURE 0x61564d4c
// the following signature is "LMVb"
#define LDAP_MOD_VALUE_BERVAL_SIGNATURE 0x62564d4c
// the following signature is "LSel"
#define LDAP_SELECT_READ_SIGNATURE 0x6c65534c
// the following signature is "LCnt"
#define LDAP_CONTROL_SIGNATURE 0x746e434c
// the following signature is "LCrl"
#define LDAP_CONTROL_LIST_SIGNATURE 0x6c72434c
// the following signature is "LBad"
#define LDAP_DONT_FREE_SIGNATURE 0x6461424c
// the following signature is "LFre"
#define LDAP_FREED_SIGNATURE 0x6572464c
// the following signature is "LExO"
#define LDAP_EXTENDED_OP_SIGNATURE 0x4f78454c
// the following signature is "LCda"
#define LDAP_COMPARE_DATA_SIGNATURE 0x6164434c
// the following signature is "LEsc"
#define LDAP_ESCAPE_FILTER_SIGNATURE 0x6373454c
// the following signature is "LHst"
#define LDAP_HOST_NAME_SIGNATURE 0x7473484c
// the following signature is "LBvl"
#define LDAP_BERVAL_SIGNATURE 0x6c76424c
// the following signature is "LSrv"
#define LDAP_SERVICE_NAME_SIGNATURE 0x7672534c
// the following signature is "LSdr"
#define LDAP_SOCKADDRL_SIGNATURE 0x7264534c
// the following signature is "LErr"
#define LDAP_ERROR_SIGNATURE 0x7272454c
// the following signature is "LUrl"
#define LDAP_URL_SIGNATURE 0x6c72554c
// the following signature is "LSal"
#define LDAP_SASL_SIGNATURE 0x6c61534c
// the following signature is "LThd"
#define LDAP_PER_THREAD_SIGNATURE 0x6c546864
//
// function declarations
//
PLDAP_CONN
GetConnectionPointer(
LDAP *ExternalHandle
);
PLDAP_CONN
GetConnectionPointer2(
LDAP *ExternalHandle
);
PLDAP_CONN
ReferenceLdapConnection(
PLDAP_CONN Connection
);
PLDAP_REQUEST
ReferenceLdapRequest(
PLDAP_REQUEST request
);
BOOL
LdapInitializeWinsock (
VOID
);
VOID
CloseLdapConnection (
PLDAP_CONN Connection
);
PLDAP_CONN
LdapAllocateConnection (
PWCHAR HostName,
ULONG PortNumber,
ULONG Secure,
BOOLEAN Udp
);
VOID
DereferenceLdapConnection2 (
PLDAP_CONN connection
);
LPVOID
ldapMalloc (
DWORD Bytes,
ULONG Tag
);
VOID
ldapFree (
LPVOID Block,
ULONG Tag
);
VOID
ldapSecureFree (
LPVOID Block,
ULONG Tag
);
BOOLEAN
ldapSwapTags (
LPVOID Block,
ULONG OldTag,
ULONG NewTag
);
VOID
ldap_MoveMemory (
PCHAR dest,
PCHAR source,
ULONG length
);
PLDAP_REQUEST LdapCreateRequest (
PLDAP_CONN Connection,
UCHAR Operation
);
VOID
DereferenceLdapRequest2 (
PLDAP_REQUEST Request
);
PLDAP_RECVBUFFER
LdapGetReceiveStructure (
DWORD cbBuffer
);
VOID
LdapFreeReceiveStructure (
IN PLDAP_RECVBUFFER ReceiveBuffer,
IN BOOLEAN HaveLock
);
PLDAP_MESSAGEWAIT
LdapGetMessageWaitStructure (
IN PLDAP_CONN Connection,
IN ULONG CompleteMessages,
IN ULONG MessageNumber,
IN BOOLEAN PendingSendOnly
);
VOID
LdapFreeMessageWaitStructure (
PLDAP_MESSAGEWAIT Message
);
VOID
CloseLdapRequest (
PLDAP_REQUEST Request
);
PLDAP_REQUEST
FindLdapRequest(
LONG MessageId
);
PCHAR
ldap_dup_string (
PCHAR String,
ULONG Extra,
ULONG Tag
);
PWCHAR
ldap_dup_stringW (
PWCHAR String,
ULONG Extra,
ULONG Tag
);
ULONG
add_string_to_list (
PWCHAR **ArrayToReturn,
ULONG *ArraySize,
PWCHAR StringToAdd,
BOOLEAN CreateCopy
);
VOID
SetConnectionError (
PLDAP_CONN Connection,
ULONG LdapError,
PCHAR DNNameInError
);
ULONG
HandleReferrals (
PLDAP_CONN Connection,
PLDAPMessage *FirstSearchEntry,
PLDAP_REQUEST Request
);
ULONG
LdapSendCommand (
PLDAP_CONN Connection,
PLDAP_REQUEST Request,
USHORT ReferralNumber
);
ULONG
LdapBind (
PLDAP_CONN connection,
PWCHAR BindDistName,
ULONG Method,
PWCHAR BindCred,
BOOLEAN Synchronous
);
BOOLEAN
LdapInitSecurity (
VOID
);
BOOLEAN
LdapInitSsl (
VOID
);
BOOLEAN
CheckForNullCredentials (
PLDAP_CONN Connection
);
VOID
CloseCredentials (
PLDAP_CONN Connection
);
VOID
SetNullCredentials (
PLDAP_CONN Connection
);
ULONG
LdapConvertSecurityError (
PLDAP_CONN Connection,
SECURITY_STATUS sErr
);
ULONG
LdapSspiBind (
PLDAP_CONN Connection,
PSecPkgInfoW Package,
ULONG UserMethod,
ULONG SspiFlags,
PWCHAR UserName,
PWCHAR TargetName,
PWCHAR Credentials
);
ULONG
LdapGetSicilyPackageList(
PLDAP_CONN Connection,
PBYTE PackageList,
ULONG Length,
PULONG pResponseLen
);
VOID
LdapClearSspiState(
PLDAP_CONN Connection
);
ULONG
LdapSetSspiContinueState(
PLDAP_CONN Connection,
SECURITY_STATUS sErr
);
ULONG
LdapExchangeOpaqueToken(
PLDAP_CONN Connection,
ULONG UserMethod,
PWCHAR MethodOID,
PWCHAR UserName,
PVOID pOutboundToken,
ULONG cbTokenLength,
SecBufferDesc *pInboundToken,
BERVAL **ServerCred,
PLDAPControlW *ServerControls,
PLDAPControlW *ClientControls,
PULONG MessageNumber,
BOOLEAN SendOnly,
BOOLEAN Unicode,
BOOLEAN * pSentMessage
);
ULONG
LdapTryAllMsnAuthentication(
PLDAP_CONN Connection,
PWCHAR BindCred
);
ULONG
LdapSetupSslSession (
PLDAP_CONN Connection
);
DWORD
LdapSendRaw (
IN PLDAP_CONN Connection,
PCHAR Data,
ULONG DataCount
);
DWORD
GetDefaultLdapServer(
PWCHAR DomainName,
LPWSTR Addresses[],
LPWSTR DnsHostNames[],
LPWSTR MemberDomains[],
LPDWORD Count,
ULONG DsFlags,
BOOLEAN *SameSite,
USHORT PortNumber,
ULONG *pResolvedDsFlags
);
DWORD
InitLdapServerFromDomain(
LPCWSTR DomainName,
ULONG Flags,
OUT HANDLE *Handle,
LPWSTR *Site
);
DWORD
NextLdapServerFromDomain(
HANDLE Handle,
LPSOCKET_ADDRESS *lpSockAddresses,
PWCHAR *DnsHostName,
PULONG SocketCount
);
DWORD
CloseLdapServerFromDomain(
HANDLE Handle,
LPWSTR Site
);
ULONG
ParseLdapToken (
PWCHAR CurrentPosition,
PWCHAR *StartOfToken,
PWCHAR *EqualSign,
PWCHAR *EndOfToken
);
ULONG
FromUnicodeWithAlloc (
PWCHAR Source,
PCHAR *Output,
ULONG Tag,
ULONG CodePage
);
ULONG
ToUnicodeWithAlloc (
PCHAR Source,
LONG SourceLength,
PWCHAR *Output,
ULONG Tag,
ULONG CodePage
);
ULONG
strlenW(
PWCHAR string
);
BOOLEAN
ldapWStringsIdentical (
PWCHAR string1,
LONG length1,
PWCHAR string2,
LONG length2
);
ULONG
DrainPendingCryptoStream (
PLDAP_CONN Connection
);
ULONG
LdapDupLDAPModStructure (
LDAPModW *AttributeList[],
BOOLEAN Unicode,
LDAPModW **OutputList[]
);
VOID
LdapFreeLDAPModStructure (
PLDAPModW *AttrList,
BOOLEAN Unicode
);
ULONG
AddToPendingList (
PLDAP_REQUEST Request,
PLDAP_CONN Connection
);
VOID
DecrementPendingList (
PLDAP_REQUEST Request,
PLDAP_CONN Connection
);
VOID
ClearPendingListForRequest (
PLDAP_REQUEST Request
);
VOID
ClearPendingListForConnection (
PLDAP_CONN Connection
);
ULONG
LdapCheckControls (
PLDAP_REQUEST Request,
PLDAPControlW *ServerControls,
PLDAPControlW *ClientControls,
BOOLEAN Unicode,
ULONG ExtraSlots
);
VOID
FreeLdapControl(
PLDAPControlW *Controls
);
BOOLEAN
LdapCheckForMandatoryControl (
PLDAPControlW *Controls
);
ULONG
ldap_result_with_error (
PLDAP_CONN Connection,
ULONG msgid,
ULONG AllOfMessage,
struct l_timeval *TimeOut,
LDAPMessage **res,
LDAPMessage **LastResult
);
ULONG
FreeCurrentCredentials (
PLDAP_CONN Connection
);
ULONG
LdapSaveSearchParameters (
PLDAP_REQUEST Request,
PWCHAR DistinguishedName,
PWCHAR SearchFilter,
PWCHAR AttributeList[],
BOOLEAN Unicode
);
ULONG
LdapSearch (
PLDAP_CONN connection,
PWCHAR DistinguishedName,
ULONG ScopeOfSearch,
PWCHAR SearchFilter,
PWCHAR AttributeList[],
ULONG AttributesOnly,
BOOLEAN Unicode,
BOOLEAN Synchronous,
PLDAPControlW *ServerControls,
PLDAPControlW *ClientControls,
ULONG TimeLimit,
ULONG SizeLimit,
ULONG *MessageNumber
);
ULONG
LdapAbandon (
PLDAP_CONN connection,
ULONG msgid,
BOOLEAN SendAbandon
);
PLDAPMessage
ldap_first_record (
PLDAP_CONN connection,
LDAPMessage *Results,
ULONG MessageType
);
PLDAPMessage
ldap_next_record (
PLDAP_CONN connection,
LDAPMessage *Results,
ULONG MessageType
);
ULONG
ldap_count_records (
PLDAP_CONN connection,
LDAPMessage *Results,
ULONG MessageType
);
VOID
GetCurrentLuid (
PLUID Luid
);
ULONG
LdapMakeCredsWide(
PCHAR pAnsiAuthIdent,
PCHAR *ppWideAuthIdent,
BOOLEAN FromWide
);
ULONG
LdapMakeCredsThin(
PCHAR pAnsiAuthIdent,
PCHAR *ppWideAuthIdent,
BOOLEAN FromWide
);
ULONG
LdapMakeEXCredsWide(
PCHAR pAnsiAuthIdentEX,
PCHAR *ppWideAuthIdentEX,
BOOLEAN FromWide
);
ULONG
LdapMakeEXCredsThin(
PCHAR pAnsiAuthIdentEX,
PCHAR *ppWideAuthIdentEX,
BOOLEAN FromWide
);
BOOLEAN
LdapAuthError(
ULONG err
);
ULONG
LdapPingServer(
PLDAP_CONN Connection
);
VOID
UnloadPingLibrary(
VOID
);
VOID
LdapWakeupSelect (
VOID
);
VOID
CheckForWaiters (
ULONG MessageNumber,
BOOLEAN AnyWaiter,
PLDAP_CONN Connection
);
ULONG
LdapEncodeSortControl (
PLDAP_CONN connection,
PLDAPSortKeyW *SortKeys,
PLDAPControlW Control,
BOOLEAN Criticality,
ULONG codePage
);
ULONG
LdapParseResult (
PLDAP_CONN connection,
LDAPMessage *ResultMessage,
ULONG *ReturnCode OPTIONAL, // returned by server
PWCHAR *MatchedDNs OPTIONAL, // free with ldap_value_freeW
PWCHAR *ErrorMessage OPTIONAL, // free with ldap_value_freeW
PWCHAR **Referrals OPTIONAL, // free with ldap_value_freeW
PLDAPControlW **ServerControls OPTIONAL,
BOOLEAN Freeit,
ULONG codePage
);
ULONG LdapParseExtendedResult (
PLDAP_CONN connection,
LDAPMessage *ResultMessage,
PWCHAR *ResultOID,
struct berval **ResultData,
BOOLEAN Freeit,
ULONG codePage
);
ULONG
LdapAutoReconnect (
PLDAP_CONN Connection
);
ULONG
SimulateErrorMessage (
PLDAP_CONN Connection,
PLDAP_REQUEST Request,
ULONG Error
);
ULONG
LdapConnect (
PLDAP_CONN connection,
struct l_timeval *timeout,
BOOLEAN DontWait
);
ULONG
ProcessAlternateCreds (
PLDAP_CONN Connection,
PSecPkgInfoW Package,
PWCHAR Credentials,
PWCHAR *newcreds
);
BOOLEAN
LdapIsAddressNumeric (
PWCHAR HostName
);
ULONG
LdapDetermineServerVersion (
PLDAP_CONN Connection,
struct l_timeval *Timeout,
BOOLEAN *pfIsServerWhistler // OUT
);
BOOLEAN LoadUser32Now(
VOID
);
ULONG
ConnectToSRVrecs(
PLDAP_CONN Connection,
PWCHAR HostName,
BOOLEAN SuggestedHost,
USHORT port,
struct l_timeval *timeout
);
ULONG
ConnectToArecs(
PLDAP_CONN Connection,
struct hostent *hostEntry,
BOOLEAN SuggestedHost,
USHORT port,
struct l_timeval *timeout
);
ULONG
LdapParallelConnect(
PLDAP_CONN Connection,
PSOCKHOLDER2 *sockAddressArr,
USHORT port,
UINT totalCount,
struct l_timeval *timeout
);
VOID
InsertErrorMessage(
PLDAP_CONN Connection,
PWCHAR ErrorMessage
);
PVOID
GetErrorMessage(
PLDAP_CONN Connection,
BOOLEAN Unicode
);
BOOL
AddPerThreadEntry(
DWORD ThreadID
);
BOOL
RemovePerThreadEntry(
DWORD ThreadID
);
VOID
RoundUnicodeStringMaxLength(
UNICODE_STRING *pString,
USHORT dwMultiple
);
VOID
EncodeUnicodeString(
UNICODE_STRING *pString
);
VOID
DecodeUnicodeString(
UNICODE_STRING *pString
);
HMODULE
LoadSystem32LibraryA(
PCHAR lpFileName
);
BOOLEAN
IsMessageIdValid(
LONG MessageId
);
PLDAPReferralDN
LdapParseReferralDN(
PWCHAR newDN
);
VOID
DebugReferralOutput(
PLDAP_REQUEST Request,
PWCHAR HostAddr,
PWCHAR NewUrlDN
);
VOID
DiscoverDebugRegKey(
VOID
);
DWORD
ReadRegIntegrityDefault(
DWORD *pdwIntegrity
);
#define DEFAULT_INTEGRITY_NONE 0
#define DEFAULT_INTEGRITY_PREFERRED 1
#define DEFAULT_INTEGRITY_REQUIRED 2
VOID
FreeEntireLdapCache(
VOID
);
VOID
InitializeLdapCache (
VOID
);
PWCHAR
LdapFirstAttribute (
PLDAP_CONN connection,
LDAPMessage *Message,
BerElement **OpaqueResults,
BOOLEAN Unicode
);
PWCHAR
LdapNextAttribute (
PLDAP_CONN connection,
LDAPMessage *Message,
BerElement *OpaqueResults,
BOOLEAN Unicode
);
ULONG
LdapGetValues (
PLDAP_CONN connection,
LDAPMessage *Message,
PWCHAR attr,
BOOLEAN BerVal,
BOOLEAN Unicode,
PVOID *Output
);
ULONG LdapGetConnectionOption (
PLDAP_CONN connection,
int option,
void *outvalue,
BOOLEAN Unicode
);
ULONG LdapSetConnectionOption (
PLDAP_CONN connection,
int option,
const void *invalue,
BOOLEAN Unicode
);
ULONG LDAPAPI LdapGetPagedCount(
PLDAP_CONN connection,
PLDAP_REQUEST request,
ULONG *TotalCount,
PLDAPMessage Results
);
ULONGLONG
LdapGetTickCount(
VOID
);
ULONG
LdapGetModuleBuildNum(
VOID
);
//
// Here's the function declarations for dynamically loading winsock
//
// We dynamically load winsock so that we can either load winsock 1.1 or 2.0,
// and the functions we pull in depend on what version we're going to use.
//
typedef int (PASCAL FAR *FNWSAFDISSET)(SOCKET, fd_set FAR *);
extern LPFN_WSASTARTUP pWSAStartup;
extern LPFN_WSACLEANUP pWSACleanup;
extern LPFN_WSAGETLASTERROR pWSAGetLastError;
extern LPFN_RECV precv;
extern LPFN_SELECT pselect;
extern LPFN_WSARECV pWSARecv;
extern LPFN_SOCKET psocket;
extern LPFN_CONNECT pconnect;
extern LPFN_GETHOSTBYNAME pgethostbyname;
extern LPFN_GETHOSTBYADDR pgethostbyaddr;
extern LPFN_INET_ADDR pinet_addr;
extern LPFN_INET_NTOA pinet_ntoa;
extern LPFN_HTONS phtons;
extern LPFN_HTONL phtonl;
extern LPFN_NTOHL pntohl;
extern LPFN_CLOSESOCKET pclosesocket;
extern LPFN_SEND psend;
extern LPFN_IOCTLSOCKET pioctlsocket;
extern LPFN_SETSOCKOPT psetsockopt;
extern FNWSAFDISSET pwsafdisset;
extern LPFN_WSALOOKUPSERVICEBEGINW pWSALookupServiceBeginW;
extern LPFN_WSALOOKUPSERVICENEXTW pWSALookupServiceNextW;
extern LPFN_WSALOOKUPSERVICEEND pWSALookupServiceEnd;
//
// Function declarations for loading NTDS APIs
//
typedef DWORD (*FNDSMAKESPNW) (
LPWSTR ServiceClass,
LPWSTR ServiceName,
LPWSTR InstanceName,
USHORT InstancePort,
LPWSTR Referrer,
DWORD *pcSpnLength,
LPWSTR pszSpn
);
extern FNDSMAKESPNW pDsMakeSpnW;
//
// Function declarations for loading Rtl APIs
//
typedef VOID (*FNRTLINITUNICODESTRING) (
PUNICODE_STRING DestinationString,
PCWSTR SourceString
);
extern FNRTLINITUNICODESTRING pRtlInitUnicodeString;
typedef VOID (*FRTLRUNENCODEUNICODESTRING) (
PUCHAR Seed,
PUNICODE_STRING String
);
extern FRTLRUNENCODEUNICODESTRING pRtlRunEncodeUnicodeString;
typedef VOID (*FRTLRUNDECODEUNICODESTRING) (
UCHAR Seed,
PUNICODE_STRING String
);
extern FRTLRUNDECODEUNICODESTRING pRtlRunDecodeUnicodeString;
typedef NTSTATUS (*FRTLENCRYPTMEMORY) (
PVOID Memory,
ULONG MemoryLength,
ULONG OptionFlags
);
extern FRTLENCRYPTMEMORY pRtlEncryptMemory;
typedef NTSTATUS (*FRTLDECRYPTMEMORY) (
PVOID Memory,
ULONG MemoryLength,
ULONG OptionFlags
);
extern FRTLDECRYPTMEMORY pRtlDecryptMemory;
//
// Function declarations for loading USER32 APIs
//
typedef int (*FNLOADSTRINGA) (
IN HINSTANCE hInstance,
IN UINT uID,
OUT LPSTR lpBuffer,
IN int nBufferMax
);
extern FNLOADSTRINGA pfLoadStringA;
typedef int (*FNWSPRINTFW) (
OUT LPWSTR,
IN LPCWSTR,
...);
extern FNWSPRINTFW pfwsprintfW;
typedef int (*FNMESAGEBOXW) (
IN HWND hWnd,
IN LPCWSTR lpText,
IN LPCWSTR lpCaption,
IN UINT uType
);
extern FNMESAGEBOXW pfMessageBoxW;
//
// Function declarations for loading SECUR32 APIs
//
typedef BOOL (WINAPI *FGETTOKENINFORMATION) (
HANDLE TokenHandle,
TOKEN_INFORMATION_CLASS TokenInformationClass,
LPVOID TokenInformation,
DWORD TokenInformationLength,
PDWORD ReturnLength
);
typedef BOOL (WINAPI *FOPENPROCESSTOKEN) (
HANDLE ProcessHandle,
DWORD DesiredAccess,
PHANDLE TokenHandle
);
typedef BOOL (WINAPI *FOPENTHREADTOKEN) (
HANDLE ThreadHandle,
DWORD DesiredAccess,
BOOL OpenAsSelf,
PHANDLE TokenHandle
);
typedef SECURITY_STATUS (SEC_ENTRY *FSASLGETPROFILEPACKAGEW) (
IN LPWSTR ProfileName,
OUT PSecPkgInfoW * PackageInfo
);
extern FSASLGETPROFILEPACKAGEW pSaslGetProfilePackageW;
typedef SECURITY_STATUS (SEC_ENTRY *FSASLINITIALIZESECURITYCONTEXTW) (
PCredHandle phCredential,
PCtxtHandle phContext,
LPWSTR pszTargetName,
unsigned long fContextReq,
unsigned long Reserved1,
unsigned long TargetDataRep,
PSecBufferDesc pInput,
unsigned long Reserved2,
PCtxtHandle phNewContext,
PSecBufferDesc pOutput,
unsigned long SEC_FAR * pfContextAttr,
PTimeStamp ptsExpiry
);
extern FSASLINITIALIZESECURITYCONTEXTW pSaslInitializeSecurityContextW;
typedef SECURITY_STATUS (SEC_ENTRY *FQUERYCONTEXTATTRIBUTESW) (
PCtxtHandle phContext, // Context to query
unsigned long ulAttribute, // Attribute to query
void SEC_FAR * pBuffer // Buffer for attributes
);
extern FQUERYCONTEXTATTRIBUTESW pQueryContextAttributesW;
typedef PSecurityFunctionTableW (*FSECINITSECURITYINTERFACEW)( VOID );
typedef PSecurityFunctionTableA (*FSECINITSECURITYINTERFACEA)( VOID );
extern FSECINITSECURITYINTERFACEW pSspiInitialize;
extern FSECINITSECURITYINTERFACEW pSslInitialize;
PSecurityFunctionTableW Win9xSspiInitialize();
PSecurityFunctionTableW Win9xSslInitialize();
//
// Macros that let us call Unicode version in NT and Ansi version in Win9x
//
#define LdapSspiInitialize() (GlobalWin9x ? Win9xSspiInitialize() : (*pSspiInitialize)())
#define LdapSslInitialize() (GlobalWin9x ? Win9xSslInitialize() : (*pSslInitialize)())
#endif // LDAP_CLIENT_INTERNAL_DEFINED
| 25.452514 | 120 | 0.661567 |
bf0960d79c4cd25e906fd67004cee59b90264307 | 2,318 | h | C | mindspore/lite/tools/optimizer/fusion/layer_norm_fusion.h | GuoSuiming/mindspore | 48afc4cfa53d970c0b20eedfb46e039db2a133d5 | [
"Apache-2.0"
] | 1 | 2021-01-28T11:08:20.000Z | 2021-01-28T11:08:20.000Z | mindspore/lite/tools/optimizer/fusion/layer_norm_fusion.h | GuoSuiming/mindspore | 48afc4cfa53d970c0b20eedfb46e039db2a133d5 | [
"Apache-2.0"
] | null | null | null | mindspore/lite/tools/optimizer/fusion/layer_norm_fusion.h | GuoSuiming/mindspore | 48afc4cfa53d970c0b20eedfb46e039db2a133d5 | [
"Apache-2.0"
] | null | null | null | /**
* Copyright 2020 Huawei Technologies Co., Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MINDSPORE_LITE_TOOLS_OPTIMIZER_FUSION_LAYER_NORM_FUSION_H_
#define MINDSPORE_LITE_TOOLS_OPTIMIZER_FUSION_LAYER_NORM_FUSION_H_
#include <vector>
#include <memory>
#include <string>
#include "backend/optimizer/common/optimizer.h"
#include "utils/utils.h"
namespace mindspore {
namespace opt {
class LayerNormFusion : public PatternProcessPass {
public:
explicit LayerNormFusion(const std::string &name = "layer_norm_fusion", bool multigraph = true)
: PatternProcessPass(name, multigraph) {
input_ = std::make_shared<Var>();
mean1_ = std::make_shared<Var>();
mean2_ = std::make_shared<Var>();
gamma_ = std::make_shared<Var>();
beta_ = std::make_shared<Var>();
epsilon_ = std::make_shared<Var>();
}
~LayerNormFusion() override = default;
const BaseRef DefinePattern() const override;
const AnfNodePtr Process(const FuncGraphPtr &, const AnfNodePtr &, const EquivPtr &) const override;
private:
bool GetAxis(const CNodePtr &input_cnode, const std::vector<int> &mean_axes, const std::vector<int> ¶ms_shape,
int *begin_norm_axis, int *begin_params_axis) const;
bool CheckPattern(const EquivPtr &equiv, float *epsilon, int *begin_norm_axis, int *begin_params_axis) const;
CNodePtr CreateLayerNormNode(const FuncGraphPtr &func_graph, const EquivPtr &equiv, float epsilon,
int begin_norm_axis, int begin_params_axis) const;
VarPtr input_ = nullptr;
VarPtr mean1_ = nullptr;
VarPtr mean2_ = nullptr;
VarPtr gamma_ = nullptr;
VarPtr beta_ = nullptr;
VarPtr epsilon_ = nullptr;
};
} // namespace opt
} // namespace mindspore
#endif // MINDSPORE_LITE_TOOLS_OPTIMIZER_FUSION_LAYER_NORM_FUSION_H_
| 37.387097 | 116 | 0.739862 |
bf5950a20d7ccb4ee6fabebbd080fda2173412f1 | 990 | h | C | build/3dparty/taglib/config.h | dmushynska/utag | 41c26250199d7b62ed2d91d07fb61568dbd81d10 | [
"MIT"
] | null | null | null | build/3dparty/taglib/config.h | dmushynska/utag | 41c26250199d7b62ed2d91d07fb61568dbd81d10 | [
"MIT"
] | null | null | null | build/3dparty/taglib/config.h | dmushynska/utag | 41c26250199d7b62ed2d91d07fb61568dbd81d10 | [
"MIT"
] | null | null | null | /* config.h. Generated by cmake from config.h.cmake */
#ifndef TAGLIB_CONFIG_H
#define TAGLIB_CONFIG_H
/* Defined if your compiler supports some byte swap functions */
#define HAVE_GCC_BYTESWAP 1
/* #undef HAVE_GLIBC_BYTESWAP */
/* #undef HAVE_MSC_BYTESWAP */
/* #undef HAVE_MAC_BYTESWAP */
/* #undef HAVE_OPENBSD_BYTESWAP */
/* Defined if your compiler supports some atomic operations */
#define HAVE_STD_ATOMIC 1
/* #undef HAVE_GCC_ATOMIC */
/* #undef HAVE_MAC_ATOMIC */
/* #undef HAVE_WIN_ATOMIC */
/* #undef HAVE_IA64_ATOMIC */
/* Defined if your compiler supports some safer version of vsprintf */
#define HAVE_VSNPRINTF 1
/* #undef HAVE_VSPRINTF_S */
/* Defined if your compiler supports ISO _strdup */
/* #undef HAVE_ISO_STRDUP */
/* Defined if zlib is installed */
#define HAVE_ZLIB 1
/* Indicates whether debug messages are shown even in release mode */
/* #undef TRACE_IN_RELEASE */
#define TESTS_DIR "/Users/dmushynska/Desktop/utag/3dparty/taglib/tests/"
#endif
| 27.5 | 72 | 0.742424 |
c7f0505010cd1d4c8b5faf26a78d073ce8b8d07e | 129 | h | C | Vendor/PhysX/include/PhysX/cooking/PxMidphaseDesc.h | wdrDarx/DEngine3 | 27e2de3b56b6d4c8705e8a0e36f5911d8651caa2 | [
"MIT"
] | 2 | 2022-01-11T21:15:31.000Z | 2022-02-22T21:14:33.000Z | Vendor/PhysX/include/PhysX/cooking/PxMidphaseDesc.h | wdrDarx/DEngine3 | 27e2de3b56b6d4c8705e8a0e36f5911d8651caa2 | [
"MIT"
] | null | null | null | Vendor/PhysX/include/PhysX/cooking/PxMidphaseDesc.h | wdrDarx/DEngine3 | 27e2de3b56b6d4c8705e8a0e36f5911d8651caa2 | [
"MIT"
] | null | null | null | version https://git-lfs.github.com/spec/v1
oid sha256:635cebc896ba513a02ccae6e5f65aae28f5e43e275eeef6d17a5254e89390e7e
size 3618
| 32.25 | 75 | 0.883721 |
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