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ERROR: type should be string, got "https://github.com/zlib-ng/zlib-ng/commit/43dbfd6709fb3a8028430ea30f3da88fbeb3ced9 breaks adler32_neon support for Android arm target\n\n\nTombstones here\n\nBuild fingerprint: 'Redmi/picasso/picasso:11/RKQ1.200826.002/V12.5.2.0.RGICNXM:user/release-keys'\nRevision: '0'\nABI: 'arm'\nTimestamp: 2022-09-11 12:08:04.763957964+0800\nProcess uptime: 2s\nCmdline: zygote\npid: 2028, tid: 2028, name: main >>> zygote <<<\nuid: 0\nsignal 7 (SIGBUS), code 1 (BUS_ADRALN), fault addr 0xe4e5adb0\nr0 e4e5adb0 r1 e87f1098 r2 00006550 r3 00000000\nr4 00000000 r5 00000056 r6 00000000 r7 e87f2640\nr8 00000000 r9 0000fff1 r10 00000008 r11 000015a8\nip 00000008 sp ff89e7f0 lr ff89e828 pc e4e67f64\nbacktrace:\n#00 pc 00011f64 /system/lib/libz.so (adler32_neon+320) (BuildId: 29a5b7ef6252f153585ea0cb10ea7021)\n#01 pc 000171c7 /apex/com.android.art/lib/libdexfile.so (art::DexFile::CalculateChecksum() const+24) (BuildId: 8fb71c781ff03cc731e29bdfeae0c86f)\n#02 pc 0001dd5d /apex/com.android.art/lib/libdexfile.so (art::dex::DexFileVerifier::CheckHeader()+36) (BuildId: 8fb71c781ff03cc731e29bdfeae0c86f)\n#03 pc 00024b7f /apex/com.android.art/lib/libdexfile.so (art::dex::DexFileVerifier::Verify()+18) (BuildId: 8fb71c781ff03cc731e29bdfeae0c86f)\n#04 pc 000251dd /apex/com.android.art/lib/libdexfile.so (art::dex::Verify(art::DexFile const*, unsigned char const*, unsigned int, char const*, bool, std::__1::basic_string<char, std::__1::char_traits, std::__1::allocator >)+140) (BuildId: 8fb71c781ff03cc731e29bdfeae0c86f)\n#05 pc 0001b227 /apex/com.android.art/lib/libdexfile.so (art::DexFileLoader::OpenCommon(unsigned char const, unsigned int, unsigned char const*, unsigned int, std::__1::basic_string<char, std::__1::char_traits, std::__1::allocator > const&, unsigned int, art::OatDexFile const*, bool, bool, std::__1::basic_string<char, std::__1::char_traits, std::__1::allocator >, std::__1::unique_ptr<art::DexFileContainer, std::__1::default_deleteart::DexFileContainer >, art::DexFileLoader::VerifyResult)+198) (BuildId: 8fb71c781ff03cc731e29bdfeae0c86f)\n#06 pc 00014bc9 /apex/com.android.art/lib/libdexfile.so (art::ArtDexFileLoader::OpenOneDexFileFromZip(art::ZipArchive const&, char const*, std::__1::basic_string<char, std::__1::char_traits, std::__1::allocator > const&, bool, bool, std::__1::basic_string<char, std::__1::char_traits, std::__1::allocator >, art::DexFileLoaderErrorCode) const+708) (BuildId: 8fb71c781ff03cc731e29bdfeae0c86f)\n#07 pc 0001464b /apex/com.android.art/lib/libdexfile.so (art::ArtDexFileLoader::OpenAllDexFilesFromZip(art::ZipArchive const&, std::__1::basic_string<char, std::__1::char_traits, std::__1::allocator > const&, bool, bool, std::__1::basic_string<char, std::__1::char_traits, std::__1::allocator >, std::__1::vector<std::__1::unique_ptr<art::DexFile const, std::__1::default_delete<art::DexFile const> >, std::__1::allocator<std::__1::unique_ptr<art::DexFile const, std::__1::default_delete<art::DexFile const> > > >) const+142) (BuildId: 8fb71c781ff03cc731e29bdfeae0c86f)\nMeanwhile i find that partially revert that commit: See https://github.com/AcmeUI/android_external_zlib-ng/commit/9c79620f2e145861e58146e7ca7134969f9b9e18 does help\n\n\nThis seems alignment-related issue. @KungFuJesus\n\n\nWhere are you seeing alignment issues? Arm has no such alignment requirement but even so the neon implementation of adler32 does scalar sums until it's aligned to 16 bytes for the loads.\n\n\nWhat instruction is 0x320 bytes into the adler32_neon function? It'd be good to know which load is causing your issues. As far as I can tell though everything should be properly aligned to their proper types, including the bytes being summed (despite that not actually being a requirement).\n\n\nAlso interesting is that the address it's faulting on modulo 16 is zero. That means that even widest possible load would be a naturally aligned one. This sigbus makes no sense. Usually you see sigbus on arm by violating natural alignment for scalar types. All of the scalar arguments here are not doing any sort of aliasing with pointers.\n\n\n@asuka-mio is this reproducible with a debug build? Might it be possible to at least provide a core dump for some post mortem? On paper it seems like this shouldn't be happening unless maybe something lied about the length of a buffer somewhere and nothing verified it.\n\n\n\n@asuka-mio is this reproducible with a debug build? Might it be possible to at least provide a core dump for some post mortem? On paper it seems like this shouldn't be happening unless maybe something lied about the length of a buffer somewhere and nothing verified it.\n\nYes, we can reproduce it just through download the newest android ndk\nCC=$NDK/toolchains/llvm/prebuilt/linux-x86_64/bin/armv7a-linux-androideabi33-clang ./configure --zlib-compat\nmake\nAnd ship the libz to device\ncompile a short test:\n#include <stddef.h>\n#include <sys/types.h>\n#include <zlib.h>\n#include <stdlib.h>\nint main()\n{\nsize_t len = 8192;\nvoid* buffer = malloc(len);\nu_int32_t adler = adler32(0L, Z_NULL, 0);\nu_int32_t aadler = adler32(adler, buffer, len);\nfree(buffer);\nreturn 0;\n}\nThen compile it $NDK/toolchains/llvm/prebuilt/linux-x86_64/bin/armv7a-linux-androideabi33-clang source.c -lz and ship it to device\nIf we just execute it with normal libz, then nothing happen\nBut we use LD_PRELOAD=/path/to/shiped/libz , a SIGBUS will trigger\nAnd with this patch applied https://github.com/AcmeUI/android_external_zlib-ng/commit/9c79620f2e145861e58146e7ca7134969f9b9e18 it works well too\n\n\n\n@asuka-mio is this reproducible with a debug build? Might it be possible to at least provide a core dump for some post mortem? On paper it seems like this shouldn't be happening unless maybe something lied about the length of a buffer somewhere and nothing verified it.\nAnd certainly, coredump here\ncore.txt\nI rename the extension to upload via github webpage\n\n\n\n@KungFuJesus Any idea about resolving it?\n\n\nAny way you can get me the final binary as well? I should be able to attach the coredump in gdb and inspect the state of your heap and stack at the time of the SIGBUS to see which load is causing your SIGBUS.\nFWIW here's your test binary compiled on an aarch64 with Linux:\n[adam@odroid ~]$ gcc -O3 -march=native test.c ~/zlib-ng-install/lib/libz.a -o test.out\n[adam@odroid ~]$ ./test.out \n[adam@odroid ~]$ echo $?\n0\n\nIf it's that easy trigger your segfault though something else seems amiss. Zlib quite recently bumped their API for 1.2.12 and zlib-ng was modified to be compatible with it. Are you sure you're not LD_PRELOAD'ing over zlib 1.2.11?\n\n\n\nAny way you can get me the final binary as well? I should be able to attach the coredump in gdb and inspect the state of your heap and stack at the time of the SIGBUS to see which load is causing your SIGBUS.\nFWIW here's your test binary compiled on an aarch64 with Linux:\n[adam@odroid ~]$ gcc -O3 -march=native test.c ~/zlib-ng-install/lib/libz.a -o test.out\n[adam@odroid ~]$ ./test.out \n[adam@odroid ~]$ echo $?\n0\n\nIf it's that easy trigger your segfault though something else seems amiss. Zlib quite recently bumped their API for 1.2.12 and zlib-ng was modified to be compatible with it. Are you sure you're not LD_PRELOAD'ing over zlib 1.2.11?\nOne thing you can try is your example directly linked to zlib-ng. Does that crash?\n\nTest program crashs if and only if it access the adler32 function, directly linking it won't trigger that problem\nHere is binary files and coredump\nfiles.zip\n\n\nAnd I'm sure that something wrong in NEON_accum32 and that's what caused it\n\n\n\nAnd I'm sure that something wrong in NEON_accum32 and that's what caused it\n\nI tried simplify the problem\nTry another test\nfile1: adler32_p.h\n/* adler32_p.h -- Private inline functions and macros shared with\n\n\n different computation of the Adler-32 checksum\n\n\n\n of a data stream.\n\n\nCopyright (C) 1995-2011, 2016 Mark Adler\nFor conditions of distribution and use, see copyright notice in zlib.h\n*/\n\n#ifndef ADLER32_P_H\n#define ADLER32_P_H\n#define BASE 65521U /* largest prime smaller than 65536 /\n#define NMAX 5552\n/ NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */\n#define DO1(sum1, sum2, buf, i) {(sum1) += buf[(i)]; (sum2) += (sum1);}\n#define DO2(sum1, sum2, buf, i) {DO1(sum1, sum2, buf, i); DO1(sum1, sum2, buf, i+1);}\n#define DO4(sum1, sum2, buf, i) {DO2(sum1, sum2, buf, i); DO2(sum1, sum2, buf, i+2);}\n#define DO8(sum1, sum2, buf, i) {DO4(sum1, sum2, buf, i); DO4(sum1, sum2, buf, i+4);}\n#define DO16(sum1, sum2, buf) {DO8(sum1, sum2, buf, 0); DO8(sum1, sum2, buf, 8);}\nstatic inline uint32_t adler32_len_1(uint32_t adler, const uint8_t *buf, uint32_t sum2) {\nadler += buf[0];\nadler %= BASE;\nsum2 += adler;\nsum2 %= BASE;\nreturn adler | (sum2 << 16);\n}\nstatic inline uint32_t adler32_len_16(uint32_t adler, const uint8_t *buf, uint64_t len, uint32_t sum2) {\nwhile (len) {\n--len;\nadler += buf++;\nsum2 += adler;\n}\nadler %= BASE;\nsum2 %= BASE; / only added so many BASE's /\n/ return recombined sums */\nreturn adler | (sum2 << 16);\n}\nstatic inline uint32_t adler32_copy_len_16(uint32_t adler, const uint8_t *buf, uint8_t *dst, uint64_t len, uint32_t sum2) {\nwhile (len--) {\n*dst = *buf++;\nadler += dst++;\nsum2 += adler;\n}\nadler %= BASE;\nsum2 %= BASE; / only added so many BASE's /\n/ return recombined sums */\nreturn adler | (sum2 << 16);\n}\nstatic inline uint32_t adler32_len_64(uint32_t adler, const uint8_t buf, uint64_t len, uint32_t sum2) {\n#ifdef UNROLL_MORE\nwhile (len >= 16) {\nlen -= 16;\nDO16(adler, sum2, buf);\nbuf += 16;\n#else\nwhile (len >= 8) {\nlen -= 8;\nDO8(adler, sum2, buf, 0);\nbuf += 8;\n#endif\n}\n/ Process tail (len < 16). */\nreturn adler32_len_16(adler, buf, len, sum2);\n}\n#endif /* ADLER32_P_H */\n\nfile2 source.c:\n#include <stddef.h>\n#include <string.h>\n#include <stdlib.h>\n#include <stdint.h>\n#include <arm_neon.h>\n#include \"adler32_p.h\"\n#if defined(clang) || defined(GNUC)\ndefine ALIGNED_(x) attribute ((aligned(x)))\n#elif defined(_MSC_VER)\ndefine ALIGNED_(x) __declspec(align(x))\n#endif\n/* Minimum of a and b. /\n#define MIN(a, b) ((a) > (b) ? (b) : (a))\n/ Maximum of a and b. */\n#define MAX(a, b) ((a) < (b) ? (b) : (a))\n#define vmull_high_u8(a, b) vmull_u8(vget_high_u8(a), vget_high_u8(b))\n#define vmlal_high_u8(a, b, c) vmlal_u8(a, vget_high_u8(b), vget_high_u8(c))\n#define vmlal_high_u16(a, b, c) vmlal_u16(a, vget_high_u16(b), vget_high_u16(c))\n#define vaddw_high_u8(a, b) vaddw_u8(a, vget_high_u8(b))\nstatic void NEON_accum32(uint32_t *s, const uint8_t *buf, uint64_t len) {\nstatic const uint16_t ALIGNED_(16) taps[64] = {\n64, 63, 62, 61, 60, 59, 58, 57,\n56, 55, 54, 53, 52, 51, 50, 49,\n48, 47, 46, 45, 44, 43, 42, 41,\n40, 39, 38, 37, 36, 35, 34, 33,\n32, 31, 30, 29, 28, 27, 26, 25,\n24, 23, 22, 21, 20, 19, 18, 17,\n16, 15, 14, 13, 12, 11, 10, 9,\n8, 7, 6, 5, 4, 3, 2, 1 };\nuint32x4_t adacc = vdupq_n_u32(0);\nuint32x4_t s2acc = vdupq_n_u32(0);\nuint32x4_t s2acc_0 = vdupq_n_u32(0);\nuint32x4_t s2acc_1 = vdupq_n_u32(0);\nuint32x4_t s2acc_2 = vdupq_n_u32(0);\n\nadacc = vsetq_lane_u32(s[0], adacc, 0);\ns2acc = vsetq_lane_u32(s[1], s2acc, 0);\n\nuint32x4_t s3acc = vdupq_n_u32(0);\nuint32x4_t adacc_prev = adacc;\n\nuint16x8_t s2_0, s2_1, s2_2, s2_3;\ns2_0 = s2_1 = s2_2 = s2_3 = vdupq_n_u16(0);\n\nuint16x8_t s2_4, s2_5, s2_6, s2_7;\ns2_4 = s2_5 = s2_6 = s2_7 = vdupq_n_u16(0);\n\nuint64_t num_iter = len >> 2;\nint rem = len & 3;\n\nfor (uint64_t i = 0; i < num_iter; ++i) {\n uint8x16x4_t d0_d3 = vld1q_u8_x4(buf);\n\n /* Unfortunately it doesn't look like there's a direct sum 8 bit to 32\n * bit instruction, we'll have to make due summing to 16 bits first */\n uint16x8x2_t hsum, hsum_fold;\n hsum.val[0] = vpaddlq_u8(d0_d3.val[0]);\n hsum.val[1] = vpaddlq_u8(d0_d3.val[1]);\n\n hsum_fold.val[0] = vpadalq_u8(hsum.val[0], d0_d3.val[2]);\n hsum_fold.val[1] = vpadalq_u8(hsum.val[1], d0_d3.val[3]);\n\n adacc = vpadalq_u16(adacc, hsum_fold.val[0]);\n s3acc = vaddq_u32(s3acc, adacc_prev);\n adacc = vpadalq_u16(adacc, hsum_fold.val[1]);\n\n /* If we do straight widening additions to the 16 bit values, we don't incur\n * the usual penalties of a pairwise add. We can defer the multiplications\n * until the very end. These will not overflow because we are incurring at\n * most 408 loop iterations (NMAX / 64), and a given lane is only going to be\n * summed into once. This means for the maximum input size, the largest value\n * we will see is 255 * 102 = 26010, safely under uint16 max */\n s2_0 = vaddw_u8(s2_0, vget_low_u8(d0_d3.val[0]));\n s2_1 = vaddw_high_u8(s2_1, d0_d3.val[0]);\n s2_2 = vaddw_u8(s2_2, vget_low_u8(d0_d3.val[1]));\n s2_3 = vaddw_high_u8(s2_3, d0_d3.val[1]);\n s2_4 = vaddw_u8(s2_4, vget_low_u8(d0_d3.val[2]));\n s2_5 = vaddw_high_u8(s2_5, d0_d3.val[2]);\n s2_6 = vaddw_u8(s2_6, vget_low_u8(d0_d3.val[3]));\n s2_7 = vaddw_high_u8(s2_7, d0_d3.val[3]);\n\n adacc_prev = adacc;\n buf += 64;\n}\n\ns3acc = vshlq_n_u32(s3acc, 6);\n\nif (rem) {\n uint32x4_t s3acc_0 = vdupq_n_u32(0);\n while (rem--) {\n uint8x16_t d0 = vld1q_u8(buf);\n uint16x8_t adler;\n adler = vpaddlq_u8(d0);\n s2_6 = vaddw_u8(s2_6, vget_low_u8(d0));\n s2_7 = vaddw_high_u8(s2_7, d0);\n adacc = vpadalq_u16(adacc, adler);\n s3acc_0 = vaddq_u32(s3acc_0, adacc_prev);\n adacc_prev = adacc;\n buf += 16;\n }\n\n s3acc_0 = vshlq_n_u32(s3acc_0, 4);\n s3acc = vaddq_u32(s3acc_0, s3acc);\n}\n\nuint16x8x4_t t0_t3 = vld1q_u16_x4(taps);\nuint16x8x4_t t4_t7 = vld1q_u16_x4(taps + 32);\n\ns2acc = vmlal_high_u16(s2acc, t0_t3.val[0], s2_0);\ns2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t0_t3.val[0]), vget_low_u16(s2_0));\ns2acc_1 = vmlal_high_u16(s2acc_1, t0_t3.val[1], s2_1);\ns2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t0_t3.val[1]), vget_low_u16(s2_1));\n\ns2acc = vmlal_high_u16(s2acc, t0_t3.val[2], s2_2);\ns2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t0_t3.val[2]), vget_low_u16(s2_2));\ns2acc_1 = vmlal_high_u16(s2acc_1, t0_t3.val[3], s2_3);\ns2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t0_t3.val[3]), vget_low_u16(s2_3));\n\ns2acc = vmlal_high_u16(s2acc, t4_t7.val[0], s2_4);\ns2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t4_t7.val[0]), vget_low_u16(s2_4));\ns2acc_1 = vmlal_high_u16(s2acc_1, t4_t7.val[1], s2_5);\ns2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t4_t7.val[1]), vget_low_u16(s2_5));\n\ns2acc = vmlal_high_u16(s2acc, t4_t7.val[2], s2_6);\ns2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t4_t7.val[2]), vget_low_u16(s2_6));\ns2acc_1 = vmlal_high_u16(s2acc_1, t4_t7.val[3], s2_7);\ns2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t4_t7.val[3]), vget_low_u16(s2_7));\n\ns2acc = vaddq_u32(s2acc_0, s2acc);\ns2acc_2 = vaddq_u32(s2acc_1, s2acc_2);\ns2acc = vaddq_u32(s2acc, s2acc_2);\n\nuint32x2_t adacc2, s2acc2, as;\ns2acc = vaddq_u32(s2acc, s3acc);\nadacc2 = vpadd_u32(vget_low_u32(adacc), vget_high_u32(adacc));\ns2acc2 = vpadd_u32(vget_low_u32(s2acc), vget_high_u32(s2acc));\nas = vpadd_u32(adacc2, s2acc2);\ns[0] = vget_lane_u32(as, 0);\ns[1] = vget_lane_u32(as, 1);\n\n}\nstatic void NEON_handle_tail(uint32_t *pair, const uint8_t *buf, uint64_t len) {\nunsigned int i;\nfor (i = 0; i < len; ++i) {\npair[0] += buf[i];\npair[1] += pair[0];\n}\n}\nuint32_t adler32_neon(uint32_t adler, const uint8_t buf, uint64_t len) {\n/ split Adler-32 into component sums */\nuint32_t sum2 = (adler >> 16) & 0xffff;\nadler &= 0xffff;\n/* in case user likes doing a byte at a time, keep it fast */\nif (len == 1)\n return adler32_len_1(adler, buf, sum2);\n\n/* initial Adler-32 value (deferred check for len == 1 speed) */\nif (buf == NULL)\n return 1L;\n\n/* in case short lengths are provided, keep it somewhat fast */\nif (len < 16)\n return adler32_len_16(adler, buf, len, sum2);\n\nuint32_t pair[2];\nint n = NMAX;\nunsigned int done = 0;\n\n/* Split Adler-32 into component sums, it can be supplied by\n * the caller sites (e.g. in a PNG file).\n */\npair[0] = adler;\npair[1] = sum2;\n\n/* If memory is not SIMD aligned, do scalar sums to an aligned\n * offset, provided that doing so doesn't completely eliminate\n * SIMD operation. Aligned loads are still faster on ARM, even\n * though there's no explicit aligned load instruction */\nunsigned int align_offset = ((uintptr_t)buf & 15);\nunsigned int align_adj = (align_offset) ? 16 - align_offset : 0;\n\nif (align_offset && len >= (16 + align_adj)) {\n NEON_handle_tail(pair, buf, align_adj);\n n -= align_adj;\n done += align_adj;\n\n} else {\n /* If here, we failed the len criteria test, it wouldn't be\n * worthwhile to do scalar aligning sums */\n align_adj = 0;\n}\n\nwhile (done < len) {\n int remaining = (int)(len - done);\n n = MIN(remaining, (done == align_adj) ? n : NMAX);\n\n if (n < 16)\n break;\n\n NEON_accum32(pair, buf + done, n >> 4);\n pair[0] %= BASE;\n pair[1] %= BASE;\n\n int actual_nsums = (n >> 4) << 4;\n done += actual_nsums;\n}\n\n/* Handle the tail elements. */\nif (done < len) {\n NEON_handle_tail(pair, (buf + done), len - done);\n pair[0] %= BASE;\n pair[1] %= BASE;\n}\n\n/* D = B * 65536 + A, see: https://en.wikipedia.org/wiki/Adler-32. */\nreturn (pair[1] << 16) | pair[0];\n\n}\n#define adler32 adler32_neon\n#define Z_NULL NULL\nint main()\n{\nsize_t len = 8192;\nvoid* buffer = malloc(len);\nu_int32_t adler = adler32(0L, Z_NULL, 0);\nu_int32_t aadler = adler32(adler, buffer, len);\nfree(buffer);\nreturn 0;\n}\n\nCompile it directly: /opt/android-ndk/toolchains/llvm/prebuilt/linux-x86_64/bin/armv7a-linux-androideabi33-clang source.c\nShip it to device, execute it, crashed\n\n\nsource.zip\n\n\nIf it's not crashing with direct linking it seems very likely to not be an issue with the adler32 function itself but with an API incompatibility. It seems probable that the change in API is making the function resolution break in strange ways from the global descriptor table from the ELF binary.\nWe can probably confirm this if you can compile something against vanilla zlib 1.2.12 and then LD_PRELOAD zlib-ng.\nYour test binary also seems to be aarch32. While I probably do have a 32 bit ARM system, I'm sure it doesn't have neon support. Your crashing load when running objdump on your binary seems to be around here:\n 17b44: eea07b90 vdup.32 q8, r7\n 17b48: e1a0c009 mov ip, r9\n 17b4c: e3a08000 mov r8, #0\n 17b50: f4440aef vst1.64 {d16-d17}, [r4 :128]```\n\nvst1.64 is storing 2 x 64 bit wide stores from registers d16-d17 into the address contained in register 4 (which is presumed to be aligned to a 128 bit boundary, given the :128 hint). From your stack trace + register printout, that address is in fact 128 bit (16 byte) aligned. Interesting that the dump here shows the store into r4 and not r0, though it's possible you have some variance in your compilation from that crash that I may not be looking at the proper instruction. Somewhat interesting is that we don't intentionally generate any stores until the final checksum, so this is very likely a compiler generated register spill. Given that it assumes it can be aligned, it's probably spilling the `taps` array (aarch32 I would expect to have some register starvation so that makes sense).\n\nNow, why there would be issues with stack alignment here...perhaps that's an android ABI thing? The address certainly appears to be the proper alignment and you're not seeing crashes when linking directly, which is telling. You could try removing that \"ALIGNED_(16)\" macro and that might coincidentally fix your problem but this seems like something stranger is happening. Can you try linking your test application to zlib 1.2.12 and then LD_PRELOAD'ing the zlib-ng shared lib? Officially, this method, while it works, is kind of discouraged, especially system-wide. In particular you're subverting the loader and telling it to load all of the exported functions from the shared library before anything else and hoping that it's API compatible. \n\n\n\nOh my fault, I mistake your meaning, I just do linking and removed the function call, actually regardless of how to link, program only crash when it execute the adler32_neon\n\n\nJust to double check your use case as close as possible (I'm on aarch64 and using Linux, not android, but perhaps this is a good enough test):\n[adam@odroid ~]$ cat test.c \n#include <stddef.h>\n#include <sys/types.h>\n#include <zlib.h>\n#include <stdlib.h>\n\nint main()\n{\n size_t len = 8192;\n void* buffer = malloc(len);\n u_int32_t adler = adler32(0L, Z_NULL, 0);\n u_int32_t aadler = adler32(adler, buffer, len);\n free(buffer);\n return 0;\n}\n\n[adam@odroid blah]$ ls -alh /usr/lib/libz.so.1.2.12 \n-rwxr-xr-x 1 root root 90K Apr 24 06:07 /usr/lib/libz.so.1.2.12\n[adam@odroid blah]$ cd\n[adam@odroid ~]$ gcc -O3 -march=native test.c -lz -o test.out\n[adam@odroid ~]$ ldd test.out \n\tlinux-vdso.so.1 (0x0000ffffa93be000)\n\tlibz.so.1 => /usr/lib/libz.so.1 (0x0000ffffa9330000)\n\tlibc.so.6 => /usr/lib/libc.so.6 (0x0000ffffa9170000)\n\t/lib/ld-linux-aarch64.so.1 => /usr/lib/ld-linux-aarch64.so.1 (0x0000ffffa9385000)\n[adam@odroid ~]$ LD_PRELOAD=/home/adam/zlib-ng-install/lib/libz.so.1.2.12.zlib-ng ./test.out \n[adam@odroid ~]$ echo $?\n0\n\n\n\n\nsource.zip\n\nThis test I extracted the function standalone and it does crashed\n\n\n[adam@odroid blah]$ cat source.c\n#include <stddef.h>\n#include <string.h>\n#include <stdlib.h>\n#include <stdint.h>\n\n#include <arm_neon.h>\n#include \"adler32_p.h\"\n\n#if defined(__clang__) || defined(__GNUC__)\n# define ALIGNED_(x) __attribute__ ((aligned(x)))\n#elif defined(_MSC_VER)\n# define ALIGNED_(x) __declspec(align(x))\n#endif\n\n/* Minimum of a and b. */\n#define MIN(a, b) ((a) > (b) ? (b) : (a))\n/* Maximum of a and b. */\n#define MAX(a, b) ((a) < (b) ? (b) : (a))\n\n#define vmull_high_u8(a, b) vmull_u8(vget_high_u8(a), vget_high_u8(b))\n#define vmlal_high_u8(a, b, c) vmlal_u8(a, vget_high_u8(b), vget_high_u8(c))\n#define vmlal_high_u16(a, b, c) vmlal_u16(a, vget_high_u16(b), vget_high_u16(c))\n#define vaddw_high_u8(a, b) vaddw_u8(a, vget_high_u8(b))\n\nstatic void NEON_accum32(uint32_t *s, const uint8_t *buf, uint64_t len) {\n static const uint16_t ALIGNED_(16) taps[64] = {\n 64, 63, 62, 61, 60, 59, 58, 57,\n 56, 55, 54, 53, 52, 51, 50, 49,\n 48, 47, 46, 45, 44, 43, 42, 41,\n 40, 39, 38, 37, 36, 35, 34, 33,\n 32, 31, 30, 29, 28, 27, 26, 25,\n 24, 23, 22, 21, 20, 19, 18, 17,\n 16, 15, 14, 13, 12, 11, 10, 9,\n 8, 7, 6, 5, 4, 3, 2, 1 };\n\n uint32x4_t adacc = vdupq_n_u32(0);\n uint32x4_t s2acc = vdupq_n_u32(0);\n uint32x4_t s2acc_0 = vdupq_n_u32(0);\n uint32x4_t s2acc_1 = vdupq_n_u32(0);\n uint32x4_t s2acc_2 = vdupq_n_u32(0);\n\n adacc = vsetq_lane_u32(s[0], adacc, 0);\n s2acc = vsetq_lane_u32(s[1], s2acc, 0);\n\n uint32x4_t s3acc = vdupq_n_u32(0);\n uint32x4_t adacc_prev = adacc;\n\n uint16x8_t s2_0, s2_1, s2_2, s2_3;\n s2_0 = s2_1 = s2_2 = s2_3 = vdupq_n_u16(0);\n\n uint16x8_t s2_4, s2_5, s2_6, s2_7;\n s2_4 = s2_5 = s2_6 = s2_7 = vdupq_n_u16(0);\n\n uint64_t num_iter = len >> 2;\n int rem = len & 3;\n\n for (uint64_t i = 0; i < num_iter; ++i) {\n uint8x16x4_t d0_d3 = vld1q_u8_x4(buf);\n\n /* Unfortunately it doesn't look like there's a direct sum 8 bit to 32\n * bit instruction, we'll have to make due summing to 16 bits first */\n uint16x8x2_t hsum, hsum_fold;\n hsum.val[0] = vpaddlq_u8(d0_d3.val[0]);\n hsum.val[1] = vpaddlq_u8(d0_d3.val[1]);\n\n hsum_fold.val[0] = vpadalq_u8(hsum.val[0], d0_d3.val[2]);\n hsum_fold.val[1] = vpadalq_u8(hsum.val[1], d0_d3.val[3]);\n\n adacc = vpadalq_u16(adacc, hsum_fold.val[0]);\n s3acc = vaddq_u32(s3acc, adacc_prev);\n adacc = vpadalq_u16(adacc, hsum_fold.val[1]);\n\n /* If we do straight widening additions to the 16 bit values, we don't incur\n * the usual penalties of a pairwise add. We can defer the multiplications\n * until the very end. These will not overflow because we are incurring at\n * most 408 loop iterations (NMAX / 64), and a given lane is only going to be\n * summed into once. This means for the maximum input size, the largest value\n * we will see is 255 * 102 = 26010, safely under uint16 max */\n s2_0 = vaddw_u8(s2_0, vget_low_u8(d0_d3.val[0]));\n s2_1 = vaddw_high_u8(s2_1, d0_d3.val[0]);\n s2_2 = vaddw_u8(s2_2, vget_low_u8(d0_d3.val[1]));\n s2_3 = vaddw_high_u8(s2_3, d0_d3.val[1]);\n s2_4 = vaddw_u8(s2_4, vget_low_u8(d0_d3.val[2]));\n s2_5 = vaddw_high_u8(s2_5, d0_d3.val[2]);\n s2_6 = vaddw_u8(s2_6, vget_low_u8(d0_d3.val[3]));\n s2_7 = vaddw_high_u8(s2_7, d0_d3.val[3]);\n\n adacc_prev = adacc;\n buf += 64;\n }\n\n s3acc = vshlq_n_u32(s3acc, 6);\n\n if (rem) {\n uint32x4_t s3acc_0 = vdupq_n_u32(0);\n while (rem--) {\n uint8x16_t d0 = vld1q_u8(buf);\n uint16x8_t adler;\n adler = vpaddlq_u8(d0);\n s2_6 = vaddw_u8(s2_6, vget_low_u8(d0));\n s2_7 = vaddw_high_u8(s2_7, d0);\n adacc = vpadalq_u16(adacc, adler);\n s3acc_0 = vaddq_u32(s3acc_0, adacc_prev);\n adacc_prev = adacc;\n buf += 16;\n }\n\n s3acc_0 = vshlq_n_u32(s3acc_0, 4);\n s3acc = vaddq_u32(s3acc_0, s3acc);\n }\n\n uint16x8x4_t t0_t3 = vld1q_u16_x4(taps);\n uint16x8x4_t t4_t7 = vld1q_u16_x4(taps + 32);\n\n s2acc = vmlal_high_u16(s2acc, t0_t3.val[0], s2_0);\n s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t0_t3.val[0]), vget_low_u16(s2_0));\n s2acc_1 = vmlal_high_u16(s2acc_1, t0_t3.val[1], s2_1);\n s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t0_t3.val[1]), vget_low_u16(s2_1));\n\n s2acc = vmlal_high_u16(s2acc, t0_t3.val[2], s2_2);\n s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t0_t3.val[2]), vget_low_u16(s2_2));\n s2acc_1 = vmlal_high_u16(s2acc_1, t0_t3.val[3], s2_3);\n s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t0_t3.val[3]), vget_low_u16(s2_3));\n\n s2acc = vmlal_high_u16(s2acc, t4_t7.val[0], s2_4);\n s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t4_t7.val[0]), vget_low_u16(s2_4));\n s2acc_1 = vmlal_high_u16(s2acc_1, t4_t7.val[1], s2_5);\n s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t4_t7.val[1]), vget_low_u16(s2_5));\n\n s2acc = vmlal_high_u16(s2acc, t4_t7.val[2], s2_6);\n s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t4_t7.val[2]), vget_low_u16(s2_6));\n s2acc_1 = vmlal_high_u16(s2acc_1, t4_t7.val[3], s2_7);\n s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t4_t7.val[3]), vget_low_u16(s2_7));\n\n s2acc = vaddq_u32(s2acc_0, s2acc);\n s2acc_2 = vaddq_u32(s2acc_1, s2acc_2);\n s2acc = vaddq_u32(s2acc, s2acc_2);\n\n uint32x2_t adacc2, s2acc2, as;\n s2acc = vaddq_u32(s2acc, s3acc);\n adacc2 = vpadd_u32(vget_low_u32(adacc), vget_high_u32(adacc));\n s2acc2 = vpadd_u32(vget_low_u32(s2acc), vget_high_u32(s2acc));\n as = vpadd_u32(adacc2, s2acc2);\n s[0] = vget_lane_u32(as, 0);\n s[1] = vget_lane_u32(as, 1);\n}\n\nstatic void NEON_handle_tail(uint32_t *pair, const uint8_t *buf, uint64_t len) {\n unsigned int i;\n for (i = 0; i < len; ++i) {\n pair[0] += buf[i];\n pair[1] += pair[0];\n }\n}\n\nuint32_t adler32_neon(uint32_t adler, const uint8_t *buf, uint64_t len) {\n /* split Adler-32 into component sums */\n uint32_t sum2 = (adler >> 16) & 0xffff;\n adler &= 0xffff;\n\n /* in case user likes doing a byte at a time, keep it fast */\n if (len == 1)\n return adler32_len_1(adler, buf, sum2);\n\n /* initial Adler-32 value (deferred check for len == 1 speed) */\n if (buf == NULL)\n return 1L;\n\n /* in case short lengths are provided, keep it somewhat fast */\n if (len < 16)\n return adler32_len_16(adler, buf, len, sum2);\n\n uint32_t pair[2];\n int n = NMAX;\n unsigned int done = 0;\n\n /* Split Adler-32 into component sums, it can be supplied by\n * the caller sites (e.g. in a PNG file).\n */\n pair[0] = adler;\n pair[1] = sum2;\n\n /* If memory is not SIMD aligned, do scalar sums to an aligned\n * offset, provided that doing so doesn't completely eliminate\n * SIMD operation. Aligned loads are still faster on ARM, even\n * though there's no explicit aligned load instruction */\n unsigned int align_offset = ((uintptr_t)buf & 15);\n unsigned int align_adj = (align_offset) ? 16 - align_offset : 0;\n\n if (align_offset && len >= (16 + align_adj)) {\n NEON_handle_tail(pair, buf, align_adj);\n n -= align_adj;\n done += align_adj;\n\n } else {\n /* If here, we failed the len criteria test, it wouldn't be\n * worthwhile to do scalar aligning sums */\n align_adj = 0;\n }\n\n while (done < len) {\n int remaining = (int)(len - done);\n n = MIN(remaining, (done == align_adj) ? n : NMAX);\n\n if (n < 16)\n break;\n\n NEON_accum32(pair, buf + done, n >> 4);\n pair[0] %= BASE;\n pair[1] %= BASE;\n\n int actual_nsums = (n >> 4) << 4;\n done += actual_nsums;\n }\n\n /* Handle the tail elements. */\n if (done < len) {\n NEON_handle_tail(pair, (buf + done), len - done);\n pair[0] %= BASE;\n pair[1] %= BASE;\n }\n\n /* D = B * 65536 + A, see: https://en.wikipedia.org/wiki/Adler-32. */\n return (pair[1] << 16) | pair[0];\n}\n\n#define adler32 adler32_neon\n#define Z_NULL NULL\n\nint main()\n{\n size_t len = 8192;\n void* buffer = malloc(len);\n u_int32_t adler = adler32(0L, Z_NULL, 0);\n u_int32_t aadler = adler32(adler, buffer, len);\n free(buffer);\n return 0;\n}[adam@odroid blah]$ gcc -march=native source.c -o test.out -lz\n[adam@odroid blah]$ LD_PRELOAD=/home/adam/zlib-ng-install/lib/libz.so.1.2.12.zlib-ng ./test.out \n[adam@odroid blah]$ echo $?\n0\n\nThe -march=native is merely to enable neon at compilation time. Though, that bit probably isn't strictly necessary with aarch64 since asimd is pretty much implicit, I think. I'm definitely not seeing a crash. What version of vanilla zlib are you linking to? This matters a lot. You said you see this crash if you link directly to zlib-ng as well?\n\n\n\nThis test doesn't link to zlib, I just extract the function out\n\n\ndump.zip\nAnd dumps here\n\n\n\n[adam@odroid blah]$ cat source.c\n#include <stddef.h>\n#include <string.h>\n#include <stdlib.h>\n#include <stdint.h>\n\n#include <arm_neon.h>\n#include \"adler32_p.h\"\n\n#if defined(__clang__) || defined(__GNUC__)\n# define ALIGNED_(x) __attribute__ ((aligned(x)))\n#elif defined(_MSC_VER)\n# define ALIGNED_(x) __declspec(align(x))\n#endif\n\n/* Minimum of a and b. */\n#define MIN(a, b) ((a) > (b) ? (b) : (a))\n/* Maximum of a and b. */\n#define MAX(a, b) ((a) < (b) ? (b) : (a))\n\n#define vmull_high_u8(a, b) vmull_u8(vget_high_u8(a), vget_high_u8(b))\n#define vmlal_high_u8(a, b, c) vmlal_u8(a, vget_high_u8(b), vget_high_u8(c))\n#define vmlal_high_u16(a, b, c) vmlal_u16(a, vget_high_u16(b), vget_high_u16(c))\n#define vaddw_high_u8(a, b) vaddw_u8(a, vget_high_u8(b))\n\nstatic void NEON_accum32(uint32_t *s, const uint8_t *buf, uint64_t len) {\n static const uint16_t ALIGNED_(16) taps[64] = {\n 64, 63, 62, 61, 60, 59, 58, 57,\n 56, 55, 54, 53, 52, 51, 50, 49,\n 48, 47, 46, 45, 44, 43, 42, 41,\n 40, 39, 38, 37, 36, 35, 34, 33,\n 32, 31, 30, 29, 28, 27, 26, 25,\n 24, 23, 22, 21, 20, 19, 18, 17,\n 16, 15, 14, 13, 12, 11, 10, 9,\n 8, 7, 6, 5, 4, 3, 2, 1 };\n\n uint32x4_t adacc = vdupq_n_u32(0);\n uint32x4_t s2acc = vdupq_n_u32(0);\n uint32x4_t s2acc_0 = vdupq_n_u32(0);\n uint32x4_t s2acc_1 = vdupq_n_u32(0);\n uint32x4_t s2acc_2 = vdupq_n_u32(0);\n\n adacc = vsetq_lane_u32(s[0], adacc, 0);\n s2acc = vsetq_lane_u32(s[1], s2acc, 0);\n\n uint32x4_t s3acc = vdupq_n_u32(0);\n uint32x4_t adacc_prev = adacc;\n\n uint16x8_t s2_0, s2_1, s2_2, s2_3;\n s2_0 = s2_1 = s2_2 = s2_3 = vdupq_n_u16(0);\n\n uint16x8_t s2_4, s2_5, s2_6, s2_7;\n s2_4 = s2_5 = s2_6 = s2_7 = vdupq_n_u16(0);\n\n uint64_t num_iter = len >> 2;\n int rem = len & 3;\n\n for (uint64_t i = 0; i < num_iter; ++i) {\n uint8x16x4_t d0_d3 = vld1q_u8_x4(buf);\n\n /* Unfortunately it doesn't look like there's a direct sum 8 bit to 32\n * bit instruction, we'll have to make due summing to 16 bits first */\n uint16x8x2_t hsum, hsum_fold;\n hsum.val[0] = vpaddlq_u8(d0_d3.val[0]);\n hsum.val[1] = vpaddlq_u8(d0_d3.val[1]);\n\n hsum_fold.val[0] = vpadalq_u8(hsum.val[0], d0_d3.val[2]);\n hsum_fold.val[1] = vpadalq_u8(hsum.val[1], d0_d3.val[3]);\n\n adacc = vpadalq_u16(adacc, hsum_fold.val[0]);\n s3acc = vaddq_u32(s3acc, adacc_prev);\n adacc = vpadalq_u16(adacc, hsum_fold.val[1]);\n\n /* If we do straight widening additions to the 16 bit values, we don't incur\n * the usual penalties of a pairwise add. We can defer the multiplications\n * until the very end. These will not overflow because we are incurring at\n * most 408 loop iterations (NMAX / 64), and a given lane is only going to be\n * summed into once. This means for the maximum input size, the largest value\n * we will see is 255 * 102 = 26010, safely under uint16 max */\n s2_0 = vaddw_u8(s2_0, vget_low_u8(d0_d3.val[0]));\n s2_1 = vaddw_high_u8(s2_1, d0_d3.val[0]);\n s2_2 = vaddw_u8(s2_2, vget_low_u8(d0_d3.val[1]));\n s2_3 = vaddw_high_u8(s2_3, d0_d3.val[1]);\n s2_4 = vaddw_u8(s2_4, vget_low_u8(d0_d3.val[2]));\n s2_5 = vaddw_high_u8(s2_5, d0_d3.val[2]);\n s2_6 = vaddw_u8(s2_6, vget_low_u8(d0_d3.val[3]));\n s2_7 = vaddw_high_u8(s2_7, d0_d3.val[3]);\n\n adacc_prev = adacc;\n buf += 64;\n }\n\n s3acc = vshlq_n_u32(s3acc, 6);\n\n if (rem) {\n uint32x4_t s3acc_0 = vdupq_n_u32(0);\n while (rem--) {\n uint8x16_t d0 = vld1q_u8(buf);\n uint16x8_t adler;\n adler = vpaddlq_u8(d0);\n s2_6 = vaddw_u8(s2_6, vget_low_u8(d0));\n s2_7 = vaddw_high_u8(s2_7, d0);\n adacc = vpadalq_u16(adacc, adler);\n s3acc_0 = vaddq_u32(s3acc_0, adacc_prev);\n adacc_prev = adacc;\n buf += 16;\n }\n\n s3acc_0 = vshlq_n_u32(s3acc_0, 4);\n s3acc = vaddq_u32(s3acc_0, s3acc);\n }\n\n uint16x8x4_t t0_t3 = vld1q_u16_x4(taps);\n uint16x8x4_t t4_t7 = vld1q_u16_x4(taps + 32);\n\n s2acc = vmlal_high_u16(s2acc, t0_t3.val[0], s2_0);\n s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t0_t3.val[0]), vget_low_u16(s2_0));\n s2acc_1 = vmlal_high_u16(s2acc_1, t0_t3.val[1], s2_1);\n s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t0_t3.val[1]), vget_low_u16(s2_1));\n\n s2acc = vmlal_high_u16(s2acc, t0_t3.val[2], s2_2);\n s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t0_t3.val[2]), vget_low_u16(s2_2));\n s2acc_1 = vmlal_high_u16(s2acc_1, t0_t3.val[3], s2_3);\n s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t0_t3.val[3]), vget_low_u16(s2_3));\n\n s2acc = vmlal_high_u16(s2acc, t4_t7.val[0], s2_4);\n s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t4_t7.val[0]), vget_low_u16(s2_4));\n s2acc_1 = vmlal_high_u16(s2acc_1, t4_t7.val[1], s2_5);\n s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t4_t7.val[1]), vget_low_u16(s2_5));\n\n s2acc = vmlal_high_u16(s2acc, t4_t7.val[2], s2_6);\n s2acc_0 = vmlal_u16(s2acc_0, vget_low_u16(t4_t7.val[2]), vget_low_u16(s2_6));\n s2acc_1 = vmlal_high_u16(s2acc_1, t4_t7.val[3], s2_7);\n s2acc_2 = vmlal_u16(s2acc_2, vget_low_u16(t4_t7.val[3]), vget_low_u16(s2_7));\n\n s2acc = vaddq_u32(s2acc_0, s2acc);\n s2acc_2 = vaddq_u32(s2acc_1, s2acc_2);\n s2acc = vaddq_u32(s2acc, s2acc_2);\n\n uint32x2_t adacc2, s2acc2, as;\n s2acc = vaddq_u32(s2acc, s3acc);\n adacc2 = vpadd_u32(vget_low_u32(adacc), vget_high_u32(adacc));\n s2acc2 = vpadd_u32(vget_low_u32(s2acc), vget_high_u32(s2acc));\n as = vpadd_u32(adacc2, s2acc2);\n s[0] = vget_lane_u32(as, 0);\n s[1] = vget_lane_u32(as, 1);\n}\n\nstatic void NEON_handle_tail(uint32_t *pair, const uint8_t *buf, uint64_t len) {\n unsigned int i;\n for (i = 0; i < len; ++i) {\n pair[0] += buf[i];\n pair[1] += pair[0];\n }\n}\n\nuint32_t adler32_neon(uint32_t adler, const uint8_t *buf, uint64_t len) {\n /* split Adler-32 into component sums */\n uint32_t sum2 = (adler >> 16) & 0xffff;\n adler &= 0xffff;\n\n /* in case user likes doing a byte at a time, keep it fast */\n if (len == 1)\n return adler32_len_1(adler, buf, sum2);\n\n /* initial Adler-32 value (deferred check for len == 1 speed) */\n if (buf == NULL)\n return 1L;\n\n /* in case short lengths are provided, keep it somewhat fast */\n if (len < 16)\n return adler32_len_16(adler, buf, len, sum2);\n\n uint32_t pair[2];\n int n = NMAX;\n unsigned int done = 0;\n\n /* Split Adler-32 into component sums, it can be supplied by\n * the caller sites (e.g. in a PNG file).\n */\n pair[0] = adler;\n pair[1] = sum2;\n\n /* If memory is not SIMD aligned, do scalar sums to an aligned\n * offset, provided that doing so doesn't completely eliminate\n * SIMD operation. Aligned loads are still faster on ARM, even\n * though there's no explicit aligned load instruction */\n unsigned int align_offset = ((uintptr_t)buf & 15);\n unsigned int align_adj = (align_offset) ? 16 - align_offset : 0;\n\n if (align_offset && len >= (16 + align_adj)) {\n NEON_handle_tail(pair, buf, align_adj);\n n -= align_adj;\n done += align_adj;\n\n } else {\n /* If here, we failed the len criteria test, it wouldn't be\n * worthwhile to do scalar aligning sums */\n align_adj = 0;\n }\n\n while (done < len) {\n int remaining = (int)(len - done);\n n = MIN(remaining, (done == align_adj) ? n : NMAX);\n\n if (n < 16)\n break;\n\n NEON_accum32(pair, buf + done, n >> 4);\n pair[0] %= BASE;\n pair[1] %= BASE;\n\n int actual_nsums = (n >> 4) << 4;\n done += actual_nsums;\n }\n\n /* Handle the tail elements. */\n if (done < len) {\n NEON_handle_tail(pair, (buf + done), len - done);\n pair[0] %= BASE;\n pair[1] %= BASE;\n }\n\n /* D = B * 65536 + A, see: https://en.wikipedia.org/wiki/Adler-32. */\n return (pair[1] << 16) | pair[0];\n}\n\n#define adler32 adler32_neon\n#define Z_NULL NULL\n\nint main()\n{\n size_t len = 8192;\n void* buffer = malloc(len);\n u_int32_t adler = adler32(0L, Z_NULL, 0);\n u_int32_t aadler = adler32(adler, buffer, len);\n free(buffer);\n return 0;\n}[adam@odroid blah]$ gcc -march=native source.c -o test.out -lz\n[adam@odroid blah]$ LD_PRELOAD=/home/adam/zlib-ng-install/lib/libz.so.1.2.12.zlib-ng ./test.out \n[adam@odroid blah]$ echo $?\n0\n\nThe -march=native is merely to enable neon at compilation time. Though, that bit probably isn't strictly necessary with aarch64 since asimd is pretty much implicit, I think. I'm definitely not seeing a crash. What version of vanilla zlib are you linking to? This matters a lot. You said you see this crash if you link directly to zlib-ng as well?\n\nYes, directly linking it crashed as well if I called the adler32 function\n\n\nSo I make the adler32 neon impl standalone to test if it will crash\nAnd significantly the same error\n\n\nThat's peculiar. I'm pretty sure our ci has an aarch32 target running neon (on Linux, at least). Does the crash go away if you remove the ALIGNED_(16) macro? There's no technical reason it needs it, it's simply an (probably meaningful on aarch32) optimization. Doing so should remove that alignment hint.\nIf that's the case, there might be a bug in the clang distributed with NDK.\n\n\n\nNo, after delete the ALIGNED marco, it triggered a bus error as well\n\n\nThere's no obvious bug here that would trigger this. The loads themselves are of the natural type for a byte and the spills are generated by the compiler.\nThe only thing I can think of is the 4x load rather than 4 separate discrete loads. I'm fairly certain there's no alignment requirement for that in the arm abi to begin with, but maybe?\n\n\nI suspect clang is generating an alignment hint regardless at those stores. Now the address at the sigbus seemed properly aligned so that was weird but:\nhttps://github.com/android/ndk/issues/640\nThere's at least some evidence that clang excessively decorates with that hint. Which of course will generate a fault if not properly aligned. This is really strange. It's an issue that disappears entirely on aarch64 as that hint I think is non-existent.\n\n\nYes, it's a clang specific issue, I tried compile with arm gcc and libc static linked, works well\n\nI suspect clang is generating an alignment hint regardless at those stores. Now the address at the sigbus seemed properly aligned so that was weird but: android/ndk#640\nThere's at least some evidence that clang excessively decorates with that hint. Which of course will generate a fault if not properly aligned. This is really strange. It's an issue that disappears entirely on aarch64 as that hint I think is non-existent.\n\n\n\nSeem that bus error at this line https://github.com/zlib-ng/zlib-ng/blob/ce01b1e41da298334f8214389cc9369540a7560f/arch/arm/adler32_neon.c#L51\n\n\n\nSeem that bus error at this line\nhttps://github.com/zlib-ng/zlib-ng/blob/ce01b1e41da298334f8214389cc9369540a7560f/arch/arm/adler32_neon.c#L51\n\nBut if we don't use <arm_neon>'s vld1q_u8_x4 vld1q_u16_x4\nbut the fallback https://github.com/zlib-ng/zlib-ng/blob/ce01b1e41da298334f8214389cc9369540a7560f/fallback_builtins.h#L111\nhttps://github.com/zlib-ng/zlib-ng/blob/ce01b1e41da298334f8214389cc9369540a7560f/fallback_builtins.h#L102\nprogram will pass\n\n\nMaybe we should not use these builtin functions althouth <arm_neon> have it but override them?\n\n\nBut fact is that my device does support LD4\nI tried a small test\n#include <alloca.h>\n#include <arm_neon.h>\nint main()\n{\nsize_t len = 64;\nvoid* buffer = alloca(len);\nuint32_t pair[2];\nvld1q_u16_x4(buffer);\nreturn 0;\n}\nprograms trigger bus error randomly\nSeems vld1q_u16_x4 usage have some alignment requirement and our zlib-ng just not satisfy it\n\n\nAnd call vld1q_u16 respectively doesn't have such requirement :\n#include <alloca.h>\n#include <arm_neon.h>\nstatic inline uint16x8x4_t vld1q_u16_x4__(uint16_t *a) {\nuint16x8x4_t ret = (uint16x8x4_t) {{\nvld1q_u16(a),\nvld1q_u16(a+8),\nvld1q_u16(a+16),\nvld1q_u16(a+24)}};\nreturn ret;\n}\nint main()\n{\nsize_t len = 64;\nvoid* buffer = alloca(len);\nuint32_t pair[2];\nvld1q_u16_x4__(buffer);\nreturn 0;\n}\nprogram never fails\n\n\n@KungFuJesus Any idea?\n\n\n\nThere's no obvious bug here that would trigger this. The loads themselves are of the natural type for a byte and the spills are generated by the compiler.\nThe only thing I can think of is the 4x load rather than 4 separate discrete loads. I'm fairly certain there's no alignment requirement for that in the arm abi to begin with, but maybe?\n\nFeel like it just because 4x load have alignment requirement (at least on my environment)\n\n\nIf the alignment is required by Android ABI, maybe we need specific workaround for combination of Android and Clang... I know we have had workarounds for Clang before.\n\n\nIt's unclear if it's a requirement of the Android ABI, the aarch32 ABI, or both. I can't find any such documentation specifying the need for alignment for a 4x load. The load in the loop most of the time actually is aligned, except for the case that doing scalar sums to get to alignment would bypass the vectorized function entirely. Certainly the example with 8k bytes here, this is the case and he's still seeing a crash with it?\nIf we can find out what is requiring this we can probably surmise a combination in the preprocessor to make these conditions compile to the fallback. This isn't the only place the 4x wide load is used, though. It's used in slidehash as well, where we always have guaranteed 16 byte alignment.\n\n\n\nIt really shouldn't require alignment for a 4x load. It really seems like a compiler bug. Does gcc actually generate the 4x load or does it not have the intrinsic and just use the fallback?\n\ngcc doesn't have such a 4x load intrinsic, just use the fallback\n\n\nI mean...https://www.google.com/search?q=\"vld1q_u8_x4\"+sigbus&sxsrf=ALiCzsY7uWuymeHoWL1eJw17w-Zspvnq-w%3A1663077828766&ei=xI0gY_6ZLoyp5NoP7M-4SA&ved=0ahUKEwj-i97Z95H6AhWMFFkFHewnDgkQ4dUDCA4&uact=5&oq=\"vld1q_u8_x4\"+sigbus&gs_lcp=Cgdnd3Mtd2l6EAMyCAgAEKIEELADMggIABCiBBCwAzIICAAQogQQsAMyCAgAEKIEELADMggIABCiBBCwA0oECEEYAUoECEYYAFAAWABgogZoAnAAeACAAQCIAQCSAQCYAQDIAQXAAQE&sclient=gws-wiz\n0 results. Are we literally the only people to have seen this? Something doesn't seem quite right, here. This crash is on actual hardware and not with a qemu target?\n\n\n\nIt's unclear if it's a requirement of the Android ABI, the aarch32 ABI, or both. I can't find any such documentation specifying the need for alignment for a 4x load. The load in the loop most of the time actually is aligned, except for the case that doing scalar sums to get to alignment would bypass the vectorized function entirely. Certainly the example with 8k bytes here, this is the case and he's still seeing a crash with it?\n\nAs far as I know, only 32-bit Android ABI used both gcc and clang and this is clearly issue with Android ABI versions that already used Clang. The stricter alignment requirement was clearly for backwards compatibility and doesn't make much sense to keep it for 64-bit binaries as the shift from 32-bit to 64-bit addressing model already require rewrite of the ABI.\n\n\nAnd vld1qx? for armv7 is supported in clang since https://github.com/llvm/llvm-project/commit/9c40c0ad0ca49a0b4eff20bf85b088daecb0014f\n\n\n@KungFuJesus I suspect it is combination of using specific Android ABI version as a target for clang and complexity of code. When we confirm the exact line where the alignment exception happens, we need to force compiler to align all variables used in that line. Using the current fallback might be the last solution, as we don't know (yet) if splitting the x4 load to two x2 loads avoids the exception...\nI've seen similar issue with 32-bit PowerPC processors using vector instructions.\n\n\nI feel like this should be a bug filed with NDK. Why does Google think it can assume any alignment here, let alone 256 bit alignment at this address? Do newer versions of the NDK distribute newer versions of clang that maybe have this feature removed?\n\n\nGoogle has pretty much killed most of Android development in C or C++ with the change to Clang and custom C library... Only applications that are still released are either written in Java or JavaScript.\nAlthough we could blame Google and ask affected zlib-ng users to file another bug report against Android NDK, I'm pessimistic about them fixing anything for the 32-bit ABI.\n\n\n@asuka-mio could carry a custom patch that forces this to 4x discretized loads I guess, but it seems awfully silly. The register spills on aarch32 also bothers me a bit. @dougallj has a better adler32 implementation (leveraging a more direct widening fused multiply add) that myself or him could drop in at any time, but I don't think that really would help all that much with the register pressure situation. I'm also not entirely sure that instruction exists in armv7.\n\n\n\n@asuka-mio could carry a custom patch that forces this to 4x discretized loads I guess, but it seems awfully silly. The register spills on aarch32 also bothers me a bit. @dougallj has a better adler32 implementation (leveraging a more direct widening fused multiply add) that myself or him could drop in at any time, but I don't think that really would help all that much with the register pressure situation. I'm also not entirely sure that instruction exists in armv7.\n\nIt's up to us to decide if it's worth adding workaround in the official zlib-ng sources or downstream the patch to third-party port... I usually tag people I think should participate in the discussion and anyone is free to tag more people even if our guidelines say those people have no vote in final decisions because they are not long-time contributors.\n\n\nI mentioned an NDK bug in this - maybe that will draw some attention from Google NDK people? I certainly suggest filing an issue on the NDK github repo, this is definitely clang doing something it shouldn't. I tagged dougallj mostly to properly credit the better adler32 implementation, however he does have some ARM expertise so his input / speculation here could be valuable.\n\n\nReminds me of all the issues we have had with Microsoft breaking things... We actually managed to get them fix some of their issues, which is quite an achievement for a project of this size.\n\n\n\n@dougallj has a better adler32 implementation (leveraging a more direct widening fused multiply add) that myself or him could drop in at any time, but I don't think that really would help all that much with the register pressure situation. I'm also not entirely sure that instruction exists in armv7.\n\nYeah, unfortunately my implementation isn't a drop-in replacement, as it requires FEAT_DotProd (which is available in 32-bit code, but not prior to ARMv8.2, optional in 8.2/8.3 and present in ARMv8.4 onwards). If there is a register pressure issue, then I'd imagine switching to a narrower implementation would improve performance.\nI don't have much experience with 32-bit ARM, but I agree that the 256-bit alignment looks like a compiler bug (given the intrinsic takes an argument with 8-bit alignment): https://godbolt.org/z/MGq48jcqx\n\nI usually tag people I think should participate in the discussion and anyone is free to tag more people even if our guidelines say those people have no vote in final decisions because they are not long-time contributors.\n\nI'm not looking for a vote, just trying to help out :)\n\n\nIf it's anything like the VNNI implementation was, there was room to overlap 2 running sums. This version is tracking many more sums to try to maximize overlap but I imagine a version that widens at the same time as the dot prod will probably require much fewer in flight registers.\nAs far as detecting if available, I'm sure we can make that work with the standard function table + runtime detection, keeping this one for CPUs that lack that capability.\n\n\nYeah, I imagine we could make something work.\nIt looks like A32 has 16 128-bit registers (half as many as A64). My current code uses 16 registers for the accumulators and multipliers/taps – so there aren't registers left over for the data:\n uint8x16x4_t mul = vld1q_u8_x4(MULTIPLIERS);\n uint32x4_t accs[4] = { 0 };\n uint32x4_t sums[4] = { 0 };\n uint32x4_t extras[4] = { 0 };\n\nSo I'd change it to avoid spilling if 32-bit ARM is an important target. (On M1 keeping those separate maximises throughput by having separate latency chains, but that's unlikely to make a difference on the 32-bit targets I'm aware of.)\n\n\nWe have google benchmarks that time various buffer lengths through the adler functions. It's easy to wire up a new implementation to it and we could test it on a variety of Cortex implementations. It seems likely that breaking data dependency chains is beneficial - that was certainly the case for PowerPC (good lord I had to unroll a lot wider than the max vector with on a G5) and x86. I imagine with big.LITTLE, the little architectures might need the unrolling to get max throughput.\n\n\n\nI'm not looking for a vote, just trying to help out :)\n\nI know... I have been contributor to this project since when the only optimizations were for x86... I started with PowerPC and ARM optimizations while I was still studying the instruction sets, so my knowledge was limited... My primary goal was to add enough code to attract more developers who are more familiar with the different instruction sets.\n\n\nThis breaks support for Raspberry Pi v3b as well.\n"