question stringlengths 23 136 | answer stringlengths 127 6.26k | image_path imagewidth (px) 788 2.48k ⌀ | netlist stringlengths 27 549 ⌀ |
|---|---|---|---|
If we double the length and width of a MOSFET, what happens to its intrinsic gain? | Hello! I am an analog integrated-circuit design expert. Regarding your question about the effect of MOSFET size scaling on intrinsic gain, here is my analysis and answer.
### 1) Derivation and Thought Process
The **intrinsic gain (Intrinsic Gain, $A_v$)** of a MOSFET is defined as the maximum voltage gain of a single... | Not supported with pagination yet | null |
Student A says the transconductance of a MOSFET goes up as the overdrive voltage increases. Student B says it goes down. Who is correct? | Hello! As an analog integrated-circuit design expert, this is a very classic question that touches the core operating principle of the MOSFET. Although you did not attach a specific netlist or circuit diagram, the question itself is purely theoretical, and we can analyze it in depth according to the MOSFET **square-law... | Not supported with pagination yet | null |
Is the small-signal model of a PMOS device identical to that of an NMOS device? | Hello! As an analog integrated-circuit design expert, regarding your question about the small-signal models of PMOS and NMOS, I will provide the following analysis and answer.
### 1. Analysis and Derivation Approach
To answer this question, we need to distinguish between **DC large-signal behavior** and the **AC smal... | Not supported with pagination yet | null |
Sketch IX versus VX in the circuit in Figure 1. | Hello! I am an analog integrated-circuit design expert. Regarding the question, netlist, and circuit diagram you provided, I will perform a detailed analysis.
### 1. Analysis and Derivation Approach
**Circuit identification:**
According to the circuit diagram and the netlist `M1 (net7 net7 VSS VSS) nmos`, we can see ... | Vx (net7 VSS) vsource
M1 (net7 net7 VSS VSS) nmos | |
Sketch IX versus VX in the circuit of Figure 2. | Hello! I am an analog integrated-circuit design expert. Regarding the circuit diagram (Figure 2) and netlist you provided, I will analyze the relationship between $I_X$ and $V_X$ (that is, the $I_X - V_X$ curve).
### 1. Analysis Approach and Derivation
First, we need to clarify the voltage definitions at each termina... | Vx (net9 VSS) vsource
Ix (net8 net9 VSS VSS) nmos
V1 (net8 VSS) vsource | |
Can the device shown in Figure 3 act as a current source? | Based on the question, netlist, and circuit diagram you provided, as an analog integrated-circuit design expert I provide the following analysis:
### 1. Derivation and Thought Process
**Circuit-connection analysis:**
* According to the netlist `M1 (VSS VSS net4 net4) pmos` and the circuit diagram:
* **Device ... | M1 (VSS VSS net4 net4) pmos | |
Analyze the circuit shown in Figure 4. | Hello! I am an analog integrated-circuit design expert. I have performed a detailed analysis of the question, netlist, and circuit diagram you provided.
This is a **PMOS-based common-source amplifier (Common-Source Amplifier) with source degeneration (Source Degeneration)**.
The specific analysis process and conclusi... | RD (VO VSS) resistor
Rs (VDD net7) resistor
M1 (VO VIN net7 net7) pmos | |
Analyze the circuit shown in Figure 5. | Hello! I am an analog integrated-circuit design expert. I have performed a detailed analysis of the circuit diagram (Figure 5) and netlist you provided.
This is a classic **source follower (Source Follower)**, also called a **common-drain amplifier (Common-Drain Amplifier)**.
The specific analysis process and conclus... | Rs (net9 VSS) resistor
M1 (VDD VIN net9 net9) nmos | |
Analyze the circuit shown in Figure 6. | Hello! As an analog integrated-circuit design expert, I will analyze this circuit in detail based on the circuit diagram and netlist you provided.
### 1. Circuit Topology Identification
According to the circuit diagram and netlist information:
* The **input ($V_{in}$)** is connected to the **source (Source)** of NM... | RD (net8 VO) resistor
M1 (VO VDD VIN VIN) nmos | |
Analyze the circuit shown in Figure 7. | The source (S) of MOS transistor M1 in this circuit topology is always connected to ground under both DC and AC conditions.
--- | subckt ckt_common_gate VDD VSS VIN VB VOUT
RD (VDD VOUT) resistor
C1 (VIN net_s) capacitor
M1 (VOUT VB net_s VSS) nmos
VSRC_GND (net_s VSS) vsource
ends ckt_common_gate | |
How many poles does the circuit of Figure 8 have? | OK, as an experienced analog integrated-circuit design expert, I will analyze and answer this question.
### Derivation and Thought Process
1. **Basic concept of poles**:
In circuit analysis, the number of poles of a system is usually equal to the order of the denominator polynomial of its transfer function. Phys... | M1 (net13 net12 VSS Vbulk) nmos
CGS (net12 VSS) capacitor
CSB (VSS VSS) capacitor
RD (VDD VO) resistor
Rs (VIN net12) resistor
CDB (VO VSS) capacitor
CGD (net12 VO) capacitor | |
Analyze the circuit shown in Figure 9. | This is a classic analog integrated-circuit analysis problem. According to the provided circuit diagram and netlist, we can determine that this is a **common-gate amplifier with voltage-series negative feedback**.
The detailed analysis process and conclusion are as follows:
### 1. Circuit Topology and Characteristic ... | R1 (VO net9) resistor
R2 (net9 VSS) resistor
RD (VDD VO) resistor
M1 (VO net9 VIN VIN) nmos | |
Analyze the circuit shown in Figure 10. | OK, as an experienced analog integrated-circuit design expert, I will analyze the circuit you provided.
---
### **Analysis and Derivation Approach**
1. **Circuit topology identification**:
* The circuit consists of two NMOS transistors, M1 and M2, connected in series.
* **M1 transistor**: The input sign... | M1 (VDD VIN VO VO) nmos
M2 (VO Vb VSS VSS) nmos | |
Analyze the circuit of Figure 11(a). | OK, as an experienced analog integrated-circuit design expert, I will analyze the circuit you provided.
---
### **Circuit Analysis**
#### **1) Derivation and Thought Process**
1. **Circuit identification**:
* This circuit is composed of one PMOS transistor (M2) and one NMOS transistor (M1).
* The sourc... | M2 (VO VIN VDD VDD) pmos
M1 (VO VIN VSS VSS) nmos | |
Analyze the circuit shown in Figure 11(b). | OK, as an experienced analog integrated-circuit design expert, I will analyze the circuit you provided in detail.
---
### Circuit Analysis
This circuit is a push-pull structure made of two N-channel MOSFETs (M1 and M2). The input signal `Vin` is applied to the gates of both transistors. The drain of M1 is connected ... | M1 (VDD VIN VO VO) nmos
M2 (VO VIN VSS VSS) nmos | |
Analyze the circuit of Figure 12. | Hello! As an analog integrated-circuit design expert, I will analyze the circuit shown in Figure 12 in detail.
### 1. Analysis Derivation and Thought Process
**1.1 Circuit topology identification**
* **M1 (NMOS)**: source grounded, gate connected to input signal $V_{in}$, and drain connected to output $V_{out}$. Th... | M2 (VO VO VDD VDD) pmos
M1 (VO VIN VSS VSS) nmos | |
Analyze the circuit of Figure 13. | Based on the provided circuit diagram and netlist, this is a **PMOS common-source amplifier with an active load** (Common-Source Amplifier with Active Load).
The detailed analysis process and conclusion are as follows:
### 1. Circuit Topology and Device-State Analysis
* **M2 (driver transistor):**
* Connecti... | M2 (VO VIN VDD VDD) pmos
M1 (VSS VSS VO VO) pmos | |
Find Rout in Figure 14. | Hello! I am an analog integrated-circuit design expert. Regarding the question, netlist, and circuit diagram (Figure 14) you provided, I have performed a detailed analysis. My answer is as follows.
### 1. Analysis and Derivation Approach
**Circuit structure analysis:**
This circuit is a **PMOS cascode current source*... | M2 (net8 Vb2 VDD VDD) pmos
M1 (net10 Vb1 net8 net8) pmos | |
How do we ensure that M2 is in saturation in Figure 14? | This is a classic question in analog CMOS circuit design involving the bias conditions of a PMOS cascode structure.
According to the question, circuit diagram, and netlist provided, the detailed analysis and answer are as follows:
### 1) Derivation and Thought Process
To ensure transistor $M_2$ is in the **saturatio... | M2 (net8 Vb2 VDD VDD) pmos
M1 (net10 Vb1 net8 net8) pmos | |
Analyze the circuit shown in Figure 15. | Hello! As an analog integrated-circuit design expert, I will analyze the circuit diagram and netlist you provided in detail.
### 1. Circuit Structure Identification
According to the circuit diagram (Figure 15) and netlist, this is a classic **NMOS telescopic cascode amplifier (Telescopic Cascode Amplifier)** with an i... | I1 (VDD VO) isource
M2 (VO Vb1 net10 net10) nmos
M1 (net10 VIN VSS VSS) nmos | |
Is the circuit of Figure 16 a cascode structure? | OK, as an experienced analog integrated-circuit design expert, I will analyze and answer your question.
---
### 1) Derivation or Thought Process
1. **Analyze the netlist connections**:
* `M1 (VSS VIN net10 net10) pmos`: This is a **PMOS** transistor. Its drain (D) is connected to `VSS` (ground), and its sour... | M2 (VO Vb1 net10 net10) nmos
RD (VDD VO) resistor
M1 (VSS VIN net10 net10) pmos | |
Explain why the Miller effect is less pronounced in a cascode. | Hello! As an analog integrated-circuit design expert, regarding the question “why the Miller effect (Miller Effect) is less pronounced in a cascode,” I will derive and explain it from the perspectives of circuit principle, gain analysis, and equivalent capacitance.
### 1. Analysis and Derivation Approach
To understan... | Not supported with pagination yet | null |
Analyze the circuit shown in Figure 17. | Hello! I am an analog integrated-circuit design expert. Regarding the circuit diagram (Figure 17) and netlist you provided, I will give a detailed analysis.
### 1. Circuit Topology Identification and Basic Analysis
According to the circuit diagram and netlist:
* **M1 (PMOS)**: source connected to $V_{DD}$, gate con... | M1 (VO Vb2 VDD VDD) pmos
M2 (VO Vb1 VIN VIN) nmos | |
How many poles does the circuit of Figure 18 have? | Based on the provided circuit diagram and netlist, the following is the analysis and conclusion regarding the number of poles in this circuit.
### 1) Analysis and Derivation Approach
**Circuit topology identification:**
This circuit is a common-source amplifier with a gate resistor $R_S$.
* **M1** is the main ampli... | M1 (net20 net19 VSS VSS) nmos
CGS (net19 VSS) capacitor
M2 (VO VSS VSS VSS) pmos
CDB2 (VSS VO) capacitor
RS (VIN net19) resistor
CGD2 (VSS VO) capacitor
CGD (net19 VO) capacitor
CDB (VO VSS) capacitor | |
Analyze the circuit shown in Figure 19. | This is a very classic analog integrated-circuit structure. Based on the provided circuit diagram and netlist, I will analyze the circuit in detail.
### 1. Analysis Derivation and Thought Process
#### A. Circuit topology identification
* **Overall structure**: This is a **common-source amplifier (Common-Source Ampl... | M2 (VO VIN net12 net12) nmos
M1 (net12 VIN VSS VSS) nmos
RD (VDD VO) resistor | |
Analyze the circuit of Figure 20. | Hello! As an analog integrated-circuit design expert, I will analyze the circuit diagram (Figure 20) and netlist you provided in detail.
### 1. Circuit Structure and Characteristic Analysis
**Circuit topology identification:**
This circuit is a **differential pair (Differential Pair)** structure, but it uses a **sing... | M1 (VDD VIN net16 net16) nmos
I1 (net16 VSS) isource
M2 (VO Vb net16 net16) nmos
RD (net12 VO) resistor | |
Explain why the output impedance of the circuit shown in Figure 21 can be inductive. | Hello! I am an analog integrated-circuit design expert. Regarding the question, netlist, and circuit diagram you provided, I will analyze why the output impedance of this circuit can appear inductive (Inductive).
### 1. Analysis Approach and Derivation
This circuit is a classic **source follower (Source Follower)**, ... | M1 (VDD net12 VO VO) nmos
M2 (VO Vb VSS VSS) nmos
Rs (VIN net12) resistor | |
Analyze the circuit shown in Figure 22. | This is a classic analog integrated-circuit analysis problem that tests understanding of feedback type, small-signal impedance, and large-signal operating point.
The following is a detailed analysis based on the provided circuit diagram and netlist:
### 1. Analysis Approach and Derivation
#### 1.1 Circuit topology a... | M2 (net10 VO VSS VSS) nmos
M1 (VO net10 VSS VSS) nmos
RD1 (VDD VO) resistor | |
Analyze the circuit of Figure 23. | This is a classic analysis problem in analog integrated-circuit design. According to the circuit diagram (Figure 23) and netlist, the circuit is a **transimpedance amplifier (Transimpedance Amplifier, TIA)** with **shunt-shunt feedback (Shunt-Shunt Feedback)**.
The detailed analysis, derivation approach, and final con... | Iin (VSS net14) isource
M1 (net11 Vb net14 net14) nmos
M2 (VO net11 VSS VSS) nmos
RD2 (net9 VO) resistor
RF_1 (net14 VO) resistor
RD1 (net9 net11) resistor | |
Analyze the circuit shown in Figure 24. | This is a classic analog integrated-circuit structure. According to the provided circuit diagram and netlist, this circuit is a **regulated common-gate (Regulated Common-Gate, RGC) transimpedance amplifier (Transimpedance Amplifier, TIA)**.
The detailed analysis process and conclusion are as follows:
### 1. Circuit S... | Iin (VSS net17) isource
I1 (net17 VSS) isource
I2 (VDD VO) isource
M1 (VO Vb net17 net17) nmos
M2 (net17 VO VDD VDD) pmos | |
Does the circuit in Figure 5 fail to oscillate if the three capacitors become arbitrarily large? | No. With identical capacitors added at all three nodes of the ring oscillator, the circuit continues to oscillate, but the oscillation frequency decreases as the node capacitance increases.
The capacitors slow each inverter transition and increase the delay per stage. In a three-stage ring, oscillation is maintained a... | subckt ckt_figure-05 VSS
INV1 (net1 net2) inverter
C2 (net3 VSS) capacitor
C3 (net1 VSS) capacitor
INV2 (net2 net3) inverter
C1 (net2 VSS) capacitor
INV3 (net3 net1) inverter
ends ckt_figure-05 | |
What happens to the phase noise if the three capacitors in Figure 5 are doubled? | Doubling all three load capacitors lowers the oscillation frequency by about a factor of two. For white-noise-induced phase noise in this ring oscillator, the relevant expression scales with `f0^2` while the other parameters are approximately independent of `CL`.
Therefore, when `CL` is doubled and `f0` is halved, the... | subckt ckt_figure-05 VSS
INV1 (net1 net2) inverter
C2 (net3 VSS) capacitor
C3 (net1 VSS) capacitor
INV2 (net2 net3) inverter
C1 (net2 VSS) capacitor
INV3 (net3 net1) inverter
ends ckt_figure-05 | |
Does the circuit in Figure 6 fail to oscillate if CL becomes arbitrarily large? | Yes. When a large capacitor is added to only one node, it creates a dominant pole that causes excessive gain roll-off around the loop.
For sufficiently large `CL`, the loop gain falls below unity at the phase-crossover frequency, so the Barkhausen condition is no longer satisfied and oscillation fails. | subckt ckt_figure-06 VSS
INV2 (net2 net3) inverter
INV1 (net1 net2) inverter
CL (net2 VSS) capacitor
INV3 (net3 net1) inverter
ends ckt_figure-06 | |
If we double the widths of the NMOS and PMOS devices in Figure 7, what happens to the phase noise? | Doubling the widths of all NMOS and PMOS devices reduces the phase noise by about 3 dB.
A linear scaling argument gives this result: doubling device widths doubles the drive strength and capacitances in a way roughly equivalent to placing two identical ring oscillators in parallel. The signal power/current capability ... | subckt ckt_figure-07 VDD VSS
MN1 (net13 net12 VSS VSS) nmos
MN2 (net14 net13 VSS VSS) nmos
MN3 (net12 net14 VSS VSS) nmos
MP1 (net13 net12 VDD VDD) pmos
MP2 (net14 net13 VDD VDD) pmos
MP3 (net12 net14 VDD VDD) pmos
ends ckt_figure-07 | |
Determine the small-signal resistance seen looking into the supply node of the ring oscillator in Figure 8. | The resistance seen looking into the supply node of the oscillating ring is not simply the static resistance of diode-connected inverter devices. Oscillation matters because the supply current charges and discharges the three load capacitances each cycle.
For a three-stage ring with node capacitance `CL` and oscillati... | subckt ckt_figure-08 VSS R
INV1 (net2 net3 VSS R) inverter
INV2 (net3 net4 VSS R) inverter
INV3 (net4 net2 VSS R) inverter
ends ckt_figure-08 | |
If the circuit oscillates, determine the small-signal resistance seen looking into the supply node of the ring oscillator in Figure 8. | Considering the oscillation does not make `RX` much larger. The effective resistance is set by the dynamic charging and discharging of the oscillator nodes, not by a dc path that is mostly off.
Using `f0 = 1/(6 TD)` for a three-stage ring, the equivalent supply resistance can be written approximately as
`RX ~= 2 TD /... | subckt ckt_figure-08 VSS R
INV1 (net2 net3 VSS R) inverter
INV2 (net3 net4 VSS R) inverter
INV3 (net4 net2 VSS R) inverter
ends ckt_figure-08 | |
In the circuit of Figure 9, what happens to the initial voltage gain as the width of M7 increases? | As the width of tail transistor `M7` increases, the initial voltage gain decreases.
A wider `M7` increases the tail current available during regeneration. In the StrongARM comparator relation cited by Razavi, the initial gain scales roughly like
`Av ~= gm1,2 VTHN / ICM`,
where `ICM` is tied to the current through `M... | subckt ckt_figure-09 VDD VSS CK Vin1 Vin2 X Y
M7 (Tail CK VSS VSS) nmos
M1 (P Vin1 Tail VSS) nmos
M2 (Q Vin2 Tail VSS) nmos
M3 (X Y P VSS) nmos
M4 (Y X Q VSS) nmos
M5 (X Y VDD VDD) pmos
M6 (Y X VDD VDD) pmos
S1 (P CK VDD VDD) pmos
S2 (Q CK VDD VDD) pmos
S3 (X CK VDD VDD) pmos
... | |
In Figure 9, what happens to the initial voltage gain if we increase the capacitance at nodes P and Q? | The initial voltage gain remains constant.
The initial gain expression depends mainly on the transconductance of the input pair and the common-mode/tail current, not directly on the capacitance at nodes `P` and `Q`. Increasing those capacitances slows the transient response, but it does not change the initial gain set... | subckt ckt_figure-09 VDD VSS CK Vin1 Vin2 X Y
M7 (Tail CK VSS VSS) nmos
M1 (P Vin1 Tail VSS) nmos
M2 (Q Vin2 Tail VSS) nmos
M3 (X Y P VSS) nmos
M4 (Y X Q VSS) nmos
M5 (X Y VDD VDD) pmos
M6 (Y X VDD VDD) pmos
S1 (P CK VDD VDD) pmos
S2 (Q CK VDD VDD) pmos
S3 (X CK VDD VDD) pmos
... | |
If we increase the widths of M5 and M6 in Figure 9, does the speed improve or degrade? | Increasing the widths of `M5` and `M6` initially improves speed.
Although their capacitances increase, the dominant capacitances at nodes `X` and `Y` initially come from other devices and nodes. Wider `M5`/`M6` provide stronger regenerative or pull-up action, so the comparator speeds up until the added capacitance fro... | subckt ckt_figure-09 VDD VSS CK Vin1 Vin2 X Y
M7 (Tail CK VSS VSS) nmos
M1 (P Vin1 Tail VSS) nmos
M2 (Q Vin2 Tail VSS) nmos
M3 (X Y P VSS) nmos
M4 (Y X Q VSS) nmos
M5 (X Y VDD VDD) pmos
M6 (Y X VDD VDD) pmos
S1 (P CK VDD VDD) pmos
S2 (Q CK VDD VDD) pmos
S3 (X CK VDD VDD) pmos
... | |
In the circuit of Figure 10, does the speed improve or degrade if we increase the widths of the clocked transistors? | For the C2MOS divider in Figure 10, increasing the widths of the clocked transistors can improve speed initially.
If the data-driven devices are the bottleneck, stronger clocked devices reduce their on-resistance and help the latch transfer data faster. These wider clocked devices also add capacitance in the data path... | subckt ckt_figure-10 VDD VSS P1 P2 P3 P4
M6 (net13 P4 net10 VDD) pmos
M7 (net13 P1 net17 VSS) nmos
M2 (net8 P2 net9 VDD) pmos
M1 (net9 net1 VDD VDD) pmos
M8 (net17 net8 VSS VSS) nmos
M5 (net10 net8 VDD VDD) pmos
M3 (net8 P3 net16 VSS) nmos
M4 (net16 net1 VSS VSS) nmos
U1 (net13 net1 ... | |
Does the structure in Figure 10 provide quadrature outputs? | The structure does not provide ideal quadrature outputs in a robust sense.
The internal nodes can appear phase-shifted, but the delay through `Inv3` skews node `Z`. Also, the two latches do not necessarily see equal load capacitances. For example, the gate-drain capacitances in `Inv3` experience Miller multiplication,... | subckt ckt_figure-10 VDD VSS P1 P2 P3 P4
M6 (net13 P4 net10 VDD) pmos
M7 (net13 P1 net17 VSS) nmos
M2 (net8 P2 net9 VDD) pmos
M1 (net9 net1 VDD VDD) pmos
M8 (net17 net8 VSS VSS) nmos
M5 (net10 net8 VDD VDD) pmos
M3 (net8 P3 net16 VSS) nmos
M4 (net16 net1 VSS VSS) nmos
U1 (net13 net1 ... | |
In the circuit of Figure 11, does the speed improve or degrade if we increase the widths of the clocked transistors? | For the topology in Figure 11, increasing the widths of the clocked transistors improves speed considerably over an initial useful range.
In this arrangement, the clocked devices do not interfere strongly with the data path, so their lower on-resistance directly helps the transition speed. Charge sharing can occur, bu... | subckt ckt_figure-11 VDD VSS P1 P2 P3 P4
M4 (net15 P3 VSS VSS) nmos
M8 (net14 P1 VSS VSS) nmos
M5 (net11 P4 VDD VDD) pmos
M1 (net10 P2 VDD VDD) pmos
M7 (net13 net12 net14 VSS) nmos
M2 (net12 net1 net10 VDD) pmos
M3 (net12 net1 net15 VSS) nmos
M6 (net13 net12 net11 VDD) pmos
U1 (net13... | |
Analyze the arrangement in Figure 12(a). | Figure 12(a) is a divide-by-two circuit built from dynamic latches.
The clocked latches alternately sample and hold, so the output toggles once for every two input clock cycles. The dynamic nature means stored charge and leakage matter, but the intended function is a frequency divider by two. | subckt ckt_figure-12a
S1 (net_a_fb net_a_in1) switch
U1 (net_a_in1 net_a_out1) inverter
S2 (net_a_out1 net_a_in2) switch
U2 (net_a_in2 net_a_out2) inverter
U3 (net_a_out2 net_a_fb) inverter
ends ckt_figure-12a
subckt ckt_figure-12b
S3 (net_b_fb net_b_in1) switch
U5 (net_b_i... | |
How does the red inverter in Figure 12(b) affect the performance? | The red inverter creates a feedforward path around the first latch. This feedforward path improves divider speed because part of the signal can bypass the main latch path.
It is not simply a keeper or a cross-coupled latch with `Inv1`. At low clock frequencies, the unclocked feedforward branch can dominate the main pa... | subckt ckt_figure-12a
S1 (net_a_fb net_a_in1) switch
U1 (net_a_in1 net_a_out1) inverter
S2 (net_a_out1 net_a_in2) switch
U2 (net_a_in2 net_a_out2) inverter
U3 (net_a_out2 net_a_fb) inverter
ends ckt_figure-12a
subckt ckt_figure-12b
S3 (net_b_fb net_b_in1) switch
U5 (net_b_i... | |
How does the red inverter in Figure 12(b) affect the performance? The input of the red inverter is not tied to the output of Inv1. | Because the input of the red inverter is not tied to the output of `Inv1`, the red inverter is not cross-coupled with `Inv1` and should not be interpreted as a keeper.
Instead, it is a feedforward branch. It takes an earlier signal and drives a later node, bypassing part of the latch path. This can improve high-speed ... | subckt ckt_figure-12a
S1 (net_a_fb net_a_in1) switch
U1 (net_a_in1 net_a_out1) inverter
S2 (net_a_out1 net_a_in2) switch
U2 (net_a_in2 net_a_out2) inverter
U3 (net_a_out2 net_a_fb) inverter
ends ckt_figure-12a
subckt ckt_figure-12b
S3 (net_b_fb net_b_in1) switch
U5 (net_b_i... | |
How do we optimize the circuit of Figure 13 for the NF if Rin must remain equal to 50 Ohm? | The circuit should be optimized by using channel-length modulation and feedback together, not by simply making the load resistance as large as possible.
With `Rin` constrained to 50 ohm, the design variables must be chosen so that the input match is maintained while the noise contribution of the active devices and fee... | subckt ckt_figure-13 VDD VSS in out
M1 (out net2 VSS VSS) nmos
M2 (out net2 VDD VDD) pmos
C1 (in net2) capacitor
RF (net2 out) resistor
ends ckt_figure-13 | |
Compute the input impedance of the circuit in Figure 14(a). | Use the simplified model in Figure 14(b) and apply Miller's theorem to the feedback resistor.
The exact input resistance is
`Rin = (RF + RD2) / (1 + A0)`
where the unloaded gain is
`A0 = (1/2) gm1 gm2,3 RD1 RD2`.
This expression is preferable to a generic shunt-shunt feedback formula because it follows the actual ... | subckt ckt_figure-14a VDD VSS Vb P Vout
Iin (P VSS) isource
Cin (P VSS) capacitor
M1 (X P VSS VSS) nmos
RD1 (VDD X) resistor
ISS (VDD Tail) isource
M2 (VSS X Tail VDD) pmos
M3 (Vout Vb Tail VDD) pmos
RD2 (Vout VSS) resistor
RF (P Vout) resistor
ends ckt_figure-14a
subckt ck... | |
If the LDO regulator in Figure 15 generates thermal noise with spectrum Sth, how do we compute the VCO output phase noise? | The LDO output noise modulates the VCO frequency through the supply-pushing gain. First determine the pushing gain
`Kpush = d fosc / d Vout`
usually by simulation or perturbation analysis. Then convert the LDO noise spectrum `Sth` to phase noise through frequency modulation. In the notation of the article, the single... | subckt ckt_figure-15 VDD VSS Vcont X Y
XLDO (VDD Vout VSS) LDO_subcircuit
L1 (Vout X) inductor
L2 (Vout Y) inductor
M1 (X Y net9 VSS) nmos
M2 (Y X net9 VSS) nmos
I (net9 VSS) isource
M_v1 (Vcont X Vcont Vcont) nmos_varactor
M_v2 (Vcont Y Vcont Vcont) nmos_varactor
C1 (X net7) capaci... | |
We add CT to the tail node, as in Figure 16. What happens to the phase noise? | Adding `CT` to the tail node has a nonmonotonic effect on phase noise.
For small or moderate `CT`, the tail-node waveform changes and the flicker noise of `M1` and `M2` can be upconverted to phase noise unless the devices follow an ideal square law. For a certain range of `CT`, the cross-coupled devices enter class-C-... | subckt ckt_figure-16 VDD VSS X Y
M1 (X Y P VSS) nmos
M2 (Y X P VSS) nmos
L1 (VDD X) inductor
L2 (VDD Y) inductor
ISS (P VSS) isource
CT (P VSS) capacitor
ends ckt_figure-16 | |
Estimate the oscillation frequency of the circuit in Figure 17. | Start from the tank resonance
`omega0 = 1 / sqrt(L Cnode)`.
The coupling shifts the oscillation frequency away from resonance. The shift is
`Delta omega = alpha omega0 / (2 Q)`
where `alpha` is the coupling coefficient. In a typical large-signal design with nearly complete switching,
`alpha ~= I1 / ISS`,
so
`Del... | subckt ckt_figure-17 VDD VSS X1 Y1 X2 Y2
L1 (VDD X1) inductor
L2 (VDD Y1) inductor
M2 (X1 Y1 tail_in1 VSS) nmos
M3 (Y1 X1 tail_in1 VSS) nmos
I1 (tail_in1 VSS) isource
M1 (X1 Y2 tail_out1 VSS) nmos
M4 (Y1 X2 tail_out1 VSS) nmos
I2 (tail_out1 VSS) isource
L3 (VDD X2) inductor
L4 (V... |
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