module stringlengths 21 82.9k |
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module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output... |
module softmax(
input wire Clock,
input wire Reset,
input wire Start,
input wire [`DATALENGTH-1:0] Datain,
input wire [`INPUTMAX:0] N,
output reg [`DATALENGTH-1:0] Dataout
);
integer m;
// reg [`DATALENGTH-1:0] Dataout;
reg [`DATALENGTH-1:0] InputBuffer[2**`INPUTMAX - 1:0];
reg [`DAT... |
module softmax_tb(
);
reg Clock;
reg Reset;
reg Start;
reg [`DATALENGTH-1:0] Datain;
reg [`INPUTMAX-1:0] N;
wire [`DATALENGTH-1:0] Dataout;
softmax DUT (Clock, Reset, Start, Datain,N, Dataout);
initial begin
Clock = 1;
Reset = 1;
N = 3;
#10
Start = 1;
Reset = 0;
Datain = 32'h3f80000... |
module core(clk, rst); // Top-level entity(except core-tb)
input clk, rst;
wire write_r, read_r, PC_en, ac_ena, ram_ena, rom_ena;
wire ram_write, ram_read, rom_read, ad_sel;
wire [1:0] fetch;
wire [7:0] data, addr;
wire [7:0] accum_out, alu_out;
wire [7:0] ir_ad, pc_ad;
wire [4:0] reg_ad;
wire [2:0] ins;
ram RAM1(.d... |
module reg_32(in, data, write, read, addr, clk);
input write, read, clk;
input [7:0] in;
input [7:0] addr; //!Warning: addr should be reduced to 5 bits width, not 8 bits width.
//input [4:0] addr;
output [7:0] data;
reg [7:0] R[31:0]; //32Byte
wire [4:0] r_addr;
assign r_addr = addr[4:0];
assign data = (read)? R[r_a... |
module machine(ins, clk, rst, write_r, read_r, PC_en, fetch, ac_ena, ram_ena, rom_ena,ram_write, ram_read, rom_read, ad_sel);
input clk, rst; // clock, reset
input [2:0] ins; // instructions, 3 bits, 8 types
// Enable signals
output reg write_r, read_r, PC_en, ac_ena, ram_ena, rom_ena;
// ROM: where instructi... |
module ram(data, addr, ena, read, write);
input ena, read, write;
input [7:0] addr;
inout [7:0] data;
reg [7:0] ram[255:0];
assign data = (read&&ena)? ram[addr]:8'hzz; // read data from RAM
always @(posedge write) begin // write data to RAM
ram[addr] <= data;
end
endmodule |
module counter(pc_addr, clock, rst, en);
input clock, rst, en;
output reg [7:0] pc_addr;
always @(posedge clock or negedge rst) begin
if(!rst) begin
pc_addr <= 8'd0;
end
else begin
if(en) pc_addr <= pc_addr+1;
else pc_addr <= pc_addr;
end
end
endmodule |
module rom(data, addr, read, ena);
input read, ena;
input [7:0] addr;
output [7:0] data;
reg [7:0] memory[255:0];
// note: Decimal number in the bracket
initial begin
memory[0] = 8'b000_00000; //NOP
// [ins] [target_reg_addr] [from_rom_addr]
memory[1] = 8'b001_00001; //LDO s1
memory[2] = 8'b010_00001; //rom(6... |
module controller_purify(ins, clk, rst, write_r, read_r, PC_en, fetch, ac_ena, ram_ena, rom_ena,ram_write, ram_read, rom_read, ad_sel);
input clk, rst; // clock, reset
input [2:0] ins; // instructions, 3 bits, 8 types
// Enable signals
output reg write_r, read_r, PC_en, ac_ena, ram_ena, rom_ena;
// ROM: where... |
module accum( in, out, ena, clk, rst); // a register, to storage result after computing
input clk,rst,ena;
input [7:0] in;
output reg [7:0] out;
always @(posedge clk or negedge rst) begin
if(!rst) out <= 8'd0;
else begin
if(ena) out <= in;
else out <= out;
end
end
endmodule |
module core_tb_00 ;
reg rst ;
reg clk ;
core
DUT (
.rst (rst ) ,
.clk (clk ) );
// "Clock Pattern" : dutyCycle = 50
// Start Time = 0 ps, End Time = 10 ns, Period = 100 ps
initial
begin
clk = 1'b0 ;
# 150 ;
// 50 ps, single loop till start period.
repeat(99)
... |
module ins_reg(data, fetch, clk, rst, ins, ad1, ad2); // instruction register
input clk, rst;
input [1:0] fetch;
input [7:0] data;
output [2:0] ins;
output [4:0] ad1;
output [7:0] ad2;
reg [7:0] ins_p1, ins_p2;
reg [2:0] state;
assign ins = ins_p1[7:5]; //hign 3 bits, instructions
assign ad1 = ins_p1[4:0]; //low 5 bi... |
module addr_mux(addr, sel, ir_ad, pc_ad);
// Address multiplexer
// to choose address of instruction register or address of program counter
input [7:0] ir_ad, pc_ad;
input sel;
output [7:0] addr;
assign addr = (sel)? ir_ad:pc_ad;
endmodule |
module alu(alu_out, alu_in, accum, op);// arithmetic logic unit
// to perform arithmetic and logic operations.
input [2:0] op;
input [7:0] alu_in,accum;
output reg [7:0] alu_out;
parameter NOP=3'b000,
LDO=3'b001,
LDA=3'b010,
STO=3'b011,
PRE=3'b100,
ADD=3'b101,
LDM=3'b110,
HLT=3'b111;
alway... |
module random (
input clock,
output reg [30:0] lfsr
);
always @(posedge clock) begin
lfsr <= {lfsr[29:0], lfsr[30] ^~ lfsr[27]};
end
endmodule |
module row (
input clock,
input [0:0] shiftin,
output [0:0] shiftout
);
altshift_taps ALTSHIFT_TAPS_component (
.clock (clock),
.shiftin (shiftin),
.shiftout (shiftout)
);
defparam
ALTSHIFT_TAPS_component.intended_device_family = "C... |
module ring (
input clock,
input enable,
input shiftin,
output shiftout,
input [31:0] status
);
reg [21:0] counter = 0;
always @(posedge clock) begin
if (enable)
counter <= ~|counter ? 2472795 : counter - 1'b1;
end
altsyncram a... |
module DE10STDrsyocto(
/////////////////////////////////////////////// CLOCK ////////////////////////////////////////////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
/////////////////////////////////////////////// KEY ////////////... |
module DE10NANOrsyocto(
////////////////////////////////////////////////// ADC ////////////////////////////////////////////////
`ifdef USE_ADC
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,
`endif
/////////////////////////////////////////////... |
module s27 (
G1,
G2,
clk_net,
reset_net,
G3,
G0,
G17);
// Start PIs
input G1;
input G2;
input clk_net;
input reset_net;
input G3;
input G0;
// Start POs
output G17;
// Start wires
wire G1;
wire net_5;
wire net_15;
wire net_27;
wire G17;
wire reset_net;
wire net_14;
wire G3;
wire net_26;
wire clk_net;
wire net_13;
wi... |
module s349 (
B0,
A1,
B1,
A2,
A3,
blif_clk_net,
START,
B3,
A0,
blif_reset_net,
B2,
P7,
P5,
CNTVCON2,
P2,
P1,
CNTVCO2,
P0,
P6,
READY,
P3,
P4);
// Start PIs
input B0;
input A1;
input B1;
input A2;
input A3;
input blif_clk_net;
input START;
input B3;
input A0;
input blif_reset_net;
input B2;
// Start POs
output P7;
outp... |
module s386 (
v4,
v3,
v5,
v1,
v0,
blif_clk_net,
v2,
v6,
blif_reset_net,
v13_D_11,
v13_D_6,
v13_D_10,
v13_D_12,
v13_D_7,
v13_D_8,
v13_D_9);
// Start PIs
input v4;
input v3;
input v5;
input v1;
input v0;
input blif_clk_net;
input v2;
input v6;
input blif_reset_net;
// Start POs
output v13_D_11;
output v13_D_6;
output v... |
module c499 (
nid20,
nid6,
nid21,
nic7,
nid0,
nid11,
nid13,
nr,
nic0,
nid1,
nic4,
nid10,
nid31,
nid3,
nic1,
nid22,
nic3,
nid26,
nid23,
nid16,
nid17,
nid27,
nid9,
nic2,
nid7,
nic5,
nid30,
nic6,
nid14,
nid29,
nid8,
nid12,
nid5,
nid15,
nid25,
nid18,
nid28,
nid24,
nid4,
nid19,
nid2,
nod24,
nod6,
nod23,
nod31,
nod14,
nod11,... |
module c3_path (
nx1,
nx3,
nx2,
nx4,
nx33,
nx44,
nx12);
// Start PIs
input nx1;
input nx3;
input nx2;
input nx4;
// Start POs
output nx33;
output nx44;
output nx12;
// Start wires
wire nx1;
wire nx3;
wire nx33;
wire nx44;
wire nx12;
wire nx2;
wire nx4;
// Start cells
BUF_X1 inst_2 ( .Z(nx44), .A(nx4) );
INV_X1 inst... |
module c1355 (
n43gat,
n190gat,
n99gat,
n78gat,
n85gat,
n232gat,
n211gat,
n226gat,
n155gat,
n176gat,
n162gat,
n64gat,
n230gat,
n92gat,
n228gat,
n127gat,
n22gat,
n1gat,
n113gat,
n183gat,
n148gat,
n29gat,
n197gat,
n134gat,
n204gat,
n218gat,
n227gat,
n8gat,
n169gat,
n225gat,
n36gat,
n57gat,
n231gat,
n106gat,
n233gat,
n50g... |
module c432 (
n43gat,
n17gat,
n34gat,
n27gat,
n82gat,
n99gat,
n21gat,
n66gat,
n102gat,
n47gat,
n92gat,
n14gat,
n95gat,
n105gat,
n30gat,
n1gat,
n40gat,
n37gat,
n4gat,
n112gat,
n76gat,
n56gat,
n115gat,
n53gat,
n86gat,
n69gat,
n8gat,
n79gat,
n73gat,
n11gat,
n60gat,
n50gat,
n108gat,
n63gat,
n24gat,
n89gat,
n432gat,
n430gat... |
module s400 (
TEST,
FM,
blif_clk_net,
CLR,
blif_reset_net,
YLW1,
RED2,
GRN1,
RED1,
YLW2,
GRN2);
// Start PIs
input TEST;
input FM;
input blif_clk_net;
input CLR;
input blif_reset_net;
// Start POs
output YLW1;
output RED2;
output GRN1;
output RED1;
output YLW2;
output GRN2;
// Start wires
wire net_166;
wire net_107;... |
module c1908 (
n227,
n902,
n217,
n237,
n143,
n131,
n110,
n134,
n952,
n221,
n900,
n140,
n113,
n234,
n146,
n122,
n472,
n104,
n107,
n128,
n953,
n101,
n125,
n224,
n116,
n210,
n475,
n119,
n478,
n898,
n214,
n137,
n469,
n66,
n72,
n69,
n54,
n18,
n24,
n75,
n60,
n39,
n45,
n42,
n30,
n63,
n57,
n9,
n21,
n51,
n33,
n6,
n15,
n12,
n3,
... |
module s344 (
B0,
A1,
B1,
A2,
A3,
blif_clk_net,
START,
B3,
A0,
blif_reset_net,
B2,
P7,
P5,
CNTVCON2,
P2,
CNTVCO2,
P1,
P0,
READY,
P6,
P3,
P4);
// Start PIs
input B0;
input A1;
input B1;
input A2;
input A3;
input blif_clk_net;
input START;
input B3;
input A0;
input blif_reset_net;
input B2;
// Start POs
output P7;
outp... |
module c3_slack (
nx1,
nx3,
nx2,
nx4,
nx33,
nx44,
nx12);
// Start PIs
input nx1;
input nx3;
input nx2;
input nx4;
// Start POs
output nx33;
output nx44;
output nx12;
// Start wires
wire nx1;
wire nx3;
wire nx33;
wire nx44;
wire nx12;
wire nx2;
wire nx4;
// Start cells
BUF_X1 inst_2 ( .Z(nx44), .A(nx4) );
INV_X1 ins... |
module s27_path (
G1,
G2,
clk_net,
reset_net,
G3,
G0,
G17);
// Start PIs
input G1;
input G2;
input clk_net;
input reset_net;
input G3;
input G0;
// Start POs
output G17;
// Start wires
wire G1;
wire net_5;
wire net_15;
wire net_27;
wire G17;
wire reset_net;
wire net_14;
wire G3;
wire net_26;
wire clk_net;
wire net_1... |
module simple (
inp1,
inp2,
tau2015_clk,
out
);
// Start PIs
input inp1;
input inp2;
input tau2015_clk;
// Start POs
output out;
// Start wires
wire n1;
wire n2;
wire n3;
wire n4;
wire inp1;
wire inp2;
wire tau2015_clk;
wire out;
// Start cells
NAND2_X1 u1 ( .a(inp1), .b(inp2), .o(n1) );
DFF_X80 f1 ( .d(n2), .ck(ta... |
module s510 (
cnt509,
pcnt12,
cnt283,
cnt44,
cnt13,
pcnt241,
blif_clk_net,
pcnt6,
cnt261,
john,
pcnt17,
cnt511,
cnt272,
cnt21,
cnt567,
cnt10,
cnt45,
pcnt27,
cnt284,
cnt591,
blif_reset_net,
cclr,
vsync,
cblank,
csync,
pc,
csm,
pclr);
// Start PIs
input cnt509;
input pcnt12;
input cnt283;
input cnt44;
input cnt13;
input... |
module c17 (
nx1,
nx7,
nx3,
nx2,
nx6,
nx23,
nx22);
// Start PIs
input nx1;
input nx7;
input nx3;
input nx2;
input nx6;
// Start POs
output nx23;
output nx22;
// Start wires
wire net_1;
wire nx23;
wire nx1;
wire nx7;
wire nx3;
wire net_2;
wire nx22;
wire nx6;
wire net_0;
wire net_3;
wire nx2;
// Start cells
NAND2_X1... |
module c17_slack (
nx1,
nx7,
nx3,
nx2,
nx6,
nx23,
nx22);
// Start PIs
input nx1;
input nx7;
input nx3;
input nx2;
input nx6;
// Start POs
output nx23;
output nx22;
// Start wires
wire net_1;
wire nx23;
wire nx1;
wire nx7;
wire nx3;
wire net_2;
wire nx22;
wire nx6;
wire net_0;
wire net_3;
wire nx2;
// Start cells
NA... |
module s526 (
G1,
G2,
blif_clk_net,
blif_reset_net,
G0,
G198,
G213,
G148,
G214,
G199,
G147);
// Start PIs
input G1;
input G2;
input blif_clk_net;
input blif_reset_net;
input G0;
// Start POs
output G198;
output G213;
output G148;
output G214;
output G199;
output G147;
// Start wires
wire net_47;
wire net_176;
wire n... |
module c880 (
n201gat,
n189gat,
n17gat,
n72gat,
n152gat,
n255gat,
n159gat,
n85gat,
n267gat,
n87gat,
n116gat,
n74gat,
n55gat,
n90gat,
n210gat,
n96gat,
n228gat,
n260gat,
n143gat,
n80gat,
n207gat,
n153gat,
n268gat,
n171gat,
n1gat,
n135gat,
n111gat,
n237gat,
n183gat,
n130gat,
n29gat,
n261gat,
n101gat,
n59gat,
n138gat,
n149... |
module i2c_master_byte_ctrl
(
clk, my_addr, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in,
din, cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, sl_cont, scl_o,
scl_oen, sda_i, sda_o, sda_oen,slave_dat_req, slave_en, slave_dat_avail,
slave_act, slave_cmd_ack
);
//
// inputs & outputs
... |
module i2c_master_bit_ctrl (
input clk, // system clock
input rst, // synchronous active high reset
input nReset, // asynchronous active low reset
input ena, // core enable signal
input [15:0] clk_cnt, // clock prescale value
... |
module i2c_master_top
(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b1; // asynchronous reset level
parameter [6:0] DEFAULT_SLAVE_... |
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
parameter dwidth = 32;
parameter awidth = 32;
input clk, rst;
output [awidth -1:0] adr;
input [dwidth -1:0] din;
output [dwidth -1:0] dout;
output cyc, stb;
output we;
output [dw... |
module i2c_slave_model (scl, sda);
//
// parameters
//
parameter I2C_ADR = 7'b001_0000;
//
// input && outpus
//
input scl;
inout sda;
//
// Variable declaration
//
wire debug = 1'b1;
reg [7:0] mem [3:0]; // initiate memory
reg [7:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data o... |
module dcm12_100
(
// Inputs
input clkref_i
// Outputs
,output clkout0_o
);
wire clkref_buffered_w;
wire clkfb;
wire clk0;
wire clkfx;
// Clocking primitive
DCM_SP
#(
.CLKDV_DIVIDE(2.000),
.CLKFX_DIVIDE(3),
.CLKFX_MULTIPLY(25),
.CLKIN_PERIOD(83.3333333333),
.CL... |
module fpga_top
(
// Inputs
input ftdi_clk_i
,input ftdi_rst_i
,input sample_clk_i
,input sample_rst_i
,input mem_clk_i
,input mem_rst_i
,input clk_i
,input rst_i
,input ftdi_rxf_i
,inp... |
module reset_gen
(
input clk_i,
output rst_o
);
reg rst_q = 1'b1;
always @(posedge clk_i)
rst_q <= 1'b0;
assign rst_o = rst_q;
endmodule |
module spartan6_pll
(
// Inputs
input clkref_i
// Outputs
,output clkout0_o
);
wire clkref_buffered_w;
wire clkfbout_w;
wire pll_clkout0_w;
wire pll_clkout0_buffered_w;
// Input buffering
assign clkref_buffered_w = clkref_i;
// Clocking primitive
PLL_BASE
#(
.BANDWIDTH ... |
module dcm12_48
(
// Inputs
input clkref_i
// Outputs
,output clkout0_o
);
wire clkref_buffered_w;
wire clkfb;
wire clk0;
wire clkfx;
// Clocking primitive
DCM_SP
#(
.CLKDV_DIVIDE(2.000),
.CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4),
.CLKIN_PERIOD(83.3333333333),
.CLKO... |
module top
(
// Clocks
input CLK12
,output LD2_B
,output LD2_R
,output LD2_G
,output LD1_R
,output LD1_G
,output LD1_B
,input FTDI_CLK
,inout [7:0] FTDI_D
,input FTDI_RXF
,input ... |
module infrastructure #
(
parameter C_INCLK_PERIOD = 2500,
parameter C_RST_ACT_LOW = 1,
parameter C_INPUT_CLK_TYPE = "DIFFERENTIAL",
parameter C_CLKOUT0_DIVIDE = 1,
parameter C_CLKOUT1_DIVIDE = 1,
parameter C_CLKOUT2_DIVIDE = 16,
parameter C_CLKOUT3_DIVIDE = 8,
parameter C_CL... |
module cmd_prbs_gen_axi #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter ADDR_WIDTH = 29,
parameter DWIDTH = 32,
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
parameter PRBS_WIDTH = 64, // ... |
module axi4_tg #(
parameter C_AXI_ID_WIDTH = 4, // The AXI id width used for read and write
// This is an integer between 1-16
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
... |
module mcb_soft_calibration_top # (
parameter C_MEM_TZQINIT_MAXCNT = 10'h512, // DDR3 Minimum delay between resets
parameter C_MC_CALIBRATION_MODE = "CALIBRATION", // if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values, and does dynamic recal,
... |
module iodrp_controller(
input wire [7:0] memcell_address,
input wire [7:0] write_data,
output reg [7:0] read_data,
input wire rd_not_write,
input wire cmd_valid,
output wire rdy_busy_n,
input wire use_broadcast,
input wire sync_rst,
input wire ... |
module iodrp_mcb_controller(
input wire [7:0] memcell_address,
input wire [7:0] write_data,
output reg [7:0] read_data = 0,
input wire rd_not_write,
input wire cmd_valid,
output wire rdy_busy_n,
input wire use_broadcast,
input wire [4:0] drp_ioi_addr,
inp... |
module axi_mcb_cmd_translator #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_AD... |
module r_upsizer #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of converter.
... |
module axi_upsizer #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of converter.
... |
module axi_mcb_cmd_fsm
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire ... |
module axi_mcb_incr_cmd #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WID... |
module axi_mcb_cmd_arbiter #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MCB... |
module carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////... |
module carry #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
//////////////////////////////... |
module carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////... |
module axi_mcb_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_W... |
module mux_enc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_RATIO = 4,
// Mux select ratio. Can be any binary value (>= 1)
parameter integer C_SEL_WI... |
module comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter intege... |
module comparator_sel_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire ... |
module axi_mcb_r_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_W... |
module carry_latch_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
////////////////////////////////////////////////... |
module comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire ... |
module comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire ... |
module comparator_sel_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter i... |
module mcb_ui_top_synch #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_SYNCH_WIDTH = 0
)
(
//////////////////////////////////////... |
module comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integ... |
module axi_mcb_w_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
par... |
module axi_mcb_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_... |
module axi_mcb_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
... |
module axi_mcb_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_... |
module comparator #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire ... |
module command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
... |
module axi_mcb_wrap_cmd #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WID... |
module carry_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
////////////////////////////////////////////////////... |
module comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_... |
module axi_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
param... |
module ft245_fifo
(
// Inputs
input clk_i
,input rst_i
,input ftdi_rxf_i
,input ftdi_txe_i
,input [ 7:0] ftdi_data_in_i
,input inport_valid_i
,input [ 7:0] inport_data_i
,input outport_accept_i
// Outputs
,ou... |
module ft245_ram_dp
(
// Inputs
input clk0_i
,input rst0_i
,input [ 10:0] addr0_i
,input [ 7:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 10:0] addr1_i
,input [ 7:0] data1_i
,input wr1_i
... |
module ft245_axi_retime
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter AXI4_RETIME_WR_REQ = 1
,parameter AXI4_RETIME_WR_RESP = 1
,parameter AXI4_RETIME_RD_REQ = 1
,parameter AXI4_RETIME_RD_RE... |
module ft245_axi_retime_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter ADDR_W = 1
)
//----------------------------------------------------------... |
module ft245_axi
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RETIME_AXI = 1
,parameter AXI_ID = 8
)
//-----------------------------------------------------------------
// Ports
//-... |
module ft245_axi_fifo_8_32
(
// Inputs
input clk_i
,input rst_i
,input inport_valid_i
,input [ 7:0] inport_data_i
,input outport_accept_i
// Outputs
,output inport_accept_o
,output outport_valid_o
,output [ 31:0] out... |
module ft245_axi_fifo_32_8
(
// Inputs
input clk_i
,input rst_i
,input inport_valid_i
,input [ 31:0] inport_data_i
,input outport_accept_i
// Outputs
,output inport_accept_o
,output [ 7:0] outport_data_o
,output outp... |
module axi4_cdc_fifo39
(
// Inputs
input rd_clk_i
,input rd_rst_i
,input rd_pop_i
,input wr_clk_i
,input wr_rst_i
,input [ 38:0] wr_data_i
,input wr_push_i
// Outputs
,output [ 38:0] rd_data_o
,output r... |
module axi4_cdc_fifo39_ram_dp_32_5
(
// Inputs
input clk0_i
,input rst0_i
,input [ 4:0] addr0_i
,input [ 38:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 4:0] addr1_i
,input [ 38:0] data1_i
,input ... |
module axi4_cdc_fifo39_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 4
)
//-----------------------------------------------------------------
// Ports
//----------------------------... |
module axi4_cdc_fifo39_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------... |
module axi4_lite_tap
(
// Inputs
input clk_i
,input rst_i
,input inport_awvalid_i
,input [ 31:0] inport_awaddr_i
,input [ 3:0] inport_awid_i
,input [ 7:0] inport_awlen_i
,input [ 1:0] inport_awburst_i
,input inport_wvalid_i
,inp... |
module axi4_arb
(
// Inputs
input clk_i
,input rst_i
,input inport0_awvalid_i
,input [ 31:0] inport0_awaddr_i
,input [ 3:0] inport0_awid_i
,input [ 7:0] inport0_awlen_i
,input [ 1:0] inport0_awburst_i
,input inport0_wvalid_i
,in... |
module axi4_arb_onehot2
(
// Inputs
input clk_i
,input rst_i
,input hold_i
,input [1:0] request_i
// Outputs
,output [1:0] grant_o
);
//-----------------------------------------------------------------
// Registers / Wi... |
module axi4_retime
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter AXI4_RETIME_WR_REQ = 1
,parameter AXI4_RETIME_WR_RESP = 1
,parameter AXI4_RETIME_RD_REQ = 1
,parameter AXI4_RETIME_RD_RESP = ... |
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