module stringlengths 21 82.9k |
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module aib_top_wrapper_v2s
# (
parameter DATA_WIDTH = 78,
parameter TOTAL_CHNL_NUM = 24
)
(
//================================================================================================
// Reset Inteface
input i_conf_done, // AI... |
module c3lib_sync3_reset_ulvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 0 ),
// .SYNC_STAGES( 3 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n (... |
module c3lib_sync2_set_lvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 1 ),
// .SYNC_STAGES( 2 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n (... |
module c3lib_sync2_set_ulvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 1 ),
// .SYNC_STAGES( 2 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n ... |
module c3lib_sync2_reset_lvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// AYAR RESET SYNC VERSION WITH 2 deep synchronizer to mimic the behavioral model below Chandru Ramamurthy!!
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 0 ... |
module c3lib_sync3_set_ulvt_gate (
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
// c3lib_sync_metastable_behav_gate #(
//
// .RESET_VAL ( 1 ),
// .SYNC_STAGES( 3 )
//
// ) u_c3lib_sync2_reset_lvt_gate (
//
// .clk ( clk ),
// .rst_n (... |
module c3lib_ckg_lvt_8x(
tst_en,
clk_en,
clk,
gated_clk
);
input wire tst_en;
input wire clk_en;
input wire clk;
output wire gated_clk;
`ifdef BEHAVIORAL
var logic latch_d;
var logic latch_q;
// Formulate control signal
assign latch_d = clk_en | tst_en;
// Latch control... |
module c3lib_ckinv_svt_8x(
in,
out
);
input in;
output out;
`ifdef BEHAVIORAL
assign out = ~in;
`else
clock_inv u_clock_inv (.out(out), .in(in));
`endif
endmodule |
module aibio_clkdist_inv1_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input clkp,
input clkn,
//------Output pins------//
output clkp_b,
output clkn_b
);
wire clkp_b_1;
wire clkp_b_2;
wire clkn_b_1;
wire clkn_b_2;
`ifdef POST_WORST
localparam delay_1 = 100;
localpar... |
module aibio_rxclk_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input [4:0] dcc_p_pdsel,
input [4:0] dcc_p_pusel,
input [4:0] dcc_n_pdsel,
input [4:0] dcc_n_pusel,
input rxclkp,
input rxclkn,
input rxclk_en,
input rxclk_localbias_en,
input ipbias,
input [2:0] ibias_... |
module aibio_clkdist_inv2_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input clkp,
input clkn,
//------Output pins------//
output clkp_b,
output clkn_b
);
wire clkp_b_1;
wire clkp_b_2;
wire clkn_b_1;
wire clkn_b_2;
`ifdef POST_WORST
localparam delay_1 = 100;... |
module aibio_outclk_select
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [15:0]i_clkphb,
input [3:0]i_adapter_code,
input [3:0]i_soc_code,
//--------Output pins---------//
output o_clk_adapter,
output o_clk_soc
);
assign o_clk_adapter = ~ ... |
module aibio_txdll_cbb
(
//------Supply pins------//
input vddcq,
input vddc,
input vss,
//------Input pins------//
input ck_in,
input ck_loopback,
input ck_sys,
input ck_jtag,
input [1:0] inp_clksel,
input dll_en,
input dll_reset,
input [3:0] dll_biasctrl,
input [4:0] dll_capctrl,
input [3:0] dll_cksoc_... |
module aibio_inpclk_select_txdll
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input i_clk_in,
input i_clk_loopback,
input i_clk_sys,
input i_clk_jtag,
input [1:0] i_clksel,
//--------Output pins-----------//
output o_clkp,
output o_clkn
);
wi... |
module aibio_pulsegen_top
(
//---------Supply pins----------//
input vddcq,
input vss,
//---------Input pins----------//
input [15:0] i_clkph,
input [3:0] i_dll_even_phase1_sel,
input [3:0] i_dll_odd_phase1_sel,
input [3:0] i_dll_even_phase2_sel,
input [3:0] i_dll_odd_phase2_sel,
//--------Output ... |
module aibio_vref_cbb
(
//------Supply pins------//
input vddc,
input vddtx,
inout vss,
//------Input pins------//
input vref_en,
input calvref_en,
input [6:0] vref_bin_0,
input [6:0] vref_bin_1,
input [6:0] vref_bin_2,
input [6:0] vref_bin_3,
input [4:0] calvref_bin,
input gen1mode_en,
input pwrgood_in,
... |
module en_logic_xxpad
(
input data,
input pwrgoodtx,
input pwrgood,
input rst_strap,
input wk_pu_en,
input wk_pd_en,
input compen_n,
input compen_p,
input tx_en,
input sdr_mode_en,
input tx_async_en,
input gen1_en,
output reg pu_en_gen1,
output reg pd_en_gen1,
output reg pu_en_gen2,
ou... |
module pad_out_logic
(
input rst,
input pu_gen1,
input pd_gen1,
input pu_gen2,
input pd_gen2,
input wkpu,
input wkpd,
output reg data_out
);
always @(rst,wkpu,wkpd,pu_gen1,pd_gen1,pu_gen2,pd_gen2)
begin
if(rst)
begin
data_out = 1'b0;
end
else if(wkpu)
begin
data_out = 1'b1;
end
else if(w... |
module aibio_pvtmon_3to8dec(
//-----Supply Pins---//
input logic vdd,
input logic vss,
//-----Input Pins---//
input logic [2:0]sel,
//----Output pins----//
output logic [7:0]out
);
always @(sel)
begin
case(sel)
3'b000 : out=8'b0000_0001;
3'b001 : out=8'b0000_0010;
3'b0... |
module mux2x1 (
//-----Supply Pins---//
input logic vdd,
input logic vss,
//-----Input Pins---//
input logic [1:0]in,
input logic s,
//----Output pins----//
output logic out
);
always @(in or s)
begin
if(s)
out= in[1];
else
out=in[0];
end
endmodule |
module DFF(
//-----Supply Pins---//
input logic vdd,
input logic vss,
//-----Input Pins---//
input logic clk,
input logic rb,
input logic d,
//----Output pins----//
output logic o
);
initial o <= 0;
always @(posedge clk or negedge rb )
begin
if(rb == 1'b0)
begin
o = 'd0;
end
else
begi... |
module aibio_decoder3x8
(
//---------Supply pins---------//
input vddcq,
input vss,
//--------Input pins----------//
input [2:0] i,
//--------Output pins---------//
output reg [7:0] o
);
always @(i)
case(i)
3'b000 : o = 8'b0000_0001;
3'b001 : o = 8'b0000_0010;
3'b010 : o = 8'b0000_0100;
... |
module aibio_decoder2x4
(
//----------Supply pins------------//
input vddcq,
input vss,
//----------Input pins------------//
input [1:0] i,
//----------Output pins----------//
output reg [3:0] o
);
always @(i)
case(i)
2'b00 : o = 4'b0001;
2'b01 : o = 4'b0010;
2'b10 : o = 4'b0100;
2'b11 : o ... |
module aibio_outclk_mux16x1
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [15:0]i_clkph,
input [3:0]i_clksel,
//--------Output pins---------//
output o_clk
);
wire [3:0] clk_sel_stg1;
wire [3:0] clk_sel_stg2;
wire [3:0] clkphsel_stg2;
aibio_dec... |
module aibio_pimux4x1
(
//----------Supply pins----------//
input vddcq,
input vss,
//---------Input pins-----------//
input [3:0]i_clkph,
input [3:0]i_clkph_sel,
//---------Output pins----------//
output o_clkph
);
assign o_clkph = (i_clkph_sel == 4'b0001) ? i_clkph[0] :
(i_clkph_sel == 4'b0010) ? i_... |
module aibio_clock_dist
(
//---------Supply pins------------//
input vddcq,
input vss,
//---------Input pins------------//
input i_piclk_even_in,
input i_piclk_odd_in,
input i_loopback_en,
//---------Output pins----------//
output o_piclk_even_loopback,
output o_piclk_odd_loopback
);
assign o_p... |
module aibio_outclk_select
(
//----------Supply pins-----------//
input vddcq,
input vss,
//----------Input pins-----------//
input [3:0] i_adapter_code,
input [3:0] i_soc_code,
input [15:0] i_clkphb,
//----------Output pins-----------//
output o_clk_adapter,
output o_clk_soc
);
wire clk_adapte... |
module aibio_se_to_diff
(
input vddcq,
input vss,
input i,
output o,
output o_b
);
assign o = i;
assign o_b = ~i;
endmodule |
module aibio_auxch_Schmit_trigger
(
//-------Supply pins----------//
input vddc,
input vss,
//-------Input pin-----------//
input vin,
//-------Output pin---------//
output vout
);
assign vout=vin;
endmodule |
module aibio_auxch_cbb
(
//----supply pins----//
input vddc,
input vss,
//-----input pins-------------//
input dual_mode_sel,
input i_m_power_on_reset,
input m_por_ovrd,
input m_device_detect_ovrd,
input [2:0]rxbuf_cfg,
input powergood,
input gen1mode_en,
//-----inout pins-----------------//
... |
module aibio_pulsegen_phsel_halfside
(
//---------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [7:0]i_clkph,
input [2:0]i_ph1sel,
input [2:0]i_ph2sel,
//--------Output pins---------//
output o_clkph1,
output o_clkph2
);
aibio_pulsegen_mux8x1 I0
(
.... |
module aibio_inpclk_select_txdll
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input i_clk_in,
input i_clk_loopback,
input i_clk_sys,
input i_clk_jtag,
input [1:0] i_clksel,
//--------Output pins-----------//
output o_clkp,
output o_clkn
);
/*
... |
module aibio_pulsegen_muxfinal
(
//-------Supply pins--------//
input vddcq,
input vss,
//-------Input pins--------//
input [1:0]i_clkph1_even,
input [1:0]i_clkph1_odd,
input [1:0]i_clkph1_sel_even,
input [1:0]i_clkph1_sel_odd,
input [1:0]i_clkph2_even,
input [1:0]i_clkph2_odd,
input [1:0]i_clkp... |
module aibio_pulsegen_oddevn_halfside
(
//---------Supply pins----------//
input vddcq,
input vss,
//---------Input pins----------//
input [7:0]i_clkph,
input [2:0]i_evn_ph1_sel,
input [2:0]i_evn_ph2_sel,
input [2:0]i_odd_ph1_sel,
input [2:0]i_odd_ph2_sel,
//--------Output pins-----------//
outp... |
module aibio_pulsegen_mux8x1
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input [7:0] i_clkph,
input [2:0] i_clksel,
//-------Output pins---------//
output wor o_clkph
// output o_clkph //For LEC comment above line and uncomment this line
);
wire [7:0... |
module aibio_pulsegen_mux2x1
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input [1:0] i_clkph,
input [1:0] i_clkph_sel,
//-------Output pins--------//
output o_clkph
);
assign o_clkph = (i_clkph_sel == 2'b01) ? i_clkph[0] :
(i_clkph_sel == 2'b10) ... |
module aibio_txdll_cbb
(
//------Supply pins------//
input vddcq,
input vss,
//------Input pins------//
input ck_in,
input ck_loopback,
input ck_sys,
input ck_jtag,
input [1:0] inp_cksel,
input dll_en,
input dll_reset,
input [3:0] dll_biasctrl,
input [4:0] dll_capctrl,
input [3:0] dll_cksoc_code,
input [... |
module aibio_pulsegen_top
(
//---------Supply pins----------//
input vddcq,
input vss,
//---------Input pins----------//
input [15:0] i_clkphb,
input [3:0] i_dll_even_phase1_sel,
input [3:0] i_dll_odd_phase1_sel,
input [3:0] i_dll_even_phase2_sel,
input [3:0] i_dll_odd_phase2_sel,
//--------Output... |
module aibio_pioddevn_top
(
//--------Supply pins-----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [15:0]i_clkphb,
input [7:0]i_picode_evn,
input [7:0]i_picode_odd,
input i_pbias,
input i_nbias,
input [2:0]i_bias_trim,
input [1:0]i_capsel,
input [1:0]i_capselb,
in... |
module aibio_pi_decode_sync
(
//---------Supply pins--------//
input vddcq,
input vss,
//---------Input pins----------//
input i_clk_en,
input i_clk_sync,
input [7:0] i_picode,
input i_reset,
input i_update,
//---------Output pins---------//
output [7:0] o_clkphsel_stg1_synced,
output [1:0] o_... |
module aibio_pi_decode
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input [7:0] i_picode,
//--------Output pins----------//
output [7:0]o_clkphsel_stg1,
output [1:0]o_clkphsel_stg2,
output [7:0]o_pimixer
);
wire [3:0] picode_plus1;
wire mix_on;
wir... |
module aibio_pioddevn_mixer_top
(
//--------Supply pins--------//
input vddcq,
input vss,
//--------Input pins---------//
input i_clkevn_evn,
input i_clkevn_odd,
input i_clkodd_evn,
input i_clkodd_odd,
input i_pien,
input [7:0]i_pimixer_evn,
input [7:0]i_pimixer_odd,
input [15:0]i_clkph,
inp... |
module aibio_half_adder
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input a,
input b,
//------Output pins---------//
output c,
output s
);
assign s = a^b;
assign c = a&&b;
endmodule |
module aibio_pi_phsel_halfside
(
//---------Supply pins--------//
input vddcq,
input vss,
//--------Input pins---------//
input [1:0]i_cap_sel,
input [1:0]i_cap_selb,
input [3:0]i_clk_evnph,
input [3:0]i_clk_evnphsel_stg1,
input i_clk_evnphsel_stg2,
input [3:0]i_clk_oddph,
input [3:0]i_clk_oddph... |
module aibio_4bit_plus1
(
//-------Supply pins------//
input vddcq,
input vss,
//-------Input pins--------//
input [3:0] i_code,
//-------Output pins-------//
output [3:0] o_code
);
wire net13;
wire net14;
wire net15;
wire net27;
aibio_half_adder I0
(
.vddcq(vddcq),
.vss(vss),
.a(i_code[0]),... |
module aibio_inpclk_select
(
//--------Supply pins----------//
input vddcq,
input vss,
//--------Input pins-----------//
input i_clk_inp,
input i_clk_inn,
input i_clk_loopback,
input i_clk_sys,
input i_clk_jtag,
input i_clk_cdr_inp,
input i_clk_cdr_inn,
input [1:0] i_clksel,
//--------Output... |
module aibio_pi_phsel_quarter
(
//--------Supply pins-------------//
input vddcq,
input vss,
//--------Input pins-------------//
input [3:0] i_clkph,
input [3:0] i_clkphsel_stg1,
input i_clkphsel_stg2,
input i_pbias,
input [2:0] i_pbias_trim,
input i_nbias,
input [2:0] i_nbias_trim,
input [1:0... |
module aibio_pioddevn_phsel_half
(
//--------Supply pins---------//
input vddcq,
input vss,
//--------Input pins----------//
input [1:0]i_cap_sel,
input [1:0]i_cap_selb,
input [3:0]i_clk_evnph,
input [3:0]i_clk_evnphsel_stg1_evn,
input [3:0]i_clk_evnphsel_stg1_odd,
input i_clk_evnphsel_stg2_evn,
... |
module aibio_cdr_detect
(
//----------Supply pins------------//
input vddcq,
input vss,
//---------Input pins--------------//
input i_cdr_clk,
input i_piclk_90,
input i_piclk_180,
input i_sdr_mode,
input i_reset,
//---------Output pins-------------//
output reg o_cdr_phdet
);
wire clk_int;
wi... |
module aibio_3bit_bin_to_therm
(
//--------Supply pins---------//
input vddcq,
input vss,
//-------Input pins----------//
input [2:0] b,
//-------Outptu pins---------//
output reg [6:0] t
);
always @(b)
case(b)
3'b000 : t = 7'b000_0000;
3'b001 : t = 7'b000_0001;
3'b010 : t = 7'b000_0011;... |
module aibio_bias_trim
(
//-------Supply pins---------//
input vddcq,
input vss,
//-------Input pins---------//
input [2:0]i_bias_trim,
input i_pbias,
input i_nbias,
//--------Output pins----------//
output [2:0]o_pbias_trim,
output [2:0]o_nbias_trim
);
//assign o_pbias_trim = ~(i_bias_trim);
... |
module aib_avmm_glue_logic(
// Inputs
input [23:0] i_waitreq_ch, // Wait request of each channel
input [23:0] i_rdatavld_ch, // Read data valid of each channel
input [31:0] o_rdata_ch_0, // Channel 0 read data bus
input [31:0] o_rdata_ch_1, // Channel 1 read data bus
input [31:0] o_rdata_ch_2, ... |
module aib_fifo_rdata_ored #(
parameter DWIDTH = 80, // FIFO Input data width
parameter DEPTH = 3 // FIFO Depth
)
(
// Output
output reg [DWIDTH-1:0] fifo_rdata,
// Input
input [DEPTH-1:0][DWIDTH-1:0] fifo_out_sel
);
integer n;
always @(*)
begin
fifo_rdata = {DWIDTH{1'b0}};
for(n = 0; n < DEPTH; n ... |
module aib_rxfifo_rd_dpath #(
parameter DWIDTH = 320,
parameter DEPTH = 16,
parameter DEPTH4 = DEPTH*4
)
(
output [DWIDTH-1:0] rdata_sync_ff, // Read data synchronized
input [DEPTH4-1:0] fifo_rd_en, // FIFO element selector
input [1:0] r_fifo_mode, // FIFO mode
input m_gen2_mode, /... |
module aib_txfifo_rd_dpath #(
parameter DINW = 320,
parameter DOUTW = 80,
parameter DEPTH = 16,
parameter DEPTH4 = DEPTH * 4
)
(
output [DOUTW-1:0] rdata_sync_ff, // Read data synchronized
input [DEPTH4-1:0] fifo_rd_en, // FIFO element selector
input [DEPTH-1:0][DINW-1:0] fifo_data_as... |
module aib_tx_bert #(
parameter [0:0] BERT_BUF_MODE_EN = 1 // Enables Buffer mode for BERT
)
(
input clk, // TX BERT clock
input rstn, // Active low asynchronous reset
input [ 3:0] tx_start_pulse, // Start pulse to enable LFSR and Pattern
input [ 3:0] tx_rst_pulse, ... |
module emib_ch_m2s2 (
inout [101:0] s_aib,
inout [101:0] m_aib
);
genvar i;
generate
for (i=0; i<102; i=i+1) begin: aib_io_conn
aliasv xaliasv95 (
.PLUS(m_aib[i]),
.MINUS(s_aib[101-i])
);
end
endgenerate
endmodule |
module emib_m2s2 # ( parameter ROTATE = 0) (
inout [101:0] s_ch0_aib,
inout [101:0] s_ch1_aib,
inout [101:0] s_ch2_aib,
inout [101:0] s_ch3_aib,
inout [101:0] s_ch4_aib,
inout [101:0] s_ch5_aib,
inout [101:0] s_ch6_aib,
inout [101:0] s_ch7_aib,
inout [101:0] s_ch8_aib,
inout [101:0] s_ch9_aib,
inout [... |
module emib_ch_m2s1 (
inout [95:0] s_aib,
inout [101:0] m_aib
);
wire tie_low = 1'b0;
aliasv xaliasv101 (
.PLUS(m_aib[101]),
.MINUS()
);
aliasv xaliasv100 (
.PLUS(m_aib[100]),
.MINUS()
);
aliasv xaliasv99 (
.PLUS(m_aib[99]),
.MINUS()
);
aliasv xaliasv98 (
.PLUS(m_aib[98]),
.MINUS()
);
... |
module emib_ch_m1s2 (
inout [95:0] m_aib,
inout [101:0] s_aib
);
wire tie_low = 1'b0;
wire tie_hi = 1'b1;
aliasv xaliasv101 (
.MINUS(s_aib[101]),
.PLUS()
);
aliasv xaliasv100 (
.MINUS(s_aib[100]),
.PLUS()
);
aliasv xaliasv99 (
.MINUS(s_aib[99]),
.PLUS()
);
aliasv xaliasv98 (
.MINUS(s_aib[... |
module emib_m2s1 (
inout [95:0] s_ch0_aib,
inout [95:0] s_ch1_aib,
inout [95:0] s_ch2_aib,
inout [95:0] s_ch3_aib,
inout [95:0] s_ch4_aib,
inout [95:0] s_ch5_aib,
inout [95:0] s_ch6_aib,
inout [95:0] s_ch7_aib,
inout [95:0] s_ch8_aib,
inout [95:0] s_ch9_aib,
inout [95:0] s_ch10_aib,
inout [95:... |
module lut_C
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 182;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010001100101;
2: y = 16'b0000100011001000;
3: y = 16'b0000110100101001;
4: y = 16'... |
module lut_Cs
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 172;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010010100110;
2: y = 16'b0000100101001010;
3: y = 16'b0000110111101011;
4: y = 16... |
module lut_D
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 162;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010011101111;
2: y = 16'b0000100111011100;
3: y = 16'b0000111011000101;
4: y = 16'... |
module lut_Ds
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 153;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010100111001;
2: y = 16'b0000101001101111;
3: y = 16'b0000111110100001;
4: y = 16... |
module lut_E
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 144;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010110001011;
2: y = 16'b0000101100010100;
3: y = 16'b0001000010011000;
4: y = 16'... |
module lut_F
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 136;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000010111011110;
2: y = 16'b0000101110111001;
3: y = 16'b0001000110001110;
4: y = 16'... |
module lut_Fs
(
input [7:0] x,
output [7:0] x_max,
output reg [15:0] y
);
assign x_max = 128;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011000111011;
2: y = 16'b0000110001110011;
3: y = 16'b0001001010100011;
4: y = 16... |
module lut_G
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 121;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011010010111;
2: y = 16'b0000110100101001;
3: y = 16'b0001001110110011;
4: y = 16'... |
module lut_Gs
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 114;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011011111101;
2: y = 16'b0000110111110101;
3: y = 16'b0001010011100011;
4: y = 16... |
module lut_A
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 108;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011101100000;
2: y = 16'b0000111010111001;
3: y = 16'b0001011000000110;
4: y = 16'... |
module lut_As
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 101;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000011111100001;
2: y = 16'b0000111110111011;
3: y = 16'b0001011110000101;
4: y = 16... |
module lut_B
(
input [6:0] x,
output [6:0] x_max,
output reg [15:0] y
);
assign x_max = 96;
always @ (*)
case (x)
0: y = 16'b0000000000000000;
1: y = 16'b0000100001001001;
2: y = 16'b0001000010001001;
3: y = 16'b0001100010110111;
4: y = 16'b... |
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