repo_name stringlengths 6 79 | path stringlengths 6 236 | copies int64 1 472 | size int64 137 1.04M | content stringlengths 137 1.04M | license stringclasses 15
values | hash stringlengths 32 32 | alpha_frac float64 0.25 0.96 | ratio float64 1.51 17.5 | autogenerated bool 1
class | config_or_test bool 2
classes | has_no_keywords bool 1
class | has_few_assignments bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
malkadi/FGPU | RTL/floating_point/fmul.vhd | 1 | 10,488 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | gpl-3.0 | 51eadc17385f1b2f8c673bdac989a84e | 0.628242 | 3.230059 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_float_8ALUs_2AXI.vhd | 1 | 23,540 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 4bf42eec09d2799d79016980c8054233 | 0.568734 | 3.717038 | false | false | false | false |
Kinxil/VHDL_Projects | Mandelbrot/cpt_iter.vhd | 1 | 884 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
entity cpt_iter is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
inib : in std_logic;
endcalcul : in STD_LOGIC;
maxiter : in STD_LOGIC;
iter : out STD_LOGIC_VECTOR(ITER_... | gpl-3.0 | 47e1e04b1d0e8c2f67d10dec8ff46bed | 0.683258 | 2.736842 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_fsqrt_uitofp.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 20fde2ec2a04026663c15c3fa01642d6 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | RTL/CU_instruction_dispatcher.vhd | 1 | 10,173 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
------------------------------------------------------------------------------------... | gpl-3.0 | a9a2f45df88b09bf35c95c9cee5bb24b | 0.497788 | 3.230549 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/xilinx/xil_SystemMonitor_Virtex6.vhdl | 2 | 5,256 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: System Monitor wrapper f... | agpl-3.0 | d1eef6130d2fe5c57ac20109d57f6d82 | 0.509513 | 3.268657 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_2CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 1426be4e6fdf5b9c0d6fe9b113384af1 | 0.567707 | 3.729005 | false | false | false | false |
jpidancet/mips | rtl/mips_defs.vhd | 1 | 3,801 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
package mips_defs is
subtype mips_opcode_type is std_logic_vector(5 downto 0);
subtype mips_func_type is std_logic_vector(5 downto 0);
constant OP_SPECIAL : std_logic_vector(5 downto 0) := "000000";
c... | isc | aa8023f06d541d6a8209ed69329f0d49 | 0.552486 | 3.726471 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd | 2 | 136,312 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | 6c7a32c885f78d562f59ef0102b884af | 0.954267 | 1.831141 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/nf/nf_transmitter.vhd | 1 | 3,866 | -------------------------------------------------------------------------------
--! @file nf_transmitter.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-23
--! @brief NanoFIP transmitter.
--------------------------------------------------------... | mit | 0496a48fdbd4ed236824656e758d6b3b | 0.433523 | 4.052411 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fmul_2AXI.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 722b2b97158fd9d1354d6d49ccae1ef7 | 0.567707 | 3.729005 | false | false | false | false |
Ttl/fsm_uart | examples/echo_tb.vhd | 1 | 2,605 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY echo_tb IS
END echo_tb;
ARCHITECTURE behavior OF echo_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT echo
PORT(
rx : IN std_logic;
tx : OUT std_logic;
clk : IN std_logic
);
END COMP... | lgpl-3.0 | ee7e4efd33d50dc750c73f24b5769962 | 0.583877 | 2.884828 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_1CU_min_area.vhd | 1 | 23,421 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | e774854ff2b9448a104943e4341ac93c | 0.569105 | 3.711139 | false | false | false | false |
Ttl/fsm_uart | uart.vhd | 1 | 7,839 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity uart is
generic (
CLK_FREQ : integer := 32; -- Main frequency (MHz)
SER_FREQ : integer := 9600; -- Baud rate (bps)
PARITY_BIT : boolean := true -- Parity bit enable/disable
);
port (
-- Control
clk ... | lgpl-3.0 | 02bbacdb7bdb41ba664a0c53692a59a3 | 0.57367 | 2.679084 | false | false | false | false |
jcowgill/cs-dacs-robot | Robot/DecoderTB.vhd | 1 | 1,635 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Decoder_Decoder_sch_tb IS
END Decoder_Decoder_sch_tb;
ARCHITECTURE behavioral OF Decoder_Decoder_sch_tb IS
COMPONENT Decoder
PORT ( RF : OUT STD_LOGIC;
RR : OUT STD_LOGIC;
LF : OUT STD_LOGIC... | apache-2.0 | c3f91044781e9a8336a5e37408280b58 | 0.480122 | 3.874408 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_8Banks.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 0be3fc6835d9c4a1bf0e60fca3523011 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_4AXI_2TAGM.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | cb834c4f72b1f9d0f09bd62df4ce65c2 | 0.567707 | 3.729005 | false | false | false | false |
jpidancet/mips | rtl/register_file.vhd | 1 | 1,843 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity register_file is
port (clk : in std_logic;
rst : in std_logic;
a1 : in std_logic_vector(4 downto 0);
a2 : in std_logic_vector(4 do... | isc | 3442883408312c96b292fcae26b3e35b | 0.502984 | 3.47081 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/io/io_TimingCounter.vhdl | 2 | 3,246 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: optimized down-counter t... | agpl-3.0 | 51a84f8048fd9a5d31d98a0c9be7b9c8 | 0.609057 | 3.602664 | false | false | false | false |
malkadi/FGPU | RTL/gmem_cntrl_tag.vhd | 1 | 58,217 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
------------------------------------------------------------------------------------... | gpl-3.0 | d7ad03f8bc1b5e86c207f04514c00d70 | 0.535892 | 3.321182 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fslt_2AXI_4CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | d5730168d4285270a67fec42f00dcb43 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | RTL/floating_point/fsqrt.vhd | 1 | 10,200 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | gpl-3.0 | 461b8c766e2b18b936eeb20fc880566e | 0.625784 | 3.248408 | false | false | false | false |
preusser/q27 | src/vhdl/queens/msg_tap.vhdl | 2 | 3,596 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | 07724aea8e5ffb90d37be67eed5a4db8 | 0.521413 | 3.947311 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_8Stations.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | b6136fdfb9d6774cf3b47bc091e8d20c | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_6Stations_2AXI.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 2c026ddbdfc513ba5fa5198546e4fa19 | 0.567707 | 3.729005 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_pkg.vhd | 2 | 123,927 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | 71790a5e36c1d3a7a83955d86649eab8 | 0.953424 | 1.829424 | false | false | false | false |
joalcava/sparcv8-monocicle | DM.vhd | 1 | 987 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DataMemory is
Port ( enableMem : in STD_LOGIC;
reset : in STD_LOGIC;
cRD : in STD_LOGIC_VECTOR (31 downto 0);
address : in STD_LOGIC_VECTOR (31 downto 0);
wrEnMem : in STD_LOGIC;
d... | gpl-3.0 | 791f6fe907e0ee0109301231942cbf63 | 0.630193 | 3.194175 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_Atomic_2AXI.vhd | 1 | 23,372 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 3399b5be760eb0668a77ebe0bac91ba3 | 0.568971 | 3.706899 | false | false | false | false |
joalcava/sparcv8-monocicle | Sparcv8Monocicle.vhd | 1 | 7,979 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Sparcv8Monocicle is
Port ( CLK : in STD_LOGIC;
RST: in STD_LOGIC;
R : out STD_LOGIC_VECTOR(31 downto 0)
);
end Sparcv8Monocicle;
architecture Behavioral of Sparcv8Monocicle is
---Componentes
COMPONENT windows_manager
PORT(
cwp : IN std_log... | gpl-3.0 | 655d9ed71284db31feb668f2b6b5ba44 | 0.599825 | 2.837482 | false | false | false | false |
malkadi/FGPU | HW/sources/IPs/FGPU_2.1/hdl/FGPU_v2_1.vhd | 1 | 18,906 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
library xil_defaultlib;
use xil_defaultlib.all;
---------------------------------------------... | gpl-3.0 | 82be568a0f583d9fafc3942274b061b9 | 0.59177 | 2.758389 | false | false | false | false |
preusser/q27 | src/vhdl/queens/queens_slice0_tb.vhdl | 1 | 3,447 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | e97808ced03b3916b71330b31e9a4891 | 0.527125 | 3.742671 | false | false | false | false |
jpidancet/mips | rtl/cpu_execute.vhd | 1 | 2,970 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
library work;
use work.mips_defs.ALL;
entity cpu_execute is
port (rt : in std_logic_vector(4 downto 0);
rd : in std_logic_vector(4 downto 0);
shamt : in ... | isc | c9d1b9ba3debdab59f955e6e95bef9eb | 0.516498 | 3.822394 | false | false | false | false |
preusser/q27 | src/vhdl/top/dnk7_f5/dnk7_queens0.vhdl | 1 | 27,860 | library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity dnk7_queens0 is
generic (
-- Design Parameters
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 240;
COUNT_CYCLES : boolean := false;
SENTINEL : std_logic_vector(7 downto 0) := x"FA"; -... | agpl-3.0 | e0bbd69eccd385ca2a3cbf7d58d548dd | 0.479182 | 3.763339 | false | false | false | false |
viccuad/fpga-thingies | cronometer/debouncer.vhd | 1 | 2,643 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY debouncer IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
x: IN std_logic;
xDeb: OUT std_logic;
xDebFallingEdge: OUT std_logic;
xDebRisingEdge: OUT std_logic
);
END debouncer;
ARCHITECTURE debouncerArch of d... | gpl-3.0 | 5e3cca487ce1f6ec82745d503eb9aa13 | 0.565645 | 3.944776 | false | false | false | false |
preusser/q27 | src/vhdl/top/xilinx/xupv5_queens_uart.vhdl | 1 | 4,404 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | 0a51b1c82c035509d28ad574df0f87aa | 0.50931 | 4.115888 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fdiv_fadd.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 7eac373ccecc914faa048086d4747c18 | 0.567707 | 3.729005 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_bindec.vhd | 2 | 10,218 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | 755aafd6055cb72c60fdc99e097ce1a8 | 0.925034 | 1.903148 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_tx_osc.vhd | 1 | 12,737 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | f5446c81c184739860128388445b44d6 | 0.28217 | 5.148343 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_LMEM.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 14de120d09595a397e92ed0aa2747f78 | 0.567707 | 3.729005 | false | false | false | false |
kennethlyn/fpga-image-example | hdl_nodes/adder/adder.srcs/sources_1/dyplo_user_logic_adder.vhd | 1 | 5,765 | -- File: dyplo_user_logic_stub.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property ... | gpl-2.0 | 9686c6a74fcedd114484c1dc2b6506cf | 0.601876 | 3.523256 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_prim_width.vhd | 2 | 71,859 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | 95f62ef4a2158c73890aec60bd92daa8 | 0.951767 | 1.8415 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_4_CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | b1e1ad1e8b6f4cd7100178c94a0b473b | 0.567707 | 3.729005 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/nf/nf_tx_registers.vhd | 1 | 7,537 | -------------------------------------------------------------------------------
--! @file nf_tx_registers.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-23
--! @brief NanoFIP transmitter registers.
---------------------------------------------... | mit | 36bf44d5698aad2a6ccb6b1b404cb241 | 0.476051 | 3.219564 | false | false | false | false |
malkadi/FGPU | RTL/CU_scheduler.vhd | 1 | 53,659 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
-----------------------------------------------------------------------------... | gpl-3.0 | 8aa9352c2fd2886627bf7b5e26c32574 | 0.469763 | 3.406056 | false | false | false | false |
Kinxil/VHDL_Projects | Mandelbrot/Colorgen.vhd | 1 | 74,598 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Colorgen is
Port ( iters : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
itermax : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
color : out STD_LOGIC_VECTOR (bit_per_pixel-1 do... | gpl-3.0 | 643abb10fc2df6ddca4b091048626b6c | 0.667256 | 3.59266 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_6Stations.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | a4743406565e4ef32af5eff74cc16d9d | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_SubInteger.vhd | 1 | 23,421 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 705bfd499fa826d4c87b4001492ef460 | 0.569105 | 3.711139 | false | false | false | false |
preusser/q27 | src/vhdl/top/xilinx/sdrc_queens_master.vhdl | 1 | 14,514 | library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity sdrc_queens_master is
generic (
-- Design Parameters
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 90;
COUNT_CYCLES : boolean := false;
-- Local Clock Parameters
CLK_FREQ : FREQ :... | agpl-3.0 | 4c5d4802f60c1802fd7309264b042f7e | 0.470856 | 3.633951 | false | false | false | false |
kennethlyn/fpga-image-example | hdl_nodes/subtractor/subtractor.srcs/sim_1/backplane_simulator.vhd | 3 | 30,931 | -- File: backplane_simulator.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property la... | gpl-2.0 | a6334997d2da6a7dfcb4c72555827e87 | 0.473342 | 4.011543 | false | false | false | false |
jpidancet/mips | rtl/alu.vhd | 1 | 2,236 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
library work;
use work.mips_defs.ALL;
entity alu is
port (op : in alucontrol_type;
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
... | isc | dafe1ca6ead2f7f61ff3dd01e7641e2e | 0.451699 | 3.848537 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_output_block.vhd | 2 | 17,242 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | e3cca48a2dc3a1bc405f9708ee4f4ad1 | 0.93742 | 1.883342 | false | false | false | false |
malkadi/FGPU | RTL/CU_mem_cntrl.vhd | 1 | 48,424 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
-----------------------------------------------------------------------------... | gpl-3.0 | 3f09e7127002a8ea848484ea81a4f72d | 0.519639 | 3.393651 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_no_fdiv_area_estimation.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | a44de22ad437649e4d322fd01f514bd2 | 0.567707 | 3.729005 | false | false | false | false |
joalcava/sparcv8-monocicle | register_file.vhd | 1 | 1,081 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity register_file is
Port( Wren : in STD_LOGIC;
rst : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
data : in STD_LOGIC_VECT... | gpl-3.0 | 74c45b379c857e7e31b66915f8c49de0 | 0.623497 | 2.722922 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_model_constr_decoder.vhd | 1 | 11,488 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | 25bb6c227d5d2268b8dfb7865b703268 | 0.344708 | 5.552441 | false | false | false | false |
malkadi/FGPU | RTL/gmem_atomics.vhd | 1 | 23,616 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
------------------------------------------------------------------------------------... | gpl-3.0 | 4bb6361250f7431a1401f035d1cc5ebe | 0.482215 | 3.835011 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/fifo/fifo_glue.vhdl | 2 | 3,314 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module: minimal FIFO, common clock (cc),
-- pipelined... | agpl-3.0 | 97c54405a3b6af4cddc41377a685fe55 | 0.487628 | 4.194937 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_write_wrapper.vhd | 2 | 66,283 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | e3cdccc37a4e7b5225bcb3fe6cc14865 | 0.9513 | 1.83523 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_8Stations_2AXI_2TAGM.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 391e30b01ba5349a04808465ff7365c7 | 0.567707 | 3.729005 | false | false | false | false |
preusser/q27 | src/vhdl/top/xilinx/sdrc_queens_slave.vhdl | 1 | 14,930 | library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity sdrc_queens_slave is
generic (
-- Design Parameters
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 90;
COUNT_CYCLES : boolean := false;
-- Local Clock Parameters
CLK_FREQ : FREQ :=... | agpl-3.0 | 1848736eda8be8885aba133032388745 | 0.450971 | 3.910424 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_8Stations_2AXI_2TAGM_2CACHE_W.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 25ce6ba1b8a3fd491498cbf78c9f55cb | 0.567707 | 3.729005 | false | false | false | false |
jpidancet/mips | rtl/cpu_fetch.vhd | 1 | 905 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity cpu_fetch is
port (pc : in std_logic_vector(31 downto 0);
pcbranch : in std_logic_vector(31 downto 0);
pcsrc : in std_logic;
instr_n : ou... | isc | 5f92024a3d2040be6f70c0612b028cda | 0.574586 | 3.376866 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/fetch_page/fetch_page_ow.vhd | 1 | 5,203 | -------------------------------------------------------------------------------
--! @file fetch_page_ow.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-11-19
--! @brief Prepare one-wire page for NanoFIP communication.
-----------------------------... | mit | b0d1cb7bcf989dbe7556bdb8ffc3afe3 | 0.419373 | 4.002308 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/common/strings.vhdl | 1 | 35,345 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick ... | agpl-3.0 | b0ea63feea60cf9182a58e5525d3159e | 0.646258 | 3.285767 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/fifo/fifo_cc_got_tempput.vhdl | 1 | 13,774 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =========================================================================================================================================================... | agpl-3.0 | ef4f5453d52aca1ac947d91ab3d89851 | 0.519965 | 3.962601 | false | false | false | false |
jcowgill/cs-dacs-robot | Common/AsyncTxTest.vhd | 1 | 1,278 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY AsyncTxTest IS
END AsyncTxTest;
ARCHITECTURE behavioral OF AsyncTxTest IS
COMPONENT AsyncTx
PORT ( TX : OUT STD_LOGIC;
ACTIVE : OUT STD_LOGIC;
SEND : IN STD_LOGIC;
CLR : IN STD_LOGIC;
... | apache-2.0 | 7204d74e74dfc00903e03cb6db300eee | 0.492175 | 3.630682 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_top.vhd | 2 | 73,440 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | 6baa9e1d0839c23b982d8f3a36e43523 | 0.952233 | 1.83908 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/dualram_512x8.vhd | 1 | 13,373 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | f7a88a4e17290e62410ad44d0fe322b1 | 0.396471 | 5.050227 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/fetch_page/fetch_page_sram_adc.vhd | 1 | 5,657 | -------------------------------------------------------------------------------
--! @file fetch_page_sram_adc.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-11-19
--! @brief Prepare SRAM page with ADC data for NanoFIP communication.
-------------... | mit | 5ee535a25ad0212c0e878974951073cf | 0.431678 | 3.94216 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/common/config.vhdl | 1 | 46,749 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick ... | agpl-3.0 | 0616c1009eb9be89f88676e8265d82c0 | 0.62857 | 3.262317 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_2CUs_float.vhd | 1 | 23,540 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 522896b227d45429c7091df95c7bafb7 | 0.568734 | 3.715864 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_no_float_area_estimation.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | e481914e4dad03e6266c90806db4bb1c | 0.567707 | 3.729005 | false | false | false | false |
preusser/q27 | src/vhdl/top/xilinx/s3sk_queens_uart.vhdl | 1 | 4,543 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | d551a50b1d474843ae68ce7ef45bf474 | 0.504292 | 4.13 | false | false | false | false |
malkadi/FGPU | RTL/ALU.vhd | 1 | 15,756 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
------------------------------------------------------------------------------------... | gpl-3.0 | cafceba4509dce30b8c9168a89b7189c | 0.472772 | 3.205697 | false | false | false | false |
joalcava/sparcv8-monocicle | instruction_memory.vhd | 1 | 1,784 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:30:27 10/04/2016
-- Design Name:
-- Module Name: instruction_memory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... | gpl-3.0 | 2554fbd60048744b89ce22c5d2d29671 | 0.618274 | 3.640816 | false | false | false | false |
preusser/q27 | src/vhdl/top/xilinx/sdrc4_queens_uart.vhdl | 1 | 4,176 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... | agpl-3.0 | 5088d96406700fd6b2018c7fa78fbb6a | 0.511494 | 4.070175 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/fetch_page.vhd | 1 | 9,258 | -------------------------------------------------------------------------------
--! @file fetch_page.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-11-19
--! @brief Prepare page for NanoFIP communication.
-----------------------------------------... | mit | 75a238bf3d8c4f62b28748f4c504db2f | 0.469432 | 3.455767 | false | false | false | false |
jpidancet/mips | tests/cpu_tb.vhd | 1 | 3,189 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity cpu_tb is
generic (FIRMWARE : string);
end entity cpu_tb;
architecture behav of cpu_tb is
component cpu is
port (clk : in std_logic;
rst : in std_logic;
... | isc | 74e344c3f1e19ce4b02d4f623ecb664a | 0.498902 | 3.889024 | false | false | false | false |
jpidancet/mips | rtl/cpu.vhd | 1 | 18,402 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
library work;
use work.mips_defs.ALL;
entity cpu is
port (clk : in std_logic;
rst : in std_logic;
mem_halt : in std_logic;
pc : out std_logic_v... | isc | 72cfe58195f85b23e292810aa2785fba | 0.45457 | 4.353442 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_defaults.vhd | 2 | 32,589 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | 7742bcbcf0f7803cd1925b5941f34166 | 0.947344 | 1.848707 | false | false | false | false |
dtysky/LD3320_AXI | src/LIST/synth/LIST.vhd | 1 | 13,748 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit | 121c6d0b4b3ff5e10aacd5dd4e86f481 | 0.628455 | 3.041593 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fdiv_2AXI.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 1c050a1ab347aa17349a167de6a3826a | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_max_mem_cntrl.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | ab7d4656dc9b0bf226702bc574c9f717 | 0.567707 | 3.729005 | false | false | false | false |
chrbirks/NiosII-basic | nios_system/nios_system_inst.vhd | 1 | 732 | component nios_system is
port (
switches_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
leds_export : out std_logic_vector(3 downto 0); -- export
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic ... | gpl-3.0 | 33e21fe8a7dba255cf19074095d6bdd8 | 0.521858 | 3.373272 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_2AXI_2CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 6ca7d27e652775bfdae7d6a6f0ffff91 | 0.567707 | 3.729005 | false | false | false | false |
viccuad/fpga-thingies | tron/tron.vhd | 1 | 25,208 | -- hecho para ser visto con tab size = 3
library IEEE;
library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tron is
port (
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
clk: IN std_logic;
reset: IN std_logic; --reset activo a baja!
hSync: ... | gpl-3.0 | ccbab33b09ac435582eb81db029d8ee5 | 0.613456 | 3.242604 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_wrapper.vhd | 2 | 57,813 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit | ca4938449d27ddff50df4f9606be9925 | 0.950599 | 1.846176 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/debug_serial.vhd | 1 | 3,672 | -------------------------------------------------------------------------------
--! @file debug_serial.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2015-01-20
--! @brief Debugging serial interface.
---------------------------------------------------... | mit | fd5c1aa39591bb21324d015a0acfb869 | 0.435185 | 3.785567 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_2AXI.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 18935be0c51b0848988ba5dbd1b5615c | 0.567707 | 3.729005 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/common/components.vhdl | 2 | 11,401 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Common primitives descr... | agpl-3.0 | 8201e53a7d6b1d4f7e821c914f8f1b2d | 0.672836 | 3.282753 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_rx_deglitcher.vhd | 1 | 10,214 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | 6deff1c08ea25fefb50fa3dcfb45d4b5 | 0.319561 | 5.624449 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/ab.vhd | 1 | 10,554 | -------------------------------------------------------------------------------
--! @file ab.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-08
--! @brief Analogue board control and filters.
-----------------------------------------------------... | mit | f6c2aee3439e8916e76674475992ad0d | 0.481524 | 3.204007 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_float.vhd | 1 | 23,540 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | 079a63acf9c65477bf1d4e014cd772c3 | 0.568734 | 3.717038 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_2AXI_2CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... | gpl-3.0 | c5638b1cf009292e0cff592f8a3ca1c4 | 0.567707 | 3.729005 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/synth/VOICE_ROM_INIT.vhd | 1 | 13,888 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit | 55c629036c4a6883a57c195a28c96620 | 0.630328 | 3.03895 | false | false | false | false |
dtysky/LD3320_AXI | hdl/VOICE_DELAY.vhd | 2 | 889 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity VOICE_DELAY is
port
(
clk:in std_logic;
start:in std_logic:='0';
total:in std_logic_vector(7 downto 0);
finish:out std_logic:='1'
);
end entity;
architecture delayx ... | mit | 3f9ffdd4bf55d4eb63ed4697c427dcc8 | 0.647919 | 2.685801 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_prod_data_lgth_calc.vhd | 1 | 13,111 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | 12d2c083d3fae2e0cb623af9803563b7 | 0.309969 | 5.529734 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_crc.vhd | 1 | 10,402 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | 1cc1584fdadefe0fa117264303ad4bf0 | 0.322342 | 5.947399 | false | false | false | false |
preusser/q27 | src/vhdl/top/dnk7_f5/dnk7_queens1.vhdl | 1 | 14,724 | library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity dnk7_queens1 is
generic (
-- Design Parameters
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 240;
COUNT_CYCLES : boolean := false;
-- Local Clock Parameters
CLK_FREQ : FREQ :=... | agpl-3.0 | 5c6157a2c1b6f385b24d2a38c1658c61 | 0.45633 | 3.940059 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_incr_counter.vhd | 1 | 7,070 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit | dcfc2a40e7952cda7ee5404ad8c510c1 | 0.273833 | 7.084168 | false | false | false | false |
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