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CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | cnn_pruning | \cite{cnn_pruning} | Pruning convolutional neural networks for resource efficient inference | null | null | true | false | Molchanov, Pavlo and Tyree, Stephen and Karras, Tero and Aila, Timo and Kautz, Jan | 2,016 | null | null | null | arXiv preprint arXiv:1611.06440 | Pruning convolutional neural networks for resource efficient inference | Pruning Convolutional Neural Networks for Resource Efficient Inference | http://arxiv.org/pdf/1611.06440v2 | We propose a new formulation for pruning convolutional kernels in neural
networks to enable efficient inference. We interleave greedy criteria-based
pruning with fine-tuning by backpropagation - a computationally efficient
procedure that maintains good generalization in the pruned network. We propose
a new criterion ba... |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | Pruner-Zero | \cite{Pruner-Zero} | Pruner-Zero: Evolving Symbolic Pruning Metric From Scratch for Large
Language Models | null | null | true | false | Peijie Dong and
Lujun Li and
Zhenheng Tang and
Xiang Liu and
Xinglin Pan and
Qiang Wang and
Xiaowen Chu | 2,024 | null | https://openreview.net/forum?id=1tRLxQzdep | null | null | Pruner-Zero: Evolving Symbolic Pruning Metric From Scratch for Large
Language Models | Pruner-Zero: Evolving Symbolic Pruning Metric from scratch for LLMs | https://github.com/pprp/Pruner-Zero | GitHub - pprp/Pruner-Zero: [ICML24] Pruner-Zero: Evolving Symbolic Pruning Metric from scratch for LLMs [ICML24] Pruner-Zero: Evolving Symbolic Pruning Metric from scratch for LLMs | main.py | main.py | Update rest code at once | Jun 6, 2024 | | main_opt.py | main_opt.py | Update rest code at once | Jun 6, 2024 | **Pru... |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | SparseGPT | \cite{SparseGPT} | SparseGPT: Massive Language Models Can Be Accurately Pruned in One-Shot | http://arxiv.org/abs/2301.00774v3 | We show for the first time that large-scale generative pretrained transformer
(GPT) family models can be pruned to at least 50% sparsity in one-shot, without
any retraining, at minimal loss of accuracy. This is achieved via a new pruning
method called SparseGPT, specifically designed to work efficiently and
accurately ... | true | true | Elias Frantar and
Dan Alistarh | 2,023 | null | https://proceedings.mlr.press/v202/frantar23a.html | null | null | SparseGPT: Massive Language Models Can Be Accurately Pruned in One-Shot | SparseGPT: Massive Language Models Can Be Accurately ... | https://arxiv.org/abs/2301.00774 | by E Frantar · 2023 · Cited by 887 — We show for the first time that large-scale generative pretrained transformer (GPT) family models can be pruned to at least 50% sparsity in one-shot.See more |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | DistiLLM | \cite{DistiLLM} | DistiLLM: Towards Streamlined Distillation for Large Language Models | http://arxiv.org/abs/2402.03898v2 | Knowledge distillation (KD) is widely used for compressing a teacher model to
a smaller student model, reducing its inference cost and memory footprint while
preserving model capabilities. However, current KD methods for auto-regressive
sequence models (e.g., large language models) suffer from missing a
standardized ob... | true | true | Jongwoo Ko and
Sungnyun Kim and
Tianyi Chen and
Se{-}Young Yun | 2,024 | null | https://openreview.net/forum?id=lsHZNNoC7r | null | null | DistiLLM: Towards Streamlined Distillation for Large Language Models | DistiLLM: Towards Streamlined Distillation for Large Language Models | http://arxiv.org/pdf/2402.03898v2 | Knowledge distillation (KD) is widely used for compressing a teacher model to
a smaller student model, reducing its inference cost and memory footprint while
preserving model capabilities. However, current KD methods for auto-regressive
sequence models (e.g., large language models) suffer from missing a
standardized ob... |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | MiniLLM | \cite{MiniLLM} | MiniLLM: Knowledge Distillation of Large Language Models | http://arxiv.org/abs/2306.08543v4 | Knowledge Distillation (KD) is a promising technique for reducing the high
computational demand of large language models (LLMs). However, previous KD
methods are primarily applied to white-box classification models or training
small models to imitate black-box model APIs like ChatGPT. How to effectively
distill the kno... | true | true | Yuxian Gu and
Li Dong and
Furu Wei and
Minlie Huang | 2,024 | null | https://openreview.net/forum?id=5h0qf7IBZZ | null | null | MiniLLM: Knowledge Distillation of Large Language Models | MiniLLM: Knowledge Distillation of Large Language Models | http://arxiv.org/pdf/2306.08543v4 | Knowledge Distillation (KD) is a promising technique for reducing the high
computational demand of large language models (LLMs). However, previous KD
methods are primarily applied to white-box classification models or training
small models to imitate black-box model APIs like ChatGPT. How to effectively
distill the kno... |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | pytorch-1 | \cite{pytorch-1} | PyTorch: An Open Source Machine Learning Framework | null | null | true | false | {PyTorch Contributors} | 2,024 | null | https://pytorch.org/ | null | null | PyTorch: An Open Source Machine Learning Framework | PyTorch | https://en.wikipedia.org/wiki/PyTorch | PyTorch is a machine learninglibrary based on the Torch library,[4][5][6] used for applications such as computer vision and natural language processing,[7] originally developed by Meta AI and now part of the Linux Foundation umbrella.[8][9][10][11] It is one of the most popular deep learning frameworks, alongside other... |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | tensorflow | \cite{tensorflow} | TensorFlow: An Open Source Machine Learning Framework for Everyone | null | null | true | false | {TensorFlow Contributors} | 2,024 | null | https://www.tensorflow.org/ | null | null | TensorFlow: An Open Source Machine Learning Framework for Everyone | tensorflow/tensorflow: An Open Source Machine Learning ... | https://github.com/tensorflow/tensorflow | TensorFlow is an end-to-end open source platform for machine learning. It has a comprehensive, flexible ecosystem of tools, libraries, and community resources. |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | deepspeed | \cite{deepspeed} | DeepSpeed: Advancing the Science of AI Through Efficient Training of Large Models | null | null | true | false | {Microsoft DeepSpeed Team} | 2,024 | null | https://www.deepspeed.ai/ | null | null | DeepSpeed: Advancing the Science of AI Through Efficient Training of Large Models | DeepSpeed: Latest News | https://www.deepspeed.ai/ | DeepSpeed is a deep learning optimization library that makes distributed training easy, efficient, and effective. |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | huggingface_transformers | \cite{huggingface_transformers} | Transformers Documentation | null | null | true | false | {HuggingFace Team} | 2,024 | null | https://huggingface.co/docs/transformers/index | null | null | Transformers Documentation | Transformers — transformers 3.0.2 documentation - Hugging Face | https://huggingface.co/transformers/v3.0.2/index.html | Transformers is a state-of-the-art NLP library for Pytorch and TensorFlow 2.0, providing architectures for NLU and NLG with high performance and low barrier to |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | flexgen | \cite{flexgen} | FlexGen: High-Throughput Generative Inference of Large Language Models
with a Single GPU | http://arxiv.org/abs/2303.06865v2 | The high computational and memory requirements of large language model (LLM)
inference make it feasible only with multiple high-end accelerators. Motivated
by the emerging demand for latency-insensitive tasks with batched processing,
this paper initiates the study of high-throughput LLM inference using limited
resource... | true | true | Sheng, Ying and Zheng, Lianmin and Yuan, Binhang and Li, Zhuohan and Ryabinin, Max and Chen, Beidi and Liang, Percy and R{\'e}, Christopher and Stoica, Ion and Zhang, Ce | 2,023 | null | null | null | null | FlexGen: High-Throughput Generative Inference of Large Language Models
with a Single GPU | [PDF] FlexGen: High-Throughput Generative Inference of Large Language ... | https://openreview.net/pdf?id=RRntzKrBTp | FlexGen is a high-throughput engine for running LLMs with limited GPU memory, using GPU, CPU, and disk, and achieving 1 token/s throughput. |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | Orca | \cite{Orca} | Orca: {A} Distributed Serving System for Transformer-Based Generative
Models | null | null | true | false | Gyeong{-}In Yu and
Joo Seong Jeong and
Geon{-}Woo Kim and
Soojeong Kim and
Byung{-}Gon Chun | 2,022 | null | https://www.usenix.org/conference/osdi22/presentation/yu | null | null | Orca: {A} Distributed Serving System for Transformer-Based Generative
Models | Orca: A Distributed Serving System for Transformer-Based ... | https://www.usenix.org/conference/osdi22/presentation/yu | + Poster Session # Orca: A Distributed Serving System for Transformer-Based Generative Models In this paper, we propose iteration-level scheduling, a new scheduling mechanism that schedules execution at the granularity of iteration (instead of request) where the scheduler invokes the execution engine to run only a sing... |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | zhao4 | \cite{zhao4} | A Reconfigurable 0.69-1.02 nJ/Classification Biomedical AI Processor for Intelligent Health Monitoring Devices | null | null | true | false | Zhao, Yuanzhe and Wang, Yuheng and Wang, Zijian and Zhu, Yan and Martins, RP and Chan, Chi-Hang and Zhang, Minglei | 2,025 | null | null | null | null | A Reconfigurable 0.69-1.02 nJ/Classification Biomedical AI Processor for Intelligent Health Monitoring Devices | 4.5 BioAIP: A Reconfigurable Biomedical AI Processor with Adaptive ... | https://www.researchgate.net/publication/350171989_45_BioAIP_A_Reconfigurable_Biomedical_AI_Processor_with_Adaptive_Learning_for_Versatile_Intelligent_Health_Monitoring | A Reconfigurable 0.69-1.02nJ/Classification Biomedical AI Processor for Intelligent Health Monitoring Devices. Conference Paper. Apr 2025. Yuanzhe Zhao · Yuheng |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | zhao5 | \cite{zhao5} | A 28nm Value-Wise Hybrid-Domain Compute-in-Memory Macro with Heterogeneous Memory Fabric and Asynchronous Sparsity Manager | null | null | true | false | Zhao, Yuanzhe and Wang, Yang and Wang, Yuheng and Xie, Heng and Zhu, Yan and Martins, RP and Chan, Chi-Hang and Yin, Shouyi and Zhang, Minglei | 2,025 | null | null | null | null | A 28nm Value-Wise Hybrid-Domain Compute-in-Memory Macro with Heterogeneous Memory Fabric and Asynchronous Sparsity Manager | A 28nm Value-Wise Hybrid-Domain Compute-in-Memory ... | https://unpaywall.org/10.1109%2FCICC63670.2025.10982876 | Abstract: Edge AI devices need to be energy-efficient and compact while maintaining sufficient accuracy. Compute-in-memory (CIM) is a promising approach to |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | zhao6 | \cite{zhao6} | A One-Shot Floating-Point Compute-in-Memory Macro Featuring PVT Robustness and Mismatch Tolerance for Edge LLMs | null | null | true | false | Zhao, Yuanzhe and Xie, Heng and Wang, Zijian and Tian, Chunlin and Li, Li and Zhu, Yan and Martins, RP and Chan, Chi-Hang and Zhang, Minglei | 2,025 | null | null | null | null | A One-Shot Floating-Point Compute-in-Memory Macro Featuring PVT Robustness and Mismatch Tolerance for Edge LLMs | A One-Shot Floating-Point Compute-in-Memory Macro ... | https://www.researchgate.net/publication/391898058_A_One-Shot_Floating-Point_Compute-in-Memory_Macro_Featuring_PVT_Robustness_and_Mismatch_Tolerance_for_Edge_LLMs | Robustness. Conference Paper. A One-Shot Floating-Point Compute-in-Memory Macro Featuring PVT Robustness and Mismatch Tolerance for Edge LLMs. |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | zhao7 | \cite{zhao7} | A 28-nm 3.32-nJ/Frame Compute-in-Memory CNN Processor With Layer Fusion for Always-on Applications | null | null | true | false | Zhao, Yuanzhe and He, Pengyu and Zhu, Yan and Martins, Rui P and Chan, Chi-Hang and Zhang, Minglei | 2,025 | null | null | null | IEEE Transactions on Circuits and Systems I: Regular Papers | A 28-nm 3.32-nJ/Frame Compute-in-Memory CNN Processor With Layer Fusion for Always-on Applications | A 28-nm 3.32-nJ/Frame Compute-in-Memory CNN Processor With ... | https://ieeexplore.ieee.org/document/10902457/ | This work presents an always-on CNN processor featuring compute-in-memory (CIM) and layer-fusion (LF) techniques. It demonstrates an end-to-end neural network |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | zhao8 | \cite{zhao8} | A Reconfigurable Floating-Point Compute-In-Memory With Analog Exponent Pre-Processes | null | null | true | false | He, Pengyu and Zhao, Yuanzhe and Xie, Heng and Wang, Yang and Yin, Shouyi and Li, Li and Zhu, Yan and Martins, Rui P and Chan, Chi-Hang and Zhang, Minglei | 2,024 | null | null | null | IEEE Solid-State Circuits Letters | A Reconfigurable Floating-Point Compute-In-Memory With Analog Exponent Pre-Processes | A Reconfigurable Floating-Point Compute-in-Memory With ... | http://ieeexplore.ieee.org/document/10683795/ | This letter presents a reconfigurable floating-point compute-in-memory (FP-CIM) macro that preprocesses the exponent in the analog domain.See more |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | tambe2021edgebert | \cite{tambe2021edgebert} | EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware
Multi-Task NLP Inference | http://arxiv.org/abs/2011.14203v5 | Transformer-based language models such as BERT provide significant accuracy
improvement for a multitude of natural language processing (NLP) tasks.
However, their hefty computational and memory demands make them challenging to
deploy to resource-constrained edge platforms with strict latency requirements.
We present Ed... | true | true | Tambe, Thierry and Hooper, Coleman and Pentecost, Lillian and Jia, Tianyu and Yang, En-Yu and Donato, Marco and Sanh, Victor and Whatmough, Paul and Rush, Alexander M and Brooks, David and others | 2,021 | null | null | null | null | EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware
Multi-Task NLP Inference | Sentence-Level Energy Optimizations for Latency-Aware ... | https://dl.acm.org/doi/10.1145/3466752.3480095 | We present EdgeBERT, an in-depth algorithm-hardware co-design for latency-aware energy optimizations for multi-task NLP. |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | zhao2023approxcaliper | \cite{zhao2023approxcaliper} | Approxcaliper: A programmable framework for application-aware neural network optimization | null | null | true | false | Zhao, Yifan and Sharif, Hashim and Pao-Huang, Peter and Shah, Vatsin and Sivakumar, Arun Narenthiran and Valverde Gasparino, Mateus and Mahmoud, Abdulrahman and Zhao, Nathan and Adve, Sarita and Chowdhary, Girish and others | 2,023 | null | null | null | Proceedings of Machine Learning and Systems | Approxcaliper: A programmable framework for application-aware neural network optimization | ApproxCaliper: A Programmable Framework for ... | https://ma3mool.github.io/publication/mlsys23.html | "ApproxCaliper: A Programmable Framework for Application-aware Neural Network Optimization," Sixth Conference on Machine Learning and Systems (MLSys), Miami, |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | liberis2023differentiable | \cite{liberis2023differentiable} | Differentiable neural network pruning to enable smart applications on microcontrollers | null | null | true | false | Liberis, Edgar and Lane, Nicholas D | 2,023 | null | null | null | Proceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies | Differentiable neural network pruning to enable smart applications on microcontrollers | Differentiable Neural Network Pruning to Enable Smart Applications ... | https://dl.acm.org/doi/abs/10.1145/3569468 | We present a differentiable structured pruning method for convolutional neural networks, which integrates a model's MCU-specific resource usage and parameter |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | zhao2024felix | \cite{zhao2024felix} | Felix: Optimizing Tensor Programs with Gradient Descent | null | null | true | false | Zhao, Yifan and Sharif, Hashim and Adve, Vikram and Misailovic, Sasa | 2,024 | null | null | null | null | Felix: Optimizing Tensor Programs with Gradient Descent | Felix: Optimizing Tensor Programs with Gradient Descent | https://misailo.cs.illinois.edu/papers/felix-asplos24.pdf | Felix creates a differentiable space of tensor programs that is amenable to search by gradient descent. Felix applies continuous re- laxation on the space of |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | tam2024fedhybrid | \cite{tam2024fedhybrid} | FedHybrid: Breaking the Memory Wall of Federated Learning via Hybrid Tensor Management | null | null | true | false | Tam, Kahou and Tian, Chunlin and Li, Li and Zhao, Haikai and Xu, ChengZhong | 2,024 | null | null | null | null | FedHybrid: Breaking the Memory Wall of Federated Learning via Hybrid Tensor Management | Breaking the Memory Wall of Federated Learning via Hybrid Tensor ... | https://www.researchgate.net/publication/385538059_FedHybrid_Breaking_the_Memory_Wall_of_Federated_Learning_via_Hybrid_Tensor_Management | FedHybrid: Breaking the Memory Wall of Federated Learning via Hybrid Tensor Management ... Wall for Heterogeneous Federated Learning via Progressive Training. |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | dvfsasplos | \cite{dvfsasplos} | Expanding Datacenter Capacity with {DVFS} Boosting: {A} safe and scalable
deployment experience | null | null | true | false | Leonardo Piga and
Iyswarya Narayanan and
Aditya Sundarrajan and
Matt Skach and
Qingyuan Deng and
Biswadip Maity and
Manoj Chakkaravarthy and
Alison Huang and
Abhishek Dhanotia ... | 2,024 | null | https://doi.org/10.1145/3617232.3624853 | 10.1145/3617232.3624853 | null | Expanding Datacenter Capacity with {DVFS} Boosting: {A} safe and scalable
deployment experience | Expanding Datacenter Capacity with DVFS Boosting | https://www.researchgate.net/publication/379917331_Expanding_Datacenter_Capacity_with_DVFS_Boosting_A_safe_and_scalable_deployment_experience | [35] DVFS Boosting was explored as a scalable and secure approach to enhance data center capacity, tackling power consumption, hardware heterogeneity, and ...See more |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | dfvs-4 | \cite{dfvs-4} | Improving {DVFS} in NoCs with Coherence Prediction | null | null | true | false | Robert Hesse and
Natalie D. Enright Jerger | 2,015 | null | https://doi.org/10.1145/2786572.2786595 | 10.1145/2786572.2786595 | null | Improving {DVFS} in NoCs with Coherence Prediction | Improving DVFS in NoCs with Coherence Prediction | https://dl.acm.org/doi/10.1145/2786572.2786595 | In this work, we propose to utilize highly predictable properties of cache-coherence communication to derive more specific and reliable NoC traffic predictions. |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | dvfs-2 | \cite{dvfs-2} | Variation-aware dynamic voltage/frequency scaling | null | null | true | false | Sebastian Herbert and
Diana Marculescu | 2,009 | null | https://doi.org/10.1109/HPCA.2009.4798265 | 10.1109/HPCA.2009.4798265 | null | Variation-aware dynamic voltage/frequency scaling | Variation-aware dynamic voltage/frequency scaling | https://ieeexplore.ieee.org/document/4798265/ | by S Herbert · 2009 · Cited by 174 — Fine-grained dynamic voltage/frequency scaling (DVFS) is an important tool in managing the balance between power and performance in chip-multiprocessors. |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | dvfs-3 | \cite{dvfs-3} | System level analysis of fast, per-core {DVFS} using on-chip switching
regulators | null | null | true | false | Wonyoung Kim and
Meeta Sharma Gupta and
Gu{-}Yeon Wei and
David M. Brooks | 2,008 | null | https://doi.org/10.1109/HPCA.2008.4658633 | 10.1109/HPCA.2008.4658633 | null | System level analysis of fast, per-core {DVFS} using on-chip switching
regulators | System Level Analysis of Fast, Per-Core DVFS Using On- ... | https://www.slideserve.com/malise/system-level-analysis-of-fast-per-core-dvfs-using-on-chip-switching-regulators | System Level Analysis of Fast, Per-Core DVFS Using On-Chip Switching Regulators. Wonyoung Kim, Meeta Gupta Prof. Gu-Yeon Wei, Prof. David Brooks |
CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the
Edge | 2506.02847v1 | bateni2020neuos | \cite{bateni2020neuos} | $\{$NeuOS$\}$: A $\{$Latency-Predictable$\}$$\{$Multi-Dimensional$\}$ Optimization Framework for $\{$DNN-driven$\}$ Autonomous Systems | null | null | true | false | Bateni, Soroush and Liu, Cong | 2,020 | null | null | null | null | $\{$NeuOS$\}$: A $\{$Latency-Predictable$\}$$\{$Multi-Dimensional$\}$ Optimization Framework for $\{$DNN-driven$\}$ Autonomous Systems | Soroush Bateni - DBLP | https://dblp.org/pid/224/5652 | NeuOS: A Latency-Predictable Multi-Dimensional Optimization Framework for DNN-driven Autonomous Systems. USENIX ATC 2020: 371-385. [i2]. view. |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | lin2017accurate | \cite{lin2017accurate} | Towards Accurate Binary Convolutional Neural Network | http://arxiv.org/abs/1711.11294v1 | We introduce a novel scheme to train binary convolutional neural networks
(CNNs) -- CNNs with weights and activations constrained to {-1,+1} at run-time.
It has been known that using binary weights and activations drastically reduce
memory size and accesses, and can replace arithmetic operations with more
efficient bit... | true | true | Xiaofan Lin and Cong Zhao and Wei Pan | 2,017 | null | null | null | null | Towards Accurate Binary Convolutional Neural Network | Towards Accurate Binary Convolutional Neural Network | http://arxiv.org/pdf/1711.11294v1 | We introduce a novel scheme to train binary convolutional neural networks
(CNNs) -- CNNs with weights and activations constrained to {-1,+1} at run-time.
It has been known that using binary weights and activations drastically reduce
memory size and accesses, and can replace arithmetic operations with more
efficient bit... |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | zhang2018lqnets | \cite{zhang2018lqnets} | LQ-Nets: Learned Quantization for Highly Accurate and Compact Deep Neural Networks | null | null | true | false | Dongqing Zhang and Jiaolong Yang and Dongqiangzi Ye and Gang Hua | 2,018 | null | null | null | null | LQ-Nets: Learned Quantization for Highly Accurate and Compact Deep Neural Networks | LQ-Nets: Learned Quantization for Highly Accurate and Compact Deep Neural Networks | http://arxiv.org/pdf/1807.10029v1 | Although weight and activation quantization is an effective approach for Deep
Neural Network (DNN) compression and has a lot of potentials to increase
inference speed leveraging bit-operations, there is still a noticeable gap in
terms of prediction accuracy between the quantized model and the full-precision
model. To a... |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | wu2018training | \cite{wu2018training} | Training and Inference with Integers in Deep Neural Networks | http://arxiv.org/abs/1802.04680v1 | Researches on deep neural networks with discrete parameters and their
deployment in embedded systems have been active and promising topics. Although
previous works have successfully reduced precision in inference, transferring
both training and inference processes to low-bitwidth integers has not been
demonstrated simu... | true | true | Wu, Shuang and Li, Guoqi and Chen, Feng and Shi, Luping | 2,018 | null | null | null | arXiv preprint arXiv:1802.04680 | Training and Inference with Integers in Deep Neural Networks | Training and Inference with Integers in Deep Neural Networks | http://arxiv.org/pdf/1802.04680v1 | Researches on deep neural networks with discrete parameters and their
deployment in embedded systems have been active and promising topics. Although
previous works have successfully reduced precision in inference, transferring
both training and inference processes to low-bitwidth integers has not been
demonstrated simu... |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | krishnamoorthi2018quantizing | \cite{krishnamoorthi2018quantizing} | Quantizing deep convolutional networks for efficient inference: A whitepaper | null | null | true | false | Krishnamoorthi, Raghuraman | 2,018 | null | null | null | arXiv preprint arXiv:1806.08342 | Quantizing deep convolutional networks for efficient inference: A whitepaper | Quantizing deep convolutional networks for efficient inference: A whitepaper | http://arxiv.org/pdf/1806.08342v1 | We present an overview of techniques for quantizing convolutional neural
networks for inference with integer weights and activations. Per-channel
quantization of weights and per-layer quantization of activations to 8-bits of
precision post-training produces classification accuracies within 2% of
floating point networks... |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | dai2021vs | \cite{dai2021vs} | Vs-quant: Per-vector scaled quantization for accurate low-precision neural network inference | null | null | true | false | Dai, Steve and Venkatesan, Rangha and Ren, Mark and Zimmer, Brian and Dally, William and Khailany, Brucek | 2,021 | null | null | null | Proceedings of Machine Learning and Systems | Vs-quant: Per-vector scaled quantization for accurate low-precision neural network inference | [PDF] VS-Quant: Per-vector Scaled Quantization for Accurate Low ... - arXiv | https://arxiv.org/pdf/2102.04503 | We find that per-vector scaling consistently achieves better inference accuracy at low precision compared to conventional scaling techniques for |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | harma2022accuracy | \cite{harma2022accuracy} | Accuracy Boosters: Epoch-Driven Mixed-Mantissa Block Floating-Point for DNN Training | null | null | true | false | Harma, Simla Burcu and S{\"o}nmez, Canberk and Falsafi, Babak and Jaggi, Martin and Oh, Yunho | 2,022 | null | null | null | arXiv preprint arXiv:2211.10737 | Accuracy Boosters: Epoch-Driven Mixed-Mantissa Block Floating-Point for DNN Training | [PDF] Epoch-Driven Mixed-Mantissa Block Floating Point for DNN Training | https://openreview.net/pdf?id=nfmfqzQ4Mwl | Using analytic models, we show Accuracy Boosters enable increasing arithmetic density for an HBFP training accelerator by up to 21.3× compared to FP32 and up to |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | darvish2020pushing | \cite{darvish2020pushing} | Pushing the limits of narrow precision inferencing at cloud scale with microsoft floating point | null | null | true | false | Darvish Rouhani, Bita and Lo, Daniel and Zhao, Ritchie and Liu, Ming and Fowers, Jeremy and Ovtcharov, Kalin and Vinogradsky, Anna and Massengill, Sarah and Yang, Lita and Bittner, Ray and others | 2,020 | null | null | null | Advances in neural information processing systems | Pushing the limits of narrow precision inferencing at cloud scale with microsoft floating point | [PDF] Pushing the Limits of Narrow Precision Inferencing at Cloud Scale ... | https://proceedings.neurips.cc/paper/2020/file/747e32ab0fea7fbd2ad9ec03daa3f840-Paper.pdf | In this paper, we explore the limits of Microsoft Floating Point (MSFP), a new class of datatypes developed for production cloud-scale inferencing on custom |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | darvish2023shared | \cite{darvish2023shared} | With Shared Microexponents, A Little Shifting Goes a Long Way | http://arxiv.org/abs/2302.08007v2 | This paper introduces Block Data Representations (BDR), a framework for
exploring and evaluating a wide spectrum of narrow-precision formats for deep
learning. It enables comparison of popular quantization standards, and through
BDR, new formats based on shared microexponents (MX) are identified, which
outperform other... | true | true | Darvish Rouhani, Bita and Zhao, Ritchie and Elango, Venmugil and Shafipour, Rasoul and Hall, Mathew and Mesmakhosroshahi, Maral and More, Ankit and Melnick, Levi and Golub, Maximilian and Varatkar, Girish and others | 2,023 | null | null | null | null | With Shared Microexponents, A Little Shifting Goes a Long Way | With Shared Microexponents, A Little Shifting Goes a Long Way | http://arxiv.org/pdf/2302.08007v2 | This paper introduces Block Data Representations (BDR), a framework for
exploring and evaluating a wide spectrum of narrow-precision formats for deep
learning. It enables comparison of popular quantization standards, and through
BDR, new formats based on shared microexponents (MX) are identified, which
outperform other... |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | andri2022going | \cite{andri2022going} | Going Further With Winograd Convolutions: Tap-Wise Quantization for
Efficient Inference on 4x4 Tile | http://arxiv.org/abs/2209.12982v1 | Most of today's computer vision pipelines are built around deep neural
networks, where convolution operations require most of the generally high
compute effort. The Winograd convolution algorithm computes convolutions with
fewer MACs compared to the standard algorithm, reducing the operation count by
a factor of 2.25x ... | true | true | Andri, Renzo and Bussolino, Beatrice and Cipolletta, Antonio and Cavigelli, Lukas and Wang, Zhe | 2,022 | null | null | null | null | Going Further With Winograd Convolutions: Tap-Wise Quantization for
Efficient Inference on 4x4 Tile | Tap-Wise Quantization for Efficient Inference on 4x4 Tile - arXiv | https://arxiv.org/abs/2209.12982 | The Winograd convolution algorithm computes convolutions with fewer MACs compared to the standard algorithm, reducing the operation count by a |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | song2020drq | \cite{song2020drq} | Drq: dynamic region-based quantization for deep neural network acceleration | null | null | true | false | Song, Zhuoran and Fu, Bangqi and Wu, Feiyang and Jiang, Zhaoming and Jiang, Li and Jing, Naifeng and Liang, Xiaoyao | 2,020 | null | null | null | null | Drq: dynamic region-based quantization for deep neural network acceleration | DRQ Dynamic Region-based Quantization for Deep Neural Network ... | https://github.com/BirenResearch/AIChip_Paper_List/blob/master/notes/ISCA/DRQ%20Dynamic%20Region-based%20Quantization%20for%20Deep%20Neural%20Network%20Acceleration.md | Paper title: DRQ: Dynamic Region-based Quantization for Deep Neural Network Acceleration · Publication: ISCA'20 · Problem to solve: Quantification is an effective |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | zadeh2022mokey | \cite{zadeh2022mokey} | Mokey: Enabling Narrow Fixed-Point Inference for Out-of-the-Box
Floating-Point Transformer Models | http://arxiv.org/abs/2203.12758v1 | Increasingly larger and better Transformer models keep advancing
state-of-the-art accuracy and capability for Natural Language Processing
applications. These models demand more computational power, storage, and
energy. Mokey reduces the footprint of state-of-the-art 32-bit or 16-bit
floating-point transformer models by... | true | true | Zadeh, Ali Hadi and Mahmoud, Mostafa and Abdelhadi, Ameer and Moshovos, Andreas | 2,022 | null | null | null | null | Mokey: Enabling Narrow Fixed-Point Inference for Out-of-the-Box
Floating-Point Transformer Models | Mokey: Enabling Narrow Fixed-Point Inference for Out-of-the-Box ... | https://arxiv.org/abs/2203.12758 | Mokey reduces the footprint of state-of-the-art 32-bit or 16-bit floating-point transformer models by quantizing all values to 4-bit indexes into dictionaries. |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | zhao2021cambricon | \cite{zhao2021cambricon} | Cambricon-Q: A hybrid architecture for efficient training | null | null | true | false | Zhao, Yongwei and Liu, Chang and Du, Zidong and Guo, Qi and Hu, Xing and Zhuang, Yimin and Zhang, Zhenxing and Song, Xinkai and Li, Wei and Zhang, Xishan and others | 2,021 | null | null | null | null | Cambricon-Q: A hybrid architecture for efficient training | Cambricon-Q: A Hybrid Architecture for Efficient Training | https://www.computer.org/csdl/proceedings-article/isca/2021/333300a706/1vNjDWVoisw | Cambricon-Q features a hybrid architecture consisting of an ASIC acceleration core and a near-data-processing (NDP) engine. The acceleration core mainly targets |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | wang2019haq | \cite{wang2019haq} | HAQ: Hardware-Aware Automated Quantization with Mixed Precision | http://arxiv.org/abs/1811.08886v3 | Model quantization is a widely used technique to compress and accelerate deep
neural network (DNN) inference. Emergent DNN hardware accelerators begin to
support mixed precision (1-8 bits) to further improve the computation
efficiency, which raises a great challenge to find the optimal bitwidth for
each layer: it requi... | true | true | Wang, Kuan and Liu, Zhijian and Lin, Yujun and Lin, Ji and Han, Song | 2,019 | null | null | null | null | HAQ: Hardware-Aware Automated Quantization with Mixed Precision | HAQ: Hardware-Aware Automated Quantization with Mixed Precision | https://arxiv.org/abs/1811.08886 | In this paper, we introduce the Hardware-Aware Automated Quantization (HAQ) framework which leverages the reinforcement learning to automatically determine the |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | dettmers2022llm | \cite{dettmers2022llm} | Llm. int8 (): 8-bit matrix multiplication for transformers at scale | null | null | true | false | Dettmers, Tim and Lewis, Mike and Belkada, Younes and Zettlemoyer, Luke | 2,022 | null | null | null | arXiv preprint arXiv:2208.07339 | Llm. int8 (): 8-bit matrix multiplication for transformers at scale | LLM.int8(): 8-bit matrix multiplication for transformers at scale | https://dl.acm.org/doi/10.5555/3600270.3602468 | We develop a procedure for Int8 matrix multiplication for feed-forward and attention projection layers in transformers, which cut the memory needed for |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | frantar2022gptq | \cite{frantar2022gptq} | GPTQ: Accurate Post-Training Quantization for Generative Pre-trained
Transformers | http://arxiv.org/abs/2210.17323v2 | Generative Pre-trained Transformer models, known as GPT or OPT, set
themselves apart through breakthrough performance across complex language
modelling tasks, but also by their extremely high computational and storage
costs. Specifically, due to their massive size, even inference for large,
highly-accurate GPT models m... | true | true | Frantar, Elias and Ashkboos, Saleh and Hoefler, Torsten and Alistarh, Dan | 2,022 | null | null | null | arXiv preprint arXiv:2210.17323 | GPTQ: Accurate Post-Training Quantization for Generative Pre-trained
Transformers | [PDF] gptq: accurate post-training quantization - arXiv | https://arxiv.org/pdf/2210.17323 | Generative Pre-trained Transformer models, known as GPT or OPT, set them- selves apart through breakthrough performance across complex |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | dong2019hawq | \cite{dong2019hawq} | HAWQ: Hessian AWare Quantization of Neural Networks with Mixed-Precision | http://arxiv.org/abs/1905.03696v1 | Model size and inference speed/power have become a major challenge in the
deployment of Neural Networks for many applications. A promising approach to
address these problems is quantization. However, uniformly quantizing a model
to ultra low precision leads to significant accuracy degradation. A novel
solution for this... | true | true | Dong, Zhen and Yao, Zhewei and Gholami, Amir and Mahoney, Michael W and Keutzer, Kurt | 2,019 | null | null | null | null | HAWQ: Hessian AWare Quantization of Neural Networks with Mixed-Precision | [PDF] Hessian AWare Quantization of Neural Networks With Mixed-Precision | https://www.stat.berkeley.edu/~mmahoney/pubs/HAWQ_ICCV_2019_paper.pdf | HAWQ allows for the automatic se- lection of the relative quantization precision of each layer, based on the layer's Hessian spectrum. Moreover, HAWQ provides a |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | xiao2022smoothquant | \cite{xiao2022smoothquant} | SmoothQuant: Accurate and Efficient Post-Training Quantization for Large
Language Models | http://arxiv.org/abs/2211.10438v7 | Large language models (LLMs) show excellent performance but are compute- and
memory-intensive. Quantization can reduce memory and accelerate inference.
However, existing methods cannot maintain accuracy and hardware efficiency at
the same time. We propose SmoothQuant, a training-free, accuracy-preserving,
and general-p... | true | true | Xiao, Guangxuan and Lin, Ji and Seznec, Mickael and Demouth, Julien and Han, Song | 2,022 | null | null | null | arXiv preprint arXiv:2211.10438 | SmoothQuant: Accurate and Efficient Post-Training Quantization for Large
Language Models | SmoothQuant: Accurate and Efficient Post-Training Quantization for ... | https://arxiv.org/abs/2211.10438 | Image 2: arxiv logo>cs> arXiv:2211.10438 **arXiv:2211.10438** (cs) View a PDF of the paper titled SmoothQuant: Accurate and Efficient Post-Training Quantization for Large Language Models, by Guangxuan Xiao and 5 other authors View a PDF of the paper titled SmoothQuant: Accurate and Efficient Post-Training Quantizatio... |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | yao2022zeroquant | \cite{yao2022zeroquant} | ZeroQuant: Efficient and Affordable Post-Training Quantization for
Large-Scale Transformers | http://arxiv.org/abs/2206.01861v1 | How to efficiently serve ever-larger trained natural language models in
practice has become exceptionally challenging even for powerful cloud servers
due to their prohibitive memory/computation requirements. In this work, we
present an efficient and affordable post-training quantization approach to
compress large Trans... | true | true | Yao, Zhewei and Yazdani Aminabadi, Reza and Zhang, Minjia and Wu, Xiaoxia and Li, Conglong and He, Yuxiong | 2,022 | null | null | null | Advances in Neural Information Processing Systems | ZeroQuant: Efficient and Affordable Post-Training Quantization for
Large-Scale Transformers | ZeroQuant: Efficient and Affordable Post-Training Quantization for ... | https://arxiv.org/abs/2206.01861 | In this work, we present an efficient and affordable post-training quantization approach to compress large Transformer-based models, termed as ZeroQuant. |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | liu2023psq | \cite{liu2023psq} | PSQ: An Automatic Search Framework for Data-Free Quantization on PIM-based Architecture | null | null | true | false | Liu, Fangxin and Yang, Ning and Jiang, Li | 2,023 | null | null | null | null | PSQ: An Automatic Search Framework for Data-Free Quantization on PIM-based Architecture | PSQ: An Automatic Search Framework for Data-Free Quantization ... | https://ieeexplore.ieee.org/servlet/Login?logout=/document/10361000 | The scheme tightly combines the search principle of quantization and the PIM architecture to provide smooth hardware-friendly quantization. We leverage the |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | liu2024spark | \cite{liu2024spark} | SPARK: Scalable and Precision-Aware Acceleration of Neural Networks via Efficient Encoding | null | null | true | false | Liu, Fangxin and Yang, Ning and Li, Haomin and Wang, Zongwu and Song, Zhuoran and Pei, Songwen and Jiang, Li | 2,024 | null | null | null | null | SPARK: Scalable and Precision-Aware Acceleration of Neural Networks via Efficient Encoding | Scalable and Precision-Aware Acceleration of Neural ... | https://ieeexplore.ieee.org/document/10476472/ | by F Liu · 2024 · Cited by 31 — SPARK: Scalable and Precision-Aware Acceleration of Neural Networks via Efficient Encoding ; Article #: ; Date of Conference: 02-06 March 2024 ; Date Added to IEEE |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | chang2021mix | \cite{chang2021mix} | Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization
Framework | http://arxiv.org/abs/2012.04240v2 | Deep Neural Networks (DNNs) have achieved extraordinary performance in
various application domains. To support diverse DNN models, efficient
implementations of DNN inference on edge-computing platforms, e.g., ASICs,
FPGAs, and embedded systems, are extensively investigated. Due to the huge
model size and computation am... | true | true | Chang, Sung-En and Li, Yanyu and Sun, Mengshu and Shi, Runbin and So, Hayden K-H and Qian, Xuehai and Wang, Yanzhi and Lin, Xue | 2,021 | null | null | null | null | Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization
Framework | [PDF] A Novel FPGA-Centric Deep Neural Network Quantization Framework | https://par.nsf.gov/servlets/purl/10232486 | This paper proposes a DNN quantization framework that applies different quantization schemes for different weight matrix rows, using a hardware-friendly SP2 |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | wu2023msd | \cite{wu2023msd} | MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources | null | null | true | false | Wu, Jiajun and Zhou, Jiajun and Gao, Yizhao and Ding, Yuhao and Wong, Ngai and So, Hayden Kwok-Hay | 2,023 | null | null | null | null | MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources | MSD: Mixing Signed Digit Representations for Hardware-efficient ... | https://www.researchgate.net/publication/372264814_MSD_Mixing_Signed_Digit_Representations_for_Hardware-efficient_DNN_Acceleration_on_FPGA_with_Heterogeneous_Resources | MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources ... effectively improve training efficiency |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | sharma2018bit | \cite{sharma2018bit} | Bit Fusion: Bit-Level Dynamically Composable Architecture for
Accelerating Deep Neural Networks | http://arxiv.org/abs/1712.01507v2 | Fully realizing the potential of acceleration for Deep Neural Networks (DNNs)
requires understanding and leveraging algorithmic properties. This paper builds
upon the algorithmic insight that bitwidth of operations in DNNs can be reduced
without compromising their classification accuracy. However, to prevent
accuracy l... | true | true | Sharma, Hardik and Park, Jongse and Suda, Naveen and Lai, Liangzhen and Chau, Benson and Kim, Joon Kyung and Chandra, Vikas and Esmaeilzadeh, Hadi | 2,018 | null | null | null | null | Bit Fusion: Bit-Level Dynamically Composable Architecture for
Accelerating Deep Neural Networks | [PDF] Bit Fusion: Bit-Level Dynamically Composable Architecture for ... | https://bpb-us-w2.wpmucdn.com/sites.coecis.cornell.edu/dist/7/587/files/2023/06/Sharma_2018_Bit.pdf | RETROSPECTIVE: Bit Fusion: Bit-Level. Dynamically Composable Architecture for. Accelerating Deep Neural Networks. Hardik Sharma1. Jongse Park2. Naveen Suda3. |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | fan2022adaptable | \cite{fan2022adaptable} | Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and
Algorithm Co-design | http://arxiv.org/abs/2209.09570v1 | Attention-based neural networks have become pervasive in many AI tasks.
Despite their excellent algorithmic performance, the use of the attention
mechanism and feed-forward network (FFN) demands excessive computational and
memory resources, which often compromises their hardware performance. Although
various sparse var... | true | true | Fan, Hongxiang and Chau, Thomas and Venieris, Stylianos I and Lee, Royson and Kouris, Alexandros and Luk, Wayne and Lane, Nicholas D and Abdelfattah, Mohamed S | 2,022 | null | null | null | null | Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and
Algorithm Co-design | Adaptable Butterfly Accelerator for Attention-based NNs via ... | https://ieeexplore.ieee.org/iel7/9923754/9923780/09923888.pdf | by H Fan · 2022 · Cited by 74 — In this work, we address this challenge by adopting an algorithm and hardware co-design approach. On the algorithmic level, a hardware-friendly model called. |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | ham20203 | \cite{ham20203} | A$^3$: Accelerating Attention Mechanisms in Neural Networks with
Approximation | http://arxiv.org/abs/2002.10941v1 | With the increasing computational demands of neural networks, many hardware
accelerators for the neural networks have been proposed. Such existing neural
network accelerators often focus on popular neural network types such as
convolutional neural networks (CNNs) and recurrent neural networks (RNNs);
however, not much ... | true | true | Ham, Tae Jun and Jung, Sung Jun and Kim, Seonghak and Oh, Young H and Park, Yeonhong and Song, Yoonho and Park, Jung-Hun and Lee, Sanghee and Park, Kyoung and Lee, Jae W and others | 2,020 | null | null | null | null | A$^3$: Accelerating Attention Mechanisms in Neural Networks with
Approximation | A$^3$: Accelerating Attention Mechanisms in Neural Networks with ... | https://arxiv.org/abs/2002.10941 | Based on this observation, we design and architect A3, which accelerates attention mechanisms in neural networks with algorithmic approximation |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | ham2021elsa | \cite{ham2021elsa} | ELSA: Hardware-software co-design for efficient, lightweight self-attention mechanism in neural networks | null | null | true | false | Ham, Tae Jun and Lee, Yejin and Seo, Seong Hoon and Kim, Soosung and Choi, Hyunji and Jung, Sung Jun and Lee, Jae W | 2,021 | null | null | null | null | ELSA: Hardware-software co-design for efficient, lightweight self-attention mechanism in neural networks | ELSA: Hardware-software Co-design for efficient, lightweight ... | https://s-space.snu.ac.kr/handle/10371/183738 | ELSA: Hardware-software Co-design for efficient, lightweight self-attention mechanism in neural networks. Cited 111 time in Web of Science Cited 133 time in |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | hong2022dfx | \cite{hong2022dfx} | DFX: A Low-latency Multi-FPGA Appliance for Accelerating
Transformer-based Text Generation | http://arxiv.org/abs/2209.10797v1 | Transformer is a deep learning language model widely used for natural
language processing (NLP) services in datacenters. Among transformer models,
Generative Pre-trained Transformer (GPT) has achieved remarkable performance in
text generation, or natural language generation (NLG), which needs the
processing of a large ... | true | true | Hong, Seongmin and Moon, Seungjae and Kim, Junsoo and Lee, Sungjae and Kim, Minsub and Lee, Dongsoo and Kim, Joo-Young | 2,022 | null | null | null | null | DFX: A Low-latency Multi-FPGA Appliance for Accelerating
Transformer-based Text Generation | DFX: A Low-latency Multi-FPGA Appliance for Accelerating ... | https://ieeexplore.ieee.org/document/9895626 | by S Hong · 2022 · Cited by 104 — DFX is a multi-FPGA appliance that accelerates transformer-based text generation. DFX adopts model parallelism to efficiently process the large-scale language |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | kao2023flat | \cite{kao2023flat} | FLAT: An Optimized Dataflow for Mitigating Attention Bottlenecks | http://arxiv.org/abs/2107.06419v7 | Attention mechanisms, primarily designed to capture pairwise correlations
between words, have become the backbone of machine learning, expanding beyond
natural language processing into other domains. This growth in adaptation comes
at the cost of prohibitively large memory requirements and computational
complexity, esp... | true | true | Kao, Sheng-Chun and Subramanian, Suvinay and Agrawal, Gaurav and Yazdanbakhsh, Amir and Krishna, Tushar | 2,023 | null | null | null | null | FLAT: An Optimized Dataflow for Mitigating Attention Bottlenecks | FLAT: An Optimized Dataflow for Mitigating Attention Bottlenecks | http://arxiv.org/pdf/2107.06419v7 | Attention mechanisms, primarily designed to capture pairwise correlations
between words, have become the backbone of machine learning, expanding beyond
natural language processing into other domains. This growth in adaptation comes
at the cost of prohibitively large memory requirements and computational
complexity, esp... |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | li2020ftrans | \cite{li2020ftrans} | FTRANS: Energy-Efficient Acceleration of Transformers using FPGA | http://arxiv.org/abs/2007.08563v1 | In natural language processing (NLP), the "Transformer" architecture was
proposed as the first transduction model replying entirely on self-attention
mechanisms without using sequence-aligned recurrent neural networks (RNNs) or
convolution, and it achieved significant improvements for sequence to sequence
tasks. The in... | true | true | Li, Bingbing and Pandey, Santosh and Fang, Haowen and Lyv, Yanjun and Li, Ji and Chen, Jieyang and Xie, Mimi and Wan, Lipeng and Liu, Hang and Ding, Caiwen | 2,020 | null | null | null | null | FTRANS: Energy-Efficient Acceleration of Transformers using FPGA | [PDF] FTRANS: Energy-Efficient Acceleration of Transformers using FPGA | https://scispace.com/pdf/ftrans-energy-efficient-acceleration-of-transformers-using-4ipjn26xe9.pdf | In this paper, we propose an energy-efficient acceleration frame- work, Ftrans, for transformer-based large scale language repre- sentations using FPGA. Ftrans |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | lu2021sanger | \cite{lu2021sanger} | Sanger: A co-design framework for enabling sparse attention using reconfigurable architecture | null | null | true | false | Lu, Liqiang and Jin, Yicheng and Bi, Hangrui and Luo, Zizhang and Li, Peng and Wang, Tao and Liang, Yun | 2,021 | null | null | null | null | Sanger: A co-design framework for enabling sparse attention using reconfigurable architecture | hatsu3/Sanger - GitHub | https://github.com/hatsu3/Sanger | This repository implements the proposed framework in the paper Sanger: A Co-Design Framework for Enabling Sparse Attention using Reconfigurable Architecture ( |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | zadeh2020gobo | \cite{zadeh2020gobo} | GOBO: Quantizing Attention-Based NLP Models for Low Latency and Energy
Efficient Inference | http://arxiv.org/abs/2005.03842v2 | Attention-based models have demonstrated remarkable success in various
natural language understanding tasks. However, efficient execution remains a
challenge for these models which are memory-bound due to their massive number
of parameters. We present GOBO, a model quantization technique that compresses
the vast majori... | true | true | Zadeh, Ali Hadi and Edo, Isak and Awad, Omar Mohamed and Moshovos, Andreas | 2,020 | null | null | null | null | GOBO: Quantizing Attention-Based NLP Models for Low Latency and Energy
Efficient Inference | [PDF] GOBO: Quantizing Attention-Based NLP Models for Low Latency ... | https://microarch.org/micro53/papers/738300a811.pdf | GOBO is a model quantization technique that compresses 99.9% of NLP model parameters to 3 bits, maintaining accuracy without fine-tuning. |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | tambe2021edgebert | \cite{tambe2021edgebert} | EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware
Multi-Task NLP Inference | http://arxiv.org/abs/2011.14203v5 | Transformer-based language models such as BERT provide significant accuracy
improvement for a multitude of natural language processing (NLP) tasks.
However, their hefty computational and memory demands make them challenging to
deploy to resource-constrained edge platforms with strict latency requirements.
We present Ed... | true | true | Tambe, Thierry and Hooper, Coleman and Pentecost, Lillian and Jia, Tianyu and Yang, En-Yu and Donato, Marco and Sanh, Victor and Whatmough, Paul and Rush, Alexander M. and Brooks, David and Wei, Gu-Yeon | 2,021 | null | https://doi.org/10.1145/3466752.3480095 | 10.1145/3466752.3480095 | null | EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware
Multi-Task NLP Inference | Sentence-Level Energy Optimizations for Latency-Aware ... | https://dl.acm.org/doi/10.1145/3466752.3480095 | We present EdgeBERT, an in-depth algorithm-hardware co-design for latency-aware energy optimizations for multi-task NLP. |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | qin2023fact | \cite{qin2023fact} | FACT: FFN-attention Co-optimized transformer architecture with eager correlation prediction | null | null | true | false | Qin, Yubin and Wang, Yang and Deng, Dazheng and Zhao, Zhiren and Yang, Xiaolong and Liu, Leibo and Wei, Shaojun and Hu, Yang and Yin, Shouyi | 2,023 | null | null | null | null | FACT: FFN-attention Co-optimized transformer architecture with eager correlation prediction | FACT: FFN-Attention Co-optimized Transformer Architecture with ... | https://dl.acm.org/doi/pdf/10.1145/3579371.3589057 | We first propose an eager prediction algorithm which predicts the attention matrix before QKV generation. It fur- ther detects the unnecessary |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | zeng2024flightllm | \cite{zeng2024flightllm} | FlightLLM: Efficient Large Language Model Inference with a Complete
Mapping Flow on FPGAs | http://arxiv.org/abs/2401.03868v2 | Transformer-based Large Language Models (LLMs) have made a significant impact
on various domains. However, LLMs' efficiency suffers from both heavy
computation and memory overheads. Compression techniques like sparsification
and quantization are commonly used to mitigate the gap between LLM's
computation/memory overhea... | true | true | Zeng, Shulin and Liu, Jun and Dai, Guohao and Yang, Xinhao and Fu, Tianyu and Wang, Hongyi and Ma, Wenheng and Sun, Hanbo and Li, Shiyao and Huang, Zixiao and others | 2,024 | null | null | null | arXiv preprint arXiv:2401.03868 | FlightLLM: Efficient Large Language Model Inference with a Complete
Mapping Flow on FPGAs | FlightLLM: Efficient Large Language Model Inference with a ... | https://dl.acm.org/doi/10.1145/3626202.3637562 | This paper proposes FlightLLM, enabling efficient LLMs inference with a complete mapping flow on FPGAs. |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | li2022auto | \cite{li2022auto} | Auto-vit-acc: An fpga-aware automatic acceleration framework for vision transformer with mixed-scheme quantization | null | null | true | false | Li, Zhengang and Sun, Mengshu and Lu, Alec and Ma, Haoyu and Yuan, Geng and Xie, Yanyue and Tang, Hao and Li, Yanyu and Leeser, Miriam and Wang, Zhangyang and others | 2,022 | null | null | null | null | Auto-vit-acc: An fpga-aware automatic acceleration framework for vision transformer with mixed-scheme quantization | [PDF] Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework ... | https://www.sfu.ca/~zhenman/files/C25-FPL2022-Auto-ViT-Acc.pdf | Missing: 04/08/2025 |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | dong2023heatvit | \cite{dong2023heatvit} | HeatViT: Hardware-Efficient Adaptive Token Pruning for Vision
Transformers | http://arxiv.org/abs/2211.08110v2 | While vision transformers (ViTs) have continuously achieved new milestones in
the field of computer vision, their sophisticated network architectures with
high computation and memory costs have impeded their deployment on
resource-limited edge devices. In this paper, we propose a hardware-efficient
image-adaptive token... | true | true | Dong, Peiyan and Sun, Mengshu and Lu, Alec and Xie, Yanyue and Liu, Kenneth and Kong, Zhenglun and Meng, Xin and Li, Zhengang and Lin, Xue and Fang, Zhenman and others | 2,023 | null | null | null | null | HeatViT: Hardware-Efficient Adaptive Token Pruning for Vision
Transformers | Hardware-Efficient Adaptive Token Pruning for Vision Transformers | https://ieeexplore.ieee.org/iel7/10070856/10070923/10071047.pdf | HeatViT is a hardware-efficient token pruning framework for ViTs, using a token selector to reduce token number and package non-informative tokens. |
Refining Datapath for Microscaling ViTs | 2505.22194v1 | huang2023integer | \cite{huang2023integer} | An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge | null | null | true | false | Huang, Mingqiang and Luo, Junyi and Ding, Chenchen and Wei, Zikun and Huang, Sixiao and Yu, Hao | 2,023 | null | null | null | IEEE Transactions on Circuits and Systems I: Regular Papers | An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge | An Integer-Only and Group-Vector Systolic Accelerator for ... | https://colab.ws/articles/10.1109%2Ftcsi.2023.3312775 | Therefore, in this work, we propose the ViA, a novel vision transformer (ViT) accelerator architecture based on FPGA, to execute the transformer |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | DBLP:conf/rtss/BrandenburgG16 | \cite{DBLP:conf/rtss/BrandenburgG16} | Global Scheduling Not Required: Simple, Near-Optimal Multiprocessor
Real-Time Scheduling with Semi-Partitioned Reservations | null | null | true | false | Bj{\"{o}}rn B. Brandenburg and
Mahircan Gul | 2,016 | null | null | null | null | Global Scheduling Not Required: Simple, Near-Optimal Multiprocessor
Real-Time Scheduling with Semi-Partitioned Reservations | [PDF] Simple, Near-Optimal Multiprocessor Real-Time Scheduling with ... | https://people.mpi-sws.org/~bbb/papers/pdf/rtss16b.pdf | Missing: 04/08/2025 |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | ekberg2021partitioned | \cite{ekberg2021partitioned} | Partitioned Scheduling of Recurrent Real-Time Tasks | null | null | true | false | Ekberg, Pontus and Baruah, Sanjoy | 2,021 | null | null | null | null | Partitioned Scheduling of Recurrent Real-Time Tasks | Partitioned Scheduling of Recurrent Real-Time Tasks | https://user.it.uu.se/~ponek616/files/RTSS21/RTSS21.pdf | by P Ekberg · Cited by 11 — Under the partitioned paradigm of multiprocessor scheduling for recurrent tasks, each task is pre-assigned to an individual processor and all jobs generated by |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Burchard:1995 | \cite{Burchard:1995} | New strategies for assigning real-time tasks to multiprocessor systems | null | null | true | false | Burchard, Almut and Liebeherr, Jörg and Oh, Yingfeng and Son, Sang H. | 1,995 | null | null | null | IEEE Transactions on Computers | New strategies for assigning real-time tasks to multiprocessor systems | New Strategies for Assigning Real-Time Tasks to ... | https://www.computer.org/csdl/journal/tc/1995/12/t1429/13rRUwd9CF8 | by J Liebeherr · 1995 · Cited by 378 — There are two strategies for scheduling real-time tasks on a multiprocessor system. In a global scheme each occurrence of a real-time task may be executed on a |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Dhall:1978 | \cite{Dhall:1978} | On a real-time scheduling problem | null | null | true | false | Dhall, Sudarshan K and Liu, Chung Laung | 1,978 | null | null | null | Operations research | On a real-time scheduling problem | On a Real-Time Scheduling Problem | Operations Research | https://pubsonline.informs.org/doi/10.1287/opre.26.1.127 | The scheduling problem is to specify an order in which the requests of a set of tasks are to be executed and the processor to be used, with the goal of meeting |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Baruah:2005 | \cite{Baruah:2005} | The partitioned multiprocessor scheduling of sporadic task systems | null | null | true | false | Baruah, Sanjoy and Fisher, Nathan | 2,005 | null | null | null | null | The partitioned multiprocessor scheduling of sporadic task systems | The partitioned multiprocessor scheduling of sporadic task ... | https://ieeexplore.ieee.org/document/1563119/ | por S Baruah · 2005 · Mencionado por 204 — A polynomial-time algorithm is presented for partitioning a collection of sporadic tasks among the processors of an identical multiprocessor platform. |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Lopez:2000 | \cite{Lopez:2000} | Worst-case utilization bound for EDF scheduling on real-time multiprocessor systems | null | null | true | false | José María López and Garcia, Manuel and Díaz, Jose and Garcia, Frk Daniel | 2,000 | null | null | null | null | Worst-case utilization bound for EDF scheduling on real-time multiprocessor systems | EDF Scheduling on Heterogeneous Multiprocessors | https://research.engineering.wustl.edu/~baruah/DISSERTATIONS/01funk.pdf | by SH Funk · 2004 · Cited by 57 — Worst- case utilization bound for EDF scheduling on real-time multiprocessor systems. In Proceedings of the EuroMicro Conference on Real-Time Systems, pages |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Fisher:2006 | \cite{Fisher:2006} | The partitioned multiprocessor scheduling of non-preemptive sporadic task systems | null | null | true | false | Fisher, Nathan and Baruah, Sanjoy | 2,006 | null | null | null | null | The partitioned multiprocessor scheduling of non-preemptive sporadic task systems | The Partitioned Multiprocessor Scheduling of Sporadic Task Systems | https://fishern.eng.wayne.edu/papers/2005-baruahFisher-RTSS.pdf | On multiprocessor systems, two alternative paradigms for scheduling collections of sporadic tasks have been considered: partitioned and global scheduling. In the partitioned approach, the tasks are statically partitioned among the processors, i.e., each task is assigned to a processor and is always executed on it . |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Senoussaoui:2020 | \cite{Senoussaoui:2020} | Allocation of Real-Time Tasks onto Identical Core Platforms under Deferred fixed Preemption-Point Model | null | null | true | false | Senoussaoui, Ikram and Zahaf, Houssam-Eddine and Benhaoua, Mohammed Kamel and Lipari, Giuseppe and Olejnik, Richard | 2,020 | null | null | 10.1145/3394810.3394821 | null | Allocation of Real-Time Tasks onto Identical Core Platforms under Deferred fixed Preemption-Point Model | [PDF] Allocation of Real-Time Tasks onto Identical Core Platforms ... - HAL | https://hal.science/hal-02886816/document | Missing: 04/08/2025 |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | fonseca2016response | \cite{fonseca2016response} | Response time analysis of sporadic DAG tasks under partitioned scheduling | null | null | true | false | Fonseca, Jos{\'e} and Nelissen, Geoffrey and Nelis, Vincent and Pinho, Lu{\'\i}s Miguel | 2,016 | null | null | null | null | Response time analysis of sporadic DAG tasks under partitioned scheduling | Response time analysis of sporadic DAG tasks under partitioned ... | https://ieeexplore.ieee.org/document/7509443 | More precisely, we present a response time analysis for sporadic DAG tasks atop multiprocessors under partitioned fixed-priority scheduling. We assume the |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | casini2018partitioned | \cite{casini2018partitioned} | Partitioned fixed-priority scheduling of parallel tasks without preemptions | null | null | true | false | Casini, Daniel and Biondi, Alessandro and Nelissen, Geoffrey and Buttazzo, Giorgio | 2,018 | null | null | null | null | Partitioned fixed-priority scheduling of parallel tasks without preemptions | Partitioned Fixed-Priority Scheduling of Parallel Tasks ... | http://ieeexplore.ieee.org/document/8603232/ | Abstract: The study of parallel task models executed with predictable scheduling approaches is a fundamental problem for real-time multiprocessor systems. |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Zahaf:2020 | \cite{Zahaf:2020} | Preemption-Aware Allocation, Deadline Assignment for Conditional DAGs on Partitioned EDF | null | null | true | false | Zahaf, Houssam-Eddine and Lipari, Giuseppe and Niar, Smail and Hassan Benyamina, Abou El | 2,020 | null | null | 10.1109/RTCSA50079.2020.9203643 | null | Preemption-Aware Allocation, Deadline Assignment for Conditional DAGs on Partitioned EDF | Preemption-Aware Allocation, Deadline Assignment for Conditional ... | https://www.computer.org/csdl/proceedings-article/rtcsa/2020/09203643/1nkD7ZL5ycE | Preemption-Aware Allocation, Deadline Assignment for Conditional DAGs on Partitioned EDF. 2020, pp. 1-10,. DOI Bookmark: 10.1109/RTCSA50079.2020.9203643. |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Ueter:2021 | \cite{Ueter:2021} | {Hard Real-Time Stationary GANG-Scheduling} | null | null | true | false | Ueter, Niklas and G\"{u}nzel, Mario and von der Br\"{u}ggen, Georg and Chen, Jian-Jia | 2,021 | null | null | 10.4230/LIPIcs.ECRTS.2021.10 | null | {Hard Real-Time Stationary GANG-Scheduling} | [PDF] Hard Real-Time Stationary GANG-Scheduling - DROPS | https://drops.dagstuhl.de/storage/00lipics/lipics-vol196-ecrts2021/LIPIcs.ECRTS.2021.10/LIPIcs.ECRTS.2021.10.pdf | Contributions: In this paper we explore stationary gang scheduling for a set of sporadic real- time tasks with constrained deadlines (i.e., the relative |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | sun2024strict | \cite{sun2024strict} | Strict Partitioning for Sporadic Rigid Gang Tasks | http://arxiv.org/abs/2403.10726v2 | The rigid gang task model is based on the idea of executing multiple threads
simultaneously on a fixed number of processors to increase efficiency and
performance. Although there is extensive literature on global rigid gang
scheduling, partitioned approaches have several practical advantages (e.g.,
task isolation and r... | true | true | Sun, Binqi and Kloda, Tomasz and Caccamo, Marco | 2,024 | null | null | null | null | Strict Partitioning for Sporadic Rigid Gang Tasks | Strict Partitioning for Sporadic Rigid Gang Tasks | http://arxiv.org/pdf/2403.10726v2 | The rigid gang task model is based on the idea of executing multiple threads
simultaneously on a fixed number of processors to increase efficiency and
performance. Although there is extensive literature on global rigid gang
scheduling, partitioned approaches have several practical advantages (e.g.,
task isolation and r... |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | sun2024partitioned | \cite{sun2024partitioned} | Partitioned scheduling and parallelism assignment for real-time DNN inference tasks on multi-TPU | null | null | true | false | Sun, Binqi and Kloda, Tomasz and Wu, Chu-ge and Caccamo, Marco | 2,024 | null | null | null | null | Partitioned scheduling and parallelism assignment for real-time DNN inference tasks on multi-TPU | [PDF] Partitioned Scheduling and Parallelism Assignment for Real-Time ... | https://laas.hal.science/hal-04803800/document | We propose an NPG strict partitioning strategy for scheduling. DNN tasks on multi-TPU and a strict partitioning heuristic to determine the |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Zahaf:2021 | \cite{Zahaf:2021} | Contention-Aware GPU Partitioning and Task-to-Partition Allocation for
Real-Time Workloads | http://arxiv.org/abs/2105.10312v1 | In order to satisfy timing constraints, modern real-time applications require
massively parallel accelerators such as General Purpose Graphic Processing
Units (GPGPUs). Generation after generation, the number of computing clusters
made available in novel GPU architectures is steadily increasing, hence,
investigating su... | true | true | Zahaf, Houssam-Eddine and Olmedo, Ignacio Sanudo and Singh, Jayati and Capodieci, Nicola and Faucou, Sebastien | 2,021 | null | null | 10.1145/3453417.3453439 | null | Contention-Aware GPU Partitioning and Task-to-Partition Allocation for
Real-Time Workloads | Contention-Aware GPU Partitioning and Task-to- ... | http://pagesperso.ls2n.fr/~zahaf-h/research/2021/rtns_2021.pdf | by HE Zahaf · Cited by 12 — Contention-Aware GPU Partitioning and Task-to-Partition Allocation for. Real-Time Workloads. Houssam-Eddine Zahaf, Ignacio Sañudo Olmedo, Jayati Singh, Nicola. |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | abeni2022partitioning | \cite{abeni2022partitioning} | Partitioning real-time workloads on multi-core virtual machines | null | null | true | false | Abeni, Luca and Biondi, Alessandro and Bini, Enrico | 2,022 | null | null | null | Journal of Systems Architecture | Partitioning real-time workloads on multi-core virtual machines | [PDF] Partitioning Real-Time Workloads on Multi-Core Virtual Machines | https://iris.unito.it/retrieve/fb327f6c-20e4-4a18-b202-acf4643df773/main.pdf | duling), this paper proposes and compares some approaches for partitioning the real-time workloads in multi-core VMs. Some of the proposed |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Mo:2023 | \cite{Mo:2023} | Energy Optimized Task Mapping for Reliable and Real-Time Networked Systems | null | null | true | false | Mo, Lei and Zhou, Qi and Kritikakou, Angeliki and Cao, Xianghui | 2,023 | null | null | 10.1145/3584985 | ACM Trans. Sen. Netw. | Energy Optimized Task Mapping for Reliable and Real-Time Networked Systems | Energy Optimized Task Mapping for Reliable and Real-Time ... | https://dl.acm.org/doi/10.1145/3584985 | Energy efficiency, real-time response, and data transmission reliability are important objectives during networked systems design. |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | MDBCCP:13 | \cite{MDBCCP:13} | {Real-time cache management framework for multi-core architectures} | null | null | true | false | Mancuso, Renato and Dudko, Roman and Betti, Emiliano and Cesati, Marco and Caccamo, Marco and Pellizzoni, Rodolfo | 2,013 | null | null | null | null | {Real-time cache management framework for multi-core architectures} | [PDF] Cache Management and Time-triggered Scheduling for Hard Real ... | https://mediatum.ub.tum.de/attfile/1200769/hd2/incoming/2014-Apr/394974.pdf | Real-time cache management framework for multi-core archi- tectures. In 2013 IEEE 19th Real-Time and Embedded Technology and. Applications Symposium (RTAS), |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Kim16:EMSOFT | \cite{Kim16:EMSOFT} | Real-time cache management for multi-core virtualization | null | null | true | false | Kim, Hyoseung and Rajkumar, Ragunathan | 2,016 | null | null | null | null | Real-time cache management for multi-core virtualization | Real-time cache management for multi-core virtualization | https://ieeexplore.ieee.org/document/7743233/ | In this paper, we propose a real-time cache management framework for multi-core virtualization. Our framework introduces two hypervisor-level techniques, vLLC |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | KWCFAS:17 | \cite{KWCFAS:17} | Attacking the One-Out-Of-m Multicore Problem by Combining Hardware Management with Mixed-Criticality Provisioning | null | null | true | false | Kim, Namhoon and Ward, Bryan C. and Chisholm, Micaiah and Fu, Cheng-Yang and Anderson, James H. and Smith, F. Donelson | 2,017 | null | null | null | Real-Time Systems | Attacking the One-Out-Of-m Multicore Problem by Combining Hardware Management with Mixed-Criticality Provisioning | IEEE Real-Time and Embedded Technology and Applications ... | http://www.findresearch.org/conferences/conf/rtas/2016/conference.html | Attacking the One-Out-Of-m Multicore Problem by Combining Hardware Management with Mixed-Criticality Provisioning · Details. Discussion Comments: 0. |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | KSMCV:19 | \cite{KSMCV:19} | Deterministic memory hierarchy and virtualization for modern multi-core embedded systems | null | null | true | false | Tomasz {Kloda} and Marco {Solieri} and Renato {Mancuso} and Nicola {Capodieci} and Paolo {Valente} and Marko {Bertogna} | 2,019 | null | null | null | null | Deterministic memory hierarchy and virtualization for modern multi-core embedded systems | [PDF] The Key Role of Memory in Next-Generation Embedded Systems for ... | https://scispace.com/pdf/the-key-role-of-memory-in-next-generation-embedded-systems-43iu341iwc.pdf | Deterministic Memory Hierarchy and Virtualization for. Modern Multi-Core Embedded Systems. In 25th IEEE Real-Time and Embedded. Technology and Applications |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | xilinx-xen-cache-color | \cite{xilinx-xen-cache-color} | {Xilinx Xen Support with Cache-Coloring} | null | null | true | false | Xilinx | null | null | null | null | null | {Xilinx Xen Support with Cache-Coloring} | Cache Coloring: Interference-free Real-time Virtualization | https://xenproject.org/blog/cache-coloring-interference-free-real-time-virtualization/ | Stefano Stabellini from Xilinx gave a talk on Cache Coloring, a new feature for Xen that helps better support real-time workloads. |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | minerva-jailhouse | \cite{minerva-jailhouse} | {Memory-aware Jailhouse hypervisor} | null | null | true | false | {Minerva Systems} | null | null | null | null | null | {Memory-aware Jailhouse hypervisor} | Understanding the Jailhouse hypervisor, part 1 - LWN.net | https://lwn.net/Articles/578295/ | To enable the hypervisor, Jailhouse needs to initialize its subsystems, create a Linux cell according to the system configuration, enable VT-x on each CPU, and, finally, migrate Linux into its cell to continue running in guest mode. The entry point is defined in hypervisor/setup.c as arch_entry, which is coded in assem... |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Survey-Way-Part | \cite{Survey-Way-Part} | A Survey on Way-Based Cache Partitioning | null | null | true | false | Das, Purnendu and Barbhuiya, Nurulla Mansur and Ranjan Roy, Bishwa | 2,023 | null | null | null | null | A Survey on Way-Based Cache Partitioning | Multi-Objective Memory Bandwidth Regulation and Cache ... | https://arxiv.org/html/2505.11554v1 | A survey on way-based cache partitioning. In IEEE Silchar Subsection Conference (SILCON), pages 1–7, 2023. [18] ↑ Howard David, Chris |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | arm-dynamiciq | \cite{arm-dynamiciq} | {Arm DynamIQ Shared Unit Technical Reference Manual} | null | null | true | false | Arm | null | null | null | null | null | {Arm DynamIQ Shared Unit Technical Reference Manual} | Arm DynamIQ Shared Unit Technical Reference Manual | https://developer.arm.com/documentation/100453/latest/ | This Technical Reference Manual is for the DynamIQ Shared Unit ( DSU ). It describes the overall structure of the DSU including the main interfaces. |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | yun2013memguard | \cite{yun2013memguard} | {MemGuard}: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms | null | null | true | false | Yun, Heechul and Yao, Gang and Pellizzoni, Rodolfo and Caccamo, Marco and Sha, Lui | 2,013 | null | null | null | null | {MemGuard}: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms | SlideShare MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isolation in Multicore Platforms | PPTX | https://www.slideshare.net/slideshow/mem-guard-rtas13web-25212473/25212473 | This document describes MemGuard , an operating system mechanism for providing efficient per- core memory performance isolation on commercial off-the-shelf hardware. MemGuard uses memory bandwidth reservation to guarantee each core 's minimum memory bandwidth . It then performs predictive bandwidth |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | MemPol | \cite{MemPol} | {MemPol}: Policing Core Memory Bandwidth from Outside of the Cores | null | null | true | false | Alexander Zuepke and
Andrea Bastoni and
Weifan Chen and
Marco Caccamo and
Renato Mancuso | 2,023 | null | null | null | null | {MemPol}: Policing Core Memory Bandwidth from Outside of the Cores | [PDF] MemPol: Policing Core Memory Bandwidth from Outside of the Cores | https://blexi.de/papers/rtas2023.pdf | In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core's |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | hassan2019reduced | \cite{hassan2019reduced} | {Reduced latency DRAM for multi-core safety-critical real-time systems} | null | null | true | false | Hassan, Mohamed | 2,019 | null | null | null | Real-Time Systems | {Reduced latency DRAM for multi-core safety-critical real-time systems} | Reduced latency DRAM for multi-core safety-critical real-time ... | https://www.ece.mcmaster.ca/faculty/hassan/assets/publications/hassan2019reduced.pdf | by M Hassan · 2019 · Cited by 16 — Targeting these systems, we promote an alternative off-chip memory solution that is based on the emerging Reduced Latency. DRAM (RLDRAM) protocol, and propose a |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | BRU:20 | \cite{BRU:20} | {BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors} | null | null | true | false | Farshchi, Farzad and Huang, Qijing and Yun, Heechul | 2,020 | null | null | null | null | {BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors} | BRU: Bandwidth Regulation Unit for Real-Time Multicore ... | https://github.com/CSL-KU/bru-firesim | BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors. This repository contains the necessary files to reproduce the experiment results in the |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | intel-rdt | \cite{intel-rdt} | {Resource Director Technology} | null | null | true | false | Intel | null | null | null | null | null | {Resource Director Technology} | Intel® Resource Director Technology (Intel® RDT) | https://www.intel.com/content/www/us/en/architecture-and-technology/resource-director-technology.html | Intel® Resource Director Technology enables monitoring and control over shared processor resources, improved consolidation density and reduced TCO. |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | XPCLLLL:19 | \cite{XPCLLLL:19} | Holistic resource allocation for multicore real-time systems | null | null | true | false | Xu, Meng and Phan, Linh Thi Xuan and Choi, Hyon-Young and Lin, Yuhan and Li, Haoran and Lu, Chenyang and Lee, Insup | 2,019 | null | null | null | null | Holistic resource allocation for multicore real-time systems | Holistic resource allocation for multicore real-time systems ... | https://www.cis.upenn.edu/~linhphan/papers/rtas19-CaM-techreport.pdf | Rather than decoupling them, we compute the mapping of tasks and the allocation of shared resources to cores in an integrated resource allocation strategy called CaM that considers the demands on CPU, cache, and memory bandwidth concurrently to minimize resources while ensuring timing guarantees. Existing work has also... |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | SBMYK:22 | \cite{SBMYK:22} | {A Closer Look at Intel Resource Director Technology (RDT)} | null | null | true | false | Sohal, Parul and Bechtel, Michael and Mancuso, Renato and Yun, Heechul and Krieger, Orran | 2,022 | null | null | null | null | {A Closer Look at Intel Resource Director Technology (RDT)} | A Closer Look at Intel Resource Director Technology (RDT) | https://dl.acm.org/doi/abs/10.1145/3534879.3534882 | We aim at conducting a systematic investigation of the RDT mechanisms from a real-time perspective. We experimentally evaluate the functionality and |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | arm-mpam | \cite{arm-mpam} | {Arm Memory System Resource Partitioning and Monitoring (MPAM) System Component Specification} | null | null | true | false | Arm | null | null | null | null | null | {Arm Memory System Resource Partitioning and Monitoring (MPAM) System Component Specification} | Memory System Resource Partitioning and Monitoring (MPAM ... | https://developer.arm.com/documentation/107768/latest/Overview | MPAM is an optional Arm architecture addition for memory system partitioning. It's documented in two specifications, one for processor features and one for |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Altmeyer:2014 | \cite{Altmeyer:2014} | OUTSTANDING PAPER: Evaluation of Cache Partitioning for Hard Real-Time Systems | null | null | true | false | Altmeyer, Sebastian and Douma, Roeland and Lunniss, Will and Davis, Robert I. | 2,014 | null | null | 10.1109/ECRTS.2014.11 | null | OUTSTANDING PAPER: Evaluation of Cache Partitioning for Hard Real-Time Systems | Will Lunniss - Google Scholar | https://scholar.google.com/citations?user=v_HmmSsAAAAJ&hl=en | Outstanding paper: Evaluation of cache partitioning for hard real-time systems. S Altmeyer, R Douma, W Lunniss, RI Davis. 2014 26th Euromicro Conference on Real |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Altmeyer:2016 | \cite{Altmeyer:2016} | On the effectiveness of cache partitioning in hard real-time systems | null | null | true | false | Sebastian A. Altmeyer and Roeland Douma and Will Lunniss and Robert I. Davis | 2,016 | null | null | null | Real Time Systems | On the effectiveness of cache partitioning in hard real-time systems | [PDF] On the effectiveness of cache partitioning in hard real-time systems | https://eprints.whiterose.ac.uk/id/eprint/93504/1/art_3A10.1007_2Fs11241_015_9246_8.pdf | Cache partitioning is often suggested as a means of increasing the predictability of caches in pre-emptively scheduled hard real-time systems. The rationale |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Bui:2008 | \cite{Bui:2008} | Impact of cache partitioning on multi-tasking real time embedded systems | null | null | true | false | Bui, Bach D. and Caccamo, Marco and Sha, Lui and Martinez, Joseph | 2,008 | null | null | null | null | Impact of cache partitioning on multi-tasking real time embedded systems | Impact of cache partitioning on multi-tasking real time ... | https://experts.illinois.edu/en/publications/impact-of-cache-partitioning-on-multi-tasking-real-time-embedded- | by BD Bui · 2008 · Cited by 159 — A case study and experiments show that in a typical real-time embedded system, the proposed algorithm is able to reduce the worst-case utilization by 15% (on |
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for
Multicore Real-Time Systems | 2505.11554v1 | Meroni:2023 | \cite{Meroni:2023} | Mapping and Integration of Event- and Time-triggered Real-time Tasks on Partitioned Multi-core Systems | null | null | true | false | Meroni, Carlo and Craciunas, Silviu S. and Finzi, Anaïs and Pop, Paul | 2,023 | null | null | 10.1109/ETFA54631.2023.10275547 | null | Mapping and Integration of Event- and Time-triggered Real-time Tasks on Partitioned Multi-core Systems | Multi-Objective Memory Bandwidth Regulation and Cache ... - DROPS | https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2025.2 | Mapping and integration of event- and time-triggered real-time tasks on partitioned multi-core systems. In 2023 IEEE 28th International Conference on |
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