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e98d6132cf0f6481a02a3c132eeaa217a8b303a2 | 53,845 | asm | Assembly | components/x264/x264-snapshot-20181221-2245-stable/common/x86/sad-a.asm | plkumar/esp32-homekit-camera | 9ae7bf0482bfa08eec7a7e52a920a2664e19f7d6 | [
"MIT"
] | 286 | 2019-01-09T14:33:32.000Z | 2022-03-29T00:18:28.000Z | components/x264/x264-snapshot-20181221-2245-stable/common/x86/sad-a.asm | jangolen/esp32-homekit-camera | 8a2f6e5e92c148853f681b427cd7c73e30ec3f57 | [
"MIT"
] | 95 | 2019-01-13T13:14:12.000Z | 2022-03-26T16:15:50.000Z | components/x264/x264-snapshot-20181221-2245-stable/common/x86/sad-a.asm | jangolen/esp32-homekit-camera | 8a2f6e5e92c148853f681b427cd7c73e30ec3f57 | [
"MIT"
] | 71 | 2019-01-07T22:56:17.000Z | 2022-03-03T19:53:37.000Z | ;*****************************************************************************
;* sad-a.asm: x86 sad functions
;*****************************************************************************
;* Copyright (C) 2003-2018 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Fiona Glaser <fiona@x264.com>
;* Laurent Aimar <fenrir@via.ecp.fr>
;* Alex Izvorski <aizvorksi@gmail.com>
;*
;* This program is free software; you can redistribute it and/or modify
;* it under the terms of the GNU General Public License as published by
;* the Free Software Foundation; either version 2 of the License, or
;* (at your option) any later version.
;*
;* This program is distributed in the hope that it will be useful,
;* but WITHOUT ANY WARRANTY; without even the implied warranty of
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;* GNU General Public License for more details.
;*
;* You should have received a copy of the GNU General Public License
;* along with this program; if not, write to the Free Software
;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
;*
;* This program is also available under a commercial proprietary license.
;* For more information, contact us at licensing@x264.com.
;*****************************************************************************
%include "x86inc.asm"
%include "x86util.asm"
SECTION_RODATA 32
pb_shuf8x8c2: times 2 db 0,0,0,0,8,8,8,8,-1,-1,-1,-1,-1,-1,-1,-1
hpred_shuf: db 0,0,2,2,8,8,10,10,1,1,3,3,9,9,11,11
SECTION .text
cextern pb_3
cextern pb_shuf8x8c
cextern pw_8
cextern sw_64
;=============================================================================
; SAD MMX
;=============================================================================
%macro SAD_INC_2x16P 0
movq mm1, [r0]
movq mm2, [r0+8]
movq mm3, [r0+r1]
movq mm4, [r0+r1+8]
psadbw mm1, [r2]
psadbw mm2, [r2+8]
psadbw mm3, [r2+r3]
psadbw mm4, [r2+r3+8]
lea r0, [r0+2*r1]
paddw mm1, mm2
paddw mm3, mm4
lea r2, [r2+2*r3]
paddw mm0, mm1
paddw mm0, mm3
%endmacro
%macro SAD_INC_2x8P 0
movq mm1, [r0]
movq mm2, [r0+r1]
psadbw mm1, [r2]
psadbw mm2, [r2+r3]
lea r0, [r0+2*r1]
paddw mm0, mm1
paddw mm0, mm2
lea r2, [r2+2*r3]
%endmacro
%macro SAD_INC_2x4P 0
movd mm1, [r0]
movd mm2, [r2]
punpckldq mm1, [r0+r1]
punpckldq mm2, [r2+r3]
psadbw mm1, mm2
paddw mm0, mm1
lea r0, [r0+2*r1]
lea r2, [r2+2*r3]
%endmacro
;-----------------------------------------------------------------------------
; int pixel_sad_16x16( uint8_t *, intptr_t, uint8_t *, intptr_t )
;-----------------------------------------------------------------------------
%macro SAD 2
cglobal pixel_sad_%1x%2_mmx2, 4,4
pxor mm0, mm0
%rep %2/2
SAD_INC_2x%1P
%endrep
movd eax, mm0
RET
%endmacro
SAD 16, 16
SAD 16, 8
SAD 8, 16
SAD 8, 8
SAD 8, 4
SAD 4, 16
SAD 4, 8
SAD 4, 4
;=============================================================================
; SAD XMM
;=============================================================================
%macro SAD_END_SSE2 0
MOVHL m1, m0
paddw m0, m1
movd eax, m0
RET
%endmacro
;-----------------------------------------------------------------------------
; int pixel_sad_16x16( uint8_t *, intptr_t, uint8_t *, intptr_t )
;-----------------------------------------------------------------------------
%macro SAD_W16 1 ; h
cglobal pixel_sad_16x%1, 4,4
%ifidn cpuname, sse2
.skip_prologue:
%endif
%assign %%i 0
%if ARCH_X86_64
lea r6, [3*r1] ; r6 results in fewer REX prefixes than r4 and both are volatile
lea r5, [3*r3]
%rep %1/4
movu m1, [r2]
psadbw m1, [r0]
movu m3, [r2+r3]
psadbw m3, [r0+r1]
movu m2, [r2+2*r3]
psadbw m2, [r0+2*r1]
movu m4, [r2+r5]
psadbw m4, [r0+r6]
%if %%i != %1/4-1
lea r2, [r2+4*r3]
lea r0, [r0+4*r1]
%endif
paddw m1, m3
paddw m2, m4
ACCUM paddw, 0, 1, %%i
paddw m0, m2
%assign %%i %%i+1
%endrep
%else ; The cost of having to save and restore registers on x86-32
%rep %1/2 ; nullifies the benefit of having 3*stride in registers.
movu m1, [r2]
psadbw m1, [r0]
movu m2, [r2+r3]
psadbw m2, [r0+r1]
%if %%i != %1/2-1
lea r2, [r2+2*r3]
lea r0, [r0+2*r1]
%endif
ACCUM paddw, 0, 1, %%i
paddw m0, m2
%assign %%i %%i+1
%endrep
%endif
SAD_END_SSE2
%endmacro
INIT_XMM sse2
SAD_W16 16
SAD_W16 8
INIT_XMM sse3
SAD_W16 16
SAD_W16 8
INIT_XMM sse2, aligned
SAD_W16 16
SAD_W16 8
%macro SAD_INC_4x8P_SSE 1
movq m1, [r0]
movq m2, [r0+r1]
lea r0, [r0+2*r1]
movq m3, [r2]
movq m4, [r2+r3]
lea r2, [r2+2*r3]
movhps m1, [r0]
movhps m2, [r0+r1]
movhps m3, [r2]
movhps m4, [r2+r3]
lea r0, [r0+2*r1]
psadbw m1, m3
psadbw m2, m4
lea r2, [r2+2*r3]
ACCUM paddw, 0, 1, %1
paddw m0, m2
%endmacro
INIT_XMM
;Even on Nehalem, no sizes other than 8x16 benefit from this method.
cglobal pixel_sad_8x16_sse2, 4,4
SAD_INC_4x8P_SSE 0
SAD_INC_4x8P_SSE 1
SAD_INC_4x8P_SSE 1
SAD_INC_4x8P_SSE 1
SAD_END_SSE2
%macro SAD_W48_AVX512 3 ; w, h, d/q
cglobal pixel_sad_%1x%2, 4,4
kxnorb k1, k1, k1
kaddb k1, k1, k1
%assign %%i 0
%if ARCH_X86_64 && %2 != 4
lea r6, [3*r1]
lea r5, [3*r3]
%rep %2/4
mov%3 m1, [r0]
vpbroadcast%3 m1 {k1}, [r0+r1]
mov%3 m3, [r2]
vpbroadcast%3 m3 {k1}, [r2+r3]
mov%3 m2, [r0+2*r1]
vpbroadcast%3 m2 {k1}, [r0+r6]
mov%3 m4, [r2+2*r3]
vpbroadcast%3 m4 {k1}, [r2+r5]
%if %%i != %2/4-1
lea r0, [r0+4*r1]
lea r2, [r2+4*r3]
%endif
psadbw m1, m3
psadbw m2, m4
ACCUM paddd, 0, 1, %%i
paddd m0, m2
%assign %%i %%i+1
%endrep
%else
%rep %2/2
mov%3 m1, [r0]
vpbroadcast%3 m1 {k1}, [r0+r1]
mov%3 m2, [r2]
vpbroadcast%3 m2 {k1}, [r2+r3]
%if %%i != %2/2-1
lea r0, [r0+2*r1]
lea r2, [r2+2*r3]
%endif
psadbw m1, m2
ACCUM paddd, 0, 1, %%i
%assign %%i %%i+1
%endrep
%endif
%if %1 == 8
punpckhqdq m1, m0, m0
paddd m0, m1
%endif
movd eax, m0
RET
%endmacro
INIT_XMM avx512
SAD_W48_AVX512 4, 4, d
SAD_W48_AVX512 4, 8, d
SAD_W48_AVX512 4, 16, d
SAD_W48_AVX512 8, 4, q
SAD_W48_AVX512 8, 8, q
SAD_W48_AVX512 8, 16, q
%macro SAD_W16_AVX512_START 1 ; h
cmp r1d, FENC_STRIDE ; optimized for the most common fenc case, which
jne pixel_sad_16x%1_sse2.skip_prologue ; has the rows laid out contiguously in memory
lea r1, [3*r3]
%endmacro
%macro SAD_W16_AVX512_END 0
paddd m0, m1
paddd m0, m2
paddd m0, m3
%if mmsize == 64
vextracti32x8 ym1, m0, 1
paddd ym0, ym1
%endif
vextracti128 xm1, ym0, 1
paddd xmm0, xm0, xm1
punpckhqdq xmm1, xmm0, xmm0
paddd xmm0, xmm1
movd eax, xmm0
RET
%endmacro
INIT_YMM avx512
cglobal pixel_sad_16x8, 4,4
SAD_W16_AVX512_START 8
movu xm0, [r2]
vinserti128 m0, [r2+r3], 1
psadbw m0, [r0+0*32]
movu xm1, [r2+2*r3]
vinserti128 m1, [r2+r1], 1
lea r2, [r2+4*r3]
psadbw m1, [r0+1*32]
movu xm2, [r2]
vinserti128 m2, [r2+r3], 1
psadbw m2, [r0+2*32]
movu xm3, [r2+2*r3]
vinserti128 m3, [r2+r1], 1
psadbw m3, [r0+3*32]
SAD_W16_AVX512_END
INIT_ZMM avx512
cglobal pixel_sad_16x16, 4,4
SAD_W16_AVX512_START 16
movu xm0, [r2]
vinserti128 ym0, [r2+r3], 1
movu xm1, [r2+4*r3]
vinserti32x4 m0, [r2+2*r3], 2
vinserti32x4 m1, [r2+2*r1], 2
vinserti32x4 m0, [r2+r1], 3
lea r2, [r2+4*r3]
vinserti32x4 m1, [r2+r3], 1
psadbw m0, [r0+0*64]
vinserti32x4 m1, [r2+r1], 3
lea r2, [r2+4*r3]
psadbw m1, [r0+1*64]
movu xm2, [r2]
vinserti128 ym2, [r2+r3], 1
movu xm3, [r2+4*r3]
vinserti32x4 m2, [r2+2*r3], 2
vinserti32x4 m3, [r2+2*r1], 2
vinserti32x4 m2, [r2+r1], 3
lea r2, [r2+4*r3]
vinserti32x4 m3, [r2+r3], 1
psadbw m2, [r0+2*64]
vinserti32x4 m3, [r2+r1], 3
psadbw m3, [r0+3*64]
SAD_W16_AVX512_END
;-----------------------------------------------------------------------------
; void pixel_vsad( pixel *src, intptr_t stride );
;-----------------------------------------------------------------------------
%if ARCH_X86_64 == 0
INIT_MMX
cglobal pixel_vsad_mmx2, 3,3
mova m0, [r0]
mova m1, [r0+8]
mova m2, [r0+r1]
mova m3, [r0+r1+8]
lea r0, [r0+r1*2]
psadbw m0, m2
psadbw m1, m3
paddw m0, m1
sub r2d, 2
je .end
.loop:
mova m4, [r0]
mova m5, [r0+8]
mova m6, [r0+r1]
mova m7, [r0+r1+8]
lea r0, [r0+r1*2]
psadbw m2, m4
psadbw m3, m5
psadbw m4, m6
psadbw m5, m7
;max sum: 31*16*255(pixel_max)=126480
paddd m0, m2
paddd m0, m3
paddd m0, m4
paddd m0, m5
mova m2, m6
mova m3, m7
sub r2d, 2
jg .loop
.end:
movd eax, m0
RET
%endif
INIT_XMM
cglobal pixel_vsad_sse2, 3,3
mova m0, [r0]
mova m1, [r0+r1]
lea r0, [r0+r1*2]
psadbw m0, m1
sub r2d, 2
je .end
.loop:
mova m2, [r0]
mova m3, [r0+r1]
lea r0, [r0+r1*2]
psadbw m1, m2
psadbw m2, m3
paddw m0, m1
paddw m0, m2
mova m1, m3
sub r2d, 2
jg .loop
.end:
MOVHL m1, m0
;max sum: 31*16*255(pixel_max)=126480
paddd m0, m1
movd eax, m0
RET
;-----------------------------------------------------------------------------
; void intra_sad_x3_4x4( uint8_t *fenc, uint8_t *fdec, int res[3] );
;-----------------------------------------------------------------------------
cglobal intra_sad_x3_4x4_mmx2, 3,3
pxor mm7, mm7
movd mm0, [r1-FDEC_STRIDE]
movd mm1, [r0+FENC_STRIDE*0]
movd mm2, [r0+FENC_STRIDE*2]
punpckldq mm0, mm0
punpckldq mm1, [r0+FENC_STRIDE*1]
punpckldq mm2, [r0+FENC_STRIDE*3]
movq mm6, mm0
movq mm3, mm1
psadbw mm3, mm0
psadbw mm0, mm2
paddw mm0, mm3
movd [r2], mm0 ;V prediction cost
movd mm3, [r1+FDEC_STRIDE*0-4]
movd mm0, [r1+FDEC_STRIDE*1-4]
movd mm4, [r1+FDEC_STRIDE*2-4]
movd mm5, [r1+FDEC_STRIDE*3-4]
punpcklbw mm3, mm0
punpcklbw mm4, mm5
movq mm5, mm3
punpckhwd mm5, mm4
punpckhdq mm5, mm6
psadbw mm5, mm7
punpckhbw mm3, mm3
punpckhbw mm4, mm4
punpckhwd mm3, mm3
punpckhwd mm4, mm4
psraw mm5, 2
pavgw mm5, mm7
punpcklbw mm5, mm5
pshufw mm5, mm5, 0 ;DC prediction
movq mm6, mm5
psadbw mm5, mm1
psadbw mm6, mm2
psadbw mm1, mm3
psadbw mm2, mm4
paddw mm5, mm6
paddw mm1, mm2
movd [r2+8], mm5 ;DC prediction cost
movd [r2+4], mm1 ;H prediction cost
RET
;-----------------------------------------------------------------------------
; void intra_sad_x3_8x8( uint8_t *fenc, uint8_t edge[36], int res[3]);
;-----------------------------------------------------------------------------
;m0 = DC
;m6 = V
;m7 = H
;m1 = DC score
;m2 = V score
;m3 = H score
;m5 = pixel row
;m4 = temp
%macro INTRA_SAD_HVDC_ITER 2
movq m5, [r0+FENC_STRIDE*%1]
movq m4, m5
psadbw m4, m0
ACCUM paddw, 1, 4, %1
movq m4, m5
psadbw m4, m6
ACCUM paddw, 2, 4, %1
pshufw m4, m7, %2
psadbw m5, m4
ACCUM paddw, 3, 5, %1
%endmacro
INIT_MMX
cglobal intra_sad_x3_8x8_mmx2, 3,3
movq m7, [r1+7]
pxor m0, m0
movq m6, [r1+16] ;V prediction
pxor m1, m1
psadbw m0, m7
psadbw m1, m6
paddw m0, m1
paddw m0, [pw_8]
psrlw m0, 4
punpcklbw m0, m0
pshufw m0, m0, q0000 ;DC prediction
punpckhbw m7, m7
INTRA_SAD_HVDC_ITER 0, q3333
INTRA_SAD_HVDC_ITER 1, q2222
INTRA_SAD_HVDC_ITER 2, q1111
INTRA_SAD_HVDC_ITER 3, q0000
movq m7, [r1+7]
punpcklbw m7, m7
INTRA_SAD_HVDC_ITER 4, q3333
INTRA_SAD_HVDC_ITER 5, q2222
INTRA_SAD_HVDC_ITER 6, q1111
INTRA_SAD_HVDC_ITER 7, q0000
movd [r2+0], m2
movd [r2+4], m3
movd [r2+8], m1
RET
;-----------------------------------------------------------------------------
; void intra_sad_x3_8x8c( uint8_t *fenc, uint8_t *fdec, int res[3] );
;-----------------------------------------------------------------------------
%macro INTRA_SAD_HV_ITER 1
%if cpuflag(ssse3)
movd m1, [r1 + FDEC_STRIDE*(%1-4) - 4]
movd m3, [r1 + FDEC_STRIDE*(%1-3) - 4]
pshufb m1, m7
pshufb m3, m7
%else
movq m1, [r1 + FDEC_STRIDE*(%1-4) - 8]
movq m3, [r1 + FDEC_STRIDE*(%1-3) - 8]
punpckhbw m1, m1
punpckhbw m3, m3
pshufw m1, m1, q3333
pshufw m3, m3, q3333
%endif
movq m4, [r0 + FENC_STRIDE*(%1+0)]
movq m5, [r0 + FENC_STRIDE*(%1+1)]
psadbw m1, m4
psadbw m3, m5
psadbw m4, m6
psadbw m5, m6
paddw m1, m3
paddw m4, m5
ACCUM paddw, 0, 1, %1
ACCUM paddw, 2, 4, %1
%endmacro
%macro INTRA_SAD_8x8C 0
cglobal intra_sad_x3_8x8c, 3,3
movq m6, [r1 - FDEC_STRIDE]
add r1, FDEC_STRIDE*4
%if cpuflag(ssse3)
movq m7, [pb_3]
%endif
INTRA_SAD_HV_ITER 0
INTRA_SAD_HV_ITER 2
INTRA_SAD_HV_ITER 4
INTRA_SAD_HV_ITER 6
movd [r2+4], m0
movd [r2+8], m2
pxor m7, m7
movq m2, [r1 + FDEC_STRIDE*-4 - 8]
movq m4, [r1 + FDEC_STRIDE*-2 - 8]
movq m3, [r1 + FDEC_STRIDE* 0 - 8]
movq m5, [r1 + FDEC_STRIDE* 2 - 8]
punpckhbw m2, [r1 + FDEC_STRIDE*-3 - 8]
punpckhbw m4, [r1 + FDEC_STRIDE*-1 - 8]
punpckhbw m3, [r1 + FDEC_STRIDE* 1 - 8]
punpckhbw m5, [r1 + FDEC_STRIDE* 3 - 8]
punpckhbw m2, m4
punpckhbw m3, m5
psrlq m2, 32
psrlq m3, 32
psadbw m2, m7 ; s2
psadbw m3, m7 ; s3
movq m1, m6
SWAP 0, 6
punpckldq m0, m7
punpckhdq m1, m7
psadbw m0, m7 ; s0
psadbw m1, m7 ; s1
punpcklwd m0, m1
punpcklwd m2, m3
punpckldq m0, m2 ;s0 s1 s2 s3
pshufw m3, m0, q3312 ;s2,s1,s3,s3
pshufw m0, m0, q1310 ;s0,s1,s3,s1
paddw m0, m3
psrlw m0, 2
pavgw m0, m7 ; s0+s2, s1, s3, s1+s3
%if cpuflag(ssse3)
movq2dq xmm0, m0
pshufb xmm0, [pb_shuf8x8c]
movq xmm1, [r0+FENC_STRIDE*0]
movq xmm2, [r0+FENC_STRIDE*1]
movq xmm3, [r0+FENC_STRIDE*2]
movq xmm4, [r0+FENC_STRIDE*3]
movhps xmm1, [r0+FENC_STRIDE*4]
movhps xmm2, [r0+FENC_STRIDE*5]
movhps xmm3, [r0+FENC_STRIDE*6]
movhps xmm4, [r0+FENC_STRIDE*7]
psadbw xmm1, xmm0
psadbw xmm2, xmm0
psadbw xmm3, xmm0
psadbw xmm4, xmm0
paddw xmm1, xmm2
paddw xmm1, xmm3
paddw xmm1, xmm4
MOVHL xmm0, xmm1
paddw xmm1, xmm0
movd [r2], xmm1
%else
packuswb m0, m0
punpcklbw m0, m0
movq m1, m0
punpcklbw m0, m0 ; 4x dc0 4x dc1
punpckhbw m1, m1 ; 4x dc2 4x dc3
movq m2, [r0+FENC_STRIDE*0]
movq m3, [r0+FENC_STRIDE*1]
movq m4, [r0+FENC_STRIDE*2]
movq m5, [r0+FENC_STRIDE*3]
movq m6, [r0+FENC_STRIDE*4]
movq m7, [r0+FENC_STRIDE*5]
psadbw m2, m0
psadbw m3, m0
psadbw m4, m0
psadbw m5, m0
movq m0, [r0+FENC_STRIDE*6]
psadbw m6, m1
psadbw m7, m1
psadbw m0, m1
psadbw m1, [r0+FENC_STRIDE*7]
paddw m2, m3
paddw m4, m5
paddw m6, m7
paddw m0, m1
paddw m2, m4
paddw m6, m0
paddw m2, m6
movd [r2], m2
%endif
RET
%endmacro
INIT_MMX mmx2
INTRA_SAD_8x8C
INIT_MMX ssse3
INTRA_SAD_8x8C
INIT_YMM avx2
cglobal intra_sad_x3_8x8c, 3,3,7
vpbroadcastq m2, [r1 - FDEC_STRIDE] ; V pred
add r1, FDEC_STRIDE*4-1
pxor xm5, xm5
punpckldq xm3, xm2, xm5 ; V0 _ V1 _
movd xm0, [r1 + FDEC_STRIDE*-1 - 3]
movd xm1, [r1 + FDEC_STRIDE* 3 - 3]
pinsrb xm0, [r1 + FDEC_STRIDE*-4], 0
pinsrb xm1, [r1 + FDEC_STRIDE* 0], 0
pinsrb xm0, [r1 + FDEC_STRIDE*-3], 1
pinsrb xm1, [r1 + FDEC_STRIDE* 1], 1
pinsrb xm0, [r1 + FDEC_STRIDE*-2], 2
pinsrb xm1, [r1 + FDEC_STRIDE* 2], 2
punpcklqdq xm0, xm1 ; H0 _ H1 _
vinserti128 m3, m3, xm0, 1 ; V0 V1 H0 H1
pshufb xm0, [hpred_shuf] ; H00224466 H11335577
psadbw m3, m5 ; s0 s1 s2 s3
vpermq m4, m3, q3312 ; s2 s1 s3 s3
vpermq m3, m3, q1310 ; s0 s1 s3 s1
paddw m3, m4
psrlw m3, 2
pavgw m3, m5 ; s0+s2 s1 s3 s1+s3
pshufb m3, [pb_shuf8x8c2] ; DC0 _ DC1 _
vpblendd m3, m3, m2, 11001100b ; DC0 V DC1 V
vinserti128 m1, m3, xm3, 1 ; DC0 V DC0 V
vperm2i128 m6, m3, m3, q0101 ; DC1 V DC1 V
vpermq m0, m0, q3120 ; H00224466 _ H11335577 _
movddup m2, [r0+FENC_STRIDE*0]
movddup m4, [r0+FENC_STRIDE*2]
pshuflw m3, m0, q0000
psadbw m3, m2
psadbw m2, m1
pshuflw m5, m0, q1111
psadbw m5, m4
psadbw m4, m1
paddw m2, m4
paddw m3, m5
movddup m4, [r0+FENC_STRIDE*4]
pshuflw m5, m0, q2222
psadbw m5, m4
psadbw m4, m6
paddw m2, m4
paddw m3, m5
movddup m4, [r0+FENC_STRIDE*6]
pshuflw m5, m0, q3333
psadbw m5, m4
psadbw m4, m6
paddw m2, m4
paddw m3, m5
vextracti128 xm0, m2, 1
vextracti128 xm1, m3, 1
paddw xm2, xm0 ; DC V
paddw xm3, xm1 ; H
pextrd [r2+8], xm2, 2 ; V
movd [r2+4], xm3 ; H
movd [r2+0], xm2 ; DC
RET
;-----------------------------------------------------------------------------
; void intra_sad_x3_16x16( uint8_t *fenc, uint8_t *fdec, int res[3] );
;-----------------------------------------------------------------------------
;xmm7: DC prediction xmm6: H prediction xmm5: V prediction
;xmm4: DC pred score xmm3: H pred score xmm2: V pred score
%macro INTRA_SAD16 0
cglobal intra_sad_x3_16x16, 3,5,8
pxor mm0, mm0
pxor mm1, mm1
psadbw mm0, [r1-FDEC_STRIDE+0]
psadbw mm1, [r1-FDEC_STRIDE+8]
paddw mm0, mm1
movd r3d, mm0
%if cpuflag(ssse3)
mova m1, [pb_3]
%endif
%assign x 0
%rep 16
movzx r4d, byte [r1-1+FDEC_STRIDE*(x&3)]
%if (x&3)==3 && x!=15
add r1, FDEC_STRIDE*4
%endif
add r3d, r4d
%assign x x+1
%endrep
sub r1, FDEC_STRIDE*12
add r3d, 16
shr r3d, 5
imul r3d, 0x01010101
movd m7, r3d
mova m5, [r1-FDEC_STRIDE]
%if mmsize==16
pshufd m7, m7, 0
%else
mova m1, [r1-FDEC_STRIDE+8]
punpckldq m7, m7
%endif
pxor m4, m4
pxor m3, m3
pxor m2, m2
mov r3d, 15*FENC_STRIDE
.vloop:
SPLATB_LOAD m6, r1+r3*2-1, m1
mova m0, [r0+r3]
psadbw m0, m7
paddw m4, m0
mova m0, [r0+r3]
psadbw m0, m5
paddw m2, m0
%if mmsize==8
mova m0, [r0+r3]
psadbw m0, m6
paddw m3, m0
mova m0, [r0+r3+8]
psadbw m0, m7
paddw m4, m0
mova m0, [r0+r3+8]
psadbw m0, m1
paddw m2, m0
psadbw m6, [r0+r3+8]
paddw m3, m6
%else
psadbw m6, [r0+r3]
paddw m3, m6
%endif
add r3d, -FENC_STRIDE
jge .vloop
%if mmsize==16
pslldq m3, 4
por m3, m2
MOVHL m1, m3
paddw m3, m1
movq [r2+0], m3
MOVHL m1, m4
paddw m4, m1
%else
movd [r2+0], m2
movd [r2+4], m3
%endif
movd [r2+8], m4
RET
%endmacro
INIT_MMX mmx2
INTRA_SAD16
INIT_XMM sse2
INTRA_SAD16
INIT_XMM ssse3
INTRA_SAD16
INIT_YMM avx2
cglobal intra_sad_x3_16x16, 3,5,6
pxor xm0, xm0
psadbw xm0, [r1-FDEC_STRIDE]
MOVHL xm1, xm0
paddw xm0, xm1
movd r3d, xm0
%assign x 0
%rep 16
movzx r4d, byte [r1-1+FDEC_STRIDE*(x&3)]
%if (x&3)==3 && x!=15
add r1, FDEC_STRIDE*4
%endif
add r3d, r4d
%assign x x+1
%endrep
sub r1, FDEC_STRIDE*12
add r3d, 16
shr r3d, 5
movd xm5, r3d
vpbroadcastb xm5, xm5
vinserti128 m5, m5, [r1-FDEC_STRIDE], 1 ; m5 contains DC and V prediction
pxor m4, m4 ; DC / V accumulator
pxor xm3, xm3 ; H accumulator
mov r3d, 15*FENC_STRIDE
.vloop:
vpbroadcastb xm2, [r1+r3*2-1]
vbroadcasti128 m0, [r0+r3]
psadbw m1, m0, m5
psadbw xm0, xm2
paddw m4, m1
paddw xm3, xm0
add r3d, -FENC_STRIDE
jge .vloop
punpckhqdq m5, m4, m4
MOVHL xm2, xm3
paddw m4, m5 ; DC / V
paddw xm3, xm2 ; H
vextracti128 xm2, m4, 1
movd [r2+0], xm2
movd [r2+4], xm3
movd [r2+8], xm4
RET
;=============================================================================
; SAD x3/x4 MMX
;=============================================================================
%macro SAD_X3_START_1x8P 0
movq mm3, [r0]
movq mm0, [r1]
movq mm1, [r2]
movq mm2, [r3]
psadbw mm0, mm3
psadbw mm1, mm3
psadbw mm2, mm3
%endmacro
%macro SAD_X3_1x8P 2
movq mm3, [r0+%1]
movq mm4, [r1+%2]
movq mm5, [r2+%2]
movq mm6, [r3+%2]
psadbw mm4, mm3
psadbw mm5, mm3
psadbw mm6, mm3
paddw mm0, mm4
paddw mm1, mm5
paddw mm2, mm6
%endmacro
%macro SAD_X3_START_2x4P 3
movd mm3, [r0]
movd %1, [r1]
movd %2, [r2]
movd %3, [r3]
punpckldq mm3, [r0+FENC_STRIDE]
punpckldq %1, [r1+r4]
punpckldq %2, [r2+r4]
punpckldq %3, [r3+r4]
psadbw %1, mm3
psadbw %2, mm3
psadbw %3, mm3
%endmacro
%macro SAD_X3_2x16P 1
%if %1
SAD_X3_START_1x8P
%else
SAD_X3_1x8P 0, 0
%endif
SAD_X3_1x8P 8, 8
SAD_X3_1x8P FENC_STRIDE, r4
SAD_X3_1x8P FENC_STRIDE+8, r4+8
add r0, 2*FENC_STRIDE
lea r1, [r1+2*r4]
lea r2, [r2+2*r4]
lea r3, [r3+2*r4]
%endmacro
%macro SAD_X3_2x8P 1
%if %1
SAD_X3_START_1x8P
%else
SAD_X3_1x8P 0, 0
%endif
SAD_X3_1x8P FENC_STRIDE, r4
add r0, 2*FENC_STRIDE
lea r1, [r1+2*r4]
lea r2, [r2+2*r4]
lea r3, [r3+2*r4]
%endmacro
%macro SAD_X3_2x4P 1
%if %1
SAD_X3_START_2x4P mm0, mm1, mm2
%else
SAD_X3_START_2x4P mm4, mm5, mm6
paddw mm0, mm4
paddw mm1, mm5
paddw mm2, mm6
%endif
add r0, 2*FENC_STRIDE
lea r1, [r1+2*r4]
lea r2, [r2+2*r4]
lea r3, [r3+2*r4]
%endmacro
%macro SAD_X4_START_1x8P 0
movq mm7, [r0]
movq mm0, [r1]
movq mm1, [r2]
movq mm2, [r3]
movq mm3, [r4]
psadbw mm0, mm7
psadbw mm1, mm7
psadbw mm2, mm7
psadbw mm3, mm7
%endmacro
%macro SAD_X4_1x8P 2
movq mm7, [r0+%1]
movq mm4, [r1+%2]
movq mm5, [r2+%2]
movq mm6, [r3+%2]
psadbw mm4, mm7
psadbw mm5, mm7
psadbw mm6, mm7
psadbw mm7, [r4+%2]
paddw mm0, mm4
paddw mm1, mm5
paddw mm2, mm6
paddw mm3, mm7
%endmacro
%macro SAD_X4_START_2x4P 0
movd mm7, [r0]
movd mm0, [r1]
movd mm1, [r2]
movd mm2, [r3]
movd mm3, [r4]
punpckldq mm7, [r0+FENC_STRIDE]
punpckldq mm0, [r1+r5]
punpckldq mm1, [r2+r5]
punpckldq mm2, [r3+r5]
punpckldq mm3, [r4+r5]
psadbw mm0, mm7
psadbw mm1, mm7
psadbw mm2, mm7
psadbw mm3, mm7
%endmacro
%macro SAD_X4_INC_2x4P 0
movd mm7, [r0]
movd mm4, [r1]
movd mm5, [r2]
punpckldq mm7, [r0+FENC_STRIDE]
punpckldq mm4, [r1+r5]
punpckldq mm5, [r2+r5]
psadbw mm4, mm7
psadbw mm5, mm7
paddw mm0, mm4
paddw mm1, mm5
movd mm4, [r3]
movd mm5, [r4]
punpckldq mm4, [r3+r5]
punpckldq mm5, [r4+r5]
psadbw mm4, mm7
psadbw mm5, mm7
paddw mm2, mm4
paddw mm3, mm5
%endmacro
%macro SAD_X4_2x16P 1
%if %1
SAD_X4_START_1x8P
%else
SAD_X4_1x8P 0, 0
%endif
SAD_X4_1x8P 8, 8
SAD_X4_1x8P FENC_STRIDE, r5
SAD_X4_1x8P FENC_STRIDE+8, r5+8
add r0, 2*FENC_STRIDE
lea r1, [r1+2*r5]
lea r2, [r2+2*r5]
lea r3, [r3+2*r5]
lea r4, [r4+2*r5]
%endmacro
%macro SAD_X4_2x8P 1
%if %1
SAD_X4_START_1x8P
%else
SAD_X4_1x8P 0, 0
%endif
SAD_X4_1x8P FENC_STRIDE, r5
add r0, 2*FENC_STRIDE
lea r1, [r1+2*r5]
lea r2, [r2+2*r5]
lea r3, [r3+2*r5]
lea r4, [r4+2*r5]
%endmacro
%macro SAD_X4_2x4P 1
%if %1
SAD_X4_START_2x4P
%else
SAD_X4_INC_2x4P
%endif
add r0, 2*FENC_STRIDE
lea r1, [r1+2*r5]
lea r2, [r2+2*r5]
lea r3, [r3+2*r5]
lea r4, [r4+2*r5]
%endmacro
%macro SAD_X3_END 0
%if UNIX64
movd [r5+0], mm0
movd [r5+4], mm1
movd [r5+8], mm2
%else
mov r0, r5mp
movd [r0+0], mm0
movd [r0+4], mm1
movd [r0+8], mm2
%endif
RET
%endmacro
%macro SAD_X4_END 0
mov r0, r6mp
movd [r0+0], mm0
movd [r0+4], mm1
movd [r0+8], mm2
movd [r0+12], mm3
RET
%endmacro
;-----------------------------------------------------------------------------
; void pixel_sad_x3_16x16( uint8_t *fenc, uint8_t *pix0, uint8_t *pix1,
; uint8_t *pix2, intptr_t i_stride, int scores[3] )
;-----------------------------------------------------------------------------
%macro SAD_X 3
cglobal pixel_sad_x%1_%2x%3_mmx2, %1+2, %1+2
SAD_X%1_2x%2P 1
%rep %3/2-1
SAD_X%1_2x%2P 0
%endrep
SAD_X%1_END
%endmacro
INIT_MMX
SAD_X 3, 16, 16
SAD_X 3, 16, 8
SAD_X 3, 8, 16
SAD_X 3, 8, 8
SAD_X 3, 8, 4
SAD_X 3, 4, 8
SAD_X 3, 4, 4
SAD_X 4, 16, 16
SAD_X 4, 16, 8
SAD_X 4, 8, 16
SAD_X 4, 8, 8
SAD_X 4, 8, 4
SAD_X 4, 4, 8
SAD_X 4, 4, 4
;=============================================================================
; SAD x3/x4 XMM
;=============================================================================
%macro SAD_X3_START_1x16P_SSE2 0
mova m2, [r0]
%if cpuflag(avx)
psadbw m0, m2, [r1]
psadbw m1, m2, [r2]
psadbw m2, [r3]
%else
movu m0, [r1]
movu m1, [r2]
movu m3, [r3]
psadbw m0, m2
psadbw m1, m2
psadbw m2, m3
%endif
%endmacro
%macro SAD_X3_1x16P_SSE2 2
mova m3, [r0+%1]
%if cpuflag(avx)
psadbw m4, m3, [r1+%2]
psadbw m5, m3, [r2+%2]
psadbw m3, [r3+%2]
%else
movu m4, [r1+%2]
movu m5, [r2+%2]
movu m6, [r3+%2]
psadbw m4, m3
psadbw m5, m3
psadbw m3, m6
%endif
paddw m0, m4
paddw m1, m5
paddw m2, m3
%endmacro
%if ARCH_X86_64
DECLARE_REG_TMP 6
%else
DECLARE_REG_TMP 5
%endif
%macro SAD_X3_4x16P_SSE2 2
%if %1==0
lea t0, [r4*3]
SAD_X3_START_1x16P_SSE2
%else
SAD_X3_1x16P_SSE2 FENC_STRIDE*(0+(%1&1)*4), r4*0
%endif
SAD_X3_1x16P_SSE2 FENC_STRIDE*(1+(%1&1)*4), r4*1
SAD_X3_1x16P_SSE2 FENC_STRIDE*(2+(%1&1)*4), r4*2
SAD_X3_1x16P_SSE2 FENC_STRIDE*(3+(%1&1)*4), t0
%if %1 != %2-1
%if (%1&1) != 0
add r0, 8*FENC_STRIDE
%endif
lea r1, [r1+4*r4]
lea r2, [r2+4*r4]
lea r3, [r3+4*r4]
%endif
%endmacro
%macro SAD_X3_START_2x8P_SSE2 0
movq m3, [r0]
movq m0, [r1]
movq m1, [r2]
movq m2, [r3]
movhps m3, [r0+FENC_STRIDE]
movhps m0, [r1+r4]
movhps m1, [r2+r4]
movhps m2, [r3+r4]
psadbw m0, m3
psadbw m1, m3
psadbw m2, m3
%endmacro
%macro SAD_X3_2x8P_SSE2 4
movq m6, [r0+%1]
movq m3, [r1+%2]
movq m4, [r2+%2]
movq m5, [r3+%2]
movhps m6, [r0+%3]
movhps m3, [r1+%4]
movhps m4, [r2+%4]
movhps m5, [r3+%4]
psadbw m3, m6
psadbw m4, m6
psadbw m5, m6
paddw m0, m3
paddw m1, m4
paddw m2, m5
%endmacro
%macro SAD_X4_START_2x8P_SSE2 0
movq m4, [r0]
movq m0, [r1]
movq m1, [r2]
movq m2, [r3]
movq m3, [r4]
movhps m4, [r0+FENC_STRIDE]
movhps m0, [r1+r5]
movhps m1, [r2+r5]
movhps m2, [r3+r5]
movhps m3, [r4+r5]
psadbw m0, m4
psadbw m1, m4
psadbw m2, m4
psadbw m3, m4
%endmacro
%macro SAD_X4_2x8P_SSE2 4
movq m6, [r0+%1]
movq m4, [r1+%2]
movq m5, [r2+%2]
movhps m6, [r0+%3]
movhps m4, [r1+%4]
movhps m5, [r2+%4]
psadbw m4, m6
psadbw m5, m6
paddw m0, m4
paddw m1, m5
movq m4, [r3+%2]
movq m5, [r4+%2]
movhps m4, [r3+%4]
movhps m5, [r4+%4]
psadbw m4, m6
psadbw m5, m6
paddw m2, m4
paddw m3, m5
%endmacro
%macro SAD_X4_START_1x16P_SSE2 0
mova m3, [r0]
%if cpuflag(avx)
psadbw m0, m3, [r1]
psadbw m1, m3, [r2]
psadbw m2, m3, [r3]
psadbw m3, [r4]
%else
movu m0, [r1]
movu m1, [r2]
movu m2, [r3]
movu m4, [r4]
psadbw m0, m3
psadbw m1, m3
psadbw m2, m3
psadbw m3, m4
%endif
%endmacro
%macro SAD_X4_1x16P_SSE2 2
mova m6, [r0+%1]
%if cpuflag(avx)
psadbw m4, m6, [r1+%2]
psadbw m5, m6, [r2+%2]
%else
movu m4, [r1+%2]
movu m5, [r2+%2]
psadbw m4, m6
psadbw m5, m6
%endif
paddw m0, m4
paddw m1, m5
%if cpuflag(avx)
psadbw m4, m6, [r3+%2]
psadbw m5, m6, [r4+%2]
%else
movu m4, [r3+%2]
movu m5, [r4+%2]
psadbw m4, m6
psadbw m5, m6
%endif
paddw m2, m4
paddw m3, m5
%endmacro
%macro SAD_X4_4x16P_SSE2 2
%if %1==0
lea r6, [r5*3]
SAD_X4_START_1x16P_SSE2
%else
SAD_X4_1x16P_SSE2 FENC_STRIDE*(0+(%1&1)*4), r5*0
%endif
SAD_X4_1x16P_SSE2 FENC_STRIDE*(1+(%1&1)*4), r5*1
SAD_X4_1x16P_SSE2 FENC_STRIDE*(2+(%1&1)*4), r5*2
SAD_X4_1x16P_SSE2 FENC_STRIDE*(3+(%1&1)*4), r6
%if %1 != %2-1
%if (%1&1) != 0
add r0, 8*FENC_STRIDE
%endif
lea r1, [r1+4*r5]
lea r2, [r2+4*r5]
lea r3, [r3+4*r5]
lea r4, [r4+4*r5]
%endif
%endmacro
%macro SAD_X3_4x8P_SSE2 2
%if %1==0
lea t0, [r4*3]
SAD_X3_START_2x8P_SSE2
%else
SAD_X3_2x8P_SSE2 FENC_STRIDE*(0+(%1&1)*4), r4*0, FENC_STRIDE*(1+(%1&1)*4), r4*1
%endif
SAD_X3_2x8P_SSE2 FENC_STRIDE*(2+(%1&1)*4), r4*2, FENC_STRIDE*(3+(%1&1)*4), t0
%if %1 != %2-1
%if (%1&1) != 0
add r0, 8*FENC_STRIDE
%endif
lea r1, [r1+4*r4]
lea r2, [r2+4*r4]
lea r3, [r3+4*r4]
%endif
%endmacro
%macro SAD_X4_4x8P_SSE2 2
%if %1==0
lea r6, [r5*3]
SAD_X4_START_2x8P_SSE2
%else
SAD_X4_2x8P_SSE2 FENC_STRIDE*(0+(%1&1)*4), r5*0, FENC_STRIDE*(1+(%1&1)*4), r5*1
%endif
SAD_X4_2x8P_SSE2 FENC_STRIDE*(2+(%1&1)*4), r5*2, FENC_STRIDE*(3+(%1&1)*4), r6
%if %1 != %2-1
%if (%1&1) != 0
add r0, 8*FENC_STRIDE
%endif
lea r1, [r1+4*r5]
lea r2, [r2+4*r5]
lea r3, [r3+4*r5]
lea r4, [r4+4*r5]
%endif
%endmacro
%macro SAD_X3_END_SSE2 0
movifnidn r5, r5mp
%if cpuflag(ssse3)
packssdw m0, m1
packssdw m2, m2
phaddd m0, m2
mova [r5], m0
%else
movhlps m3, m0
movhlps m4, m1
movhlps m5, m2
paddw m0, m3
paddw m1, m4
paddw m2, m5
movd [r5+0], m0
movd [r5+4], m1
movd [r5+8], m2
%endif
RET
%endmacro
%macro SAD_X4_END_SSE2 0
mov r0, r6mp
%if cpuflag(ssse3)
packssdw m0, m1
packssdw m2, m3
phaddd m0, m2
mova [r0], m0
%else
psllq m1, 32
psllq m3, 32
paddw m0, m1
paddw m2, m3
movhlps m1, m0
movhlps m3, m2
paddw m0, m1
paddw m2, m3
movq [r0+0], m0
movq [r0+8], m2
%endif
RET
%endmacro
%macro SAD_X4_START_2x8P_SSSE3 0
movddup m4, [r0]
movq m0, [r1]
movq m1, [r3]
movhps m0, [r2]
movhps m1, [r4]
movddup m5, [r0+FENC_STRIDE]
movq m2, [r1+r5]
movq m3, [r3+r5]
movhps m2, [r2+r5]
movhps m3, [r4+r5]
psadbw m0, m4
psadbw m1, m4
psadbw m2, m5
psadbw m3, m5
paddw m0, m2
paddw m1, m3
%endmacro
%macro SAD_X4_2x8P_SSSE3 4
movddup m6, [r0+%1]
movq m2, [r1+%2]
movq m3, [r3+%2]
movhps m2, [r2+%2]
movhps m3, [r4+%2]
movddup m7, [r0+%3]
movq m4, [r1+%4]
movq m5, [r3+%4]
movhps m4, [r2+%4]
movhps m5, [r4+%4]
psadbw m2, m6
psadbw m3, m6
psadbw m4, m7
psadbw m5, m7
paddw m0, m2
paddw m1, m3
paddw m0, m4
paddw m1, m5
%endmacro
%macro SAD_X4_4x8P_SSSE3 2
%if %1==0
lea r6, [r5*3]
SAD_X4_START_2x8P_SSSE3
%else
SAD_X4_2x8P_SSSE3 FENC_STRIDE*(0+(%1&1)*4), r5*0, FENC_STRIDE*(1+(%1&1)*4), r5*1
%endif
SAD_X4_2x8P_SSSE3 FENC_STRIDE*(2+(%1&1)*4), r5*2, FENC_STRIDE*(3+(%1&1)*4), r6
%if %1 != %2-1
%if (%1&1) != 0
add r0, 8*FENC_STRIDE
%endif
lea r1, [r1+4*r5]
lea r2, [r2+4*r5]
lea r3, [r3+4*r5]
lea r4, [r4+4*r5]
%endif
%endmacro
%macro SAD_X4_END_SSSE3 0
mov r0, r6mp
packssdw m0, m1
mova [r0], m0
RET
%endmacro
%macro SAD_X3_START_2x16P_AVX2 0
movu m3, [r0] ; assumes FENC_STRIDE == 16
movu xm0, [r1]
movu xm1, [r2]
movu xm2, [r3]
vinserti128 m0, m0, [r1+r4], 1
vinserti128 m1, m1, [r2+r4], 1
vinserti128 m2, m2, [r3+r4], 1
psadbw m0, m3
psadbw m1, m3
psadbw m2, m3
%endmacro
%macro SAD_X3_2x16P_AVX2 3
movu m3, [r0+%1] ; assumes FENC_STRIDE == 16
movu xm4, [r1+%2]
movu xm5, [r2+%2]
movu xm6, [r3+%2]
vinserti128 m4, m4, [r1+%3], 1
vinserti128 m5, m5, [r2+%3], 1
vinserti128 m6, m6, [r3+%3], 1
psadbw m4, m3
psadbw m5, m3
psadbw m6, m3
paddw m0, m4
paddw m1, m5
paddw m2, m6
%endmacro
%macro SAD_X3_4x16P_AVX2 2
%if %1==0
lea t0, [r4*3]
SAD_X3_START_2x16P_AVX2
%else
SAD_X3_2x16P_AVX2 FENC_STRIDE*(0+(%1&1)*4), r4*0, r4*1
%endif
SAD_X3_2x16P_AVX2 FENC_STRIDE*(2+(%1&1)*4), r4*2, t0
%if %1 != %2-1
%if (%1&1) != 0
add r0, 8*FENC_STRIDE
%endif
lea r1, [r1+4*r4]
lea r2, [r2+4*r4]
lea r3, [r3+4*r4]
%endif
%endmacro
%macro SAD_X4_START_2x16P_AVX2 0
vbroadcasti128 m4, [r0]
vbroadcasti128 m5, [r0+FENC_STRIDE]
movu xm0, [r1]
movu xm1, [r2]
movu xm2, [r1+r5]
movu xm3, [r2+r5]
vinserti128 m0, m0, [r3], 1
vinserti128 m1, m1, [r4], 1
vinserti128 m2, m2, [r3+r5], 1
vinserti128 m3, m3, [r4+r5], 1
psadbw m0, m4
psadbw m1, m4
psadbw m2, m5
psadbw m3, m5
paddw m0, m2
paddw m1, m3
%endmacro
%macro SAD_X4_2x16P_AVX2 4
vbroadcasti128 m6, [r0+%1]
vbroadcasti128 m7, [r0+%3]
movu xm2, [r1+%2]
movu xm3, [r2+%2]
movu xm4, [r1+%4]
movu xm5, [r2+%4]
vinserti128 m2, m2, [r3+%2], 1
vinserti128 m3, m3, [r4+%2], 1
vinserti128 m4, m4, [r3+%4], 1
vinserti128 m5, m5, [r4+%4], 1
psadbw m2, m6
psadbw m3, m6
psadbw m4, m7
psadbw m5, m7
paddw m0, m2
paddw m1, m3
paddw m0, m4
paddw m1, m5
%endmacro
%macro SAD_X4_4x16P_AVX2 2
%if %1==0
lea r6, [r5*3]
SAD_X4_START_2x16P_AVX2
%else
SAD_X4_2x16P_AVX2 FENC_STRIDE*(0+(%1&1)*4), r5*0, FENC_STRIDE*(1+(%1&1)*4), r5*1
%endif
SAD_X4_2x16P_AVX2 FENC_STRIDE*(2+(%1&1)*4), r5*2, FENC_STRIDE*(3+(%1&1)*4), r6
%if %1 != %2-1
%if (%1&1) != 0
add r0, 8*FENC_STRIDE
%endif
lea r1, [r1+4*r5]
lea r2, [r2+4*r5]
lea r3, [r3+4*r5]
lea r4, [r4+4*r5]
%endif
%endmacro
%macro SAD_X3_END_AVX2 0
movifnidn r5, r5mp
packssdw m0, m1 ; 0 0 1 1 0 0 1 1
packssdw m2, m2 ; 2 2 _ _ 2 2 _ _
phaddd m0, m2 ; 0 1 2 _ 0 1 2 _
vextracti128 xm1, m0, 1
paddd xm0, xm1 ; 0 1 2 _
mova [r5], xm0
RET
%endmacro
%macro SAD_X4_END_AVX2 0
mov r0, r6mp
packssdw m0, m1 ; 0 0 1 1 2 2 3 3
vextracti128 xm1, m0, 1
phaddd xm0, xm1 ; 0 1 2 3
mova [r0], xm0
RET
%endmacro
;-----------------------------------------------------------------------------
; void pixel_sad_x3_16x16( uint8_t *fenc, uint8_t *pix0, uint8_t *pix1,
; uint8_t *pix2, intptr_t i_stride, int scores[3] )
;-----------------------------------------------------------------------------
%macro SAD_X_SSE2 4
cglobal pixel_sad_x%1_%2x%3, 2+%1,3+%1,%4
%assign x 0
%rep %3/4
SAD_X%1_4x%2P_SSE2 x, %3/4
%assign x x+1
%endrep
SAD_X%1_END_SSE2
%endmacro
INIT_XMM sse2
SAD_X_SSE2 3, 16, 16, 7
SAD_X_SSE2 3, 16, 8, 7
SAD_X_SSE2 3, 8, 16, 7
SAD_X_SSE2 3, 8, 8, 7
SAD_X_SSE2 3, 8, 4, 7
SAD_X_SSE2 4, 16, 16, 7
SAD_X_SSE2 4, 16, 8, 7
SAD_X_SSE2 4, 8, 16, 7
SAD_X_SSE2 4, 8, 8, 7
SAD_X_SSE2 4, 8, 4, 7
INIT_XMM sse3
SAD_X_SSE2 3, 16, 16, 7
SAD_X_SSE2 3, 16, 8, 7
SAD_X_SSE2 4, 16, 16, 7
SAD_X_SSE2 4, 16, 8, 7
%macro SAD_X_SSSE3 3
cglobal pixel_sad_x%1_%2x%3, 2+%1,3+%1,8
%assign x 0
%rep %3/4
SAD_X%1_4x%2P_SSSE3 x, %3/4
%assign x x+1
%endrep
SAD_X%1_END_SSSE3
%endmacro
INIT_XMM ssse3
SAD_X_SSE2 3, 16, 16, 7
SAD_X_SSE2 3, 16, 8, 7
SAD_X_SSE2 4, 16, 16, 7
SAD_X_SSE2 4, 16, 8, 7
SAD_X_SSSE3 4, 8, 16
SAD_X_SSSE3 4, 8, 8
SAD_X_SSSE3 4, 8, 4
INIT_XMM avx
SAD_X_SSE2 3, 16, 16, 6
SAD_X_SSE2 3, 16, 8, 6
SAD_X_SSE2 4, 16, 16, 7
SAD_X_SSE2 4, 16, 8, 7
%macro SAD_X_AVX2 4
cglobal pixel_sad_x%1_%2x%3, 2+%1,3+%1,%4
%assign x 0
%rep %3/4
SAD_X%1_4x%2P_AVX2 x, %3/4
%assign x x+1
%endrep
SAD_X%1_END_AVX2
%endmacro
INIT_YMM avx2
SAD_X_AVX2 3, 16, 16, 7
SAD_X_AVX2 3, 16, 8, 7
SAD_X_AVX2 4, 16, 16, 8
SAD_X_AVX2 4, 16, 8, 8
%macro SAD_X_W4_AVX512 2 ; x, h
cglobal pixel_sad_x%1_4x%2, %1+2,%1+3
mov t1d, 0xa
kmovb k1, t1d
lea t1, [3*t0]
kaddb k2, k1, k1
kshiftlb k3, k1, 2
%assign %%i 0
%rep %2/4
movu m6, [r0+%%i*64]
vmovddup m6 {k1}, [r0+%%i*64+32]
movd xmm2, [r1]
movd xmm4, [r1+t0]
vpbroadcastd xmm2 {k1}, [r1+2*t0]
vpbroadcastd xmm4 {k1}, [r1+t1]
vpbroadcastd xmm2 {k2}, [r2+t0]
vpbroadcastd xmm4 {k2}, [r2]
vpbroadcastd xmm2 {k3}, [r2+t1] ; a0 a2 b1 b3
vpbroadcastd xmm4 {k3}, [r2+2*t0] ; a1 a3 b0 b2
vpmovqd s1, m6 ; s0 s2 s1 s3
movd xmm3, [r3]
movd xmm5, [r3+t0]
vpbroadcastd xmm3 {k1}, [r3+2*t0]
vpbroadcastd xmm5 {k1}, [r3+t1]
%if %1 == 4
vpbroadcastd xmm3 {k2}, [r4+t0]
vpbroadcastd xmm5 {k2}, [r4]
vpbroadcastd xmm3 {k3}, [r4+t1] ; c0 c2 d1 d3
vpbroadcastd xmm5 {k3}, [r4+2*t0] ; c1 c3 d0 d2
%endif
%if %%i != %2/4-1
%assign %%j 1
%rep %1
lea r%+%%j, [r%+%%j+4*t0]
%assign %%j %%j+1
%endrep
%endif
pshufd s2, s1, q1032
psadbw xmm2, s1
psadbw xmm4, s2
psadbw xmm3, s1
psadbw xmm5, s2
%if %%i
paddd xmm0, xmm2
paddd xmm1, xmm3
paddd xmm0, xmm4
paddd xmm1, xmm5
%else
paddd xmm0, xmm2, xmm4
paddd xmm1, xmm3, xmm5
%endif
%assign %%i %%i+1
%endrep
%if %1 == 4
movifnidn t2, r6mp
%else
movifnidn t2, r5mp
%endif
packusdw xmm0, xmm1
mova [t2], xmm0
RET
%endmacro
%macro SAD_X_W8_AVX512 2 ; x, h
cglobal pixel_sad_x%1_8x%2, %1+2,%1+3
kxnorb k3, k3, k3
lea t1, [3*t0]
kaddb k1, k3, k3
kshiftlb k2, k3, 2
kshiftlb k3, k3, 3
%assign %%i 0
%rep %2/4
movddup m6, [r0+%%i*64] ; s0 s0 s1 s1
movq xm2, [r1]
movq xm4, [r1+2*t0]
vpbroadcastq xm2 {k1}, [r2]
vpbroadcastq xm4 {k1}, [r2+2*t0]
vpbroadcastq m2 {k2}, [r1+t0]
vpbroadcastq m4 {k2}, [r1+t1]
vpbroadcastq m2 {k3}, [r2+t0] ; a0 b0 a1 b1
vpbroadcastq m4 {k3}, [r2+t1] ; a2 b2 a3 b3
movddup m7, [r0+%%i*64+32] ; s2 s2 s3 s3
movq xm3, [r3]
movq xm5, [r3+2*t0]
%if %1 == 4
vpbroadcastq xm3 {k1}, [r4]
vpbroadcastq xm5 {k1}, [r4+2*t0]
%endif
vpbroadcastq m3 {k2}, [r3+t0]
vpbroadcastq m5 {k2}, [r3+t1]
%if %1 == 4
vpbroadcastq m3 {k3}, [r4+t0] ; c0 d0 c1 d1
vpbroadcastq m5 {k3}, [r4+t1] ; c2 d2 c3 d3
%endif
%if %%i != %2/4-1
%assign %%j 1
%rep %1
lea r%+%%j, [r%+%%j+4*t0]
%assign %%j %%j+1
%endrep
%endif
psadbw m2, m6
psadbw m4, m7
psadbw m3, m6
psadbw m5, m7
ACCUM paddd, 0, 2, %%i
ACCUM paddd, 1, 3, %%i
paddd m0, m4
paddd m1, m5
%assign %%i %%i+1
%endrep
%if %1 == 4
movifnidn t2, r6mp
%else
movifnidn t2, r5mp
%endif
packusdw m0, m1
vextracti128 xm1, m0, 1
paddd xm0, xm1
mova [t2], xm0
RET
%endmacro
%macro SAD_X_W16_AVX512 2 ; x, h
cglobal pixel_sad_x%1_16x%2, %1+2,%1+3
lea t1, [3*t0]
%assign %%i 0
%rep %2/4
mova m6, [r0+%%i*64] ; s0 s1 s2 s3
movu xm2, [r3]
movu xm4, [r3+t0]
%if %1 == 4
vinserti128 ym2, [r4+t0], 1
vinserti128 ym4, [r4], 1
%endif
vinserti32x4 m2, [r1+2*t0], 2
vinserti32x4 m4, [r1+t1], 2
vinserti32x4 m2, [r2+t1], 3 ; c0 d1 a2 b3
vinserti32x4 m4, [r2+2*t0], 3 ; c1 d0 a3 b2
vpermq m7, m6, q1032 ; s1 s0 s3 s2
movu xm3, [r1]
movu xm5, [r1+t0]
vinserti128 ym3, [r2+t0], 1
vinserti128 ym5, [r2], 1
vinserti32x4 m3, [r3+2*t0], 2
vinserti32x4 m5, [r3+t1], 2
%if %1 == 4
vinserti32x4 m3, [r4+t1], 3 ; a0 b1 c2 d3
vinserti32x4 m5, [r4+2*t0], 3 ; a1 b0 c3 d2
%endif
%if %%i != %2/4-1
%assign %%j 1
%rep %1
lea r%+%%j, [r%+%%j+4*t0]
%assign %%j %%j+1
%endrep
%endif
psadbw m2, m6
psadbw m4, m7
psadbw m3, m6
psadbw m5, m7
ACCUM paddd, 0, 2, %%i
ACCUM paddd, 1, 3, %%i
paddd m0, m4
paddd m1, m5
%assign %%i %%i+1
%endrep
%if %1 == 4
movifnidn t2, r6mp
%else
movifnidn t2, r5mp
%endif
mov t1d, 0x1111
kmovw k1, t1d
vshufi32x4 m0, m0, q1032
paddd m0, m1
punpckhqdq m1, m0, m0
paddd m0, m1
vpcompressd m0 {k1}{z}, m0
mova [t2], xm0
RET
%endmacro
; t0 = stride, t1 = tmp/stride3, t2 = scores
%if WIN64
%define s1 xmm16 ; xmm6 and xmm7 reduces code size, but
%define s2 xmm17 ; they're callee-saved on win64
DECLARE_REG_TMP 4, 6, 0
%else
%define s1 xmm6
%define s2 xmm7
%if ARCH_X86_64
DECLARE_REG_TMP 4, 6, 5 ; scores is passed in a register on unix64
%else
DECLARE_REG_TMP 4, 5, 0
%endif
%endif
INIT_YMM avx512
SAD_X_W4_AVX512 3, 4 ; x3_4x4
SAD_X_W4_AVX512 3, 8 ; x3_4x8
SAD_X_W8_AVX512 3, 4 ; x3_8x4
SAD_X_W8_AVX512 3, 8 ; x3_8x8
SAD_X_W8_AVX512 3, 16 ; x3_8x16
INIT_ZMM avx512
SAD_X_W16_AVX512 3, 8 ; x3_16x8
SAD_X_W16_AVX512 3, 16 ; x3_16x16
DECLARE_REG_TMP 5, 6, 0
INIT_YMM avx512
SAD_X_W4_AVX512 4, 4 ; x4_4x4
SAD_X_W4_AVX512 4, 8 ; x4_4x8
SAD_X_W8_AVX512 4, 4 ; x4_8x4
SAD_X_W8_AVX512 4, 8 ; x4_8x8
SAD_X_W8_AVX512 4, 16 ; x4_8x16
INIT_ZMM avx512
SAD_X_W16_AVX512 4, 8 ; x4_16x8
SAD_X_W16_AVX512 4, 16 ; x4_16x16
;=============================================================================
; SAD cacheline split
;=============================================================================
; Core2 (Conroe) can load unaligned data just as quickly as aligned data...
; unless the unaligned data spans the border between 2 cachelines, in which
; case it's really slow. The exact numbers may differ, but all Intel cpus prior
; to Nehalem have a large penalty for cacheline splits.
; (8-byte alignment exactly half way between two cachelines is ok though.)
; LDDQU was supposed to fix this, but it only works on Pentium 4.
; So in the split case we load aligned data and explicitly perform the
; alignment between registers. Like on archs that have only aligned loads,
; except complicated by the fact that PALIGNR takes only an immediate, not
; a variable alignment.
; It is also possible to hoist the realignment to the macroblock level (keep
; 2 copies of the reference frame, offset by 32 bytes), but the extra memory
; needed for that method makes it often slower.
; sad 16x16 costs on Core2:
; good offsets: 49 cycles (50/64 of all mvs)
; cacheline split: 234 cycles (14/64 of all mvs. ammortized: +40 cycles)
; page split: 3600 cycles (14/4096 of all mvs. ammortized: +11.5 cycles)
; cache or page split with palignr: 57 cycles (ammortized: +2 cycles)
; computed jump assumes this loop is exactly 80 bytes
%macro SAD16_CACHELINE_LOOP_SSE2 1 ; alignment
ALIGN 16
sad_w16_align%1_sse2:
movdqa xmm1, [r2+16]
movdqa xmm2, [r2+r3+16]
movdqa xmm3, [r2]
movdqa xmm4, [r2+r3]
pslldq xmm1, 16-%1
pslldq xmm2, 16-%1
psrldq xmm3, %1
psrldq xmm4, %1
por xmm1, xmm3
por xmm2, xmm4
psadbw xmm1, [r0]
psadbw xmm2, [r0+r1]
paddw xmm0, xmm1
paddw xmm0, xmm2
lea r0, [r0+2*r1]
lea r2, [r2+2*r3]
dec r4
jg sad_w16_align%1_sse2
ret
%endmacro
; computed jump assumes this loop is exactly 64 bytes
%macro SAD16_CACHELINE_LOOP_SSSE3 1 ; alignment
ALIGN 16
sad_w16_align%1_ssse3:
movdqa xmm1, [r2+16]
movdqa xmm2, [r2+r3+16]
palignr xmm1, [r2], %1
palignr xmm2, [r2+r3], %1
psadbw xmm1, [r0]
psadbw xmm2, [r0+r1]
paddw xmm0, xmm1
paddw xmm0, xmm2
lea r0, [r0+2*r1]
lea r2, [r2+2*r3]
dec r4
jg sad_w16_align%1_ssse3
ret
%endmacro
%macro SAD16_CACHELINE_FUNC 2 ; cpu, height
cglobal pixel_sad_16x%2_cache64_%1
mov eax, r2m
and eax, 0x37
cmp eax, 0x30
jle pixel_sad_16x%2_sse2
PROLOGUE 4,6
mov r4d, r2d
and r4d, 15
%ifidn %1, ssse3
shl r4d, 6 ; code size = 64
%else
lea r4, [r4*5]
shl r4d, 4 ; code size = 80
%endif
%define sad_w16_addr (sad_w16_align1_%1 + (sad_w16_align1_%1 - sad_w16_align2_%1))
%ifdef PIC
lea r5, [sad_w16_addr]
add r5, r4
%else
lea r5, [sad_w16_addr + r4]
%endif
and r2, ~15
mov r4d, %2/2
pxor xmm0, xmm0
call r5
MOVHL xmm1, xmm0
paddw xmm0, xmm1
movd eax, xmm0
RET
%endmacro
%macro SAD_CACHELINE_START_MMX2 4 ; width, height, iterations, cacheline
mov eax, r2m
and eax, 0x17|%1|(%4>>1)
cmp eax, 0x10|%1|(%4>>1)
jle pixel_sad_%1x%2_mmx2
and eax, 7
shl eax, 3
movd mm6, [sw_64]
movd mm7, eax
psubw mm6, mm7
PROLOGUE 4,5
and r2, ~7
mov r4d, %3
pxor mm0, mm0
%endmacro
%macro SAD16_CACHELINE_FUNC_MMX2 2 ; height, cacheline
cglobal pixel_sad_16x%1_cache%2_mmx2
SAD_CACHELINE_START_MMX2 16, %1, %1, %2
.loop:
movq mm1, [r2]
movq mm2, [r2+8]
movq mm3, [r2+16]
movq mm4, mm2
psrlq mm1, mm7
psllq mm2, mm6
psllq mm3, mm6
psrlq mm4, mm7
por mm1, mm2
por mm3, mm4
psadbw mm1, [r0]
psadbw mm3, [r0+8]
paddw mm0, mm1
paddw mm0, mm3
add r2, r3
add r0, r1
dec r4
jg .loop
movd eax, mm0
RET
%endmacro
%macro SAD8_CACHELINE_FUNC_MMX2 2 ; height, cacheline
cglobal pixel_sad_8x%1_cache%2_mmx2
SAD_CACHELINE_START_MMX2 8, %1, %1/2, %2
.loop:
movq mm1, [r2+8]
movq mm2, [r2+r3+8]
movq mm3, [r2]
movq mm4, [r2+r3]
psllq mm1, mm6
psllq mm2, mm6
psrlq mm3, mm7
psrlq mm4, mm7
por mm1, mm3
por mm2, mm4
psadbw mm1, [r0]
psadbw mm2, [r0+r1]
paddw mm0, mm1
paddw mm0, mm2
lea r2, [r2+2*r3]
lea r0, [r0+2*r1]
dec r4
jg .loop
movd eax, mm0
RET
%endmacro
; sad_x3/x4_cache64: check each mv.
; if they're all within a cacheline, use normal sad_x3/x4.
; otherwise, send them individually to sad_cache64.
%macro CHECK_SPLIT 3 ; pix, width, cacheline
mov eax, %1
and eax, 0x17|%2|(%3>>1)
cmp eax, 0x10|%2|(%3>>1)
jg .split
%endmacro
%macro SADX3_CACHELINE_FUNC 6 ; width, height, cacheline, normal_ver, split_ver, name
cglobal pixel_sad_x3_%1x%2_cache%3_%6
CHECK_SPLIT r1m, %1, %3
CHECK_SPLIT r2m, %1, %3
CHECK_SPLIT r3m, %1, %3
jmp pixel_sad_x3_%1x%2_%4
.split:
%if ARCH_X86_64
PROLOGUE 6,9
push r3
push r2
%if WIN64
movsxd r4, r4d
sub rsp, 40 ; shadow space and alignment
%endif
mov r2, r1
mov r1, FENC_STRIDE
mov r3, r4
mov r7, r0
mov r8, r5
call pixel_sad_%1x%2_cache%3_%5
mov [r8], eax
%if WIN64
mov r2, [rsp+40+0*8]
%else
pop r2
%endif
mov r0, r7
call pixel_sad_%1x%2_cache%3_%5
mov [r8+4], eax
%if WIN64
mov r2, [rsp+40+1*8]
%else
pop r2
%endif
mov r0, r7
call pixel_sad_%1x%2_cache%3_%5
mov [r8+8], eax
%if WIN64
add rsp, 40+2*8
%endif
RET
%else
push edi
mov edi, [esp+28]
push dword [esp+24]
push dword [esp+16]
push dword 16
push dword [esp+20]
call pixel_sad_%1x%2_cache%3_%5
mov ecx, [esp+32]
mov [edi], eax
mov [esp+8], ecx
call pixel_sad_%1x%2_cache%3_%5
mov ecx, [esp+36]
mov [edi+4], eax
mov [esp+8], ecx
call pixel_sad_%1x%2_cache%3_%5
mov [edi+8], eax
add esp, 16
pop edi
ret
%endif
%endmacro
%macro SADX4_CACHELINE_FUNC 6 ; width, height, cacheline, normal_ver, split_ver, name
cglobal pixel_sad_x4_%1x%2_cache%3_%6
CHECK_SPLIT r1m, %1, %3
CHECK_SPLIT r2m, %1, %3
CHECK_SPLIT r3m, %1, %3
CHECK_SPLIT r4m, %1, %3
jmp pixel_sad_x4_%1x%2_%4
.split:
%if ARCH_X86_64
PROLOGUE 6,9
mov r8, r6mp
push r4
push r3
push r2
%if WIN64
sub rsp, 32 ; shadow space
%endif
mov r2, r1
mov r1, FENC_STRIDE
mov r3, r5
mov r7, r0
call pixel_sad_%1x%2_cache%3_%5
mov [r8], eax
%if WIN64
mov r2, [rsp+32+0*8]
%else
pop r2
%endif
mov r0, r7
call pixel_sad_%1x%2_cache%3_%5
mov [r8+4], eax
%if WIN64
mov r2, [rsp+32+1*8]
%else
pop r2
%endif
mov r0, r7
call pixel_sad_%1x%2_cache%3_%5
mov [r8+8], eax
%if WIN64
mov r2, [rsp+32+2*8]
%else
pop r2
%endif
mov r0, r7
call pixel_sad_%1x%2_cache%3_%5
mov [r8+12], eax
%if WIN64
add rsp, 32+3*8
%endif
RET
%else
push edi
mov edi, [esp+32]
push dword [esp+28]
push dword [esp+16]
push dword 16
push dword [esp+20]
call pixel_sad_%1x%2_cache%3_%5
mov ecx, [esp+32]
mov [edi], eax
mov [esp+8], ecx
call pixel_sad_%1x%2_cache%3_%5
mov ecx, [esp+36]
mov [edi+4], eax
mov [esp+8], ecx
call pixel_sad_%1x%2_cache%3_%5
mov ecx, [esp+40]
mov [edi+8], eax
mov [esp+8], ecx
call pixel_sad_%1x%2_cache%3_%5
mov [edi+12], eax
add esp, 16
pop edi
ret
%endif
%endmacro
%macro SADX34_CACHELINE_FUNC 1+
SADX3_CACHELINE_FUNC %1
SADX4_CACHELINE_FUNC %1
%endmacro
; instantiate the aligned sads
INIT_MMX
%if ARCH_X86_64 == 0
SAD16_CACHELINE_FUNC_MMX2 8, 32
SAD16_CACHELINE_FUNC_MMX2 16, 32
SAD8_CACHELINE_FUNC_MMX2 4, 32
SAD8_CACHELINE_FUNC_MMX2 8, 32
SAD8_CACHELINE_FUNC_MMX2 16, 32
SAD16_CACHELINE_FUNC_MMX2 8, 64
SAD16_CACHELINE_FUNC_MMX2 16, 64
%endif ; !ARCH_X86_64
SAD8_CACHELINE_FUNC_MMX2 4, 64
SAD8_CACHELINE_FUNC_MMX2 8, 64
SAD8_CACHELINE_FUNC_MMX2 16, 64
%if ARCH_X86_64 == 0
SADX34_CACHELINE_FUNC 16, 16, 32, mmx2, mmx2, mmx2
SADX34_CACHELINE_FUNC 16, 8, 32, mmx2, mmx2, mmx2
SADX34_CACHELINE_FUNC 8, 16, 32, mmx2, mmx2, mmx2
SADX34_CACHELINE_FUNC 8, 8, 32, mmx2, mmx2, mmx2
SADX34_CACHELINE_FUNC 16, 16, 64, mmx2, mmx2, mmx2
SADX34_CACHELINE_FUNC 16, 8, 64, mmx2, mmx2, mmx2
%endif ; !ARCH_X86_64
SADX34_CACHELINE_FUNC 8, 16, 64, mmx2, mmx2, mmx2
SADX34_CACHELINE_FUNC 8, 8, 64, mmx2, mmx2, mmx2
%if ARCH_X86_64 == 0
SAD16_CACHELINE_FUNC sse2, 8
SAD16_CACHELINE_FUNC sse2, 16
%assign i 1
%rep 15
SAD16_CACHELINE_LOOP_SSE2 i
%assign i i+1
%endrep
SADX34_CACHELINE_FUNC 16, 16, 64, sse2, sse2, sse2
SADX34_CACHELINE_FUNC 16, 8, 64, sse2, sse2, sse2
%endif ; !ARCH_X86_64
SADX34_CACHELINE_FUNC 8, 16, 64, sse2, mmx2, sse2
SAD16_CACHELINE_FUNC ssse3, 8
SAD16_CACHELINE_FUNC ssse3, 16
%assign i 1
%rep 15
SAD16_CACHELINE_LOOP_SSSE3 i
%assign i i+1
%endrep
SADX34_CACHELINE_FUNC 16, 16, 64, sse2, ssse3, ssse3
SADX34_CACHELINE_FUNC 16, 8, 64, sse2, ssse3, ssse3
| 24.298285 | 91 | 0.532603 |
e2d8e0173164b98225122682593eb37f74a5ae51 | 887 | asm | Assembly | programs/oeis/109/A109437.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/109/A109437.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | programs/oeis/109/A109437.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | ; A109437: a(-1) = a(0) = 0, a(1) = 1; a(n) = 5a(n-1) - 5a(n-2) + a(n-3) + 2*(-1)^(n+1), alternatively a(n) = 3a(n-1) + 3a(n-2) - a(n-3).
; 0,1,3,12,44,165,615,2296,8568,31977,119339,445380,1662180,6203341,23151183,86401392,322454384,1203416145,4491210195,16761424636,62554488348,233456528757,871271626679,3251629977960,12135248285160
mov $14,1
lpb $14
mov $9,$0
mov $11,$0
add $11,1
sub $14,1
lpb $11
mov $0,$9
sub $11,1
sub $0,$11
mov $5,$0
mov $7,2
lpb $7
clr $0,5
mov $0,$5
sub $7,1
add $0,$7
sub $0,2
mov $1,1
lpb $0
sub $0,1
add $3,2
add $1,$3
add $3,$1
add $1,$3
add $1,2
lpe
div $3,3
add $3,1
mov $1,$3
mov $8,$7
lpb $8
mov $6,$1
sub $8,1
lpe
lpe
add $10,$6
lpe
lpe
mov $1,$10
sub $1,1
| 19.711111 | 196 | 0.482525 |
3ebb2001ed2677238583da2939a2ed5f68bf8c0d | 158,374 | asm | Assembly | adi_study_watch/nrf5_sdk_15.2.0/adi_study_watch/tst/lfs/ses/Output/ADI_project Release/Obj/fenda.asm | ArrowElectronics/Vital-Signs-Monitoring | ba43fe9a116d94170561433910fd7bffba5726e7 | [
"Unlicense"
] | 5 | 2021-06-13T17:11:19.000Z | 2021-12-01T18:20:38.000Z | adi_study_watch/nrf5_sdk_15.2.0/adi_study_watch/tst/lfs/ses/Output/ADI_project Release/Obj/fenda.asm | ArrowElectronics/Vital-Signs-Monitoring | ba43fe9a116d94170561433910fd7bffba5726e7 | [
"Unlicense"
] | null | null | null | adi_study_watch/nrf5_sdk_15.2.0/adi_study_watch/tst/lfs/ses/Output/ADI_project Release/Obj/fenda.asm | ArrowElectronics/Vital-Signs-Monitoring | ba43fe9a116d94170561433910fd7bffba5726e7 | [
"Unlicense"
] | 1 | 2022-01-08T15:01:44.000Z | 2022-01-08T15:01:44.000Z | .cpu cortex-m4
.eabi_attribute 27, 1
.eabi_attribute 28, 1
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 26, 1
.eabi_attribute 30, 4
.eabi_attribute 34, 1
.eabi_attribute 18, 4
.file "fenda.c"
.text
.Ltext0:
.global bmfenda
.section .rodata._Colorsfenda,"a",%progbits
.align 2
.type _Colorsfenda, %object
.size _Colorsfenda, 32
_Colorsfenda:
.word 0
.word 255
.word 65280
.word 65535
.word 16711680
.word 16711935
.word 16776960
.word 16777215
.section .rodata._Palfenda,"a",%progbits
.align 2
.type _Palfenda, %object
.size _Palfenda, 12
_Palfenda:
.word 8
.byte 0
.space 3
.word _Colorsfenda
.section .rodata._acfenda,"a",%progbits
.type _acfenda, %object
.size _acfenda, 5928
_acfenda:
.byte 119
.byte 119
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.section .rodata.bmfenda,"a",%progbits
.align 2
.type bmfenda, %object
.size bmfenda, 16
bmfenda:
.short 207
.short 57
.short 104
.short 4
.word _acfenda
.word _Palfenda
.text
.Letext0:
.file 1 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.12/include/__crossworks.h"
.file 2 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.12/include/stdint.h"
.file 3 "..\\..\\..\\..\\adi_study_watch\\tst\\display/GUI.h"
.file 4 "C:\\Work\\PortingtoSegger\\study_watch\\study_watch\\nrf5_sdk_15.2.0\\adi_study_watch\\tst\\display\\image\\fenda.c"
.section .debug_info,"",%progbits
.Ldebug_info0:
.4byte 0x874
.2byte 0x4
.4byte .Ldebug_abbrev0
.byte 0x4
.uleb128 0x1
.4byte .LASF926
.byte 0xc
.4byte .LASF927
.4byte .LASF928
.4byte .Ldebug_line0
.4byte .Ldebug_macro0
.uleb128 0x2
.4byte .LASF856
.byte 0x8
.byte 0x1
.byte 0x7e
.4byte 0x46
.uleb128 0x3
.4byte .LASF804
.byte 0x1
.byte 0x7f
.4byte 0x46
.byte 0
.uleb128 0x3
.4byte .LASF805
.byte 0x1
.byte 0x80
.4byte 0x4d
.byte 0x4
.byte 0
.uleb128 0x4
.byte 0x4
.byte 0x5
.ascii "int\000"
.uleb128 0x5
.byte 0x4
.byte 0x5
.4byte .LASF806
.uleb128 0x6
.4byte 0x46
.4byte 0x6d
.uleb128 0x7
.4byte 0x6d
.uleb128 0x7
.4byte 0x7f
.uleb128 0x7
.4byte 0x86
.byte 0
.uleb128 0x8
.byte 0x4
.4byte 0x73
.uleb128 0x5
.byte 0x1
.byte 0x8
.4byte .LASF807
.uleb128 0x9
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.byte 0x4
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.4byte 0xaa
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.byte 0x4
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.byte 0x1
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.2byte 0x254
.4byte 0x569
.byte 0x1
.uleb128 0x13
.4byte .LASF899
.byte 0x3
.2byte 0x255
.4byte 0x569
.byte 0x2
.uleb128 0x13
.4byte .LASF901
.byte 0x3
.2byte 0x256
.4byte 0x6b6
.byte 0x4
.byte 0
.uleb128 0x8
.byte 0x4
.4byte 0x256
.uleb128 0x11
.4byte .LASF905
.byte 0x3
.2byte 0x257
.4byte 0x678
.uleb128 0x9
.4byte 0x6bc
.uleb128 0x12
.4byte .LASF906
.byte 0xc
.byte 0x3
.2byte 0x259
.4byte 0x70f
.uleb128 0x13
.4byte .LASF907
.byte 0x3
.2byte 0x25a
.4byte 0x580
.byte 0
.uleb128 0x13
.4byte .LASF908
.byte 0x3
.2byte 0x25b
.4byte 0x580
.byte 0x2
.uleb128 0x13
.4byte .LASF909
.byte 0x3
.2byte 0x25c
.4byte 0x714
.byte 0x4
.uleb128 0x13
.4byte .LASF910
.byte 0x3
.2byte 0x25d
.4byte 0x71a
.byte 0x8
.byte 0
.uleb128 0x9
.4byte 0x6cd
.uleb128 0x8
.byte 0x4
.4byte 0x6c8
.uleb128 0x8
.byte 0x4
.4byte 0x70f
.uleb128 0x11
.4byte .LASF906
.byte 0x3
.2byte 0x25e
.4byte 0x6cd
.uleb128 0x9
.4byte 0x720
.uleb128 0x15
.byte 0x4
.byte 0x3
.2byte 0x266
.4byte 0x747
.uleb128 0x16
.4byte .LASF930
.byte 0x3
.2byte 0x269
.4byte 0x747
.byte 0
.uleb128 0x8
.byte 0x4
.4byte 0x72c
.uleb128 0x12
.4byte .LASF911
.byte 0xc
.byte 0x3
.2byte 0x260
.4byte 0x7c1
.uleb128 0x13
.4byte .LASF898
.byte 0x3
.2byte 0x262
.4byte 0x569
.byte 0
.uleb128 0x13
.4byte .LASF912
.byte 0x3
.2byte 0x263
.4byte 0x569
.byte 0x1
.uleb128 0x13
.4byte .LASF913
.byte 0x3
.2byte 0x264
.4byte 0x569
.byte 0x2
.uleb128 0x13
.4byte .LASF914
.byte 0x3
.2byte 0x265
.4byte 0x569
.byte 0x3
.uleb128 0x17
.ascii "p\000"
.byte 0x3
.2byte 0x26b
.4byte 0x731
.byte 0x4
.uleb128 0x13
.4byte .LASF915
.byte 0x3
.2byte 0x26c
.4byte 0x569
.byte 0x8
.uleb128 0x13
.4byte .LASF916
.byte 0x3
.2byte 0x26d
.4byte 0x569
.byte 0x9
.uleb128 0x13
.4byte .LASF917
.byte 0x3
.2byte 0x26e
.4byte 0x569
.byte 0xa
.byte 0
.uleb128 0x11
.4byte .LASF911
.byte 0x3
.2byte 0x26f
.4byte 0x74d
.uleb128 0x9
.4byte 0x7c1
.uleb128 0xe
.4byte .LASF918
.byte 0x3
.2byte 0x271
.4byte 0x7cd
.uleb128 0xe
.4byte .LASF919
.byte 0x3
.2byte 0x272
.4byte 0x7cd
.uleb128 0xe
.4byte .LASF920
.byte 0x3
.2byte 0x273
.4byte 0x7cd
.uleb128 0xe
.4byte .LASF921
.byte 0x3
.2byte 0x274
.4byte 0x7cd
.uleb128 0x18
.4byte .LASF922
.byte 0x4
.byte 0x1f
.4byte 0x673
.uleb128 0xc
.4byte 0x5b8
.4byte 0x81d
.uleb128 0xd
.4byte 0x7f
.byte 0x7
.byte 0
.uleb128 0x9
.4byte 0x80d
.uleb128 0x19
.4byte .LASF923
.byte 0x4
.byte 0x2e
.4byte 0x81d
.uleb128 0x5
.byte 0x3
.4byte _Colorsfenda
.uleb128 0x19
.4byte .LASF924
.byte 0x4
.byte 0x33
.4byte 0x606
.uleb128 0x5
.byte 0x3
.4byte _Palfenda
.uleb128 0xc
.4byte 0x256
.4byte 0x855
.uleb128 0x1a
.4byte 0x7f
.2byte 0x1727
.byte 0
.uleb128 0x9
.4byte 0x844
.uleb128 0x19
.4byte .LASF925
.byte 0x4
.byte 0x39
.4byte 0x855
.uleb128 0x5
.byte 0x3
.4byte _acfenda
.uleb128 0x1b
.4byte 0x802
.byte 0xe7
.uleb128 0x5
.byte 0x3
.4byte bmfenda
.byte 0
.section .debug_abbrev,"",%progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0xe
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0xe
.uleb128 0x1b
.uleb128 0xe
.uleb128 0x10
.uleb128 0x17
.uleb128 0x2119
.uleb128 0x17
.uleb128 0x2134
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x13
.byte 0x1
.uleb128 0x3
.uleb128 0xe
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x38
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0xe
.byte 0
.byte 0
.uleb128 0x6
.uleb128 0x15
.byte 0x1
.uleb128 0x27
.uleb128 0x19
.uleb128 0x49
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x7
.uleb128 0x5
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x8
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x9
.uleb128 0x26
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xa
.uleb128 0x13
.byte 0x1
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xb
.uleb128 0x16
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xc
.uleb128 0x1
.byte 0x1
.uleb128 0x49
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xd
.uleb128 0x21
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2f
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0xe
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0x5
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0xf
.uleb128 0x21
.byte 0
.byte 0
.byte 0
.uleb128 0x10
.uleb128 0x13
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x11
.uleb128 0x16
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0x5
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x12
.uleb128 0x13
.byte 0x1
.uleb128 0x3
.uleb128 0xe
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0x5
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x13
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0x5
.uleb128 0x49
.uleb128 0x13
.uleb128 0x38
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x14
.uleb128 0x13
.byte 0x1
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0x5
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x15
.uleb128 0x17
.byte 0x1
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0x5
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x16
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0x5
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x17
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0x5
.uleb128 0x49
.uleb128 0x13
.uleb128 0x38
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x18
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x19
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x1a
.uleb128 0x21
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2f
.uleb128 0x5
.byte 0
.byte 0
.uleb128 0x1b
.uleb128 0x34
.byte 0
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.byte 0
.section .debug_pubnames,"",%progbits
.4byte 0x46
.2byte 0x2
.4byte .Ldebug_info0
.4byte 0x878
.4byte 0x822
.ascii "_Colorsfenda\000"
.4byte 0x833
.ascii "_Palfenda\000"
.4byte 0x85a
.ascii "_acfenda\000"
.4byte 0x86b
.ascii "bmfenda\000"
.4byte 0
.section .debug_pubtypes,"",%progbits
.4byte 0x22d
.2byte 0x2
.4byte .Ldebug_info0
.4byte 0x878
.4byte 0x46
.ascii "int\000"
.4byte 0x4d
.ascii "long int\000"
.4byte 0x21
.ascii "__mbstate_s\000"
.4byte 0x73
.ascii "char\000"
.4byte 0x7f
.ascii "unsigned int\000"
.4byte 0x23f
.ascii "__RAL_locale_data_t\000"
.4byte 0x24f
.ascii "unsigned char\000"
.4byte 0x32e
.ascii "__RAL_locale_codeset_t\000"
.4byte 0x377
.ascii "__RAL_locale_t\000"
.4byte 0x387
.ascii "__locale_s\000"
.4byte 0x4e7
.ascii "short unsigned int\000"
.4byte 0x4ee
.ascii "__RAL_error_decoder_fn_t\000"
.4byte 0x50f
.ascii "__RAL_error_decoder_s\000"
.4byte 0x53d
.ascii "__RAL_error_decoder_t\000"
.4byte 0x55b
.ascii "long long int\000"
.4byte 0x562
.ascii "signed char\000"
.4byte 0x569
.ascii "uint8_t\000"
.4byte 0x579
.ascii "short int\000"
.4byte 0x580
.ascii "uint16_t\000"
.4byte 0x58b
.ascii "uint32_t\000"
.4byte 0x596
.ascii "long long unsigned int\000"
.4byte 0x59d
.ascii "LCD_COLOR\000"
.4byte 0x5ad
.ascii "GUI_COLOR\000"
.4byte 0x5f0
.ascii "LCD_LOGPALETTE\000"
.4byte 0x5fb
.ascii "GUI_LOGPALETTE\000"
.4byte 0x668
.ascii "GUI_BITMAP\000"
.4byte 0x6bc
.ascii "GUI_CHARINFO\000"
.4byte 0x6cd
.ascii "GUI_FONT_PROP\000"
.4byte 0x720
.ascii "GUI_FONT_PROP\000"
.4byte 0x74d
.ascii "GUI_FONT\000"
.4byte 0x7c1
.ascii "GUI_FONT\000"
.4byte 0
.section .debug_aranges,"",%progbits
.4byte 0x14
.2byte 0x2
.4byte .Ldebug_info0
.byte 0x4
.byte 0
.2byte 0
.2byte 0
.4byte 0
.4byte 0
.section .debug_macro,"",%progbits
.Ldebug_macro0:
.2byte 0x4
.byte 0x2
.4byte .Ldebug_line0
.byte 0x7
.4byte .Ldebug_macro1
.byte 0x3
.uleb128 0
.uleb128 0x4
.file 5 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.12/include/stdlib.h"
.byte 0x3
.uleb128 0x17
.uleb128 0x5
.byte 0x5
.uleb128 0x2d
.4byte .LASF456
.byte 0x3
.uleb128 0x2f
.uleb128 0x1
.byte 0x7
.4byte .Ldebug_macro2
.byte 0x4
.byte 0x7
.4byte .Ldebug_macro3
.byte 0x4
.byte 0x3
.uleb128 0x19
.uleb128 0x3
.byte 0x5
.uleb128 0x15
.4byte .LASF485
.byte 0x3
.uleb128 0x1a
.uleb128 0x2
.byte 0x7
.4byte .Ldebug_macro4
.byte 0x4
.byte 0x7
.4byte .Ldebug_macro5
.byte 0x4
.byte 0x4
.byte 0
.section .debug_macro,"G",%progbits,wm4.0.1a6b52451ff263967103185a0aef6166,comdat
.Ldebug_macro1:
.2byte 0x4
.byte 0
.byte 0x5
.uleb128 0
.4byte .LASF0
.byte 0x5
.uleb128 0
.4byte .LASF1
.byte 0x5
.uleb128 0
.4byte .LASF2
.byte 0x5
.uleb128 0
.4byte .LASF3
.byte 0x5
.uleb128 0
.4byte .LASF4
.byte 0x5
.uleb128 0
.4byte .LASF5
.byte 0x5
.uleb128 0
.4byte .LASF6
.byte 0x5
.uleb128 0
.4byte .LASF7
.byte 0x5
.uleb128 0
.4byte .LASF8
.byte 0x5
.uleb128 0
.4byte .LASF9
.byte 0x5
.uleb128 0
.4byte .LASF10
.byte 0x5
.uleb128 0
.4byte .LASF11
.byte 0x5
.uleb128 0
.4byte .LASF12
.byte 0x5
.uleb128 0
.4byte .LASF13
.byte 0x5
.uleb128 0
.4byte .LASF14
.byte 0x5
.uleb128 0
.4byte .LASF15
.byte 0x5
.uleb128 0
.4byte .LASF16
.byte 0x5
.uleb128 0
.4byte .LASF17
.byte 0x5
.uleb128 0
.4byte .LASF18
.byte 0x5
.uleb128 0
.4byte .LASF19
.byte 0x5
.uleb128 0
.4byte .LASF20
.byte 0x5
.uleb128 0
.4byte .LASF21
.byte 0x5
.uleb128 0
.4byte .LASF22
.byte 0x5
.uleb128 0
.4byte .LASF23
.byte 0x5
.uleb128 0
.4byte .LASF24
.byte 0x5
.uleb128 0
.4byte .LASF25
.byte 0x5
.uleb128 0
.4byte .LASF26
.byte 0x5
.uleb128 0
.4byte .LASF27
.byte 0x5
.uleb128 0
.4byte .LASF28
.byte 0x5
.uleb128 0
.4byte .LASF29
.byte 0x5
.uleb128 0
.4byte .LASF30
.byte 0x5
.uleb128 0
.4byte .LASF31
.byte 0x5
.uleb128 0
.4byte .LASF32
.byte 0x5
.uleb128 0
.4byte .LASF33
.byte 0x5
.uleb128 0
.4byte .LASF34
.byte 0x5
.uleb128 0
.4byte .LASF35
.byte 0x5
.uleb128 0
.4byte .LASF36
.byte 0x5
.uleb128 0
.4byte .LASF37
.byte 0x5
.uleb128 0
.4byte .LASF38
.byte 0x5
.uleb128 0
.4byte .LASF39
.byte 0x5
.uleb128 0
.4byte .LASF40
.byte 0x5
.uleb128 0
.4byte .LASF41
.byte 0x5
.uleb128 0
.4byte .LASF42
.byte 0x5
.uleb128 0
.4byte .LASF43
.byte 0x5
.uleb128 0
.4byte .LASF44
.byte 0x5
.uleb128 0
.4byte .LASF45
.byte 0x5
.uleb128 0
.4byte .LASF46
.byte 0x5
.uleb128 0
.4byte .LASF47
.byte 0x5
.uleb128 0
.4byte .LASF48
.byte 0x5
.uleb128 0
.4byte .LASF49
.byte 0x5
.uleb128 0
.4byte .LASF50
.byte 0x5
.uleb128 0
.4byte .LASF51
.byte 0x5
.uleb128 0
.4byte .LASF52
.byte 0x5
.uleb128 0
.4byte .LASF53
.byte 0x5
.uleb128 0
.4byte .LASF54
.byte 0x5
.uleb128 0
.4byte .LASF55
.byte 0x5
.uleb128 0
.4byte .LASF56
.byte 0x5
.uleb128 0
.4byte .LASF57
.byte 0x5
.uleb128 0
.4byte .LASF58
.byte 0x5
.uleb128 0
.4byte .LASF59
.byte 0x5
.uleb128 0
.4byte .LASF60
.byte 0x5
.uleb128 0
.4byte .LASF61
.byte 0x5
.uleb128 0
.4byte .LASF62
.byte 0x5
.uleb128 0
.4byte .LASF63
.byte 0x5
.uleb128 0
.4byte .LASF64
.byte 0x5
.uleb128 0
.4byte .LASF65
.byte 0x5
.uleb128 0
.4byte .LASF66
.byte 0x5
.uleb128 0
.4byte .LASF67
.byte 0x5
.uleb128 0
.4byte .LASF68
.byte 0x5
.uleb128 0
.4byte .LASF69
.byte 0x5
.uleb128 0
.4byte .LASF70
.byte 0x5
.uleb128 0
.4byte .LASF71
.byte 0x5
.uleb128 0
.4byte .LASF72
.byte 0x5
.uleb128 0
.4byte .LASF73
.byte 0x5
.uleb128 0
.4byte .LASF74
.byte 0x5
.uleb128 0
.4byte .LASF75
.byte 0x5
.uleb128 0
.4byte .LASF76
.byte 0x5
.uleb128 0
.4byte .LASF77
.byte 0x5
.uleb128 0
.4byte .LASF78
.byte 0x5
.uleb128 0
.4byte .LASF79
.byte 0x5
.uleb128 0
.4byte .LASF80
.byte 0x5
.uleb128 0
.4byte .LASF81
.byte 0x5
.uleb128 0
.4byte .LASF82
.byte 0x5
.uleb128 0
.4byte .LASF83
.byte 0x5
.uleb128 0
.4byte .LASF84
.byte 0x5
.uleb128 0
.4byte .LASF85
.byte 0x5
.uleb128 0
.4byte .LASF86
.byte 0x5
.uleb128 0
.4byte .LASF87
.byte 0x5
.uleb128 0
.4byte .LASF88
.byte 0x5
.uleb128 0
.4byte .LASF89
.byte 0x5
.uleb128 0
.4byte .LASF90
.byte 0x5
.uleb128 0
.4byte .LASF91
.byte 0x5
.uleb128 0
.4byte .LASF92
.byte 0x5
.uleb128 0
.4byte .LASF93
.byte 0x5
.uleb128 0
.4byte .LASF94
.byte 0x5
.uleb128 0
.4byte .LASF95
.byte 0x5
.uleb128 0
.4byte .LASF96
.byte 0x5
.uleb128 0
.4byte .LASF97
.byte 0x5
.uleb128 0
.4byte .LASF98
.byte 0x5
.uleb128 0
.4byte .LASF99
.byte 0x5
.uleb128 0
.4byte .LASF100
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.4byte .LASF454
.byte 0x5
.uleb128 0
.4byte .LASF455
.byte 0
.section .debug_macro,"G",%progbits,wm4.__crossworks.h.45.c15bb6e0a60630589d552427ceaabe49,comdat
.Ldebug_macro2:
.2byte 0x4
.byte 0
.byte 0x5
.uleb128 0x2d
.4byte .LASF457
.byte 0x5
.uleb128 0x41
.4byte .LASF458
.byte 0x6
.uleb128 0x43
.4byte .LASF459
.byte 0x5
.uleb128 0x45
.4byte .LASF460
.byte 0x5
.uleb128 0x49
.4byte .LASF461
.byte 0x5
.uleb128 0x4b
.4byte .LASF462
.byte 0x5
.uleb128 0x5c
.4byte .LASF463
.byte 0x5
.uleb128 0x63
.4byte .LASF458
.byte 0x5
.uleb128 0x69
.4byte .LASF464
.byte 0x5
.uleb128 0x6a
.4byte .LASF465
.byte 0x5
.uleb128 0x6b
.4byte .LASF466
.byte 0x5
.uleb128 0x6c
.4byte .LASF467
.byte 0x5
.uleb128 0x6d
.4byte .LASF468
.byte 0x5
.uleb128 0x6e
.4byte .LASF469
.byte 0x5
.uleb128 0x6f
.4byte .LASF470
.byte 0x5
.uleb128 0x70
.4byte .LASF471
.byte 0x5
.uleb128 0x73
.4byte .LASF472
.byte 0x5
.uleb128 0x74
.4byte .LASF473
.byte 0x5
.uleb128 0x75
.4byte .LASF474
.byte 0x5
.uleb128 0x76
.4byte .LASF475
.byte 0x5
.uleb128 0x7b
.4byte .LASF476
.byte 0x5
.uleb128 0xda
.4byte .LASF477
.byte 0
.section .debug_macro,"G",%progbits,wm4.stdlib.h.54.34e6c3eb1c7772d5405254538c14b58d,comdat
.Ldebug_macro3:
.2byte 0x4
.byte 0
.byte 0x5
.uleb128 0x36
.4byte .LASF478
.byte 0x5
.uleb128 0x3c
.4byte .LASF479
.byte 0x5
.uleb128 0x42
.4byte .LASF480
.byte 0x5
.uleb128 0x4a
.4byte .LASF481
.byte 0x5
.uleb128 0x51
.4byte .LASF482
.byte 0x5
.uleb128 0x59
.4byte .LASF483
.byte 0x5
.uleb128 0x63
.4byte .LASF484
.byte 0
.section .debug_macro,"G",%progbits,wm4.stdint.h.45.370e29a4497ae7c3b4c92e383ca5b648,comdat
.Ldebug_macro4:
.2byte 0x4
.byte 0
.byte 0x5
.uleb128 0x2d
.4byte .LASF486
.byte 0x5
.uleb128 0x79
.4byte .LASF487
.byte 0x5
.uleb128 0x7b
.4byte .LASF488
.byte 0x5
.uleb128 0x7c
.4byte .LASF489
.byte 0x5
.uleb128 0x7e
.4byte .LASF490
.byte 0x5
.uleb128 0x80
.4byte .LASF491
.byte 0x5
.uleb128 0x81
.4byte .LASF492
.byte 0x5
.uleb128 0x83
.4byte .LASF493
.byte 0x5
.uleb128 0x84
.4byte .LASF494
.byte 0x5
.uleb128 0x85
.4byte .LASF495
.byte 0x5
.uleb128 0x87
.4byte .LASF496
.byte 0x5
.uleb128 0x88
.4byte .LASF497
.byte 0x5
.uleb128 0x89
.4byte .LASF498
.byte 0x5
.uleb128 0x8b
.4byte .LASF499
.byte 0x5
.uleb128 0x8c
.4byte .LASF500
.byte 0x5
.uleb128 0x8d
.4byte .LASF501
.byte 0x5
.uleb128 0x90
.4byte .LASF502
.byte 0x5
.uleb128 0x91
.4byte .LASF503
.byte 0x5
.uleb128 0x92
.4byte .LASF504
.byte 0x5
.uleb128 0x93
.4byte .LASF505
.byte 0x5
.uleb128 0x94
.4byte .LASF506
.byte 0x5
.uleb128 0x95
.4byte .LASF507
.byte 0x5
.uleb128 0x96
.4byte .LASF508
.byte 0x5
.uleb128 0x97
.4byte .LASF509
.byte 0x5
.uleb128 0x98
.4byte .LASF510
.byte 0x5
.uleb128 0x99
.4byte .LASF511
.byte 0x5
.uleb128 0x9a
.4byte .LASF512
.byte 0x5
.uleb128 0x9b
.4byte .LASF513
.byte 0x5
.uleb128 0x9d
.4byte .LASF514
.byte 0x5
.uleb128 0x9e
.4byte .LASF515
.byte 0x5
.uleb128 0x9f
.4byte .LASF516
.byte 0x5
.uleb128 0xa0
.4byte .LASF517
.byte 0x5
.uleb128 0xa1
.4byte .LASF518
.byte 0x5
.uleb128 0xa2
.4byte .LASF519
.byte 0x5
.uleb128 0xa3
.4byte .LASF520
.byte 0x5
.uleb128 0xa4
.4byte .LASF521
.byte 0x5
.uleb128 0xa5
.4byte .LASF522
.byte 0x5
.uleb128 0xa6
.4byte .LASF523
.byte 0x5
.uleb128 0xa7
.4byte .LASF524
.byte 0x5
.uleb128 0xa8
.4byte .LASF525
.byte 0x5
.uleb128 0xad
.4byte .LASF526
.byte 0x5
.uleb128 0xae
.4byte .LASF527
.byte 0x5
.uleb128 0xaf
.4byte .LASF528
.byte 0x5
.uleb128 0xb1
.4byte .LASF529
.byte 0x5
.uleb128 0xb2
.4byte .LASF530
.byte 0x5
.uleb128 0xb3
.4byte .LASF531
.byte 0x5
.uleb128 0xc3
.4byte .LASF532
.byte 0x5
.uleb128 0xc4
.4byte .LASF533
.byte 0x5
.uleb128 0xc5
.4byte .LASF534
.byte 0x5
.uleb128 0xc6
.4byte .LASF535
.byte 0x5
.uleb128 0xc7
.4byte .LASF536
.byte 0x5
.uleb128 0xc8
.4byte .LASF537
.byte 0x5
.uleb128 0xc9
.4byte .LASF538
.byte 0x5
.uleb128 0xca
.4byte .LASF539
.byte 0x5
.uleb128 0xcc
.4byte .LASF540
.byte 0x5
.uleb128 0xcd
.4byte .LASF541
.byte 0x5
.uleb128 0xd7
.4byte .LASF542
.byte 0x5
.uleb128 0xd8
.4byte .LASF543
.byte 0x5
.uleb128 0xdc
.4byte .LASF544
.byte 0x5
.uleb128 0xdd
.4byte .LASF545
.byte 0
.section .debug_macro,"G",%progbits,wm4.GUI.h.32.069f62579959108f32cd788b88512d84,comdat
.Ldebug_macro5:
.2byte 0x4
.byte 0
.byte 0x5
.uleb128 0x20
.4byte .LASF546
.byte 0x5
.uleb128 0x28
.4byte .LASF547
.byte 0x5
.uleb128 0x4e
.4byte .LASF548
.byte 0x5
.uleb128 0x4f
.4byte .LASF549
.byte 0x5
.uleb128 0x50
.4byte .LASF550
.byte 0x5
.uleb128 0x51
.4byte .LASF551
.byte 0x5
.uleb128 0x52
.4byte .LASF552
.byte 0x5
.uleb128 0x53
.4byte .LASF553
.byte 0x5
.uleb128 0x54
.4byte .LASF554
.byte 0x5
.uleb128 0x55
.4byte .LASF555
.byte 0x5
.uleb128 0x56
.4byte .LASF556
.byte 0x5
.uleb128 0x57
.4byte .LASF557
.byte 0x5
.uleb128 0x58
.4byte .LASF558
.byte 0x5
.uleb128 0x59
.4byte .LASF559
.byte 0x5
.uleb128 0x5a
.4byte .LASF560
.byte 0x5
.uleb128 0x5b
.4byte .LASF561
.byte 0x5
.uleb128 0x5c
.4byte .LASF562
.byte 0x5
.uleb128 0x5d
.4byte .LASF563
.byte 0x5
.uleb128 0x5e
.4byte .LASF564
.byte 0x5
.uleb128 0x5f
.4byte .LASF565
.byte 0x5
.uleb128 0x60
.4byte .LASF566
.byte 0x5
.uleb128 0x61
.4byte .LASF567
.byte 0x5
.uleb128 0x62
.4byte .LASF568
.byte 0x5
.uleb128 0x63
.4byte .LASF569
.byte 0x5
.uleb128 0x64
.4byte .LASF570
.byte 0x5
.uleb128 0x65
.4byte .LASF571
.byte 0x5
.uleb128 0x66
.4byte .LASF572
.byte 0x5
.uleb128 0x67
.4byte .LASF573
.byte 0x5
.uleb128 0x68
.4byte .LASF574
.byte 0x5
.uleb128 0x69
.4byte .LASF575
.byte 0x5
.uleb128 0x6a
.4byte .LASF576
.byte 0x5
.uleb128 0x6b
.4byte .LASF577
.byte 0x5
.uleb128 0x6c
.4byte .LASF578
.byte 0x5
.uleb128 0x6d
.4byte .LASF579
.byte 0x5
.uleb128 0x6e
.4byte .LASF580
.byte 0x5
.uleb128 0x6f
.4byte .LASF581
.byte 0x5
.uleb128 0x70
.4byte .LASF582
.byte 0x5
.uleb128 0x71
.4byte .LASF583
.byte 0x5
.uleb128 0x72
.4byte .LASF584
.byte 0x5
.uleb128 0x73
.4byte .LASF585
.byte 0x5
.uleb128 0x74
.4byte .LASF586
.byte 0x5
.uleb128 0x75
.4byte .LASF587
.byte 0x5
.uleb128 0x76
.4byte .LASF588
.byte 0x5
.uleb128 0x77
.4byte .LASF589
.byte 0x5
.uleb128 0x78
.4byte .LASF590
.byte 0x5
.uleb128 0x79
.4byte .LASF591
.byte 0x5
.uleb128 0x7a
.4byte .LASF592
.byte 0x5
.uleb128 0x7b
.4byte .LASF593
.byte 0x5
.uleb128 0x7c
.4byte .LASF594
.byte 0x5
.uleb128 0x7d
.4byte .LASF595
.byte 0x5
.uleb128 0x7e
.4byte .LASF596
.byte 0x5
.uleb128 0x7f
.4byte .LASF597
.byte 0x5
.uleb128 0x80
.4byte .LASF598
.byte 0x5
.uleb128 0x81
.4byte .LASF599
.byte 0x5
.uleb128 0x82
.4byte .LASF600
.byte 0x5
.uleb128 0x83
.4byte .LASF601
.byte 0x5
.uleb128 0x84
.4byte .LASF602
.byte 0x5
.uleb128 0x85
.4byte .LASF603
.byte 0x5
.uleb128 0x86
.4byte .LASF604
.byte 0x5
.uleb128 0x87
.4byte .LASF605
.byte 0x5
.uleb128 0x88
.4byte .LASF606
.byte 0x5
.uleb128 0x89
.4byte .LASF607
.byte 0x5
.uleb128 0x8a
.4byte .LASF608
.byte 0x5
.uleb128 0x8b
.4byte .LASF609
.byte 0x5
.uleb128 0x8c
.4byte .LASF610
.byte 0x5
.uleb128 0x8d
.4byte .LASF611
.byte 0x5
.uleb128 0x8e
.4byte .LASF612
.byte 0x5
.uleb128 0x8f
.4byte .LASF613
.byte 0x5
.uleb128 0x90
.4byte .LASF614
.byte 0x5
.uleb128 0x91
.4byte .LASF615
.byte 0x5
.uleb128 0x92
.4byte .LASF616
.byte 0x5
.uleb128 0x93
.4byte .LASF617
.byte 0x5
.uleb128 0x94
.4byte .LASF618
.byte 0x5
.uleb128 0x95
.4byte .LASF619
.byte 0x5
.uleb128 0x96
.4byte .LASF620
.byte 0x5
.uleb128 0x97
.4byte .LASF621
.byte 0x5
.uleb128 0x98
.4byte .LASF622
.byte 0x5
.uleb128 0x99
.4byte .LASF623
.byte 0x5
.uleb128 0x9a
.4byte .LASF624
.byte 0x5
.uleb128 0x9b
.4byte .LASF625
.byte 0x5
.uleb128 0x9c
.4byte .LASF626
.byte 0x5
.uleb128 0x9d
.4byte .LASF627
.byte 0x5
.uleb128 0x9e
.4byte .LASF628
.byte 0x5
.uleb128 0x9f
.4byte .LASF629
.byte 0x5
.uleb128 0xa0
.4byte .LASF630
.byte 0x5
.uleb128 0xa1
.4byte .LASF631
.byte 0x5
.uleb128 0xa2
.4byte .LASF632
.byte 0x5
.uleb128 0xa3
.4byte .LASF633
.byte 0x5
.uleb128 0xa4
.4byte .LASF634
.byte 0x5
.uleb128 0xa5
.4byte .LASF635
.byte 0x5
.uleb128 0xa6
.4byte .LASF636
.byte 0x5
.uleb128 0xa7
.4byte .LASF637
.byte 0x5
.uleb128 0xa8
.4byte .LASF638
.byte 0x5
.uleb128 0xa9
.4byte .LASF639
.byte 0x5
.uleb128 0xaa
.4byte .LASF640
.byte 0x5
.uleb128 0xab
.4byte .LASF641
.byte 0x5
.uleb128 0xac
.4byte .LASF642
.byte 0x5
.uleb128 0xad
.4byte .LASF643
.byte 0x5
.uleb128 0xae
.4byte .LASF644
.byte 0x5
.uleb128 0xaf
.4byte .LASF645
.byte 0x5
.uleb128 0xb0
.4byte .LASF646
.byte 0x5
.uleb128 0xb1
.4byte .LASF647
.byte 0x5
.uleb128 0xb2
.4byte .LASF648
.byte 0x5
.uleb128 0xb3
.4byte .LASF649
.byte 0x5
.uleb128 0xb4
.4byte .LASF650
.byte 0x5
.uleb128 0xb5
.4byte .LASF651
.byte 0x5
.uleb128 0xb6
.4byte .LASF652
.byte 0x5
.uleb128 0xb7
.4byte .LASF653
.byte 0x5
.uleb128 0xb8
.4byte .LASF654
.byte 0x5
.uleb128 0xb9
.4byte .LASF655
.byte 0x5
.uleb128 0xba
.4byte .LASF656
.byte 0x5
.uleb128 0xbb
.4byte .LASF657
.byte 0x5
.uleb128 0xbc
.4byte .LASF658
.byte 0x5
.uleb128 0xbd
.4byte .LASF659
.byte 0x5
.uleb128 0xbe
.4byte .LASF660
.byte 0x5
.uleb128 0xbf
.4byte .LASF661
.byte 0x5
.uleb128 0xc0
.4byte .LASF662
.byte 0x5
.uleb128 0xc1
.4byte .LASF663
.byte 0x5
.uleb128 0xc2
.4byte .LASF664
.byte 0x5
.uleb128 0xc3
.4byte .LASF665
.byte 0x5
.uleb128 0xc4
.4byte .LASF666
.byte 0x5
.uleb128 0xc5
.4byte .LASF667
.byte 0x5
.uleb128 0xc6
.4byte .LASF668
.byte 0x5
.uleb128 0xc7
.4byte .LASF669
.byte 0x5
.uleb128 0xc8
.4byte .LASF670
.byte 0x5
.uleb128 0xc9
.4byte .LASF671
.byte 0x5
.uleb128 0xca
.4byte .LASF672
.byte 0x5
.uleb128 0xcb
.4byte .LASF673
.byte 0x5
.uleb128 0xcc
.4byte .LASF674
.byte 0x5
.uleb128 0xcd
.4byte .LASF675
.byte 0x5
.uleb128 0xce
.4byte .LASF676
.byte 0x5
.uleb128 0xcf
.4byte .LASF677
.byte 0x5
.uleb128 0xd0
.4byte .LASF678
.byte 0x5
.uleb128 0xd1
.4byte .LASF679
.byte 0x5
.uleb128 0xd2
.4byte .LASF680
.byte 0x5
.uleb128 0xd3
.4byte .LASF681
.byte 0x5
.uleb128 0xd4
.4byte .LASF682
.byte 0x5
.uleb128 0xd5
.4byte .LASF683
.byte 0x5
.uleb128 0xd6
.4byte .LASF684
.byte 0x5
.uleb128 0xd7
.4byte .LASF685
.byte 0x5
.uleb128 0xd8
.4byte .LASF686
.byte 0x5
.uleb128 0xd9
.4byte .LASF687
.byte 0x5
.uleb128 0xda
.4byte .LASF688
.byte 0x5
.uleb128 0xdb
.4byte .LASF689
.byte 0x5
.uleb128 0xdc
.4byte .LASF690
.byte 0x5
.uleb128 0xdd
.4byte .LASF691
.byte 0x5
.uleb128 0xde
.4byte .LASF692
.byte 0x5
.uleb128 0xdf
.4byte .LASF693
.byte 0x5
.uleb128 0xe0
.4byte .LASF694
.byte 0x5
.uleb128 0xe1
.4byte .LASF695
.byte 0x5
.uleb128 0xe2
.4byte .LASF696
.byte 0x5
.uleb128 0xe3
.4byte .LASF697
.byte 0x5
.uleb128 0xe4
.4byte .LASF698
.byte 0x5
.uleb128 0xe5
.4byte .LASF699
.byte 0x5
.uleb128 0xe6
.4byte .LASF700
.byte 0x5
.uleb128 0xe7
.4byte .LASF701
.byte 0x5
.uleb128 0xe8
.4byte .LASF702
.byte 0x5
.uleb128 0xe9
.4byte .LASF703
.byte 0x5
.uleb128 0xea
.4byte .LASF704
.byte 0x5
.uleb128 0xeb
.4byte .LASF705
.byte 0x5
.uleb128 0xec
.4byte .LASF706
.byte 0x5
.uleb128 0xed
.4byte .LASF707
.byte 0x5
.uleb128 0xee
.4byte .LASF708
.byte 0x5
.uleb128 0xef
.4byte .LASF709
.byte 0x5
.uleb128 0xf0
.4byte .LASF710
.byte 0x5
.uleb128 0xf1
.4byte .LASF711
.byte 0x5
.uleb128 0xf2
.4byte .LASF712
.byte 0x5
.uleb128 0xf3
.4byte .LASF713
.byte 0x5
.uleb128 0xf4
.4byte .LASF714
.byte 0x5
.uleb128 0xf5
.4byte .LASF715
.byte 0x5
.uleb128 0xf6
.4byte .LASF716
.byte 0x5
.uleb128 0xf7
.4byte .LASF717
.byte 0x5
.uleb128 0xf8
.4byte .LASF718
.byte 0x5
.uleb128 0xf9
.4byte .LASF719
.byte 0x5
.uleb128 0xfa
.4byte .LASF720
.byte 0x5
.uleb128 0xfb
.4byte .LASF721
.byte 0x5
.uleb128 0xfc
.4byte .LASF722
.byte 0x5
.uleb128 0xfd
.4byte .LASF723
.byte 0x5
.uleb128 0xfe
.4byte .LASF724
.byte 0x5
.uleb128 0xff
.4byte .LASF725
.byte 0x5
.uleb128 0x100
.4byte .LASF726
.byte 0x5
.uleb128 0x101
.4byte .LASF727
.byte 0x5
.uleb128 0x102
.4byte .LASF728
.byte 0x5
.uleb128 0x103
.4byte .LASF729
.byte 0x5
.uleb128 0x104
.4byte .LASF730
.byte 0x5
.uleb128 0x105
.4byte .LASF731
.byte 0x5
.uleb128 0x106
.4byte .LASF732
.byte 0x5
.uleb128 0x107
.4byte .LASF733
.byte 0x5
.uleb128 0x108
.4byte .LASF734
.byte 0x5
.uleb128 0x109
.4byte .LASF735
.byte 0x5
.uleb128 0x10a
.4byte .LASF736
.byte 0x5
.uleb128 0x10b
.4byte .LASF737
.byte 0x5
.uleb128 0x10c
.4byte .LASF738
.byte 0x5
.uleb128 0x10d
.4byte .LASF739
.byte 0x5
.uleb128 0x10e
.4byte .LASF740
.byte 0x5
.uleb128 0x10f
.4byte .LASF741
.byte 0x5
.uleb128 0x110
.4byte .LASF742
.byte 0x5
.uleb128 0x111
.4byte .LASF743
.byte 0x5
.uleb128 0x112
.4byte .LASF744
.byte 0x5
.uleb128 0x113
.4byte .LASF745
.byte 0x5
.uleb128 0x114
.4byte .LASF746
.byte 0x5
.uleb128 0x115
.4byte .LASF747
.byte 0x5
.uleb128 0x116
.4byte .LASF748
.byte 0x5
.uleb128 0x117
.4byte .LASF749
.byte 0x5
.uleb128 0x118
.4byte .LASF750
.byte 0x5
.uleb128 0x119
.4byte .LASF751
.byte 0x5
.uleb128 0x11a
.4byte .LASF752
.byte 0x5
.uleb128 0x11b
.4byte .LASF753
.byte 0x5
.uleb128 0x11c
.4byte .LASF754
.byte 0x5
.uleb128 0x11d
.4byte .LASF755
.byte 0x5
.uleb128 0x11e
.4byte .LASF756
.byte 0x5
.uleb128 0x11f
.4byte .LASF757
.byte 0x5
.uleb128 0x120
.4byte .LASF758
.byte 0x5
.uleb128 0x121
.4byte .LASF759
.byte 0x5
.uleb128 0x122
.4byte .LASF760
.byte 0x5
.uleb128 0x123
.4byte .LASF761
.byte 0x5
.uleb128 0x124
.4byte .LASF762
.byte 0x5
.uleb128 0x125
.4byte .LASF763
.byte 0x5
.uleb128 0x126
.4byte .LASF764
.byte 0x5
.uleb128 0x127
.4byte .LASF765
.byte 0x5
.uleb128 0x128
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| 13.428353 | 126 | 0.673033 |
7227850ccf8ae8cb3bae340b0eefda16d1e9fcdc | 556 | asm | Assembly | data/baseStats/hoppip.asm | adhi-thirumala/EvoYellow | 6fb1b1d6a1fa84b02e2d982f270887f6c63cdf4c | [
"Unlicense"
] | 16 | 2018-08-28T21:47:01.000Z | 2022-02-20T20:29:59.000Z | data/baseStats/hoppip.asm | adhi-thirumala/EvoYellow | 6fb1b1d6a1fa84b02e2d982f270887f6c63cdf4c | [
"Unlicense"
] | 5 | 2019-04-03T19:53:11.000Z | 2022-03-11T22:49:34.000Z | data/baseStats/hoppip.asm | adhi-thirumala/EvoYellow | 6fb1b1d6a1fa84b02e2d982f270887f6c63cdf4c | [
"Unlicense"
] | 2 | 2019-12-09T19:46:02.000Z | 2020-12-05T21:36:30.000Z | db DEX_HOPPIP ; pokedex id
db 35 ; base hp
db 35 ; base attack
db 40 ; base defense
db 50 ; base speed
db 45 ; base special
db GRASS ; species type 1
db FLYING ; species type 2
db 255 ; catch rate
db 74 ; base exp yield
INCBIN "pic/ymon/hoppip.pic",0,1 ; 55, sprite dimensions
dw HoppipPicFront
dw HoppipPicBack
; attacks known at lvl 0
db SPLASH
db 0
db 0
db 0
db 3 ; growth rate
; learnset
tmlearn 2,3,4,6
tmlearn 9,10
tmlearn 20,21,22
tmlearn 31,32
tmlearn 33,34
tmlearn 43,44
tmlearn 50,51
db Bank(HoppipPicFront) ; padding
| 19.172414 | 57 | 0.703237 |
b38effe7ec623b13a0c5079e34b34d21e1581a45 | 159 | asm | Assembly | src/patches/maphacks-jp.asm | SenhorGatinho/kale | a4e1819c568c3925cd7e94a8b06608e1c233ebf9 | [
"MIT"
] | 32 | 2015-03-02T05:40:42.000Z | 2022-02-21T04:13:02.000Z | src/patches/maphacks-jp.asm | SenhorGatinho/kale | a4e1819c568c3925cd7e94a8b06608e1c233ebf9 | [
"MIT"
] | null | null | null | src/patches/maphacks-jp.asm | SenhorGatinho/kale | a4e1819c568c3925cd7e94a8b06608e1c233ebf9 | [
"MIT"
] | 3 | 2017-02-03T05:01:51.000Z | 2022-01-10T01:38:13.000Z | incsrc "vars.asm"
//; Japan code locations
define SwapBank8 $d787
define SwapBankA $d796
define SwitchOld $a000
define GetTilePtr $efaa
incsrc "mapextra.asm" | 17.666667 | 24 | 0.786164 |
ccf13e0d5db9f82bf943cda1f7eb426ce341e9ba | 7,534 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca.log_21829_594.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca.log_21829_594.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca.log_21829_594.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r14
push %rax
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_WT_ht+0xbf1a, %rsi
nop
nop
nop
nop
nop
sub $50315, %r14
movb $0x61, (%rsi)
nop
nop
nop
sub $42187, %rax
lea addresses_WT_ht+0xb270, %rcx
nop
nop
nop
nop
lfence
movb $0x61, (%rcx)
nop
nop
nop
nop
nop
inc %rax
lea addresses_WC_ht+0x116f0, %r12
nop
nop
nop
nop
nop
sub $22225, %rbp
mov (%r12), %ax
nop
nop
nop
nop
nop
add $12348, %rcx
lea addresses_WC_ht+0xb0f0, %r14
nop
nop
nop
nop
add %rcx, %rcx
mov $0x6162636465666768, %rax
movq %rax, %xmm7
movups %xmm7, (%r14)
nop
nop
nop
xor $24358, %r11
lea addresses_A_ht+0x2f0, %rsi
nop
dec %rcx
mov $0x6162636465666768, %r14
movq %r14, (%rsi)
and $62173, %rcx
lea addresses_UC_ht+0x13795, %rsi
lea addresses_D_ht+0x19010, %rdi
nop
nop
nop
nop
nop
xor $9546, %rax
mov $66, %rcx
rep movsw
nop
nop
nop
dec %rcx
lea addresses_UC_ht+0x10af0, %rsi
lea addresses_WC_ht+0x17b90, %rdi
nop
nop
nop
nop
nop
dec %rbp
mov $54, %rcx
rep movsb
nop
nop
nop
nop
xor $26064, %rbp
lea addresses_A_ht+0xeef0, %r11
nop
nop
nop
xor %rax, %rax
mov $0x6162636465666768, %rdi
movq %rdi, %xmm5
and $0xffffffffffffffc0, %r11
movaps %xmm5, (%r11)
nop
nop
add %r12, %r12
lea addresses_WT_ht+0x6450, %rbp
clflush (%rbp)
nop
and %r12, %r12
movw $0x6162, (%rbp)
nop
nop
nop
inc %r12
lea addresses_D_ht+0xdbb9, %rdi
nop
nop
nop
nop
and $14923, %rbp
movups (%rdi), %xmm7
vpextrq $1, %xmm7, %r14
nop
nop
nop
nop
nop
add $4484, %rsi
lea addresses_UC_ht+0x75f0, %rax
nop
nop
nop
nop
nop
and %rsi, %rsi
mov $0x6162636465666768, %rdi
movq %rdi, %xmm7
movups %xmm7, (%rax)
nop
nop
sub $52481, %r12
lea addresses_UC_ht+0x18ef0, %rax
nop
xor $64244, %rcx
movl $0x61626364, (%rax)
nop
add $35521, %rsi
lea addresses_normal_ht+0x14435, %r14
nop
nop
nop
xor $50819, %r12
movups (%r14), %xmm4
vpextrq $1, %xmm4, %rdi
nop
nop
nop
nop
nop
add $31092, %r11
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %rax
pop %r14
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r12
push %r13
push %rcx
push %rdx
push %rsi
// Store
mov $0x7ad, %rsi
nop
nop
nop
add %r10, %r10
mov $0x5152535455565758, %rdx
movq %rdx, %xmm2
vmovups %ymm2, (%rsi)
xor $36909, %r10
// Faulty Load
lea addresses_PSE+0x13af0, %r12
inc %r10
mov (%r12), %rcx
lea oracles, %rdx
and $0xff, %rcx
shlq $12, %rcx
mov (%rdx,%rcx,1), %rcx
pop %rsi
pop %rdx
pop %rcx
pop %r13
pop %r12
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'size': 4, 'NT': False, 'type': 'addresses_PSE', 'same': False, 'AVXalign': False, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'size': 32, 'NT': False, 'type': 'addresses_P', 'same': False, 'AVXalign': False, 'congruent': 0}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'size': 8, 'NT': False, 'type': 'addresses_PSE', 'same': True, 'AVXalign': False, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'size': 1, 'NT': False, 'type': 'addresses_WT_ht', 'same': True, 'AVXalign': False, 'congruent': 1}}
{'OP': 'STOR', 'dst': {'size': 1, 'NT': False, 'type': 'addresses_WT_ht', 'same': False, 'AVXalign': False, 'congruent': 7}}
{'OP': 'LOAD', 'src': {'size': 2, 'NT': True, 'type': 'addresses_WC_ht', 'same': False, 'AVXalign': True, 'congruent': 10}}
{'OP': 'STOR', 'dst': {'size': 16, 'NT': False, 'type': 'addresses_WC_ht', 'same': False, 'AVXalign': False, 'congruent': 3}}
{'OP': 'STOR', 'dst': {'size': 8, 'NT': False, 'type': 'addresses_A_ht', 'same': False, 'AVXalign': True, 'congruent': 10}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_UC_ht', 'congruent': 0}, 'dst': {'same': False, 'type': 'addresses_D_ht', 'congruent': 5}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_UC_ht', 'congruent': 11}, 'dst': {'same': False, 'type': 'addresses_WC_ht', 'congruent': 5}}
{'OP': 'STOR', 'dst': {'size': 16, 'NT': False, 'type': 'addresses_A_ht', 'same': False, 'AVXalign': True, 'congruent': 10}}
{'OP': 'STOR', 'dst': {'size': 2, 'NT': False, 'type': 'addresses_WT_ht', 'same': False, 'AVXalign': True, 'congruent': 5}}
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_D_ht', 'same': True, 'AVXalign': False, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'size': 16, 'NT': False, 'type': 'addresses_UC_ht', 'same': True, 'AVXalign': False, 'congruent': 8}}
{'OP': 'STOR', 'dst': {'size': 4, 'NT': False, 'type': 'addresses_UC_ht', 'same': False, 'AVXalign': False, 'congruent': 10}}
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_normal_ht', 'same': False, 'AVXalign': False, 'congruent': 0}}
{'33': 21829}
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
*/
| 32.059574 | 2,999 | 0.657951 |
f1b3e8268b0bb4aec38b4b9972193f14ad448d64 | 1,246 | asm | Assembly | lc4programs/gcd.asm | ArmaanT/yallc | 9de5bf51025221454212410c14bae02b7b7dd5f3 | [
"MIT"
] | 2 | 2020-12-17T17:27:06.000Z | 2020-12-18T18:44:43.000Z | lc4programs/gcd.asm | ArmaanT/yallc | 9de5bf51025221454212410c14bae02b7b7dd5f3 | [
"MIT"
] | null | null | null | lc4programs/gcd.asm | ArmaanT/yallc | 9de5bf51025221454212410c14bae02b7b7dd5f3 | [
"MIT"
] | null | null | null | ;; Expected: 21
gcd
ADD R6, R6, #-3
STR R7, R6, #1
STR R5, R6, #0
ADD R5, R6, #0
LDR R0, R5, #4
ADD R6, R6, #-1
STR R0, R6, #0
CONST R0, #0
ADD R6, R6, #-1
STR R0, R6, #0
LDR R0, R6, #0
LDR R1, R6, #1
CMP R0, R1
BRz test_gcd_j_cmp_true_0
CONST R0, #0
STR R0, R6, #1
BRnzp test_gcd_j_cmp_end_0
test_gcd_j_cmp_true_0
CONST R0, #1
STR R0, R6, #1
test_gcd_j_cmp_end_0
ADD R6, R6, #1
ADD R6, R6, #1
LDR R0, R6, #-1
BRz test_gcd_j_else_0
LDR R0, R5, #3
ADD R6, R6, #-1
STR R0, R6, #0
BRnzp test_gcd_j_endif_0
test_gcd_j_else_0
LDR R0, R5, #4
ADD R6, R6, #-1
STR R0, R6, #0
LDR R0, R5, #3
ADD R6, R6, #-1
STR R0, R6, #0
LDR R0, R6, #0
LDR R1, R6, #1
MOD R0, R0, R1
ADD R6, R6, #1
STR R0, R6, #0
LDR R0, R5, #4
ADD R6, R6, #-1
STR R0, R6, #0
JSR gcd
ADD R6, R6, #-1
test_gcd_j_endif_0
LDR R7, R6, #0
STR R7, R5, #2
ADD R6, R5, #0
LDR R5, R6, #0
LDR R7, R6, #1
ADD R6, R6, #3
RET
main
ADD R6, R6, #-3
STR R7, R6, #1
STR R5, R6, #0
ADD R5, R6, #0
CONST R0, #206
HICONST R0, #1
ADD R6, R6, #-1
STR R0, R6, #0
CONST R0, #47
HICONST R0, #4
ADD R6, R6, #-1
STR R0, R6, #0
JSR gcd
ADD R6, R6, #-1
LDR R7, R6, #0
STR R7, R5, #2
ADD R6, R5, #0
LDR R5, R6, #0
LDR R7, R6, #1
ADD R6, R6, #3
RET | 15.974359 | 27 | 0.573034 |
c5071d75436fea9c6e003f7c79ef33e5b90ca96d | 713 | asm | Assembly | oeis/244/A244352.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/244/A244352.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/244/A244352.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A244352: Pell(n)^3 - Pell(n)^2, where Pell(n) is the n-th Pell number (A000129).
; Submitted by Christian Krause
; 0,0,4,100,1584,23548,338100,4798248,67750848,954701400,13441659268,189185124940,2662308356400,37463104912660,527155118240244,7417689205890000,104375121328998144,1468671237346368048,20665783224031936900,290789699203441908148,4091721938270110043568,57574898969343033385900,810140319949022144026548,11399539450760994443775480,160403693053195038216369600,2257051244658538763157334920,31759121132628429001884871684,446884747185127645302139539100,6288145582212086374860188585904
seq $0,129 ; Pell numbers: a(0) = 0, a(1) = 1; for n > 1, a(n) = 2*a(n-1) + a(n-2).
add $2,$0
bin $0,2
mul $0,$2
mul $0,2
| 71.3 | 474 | 0.816269 |
577ea572022c9c7365da864f6ed74ab335ed3a8f | 328 | asm | Assembly | programs/oeis/043/A043529.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/043/A043529.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/043/A043529.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A043529: Number of distinct base-2 digits of n.
; 1,1,2,1,2,2,2,1,2,2,2,2,2,2,2,1,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,1,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,1,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2
lpb $0
sub $0,1
mul $0,2
dif $0,4
lpe
lpb $0
mov $0,1
lpe
add $0,1
| 25.230769 | 201 | 0.536585 |
1d9628a49f68c729152040e67cb387f3ced57c2a | 9,781 | asm | Assembly | ASM/src/item_overrides.asm | ShadoMagi/OoT-Randomizer | f9abb00a299e2f50f52fee4962047f8ab7f84975 | [
"MIT"
] | null | null | null | ASM/src/item_overrides.asm | ShadoMagi/OoT-Randomizer | f9abb00a299e2f50f52fee4962047f8ab7f84975 | [
"MIT"
] | null | null | null | ASM/src/item_overrides.asm | ShadoMagi/OoT-Randomizer | f9abb00a299e2f50f52fee4962047f8ab7f84975 | [
"MIT"
] | null | null | null | inventory_check:
andi a0, a0, 0xFF
li t0, SAVE_CONTEXT
beq a0, 0x8C, @@return ; Deku Nuts (5)
lbu v0, 0x75 (t0)
beq a0, 0x8D, @@return ; Deku Nuts (10)
lbu v0, 0x75 (t0)
beq a0, 0x00, @@return ; Deku Stick
lbu v0, 0x74 (t0)
beq a0, 0x8A, @@return ; Deku Sticks (5)
lbu v0, 0x74 (t0)
beq a0, 0x8B, @@return ; Deku Sticks (10)
lbu v0, 0x74 (t0)
beq a0, 0x58, @@return ; Deku Seeds (5)
li v0, 0x00
beq a0, 0x78, @@return ; Small Magic Jar
li v0, 0x00
beq a0, 0x79, @@return ; Large Magic Jar
li v0, 0x00
li v0, 0xFF
@@return:
jr ra
nop
;==================================================================================================
override_object_npc:
lw a2, 0x0030 (sp)
lh a1, 0x0004 (a2)
j override_object
nop
override_object_chest:
lw t9, 0x002C (sp)
lh a1, 0x0004 (t9)
j override_object
nop
override_object:
li t2, EXTENDED_ITEM_DATA
lw t3, ITEM_ROW_IS_EXTENDED (t2)
beqz t3, @@return
nop
; Override Object ID
lhu a1, ITEM_ROW_OBJECT_ID (t2)
@@return:
; Clear any pending special item, now that it's being received
li t2, PENDING_SPECIAL_ITEM
sb r0, 0x00 (t2)
; Re-enable warping (disabled by pending item)
li t2, GLOBAL_CONTEXT + 0x104E4
sh r0, 0x00 (t2)
jr ra
nop
;==================================================================================================
override_graphic:
li t0, EXTENDED_ITEM_DATA
lw t1, ITEM_ROW_IS_EXTENDED (t0)
beqz t1, @@return
nop
; Override Graphic ID
lb v1, ITEM_ROW_GRAPHIC_ID (t0)
@@return:
; Displaced code
abs t0, v1
sb t0, 0x0852 (a0)
jr ra
nop
;==================================================================================================
override_text:
lbu a1, 0x03 (v0) ; Displaced code
li t0, EXTENDED_ITEM_DATA
lw t1, ITEM_ROW_IS_EXTENDED (t0)
beqz t1, @@return
nop
; Override Text ID
lbu a1, ITEM_ROW_TEXT_ID (t0)
@@return:
jr ra
nop
;==================================================================================================
override_action:
; Displaced code
lw v0, 0x24 (sp)
lbu a1, 0x0000 (v0)
li t0, EXTENDED_ITEM_DATA
lw t1, ITEM_ROW_IS_EXTENDED (t0)
beqz t1, @@return
nop
; Override Action ID
lbu a1, ITEM_ROW_ACTION_ID (t0)
sw a0, 0x00 (sp)
sw a1, 0x04 (sp)
sw a2, 0x08 (sp)
addiu sp, sp, -0x18
sw ra, 0x10 (sp)
; Run effect function
li a0, SAVE_CONTEXT
lbu a1, ITEM_ROW_EFFECT_ARG1 (t0)
lbu a2, ITEM_ROW_EFFECT_ARG2 (t0)
lw t1, ITEM_ROW_EFFECT_FN (t0)
jalr t1
nop
lw ra, 0x10 (sp)
addiu sp, sp, 0x18
lw a0, 0x00 (sp)
lw a1, 0x04 (sp)
lw a2, 0x08 (sp)
@@return:
jr ra
nop
;==================================================================================================
store_item_data_hook:
sb a2, 0x0424 (a3) ; Displaced code
addiu sp, sp, -0x20
sw v0, 0x10 (sp)
sw v1, 0x14 (sp)
sw ra, 0x18 (sp)
jal store_item_data
nop
lw v0, 0x10 (sp)
lw v1, 0x14 (sp)
lw ra, 0x18 (sp)
addiu sp, sp, 0x20
jr ra
nop
;==================================================================================================
store_item_data:
addiu sp, sp, -0x18
sw ra, 0x10 (sp)
; Clear current item data
li t0, EXTENDED_ITEM_DATA
sw r0, 0x00 (t0)
sw r0, 0x04 (t0)
sw r0, 0x08 (t0)
sw r0, 0x0C (t0)
li t0, PLAYER_ACTOR
lb t1, 0x0424 (t0) ; t1 = item ID being received
beqz t1, @@return
nop
abs a0, t1
lw a1, 0x0428 (t0) ; a1 = actor giving the item
jal lookup_override ; v0 = new item ID from override
nop
bltz v0, @@return
nop
ori a0, v0, 0
jal resolve_extended_item ; v0 = resolved item ID, v1 = ITEM_TABLE entry
nop
beqz v1, @@update_base_game
nop
; Store extended item data
li t0, EXTENDED_ITEM_DATA
lw t1, 0x00 (v1)
sw t1, 0x00 (t0)
lw t1, 0x04 (v1)
sw t1, 0x04 (t0)
lw t1, 0x08 (v1)
sw t1, 0x08 (t0)
; Mark the extended item data as active
li t1, 1
sw t1, ITEM_ROW_IS_EXTENDED (t0)
; Load the base item to be stored back in the player actor / chest
lbu v0, ITEM_ROW_BASE_ITEM (v1)
@@update_base_game:
li t0, PLAYER_ACTOR
; If the giving actor is a chest, update it with new contents
lw t1, 0x0428 (t0)
lhu t2, 0x00 (t1)
bne t2, 0x000A, @@not_chest
nop
lhu t2, 0x1C (t1)
andi t2, t2, 0xF01F
sll t3, v0, 5
or t2, t2, t3
sh t2, 0x1C (t1)
@@not_chest:
; Update player actor
lb t1, 0x0424 (t0)
bgez t1, @@not_negative
nop
; The input was negative (item is in a nearby chest), so make the result negative
subu v0, r0, v0
@@not_negative:
sb v0, 0x0424 (t0)
@@return:
lw ra, 0x10 (sp)
addiu sp, sp, 0x18
jr ra
nop
;==================================================================================================
lookup_override:
; a0 = item ID being received
; a1 = actor giving the item
addiu sp, sp, -0x18
sw ra, 0x10 (sp)
jal get_override_search_key
nop
beq v0, -1, @@return
nop
ori a0, v0, 0
jal scan_override_table
nop
@@return:
lw ra, 0x10 (sp)
addiu sp, sp, 0x18
jr ra
nop
;==================================================================================================
get_override_search_key:
; a0 = item ID being received
; a1 = actor giving the item
; Load the current scene number
li v0, GLOBAL_CONTEXT
lhu v0, 0xA4 (v0)
li t0, 0x00 ; t0 = override type
ori t1, a0, 0 ; t1 = override ID
lhu t2, 0x00 (a1) ; t2 = actor ID
bne t2, 0x000A, @@not_chest
nop
lhu t3, 0x1C (a1)
bne v0, 0x10, @@valid_chest
nop
; Current scene is the treasure chest game.
; Don't apply the override if the chest contains 0x75 (Winner! purple rupee)
andi t4, t3, (0x7F << 5)
bne t4, (0x75 << 5), @@valid_chest
nop
li v0, -1
b @@return
nop
@@valid_chest:
li t0, 0x01
andi t1, t3, 0x1F ; t1 = chest flag
@@not_chest:
bne t2, 0x0015, @@not_collectable
nop
beq a0, 0x3E, @@valid_collectable
nop
beq a0, 0x42, @@valid_collectable
nop
li v0, -1
b @@return
nop
@@valid_collectable:
li t0, 0x02
lbu t1, 0x0141 (a1) ; t1 = collectable flag
@@not_collectable:
; Construct ID used to search the override table
; v0 = (scene << 16) | (override_type << 8) | override_id
sll v0, v0, 8
or v0, v0, t0
sll v0, v0, 8
or v0, v0, t1
@@return:
jr ra
nop
;==================================================================================================
scan_override_table:
; a0 = override search key
li v0, -1
; Look up override
li t0, (ITEM_OVERRIDES - 0x04)
@@lookup_loop:
addiu t0, t0, 0x04
lw t1, 0x00 (t0) ; t1 = override entry
beqz t1, @@return ; Reached end of override table
nop
srl t2, t1, 8 ; t2 = override key
bne t2, a0, @@lookup_loop
nop
andi v0, t1, 0xFF ; v0 = found item ID
@@return:
jr ra
nop
;==================================================================================================
resolve_extended_item:
; a0 = input item ID
addiu sp, sp, -0x20
sw s0, 0x10 (sp)
sw s1, 0x14 (sp)
sw ra, 0x18 (sp)
ori v0, a0, 0 ; Return resolved item ID in v0
@@loop:
ori s0, v0, 0
addiu t0, s0, -0x80 ; t0 = index into extended ITEM_TABLE
bltz t0, @@not_extended ; Item IDs in range 0x00 - 0x7F are not extended
nop
; Load table entry
li s1, ITEM_TABLE
li t1, ITEM_TABLE_ROW_SIZE
mult t0, t1
mflo t0
addu s1, s1, t0 ; s1 = pointer to table entry
; Check whether this item will upgrade into another item
; Conventions for upgrade functions:
; - They receive a pointer to the save context in a0
; - They receive their item ID in a1
; - They store their result in v0
li a0, SAVE_CONTEXT
ori a1, s0, 0
lw t0, ITEM_ROW_UPGRADE_FN (s1)
jalr t0 ; v0 = upgraded item ID
nop
; If the upgrade function returned a new item ID, start resolution over again
bne v0, s0, @@loop
nop
ori v1, s1, 0 ; Return pointer to ITEM_TABLE entry in v1
b @@return
nop
@@not_extended:
li v1, 0
@@return:
lw s0, 0x10 (sp)
lw s1, 0x14 (sp)
lw ra, 0x18 (sp)
addiu sp, sp, 0x20
jr ra
nop
| 24.951531 | 100 | 0.463347 |
e204d01f9a303637eefa6b83b038c605485a24e0 | 782 | asm | Assembly | libsrc/graphics/w_draw.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | null | null | null | libsrc/graphics/w_draw.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | null | null | null | libsrc/graphics/w_draw.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | null | null | null | ;
; Z88 Graphics Functions - Small C+ stubs
;
; Written around the Interlogic Standard Library
;
; Stubs Written by D Morris - 30/9/98
;
; Wide resolution (int type parameters) version by Stefano Bodrato
;
;
; $Id: w_draw.asm $
;
;
; CALLER LINKAGE FOR FUNCTION POINTERS
; ----- void draw(int x, int y, int x2, int y2)
SECTION code_graphics
PUBLIC draw
PUBLIC _draw
EXTERN draw_callee
EXTERN ASMDISP_DRAW_CALLEE
;EXTERN __gfx_color
.draw
._draw
pop af
;pop bc ; color
pop de
pop hl
exx ; w_plotpixel and swapgfxbk must not use the alternate registers, no problem with w_line_r
pop hl
pop de
push de
push hl
exx
push hl
push de
;exx
;push bc
push af ; ret addr
jp draw_callee + ASMDISP_DRAW_CALLEE
| 15.64 | 98 | 0.670077 |
193da8e890d4d47597b58433fe2907c7803dcb04 | 758 | asm | Assembly | programs/oeis/036/A036450.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/036/A036450.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/036/A036450.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A036450: a(n) = d(d(d(n))), the 3rd iterate of the number-of-divisors function with an initial value of n.
; 1,2,2,2,2,2,2,2,2,2,2,3,2,2,2,2,2,3,2,3,2,2,2,3,2,2,2,3,2,3,2,3,2,2,2,2,2,2,2,3,2,3,2,3,3,2,2,3,2,3,2,3,2,3,2,3,2,2,2,4,2,2,3,2,2,3,2,3,2,3,2,4,2,2,3,3,2,3,2,3,2,2,2,4,2,2,2,3,2,4,2,3,2,2,2,4,2,3,3,2,2,3,2,3,3,2,2,4,2,3,2,3,2,3,2,3,3,2,2,2,2,2,2,3,2,4,2,3,2,3,2,4,2,2,3,3,2,3,2,4,2,2,2,3,2,2,3,3,2,4,2,3,3,3,2,4,2,2,2,4,2,3,2,3,3,2,2,2,2,3,3,3,2,3,3,3,2,2,2,4,2,3,2,3,2,3,2,3,3,3,2,3,2,2,3,2,2,4,2,4,2,2,2,4,2,2,3,3,2,2,2,3,2,2,2,2,2,2,2,4,2,3,2,4,2,2,2,4,2,3,3,3,2,4,2,3,2,3,2,4,2,3,3,3,3,3,2,3,2,3
mov $2,5
lpb $2,1
div $2,2
cal $0,5 ; d(n) (also called tau(n) or sigma_0(n)), the number of divisors of n.
sub $0,1
lpe
mov $1,$0
add $1,1
| 63.166667 | 501 | 0.543536 |
65081c3834a7f3f36aa133a5a0ff1b79faf7670f | 4,040 | asm | Assembly | code/6502/invaders/aliens.asm | visrealm/hbc-56 | 9c082946e247e79edc12867299b5b0fda3b6c873 | [
"MIT"
] | 65 | 2021-07-22T10:32:02.000Z | 2022-03-30T04:42:45.000Z | code/6502/invaders/aliens.asm | visrealm/hbc-56 | 9c082946e247e79edc12867299b5b0fda3b6c873 | [
"MIT"
] | 5 | 2022-03-29T20:23:57.000Z | 2022-03-30T23:12:42.000Z | code/6502/invaders/aliens.asm | visrealm/hbc-56 | 9c082946e247e79edc12867299b5b0fda3b6c873 | [
"MIT"
] | 4 | 2021-12-30T17:13:23.000Z | 2022-03-05T09:07:22.000Z | ; Troy's HBC-56 - 6502 - Invaders - Aliens
;
; Copyright (c) 2021 Troy Schrapel
;
; This code is licensed under the MIT license
;
; https://github.com/visrealm/hbc-56
;
;
INVADER1_TYPE = INVADER1
INVADER2_TYPE = INVADER2
INVADER3_TYPE = INVADER3
INVADER1_PATT = 128
INVADER2_PATT = 136
INVADER3_PATT = 144
; -----------------------------------------------------------------------------
; Aliens setup
; -----------------------------------------------------------------------------
setupAliens:
; setup alien types
lda #<INVADER1_TYPE
sta INV1_BASE_ADDR_L
lda #>INVADER1_TYPE
sta INV1_BASE_ADDR_H
lda #<INVADER2_TYPE
sta INV2_BASE_ADDR_L
lda #>INVADER2_TYPE
sta INV2_BASE_ADDR_H
lda #<INVADER3_TYPE
sta INV3_BASE_ADDR_L
lda #>INVADER3_TYPE
sta INV3_BASE_ADDR_H
; colors
+tmsSetAddrColorTable 16
ldy #INVADER_OFFSET_COLOR
lda (INV1_BASE_ADDR_L), y
+tmsPut
lda (INV2_BASE_ADDR_L), y
+tmsPut
lda (INV3_BASE_ADDR_L), y
+tmsPut
jsr aliensSetTiles0
rts
; -----------------------------------------------------------------------------
; aliensUpdateTileset: Update patterns for a single alien type
; -----------------------------------------------------------------------------
!macro aliensUpdateAlienTileset .patternIndex, .baseAddress, .offset {
+tmsSetAddrPattTableInd .patternIndex
+tmsSetSourceAddressIndOffset .baseAddress, .offset
+tmsSendBytes 16
}
; -----------------------------------------------------------------------------
; aliensUpdateTileset: Update patterns for all aliens
; -----------------------------------------------------------------------------
!macro aliensUpdateTileset .offset {
+aliensUpdateAlienTileset INVADER1_PATT, INV1_BASE_ADDR_L, .offset
+aliensUpdateAlienTileset INVADER2_PATT, INV2_BASE_ADDR_L, .offset
+aliensUpdateAlienTileset INVADER3_PATT, INV3_BASE_ADDR_L, .offset
}
; -----------------------------------------------------------------------------
; alienColor: Get the color for the given alien type
; -----------------------------------------------------------------------------
; Inputs:
; A: tile index
; Outputs:
; A: color
; -----------------------------------------------------------------------------
alien1Color:
lda (INV1_BASE_ADDR_L), y
+lsr4
rts
alien2Color:
lda (INV2_BASE_ADDR_L), y
+lsr4
rts
alien3Color:
lda (INV3_BASE_ADDR_L), y
+lsr4
rts
alienColor:
ldy #INVADER_OFFSET_COLOR
cmp #INVADER2_PATT
bcc alien1Color
cmp #INVADER3_PATT
bcc alien2Color
jmp alien3Color
; -----------------------------------------------------------------------------
; Alien tileset 0: Base offset
; -----------------------------------------------------------------------------
aliensSetTiles0:
+aliensUpdateTileset 0
lda #0
sta INVADER_PIXEL_OFFSET
rts
; -----------------------------------------------------------------------------
; Alien tileset 1: 2px offset
; -----------------------------------------------------------------------------
aliensSetTiles1:
+aliensUpdateTileset INVADER_OFFSET_2
lda #2
sta INVADER_PIXEL_OFFSET
rts
; -----------------------------------------------------------------------------
; Alien tileset 2: 4px offset
; -----------------------------------------------------------------------------
aliensSetTiles2:
+aliensUpdateTileset INVADER_OFFSET_4
lda #4
sta INVADER_PIXEL_OFFSET
rts
; -----------------------------------------------------------------------------
; Alien tileset 3: 6px offset
; -----------------------------------------------------------------------------
aliensSetTiles3:
+aliensUpdateTileset INVADER_OFFSET_6
lda #6
sta INVADER_PIXEL_OFFSET
rts
| 28.251748 | 79 | 0.436881 |
b9ff75033b1a4576063b6e20852bb090e20da327 | 1,101 | asm | Assembly | main.asm | szymbar15/Mario-Kart-DS-ASM-hacks-from-YouTube-Videos | c5362be4b16e8ff279abc09cab6b586248b0d090 | [
"MIT"
] | 1 | 2020-12-07T22:55:47.000Z | 2020-12-07T22:55:47.000Z | main.asm | szymbar15/Mario-Kart-DS-ASM-hacks-from-YouTube-Videos | c5362be4b16e8ff279abc09cab6b586248b0d090 | [
"MIT"
] | null | null | null | main.asm | szymbar15/Mario-Kart-DS-ASM-hacks-from-YouTube-Videos | c5362be4b16e8ff279abc09cab6b586248b0d090 | [
"MIT"
] | null | null | null | .nds
CustomStuffRegion equ 0x21DA340
Offset equ CustomStuffRegion-DefaultCustomDataStart
DefaultCustomDataStart equ 0x21773C0
KartCount equ #0x25
.open "arm9.bin",0x02000000
.thumb
; List of hooks
.org 0x2025EA8
dcd DefaultKartOrder
.org 0x2025E30
dcd MenuKartIDOrder
.org 0x2025E5C
dcd MenuKartIDOrder
; Reading kart_appear longer
.org 0x2025E18
cmp r4, KartCount
; Loading one more character slot
.org 0x2025DDE
CMP R4, KartCount
.org 0x2025E3C
CMP R4, KartCount
.org 0x2025E50
CMP R4, KartCount
; Arrow left
.org 0x202925A
mov R5, KartCount-1
.org 0x202929A
MOV R5, KartCount-1
; Arrow right
.org 0x20292CA
CMP R5, KartCount
.org 0x202930A
CMP R5, KartCount
.org 0x2025DA0
dcd KartNameReferenceList
.arm
.org 0x2071B3C
bl kartSoundsTable
.include "autoloadtableregen.asm"
.close
.open "arm9.bin",0x02000000+Offset
.skip DefaultCustomDataStart-0x2000000
ExtraDataStartingPosition:
.include "defaultkartorder.asm"
.include "menukartidorder.asm"
.include "kartnamereferencelist.asm"
.include "sounds.asm"
LengthOfTheFile:
.close | 15.728571 | 51 | 0.766576 |
2db1c76ebfd399d0288bfec650f67c521ea477a3 | 5,825 | asm | Assembly | Osdk/_final_/sample/floppybuilder/code/sector_2-microdisc.asm | nekoniaow/OSDK | ba6692caba3da0afde67e5709de21aacab8b03b7 | [
"WTFPL",
"Zlib"
] | 5 | 2018-10-31T10:33:44.000Z | 2022-02-28T14:33:52.000Z | Osdk/_final_/sample/floppybuilder/code/sector_2-microdisc.asm | nekoniaow/OSDK | ba6692caba3da0afde67e5709de21aacab8b03b7 | [
"WTFPL",
"Zlib"
] | 2 | 2018-05-15T06:06:14.000Z | 2018-05-17T05:52:59.000Z | Osdk/_final_/sample/floppybuilder/code/sector_2-microdisc.asm | nekoniaow/OSDK | ba6692caba3da0afde67e5709de21aacab8b03b7 | [
"WTFPL",
"Zlib"
] | 1 | 2018-10-31T10:35:20.000Z | 2018-10-31T10:35:20.000Z | ;
; This part of the code is a bit tricky: Basically the Atmos with Microdisc and the Telestrat despite using a similar boot
; loading system are actually loading the boot sector at different addresses.
;
; Since the 6502 is not particularly well equiped to handle code that can be loaded at any address we had to find a trick.
; What we are doing is to make the code run at a particular address, and have a small module that makes sure that it is
; moved at the correct place wherever it was loaded in first place. That makes the code a lot easier to write :)
;
; Warning: This whole code CANNOT be more than 256 bytes (ie: the size of the sector)
;
; The bootloader will be placed in the screen area because we know that this is not going to be used by the operating system.
; By chosing an address in HIRES area, we also guarantee that it will not be visible on the screen (the Oric boots in TEXT).
;
#define FINAL_ADRESS $9800 ; First 256 bytes of the STD charset are invisible
#define OPCODE_RTS $60
#define FDC_command_register $0310
#define FDC_status_register $0310
#define FDC_track_register $0311
#define FDC_sector_register $0312
#define FDC_data $0313
#define FDC_flags $0314
#define FDC_drq $0318
#define FDC_Flag_DiscSide %00010000
#define CMD_ReadSector $80
#define CMD_Seek $1F
#define wait_status_floppy 30
#include "floppy_description.h" ; This file is generated by the floppy builder
.zero
*=$00
retry_counter .dsb 1 ; Number of attempts at loading data (ie: not quite clear what happens when this fails...)
.text
;
; These are the 23 header bytes that goes before the actual executable part of the bootsector
;
.byt $00,$00,$FF,$00,$D0,$9F,$D0,$9F,$02,$B9,$01,$00,$FF,$00,$00,$B9,$E4,$B9,$00,$00,$E6,$12,$00
.text
;
; Here starts the actual executable part, maximum available size is 233 bytes (256-23)
;
;
; Try to find the load address
;
sei ; Disable interruptions
lda #OPCODE_RTS
sta $00 ; Write in $00 Page => take one less byte
jsr $0000 ; JSR on the RTS immediately return.
;
; Compute the absolute address of where the code we want to copy begins,
; and save it in zero page ($00 and $01)
;
_start_relocator_
tsx ; Get stack offset
dex
clc
lda $0100,x ; Get LOW adress byte
adc #<(_end_relocator_-_start_relocator_+1)
sta $00
lda $0101,x ; Get HIGH adress byte
adc #>(_end_relocator_-_start_relocator_+1)
sta $01
; Now $00 and $01 contain the adress of LABEL
; We can now copy the whole code to it's new
; location
ldy #0
copy_loop
lda ($00),y
sta FINAL_ADRESS,y
iny
cpy #(_END_-_BEGIN_)
bne copy_loop
jmp FINAL_ADRESS
_end_relocator_
;
; Here is some code compiled at a fixed adress in memory.
;
*=FINAL_ADRESS
_BEGIN_
;
; Switch to HIRES
;
ldy #39 ; From $9900 to $c000 is 39 pages (9984 bytes)
lda #0
loop_hires_outer
tax
loop_hires_inner
__auto_hires
sta $9900,x
inx
bne loop_hires_inner
inc __auto_hires+2
dey
bne loop_hires_outer
lda #30 ; Write hires switch
sta $bfdf
;
; Read sector data
;
ldy #4
sty retry_counter
read_sectors_loop
readretryloop
nop
nop
nop
read_one_sector
;
; Check if we are on the correct track already and if not
; then send a SEEK command to the FDC to move the head to
; the correct track.
;
ldx #FLOPPY_LOADER_TRACK
cpx FDC_track_register
beq track_ok
; Write the track number in the FDC data register
stx FDC_data
wait_drive2
lda FDC_drq ; We are waiting for the drive maybe not useful if drive is ready after the eprom boot
bmi wait_drive2
;
; Send a SEEK command (change track)
;
lda #CMD_Seek
sta FDC_command_register
;
; Command words should only be loaded in the Command Register when the Busy status bit is off (Status bit 0). The one exception is the Force Interrupt command.
; Whenever a command is being executed, the Busy status bit is set.
; When a command is completed, an interrupt is generated and the busy status bit is reset.
; The Status Register indicates whethter the completed command encountered an error or was fault free. For ease of discussion, commands are divided into four types (I, II, III, IV).
ldy #4
r_wait_completion
dey
bne r_wait_completion
r2_wait_completion
lda FDC_status_register
lsr
bcs r2_wait_completion
asl
track_ok
; Write the sector number in the FDC sector register
__auto__sector_index
lda #FLOPPY_LOADER_SECTOR
sta FDC_sector_register ;
lda #%10000100 ; Force the system to use the Side 0 of the A: drive
sta FDC_flags
;
; Send a READSECTOR command
;
lda #CMD_ReadSector
sta FDC_command_register
ldy #wait_status_floppy
waitcommand
nop ; Not useful but for old Floppy drive maybe
nop ; Not useful but for old Floppy drive maybe
dey
bne waitcommand
;
; Read the sector data
;
ldy #0
fetch_bytes_from_FDC
lda FDC_drq
bmi fetch_bytes_from_FDC
lda FDC_data
__auto_write_address
sta FLOPPY_LOADER_ADDRESS,y
iny
bne fetch_bytes_from_FDC
; Done loading the sector
lda FDC_status_register
and #$1C
beq sector_OK
dec retry_counter
bne readretryloop
sector_OK
inc __auto__sector_index+1
inc __auto_write_address+2
dec sector_counter
bne read_sectors_loop
;
; Data successfully loader (we hope)
;
sei
lda #%10000001 ; Disable the FDC (Eprom select + FDC Interrupt request)
sta FDC_flags
ldx #0 ; 0 = Microdisc initialisation code
jmp FLOPPY_LOADER_ADDRESS
sector_counter .byt (($FFFF-FLOPPY_LOADER_ADDRESS)+1)/256
_END_
| 24.47479 | 183 | 0.698712 |
c4ef12fd53f4374c522a5a0801648fedce25bf25 | 822 | asm | Assembly | oeis/159/A159664.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/159/A159664.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/159/A159664.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A159664: The general form of the recurrences are the a(j), b(j) and n(j) solutions of the 2 equations problem: 11*n(j)+1=a(j)*a(j) and 13*n(j)+1=b(j)*b(j); with positive integer numbers.
; Submitted by Jamie Morken(s4)
; 1,23,551,13201,316273,7577351,181540151,4349386273,104203730401,2496540143351,59812759710023,1433009692897201,34332419869822801,822545067182850023,19706749192518577751,472139435553263016001,11311639704085793806273,271007213462505788334551,6492861483396053126222951,155557668388042769241016273,3726891179829630408658167601,89289830647523087038555006151,2139229044360724458516661980023,51252207234009863917361332514401,1227913744571876009558155318365601,29418677662491014365478366308260023
lpb $0
sub $0,1
mov $1,$3
mul $1,22
add $2,1
add $2,$1
add $3,$2
lpe
mov $0,$3
mul $0,22
add $0,1
| 51.375 | 489 | 0.815085 |
7077573a69df946076a6c2ac918849d2976733f3 | 560 | asm | Assembly | programs/oeis/023/A023002.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/023/A023002.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | programs/oeis/023/A023002.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | ; A023002: Sum of 10th powers.
; 0,1,1025,60074,1108650,10874275,71340451,353815700,1427557524,4914341925,14914341925,40851766526,102769130750,240627622599,529882277575,1106532668200,2206044295976,4222038196425,7792505423049,13923571680850,24163571680850,40843452659051,67403375450475,108829886664124,172233267629500,267600699270125,408767794923501,614658927018150,910855693713574,1331562927013775,1922052927013775,2741681213994576,3867581120837200,5399160106101649,7463537860161425
mov $1,2
lpb $0
mov $2,$0
sub $0,1
pow $2,10
add $1,$2
lpe
sub $1,2
| 46.666667 | 451 | 0.848214 |
53252140952afe11eec57a457cda5f83fdb63251 | 315 | asm | Assembly | programs/oeis/002/A002697.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/002/A002697.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/002/A002697.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A002697: a(n) = n*4^(n-1).
; 0,1,8,48,256,1280,6144,28672,131072,589824,2621440,11534336,50331648,218103808,939524096,4026531840,17179869184,73014444032,309237645312,1305670057984,5497558138880,23089744183296,96757023244288,404620279021568,1688849860263936,7036874417766400
mov $1,4
pow $1,$0
mul $1,$0
div $1,4
| 39.375 | 246 | 0.8 |
1505fce3b52fa55c8cf8fbdc2d8c4f8d9293bd85 | 217 | asm | Assembly | src/cesplib_rars.asm | tina-hoeflich/pong | 2420f504c323582e7f0bf6f51753d062a0674c92 | [
"MIT"
] | null | null | null | src/cesplib_rars.asm | tina-hoeflich/pong | 2420f504c323582e7f0bf6f51753d062a0674c92 | [
"MIT"
] | null | null | null | src/cesplib_rars.asm | tina-hoeflich/pong | 2420f504c323582e7f0bf6f51753d062a0674c92 | [
"MIT"
] | null | null | null | .data
.eqv DISPLAY_ADDRESS 0x10010000
.eqv DISPLAY_WIDTH 256
.eqv DISPLAY_HEIGHT 128
.eqv KEYBOARD_ADDDRESS 0xFFFF0000
#cesp_sleep:
# Input:
# a0: number of ms to sleep
#li a7, 32
#ecall
#ret
#cesplib.end:
| 13.5625 | 33 | 0.732719 |
7ac8ec8033005e8da58e3ec43237d29086838e4d | 701 | asm | Assembly | oeis/271/A271512.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/271/A271512.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/271/A271512.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A271512: a(n) = (p+1)*(p+2)*(p+3)/6 where p is the n-th prime.
; Submitted by Jon Maiga
; 10,20,56,120,364,560,1140,1540,2600,4960,5984,9880,13244,15180,19600,27720,37820,41664,54740,64824,70300,88560,102340,125580,161700,182104,192920,215820,227920,253460,357760,392084,447580,467180,573800,596904,669920,748660,804440,893200,988260,1021384,1198144,1235780,1313400,1353400,1610564,1898400,2001460,2054360,2162940,2332880,2391444,2699004,2895620,3101560,3317040,3391024,3619560,3777484,3858140,4278680,4917220,5110664,5209260,5410240,6154284,6492980,7084700,7207200,7456420,7840920,8373840
seq $0,40 ; The prime numbers.
mov $2,$0
add $2,2
pow $2,3
sub $2,$0
mov $0,$2
sub $0,62
div $0,6
add $0,10
| 50.071429 | 501 | 0.776034 |
20c3277a2695e25742b861c9d4bfb07a466a728b | 9,536 | asm | Assembly | contrib/SDL-1.2.15/src/hermes/mmxp2_32.asm | CronosTs/phobos3d | c0336456d946f3a9e62fb9b7815831ad32820da5 | [
"Zlib"
] | 33 | 2020-11-20T16:38:43.000Z | 2021-10-17T04:21:44.000Z | contrib/SDL-1.2.15/src/hermes/mmxp2_32.asm | CronosTs/phobos3d | c0336456d946f3a9e62fb9b7815831ad32820da5 | [
"Zlib"
] | 2 | 2020-11-21T00:32:37.000Z | 2020-11-23T17:38:26.000Z | contrib/SDL-1.2.15/src/hermes/mmxp2_32.asm | CronosTs/phobos3d | c0336456d946f3a9e62fb9b7815831ad32820da5 | [
"Zlib"
] | 5 | 2017-09-29T04:02:20.000Z | 2022-03-18T01:08:05.000Z | ;
; pII-optimised MMX format converters for HERMES
; Copyright (c) 1998 Christian Nentwich (c.nentwich@cs.ucl.ac.uk)
; and (c) 1999 Jonathan Matthew (jmatthew@uq.net.au)
; This source code is licensed under the GNU LGPL
;
; Please refer to the file COPYING.LIB contained in the distribution for
; licensing conditions
;
; COPYRIGHT NOTICE
;
; This file partly contains code that is (c) Intel Corporation, specifically
; the mode detection routine, and the converter to 15 bit (8 pixel
; conversion routine from the mmx programming tutorial pages).
;
;
; These routines aren't exactly pII optimised - it's just that as they
; are, they're terrible on p5 MMXs, but less so on pIIs. Someone needs to
; optimise them for p5 MMXs..
BITS 32
%include "common.inc"
SDL_FUNC _ConvertMMXpII32_24RGB888
SDL_FUNC _ConvertMMXpII32_16RGB565
SDL_FUNC _ConvertMMXpII32_16BGR565
SDL_FUNC _ConvertMMXpII32_16RGB555
SDL_FUNC _ConvertMMXpII32_16BGR555
;; Macros for conversion routines
%macro _push_immq_mask 1
push dword %1
push dword %1
%endmacro
%macro load_immq 2
_push_immq_mask %2
movq %1, [esp]
%endmacro
%macro pand_immq 2
_push_immq_mask %2
pand %1, [esp]
%endmacro
%define CLEANUP_IMMQ_LOADS(num) \
add esp, byte 8 * num
%define mmx32_rgb888_mask 00ffffffh
%define mmx32_rgb565_b 000000f8h
%define mmx32_rgb565_g 0000fc00h
%define mmx32_rgb565_r 00f80000h
%define mmx32_rgb555_rb 00f800f8h
%define mmx32_rgb555_g 0000f800h
%define mmx32_rgb555_mul 20000008h
%define mmx32_bgr555_mul 00082000h
SECTION .text
_ConvertMMXpII32_24RGB888:
; set up mm6 as the mask, mm7 as zero
load_immq mm6, mmx32_rgb888_mask
CLEANUP_IMMQ_LOADS(1)
pxor mm7, mm7
mov edx, ecx ; save ecx
and ecx, 0fffffffch ; clear lower two bits
jnz .L1
jmp .L2
.L1:
movq mm0, [esi] ; A R G B a r g b
pand mm0, mm6 ; 0 R G B 0 r g b
movq mm1, [esi+8] ; A R G B a r g b
pand mm1, mm6 ; 0 R G B 0 r g b
movq mm2, mm0 ; 0 R G B 0 r g b
punpckhdq mm2, mm7 ; 0 0 0 0 0 R G B
punpckldq mm0, mm7 ; 0 0 0 0 0 r g b
psllq mm2, 24 ; 0 0 R G B 0 0 0
por mm0, mm2 ; 0 0 R G B r g b
movq mm3, mm1 ; 0 R G B 0 r g b
psllq mm3, 48 ; g b 0 0 0 0 0 0
por mm0, mm3 ; g b R G B r g b
movq mm4, mm1 ; 0 R G B 0 r g b
punpckhdq mm4, mm7 ; 0 0 0 0 0 R G B
punpckldq mm1, mm7 ; 0 0 0 0 0 r g b
psrlq mm1, 16 ; 0 0 0 R G B 0 r
psllq mm4, 8 ; 0 0 0 0 R G B 0
por mm1, mm4 ; 0 0 0 0 R G B r
movq [edi], mm0
add esi, BYTE 16
movd [edi+8], mm1
add edi, BYTE 12
sub ecx, BYTE 4
jnz .L1
.L2:
mov ecx, edx
and ecx, BYTE 3
jz .L4
.L3:
mov al, [esi]
mov bl, [esi+1]
mov dl, [esi+2]
mov [edi], al
mov [edi+1], bl
mov [edi+2], dl
add esi, BYTE 4
add edi, BYTE 3
dec ecx
jnz .L3
.L4:
retn
_ConvertMMXpII32_16RGB565:
; set up masks
load_immq mm5, mmx32_rgb565_b
load_immq mm6, mmx32_rgb565_g
load_immq mm7, mmx32_rgb565_r
CLEANUP_IMMQ_LOADS(3)
mov edx, ecx
shr ecx, 2
jnz .L1
jmp .L2 ; not necessary at the moment, but doesn't hurt (much)
.L1:
movq mm0, [esi] ; argb
movq mm1, mm0 ; argb
pand mm0, mm6 ; 00g0
movq mm3, mm1 ; argb
pand mm1, mm5 ; 000b
pand mm3, mm7 ; 0r00
pslld mm1, 2 ; 0 0 000000bb bbb00000
por mm0, mm1 ; 0 0 ggggggbb bbb00000
psrld mm0, 5 ; 0 0 00000ggg gggbbbbb
movq mm4, [esi+8] ; argb
movq mm2, mm4 ; argb
pand mm4, mm6 ; 00g0
movq mm1, mm2 ; argb
pand mm2, mm5 ; 000b
pand mm1, mm7 ; 0r00
pslld mm2, 2 ; 0 0 000000bb bbb00000
por mm4, mm2 ; 0 0 ggggggbb bbb00000
psrld mm4, 5 ; 0 0 00000ggg gggbbbbb
packuswb mm3, mm1 ; R 0 r 0
packssdw mm0, mm4 ; as above.. ish
por mm0, mm3 ; done.
movq [edi], mm0
add esi, 16
add edi, 8
dec ecx
jnz .L1
.L2:
mov ecx, edx
and ecx, BYTE 3
jz .L4
.L3:
mov al, [esi]
mov bh, [esi+1]
mov ah, [esi+2]
shr al, 3
and eax, 0F81Fh ; BYTE?
shr ebx, 5
and ebx, 07E0h ; BYTE?
add eax, ebx
mov [edi], al
mov [edi+1], ah
add esi, BYTE 4
add edi, BYTE 2
dec ecx
jnz .L3
.L4:
retn
_ConvertMMXpII32_16BGR565:
load_immq mm5, mmx32_rgb565_r
load_immq mm6, mmx32_rgb565_g
load_immq mm7, mmx32_rgb565_b
CLEANUP_IMMQ_LOADS(3)
mov edx, ecx
shr ecx, 2
jnz .L1
jmp .L2
.L1:
movq mm0, [esi] ; a r g b
movq mm1, mm0 ; a r g b
pand mm0, mm6 ; 0 0 g 0
movq mm3, mm1 ; a r g b
pand mm1, mm5 ; 0 r 0 0
pand mm3, mm7 ; 0 0 0 b
psllq mm3, 16 ; 0 b 0 0
psrld mm1, 14 ; 0 0 000000rr rrr00000
por mm0, mm1 ; 0 0 ggggggrr rrr00000
psrld mm0, 5 ; 0 0 00000ggg gggrrrrr
movq mm4, [esi+8] ; a r g b
movq mm2, mm4 ; a r g b
pand mm4, mm6 ; 0 0 g 0
movq mm1, mm2 ; a r g b
pand mm2, mm5 ; 0 r 0 0
pand mm1, mm7 ; 0 0 0 b
psllq mm1, 16 ; 0 b 0 0
psrld mm2, 14 ; 0 0 000000rr rrr00000
por mm4, mm2 ; 0 0 ggggggrr rrr00000
psrld mm4, 5 ; 0 0 00000ggg gggrrrrr
packuswb mm3, mm1 ; BBBBB000 00000000 bbbbb000 00000000
packssdw mm0, mm4 ; 00000GGG GGGRRRRR 00000GGG GGGRRRRR
por mm0, mm3 ; BBBBBGGG GGGRRRRR bbbbbggg gggrrrrr
movq [edi], mm0
add esi, BYTE 16
add edi, BYTE 8
dec ecx
jnz .L1
.L2:
and edx, BYTE 3
jz .L4
.L3:
mov al, [esi+2]
mov bh, [esi+1]
mov ah, [esi]
shr al, 3
and eax, 0F81Fh ; BYTE ?
shr ebx, 5
and ebx, 07E0h ; BYTE ?
add eax, ebx
mov [edi], al
mov [edi+1], ah
add esi, BYTE 4
add edi, BYTE 2
dec edx
jnz .L3
.L4:
retn
_ConvertMMXpII32_16BGR555:
; the 16BGR555 converter is identical to the RGB555 one,
; except it uses a different multiplier for the pmaddwd
; instruction. cool huh.
load_immq mm7, mmx32_bgr555_mul
jmp _convert_bgr555_cheat
; This is the same as the Intel version.. they obviously went to
; much more trouble to expand/coil the loop than I did, so theirs
; would almost certainly be faster, even if only a little.
; I did rename 'mmx32_rgb555_add' to 'mmx32_rgb555_mul', which is
; (I think) a more accurate name..
_ConvertMMXpII32_16RGB555:
load_immq mm7, mmx32_rgb555_mul
_convert_bgr555_cheat:
load_immq mm6, mmx32_rgb555_g
CLEANUP_IMMQ_LOADS(2)
mov edx,ecx ; Save ecx
and ecx,DWORD 0fffffff8h ; clear lower three bits
jnz .L_OK
jmp near .L2
.L_OK:
movq mm2,[esi+8]
movq mm0,[esi]
movq mm3,mm2
pand_immq mm3, mmx32_rgb555_rb
movq mm1,mm0
pand_immq mm1, mmx32_rgb555_rb
pmaddwd mm3,mm7
CLEANUP_IMMQ_LOADS(2)
pmaddwd mm1,mm7
pand mm2,mm6
.L1:
movq mm4,[esi+24]
pand mm0,mm6
movq mm5,[esi+16]
por mm3,mm2
psrld mm3,6
por mm1,mm0
movq mm0,mm4
psrld mm1,6
pand_immq mm0, mmx32_rgb555_rb
packssdw mm1,mm3
movq mm3,mm5
pmaddwd mm0,mm7
pand_immq mm3, mmx32_rgb555_rb
pand mm4,mm6
movq [edi],mm1
pmaddwd mm3,mm7
add esi,BYTE 32
por mm4,mm0
pand mm5,mm6
psrld mm4,6
movq mm2,[esi+8]
por mm5,mm3
movq mm0,[esi]
psrld mm5,6
movq mm3,mm2
movq mm1,mm0
pand_immq mm3, mmx32_rgb555_rb
packssdw mm5,mm4
pand_immq mm1, mmx32_rgb555_rb
pand mm2,mm6
CLEANUP_IMMQ_LOADS(4)
movq [edi+8],mm5
pmaddwd mm3,mm7
pmaddwd mm1,mm7
add edi,BYTE 16
sub ecx,BYTE 8
jz .L2
jmp .L1
.L2:
mov ecx,edx
and ecx,BYTE 7
jz .L4
.L3:
mov ebx,[esi]
add esi,BYTE 4
mov eax,ebx
mov edx,ebx
shr eax,3
shr edx,6
and eax,BYTE 0000000000011111b
and edx, 0000001111100000b
shr ebx,9
or eax,edx
and ebx, 0111110000000000b
or eax,ebx
mov [edi],ax
add edi,BYTE 2
dec ecx
jnz .L3
.L4:
retn
%ifidn __OUTPUT_FORMAT__,elf32
section .note.GNU-stack noalloc noexec nowrite progbits
%endif
| 23.487685 | 78 | 0.527265 |
69c7a18ed93e6105ef018c1ef9a75ed33225e04e | 6,180 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_sm_/i7-8650U_0xd2.log_2506_1365.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_sm_/i7-8650U_0xd2.log_2506_1365.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_sm_/i7-8650U_0xd2.log_2506_1365.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r14
push %r15
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x1c9f2, %rsi
lea addresses_WC_ht+0x3f2, %rdi
nop
nop
nop
xor $26166, %r11
mov $90, %rcx
rep movsw
dec %r11
lea addresses_D_ht+0x103f2, %r15
nop
nop
nop
nop
cmp %rsi, %rsi
mov $0x6162636465666768, %rcx
movq %rcx, (%r15)
nop
nop
nop
sub %r15, %r15
lea addresses_D_ht+0x193f2, %r14
nop
nop
nop
nop
and $61272, %r10
movw $0x6162, (%r14)
nop
nop
nop
xor $9048, %r10
lea addresses_WC_ht+0x19172, %rsi
lea addresses_WC_ht+0x1a7f2, %rdi
clflush (%rdi)
nop
mfence
mov $80, %rcx
rep movsl
nop
nop
nop
nop
nop
and $3642, %r14
pop %rsi
pop %rdi
pop %rcx
pop %r15
pop %r14
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r12
push %r15
push %rbp
push %rbx
push %rcx
push %rdi
// Store
lea addresses_normal+0xe7f2, %rcx
nop
nop
nop
nop
nop
cmp $53346, %rdi
movw $0x5152, (%rcx)
xor $13550, %r10
// Store
lea addresses_WT+0x6172, %rdi
nop
nop
nop
nop
and $26966, %rbp
movb $0x51, (%rdi)
nop
nop
nop
cmp %rdi, %rdi
// Store
lea addresses_UC+0x1bf2, %r12
nop
nop
nop
nop
nop
and %rdi, %rdi
movl $0x51525354, (%r12)
nop
nop
xor $41473, %rdi
// Load
lea addresses_WC+0x188b2, %r12
nop
and $47899, %rbp
mov (%r12), %bx
nop
sub $7499, %r12
// Store
lea addresses_RW+0x196e, %rbp
clflush (%rbp)
nop
nop
nop
nop
nop
add $65229, %rcx
mov $0x5152535455565758, %r15
movq %r15, %xmm1
vmovups %ymm1, (%rbp)
nop
nop
sub $17517, %rcx
// Faulty Load
lea addresses_UC+0x1bf2, %r15
add $31825, %rbx
mov (%r15), %r10w
lea oracles, %rcx
and $0xff, %r10
shlq $12, %r10
mov (%rcx,%r10,1), %r10
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r15
pop %r12
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_UC', 'size': 8, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT', 'size': 1, 'AVXalign': False, 'NT': True, 'congruent': 7, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WC', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 6, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_RW', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 1, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_UC', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'type': 'addresses_D_ht', 'congruent': 8, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 11, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'size': 8, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 11, 'same': True}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 4, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 10, 'same': False}}
{'54': 2506}
54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54
*/
| 36.140351 | 2,999 | 0.656472 |
aaaea7835b571994830d7c664b5b0e0287e84fd2 | 55,331 | asm | Assembly | src/x86/looprestoration_ssse3.asm | myarchsource/dav1d | ae3b6b26def1da5a017f6a19e6dd4ce8dc7197ea | [
"BSD-2-Clause"
] | null | null | null | src/x86/looprestoration_ssse3.asm | myarchsource/dav1d | ae3b6b26def1da5a017f6a19e6dd4ce8dc7197ea | [
"BSD-2-Clause"
] | null | null | null | src/x86/looprestoration_ssse3.asm | myarchsource/dav1d | ae3b6b26def1da5a017f6a19e6dd4ce8dc7197ea | [
"BSD-2-Clause"
] | null | null | null | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2018, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
%include "ext/x86/x86inc.asm"
SECTION_RODATA 16
pb_right_ext_mask: times 16 db 0xff
times 16 db 0
pb_14x0_1_2: times 14 db 0
db 1, 2
pb_0_to_15_min_n: db 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 13
db 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14
pb_unpcklwdw: db 0, 1, 0, 1, 4, 5, 4, 5, 8, 9, 8, 9, 12, 13, 12, 13
pb_0: times 16 db 0
pb_2: times 16 db 2
pb_3: times 16 db 3
pb_4: times 16 db 4
pb_15: times 16 db 15
pb_0_1: times 8 db 0, 1
pb_6_7: times 8 db 6, 7
pb_14_15: times 8 db 14, 15
pw_1: times 8 dw 1
pw_16: times 8 dw 16
pw_128: times 8 dw 128
pw_255: times 8 dw 255
pw_256: times 8 dw 256
pw_2048: times 8 dw 2048
pw_16380: times 8 dw 16380
pw_5_6: times 4 dw 5, 6
pw_0_128: times 4 dw 0, 128
pd_1024: times 4 dd 1024
%if ARCH_X86_32
pd_256: times 4 dd 256
pd_512: times 4 dd 512
pd_2048: times 4 dd 2048
%endif
pd_0xF0080029: times 4 dd 0xF0080029
pd_0xF00801C7: times 4 dd 0XF00801C7
cextern sgr_x_by_x
SECTION .text
%if ARCH_X86_32
%define PIC_base_offset $$
%macro SETUP_PIC 1-3 1,0 ; PIC_reg, save_PIC_reg, restore_PIC_reg
%assign pic_reg_stk_off 4
%xdefine PIC_reg %1
%if %2 == 1
mov [esp], %1
%endif
LEA PIC_reg, PIC_base_offset
%if %3 == 1
XCHG_PIC_REG
%endif
%endmacro
%macro XCHG_PIC_REG 0
mov [esp+pic_reg_stk_off], PIC_reg
%assign pic_reg_stk_off (pic_reg_stk_off+4) % 8
mov PIC_reg, [esp+pic_reg_stk_off]
%endmacro
%define PIC_sym(sym) (PIC_reg+(sym)-PIC_base_offset)
%else
%macro XCHG_PIC_REG 0
%endmacro
%define PIC_sym(sym) (sym)
%endif
%macro PALIGNR 4 ; dst, src1, src2, shift
%if cpuflag(ssse3)
palignr %1, %2, %3, %4
%else
%assign %%i regnumof%+%1 + 1
%define %%tmp m %+ %%i
psrldq %1, %3, %4
pslldq %%tmp, %2, 16-%4
por %1, %%tmp
%endif
%endmacro
%macro PMADDUBSW 5 ; dst, src, zero, tmp, reset_zero
%if cpuflag(ssse3)
pmaddubsw %1, %2
%else
%if %5 == 1
pxor %3, %3
%endif
punpckhbw %4, %1, %3
punpcklbw %1, %3
pmaddwd %4, %2
pmaddwd %1, %2
packssdw %1, %4
%endif
%endmacro
;;;;;;;;;;;;;;;;;;;;;;
;; wiener ;;
;;;;;;;;;;;;;;;;;;;;;;
%macro WIENER_H 0
%if ARCH_X86_64
cglobal wiener_filter_h, 5, 15, 16, dst, left, src, stride, fh, w, h, edge
mov edged, edgem
movifnidn wd, wm
mov hd, hm
%else
cglobal wiener_filter_h, 5, 7, 8, -84, dst, left, src, stride, fh, w, h, edge
mov r5, edgem
mov [esp+12], r5
mov wd, wm
mov hd, hm
SETUP_PIC hd
%define m15 m0
%define m14 m1
%define m13 m2
%define m12 m3
%endif
movq m15, [fhq]
%if cpuflag(ssse3)
pshufb m12, m15, [PIC_sym(pb_6_7)]
pshufb m13, m15, [PIC_sym(pb_4)]
pshufb m14, m15, [PIC_sym(pb_2)]
pshufb m15, m15, [PIC_sym(pb_0)]
%else
pshuflw m12, m15, q3333
punpcklbw m15, m15
pshufhw m13, m15, q0000
pshuflw m14, m15, q2222
pshuflw m15, m15, q0000
punpcklqdq m12, m12
punpckhqdq m13, m13
punpcklqdq m14, m14
punpcklqdq m15, m15
psraw m13, 8
psraw m14, 8
psraw m15, 8
%endif
%if ARCH_X86_64
mova m11, [pw_2048]
mova m10, [pw_16380]
lea r11, [pb_right_ext_mask]
DEFINE_ARGS dst, left, src, stride, x, w, h, edge, srcptr, dstptr, xlim
%else
%define m10 [PIC_sym(pw_16380)]
%define m11 [PIC_sym(pw_2048)]
%define m12 [esp+0x14]
%define m13 [esp+0x24]
%define m14 [esp+0x34]
%define m15 [esp+0x44]
mova m12, m3
mova m13, m2
mova m14, m1
mova m15, m0
DEFINE_ARGS dst, left, src, stride, x, w, h, edge
%define srcptrq srcq
%define dstptrq dstq
%define hd dword [esp+ 0]
%define edgeb byte [esp+12]
%define xlimd dword [esp+16]
%endif
; if (edge & has_right) align_w_to_16
; else w -= 3, and use that as limit in x loop
test edgeb, 2 ; has_right
jnz .align
mov xlimd, -3
jmp .loop
.align:
add wd, 15
and wd, ~15
%if ARCH_X86_64
xor xlimd, xlimd
%else
mov xlimd, 0
%endif
; main y loop for vertical filter
.loop:
%if ARCH_X86_64
mov srcptrq, srcq
mov dstptrq, dstq
lea xd, [wq+xlimq]
%else
mov [esp+8], srcq
mov [esp+4], dstq
mov xd, xlimd
add xd, wd
%endif
; load left edge pixels
test edgeb, 1 ; have_left
jz .emu_left
test leftq, leftq ; left == NULL for the edge-extended bottom/top
jz .load_left_combined
movd m0, [leftq]
movd m1, [srcq]
punpckldq m0, m1
pslldq m0, 9
add leftq, 4
jmp .left_load_done
.load_left_combined:
movq m0, [srcq-3]
pslldq m0, 10
jmp .left_load_done
.emu_left:
movd m0, [srcq]
%if cpuflag(ssse3)
pshufb m0, [PIC_sym(pb_14x0_1_2)]
%else
pslldq m1, m0, 13
punpcklbw m0, m0
pshuflw m0, m0, q0000
punpcklqdq m0, m0
psrldq m0, 2
por m0, m1
%endif
; load right edge pixels
.left_load_done:
cmp xd, 16
jg .main_load
test xd, xd
jg .load_and_splat
je .splat_right
; for very small images (w=[1-2]), edge-extend the original cache,
; ugly, but only runs in very odd cases
%if cpuflag(ssse3)
add wd, wd
%if ARCH_X86_64
pshufb m0, [r11-pb_right_ext_mask+pb_0_to_15_min_n+wq*8-16]
%else
pshufb m0, [PIC_sym(pb_0_to_15_min_n)+wq*8-16]
%endif
shr wd, 1
%else
shl wd, 4
pcmpeqd m2, m2
movd m3, wd
psrldq m2, 2
punpckhbw m1, m0, m0
pshufhw m1, m1, q1122
psllq m1, m3
pand m0, m2
pandn m2, m1
por m0, m2
shr wd, 4
%endif
; main x loop, mostly this starts in .main_load
.splat_right:
; no need to load new pixels, just extend them from the (possibly previously
; extended) previous load into m0
%if cpuflag(ssse3)
pshufb m1, m0, [PIC_sym(pb_15)]
%else
punpckhbw m1, m0, m0
pshufhw m1, m1, q3333
punpckhqdq m1, m1
%endif
jmp .main_loop
.load_and_splat:
; load new pixels and extend edge for right-most
movu m1, [srcptrq+3]
%if ARCH_X86_64
sub r11, xq
movu m2, [r11+16]
add r11, xq
%else
sub PIC_reg, xd
movu m2, [PIC_sym(pb_right_ext_mask)+16]
add PIC_reg, xd
%endif
movd m3, [srcptrq+2+xq]
%if cpuflag(ssse3)
pshufb m3, [PIC_sym(pb_0)]
%else
punpcklbw m3, m3
pshuflw m3, m3, q0000
punpcklqdq m3, m3
%endif
pand m1, m2
pxor m2, [PIC_sym(pb_right_ext_mask)]
pand m3, m2
pxor m2, [PIC_sym(pb_right_ext_mask)]
por m1, m3
jmp .main_loop
.main_load:
; load subsequent line
movu m1, [srcptrq+3]
.main_loop:
%if ARCH_X86_64
PALIGNR m2, m1, m0, 10
PALIGNR m3, m1, m0, 11
PALIGNR m4, m1, m0, 12
PALIGNR m5, m1, m0, 13
PALIGNR m6, m1, m0, 14
PALIGNR m7, m1, m0, 15
punpcklbw m0, m2, m1
punpckhbw m2, m1
punpcklbw m8, m3, m7
punpckhbw m3, m7
punpcklbw m7, m4, m6
punpckhbw m4, m6
PMADDUBSW m0, m15, m6, m9, 1
PMADDUBSW m2, m15, m6, m9, 0
PMADDUBSW m8, m14, m6, m9, 0
PMADDUBSW m3, m14, m6, m9, 0
PMADDUBSW m7, m13, m6, m9, 0
PMADDUBSW m4, m13, m6, m9, 0
paddw m0, m8
paddw m2, m3
%if cpuflag(ssse3)
pxor m6, m6
%endif
punpcklbw m3, m5, m6
punpckhbw m5, m6
psllw m8, m3, 7
psllw m6, m5, 7
psubw m8, m10
psubw m6, m10
pmullw m3, m12
pmullw m5, m12
paddw m0, m7
paddw m2, m4
paddw m0, m3
paddw m2, m5
paddsw m0, m8 ; see the avx2 for an explanation
paddsw m2, m6 ; of how the clipping works here
psraw m0, 3
psraw m2, 3
paddw m0, m11
paddw m2, m11
mova [dstptrq+ 0], m0
mova [dstptrq+16], m2
%else
PALIGNR m2, m1, m0, 10
punpcklbw m3, m2, m1
punpckhbw m2, m1
PMADDUBSW m3, m15, m4, m5, 1
PMADDUBSW m2, m15, m4, m5, 0
PALIGNR m4, m1, m0, 11
PALIGNR m5, m1, m0, 15
punpcklbw m6, m4, m5
punpckhbw m4, m5
PMADDUBSW m6, m14, m5, m7, 1
PMADDUBSW m4, m14, m5, m7, 0
paddw m3, m6
paddw m2, m4
PALIGNR m4, m1, m0, 12
PALIGNR m5, m1, m0, 14
punpcklbw m6, m4, m5
punpckhbw m4, m5
PMADDUBSW m6, m13, m5, m7, 1
PMADDUBSW m4, m13, m5, m7, 0
paddw m3, m6
paddw m2, m4
PALIGNR m6, m1, m0, 13
%if cpuflag(ssse3)
pxor m5, m5
%endif
punpcklbw m4, m6, m5
punpckhbw m6, m5
psllw m5, m4, 7
psllw m7, m6, 7
psubw m5, m10
psubw m7, m10
pmullw m4, m12
pmullw m6, m12
paddw m3, m4
paddw m2, m6
paddsw m3, m5
paddsw m2, m7
psraw m3, 3
psraw m2, 3
paddw m3, m11
paddw m2, m11
mova [dstptrq+ 0], m3
mova [dstptrq+16], m2
%endif
mova m0, m1
add srcptrq, 16
add dstptrq, 32
sub xd, 16
cmp xd, 16
jg .main_load
test xd, xd
jg .load_and_splat
cmp xd, xlimd
jg .splat_right
%if ARCH_X86_32
mov srcq, [esp+8]
mov dstq, [esp+4]
%endif
add srcq, strideq
add dstq, 384*2
dec hd
jg .loop
RET
%endmacro
%macro WIENER_V 0
%if ARCH_X86_64
cglobal wiener_filter_v, 4, 10, 16, dst, stride, mid, w, h, fv, edge
mov edged, edgem
movifnidn fvq, fvmp
movifnidn hd, hm
movq m15, [fvq]
pshufd m14, m15, q1111
pshufd m15, m15, q0000
paddw m14, [pw_0_128]
mova m12, [pd_1024]
DEFINE_ARGS dst, stride, mid, w, h, y, edge, ylim, mptr, dstptr
mov ylimd, edged
and ylimd, 8 ; have_bottom
shr ylimd, 2
sub ylimd, 3
%else
cglobal wiener_filter_v, 5, 7, 8, -96, dst, stride, mid, w, h, fv, edge
%define ylimd [esp+12]
mov r5d, edgem
and r5d, 8
shr r5d, 2
sub r5d, 3
mov ylimd, r5d
mov fvq, fvmp
mov edged, edgem
SETUP_PIC edged
movq m0, [fvq]
pshufd m1, m0, q1111
pshufd m0, m0, q0000
paddw m1, [PIC_sym(pw_0_128)]
mova [esp+0x50], m0
mova [esp+0x40], m1
DEFINE_ARGS dst, stride, mid, w, h, y, edge
%define mptrq midq
%define dstptrq dstq
%define edgeb byte [esp]
%endif
; main x loop for vertical filter, does one column of 16 pixels
.loop_x:
mova m3, [midq] ; middle line
; load top pixels
test edgeb, 4 ; have_top
jz .emu_top
mova m0, [midq-384*4]
mova m2, [midq-384*2]
mova m1, m0
jmp .load_bottom_pixels
.emu_top:
mova m0, m3
mova m1, m3
mova m2, m3
; load bottom pixels
.load_bottom_pixels:
mov yd, hd
%if ARCH_X86_64
mov mptrq, midq
mov dstptrq, dstq
add yd, ylimd
%else
mov [esp+8], midq
mov [esp+4], dstq
add yd, ylimd
%endif
jg .load_threelines
; the remainder here is somewhat messy but only runs in very weird
; circumstances at the bottom of the image in very small blocks (h=[1-3]),
; so performance is not terribly important here...
je .load_twolines
cmp yd, -1
je .load_oneline
; h == 1 case
mova m5, m3
mova m4, m3
mova m6, m3
jmp .loop
.load_oneline:
; h == 2 case
mova m4, [midq+384*2]
mova m5, m4
mova m6, m4
jmp .loop
.load_twolines:
; h == 3 case
mova m4, [midq+384*2]
mova m5, [midq+384*4]
mova m6, m5
jmp .loop
.load_threelines:
; h > 3 case
mova m4, [midq+384*2]
mova m5, [midq+384*4]
; third line loaded in main loop below
; main y loop for vertical filter
.loop_load:
; load one line into m6. if that pixel is no longer available, do
; nothing, since m6 still has the data from the previous line in it. We
; try to structure the loop so that the common case is evaluated fastest
mova m6, [mptrq+384*6]
.loop:
%if ARCH_X86_64
paddw m7, m0, m6
paddw m8, m1, m5
paddw m9, m2, m4
punpcklwd m10, m7, m8
punpckhwd m7, m8
punpcklwd m11, m9, m3
punpckhwd m9, m3
pmaddwd m10, m15
pmaddwd m7, m15
pmaddwd m11, m14
pmaddwd m9, m14
paddd m10, m12
paddd m7, m12
paddd m10, m11
paddd m7, m9
psrad m10, 11
psrad m7, 11
packssdw m10, m7
packuswb m10, m10
movq [dstptrq], m10
%else
mova [esp+0x30], m1
mova [esp+0x20], m2
mova [esp+0x10], m3
paddw m0, m6
paddw m1, m5
paddw m2, m4
punpcklwd m7, m2, m3
punpckhwd m2, m3
punpcklwd m3, m0, m1
punpckhwd m0, m1
mova m1, [esp+0x50]
pmaddwd m3, m1
pmaddwd m0, m1
mova m1, [esp+0x40]
pmaddwd m7, m1
pmaddwd m2, m1
paddd m3, [PIC_sym(pd_1024)]
paddd m0, [PIC_sym(pd_1024)]
paddd m3, m7
paddd m0, m2
psrad m3, 11
psrad m0, 11
packssdw m3, m0
packuswb m3, m3
movq [dstq], m3
mova m1, [esp+0x30]
mova m2, [esp+0x20]
mova m3, [esp+0x10]
%endif
; shift pixels one position
mova m0, m1
mova m1, m2
mova m2, m3
mova m3, m4
mova m4, m5
mova m5, m6
add mptrq, 384*2
add dstptrq, strideq
dec yd
jg .loop_load
; for the bottom pixels, continue using m6 (as extended edge)
cmp yd, ylimd
jg .loop
%if ARCH_X86_32
mov midq, [esp+8]
mov dstq, [esp+4]
%endif
add midq, 16
add dstq, 8
sub wd, 8
jg .loop_x
RET
%endmacro
INIT_XMM sse2
WIENER_H
WIENER_V
INIT_XMM ssse3
WIENER_H
WIENER_V
;;;;;;;;;;;;;;;;;;;;;;;;;;
;; self-guided ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;
%macro MULLD 2
pmulhuw m5, %1, %2
pmullw %1, %2
pslld m5, 16
paddd %1, m5
%endmacro
%macro GATHERDD 2
mova m5, m7
movd r6d, %2
%if ARCH_X86_64
movd %1, [r5+r6]
pextrw r6d, %2, 2
pinsrw m5, [r5+r6+2], 3
pextrw r6d, %2, 4
pinsrw %1, [r5+r6+2], 5
pextrw r6d, %2, 6
pinsrw m5, [r5+r6+2], 7
%else
movd %1, [PIC_sym(sgr_x_by_x-0xF03)+r6]
pextrw r6d, %2, 2
pinsrw m5, [PIC_sym(sgr_x_by_x-0xF03)+r6+2], 3
pextrw r6d, %2, 4
pinsrw %1, [PIC_sym(sgr_x_by_x-0xF03)+r6+2], 5
pextrw r6d, %2, 6
pinsrw m5, [PIC_sym(sgr_x_by_x-0xF03)+r6+2], 7
%endif
por %1, m5
%endmacro
%if ARCH_X86_64
cglobal sgr_box3_h, 5, 11, 8, sumsq, sum, left, src, stride, x, h, edge, w, xlim
mov xlimd, edgem
movifnidn xd, xm
mov hd, hm
mov edged, xlimd
and xlimd, 2 ; have_right
add xd, xlimd
xor xlimd, 2 ; 2*!have_right
%else
cglobal sgr_box3_h, 6, 7, 8, sumsq, sum, left, src, stride, x, h, edge, w, xlim
%define wq r0m
%define xlimd r1m
%define hd hmp
%define edgeb byte edgem
mov r6, edgem
and r6, 2 ; have_right
add xd, r6
xor r6, 2 ; 2*!have_right
mov xlimd, r6
SETUP_PIC r6, 0
%endif
jnz .no_right
add xd, 7
and xd, ~7
.no_right:
pxor m1, m1
lea srcq, [srcq+xq]
lea sumq, [sumq+xq*2-2]
lea sumsqq, [sumsqq+xq*4-4]
neg xq
mov wq, xq
%if ARCH_X86_64
lea r10, [pb_right_ext_mask+16]
%endif
.loop_y:
mov xq, wq
; load left
test edgeb, 1 ; have_left
jz .no_left
test leftq, leftq
jz .load_left_from_main
movd m0, [leftq]
pslldq m0, 12
add leftq, 4
jmp .expand_x
.no_left:
movd m0, [srcq+xq]
pshufb m0, [PIC_sym(pb_0)]
jmp .expand_x
.load_left_from_main:
movd m0, [srcq+xq-2]
pslldq m0, 14
.expand_x:
punpckhbw xm0, xm1
; when we reach this, m0 contains left two px in highest words
cmp xd, -8
jle .loop_x
.partial_load_and_extend:
movd m3, [srcq-4]
pshufb m3, [PIC_sym(pb_3)]
movq m2, [srcq+xq]
punpcklbw m2, m1
punpcklbw m3, m1
%if ARCH_X86_64
movu m4, [r10+xq*2]
%else
movu m4, [PIC_sym(pb_right_ext_mask+16)+xd*2]
%endif
pand m2, m4
pandn m4, m3
por m2, m4
jmp .loop_x_noload
.right_extend:
pshufb m2, m0, [PIC_sym(pb_14_15)]
jmp .loop_x_noload
.loop_x:
movq m2, [srcq+xq]
punpcklbw m2, m1
.loop_x_noload:
palignr m3, m2, m0, 12
palignr m4, m2, m0, 14
punpcklwd m5, m3, m2
punpckhwd m6, m3, m2
paddw m3, m4
punpcklwd m7, m4, m1
punpckhwd m4, m1
pmaddwd m5, m5
pmaddwd m6, m6
pmaddwd m7, m7
pmaddwd m4, m4
paddd m5, m7
paddd m6, m4
paddw m3, m2
movu [sumq+xq*2], m3
movu [sumsqq+xq*4+ 0], m5
movu [sumsqq+xq*4+16], m6
mova m0, m2
add xq, 8
; if x <= -8 we can reload more pixels
; else if x < 0 we reload and extend (this implies have_right=0)
; else if x < xlimd we extend from previous load (this implies have_right=0)
; else we are done
cmp xd, -8
jle .loop_x
test xd, xd
jl .partial_load_and_extend
cmp xd, xlimd
jl .right_extend
add sumsqq, (384+16)*4
add sumq, (384+16)*2
add srcq, strideq
dec hd
jg .loop_y
RET
%if ARCH_X86_64
cglobal sgr_box3_v, 4, 10, 9, sumsq, sum, w, h, edge, x, y, sumsq_base, sum_base, ylim
movifnidn edged, edgem
%else
cglobal sgr_box3_v, 3, 7, 8, -28, sumsq, sum, w, edge, h, x, y
%define sumsq_baseq dword [esp+0]
%define sum_baseq dword [esp+4]
%define ylimd dword [esp+8]
%define m8 [esp+12]
mov edged, r4m
mov hd, r3m
%endif
mov xq, -2
%if ARCH_X86_64
mov ylimd, edged
and ylimd, 8 ; have_bottom
shr ylimd, 2
sub ylimd, 2 ; -2 if have_bottom=0, else 0
mov sumsq_baseq, sumsqq
mov sum_baseq, sumq
.loop_x:
mov sumsqq, sumsq_baseq
mov sumq, sum_baseq
lea yd, [hq+ylimq+2]
%else
mov yd, edged
and yd, 8 ; have_bottom
shr yd, 2
sub yd, 2 ; -2 if have_bottom=0, else 0
mov sumsq_baseq, sumsqq
mov sum_baseq, sumq
mov ylimd, yd
.loop_x:
mov sumsqd, sumsq_baseq
mov sumd, sum_baseq
lea yd, [hq+2]
add yd, ylimd
%endif
lea sumsqq, [sumsqq+xq*4+4-(384+16)*4]
lea sumq, [sumq+xq*2+2-(384+16)*2]
test edgeb, 4 ; have_top
jnz .load_top
movu m0, [sumsqq+(384+16)*4*1]
movu m1, [sumsqq+(384+16)*4*1+16]
mova m2, m0
mova m3, m1
mova m4, m0
mova m5, m1
movu m6, [sumq+(384+16)*2*1]
mova m7, m6
mova m8, m6
jmp .loop_y_noload
.load_top:
movu m0, [sumsqq-(384+16)*4*1] ; l2sq [left]
movu m1, [sumsqq-(384+16)*4*1+16] ; l2sq [right]
movu m2, [sumsqq-(384+16)*4*0] ; l1sq [left]
movu m3, [sumsqq-(384+16)*4*0+16] ; l1sq [right]
movu m6, [sumq-(384+16)*2*1] ; l2
movu m7, [sumq-(384+16)*2*0] ; l1
.loop_y:
%if ARCH_X86_64
movu m8, [sumq+(384+16)*2*1] ; l0
%else
movu m4, [sumq+(384+16)*2*1] ; l0
mova m8, m4
%endif
movu m4, [sumsqq+(384+16)*4*1] ; l0sq [left]
movu m5, [sumsqq+(384+16)*4*1+16] ; l0sq [right]
.loop_y_noload:
paddd m0, m2
paddd m1, m3
paddw m6, m7
paddd m0, m4
paddd m1, m5
paddw m6, m8
movu [sumsqq+ 0], m0
movu [sumsqq+16], m1
movu [sumq], m6
; shift position down by one
mova m0, m2
mova m1, m3
mova m2, m4
mova m3, m5
mova m6, m7
mova m7, m8
add sumsqq, (384+16)*4
add sumq, (384+16)*2
dec yd
jg .loop_y
cmp yd, ylimd
jg .loop_y_noload
add xd, 8
cmp xd, wd
jl .loop_x
RET
cglobal sgr_calc_ab1, 4, 7, 12, a, b, w, h, s
movifnidn sd, sm
sub aq, (384+16-1)*4
sub bq, (384+16-1)*2
add hd, 2
%if ARCH_X86_64
LEA r5, sgr_x_by_x-0xF03
%else
SETUP_PIC r5, 0
%endif
movd m6, sd
pshuflw m6, m6, q0000
punpcklqdq m6, m6
pxor m7, m7
DEFINE_ARGS a, b, w, h, x
%if ARCH_X86_64
mova m8, [pd_0xF00801C7]
mova m9, [pw_256]
psrld m10, m9, 13 ; pd_2048
mova m11, [pb_unpcklwdw]
%else
%define m8 [PIC_sym(pd_0xF00801C7)]
%define m9 [PIC_sym(pw_256)]
%define m10 [PIC_sym(pd_2048)]
%define m11 [PIC_sym(pb_unpcklwdw)]
%endif
.loop_y:
mov xq, -2
.loop_x:
movq m0, [bq+xq*2]
movq m1, [bq+xq*2+(384+16)*2]
punpcklwd m0, m7
punpcklwd m1, m7
movu m2, [aq+xq*4]
movu m3, [aq+xq*4+(384+16)*4]
pslld m4, m2, 3
pslld m5, m3, 3
paddd m2, m4 ; aa * 9
paddd m3, m5
pmaddwd m4, m0, m0
pmaddwd m5, m1, m1
pmaddwd m0, m8
pmaddwd m1, m8
psubd m2, m4 ; p = aa * 9 - bb * bb
psubd m3, m5
MULLD m2, m6
MULLD m3, m6
paddusw m2, m8
paddusw m3, m8
psrld m2, 20 ; z
psrld m3, 20
GATHERDD m4, m2 ; xx
GATHERDD m2, m3
psrld m4, 24
psrld m2, 24
packssdw m3, m4, m2
pshufb m4, m11
MULLD m0, m4
pshufb m2, m11
MULLD m1, m2
psubw m5, m9, m3
paddd m0, m10
paddd m1, m10
psrld m0, 12
psrld m1, 12
movq [bq+xq*2], m5
psrldq m5, 8
movq [bq+xq*2+(384+16)*2], m5
movu [aq+xq*4], m0
movu [aq+xq*4+(384+16)*4], m1
add xd, 4
cmp xd, wd
jl .loop_x
add aq, (384+16)*4*2
add bq, (384+16)*2*2
sub hd, 2
jg .loop_y
RET
%if ARCH_X86_64
cglobal sgr_finish_filter1, 5, 13, 16, t, src, stride, a, b, w, h, \
tmp_base, src_base, a_base, b_base, x, y
movifnidn wd, wm
mov hd, hm
mova m15, [pw_16]
mov tmp_baseq, tq
mov src_baseq, srcq
mov a_baseq, aq
mov b_baseq, bq
xor xd, xd
%else
cglobal sgr_finish_filter1, 7, 7, 8, -144, t, src, stride, a, b, x, y
%define tmp_baseq [esp+8]
%define src_baseq [esp+12]
%define a_baseq [esp+16]
%define b_baseq [esp+20]
%define wd [esp+24]
%define hd [esp+28]
mov tmp_baseq, tq
mov src_baseq, srcq
mov a_baseq, aq
mov b_baseq, bq
mov wd, xd
mov hd, yd
xor xd, xd
SETUP_PIC yd, 1, 1
jmp .loop_start
%endif
.loop_x:
mov tq, tmp_baseq
mov srcq, src_baseq
mov aq, a_baseq
mov bq, b_baseq
%if ARCH_X86_32
.loop_start:
movu m0, [bq+xq*2-(384+16)*2-2]
movu m2, [bq+xq*2-(384+16)*2+2]
mova m1, [bq+xq*2-(384+16)*2] ; b:top
paddw m0, m2 ; b:tl+tr
movu m2, [bq+xq*2-2]
movu m3, [bq+xq*2+2]
paddw m1, [bq+xq*2] ; b:top+ctr
paddw m2, m3 ; b:l+r
mova [esp+0x80], m0
mova [esp+0x70], m1
mova [esp+0x60], m2
%endif
movu m0, [aq+xq*4-(384+16)*4-4]
movu m2, [aq+xq*4-(384+16)*4+4]
mova m1, [aq+xq*4-(384+16)*4] ; a:top [first half]
paddd m0, m2 ; a:tl+tr [first half]
movu m2, [aq+xq*4-(384+16)*4-4+16]
movu m4, [aq+xq*4-(384+16)*4+4+16]
mova m3, [aq+xq*4-(384+16)*4+16] ; a:top [second half]
paddd m2, m4 ; a:tl+tr [second half]
movu m4, [aq+xq*4-4]
movu m5, [aq+xq*4+4]
paddd m1, [aq+xq*4] ; a:top+ctr [first half]
paddd m4, m5 ; a:l+r [first half]
movu m5, [aq+xq*4+16-4]
movu m6, [aq+xq*4+16+4]
paddd m3, [aq+xq*4+16] ; a:top+ctr [second half]
paddd m5, m6 ; a:l+r [second half]
%if ARCH_X86_64
movu m6, [bq+xq*2-(384+16)*2-2]
movu m8, [bq+xq*2-(384+16)*2+2]
mova m7, [bq+xq*2-(384+16)*2] ; b:top
paddw m6, m8 ; b:tl+tr
movu m8, [bq+xq*2-2]
movu m9, [bq+xq*2+2]
paddw m7, [bq+xq*2] ; b:top+ctr
paddw m8, m9 ; b:l+r
%endif
lea tq, [tq+xq*2]
lea srcq, [srcq+xq*1]
lea aq, [aq+xq*4+(384+16)*4]
lea bq, [bq+xq*2+(384+16)*2]
mov yd, hd
.loop_y:
%if ARCH_X86_64
movu m9, [bq-2]
movu m10, [bq+2]
paddw m7, [bq] ; b:top+ctr+bottom
paddw m9, m10 ; b:bl+br
paddw m10, m7, m8 ; b:top+ctr+bottom+l+r
paddw m6, m9 ; b:tl+tr+bl+br
psubw m7, [bq-(384+16)*2*2] ; b:ctr+bottom
paddw m10, m6
psllw m10, 2
psubw m10, m6 ; aa
pxor m14, m14
movq m12, [srcq]
punpcklbw m12, m14
punpcklwd m6, m10, m15
punpckhwd m10, m15
punpcklwd m13, m12, m15
punpckhwd m12, m15
pmaddwd m6, m13 ; aa*src[x]+256 [first half]
pmaddwd m10, m12 ; aa*src[x]+256 [second half]
%else
paddd m1, [aq] ; a:top+ctr+bottom [first half]
paddd m3, [aq+16] ; a:top+ctr+bottom [second half]
mova [esp+0x50], m1
mova [esp+0x40], m3
mova [esp+0x30], m4
movu m6, [aq-4]
movu m7, [aq+4]
paddd m1, m4 ; a:top+ctr+bottom+l+r [first half]
paddd m3, m5 ; a:top+ctr+bottom+l+r [second half]
paddd m6, m7 ; a:bl+br [first half]
movu m7, [aq+16-4]
movu m4, [aq+16+4]
paddd m7, m4 ; a:bl+br [second half]
paddd m0, m6 ; a:tl+tr+bl+br [first half]
paddd m2, m7 ; a:tl+tr+bl+br [second half]
paddd m1, m0
paddd m3, m2
pslld m1, 2
pslld m3, 2
psubd m1, m0 ; bb [first half]
psubd m3, m2 ; bb [second half]
%endif
%if ARCH_X86_64
movu m11, [aq-4]
movu m12, [aq+4]
paddd m1, [aq] ; a:top+ctr+bottom [first half]
paddd m11, m12 ; a:bl+br [first half]
movu m12, [aq+16-4]
movu m13, [aq+16+4]
paddd m3, [aq+16] ; a:top+ctr+bottom [second half]
paddd m12, m13 ; a:bl+br [second half]
paddd m13, m1, m4 ; a:top+ctr+bottom+l+r [first half]
paddd m14, m3, m5 ; a:top+ctr+bottom+l+r [second half]
paddd m0, m11 ; a:tl+tr+bl+br [first half]
paddd m2, m12 ; a:tl+tr+bl+br [second half]
paddd m13, m0
paddd m14, m2
pslld m13, 2
pslld m14, 2
psubd m13, m0 ; bb [first half]
psubd m14, m2 ; bb [second half]
psubd m1, [aq-(384+16)*4*2] ; a:ctr+bottom [first half]
psubd m3, [aq-(384+16)*4*2+16] ; a:ctr+bottom [second half]
%else
mova m4, [esp+0x80]
mova [esp+0x80], m5
mova m5, [esp+0x70]
mova [esp+0x70], m6
mova m6, [esp+0x60]
mova [esp+0x60], m7
mova [esp+0x20], m1
movu m7, [bq-2]
movu m1, [bq+2]
paddw m5, [bq] ; b:top+ctr+bottom
paddw m7, m1
paddw m1, m5, m6 ; b:top+ctr+bottom+l+r
paddw m4, m7 ; b:tl+tr+bl+br
psubw m5, [bq-(384+16)*2*2] ; b:ctr+bottom
paddw m1, m4
psllw m1, 2
psubw m1, m4 ; aa
movq m0, [srcq]
XCHG_PIC_REG
punpcklbw m0, [PIC_sym(pb_right_ext_mask)+16]
punpcklwd m4, m1, [PIC_sym(pw_16)]
punpckhwd m1, [PIC_sym(pw_16)]
punpcklwd m2, m0, [PIC_sym(pw_16)]
punpckhwd m0, [PIC_sym(pw_16)]
XCHG_PIC_REG
pmaddwd m4, m2 ; aa*src[x]+256 [first half]
pmaddwd m1, m0 ; aa*src[x]+256 [second half]
%endif
%if ARCH_X86_64
paddd m6, m13
paddd m10, m14
psrad m6, 9
psrad m10, 9
packssdw m6, m10
mova [tq], m6
%else
paddd m4, [esp+0x20]
paddd m1, m3
psrad m4, 9
psrad m1, 9
packssdw m4, m1
mova [tq], m4
%endif
; shift to next row
%if ARCH_X86_64
mova m0, m4
mova m2, m5
mova m4, m11
mova m5, m12
mova m6, m8
mova m8, m9
%else
mova m1, [esp+0x50]
mova m3, [esp+0x40]
mova m0, [esp+0x30]
mova m2, [esp+0x80]
mova m4, [esp+0x70]
mova [esp+0x70], m5
mova m5, [esp+0x60]
mova [esp+0x80], m6
mova [esp+0x60], m7
psubd m1, [aq-(384+16)*4*2] ; a:ctr+bottom [first half]
psubd m3, [aq-(384+16)*4*2+16] ; a:ctr+bottom [second half]
%endif
add srcq, strideq
add aq, (384+16)*4
add bq, (384+16)*2
add tq, 384*2
dec yd
jg .loop_y
add xd, 8
cmp xd, wd
jl .loop_x
RET
cglobal sgr_weighted1, 4, 7, 8, dst, stride, t, w, h, wt
movifnidn hd, hm
%if ARCH_X86_32
SETUP_PIC r6, 0
%endif
movd m0, wtm
pshufb m0, [PIC_sym(pb_0_1)]
psllw m0, 4
pxor m7, m7
DEFINE_ARGS dst, stride, t, w, h, idx
.loop_y:
xor idxd, idxd
.loop_x:
mova m1, [tq+idxq*2+ 0]
mova m4, [tq+idxq*2+16]
mova m5, [dstq+idxq]
punpcklbw m2, m5, m7
punpckhbw m5, m7
psllw m3, m2, 4
psllw m6, m5, 4
psubw m1, m3
psubw m4, m6
pmulhrsw m1, m0
pmulhrsw m4, m0
paddw m1, m2
paddw m4, m5
packuswb m1, m4
mova [dstq+idxq], m1
add idxd, 16
cmp idxd, wd
jl .loop_x
add dstq, strideq
add tq, 384 * 2
dec hd
jg .loop_y
RET
%if ARCH_X86_64
cglobal sgr_box5_h, 5, 11, 12, sumsq, sum, left, src, stride, w, h, edge, x, xlim
mov edged, edgem
movifnidn wd, wm
mov hd, hm
mova m10, [pb_0]
mova m11, [pb_0_1]
%else
cglobal sgr_box5_h, 7, 7, 8, sumsq, sum, left, src, xlim, x, h, edge
%define edgeb byte edgem
%define wd xd
%define wq wd
%define wm r5m
%define strideq r4m
SUB esp, 8
SETUP_PIC sumsqd, 1, 1
%define m10 [PIC_sym(pb_0)]
%define m11 [PIC_sym(pb_0_1)]
%endif
test edgeb, 2 ; have_right
jz .no_right
xor xlimd, xlimd
add wd, 2
add wd, 15
and wd, ~15
jmp .right_done
.no_right:
mov xlimd, 3
dec wd
.right_done:
pxor m1, m1
lea srcq, [srcq+wq+1]
lea sumq, [sumq+wq*2-2]
lea sumsqq, [sumsqq+wq*4-4]
neg wq
%if ARCH_X86_64
lea r10, [pb_right_ext_mask+16]
%else
mov wm, xd
%define wq wm
%endif
.loop_y:
mov xq, wq
; load left
test edgeb, 1 ; have_left
jz .no_left
test leftq, leftq
jz .load_left_from_main
movd m0, [leftq]
movd m2, [srcq+xq-1]
pslldq m2, 4
por m0, m2
pslldq m0, 11
add leftq, 4
jmp .expand_x
.no_left:
movd m0, [srcq+xq-1]
XCHG_PIC_REG
pshufb m0, m10
XCHG_PIC_REG
jmp .expand_x
.load_left_from_main:
movd m0, [srcq+xq-4]
pslldq m0, 12
.expand_x:
punpckhbw m0, m1
; when we reach this, m0 contains left two px in highest words
cmp xd, -8
jle .loop_x
test xd, xd
jge .right_extend
.partial_load_and_extend:
XCHG_PIC_REG
movd m3, [srcq-1]
movq m2, [srcq+xq]
pshufb m3, m10
punpcklbw m3, m1
punpcklbw m2, m1
%if ARCH_X86_64
movu m4, [r10+xq*2]
%else
movu m4, [PIC_sym(pb_right_ext_mask+16)+xd*2]
XCHG_PIC_REG
%endif
pand m2, m4
pandn m4, m3
por m2, m4
jmp .loop_x_noload
.right_extend:
psrldq m2, m0, 14
XCHG_PIC_REG
pshufb m2, m11
XCHG_PIC_REG
jmp .loop_x_noload
.loop_x:
movq m2, [srcq+xq]
punpcklbw m2, m1
.loop_x_noload:
palignr m3, m2, m0, 8
palignr m4, m2, m0, 10
palignr m5, m2, m0, 12
palignr m6, m2, m0, 14
%if ARCH_X86_64
paddw m0, m3, m2
punpcklwd m7, m3, m2
punpckhwd m3, m2
paddw m0, m4
punpcklwd m8, m4, m5
punpckhwd m4, m5
paddw m0, m5
punpcklwd m9, m6, m1
punpckhwd m5, m6, m1
paddw m0, m6
pmaddwd m7, m7
pmaddwd m3, m3
pmaddwd m8, m8
pmaddwd m4, m4
pmaddwd m9, m9
pmaddwd m5, m5
paddd m7, m8
paddd m3, m4
paddd m7, m9
paddd m3, m5
movu [sumq+xq*2], m0
movu [sumsqq+xq*4+ 0], m7
movu [sumsqq+xq*4+16], m3
%else
paddw m0, m3, m2
paddw m0, m4
paddw m0, m5
paddw m0, m6
movu [sumq+xq*2], m0
punpcklwd m7, m3, m2
punpckhwd m3, m2
punpcklwd m0, m4, m5
punpckhwd m4, m5
punpckhwd m5, m6, m1
pmaddwd m7, m7
pmaddwd m3, m3
pmaddwd m0, m0
pmaddwd m4, m4
pmaddwd m5, m5
paddd m7, m0
paddd m3, m4
paddd m3, m5
punpcklwd m0, m6, m1
pmaddwd m0, m0
paddd m7, m0
movu [sumsqq+xq*4+ 0], m7
movu [sumsqq+xq*4+16], m3
%endif
mova m0, m2
add xq, 8
; if x <= -8 we can reload more pixels
; else if x < 0 we reload and extend (this implies have_right=0)
; else if x < xlimd we extend from previous load (this implies have_right=0)
; else we are done
cmp xd, -8
jle .loop_x
test xd, xd
jl .partial_load_and_extend
cmp xd, xlimd
jl .right_extend
add srcq, strideq
add sumsqq, (384+16)*4
add sumq, (384+16)*2
dec hd
jg .loop_y
%if ARCH_X86_32
ADD esp, 8
%endif
RET
%if ARCH_X86_64
cglobal sgr_box5_v, 4, 10, 15, sumsq, sum, w, h, edge, x, y, sumsq_ptr, sum_ptr, ylim
movifnidn edged, edgem
mov ylimd, edged
%else
cglobal sgr_box5_v, 5, 7, 8, -44, sumsq, sum, x, y, ylim, sumsq_ptr, sum_ptr
%define wm [esp+0]
%define hm [esp+4]
%define edgem [esp+8]
mov wm, xd
mov hm, yd
mov edgem, ylimd
%endif
and ylimd, 8 ; have_bottom
shr ylimd, 2
sub ylimd, 3 ; -3 if have_bottom=0, else -1
mov xq, -2
%if ARCH_X86_64
.loop_x:
lea yd, [hd+ylimd+2]
lea sumsq_ptrq, [sumsqq+xq*4+4-(384+16)*4]
lea sum_ptrq, [ sumq+xq*2+2-(384+16)*2]
test edgeb, 4 ; have_top
jnz .load_top
movu m0, [sumsq_ptrq+(384+16)*4*1]
movu m1, [sumsq_ptrq+(384+16)*4*1+16]
mova m2, m0
mova m3, m1
mova m4, m0
mova m5, m1
mova m6, m0
mova m7, m1
movu m10, [sum_ptrq+(384+16)*2*1]
mova m11, m10
mova m12, m10
mova m13, m10
jmp .loop_y_second_load
.load_top:
movu m0, [sumsq_ptrq-(384+16)*4*1] ; l3/4sq [left]
movu m1, [sumsq_ptrq-(384+16)*4*1+16] ; l3/4sq [right]
movu m4, [sumsq_ptrq-(384+16)*4*0] ; l2sq [left]
movu m5, [sumsq_ptrq-(384+16)*4*0+16] ; l2sq [right]
mova m2, m0
mova m3, m1
movu m10, [sum_ptrq-(384+16)*2*1] ; l3/4
movu m12, [sum_ptrq-(384+16)*2*0] ; l2
mova m11, m10
.loop_y:
movu m6, [sumsq_ptrq+(384+16)*4*1] ; l1sq [left]
movu m7, [sumsq_ptrq+(384+16)*4*1+16] ; l1sq [right]
movu m13, [sum_ptrq+(384+16)*2*1] ; l1
.loop_y_second_load:
test yd, yd
jle .emulate_second_load
movu m8, [sumsq_ptrq+(384+16)*4*2] ; l0sq [left]
movu m9, [sumsq_ptrq+(384+16)*4*2+16] ; l0sq [right]
movu m14, [sum_ptrq+(384+16)*2*2] ; l0
.loop_y_noload:
paddd m0, m2
paddd m1, m3
paddw m10, m11
paddd m0, m4
paddd m1, m5
paddw m10, m12
paddd m0, m6
paddd m1, m7
paddw m10, m13
paddd m0, m8
paddd m1, m9
paddw m10, m14
movu [sumsq_ptrq+ 0], m0
movu [sumsq_ptrq+16], m1
movu [sum_ptrq], m10
; shift position down by one
mova m0, m4
mova m1, m5
mova m2, m6
mova m3, m7
mova m4, m8
mova m5, m9
mova m10, m12
mova m11, m13
mova m12, m14
add sumsq_ptrq, (384+16)*4*2
add sum_ptrq, (384+16)*2*2
sub yd, 2
jge .loop_y
; l1 = l0
mova m6, m8
mova m7, m9
mova m13, m14
cmp yd, ylimd
jg .loop_y_noload
add xd, 8
cmp xd, wd
jl .loop_x
RET
.emulate_second_load:
mova m8, m6
mova m9, m7
mova m14, m13
jmp .loop_y_noload
%else
.sumsq_loop_x:
lea yd, [ylimd+2]
add yd, hm
lea sumsq_ptrq, [sumsqq+xq*4+4-(384+16)*4]
test byte edgem, 4 ; have_top
jnz .sumsq_load_top
movu m0, [sumsq_ptrq+(384+16)*4*1]
movu m1, [sumsq_ptrq+(384+16)*4*1+16]
mova m4, m0
mova m5, m1
mova m6, m0
mova m7, m1
mova [esp+0x1c], m0
mova [esp+0x0c], m1
jmp .sumsq_loop_y_second_load
.sumsq_load_top:
movu m0, [sumsq_ptrq-(384+16)*4*1] ; l3/4sq [left]
movu m1, [sumsq_ptrq-(384+16)*4*1+16] ; l3/4sq [right]
movu m4, [sumsq_ptrq-(384+16)*4*0] ; l2sq [left]
movu m5, [sumsq_ptrq-(384+16)*4*0+16] ; l2sq [right]
mova [esp+0x1c], m0
mova [esp+0x0c], m1
.sumsq_loop_y:
movu m6, [sumsq_ptrq+(384+16)*4*1] ; l1sq [left]
movu m7, [sumsq_ptrq+(384+16)*4*1+16] ; l1sq [right]
.sumsq_loop_y_second_load:
test yd, yd
jle .sumsq_emulate_second_load
movu m2, [sumsq_ptrq+(384+16)*4*2] ; l0sq [left]
movu m3, [sumsq_ptrq+(384+16)*4*2+16] ; l0sq [right]
.sumsq_loop_y_noload:
paddd m0, [esp+0x1c]
paddd m1, [esp+0x0c]
paddd m0, m4
paddd m1, m5
paddd m0, m6
paddd m1, m7
paddd m0, m2
paddd m1, m3
movu [sumsq_ptrq+ 0], m0
movu [sumsq_ptrq+16], m1
; shift position down by one
mova m0, m4
mova m1, m5
mova m4, m2
mova m5, m3
mova [esp+0x1c], m6
mova [esp+0x0c], m7
add sumsq_ptrq, (384+16)*4*2
sub yd, 2
jge .sumsq_loop_y
; l1 = l0
mova m6, m2
mova m7, m3
cmp yd, ylimd
jg .sumsq_loop_y_noload
add xd, 8
cmp xd, wm
jl .sumsq_loop_x
mov xd, -2
.sum_loop_x:
lea yd, [ylimd+2]
add yd, hm
lea sum_ptrq, [sumq+xq*2+2-(384+16)*2]
test byte edgem, 4 ; have_top
jnz .sum_load_top
movu m0, [sum_ptrq+(384+16)*2*1]
mova m1, m0
mova m2, m0
mova m3, m0
jmp .sum_loop_y_second_load
.sum_load_top:
movu m0, [sum_ptrq-(384+16)*2*1] ; l3/4
movu m2, [sum_ptrq-(384+16)*2*0] ; l2
mova m1, m0
.sum_loop_y:
movu m3, [sum_ptrq+(384+16)*2*1] ; l1
.sum_loop_y_second_load:
test yd, yd
jle .sum_emulate_second_load
movu m4, [sum_ptrq+(384+16)*2*2] ; l0
.sum_loop_y_noload:
paddw m0, m1
paddw m0, m2
paddw m0, m3
paddw m0, m4
movu [sum_ptrq], m0
; shift position down by one
mova m0, m2
mova m1, m3
mova m2, m4
add sum_ptrq, (384+16)*2*2
sub yd, 2
jge .sum_loop_y
; l1 = l0
mova m3, m4
cmp yd, ylimd
jg .sum_loop_y_noload
add xd, 8
cmp xd, wm
jl .sum_loop_x
RET
.sumsq_emulate_second_load:
mova m2, m6
mova m3, m7
jmp .sumsq_loop_y_noload
.sum_emulate_second_load:
mova m4, m3
jmp .sum_loop_y_noload
%endif
cglobal sgr_calc_ab2, 4, 7, 11, a, b, w, h, s
movifnidn sd, sm
sub aq, (384+16-1)*4
sub bq, (384+16-1)*2
add hd, 2
%if ARCH_X86_64
LEA r5, sgr_x_by_x-0xF03
%else
SETUP_PIC r5, 0
%endif
movd m6, sd
pshuflw m6, m6, q0000
punpcklqdq m6, m6
pxor m7, m7
DEFINE_ARGS a, b, w, h, x
%if ARCH_X86_64
mova m8, [pd_0xF0080029]
mova m9, [pw_256]
psrld m10, m9, 15 ; pd_512
%else
%define m8 [PIC_sym(pd_0xF0080029)]
%define m9 [PIC_sym(pw_256)]
%define m10 [PIC_sym(pd_512)]
%endif
.loop_y:
mov xq, -2
.loop_x:
movq m0, [bq+xq*2+0]
movq m1, [bq+xq*2+8]
punpcklwd m0, m7
punpcklwd m1, m7
movu m2, [aq+xq*4+ 0]
movu m3, [aq+xq*4+16]
pslld m4, m2, 3 ; aa * 8
pslld m5, m3, 3
paddd m2, m4 ; aa * 9
paddd m3, m5
paddd m4, m4 ; aa * 16
paddd m5, m5
paddd m2, m4 ; aa * 25
paddd m3, m5
pmaddwd m4, m0, m0
pmaddwd m5, m1, m1
psubd m2, m4 ; p = aa * 25 - bb * bb
psubd m3, m5
MULLD m2, m6
MULLD m3, m6
paddusw m2, m8
paddusw m3, m8
psrld m2, 20 ; z
psrld m3, 20
GATHERDD m4, m2 ; xx
GATHERDD m2, m3
psrld m4, 24
psrld m2, 24
packssdw m3, m4, m2
pmullw m4, m8
pmullw m2, m8
psubw m5, m9, m3
pmaddwd m0, m4
pmaddwd m1, m2
paddd m0, m10
paddd m1, m10
psrld m0, 10
psrld m1, 10
movu [bq+xq*2], m5
movu [aq+xq*4+ 0], m0
movu [aq+xq*4+16], m1
add xd, 8
cmp xd, wd
jl .loop_x
add aq, (384+16)*4*2
add bq, (384+16)*2*2
sub hd, 2
jg .loop_y
RET
%if ARCH_X86_64
cglobal sgr_finish_filter2, 5, 13, 14, t, src, stride, a, b, w, h, \
tmp_base, src_base, a_base, b_base, x, y
movifnidn wd, wm
mov hd, hm
mov tmp_baseq, tq
mov src_baseq, srcq
mov a_baseq, aq
mov b_baseq, bq
mova m9, [pw_5_6]
mova m12, [pw_256]
psrlw m10, m12, 8 ; pw_1
psrlw m11, m12, 1 ; pw_128
pxor m13, m13
%else
cglobal sgr_finish_filter2, 6, 7, 8, t, src, stride, a, b, x, y
%define tmp_baseq r0m
%define src_baseq r1m
%define a_baseq r3m
%define b_baseq r4m
%define wd r5m
%define hd r6m
SUB esp, 8
SETUP_PIC yd
%define m8 m5
%define m9 [PIC_sym(pw_5_6)]
%define m10 [PIC_sym(pw_1)]
%define m11 [PIC_sym(pw_128)]
%define m12 [PIC_sym(pw_256)]
%define m13 m0
%endif
xor xd, xd
.loop_x:
mov tq, tmp_baseq
mov srcq, src_baseq
mov aq, a_baseq
mov bq, b_baseq
movu m0, [aq+xq*4-(384+16)*4-4]
mova m1, [aq+xq*4-(384+16)*4]
movu m2, [aq+xq*4-(384+16)*4+4]
movu m3, [aq+xq*4-(384+16)*4-4+16]
mova m4, [aq+xq*4-(384+16)*4+16]
movu m5, [aq+xq*4-(384+16)*4+4+16]
paddd m0, m2
paddd m3, m5
paddd m0, m1
paddd m3, m4
pslld m2, m0, 2
pslld m5, m3, 2
paddd m2, m0
paddd m5, m3
paddd m0, m2, m1 ; prev_odd_b [first half]
paddd m1, m5, m4 ; prev_odd_b [second half]
movu m3, [bq+xq*2-(384+16)*2-2]
mova m4, [bq+xq*2-(384+16)*2]
movu m5, [bq+xq*2-(384+16)*2+2]
paddw m3, m5
punpcklwd m5, m3, m4
punpckhwd m3, m4
pmaddwd m5, m9
pmaddwd m3, m9
mova m2, m5
packssdw m2, m3 ; prev_odd_a
lea tq, [tq+xq*2]
lea srcq, [srcq+xq*1]
lea aq, [aq+xq*4+(384+16)*4]
lea bq, [bq+xq*2+(384+16)*2]
%if ARCH_X86_32
mov [esp], PIC_reg
%endif
mov yd, hd
XCHG_PIC_REG
.loop_y:
movu m3, [aq-4]
mova m4, [aq]
movu m5, [aq+4]
paddd m3, m5
paddd m3, m4
pslld m5, m3, 2
paddd m5, m3
paddd m5, m4 ; cur_odd_b [first half]
movu m3, [aq+16-4]
mova m6, [aq+16]
movu m7, [aq+16+4]
paddd m3, m7
paddd m3, m6
pslld m7, m3, 2
paddd m7, m3
paddd m4, m7, m6 ; cur_odd_b [second half]
movu m3, [bq-2]
mova m6, [bq]
movu m7, [bq+2]
paddw m3, m7
punpcklwd m7, m3, m6
punpckhwd m3, m6
pmaddwd m7, m9
pmaddwd m3, m9
packssdw m6, m7, m3 ; cur_odd_a
paddd m0, m5 ; cur_even_b [first half]
paddd m1, m4 ; cur_even_b [second half]
paddw m2, m6 ; cur_even_a
movq m3, [srcq]
%if ARCH_X86_64
punpcklbw m3, m13
%else
mova [td], m5
pxor m7, m7
punpcklbw m3, m7
%endif
punpcklwd m7, m3, m10
punpckhwd m3, m10
punpcklwd m8, m2, m12
punpckhwd m2, m12
pmaddwd m7, m8
pmaddwd m3, m2
paddd m7, m0
paddd m3, m1
psrad m7, 9
psrad m3, 9
%if ARCH_X86_32
pxor m13, m13
%endif
movq m8, [srcq+strideq]
punpcklbw m8, m13
punpcklwd m0, m8, m10
punpckhwd m8, m10
punpcklwd m1, m6, m11
punpckhwd m2, m6, m11
pmaddwd m0, m1
pmaddwd m8, m2
%if ARCH_X86_64
paddd m0, m5
%else
paddd m0, [td]
%endif
paddd m8, m4
psrad m0, 8
psrad m8, 8
packssdw m7, m3
packssdw m0, m8
%if ARCH_X86_32
mova m5, [td]
%endif
mova [tq+384*2*0], m7
mova [tq+384*2*1], m0
mova m0, m5
mova m1, m4
mova m2, m6
add aq, (384+16)*4*2
add bq, (384+16)*2*2
add tq, 384*2*2
lea srcq, [srcq+strideq*2]
%if ARCH_X86_64
sub yd, 2
%else
sub dword [esp+4], 2
%endif
jg .loop_y
add xd, 8
cmp xd, wd
jl .loop_x
%if ARCH_X86_32
ADD esp, 8
%endif
RET
cglobal sgr_weighted2, 4, 7, 12, dst, stride, t1, t2, w, h, wt
movifnidn wd, wm
movd m0, wtm
%if ARCH_X86_64
movifnidn hd, hm
mova m10, [pd_1024]
pxor m11, m11
%else
SETUP_PIC hd, 0
%define m10 [PIC_sym(pd_1024)]
%define m11 m7
%endif
pshufd m0, m0, 0
DEFINE_ARGS dst, stride, t1, t2, w, h, idx
%if ARCH_X86_32
%define hd hmp
%endif
.loop_y:
xor idxd, idxd
.loop_x:
mova m1, [t1q+idxq*2+ 0]
mova m2, [t1q+idxq*2+16]
mova m3, [t2q+idxq*2+ 0]
mova m4, [t2q+idxq*2+16]
mova m6, [dstq+idxq]
%if ARCH_X86_32
pxor m11, m11
%endif
punpcklbw m5, m6, m11
punpckhbw m6, m11
psllw m7, m5, 4
psubw m1, m7
psubw m3, m7
psllw m7, m6, 4
psubw m2, m7
psubw m4, m7
punpcklwd m7, m1, m3
punpckhwd m1, m3
punpcklwd m3, m2, m4
punpckhwd m2, m4
pmaddwd m7, m0
pmaddwd m1, m0
pmaddwd m3, m0
pmaddwd m2, m0
paddd m7, m10
paddd m1, m10
paddd m3, m10
paddd m2, m10
psrad m7, 11
psrad m1, 11
psrad m3, 11
psrad m2, 11
packssdw m7, m1
packssdw m3, m2
paddw m7, m5
paddw m3, m6
packuswb m7, m3
mova [dstq+idxq], m7
add idxd, 16
cmp idxd, wd
jl .loop_x
add dstq, strideq
add t1q, 384 * 2
add t2q, 384 * 2
dec hd
jg .loop_y
RET
| 28.331285 | 88 | 0.471905 |
b76b0e7329b61d4482ef37f744b96a8f3e082e3e | 607 | asm | Assembly | other/Fothish/lib/joypad.asm | gb-archive/really-old-stuff | ffb39a518cad47e23353b3420b88e2f3521fd3d7 | [
"Apache-2.0"
] | 10 | 2016-10-27T20:46:02.000Z | 2021-11-01T15:49:13.000Z | lib/joypad.asm | jflores82/sam | 9d13ee16a9e89d3019a9132eb3e300c025d6b809 | [
"Apache-2.0"
] | 7 | 2015-01-11T18:45:02.000Z | 2019-02-13T22:40:26.000Z | lib/joypad.asm | jflores82/sam | 9d13ee16a9e89d3019a9132eb3e300c025d6b809 | [
"Apache-2.0"
] | 2 | 2015-03-29T13:06:40.000Z | 2018-09-11T19:05:50.000Z | .ramsection "Joypad Variables" slot 3
joypad_1 db
joypad_2 db
.ends
.section "Read both joypads" free
ReadJoypads:
; Joypad reading
in a, ($DD)
ld h, a
in a, ($DC)
ld l, a
; Joypad 1
cpl
and $7F
ld (joypad_1), a
; Joypad 2
add hl, hl
add hl, hl ; Shifts top two bits from l (U/D Joypad 2) to h.
ld a, h
cpl
and $7F
ld (joypad_2), a
ret
.ends
.section "Wait for button press" free
WaitForButton:
--
ld a, (joypad_1)
and $30 ; Only considers the fire buttons
jr z, --
---
ld a, (joypad_1)
or a
jr nz, ---
ret
.ends
| 13.195652 | 65 | 0.568369 |
05f08e380c4094eda20ee08692ac3bcb7953bd9c | 1,333 | asm | Assembly | programs/oeis/010/A010965.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/010/A010965.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/010/A010965.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A010965: a(n) = binomial(n,12).
; 1,13,91,455,1820,6188,18564,50388,125970,293930,646646,1352078,2704156,5200300,9657700,17383860,30421755,51895935,86493225,141120525,225792840,354817320,548354040,834451800,1251677700,1852482996,2707475148,3910797436,5586853480,7898654920,11058116888,15338678264,21090682613,28760021745,38910617655,52251400851,69668534468,92263734836,121399651100,158753389900,206379406870,266783135710,343006888770,438729741450,558383307300,707285522580,891794789340,1119487075980,1399358844975,1742058970275,2160153123141,2668424446233,3284214703056,4027810484880,4922879481520,5996962277488,7282025622664,8815083648488,10638894058520,12802736917880,15363284301456,18385569737808,21944067106416,26123889412400,31022118677225,36749279048405,43430966148115,51209646652255,60246643120300,70724320184700,82848489359220,96851050941060,112992892764570,131567066917650,152902266958350,177366629671686,205371886988268,237377895350076,273897571557780,315502265971620,362827605867363,416579843773639,477542747740513,546585072715045,624668654531480,712857170465336,812325612855848,924370524973896,1050421051106700,1192050855750300,1350990969850340,1529143625215220,1728597141547640,1951641934005400,2200787712814600,2478781950222760,2788629694000605,3133614810784185,3517322746798575,3943664897925675
add $0,12
bin $0,12
| 222.166667 | 1,277 | 0.906227 |
3f6a675f7f9730687630048f3d3d8b6d11535f84 | 272 | asm | Assembly | programs/oeis/004/A004391.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/004/A004391.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/004/A004391.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A004391: Binomial coefficient C(8n,n-10).
; 1,88,4560,182104,6210820,190578024,5423611200,145944307080,3762079360182,93755645897200,2274048887320496,53952131116576224,1256860484360380900,28835791641008439920,653085721923526608480
mov $1,$0
add $0,10
mul $0,8
bin $0,$1
| 34 | 187 | 0.823529 |
bb565b9e73e0d75bd2c57f99f4e1bd9145c787ca | 799 | asm | Assembly | oeis/121/A121443.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/121/A121443.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/121/A121443.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A121443: Sum of divisors d of n which are odd and n/d is not divisible by 3.
; Submitted by Jamie Morken(s3)
; 1,1,3,1,6,3,8,1,9,6,12,3,14,8,18,1,18,9,20,6,24,12,24,3,31,14,27,8,30,18,32,1,36,18,48,9,38,20,42,6,42,24,44,12,54,24,48,3,57,31,54,14,54,27,72,8,60,30,60,18,62,32,72,1,84,36,68,18,72,48,72,9,74,38,93,20,96,42,80,6,81,42,84,24,108,44,90,12,90,54,112,24,96,48,120,3,98,57,108,31
mov $6,1
lpb $6
add $0,1
mov $1,1
sub $6,1
lpb $0
mov $3,$0
lpb $3
mov $4,$0
mov $7,$2
cmp $7,0
add $2,$7
mod $4,$2
cmp $4,0
cmp $4,0
mov $5,$2
add $2,2
cmp $5,1
max $4,$5
sub $3,$4
lpe
mov $5,1
lpb $0
dif $0,$2
mul $5,$2
add $5,1
sub $5,$7
lpe
mul $1,$5
lpe
lpe
mov $0,$1
| 21.594595 | 279 | 0.509387 |
67de49b4f78840c53b08653eb62f4ece4449a2c5 | 5,005 | asm | Assembly | Transynther/x86/_processed/NC/_zr_/i7-7700_9_0x48.log_21829_243.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NC/_zr_/i7-7700_9_0x48.log_21829_243.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NC/_zr_/i7-7700_9_0x48.log_21829_243.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r14
push %r15
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x9941, %rsi
lea addresses_UC_ht+0x4221, %rdi
clflush (%rsi)
nop
nop
nop
nop
nop
add $17766, %r11
mov $10, %rcx
rep movsq
nop
inc %r15
lea addresses_WT_ht+0x3ca1, %rsi
lea addresses_D_ht+0x1f55, %rdi
nop
nop
nop
nop
sub %r12, %r12
mov $59, %rcx
rep movsw
nop
nop
nop
add $33511, %r11
lea addresses_UC_ht+0x12521, %rsi
lea addresses_WT_ht+0x543d, %rdi
nop
nop
nop
nop
cmp $60669, %rbx
mov $97, %rcx
rep movsb
and $240, %r11
lea addresses_WT_ht+0x1c6a1, %rsi
lea addresses_UC_ht+0xc0c1, %rdi
nop
nop
nop
nop
nop
mfence
mov $91, %rcx
rep movsb
nop
nop
xor %r12, %r12
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %r15
pop %r14
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %rax
push %rbx
push %rcx
push %rsi
// Faulty Load
mov $0x2a509d0000000a21, %rsi
nop
nop
nop
sub $13241, %rcx
mov (%rsi), %eax
lea oracles, %rcx
and $0xff, %rax
shlq $12, %rax
mov (%rcx,%rax,1), %rax
pop %rsi
pop %rcx
pop %rbx
pop %rax
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_NC', 'AVXalign': False, 'congruent': 0, 'size': 2, 'same': False, 'NT': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_NC', 'AVXalign': False, 'congruent': 0, 'size': 4, 'same': True, 'NT': False}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'type': 'addresses_D_ht', 'congruent': 4, 'same': True}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 10, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 6, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 2, 'same': True}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 8, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 1, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 6, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 5, 'same': True}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
| 45.5 | 2,999 | 0.664735 |
7336d082262d0124b8f3046ec815be0ecf826298 | 51 | asm | Assembly | PRG/maps/World7OI.asm | narfman0/smb3_pp1 | 38a58adafff67a403591e38875e9fae943a5fe76 | [
"Unlicense"
] | null | null | null | PRG/maps/World7OI.asm | narfman0/smb3_pp1 | 38a58adafff67a403591e38875e9fae943a5fe76 | [
"Unlicense"
] | null | null | null | PRG/maps/World7OI.asm | narfman0/smb3_pp1 | 38a58adafff67a403591e38875e9fae943a5fe76 | [
"Unlicense"
] | null | null | null | .byte $00, $00, $08, $01, $00, $00, $00, $00, $00
| 25.5 | 50 | 0.431373 |
2d3e55f787e12fb81c8c9811e71be1e348e93787 | 154 | asm | Assembly | libsrc/_DEVELOPMENT/z80/c/sccz80/z80_get_int_state.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/z80/c/sccz80/z80_get_int_state.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/z80/c/sccz80/z80_get_int_state.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null |
; uint z80_get_int_state(void)
SECTION code_z80
PUBLIC z80_get_int_state
EXTERN asm_z80_get_int_state
defc z80_get_int_state = asm_z80_get_int_state
| 14 | 46 | 0.857143 |
c0416928f182cf34c57ea01c458fc9b755d79cad | 521 | asm | Assembly | libsrc/stdio/_printk.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | null | null | null | libsrc/stdio/_printk.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | null | null | null | libsrc/stdio/_printk.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | null | null | null |
MODULE _printk
SECTION code_clib
PUBLIC _printk
PUBLIC _cprintf
EXTERN asm_printf
EXTERN printk_outc
;sdcc version
_printk:
_cprintf:
ld hl,4
add hl,sp ;points to first argument
pop bc ;ret address
pop de ;fmt
push de
push bc
IF !__CPU_INTEL__
push ix ;save ix
ENDIF
push bc ;fp (we don't care about it)
ld bc,printk_outc
push bc
ld bc,0 ;flag
push bc
push de ;fmt
push hl ;argument
call asm_printf
pop bc
pop bc
pop bc
pop bc
pop bc
IF !__CPU_INTEL__
pop ix ;restore ix
ENDIF
ret
| 11.577778 | 38 | 0.71977 |
ba02f2f83bd45314c5ca4693f0231ecd02345bc6 | 138 | asm | Assembly | libsrc/_DEVELOPMENT/libgen/c/sdcc/basename_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 640 | 2017-01-14T23:33:45.000Z | 2022-03-30T11:28:42.000Z | libsrc/_DEVELOPMENT/libgen/c/sdcc/basename_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 1,600 | 2017-01-15T16:12:02.000Z | 2022-03-31T12:11:12.000Z | libsrc/_DEVELOPMENT/libgen/c/sdcc/basename_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 215 | 2017-01-17T10:43:03.000Z | 2022-03-23T17:25:02.000Z | ; char *basename(char *path)
SECTION code_string
PUBLIC _basename_fastcall
EXTERN asm_basename
defc _basename_fastcall = asm_basename
| 13.8 | 38 | 0.826087 |
a3b4e2718d67ed349e0a1014fb7838dc78a8b472 | 645 | asm | Assembly | oeis/190/A190981.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/190/A190981.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/190/A190981.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A190981: a(n) = 9*a(n-1) - 4*a(n-2), with a(0)=0, a(1)=1.
; 0,1,9,77,657,5605,47817,407933,3480129,29689429,253284345,2160801389,18434075121,157263470533,1341634934313,11445660526685,97644405002913,833017002919477,7106575406263641,60627110644694861,517217694177199185,4412450805016013221,37643186468435322249,321138874995853847357,2739677129088943337217,23372538661817074645525,199394139439997898460857,1701057100312712787565613,14511937345054423494247089,123803207704238960297961349,1056181119957932948704663785,9010417248804440697150128669
mov $2,1
lpb $0
sub $0,1
add $3,$2
add $1,$3
add $3,$1
mul $3,2
mov $2,$3
lpe
mov $0,$1
| 46.071429 | 483 | 0.812403 |
77bfedad094ae901a87adeacbf397d8e67a1b7b0 | 13,586 | asm | Assembly | enduser/netmeeting/as/cpi32.95/i386/asthkls.asm | npocmaka/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 17 | 2020-11-13T13:42:52.000Z | 2021-09-16T09:13:13.000Z | enduser/netmeeting/as/cpi32.95/i386/asthkls.asm | sancho1952007/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 2 | 2020-10-19T08:02:06.000Z | 2020-10-19T08:23:18.000Z | enduser/netmeeting/as/cpi32.95/i386/asthkls.asm | sancho1952007/Windows-Server-2003 | 5c6fe3db626b63a384230a1aa6b92ac416b0765f | [
"Unlicense"
] | 14 | 2020-11-14T09:43:20.000Z | 2021-08-28T08:59:57.000Z | page ,132
;Thunk Compiler Version 1.8 Dec 14 1994 14:53:05
;File Compiled Thu Apr 01 11:42:56 1999
;Command Line: d:\projects\cayman\dev\bin\misc\i386\thunk -t thk -o i386\asthkls.asm ..\thk\asthkls.thk
TITLE $i386\asthkls.asm
.386
OPTION READONLY
OPTION OLDSTRUCTS
IFNDEF IS_16
IFNDEF IS_32
%out command line error: specify one of -DIS_16, -DIS_32
.err
ENDIF ;IS_32
ENDIF ;IS_16
IFDEF IS_32
IFDEF IS_16
%out command line error: you can't specify both -DIS_16 and -DIS_32
.err
ENDIF ;IS_16
;************************* START OF 32-BIT CODE *************************
.model FLAT,STDCALL
;-- Import common flat thunk routines (in k32)
externDef AllocMappedBuffer :near32
externDef FreeMappedBuffer :near32
externDef MapHInstLS :near32
externDef MapHInstLS_PN :near32
externDef MapHInstSL :near32
externDef MapHInstSL_PN :near32
externDef FT_PrologPrime :near32
externDef FT_Prolog :near32
externDef FT_Thunk :near32
externDef QT_Thunk :near32
externDef QT_ThunkPrime :near32
externDef FT_Exit0 :near32
externDef FT_Exit4 :near32
externDef FT_Exit8 :near32
externDef FT_Exit12 :near32
externDef FT_Exit16 :near32
externDef FT_Exit20 :near32
externDef FT_Exit24 :near32
externDef FT_Exit28 :near32
externDef FT_Exit32 :near32
externDef FT_Exit36 :near32
externDef FT_Exit40 :near32
externDef FT_Exit44 :near32
externDef FT_Exit48 :near32
externDef FT_Exit52 :near32
externDef FT_Exit56 :near32
externDef SMapLS :near32
externDef SUnMapLS :near32
externDef SMapLS_IP_EBP_8 :near32
externDef SUnMapLS_IP_EBP_8 :near32
externDef SMapLS_IP_EBP_12 :near32
externDef SUnMapLS_IP_EBP_12 :near32
externDef SMapLS_IP_EBP_16 :near32
externDef SUnMapLS_IP_EBP_16 :near32
externDef SMapLS_IP_EBP_20 :near32
externDef SUnMapLS_IP_EBP_20 :near32
externDef SMapLS_IP_EBP_24 :near32
externDef SUnMapLS_IP_EBP_24 :near32
externDef SMapLS_IP_EBP_28 :near32
externDef SUnMapLS_IP_EBP_28 :near32
externDef SMapLS_IP_EBP_32 :near32
externDef SUnMapLS_IP_EBP_32 :near32
externDef SMapLS_IP_EBP_36 :near32
externDef SUnMapLS_IP_EBP_36 :near32
externDef SMapLS_IP_EBP_40 :near32
externDef SUnMapLS_IP_EBP_40 :near32
MapLS PROTO NEAR STDCALL :DWORD
UnMapLS PROTO NEAR STDCALL :DWORD
MapSL PROTO NEAR STDCALL p32:DWORD
;***************** START OF KERNEL32-ONLY SECTION ******************
; Hacks for kernel32 initialization.
IFDEF FT_DEFINEFTCOMMONROUTINES
.data
public FT_thkTargetTable ;Flat address of target table in 16-bit module.
public FT_thkChecksum32
FT_thkChecksum32 dd 016bddh
ENDIF ;FT_DEFINEFTCOMMONROUTINES
;***************** END OF KERNEL32-ONLY SECTION ******************
.code
;************************* COMMON PER-MODULE ROUTINES *************************
.data
;---------------------------------------------------------------
;Flat address of target table in 16-bit module name.
;Filled in by the initial handshaking routine: FT_thkConnectToFlatThkPeer
;---------------------------------------------------------------
FT_thkTargetTable dd 0 ;Flat address of target table in 16-bit module.
.code
FT_thkDynaName db 'FT_thkThkConnectionData',0
;------------------------------------------------------------
;FT_thkConnectToFlatThkPeer:;
; The 32-bit dll must call this routine once at initialization
; time. It will load the 16-bit library and fetch the pointers
; needed to make the flat thunk run.
;
; Calling sequence:
;
; FT_thkConnectToFlatThkPeer proto near stdcall, dll16:dword, dll32:dword
;
; Name16 db 'mumble16.dll',0 ;Name of 16-bit library
; Name32 db 'mumble32.dll',0 ;Name of 32-bit library
;
; invoke FT_thkConnectToFlatThkPeer offset Name16, offset Name32
; or eax,eax
; jz failed
; ;success
;
;------------------------------------------------------------
public FT_thkConnectToFlatThkPeer@8
FT_thkConnectToFlatThkPeer@8:
extern ThunkInitLSF@20:near32
pop edx ;Pop return address
push offset 016bddh ;Checksum
push offset FT_thkDynaName ;Symbol exported from peer.
push offset FT_thkTargetTable ;Address of destination.
push edx
jmp ThunkInitLSF@20
pfnQT_Thunk_thk dd offset QT_Thunk_thk
pfnFT_Prolog_thk dd offset FT_Prolog_thk
.data
QT_Thunk_thk db 0ebh, 30
db 30 dup(0cch) ;Patch space.
db 0e8h,0,0,0,0 ;CALL NEAR32 $
db 58h ;POP EAX
db 2dh,32+5,0,0,0 ;SUB EAX, IMM32
db 0bah ;MOV EDX, IMM32
dd offset FT_thkTargetTable - offset QT_Thunk_thk
db 068h ;PUSH IMM32
dd offset QT_ThunkPrime
db 0c3h ;RETN
FT_Prolog_thk db 0ebh, 30
db 30 dup(0cch) ;Patch space.
db 0e8h,0,0,0,0 ;CALL NEAR32 $
db 5ah ;POP EDX
db 81h,0eah, 32+5,0,0,0 ;SUB EDX, IMM32
db 52h ;PUSH EDX
db 068h ;PUSH IMM32
dd offset FT_thkTargetTable - offset FT_Prolog_thk
db 068h ;PUSH IMM32
dd offset FT_PrologPrime
db 0c3h ;RETN
.code
ebp_top equ <[ebp + 8]> ;First api parameter
ebp_retval equ <[ebp + -64]> ;Api return value
FT_ESPFIXUP macro dwSpOffset
or dword ptr [ebp + -20], 1 SHL ((dwSpOffset) SHR 1)
endm
ebp_qttop equ <[ebp + 8]>
include fltthk.inc ;Support definitions
include asthkls.inc
;************************ START OF THUNK BODIES************************
;
public OSILoad16@4
OSILoad16@4:
FAPILOG16 270
mov cl,11
; OSILoad16(16) = OSILoad16(32) {}
;
; dword ptr [ebp+8]: phInstance
;
public IIOSILoad16@4
IIOSILoad16@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
call SMapLS_IP_EBP_8
push eax
call dword ptr [pfnQT_Thunk_thk]
call SUnMapLS_IP_EBP_8
leave
retn 4
;
public OSIInit16@36
OSIInit16@36:
FAPILOG16 256
mov cl,10
; OSIInit16(16) = OSIInit16(32) {}
;
; dword ptr [ebp+8]: version
; dword ptr [ebp+12]: hwnd
; dword ptr [ebp+16]: atom
; dword ptr [ebp+20]: ppShared
; dword ptr [ebp+24]: ppoaShared
; dword ptr [ebp+28]: pimShared
; dword ptr [ebp+32]: psbcEnabled
; dword ptr [ebp+36]: psbcShunt
; dword ptr [ebp+40]: pBitmasks
;
public IIOSIInit16@36
IIOSIInit16@36:
push ebp
mov ebp,esp
push ecx
sub esp,60
push dword ptr [ebp+8] ;version: dword->dword
push word ptr [ebp+12] ;hwnd: dword->word
push word ptr [ebp+16] ;atom: dword->word
call SMapLS_IP_EBP_20
push eax
call SMapLS_IP_EBP_24
push eax
call SMapLS_IP_EBP_28
push eax
call SMapLS_IP_EBP_32
push eax
call SMapLS_IP_EBP_36
push eax
call SMapLS_IP_EBP_40
push eax
call dword ptr [pfnQT_Thunk_thk]
cwde
call SUnMapLS_IP_EBP_20
call SUnMapLS_IP_EBP_24
call SUnMapLS_IP_EBP_28
call SUnMapLS_IP_EBP_32
call SUnMapLS_IP_EBP_36
call SUnMapLS_IP_EBP_40
leave
retn 36
;
public OSITerm16@4
OSITerm16@4:
FAPILOG16 242
mov cl,9
; OSITerm16(16) = OSITerm16(32) {}
;
; dword ptr [ebp+8]: fUnloading
;
public IIOSITerm16@4
IIOSITerm16@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;fUnloading: dword->word
call dword ptr [pfnQT_Thunk_thk]
leave
retn 4
;
public OSIFunctionRequest16@12
OSIFunctionRequest16@12:
FAPILOG16 217
mov cl,8
; OSIFunctionRequest16(16) = OSIFunctionRequest16(32) {}
;
; dword ptr [ebp+8]: escape
; dword ptr [ebp+12]: lpvEsc
; dword ptr [ebp+16]: cbEsc
;
public IIOSIFunctionRequest16@12
IIOSIFunctionRequest16@12:
push ebp
mov ebp,esp
push ecx
sub esp,60
push dword ptr [ebp+8] ;escape: dword->dword
call SMapLS_IP_EBP_12
push eax
push dword ptr [ebp+16] ;cbEsc: dword->dword
call dword ptr [pfnQT_Thunk_thk]
cwde
call SUnMapLS_IP_EBP_12
leave
retn 12
;
public OSIStartWindowTracking16@0
OSIStartWindowTracking16@0:
FAPILOG16 188
mov cl,7
; OSIStartWindowTracking16(16) = OSIStartWindowTracking16(32) {}
;
;
public IIOSIStartWindowTracking16@0
IIOSIStartWindowTracking16@0:
push ebp
mov ebp,esp
push ecx
sub esp,60
call dword ptr [pfnQT_Thunk_thk]
cwde
leave
retn
;
public OSIStopWindowTracking16@0
OSIStopWindowTracking16@0:
FAPILOG16 160
mov cl,6
; OSIStopWindowTracking16(16) = OSIStopWindowTracking16(32) {}
;
;
public IIOSIStopWindowTracking16@0
IIOSIStopWindowTracking16@0:
push ebp
mov ebp,esp
push ecx
sub esp,60
call dword ptr [pfnQT_Thunk_thk]
leave
retn
;
public OSIShareWindow16@16
OSIShareWindow16@16:
FAPILOG16 139
mov cl,5
; OSIShareWindow16(16) = OSIShareWindow16(32) {}
;
; dword ptr [ebp+8]: hwnd
; dword ptr [ebp+12]: uType
; dword ptr [ebp+16]: fRedraw
; dword ptr [ebp+20]: fUpdate
;
public IIOSIShareWindow16@16
IIOSIShareWindow16@16:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;hwnd: dword->word
push word ptr [ebp+12] ;uType: dword->word
push word ptr [ebp+16] ;fRedraw: dword->word
push word ptr [ebp+20] ;fUpdate: dword->word
call dword ptr [pfnQT_Thunk_thk]
cwde
leave
retn 16
;
public OSIIsWindowScreenSaver16@4
OSIIsWindowScreenSaver16@4:
FAPILOG16 87
mov cl,3
; OSIIsWindowScreenSaver16(16) = OSIIsWindowScreenSaver16(32) {}
;
; dword ptr [ebp+8]: hwnd
;
public IIOSIIsWindowScreenSaver16@4
IIOSIIsWindowScreenSaver16@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;hwnd: dword->word
call dword ptr [pfnQT_Thunk_thk]
cwde
leave
retn 4
;
public OSIInstallControlledHooks16@8
OSIInstallControlledHooks16@8:
FAPILOG16 55
mov cl,2
jmp IIOSIInstallControlledHooks16@8
public OSIUnshareWindow16@8
OSIUnshareWindow16@8:
FAPILOG16 116
mov cl,4
; OSIInstallControlledHooks16(16) = OSIInstallControlledHooks16(32) {}
;
; dword ptr [ebp+8]: fInstall
; dword ptr [ebp+12]: fDesktop
;
public IIOSIInstallControlledHooks16@8
IIOSIInstallControlledHooks16@8:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;fInstall: dword->word
push word ptr [ebp+12] ;fDesktop: dword->word
call dword ptr [pfnQT_Thunk_thk]
cwde
leave
retn 8
;
public OSIInjectMouseEvent16@20
OSIInjectMouseEvent16@20:
FAPILOG16 29
mov cl,1
; OSIInjectMouseEvent16(16) = OSIInjectMouseEvent16(32) {}
;
; dword ptr [ebp+8]: param1
; dword ptr [ebp+12]: param2
; dword ptr [ebp+16]: param3
; dword ptr [ebp+20]: param4
; dword ptr [ebp+24]: param5
;
public IIOSIInjectMouseEvent16@20
IIOSIInjectMouseEvent16@20:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;param1: dword->word
push word ptr [ebp+12] ;param2: dword->word
push word ptr [ebp+16] ;param3: dword->word
push word ptr [ebp+20] ;param4: dword->word
push dword ptr [ebp+24] ;param5: dword->dword
call dword ptr [pfnQT_Thunk_thk]
leave
retn 20
;
public OSIInjectKeyboardEvent16@16
OSIInjectKeyboardEvent16@16:
FAPILOG16 0
mov cl,0
; OSIInjectKeyboardEvent16(16) = OSIInjectKeyboardEvent16(32) {}
;
; dword ptr [ebp+8]: param1
; dword ptr [ebp+12]: param2
; dword ptr [ebp+16]: param3
; dword ptr [ebp+20]: param4
;
public IIOSIInjectKeyboardEvent16@16
IIOSIInjectKeyboardEvent16@16:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;param1: dword->word
push word ptr [ebp+12] ;param2: dword->word
push word ptr [ebp+16] ;param3: dword->word
push dword ptr [ebp+20] ;param4: dword->dword
call dword ptr [pfnQT_Thunk_thk]
leave
retn 16
;-----------------------------------------------------------
ifdef DEBUG
FT_ThunkLogNames label byte
db '[F] OSIInjectKeyboardEvent16',0
db '[F] OSIInjectMouseEvent16',0
db '[F] OSIInstallControlledHooks16',0
db '[F] OSIIsWindowScreenSaver16',0
db '[F] OSIUnshareWindow16',0
db '[F] OSIShareWindow16',0
db '[F] OSIStopWindowTracking16',0
db '[F] OSIStartWindowTracking16',0
db '[F] OSIFunctionRequest16',0
db '[F] OSITerm16',0
db '[F] OSIInit16',0
db '[F] OSILoad16',0
endif ;DEBUG
;-----------------------------------------------------------
ELSE
;************************* START OF 16-BIT CODE *************************
OPTION SEGMENT:USE16
.model LARGE,PASCAL
.code
externDef OSIInjectKeyboardEvent16:far16
externDef OSIInjectMouseEvent16:far16
externDef OSIInstallControlledHooks16:far16
externDef OSIIsWindowScreenSaver16:far16
externDef OSIUnshareWindow16:far16
externDef OSIShareWindow16:far16
externDef OSIStopWindowTracking16:far16
externDef OSIStartWindowTracking16:far16
externDef OSIFunctionRequest16:far16
externDef OSITerm16:far16
externDef OSIInit16:far16
externDef OSILoad16:far16
FT_thkTargetTable label word
dw offset OSIInjectKeyboardEvent16
dw seg OSIInjectKeyboardEvent16
dw offset OSIInjectMouseEvent16
dw seg OSIInjectMouseEvent16
dw offset OSIInstallControlledHooks16
dw seg OSIInstallControlledHooks16
dw offset OSIIsWindowScreenSaver16
dw seg OSIIsWindowScreenSaver16
dw offset OSIUnshareWindow16
dw seg OSIUnshareWindow16
dw offset OSIShareWindow16
dw seg OSIShareWindow16
dw offset OSIStopWindowTracking16
dw seg OSIStopWindowTracking16
dw offset OSIStartWindowTracking16
dw seg OSIStartWindowTracking16
dw offset OSIFunctionRequest16
dw seg OSIFunctionRequest16
dw offset OSITerm16
dw seg OSITerm16
dw offset OSIInit16
dw seg OSIInit16
dw offset OSILoad16
dw seg OSILoad16
; The following symbol must be exported in the .def file.
public FT_thkThkConnectionData
FT_thkThkConnectionData label dword
dd 016bddh ;Checksum
dw offset FT_thkTargetTable
dw seg FT_thkTargetTable
ENDIF
END
| 21.948304 | 105 | 0.695275 |
dfdb262de859288b9feff68582af156833952659 | 3,740 | asm | Assembly | src/drivers/OPL3.asm | sharksym/vgmplay-sharksym | d7763b87a379da4e6dadcc55026969d310957952 | [
"BSD-2-Clause"
] | 6 | 2020-04-21T17:26:27.000Z | 2021-09-25T18:41:01.000Z | src/drivers/OPL3.asm | sharksym/vgmplay-sharksym | d7763b87a379da4e6dadcc55026969d310957952 | [
"BSD-2-Clause"
] | null | null | null | src/drivers/OPL3.asm | sharksym/vgmplay-sharksym | d7763b87a379da4e6dadcc55026969d310957952 | [
"BSD-2-Clause"
] | null | null | null | ;
; YMF262 OPL3
;
OPL3_BASE_PORT: equ 0C0H
OPL3_STATUS: equ 00H
OPL3_FM_ADDRESS: equ 00H
OPL3_FM_DATA: equ 01H
OPL3_FM2_ADDRESS: equ 02H
OPL3_FM2_DATA: equ 03H
OPL3_FM2_NEW: equ 05H
OPL3_CLOCK: equ 14318182
OPL3_TIMER_1: equ 02H
OPL3_FLAG_CONTROL: equ 04H
OPL3: MACRO ?base = OPL3_BASE_PORT, ?name = OPL3_name
this:
super: Driver ?name, OPL3_CLOCK, Driver_PrintInfoImpl
; e = register
; d = value
SafeWriteRegister:
ld a,e
cp 20H
jr c,MaskControl
; a = register
; d = value
WriteRegister:
di
out (?base + OPL3_FM_ADDRESS),a
basePort: equ $ - 1
cp (hl) ; wait 32 / 14.32 µs
ld a,d
ei
out (?base + OPL3_FM_DATA),a
ret
MaskControl:
cp 8H
jr z,WriteRegister
cp 1H
ret nz
MaskTest:
ld a,d
and 00100000B ; pass waveform select enable for OPL2s
ld d,a
ld a,e
jr WriteRegister
; e = register
; d = value
SafeWriteRegister2:
ld a,e
; a = register
; d = value
WriteRegister2:
di
out (?base + OPL3_FM2_ADDRESS),a
cp (hl) ; wait 32 / 14.32 µs
ld a,d
ei
out (?base + OPL3_FM2_DATA),a
ret
; a <- value
ReadRegisterStatus:
in a,(?base + OPL3_STATUS)
ret
ENDM
; ix = this
; iy = drivers
OPL3_Construct:
call Driver_Construct
call OPL3_Detect
jp nc,Driver_NotFound
jr OPL3_Reset
; ix = this
OPL3_Destruct:
call Driver_IsFound
ret nc
jr OPL3_Mute
; e = register
; d = value
; ix = this
OPL3_WriteRegister:
ld a,e
ld bc,OPL3.WriteRegister
jp Utils_JumpIXOffsetBC
; e = register
; d = value
; ix = this
OPL3_WriteRegister2:
ld a,e
ld bc,OPL3.WriteRegister2
jp Utils_JumpIXOffsetBC
; ix = this
; a <- value
OPL3_ReadRegisterStatus:
ld bc,OPL3.ReadRegisterStatus
jp Utils_JumpIXOffsetBC
; b = count
; e = register base
; d = value
; ix = this
OPL3_FillRegisterPairs:
push bc
push de
call OPL3_WriteRegister
pop de
push de
call OPL3_WriteRegister2
pop de
pop bc
inc e
djnz OPL3_FillRegisterPairs
ret
; ix = this
OPL3_Mute:
ld de,00BDH
call OPL3_WriteRegister ; rhythm off
ld b,16H
ld de,0F80H
call OPL3_FillRegisterPairs ; max release rate
ld b,16H
ld de,3F40H
call OPL3_FillRegisterPairs ; min total level
ld b,09H
ld de,00A0H
call OPL3_FillRegisterPairs ; frequency 0
ld b,09H
ld de,00B0H
jr OPL3_FillRegisterPairs ; key off
; ix = this
OPL3_Reset:
ld de,00000001B << 8 | OPL3_FM2_NEW
call OPL3_WriteRegister2
ld b,0D6H
ld de,0020H
call OPL3_FillRegisterPairs
ld de,0001H
call OPL3_WriteRegister
ld de,0008H
call OPL3_WriteRegister
ld de,0004H
call OPL3_WriteRegister2
ld de,00000000B << 8 | OPL3_FM2_NEW
jr OPL3_WriteRegister2
; ix = this
; f <- c: Found
OPL3_Detect:
ld c,(ix + OPL3.basePort)
; c = base I/O port
; f <- c: Found
; c <- base I/O port
OPL3_DetectPort: PROC
in a,(c)
and 11111101B ; if OPL4 bit 1 can be set
ret nz
di
ld de,10000000B << 8 | OPL3_FLAG_CONTROL
call WriteRegister
ld de,0FFH << 8 | OPL3_TIMER_1 ; detect with timer
call WriteRegister
ld de,00111001B << 8 | OPL3_FLAG_CONTROL
call WriteRegister
ld de,10000000B << 8 | MSXAudio_ADPCM_CONTROL ; ensure it’s no MSX-AUDIO
call WriteRegister
ld b,0 ; wait >80 µs
djnz $
in a,(c)
push af
ld de,01111000B << 8 | OPL3_FLAG_CONTROL
call WriteRegister
ld de,00000000B << 8 | MSXAudio_ADPCM_CONTROL
call WriteRegister
ei
pop af
and 11111101B ; if OPL4 bit 1 can be set
xor 11000000B
ret nz
scf
ret
WriteRegister:
out (c),e
in a,(c) ; wait 12 / 3.58 µs (in case of MSX-AUDIO)
cp (hl) ; "
inc c
out (c),d
dec c
ret
ENDP
;
SECTION RAM
OPL3_instance: OPL3
ENDS
OPL3_interface:
InterfaceOffset OPL3.SafeWriteRegister
InterfaceOffset OPL3.SafeWriteRegister2
OPL3_interfaceY8950:
InterfaceOffset OPL3.SafeWriteRegister
InterfaceAddress Player_SkipDataBlock
OPL3_name:
db "OPL3",0
| 17.235023 | 74 | 0.716845 |
5ab077d3ca59f4c7d79072d7a54b0a343d0cd041 | 2,997 | asm | Assembly | source/tokeniser/tokenise/tokident.asm | paulscottrobson/6502-basic | d4c360041bfa49427a506465e58bb0ef94beaa44 | [
"MIT"
] | 3 | 2021-09-30T19:34:11.000Z | 2021-10-31T06:55:50.000Z | source/tokeniser/tokenise/tokident.asm | paulscottrobson/6502-Basic | d4c360041bfa49427a506465e58bb0ef94beaa44 | [
"MIT"
] | null | null | null | source/tokeniser/tokenise/tokident.asm | paulscottrobson/6502-Basic | d4c360041bfa49427a506465e58bb0ef94beaa44 | [
"MIT"
] | 1 | 2021-12-07T21:58:44.000Z | 2021-12-07T21:58:44.000Z | ; ************************************************************************************************
; ************************************************************************************************
;
; Name: tokident.asm
; Purpose: Tokenise identifier
; Created: 9th March 2021
; Reviewed: 16th March 2021
; Author: Paul Robson (paul@robsons.org.uk)
;
; ************************************************************************************************
; ************************************************************************************************
.section code
; ************************************************************************************************
;
; Tokenise identifier at (codePtr) into a token/identifier
; CS if tokenising successful.
;
; ************************************************************************************************
TokeniseIdentifier:
;
; Firstly copy identifier to convertBuffer. We know the first letter is A-Z.
;
ldx #0
_TICopyID:
lda (codePtr),y ; get characters
cmp #"_" ; underscore converted to minus internally.
beq _TICopyUnderscore
cmp #"."
beq _TICopyIn
cmp #"0"
bcc _TIEndCopy
cmp #"9"+1
bcc _TICopyIn
cmp #"A"
bcc _TIEndCopy
cmp #"Z"+1
bcs _TIEndCopy
bcc _TICopyIn
_TICopyUnderScore:
lda #"-" ; _ is mapped to -
_TICopyIn:
inx ; write into buffer in 7 bit ASCII form
sta convertBuffer,x
stx convertBuffer
iny ; next character
jmp _TICopyID ; loop round
_TIEndCopy:
;
; Check if followed by $/# then (, copy as is. We check the 'full ASCII' against
; the token tables, and convert to the $3A-$3F endings later.
;
lda #"$"
jsr TIDCheckCopy
lda #"#"
jsr TIDCheckCopy
lda #"("
jsr TIDCheckCopy
;
; Is it a token
;
jsr TokenSearch ; is it a token
bcs _TIExit ; if so, then exit.
;
; Convert the ending #$( to the $3A-$3F end of identifier markers.
;
.pshy ; save Y
ldy #$3A ; default type.
ldx convertBuffer ; is last character (
lda convertBuffer,x
cmp #"("
bne _TINotArray
dex ; yes, remove it and convert to array.
iny
_TINotArray:
lda convertBuffer,x ; check for $
cmp #"$"
bne _TINotString
dex
iny
iny
_TINotString:
lda convertBuffer,x ; check for #
cmp #"#"
bne _TINotFloat
dex
iny
iny
iny
iny
_TINotFloat:
inx ; write end marker for identifier.
tya
sta convertBuffer,x
stx convertBuffer ; update length.
;
; Copy into tokenise buffer
;
ldx #1
_TIOutput:
lda convertBuffer,x
and #$3F
pha
jsr TokenWrite
inx
pla
cmp #$3A
bcc _TIOutput
.puly
_TIExit:
sec ; this can't fail.
rts
;
; If next character in stream is A, then copy it to the convertBuffer
;
TIDCheckCopy:
cmp (codePtr),y
bne _TIDCCExit
inx
sta convertBuffer,x
stx convertBuffer
iny
_TIDCCExit:
rts
.send code | 23.232558 | 98 | 0.498832 |
9f819c0dfc61dd123d89221bd6cd6e52e9094fa3 | 827 | asm | Assembly | oeis/188/A188557.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/188/A188557.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/188/A188557.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A188557: Number of 6 X n binary arrays without the pattern 0 1 diagonally, vertically, antidiagonally or horizontally.
; 7,13,24,44,80,144,256,448,769,1291,2116,3384,5282,8054,12012,17548,25147,35401,49024,66868,89940,119420,156680,203304,261109,332167,418828,523744,649894,800610,979604,1190996,1439343,1729669,2067496,2458876,2910424,3429352,4023504,4701392,5472233,6345987,7333396,8446024,9696298,11097550,12664060,14411100,16354979,18513089,20903952,23547268,26463964,29676244,33207640,37083064,41328861,45972863,51044444,56574576,62595886,69142714,76251172,83959204,92306647,101335293,111088952,121613516,132957024
lpb $0
sub $0,1
mov $2,$0
max $2,0
seq $2,188556 ; Number of 5 X n binary arrays without the pattern 0 1 diagonally, vertically, antidiagonally or horizontally.
add $1,$2
lpe
add $1,7
mov $0,$1
| 63.615385 | 500 | 0.802902 |
06794baef81d51b2d2915e9f8f4562d6c7e39475 | 4,914 | asm | Assembly | OvmfPkg/ResetVector/Ia32/IntelTdx.asm | nicklela/edk2 | dfafa8e45382939fb5dc78e9d37b97b500a43613 | [
"Python-2.0",
"Zlib",
"BSD-2-Clause",
"MIT",
"BSD-2-Clause-Patent",
"BSD-3-Clause"
] | 3,012 | 2015-01-01T19:58:18.000Z | 2022-03-31T22:07:14.000Z | OvmfPkg/ResetVector/Ia32/IntelTdx.asm | nicklela/edk2 | dfafa8e45382939fb5dc78e9d37b97b500a43613 | [
"Python-2.0",
"Zlib",
"BSD-2-Clause",
"MIT",
"BSD-2-Clause-Patent",
"BSD-3-Clause"
] | 1,199 | 2015-01-12T08:00:01.000Z | 2022-03-29T18:14:42.000Z | OvmfPkg/ResetVector/Ia32/IntelTdx.asm | nicklela/edk2 | dfafa8e45382939fb5dc78e9d37b97b500a43613 | [
"Python-2.0",
"Zlib",
"BSD-2-Clause",
"MIT",
"BSD-2-Clause-Patent",
"BSD-3-Clause"
] | 1,850 | 2015-01-01T11:28:12.000Z | 2022-03-31T18:10:59.000Z | ;------------------------------------------------------------------------------
; @file
; Intel TDX routines
;
; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
%define VM_GUEST_TDX 2
BITS 32
;
; Check if it is Intel Tdx
;
; Modified: EAX, EBX, ECX, EDX
;
; If it is Intel Tdx, EAX is 1
; If it is not Intel Tdx, EAX is 0
;
IsTdx:
;
; CPUID (0)
;
mov eax, 0
cpuid
cmp ebx, 0x756e6547 ; "Genu"
jne IsNotTdx
cmp edx, 0x49656e69 ; "ineI"
jne IsNotTdx
cmp ecx, 0x6c65746e ; "ntel"
jne IsNotTdx
;
; CPUID (1)
;
mov eax, 1
cpuid
test ecx, 0x80000000
jz IsNotTdx
;
; CPUID[0].EAX >= 0x21?
;
mov eax, 0
cpuid
cmp eax, 0x21
jl IsNotTdx
;
; CPUID (0x21,0)
;
mov eax, 0x21
mov ecx, 0
cpuid
cmp ebx, 0x65746E49 ; "Inte"
jne IsNotTdx
cmp edx, 0x5844546C ; "lTDX"
jne IsNotTdx
cmp ecx, 0x20202020 ; " "
jne IsNotTdx
mov eax, 1
jmp ExitIsTdx
IsNotTdx:
xor eax, eax
ExitIsTdx:
OneTimeCallRet IsTdx
;
; Initialize work area if it is Tdx guest. Detailed definition is in
; OvmfPkg/Include/WorkArea.h.
; BSP and APs all go here. Only BSP initialize this work area.
;
; Param[in] EBX[5:0] CPU Supported GPAW (48 or 52)
; Param[in] ESI[31:0] vCPU ID (BSP is 0, others are AP)
;
; Modified: EBX
;
InitTdxWorkarea:
;
; First check if it is Tdx
;
OneTimeCall IsTdx
test eax, eax
jz ExitInitTdxWorkarea
cmp esi, 0
je TdxBspEntry
;
; In Td guest, BSP/AP shares the same entry point
; BSP builds up the page table, while APs shouldn't do the same task.
; Instead, APs just leverage the page table which is built by BSP.
; APs will wait until the page table is ready.
;
TdxApWait:
cmp byte[TDX_WORK_AREA_PGTBL_READY], 0
je TdxApWait
jmp ExitInitTdxWorkarea
TdxBspEntry:
;
; Set Type of WORK_AREA_GUEST_TYPE so that the following code can use
; these information.
;
mov byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX
;
; EBX[5:0] CPU supported GPA width
;
and ebx, 0x3f
mov DWORD[TDX_WORK_AREA_GPAW], ebx
ExitInitTdxWorkarea:
OneTimeCallRet InitTdxWorkarea
;
; Load the GDT and set the CS/DS/ES/FS/GS/SS.
;
; Modified: EAX, DS, ES, FS, GS, SS, CS
;
ReloadFlat32:
cli
mov eax, ADDR_OF(gdtr)
lgdt [eax]
jmp LINEAR_CODE_SEL:dword ADDR_OF(jumpToFlat32BitAndLandHere)
jumpToFlat32BitAndLandHere:
debugShowPostCode POSTCODE_32BIT_MODE
mov ax, LINEAR_SEL
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
OneTimeCallRet ReloadFlat32
;
; Tdx initialization after entering into ResetVector
;
; Modified: EAX, EBX, ECX, EDX, EBP, EDI, ESP
;
InitTdx:
;
; First load the GDT and jump to Flat32 mode
;
OneTimeCall ReloadFlat32
;
; Initialization of Tdx work area
;
OneTimeCall InitTdxWorkarea
OneTimeCallRet InitTdx
;
; Check TDX features, TDX or TDX-BSP or TDX-APs?
;
; By design TDX BSP is reponsible for initializing the PageTables.
; After PageTables are ready, byte[TDX_WORK_AREA_PGTBL_READY] is set to 1.
; APs will spin when byte[TDX_WORK_AREA_PGTBL_READY] is 0 until it is set to 1.
;
; When this routine is run on TDX BSP, byte[TDX_WORK_AREA_PGTBL_READY] should be 0.
; When this routine is run on TDX APs, byte[TDX_WORK_AREA_PGTBL_READY] should be 1.
;
;
; Modified: EAX, EDX
;
; 0-NonTdx, 1-TdxBsp, 2-TdxAps
;
CheckTdxFeaturesBeforeBuildPagetables:
xor eax, eax
cmp byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX
jne NotTdx
xor edx, edx
mov al, byte[TDX_WORK_AREA_PGTBL_READY]
inc eax
NotTdx:
OneTimeCallRet CheckTdxFeaturesBeforeBuildPagetables
;
; Set byte[TDX_WORK_AREA_PGTBL_READY] to 1
;
TdxPostBuildPageTables:
cmp byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX
jne ExitTdxPostBuildPageTables
mov byte[TDX_WORK_AREA_PGTBL_READY], 1
ExitTdxPostBuildPageTables:
OneTimeCallRet TdxPostBuildPageTables
;
; Check if TDX is enabled
;
; Modified: EAX
;
; If TDX is enabled then EAX will be 1
; If TDX is disabled then EAX will be 0.
;
IsTdxEnabled:
xor eax, eax
cmp byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX
jne TdxNotEnabled
mov eax, 1
TdxNotEnabled:
OneTimeCallRet IsTdxEnabled
| 22.035874 | 84 | 0.590354 |
5f17f85bcdff67306b70d9be930fa8c811dfe9a7 | 1,228 | asm | Assembly | unordnung_auch_assembler/asm/attiny13/versuche/twoTonesFromMemory.asm | no-go/Blink_atmega328p | a81e41906c4a6d843a7fb87962288a0894105bd7 | [
"Unlicense"
] | null | null | null | unordnung_auch_assembler/asm/attiny13/versuche/twoTonesFromMemory.asm | no-go/Blink_atmega328p | a81e41906c4a6d843a7fb87962288a0894105bd7 | [
"Unlicense"
] | null | null | null | unordnung_auch_assembler/asm/attiny13/versuche/twoTonesFromMemory.asm | no-go/Blink_atmega328p | a81e41906c4a6d843a7fb87962288a0894105bd7 | [
"Unlicense"
] | null | null | null | ; atTINY 13 - Board without 7seg display
.equ PORTB, 0x18
.equ DDRB, 0x17
.equ PINB, 0x16
.equ TCCR0B, 0x33
.equ TCNT0, 0x32
Z = 30
ZH = 31
ZL = 30
.section .text
ldi r16, 0b00010000 ; Pin 4 is output
out DDRB, r16
Start: ldi ZL, lo8(TTTT)
ldi ZH, hi8(TTTT)
lpm ; r0 :=(Z)
Next: mov r17, r0 ; copy r0 to tonefreq register = r17
cpi r17, 0xFF ; Last Tone?
breq Start
rcall Tone
rcall Tone
rcall Tone
rcall Tone
adiw Z, 1 ; next toneon address Z := Z+1
lpm ; load the value from 30:31 16bit Register Z Adress to r0
rjmp Next
; Subroutine
Tone:
push r17
push r16
ldi r16, 81 ; dauer
sub r16, r17 ; dauer = 90 - ton(30 bis 80)
lsl r16 ; *2
lsl r16 ; *2
Lenght: rcall Toggle
rcall Waiter
dec r16
brne Lenght
pop r16 ; wiederherstellen
pop r17
ret
; Subroutine
Waiter:
push r17
WLoop: dec r17 ; zeit zwischen toggles = ton
brne WLoop
pop r17
ret
; Subroutine Toggle() toggles a bit
Toggle:
push r17
push r18
ldi r18, 0b00010000 ; bitmask
in r17, PORTB
eor r18, r17 ; r18 := r18 XOR r17
out PORTB, r18
pop r18
pop r17
ret
TTTT:
.byte 30,50,0xFF
| 17.542857 | 69 | 0.60342 |
3433913700a40a29df22856e8d4fcece8c0c675f | 729 | asm | Assembly | oeis/015/A015183.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/015/A015183.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/015/A015183.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A015183: Sum of (Gaussian) q-binomial coefficients for q=-16.
; Submitted by Christian Krause
; 1,2,-13,484,54229,31827398,-56799627337,533861499881896,15248101644637051801,2292948178255678956694922,-1047836980355690810689170063493,2521121088203661718431826043956531564,18433748144879610463916823544633620321231709,709632536454363162004311139704656093555312045077838,-83018219857056331122908240504064302293862680150503837333697,51134413061897157258676432583592890317400202813522982851193634937136,95713491049648232170915698673940279878816969864034969226034419535529034558241
mov $1,$0
mov $0,0
add $1,1
mov $2,1
mov $3,1
lpb $1
sub $1,1
mov $4,$2
mul $2,-16
mul $4,$3
add $0,$4
sub $3,$4
add $3,$0
lpe
mov $0,$3
| 36.45 | 480 | 0.828532 |
92adcadb7e5f128fe3d9f345701376e76e1f896a | 493 | asm | Assembly | programs/oeis/083/A083337.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/083/A083337.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | programs/oeis/083/A083337.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | ; A083337: a(n) = 2*a(n-1) + 2*a(n-2); a(0)=0, a(1)=3.
; 0,3,6,18,48,132,360,984,2688,7344,20064,54816,149760,409152,1117824,3053952,8343552,22795008,62277120,170144256,464842752,1269974016,3469633536,9479215104,25897697280,70753824768,193303044096,528113737728,1442833563648,3941894602752,10769456332800,29422701871104,80384316407808,219614036557824,599996705931264,1639221484978176,4478436381818880
mov $2,3
lpb $0
sub $0,1
add $1,$2
mov $3,$2
mov $2,$1
add $2,$1
mov $1,$3
lpe
| 37.923077 | 345 | 0.754564 |
94017c1604a1df9527b8b7ccd5ade5e44072eb77 | 314 | asm | Assembly | libsrc/_DEVELOPMENT/stdio/c/sdcc_ix/open_memstream_callee.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/stdio/c/sdcc_ix/open_memstream_callee.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/stdio/c/sdcc_ix/open_memstream_callee.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null |
; FILE *open_memstream_callee(char **bufp, size_t *sizep)
SECTION code_stdio
PUBLIC _open_memstream_callee, l0_open_memstream_callee
EXTERN asm_open_memstream
_open_memstream_callee:
pop hl
pop de
ex (sp),hl
l0_open_memstream_callee:
push ix
call asm_open_memstream
pop ix
ret
| 13.083333 | 57 | 0.748408 |
b77f7213ab26790bcb8533d07f4083d042419214 | 864 | asm | Assembly | src/test/ref/index-pointer-rewrite-4.asm | jbrandwood/kickc | d4b68806f84f8650d51b0e3ef254e40f38b0ffad | [
"MIT"
] | 2 | 2022-03-01T02:21:14.000Z | 2022-03-01T04:33:35.000Z | src/test/ref/index-pointer-rewrite-4.asm | jbrandwood/kickc | d4b68806f84f8650d51b0e3ef254e40f38b0ffad | [
"MIT"
] | null | null | null | src/test/ref/index-pointer-rewrite-4.asm | jbrandwood/kickc | d4b68806f84f8650d51b0e3ef254e40f38b0ffad | [
"MIT"
] | null | null | null | // Test array index pointer rewriting
// 8bit array with 8bit index
// Fibonacci calculation uses adjacent indices inside the loop
// Commodore 64 PRG executable file
.file [name="index-pointer-rewrite-4.prg", type="prg", segments="Program"]
.segmentdef Program [segments="Basic, Code, Data"]
.segmentdef Basic [start=$0801]
.segmentdef Code [start=$80d]
.segmentdef Data [startAfter="Code"]
.segment Basic
:BasicUpstart(main)
.segment Code
main: {
// fibs[0] = 0
lda #0
sta fibs
// fibs[1] = 1
lda #1
sta fibs+1
ldx #0
__b1:
// for(char i=0;i<NUM_FIBS-2;i++)
cpx #$19-2
bcc __b2
// }
rts
__b2:
// fibs[i]+fibs[i+1]
lda fibs,x
clc
adc fibs+1,x
// fibs[i+2] = fibs[i]+fibs[i+1]
sta fibs+2,x
// for(char i=0;i<NUM_FIBS-2;i++)
inx
jmp __b1
}
.segment Data
fibs: .fill $19, 0
| 21.6 | 74 | 0.615741 |
304a92c4a5df49acf8130351280ab64fcc29d3af | 652 | asm | Assembly | oeis/236/A236856.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/236/A236856.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/236/A236856.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A236856: Partial sums of A003418 starting summing from A003418(1), with a(0) = 0.
; Submitted by Christian Krause
; 0,1,3,9,21,81,141,561,1401,3921,6441,34161,61881,422241,782601,1142961,1863681,14115921,26368161,259160721,491953281,724745841,957538401,6311767281,11665996161,38437140561,65208284961,145521718161,225835151361,2554924714161,4884014276961,77085790723761,221489343617361,365892896510961,510296449404561,654700002298161,799103555191761,6142035012254961,11484966469318161,16827897926381361,22170829383444561,241231019123035761,460291208862626961,9879879367665048561,19299467526467470161
seq $0,173185 ; Partial sums of A003418.
sub $0,1
| 93.142857 | 484 | 0.858896 |
4df98fd441219e2d6322dca950d61bd5b82e9b6f | 148 | asm | Assembly | other.7z/NEWS.7z/NEWS/テープリストア/NEWS_05/NEWS_05.tar/home/kimura/kart/risc.lzh/risc/join/w-select-e.asm | prismotizm/gigaleak | d082854866186a05fec4e2fdf1def0199e7f3098 | [
"MIT"
] | null | null | null | other.7z/NEWS.7z/NEWS/テープリストア/NEWS_05/NEWS_05.tar/home/kimura/kart/risc.lzh/risc/join/w-select-e.asm | prismotizm/gigaleak | d082854866186a05fec4e2fdf1def0199e7f3098 | [
"MIT"
] | null | null | null | other.7z/NEWS.7z/NEWS/テープリストア/NEWS_05/NEWS_05.tar/home/kimura/kart/risc.lzh/risc/join/w-select-e.asm | prismotizm/gigaleak | d082854866186a05fec4e2fdf1def0199e7f3098 | [
"MIT"
] | null | null | null | Name: w-select-e.asm
Type: file
Size: 25167
Last-Modified: '1992-11-18T01:42:36Z'
SHA-1: CCD6F4B2D6DF7A560ADCDEE8BCE11A3C9A6CE009
Description: null
| 21.142857 | 47 | 0.804054 |
975740a8bf906049e9b5a5f4514fb397e79038a9 | 204 | asm | Assembly | hello/hello.asm | zhamao-robot/hello-example | 0442734f37991440f7478c43edc6b4d211af33a1 | [
"WTFPL"
] | null | null | null | hello/hello.asm | zhamao-robot/hello-example | 0442734f37991440f7478c43edc6b4d211af33a1 | [
"WTFPL"
] | null | null | null | hello/hello.asm | zhamao-robot/hello-example | 0442734f37991440f7478c43edc6b4d211af33a1 | [
"WTFPL"
] | null | null | null | section .data
msg db "hello world", 0ah
section .text
global _start
_start:
mov rax, 1
mov rdi, 1
mov rsi, msg
mov rdx, 13
syscall
mov rax, 60
mov rdi, 0
syscall
| 12.75 | 29 | 0.578431 |
5895e1d601c34eed9c20a895b5a84881a8d89d14 | 605 | asm | Assembly | programs/oeis/031/A031381.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/031/A031381.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/031/A031381.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A031381: a(n) = prime(7*n - 2).
; 11,37,67,101,137,173,211,251,283,337,379,421,461,503,563,601,643,683,739,787,829,881,937,983,1031,1069,1117,1181,1229,1283,1319,1399,1447,1487,1543,1583,1621,1693,1741,1789,1867,1907,1979,2017,2081,2129,2179,2243,2293,2347,2389,2441,2521,2579,2647,2687,2719,2777,2833,2887,2953,3011,3067,3137,3203,3257,3319,3361,3433,3491,3539,3583,3637,3697,3761,3821,3877,3923,4001,4049,4099,4157,4229,4271,4339,4409,4463,4519,4591,4649,4703,4783,4817,4909,4957,5003,5059,5113,5189,5261
mul $0,7
add $0,3
seq $0,98090 ; Numbers k such that 2k-3 is prime.
sub $0,5
mul $0,2
add $0,7
| 60.5 | 474 | 0.743802 |
ac4cfb941e1fc6916329771d65a45b874014a24d | 633 | asm | Assembly | oeis/206/A206809.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/206/A206809.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/206/A206809.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A206809: Sum_{0<j<k<=n} k^3-j^3.
; 7,52,208,608,1463,3080,5880,10416,17391,27676,42328,62608,89999,126224,173264,233376,309111,403332,519232,660352,830599,1034264,1276040,1561040,1894815,2283372,2733192,3251248,3845023,4522528,5292320,6163520,7145831,8249556,9485616,10865568,12401623,14106664,15994264,18078704,20374991,22898876,25666872,28696272,32005167,35612464,39537904,43802080,48426455,53433380,58846112,64688832,70986663,77765688,85052968,92876560,101265535,110249996,119861096,130131056,141093183,152781888,165232704
lpb $0
mov $2,$0
sub $0,1
seq $2,206808 ; Sum_{0<j<n} n^3-j^3.
add $1,$2
lpe
add $1,7
mov $0,$1
| 52.75 | 492 | 0.789889 |
208e5257a6061c2d9491bf4cb4c19f4fc8ab2808 | 489 | asm | Assembly | programs/oeis/003/A003688.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/003/A003688.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/003/A003688.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A003688: a(n) = 3*a(n-1) + a(n-2), with a(1)=1 and a(2)=4.
; 1,4,13,43,142,469,1549,5116,16897,55807,184318,608761,2010601,6640564,21932293,72437443,239244622,790171309,2609758549,8619446956,28468099417,94023745207,310539335038,1025641750321,3387464586001,11188035508324,36951571110973,122042748841243,403079817634702,1331282201745349,4396926422870749
mov $2,1
mov $4,1
lpb $0,1
sub $0,1
mov $3,$2
mov $2,$4
add $3,$4
add $1,$3
add $4,$1
mov $1,$4
add $4,1
lpe
add $1,1
| 28.764706 | 292 | 0.719836 |
f571e6ce2b47eea979e8e14ef6299787a683f3cd | 969 | asm | Assembly | programs/oeis/215/A215465.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/215/A215465.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/215/A215465.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A215465: a(n) = (Lucas(4n) - Lucas(2n))/4.
; 0,1,10,76,540,3751,25840,177451,1217160,8344876,57202750,392089501,2687463360,18420257701,126254611990,865362736876,5931286406640,40653646980451,278644255208560,1909856172864751,13090349042248500,89722587351700876,614967763018732210,4215051755347822201,28890394528522141440,198017709955057125001,1357233575185021486690,9302617316413774584076,63761087639904300755460,437024996163421349862751,2995413885505367305606000,20530872202377611242187251,140720691531146973590806560,964513968515674929043956076,6610877088078639642967276390,45311625648034965186327652501,310570502448166542391877922240,2128681891489131946133872022701,14590202737975759998545837264110,100002737274341195683111767688876,685428958182412629783510262119000,4697999970002547265162856464964251,32200570831835418363440400460530160,220705995852845381637810296764624951
seq $0,5248 ; Bisection of Lucas numbers: a(n) = L(2*n) = A000032(2*n).
bin $0,2
div $0,2
| 138.428571 | 832 | 0.893705 |
786999447be8a5b9375aebdcecd8f642ed02e6ba | 2,820 | asm | Assembly | libsrc/_DEVELOPMENT/fcntl/z80/drivers/terminal/console_01/input/console_01_input_terminal/console_01_input_stdio_msg_ictl.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/fcntl/z80/drivers/terminal/console_01/input/console_01_input_terminal/console_01_input_stdio_msg_ictl.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/fcntl/z80/drivers/terminal/console_01/input/console_01_input_terminal/console_01_input_stdio_msg_ictl.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null |
SECTION code_fcntl
PUBLIC console_01_input_stdio_msg_ictl
PUBLIC console_01_input_stdio_msg_ictl_0
EXTERN asm_vioctl_driver, error_einval_zc
EXTERN l_offset_ix_de, l_setmem_hl
EXTERN console_01_input_stdio_msg_flsh
console_01_input_stdio_msg_ictl:
; ioctl messages understood:
;
; defc IOCTL_ITERM_RESET = $0101
; defc IOCTL_ITERM_TIE = $0201
; defc IOCTL_ITERM_GET_EDITBUF = $0381
; defc IOCTL_ITERM_SET_EDITBUF = $0301
;
; in addition to flags managed by stdio
;
; enter : ix = & FDSTRUCT.JP
; bc = first parameter
; de = request
; hl = void *arg (0 if stdio flags)
;
; exit : hl = return value
; carry set if ioctl rejected
;
; uses : af, bc, de, hl
; flag bits managed by stdio?
ld a,h
or l
jr nz, _ictl_messages
; if line mode is being disabled reset the edit buffer
ld a,e
and $20
jp z, asm_vioctl_driver ; if line mode not being disabled
and c
jp nz, asm_vioctl_driver ; if line mode not being disabled
call asm_vioctl_driver ; set stdio flags
push hl ; save return value
call console_01_input_stdio_msg_flsh
pop hl
ret
_ictl_messages:
; check the message is specifically for an input terminal
ld a,e
and $07
cp $01 ; input terminals are type $01
jp nz, error_einval_zc
console_01_input_stdio_msg_ictl_0:
; interpret ioctl message
ld a,d
dec a
jp z, console_01_input_stdio_msg_flsh ; reset == flush ??
dec a
jr z, _ioctl_tie
dec a
jp nz, error_einval_zc
_ioctl_getset_editbuf:
; e & $80 = 1 for get
; bc = first parameter (b_array *)
; hl = void *arg
ld a,e
ld hl,16
call l_offset_ix_de ; hl = & fdstruct.pending_char
ld e,c
ld d,b ; de = & b_array
add a,a
jr c, _ioctl_get_editbuf
_ioctl_set_editbuf:
set 6,(ix+7) ; indicate buffer pushed into edit terminal
xor a
call l_setmem_hl - 6 ; hl = & fdstruct.b_array
ex de,hl
jr _ioctl_editbuf_copy
_ioctl_get_editbuf:
inc hl
inc hl
inc hl ; hl = & fdstruct.b_array
_ioctl_editbuf_copy:
ld bc,6
ldir
or a
ret
_ioctl_tie:
; bc = first parameter (new oterm *)
; hl = void *arg
call console_01_input_stdio_msg_flsh
ld hl,14
call l_offset_ix_de ; hl = & fdstruct.oterm
ld e,(hl)
inc hl
ld d,(hl) ; de = old oterm
ld a,b
and c
inc a
jr z, _ioctl_tie_exit ; if oterm == -1
ld (hl),b
dec hl
ld (hl),c ; store new oterm
_ioctl_tie_exit:
ex de,hl ; hl = old oterm
ret
| 19.054054 | 74 | 0.593262 |
07ba9e2ea3f52fe7fa64dffe8ff40f0dc87ee722 | 34,512 | asm | Assembly | hdrvtest.asm | ddribin/hdrv-snes-test | 8b7dbec72a5ead9b8a02f663a3b72ac2b0bd16b9 | [
"CC0-1.0"
] | 1 | 2022-02-12T18:35:55.000Z | 2022-02-12T18:35:55.000Z | hdrvtest.asm | ddribin/hdrv-snes-test | 8b7dbec72a5ead9b8a02f663a3b72ac2b0bd16b9 | [
"CC0-1.0"
] | null | null | null | hdrvtest.asm | ddribin/hdrv-snes-test | 8b7dbec72a5ead9b8a02f663a3b72ac2b0bd16b9 | [
"CC0-1.0"
] | null | null | null | ; Super Nintendo HDRV Test Software
; Version: v1.4
; Date: 2018-01-27
; CHANGE NOTES from v1.0 -> v1.1: Added Bandwidth Test Patterns
; CHANGE NOTES from v1.1 -> v1.2: Added 75% (really 74.19%) Colorbar Test Pattern
; CHANGE NOTES from v1.2 -> v1.3: Added full green screen test pattern
; Replaced all instances of "Factory" with "HDRV"
; Increased ROM size from 2Mbit to 4Mbit for better compatibility with flash carts
; Changed output ROM file extension from .SMC to .SFC
; CHANGE NOTES from v1.3 -> v1.4: Added ability to change to 224x239 screen size (239p mode)
; Changed DrawLines routine to draw 4 lines at a time to support reduced vblank time during 239p mode
; Added alternating frame 60Hz/50Hz flash test for checking 240p processing
;
; First written in 2015 by HD Retrovision LLC
; http://www.hdretrovision.com
; Authors: Ste Kulov, Nick Mueller, Chris Sowa
;
; To the extent possible under law, the author(s) have dedicated all copyright
; and related and neighboring rights to this software to the public domain worldwide.
; This software is distributed without any warranty.
;
; You should have received a copy of the CC0 Public Domain Dedication along with this software.
; If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
;============================================================================
; Includes
;============================================================================
;== Include SNES Definitions ==
.INCLUDE "snes.inc"
;== Include MemoryMap, Vector Table, and HeaderInfo ==
.INCLUDE "header.inc"
;== Include SNES Initialization Routines ==
.INCLUDE "initSNES.inc"
;== Include SNES Joypad Input Routines ==
.INCLUDE "joypad.inc"
;== Include SPC700 sound test code ==
.INCLUDE "sound.inc"
;============================================================================
; Definitions
;============================================================================
; VRAM Tilemap Positions
.EQU TILEMAP_TOP $2000 ; the first address of the tilemap in VRAM
.EQU LOGO_START $2065 ; the tilemap address where the logo is properly positioned
.EQU TIMER_POS $2274 ; countdown timer in the splash screen
.EQU RESPOS_SPLASH $2173 ; screen size text within the splash screen
.EQU RESPOS_HELP $2213 ; screen size text within the help screen
.EQU RESPOS_MAIN $22E3 ; screen size text within main test patterns
.EQU SCANPOS_SPLASH $218F ; scan mode text within the splash screen
.EQU SCANPOS_HELP $2230 ; scan mode text within the help screen
.EQU SCANPOS_MAIN $22E3 ; scan mode text within main test patterns
.EQU LAUDIO_POS $22E1 ; left audio text indicator
.EQU RAUDIO_POS $22F1 ; right audio text indicator
.EQU FLASHBOX_POS $214C ; flashing box object
; VRAM Tilemap Sizes
.EQU PAL_SIZE 128 ; palette size = 2 bytes for every color, 64 colors (128 = 2 * 64)
.EQU TILEDEF_SIZE 4256 ; tile data size = 32 bytes/tile * #of tile entries (4256 = 32 * 133)
.EQU FULLMAP_SIZE 2048 ; full tilemap = 32 * 32 * 2 = 2048
.EQU LOGO_SIZE 170 ; logo
.EQU RES_SIZE 14 ; screen size text
.EQU SCAN_SIZE 26 ; interlace/non-interlace text
.EQU SCAN_SIZE_MAIN 50 ; scan-mode text during main test patterns
.EQU LAUDIO_SIZE 26 ; left audio indicator
.EQU RAUDIO_SIZE 28 ; right audio indicator
;============================================================================
; Variables
;============================================================================
.ENUM $0000
CurrPattern DB ; storage for current screen mode
Countdown DB ; counter for countdown timer
DoFlash DB ; keeps track if the flashing object is enabled or not
FlashFrame DB ; if yes, this flag tracks if it's on or off during the current frame
TimerText DW ; pointer to current text character for countdown timer
HelpFlag DB ; keeps track on whether help mode is engaged or not
JoyDelay DB ; storage for accumulated joypad data during delay routine
VideoSet DB ; variable to track what's in the REG_SETINI register
CurrLineL DB ; holds current line being drawn
CurrLineH DB
MapBank DB ; storage for ROM bank of tile map
MapAdr DW ; storage for ROM address of tile map
MapPlaceL DB ; storage for location of where to start drawing the tile map
MapPlaceH DB
MapSize DW ; storage for size of tile map
Joy1RawL DB ; Holder of RAW joypad data from register (from last frame)
Joy1RawH DB
Joy1PressL DB ; Contains only pressed buttons (not held down)
Joy1PressH DB
.ENDE
;============================================================================
; Macros
;============================================================================
;----------------------------------------------------------------------------
;============================================================================
; DrawPattern - Draws the referenced one-line tilemap onto the entire screen
;----------------------------------------------------------------------------
; In: 1.)PATTERN -- 24 bit address of tilemap for test pattern
;----------------------------------------------------------------------------
; Out: None
;----------------------------------------------------------------------------
; Modifies: A, X, and Y (through DrawLines routine)
; Requires: mem/A = 8 bit, X/Y = 16 bit
;----------------------------------------------------------------------------
; Usage:
; DrawPattern PATTERN
;----------------------------------------------------------------------------
.MACRO DrawPattern
LDA #:\1 ; Bank of tilemap (using a colon before the parameter gets its bank)
STA MapBank
LDX #\1 ; Tilemap address (not using a colon gets the offset address)
STX MapAdr
JSR DrawLines ; Draw the one row tilemap repeatedly to fill the entire screen
.ENDM
;============================================================================
; DrawMap - Draws pre-mapped data at the location specified
;----------------------------------------------------------------------------
; In: 1.) VRAM_START -- Location (word address) in VRAM where to start writing
; In: 2.) TILEMAP_ADDR -- 24 bit address of pre-defined tilemap
; In: 3.) MAP_SIZE -- Size (in bytes) of tilemap
;----------------------------------------------------------------------------
; Out: None
;----------------------------------------------------------------------------
; Modifies: A, X, and Y (through DrawLines routine)
; Requires: mem/A = 8 bit, X/Y = 16 bit
;----------------------------------------------------------------------------
; Usage:
; DrawMap VRAM_START, TILEMAP_ADDR, MAP_SIZE
;----------------------------------------------------------------------------
.MACRO DrawMap
LDX #\1 ; word address in VRAM where tilemap should start. Multiply by two to get the byte address
STX MapPlaceL
LDA #:\2 ; Bank of tilemap (using a colon before the parameter gets its bank)
STA MapBank
LDX #\2 ; Tilemap address (not using a colon gets the offset address)
STX MapAdr
LDX #\3 ; Tilemap size
STX MapSize
JSR DrawMapSR
.ENDM
;============================================================================
;============================================================================
; Main Code
;============================================================================
.BANK 0 SLOT 0
.ORG 0
.SECTION "MainCode"
Start:
InitSNES ; Clear registers, etc...see "initSNES.inc" for details
STZ REG_SETINI ; Explicitly initialize SETINI register to zero
STZ VideoSet ; Initialize tracking variable for SETINI register
; Load all palette data for our tiles
STZ REG_CGADD ; Start at first color (zero)
LDA #:Palette ; Using a colon before the parameter gets its bank.
LDX #Palette ; Not using a colon gets the offset address.
LDY #PAL_SIZE.W ; Palette size = 2 bytes for every color, 64 colors
STX REG_A1T0L ; Store Data offset into DMA source offset
STA REG_A1B0 ; Store data Bank into DMA source bank
STY REG_DAS0L ; Store size of data block
STZ REG_DMAP0 ; Set DMA mode (byte, normal increment)
LDA #$22.B ; Set destination register ($2122 - CGRAM Write)
STA REG_BBAD0
LDA #$01.B ; Initiate DMA transfer (channel 1)
STA REG_MDMAEN
; Load all tile data into beginning of VRAM
LDA #$80.B ; Word VRAM access, increment by 1, no address remapping
STA REG_VMAIN
LDX #$0000.W ; Start at beginning of VRAM
STX REG_VMADDL ; $2116: Word address for accessing VRAM.
LDA #:Tiles ; Using a colon before the parameter gets its bank.
LDX #Tiles ; Not using a colon gets the offset address.
LDY #TILEDEF_SIZE.W ; Tile data size = 32 bytes/tile * #of tile entries
JSR LoadVRAM ; Perform DMA in subroutine
; Setup Joypad Input
LDX #$0000
STX Joy1RawL ; initialize Joypad1 data storage
STX Joy1PressL
STZ REG_JOYSER0 ; check if Joypad1 is connected
LDA #$81.B
STA REG_NMITIMEN ; enable NMI and auto-joypad read
; Draw the text for the splash screen
DrawMap TILEMAP_TOP.W, Splash, FULLMAP_SIZE.W
; Draw the logo for the splash screen
DrawMap LOGO_START.W, Logo, LOGO_SIZE.W
; Draw Screen Size Text
LDA VideoSet ; extract out the two screen size bits (bits2&3 of VideoSet)
BIT #$0C.B ; bit3-horizontal: 0 => 256 1 => 512 ///// bit2-vertical: 0 => 224 1 => 239
BEQ + ; draw 256x224 if both are zero
CMP #$0C.B
BEQ ++ ; draw 512x239 if both are one
CMP #$08.B
BEQ +++ ; draw 512x224 only if horizontal is 1
DrawMap RESPOS_SPLASH.W, r256x239, RES_SIZE.W ; otherwise draw 256x239
JMP Splash_scan ; continue to draw scan mode
+: DrawMap RESPOS_SPLASH.W, r256x224, RES_SIZE.W
JMP Splash_scan ; continue to draw scan mode
++: DrawMap RESPOS_SPLASH.W, r512x239, RES_SIZE.W
JMP Splash_scan ; continue to draw scan mode
+++:DrawMap RESPOS_SPLASH.W, r512x224, RES_SIZE.W
; Draw Interlace/Non-Interlace Text
Splash_scan:
LDA VideoSet ; extract out the scan mode bit (bit0 of VideoSet)
BIT #$01.B ; 0 => noninterlace, 1 => interlace
BEQ + ; draw corresponding text based on the value
DrawMap SCANPOS_SPLASH.W, Interlace, SCAN_SIZE.W
JMP TurnOn
+: DrawMap SCANPOS_SPLASH.W, Noninterlace, SCAN_SIZE.W
; Setup Video modes, tilemap size, and VRAM offset
; Then turn on the screen
TurnOn:
JSR SetupVideo
; Countdown Timer Loop
WAI ; Wait for VBlank before beginning
LDA #5.B
STA Countdown ; Initialize countdown timer to 5 seconds
LDX #Timer.W
STX TimerText ; Initialize text pointer to first character entry
LDA #$80.B
STA REG_VMAIN ; Word VRAM access, increment by 1, no address remapping
LDY #2.W ; single character of text = 2 bytes
countdownLoop:
LDX #TIMER_POS.W
STX REG_VMADDL ; reset the position for the counter text
LDA #:Timer ; use the starting point label to get the bank
LDX TimerText ; load current timer character
JSR LoadVRAM ; Perform DMA to update the timer text
STZ JoyDelay ; reset accumulated joypad data
LDA #1.B
JSR DelaySec ; one second delay
LDA JoyDelay
BIT #BUTTONH_START ; check if start was pressed during delay
BNE Setup ; if it was, then begin normal operation
INC TimerText ; otherwise...
INC TimerText ; increment the text pointer to the next character (2 bytes)
DEC Countdown ; decrement counter timer
BNE countdownLoop ; end if 5 seconds passed, otherwise repeat
; Initialize the first pattern to be 100% colorbars
Setup:
WAI ; Wait for VBlank before beginning
DrawPattern Color ; draw colorbar screen
STZ CurrPattern ; set pattern tracker to match 100% colorbar index
STZ HelpFlag ; clear help mode flag
STZ DoFlash ; no flashing object yet
STZ FlashFrame ; initialize on/off flash frame tracker to zero
; Main processing loop.
; Check for button presses and change display modes accordingly.
mainLoop:
WAI ; wait for VBlank
JSR Joypad ; grab joypad data
LDA HelpFlag ; check if we are in help mode
BEQ NonHelpJump ; branch around if we are not
LDA Joy1PressL
BIT #BUTTON_X ; otherwise check for scan mode change via X button
BNE SwitchScanJump ; and go handle the change
LDA Joy1PressH
BIT #BUTTONH_Y ; or check for screen height change via Y button
BNE SwitchHeightHelp; and handle it
BIT #BUTTONH_START ; or check for help mode exit command via START button
BNE EndHelpJump ; and handle it
JMP mainLoop ; otherwise repeat the loop
NonHelpJump:
JMP NonHelp
EndHelpJump:
JMP EndHelp
SwitchScanJump:
JMP SwitchScanHelp
SwitchHeightHelp:
DrawPattern Black ; clear the screen of tile data from previous screen height setting
LDA VideoSet ; load dummy variable which contains the screen height setting
EOR #$04.B ; toggle vertical height (bit2)
STA REG_SETINI ; send the update to the video processor
STA VideoSet ; and store the changes in memory
JSR DrawHelp
LDA VideoSet ; extract out the two screen size bits (bits2&3 of VideoSet)
BIT #$0C.B ; bit3-horizontal: 0 => 256 1 => 512 ///// bit2-vertical: 0 => 224 1 => 239
BEQ + ; draw 256x224 if both are zero
CMP #$0C.B
BEQ ++ ; draw 512x239 if both are one
CMP #$08.B
BEQ +++ ; draw 512x224 only if horizontal is 1
DrawMap RESPOS_HELP.W, r256x239, RES_SIZE.W ; otherwise draw 256x239
JMP mainLoop ; continue to draw scan mode
+: DrawMap RESPOS_HELP.W, r256x224, RES_SIZE.W
JMP mainLoop ; continue to draw scan mode
++: DrawMap RESPOS_HELP.W, r512x239, RES_SIZE.W
JMP mainLoop ; continue to draw scan mode
+++:DrawMap RESPOS_HELP.W, r512x224, RES_SIZE.W
JMP mainLoop
SwitchScanHelp:
LDA VideoSet ; load dummy variable which contains the scan mode setting
EOR #$01.B ; toggle scan mode (bit0)
STA REG_SETINI ; send the update to the video processor
STA VideoSet ; and store the changes in memory
BIT #$01.B ; 0 => noninterlace, 1 => interlace
BEQ + ; redraw the corresponding text and repeat the loop
DrawMap SCANPOS_HELP.W, Interlace, SCAN_SIZE.W
JMP mainLoop
+: DrawMap SCANPOS_HELP.W, Noninterlace, SCAN_SIZE.W
JMP mainLoop
EndHelp:
STZ HelpFlag ; clear help flag indicating we are no longer in help mode
JMP Redraw ; jump down to redraw the current test pattern
NonHelp:
LDA Joy1PressL
BIT #BUTTON_X ; check if X button is pressed
BNE SwitchScan ; if yes, then toggle the scan mode (interlace/non-interlace)
BIT #BUTTON_A ; check if A button is pressed
BNE NextPattern ; if yes, then switch to next video mode
LDA Joy1PressH
BIT #BUTTONH_Y ; check if Y button is pressed
BNE ChangeHeightJump; if yes, then change screen height
BIT #BUTTONH_B ; check if B button is pressed
BNE PrevPattern ; if yes, then switch to previous video mode
BIT #BUTTONH_UP ; check if D-PAD Up button is pressed
BNE ToggleFlash ; if yes, then toggle flashing object on/off
BIT #BUTTONH_LEFT ; check if D-PAD Left button is pressed
BNE LeftAudioJump ; if yes, then play left channel audio test
BIT #BUTTONH_RIGHT ; check if D-PAD Right button is pressed
BNE RightAudioJump ; if yes, then play right channel audio test
BIT #BUTTONH_START ; check if START button is pressed
BEQ + ; if not, then check if flashing object is enabled
JSR DrawHelp ; if it was, then draw the help screen
INC HelpFlag ; and track the mode was entered by setting the help flag
JMP ++
+: LDA DoFlash ; is flashing object enabled?
BNE Redraw ; if yes, we better go to the drawing loop, otherwise
++: JMP mainLoop ; repeat the main loop
ToggleFlash:
LDA DoFlash ; load flashing object tracking flag
EOR #$01.B ; toggle it
STA DoFlash ; and store it back into memory
JMP Redraw ; go to drawing loop
NextPattern:
LDA CurrPattern
INC A ; increment the tracker for the current pattern
CMP #$0A.B ; check if we've blown past the last pattern
BNE + ; if not, then continue
LDA #$00.B ; otherwise set the pattern to zero
+: STA CurrPattern ; and store the new current pattern setting
JMP Redraw ; and redraw the screen
PrevPattern:
LDA CurrPattern
DEC A ; decrement the tracker for the current pattern
CMP #$FF.B ; check if we've blown past the first pattern
BNE + ; if not, then continue
LDA #$09.B ; otherwise set the pattern to the last one
+: STA CurrPattern ; and store the new current pattern setting
JMP Redraw ; and redraw the screen
LeftAudioJump:
JMP LeftAudio
RightAudioJump:
JMP RightAudio
ChangeHeightJump:
JMP ChangeHeight
Redraw:
LDA DoFlash ; load flashing object flag and check if we're supposed to flash
BEQ + ; if not, just redraw the pattern
LDA FlashFrame ; otherwise, load up if this is an on/off frame
EOR #$01.B ; flip it for the next time
STA FlashFrame ; and store it back
BEQ + ; then decide whether to erase the object
JSR DrawBox ; or to draw it
JMP ++
+: JSR PatternSelect ; draws the current pattern
++: JMP mainLoop ; and then repeat the main loop
SwitchScan:
JSR PatternSelect
LDA VideoSet ; load register which contains scan mode setting
EOR #$01.B ; toggle scan mode (bit0)
STA REG_SETINI ; send the update to the video processor
STA VideoSet ; and store the changes in memory
BIT #$01.B ; 0 => noninterlace, 1 => interlace
BEQ + ; redraw the corresponding text on the screen
DrawMap SCANPOS_MAIN.W, Scanmode_interlace, SCAN_SIZE_MAIN.W
JMP ++
+: DrawMap SCANPOS_MAIN.W, Scanmode_noninterlace, SCAN_SIZE_MAIN.W
++: LDA #1.B
JSR DelaySec ; delay for one second and then redraw entire screen to remove text
JMP Redraw
ChangeHeight:
JSR PatternSelect
LDA VideoSet ; load register which contains screen height setting
EOR #$04.B ; toggle height (bit2)
STA REG_SETINI ; send the update to the video processor
STA VideoSet ; and store the changes in memory
BIT #$0C.B ; bit3-horizontal: 0 => 256 1 => 512 ///// bit2-vertical: 0 => 224 1 => 239
BEQ + ; draw 256x224 if both are zero
CMP #$0C.B
BEQ ++ ; draw 512x239 if both are one
CMP #$08.B
BEQ +++ ; draw 512x224 only if horizontal is 1
DrawMap RESPOS_MAIN.W, r256x239, RES_SIZE.W ; otherwise draw 256x239
LDA #1.B
JSR DelaySec
JMP Redraw
+: DrawMap RESPOS_MAIN.W, r256x224, RES_SIZE.W
LDA #1.B
JSR DelaySec
JMP Redraw
++: DrawMap RESPOS_MAIN.W, r512x239, RES_SIZE.W
LDA #1.B
JSR DelaySec
JMP Redraw
+++:DrawMap RESPOS_MAIN.W, r512x224, RES_SIZE.W
LDA #1.B
JSR DelaySec
JMP Redraw
LeftAudio:
JSR PlaySoundL ; play left channel sound effect
WAI ; wait for VBlank and then draw the indicator on the screen
JSR PatternSelect
DrawMap LAUDIO_POS.W, LeftAud, LAUDIO_SIZE.W
LDA #1.B
JSR DelaySec ; delay for one second
JMP Redraw ; and then redraw entire screen to remove the indicator
RightAudio:
JSR PlaySoundR ; play right channel sound effect
WAI ; wait for VBlank and then draw the indicator on the screen
JSR PatternSelect
DrawMap RAUDIO_POS.W, RightAud, RAUDIO_SIZE.W
LDA #1.B
JSR DelaySec ; delay for one second
JMP Redraw ; and then redraw entire screen to remove the indicator
;============================================================================
;============================================================================
; Routines
;============================================================================
;----------------------------------------------------------------------------
;============================================================================
; PatternSelect -- Selects the correct pattern to draw and draws it
;----------------------------------------------------------------------------
; In: None
;----------------------------------------------------------------------------
; Out: None
;----------------------------------------------------------------------------
; Modifies: A, X, and Y
;----------------------------------------------------------------------------
; Notes: Uses the value in CurrPattern to make the decision.
; Gets called from the main loop.
;----------------------------------------------------------------------------
PatternSelect:
LDA CurrPattern
BEQ DrawColor ; draw 100% colorbars if current pattern = 0
CMP #$01.B
BEQ DrawColor75 ; draw 75% (74.19%) colorbars if current pattern = 1
CMP #$02.B
BEQ DrawGray ; draw graybars if current pattern = 2
CMP #$03.B
BEQ DrawWhite ; draw white screen if current pattern = 3
CMP #$04.B
BEQ DrawGreen ; draw green screen if current pattern = 4
CMP #$05.B
BEQ DrawMagenta ; draw magenta screen if current pattern = 5
CMP #$06.B
BEQ DrawBlue ; draw blue screen if current pattern = 6
CMP #$07.B
BEQ DrawBlack ; draw black screen if current pattern = 7
CMP #$08.B
BEQ DrawSlow ; draw slow bandwidth screen if current pattern = 8
CMP #$09.B
JMP DrawFast ; draw fast bandwidth screen if current pattern = 9
DrawColor:
DrawPattern Color ; draw 100% colorbars
JMP EndDraw ; and jump to the end of routine
DrawColor75:
DrawPattern Color75 ; draw 75% (74.19%) colorbars
JMP EndDraw ; and jump to the end of routine
DrawGray:
DrawPattern Gray ; draw graybars
JMP EndDraw ; and jump to the end of routine
DrawWhite:
DrawPattern White ; draw white screen
JMP EndDraw ; and jump to the end of routine
DrawGreen:
DrawPattern Green ; draw white screen
JMP EndDraw ; and jump to the end of routine
DrawMagenta:
DrawPattern Magenta ; draw magenta screen
JMP EndDraw ; and jump to the end of routine
DrawBlue:
DrawPattern Blue ; draw blue screen
JMP EndDraw ; and jump to the end of routine
DrawBlack:
DrawPattern Black ; draw black screen
JMP EndDraw ; and jump to the end of routine
DrawSlow:
DrawPattern SlowBand ; draw slow bandwidth test pattern
JMP EndDraw ; and jump to the end of routine
DrawFast:
DrawPattern FastBand ; draw fast bandwidth test pattern
JMP EndDraw ; and jump to the end of routine
EndDraw:
RTS ; return to main loop
;============================================================================
;============================================================================
; DelaySec -- Generic Delay Routine
;----------------------------------------------------------------------------
; In: A -- numbers of seconds to delay by
;----------------------------------------------------------------------------
; Out: None
;----------------------------------------------------------------------------
; Modifies: A, X
;----------------------------------------------------------------------------
; Notes: Load the number of seconds into A before calling
;----------------------------------------------------------------------------
DelaySec:
LDX #60.W
OneSec:
WAI ; waiting for VBlank takes approximately 1/60 of a second
; extra code to provide a hook to detect button presses during the delay routine
PHA ; push the amount of seconds to delay onto the stack
JSR Joypad ; poll the joypads
LDA JoyDelay ; load accumulated joypad data
ORA Joy1PressH ; detect any new presses
STA JoyDelay ; and save them
PLA ; recover number of delay seconds from the stack
; continue delay routine
DEX
BNE OneSec ; repeat 60 times to achieve one second of delay
DEC A
BNE DelaySec ; repeat the entire routine for the specified number of seconds
RTS
;============================================================================
;============================================================================
; LoadVRAM -- Load data into VRAM
;----------------------------------------------------------------------------
; In: A:X -- points to the data
; Y -- Number of bytes to copy (0 to 65535) (assumes 16-bit index)
;----------------------------------------------------------------------------
; Out: None
;----------------------------------------------------------------------------
; Modifies: A
;----------------------------------------------------------------------------
; Notes: Assumes VRAM address has been previously set!!
;----------------------------------------------------------------------------
LoadVRAM:
STA REG_A1B0 ; Store data Bank into DMA source bank
STX REG_A1T0L ; Store Data offset into DMA source offset
STY REG_DAS0L ; Store size of data block
LDA #$01.B
STA REG_DMAP0 ; Set DMA mode (word, normal increment)
LDA #$18.B
STA REG_BBAD0 ; Set the destination register (VRAM write register)
LDA #$01.B
STA REG_MDMAEN ; Initiate DMA transfer (channel 1)
RTS ; Return from subroutine
;============================================================================
;============================================================================
; DrawHelp -- Displays the help screen which has operating instructions
;----------------------------------------------------------------------------
; In: None
;----------------------------------------------------------------------------
; Out: None
;----------------------------------------------------------------------------
; Modifies: A, X, and Y
;----------------------------------------------------------------------------
; Notes: Once in help screen, the only valid buttons are
; X: for changing the scan mode
; START: for exiting help
;----------------------------------------------------------------------------
DrawHelp:
DrawPattern Black ; first clear the screen of erroneous tile data
; Draw the text for the splash screen
DrawMap TILEMAP_TOP.W, Help, FULLMAP_SIZE.W
; Draw Screen Size Text
LDA VideoSet ; extract out the two screen size bits (bits2&3 of VideoSet)
BIT #$0C.B ; bit3-horizontal: 0 => 256 1 => 512 ///// bit2-vertical: 0 => 224 1 => 239
BEQ + ; draw 256x224 if both are zero
CMP #$0C.B
BEQ ++ ; draw 512x239 if both are one
CMP #$08.B
BEQ +++ ; draw 512x224 only if horizontal is 1
DrawMap RESPOS_HELP.W, r256x239, RES_SIZE.W ; otherwise draw 256x239
JMP Help_scan ; continue to draw scan mode
+: DrawMap RESPOS_HELP.W, r256x224, RES_SIZE.W
JMP Help_scan ; continue to draw scan mode
++: DrawMap RESPOS_HELP.W, r512x239, RES_SIZE.W
JMP Help_scan ; continue to draw scan mode
+++:DrawMap RESPOS_HELP.W, r512x224, RES_SIZE.W
; Draw Interlace/Non-Interlace Text
Help_scan:
LDA VideoSet ; extract out the scan mode bit (bit0 of VideoSet)
BIT #$01.B ; 0 => noninterlace, 1 => interlace
BEQ + ; draw corresponding text based on the value
DrawMap SCANPOS_HELP.W, Interlace, SCAN_SIZE.W
JMP ++
+: DrawMap SCANPOS_HELP.W, Noninterlace, SCAN_SIZE.W
++: RTS
;============================================================================
;============================================================================
; DrawMapSR -- Draws any generic tilemap onto the screen at any location
;----------------------------------------------------------------------------
; In: None
;----------------------------------------------------------------------------
; Out: None
;----------------------------------------------------------------------------
; Notes: This gets called by the DrawMap MACRO
;----------------------------------------------------------------------------
DrawMapSR:
LDA #$80.B
STA REG_VMAIN ; Word VRAM access, increment by 1, no address remapping
LDA VideoSet ; extract out the screen height bit (bit2 of VideoSet)
BIT #$04.B ; 0 => 224, 1 => 239
BEQ + ; if 224, then no vertical offset correction required
LDA #$20.B ; otherwise
CLC ; clear carry
ADC MapPlaceL ; add a line of tiles for offset correction
STA MapPlaceL ; store it
LDA MapPlaceH ; also
ADC #$00.B ; add any carry to the high byte
STA MapPlaceH ; and store that too
+: LDX MapPlaceL ; load tilemap starting location
STX REG_VMADDL ; $2116: Word address for accessing VRAM.
LDA MapBank ; load bank of tilemap
LDX MapAdr ; load tilemap address
LDY MapSize ; load size of tilemap
WAI ; wait for vblank to not conflict with DMA
JSR LoadVRAM ; then perform DMA for this map data
RTS ; and return when done
;============================================================================
;============================================================================
; DrawBox -- Uses an 8 tile tilemap to make a box
;----------------------------------------------------------------------------
; In: None
;----------------------------------------------------------------------------
; Out: None
;----------------------------------------------------------------------------
; Notes: Box is also 8 tiles tall
;----------------------------------------------------------------------------
DrawBox:
LDA #:FlashBox ; Bank of tilemap (using a colon before the parameter gets its bank)
STA MapBank
LDX #FlashBox ; Tilemap address (not using a colon gets the offset address)
STX MapAdr
LDX #FLASHBOX_POS.W ; top-left corner of the flashing box
STX CurrLineL ; set it to current line
LDA #$80.B
STA REG_VMAIN ; Word VRAM access, increment by 1, no address remapping
LDA VideoSet ; extract out the screen height bit (bit2 of VideoSet)
BIT #$04.B ; 0 => 224, 1 => 239
BEQ _BoxLoop ; if 224, then no vertical offset correction required
LDA #$20.B ; otherwise
CLC ; clear carry
ADC CurrLineL ; add a line of tiles for offset correction
STA CurrLineL ; store it
LDA CurrLineH ; also
ADC #$00.B ; add any carry to the high byte
STA CurrLineH ; and store that too
_BoxLoop:
LDX CurrLineL ; get current line
STX REG_VMADDL ; $2116: Word address for accessing VRAM.
LDA MapBank ; Bank of box tilemap
LDX MapAdr ; Offset address of box tilemap
LDY #16.W ; Width of flashing box in terms of bytes (bytes = 2*tiles)
JSR LoadVRAM ; Perform DMA for one line
LDA CurrLineL ; get current line number
CLC ; clear carry before adding
ADC #$20.B ; move address to start of next line
STA CurrLineL ; store new address
LDA CurrLineH
ADC #$00.B ; add any carry to the high byte
STA CurrLineH ; and store it
CMP #$22.B ; check if all 8 box lines have been loaded (high-byte)
BNE _BoxLoop ; repeat if there are more box lines to do
LDA VideoSet ; otherwise, extract out the screen height bit (bit2 of VideoSet)
BIT #$04.B ; 0 => 224, 1 => 239
BEQ + ; if 224, then no vertical offset correction required
LDA CurrLineL ; otherwise
CMP #$6C.B ; check if all 8 box lines have been loaded (low-byte) using offset correction
BEQ ++ ; and end the routine if it is
JMP _BoxLoop ; or repeat if there are more box lines to do
+: LDA CurrLineL
CMP #$4C.B ; check if all 8 box lines have been loaded (low-byte)
BNE _BoxLoop ; repeat if there are more box lines to do
++: RTS ; return if all 8 box lines are done
;============================================================================
;============================================================================
; DrawLines -- Uses a four row tilemap to fill the entire screen
;----------------------------------------------------------------------------
; In: None
;----------------------------------------------------------------------------
; Out: None
;----------------------------------------------------------------------------
; Notes: 32 lines of 32 tiles for a full screen (32x32 tiles & 8x8 pixels ==> 256x256)
;----------------------------------------------------------------------------
DrawLines:
LDX #TILEMAP_TOP.W ; start of the line
STX CurrLineL ; set it to current line
LDA #$80.B
STA REG_VMAIN ; Word VRAM access, increment by 1, no address remapping
_LineLoop:
LDX CurrLineL ; get current line
STX REG_VMADDL ; $2116: Word address for accessing VRAM.
LDA MapBank ; Bank of test pattern map
LDX MapAdr ; Offset address of test pattern map
LDY #256.W ; Size of four lines in terms of bytes (bytes = 2*tiles)
JSR LoadVRAM ; Perform DMA for four lines
LDA CurrLineL ; get current line number
CLC ; clear carry before adding
ADC #$80.B ; move address to start of the next four lines
STA CurrLineL ; store new address
LDA CurrLineH
ADC #$00.B ; add any carry to the high byte
STA CurrLineH ; and store it
CMP #$24.B ; check if all 32 lines have been loaded
BNE _LineLoop ; repeat if there are more lines to do
RTS ; or return if all 32 lines are done
;============================================================================
;============================================================================
; SetupVideo -- Sets up the video mode and tile-related registers
;----------------------------------------------------------------------------
; In: None
;----------------------------------------------------------------------------
; Out: None
;----------------------------------------------------------------------------
SetupVideo:
LDA #BGMODE_1.B
STA REG_BGMODE ; Set Video BG Mode to 1, 8x8 tiles, BG1/BG2 = 16 colors, BG3 = 4 colors, BG4 = N/A
LDA #$20.B ; Set BG1's Tile Map offset to $2000 (Word address) in order to fit our tile data before that
STA REG_BG1SC ; and also sets the Tile Map size to 32x32
STZ REG_BG12NBA ; Set BG1's Character VRAM offset to $0000 (word address)
LDA #TM_BG1.B
STA REG_TM ; Enable BG1, leave all others disabled
LDA #$0F.B
STA REG_INIDISP ; Turn on screen, full Brightness, forced blanking is OFF
RTS
;============================================================================
;============================================================================
; VBlank -- Vertical Blanking Interrupt Routine
;----------------------------------------------------------------------------
VBlank:
PHA
PHX
PHY
PHP ; Save register states
LDA REG_RDNMI ; Clear NMI flag
PLP
PLY
PLX
PLA ; Restore register states
RTI ; Return from interrupt
;============================================================================
.ENDS
;============================================================================
; Character Data (palettes, tiles, tilemaps)
;============================================================================
.BANK 1 SLOT 0
.ORG 0
.SECTION "CharacterData"
.INCLUDE "graphics.inc"
.ENDS
| 41.985401 | 111 | 0.571222 |
92d7bcfab6a02f0ce8e139a8beff5a3b5d8af1ad | 1,087 | asm | Assembly | samples/zx/tilemap_render/multidir_scroll/settings.asm | 0x8BitDev/MAPeD-SPReD | da1a8a582980ea5963777a46fd3dfddc0d69aa82 | [
"MIT"
] | 23 | 2019-05-16T20:23:49.000Z | 2022-03-13T21:53:10.000Z | samples/zx/tilemap_render/multidir_scroll/settings.asm | 0x8BitDev/MAPeD-SPReD | da1a8a582980ea5963777a46fd3dfddc0d69aa82 | [
"MIT"
] | 6 | 2021-03-30T05:51:46.000Z | 2022-01-07T13:18:44.000Z | samples/zx/tilemap_render/multidir_scroll/settings.asm | 0x8BitDev/MAPeD-SPReD | da1a8a582980ea5963777a46fd3dfddc0d69aa82 | [
"MIT"
] | null | null | null | ;###################################################################
;
; Copyright 2018-2019 0x8BitDev ( MIT license )
;
;###################################################################
;
; Multidirectional scroller settings.
;
; move step in bits
MS_TILE equ 1 ; [tile2x2 : 16bit], [tile4x4 : 32bit]
MS_8b equ 2 ; [tile2x2]
MS_4b equ 3 ; [tile2x2] vertical scrolling is "free", horizontal one is simple RLD, so it's quite slow implementation, just to get fast result
; the best choice: pre shifted tiles or caching of shifted tiles in real-time... the best choice for real project, not for the data test demo )
; the main settings
DEFINE DEF_128K_DBL_BUFFER 1 ; 128K dbl buffering or usual 48K rendering
DEFINE DEF_FULLSCREEN 1 ; fullscreen or upper 2/3 of the screen
DEFINE DEF_COLOR 1 ; BW or CLR
DEFINE DEF_MOVE_STEP MS_TILE ; MS_TILE / MS_8b / MS_4b
DEFINE DEF_VERT_SYNC 1 ; rendering begins with HALT or not...
IF DEF_128K_DBL_BUFFER
device zxspectrum128
ELSE
device zxspectrum48
ENDIF //DEF_128K_DBL_BUFFER
| 36.233333 | 148 | 0.624655 |
2f268f7ceb26e5bfd964e39b86b5d91ad28965a8 | 4,793 | asm | Assembly | Ergastiriaki Askisi 5/Ergasia_5_b.asm | alexPlessias/AssemblyProgrammes | 5f6da80b8dfac8eb6f51c92fb32a6d23d873aa24 | [
"MIT"
] | null | null | null | Ergastiriaki Askisi 5/Ergasia_5_b.asm | alexPlessias/AssemblyProgrammes | 5f6da80b8dfac8eb6f51c92fb32a6d23d873aa24 | [
"MIT"
] | null | null | null | Ergastiriaki Askisi 5/Ergasia_5_b.asm | alexPlessias/AssemblyProgrammes | 5f6da80b8dfac8eb6f51c92fb32a6d23d873aa24 | [
"MIT"
] | null | null | null | title search_array_proc (Ergasia_5_a.asm)
; Check user input if is in limit and search for it in array.
include Irvine32.inc
; Globals.
max_limit equ 10d
min_limit equ -10d
array_size equ 10d
.data
tableContent sdword -5d, 5d, -6d, -7d, 9d, -6d, 10d, -3d, 5d, -6d
enterMsg byte "Enter a value (-10 to +10): ",0
wrongMsg byte "Input out of limits, please try again.",0
foundMsg byte "The value has been found at address (offset): ",0
notFoundMsg byte "The value hasn't been found.", 0
returned_value dword ?
.code
;-------------------------------------------------------------------------------------------------
SearchArray proc
; Search if a value exist or not in any array.
; Recieves: First param Search Value, Second param for Array Size,
; third param for Offset of first element of array and fourth param for returned_value.
; Returns: If value exist EAX = Offset of element else EAX = 0.
;-------------------------------------------------------------------------------------------------
enter 4,0 ; Create stack frame (push ebp ; mov ebp,esp ; sub esp,4) ; 0*4 localVar , 0 nestingLevel
push esi ; Store Key.
push ecx ; Size of array
push edx ; Offset of first element of array
mov [ebp-4],eax ; Local var EQU search element.
push eax ; Save search element.
push ebx ; Current element adress.
mov edx, [ebp+20] ; Offset of first element of array
mov ecx, [ebp+16] ; Size of array
mov esi, [ebp+12] ; Key
dec ecx ; start from size array -1.
scan:
;check all elements but not first.
mov ebx, ecx ; ebx = current_size
shl ebx, 2d ; ebx = ebx << 2 = ebx *4 = current_size *4 (e.g. 5*4 =20)
add ebx, edx ; ebx = ebx + edx = (current_size *4) + (Offset of first element of array)= addr of each element.
cmp esi, [ebx] ; Compare esi, [ebx] (effect Sign, Zero and Overflow Flags).
je find ; Jump if not equal(cmp_left_op!=cmp_right_op) goto L5
loop scan ; Goto label:scan . Dicrease ecx by 1 when == 0 finish.
;check first elements only.
mov ebx, ecx ; ebx = 0
add ebx, edx ; ebx = ebx + edx = 0 + (Offset of first element of array)= addr of first element.
cmp esi, [ebx] ; Compare eax, esi (effect Sign, Zero and Overflow Flags).
je find ; Jump if not equal(cmp_left_op!=cmp_right_op) goto L5
;dont find case
mov eax,[ebp+8] ; Overwrite eax.
mov ecx ,0d ; Overwrite ecx.
mov [eax], ecx ; [ebp+8] = 0.
finish:
pop ebx
mov eax, [ebp-4]
pop eax
pop edx
pop ecx
pop esi
leave ; Free stack frame (mov esp,ebp ; pop ebp)
ret 16 ; Goto main in line after call.
find:
mov eax,[ebp+8] ; Overwrite eax.
mov [eax], ebx ; [ebp+8] = ebx.
jmp finish ; Goto label:finish.
SearchArray endp
main proc
mov eax, green + (black*16) ; From Lec_04 (29).
call setTextColor ; From Lec_04 (29).
getInput:
mov edx, offset enterMsg ; edx = enterMsg.
call WriteString ; Show enterMsg (edx = enterMsg).
call ReadInt ; eax = input integer from user.
cmp eax, min_limit ; Compare eax, min_limit (effect Sign, Zero and Overflow Flags).
jl offLimit ; Jump if less(cmp_left_op<cmp_right_op) goto offLimit. ; inputUser < min_limit.
cmp eax, max_limit ; Compare eax, max_limit (effect Sign, Zero and Overflow Flags).
jg offLimit ; Jump if greater(cmp_left_op>cmp_right_op) goto offLimit. ; inputUser > min_limit.
push offset tableContent ; Argument by reference.
push array_size ; Argument by value.
push eax ; Argument by value.
push offset returned_value ; Argument by reference.
call SearchArray ; Recieves: eax, ecx, edx & Return: eax.
; Not Found case.
cmp returned_value, 0 ; Compare eax, 0 (effect Sign, Zero and Overflow Flags).
je notFound ; Jump if equal(cmp_left_op=cmp_right_op) goto notFound
; Found case.
mov edx, offset foundMsg ; edx = foundMsg.
call WriteString ; Show enterMsg (edx = foundMsg).
mov eax, returned_value
call WriteHex ; Show eax in hexMode.
call Crlf ; New line.
call Crlf ; New line.
exit
notFound:
mov edx, offset notFoundMsg ; edx = notFoundMsg.
call WriteString ; Show enterMsg (edx = notFoundMsg).
call Crlf ; New line.
call Crlf ; New line.
exit
offLimit:
mov edx, offset wrongMsg
call WriteString
call Crlf
jmp getInput
main endp
END main
; Who cmp (destination,source) work ?
; Cases | Flags
; ------------------------------------------------
; destination < source | SignFlag != OverflowFlag
; destination > source | SignFlag = OverflowFlag
; destination = source | ZeroFlag = 0
| 31.532895 | 115 | 0.612977 |
5e55ea4bc75b51553539a36bed9fd9e31276536d | 6,295 | asm | Assembly | src/TimerGameLoop.asm | glen-mac/COMP2121-16s1 | 7344e0f0fcb6634ae7bb152d42f77ddb13caf583 | [
"MIT"
] | null | null | null | src/TimerGameLoop.asm | glen-mac/COMP2121-16s1 | 7344e0f0fcb6634ae7bb152d42f77ddb13caf583 | [
"MIT"
] | null | null | null | src/TimerGameLoop.asm | glen-mac/COMP2121-16s1 | 7344e0f0fcb6634ae7bb152d42f77ddb13caf583 | [
"MIT"
] | null | null | null | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;; GAME LOOP ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;This file is for storing the MAIN code used to control the views and
;screen stages in the game. It is triggered every 100ms, and runs code
;in segments depending on the current stage of the game. A register,
;'screenStageFol' is used to ensure that the 'startup' code for a stage
;is run once, while code that follows on from each of these respective
;blocks may be run every single time the game loop executes while still
;in that very same stage.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Timer0OVF: ;This is an 8-bit timer - Main game loop.
;timer prologue
push yl
push yh
push temp
in temp, SREG
push temp
lds yl, gameloopTimer
lds yh, gameloopTimer+1
adiw Y, 1
sts gameloopTimer, yl
sts gameloopTimer+1, yh
ldi temp, high(781)
cpi yl, low(781)
cpc yh, temp
breq continueTimer0
rjmp endTimer0
continueTimer0:
clr debounce ;clear debounce flag
clear_datamem gameloopTimer ;clear the counter
;switch case for stage select
cpii screenStage, stage_countdown
breq countdownSeg
cpii screenStage, stage_pot_reset
breq potResetSeg
cpii screenStage, stage_pot_find
breq potFindSeg
cpii screenStage, stage_code_find
breq codeFindSeg
cpii screenStage, stage_code_enter
breq codeEnterSeg
cpii screenStage, stage_win
breq winSeg
cpii screenStage, stage_lose
breq loseSeg
rjmp endTimer0
countdownSeg:
rcall countdownFunc
rjmp endTimer0
potResetSeg:
rcall potResetFunc
rjmp endTimer0
potFindSeg:
rcall potFindFunc
rjmp endTimer0
codeFindSeg:
rcall codeFindFunc
rjmp endTimer0
codeEnterSeg:
rcall codeEnterFunc
rjmp endTimer0
winSeg:
rcall winFunc
rjmp endTimer0
loseSeg:
rcall loseFunc
rjmp endTimer0
endTimer0:
pop temp
out SREG, temp
pop temp
pop yh
pop yl
reti
countdownFunc:
cpii screenStageFol, stage_countdown
breq endCountdownFunc
ldii running, 1 ;backlight should be on
ldii screenStageFol, stage_countdown
do_lcd_write_str str_countdown_msg
ldi temp, 3 ;begin to write countdown to screen
addi temp, '0'
do_lcd_data temp
do_lcd_data_i '.'
do_lcd_data_i '.'
do_lcd_data_i '.'
toggle TIMSK1, 1<<TOIE1 ;countdown timer needs to be on
endCountdownFunc:
ret
potResetFunc:
cpii screenStageFol, stage_pot_reset
brne continuePotResetFunc
rjmp endPotResetFunc
continuePotResetFunc:
ldii screenStageFol, stage_pot_reset
enable_ADC ;ADC should be on
do_lcd_write_str str_reset_msg
do_lcd_command 0b11001011 ;move cursor on screen (to write countdown)
mov temp, difficultyCount
sub temp, counter
rcall asciiconv ;write countdown on screen
clr row ; this register used to ensure RESET position is held for 500ms
clr col ; this register used to count amount of times row has been seen to ->
; be one (obviously after checking twice in 500ms intervals it is RESET)
endPotResetFunc:
cpi row, 1 ; is the pot still in reset position?
breq incrementResetPotCount
clr col
ret
incrementResetPotCount:
inc col ; numbers of times seen row as 1
ldi temp, 5 ; has it been 5 x 100ms?
cp col, temp
brne endIncrementResetPotCount
ldii screenStage, stage_pot_find
endIncrementResetPotCount:
ret
potFindFunc:
cpii screenStageFol, stage_pot_find
breq endPotFindFunc
ldii screenStageFol, stage_pot_find
do_lcd_write_str str_findposition_msg ;this is the reset pot message?
do_lcd_command 0b11001011 ; move cursor so countdown can be written
mov temp, difficultyCount
sub temp, counter
rcall asciiconv
clr row ; this register used to ensure FIND position is held for 500ms
clr col ; this register used to count amount of times row has been seen to ->
; be one (obviously after checking twice in 500ms intervals it is FOUND)
endPotFindFunc:
cpi row, 1 ; is the pot still in reset position?
breq incrementFindPotCount
clr col
ret
incrementFindPotCount:
inc col ;numbers of times seen row as 1
ldi temp, 10 ;has it been 1s?
cp col, temp
brne endIncrementFindPotCount
ldii screenStage, stage_code_find
endIncrementFindPotCount:
ret
codeFindFunc:
cpii screenStageFol, stage_code_find
brne continueCodeFindFunc
rjmp endCodeFindFunc
continueCodeFindFunc:
rcall updateHighscores ;did we beat a highscore?!?!
ldii screenStageFol, stage_code_find
disable_ADC
rcall randomizePotLocation
toggle TIMSK1, 0 ;disable countdown
do_lcd_write_str str_keypadscan_msg
lds keypadCode, TCNT3L
andi keypadCode, 0b1111 ;take low 4 bits of timer as keypad button (random)
clr counter ;clear counter (for new round)
endCodeFindFunc:
ret
codeEnterFunc:
cpii screenStageFol, stage_code_enter
breq endCodeEnterFunc
ldii screenStageFol, stage_code_enter
do_lcd_command 0b00001110 ;cursor on
do_lcd_write_str str_entercode_msg
clr counter ;clear counter to count number of button presses to index memory in data seg
endCodeEnterFunc:
ret
winFunc:
cpii screenStageFol, stage_win
breq epilogueWinFunc
do_lcd_command 0b00001100 ;cursor off
clr running ;backlight should begin to fade out
ldii screenStageFol, stage_win
toggle TIMSK1, 0 ;turn off countdown timer
disable_ADC ;disable adc
speakerBeepFor speaker1000 ;make some noise!!
do_lcd_write_str str_win_msg
clr counter ;clear counter for use in the flashing below
epilogueWinFunc:
inc counter
cpii counter, 5
brne endWinFunc
toggleStrobe ;toggle strobe at 2hz
clr counter
endWinFunc:
ret
loseFunc:
cpii screenStageFol, stage_lose
breq endLoseFunc
clr running ;backlight should begin to fade out
speakerBeepFor speaker1000 ;make some noise :(
ldii screenStageFol, stage_lose
toggle TIMSK1, 0 ;turn off countdown timer
disable_ADC ;disable adc
ldi temp, 0
out PORTC, temp ;turn off LED lights
out PORTG, temp ;turn off LED lights
do_lcd_write_str str_timeout_msg
endLoseFunc:
ret
| 25.693878 | 89 | 0.713423 |
1946867ca44ad93849f282ef2a1e2014a929c44e | 539 | asm | Assembly | oeis/075/A075778.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/075/A075778.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/075/A075778.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A075778: Decimal expansion of the real root of x^3 + x^2 - 1.
; Submitted by Jamie Morken(s2)
; 7,5,4,8,7,7,6,6,6,2,4,6,6,9,2,7,6,0,0,4,9,5,0,8,8,9,6,3,5,8,5,2,8,6,9,1,8,9,4,6,0,6,6,1,7,7,7,2,7,9,3,1,4,3,9,8,9,2,8,3,9,7,0,6,4,6,0,8,0,6,5,5,1,2,8,0,8,1,0,9,0,7,3,8,2,2,7,0,9,2,8,4,2,2,5,0,3,0,3,6
add $0,1
mov $3,$0
mul $3,4
lpb $3
mul $1,$3
sub $1,10
mul $2,$3
add $1,$2
pow $2,2
div $2,$1
cmp $6,0
add $5,$6
div $1,$5
div $2,$5
add $2,$1
sub $3,1
lpe
mov $4,10
pow $4,$0
div $2,$4
div $1,$2
mod $1,10
mov $0,$1
| 19.25 | 201 | 0.523191 |
6af21d64a588898d9a3e9af85527c3819c633f2a | 2,975 | asm | Assembly | ASM_x86/LinuxAPI_11_sigaction.asm | XlogicX/Learn | 96e4b13bbc8c2589d6bf41e24e6d0857c172e3e6 | [
"MIT"
] | 43 | 2015-06-05T19:14:46.000Z | 2022-01-31T20:25:46.000Z | ASM_x86/LinuxAPI_11_sigaction.asm | tuxxy/Learn | 96e4b13bbc8c2589d6bf41e24e6d0857c172e3e6 | [
"MIT"
] | null | null | null | ASM_x86/LinuxAPI_11_sigaction.asm | tuxxy/Learn | 96e4b13bbc8c2589d6bf41e24e6d0857c172e3e6 | [
"MIT"
] | 9 | 2015-09-07T18:31:41.000Z | 2022-02-02T06:39:06.000Z | ;Example of intercepting a signal with our own handler using the signal API. API calls found in this example program:
; signal, write, exit
; High level description of what theis example program does:
; Set up a signal handler to 'handle_it' using signal API
; Proceed into infinite Loop
; In 'handle_it' tell user that 'ctrl+C'd to fuck off,
; then set up new signal handler to exit if ctrl+C is used
; return to infinite Loop
; If Ctrl+C is pressed again, program prints a message indicating defeat and exits
section .text
global _start
_start:
; Set up signal handler to intercept SIGINT (CTRL+C)
;------------------------------------------------------------------------------
mov eax, 48 ; signal
mov ebx, 2 ; SIGINT
mov ecx, handle_it ; Address to signal handler when catching sigint
int 0x80
; Infinit Loop
;------------------------------------------------------------------------------
iloop:
jmp iloop
; Handler for Interupt Signal
;------------------------------------------------------------------------------
handle_it:
mov eax, 4 ; write
mov ebx, 1 ; stdout
mov ecx, message ; '^C <- Nah, Fuck you!'
mov edx, 19 ; how many bytes to print
int 0x80
mov eax, 48 ; new signal
mov ebx, 2 ; SIGINT
mov ecx, exit ; Exit this time
int 0x80
ret ; but for now, go back to our infinite loop
; Exit
;------------------------------------------------------------------------------
exit:
mov eax, 4 ; write
mov ebx, 1 ; stdout
mov ecx, message2 ; '^C Fine...'
mov edx, 9 ; how many bytes to print
int 0x80
mov eax, 1
int 0x80
section .data
message db ' <- Nah, Fuck you!', 0x0a
message2 db ' Fine...', 0x0a
; All the standard signal codez
;------------------------------------------------------------------------------
; 1 - SIGHUP - Hangup
; 2 - SIGINT - Terminal interrupt
; 3 - SIGQUIT - Terminal quit
; 4 - SIGILL - Illegal instruction
; 5 - SIGTRAP - Trace/breakpoint trap
; 6 - SIGABRT - Abort process
; 7 - SIGBUS - Memory access error
; 8 - SIGFPE - Arithmetic exception
; 9 - SIGKILL - Sure Kill
; 10 - SIGUSR1 - User-defined signal 1
; 11 - SIGSEGV - Invalid memory reference
; 12 - SIGUSR2 - User-defined signal 2
; 13 - SIGPIP - Broken pipe
; 14 - SIGALRM - Real-time timer expired
; 15 - SIGTERM - Terminate process
; 16 - SIGSTKFLT - Stack fault on coprocessor
; 17 - SIGCHLD - Child terminated or stopped
; 18 - SIGCONT - Continue if stopped
; 19 - SIGSTOP - Sure stop
; 20 - SIGTSTP - Terminal stop
; 21 - SIGTTIN - Terminal read from BG
; 22 - SIGTTOU - Terminal write from BG
; 23 - SIGURG - Urgent data on socket
; 24 - SIGXCPU - CPU time limit exceeded
; 25 - SIGXFSZ - File size limit exceeded
; 26 - SIGVTALRM - Virtual timer expired
; 27 - SIGPROF - Profiling timer expired
; 28 - SIGWINCH - Terminal window size change
; 29 - SIGIO/POLL- I/O possible
; 30 - SIGPWR - Power about to fail
; 31 - SIGSYS - Invalid system call | 33.426966 | 117 | 0.587899 |
121e5e42a034c6ab5645ce0c785a82700129a9ec | 1,144 | asm | Assembly | programs/oeis/004/A004957.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/004/A004957.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/004/A004957.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A004957: a(n) = ceiling(n*phi^2), where phi is the golden ratio, A001622.
; 0,3,6,8,11,14,16,19,21,24,27,29,32,35,37,40,42,45,48,50,53,55,58,61,63,66,69,71,74,76,79,82,84,87,90,92,95,97,100,103,105,108,110,113,116,118,121,124,126,129,131,134,137,139,142,144,147,150,152,155,158,160,163,165,168,171,173,176,179,181,184,186,189,192,194,197,199,202,205,207,210,213,215,218,220,223,226,228,231,234,236,239,241,244,247,249,252,254,257,260,262,265,268,270,273,275,278,281,283,286,288,291,294,296,299,302,304,307,309,312,315,317,320,323,325,328,330,333,336,338,341,343,346,349,351,354,357,359,362,364,367,370,372,375,377,380,383,385,388,391,393,396,398,401,404,406,409,412,414,417,419,422,425,427,430,432,435,438,440,443,446,448,451,453,456,459,461,464,467,469,472,474,477,480,482,485,487,490,493,495,498,501,503,506,508,511,514,516,519,521,524,527,529,532,535,537,540,542,545,548,550,553,556,558,561,563,566,569,571,574,576,579,582,584,587,590,592,595,597,600,603,605,608,611,613,616,618,621,624,626,629,631,634,637,639,642,645,647,650,652
mov $1,$0
mov $2,$0
pow $2,2
mov $3,$0
lpb $2,1
add $0,2
add $1,1
add $2,1
trn $2,$0
lpe
add $1,$3
| 76.266667 | 959 | 0.710664 |
e8535ece3effb3a5f9231371e607e1e9ce943d9a | 679 | asm | Assembly | oeis/205/A205248.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/205/A205248.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/205/A205248.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A205248: Number of (n+1) X 2 0..1 arrays with the number of clockwise edge increases in every 2 X 2 subblock the same.
; 16,40,112,328,976,2920,8752,26248,78736,236200,708592,2125768,6377296,19131880,57395632,172186888,516560656,1549681960,4649045872,13947137608,41841412816,125524238440,376572715312,1129718145928,3389154437776,10167463313320,30502389939952,91507169819848,274521509459536,823564528378600,2470693585135792,7412080755407368,22236242266222096,66708726798666280,200126180395998832,600378541187996488,1801135623563989456,5403406870691968360,16210220612075905072,48630661836227715208,145891985508683145616
mov $1,3
pow $1,$0
div $1,2
mul $1,24
add $1,16
mov $0,$1
| 67.9 | 498 | 0.849779 |
ab9e18a402c44b9aa4125a1281be5aed94558d27 | 622 | asm | Assembly | libsrc/_DEVELOPMENT/target/rc2014/driver/terminal/rc_01_output_acia/rc_01_output_acia_iterm_msg_putc.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 640 | 2017-01-14T23:33:45.000Z | 2022-03-30T11:28:42.000Z | libsrc/_DEVELOPMENT/target/rc2014/driver/terminal/rc_01_output_acia/rc_01_output_acia_iterm_msg_putc.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 1,600 | 2017-01-15T16:12:02.000Z | 2022-03-31T12:11:12.000Z | libsrc/_DEVELOPMENT/target/rc2014/driver/terminal/rc_01_output_acia/rc_01_output_acia_iterm_msg_putc.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 215 | 2017-01-17T10:43:03.000Z | 2022-03-23T17:25:02.000Z | INCLUDE "config_private.inc"
SECTION code_driver
SECTION code_driver_terminal_output
PUBLIC rc_01_output_acia_iterm_msg_putc
EXTERN rc_01_output_acia_oterm_msg_putc_raw
rc_01_output_acia_iterm_msg_putc:
; enter : c = char to output
; can use: af, bc, de, hl, ix
; char to print is coming from the input terminal
; so it should not be subject to tty emulation
; input terminal must not echo control codes
ld a,c
cp 32
jp nc, rc_01_output_acia_oterm_msg_putc_raw
cp CHAR_LF
jp z, rc_01_output_acia_oterm_msg_putc_raw
ld c,'?'
jp rc_01_output_acia_oterm_msg_putc_raw
| 21.448276 | 52 | 0.755627 |
3f5f747a28bd50696e6abee68953f15ef5092add | 24,745 | asm | Assembly | libsrc/stdio/ansi/f_ansi.asm | Frodevan/z88dk | f27af9fe840ff995c63c80a73673ba7ee33fffac | [
"ClArtistic"
] | 38 | 2021-06-18T12:56:15.000Z | 2022-03-12T20:38:40.000Z | libsrc/stdio/ansi/f_ansi.asm | Frodevan/z88dk | f27af9fe840ff995c63c80a73673ba7ee33fffac | [
"ClArtistic"
] | 2 | 2021-06-20T16:28:12.000Z | 2021-11-17T21:33:56.000Z | libsrc/stdio/ansi/f_ansi.asm | Frodevan/z88dk | f27af9fe840ff995c63c80a73673ba7ee33fffac | [
"ClArtistic"
] | 6 | 2021-06-18T18:18:36.000Z | 2021-12-22T08:01:32.000Z | ;
; Z80 ANSI Library
;
;---------------------------------------------------
; ANSI specifics handling.
; (Intel 8086 to Z80 port)
;
; Optimized for speed in the case of multi-character write requests.
; Original NANSI terminal driver (C) 1986 Daniel Kegel - http://www.kegel.com
; Modifications by Tom Almy without restrictions.
;
; - Port to Z80 and some improvement by Stefano Bodrato - 21/4/2000
; - Small fix on the "set cursor position" range checks - 21/11/2002
;
; MISSING or surely buggy Escapes:
; I - Cursor up and scroll down if on top
; L - Insert lines: to be completed
; M - Delete lines: to be completed
;
;
; $Id: f_ansi.asm,v 1.15 2016-04-04 18:31:22 dom Exp $
;
SECTION code_clib
PUBLIC f_ansi
EXTERN ansi_putc
EXTERN ansi_attr
EXTERN ansi_CHAR
EXTERN ansi_cls
EXTERN ansi_LF
EXTERN ansi_DSR6
EXTERN ansi_BEL
EXTERN ansi_del_line
EXTERN __console_w
EXTERN __console_h
EXTERN __console_x
EXTERN __console_y
;---------------------------------------------------
; Fire out all the buffer (pointed by HL; len DE)
;---------------------------------------------------
.f_ansi
ld a,d
or e
ret z
.show
; **** Link to ANSI engine ****
ld bc,(escvector)
ld a,b
or c
jp nz,f_in_escape
ld a,(hl)
inc hl
dec de
cp 27
jp z,f_escape
; Hide the following two lines to disable CSI.
cp 155 ;h9b ;CSI?
jp z,f_9b
; *****************************
;------------------------
cp 12 ; Form Feed (CLS) ?
;------------------------
jr nz,noFF
call docls
jr loopn
.noFF
;------------------------
; cp 13 ; CR?
;------------------------
; jr nz,NoCR
; ld a,(__console_x)
; xor a
; ld (__console_x),a
; jr loopn
;.NoCR
;------------------------
; Temporary (?) patch.
; CR becomes CR+LF
;------------------------
cp 13
jr z,isLF
;------------------------
cp 10 ; LF?
jr nz,NoLF
;------------------------
.isLF
;------------------------
;
push hl
push de
call ansi_LF
pop de
pop hl
jr loopn
.NoLF
cp 9 ; TAB?
jr nz,NoTAB
push hl
push de
ld a,(__console_x)
rra
rra
inc a
rla
rla
push hl
ld hl,__console_w
cp (hl)
pop hl
jp p,OutTAB
ld (__console_x),a
.OutTAB
pop de
pop hl
jr loopn
.NoTAB
;------------------------
cp 7 ; BEL?
;------------------------
jr nz,NoBEL
push hl
push de
call ansi_BEL
pop de
pop hl
jr loopn
.NoBEL
;------------------------
cp 8 ; BackSpace
;------------------------
jr nz,NoBS
ld a,(__console_x)
and a
jr z,firstc ; are we in the first column?
dec a
ld (__console_x),a
jr loopn
.firstc
ld a,(__console_y)
and a
jr z,loopn
dec a
ld (__console_y),a
ld a,(__console_w)
dec a
ld (__console_x),a
jr loopn
.NoBS
; **** Link to ANSI engine ****
.f_not_ANSI ;
push hl
push de
call ansi_putc
pop de
pop hl
.loopn
ld a,d
or e
jp nz,show
.f_loopdone
ret
; *****************************
;------------------------------------------------
; Clear screen and set text position to HOME
;------------------------------------------------
.docls
push hl
push de
push bc
call ansi_cls
xor a ; HOME cursor
ld (__console_y),a
ld (__console_x),a
pop bc
pop de
pop hl
ret
; A state machine implementation of the mechanics of ANSI terminal control
; string parsing.
;
; Entered with a jump to f_escape when driver finds an escape, or
; to f_in_escape when the last string written to this device ended in the
; middle of an escape sequence.
;
; Exits by jumping to f_ANSI_exit when an escape sequence ends, or
; to f_not_ANSI when a bad escape sequence is found, or (after saving state)
; to f_loopdone when the write ends in the middle of an escape sequence.
;
; Parameters are stored as bytes in param_buffer. If a parameter is
; omitted, it is stored as zero. Each character in a keyboard reassignment
; command counts as one parameter.
;
; When a complete escape sequence has been parsed, the address of the
; ANSI routine to call is found in ansi_fn_table.
;
; Register usage during parsing:
; HL points to the incoming string.
; DE holds the length remaining in the incoming string.
; BC is the (incrementing) pointer to param_buffer
.f_ANSI_exit
ld bc,0
ld (escvector), bc
jp loopn
;----- f_in_escape ---------------------------------------------------
; Main loop noticed that escvector was not zero.
; Recall value of BC saved when sleep was jumped to, and jump into parser.
.f_in_escape
ld bc, (escvector)
push bc
ld bc, (cur_parm_ptr)
ret
;----- syntax_error ---------------------------------------
; A character was rejected by the state machine. Exit to
; main loop, and print offending character. Let main loop
; decrement DE (length of input string).
.syntax_error
ld bc,0
ld (escvector), bc
jp f_not_ANSI ; exit, print offending char
;----- f_escape ------------------------------------------------------
; We found an escape. Next character should be a left bracket.
.f_escape
; next_is f_bracket
ld a,d
or e
jr nz, f_bracket
ld bc, f_bracket
ld (escvector), bc
jp f_loopdone
;----- f_bracket -----------------------------------------------------
; Last char was an escape. This one should be a [; if not, print it.
; Next char should begin a parameter string.
.f_bracket
ld a, (hl)
inc hl
dec de
cp '['
jr nz, syntax_error
.f_9b ; Entry for CSI. (Eq. ESC[)
; Set up for getting a parameter string.
ld bc, param_buffer
xor a ; zero
ld (bc), a ; default first char
dec bc ; point buffer before start
ld (eat_key), a ; no eaten key
; next_is f_get_args
ld a,d
or e
jr nz, f_get_args
ld (cur_parm_ptr), bc
ld bc, f_get_args
ld (escvector), bc
jp f_loopdone
;----- f_get_args ---------------------------------------------------
; Last char was a [. If the current char is a '=' or a '?', save
; it for SET/RESET MODE, and then proceed to f_get_param.
.f_get_args
ld a,(hl)
inc hl
dec de
cp '='
jr z, fga_ignore
cp '?'
jr nz, get_param_B
.fga_ignore
ld (eat_key), a ; save = or ?
; next_is f_get_param
ld a,d
or e
jr nz, f_get_param
ld (cur_parm_ptr), bc
ld bc, f_get_param
ld (escvector), bc
jp f_loopdone
;----- f_get_param ---------------------------------------------------
; Last char was one of the four characters "]?=;".
; We are getting the first digit of a parameter, a quoted string,
; a ;, or a command.
.f_get_param
ld a,(hl)
inc hl
dec de
.get_param_B ; jump to here if no fetch of character
cp '0'
jp m, fgp_may_quote
cp '9'+1
jp p, fgp_may_quote
; if bc <param_end bc++
push hl
ld h,b
ld l,c
push bc
ld bc,param_end
sbc hl,bc
pop bc
pop hl
jr nc,NoBCinc
inc bc
.NoBCinc
; It's the first digit. Initialize parameter with it.
sub '0'
ld (bc), a
; next_is f_in_param
ld a,d
or e
jp nz, f_in_param
ld (cur_parm_ptr), bc
ld bc, f_in_param
ld (escvector), bc
jp f_loopdone
.fgp_may_quote
cp '"'
jr z, fgp_isquote
cp '\\'
jp nz, fgp_semi_or_cmd ; jump to code shared with f_in_param
.fgp_isquote
ld (string_term), a ; save it for end of string
; and read string into param_buffer ; next_is f_get_string
ld a,d
or e
jr nz, f_get_string
ld (cur_parm_ptr), bc
ld bc, f_get_string
ld (escvector), bc
jp f_loopdone
.fgp_semi_or_cmd
cp ';' ; is it a semi?
jp nz, fgp_cmd ; no, then it's a command
; if bc <param_end bc++
push hl
ld h,b
ld l,c
push bc
ld bc,param_end
sbc hl,bc
pop bc
pop hl
jr nc,NoBCinc2
inc bc
.NoBCinc2
xor a ; zero
ld (bc), a ; it is a zero parameter
.f_goto_next
;next_is f_get_param
ld a,d
or e
jr nz, f_get_param
ld (cur_parm_ptr), bc
ld bc, f_get_param
ld (escvector), bc
jp f_loopdone
;----- f_get_string -------------------------------------
; Last character was a quote or a string element.
; Get characters until ending quote found.
.f_get_string
ld a, (hl)
inc hl
dec de
push hl
ld hl, string_term
cp (hl)
pop hl
jr z, fgs_init_next_param
; if bc <param_end bc++
push hl
ld h,b
ld l,c
push bc
ld bc,param_end
sbc hl,bc
pop bc
pop hl
jr nc,NoBCinc3
inc bc
.NoBCinc3
ld (bc), a
;next_is f_get_string
ld a,d
or e
jr nz, f_get_string
ld (cur_parm_ptr), bc
ld bc, f_get_string
ld (escvector), bc
jp f_loopdone
; Ending quote was found.
.fgs_init_next_param
;next_is f_eat_semi
ld a,d
or e
jr nz, f_eat_semi
ld (cur_parm_ptr), bc
ld bc, f_eat_semi
ld (escvector), bc
jp f_loopdone
;----- f_eat_semi -------------------------------------
; Last character was an ending quote.
; If this char is a semi, eat it
; Then goto f_get_param
.f_eat_semi
ld a,(hl)
inc hl
dec de
cp ';'
jp nz, get_param_B
jr f_goto_next
;------ f_in_param -------------------------------------
; Last character was a digit.
; Looking for more digits, a semicolon, or a command character.
.f_in_param
ld a,(hl)
inc hl
dec de
cp '0'
jp m, fgp_not_digit
cp '9'+1
jp p, fgp_not_digit
; It's another digit. Add into current parameter.
sub '0'
push bc
push af
ld a, (bc)
ld c,a
ld b,9
.Per10
add a, c
djnz Per10
ld c,a
pop af
add a, c
pop bc
ld (bc), a
;next_is f_in_param
ld a,d
or e
jr nz, f_in_param
ld (cur_parm_ptr), bc
ld bc, f_in_param
ld (escvector), bc
jp f_loopdone
.fgp_not_digit
cp ';'
jp z, f_goto_next
.fgp_cmd
; It must be a command letter.
push hl
push de
;Count no. of parameters in reg. B
ld h,b
ld l,c
ld bc,param_buffer
dec bc
scf
ccf
sbc hl,bc
ld b,l
; if B=0 -> set to 1 first parameter (B is still = 0)
inc b
dec b
jr nz,no_default
push af
ld hl,param_buffer
ld a,1
ld (hl),a
pop af
.no_default
; Command interpreter
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%% m %%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%%%%%%%% Set graphic rendition %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'm'
jp nz,no_m
inc b
dec b
jr nz,m_nodefault
ld hl,param_buffer
ld a,0
ld (hl),a
inc b
.m_nodefault
ld hl,param_buffer
.loop_m
ld a,(hl)
call ansi_attr
inc hl
dec b
jp nz,loop_m
jp f_cmd_exit
.no_m
;.temp jp f_cmd_exit
;%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%% C %%%%%%%%%%%%%%%%%%%%%%
;%%%%%%%% Cursor forward %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'C' ; CUF - Cursor foreward
jr nz,no_C
ld hl,param_buffer
ld a,(__console_x)
add a,(hl)
push bc
push af
ld a,(__console_w)
ld b,a
pop af
inc b
cp b
pop bc
jp p, no_C_FWD
ld (__console_x),a
jp f_cmd_exit
.no_C_FWD
ld a,(__console_w)
dec a
ld (__console_x),a
jp f_cmd_exit
.no_C
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%% D %%%%%%%%%%%%%%%%%%%%%%%
;%%%%%%%% Cursor backward %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'D' ; CUB - Cursor backward
jr nz,no_D
ld hl,param_buffer
ld a,(__console_x)
sub (hl)
jp nc, no_D_TOP
xor a
.no_D_TOP
ld (__console_x),a
jp f_cmd_exit
.no_D
;%%%%%%%%%%%%%%%%%%%%%%
;%% A %%%%%%%%%%%%%%%%%
;%%%%%%%% Cursor UP %%%
;%%%%%%%%%%%%%%%%%%%%%%
cp 'A' ; CUU - Cursor up
jr nz,no_A
ld hl,param_buffer
.f_ansi_cup
ld a,(__console_y)
sub (hl)
jp p, no_A_TOP
xor a
.no_A_TOP
ld (__console_y),a
jp f_cmd_exit
.no_A
;%%%%%%%%%%%%%%%%%%%%%%%%
;%% B %%%%%%%%%%%%%%%%%%%
;%%%%%%%% Cursor DOWN %%%
;%%%%%%%%%%%%%%%%%%%%%%%%
cp 'B' ; CUD - Cursor down
jr nz,no_B
ld hl,param_buffer
ld a,(__console_y)
add a,(hl)
push bc
push af
ld a,(__console_h)
ld b,a
pop af
inc b
cp b
pop bc
jp p, no_B_FWD
ld (__console_y),a
jp f_cmd_exit
.no_B_FWD
ld a,(__console_h)
dec a
ld (__console_y),a
jp f_cmd_exit
.no_B
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%% s - j %%%%%%%%%%%%%%%%%%%%
;%%%%%%%% save cursor pos. %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cp 's' ; SCP - Save cursor position
jr z,do_s
cp 'j'
jr nz,no_s
.do_s
ld a,(__console_x)
ld (scp_x),a
ld a,(__console_y)
ld (scp_y),a
jp f_cmd_exit
.no_s
;%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%% u - k %%%%%%%%%%%%%%%%%%
;%%%%%%%% r. cursor pos. %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'u' ; RCP - Restore cursor position
jr z,do_u
cp 'k'
jr nz,no_u
.do_u
ld a,(scp_x)
ld (__console_x),a
ld a,(scp_y)
ld (__console_y),a
jp f_cmd_exit
.no_u
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%% H %%%%%%%%%%%%%%%%%%%%%%%
;%%%%%%%% SET cursor pos. %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'f' ; HVP not fully functional
jr z,IsHVP
cp 'H' ; CUP - Cursor position
jr nz,no_H
.IsHVP
inc b
dec b
jr nz,H_Nodeflt
ld hl,param_buffer
ld a,1
ld (hl),a
inc hl
ld (hl),a
.H_Nodeflt
dec b
jr nz,H_nodef1
ld hl,param_buffer
inc hl
ld a,1
ld (hl),a
.H_nodef1
ld hl,param_buffer ; point to row
ld a,(hl)
and a
jr z,HLineOK
push hl
dec a
ld hl,__console_h
cp (hl)
pop hl
jr c,HLineOK
ld a,(__console_h) ; position next char at max possible row
dec a
.HLineOK
ld (__console_y),a
inc hl ; point to column
ld a,(hl)
and a
jr z,HColOK
dec a ; char position
ld hl,__console_w
cp (hl)
jr c,HColOK
ld a,(__console_w) ; position next char at max possible column
dec a
.HColOK
ld (__console_x),a
jp f_cmd_exit
.no_H
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%% b %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%%%%%%%% Erase from start of display %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'b'
jr z,is_J1_b
;%%%%%%%%%%%%%%%%
;%% J %%%%%%%%%%%
;%%%%%%%% CLS %%%
;%%%%%%%%%%%%%%%%
cp 'J' ; ED - Erase in display
jp nz,no_J
inc b
dec b
jr nz,J_nodefault
ld hl,param_buffer
ld a,0
ld (hl),a
; inc b --not useful (1 parameter only)
.J_nodefault
ld hl,param_buffer
ld a,(hl)
and a ; from cursor to end of screen
jr nz,no_J_0
; First, from cursor to EOL
ld a,(__console_y)
push af
ld a,(__console_x)
push af
.j0loop
push af
ld a,32 ;' ' ; BLANK
call ansi_CHAR ; The low level video routine
pop af
inc a
ld (__console_x),a
ld hl,__console_w
cp (hl)
jp m,j0loop
pop af
ld (__console_x),a ; restore orig. cursor pos.
pop af
ld (__console_y),a ; restore orig. cursor pos.
; Then, from the cursor line + 1 up to the last line
.j0LineLoop
inc a
inc a
ld hl,__console_h
cp (hl)
jp z,f_cmd_exit
;dec a
push af
call ansi_del_line
pop af
jr j0LineLoop
.no_J_0
cp 1 ; from (0;0) to cursor
jr nz,no_J_1
.is_J1_b
; First, from cursor to 0
ld a,(__console_y)
push af
ld a,(__console_x)
push af
.j1loop
push af
ld a,32 ;' ' ; BLANK
call ansi_CHAR ; The low level video routine
pop af
dec a
ld (__console_x),a
cp 0
jp p,j1loop
pop af
ld (__console_x),a ; restore orig. cursor pos.
pop af
ld (__console_y),a ; restore orig. cursor pos.
; Then, from the cursor line - 1 up to 0
and a
jp z,f_cmd_exit
.j1LineLoop
dec a
push af
call ansi_del_line
pop af
cp 0
jp p,j1LineLoop
jp f_cmd_exit
.no_J_1
cp 2 ; entire screen (+home cursor [non-standard])
jp nz,f_cmd_exit ; Syntax Error!
; clear all screen
call docls
jp f_cmd_exit
.no_J
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%% o %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%%%%%%%% Erase from start of line %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'o'
jr z,is_K1_o
;%%%%%%%%%%%%%%%%%%%%%%%%%%
;%% K %%%%%%%%%%%%%%%%%%%%%
;%%%%%%%% Erase in line %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'K' ; EL - Erase in line
jp nz,no_K
inc b
dec b
jr nz,K_nodefault
ld hl,param_buffer
ld a,0
ld (hl),a
; inc b --not useful (1 parameter only)
.K_nodefault
ld hl,param_buffer
ld a,(hl)
and a ; From cursor to end of line
jr nz,no_K_0
ld a,(__console_x)
push af
.K0loop
push af
ld a,32 ; ' ' ; BLANK
call ansi_CHAR ; The low level video routine
pop af
inc a
ld (__console_x),a
ld hl,__console_w
cp (hl)
jp m,K0loop
pop af
ld (__console_x),a ; restore orig. cursor pos.
.no_K_0
cp 1 ; From beginning of line to cursor
jr nz,no_K_1
.is_K1_o
ld a,(__console_x)
push af
.K1loop
push af
ld a,32 ;' ' ; BLANK
call ansi_CHAR ; The low level video routine
pop af
dec a
ld (__console_x),a
cp 0
jp p,K1loop
pop af
ld (__console_x),a ; restore orig. cursor pos.
jp f_cmd_exit
.no_K_1
cp 2 ; entire screen (+home cursor [non-standard])
jp nz,f_cmd_exit ; Syntax Error!
ld a,(__console_y)
call ansi_del_line
jp f_cmd_exit
.no_K
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%% l %%%%%%%%%%%%%%%%%%%%%%%%%%
;%%%%%%%% Erase current line %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'l'
jr nz,noecl
ld a,(__console_y)
call ansi_del_line
jp f_cmd_exit
.noecl
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%% n %%%%%%%%%%%%%%%%%%%%%%%%%%%%
;%%%%%%%% Device Status Report %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'n' ; DSR - Device status report
jp nz,no_n
inc b
dec b
jp z, f_cmd_exit ; only mode 6 is supported
.n_nodefault
ld hl,param_buffer
ld a,(hl)
cp 6
jp z, f_cmd_exit ; only mode 6 is supported
call ansi_DSR6
jp f_cmd_exit
.no_n
;%%%%%%%%%%%%%%%%%%%%%%%%%
;%% L %%%%%%%%%%%%%%%%%%%%
;%%%%%%%% Insert Lines %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'L' ; IL - Insert lines
jr nz,no_L
ld hl,param_buffer
ld b,(hl)
ld a,(__console_y)
jp f_cmd_exit
.no_L
;%%%%%%%%%%%%%%%%%%%%%%%%%
;%% M %%%%%%%%%%%%%%%%%%%%
;%%%%%%%% Delete Lines %%%
;%%%%%%%%%%%%%%%%%%%%%%%%%
cp 'M' ; DL - Delete lines
jr nz,no_MM
ld hl,param_buffer
ld a,(hl)
.no_MM
;%% E X I T %%
.f_cmd_exit
pop de
pop hl
jp f_ANSI_exit
;-----------------------------------------
; Variables declaration
;-----------------------------------------
SECTION bss_clib
.scp_x defb 0
.scp_y defb 0
.escvector defw 0
.cur_parm_ptr defw 0
.eat_key defb 0
.string_term defb 0
.param_buffer defs 40
.param_end defw 0
| 25.275792 | 78 | 0.396686 |
41f5ee8257021ea25e6267cb996ad720ffd55f1d | 343 | asm | Assembly | programs/oeis/051/A051066.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/051/A051066.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/051/A051066.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A051066: Partial sums of A051065.
; 0,1,1,1,2,2,2,3,3,4,4,5,6,6,7,8,8,9,9,10,10,10,11,11,11,12,12,12,13,13,13,14,14,14,15,15,16,16,17,18,18,19,20,20,21,21,22,22,22,23,23,23,24,24,24,25,25,25,26,26,26,27,27,28,28,29,30,30,31,32,32,33,33,34,34
lpb $0
mov $2,$0
sub $0,1
seq $2,51065 ; a(n) = A004128(n) mod 2.
add $1,$2
lpe
mov $0,$1
| 31.181818 | 207 | 0.606414 |
5b56979167773de5468c4b03a095cf3f3d7fdaf9 | 5,464 | asm | Assembly | source/damage.asm | evanbowman/Red | 85735269a46757305a81ad39f47034bc6cd97846 | [
"BSD-2-Clause"
] | 5 | 2021-08-30T16:18:55.000Z | 2021-10-30T20:23:32.000Z | source/damage.asm | evanbowman/gbc-project | 85735269a46757305a81ad39f47034bc6cd97846 | [
"BSD-2-Clause"
] | null | null | null | source/damage.asm | evanbowman/gbc-project | 85735269a46757305a81ad39f47034bc6cd97846 | [
"BSD-2-Clause"
] | null | null | null | ;;; $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
;;;
;;; ASM Source code for Red GBC, by Evan Bowman, 2021
;;;
;;;
;;; The following licence covers the source code included in this file. The
;;; game's characters and artwork belong to Evan Bowman, and should not be used
;;; without permission.
;;;
;;;
;;; Redistribution and use in source and binary forms, with or without
;;; modification, are permitted provided that the following conditions are met:
;;;
;;; 1. Redistributions of source code must retain the above copyright notice,
;;; this list of conditions and the following disclaimer.
;;;
;;; 2. Redistributions in binary form must reproduce the above copyright notice,
;;; this list of conditions and the following disclaimer in the documentation
;;; and/or other materials provided with the distribution.
;;;
;;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;;; SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;;; POSSIBILITY OF SUCH DAMAGE.
;;;
;;; $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
;;; Really bad, but who even cares? It's only for calculating damage, and
;;; doesn't take up much space in ROM.
SoftwareMul:
;;; hl - number
;;; a - repetitions
;;; trashes b, de
ld d, h
ld e, l
ld hl, 0
.loop:
ld b, 0
cp b
jr Z, .endLoop
add hl, de
dec a
jr .loop
.endLoop:
ret
;;; ----------------------------------------------------------------------------
Mul16:
;;; hl - number
;; FIXME: `add hl, hl` repeatedly might be faster :)
swap h
ld a, h
and $f0
ld h, a
ld a, l
swap a
and $0f
or h
ld h, a
ld a, l
swap a
and $f0
ld l, a
ret
;;; ----------------------------------------------------------------------------
Div16:
;;; hl - number
swap l
ld a, l
and $0f
ld l, a
ld a, h
swap a
and $f0
or l
ld l, a
ld a, h
swap a
and $0f
ld h, a
ret
;;; ----------------------------------------------------------------------------
CalculateDamage:
;;; hl - attack base damage
;;; b - attacker's attack
;;; c - defender's defense
;;; Damage = B + ((B / 16) * A) - ((B / 16) * D)
fcall Mul16
push hl
push hl ; Store original base damage
fcall Div16 ; \
ld a, b ; | (Damage / 16) * Attacker's attack power
push bc ; | Preserve c for defense calc later
fcall SoftwareMul ; /
pop bc ; restore c
push hl ; \ copy hl -> de
pop de ; /
pop hl ; Restore base damage
push de ; Store above calculation on stack
push hl ; Store original base damage
fcall Div16 ; \
ld a, c ; | Damage / 16 * Defender's defense power
fcall SoftwareMul ; /
push hl ; \ copy hl -> bc
pop bc ; /
pop hl ; Restore base damage
pop de ; Restore first calculation
add hl, de
ld a, b ; \
cpl ; |
ld b, a ; |
ld a, c ; | Convert bc to a negative number.
cpl ; |
ld c, a ; |
inc bc ; /
add hl, bc
jr NC, .negative
fcall Div16
pop bc ; see push at fn top
ret
;;; FIXME: if the defender's defense is way larger than the attacker's attack,
;;; the damage calculation can return a negative number. Instead, we return the
;;; weapon base damage divided by 16, as a placeholder. We could instead deal
;;; zero damage, or a tiny amount, but that's no fun.
.negative:
pop hl
fcall Div16
ret
;;; ----------------------------------------------------------------------------
FormatDamage:
;;; hl - damage
;;; bc - result
ld a, l
swap a
and $f0
ld c, a
ld a, l
swap a
and $0f
ld b, a
ld a, h
and $0f
swap a
or b
ld b, a
ret
;;; ----------------------------------------------------------------------------
| 27.049505 | 80 | 0.449122 |
7a025a68f993a27fb8fd55178cec7d1e72b38309 | 528 | asm | Assembly | ssu-sys-programming/src/lab2/task1.asm | Imperat/SSU-Information-Security-Course | 24c04cb8b4da0231d65d587e981e15b1fefc19eb | [
"Apache-2.0"
] | null | null | null | ssu-sys-programming/src/lab2/task1.asm | Imperat/SSU-Information-Security-Course | 24c04cb8b4da0231d65d587e981e15b1fefc19eb | [
"Apache-2.0"
] | null | null | null | ssu-sys-programming/src/lab2/task1.asm | Imperat/SSU-Information-Security-Course | 24c04cb8b4da0231d65d587e981e15b1fefc19eb | [
"Apache-2.0"
] | null | null | null | .model small
.stack 100h
.data
D_ONE dw 04h
D_TWO dw 03h
SPACE db 20h
.code
printd proc
mov bh, al
mov ah, 02h
int 21h
mov al, bh
ret
printd endp
start: mov ax, @data
mov ds, ax
;Запись цифр в регистры
mov ax, D_ONE
add ax, 30h
mov bx, D_TWO
add bx, 30h
;Вывод первой цифры
mov dl, al
call printd
;Вывод пробела
mov dl, SPACE
mov ah, 02h
int 21h
;Вывод второй
mov dl, bl
call printd
mov dx, 13
int 21h
mov ah, 02h
mov dx, 10
int 21h
mov ax, 4c00h
int 21h
end start | 11 | 24 | 0.642045 |
f8d0f7223969025041cc72930e105b1f5c55dd28 | 287 | asm | Assembly | libsrc/_DEVELOPMENT/adt/bv_priority_queue/c/sdcc_iy/bv_priority_queue_max_size.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/adt/bv_priority_queue/c/sdcc_iy/bv_priority_queue_max_size.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/adt/bv_priority_queue/c/sdcc_iy/bv_priority_queue_max_size.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null |
; size_t bv_priority_queue_max_size(bv_priority_queue_t *q)
SECTION code_adt_bv_priority_queue
PUBLIC _bv_priority_queue_max_size
EXTERN asm_bv_priority_queue_max_size
_bv_priority_queue_max_size:
pop af
pop hl
push hl
push af
jp asm_bv_priority_queue_max_size
| 15.105263 | 59 | 0.818815 |
f97838329e9b4a72863d2ad629e2e00fcac32a14 | 2,497 | asm | Assembly | libs/CPC_V1_SimpleScreenSetup.asm | CurlyPaul/cpc-z80-poc | 93515b8fea39c05694378c48dac1a327dfad347b | [
"MIT"
] | null | null | null | libs/CPC_V1_SimpleScreenSetup.asm | CurlyPaul/cpc-z80-poc | 93515b8fea39c05694378c48dac1a327dfad347b | [
"MIT"
] | null | null | null | libs/CPC_V1_SimpleScreenSetup.asm | CurlyPaul/cpc-z80-poc | 93515b8fea39c05694378c48dac1a327dfad347b | [
"MIT"
] | null | null | null |
Screen_Init:
; Sets the screen to 16 colour/160 wide mode
ld a,0
call &BC0E ; scr_set_mode 0 - 16 colors
ret
; This is the screen address table for a standard screen
; Each word in the table is the memory address offest for the start of each screen line
; eg line 1 is at 0000 (scr_start_adr +C000 normally)
; line 2 is at 0800
; line 3 is at 1000
; line 4 is at 1800
; line 5 is at 2000 etc
align2
scr_addr_table:
defb &00,&00, &00,&08, &00,&10, &00,&18, &00,&20, &00,&28, &00,&30, &00,&38;1
defb &50,&00, &50,&08, &50,&10, &50,&18, &50,&20, &50,&28, &50,&30, &50,&38;2
defb &A0,&00, &A0,&08, &A0,&10, &A0,&18, &A0,&20, &A0,&28, &A0,&30, &A0,&38;3
defb &F0,&00, &F0,&08, &F0,&10, &F0,&18, &F0,&20, &F0,&28, &F0,&30, &F0,&38;4
defb &40,&01, &40,&09, &40,&11, &40,&19, &40,&21, &40,&29, &40,&31, &40,&39;5
defb &90,&01, &90,&09, &90,&11, &90,&19, &90,&21, &90,&29, &90,&31, &90,&39;6
defb &E0,&01, &E0,&09, &E0,&11, &E0,&19, &E0,&21, &E0,&29, &E0,&31, &E0,&39;7
defb &30,&02, &30,&0A, &30,&12, &30,&1A, &30,&22, &30,&2A, &30,&32, &30,&3A;8
defb &80,&02, &80,&0A, &80,&12, &80,&1A, &80,&22, &80,&2A, &80,&32, &80,&3A;9
defb &D0,&02, &D0,&0A, &D0,&12, &D0,&1A, &D0,&22, &D0,&2A, &D0,&32, &D0,&3A;10
defb &20,&03, &20,&0B, &20,&13, &20,&1B, &20,&23, &20,&2B, &20,&33, &20,&3B;11
defb &70,&03, &70,&0B, &70,&13, &70,&1B, &70,&23, &70,&2B, &70,&33, &70,&3B;12
defb &C0,&03, &C0,&0B, &C0,&13, &C0,&1B, &C0,&23, &C0,&2B, &C0,&33, &C0,&3B;13
defb &10,&04, &10,&0C, &10,&14, &10,&1C, &10,&24, &10,&2C, &10,&34, &10,&3C;14
defb &60,&04, &60,&0C, &60,&14, &60,&1C, &60,&24, &60,&2C, &60,&34, &60,&3C;15
defb &B0,&04, &B0,&0C, &B0,&14, &B0,&1C, &B0,&24, &B0,&2C, &B0,&34, &B0,&3C;16
defb &00,&05, &00,&0D, &00,&15, &00,&1D, &00,&25, &00,&2D, &00,&35, &00,&3D;17
defb &50,&05, &50,&0D, &50,&15, &50,&1D, &50,&25, &50,&2D, &50,&35, &50,&3D;18
defb &A0,&05, &A0,&0D, &A0,&15, &A0,&1D, &A0,&25, &A0,&2D, &A0,&35, &A0,&3D;19
defb &F0,&05, &F0,&0D, &F0,&15, &F0,&1D, &F0,&25, &F0,&2D, &F0,&35, &F0,&3D;20
defb &40,&06, &40,&0E, &40,&16, &40,&1E, &40,&26, &40,&2E, &40,&36, &40,&3E;21
defb &90,&06, &90,&0E, &90,&16, &90,&1E, &90,&26, &90,&2E, &90,&36, &90,&3E;22
defb &E0,&06, &E0,&0E, &E0,&16, &E0,&1E, &E0,&26, &E0,&2E, &E0,&36, &E0,&3E;23
defb &30,&07, &30,&0F, &30,&17, &30,&1F, &30,&27, &30,&2F, &30,&37, &30,&3F;24
defb &80,&07, &80,&0F, &80,&17, &80,&1F, &80,&27, &80,&2F, &80,&37, &80,&3F;25 | 60.902439 | 87 | 0.501001 |
deccffcf0c134bf1b200657b9e06cdfeb39a4915 | 966 | asm | Assembly | Platform Code/LAPIS_SensorPlatform_Firmware/Firmware/_output/_obj/tbc.asm | kbahar/ROHM_SensorPlatform_Multi-Sensor-Shield | 9d00077c29b1241ea5ddbb05d4bff57d327b8f2e | [
"Unlicense"
] | null | null | null | Platform Code/LAPIS_SensorPlatform_Firmware/Firmware/_output/_obj/tbc.asm | kbahar/ROHM_SensorPlatform_Multi-Sensor-Shield | 9d00077c29b1241ea5ddbb05d4bff57d327b8f2e | [
"Unlicense"
] | null | null | null | Platform Code/LAPIS_SensorPlatform_Firmware/Firmware/_output/_obj/tbc.asm | kbahar/ROHM_SensorPlatform_Multi-Sensor-Shield | 9d00077c29b1241ea5ddbb05d4bff57d327b8f2e | [
"Unlicense"
] | null | null | null | ;; Compile Options : /TML610112 /MS /near /Icommon /Imain /Iirq /Itimer /Iclock /Itbc /Iuart /Ii2c /SS 256 /SD /Oa /Ot /W 3 /Wc /Fa_output\_obj\
;; Version Number : Ver.3.41.8
;; File Name : tbc.c
type (ML610112)
model small, near
CVERSION 3.41.8
CSTRUCTTAG 0000H 0000H 0000H 0008H 00000001H "_Notag"
CSTRUCTMEM 52H 00000001H 00000000H "b0" 02H 00H 00H
CSTRUCTMEM 52H 00000001H 00000001H "b1" 02H 00H 00H
CSTRUCTMEM 52H 00000001H 00000002H "b2" 02H 00H 00H
CSTRUCTMEM 52H 00000001H 00000003H "b3" 02H 00H 00H
CSTRUCTMEM 52H 00000001H 00000004H "b4" 02H 00H 00H
CSTRUCTMEM 52H 00000001H 00000005H "b5" 02H 00H 00H
CSTRUCTMEM 52H 00000001H 00000006H "b6" 02H 00H 00H
CSTRUCTMEM 52H 00000001H 00000007H "b7" 02H 00H 00H
CTYPEDEF 0000H 0000H 43H "_BYTE_FIELD" 04H 00H 05H 00H 00H
CFILE 0001H 00000023H "main\\mcu.h"
CFILE 0002H 0000085AH "main\\ML610112.H"
CFILE 0003H 00000046H "tbc\\tbc.h"
CFILE 0000H 0000002CH "tbc\\tbc.c"
extrn code near : _main
end
| 38.64 | 145 | 0.753623 |
ede1c26bfa50796cc860404a05c4253abe6a4ee3 | 303 | asm | Assembly | programs/oeis/155/A155456.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/155/A155456.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/155/A155456.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A155456: Write (1+1/x)*log(1+x) = Sum c(n)*x^n; then a(n) = (n+1)!*c(n).
; -1,-1,1,-2,6,-24,120,-720,5040,-40320,362880,-3628800,39916800,-479001600,6227020800,-87178291200,1307674368000,-20922789888000,355687428096000,-6402373705728000
mov $1,1
mov $2,2
sub $2,$0
sub $2,1
fac $2
add $2,1
sub $1,$2
| 27.545455 | 163 | 0.666667 |
e188d3468b3d83ab656d5e1e006ce0bfc69b7de9 | 2,874 | asm | Assembly | libsrc/z80_crt0s/8080/sccz80/l_long_mult.asm | Frodevan/z88dk | f27af9fe840ff995c63c80a73673ba7ee33fffac | [
"ClArtistic"
] | 38 | 2021-06-18T12:56:15.000Z | 2022-03-12T20:38:40.000Z | libsrc/z80_crt0s/8080/sccz80/l_long_mult.asm | Frodevan/z88dk | f27af9fe840ff995c63c80a73673ba7ee33fffac | [
"ClArtistic"
] | 2 | 2021-06-20T16:28:12.000Z | 2021-11-17T21:33:56.000Z | libsrc/z80_crt0s/8080/sccz80/l_long_mult.asm | Frodevan/z88dk | f27af9fe840ff995c63c80a73673ba7ee33fffac | [
"ClArtistic"
] | 6 | 2021-06-18T18:18:36.000Z | 2021-12-22T08:01:32.000Z | ;Copyright (c) 1987, 1990, 1993, 2005 Vrije Universiteit, Amsterdam, The Netherlands.
;All rights reserved.
;
;Redistribution and use of the Amsterdam Compiler Kit in source and
;binary forms, with or without modification, are permitted provided
;that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
;
; * Redistributions in binary form must reproduce the above
; copyright notice, this list of conditions and the following
; disclaimer in the documentation and/or other materials provided
; with the distribution.
;
; * Neither the name of Vrije Universiteit nor the names of the
; software authors or contributors may be used to endorse or
; promote products derived from this software without specific
; prior written permission.
;
;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS, AUTHORS, AND
;CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
;INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
;MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
;IN NO EVENT SHALL VRIJE UNIVERSITEIT OR ANY AUTHORS OR CONTRIBUTORS BE
;LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
;BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
;OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
;EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SECTION code_crt0_sccz80
PUBLIC l_long_mult
EXTERN __retloc, __math_rhs, __math_lhs, __math_result
; 32 bits signed and unsigned integer multiply routine
; Expects operands on stack
; Yields product on stack
; Liberated from ack
l_long_mult:
LD (__math_rhs),HL ; store multiplier
ex de,hl
LD (__math_rhs+2),HL
POP HL
LD (__retloc),HL
POP HL ; store multiplicand
LD (__math_lhs),HL
POP HL
LD (__math_lhs+2),HL
LD HL,0
LD (__math_result),HL
LD (__math_result+2),HL
LD BC,0
lp1: LD HL,__math_rhs
ADD HL,BC
LD a,(HL) ; get next byte of multiplier
LD b,8
lp2: RRA
JP NC,dont_add
LD HL,(__math_lhs) ; add multiplicand to product
EX DE,HL
LD HL,(__math_result)
ADD HL,DE
LD (__math_result),HL
LD HL,(__math_lhs+2)
JP NC,noinc
INC HL
noinc: EX DE,HL
LD HL,(__math_result+2)
ADD HL,DE
LD (__math_result+2),HL
dont_add:
LD HL,(__math_lhs) ; shift multiplicand left
ADD HL,HL
LD (__math_lhs),HL
LD HL,(__math_lhs+2)
JP NC,noshift
ADD HL,HL
INC HL
JP store
noshift:
ADD HL,HL
store: LD (__math_lhs+2),HL
DEC b
JP NZ,lp2
INC c
LD a,c
CP 4
JP NZ,lp1
LD HL,(__retloc)
push hl
LD HL,(__math_result+2)
ex de,hl
LD HL,(__math_result)
ret
| 26.127273 | 85 | 0.749478 |
6688c99ad40ac74f8deda25ab8ebaeccc12df7c4 | 1,085 | asm | Assembly | _build/dispatcher/jmp_ippsGFpECAddPoint_e25c9d5a.asm | zyktrcn/ippcp | b0bbe9bbb750a7cf4af5914dd8e6776a8d544466 | [
"Apache-2.0"
] | 1 | 2021-10-04T10:21:54.000Z | 2021-10-04T10:21:54.000Z | _build/dispatcher/jmp_ippsGFpECAddPoint_e25c9d5a.asm | zyktrcn/ippcp | b0bbe9bbb750a7cf4af5914dd8e6776a8d544466 | [
"Apache-2.0"
] | null | null | null | _build/dispatcher/jmp_ippsGFpECAddPoint_e25c9d5a.asm | zyktrcn/ippcp | b0bbe9bbb750a7cf4af5914dd8e6776a8d544466 | [
"Apache-2.0"
] | null | null | null | extern m7_ippsGFpECAddPoint:function
extern n8_ippsGFpECAddPoint:function
extern y8_ippsGFpECAddPoint:function
extern e9_ippsGFpECAddPoint:function
extern l9_ippsGFpECAddPoint:function
extern n0_ippsGFpECAddPoint:function
extern k0_ippsGFpECAddPoint:function
extern ippcpJumpIndexForMergedLibs
extern ippcpSafeInit:function
segment .data
align 8
dq .Lin_ippsGFpECAddPoint
.Larraddr_ippsGFpECAddPoint:
dq m7_ippsGFpECAddPoint
dq n8_ippsGFpECAddPoint
dq y8_ippsGFpECAddPoint
dq e9_ippsGFpECAddPoint
dq l9_ippsGFpECAddPoint
dq n0_ippsGFpECAddPoint
dq k0_ippsGFpECAddPoint
segment .text
global ippsGFpECAddPoint:function (ippsGFpECAddPoint.LEndippsGFpECAddPoint - ippsGFpECAddPoint)
.Lin_ippsGFpECAddPoint:
db 0xf3, 0x0f, 0x1e, 0xfa
call ippcpSafeInit wrt ..plt
align 16
ippsGFpECAddPoint:
db 0xf3, 0x0f, 0x1e, 0xfa
mov rax, qword [rel ippcpJumpIndexForMergedLibs wrt ..gotpc]
movsxd rax, dword [rax]
lea r11, [rel .Larraddr_ippsGFpECAddPoint]
mov r11, qword [r11+rax*8]
jmp r11
.LEndippsGFpECAddPoint:
| 27.820513 | 95 | 0.797235 |
807af7bc7d45517f835d97ae6375470f2336ea54 | 766 | asm | Assembly | libsrc/_DEVELOPMENT/env/esxdos/z80/asm_tmpnam.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 640 | 2017-01-14T23:33:45.000Z | 2022-03-30T11:28:42.000Z | libsrc/_DEVELOPMENT/env/esxdos/z80/asm_tmpnam.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 1,600 | 2017-01-15T16:12:02.000Z | 2022-03-31T12:11:12.000Z | libsrc/_DEVELOPMENT/env/esxdos/z80/asm_tmpnam.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 215 | 2017-01-17T10:43:03.000Z | 2022-03-23T17:25:02.000Z | ; char *tmpnam(char *s)
INCLUDE "config_private.inc"
SECTION code_env
PUBLIC asm_tmpnam
EXTERN __ENV_TMPNAM_TEMPLATE
EXTERN asm_env_tmpnam, asm_strcpy
asm_tmpnam:
; Return an unused filename in the /tmp directory
;
; enter : hl = char *s (0 = use internal static memory)
;
; exit : success
;
; hl = char *s (or internal filename)
; carry set
;
; fail
;
; hl = 0
; carry reset
;
; uses : af, bc, de, hl, bc', de', hl', ix
ld a,h
or l
jp z, asm_env_tmpnam ; if using internal memory
ex de,hl ; de = char *s
ld hl,__ENV_TMPNAM_TEMPLATE
call asm_strcpy ; hl = char *s
jp asm_env_tmpnam
| 18.682927 | 58 | 0.539164 |
afe234b1909a669a60b352eef2e27eeaad0ae125 | 862 | asm | Assembly | oeis/164/A164404.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/164/A164404.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/164/A164404.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A164404: Number of binary strings of length n with no substrings equal to 0010 or 1011
; Submitted by Jon Maiga
; 14,24,41,70,120,206,354,608,1044,1792,3076,5280,9064,15560,26712,45856,78720,135136,231984,398240,683648,1173600,2014688,3458560,5937216,10192256,17496768,30036224,51562368,88515712,151952512,260852736,447798784,768723968,1319647488,2265402880,3888955392,6676063744,11460616704,19674128384,33774040064,57978974208,99530925056,170862026752,293314185216,503524468736,864386734080,1483869151232,2547317735424,4372910940160,7506857046016,12886816923648,22122447437824,37977002663936,65194085572608
add $0,3
mov $2,1
mov $3,1
lpb $0
sub $0,1
mul $2,2
add $3,1
mov $5,$4
add $5,2
add $5,$1
mov $1,$3
sub $3,$4
mov $4,$2
mov $2,$3
add $2,$4
sub $2,1
mov $3,$5
add $3,2
add $4,$1
lpe
mov $0,$4
sub $0,23
div $0,2
add $0,14
| 29.724138 | 495 | 0.75058 |
798fdecd0c0dff0ec4de73af52974f405afcff30 | 349 | asm | Assembly | charset/index.asm | cainex/c64_playground | 74587cd884d478eaf0d2cd3660d1b9503a7e728b | [
"Apache-2.0"
] | null | null | null | charset/index.asm | cainex/c64_playground | 74587cd884d478eaf0d2cd3660d1b9503a7e728b | [
"Apache-2.0"
] | null | null | null | charset/index.asm | cainex/c64_playground | 74587cd884d478eaf0d2cd3660d1b9503a7e728b | [
"Apache-2.0"
] | null | null | null | #import "../common/cia1_regs.asm"
#import "../common/cia2_regs.asm"
#import "../common/vic_regs.asm"
* = $0801
BasicUpstart(main)
* = $9000
#import "minirogue-c64-colors.asm"
* = $8000
#import "main.asm"
* = $3000
#import "minirogue-c64-map.asm"
* = $2000
#import "minirogue-c64-charset.asm"
| 18.368421 | 35 | 0.570201 |
e907b9c156bbd9e3dad816717d2da88129095c9c | 6,400 | asm | Assembly | mcpuinfo.asm | dd86k/mcpuinfo | 67c86470cc19d79ae503604e99765f0680086069 | [
"0BSD"
] | 2 | 2022-03-23T03:51:17.000Z | 2022-03-24T13:46:28.000Z | mcpuinfo.asm | dd86k/mcpuinfo | 67c86470cc19d79ae503604e99765f0680086069 | [
"0BSD"
] | null | null | null | mcpuinfo.asm | dd86k/mcpuinfo | 67c86470cc19d79ae503604e99765f0680086069 | [
"0BSD"
] | null | null | null | ; ======================================
; mcpuinfo.asm
;
; Turning the cpuid3a.asm sample, with tweaks, from the Intel AP-485 manual
; into a usable program for the MS-DOS operating system.
;
; Compile: nasm mcpuinfo.asm -fbin -omcpuinfo.com
; Author: dd86k <dd@dax.moe>
; License: ISC
; ======================================
BITS 16 ; Base is 16-bit code
CPU 386 ; Contains mixed 16+32-bit code
ORG 100h ; Origin of CS:0100
%define VERSION '0.1.0'
%define NL 13,10
%define ENDSTR '$' ; MS-DOS string terminator for AH=4Ch
section .text
start:
mov si,81h ; Start index of command-line (in PSP)
call skip_delim ; Skip to first token
mov bx,si ; Save delim position
mov di,opt_help ; Help switch string
mov cx,opt_helplen ; Help switch string length
repe cmpsb
jcxz cli_help
mov si,bx ; Reset to start of token
mov di,opt_helpalt ; Alt help switch string
mov cx,opt_helpaltlen ; Alt help switch string length
repe cmpsb
jcxz cli_help
mov si,bx ; Reset to start of token
mov di,opt_version ; Version switch string
mov cx,opt_versionlen ; Version switch string length
repe cmpsb
jcxz cli_version
mov si,bx ; Reset to start of token
mov di,opt_ver ; Ver switch string
mov cx,opt_verlen ; Ver switch string length
repe cmpsb
jcxz cli_ver
jmp check_8086
; Version string
cli_ver:
mov dx,page_ver
call print
jmp exit
; Version page
cli_version:
mov dx,page_version
call print
jmp exit
; Help page
cli_help:
mov dx,page_help
call print
jmp exit
; Detect i8086, snippet taken out of AP-485.
; The 8086 has FLAGS bits 15:12 always set and cannot be cleared.
; The 8086 also changes the value of SP after pushing.
check_8086:
pushf ; Push original FLAGS
pop ax ; Get FLAGS into AX
mov cx,ax ; Save original FLAGS
and ax,0fffh ; Clear bits 15:12
push ax ; Push new value into stack
popf ; Set FLAGS from value from stack
pushf ; Get new FLAGS
pop ax ; Save FLAGS value
and ax,0f000h ; Keep bits 15:12
cmp ax,0f000h ; Anything in FLAGS[15:12]?
jne check_286 ; If cleared, it's probably an i286
push sp ; Not an i286? Check for PUSH/SP diff then
pop dx ; Save SP value
cmp dx,sp ; If current SP value
jne case_8086 ;
jmp case_unknown ;
; Detect i286.
; The i286 has FLAGS bits 15:12 always cleared and cannot be set.
check_286:
or cx,0f000h ; Try to set bits 15:12 to saved FLAGS
push cx
popf ; Sets FLAGS from CX
pushf
pop dx ; Get new FLAGS into DX
and dx,0f000h ; Clear FLAGS[11:0]
jz case_286 ; Jump if FLAGS[15:12] is cleared
; Detect i386.
; This checks if we can toggle EFLAGS[AC].
check_386:
pushfd ; Push original EFLAGS
pop eax ; Get ELFAGS
mov ecx,eax ; Save EFLAGS
xor eax,40000h ; Flip EFLAGS[AC]
push eax ; Save new value on stack
popfd ; Replace EFLAGS
pushfd ; Get new EFLAGS
pop eax ; Store EFLAGS
xor eax,ecx ; If can't toggle AC, it is 80386
jz case_386
push ecx ; Restore EFLAGS
popfd
jmp case_486 ; Can toggle AC, it's an 486
; Init and check FPU control word.
check_fpu:
fninit ; Resets FPU if present
fnstsw ax ; Get FPU status word
cmp al,0 ; Do we have anything?
jne exit ; No FPU then
; Check if 8087 by checking bit 15 with FDISI.
; NOTE: Certainly doesn't seem to work with DosBox-X
;check_fpu_cw:
; fnstcw [fpucw] ; Get FPU status word
; mov ax,fpucw
; and ax,103fh ;
; cmp ax,3fh ;
; jne exit ; Failsafe: Incorrect FPU word, no FPU
check_8087:
and ax,0xff7f ; Clear other bits
mov word [_fpu_cw],ax
fldcw [_fpu_cw] ; Load control word into FPU
fdisi ; 8087-only instruction
fstcw [_fpu_cw] ; Get Control Word
test word [_fpu_cw],0x80 ; Did FDISI do anything?
je check_fpu_inf ; FDISI did nothing, go check +INF/-INF
jmp case_8087 ; FPU: 8087
; Check infinity (-INF/+INF comparison test)
check_fpu_inf:
fld1 ; Push +1.0, this will be st0
fldz ; Push +0.0, this will be st1
fdiv ; (fdivp st1,st0) 1.0/0.0 = +INF, then pop, TOP=st0
fld st0 ; Push st0 value (+INF) again into stack (now st1)
fchs ; Toggle sign to st0, making st0 -INF
fcompp ; See if st0/st1 are the same, then pop both
fstsw ax ; Get status word
sahf ; Save AH into low FLAGS to see if infinites matched
jz case_287 ; <= 80287: +inf == -inf
jmp case_387 ; >= 80387: +inf != -inf
case_8086:
mov dx,str_i8086
call print
jmp check_fpu
case_286:
mov dx,str_i286
call print
jmp check_fpu
case_386:
mov dx,str_i386
call print
jmp check_fpu
case_486:
mov dx,str_i486
call print
jmp done
case_8087:
mov dx,str_fpu87
call print
jmp done
case_287:
mov dx,str_fpu287
call print
jmp done
case_387:
mov dx,str_fpu387
call print
jmp done
case_unknown:
mov dx,str_unknown
call print
jmp done
; MS-DOS output string
; Params: DX = String pointer
print: mov ah,9
int 21h
ret
; Done, print newline and exit
done: mov dx,str_newln
call print
; Exit program (MS-DOS)
exit: mov ah,4ch
int 21h
; Sets zero flag if character a delimiter
; Params: AL = Character value
; Returns: FLAGS[ZF] is set if true
test_delim:
cmp al,32 ; Space
jz delim
cmp al,44 ; Comma
jz delim
cmp al,9 ; Hardware tab
jz delim
cmp al,59 ; Semi-colon
jz delim
cmp al,61 ; Equal sign
jz delim
cmp al,13 ; Carriage return, failsafe
delim: ret
; Skip over leading delimiters
; Params: SI = Starting source index
skip_delim:
cld ; Force direction (increments SI)
cont: lodsb ; Get character as DS:SI
call test_delim
jz cont ; If delim, continue
dec si ; Non-delim found, index is behind
end: ret
;
; Data section
;
section .data
opt_version db '--version'
opt_versionlen equ $-opt_version
opt_ver db '--ver'
opt_verlen equ $-opt_ver
opt_help db '--help'
opt_helplen equ $-opt_help
opt_helpalt db '/?'
opt_helpaltlen equ $-opt_helpalt
; DOS strings
page_version db 'mcpuinfo ',VERSION,' (built: ',__DATE__,' ',__TIME__,')',NL,ENDSTR
page_ver db VERSION,NL,ENDSTR
page_help db \
'Pre-Pentium processor/co-processor information utility.',NL,\
'Usage:',NL,\
' MCPUINFO [OPTION]',NL,\
NL,\
'OPTIONS',NL,\
' --version Show version page and quit',NL,\
' --ver Print version string and quit',NL,\
' --help, /? Show this help page and quit',NL,ENDSTR
str_newln db NL,ENDSTR ; \r\n
str_i8086 db '8086',ENDSTR
str_i286 db '80286',ENDSTR
str_i386 db '80386',ENDSTR
str_i486 db '80486',ENDSTR
str_fpu87 db '+8087',ENDSTR
str_fpu287 db '+80287',ENDSTR
str_fpu387 db '+80387',ENDSTR
str_unknown db 'unknown',ENDSTR
;
; "Stack" section
;
section .bss
_fpu_cw resw 1 | 24.150943 | 84 | 0.709844 |
9b045cc6e5a1ac786eb3d9968871cd7d03129696 | 838 | asm | Assembly | programs/oeis/285/A285076.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/285/A285076.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/285/A285076.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A285076: 1-limiting word of the morphism 0->10, 1-> 010.
; 1,0,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,0,1,0,1,0,1,0,0,1,0,1
mov $3,$0
mov $5,2
lpb $5,1
mov $0,$3
sub $5,1
add $0,$5
sub $0,1
mul $0,2
pow $0,2
mov $4,2
lpb $0,1
add $4,4
trn $0,$4
lpe
mov $2,$5
add $4,6
lpb $2,1
mov $1,$4
sub $2,1
lpe
lpe
lpb $3,1
sub $1,$4
mov $3,0
lpe
sub $1,4
div $1,4
| 27.032258 | 501 | 0.497613 |
0bacc4f8c786120895da1b5baf7928e4cf1c1661 | 65 | asm | Assembly | School Directory Project/test_data/left1.asm | AriaPahlavan/Fall-2014-EE-306-Projects-Assembly-Binary | 589bf1e85c1813efa71bfa8ec656ee8701d31a6a | [
"MIT"
] | 1 | 2016-01-14T05:17:37.000Z | 2016-01-14T05:17:37.000Z | School Directory Project/test_data/left1.asm | apahlavan1/Fall-2014-EE-306-Projects-Assembly-Binary | 589bf1e85c1813efa71bfa8ec656ee8701d31a6a | [
"MIT"
] | null | null | null | School Directory Project/test_data/left1.asm | apahlavan1/Fall-2014-EE-306-Projects-Assembly-Binary | 589bf1e85c1813efa71bfa8ec656ee8701d31a6a | [
"MIT"
] | null | null | null | .ORIG x4100
.FILL x0000
.FILL x4250
.FILL x0000
.FILL x4160
.END
| 9.285714 | 11 | 0.738462 |
a18908dfdb728d0ef243a3e715bbddac433878e0 | 1,049 | asm | Assembly | samples/vector/normalize_vector.asm | fossabot/ancient_cpu | 58e47751d8d9b3486732695db64061b7cfe38b5d | [
"MIT"
] | 17 | 2020-04-29T05:51:31.000Z | 2021-06-09T01:59:10.000Z | samples/vector/normalize_vector.asm | Magicianred/VM | c03a82b52d1ab90199e6a835def87830e77147c1 | [
"MIT"
] | 29 | 2019-07-20T00:01:42.000Z | 2020-04-05T04:04:48.000Z | samples/vector/normalize_vector.asm | Magicianred/VM | c03a82b52d1ab90199e6a835def87830e77147c1 | [
"MIT"
] | 4 | 2020-07-20T19:15:33.000Z | 2021-12-24T23:14:03.000Z | #{
~label 'x' 0x1
~label 'y' 0x2
~label 'z' 0x3
~label 'ln' 0x0A
~label 'buf' 0x8
}
.mva &(0x5) &(0xF) <| $(0x0)
; load values
.ldi &(![~x]) <| $(0x1)
.ldi &(![~y]) <| $(0x2)
.ldi &(![~z]) <| $(0x5)
; print info
.lpstr !{"Vector values:"}
.unlock &(![~buf]) str
.mvx &(0x1) &(0x6) |> &(![~buf])
.mva &(0x1) &(0x6) <| $(0x0A)
.mvj &(0x1) &(0x6) <| @string_t("x: ")
.mvx &(0x1) &(0x6) |> &(![~x])
.mva &(0x1) &(0x6) <| $(![~ln])
.mvj &(0x1) &(0x6) <| @string_t("y: ")
.mvx &(0x1) &(0x6) |> &(![~y])
.mva &(0x1) &(0x6) <| $(![~ln])
.mvj &(0x1) &(0x6) <| @string_t("z: ")
.mvx &(0x1) &(0x6) |> &(![~z])
.mva &(0x1) &(0x6) <| $(![~ln])
; normalize vector
.add &(0x4) &(0x1) &(0x2)
.swap &(0x4) &(0x2)
.add &(0x4) &(0x2) &(0x3)
.swap &(0x4) &(0x5)
.sqrt &(0x4) &(0x5)
; result
.mvj &(0x1) &(0x6) <| @string_t("Normalize value: ")
.mvx &(0x1) &(0x6) |> &(0x4)
.mva &(0x1) &(0x6) <| $(0x20)
; stage
.mva &(0x1) &(0x7) <| $(0x0)
; clear
.mva &(0x1) &(0x3) <| $(0x0)
; shutdown
.halt | 20.568627 | 53 | 0.428027 |
44b5a39e25d8c43168b78987a49599a118be5bbd | 146 | asm | Assembly | other.7z/SFC.7z/SFC/ソースデータ/ヨッシーアイランド/日本_Ver1/sfc/ys_demo.asm | prismotizm/gigaleak | d082854866186a05fec4e2fdf1def0199e7f3098 | [
"MIT"
] | null | null | null | other.7z/SFC.7z/SFC/ソースデータ/ヨッシーアイランド/日本_Ver1/sfc/ys_demo.asm | prismotizm/gigaleak | d082854866186a05fec4e2fdf1def0199e7f3098 | [
"MIT"
] | null | null | null | other.7z/SFC.7z/SFC/ソースデータ/ヨッシーアイランド/日本_Ver1/sfc/ys_demo.asm | prismotizm/gigaleak | d082854866186a05fec4e2fdf1def0199e7f3098 | [
"MIT"
] | null | null | null | Name: ys_demo.asm
Type: file
Size: 151749
Last-Modified: '2016-05-13T04:51:16Z'
SHA-1: B56ED7ECB10F441C5E2F2DEEA5EFD15367151A0B
Description: null
| 20.857143 | 47 | 0.815068 |
93653896ff3e63e46f21f78836ba40ca2008ac01 | 700 | asm | Assembly | oeis/021/A021174.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/021/A021174.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/021/A021174.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A021174: Expansion of 1/((1-x)(1-2x)(1-6x)(1-7x)).
; Submitted by Jon Maiga
; 1,16,173,1592,13461,108192,841261,6392584,47771141,352537328,2576599389,18689228376,134742802741,966708860224,6908017500557,49202455443368,349495185871461,2476934287969680,17521347937528765,123746283094195960,872805066850436501,6149121979103638496,43280772920637356013,304386924845949588552,2139237560330609253061,15025837440768104679472,105487909196099906422301,740257647037038655387544,5192857225245306987172341,36416322752633368380705408,255312192323930897635415629,1789572944600500201565743336
add $0,2
lpb $0
sub $0,1
add $2,2
mul $2,6
sub $2,11
mul $3,7
add $3,$1
mul $1,2
add $1,$2
lpe
mov $0,$3
| 41.176471 | 499 | 0.818571 |
e7fe9089dc6983916bc31ba2ba3b414e22f96117 | 1,379 | asm | Assembly | Test_B.asm | LiaoHanwen/microcomputer-experiment | 4cf617e9dd1e4b5a6bcd58fe3562477a66d8921c | [
"BSD-3-Clause"
] | null | null | null | Test_B.asm | LiaoHanwen/microcomputer-experiment | 4cf617e9dd1e4b5a6bcd58fe3562477a66d8921c | [
"BSD-3-Clause"
] | null | null | null | Test_B.asm | LiaoHanwen/microcomputer-experiment | 4cf617e9dd1e4b5a6bcd58fe3562477a66d8921c | [
"BSD-3-Clause"
] | null | null | null | ;Test B
;macro for output
output macro ostr,onum
mov dx,offset ostr
mov ah,09h
int 21h
mov dl,onum
mov ah,02h
int 21h
endm
data segment
orgin dw 1,0,2,0,3,0,4,0,5,0,6,0,7,0,8,0,9,-1,-2,-3,-4,-5,-6,-7 ;test numbers
count equ $-orgin ;size of numbers
poev db '0'
pood db '0'
neev db '0'
neod db '0'
zero db '0'
poevstr db 'Positive and even: ','$'
poodstr db 0dh,0ah,'Positive and odd: ','$'
neevstr db 0dh,0ah,'Negative and even: ','$'
neodstr db 0dh,0ah,'Negative and odd: ','$'
zerostr db 0dh,0ah,'Equal to 0: ','$'
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax ;ds=data
lea ax,orgin
mov si,ax ;si=orgin
mov ax,count
mov bl,2 ;bx=2
div bl
mov cx,ax
malp: mov ax,[si]
cmp ax,0
jz fzero ;lower than 0
jg posi ;greater than 0
jl nega ;is 0
edlp: add si,2
loop malp
jmp otpt
fzero: add [zero],1 ;zero+1
jmp edlp ;return
posi: idiv bl ;positive
cmp ah,0
jz fpoev
jmp fpood
fpoev: add poev,1 ;positive & even
jmp edlp
fpood: add pood,1 ;positive & odd
jmp edlp
nega: idiv bl ;negative
cmp ah,0
jz fneev
jmp fneod
fneev: add neev,1 ;negative & even
jmp edlp
fneod: add neod,1 ;negative & odd
jmp edlp
otpt: output poevstr,poev
output poodstr,pood
output neevstr,neev
output neodstr,neod
output zerostr,zero
mov ax,4c00h
int 21h
code ends
end start | 16.223529 | 78 | 0.655547 |
2bc0fbbee5487b03a08bfdbc6fb3037846be9fbe | 4,683 | asm | Assembly | Transynther/x86/_processed/AVXALIGN/_zr_/i7-7700_9_0xca.log_21829_1775.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/AVXALIGN/_zr_/i7-7700_9_0xca.log_21829_1775.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/AVXALIGN/_zr_/i7-7700_9_0xca.log_21829_1775.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r15
push %rax
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x141ce, %rsi
lea addresses_WT_ht+0x1214e, %rdi
nop
sub $62703, %rax
mov $107, %rcx
rep movsl
nop
nop
nop
nop
nop
sub $5664, %r10
lea addresses_UC_ht+0x87ce, %rdi
nop
nop
cmp %r15, %r15
mov $0x6162636465666768, %rax
movq %rax, %xmm0
and $0xffffffffffffffc0, %rdi
movaps %xmm0, (%rdi)
add %rsi, %rsi
lea addresses_D_ht+0x418e, %rcx
nop
nop
nop
xor %r15, %r15
vmovups (%rcx), %ymm7
vextracti128 $0, %ymm7, %xmm7
vpextrq $0, %xmm7, %rsi
add %r10, %r10
pop %rsi
pop %rdi
pop %rcx
pop %rax
pop %r15
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r14
push %rbx
push %rcx
push %rdx
push %rsi
// Faulty Load
mov $0x59e16d00000009ce, %rdx
nop
nop
nop
nop
nop
and $1171, %rbx
mov (%rdx), %r14
lea oracles, %rsi
and $0xff, %r14
shlq $12, %r14
mov (%rsi,%r14,1), %r14
pop %rsi
pop %rdx
pop %rcx
pop %rbx
pop %r14
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'congruent': 0, 'AVXalign': False, 'same': False, 'size': 2, 'NT': False, 'type': 'addresses_NC'}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'congruent': 0, 'AVXalign': True, 'same': True, 'size': 8, 'NT': False, 'type': 'addresses_NC'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'congruent': 10, 'same': False, 'type': 'addresses_D_ht'}, 'OP': 'REPM', 'dst': {'congruent': 6, 'same': False, 'type': 'addresses_WT_ht'}}
{'OP': 'STOR', 'dst': {'congruent': 7, 'AVXalign': True, 'same': False, 'size': 16, 'NT': True, 'type': 'addresses_UC_ht'}}
{'src': {'congruent': 3, 'AVXalign': False, 'same': False, 'size': 32, 'NT': False, 'type': 'addresses_D_ht'}, 'OP': 'LOAD'}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
| 52.033333 | 2,999 | 0.662823 |
73faf193a446cae85117ffd0255b1092e0a11114 | 382 | asm | Assembly | pwnlib/shellcraft/templates/amd64/linux/sched_getaffinity.asm | IMULMUL/python3-pwntools | 61210a68cd88e9084c72292d3119c38c44f07966 | [
"MIT"
] | 325 | 2016-01-25T08:38:06.000Z | 2022-03-30T14:31:50.000Z | pwnlib/shellcraft/templates/amd64/linux/sched_getaffinity.asm | IMULMUL/python3-pwntools | 61210a68cd88e9084c72292d3119c38c44f07966 | [
"MIT"
] | 8 | 2016-08-23T10:15:27.000Z | 2019-01-16T02:49:34.000Z | pwnlib/shellcraft/templates/amd64/linux/sched_getaffinity.asm | IMULMUL/python3-pwntools | 61210a68cd88e9084c72292d3119c38c44f07966 | [
"MIT"
] | 71 | 2016-07-13T10:03:52.000Z | 2022-01-10T11:57:34.000Z | <%
from pwnlib.shellcraft.amd64.linux import syscall
%>
<%page args="pid, cpusetsize, cpuset"/>
<%docstring>
Invokes the syscall sched_getaffinity. See 'man 2 sched_getaffinity' for more information.
Arguments:
pid(pid_t): pid
cpusetsize(size_t): cpusetsize
cpuset(cpu_set_t): cpuset
</%docstring>
${syscall('SYS_sched_getaffinity', pid, cpusetsize, cpuset)}
| 25.466667 | 91 | 0.727749 |
109cb9611f688c0dd6ddf084d56ee37ac84c6408 | 410 | asm | Assembly | programs/oeis/133/A133259.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/133/A133259.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | programs/oeis/133/A133259.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | ; A133259: a(6n) = 6n+1, a(6n+1) = 6n+2, a(6n+2) = 6n+3, a(6n+3) = 6n+6, a(6n+4) = 6n+5, a(6n+5) = 6n+4.
; 1,2,3,6,5,4,7,8,9,12,11,10,13,14,15,18,17,16,19,20,21,24,23,22,25,26,27,30,29,28,31,32,33,36,35,34,37,38,39,42,41,40,43,44,45,48,47,46,49,50,51,54,53,52,55,56,57,60,59,58,61,62,63,66,65,64,67,68,69,72,71,70
lpb $0
add $1,$0
add $2,$1
sub $2,1
lpb $2
sub $2,6
lpe
mov $0,$2
lpe
add $1,1
| 29.285714 | 208 | 0.553659 |
60c393a877df23c4e3281a9a990d4dfabd602ad9 | 14,541 | asm | Assembly | base/ntos/rtl/amd64/movemem.asm | yang235/wrk-v1.2 | daeeb598c7bf091b1370e8875626ad0cb3cd1ec0 | [
"Intel"
] | 209 | 2018-10-30T15:59:10.000Z | 2022-03-31T06:02:48.000Z | base/ntos/rtl/amd64/movemem.asm | WindowsExploitation/wrk-v1.2 | daeeb598c7bf091b1370e8875626ad0cb3cd1ec0 | [
"Intel"
] | 2 | 2019-01-17T04:52:33.000Z | 2019-06-11T06:37:43.000Z | base/ntos/rtl/amd64/movemem.asm | WindowsExploitation/wrk-v1.2 | daeeb598c7bf091b1370e8875626ad0cb3cd1ec0 | [
"Intel"
] | 66 | 2018-08-03T11:15:44.000Z | 2022-03-31T01:03:03.000Z | title "Memory functions"
;++
;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
; You may only use this code if you agree to the terms of the Windows Research Kernel Source Code License agreement (see License.txt).
; If you do not agree to the terms, do not use the code.
;
;
; Module Name:
;
; movemem.asm
;
; Abstract:
;
; This module implements functions to fill, copy , and compare blocks of
; memory.
;
;--
include ksamd64.inc
extern memset:proc
subttl "Compare Memory"
;++
;
; SIZE_T
; RtlCompareMemory (
; IN PVOID Source1,
; IN PVOID Source2,
; IN SIZE_T Length
; )
;
; Routine Description:
;
; This function compares two unaligned blocks of memory and returns the
; number of bytes that compared equal.
;
; Arguments:
;
; Source1 (rcx) - Supplies a pointer to the first block of memory to
; compare.
;
; Source2 (rdx) - Supplies a pointer to the second block of memory to
; compare.
;
; Length (r8) - Supplies the Length, in bytes, of the memory to be
; compared.
;
; Return Value:
;
; The number of bytes that compared equal is returned as the function
; value. If all bytes compared equal, then the length of the original
; block of memory is returned.
;
;--
CmFrame struct
SavedRsi dq ? ; saved nonvolatile registers
SavedRdi dq ? ;
CmFrame ends
NESTED_ENTRY RtlCompareMemory, _TEXT$00
alloc_stack (sizeof CmFrame) ; allocate stack frame
save_reg rsi, CmFrame.SavedRsi ; save nonvolatile registers
save_reg rdi, CmFrame.SavedRdi ;
END_PROLOGUE
mov rsi, rcx ; set address of first string
mov rdi, rdx ; set address of second string
xor edx, ecx ; check if compatible alignment
and edx, 07h ;
jnz short RlCM50 ; if nz, incompatible alignment
cmp r8, 8 ; check if length to align
jb short RlCM50 ; if b, insufficient alignment length
;
; Buffer alignment is compatible and there are enough bytes for alignment.
;
mov r9, rdi ; copy destination address
neg ecx ; compute alignment length
and ecx, 07h ;
jz short RlCM10 ; if z, buffers already aligned
sub r8, rcx ; reduce count by align length
repe cmpsb ; compare bytes to alignment
jnz short RlCM30 ; if nz, not all bytes matched
RlCM10: mov rcx, r8 ;
and rcx, -8 ; check if any quarwords to compare
jz short RlCM20 ; if z, no quadwords to compare
sub r8, rcx ; reduce length by compare count
shr rcx, 3 ; compute number of quadwords
repe cmpsq ; compare quadwords
jz short RlCM20 ; if z, all quadwords compared
inc rcx ; increment remaining count
sub rsi, 8 ; back up source address
sub rdi, 8 ; back up destination address
shl rcx, 3 ; compute uncompared bytes
RlCM20: add r8, rcx ; compute residual bytes to compare
jz short RlCM40 ; if z, all bytes compared equal
mov rcx, r8 ; set remaining bytes to compare
repe cmpsb ; compare bytes
jz short RlCM40 ; if z, all byte compared equal
RlCM30: dec rdi ; back up destination address
RlCM40: sub rdi, r9 ; compute number of bytes matched
mov rax, rdi ;
mov rsi, CmFrame.SavedRsi[rsp] ; restore nonvolatile registers
mov rdi, CmFrame.SavedRdi[rsp] ;
add rsp, (sizeof CmFrame) ; deallocate stack frame
ret ; return
;
; Buffer alignment is incompatible or there is less than 8 bytes to compare.
;
RlCM50: test r8, r8 ; test if any bytes to compare
jz short RlCM60 ; if z, no bytes to compare
mov rcx, r8 ; set number of bytes to compare
repe cmpsb ; compare bytes
jz short RlCM60 ; if z, all bytes compared equal
inc rcx ; increment remaining count
sub r8, rcx ; compute number of bytes matched
RlCM60: mov rax, r8 ;
mov rsi, CmFrame.SavedRsi[rsp] ; restore nonvolatile registers
mov rdi, CmFrame.SavedRdi[rsp] ;
add rsp, (sizeof CmFrame) ; deallocate stack frame
ret ; return
NESTED_END RtlCompareMemory, _TEXT$00
subttl "Compare Memory 32-bits"
;++
;
; SIZE_T
; RtlCompareMemoryUlong (
; IN PVOID Source,
; IN SIZE_T Length,
; IN ULONG Pattern
; )
;
; Routine Description:
;
; This function compares a block of dword aligned memory with a specified
; pattern 32-bits at a time.
;
; N.B. The low two bits of the length are assumed to be zero and are
; ignored.
;
; Arguments:
;
; Source (rcx) - Supplies a pointer to the block of memory to compare.
;
; Length (rdx) - Supplies the length, in bytes, of the memory to compare. compare.
;
; Pattern (r8d) - Supplies the pattern to be compared against.
;
; Return Value:
;
; The number of bytes that compared equal is returned as the function
; value. If all bytes compared equal, then the length of the original
; block of memory is returned.
;
;--
NESTED_ENTRY RtlCompareMemoryUlong, _TEXT$00
alloc_stack 8 ; allocate stack frame
save_reg rdi, 0 ; save nonvolatile register
END_PROLOGUE
mov rdi, rcx ; set destination address
shr rdx, 2 ; compute number of dwords
jz short RlCU10 ; if z, no dwords to compare
mov rcx, rdx ; set length of compare in dwords
mov eax, r8d ; set comparison pattern
repe scasd ; compare memory with pattern
jz short RlCU10 ; if z, all dwords compared
inc rcx ; increment remaining count
sub rdx, rcx ; compute number of bytes matched
RlCU10: lea rax, [rdx*4] ; compute successful compare in bytes
mov rdi, [rsp] ; restore nonvolatile register
add rsp, 8 ; deallocate stack frame
ret ; return
NESTED_END RtlCompareMemoryUlong, _TEXT$00
subttl "Copy Memory NonTemporal"
;++
;
; VOID
; RtlCopyMemoryNonTemporal (
; OUT VOID UNALIGNED *Destination,
; IN CONST VOID UNALIGNED * Sources,
; IN SIZE_T Length
; )
;
; Routine Description:
;
; This function copies nonoverlapping from one buffer to another using
; nontemporal moves that do not pollute the cache.
;
; Arguments:
;
; Destination (rcx) - Supplies a pointer to the destination buffer.
;
; Sources (rdx) - Supplies a pointer to the source buffer.
;
; Length (r8) - Supplies the length, in bytes, of the copy operation.
;
; Return Value:
;
; None.
;
;--
CACHE_BLOCK equ 01000h ; nontemporal move block size
LEAF_ENTRY RtlCopyMemoryNonTemporal, _TEXT$00
sub rdx, rcx ; compute relative address of source
cmp r8, 64 + 8 ; check if 64 + 8 bytes to move
jb RlNT50 ; if b, skip non-temporal move
;
; Align the destination to a 8-byte boundary.
;
test cl, 07h ; check if destination 8-byte aligned
jz RlNT30 ; if z, already aligned
mov rax, [rdx + rcx] ; read alignment bytes
add r8, rcx ; adjust remaining bytes
movnti [rcx], rax ; copy alignment bytes (sfence later)
add rcx, 8 ; compute aligned destination address
and rcx, -8 ;
sub r8, rcx ; adjust remaining bytes
jmp RlNT30 ; jump to move 64-byte blocks
;
; Copy 64-byte blocks.
;
align 16
RlNT10: prefetchnta [rdx + rax] ; prefetch 64 bytes
add rax, 64 ; advance destination address
dec r9 ; decrement count
jnz RlNT10 ; if nz, more to prefetch
sub rax, rcx ; reset move count
RlNT20: mov r9, [rdx + rcx] ; copy 64-byte blocks
mov r10, [rdx + rcx + 8] ;
movnti [rcx], r9 ;
movnti [rcx + 8], r10 ;
mov r9, [rdx + rcx + 16] ;
mov r10, [rdx + rcx + 24] ;
movnti [rcx + 16], r9 ;
movnti [rcx + 24], r10 ;
add rcx, 64 ; advance destination address
mov r9, [rdx + rcx - 32] ;
mov r10, [rdx + rcx - 24] ;
movnti [rcx - 32], r9 ;
movnti [rcx - 24], r10 ;
mov r9, [rdx + rcx - 16] ;
mov r10, [rdx + rcx - 8] ;
movnti [rcx - 16], r9 ;
movnti [rcx - 8], r10 ;
sub rax, 64 ; subtract number of bytes moved
jnz short RlNT20 ; if nz, more 64-byte blocks to move
RlNT30: cmp r8, 64 ; check if more than 64 bytes to move
jb RlNT40 ; if b, no more 64 bytes
mov rax, rcx ; save destination address
mov r9, CACHE_BLOCK/64 ; number of 64-byte blocks to move
sub r8, CACHE_BLOCK ; reduce bytes to move
jae RlNT10 ; if ae, more CACHE_BLOCK bytes to move
add r8, CACHE_BLOCK ; adjust to remaining bytes
mov r9, r8 ; compute number of 64-byte blocks left
shr r9, 6 ;
and r8, 64 - 1 ; reduce bytes to move
jmp RlNT10 ; continue to move rest 64-byte blocks
RlNT40: ;
lock or byte ptr [rsp], 0 ; flush data to memory
;
; Move residual bytes.
;
RlNT50: sub r8, 8 ; subtract out 8-byte block
jae short RlNT60 ; if ae, more than 8 bytes left
add r8, 8 ; adjust to remaining bytes
jnz short RlNT80 ; if nz, more bytes to move
ret
align 16
db 066h, 066h, 090h
db 066h, 066h, 090h
db 066h, 066h, 090h
RlNT60: mov r9, 8 ; load constant to r9
RlNT70: mov rax, [rdx + rcx] ; move 8-byte block
add rcx, r9 ; advance to next 8-byte block
mov [rcx - 8], rax ;
sub r8, r9 ; subtract out 8-byte block
jae short RlNT70 ; if ae, more 8-byte blocks
add r8, r9 ; adjust to remaining bytes
jnz short RlNT80 ; if nz, more bytes to move
ret
align 16
RlNT80: mov al, [rdx + rcx] ; move bytes
mov [rcx], al ;
inc rcx ; increment source address
dec r8 ; decrement byte count
jnz short RlNT80 ; if nz, more bytes to move
ret ; return
LEAF_END RtlCopyMemoryNonTemporal, _TEXT$00
subttl "Fill Memory"
;++
;
; VOID
; RtlFillMemory (
; IN VOID UNALIGNED *Destination,
; IN SIZE_T Length,
; IN UCHAR Fill
; )
;
; Routine Description:
;
; This function fills a block of unaligned memory with a specified pattern.
;
; Arguments:
;
; Destination (rcx) - Supplies a pointer to the memory to fill.
;
; Length (rdx) - Supplies the length, in bytes, of the memory to fill.
;
; Fill (r8b) - Supplies the value to fill memory with.
;
; Return Value:
;
; None.
;
;--
LEAF_ENTRY RtlFillMemory, _TEXT$00
xchg r8, rdx ; exchange length and pattern
jmp memset ; finish in common code
LEAF_END RtlFillMemory, _TEXT$00
subttl "Prefetch Memory NonTemporal"
;++
;
; VOID
; RtlPrefetchMemoryNonTemporal (
; IN CONST PVOID Source,
; IN SIZE_T Length
; )
;
; Routine Description:
;
; This function prefetches memory at Source, for Length bytes into the
; closest cache to the processor.
;
; Arguments:
;
; Source (rcx) - Supplies a pointer to the memory to be prefetched.
;
; Length (rdx) - Supplies the length, in bytes, of the operation.
;
; Return Value:
;
; None.
;
;--
LEAF_ENTRY RtlPrefetchMemoryNonTemporal, _TEXT$00
RlPF10: prefetchnta 0[rcx] ; prefetch line
add rcx, 64 ; increment address to prefetch
sub rdx, 64 ; subtract number of bytes prefetched
ja RlPF10 ; if above zero, more bytes to move
ret ; return
LEAF_END RtlPrefetchMemoryNonTemporal, _TEXT$00
subttl "Zero Memory"
;++
;
; VOID
; RtlZeroMemory (
; IN VOID UNALIGNED *Destination,
; IN SIZE_T Length
; )
;
; Routine Description:
;
; This function fills a block of unaligned memory with zero.
;
; Arguments:
;
; Destination (rcx) - Supplies a pointer to the memory to fill.
;
; Length (rdx) - Supplies the length, in bytes, of the memory to fill.
;
; Return Value:
;
; None.
;
;--
LEAF_ENTRY RtlZeroMemory, _TEXT$00
mov r8, rdx ; set length
xor edx, edx ; set fill pattern
jmp memset ; finish in common code
LEAF_END RtlZeroMemory, _TEXT$00
end
| 33.895105 | 134 | 0.524242 |
faeb1ec7eda849f8f60e9fc3f5147b49c1af0f40 | 876 | asm | Assembly | programs/oeis/022/A022113.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/022/A022113.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | programs/oeis/022/A022113.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | ; A022113: Fibonacci sequence beginning 2, 7.
; 2,7,9,16,25,41,66,107,173,280,453,733,1186,1919,3105,5024,8129,13153,21282,34435,55717,90152,145869,236021,381890,617911,999801,1617712,2617513,4235225,6852738,11087963,17940701,29028664,46969365,75998029,122967394,198965423,321932817,520898240,842831057,1363729297,2206560354,3570289651,5776850005,9347139656,15123989661,24471129317,39595118978,64066248295,103661367273,167727615568,271388982841,439116598409,710505581250,1149622179659,1860127760909,3009749940568,4869877701477,7879627642045,12749505343522,20629132985567,33378638329089,54007771314656,87386409643745,141394180958401,228780590602146,370174771560547,598955362162693,969130133723240,1568085495885933,2537215629609173,4105301125495106,6642516755104279
add $0,2
lpb $0
sub $0,1
mov $1,$2
trn $1,1
add $1,6
trn $2,4
add $2,$3
mov $3,$1
sub $1,4
lpe
| 58.4 | 717 | 0.832192 |
363db01d1febdd45bae8713ed7d746136318fa09 | 245 | asm | Assembly | libsrc/_DEVELOPMENT/adt/w_vector/c/sdcc_iy/w_vector_resize.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/adt/w_vector/c/sdcc_iy/w_vector_resize.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null | libsrc/_DEVELOPMENT/adt/w_vector/c/sdcc_iy/w_vector_resize.asm | meesokim/z88dk | 5763c7778f19a71d936b3200374059d267066bb2 | [
"ClArtistic"
] | null | null | null |
; int w_vector_resize(w_vector_t *v, size_t n)
SECTION code_adt_w_vector
PUBLIC _w_vector_resize
EXTERN asm_w_vector_resize
_w_vector_resize:
pop af
pop hl
pop de
push de
push hl
push af
jp asm_w_vector_resize
| 11.666667 | 46 | 0.722449 |
09caeb41fc24eb22e7ffbc9596182fe3953ce53f | 13,588 | asm | Assembly | Library/Spreadsheet/Spreadsheet/spreadsheetPasteTransTbl.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 504 | 2018-11-18T03:35:53.000Z | 2022-03-29T01:02:51.000Z | Library/Spreadsheet/Spreadsheet/spreadsheetPasteTransTbl.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 96 | 2018-11-19T21:06:50.000Z | 2022-03-06T10:26:48.000Z | Library/Spreadsheet/Spreadsheet/spreadsheetPasteTransTbl.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 73 | 2018-11-19T20:46:53.000Z | 2022-03-29T00:59:26.000Z |
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Copyright (c) Geoworks 1991 -- All Rights Reserved
PROJECT: PC GEOS
MODULE:
FILE: spreadsheetPasteTransTbl.asm
AUTHOR: Cheng, 6/91
ROUTINES:
Name Description
---- -----------
REVISION HISTORY:
Name Date Description
---- ---- -----------
Cheng 6/91 Initial revision
DESCRIPTION:
The translation table routines for the spreadsheet's paste code.
A translation table is basically an array of TransTblEntry
that is meant to track how tokens in a scrap have been translated.
Purpose of a translation table
------------------------------
The paste code will search the translation table with the scrap's
token to see if it can find a match. From the matched entry,
the new (translated) token can be gotten and used.
The maximum of a translation table is:
(65535-size TransTblEntry) / size TransTblEntry
= (65535-4) / 4
= 16382
Register usage
--------------
cx - old token
dx - new token
bx - trans table mem handle (possibly 0)
ax - size of the trans table
es - seg addr of the trans table
$Id: spreadsheetPasteTransTbl.asm,v 1.1 97/04/07 11:14:29 newdeal Exp $
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
CutPasteCode segment
;*******************************************************************************
;
; BOOK KEEPING ROUTINES
;
;*******************************************************************************
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
TransTblCleanUp
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: Free the translation tables.
CALLED BY: INTERNAL ()
PASS: PasteStackFrame
RETURN: nothing
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Cheng 6/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
TransTblCleanUp proc near uses bx
locals local CellLocals
PSF_local local PasteStackFrame
.enter inherit near
lea bx, PSF_local.PSF_formatTransTbl
call TransTblCleanUpOne
.leave
ret
TransTblCleanUp endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
TransTblCleanUpOne
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: Free the given translation table and zero out its fields.
CALLED BY: INTERNAL ()
PASS: bx - offset from ss to the translation table
RETURN: translation table freed and zeroed
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Cheng 6/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
TransTblCleanUpOne proc near uses ax
.enter
EC< cmp ss:[bx].TT_sig, TRANS_TABLE_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE >
mov ax, bx ; save bx
mov bx, ss:[bx].TT_han
tst bx
je 10$
call MemFree
10$:
mov bx, ax ; restore bx
clr ax
mov ss:[bx].TT_han, ax
mov ss:[bx].TT_size, ax
.leave
ret
TransTblCleanUpOne endp
;*******************************************************************************
;
; ENTRY CREATION ROUTINES
;
;*******************************************************************************
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
TransTblAddEntry
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: Creates a new entry in the default translation table and
stores the token mapping information.
CALLED BY: INTERNAL ()
PASS: cx - original token
dx - new token
bx - offset from ss to the translation table
RETURN: translation table updated
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Cheng 5/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
TransTblAddEntry proc near uses ax,es,di
.enter
mov ax, ss:[bx].TT_size
tst ax
jne checkTT
mov ss:[bx].TT_sig, TRANS_TABLE_SIG
jmp short doneCheck
checkTT:
EC< cmp ss:[bx].TT_sig, TRANS_TABLE_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE >
doneCheck:
push bx ; save trans tbl offset
mov bx, ss:[bx].TT_han
push cx ; save old token
push ax ; save offset
add ax, size TranslationTableEntry ; increase size
push ax ; save new size
tst bx ; any handle?
jne doRealloc ; branch if so
mov cx, (mask HAF_LOCK or mask HAF_ZERO_INIT or mask HAF_NO_ERR) shl 8 or mask HF_SWAPABLE
call MemAlloc
mov es, ax ; es <- seg addr
mov es:TTE_sig, TRANS_TABLE_ENTRY_SIG
jmp short 10$
doRealloc:
mov ch, mask HAF_LOCK or mask HAF_ZERO_INIT or mask HAF_NO_ERR
call MemReAlloc
mov es, ax ; es <- seg addr
10$:
EC< cmp es:TTE_sig, TRANS_TABLE_ENTRY_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE_ENTRY >
pop ax ; retrieve new size
pop di ; offset to new entry
pop cx ; retrieve old token
mov es:[di].TTE_srcToken, cx
mov es:[di].TTE_dstToken, dx
;-----------------------------------------------------------------------
; update trans tbl
mov di, bx ; di <- mem han
pop bx ; retrieve trans tbl offset
EC< cmp ss:[bx].TT_sig, TRANS_TABLE_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE >
mov ss:[bx].TT_han, di
mov ss:[bx].TT_size, ax
.leave
ret
TransTblAddEntry endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
TransTblAddFlag
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: Locates the translation table entry and store the flag.
CALLED BY: INTERNAL ()
PASS: cx - original token
dx - flag to store
bx - offset from ss to the translation table
RETURN: translation table updated
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Cheng 5/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
TransTblAddFlag proc near uses ax,bx,es,di
locals local CellLocals
PSF_local local PasteStackFrame
.enter inherit near
EC< cmp ss:[bx].TT_sig, TRANS_TABLE_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE >
mov ax, ss:[bx].TT_size
mov bx, ss:[bx].TT_han
call MemLock
mov es, ax
EC< cmp es:TTE_sig, TRANS_TABLE_ENTRY_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE_ENTRY >
call TransTblLocateEntry ; es:di <- entry
EC< ERROR_C PASTE_TRANS_TBL_CANT_LOCATE_ENTRY >
mov es:[di].TTE_action, dx
call MemUnlock
.leave
ret
TransTblAddFlag endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
TransTblModifyEntry
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: Modify a translation table entry.
CALLED BY: INTERNAL ()
PASS: cx - original token
dx - new destination token
bx - offset from ss to the translation table
RETURN: translation table updated
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
jcw 3/20/93 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
TransTblModifyEntry proc near uses ax,bx,es,di
locals local CellLocals
PSF_local local PasteStackFrame
.enter inherit near
EC< cmp ss:[bx].TT_sig, TRANS_TABLE_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE >
mov ax, ss:[bx].TT_size
mov bx, ss:[bx].TT_han
call MemLock
mov es, ax
EC< cmp es:TTE_sig, TRANS_TABLE_ENTRY_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE_ENTRY >
call TransTblLocateEntry ; es:di <- entry
EC< ERROR_C PASTE_TRANS_TBL_CANT_LOCATE_ENTRY >
mov es:[di].TTE_dstToken, dx
call MemUnlock
.leave
ret
TransTblModifyEntry endp
;*******************************************************************************
;
; SEARCH ROUTINES
;
;*******************************************************************************
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
TransTblSearch
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: Given a token, searches the format translation table to
see if there is a TransTblEntry that contains
the token as TTE_originalToken.
CALLED BY: INTERNAL ()
PASS: PasteStackFrame
bx - offset from ss to the translation table
cx - original token
RETURN: carry clear is match found
dx - new token
carry set otherwise
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Cheng 6/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
TransTblSearch proc near uses ax,bx,es
locals local CellLocals
PSF_local local PasteStackFrame
.enter inherit near
EC< cmp ss:[bx].TT_sig, TRANS_TABLE_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE >
mov ax, ss:[bx].TT_size
tst ax
stc
je done
mov bx, ss:[bx].TT_han
call MemLock
mov es, ax
EC< cmp es:TTE_sig, TRANS_TABLE_ENTRY_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE_ENTRY >
call TransTblMapEntry
call MemUnlock
done:
.leave
ret
TransTblSearch endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
TransTblGetFlag
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: Search for the given entry and retrieve the flag.
CALLED BY: INTERNAL ()
PASS: PasteStackFrame
bx - offset from ss to the translation table
cx - original token
RETURN: dx - flag
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Cheng 6/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
TransTblGetFlag proc near uses ax,bx,es,di
locals local CellLocals
PSF_local local PasteStackFrame
.enter inherit near
EC< cmp ss:[bx].TT_size, 0 >
EC< ERROR_E PASTE_TRANS_TBL_CANT_LOCATE_ENTRY >
mov ax, ss:[bx].TT_size
mov bx, ss:[bx].TT_han
call MemLock
mov es, ax
EC< cmp es:TTE_sig, TRANS_TABLE_ENTRY_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE_ENTRY >
call TransTblLocateEntry ; es:di <- entry
EC< ERROR_C PASTE_TRANS_TBL_CANT_LOCATE_ENTRY >
mov dx, es:[di].TTE_action
call MemUnlock
.leave
ret
TransTblGetFlag endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
TransTblMapEntry
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: Go through the current translation table and map an old token
to a new token.
CALLED BY: INTERNAL (TransTblSearch)
PASS: cx - original token
ax - size of trans table
es - seg addr of trans table
RETURN: carry clear if match found
dx - new token
carry set otherwise
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Cheng 5/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
TransTblMapEntry proc near uses ax,di
.enter
call TransTblLocateEntry ; es:di <- entry
jc done ; branch if not found
mov dx, es:[di].TTE_dstToken ; grab token
done:
.leave
ret
TransTblMapEntry endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
TransTblLocateEntry
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: Go through the current translation table and map an old token
to a new token.
CALLED BY: INTERNAL (TransTblSearch)
PASS: cx - original token
ax - size of trans table
es - seg addr of trans table
RETURN: carry clear if match found
es:di - addr of trans table entry
carry set otherwise
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Cheng 5/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
TransTblLocateEntry proc near uses ax
.enter
EC< cmp es:TTE_sig, TRANS_TABLE_ENTRY_SIG >
EC< ERROR_NE PASTE_BAD_TRANS_TABLE_ENTRY >
tst ax
je notFound
clr di ; es:di <- first entry
locateLoop:
cmp cx, es:[di].TTE_srcToken ; match?
je found ; branch if so
add di, size TranslationTableEntry ; else next
cmp di, ax
jb locateLoop
notFound:
stc ; signal not found
jmp short done
found:
clc ; signal found
done:
.leave
ret
TransTblLocateEntry endp
CutPasteCode ends
| 23.030508 | 92 | 0.545187 |
2c8e3028ca30ca213216f931d72d667fa83406e2 | 347 | asm | Assembly | programs/oeis/339/A339765.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/339/A339765.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/339/A339765.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A339765: a(n) = 2*floor(n*phi) - 3*n, where phi = (1+sqrt(5))/2.
; -1,0,-1,0,1,0,1,0,1,2,1,2,3,2,3,2,3,4,3,4,3,4,5,4,5,6,5,6,5,6,7,6,7,8,7,8,7,8,9,8,9,8,9,10,9,10,11,10,11,10,11,12,11,12,11,12,13,12,13,14,13,14,13,14,15,14,15,16,15,16,15,16,17,16,17,16
mov $1,$0
seq $0,73869 ; a(n) = Sum_{i=0..n} A002251(i)/(n+1).
mul $0,2
sub $0,$1
sub $0,1
| 38.555556 | 187 | 0.553314 |
c7aecc27d746cde3aaf9b7bad400d5605f9d9ba1 | 359 | asm | Assembly | programs/oeis/082/A082863.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/082/A082863.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/082/A082863.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A082863: Number of distinct prime factors of n^2-1.
; 1,1,2,2,2,2,2,2,2,3,2,3,3,2,3,2,2,3,3,3,3,3,2,3,2,3,2,4,2,3,3,2,4,3,3,3,3,3,3,4,2,4,3,3,3,3,2,3,3,3,3,3,3,3,4,3,3,4,2,4,3,2,4,3,3,4,3,4,3,4,2,3,3,3,4,4,3,4,2,3,2,4,3,4,4,3,3,4,3,4,4,3,4,3,3,3,3,3,3,4
add $0,2
pow $0,2
sub $0,2
seq $0,1221 ; Number of distinct primes dividing n (also called omega(n)).
| 44.875 | 201 | 0.584958 |
d3f6242d356cee959d7a797693152f9498941835 | 20,904 | asm | Assembly | sources/ippcp/asm_intel64/pcpsha512e9as.asm | dongbinghua/ipp-crypto | 5f6c4afec3d86f0f586cd9344963111fd5c04213 | [
"Apache-2.0"
] | 233 | 2018-07-20T13:17:16.000Z | 2022-03-29T03:14:40.000Z | sources/ippcp/asm_intel64/pcpsha512e9as.asm | dongbinghua/ipp-crypto | 5f6c4afec3d86f0f586cd9344963111fd5c04213 | [
"Apache-2.0"
] | 39 | 2018-10-19T22:46:28.000Z | 2022-03-15T07:56:37.000Z | sources/ippcp/asm_intel64/pcpsha512e9as.asm | dongbinghua/ipp-crypto | 5f6c4afec3d86f0f586cd9344963111fd5c04213 | [
"Apache-2.0"
] | 60 | 2018-07-29T18:21:10.000Z | 2022-03-13T02:46:39.000Z | ;===============================================================================
; Copyright 2015-2021 Intel Corporation
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;===============================================================================
;
;
; Purpose: Cryptography Primitive.
; Message block processing according to SHA512
;
; Content:
; UpdateSHA256
;
%include "asmdefs.inc"
%include "ia_32e.inc"
%include "pcpvariant.inc"
%if (_ENABLE_ALG_SHA512_)
;;%if (_IPP32E >= _IPP32E_E9)
%if (_IPP32E == _IPP32E_E9 )
%xdefine W0 xmm0
%xdefine W1 xmm1
%xdefine W2 xmm2
%xdefine W3 xmm3
%xdefine W4 xmm4
%xdefine W5 xmm5
%xdefine W6 xmm6
%xdefine W7 xmm7
%xdefine xT0 xmm8
%xdefine xT1 xmm9
%xdefine xT2 xmm10
%xdefine SIGMA xmm11
;; assign hash values to GPU registers
%xdefine A r8
%xdefine B r9
%xdefine C r10
%xdefine D r11
%xdefine E r12
%xdefine F r13
%xdefine G r14
%xdefine H r15
%xdefine T1 rax
%xdefine T2 rbx
%xdefine T0 rbp
%xdefine KK_SHA512 rcx
%macro ROTATE_H 0.nolist
%xdefine %%_TMP H
%xdefine H G
%xdefine G F
%xdefine F E
%xdefine E D
%xdefine D C
%xdefine C B
%xdefine B A
%xdefine A %%_TMP
%endmacro
%macro ROTATE_W 0.nolist
%xdefine %%DUMMY W0
%xdefine W0 W1
%xdefine W1 W2
%xdefine W2 W3
%xdefine W3 W4
%xdefine W4 W5
%xdefine W5 W6
%xdefine W6 W7
%xdefine W7 %%DUMMY
%endmacro
%macro ROR64 2.nolist
%xdefine %%r %1
%xdefine %%nbits %2
%if _IPP32E >= _IPP32E_L9
rorx %%r,%%r,%%nbits
%elif _IPP32E >= _IPP32E_Y8
shld %%r,%%r,(64-%%nbits)
%else
ror %%r,%%nbits
%endif
%endmacro
;;
;; CHJ(x,y,z) = (x & y) ^ (~x & z)
;;
;; CHJ(x,y,z) = (x & y) ^ (~x & z)
;; = (x&y) ^ ((1^x) &z)
;; = (x&y) ^ (z ^ x&z)
;; = x&y ^ z ^ x&z
;; = x&(y^z) ^z
;;
;; => CHJ(E,F,G) = ((F^G) & E) ^G
;;
%macro CHJ 4.nolist
%xdefine %%F %1
%xdefine %%X %2
%xdefine %%Y %3
%xdefine %%Z %4
mov %%F, %%Y
xor %%F, %%Z
and %%F, %%X
xor %%F, %%Z
%endmacro
;;
;; MAJ(x,y,z) = (x & y) ^ (x & z) ^ (y & z)
;;
;; MAJ(x,y,z) = (x&y) ^ (x&z) ^ (y&z)
;; = (x&y) ^ (x&z) ^ (y&z) ^ (z&z) ^z // note: ((z&z) ^z) = 0
;; = x&(y^z) ^ z&(y^z) ^z
;; = (x^z)&(y^z) ^z
;;
;; => MAJ(A,B,C) = ((A^C) & B) ^ (A&C)
;;
%macro MAJ 4.nolist
%xdefine %%F %1
%xdefine %%X %2
%xdefine %%Y %3
%xdefine %%Z %4
mov %%F, %%X
xor %%F, %%Z ;; maj = x^z
xor %%Y, %%Z ;; y ^= z
and %%F, %%Y ;; maj = (x^z)&(y^z)
xor %%F, %%Z ;; maj = (x^z)&(y^z) ^z
xor %%Y, %%Z ;; restore y
%endmacro
;;
;; SUM1(x) = ROR64(x,14) ^ ROR64(x,18) ^ ROR64(x,41)
;;
;;=> SUM1(x) = ROR((ROR((ROR(x, 23) ^x), 4) ^x), 14)
;;
%macro SUM1 2.nolist
%xdefine %%F %1
%xdefine %%X %2
mov %%F, %%X
ROR64 %%F, 23
xor %%F, %%X
ROR64 %%F, 4
xor %%F, %%X
ROR64 %%F, 14
%endmacro
;;
;; SUM0(x) = ROR64(x,28) ^ ROR64(x,34) ^ ROR64(x,39)
;;
;; => SUM0(x) = ROR((ROR((ROR(x, 5) ^x), 6) ^x), 28)
;;
%macro SUM0 2.nolist
%xdefine %%F %1
%xdefine %%X %2
mov %%F, %%X
ROR64 %%F, 5
xor %%F, %%X
ROR64 %%F, 6
xor %%F, %%X
ROR64 %%F, 28
%endmacro
;; regular SHA512 step
;;
;; Ipp64u T1 = H + SUM1(E) + CHJ(E,F,G) + K_SHA512[t] + W[t];
;; Ipp64u T2 = SUM0(A) + MAJ(A,B,C);
;; D+= T1;
;; H = T1 + T2;
;;
;; where
;; SUM1(x) = ROR64(x,14) ^ ROR64(x,18) ^ ROR64(x,41)
;; SUM0(x) = ROR64(x,28) ^ ROR64(x,34) ^ ROR64(x,39)
;;
;; CHJ(x,y,z) = (x & y) ^ (~x & z)
;; MAJ(x,y,z) = (x & y) ^ (x & z) ^ (y & z) = (x&y)^((x^y)&z)
;;
%macro SHA512_STEP_v0 1.nolist
%xdefine %%nr %1
add H, qword [rsp+(%%nr & 1)*sizeof(qword)]
SUM1 T0, E
CHJ T1, E,F,G
add H, T1
add H, T0
add D, H
SUM0 T0, A
MAJ T1, A,B,C
add H, T1
add H, T0
ROTATE_H
%endmacro
%macro SHA512_2step 9.nolist
%xdefine %%nr %1
%xdefine %%A %2
%xdefine %%B %3
%xdefine %%C %4
%xdefine %%D %5
%xdefine %%E %6
%xdefine %%F %7
%xdefine %%G %8
%xdefine %%H %9
mov T0, %%E ;; T0: SUM1(E)
ROR64 T0, 23 ;; T0: SUM1(E)
add %%H, qword [rsp+(%%nr & 1)*sizeof(qword)]
mov T1, %%F ;; T1: CHJ(E,F,G)
xor T0, %%E ;; T0: SUM1(E)
ROR64 T0, 4 ;; T0: SUM1(E)
xor T1, %%G ;; T1: CHJ(E,G,G)
and T1, %%E ;; T1: CHJ(E,G,G)
xor T0, %%E ;; T0: SUM1(E)
ROR64 T0,14 ;; T0: SUM1(E)
xor T1, %%G ;; T1: CHJ(E,G,G)
add %%H, T1
add %%H, T0 ;; H += SUM1(E) + CHJ(E,F,G) + K_SHA512[t] + W[t]
add %%D, %%H
mov T0, %%A ;; T0: SUM0(A)
ROR64 T0, 5 ;; T0: SUM0(A)
mov T1, %%A ;; T1: MAJ(A,B,C)
xor T1, %%C ;; T1: MAJ(A,B,C)
xor T0, %%A ;; T0: SUM0(A)
ROR64 T0, 6 ;; T0: SUM0(A)
xor %%B, %%C ;; T1: MAJ(A,B,C)
and T1, %%B ;; T1: MAJ(A,B,C)
xor T0, %%A ;; T0: SUM0(A)
ROR64 T0,28 ;; T0: SUM0(A)
xor %%B, %%C ;; T1: MAJ(A,B,C)
xor T1, %%C ;; T1: MAJ(A,B,C)
add %%H, T0
add %%H, T1
;ROTATE_H
mov T0, %%D ;; T0: SUM1(E)
ROR64 T0, 23 ;; T0: SUM1(E)
add %%G, qword [rsp+((%%nr+1) & 1)*sizeof(qword)]
mov T1, %%E ;; T1: CHJ(E,F,G)
xor T0, %%D ;; T0: SUM1(E)
ROR64 T0, 4 ;; T0: SUM1(E)
xor T1, %%F ;; T1: CHJ(E,G,G)
and T1, %%D ;; T1: CHJ(E,G,G)
xor T0, %%D ;; T0: SUM1(E)
ROR64 T0,14 ;; T0: SUM1(E)
xor T1, %%F ;; T1: CHJ(E,G,G)
add %%G, T1
add %%G, T0 ;; H += SUM1(E) + CHJ(E,F,G) + K_SHA512[t] + W[t]
add %%C, %%G
mov T0, %%H ;; T0: SUM0(A)
ROR64 T0, 5 ;; T0: SUM0(A)
mov T1, %%H ;; T1: MAJ(A,B,C)
xor T1, %%B ;; T1: MAJ(A,B,C)
xor T0, %%H ;; T0: SUM0(A)
ROR64 T0, 6 ;; T0: SUM0(A)
xor %%A, %%B ;; T1: MAJ(A,B,C)
and T1, %%A ;; T1: MAJ(A,B,C)
xor T0, %%H ;; T0: SUM0(A)
ROR64 T0,28 ;; T0: SUM0(A)
xor %%A, %%B ;; T1: MAJ(A,B,C)
xor T1, %%B ;; T1: MAJ(A,B,C)
add %%G, T0
add %%G, T1
;ROTATE_H
%endmacro
;;
;; update W[]
;;
;; W[j] = SIG1(W[j- 2]) + W[j- 7]
;; +SIG0(W[j-15]) + W[j-16]
;;
;; SIG0(x) = ROR(x,1) ^ROR(x,8) ^LSR(x,7)
;; SIG1(x) = ROR(x,19)^ROR(x,61) ^LSR(x,6)
;;
%macro SHA512_2Wupdate 0.nolist
vpalignr xT1, W5, W4, 8 ;; xT1 = W[t-7]
vpalignr xT0, W1, W0, 8 ;; xT0 = W[t-15]
vpaddq W0, W0, xT1 ;; W0 = W0 + W[t-7]
vpsrlq SIGMA, W7, 6 ;; SIG1: W[t-2]>>6
vpsrlq xT1, W7,61 ;; SIG1: W[t-2]>>61
vpsllq xT2, W7,(64-61) ;; SIG1: W[t-2]<<(64-61)
vpxor SIGMA, SIGMA, xT1
vpxor SIGMA, SIGMA, xT2
vpsrlq xT1, W7,19 ;; SIG1: W[t-2]>>19
vpsllq xT2, W7,(64-19) ;; SIG1: W[t-2]<<(64-19)
vpxor SIGMA, SIGMA, xT1
vpxor SIGMA, SIGMA, xT2
vpaddq W0, W0, SIGMA ;; W0 = W0 + W[t-7] + SIG1(W[t-2])
vpsrlq SIGMA, xT0, 7 ;; SIG0: W[t-15]>>7
vpsrlq xT1, xT0, 1 ;; SIG0: W[t-15]>>1
vpsllq xT2, xT0,(64-1) ;; SIG0: W[t-15]<<(64-1)
vpxor SIGMA, SIGMA, xT1
vpxor SIGMA, SIGMA, xT2
vpsrlq xT1, xT0, 8 ;; SIG0: W[t-15]>>8
vpsllq xT2, xT0,(64-8) ;; SIG0: W[t-15]<<(64-8)
vpxor SIGMA, SIGMA, xT1
vpxor SIGMA, SIGMA, xT2
vpaddq W0, W0, SIGMA ;; W0 = W0 + W[t-7] + SIG1(W[t-2]) +SIG0(W[t-15])
ROTATE_W
%endmacro
%macro SHA512_2step_2Wupdate 9.nolist
%xdefine %%nr %1
%xdefine %%A %2
%xdefine %%B %3
%xdefine %%C %4
%xdefine %%D %5
%xdefine %%E %6
%xdefine %%F %7
%xdefine %%G %8
%xdefine %%H %9
add %%H, qword [rsp+(%%nr & 1)*sizeof(qword)]
vpalignr xT1, W5, W4, 8 ;; xT1 = W[t-7]
mov T0, %%E ;; T0: SUM1(E)
ROR64 T0, 23 ;; T0: SUM1(E)
vpalignr xT0, W1, W0, 8 ;; xT0 = W[t-15]
mov T1, %%F ;; T1: CHJ(E,F,G)
xor T0, %%E ;; T0: SUM1(E)
vpaddq W0, W0, xT1 ;; W0 = W0 + W[t-7]
ROR64 T0, 4 ;; T0: SUM1(E)
xor T1, %%G ;; T1: CHJ(E,G,G)
vpsrlq SIGMA, W7, 6 ;; SIG1: W[t-2]>>6
and T1, %%E ;; T1: CHJ(E,G,G)
xor T0, %%E ;; T0: SUM1(E)
ROR64 T0,14 ;; T0: SUM1(E)
vpsrlq xT1, W7,61 ;; SIG1: W[t-2]>>61
xor T1, %%G ;; T1: CHJ(E,G,G)
add %%H, T1
add %%H, T0 ;; H += SUM1(E) + CHJ(E,F,G) + K_SHA512[t] + W[t]
vpsllq xT2, W7,(64-61) ;; SIG1: W[t-2]<<(64-61)
add %%D, %%H
mov T0, %%A ;; T0: SUM0(A)
ROR64 T0, 5 ;; T0: SUM0(A)
vpxor SIGMA, SIGMA, xT1
mov T1, %%A ;; T1: MAJ(A,B,C)
xor T1, %%C ;; T1: MAJ(A,B,C)
vpxor SIGMA, SIGMA, xT2
xor T0, %%A ;; T0: SUM0(A)
ROR64 T0, 6 ;; T0: SUM0(A)
vpsrlq xT1, W7,19 ;; SIG1: W[t-2]>>19
xor %%B, %%C ;; T1: MAJ(A,B,C)
and T1, %%B ;; T1: MAJ(A,B,C)
xor T0, %%A ;; T0: SUM0(A)
vpsllq xT2, W7,(64-19) ;; SIG1: W[t-2]<<(64-19)
ROR64 T0,28 ;; T0: SUM0(A)
xor %%B, %%C ;; T1: MAJ(A,B,C)
xor T1, %%C ;; T1: MAJ(A,B,C)
vpxor SIGMA, SIGMA, xT1
add %%H, T0
add %%H, T1
;ROTATE_H
vpxor SIGMA, SIGMA, xT2
mov T0, %%D ;; T0: SUM1(E)
ROR64 T0, 23 ;; T0: SUM1(E)
vpaddq W0, W0, SIGMA ;; W0 = W0 + W[t-7] + SIG1(W[t-2])
add %%G, qword [rsp+((%%nr+1) & 1)*sizeof(qword)]
mov T1, %%E ;; T1: CHJ(E,F,G)
vpsrlq SIGMA, xT0, 7 ;; SIG0: W[t-15]>>7
xor T0, %%D ;; T0: SUM1(E)
ROR64 T0, 4 ;; T0: SUM1(E)
xor T1, %%F ;; T1: CHJ(E,G,G)
vpsrlq xT1, xT0, 1 ;; SIG0: W[t-15]>>1
and T1, %%D ;; T1: CHJ(E,G,G)
xor T0, %%D ;; T0: SUM1(E)
ROR64 T0,14 ;; T0: SUM1(E)
vpsllq xT2, xT0,(64-1) ;; SIG0: W[t-15]<<(64-1)
xor T1, %%F ;; T1: CHJ(E,G,G)
add %%G, T1
add %%G, T0 ;; H += SUM1(E) + CHJ(E,F,G) + K_SHA512[t] + W[t]
vpxor SIGMA, SIGMA, xT1
add %%C, %%G
mov T0, %%H ;; T0: SUM0(A)
vpxor SIGMA, SIGMA, xT2
ROR64 T0, 5 ;; T0: SUM0(A)
mov T1, %%H ;; T1: MAJ(A,B,C)
vpsrlq xT1, xT0, 8 ;; SIG0: W[t-15]>>8
xor T1, %%B ;; T1: MAJ(A,B,C)
xor T0, %%H ;; T0: SUM0(A)
ROR64 T0, 6 ;; T0: SUM0(A)
vpsllq xT2, xT0,(64-8) ;; SIG0: W[t-15]<<(64-8)
xor %%A, %%B ;; T1: MAJ(A,B,C)
and T1, %%A ;; T1: MAJ(A,B,C)
xor T0, %%H ;; T0: SUM0(A)
vpxor SIGMA, SIGMA, xT1
ROR64 T0,28 ;; T0: SUM0(A)
xor %%A, %%B ;; T1: MAJ(A,B,C)
vpxor SIGMA, SIGMA, xT2
xor T1, %%B ;; T1: MAJ(A,B,C)
add %%G, T0
vpaddq W0, W0, SIGMA ;; W0 = W0 + W[t-7] + SIG1(W[t-2]) +SIG0(W[t-15])
add %%G, T1
;ROTATE_H
ROTATE_W
%endmacro
segment .text align=IPP_ALIGN_FACTOR
align IPP_ALIGN_FACTOR
SHUFB_BSWAP DB 7,6,5,4,3,2,1,0, 15,14,13,12,11,10,9,8
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; UpdateSHA512(Ipp64u digest[], Ipp8u dataBlock[], int datalen, Ipp64u K_512[])
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
align IPP_ALIGN_FACTOR
IPPASM UpdateSHA512,PUBLIC
%assign LOCAL_FRAME sizeof(oword)+sizeof(qword)
USES_GPR rbx,rsi,rdi,rbp,r12,r13,r14,r15
USES_XMM xmm6,xmm7,xmm8,xmm9,xmm10,xmm11
COMP_ABI 4
;;
;; rdi = pointer to the updated hash
;; rsi = pointer to the data block
;; rdx = data block length
;; rcx = pointer to the SHA_512 constant
;;
%xdefine MBS_SHA512 (128)
vmovdqa xT1, oword [rel SHUFB_BSWAP]
movsxd rdx, edx
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; process next data block
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
align IPP_ALIGN_FACTOR
.sha512_block_loop:
;;
;; initialize the first 16 qwords in the array W (remember about endian)
;;
vmovdqu W0, oword [rsi] ; load buffer content and swap
vpshufb W0, W0, xT1
vmovdqu W1, oword [rsi+sizeof(oword)*1];
vpshufb W1, W1, xT1
vmovdqu W2, oword [rsi+sizeof(oword)*2];
vpshufb W2, W2, xT1
vmovdqu W3, oword [rsi+sizeof(oword)*3];
vpshufb W3, W3, xT1
vmovdqu W4, oword [rsi+sizeof(oword)*4];
vpshufb W4, W4, xT1
vmovdqu W5, oword [rsi+sizeof(oword)*5];
vpshufb W5, W5, xT1
vmovdqu W6, oword [rsi+sizeof(oword)*6];
vpshufb W6, W6, xT1
vmovdqu W7, oword [rsi+sizeof(oword)*7];
vpshufb W7, W7, xT1
mov A, qword [rdi] ; load initial hash value
mov B, qword [rdi+sizeof(qword)]
mov C, qword [rdi+sizeof(qword)*2]
mov D, qword [rdi+sizeof(qword)*3]
mov E, qword [rdi+sizeof(qword)*4]
mov F, qword [rdi+sizeof(qword)*5]
mov G, qword [rdi+sizeof(qword)*6]
mov H, qword [rdi+sizeof(qword)*7]
;; perform 0- 9 rounds
vpaddq xT1, W0, oword [KK_SHA512+ 0*sizeof(qword)] ; T += K_SHA512[0-1]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 0, A,B,C,D,E,F,G,H
vpaddq xT1, W0, oword [KK_SHA512+ 2*sizeof(qword)] ; T += K_SHA512[2-3]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 2, G,H,A,B,C,D,E,F
vpaddq xT1, W0, oword [KK_SHA512+ 4*sizeof(qword)] ; T += K_SHA512[4-5]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 4, E,F,G,H,A,B,C,D
vpaddq xT1, W0, oword [KK_SHA512+ 6*sizeof(qword)] ; T += K_SHA512[6-7]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 6, C,D,E,F,G,H,A,B
vpaddq xT1, W0, oword [KK_SHA512+ 8*sizeof(qword)] ; T += K_SHA512[8-9]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 8, A,B,C,D,E,F,G,H
;; perform 10-19 rounds
vpaddq xT1, W0, oword [KK_SHA512+10*sizeof(qword)] ; T += K_SHA512[10-11]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 10, G,H,A,B,C,D,E,F
vpaddq xT1, W0, oword [KK_SHA512+12*sizeof(qword)] ; T += K_SHA512[12-13]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 12, E,F,G,H,A,B,C,D
vpaddq xT1, W0, oword [KK_SHA512+14*sizeof(qword)] ; T += K_SHA512[14-15]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 14, C,D,E,F,G,H,A,B
vpaddq xT1, W0, oword [KK_SHA512+16*sizeof(qword)] ; T += K_SHA512[16-17]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 16, A,B,C,D,E,F,G,H
vpaddq xT1, W0, oword [KK_SHA512+18*sizeof(qword)] ; T += K_SHA512[18-19]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 18, G,H,A,B,C,D,E,F
;; perform 20-29 rounds
vpaddq xT1, W0, oword [KK_SHA512+20*sizeof(qword)] ; T += K_SHA512[20-21]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 20, E,F,G,H,A,B,C,D
vpaddq xT1, W0, oword [KK_SHA512+22*sizeof(qword)] ; T += K_SHA512[22-23]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 22, C,D,E,F,G,H,A,B
vpaddq xT1, W0, oword [KK_SHA512+24*sizeof(qword)] ; T += K_SHA512[24-25]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 24, A,B,C,D,E,F,G,H
vpaddq xT1, W0, oword [KK_SHA512+26*sizeof(qword)] ; T += K_SHA512[26-27]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 26, G,H,A,B,C,D,E,F
vpaddq xT1, W0, oword [KK_SHA512+28*sizeof(qword)] ; T += K_SHA512[28-29]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 28, E,F,G,H,A,B,C,D
;; perform 30-39 rounds
vpaddq xT1, W0, oword [KK_SHA512+30*sizeof(qword)] ; T += K_SHA512[30-31]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 30, C,D,E,F,G,H,A,B
vpaddq xT1, W0, oword [KK_SHA512+32*sizeof(qword)] ; T += K_SHA512[32-33]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 32, A,B,C,D,E,F,G,H
vpaddq xT1, W0, oword [KK_SHA512+34*sizeof(qword)] ; T += K_SHA512[34-35]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 34, G,H,A,B,C,D,E,F
vpaddq xT1, W0, oword [KK_SHA512+36*sizeof(qword)] ; T += K_SHA512[36-37]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 36, E,F,G,H,A,B,C,D
vpaddq xT1, W0, oword [KK_SHA512+38*sizeof(qword)] ; T += K_SHA512[38-39]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 38, C,D,E,F,G,H,A,B
;; perform 40-49 rounds
vpaddq xT1, W0, oword [KK_SHA512+40*sizeof(qword)] ; T += K_SHA512[40-41]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 40, A,B,C,D,E,F,G,H
vpaddq xT1, W0, oword [KK_SHA512+42*sizeof(qword)] ; T += K_SHA512[42-43]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 42, G,H,A,B,C,D,E,F
vpaddq xT1, W0, oword [KK_SHA512+44*sizeof(qword)] ; T += K_SHA512[44-45]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 44, E,F,G,H,A,B,C,D
vpaddq xT1, W0, oword [KK_SHA512+46*sizeof(qword)] ; T += K_SHA512[46-47]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 46, C,D,E,F,G,H,A,B
vpaddq xT1, W0, oword [KK_SHA512+48*sizeof(qword)] ; T += K_SHA512[48-49]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 48, A,B,C,D,E,F,G,H
;; perform 50-59 rounds
vpaddq xT1, W0, oword [KK_SHA512+50*sizeof(qword)] ; T += K_SHA512[50-51]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 50, G,H,A,B,C,D,E,F
vpaddq xT1, W0, oword [KK_SHA512+52*sizeof(qword)] ; T += K_SHA512[52-53]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 52, E,F,G,H,A,B,C,D
vpaddq xT1, W0, oword [KK_SHA512+54*sizeof(qword)] ; T += K_SHA512[54-55]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 54, C,D,E,F,G,H,A,B
vpaddq xT1, W0, oword [KK_SHA512+56*sizeof(qword)] ; T += K_SHA512[56-57]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 56, A,B,C,D,E,F,G,H
vpaddq xT1, W0, oword [KK_SHA512+58*sizeof(qword)] ; T += K_SHA512[58-59]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 58, G,H,A,B,C,D,E,F
;; perform 60-69 rounds
vpaddq xT1, W0, oword [KK_SHA512+60*sizeof(qword)] ; T += K_SHA512[60-61]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 60, E,F,G,H,A,B,C,D
vpaddq xT1, W0, oword [KK_SHA512+62*sizeof(qword)] ; T += K_SHA512[62-63]
vmovdqa oword [rsp], xT1
SHA512_2step_2Wupdate 62, C,D,E,F,G,H,A,B
vpaddq xT1, W0, oword [KK_SHA512+64*sizeof(qword)] ; T += K_SHA512[64-65]
vmovdqa oword [rsp], xT1
SHA512_2step 64, A,B,C,D,E,F,G,H
ROTATE_W
vpaddq xT1, W0, oword [KK_SHA512+66*sizeof(qword)] ; T += K_SHA512[66-67]
vmovdqa oword [rsp], xT1
SHA512_2step 66, G,H,A,B,C,D,E,F
ROTATE_W
vpaddq xT1, W0, oword [KK_SHA512+68*sizeof(qword)] ; T += K_SHA512[68-69]
vmovdqa oword [rsp], xT1
SHA512_2step 68, E,F,G,H,A,B,C,D
ROTATE_W
;; perform 70-79 rounds
vpaddq xT1, W0, oword [KK_SHA512+70*sizeof(qword)] ; T += K_SHA512[70-71]
vmovdqa oword [rsp], xT1
SHA512_2step 70, C,D,E,F,G,H,A,B
ROTATE_W
vpaddq xT1, W0, oword [KK_SHA512+72*sizeof(qword)] ; T += K_SHA512[72-73]
vmovdqa oword [rsp], xT1
SHA512_2step 72, A,B,C,D,E,F,G,H
ROTATE_W
vpaddq xT1, W0, oword [KK_SHA512+74*sizeof(qword)] ; T += K_SHA512[74-75]
vmovdqa oword [rsp], xT1
SHA512_2step 74, G,H,A,B,C,D,E,F
ROTATE_W
vpaddq xT1, W0, oword [KK_SHA512+76*sizeof(qword)] ; T += K_SHA512[76-77]
vmovdqa oword [rsp], xT1
SHA512_2step 76, E,F,G,H,A,B,C,D
ROTATE_W
vpaddq xT1, W0, oword [KK_SHA512+78*sizeof(qword)] ; T += K_SHA512[78-79]
vmovdqa oword [rsp], xT1
SHA512_2step 78, C,D,E,F,G,H,A,B
ROTATE_W
add qword [rdi], A ; update shash
add qword [rdi+sizeof(qword)*1], B
add qword [rdi+sizeof(qword)*2], C
add qword [rdi+sizeof(qword)*3], D
add qword [rdi+sizeof(qword)*4], E
add qword [rdi+sizeof(qword)*5], F
add qword [rdi+sizeof(qword)*6], G
add qword [rdi+sizeof(qword)*7], H
vmovdqa xT1, oword [rel SHUFB_BSWAP]
add rsi, MBS_SHA512
sub rdx, MBS_SHA512
jg .sha512_block_loop
REST_XMM
REST_GPR
ret
ENDFUNC UpdateSHA512
%endif ;; (_IPP32E >= _IPP32E_E9 )
%endif ;; _ENABLE_ALG_SHA512_
| 28.557377 | 90 | 0.516456 |
5c844ee75ae86442f1e7140ed8020e740e15df93 | 1,057 | asm | Assembly | codegen-tests/bitfield-class/icc13.0.1/14-post-decrement.asm | Deaod/bitfields | e84c18f18621637174edaffbefec486a45fbd9cf | [
"MIT"
] | null | null | null | codegen-tests/bitfield-class/icc13.0.1/14-post-decrement.asm | Deaod/bitfields | e84c18f18621637174edaffbefec486a45fbd9cf | [
"MIT"
] | null | null | null | codegen-tests/bitfield-class/icc13.0.1/14-post-decrement.asm | Deaod/bitfields | e84c18f18621637174edaffbefec486a45fbd9cf | [
"MIT"
] | null | null | null | L__routine_start__Z11test_devicev_0:
test_device():
push rsi #270.20
call rand #272.14
mov ecx, DWORD PTR [rsp] #202.23
mov edx, ecx #203.23
and edx, -258049 #203.23
lea eax, DWORD PTR [-4096+rcx] #203.55
shr ecx, 12 #204.24
and eax, 258048 #203.97
and ecx, 63 #204.37
or edx, eax #203.97
mov DWORD PTR [rsp], edx #203.9
mov DWORD PTR [4+rsp], ecx #290.4
pop rcx #291.1
ret #291.1
| 58.722222 | 71 | 0.251656 |
6d855fce4f665c99aede4fa3fd3d584df6826c1b | 1,265 | asm | Assembly | vp8/common/ppc/copy_altivec.asm | mrchapp/libvpx | c2a8d8b54c7ebefd1cd9c55f53b9e8378f088e8b | [
"BSD-3-Clause"
] | 1 | 2015-05-03T19:25:39.000Z | 2015-05-03T19:25:39.000Z | vp8/common/ppc/copy_altivec.asm | mrchapp/libvpx | c2a8d8b54c7ebefd1cd9c55f53b9e8378f088e8b | [
"BSD-3-Clause"
] | null | null | null | vp8/common/ppc/copy_altivec.asm | mrchapp/libvpx | c2a8d8b54c7ebefd1cd9c55f53b9e8378f088e8b | [
"BSD-3-Clause"
] | null | null | null | ;
; Copyright (c) 2010 The VP8 project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing project authors may
; be found in the AUTHORS file in the root of the source tree.
;
.globl copy_mem16x16_ppc
;# r3 unsigned char *src
;# r4 int src_stride
;# r5 unsigned char *dst
;# r6 int dst_stride
;# Make the assumption that input will not be aligned,
;# but the output will be. So two reads and a perm
;# for the input, but only one store for the output.
copy_mem16x16_ppc:
mfspr r11, 256 ;# get old VRSAVE
oris r12, r11, 0xe000
mtspr 256, r12 ;# set VRSAVE
li r10, 16
mtctr r10
cp_16x16_loop:
lvsl v0, 0, r3 ;# permutate value for alignment
lvx v1, 0, r3
lvx v2, r10, r3
vperm v1, v1, v2, v0
stvx v1, 0, r5
add r3, r3, r4 ;# increment source pointer
add r5, r5, r6 ;# increment destination pointer
bdnz cp_16x16_loop
mtspr 256, r11 ;# reset old VRSAVE
blr
| 26.354167 | 70 | 0.626877 |
f99406c49876c84c2e10c86e10671506953f0456 | 1,574 | asm | Assembly | programs/oeis/064/A064800.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/064/A064800.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/064/A064800.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A064800: n plus the number of its prime factors: a(n) = n + A001222(n).
; 1,3,4,6,6,8,8,11,11,12,12,15,14,16,17,20,18,21,20,23,23,24,24,28,27,28,30,31,30,33,32,37,35,36,37,40,38,40,41,44,42,45,44,47,48,48,48,53,51,53,53,55,54,58,57,60,59,60,60,64,62,64,66,70,67,69,68,71,71,73,72,77,74,76,78,79,79,81,80,85,85,84,84,88,87,88,89,92,90,94,93,95,95,96,97,102,98,101,102,104,102,105,104,108,108,108,108,113,110,113,113,117,114,117,117,119,120,120,121,125,123,124,125,127,128,130,128,135,131,133,132,136,135,136,139,140,138,141,140,144,143,144,145,150,147,148,150,151,150,154,152,156,156,157,157,160,158,160,161,166,163,167,164,167,168,168,168,173,171,173,174,175,174,177,178,181,179,180,180,185,182,185,185,188,187,189,189,191,193,193,192,199,194,196,198,200,198,202,200,205,203,204,205,208,207,208,210,213,211,214,212,215,215,216,217,222,219,220,221,224,223,225,224,230,229,228,228,232,230,233,234,236,234,238,237,239,239,241,240,246,242,245,248,247,248,249,249,252,251,254
mov $12,$0
mov $14,2
mov $16,$0
lpb $14,1
mov $0,$12
sub $0,1
mov $6,$0
mov $8,2
sub $14,1
lpb $8,1
clr $0,6
mov $0,$6
sub $8,1
add $0,$8
sub $0,1
add $3,$0
add $4,1
add $1,$4
mul $1,2
add $0,$1
cal $0,22559 ; Sum of exponents in prime-power factorization of n!.
lpb $4,1
mov $2,$0
mov $0,$3
lpb $4,1
sub $4,1
lpe
add $0,$2
add $0,1
lpe
mov $1,$0
mov $9,$8
lpb $9,1
mov $7,$1
sub $9,1
lpe
lpe
lpb $6,1
mov $6,0
sub $7,$1
lpe
lpe
mov $1,$7
add $1,$16
| 32.791667 | 898 | 0.608005 |
710f55c6e75cbc29377365a75471c9fa511cb5f5 | 626 | asm | Assembly | programs/oeis/206/A206981.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/206/A206981.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/206/A206981.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A206981: Number of nX2 0..1 arrays avoiding the patterns 0 1 0 or 1 0 1 in any row, column, diagonal or antidiagonal
; 4,16,36,100,256,676,1764,4624,12100,31684,82944,217156,568516,1488400,3896676,10201636,26708224,69923044,183060900,479259664,1254718084,3284894596,8599965696,22515002500,58945041796,154320122896,404015326884,1057725857764,2769162246400,7249760881444,18980120397924,49690600312336,130091680539076,340584441304900,891661643375616,2334400488821956,6111539823090244
mov $2,1
mov $3,1
lpb $0,1
sub $0,1
mov $4,$3
add $3,$2
mov $2,$4
lpe
mov $1,2
mul $1,$3
pow $1,2
sub $1,4
div $1,4
mul $1,4
add $1,4
| 32.947368 | 363 | 0.777955 |
e0db992a6a11caafb3bfb9d028a18b98ada0e077 | 111 | asm | Assembly | src/main/fragment/mos6502-common/(_deref_qbuz1)_derefidx_vbuxx=(_deref_qbuz1)_derefidx_vbuxx_bor_pbuc1_derefidx_vbuyy.asm | jbrandwood/kickc | d4b68806f84f8650d51b0e3ef254e40f38b0ffad | [
"MIT"
] | 2 | 2022-03-01T02:21:14.000Z | 2022-03-01T04:33:35.000Z | src/main/fragment/mos6502-common/(_deref_qbuz1)_derefidx_vbuxx=(_deref_qbuz1)_derefidx_vbuxx_bor_pbuc1_derefidx_vbuyy.asm | jbrandwood/kickc | d4b68806f84f8650d51b0e3ef254e40f38b0ffad | [
"MIT"
] | null | null | null | src/main/fragment/mos6502-common/(_deref_qbuz1)_derefidx_vbuxx=(_deref_qbuz1)_derefidx_vbuxx_bor_pbuc1_derefidx_vbuyy.asm | jbrandwood/kickc | d4b68806f84f8650d51b0e3ef254e40f38b0ffad | [
"MIT"
] | null | null | null | sty $fd
ldy #0
lda ({z1}),y
sta $fe
iny
lda ({z1}),y
sta $ff
txa
tay
ldx $fd
lda ($fe),y
ora {c1},x
sta ($fe),y | 8.538462 | 12 | 0.567568 |
31d54c46f5ee07a9a30ad8a181691d5e5dc3dd01 | 26,857 | asm | Assembly | sources/ippcp/asm_intel64/pcpp384r1funcs_montas.asm | ymarkovitch/ipp-crypto | ac8f1c443cc79e9f2f8508f8c707c9ed0caa22c8 | [
"Apache-2.0"
] | null | null | null | sources/ippcp/asm_intel64/pcpp384r1funcs_montas.asm | ymarkovitch/ipp-crypto | ac8f1c443cc79e9f2f8508f8c707c9ed0caa22c8 | [
"Apache-2.0"
] | null | null | null | sources/ippcp/asm_intel64/pcpp384r1funcs_montas.asm | ymarkovitch/ipp-crypto | ac8f1c443cc79e9f2f8508f8c707c9ed0caa22c8 | [
"Apache-2.0"
] | null | null | null | ;===============================================================================
; Copyright 2014-2019 Intel Corporation
; All Rights Reserved.
;
; If this software was obtained under the Intel Simplified Software License,
; the following terms apply:
;
; The source code, information and material ("Material") contained herein is
; owned by Intel Corporation or its suppliers or licensors, and title to such
; Material remains with Intel Corporation or its suppliers or licensors. The
; Material contains proprietary information of Intel or its suppliers and
; licensors. The Material is protected by worldwide copyright laws and treaty
; provisions. No part of the Material may be used, copied, reproduced,
; modified, published, uploaded, posted, transmitted, distributed or disclosed
; in any way without Intel's prior express written permission. No license under
; any patent, copyright or other intellectual property rights in the Material
; is granted to or conferred upon you, either expressly, by implication,
; inducement, estoppel or otherwise. Any license under such intellectual
; property rights must be express and approved by Intel in writing.
;
; Unless otherwise agreed by Intel in writing, you may not remove or alter this
; notice or any other notice embedded in Materials by Intel or Intel's
; suppliers or licensors in any way.
;
;
; If this software was obtained under the Apache License, Version 2.0 (the
; "License"), the following terms apply:
;
; You may not use this file except in compliance with the License. You may
; obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
;
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;
; See the License for the specific language governing permissions and
; limitations under the License.
;===============================================================================
;
;
; Purpose: Cryptography Primitive.
; secp p384r1 specific implementation
;
include asmdefs.inc
include ia_32e.inc
IF _IPP32E GE _IPP32E_M7
_xEMULATION_ = 1
_ADCX_ADOX_ = 1
.LIST
IPPCODE SEGMENT 'CODE' ALIGN (IPP_ALIGN_FACTOR)
ALIGN IPP_ALIGN_FACTOR
;; The p384r1 polynomial
Lpoly DQ 000000000ffffffffh,0ffffffff00000000h,0fffffffffffffffeh
DQ 0ffffffffffffffffh,0ffffffffffffffffh,0ffffffffffffffffh
;; 2^(2*384) mod P precomputed for p384r1 polynomial
;LRR DQ 0fffffffe00000001h,00000000200000000h,0fffffffe00000000h
; DQ 00000000200000000h,00000000000000001h,00000000000000000h
LOne DD 1,1,1,1,1,1,1,1
LTwo DD 2,2,2,2,2,2,2,2
LThree DD 3,3,3,3,3,3,3,3
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; void p384r1_mul_by_2(uint64_t res[6], uint64_t a[6]);
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ALIGN IPP_ALIGN_FACTOR
IPPASM p384r1_mul_by_2 PROC PUBLIC FRAME
USES_GPR rsi,rdi,r12
LOCAL_FRAME = 0
USES_XMM
COMP_ABI 2
a0 equ rax
a1 equ rcx
a2 equ rdx
a3 equ r8
a4 equ r9
a5 equ r10
ex equ r11
t equ r12
xor ex, ex
mov a0, qword ptr[rsi+sizeof(qword)*0]
mov a1, qword ptr[rsi+sizeof(qword)*1]
mov a2, qword ptr[rsi+sizeof(qword)*2]
mov a3, qword ptr[rsi+sizeof(qword)*3]
mov a4, qword ptr[rsi+sizeof(qword)*4]
mov a5, qword ptr[rsi+sizeof(qword)*5]
shld ex, a5, 1
shld a5, a4, 1
mov qword ptr[rdi+sizeof(qword)*5], a5
shld a4, a3, 1
mov qword ptr[rdi+sizeof(qword)*4], a4
shld a3, a2, 1
mov qword ptr[rdi+sizeof(qword)*3], a3
shld a2, a1, 1
mov qword ptr[rdi+sizeof(qword)*2], a2
shld a1, a0, 1
mov qword ptr[rdi+sizeof(qword)*1], a1
shl a0, 1
mov qword ptr[rdi+sizeof(qword)*0], a0
sub a0, qword ptr Lpoly+sizeof(qword)*0
sbb a1, qword ptr Lpoly+sizeof(qword)*1
sbb a2, qword ptr Lpoly+sizeof(qword)*2
sbb a3, qword ptr Lpoly+sizeof(qword)*3
sbb a4, qword ptr Lpoly+sizeof(qword)*4
sbb a5, qword ptr Lpoly+sizeof(qword)*5
sbb ex, 0
mov t, qword ptr[rdi+sizeof(qword)*0]
cmovnz a0, t
mov t, qword ptr[rdi+sizeof(qword)*1]
cmovnz a1, t
mov t, qword ptr[rdi+sizeof(qword)*2]
cmovnz a2, t
mov t, qword ptr[rdi+sizeof(qword)*3]
cmovnz a3, t
mov t, qword ptr[rdi+sizeof(qword)*4]
cmovnz a4, t
mov t, qword ptr[rdi+sizeof(qword)*5]
cmovnz a5, t
mov qword ptr[rdi+sizeof(qword)*0], a0
mov qword ptr[rdi+sizeof(qword)*1], a1
mov qword ptr[rdi+sizeof(qword)*2], a2
mov qword ptr[rdi+sizeof(qword)*3], a3
mov qword ptr[rdi+sizeof(qword)*4], a4
mov qword ptr[rdi+sizeof(qword)*5], a5
REST_XMM
REST_GPR
ret
IPPASM p384r1_mul_by_2 ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; void p384r1_div_by_2(uint64_t res[6], uint64_t a[6]);
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ALIGN IPP_ALIGN_FACTOR
IPPASM p384r1_div_by_2 PROC PUBLIC FRAME
USES_GPR rsi,rdi,r12
LOCAL_FRAME = 0
USES_XMM
COMP_ABI 2
a0 equ rax
a1 equ rcx
a2 equ rdx
a3 equ r8
a4 equ r9
a5 equ r10
ex equ r11
t equ r12
mov a0, qword ptr[rsi+sizeof(qword)*0]
mov a1, qword ptr[rsi+sizeof(qword)*1]
mov a2, qword ptr[rsi+sizeof(qword)*2]
mov a3, qword ptr[rsi+sizeof(qword)*3]
mov a4, qword ptr[rsi+sizeof(qword)*4]
mov a5, qword ptr[rsi+sizeof(qword)*5]
xor t, t
xor ex, ex
add a0, qword ptr Lpoly+sizeof(qword)*0
adc a1, qword ptr Lpoly+sizeof(qword)*1
adc a2, qword ptr Lpoly+sizeof(qword)*2
adc a3, qword ptr Lpoly+sizeof(qword)*3
adc a4, qword ptr Lpoly+sizeof(qword)*4
adc a5, qword ptr Lpoly+sizeof(qword)*5
adc ex, 0
test a0, 1
cmovnz ex, t
mov t, qword ptr[rsi+sizeof(qword)*0]
cmovnz a0, t
mov t, qword ptr[rsi+sizeof(qword)*1]
cmovnz a1, t
mov t, qword ptr[rsi+sizeof(qword)*2]
cmovnz a2, t
mov t, qword ptr[rsi+sizeof(qword)*3]
cmovnz a3, t
mov t, qword ptr[rsi+sizeof(qword)*4]
cmovnz a4, t
mov t, qword ptr[rsi+sizeof(qword)*5]
cmovnz a5, t
shrd a0, a1, 1
shrd a1, a2, 1
shrd a2, a3, 1
shrd a3, a4, 1
shrd a4, a5, 1
shrd a5, ex, 1
mov qword ptr[rdi+sizeof(qword)*0], a0
mov qword ptr[rdi+sizeof(qword)*1], a1
mov qword ptr[rdi+sizeof(qword)*2], a2
mov qword ptr[rdi+sizeof(qword)*3], a3
mov qword ptr[rdi+sizeof(qword)*4], a4
mov qword ptr[rdi+sizeof(qword)*5], a5
REST_XMM
REST_GPR
ret
IPPASM p384r1_div_by_2 ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; void p384r1_mul_by_3(uint64_t res[6], uint64_t a[6]);
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ALIGN IPP_ALIGN_FACTOR
IPPASM p384r1_mul_by_3 PROC PUBLIC FRAME
USES_GPR rsi,rdi,r12,r13
LOCAL_FRAME = sizeof(qword)*6
USES_XMM
COMP_ABI 2
a0 equ rax
a1 equ rcx
a2 equ rdx
a3 equ r8
a4 equ r9
a5 equ r10
ex equ r11
t equ r12
xor ex, ex
mov a0, qword ptr[rsi+sizeof(qword)*0]
mov a1, qword ptr[rsi+sizeof(qword)*1]
mov a2, qword ptr[rsi+sizeof(qword)*2]
mov a3, qword ptr[rsi+sizeof(qword)*3]
mov a4, qword ptr[rsi+sizeof(qword)*4]
mov a5, qword ptr[rsi+sizeof(qword)*5]
shld ex, a5, 1
shld a5, a4, 1
mov qword ptr[rsp+sizeof(qword)*5], a5
shld a4, a3, 1
mov qword ptr[rsp+sizeof(qword)*4], a4
shld a3, a2, 1
mov qword ptr[rsp+sizeof(qword)*3], a3
shld a2, a1, 1
mov qword ptr[rsp+sizeof(qword)*2], a2
shld a1, a0, 1
mov qword ptr[rsp+sizeof(qword)*1], a1
shl a0, 1
mov qword ptr[rsp+sizeof(qword)*0], a0
sub a0, qword ptr Lpoly+sizeof(qword)*0
sbb a1, qword ptr Lpoly+sizeof(qword)*1
sbb a2, qword ptr Lpoly+sizeof(qword)*2
sbb a3, qword ptr Lpoly+sizeof(qword)*3
sbb a4, qword ptr Lpoly+sizeof(qword)*4
sbb a5, qword ptr Lpoly+sizeof(qword)*5
sbb ex, 0
mov t, qword ptr[rsp+0*sizeof(qword)]
cmovb a0, t
mov t, qword ptr[rsp+1*sizeof(qword)]
cmovb a1, t
mov t, qword ptr[rsp+2*sizeof(qword)]
cmovb a2, t
mov t, qword ptr[rsp+3*sizeof(qword)]
cmovb a3, t
mov t, qword ptr[rsp+4*sizeof(qword)]
cmovb a4, t
mov t, qword ptr[rsp+5*sizeof(qword)]
cmovb a5, t
xor ex, ex
add a0, qword ptr[rsi+sizeof(qword)*0]
mov qword ptr[rsp+sizeof(qword)*0], a0
adc a1, qword ptr[rsi+sizeof(qword)*1]
mov qword ptr[rsp+sizeof(qword)*1], a1
adc a2, qword ptr[rsi+sizeof(qword)*2]
mov qword ptr[rsp+sizeof(qword)*2], a2
adc a3, qword ptr[rsi+sizeof(qword)*3]
mov qword ptr[rsp+sizeof(qword)*3], a3
adc a4, qword ptr[rsi+sizeof(qword)*4]
mov qword ptr[rsp+sizeof(qword)*4], a4
adc a5, qword ptr[rsi+sizeof(qword)*5]
mov qword ptr[rsp+sizeof(qword)*5], a5
adc ex, 0
sub a0, qword ptr Lpoly+sizeof(qword)*0
sbb a1, qword ptr Lpoly+sizeof(qword)*1
sbb a2, qword ptr Lpoly+sizeof(qword)*2
sbb a3, qword ptr Lpoly+sizeof(qword)*3
sbb a4, qword ptr Lpoly+sizeof(qword)*4
sbb a5, qword ptr Lpoly+sizeof(qword)*5
sbb ex, 0
mov t, qword ptr[rsp+sizeof(qword)*0]
cmovb a0, t
mov t, qword ptr[rsp+sizeof(qword)*1]
cmovb a1, t
mov t, qword ptr[rsp+sizeof(qword)*2]
cmovb a2, t
mov t, qword ptr[rsp+sizeof(qword)*3]
cmovb a3, t
mov t, qword ptr[rsp+sizeof(qword)*4]
cmovb a4, t
mov t, qword ptr[rsp+sizeof(qword)*5]
cmovb a5, t
mov qword ptr[rdi+sizeof(qword)*0], a0
mov qword ptr[rdi+sizeof(qword)*1], a1
mov qword ptr[rdi+sizeof(qword)*2], a2
mov qword ptr[rdi+sizeof(qword)*3], a3
mov qword ptr[rdi+sizeof(qword)*4], a4
mov qword ptr[rdi+sizeof(qword)*5], a5
REST_XMM
REST_GPR
ret
IPPASM p384r1_mul_by_3 ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; void p384r1_add(uint64_t res[6], uint64_t a[6], uint64_t b[6]);
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ALIGN IPP_ALIGN_FACTOR
IPPASM p384r1_add PROC PUBLIC FRAME
USES_GPR rbx,rsi,rdi,r12
LOCAL_FRAME = 0
USES_XMM
COMP_ABI 3
a0 equ rax
a1 equ rcx
a2 equ rbx
a3 equ r8
a4 equ r9
a5 equ r10
ex equ r11
t equ r12
xor ex, ex
mov a0, qword ptr[rsi+sizeof(qword)*0]
mov a1, qword ptr[rsi+sizeof(qword)*1]
mov a2, qword ptr[rsi+sizeof(qword)*2]
mov a3, qword ptr[rsi+sizeof(qword)*3]
mov a4, qword ptr[rsi+sizeof(qword)*4]
mov a5, qword ptr[rsi+sizeof(qword)*5]
add a0, qword ptr[rdx+sizeof(qword)*0]
adc a1, qword ptr[rdx+sizeof(qword)*1]
adc a2, qword ptr[rdx+sizeof(qword)*2]
adc a3, qword ptr[rdx+sizeof(qword)*3]
adc a4, qword ptr[rdx+sizeof(qword)*4]
adc a5, qword ptr[rdx+sizeof(qword)*5]
adc ex, 0
mov qword ptr[rdi+sizeof(qword)*0], a0
mov qword ptr[rdi+sizeof(qword)*1], a1
mov qword ptr[rdi+sizeof(qword)*2], a2
mov qword ptr[rdi+sizeof(qword)*3], a3
mov qword ptr[rdi+sizeof(qword)*4], a4
mov qword ptr[rdi+sizeof(qword)*5], a5
sub a0, qword ptr Lpoly+sizeof(qword)*0
sbb a1, qword ptr Lpoly+sizeof(qword)*1
sbb a2, qword ptr Lpoly+sizeof(qword)*2
sbb a3, qword ptr Lpoly+sizeof(qword)*3
sbb a4, qword ptr Lpoly+sizeof(qword)*4
sbb a5, qword ptr Lpoly+sizeof(qword)*5
sbb ex, 0
mov t, qword ptr[rdi+sizeof(qword)*0]
cmovb a0, t
mov t, qword ptr[rdi+sizeof(qword)*1]
cmovb a1, t
mov t, qword ptr[rdi+sizeof(qword)*2]
cmovb a2, t
mov t, qword ptr[rdi+sizeof(qword)*3]
cmovb a3, t
mov t, qword ptr[rdi+sizeof(qword)*4]
cmovb a4, t
mov t, qword ptr[rdi+sizeof(qword)*5]
cmovb a5, t
mov qword ptr[rdi+sizeof(qword)*0], a0
mov qword ptr[rdi+sizeof(qword)*1], a1
mov qword ptr[rdi+sizeof(qword)*2], a2
mov qword ptr[rdi+sizeof(qword)*3], a3
mov qword ptr[rdi+sizeof(qword)*4], a4
mov qword ptr[rdi+sizeof(qword)*5], a5
REST_XMM
REST_GPR
ret
IPPASM p384r1_add ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; void p384r1_sub(uint64_t res[6], uint64_t a[6], uint64_t b[6]);
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ALIGN IPP_ALIGN_FACTOR
IPPASM p384r1_sub PROC PUBLIC FRAME
USES_GPR rbx,rsi,rdi,r12
LOCAL_FRAME = 0
USES_XMM
COMP_ABI 3
a0 equ rax
a1 equ rcx
a2 equ rbx
a3 equ r8
a4 equ r9
a5 equ r10
ex equ r11
t equ r12
xor ex, ex
mov a0, qword ptr[rsi+sizeof(qword)*0] ; a
mov a1, qword ptr[rsi+sizeof(qword)*1]
mov a2, qword ptr[rsi+sizeof(qword)*2]
mov a3, qword ptr[rsi+sizeof(qword)*3]
mov a4, qword ptr[rsi+sizeof(qword)*4]
mov a5, qword ptr[rsi+sizeof(qword)*5]
sub a0, qword ptr[rdx+sizeof(qword)*0] ; a-b
sbb a1, qword ptr[rdx+sizeof(qword)*1]
sbb a2, qword ptr[rdx+sizeof(qword)*2]
sbb a3, qword ptr[rdx+sizeof(qword)*3]
sbb a4, qword ptr[rdx+sizeof(qword)*4]
sbb a5, qword ptr[rdx+sizeof(qword)*5]
sbb ex, 0 ; ex = a>=b? 0 : -1
mov qword ptr[rdi+sizeof(qword)*0], a0 ; store (a-b)
mov qword ptr[rdi+sizeof(qword)*1], a1
mov qword ptr[rdi+sizeof(qword)*2], a2
mov qword ptr[rdi+sizeof(qword)*3], a3
mov qword ptr[rdi+sizeof(qword)*4], a4
mov qword ptr[rdi+sizeof(qword)*5], a5
add a0, qword ptr Lpoly+sizeof(qword)*0 ; (a-b) +poly
adc a1, qword ptr Lpoly+sizeof(qword)*1
adc a2, qword ptr Lpoly+sizeof(qword)*2
adc a3, qword ptr Lpoly+sizeof(qword)*3
adc a4, qword ptr Lpoly+sizeof(qword)*4
adc a5, qword ptr Lpoly+sizeof(qword)*5
test ex, ex ; r = (ex)? ((a-b)+poly) : (a-b)
mov t, qword ptr[rdi+sizeof(qword)*0]
cmovz a0, t
mov t, qword ptr[rdi+sizeof(qword)*1]
cmovz a1, t
mov t, qword ptr[rdi+sizeof(qword)*2]
cmovz a2, t
mov t, qword ptr[rdi+sizeof(qword)*3]
cmovz a3, t
mov t, qword ptr[rdi+sizeof(qword)*4]
cmovz a4, t
mov t, qword ptr[rdi+sizeof(qword)*5]
cmovz a5, t
mov qword ptr[rdi+sizeof(qword)*0], a0
mov qword ptr[rdi+sizeof(qword)*1], a1
mov qword ptr[rdi+sizeof(qword)*2], a2
mov qword ptr[rdi+sizeof(qword)*3], a3
mov qword ptr[rdi+sizeof(qword)*4], a4
mov qword ptr[rdi+sizeof(qword)*5], a5
REST_XMM
REST_GPR
ret
IPPASM p384r1_sub ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; void p384r1_neg(uint64_t res[6], uint64_t a[6]);
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ALIGN IPP_ALIGN_FACTOR
IPPASM p384r1_neg PROC PUBLIC FRAME
USES_GPR rsi,rdi,r12
LOCAL_FRAME = 0
USES_XMM
COMP_ABI 2
a0 equ rax
a1 equ rcx
a2 equ rdx
a3 equ r8
a4 equ r9
a5 equ r10
ex equ r11
t equ r12
xor ex, ex
xor a0, a0
xor a1, a1
xor a2, a2
xor a3, a3
xor a4, a4
xor a5, a5
sub a0, qword ptr[rsi+sizeof(qword)*0]
sbb a1, qword ptr[rsi+sizeof(qword)*1]
sbb a2, qword ptr[rsi+sizeof(qword)*2]
sbb a3, qword ptr[rsi+sizeof(qword)*3]
sbb a4, qword ptr[rsi+sizeof(qword)*4]
sbb a5, qword ptr[rsi+sizeof(qword)*5]
sbb ex, 0
mov qword ptr[rdi+sizeof(qword)*0], a0
mov qword ptr[rdi+sizeof(qword)*1], a1
mov qword ptr[rdi+sizeof(qword)*2], a2
mov qword ptr[rdi+sizeof(qword)*3], a3
mov qword ptr[rdi+sizeof(qword)*4], a4
mov qword ptr[rdi+sizeof(qword)*5], a5
add a0, qword ptr Lpoly+sizeof(qword)*0
adc a1, qword ptr Lpoly+sizeof(qword)*1
adc a2, qword ptr Lpoly+sizeof(qword)*2
adc a3, qword ptr Lpoly+sizeof(qword)*3
adc a4, qword ptr Lpoly+sizeof(qword)*4
adc a5, qword ptr Lpoly+sizeof(qword)*5
test ex, ex
mov t, qword ptr[rdi+sizeof(qword)*0]
cmovz a0, t
mov t, qword ptr[rdi+sizeof(qword)*1]
cmovz a1, t
mov t, qword ptr[rdi+sizeof(qword)*2]
cmovz a2, t
mov t, qword ptr[rdi+sizeof(qword)*3]
cmovz a3, t
mov t, qword ptr[rdi+sizeof(qword)*4]
cmovz a4, t
mov t, qword ptr[rdi+sizeof(qword)*5]
cmovz a5, t
mov qword ptr[rdi+sizeof(qword)*0], a0
mov qword ptr[rdi+sizeof(qword)*1], a1
mov qword ptr[rdi+sizeof(qword)*2], a2
mov qword ptr[rdi+sizeof(qword)*3], a3
mov qword ptr[rdi+sizeof(qword)*4], a4
mov qword ptr[rdi+sizeof(qword)*5], a5
REST_XMM
REST_GPR
ret
IPPASM p384r1_neg ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; projective point selector
;
; void p384r1_mred(Ipp464u* res, Ipp64u product);
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
mred_step MACRO a6,a5,a4,a3,a2,a1,a0, t2,t1
mov rax, a0 ;; u = (m0*a0) mod 2^64= ((2^32+1)*a0) mod 2^64
shl rax, 32
add rax, a0
mov t2, rax ;; (t2:t1) = u*2^32, store
shr t2, (64-32)
push t2
mov t1, rax
shl t1, 32
push t1
sub t1, rax ;; {t2:t1} = (2^32 -1)*u
sbb t2, 0
add a0, t1 ;; {a0:a1} += {t2:t1}
pop t1 ;; restore {t2:t1} = u*2^32
adc a1, t2 ;; and accomodate carry
pop t2
sbb t2, 0
sub a1, t1 ;; {a1:a2} -= {t1:t2}
mov t1, 0
sbb a2, t2
adc t1, 0
sub a2, rax ;; a2 -= u
adc t1, 0
sub a3, t1 ;; a3 -= borrow
sbb a4, 0 ;; a4 -= borrow
sbb a5, 0 ;; a5 -= borrow
sbb rax, 0
add rax, rdx
mov rdx, 0
adc rdx, 0
add a6, rax
adc rdx, 0
ENDM
ALIGN IPP_ALIGN_FACTOR
IPPASM p384r1_mred PROC PUBLIC FRAME
USES_GPR rsi,rdi,r12,r13,r14,r15
USES_XMM
COMP_ABI 2
;; rdi = result
;; rsi = product buffer
xor rdx, rdx
mov r8, qword ptr[rsi]
mov r9, qword ptr[rsi+sizeof(qword)]
mov r10, qword ptr[rsi+sizeof(qword)*2]
mov r11, qword ptr[rsi+sizeof(qword)*3]
mov r12, qword ptr[rsi+sizeof(qword)*4]
mov r13, qword ptr[rsi+sizeof(qword)*5]
mov r14, qword ptr[rsi+sizeof(qword)*6]
mred_step r14,r13,r12,r11,r10,r9,r8, r15,rcx
;mov qword ptr[rdi+sizeof(qword)*0], r9
;mov qword ptr[rdi+sizeof(qword)*1], r10
;mov qword ptr[rdi+sizeof(qword)*2], r11
;mov qword ptr[rdi+sizeof(qword)*3], r12
;mov qword ptr[rdi+sizeof(qword)*4], r13
;mov qword ptr[rdi+sizeof(qword)*5], r14
mov r8, qword ptr[rsi+sizeof(qword)*7]
mred_step r8,r14,r13,r12,r11,r10,r9, r15,rcx
;mov qword ptr[rdi+sizeof(qword)*0], r10
;mov qword ptr[rdi+sizeof(qword)*1], r11
;mov qword ptr[rdi+sizeof(qword)*2], r12
;mov qword ptr[rdi+sizeof(qword)*3], r13
;mov qword ptr[rdi+sizeof(qword)*4], r14
;mov qword ptr[rdi+sizeof(qword)*5], r8
mov r9, qword ptr[rsi+sizeof(qword)*8]
mred_step r9,r8,r14,r13,r12,r11,r10, r15,rcx
;mov qword ptr[rdi+sizeof(qword)*0], r11
;mov qword ptr[rdi+sizeof(qword)*1], r12
;mov qword ptr[rdi+sizeof(qword)*2], r13
;mov qword ptr[rdi+sizeof(qword)*3], r14
;mov qword ptr[rdi+sizeof(qword)*4], r8
;mov qword ptr[rdi+sizeof(qword)*5], r9
mov r10, qword ptr[rsi+sizeof(qword)*9]
mred_step r10,r9,r8,r14,r13,r12,r11, r15,rcx
;mov qword ptr[rdi+sizeof(qword)*0], r12
;mov qword ptr[rdi+sizeof(qword)*1], r13
;mov qword ptr[rdi+sizeof(qword)*2], r14
;mov qword ptr[rdi+sizeof(qword)*3], r8
;mov qword ptr[rdi+sizeof(qword)*4], r9
;mov qword ptr[rdi+sizeof(qword)*5], r10
mov r11, qword ptr[rsi+sizeof(qword)*10]
mred_step r11,r10,r9,r8,r14,r13,r12, r15,rcx
;mov qword ptr[rdi+sizeof(qword)*0], r13
;mov qword ptr[rdi+sizeof(qword)*1], r14
;mov qword ptr[rdi+sizeof(qword)*2], r8
;mov qword ptr[rdi+sizeof(qword)*3], r9
;mov qword ptr[rdi+sizeof(qword)*4], r10
;mov qword ptr[rdi+sizeof(qword)*5], r11
mov r12, qword ptr[rsi+sizeof(qword)*11]
mred_step r12,r11,r10,r9,r8,r14,r13, r15,rcx ; {r12,r11,r10,r9,r8,r14} - result
mov qword ptr[rdi+sizeof(qword)*0], r14
mov qword ptr[rdi+sizeof(qword)*1], r8
mov qword ptr[rdi+sizeof(qword)*2], r9
mov qword ptr[rdi+sizeof(qword)*3], r10
mov qword ptr[rdi+sizeof(qword)*4], r11
mov qword ptr[rdi+sizeof(qword)*5], r12
sub r14, qword ptr Lpoly+sizeof(qword)*0
sbb r8, qword ptr Lpoly+sizeof(qword)*1
sbb r9, qword ptr Lpoly+sizeof(qword)*2
sbb r10, qword ptr Lpoly+sizeof(qword)*3
sbb r11, qword ptr Lpoly+sizeof(qword)*4
sbb r12, qword ptr Lpoly+sizeof(qword)*5
sbb rdx, 0
mov rax, qword ptr[rdi+sizeof(qword)*0]
cmovnz r14, rax
mov rax, qword ptr[rdi+sizeof(qword)*1]
cmovnz r8, rax
mov rax, qword ptr[rdi+sizeof(qword)*2]
cmovnz r9, rax
mov rax, qword ptr[rdi+sizeof(qword)*3]
cmovnz r10, rax
mov rax, qword ptr[rdi+sizeof(qword)*4]
cmovnz r11, rax
mov rax, qword ptr[rdi+sizeof(qword)*5]
cmovnz r12, rax
mov qword ptr[rdi+sizeof(qword)*0], r14
mov qword ptr[rdi+sizeof(qword)*1], r8
mov qword ptr[rdi+sizeof(qword)*2], r9
mov qword ptr[rdi+sizeof(qword)*3], r10
mov qword ptr[rdi+sizeof(qword)*4], r11
mov qword ptr[rdi+sizeof(qword)*5], r12
REST_XMM
REST_GPR
ret
IPPASM p384r1_mred ENDP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; projective point selector
;
; void p384r1_select_pp_w5(P384_POINT* val, const P384_POINT* tbl, int idx);
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ALIGN IPP_ALIGN_FACTOR
IPPASM p384r1_select_pp_w5 PROC PUBLIC FRAME
USES_GPR rsi,rdi,r12,r13
LOCAL_FRAME = 0
USES_XMM xmm6,xmm7,xmm8,xmm9,xmm10,xmm11,xmm12
COMP_ABI 3
val equ rdi
tbl equ rsi
idx equ edx
Xa equ xmm0
Xb equ xmm1
Xc equ xmm2
Ya equ xmm3
Yb equ xmm4
Yc equ xmm5
Za equ xmm6
Zb equ xmm7
Zc equ xmm8
REQ_IDX equ xmm9
CUR_IDX equ xmm10
MASKDATA equ xmm11
TMP equ xmm12
movdqa CUR_IDX, oword ptr LOne
movd REQ_IDX, idx
pshufd REQ_IDX, REQ_IDX, 0
pxor Xa, Xa
pxor Xb, Xb
pxor Xc, Xc
pxor Ya, Ya
pxor Yb, Yb
pxor Yc, Yc
pxor Za, Za
pxor Zb, Zb
pxor Zc, Zc
; Skip index = 0, is implicictly infty -> load with offset -1
mov rcx, 16
select_loop:
movdqa MASKDATA, CUR_IDX ; MASK = CUR_IDX==REQ_IDX? 0xFF : 0x00
pcmpeqd MASKDATA, REQ_IDX ;
paddd CUR_IDX, oword ptr LOne
movdqa TMP, MASKDATA
pand TMP, oword ptr[tbl+sizeof(oword)*0]
por Xa, TMP
movdqa TMP, MASKDATA
pand TMP, oword ptr[tbl+sizeof(oword)*1]
por Xb, TMP
movdqa TMP, MASKDATA
pand TMP, oword ptr[tbl+sizeof(oword)*2]
por Xc, TMP
movdqa TMP, MASKDATA
pand TMP, oword ptr[tbl+sizeof(oword)*3]
por Ya, TMP
movdqa TMP, MASKDATA
pand TMP, oword ptr[tbl+sizeof(oword)*4]
por Yb, TMP
movdqa TMP, MASKDATA
pand TMP, oword ptr[tbl+sizeof(oword)*5]
por Yc, TMP
movdqa TMP, MASKDATA
pand TMP, oword ptr[tbl+sizeof(oword)*6]
por Za, TMP
movdqa TMP, MASKDATA
pand TMP, oword ptr[tbl+sizeof(oword)*7]
por Zb, TMP
movdqa TMP, MASKDATA
pand TMP, oword ptr[tbl+sizeof(oword)*8]
por Zc, TMP
add tbl, sizeof(oword)*9
dec rcx
jnz select_loop
movdqu oword ptr[val+sizeof(oword)*0], Xa
movdqu oword ptr[val+sizeof(oword)*1], Xb
movdqu oword ptr[val+sizeof(oword)*2], Xc
movdqu oword ptr[val+sizeof(oword)*3], Ya
movdqu oword ptr[val+sizeof(oword)*4], Yb
movdqu oword ptr[val+sizeof(oword)*5], Yc
movdqu oword ptr[val+sizeof(oword)*6], Za
movdqu oword ptr[val+sizeof(oword)*7], Zb
movdqu oword ptr[val+sizeof(oword)*8], Zc
REST_XMM
REST_GPR
ret
IPPASM p384r1_select_pp_w5 ENDP
IFNDEF _DISABLE_ECP_384R1_HARDCODED_BP_TBL_
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; affine point selector
;
; void p384r1_select_ap_w5(AF_POINT *val, const AF_POINT *tbl, int idx);
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ALIGN IPP_ALIGN_FACTOR
IPPASM p384r1_select_ap_w5 PROC PUBLIC FRAME
USES_GPR rsi,rdi,r12,r13
LOCAL_FRAME = 0
USES_XMM xmm6,xmm7,xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14
COMP_ABI 3
val equ rdi
in_t equ rsi
idx equ edx
Xa equ xmm0
Xb equ xmm1
Xc equ xmm2
Ya equ xmm3
Yb equ xmm4
Yc equ xmm5
TXa equ xmm6
TXb equ xmm7
TXc equ xmm8
TYa equ xmm9
TYb equ xmm10
TYc equ xmm11
REQ_IDX equ xmm12
CUR_IDX equ xmm13
MASKDATA equ xmm14
movdqa CUR_IDX, oword ptr LOne
movd REQ_IDX, idx
pshufd REQ_IDX, REQ_IDX, 0
pxor Xa, Xa
pxor Xb, Xb
pxor Xc, Xc
pxor Ya, Ya
pxor Yb, Yb
pxor Yc, Yc
; Skip index = 0, is implicictly infty -> load with offset -1
mov rcx, 16
select_loop:
movdqa MASKDATA, CUR_IDX ; MASK = CUR_IDX==REQ_IDX? 0xFF : 0x00
pcmpeqd MASKDATA, REQ_IDX ;
paddd CUR_IDX, oword ptr LOne
movdqa TXa, oword ptr[in_t+sizeof(oword)*0]
movdqa TXb, oword ptr[in_t+sizeof(oword)*1]
movdqa TXc, oword ptr[in_t+sizeof(oword)*2]
movdqa TYa, oword ptr[in_t+sizeof(oword)*3]
movdqa TYb, oword ptr[in_t+sizeof(oword)*4]
movdqa TYc, oword ptr[in_t+sizeof(oword)*5]
add tbl, sizeof(oword)*6
pand TXa, MASKDATA
pand TXb, MASKDATA
pand TXc, MASKDATA
pand TYa, MASKDATA
pand TYb, MASKDATA
pand TYc, MASKDATA
por Xa, TXa
por Xb, TXb
por Xc, TXc
por Ya, TYa
por Yb, TYb
por Yc, TYc
dec rcx
jnz select_loop
movdqu oword ptr[val+sizeof(oword)*0], Xa
movdqu oword ptr[val+sizeof(oword)*1], Xb
movdqu oword ptr[val+sizeof(oword)*2], Xc
movdqu oword ptr[val+sizeof(oword)*3], Ya
movdqu oword ptr[val+sizeof(oword)*4], Yb
movdqu oword ptr[val+sizeof(oword)*5], Yc
REST_XMM
REST_GPR
ret
IPPASM p384r1_select_ap_w5 ENDP
ENDIF
ENDIF ;; _IPP32E_M7
END
| 28.90958 | 88 | 0.589828 |
ee67d6a897172128cc31ce0d8e6a07331c706d30 | 7,014 | asm | Assembly | Transynther/x86/_processed/AVXALIGN/_st_4k_/i9-9900K_12_0xa0.log_2405_561.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/AVXALIGN/_st_4k_/i9-9900K_12_0xa0.log_2405_561.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/AVXALIGN/_st_4k_/i9-9900K_12_0xa0.log_2405_561.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r13
push %r8
push %rbp
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_UC_ht+0x1495e, %r8
nop
sub %rcx, %rcx
movl $0x61626364, (%r8)
nop
nop
and %rsi, %rsi
lea addresses_WT_ht+0x1e644, %rbp
clflush (%rbp)
nop
nop
nop
sub $15771, %rsi
movw $0x6162, (%rbp)
nop
xor $5677, %rbx
lea addresses_D_ht+0x6808, %r13
nop
nop
nop
cmp $1131, %rbp
mov $0x6162636465666768, %rcx
movq %rcx, %xmm2
movups %xmm2, (%r13)
nop
nop
sub %r13, %r13
lea addresses_normal_ht+0x14842, %rsi
lea addresses_WC_ht+0x8504, %rdi
nop
nop
nop
xor $35262, %r13
mov $32, %rcx
rep movsw
nop
nop
nop
nop
sub $47818, %rcx
lea addresses_D_ht+0x195b4, %rcx
add %rsi, %rsi
mov (%rcx), %rdi
nop
nop
xor $12924, %rbp
lea addresses_normal_ht+0x1cdb4, %rbp
xor %r8, %r8
mov (%rbp), %r13w
nop
nop
nop
sub %r8, %r8
lea addresses_D_ht+0x85b4, %rcx
clflush (%rcx)
nop
nop
add %rbx, %rbx
mov (%rcx), %ebp
nop
nop
nop
cmp %r13, %r13
lea addresses_WC_ht+0x388c, %rbp
nop
nop
nop
nop
nop
cmp $35150, %rdi
movl $0x61626364, (%rbp)
nop
cmp %r13, %r13
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r8
pop %r13
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r14
push %r15
push %rax
push %rbx
push %rcx
push %rdi
// Store
lea addresses_A+0x69b4, %rdi
nop
nop
nop
nop
nop
inc %r14
mov $0x5152535455565758, %rcx
movq %rcx, %xmm2
vmovups %ymm2, (%rdi)
nop
xor %r14, %r14
// Store
mov $0x3967a000000005b4, %rdi
nop
nop
and $38611, %r12
movl $0x51525354, (%rdi)
nop
nop
nop
nop
nop
sub $48606, %rcx
// Load
mov $0x5ad4f100000009b4, %r12
nop
nop
and %r15, %r15
mov (%r12), %bx
and $30821, %rbx
// Store
lea addresses_WT+0x1fdb4, %r15
nop
nop
add %rcx, %rcx
movb $0x51, (%r15)
nop
add %r12, %r12
// Store
lea addresses_WT+0x152b4, %rcx
nop
xor $57642, %r15
movw $0x5152, (%rcx)
nop
nop
nop
nop
inc %r12
// Faulty Load
lea addresses_UC+0x185b4, %r12
nop
nop
nop
xor $45244, %rcx
mov (%r12), %ebx
lea oracles, %r14
and $0xff, %rbx
shlq $12, %rbx
mov (%r14,%rbx,1), %rbx
pop %rdi
pop %rcx
pop %rbx
pop %rax
pop %r15
pop %r14
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_UC', 'AVXalign': False, 'size': 32}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_A', 'AVXalign': False, 'size': 32}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_NC', 'AVXalign': False, 'size': 4}}
{'src': {'NT': False, 'same': False, 'congruent': 9, 'type': 'addresses_NC', 'AVXalign': True, 'size': 2}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 11, 'type': 'addresses_WT', 'AVXalign': False, 'size': 1}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 8, 'type': 'addresses_WT', 'AVXalign': False, 'size': 2}}
[Faulty Load]
{'src': {'NT': True, 'same': True, 'congruent': 0, 'type': 'addresses_UC', 'AVXalign': True, 'size': 4}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 1, 'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 4}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_WT_ht', 'AVXalign': False, 'size': 2}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': True, 'congruent': 2, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 16}}
{'src': {'same': False, 'congruent': 1, 'type': 'addresses_normal_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 1, 'type': 'addresses_WC_ht'}}
{'src': {'NT': False, 'same': False, 'congruent': 11, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 8}, 'OP': 'LOAD'}
{'src': {'NT': True, 'same': False, 'congruent': 11, 'type': 'addresses_normal_ht', 'AVXalign': True, 'size': 2}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 2, 'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 4}}
{'54': 2405}
54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54
*/
| 35.07 | 2,999 | 0.651697 |
02c43c687482839689d9785ba0741b1f3738fc2f | 567 | asm | Assembly | programs/oeis/025/A025818.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/025/A025818.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | programs/oeis/025/A025818.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | ; A025818: Expansion of 1/((1-x^2)(1-x^7)(1-x^10)).
; 1,0,1,0,1,0,1,1,1,1,2,1,2,1,3,1,3,2,3,2,4,3,4,3,5,3,5,4,6,4,7,5,7,5,8,6,8,7,9,7,10,8,11,8,12,9,12,10,13,11,14,12,15,12,16,13,17,14,18,15,19,16,20,17,21,18,22,19,23
mov $5,$0
mov $7,2
lpb $7
clr $0,5
mov $0,$5
sub $7,1
add $0,$7
sub $0,1
add $2,17
lpb $0
mov $1,$0
sub $0,1
cal $1,25786 ; Expansion of 1/((1-x)(1-x^7)(1-x^10)).
sub $0,1
add $2,$1
lpe
mov $1,$2
sub $1,16
mov $8,$7
lpb $8
mov $6,$1
sub $8,1
lpe
lpe
lpb $5
mov $5,0
sub $6,$1
lpe
mov $1,$6
| 17.181818 | 165 | 0.500882 |
83172271fd1a5f3496c0417c77433858d868b055 | 100 | asm | Assembly | Micro/Tests/pop/pop.asm | JavierOramas/CP_AC | d2f38823c6c2fce5acab1908a6912a7c18a0dd2b | [
"MIT"
] | null | null | null | Micro/Tests/pop/pop.asm | JavierOramas/CP_AC | d2f38823c6c2fce5acab1908a6912a7c18a0dd2b | [
"MIT"
] | null | null | null | Micro/Tests/pop/pop.asm | JavierOramas/CP_AC | d2f38823c6c2fce5acab1908a6912a7c18a0dd2b | [
"MIT"
] | null | null | null | addi r1 r0 65
push r1
push r2
push r3
push r4
pop r10
pop r10
pop r10
pop r9
tty r9
halt
#pirnts A | 7.142857 | 13 | 0.73 |
faee54247f9afe0368d529a20c8d8d7d60595944 | 8,193 | asm | Assembly | Transynther/x86/_processed/NONE/_ht_st_zr_/i9-9900K_12_0xa0_notsx.log_21829_1014.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_ht_st_zr_/i9-9900K_12_0xa0_notsx.log_21829_1014.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_ht_st_zr_/i9-9900K_12_0xa0_notsx.log_21829_1014.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r14
push %r15
push %r8
push %rax
push %rcx
push %rdi
push %rsi
lea addresses_UC_ht+0x106db, %rsi
lea addresses_normal_ht+0x1379b, %rdi
nop
nop
inc %r11
mov $24, %rcx
rep movsw
nop
cmp %rdi, %rdi
lea addresses_A_ht+0x1ae89, %rsi
lea addresses_D_ht+0x1b09b, %rdi
cmp $25035, %r8
mov $91, %rcx
rep movsw
nop
nop
nop
nop
nop
inc %r8
lea addresses_D_ht+0x195aa, %rsi
lea addresses_normal_ht+0x1989b, %rdi
nop
nop
nop
nop
nop
xor $17931, %r14
mov $98, %rcx
rep movsw
nop
nop
sub $14474, %r11
lea addresses_UC_ht+0x351b, %rsi
nop
inc %rax
mov (%rsi), %r14w
nop
nop
and %rcx, %rcx
lea addresses_normal_ht+0xb21b, %rsi
lea addresses_A_ht+0x15d9b, %rdi
nop
nop
sub $40060, %r15
mov $84, %rcx
rep movsq
nop
nop
cmp $24438, %r8
lea addresses_D_ht+0x7c03, %rdi
clflush (%rdi)
nop
nop
dec %rcx
movl $0x61626364, (%rdi)
nop
nop
nop
add $17417, %rax
lea addresses_UC_ht+0xf587, %rsi
lea addresses_A_ht+0x1b575, %rdi
nop
cmp %r11, %r11
mov $34, %rcx
rep movsl
nop
nop
cmp %r14, %r14
lea addresses_UC_ht+0x151b, %rax
nop
nop
nop
nop
nop
and %r8, %r8
movups (%rax), %xmm1
vpextrq $1, %xmm1, %rsi
nop
nop
add $56715, %rdi
lea addresses_WC_ht+0x1307, %rsi
nop
nop
nop
nop
inc %rcx
mov (%rsi), %rax
nop
add %r14, %r14
lea addresses_D_ht+0xb59b, %rcx
nop
nop
sub %rdi, %rdi
mov (%rcx), %r14d
nop
nop
nop
nop
nop
cmp %r8, %r8
lea addresses_normal_ht+0x259b, %rdi
and $62315, %r14
movb (%rdi), %r15b
nop
nop
xor $9691, %rsi
lea addresses_D_ht+0x1bd0b, %rdi
nop
nop
nop
nop
nop
inc %r14
movb (%rdi), %cl
nop
nop
nop
nop
mfence
lea addresses_D_ht+0xb59b, %r8
nop
nop
nop
nop
xor %r15, %r15
movups (%r8), %xmm1
vpextrq $0, %xmm1, %rdi
sub $52698, %rdi
lea addresses_UC_ht+0x1d59b, %rsi
cmp %rdi, %rdi
vmovups (%rsi), %ymm1
vextracti128 $1, %ymm1, %xmm1
vpextrq $1, %xmm1, %rax
nop
and $18960, %rdi
pop %rsi
pop %rdi
pop %rcx
pop %rax
pop %r8
pop %r15
pop %r14
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r8
push %rax
push %rbp
push %rbx
push %rcx
push %rdi
push %rsi
// REPMOV
lea addresses_WT+0x2d9b, %rsi
lea addresses_A+0x1d5f7, %rdi
nop
sub %r8, %r8
mov $62, %rcx
rep movsb
nop
nop
and %r12, %r12
// REPMOV
lea addresses_D+0x8d9b, %rsi
lea addresses_WC+0xeeb, %rdi
clflush (%rsi)
nop
nop
nop
inc %rbp
mov $54, %rcx
rep movsw
// Exception!!!
nop
nop
mov (0), %rax
nop
nop
nop
nop
nop
inc %r12
// Faulty Load
lea addresses_A+0x14d9b, %rax
nop
nop
nop
nop
nop
cmp $32431, %r12
vmovups (%rax), %ymm6
vextracti128 $1, %ymm6, %xmm6
vpextrq $1, %xmm6, %rbx
lea oracles, %rsi
and $0xff, %rbx
shlq $12, %rbx
mov (%rsi,%rbx,1), %rbx
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %rax
pop %r8
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_A', 'AVXalign': False, 'size': 2, 'NT': True, 'same': False, 'congruent': 0}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_WT', 'congruent': 10, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_A', 'congruent': 2, 'same': True}}
{'src': {'type': 'addresses_D', 'congruent': 8, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_WC', 'congruent': 4, 'same': True}}
[Faulty Load]
{'src': {'type': 'addresses_A', 'AVXalign': False, 'size': 32, 'NT': False, 'same': True, 'congruent': 0}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'type': 'addresses_UC_ht', 'congruent': 5, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_normal_ht', 'congruent': 8, 'same': False}}
{'src': {'type': 'addresses_A_ht', 'congruent': 1, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_D_ht', 'congruent': 7, 'same': False}}
{'src': {'type': 'addresses_D_ht', 'congruent': 0, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_normal_ht', 'congruent': 6, 'same': False}}
{'src': {'type': 'addresses_UC_ht', 'AVXalign': True, 'size': 2, 'NT': False, 'same': False, 'congruent': 7}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_normal_ht', 'congruent': 7, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_A_ht', 'congruent': 11, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'AVXalign': False, 'size': 4, 'NT': False, 'same': False, 'congruent': 2}}
{'src': {'type': 'addresses_UC_ht', 'congruent': 0, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_A_ht', 'congruent': 1, 'same': False}}
{'src': {'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 16, 'NT': False, 'same': False, 'congruent': 6}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 8, 'NT': False, 'same': True, 'congruent': 2}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_D_ht', 'AVXalign': True, 'size': 4, 'NT': True, 'same': False, 'congruent': 11}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_normal_ht', 'AVXalign': False, 'size': 1, 'NT': False, 'same': False, 'congruent': 11}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_D_ht', 'AVXalign': False, 'size': 1, 'NT': False, 'same': False, 'congruent': 4}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_D_ht', 'AVXalign': False, 'size': 16, 'NT': False, 'same': False, 'congruent': 11}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 32, 'NT': False, 'same': False, 'congruent': 11}, 'OP': 'LOAD'}
{'36': 20970, '46': 13, '44': 202, '45': 622, '00': 22}
36 44 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 44 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 00 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 00 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 44 36 36 36 36 36 36 36 36 36 45 36 36 36 45 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 44 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 44 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 44 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 44 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 00 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 45 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
| 32.511905 | 2,999 | 0.654705 |
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