CircuitQA

Question answering over digital RTL (Verilog) designs, grounded in the outputs of analysis backends (static analysis, synthesis, simulation, graph extraction, optimisation advice, RTL-to-netlist mapping). Companion data and code for CircuitQA: A Grounded Architecture for Question Answering over Digital RTL Designs with Multi-Backend Query Routing. Trained adapters: drawais/circuitqa-adapters.

Contents

Path	Contents
corpus/	30,041 / 4,262 / 3,294 question-answer pairs (train / validation / test; no repository is shared between splits) and eval_sample.jsonl, the 475-question stratified sample of the test split evaluated in the paper (Section IV-G, "Released corpus").
compositional/	2,491 / 478 / 330 questions that require two or three backends (questions involving the simulation backend, and questions whose RTL-to-netlist mapping rests on a synthesis run that produced no netlist, are not included), the backend outputs they were written from (backend_results.jsonl), and the backend calls predicted by the router and executed end to end (test_e2e.jsonl, e2e_calls.jsonl, e2e_results.jsonl). The released compositional adapter was trained on 4,974 training questions, including the 2,483 excluded here.
rephrasings/	Rephrasings of 29,934 training and 4,146 validation questions of corpus/ (those for which a valid rephrasing was produced).
outputs/	Per-sample predictions on corpus/eval_sample.jsonl (corpus_eval/) and on compositional/test.jsonl (compositional/), router outputs on the compositional test set, and numeric LLM-judge scores of the compositional answers (judge_scores/). See Outputs below.
code/	Backends (eda_tools.py), corpus pipeline, training, inference, routing and evaluation code (Apache-2.0, see code/LICENSE). The scoring scripts (score.py, mt_score.py, mt_numeric.py) run on the released files; the pipeline and training scripts document how the data were built and expect the design sources and CIRCUITQA_ROOT.
scripts/fetch_sources.py	Retrieves and verifies the referenced design sources.
SHA256SUMS	SHA-256 of every file in this repository (sha256sum -c SHA256SUMS).

Record fields (corpus)

question_hash (record identifier), question, answer; module_name, category, subcategory, difficulty; tool_name, tool_parameters, stage1_target (the backend call as JSON); tool_result (the backend output the answer is computed from, as a JSON-encoded string); stage2_context (question and backend output as given to the decoder in training); source = {repository, commit, path, sha256} of the design file. In eval_sample.jsonl, prompt_code_chars (3,000) is the cap on the design-source characters given to the baseline models: the first 3,000 characters, or the whole file if shorter (CircuitQA inference used the first 2,000, --verilog-cap). In corpus records stage2_context is the decoder's excerpt of the backend output (logs, node and edge lists omitted, cut at 1,500 characters); tool_result holds the full output. The graph backend lists at most 100 nodes and 200 edges (node_count and edge_count are complete), and the simulation backend at most 200 signal toggle rates. Compositional records additionally carry design_id, plan_id, n_calls and writer_model (the LLM that wrote the question), and source_file, the design's path relative to the original collection (informational; use source to retrieve the file), split, and ctx_cap (the character budget of the decoder context); in compositional records tool_parameters is a list with one parameter object per backend call. test_e2e.jsonl holds the same questions with predicted_calls, the router's output, and with tool_result/stage2_context built from the outputs of the predicted calls (e2e_results.jsonl, a separate execution).

In compositional tool_result and stage2_context, outputs longer than the decoder's context budget (ctx_cap) are shortened, marked ...[N chars elided]...; the full outputs are in backend_results.jsonl (the shortening was applied before local temporary paths were replaced by <tmp>, so lengths and cut points differ slightly from those files). Rephrasing files hold question_hash, question (the rephrasing), question_original and paraphrase_model; judge files hold question_hash and score.

designs.jsonl: design_id, module_name, split, source. e2e_calls.jsonl: key, design_id, tool, parameters. backend_results.jsonl and e2e_results.jsonl: the same plus result and seconds; backend_results.jsonl holds every backend run on the released designs, including runs that ended with status: error (no question is built on those). Output files hold question_hash, category and prediction; router files hold question_hash, category, gold_tool, pred_tool (the set of predicted backends, +-joined as in gold_tool) and raw (the router's output).

Units and backend conventions

• Synthesis area, delay and power are gate-count-based estimates, reported in relative area units, ps and mW respectively; they are not sign-off figures for a technology library.
• optimization_advisor is rule based; its estimated_improvement values are fixed per target_metric (area, delay or power), not measured.
• simulation_tool is run with 100 cycles of a generated testbench in every record.

Outputs

File names give the system and the setting:

• v2_s4_seed{42,123,456}_B — the single-backend Response Decoder (three training seeds) on the corpus evaluation sample, given the backend output (condition B); v2_qwenbase_B — the unmodified Qwen2.5-Coder-7B-Instruct base model in the same setting.
• s4_seed*_mt_B — the single-backend decoder on the compositional test set given the correct backend outputs; mt_seed*_mt_B — the compositional decoder given the correct outputs; mt_seed*_mt_e2e — the compositional decoder given the outputs of the calls predicted by the router (end to end).
• qrm_mt_seed42_mt / qrm_s4_seed42_mt — outputs of the compositional and the single-backend router on the compositional test set.
• judge_scores/<run>.judge_<judge>.jsonl — per-question scores in [0, 1]. GLM-5.3 judged all three seeds of every compositional run; Claude Opus 5.5 judged seed 42.

Design sources are referenced, not redistributed

The design files stay in their upstream repositories under their own licence terms and are not included here. To obtain them:

python3 scripts/fetch_sources.py corpus/test.jsonl compositional/designs.jsonl --out sources/

The script downloads each repository at the recorded commit (the default branch where no commit is recorded), extracts the referenced files and keeps those whose SHA-256 matches. No commit is recorded for 1,304 training records (ucb-bar/chipyard and SpinalHDL/VexRiscv); for these the default branch is used. Most of the Chipyard paths lie inside git submodules, which repository archives do not contain; the script reports them as not found. Upstream repositories (27):

• https://github.com/SI-RISCV/e200_opensource
• https://github.com/SpinalHDL/VexRiscv
• https://github.com/The-OpenROAD-Project/OpenROAD
• https://github.com/XUANTIE-RV/openc910
• https://github.com/XUANTIE-RV/wujian100_open
• https://github.com/YosysHQ/picorv32
• https://github.com/ZipCPU/zipcpu
• https://github.com/alexforencich/verilog-axi
• https://github.com/alexforencich/verilog-ethernet
• https://github.com/alexforencich/verilog-pcie
• https://github.com/analogdevicesinc/hdl
• https://github.com/aolofsson/oh
• https://github.com/corundum/corundum
• https://github.com/darklife/darkriscv
• https://github.com/firesim/NiteFury-and-LiteFury-firesim
• https://github.com/firesim/aws-fpga-firesim
• https://github.com/firesim/firesim
• https://github.com/firesim/garnet-firesim
• https://github.com/nvdla/hw
• https://github.com/olofk/serv
• https://github.com/pConst/basic_verilog
• https://github.com/riscv-mcu/e203_hbirdv2
• https://github.com/ucb-bar/chipyard
• https://github.com/ucb-bar/nvdla-wrapper
• https://github.com/ufrisk/pcileech-fpga
• https://github.com/ultraembedded/riscv
• https://github.com/vortexgpgpu/vortex

How the data were made

• Corpus questions are instantiated from category templates. Each answer is computed from the output of the backend named in stage1_target, run on the design's full upstream source with the question's own parameters. Records whose backend reports an error are not included.
• Backends (code/eda_tools.py) use the open-source tools of OSS CAD Suite (Yosys, Icarus Verilog). Synthesis area, delay and power are gate-count-based estimates in relative units. The optimisation backend is rule based. Simulation drives a generated testbench for 100 cycles and measures toggle rates (bit transitions per bit and cycle) and toggle coverage from the VCD waveform; toggle-rate questions are kept only for signals in the recorded waveform.
• The compositional questions and reference answers and the question rephrasings were written by the authors with LLMs (Claude Opus 5.5 for compositional validation and test, GLM-5.3 for compositional training and the rephrasings) and accepted only if every number in an answer occurs in the backend outputs or the question, the answer uses a value specific to every backend, and the question names the module.
• Model: Qwen2.5-Coder-7B-Instruct (Apache-2.0) with LoRA adapters trained by the authors.

Licence

Annotations (questions, answers, backend outputs, splits, model predictions and judge scores): CC-BY-4.0. Code (code/, scripts/): Apache-2.0 (see code/LICENSE and NOTICE). Design sources are not included; each is governed by the licence terms of its upstream repository and of the file itself (some files carry their own vendor or per-file licence headers). Backend outputs are derived from the upstream designs (for example, netlist graphs keep their signal and cell names); rights in the designs remain with their owners and apply to these derived outputs to the extent they reach them.

Citation

If you use the CircuitQA dataset, code or adapters, please cite:

@misc{awais2026circuitqa,
  title        = {{CircuitQA}: A Grounded Architecture for Question Answering over Digital {RTL} Designs with Multi-Backend Query Routing},
  author       = {Awais, Muhammad and Postolache, Octavian Adrian and Oliveira, Sancho Moura},
  year         = {2026},
  howpublished = {\url{https://huggingface.co/datasets/drawais/circuitqa}},
  note         = {Dataset and code}
}

@misc{awais2026circuitqaadapters,
  title        = {{CircuitQA} Adapters: {LoRA} Adapters for {Qwen2.5-Coder-7B-Instruct}},
  author       = {Awais, Muhammad and Postolache, Octavian Adrian and Oliveira, Sancho Moura},
  year         = {2026},
  howpublished = {\url{https://huggingface.co/drawais/circuitqa-adapters}},
  note         = {Trained model adapters}
}